1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 /* This file should be included last. */
86 #include "target-def.h"
88 #ifndef TARGET_NO_PROTOTYPE
89 #define TARGET_NO_PROTOTYPE 0
92 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
93 systems will also set long double to be IEEE 128-bit. AIX and Darwin
94 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
95 those systems will not pick up this default. This needs to be after all
96 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
98 #ifndef TARGET_IEEEQUAD_DEFAULT
99 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
100 #define TARGET_IEEEQUAD_DEFAULT 1
102 #define TARGET_IEEEQUAD_DEFAULT 0
106 #define min(A,B) ((A) < (B) ? (A) : (B))
107 #define max(A,B) ((A) > (B) ? (A) : (B))
109 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
111 /* Structure used to define the rs6000 stack */
112 typedef struct rs6000_stack {
113 int reload_completed; /* stack info won't change from here on */
114 int first_gp_reg_save; /* first callee saved GP register used */
115 int first_fp_reg_save; /* first callee saved FP register used */
116 int first_altivec_reg_save; /* first callee saved AltiVec register used */
117 int lr_save_p; /* true if the link reg needs to be saved */
118 int cr_save_p; /* true if the CR reg needs to be saved */
119 unsigned int vrsave_mask; /* mask of vec registers to save */
120 int push_p; /* true if we need to allocate stack space */
121 int calls_p; /* true if the function makes any calls */
122 int world_save_p; /* true if we're saving *everything*:
123 r13-r31, cr, f14-f31, vrsave, v20-v31 */
124 enum rs6000_abi abi; /* which ABI to use */
125 int gp_save_offset; /* offset to save GP regs from initial SP */
126 int fp_save_offset; /* offset to save FP regs from initial SP */
127 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
128 int lr_save_offset; /* offset to save LR from initial SP */
129 int cr_save_offset; /* offset to save CR from initial SP */
130 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
131 int varargs_save_offset; /* offset to save the varargs registers */
132 int ehrd_offset; /* offset to EH return data */
133 int ehcr_offset; /* offset to EH CR field data */
134 int reg_size; /* register size (4 or 8) */
135 HOST_WIDE_INT vars_size; /* variable save area size */
136 int parm_size; /* outgoing parameter size */
137 int save_size; /* save area size */
138 int fixed_size; /* fixed size of stack frame */
139 int gp_size; /* size of saved GP registers */
140 int fp_size; /* size of saved FP registers */
141 int altivec_size; /* size of saved AltiVec registers */
142 int cr_size; /* size to hold CR if not in fixed area */
143 int vrsave_size; /* size to hold VRSAVE */
144 int altivec_padding_size; /* size of altivec alignment padding */
145 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
149 /* A C structure for machine-specific, per-function data.
150 This is added to the cfun structure. */
151 typedef struct GTY(()) machine_function
153 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
154 int ra_needs_full_frame;
155 /* Flags if __builtin_return_address (0) was used. */
157 /* Cache lr_save_p after expansion of builtin_eh_return. */
159 /* Whether we need to save the TOC to the reserved stack location in the
160 function prologue. */
161 bool save_toc_in_prologue;
162 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
163 varargs save area. */
164 HOST_WIDE_INT varargs_save_offset;
165 /* Alternative internal arg pointer for -fsplit-stack. */
166 rtx split_stack_arg_pointer;
167 bool split_stack_argp_used;
168 /* Flag if r2 setup is needed with ELFv2 ABI. */
169 bool r2_setup_needed;
170 /* The number of components we use for separate shrink-wrapping. */
172 /* The components already handled by separate shrink-wrapping, which should
173 not be considered by the prologue and epilogue. */
174 bool gpr_is_wrapped_separately[32];
175 bool fpr_is_wrapped_separately[32];
176 bool lr_is_wrapped_separately;
177 bool toc_is_wrapped_separately;
180 /* Support targetm.vectorize.builtin_mask_for_load. */
181 static GTY(()) tree altivec_builtin_mask_for_load;
183 /* Set to nonzero once AIX common-mode calls have been defined. */
184 static GTY(()) int common_mode_defined;
186 /* Label number of label created for -mrelocatable, to call to so we can
187 get the address of the GOT section */
188 static int rs6000_pic_labelno;
191 /* Counter for labels which are to be placed in .fixup. */
192 int fixuplabelno = 0;
195 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
198 /* Specify the machine mode that pointers have. After generation of rtl, the
199 compiler makes no further distinction between pointers and any other objects
200 of this machine mode. */
201 scalar_int_mode rs6000_pmode;
203 /* Width in bits of a pointer. */
204 unsigned rs6000_pointer_size;
206 #ifdef HAVE_AS_GNU_ATTRIBUTE
207 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
208 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
210 /* Flag whether floating point values have been passed/returned.
211 Note that this doesn't say whether fprs are used, since the
212 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
213 should be set for soft-float values passed in gprs and ieee128
214 values passed in vsx registers. */
215 static bool rs6000_passes_float;
216 static bool rs6000_passes_long_double;
217 /* Flag whether vector values have been passed/returned. */
218 static bool rs6000_passes_vector;
219 /* Flag whether small (<= 8 byte) structures have been returned. */
220 static bool rs6000_returns_struct;
223 /* Value is TRUE if register/mode pair is acceptable. */
224 static bool rs6000_hard_regno_mode_ok_p
225 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
227 /* Maximum number of registers needed for a given register class and mode. */
228 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
230 /* How many registers are needed for a given register and mode. */
231 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
233 /* Map register number to register class. */
234 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
236 static int dbg_cost_ctrl;
238 /* Built in types. */
239 tree rs6000_builtin_types[RS6000_BTI_MAX];
240 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
242 /* Flag to say the TOC is initialized */
243 int toc_initialized, need_toc_init;
244 char toc_label_name[10];
246 /* Cached value of rs6000_variable_issue. This is cached in
247 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
248 static short cached_can_issue_more;
250 static GTY(()) section *read_only_data_section;
251 static GTY(()) section *private_data_section;
252 static GTY(()) section *tls_data_section;
253 static GTY(()) section *tls_private_data_section;
254 static GTY(()) section *read_only_private_data_section;
255 static GTY(()) section *sdata2_section;
256 static GTY(()) section *toc_section;
258 struct builtin_description
260 const HOST_WIDE_INT mask;
261 const enum insn_code icode;
262 const char *const name;
263 const enum rs6000_builtins code;
266 /* Describe the vector unit used for modes. */
267 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
268 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
270 /* Register classes for various constraints that are based on the target
272 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
274 /* Describe the alignment of a vector. */
275 int rs6000_vector_align[NUM_MACHINE_MODES];
277 /* Map selected modes to types for builtins. */
278 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
280 /* What modes to automatically generate reciprocal divide estimate (fre) and
281 reciprocal sqrt (frsqrte) for. */
282 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
284 /* Masks to determine which reciprocal esitmate instructions to generate
286 enum rs6000_recip_mask {
287 RECIP_SF_DIV = 0x001, /* Use divide estimate */
288 RECIP_DF_DIV = 0x002,
289 RECIP_V4SF_DIV = 0x004,
290 RECIP_V2DF_DIV = 0x008,
292 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
293 RECIP_DF_RSQRT = 0x020,
294 RECIP_V4SF_RSQRT = 0x040,
295 RECIP_V2DF_RSQRT = 0x080,
297 /* Various combination of flags for -mrecip=xxx. */
299 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
300 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
301 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
303 RECIP_HIGH_PRECISION = RECIP_ALL,
305 /* On low precision machines like the power5, don't enable double precision
306 reciprocal square root estimate, since it isn't accurate enough. */
307 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
310 /* -mrecip options. */
313 const char *string; /* option name */
314 unsigned int mask; /* mask bits to set */
315 } recip_options[] = {
316 { "all", RECIP_ALL },
317 { "none", RECIP_NONE },
318 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
320 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
321 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
322 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
323 | RECIP_V2DF_RSQRT) },
324 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
325 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
328 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
334 { "power9", PPC_PLATFORM_POWER9 },
335 { "power8", PPC_PLATFORM_POWER8 },
336 { "power7", PPC_PLATFORM_POWER7 },
337 { "power6x", PPC_PLATFORM_POWER6X },
338 { "power6", PPC_PLATFORM_POWER6 },
339 { "power5+", PPC_PLATFORM_POWER5_PLUS },
340 { "power5", PPC_PLATFORM_POWER5 },
341 { "ppc970", PPC_PLATFORM_PPC970 },
342 { "power4", PPC_PLATFORM_POWER4 },
343 { "ppca2", PPC_PLATFORM_PPCA2 },
344 { "ppc476", PPC_PLATFORM_PPC476 },
345 { "ppc464", PPC_PLATFORM_PPC464 },
346 { "ppc440", PPC_PLATFORM_PPC440 },
347 { "ppc405", PPC_PLATFORM_PPC405 },
348 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
351 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
357 } cpu_supports_info[] = {
358 /* AT_HWCAP masks. */
359 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
360 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
361 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
362 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
363 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
364 { "booke", PPC_FEATURE_BOOKE, 0 },
365 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
366 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
367 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
368 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
369 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
370 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
371 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
372 { "notb", PPC_FEATURE_NO_TB, 0 },
373 { "pa6t", PPC_FEATURE_PA6T, 0 },
374 { "power4", PPC_FEATURE_POWER4, 0 },
375 { "power5", PPC_FEATURE_POWER5, 0 },
376 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
377 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
378 { "ppc32", PPC_FEATURE_32, 0 },
379 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
380 { "ppc64", PPC_FEATURE_64, 0 },
381 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
382 { "smt", PPC_FEATURE_SMT, 0 },
383 { "spe", PPC_FEATURE_HAS_SPE, 0 },
384 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
385 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
386 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
388 /* AT_HWCAP2 masks. */
389 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
390 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
391 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
392 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
393 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
394 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
395 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
396 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
397 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
398 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
399 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
400 { "darn", PPC_FEATURE2_DARN, 1 },
401 { "scv", PPC_FEATURE2_SCV, 1 }
404 /* On PowerPC, we have a limited number of target clones that we care about
405 which means we can use an array to hold the options, rather than having more
406 elaborate data structures to identify each possible variation. Order the
407 clones from the default to the highest ISA. */
409 CLONE_DEFAULT = 0, /* default clone. */
410 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
411 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
412 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
413 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
417 /* Map compiler ISA bits into HWCAP names. */
419 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
420 const char *name; /* name to use in __builtin_cpu_supports. */
423 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
424 { 0, "" }, /* Default options. */
425 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
426 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
427 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
428 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
432 /* Newer LIBCs explicitly export this symbol to declare that they provide
433 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
434 reference to this symbol whenever we expand a CPU builtin, so that
435 we never link against an old LIBC. */
436 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
438 /* True if we have expanded a CPU builtin. */
441 /* Pointer to function (in rs6000-c.c) that can define or undefine target
442 macros that have changed. Languages that don't support the preprocessor
443 don't link in rs6000-c.c, so we can't call it directly. */
444 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
446 /* Simplfy register classes into simpler classifications. We assume
447 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
448 check for standard register classes (gpr/floating/altivec/vsx) and
449 floating/vector classes (float/altivec/vsx). */
451 enum rs6000_reg_type {
462 /* Map register class to register type. */
463 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
465 /* First/last register type for the 'normal' register types (i.e. general
466 purpose, floating point, altivec, and VSX registers). */
467 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
469 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
472 /* Register classes we care about in secondary reload or go if legitimate
473 address. We only need to worry about GPR, FPR, and Altivec registers here,
474 along an ANY field that is the OR of the 3 register classes. */
476 enum rs6000_reload_reg_type {
477 RELOAD_REG_GPR, /* General purpose registers. */
478 RELOAD_REG_FPR, /* Traditional floating point regs. */
479 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
480 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
484 /* For setting up register classes, loop through the 3 register classes mapping
485 into real registers, and skip the ANY class, which is just an OR of the
487 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
488 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
490 /* Map reload register type to a register in the register class. */
491 struct reload_reg_map_type {
492 const char *name; /* Register class name. */
493 int reg; /* Register in the register class. */
496 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
497 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
498 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
499 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
500 { "Any", -1 }, /* RELOAD_REG_ANY. */
503 /* Mask bits for each register class, indexed per mode. Historically the
504 compiler has been more restrictive which types can do PRE_MODIFY instead of
505 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
506 typedef unsigned char addr_mask_type;
508 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
509 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
510 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
511 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
512 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
513 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
514 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
515 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
517 /* Register type masks based on the type, of valid addressing modes. */
518 struct rs6000_reg_addr {
519 enum insn_code reload_load; /* INSN to reload for loading. */
520 enum insn_code reload_store; /* INSN to reload for storing. */
521 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
522 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
523 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
524 enum insn_code fusion_gpr_ld; /* INSN for fusing gpr ADDIS/loads. */
525 /* INSNs for fusing addi with loads
526 or stores for each reg. class. */
527 enum insn_code fusion_addi_ld[(int)N_RELOAD_REG];
528 enum insn_code fusion_addi_st[(int)N_RELOAD_REG];
529 /* INSNs for fusing addis with loads
530 or stores for each reg. class. */
531 enum insn_code fusion_addis_ld[(int)N_RELOAD_REG];
532 enum insn_code fusion_addis_st[(int)N_RELOAD_REG];
533 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
534 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
535 bool fused_toc; /* Mode supports TOC fusion. */
538 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
540 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
542 mode_supports_pre_incdec_p (machine_mode mode)
544 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
548 /* Helper function to say whether a mode supports PRE_MODIFY. */
550 mode_supports_pre_modify_p (machine_mode mode)
552 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
556 /* Given that there exists at least one variable that is set (produced)
557 by OUT_INSN and read (consumed) by IN_INSN, return true iff
558 IN_INSN represents one or more memory store operations and none of
559 the variables set by OUT_INSN is used by IN_INSN as the address of a
560 store operation. If either IN_INSN or OUT_INSN does not represent
561 a "single" RTL SET expression (as loosely defined by the
562 implementation of the single_set function) or a PARALLEL with only
563 SETs, CLOBBERs, and USEs inside, this function returns false.
565 This rs6000-specific version of store_data_bypass_p checks for
566 certain conditions that result in assertion failures (and internal
567 compiler errors) in the generic store_data_bypass_p function and
568 returns false rather than calling store_data_bypass_p if one of the
569 problematic conditions is detected. */
572 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
579 in_set = single_set (in_insn);
582 if (MEM_P (SET_DEST (in_set)))
584 out_set = single_set (out_insn);
587 out_pat = PATTERN (out_insn);
588 if (GET_CODE (out_pat) == PARALLEL)
590 for (i = 0; i < XVECLEN (out_pat, 0); i++)
592 out_exp = XVECEXP (out_pat, 0, i);
593 if ((GET_CODE (out_exp) == CLOBBER)
594 || (GET_CODE (out_exp) == USE))
596 else if (GET_CODE (out_exp) != SET)
605 in_pat = PATTERN (in_insn);
606 if (GET_CODE (in_pat) != PARALLEL)
609 for (i = 0; i < XVECLEN (in_pat, 0); i++)
611 in_exp = XVECEXP (in_pat, 0, i);
612 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
614 else if (GET_CODE (in_exp) != SET)
617 if (MEM_P (SET_DEST (in_exp)))
619 out_set = single_set (out_insn);
622 out_pat = PATTERN (out_insn);
623 if (GET_CODE (out_pat) != PARALLEL)
625 for (j = 0; j < XVECLEN (out_pat, 0); j++)
627 out_exp = XVECEXP (out_pat, 0, j);
628 if ((GET_CODE (out_exp) == CLOBBER)
629 || (GET_CODE (out_exp) == USE))
631 else if (GET_CODE (out_exp) != SET)
638 return store_data_bypass_p (out_insn, in_insn);
641 /* Return true if we have D-form addressing in altivec registers. */
643 mode_supports_vmx_dform (machine_mode mode)
645 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
648 /* Return true if we have D-form addressing in VSX registers. This addressing
649 is more limited than normal d-form addressing in that the offset must be
650 aligned on a 16-byte boundary. */
652 mode_supports_vsx_dform_quad (machine_mode mode)
654 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
659 /* Processor costs (relative to an add) */
661 const struct processor_costs *rs6000_cost;
663 /* Instruction size costs on 32bit processors. */
665 struct processor_costs size32_cost = {
666 COSTS_N_INSNS (1), /* mulsi */
667 COSTS_N_INSNS (1), /* mulsi_const */
668 COSTS_N_INSNS (1), /* mulsi_const9 */
669 COSTS_N_INSNS (1), /* muldi */
670 COSTS_N_INSNS (1), /* divsi */
671 COSTS_N_INSNS (1), /* divdi */
672 COSTS_N_INSNS (1), /* fp */
673 COSTS_N_INSNS (1), /* dmul */
674 COSTS_N_INSNS (1), /* sdiv */
675 COSTS_N_INSNS (1), /* ddiv */
676 32, /* cache line size */
680 0, /* SF->DF convert */
683 /* Instruction size costs on 64bit processors. */
685 struct processor_costs size64_cost = {
686 COSTS_N_INSNS (1), /* mulsi */
687 COSTS_N_INSNS (1), /* mulsi_const */
688 COSTS_N_INSNS (1), /* mulsi_const9 */
689 COSTS_N_INSNS (1), /* muldi */
690 COSTS_N_INSNS (1), /* divsi */
691 COSTS_N_INSNS (1), /* divdi */
692 COSTS_N_INSNS (1), /* fp */
693 COSTS_N_INSNS (1), /* dmul */
694 COSTS_N_INSNS (1), /* sdiv */
695 COSTS_N_INSNS (1), /* ddiv */
696 128, /* cache line size */
700 0, /* SF->DF convert */
703 /* Instruction costs on RS64A processors. */
705 struct processor_costs rs64a_cost = {
706 COSTS_N_INSNS (20), /* mulsi */
707 COSTS_N_INSNS (12), /* mulsi_const */
708 COSTS_N_INSNS (8), /* mulsi_const9 */
709 COSTS_N_INSNS (34), /* muldi */
710 COSTS_N_INSNS (65), /* divsi */
711 COSTS_N_INSNS (67), /* divdi */
712 COSTS_N_INSNS (4), /* fp */
713 COSTS_N_INSNS (4), /* dmul */
714 COSTS_N_INSNS (31), /* sdiv */
715 COSTS_N_INSNS (31), /* ddiv */
716 128, /* cache line size */
720 0, /* SF->DF convert */
723 /* Instruction costs on MPCCORE processors. */
725 struct processor_costs mpccore_cost = {
726 COSTS_N_INSNS (2), /* mulsi */
727 COSTS_N_INSNS (2), /* mulsi_const */
728 COSTS_N_INSNS (2), /* mulsi_const9 */
729 COSTS_N_INSNS (2), /* muldi */
730 COSTS_N_INSNS (6), /* divsi */
731 COSTS_N_INSNS (6), /* divdi */
732 COSTS_N_INSNS (4), /* fp */
733 COSTS_N_INSNS (5), /* dmul */
734 COSTS_N_INSNS (10), /* sdiv */
735 COSTS_N_INSNS (17), /* ddiv */
736 32, /* cache line size */
740 0, /* SF->DF convert */
743 /* Instruction costs on PPC403 processors. */
745 struct processor_costs ppc403_cost = {
746 COSTS_N_INSNS (4), /* mulsi */
747 COSTS_N_INSNS (4), /* mulsi_const */
748 COSTS_N_INSNS (4), /* mulsi_const9 */
749 COSTS_N_INSNS (4), /* muldi */
750 COSTS_N_INSNS (33), /* divsi */
751 COSTS_N_INSNS (33), /* divdi */
752 COSTS_N_INSNS (11), /* fp */
753 COSTS_N_INSNS (11), /* dmul */
754 COSTS_N_INSNS (11), /* sdiv */
755 COSTS_N_INSNS (11), /* ddiv */
756 32, /* cache line size */
760 0, /* SF->DF convert */
763 /* Instruction costs on PPC405 processors. */
765 struct processor_costs ppc405_cost = {
766 COSTS_N_INSNS (5), /* mulsi */
767 COSTS_N_INSNS (4), /* mulsi_const */
768 COSTS_N_INSNS (3), /* mulsi_const9 */
769 COSTS_N_INSNS (5), /* muldi */
770 COSTS_N_INSNS (35), /* divsi */
771 COSTS_N_INSNS (35), /* divdi */
772 COSTS_N_INSNS (11), /* fp */
773 COSTS_N_INSNS (11), /* dmul */
774 COSTS_N_INSNS (11), /* sdiv */
775 COSTS_N_INSNS (11), /* ddiv */
776 32, /* cache line size */
780 0, /* SF->DF convert */
783 /* Instruction costs on PPC440 processors. */
785 struct processor_costs ppc440_cost = {
786 COSTS_N_INSNS (3), /* mulsi */
787 COSTS_N_INSNS (2), /* mulsi_const */
788 COSTS_N_INSNS (2), /* mulsi_const9 */
789 COSTS_N_INSNS (3), /* muldi */
790 COSTS_N_INSNS (34), /* divsi */
791 COSTS_N_INSNS (34), /* divdi */
792 COSTS_N_INSNS (5), /* fp */
793 COSTS_N_INSNS (5), /* dmul */
794 COSTS_N_INSNS (19), /* sdiv */
795 COSTS_N_INSNS (33), /* ddiv */
796 32, /* cache line size */
800 0, /* SF->DF convert */
803 /* Instruction costs on PPC476 processors. */
805 struct processor_costs ppc476_cost = {
806 COSTS_N_INSNS (4), /* mulsi */
807 COSTS_N_INSNS (4), /* mulsi_const */
808 COSTS_N_INSNS (4), /* mulsi_const9 */
809 COSTS_N_INSNS (4), /* muldi */
810 COSTS_N_INSNS (11), /* divsi */
811 COSTS_N_INSNS (11), /* divdi */
812 COSTS_N_INSNS (6), /* fp */
813 COSTS_N_INSNS (6), /* dmul */
814 COSTS_N_INSNS (19), /* sdiv */
815 COSTS_N_INSNS (33), /* ddiv */
816 32, /* l1 cache line size */
820 0, /* SF->DF convert */
823 /* Instruction costs on PPC601 processors. */
825 struct processor_costs ppc601_cost = {
826 COSTS_N_INSNS (5), /* mulsi */
827 COSTS_N_INSNS (5), /* mulsi_const */
828 COSTS_N_INSNS (5), /* mulsi_const9 */
829 COSTS_N_INSNS (5), /* muldi */
830 COSTS_N_INSNS (36), /* divsi */
831 COSTS_N_INSNS (36), /* divdi */
832 COSTS_N_INSNS (4), /* fp */
833 COSTS_N_INSNS (5), /* dmul */
834 COSTS_N_INSNS (17), /* sdiv */
835 COSTS_N_INSNS (31), /* ddiv */
836 32, /* cache line size */
840 0, /* SF->DF convert */
843 /* Instruction costs on PPC603 processors. */
845 struct processor_costs ppc603_cost = {
846 COSTS_N_INSNS (5), /* mulsi */
847 COSTS_N_INSNS (3), /* mulsi_const */
848 COSTS_N_INSNS (2), /* mulsi_const9 */
849 COSTS_N_INSNS (5), /* muldi */
850 COSTS_N_INSNS (37), /* divsi */
851 COSTS_N_INSNS (37), /* divdi */
852 COSTS_N_INSNS (3), /* fp */
853 COSTS_N_INSNS (4), /* dmul */
854 COSTS_N_INSNS (18), /* sdiv */
855 COSTS_N_INSNS (33), /* ddiv */
856 32, /* cache line size */
860 0, /* SF->DF convert */
863 /* Instruction costs on PPC604 processors. */
865 struct processor_costs ppc604_cost = {
866 COSTS_N_INSNS (4), /* mulsi */
867 COSTS_N_INSNS (4), /* mulsi_const */
868 COSTS_N_INSNS (4), /* mulsi_const9 */
869 COSTS_N_INSNS (4), /* muldi */
870 COSTS_N_INSNS (20), /* divsi */
871 COSTS_N_INSNS (20), /* divdi */
872 COSTS_N_INSNS (3), /* fp */
873 COSTS_N_INSNS (3), /* dmul */
874 COSTS_N_INSNS (18), /* sdiv */
875 COSTS_N_INSNS (32), /* ddiv */
876 32, /* cache line size */
880 0, /* SF->DF convert */
883 /* Instruction costs on PPC604e processors. */
885 struct processor_costs ppc604e_cost = {
886 COSTS_N_INSNS (2), /* mulsi */
887 COSTS_N_INSNS (2), /* mulsi_const */
888 COSTS_N_INSNS (2), /* mulsi_const9 */
889 COSTS_N_INSNS (2), /* muldi */
890 COSTS_N_INSNS (20), /* divsi */
891 COSTS_N_INSNS (20), /* divdi */
892 COSTS_N_INSNS (3), /* fp */
893 COSTS_N_INSNS (3), /* dmul */
894 COSTS_N_INSNS (18), /* sdiv */
895 COSTS_N_INSNS (32), /* ddiv */
896 32, /* cache line size */
900 0, /* SF->DF convert */
903 /* Instruction costs on PPC620 processors. */
905 struct processor_costs ppc620_cost = {
906 COSTS_N_INSNS (5), /* mulsi */
907 COSTS_N_INSNS (4), /* mulsi_const */
908 COSTS_N_INSNS (3), /* mulsi_const9 */
909 COSTS_N_INSNS (7), /* muldi */
910 COSTS_N_INSNS (21), /* divsi */
911 COSTS_N_INSNS (37), /* divdi */
912 COSTS_N_INSNS (3), /* fp */
913 COSTS_N_INSNS (3), /* dmul */
914 COSTS_N_INSNS (18), /* sdiv */
915 COSTS_N_INSNS (32), /* ddiv */
916 128, /* cache line size */
920 0, /* SF->DF convert */
923 /* Instruction costs on PPC630 processors. */
925 struct processor_costs ppc630_cost = {
926 COSTS_N_INSNS (5), /* mulsi */
927 COSTS_N_INSNS (4), /* mulsi_const */
928 COSTS_N_INSNS (3), /* mulsi_const9 */
929 COSTS_N_INSNS (7), /* muldi */
930 COSTS_N_INSNS (21), /* divsi */
931 COSTS_N_INSNS (37), /* divdi */
932 COSTS_N_INSNS (3), /* fp */
933 COSTS_N_INSNS (3), /* dmul */
934 COSTS_N_INSNS (17), /* sdiv */
935 COSTS_N_INSNS (21), /* ddiv */
936 128, /* cache line size */
940 0, /* SF->DF convert */
943 /* Instruction costs on Cell processor. */
944 /* COSTS_N_INSNS (1) ~ one add. */
946 struct processor_costs ppccell_cost = {
947 COSTS_N_INSNS (9/2)+2, /* mulsi */
948 COSTS_N_INSNS (6/2), /* mulsi_const */
949 COSTS_N_INSNS (6/2), /* mulsi_const9 */
950 COSTS_N_INSNS (15/2)+2, /* muldi */
951 COSTS_N_INSNS (38/2), /* divsi */
952 COSTS_N_INSNS (70/2), /* divdi */
953 COSTS_N_INSNS (10/2), /* fp */
954 COSTS_N_INSNS (10/2), /* dmul */
955 COSTS_N_INSNS (74/2), /* sdiv */
956 COSTS_N_INSNS (74/2), /* ddiv */
957 128, /* cache line size */
961 0, /* SF->DF convert */
964 /* Instruction costs on PPC750 and PPC7400 processors. */
966 struct processor_costs ppc750_cost = {
967 COSTS_N_INSNS (5), /* mulsi */
968 COSTS_N_INSNS (3), /* mulsi_const */
969 COSTS_N_INSNS (2), /* mulsi_const9 */
970 COSTS_N_INSNS (5), /* muldi */
971 COSTS_N_INSNS (17), /* divsi */
972 COSTS_N_INSNS (17), /* divdi */
973 COSTS_N_INSNS (3), /* fp */
974 COSTS_N_INSNS (3), /* dmul */
975 COSTS_N_INSNS (17), /* sdiv */
976 COSTS_N_INSNS (31), /* ddiv */
977 32, /* cache line size */
981 0, /* SF->DF convert */
984 /* Instruction costs on PPC7450 processors. */
986 struct processor_costs ppc7450_cost = {
987 COSTS_N_INSNS (4), /* mulsi */
988 COSTS_N_INSNS (3), /* mulsi_const */
989 COSTS_N_INSNS (3), /* mulsi_const9 */
990 COSTS_N_INSNS (4), /* muldi */
991 COSTS_N_INSNS (23), /* divsi */
992 COSTS_N_INSNS (23), /* divdi */
993 COSTS_N_INSNS (5), /* fp */
994 COSTS_N_INSNS (5), /* dmul */
995 COSTS_N_INSNS (21), /* sdiv */
996 COSTS_N_INSNS (35), /* ddiv */
997 32, /* cache line size */
1001 0, /* SF->DF convert */
1004 /* Instruction costs on PPC8540 processors. */
1006 struct processor_costs ppc8540_cost = {
1007 COSTS_N_INSNS (4), /* mulsi */
1008 COSTS_N_INSNS (4), /* mulsi_const */
1009 COSTS_N_INSNS (4), /* mulsi_const9 */
1010 COSTS_N_INSNS (4), /* muldi */
1011 COSTS_N_INSNS (19), /* divsi */
1012 COSTS_N_INSNS (19), /* divdi */
1013 COSTS_N_INSNS (4), /* fp */
1014 COSTS_N_INSNS (4), /* dmul */
1015 COSTS_N_INSNS (29), /* sdiv */
1016 COSTS_N_INSNS (29), /* ddiv */
1017 32, /* cache line size */
1020 1, /* prefetch streams /*/
1021 0, /* SF->DF convert */
1024 /* Instruction costs on E300C2 and E300C3 cores. */
1026 struct processor_costs ppce300c2c3_cost = {
1027 COSTS_N_INSNS (4), /* mulsi */
1028 COSTS_N_INSNS (4), /* mulsi_const */
1029 COSTS_N_INSNS (4), /* mulsi_const9 */
1030 COSTS_N_INSNS (4), /* muldi */
1031 COSTS_N_INSNS (19), /* divsi */
1032 COSTS_N_INSNS (19), /* divdi */
1033 COSTS_N_INSNS (3), /* fp */
1034 COSTS_N_INSNS (4), /* dmul */
1035 COSTS_N_INSNS (18), /* sdiv */
1036 COSTS_N_INSNS (33), /* ddiv */
1040 1, /* prefetch streams /*/
1041 0, /* SF->DF convert */
1044 /* Instruction costs on PPCE500MC processors. */
1046 struct processor_costs ppce500mc_cost = {
1047 COSTS_N_INSNS (4), /* mulsi */
1048 COSTS_N_INSNS (4), /* mulsi_const */
1049 COSTS_N_INSNS (4), /* mulsi_const9 */
1050 COSTS_N_INSNS (4), /* muldi */
1051 COSTS_N_INSNS (14), /* divsi */
1052 COSTS_N_INSNS (14), /* divdi */
1053 COSTS_N_INSNS (8), /* fp */
1054 COSTS_N_INSNS (10), /* dmul */
1055 COSTS_N_INSNS (36), /* sdiv */
1056 COSTS_N_INSNS (66), /* ddiv */
1057 64, /* cache line size */
1060 1, /* prefetch streams /*/
1061 0, /* SF->DF convert */
1064 /* Instruction costs on PPCE500MC64 processors. */
1066 struct processor_costs ppce500mc64_cost = {
1067 COSTS_N_INSNS (4), /* mulsi */
1068 COSTS_N_INSNS (4), /* mulsi_const */
1069 COSTS_N_INSNS (4), /* mulsi_const9 */
1070 COSTS_N_INSNS (4), /* muldi */
1071 COSTS_N_INSNS (14), /* divsi */
1072 COSTS_N_INSNS (14), /* divdi */
1073 COSTS_N_INSNS (4), /* fp */
1074 COSTS_N_INSNS (10), /* dmul */
1075 COSTS_N_INSNS (36), /* sdiv */
1076 COSTS_N_INSNS (66), /* ddiv */
1077 64, /* cache line size */
1080 1, /* prefetch streams /*/
1081 0, /* SF->DF convert */
1084 /* Instruction costs on PPCE5500 processors. */
1086 struct processor_costs ppce5500_cost = {
1087 COSTS_N_INSNS (5), /* mulsi */
1088 COSTS_N_INSNS (5), /* mulsi_const */
1089 COSTS_N_INSNS (4), /* mulsi_const9 */
1090 COSTS_N_INSNS (5), /* muldi */
1091 COSTS_N_INSNS (14), /* divsi */
1092 COSTS_N_INSNS (14), /* divdi */
1093 COSTS_N_INSNS (7), /* fp */
1094 COSTS_N_INSNS (10), /* dmul */
1095 COSTS_N_INSNS (36), /* sdiv */
1096 COSTS_N_INSNS (66), /* ddiv */
1097 64, /* cache line size */
1100 1, /* prefetch streams /*/
1101 0, /* SF->DF convert */
1104 /* Instruction costs on PPCE6500 processors. */
1106 struct processor_costs ppce6500_cost = {
1107 COSTS_N_INSNS (5), /* mulsi */
1108 COSTS_N_INSNS (5), /* mulsi_const */
1109 COSTS_N_INSNS (4), /* mulsi_const9 */
1110 COSTS_N_INSNS (5), /* muldi */
1111 COSTS_N_INSNS (14), /* divsi */
1112 COSTS_N_INSNS (14), /* divdi */
1113 COSTS_N_INSNS (7), /* fp */
1114 COSTS_N_INSNS (10), /* dmul */
1115 COSTS_N_INSNS (36), /* sdiv */
1116 COSTS_N_INSNS (66), /* ddiv */
1117 64, /* cache line size */
1120 1, /* prefetch streams /*/
1121 0, /* SF->DF convert */
1124 /* Instruction costs on AppliedMicro Titan processors. */
1126 struct processor_costs titan_cost = {
1127 COSTS_N_INSNS (5), /* mulsi */
1128 COSTS_N_INSNS (5), /* mulsi_const */
1129 COSTS_N_INSNS (5), /* mulsi_const9 */
1130 COSTS_N_INSNS (5), /* muldi */
1131 COSTS_N_INSNS (18), /* divsi */
1132 COSTS_N_INSNS (18), /* divdi */
1133 COSTS_N_INSNS (10), /* fp */
1134 COSTS_N_INSNS (10), /* dmul */
1135 COSTS_N_INSNS (46), /* sdiv */
1136 COSTS_N_INSNS (72), /* ddiv */
1137 32, /* cache line size */
1140 1, /* prefetch streams /*/
1141 0, /* SF->DF convert */
1144 /* Instruction costs on POWER4 and POWER5 processors. */
1146 struct processor_costs power4_cost = {
1147 COSTS_N_INSNS (3), /* mulsi */
1148 COSTS_N_INSNS (2), /* mulsi_const */
1149 COSTS_N_INSNS (2), /* mulsi_const9 */
1150 COSTS_N_INSNS (4), /* muldi */
1151 COSTS_N_INSNS (18), /* divsi */
1152 COSTS_N_INSNS (34), /* divdi */
1153 COSTS_N_INSNS (3), /* fp */
1154 COSTS_N_INSNS (3), /* dmul */
1155 COSTS_N_INSNS (17), /* sdiv */
1156 COSTS_N_INSNS (17), /* ddiv */
1157 128, /* cache line size */
1159 1024, /* l2 cache */
1160 8, /* prefetch streams /*/
1161 0, /* SF->DF convert */
1164 /* Instruction costs on POWER6 processors. */
1166 struct processor_costs power6_cost = {
1167 COSTS_N_INSNS (8), /* mulsi */
1168 COSTS_N_INSNS (8), /* mulsi_const */
1169 COSTS_N_INSNS (8), /* mulsi_const9 */
1170 COSTS_N_INSNS (8), /* muldi */
1171 COSTS_N_INSNS (22), /* divsi */
1172 COSTS_N_INSNS (28), /* divdi */
1173 COSTS_N_INSNS (3), /* fp */
1174 COSTS_N_INSNS (3), /* dmul */
1175 COSTS_N_INSNS (13), /* sdiv */
1176 COSTS_N_INSNS (16), /* ddiv */
1177 128, /* cache line size */
1179 2048, /* l2 cache */
1180 16, /* prefetch streams */
1181 0, /* SF->DF convert */
1184 /* Instruction costs on POWER7 processors. */
1186 struct processor_costs power7_cost = {
1187 COSTS_N_INSNS (2), /* mulsi */
1188 COSTS_N_INSNS (2), /* mulsi_const */
1189 COSTS_N_INSNS (2), /* mulsi_const9 */
1190 COSTS_N_INSNS (2), /* muldi */
1191 COSTS_N_INSNS (18), /* divsi */
1192 COSTS_N_INSNS (34), /* divdi */
1193 COSTS_N_INSNS (3), /* fp */
1194 COSTS_N_INSNS (3), /* dmul */
1195 COSTS_N_INSNS (13), /* sdiv */
1196 COSTS_N_INSNS (16), /* ddiv */
1197 128, /* cache line size */
1200 12, /* prefetch streams */
1201 COSTS_N_INSNS (3), /* SF->DF convert */
1204 /* Instruction costs on POWER8 processors. */
1206 struct processor_costs power8_cost = {
1207 COSTS_N_INSNS (3), /* mulsi */
1208 COSTS_N_INSNS (3), /* mulsi_const */
1209 COSTS_N_INSNS (3), /* mulsi_const9 */
1210 COSTS_N_INSNS (3), /* muldi */
1211 COSTS_N_INSNS (19), /* divsi */
1212 COSTS_N_INSNS (35), /* divdi */
1213 COSTS_N_INSNS (3), /* fp */
1214 COSTS_N_INSNS (3), /* dmul */
1215 COSTS_N_INSNS (14), /* sdiv */
1216 COSTS_N_INSNS (17), /* ddiv */
1217 128, /* cache line size */
1220 12, /* prefetch streams */
1221 COSTS_N_INSNS (3), /* SF->DF convert */
1224 /* Instruction costs on POWER9 processors. */
1226 struct processor_costs power9_cost = {
1227 COSTS_N_INSNS (3), /* mulsi */
1228 COSTS_N_INSNS (3), /* mulsi_const */
1229 COSTS_N_INSNS (3), /* mulsi_const9 */
1230 COSTS_N_INSNS (3), /* muldi */
1231 COSTS_N_INSNS (8), /* divsi */
1232 COSTS_N_INSNS (12), /* divdi */
1233 COSTS_N_INSNS (3), /* fp */
1234 COSTS_N_INSNS (3), /* dmul */
1235 COSTS_N_INSNS (13), /* sdiv */
1236 COSTS_N_INSNS (18), /* ddiv */
1237 128, /* cache line size */
1240 8, /* prefetch streams */
1241 COSTS_N_INSNS (3), /* SF->DF convert */
1244 /* Instruction costs on POWER A2 processors. */
1246 struct processor_costs ppca2_cost = {
1247 COSTS_N_INSNS (16), /* mulsi */
1248 COSTS_N_INSNS (16), /* mulsi_const */
1249 COSTS_N_INSNS (16), /* mulsi_const9 */
1250 COSTS_N_INSNS (16), /* muldi */
1251 COSTS_N_INSNS (22), /* divsi */
1252 COSTS_N_INSNS (28), /* divdi */
1253 COSTS_N_INSNS (3), /* fp */
1254 COSTS_N_INSNS (3), /* dmul */
1255 COSTS_N_INSNS (59), /* sdiv */
1256 COSTS_N_INSNS (72), /* ddiv */
1259 2048, /* l2 cache */
1260 16, /* prefetch streams */
1261 0, /* SF->DF convert */
1265 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1266 #undef RS6000_BUILTIN_0
1267 #undef RS6000_BUILTIN_1
1268 #undef RS6000_BUILTIN_2
1269 #undef RS6000_BUILTIN_3
1270 #undef RS6000_BUILTIN_A
1271 #undef RS6000_BUILTIN_D
1272 #undef RS6000_BUILTIN_H
1273 #undef RS6000_BUILTIN_P
1274 #undef RS6000_BUILTIN_Q
1275 #undef RS6000_BUILTIN_X
1277 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1278 { NAME, ICODE, MASK, ATTR },
1280 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1281 { NAME, ICODE, MASK, ATTR },
1283 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1284 { NAME, ICODE, MASK, ATTR },
1286 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1287 { NAME, ICODE, MASK, ATTR },
1289 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1290 { NAME, ICODE, MASK, ATTR },
1292 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1293 { NAME, ICODE, MASK, ATTR },
1295 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1296 { NAME, ICODE, MASK, ATTR },
1298 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1299 { NAME, ICODE, MASK, ATTR },
1301 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1302 { NAME, ICODE, MASK, ATTR },
1304 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1305 { NAME, ICODE, MASK, ATTR },
1307 struct rs6000_builtin_info_type {
1309 const enum insn_code icode;
1310 const HOST_WIDE_INT mask;
1311 const unsigned attr;
1314 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1316 #include "rs6000-builtin.def"
1319 #undef RS6000_BUILTIN_0
1320 #undef RS6000_BUILTIN_1
1321 #undef RS6000_BUILTIN_2
1322 #undef RS6000_BUILTIN_3
1323 #undef RS6000_BUILTIN_A
1324 #undef RS6000_BUILTIN_D
1325 #undef RS6000_BUILTIN_H
1326 #undef RS6000_BUILTIN_P
1327 #undef RS6000_BUILTIN_Q
1328 #undef RS6000_BUILTIN_X
1330 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1331 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1334 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1335 static struct machine_function * rs6000_init_machine_status (void);
1336 static int rs6000_ra_ever_killed (void);
1337 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1338 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1339 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1340 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1341 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1342 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1343 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1344 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1346 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1348 static bool is_microcoded_insn (rtx_insn *);
1349 static bool is_nonpipeline_insn (rtx_insn *);
1350 static bool is_cracked_insn (rtx_insn *);
1351 static bool is_load_insn (rtx, rtx *);
1352 static bool is_store_insn (rtx, rtx *);
1353 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1354 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1355 static bool insn_must_be_first_in_group (rtx_insn *);
1356 static bool insn_must_be_last_in_group (rtx_insn *);
1357 static void altivec_init_builtins (void);
1358 static tree builtin_function_type (machine_mode, machine_mode,
1359 machine_mode, machine_mode,
1360 enum rs6000_builtins, const char *name);
1361 static void rs6000_common_init_builtins (void);
1362 static void paired_init_builtins (void);
1363 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
1364 static void htm_init_builtins (void);
1365 static rs6000_stack_t *rs6000_stack_info (void);
1366 static void is_altivec_return_reg (rtx, void *);
1367 int easy_vector_constant (rtx, machine_mode);
1368 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1369 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1370 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1373 static void macho_branch_islands (void);
1375 static rtx rs6000_legitimize_reload_address (rtx, machine_mode, int, int,
1377 static rtx rs6000_debug_legitimize_reload_address (rtx, machine_mode, int,
1379 static bool rs6000_mode_dependent_address (const_rtx);
1380 static bool rs6000_debug_mode_dependent_address (const_rtx);
1381 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1383 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1386 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1387 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1389 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1392 static bool rs6000_debug_can_change_mode_class (machine_mode,
1395 static bool rs6000_save_toc_in_prologue_p (void);
1396 static rtx rs6000_internal_arg_pointer (void);
1398 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode, int, int,
1400 = rs6000_legitimize_reload_address;
1402 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1403 = rs6000_mode_dependent_address;
1405 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1407 = rs6000_secondary_reload_class;
1409 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1410 = rs6000_preferred_reload_class;
1412 const int INSN_NOT_AVAILABLE = -1;
1414 static void rs6000_print_isa_options (FILE *, int, const char *,
1416 static void rs6000_print_builtin_options (FILE *, int, const char *,
1418 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1420 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1421 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1422 enum rs6000_reg_type,
1424 secondary_reload_info *,
1426 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1427 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1428 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1430 /* Hash table stuff for keeping track of TOC entries. */
1432 struct GTY((for_user)) toc_hash_struct
1434 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1435 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1437 machine_mode key_mode;
1441 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1443 static hashval_t hash (toc_hash_struct *);
1444 static bool equal (toc_hash_struct *, toc_hash_struct *);
1447 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1449 /* Hash table to keep track of the argument types for builtin functions. */
1451 struct GTY((for_user)) builtin_hash_struct
1454 machine_mode mode[4]; /* return value + 3 arguments. */
1455 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1458 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1460 static hashval_t hash (builtin_hash_struct *);
1461 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1464 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1467 /* Default register names. */
1468 char rs6000_reg_names[][8] =
1470 "0", "1", "2", "3", "4", "5", "6", "7",
1471 "8", "9", "10", "11", "12", "13", "14", "15",
1472 "16", "17", "18", "19", "20", "21", "22", "23",
1473 "24", "25", "26", "27", "28", "29", "30", "31",
1474 "0", "1", "2", "3", "4", "5", "6", "7",
1475 "8", "9", "10", "11", "12", "13", "14", "15",
1476 "16", "17", "18", "19", "20", "21", "22", "23",
1477 "24", "25", "26", "27", "28", "29", "30", "31",
1478 "mq", "lr", "ctr","ap",
1479 "0", "1", "2", "3", "4", "5", "6", "7",
1481 /* AltiVec registers. */
1482 "0", "1", "2", "3", "4", "5", "6", "7",
1483 "8", "9", "10", "11", "12", "13", "14", "15",
1484 "16", "17", "18", "19", "20", "21", "22", "23",
1485 "24", "25", "26", "27", "28", "29", "30", "31",
1487 /* Soft frame pointer. */
1489 /* HTM SPR registers. */
1490 "tfhar", "tfiar", "texasr"
1493 #ifdef TARGET_REGNAMES
1494 static const char alt_reg_names[][8] =
1496 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1497 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1498 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1499 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1500 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1501 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1502 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1503 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1504 "mq", "lr", "ctr", "ap",
1505 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1507 /* AltiVec registers. */
1508 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1509 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1510 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1511 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1513 /* Soft frame pointer. */
1515 /* HTM SPR registers. */
1516 "tfhar", "tfiar", "texasr"
1520 /* Table of valid machine attributes. */
1522 static const struct attribute_spec rs6000_attribute_table[] =
1524 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1525 affects_type_identity, handler, exclude } */
1526 { "altivec", 1, 1, false, true, false, false,
1527 rs6000_handle_altivec_attribute, NULL },
1528 { "longcall", 0, 0, false, true, true, false,
1529 rs6000_handle_longcall_attribute, NULL },
1530 { "shortcall", 0, 0, false, true, true, false,
1531 rs6000_handle_longcall_attribute, NULL },
1532 { "ms_struct", 0, 0, false, false, false, false,
1533 rs6000_handle_struct_attribute, NULL },
1534 { "gcc_struct", 0, 0, false, false, false, false,
1535 rs6000_handle_struct_attribute, NULL },
1536 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1537 SUBTARGET_ATTRIBUTE_TABLE,
1539 { NULL, 0, 0, false, false, false, false, NULL, NULL }
1542 #ifndef TARGET_PROFILE_KERNEL
1543 #define TARGET_PROFILE_KERNEL 0
1546 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1547 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1549 /* Initialize the GCC target structure. */
1550 #undef TARGET_ATTRIBUTE_TABLE
1551 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1552 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1553 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1554 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1555 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1557 #undef TARGET_ASM_ALIGNED_DI_OP
1558 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1560 /* Default unaligned ops are only provided for ELF. Find the ops needed
1561 for non-ELF systems. */
1562 #ifndef OBJECT_FORMAT_ELF
1564 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1566 #undef TARGET_ASM_UNALIGNED_HI_OP
1567 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1568 #undef TARGET_ASM_UNALIGNED_SI_OP
1569 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1570 #undef TARGET_ASM_UNALIGNED_DI_OP
1571 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1574 #undef TARGET_ASM_UNALIGNED_HI_OP
1575 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1576 #undef TARGET_ASM_UNALIGNED_SI_OP
1577 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1578 #undef TARGET_ASM_UNALIGNED_DI_OP
1579 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1580 #undef TARGET_ASM_ALIGNED_DI_OP
1581 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1585 /* This hook deals with fixups for relocatable code and DI-mode objects
1587 #undef TARGET_ASM_INTEGER
1588 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1590 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1591 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1592 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1595 #undef TARGET_SET_UP_BY_PROLOGUE
1596 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1598 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1599 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1600 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1601 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1602 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1603 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1604 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1605 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1606 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1607 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1608 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1609 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1611 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1612 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1614 #undef TARGET_INTERNAL_ARG_POINTER
1615 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1617 #undef TARGET_HAVE_TLS
1618 #define TARGET_HAVE_TLS HAVE_AS_TLS
1620 #undef TARGET_CANNOT_FORCE_CONST_MEM
1621 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1623 #undef TARGET_DELEGITIMIZE_ADDRESS
1624 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1626 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1627 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1629 #undef TARGET_LEGITIMATE_COMBINED_INSN
1630 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1632 #undef TARGET_ASM_FUNCTION_PROLOGUE
1633 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1634 #undef TARGET_ASM_FUNCTION_EPILOGUE
1635 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1637 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1638 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1640 #undef TARGET_LEGITIMIZE_ADDRESS
1641 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1643 #undef TARGET_SCHED_VARIABLE_ISSUE
1644 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1646 #undef TARGET_SCHED_ISSUE_RATE
1647 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1648 #undef TARGET_SCHED_ADJUST_COST
1649 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1650 #undef TARGET_SCHED_ADJUST_PRIORITY
1651 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1652 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1653 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1654 #undef TARGET_SCHED_INIT
1655 #define TARGET_SCHED_INIT rs6000_sched_init
1656 #undef TARGET_SCHED_FINISH
1657 #define TARGET_SCHED_FINISH rs6000_sched_finish
1658 #undef TARGET_SCHED_REORDER
1659 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1660 #undef TARGET_SCHED_REORDER2
1661 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1663 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1664 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1666 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1667 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1669 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1670 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1671 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1672 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1673 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1674 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1675 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1676 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1678 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1679 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1681 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1682 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1683 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1684 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1685 rs6000_builtin_support_vector_misalignment
1686 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1687 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1688 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1689 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1690 rs6000_builtin_vectorization_cost
1691 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1692 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1693 rs6000_preferred_simd_mode
1694 #undef TARGET_VECTORIZE_INIT_COST
1695 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1696 #undef TARGET_VECTORIZE_ADD_STMT_COST
1697 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1698 #undef TARGET_VECTORIZE_FINISH_COST
1699 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1700 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1701 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1703 #undef TARGET_INIT_BUILTINS
1704 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1705 #undef TARGET_BUILTIN_DECL
1706 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1708 #undef TARGET_FOLD_BUILTIN
1709 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1710 #undef TARGET_GIMPLE_FOLD_BUILTIN
1711 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1713 #undef TARGET_EXPAND_BUILTIN
1714 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1716 #undef TARGET_MANGLE_TYPE
1717 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1719 #undef TARGET_INIT_LIBFUNCS
1720 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1723 #undef TARGET_BINDS_LOCAL_P
1724 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1727 #undef TARGET_MS_BITFIELD_LAYOUT_P
1728 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1730 #undef TARGET_ASM_OUTPUT_MI_THUNK
1731 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1733 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1734 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1736 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1737 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1739 #undef TARGET_REGISTER_MOVE_COST
1740 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1741 #undef TARGET_MEMORY_MOVE_COST
1742 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1743 #undef TARGET_CANNOT_COPY_INSN_P
1744 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1745 #undef TARGET_RTX_COSTS
1746 #define TARGET_RTX_COSTS rs6000_rtx_costs
1747 #undef TARGET_ADDRESS_COST
1748 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1749 #undef TARGET_INSN_COST
1750 #define TARGET_INSN_COST rs6000_insn_cost
1752 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1753 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1755 #undef TARGET_PROMOTE_FUNCTION_MODE
1756 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1758 #undef TARGET_RETURN_IN_MEMORY
1759 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1761 #undef TARGET_RETURN_IN_MSB
1762 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1764 #undef TARGET_SETUP_INCOMING_VARARGS
1765 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1767 /* Always strict argument naming on rs6000. */
1768 #undef TARGET_STRICT_ARGUMENT_NAMING
1769 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1770 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1771 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1772 #undef TARGET_SPLIT_COMPLEX_ARG
1773 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1774 #undef TARGET_MUST_PASS_IN_STACK
1775 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1776 #undef TARGET_PASS_BY_REFERENCE
1777 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1778 #undef TARGET_ARG_PARTIAL_BYTES
1779 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1780 #undef TARGET_FUNCTION_ARG_ADVANCE
1781 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1782 #undef TARGET_FUNCTION_ARG
1783 #define TARGET_FUNCTION_ARG rs6000_function_arg
1784 #undef TARGET_FUNCTION_ARG_PADDING
1785 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1786 #undef TARGET_FUNCTION_ARG_BOUNDARY
1787 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1789 #undef TARGET_BUILD_BUILTIN_VA_LIST
1790 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1792 #undef TARGET_EXPAND_BUILTIN_VA_START
1793 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1795 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1796 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1798 #undef TARGET_EH_RETURN_FILTER_MODE
1799 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1801 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1802 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1804 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1805 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1807 #undef TARGET_FLOATN_MODE
1808 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1810 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1811 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1813 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1814 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1816 #undef TARGET_MD_ASM_ADJUST
1817 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1819 #undef TARGET_OPTION_OVERRIDE
1820 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1822 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1823 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1824 rs6000_builtin_vectorized_function
1826 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1827 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1828 rs6000_builtin_md_vectorized_function
1830 #undef TARGET_STACK_PROTECT_GUARD
1831 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1834 #undef TARGET_STACK_PROTECT_FAIL
1835 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1839 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1840 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1843 /* Use a 32-bit anchor range. This leads to sequences like:
1845 addis tmp,anchor,high
1848 where tmp itself acts as an anchor, and can be shared between
1849 accesses to the same 64k page. */
1850 #undef TARGET_MIN_ANCHOR_OFFSET
1851 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1852 #undef TARGET_MAX_ANCHOR_OFFSET
1853 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1854 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1855 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1856 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1857 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1859 #undef TARGET_BUILTIN_RECIPROCAL
1860 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1862 #undef TARGET_SECONDARY_RELOAD
1863 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1864 #undef TARGET_SECONDARY_MEMORY_NEEDED
1865 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1866 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1867 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1869 #undef TARGET_LEGITIMATE_ADDRESS_P
1870 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1872 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1873 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1875 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1876 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1878 #undef TARGET_CAN_ELIMINATE
1879 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1881 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1882 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1884 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1885 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1887 #undef TARGET_TRAMPOLINE_INIT
1888 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1890 #undef TARGET_FUNCTION_VALUE
1891 #define TARGET_FUNCTION_VALUE rs6000_function_value
1893 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1894 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1896 #undef TARGET_OPTION_SAVE
1897 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1899 #undef TARGET_OPTION_RESTORE
1900 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1902 #undef TARGET_OPTION_PRINT
1903 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1905 #undef TARGET_CAN_INLINE_P
1906 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1908 #undef TARGET_SET_CURRENT_FUNCTION
1909 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1911 #undef TARGET_LEGITIMATE_CONSTANT_P
1912 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1914 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1915 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1917 #undef TARGET_CAN_USE_DOLOOP_P
1918 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1920 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1921 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1923 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1924 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1925 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1926 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1927 #undef TARGET_UNWIND_WORD_MODE
1928 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1930 #undef TARGET_OFFLOAD_OPTIONS
1931 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1933 #undef TARGET_C_MODE_FOR_SUFFIX
1934 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1936 #undef TARGET_INVALID_BINARY_OP
1937 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1939 #undef TARGET_OPTAB_SUPPORTED_P
1940 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1942 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1943 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1945 #undef TARGET_COMPARE_VERSION_PRIORITY
1946 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1948 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1949 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1950 rs6000_generate_version_dispatcher_body
1952 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1953 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1954 rs6000_get_function_versions_dispatcher
1956 #undef TARGET_OPTION_FUNCTION_VERSIONS
1957 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1959 #undef TARGET_HARD_REGNO_NREGS
1960 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1961 #undef TARGET_HARD_REGNO_MODE_OK
1962 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1964 #undef TARGET_MODES_TIEABLE_P
1965 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1967 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1968 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1969 rs6000_hard_regno_call_part_clobbered
1971 #undef TARGET_SLOW_UNALIGNED_ACCESS
1972 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1974 #undef TARGET_CAN_CHANGE_MODE_CLASS
1975 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1977 #undef TARGET_CONSTANT_ALIGNMENT
1978 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1980 #undef TARGET_STARTING_FRAME_OFFSET
1981 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1984 /* Processor table. */
1987 const char *const name; /* Canonical processor name. */
1988 const enum processor_type processor; /* Processor type enum value. */
1989 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1992 static struct rs6000_ptt const processor_target_table[] =
1994 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1995 #include "rs6000-cpus.def"
1999 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2003 rs6000_cpu_name_lookup (const char *name)
2009 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2010 if (! strcmp (name, processor_target_table[i].name))
2018 /* Return number of consecutive hard regs needed starting at reg REGNO
2019 to hold something of mode MODE.
2020 This is ordinarily the length in words of a value of mode MODE
2021 but can be less for certain modes in special long registers.
2023 POWER and PowerPC GPRs hold 32 bits worth;
2024 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2027 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2029 unsigned HOST_WIDE_INT reg_size;
2031 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2032 128-bit floating point that can go in vector registers, which has VSX
2033 memory addressing. */
2034 if (FP_REGNO_P (regno))
2035 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2036 ? UNITS_PER_VSX_WORD
2037 : UNITS_PER_FP_WORD);
2039 else if (ALTIVEC_REGNO_P (regno))
2040 reg_size = UNITS_PER_ALTIVEC_WORD;
2043 reg_size = UNITS_PER_WORD;
2045 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2048 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2051 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2053 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2055 if (COMPLEX_MODE_P (mode))
2056 mode = GET_MODE_INNER (mode);
2058 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2059 register combinations, and use PTImode where we need to deal with quad
2060 word memory operations. Don't allow quad words in the argument or frame
2061 pointer registers, just registers 0..31. */
2062 if (mode == PTImode)
2063 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2064 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2065 && ((regno & 1) == 0));
2067 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2068 implementations. Don't allow an item to be split between a FP register
2069 and an Altivec register. Allow TImode in all VSX registers if the user
2071 if (TARGET_VSX && VSX_REGNO_P (regno)
2072 && (VECTOR_MEM_VSX_P (mode)
2073 || FLOAT128_VECTOR_P (mode)
2074 || reg_addr[mode].scalar_in_vmx_p
2076 || (TARGET_VADDUQM && mode == V1TImode)))
2078 if (FP_REGNO_P (regno))
2079 return FP_REGNO_P (last_regno);
2081 if (ALTIVEC_REGNO_P (regno))
2083 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2086 return ALTIVEC_REGNO_P (last_regno);
2090 /* The GPRs can hold any mode, but values bigger than one register
2091 cannot go past R31. */
2092 if (INT_REGNO_P (regno))
2093 return INT_REGNO_P (last_regno);
2095 /* The float registers (except for VSX vector modes) can only hold floating
2096 modes and DImode. */
2097 if (FP_REGNO_P (regno))
2099 if (FLOAT128_VECTOR_P (mode))
2102 if (SCALAR_FLOAT_MODE_P (mode)
2103 && (mode != TDmode || (regno % 2) == 0)
2104 && FP_REGNO_P (last_regno))
2107 if (GET_MODE_CLASS (mode) == MODE_INT)
2109 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2112 if (TARGET_P8_VECTOR && (mode == SImode))
2115 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2119 if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
2120 && PAIRED_VECTOR_MODE (mode))
2126 /* The CR register can only hold CC modes. */
2127 if (CR_REGNO_P (regno))
2128 return GET_MODE_CLASS (mode) == MODE_CC;
2130 if (CA_REGNO_P (regno))
2131 return mode == Pmode || mode == SImode;
2133 /* AltiVec only in AldyVec registers. */
2134 if (ALTIVEC_REGNO_P (regno))
2135 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2136 || mode == V1TImode);
2138 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2139 and it must be able to fit within the register set. */
2141 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2144 /* Implement TARGET_HARD_REGNO_NREGS. */
2147 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2149 return rs6000_hard_regno_nregs[mode][regno];
2152 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2155 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2157 return rs6000_hard_regno_mode_ok_p[mode][regno];
2160 /* Implement TARGET_MODES_TIEABLE_P.
2162 PTImode cannot tie with other modes because PTImode is restricted to even
2163 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2166 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2167 128-bit floating point on VSX systems ties with other vectors. */
2170 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2172 if (mode1 == PTImode)
2173 return mode2 == PTImode;
2174 if (mode2 == PTImode)
2177 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2178 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2179 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2182 if (SCALAR_FLOAT_MODE_P (mode1))
2183 return SCALAR_FLOAT_MODE_P (mode2);
2184 if (SCALAR_FLOAT_MODE_P (mode2))
2187 if (GET_MODE_CLASS (mode1) == MODE_CC)
2188 return GET_MODE_CLASS (mode2) == MODE_CC;
2189 if (GET_MODE_CLASS (mode2) == MODE_CC)
2192 if (PAIRED_VECTOR_MODE (mode1))
2193 return PAIRED_VECTOR_MODE (mode2);
2194 if (PAIRED_VECTOR_MODE (mode2))
2200 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2203 rs6000_hard_regno_call_part_clobbered (unsigned int regno, machine_mode mode)
2207 && GET_MODE_SIZE (mode) > 4
2208 && INT_REGNO_P (regno))
2212 && FP_REGNO_P (regno)
2213 && GET_MODE_SIZE (mode) > 8
2214 && !FLOAT128_2REG_P (mode))
2220 /* Print interesting facts about registers. */
2222 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2226 for (r = first_regno; r <= last_regno; ++r)
2228 const char *comma = "";
2231 if (first_regno == last_regno)
2232 fprintf (stderr, "%s:\t", reg_name);
2234 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2237 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2238 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2242 fprintf (stderr, ",\n\t");
2247 if (rs6000_hard_regno_nregs[m][r] > 1)
2248 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2249 rs6000_hard_regno_nregs[m][r]);
2251 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2256 if (call_used_regs[r])
2260 fprintf (stderr, ",\n\t");
2265 len += fprintf (stderr, "%s%s", comma, "call-used");
2273 fprintf (stderr, ",\n\t");
2278 len += fprintf (stderr, "%s%s", comma, "fixed");
2284 fprintf (stderr, ",\n\t");
2288 len += fprintf (stderr, "%sreg-class = %s", comma,
2289 reg_class_names[(int)rs6000_regno_regclass[r]]);
2294 fprintf (stderr, ",\n\t");
2298 fprintf (stderr, "%sregno = %d\n", comma, r);
2303 rs6000_debug_vector_unit (enum rs6000_vector v)
2309 case VECTOR_NONE: ret = "none"; break;
2310 case VECTOR_ALTIVEC: ret = "altivec"; break;
2311 case VECTOR_VSX: ret = "vsx"; break;
2312 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2313 case VECTOR_PAIRED: ret = "paired"; break;
2314 case VECTOR_OTHER: ret = "other"; break;
2315 default: ret = "unknown"; break;
2321 /* Inner function printing just the address mask for a particular reload
2323 DEBUG_FUNCTION char *
2324 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2329 if ((mask & RELOAD_REG_VALID) != 0)
2331 else if (keep_spaces)
2334 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2336 else if (keep_spaces)
2339 if ((mask & RELOAD_REG_INDEXED) != 0)
2341 else if (keep_spaces)
2344 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2346 else if ((mask & RELOAD_REG_OFFSET) != 0)
2348 else if (keep_spaces)
2351 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2353 else if (keep_spaces)
2356 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2358 else if (keep_spaces)
2361 if ((mask & RELOAD_REG_AND_M16) != 0)
2363 else if (keep_spaces)
2371 /* Print the address masks in a human readble fashion. */
2373 rs6000_debug_print_mode (ssize_t m)
2379 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2380 for (rc = 0; rc < N_RELOAD_REG; rc++)
2381 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2382 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2384 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2385 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2386 fprintf (stderr, " Reload=%c%c",
2387 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2388 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2390 spaces += sizeof (" Reload=sl") - 1;
2392 if (reg_addr[m].scalar_in_vmx_p)
2394 fprintf (stderr, "%*s Upper=y", spaces, "");
2398 spaces += sizeof (" Upper=y") - 1;
2400 fuse_extra_p = ((reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2401 || reg_addr[m].fused_toc);
2404 for (rc = 0; rc < N_RELOAD_REG; rc++)
2406 if (rc != RELOAD_REG_ANY)
2408 if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2409 || reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2410 || reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing
2411 || reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing
2412 || reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2414 fuse_extra_p = true;
2423 fprintf (stderr, "%*s Fuse:", spaces, "");
2426 for (rc = 0; rc < N_RELOAD_REG; rc++)
2428 if (rc != RELOAD_REG_ANY)
2432 if (reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing)
2434 else if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing)
2439 if (reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2441 else if (reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing)
2446 if (load == '-' && store == '-')
2450 fprintf (stderr, "%*s%c=%c%c", (spaces + 1), "",
2451 reload_reg_map[rc].name[0], load, store);
2457 if (reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2459 fprintf (stderr, "%*sP8gpr", (spaces + 1), "");
2463 spaces += sizeof (" P8gpr") - 1;
2465 if (reg_addr[m].fused_toc)
2467 fprintf (stderr, "%*sToc", (spaces + 1), "");
2471 spaces += sizeof (" Toc") - 1;
2474 spaces += sizeof (" Fuse: G=ls F=ls v=ls P8gpr Toc") - 1;
2476 if (rs6000_vector_unit[m] != VECTOR_NONE
2477 || rs6000_vector_mem[m] != VECTOR_NONE)
2479 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2481 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2482 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2485 fputs ("\n", stderr);
2488 #define DEBUG_FMT_ID "%-32s= "
2489 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2490 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2491 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2493 /* Print various interesting information with -mdebug=reg. */
2495 rs6000_debug_reg_global (void)
2497 static const char *const tf[2] = { "false", "true" };
2498 const char *nl = (const char *)0;
2501 char costly_num[20];
2503 char flags_buffer[40];
2504 const char *costly_str;
2505 const char *nop_str;
2506 const char *trace_str;
2507 const char *abi_str;
2508 const char *cmodel_str;
2509 struct cl_target_option cl_opts;
2511 /* Modes we want tieable information on. */
2512 static const machine_mode print_tieable_modes[] = {
2548 /* Virtual regs we are interested in. */
2549 const static struct {
2550 int regno; /* register number. */
2551 const char *name; /* register name. */
2552 } virtual_regs[] = {
2553 { STACK_POINTER_REGNUM, "stack pointer:" },
2554 { TOC_REGNUM, "toc: " },
2555 { STATIC_CHAIN_REGNUM, "static chain: " },
2556 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2557 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2558 { ARG_POINTER_REGNUM, "arg pointer: " },
2559 { FRAME_POINTER_REGNUM, "frame pointer:" },
2560 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2561 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2562 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2563 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2564 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2565 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2566 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2567 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2568 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2571 fputs ("\nHard register information:\n", stderr);
2572 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2573 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2574 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2577 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2578 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2579 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2580 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2581 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2582 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2584 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2585 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2586 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2590 "d reg_class = %s\n"
2591 "f reg_class = %s\n"
2592 "v reg_class = %s\n"
2593 "wa reg_class = %s\n"
2594 "wb reg_class = %s\n"
2595 "wd reg_class = %s\n"
2596 "we reg_class = %s\n"
2597 "wf reg_class = %s\n"
2598 "wg reg_class = %s\n"
2599 "wh reg_class = %s\n"
2600 "wi reg_class = %s\n"
2601 "wj reg_class = %s\n"
2602 "wk reg_class = %s\n"
2603 "wl reg_class = %s\n"
2604 "wm reg_class = %s\n"
2605 "wo reg_class = %s\n"
2606 "wp reg_class = %s\n"
2607 "wq reg_class = %s\n"
2608 "wr reg_class = %s\n"
2609 "ws reg_class = %s\n"
2610 "wt reg_class = %s\n"
2611 "wu reg_class = %s\n"
2612 "wv reg_class = %s\n"
2613 "ww reg_class = %s\n"
2614 "wx reg_class = %s\n"
2615 "wy reg_class = %s\n"
2616 "wz reg_class = %s\n"
2617 "wA reg_class = %s\n"
2618 "wH reg_class = %s\n"
2619 "wI reg_class = %s\n"
2620 "wJ reg_class = %s\n"
2621 "wK reg_class = %s\n"
2623 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2624 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2625 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2626 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2627 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wb]],
2628 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2629 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2630 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2631 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2632 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]],
2633 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2634 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
2635 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
2636 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
2637 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
2638 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wo]],
2639 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2640 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2641 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2642 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2643 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2644 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],
2645 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2646 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2647 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2648 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
2649 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
2650 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
2651 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
2652 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
2653 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
2654 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wK]]);
2657 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2658 rs6000_debug_print_mode (m);
2660 fputs ("\n", stderr);
2662 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2664 machine_mode mode1 = print_tieable_modes[m1];
2665 bool first_time = true;
2667 nl = (const char *)0;
2668 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2670 machine_mode mode2 = print_tieable_modes[m2];
2671 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2675 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2680 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2685 fputs ("\n", stderr);
2691 if (rs6000_recip_control)
2693 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2695 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2696 if (rs6000_recip_bits[m])
2699 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2701 (RS6000_RECIP_AUTO_RE_P (m)
2703 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2704 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2706 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2709 fputs ("\n", stderr);
2712 if (rs6000_cpu_index >= 0)
2714 const char *name = processor_target_table[rs6000_cpu_index].name;
2716 = processor_target_table[rs6000_cpu_index].target_enable;
2718 sprintf (flags_buffer, "-mcpu=%s flags", name);
2719 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2722 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2724 if (rs6000_tune_index >= 0)
2726 const char *name = processor_target_table[rs6000_tune_index].name;
2728 = processor_target_table[rs6000_tune_index].target_enable;
2730 sprintf (flags_buffer, "-mtune=%s flags", name);
2731 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2734 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2736 cl_target_option_save (&cl_opts, &global_options);
2737 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2740 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2741 rs6000_isa_flags_explicit);
2743 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2744 rs6000_builtin_mask);
2746 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2748 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2749 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2751 switch (rs6000_sched_costly_dep)
2753 case max_dep_latency:
2754 costly_str = "max_dep_latency";
2758 costly_str = "no_dep_costly";
2761 case all_deps_costly:
2762 costly_str = "all_deps_costly";
2765 case true_store_to_load_dep_costly:
2766 costly_str = "true_store_to_load_dep_costly";
2769 case store_to_load_dep_costly:
2770 costly_str = "store_to_load_dep_costly";
2774 costly_str = costly_num;
2775 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2779 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2781 switch (rs6000_sched_insert_nops)
2783 case sched_finish_regroup_exact:
2784 nop_str = "sched_finish_regroup_exact";
2787 case sched_finish_pad_groups:
2788 nop_str = "sched_finish_pad_groups";
2791 case sched_finish_none:
2792 nop_str = "sched_finish_none";
2797 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2801 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2803 switch (rs6000_sdata)
2810 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2814 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2818 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2823 switch (rs6000_traceback)
2825 case traceback_default: trace_str = "default"; break;
2826 case traceback_none: trace_str = "none"; break;
2827 case traceback_part: trace_str = "part"; break;
2828 case traceback_full: trace_str = "full"; break;
2829 default: trace_str = "unknown"; break;
2832 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2834 switch (rs6000_current_cmodel)
2836 case CMODEL_SMALL: cmodel_str = "small"; break;
2837 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2838 case CMODEL_LARGE: cmodel_str = "large"; break;
2839 default: cmodel_str = "unknown"; break;
2842 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2844 switch (rs6000_current_abi)
2846 case ABI_NONE: abi_str = "none"; break;
2847 case ABI_AIX: abi_str = "aix"; break;
2848 case ABI_ELFv2: abi_str = "ELFv2"; break;
2849 case ABI_V4: abi_str = "V4"; break;
2850 case ABI_DARWIN: abi_str = "darwin"; break;
2851 default: abi_str = "unknown"; break;
2854 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2856 if (rs6000_altivec_abi)
2857 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2859 if (rs6000_darwin64_abi)
2860 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2862 fprintf (stderr, DEBUG_FMT_S, "single_float",
2863 (TARGET_SINGLE_FLOAT ? "true" : "false"));
2865 fprintf (stderr, DEBUG_FMT_S, "double_float",
2866 (TARGET_DOUBLE_FLOAT ? "true" : "false"));
2868 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2869 (TARGET_SOFT_FLOAT ? "true" : "false"));
2871 if (TARGET_LINK_STACK)
2872 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2874 if (TARGET_P8_FUSION)
2878 strcpy (options, (TARGET_P9_FUSION) ? "power9" : "power8");
2879 if (TARGET_TOC_FUSION)
2880 strcat (options, ", toc");
2882 if (TARGET_P8_FUSION_SIGN)
2883 strcat (options, ", sign");
2885 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2888 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2889 TARGET_SECURE_PLT ? "secure" : "bss");
2890 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2891 aix_struct_return ? "aix" : "sysv");
2892 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2893 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2894 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2895 tf[!!rs6000_align_branch_targets]);
2896 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2897 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2898 rs6000_long_double_type_size);
2899 if (rs6000_long_double_type_size == 128)
2901 fprintf (stderr, DEBUG_FMT_S, "long double type",
2902 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2903 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2904 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2906 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2907 (int)rs6000_sched_restricted_insns_priority);
2908 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2910 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2911 (int)RS6000_BUILTIN_COUNT);
2913 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2914 (int)TARGET_FLOAT128_ENABLE_TYPE);
2917 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2918 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2920 if (TARGET_DIRECT_MOVE_128)
2921 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2922 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2926 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2927 legitimate address support to figure out the appropriate addressing to
2931 rs6000_setup_reg_addr_masks (void)
2933 ssize_t rc, reg, m, nregs;
2934 addr_mask_type any_addr_mask, addr_mask;
2936 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2938 machine_mode m2 = (machine_mode) m;
2939 bool complex_p = false;
2940 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2943 if (COMPLEX_MODE_P (m2))
2946 m2 = GET_MODE_INNER (m2);
2949 msize = GET_MODE_SIZE (m2);
2951 /* SDmode is special in that we want to access it only via REG+REG
2952 addressing on power7 and above, since we want to use the LFIWZX and
2953 STFIWZX instructions to load it. */
2954 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2957 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2960 reg = reload_reg_map[rc].reg;
2962 /* Can mode values go in the GPR/FPR/Altivec registers? */
2963 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2965 bool small_int_vsx_p = (small_int_p
2966 && (rc == RELOAD_REG_FPR
2967 || rc == RELOAD_REG_VMX));
2969 nregs = rs6000_hard_regno_nregs[m][reg];
2970 addr_mask |= RELOAD_REG_VALID;
2972 /* Indicate if the mode takes more than 1 physical register. If
2973 it takes a single register, indicate it can do REG+REG
2974 addressing. Small integers in VSX registers can only do
2975 REG+REG addressing. */
2976 if (small_int_vsx_p)
2977 addr_mask |= RELOAD_REG_INDEXED;
2978 else if (nregs > 1 || m == BLKmode || complex_p)
2979 addr_mask |= RELOAD_REG_MULTIPLE;
2981 addr_mask |= RELOAD_REG_INDEXED;
2983 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2984 addressing. If we allow scalars into Altivec registers,
2985 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2987 For VSX systems, we don't allow update addressing for
2988 DFmode/SFmode if those registers can go in both the
2989 traditional floating point registers and Altivec registers.
2990 The load/store instructions for the Altivec registers do not
2991 have update forms. If we allowed update addressing, it seems
2992 to break IV-OPT code using floating point if the index type is
2993 int instead of long (PR target/81550 and target/84042). */
2996 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2998 && !VECTOR_MODE_P (m2)
2999 && !FLOAT128_VECTOR_P (m2)
3001 && (m != E_DFmode || !TARGET_VSX)
3002 && (m != E_SFmode || !TARGET_P8_VECTOR)
3003 && !small_int_vsx_p)
3005 addr_mask |= RELOAD_REG_PRE_INCDEC;
3007 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
3008 we don't allow PRE_MODIFY for some multi-register
3013 addr_mask |= RELOAD_REG_PRE_MODIFY;
3017 if (TARGET_POWERPC64)
3018 addr_mask |= RELOAD_REG_PRE_MODIFY;
3024 addr_mask |= RELOAD_REG_PRE_MODIFY;
3030 /* GPR and FPR registers can do REG+OFFSET addressing, except
3031 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
3032 for 64-bit scalars and 32-bit SFmode to altivec registers. */
3033 if ((addr_mask != 0) && !indexed_only_p
3035 && (rc == RELOAD_REG_GPR
3036 || ((msize == 8 || m2 == SFmode)
3037 && (rc == RELOAD_REG_FPR
3038 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
3039 addr_mask |= RELOAD_REG_OFFSET;
3041 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
3042 instructions are enabled. The offset for 128-bit VSX registers is
3043 only 12-bits. While GPRs can handle the full offset range, VSX
3044 registers can only handle the restricted range. */
3045 else if ((addr_mask != 0) && !indexed_only_p
3046 && msize == 16 && TARGET_P9_VECTOR
3047 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
3048 || (m2 == TImode && TARGET_VSX)))
3050 addr_mask |= RELOAD_REG_OFFSET;
3051 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
3052 addr_mask |= RELOAD_REG_QUAD_OFFSET;
3055 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
3056 addressing on 128-bit types. */
3057 if (rc == RELOAD_REG_VMX && msize == 16
3058 && (addr_mask & RELOAD_REG_VALID) != 0)
3059 addr_mask |= RELOAD_REG_AND_M16;
3061 reg_addr[m].addr_mask[rc] = addr_mask;
3062 any_addr_mask |= addr_mask;
3065 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
3070 /* Initialize the various global tables that are based on register size. */
3072 rs6000_init_hard_regno_mode_ok (bool global_init_p)
3078 /* Precalculate REGNO_REG_CLASS. */
3079 rs6000_regno_regclass[0] = GENERAL_REGS;
3080 for (r = 1; r < 32; ++r)
3081 rs6000_regno_regclass[r] = BASE_REGS;
3083 for (r = 32; r < 64; ++r)
3084 rs6000_regno_regclass[r] = FLOAT_REGS;
3086 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
3087 rs6000_regno_regclass[r] = NO_REGS;
3089 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
3090 rs6000_regno_regclass[r] = ALTIVEC_REGS;
3092 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
3093 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
3094 rs6000_regno_regclass[r] = CR_REGS;
3096 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
3097 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
3098 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
3099 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
3100 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
3101 rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
3102 rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
3103 rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
3104 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
3105 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
3107 /* Precalculate register class to simpler reload register class. We don't
3108 need all of the register classes that are combinations of different
3109 classes, just the simple ones that have constraint letters. */
3110 for (c = 0; c < N_REG_CLASSES; c++)
3111 reg_class_to_reg_type[c] = NO_REG_TYPE;
3113 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
3114 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
3115 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
3116 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
3117 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
3118 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
3119 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
3120 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
3121 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
3122 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
3126 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
3127 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
3131 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
3132 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3135 /* Precalculate the valid memory formats as well as the vector information,
3136 this must be set up before the rs6000_hard_regno_nregs_internal calls
3138 gcc_assert ((int)VECTOR_NONE == 0);
3139 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3140 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit));
3142 gcc_assert ((int)CODE_FOR_nothing == 0);
3143 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3145 gcc_assert ((int)NO_REGS == 0);
3146 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3148 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3149 believes it can use native alignment or still uses 128-bit alignment. */
3150 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3161 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3162 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3163 if (TARGET_FLOAT128_TYPE)
3165 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3166 rs6000_vector_align[KFmode] = 128;
3168 if (FLOAT128_IEEE_P (TFmode))
3170 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3171 rs6000_vector_align[TFmode] = 128;
3175 /* V2DF mode, VSX only. */
3178 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3179 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3180 rs6000_vector_align[V2DFmode] = align64;
3183 /* V4SF mode, either VSX or Altivec. */
3186 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3187 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3188 rs6000_vector_align[V4SFmode] = align32;
3190 else if (TARGET_ALTIVEC)
3192 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3193 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3194 rs6000_vector_align[V4SFmode] = align32;
3197 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3201 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3202 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3203 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3204 rs6000_vector_align[V4SImode] = align32;
3205 rs6000_vector_align[V8HImode] = align32;
3206 rs6000_vector_align[V16QImode] = align32;
3210 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3211 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3212 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3216 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3217 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3218 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3222 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3223 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3226 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3227 rs6000_vector_unit[V2DImode]
3228 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3229 rs6000_vector_align[V2DImode] = align64;
3231 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3232 rs6000_vector_unit[V1TImode]
3233 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3234 rs6000_vector_align[V1TImode] = 128;
3237 /* DFmode, see if we want to use the VSX unit. Memory is handled
3238 differently, so don't set rs6000_vector_mem. */
3241 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3242 rs6000_vector_align[DFmode] = 64;
3245 /* SFmode, see if we want to use the VSX unit. */
3246 if (TARGET_P8_VECTOR)
3248 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3249 rs6000_vector_align[SFmode] = 32;
3252 /* Allow TImode in VSX register and set the VSX memory macros. */
3255 rs6000_vector_mem[TImode] = VECTOR_VSX;
3256 rs6000_vector_align[TImode] = align64;
3259 /* TODO add paired floating point vector support. */
3261 /* Register class constraints for the constraints that depend on compile
3262 switches. When the VSX code was added, different constraints were added
3263 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3264 of the VSX registers are used. The register classes for scalar floating
3265 point types is set, based on whether we allow that type into the upper
3266 (Altivec) registers. GCC has register classes to target the Altivec
3267 registers for load/store operations, to select using a VSX memory
3268 operation instead of the traditional floating point operation. The
3271 d - Register class to use with traditional DFmode instructions.
3272 f - Register class to use with traditional SFmode instructions.
3273 v - Altivec register.
3274 wa - Any VSX register.
3275 wc - Reserved to represent individual CR bits (used in LLVM).
3276 wd - Preferred register class for V2DFmode.
3277 wf - Preferred register class for V4SFmode.
3278 wg - Float register for power6x move insns.
3279 wh - FP register for direct move instructions.
3280 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3281 wj - FP or VSX register to hold 64-bit integers for direct moves.
3282 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3283 wl - Float register if we can do 32-bit signed int loads.
3284 wm - VSX register for ISA 2.07 direct move operations.
3285 wn - always NO_REGS.
3286 wr - GPR if 64-bit mode is permitted.
3287 ws - Register class to do ISA 2.06 DF operations.
3288 wt - VSX register for TImode in VSX registers.
3289 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3290 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3291 ww - Register class to do SF conversions in with VSX operations.
3292 wx - Float register if we can do 32-bit int stores.
3293 wy - Register class to do ISA 2.07 SF operations.
3294 wz - Float register if we can do 32-bit unsigned int loads.
3295 wH - Altivec register if SImode is allowed in VSX registers.
3296 wI - VSX register if SImode is allowed in VSX registers.
3297 wJ - VSX register if QImode/HImode are allowed in VSX registers.
3298 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3300 if (TARGET_HARD_FLOAT)
3301 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3303 if (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
3304 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3308 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3309 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3310 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3311 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
3312 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
3313 rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
3314 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
3317 /* Add conditional constraints based on various options, to allow us to
3318 collapse multiple insn patterns. */
3320 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3322 if (TARGET_MFPGPR) /* DFmode */
3323 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
3326 rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
3328 if (TARGET_DIRECT_MOVE)
3330 rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS;
3331 rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */
3332 = rs6000_constraints[RS6000_CONSTRAINT_wi];
3333 rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
3334 = rs6000_constraints[RS6000_CONSTRAINT_ws];
3335 rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
3338 if (TARGET_POWERPC64)
3340 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3341 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3344 if (TARGET_P8_VECTOR) /* SFmode */
3346 rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
3347 rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
3348 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3350 else if (TARGET_VSX)
3351 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3354 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3357 rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */
3359 if (TARGET_FLOAT128_TYPE)
3361 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3362 if (FLOAT128_IEEE_P (TFmode))
3363 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3366 if (TARGET_P9_VECTOR)
3368 /* Support for new D-form instructions. */
3369 rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
3371 /* Support for ISA 3.0 (power9) vectors. */
3372 rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS;
3375 /* Support for new direct moves (ISA 3.0 + 64bit). */
3376 if (TARGET_DIRECT_MOVE_128)
3377 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3379 /* Support small integers in VSX registers. */
3380 if (TARGET_P8_VECTOR)
3382 rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
3383 rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
3384 if (TARGET_P9_VECTOR)
3386 rs6000_constraints[RS6000_CONSTRAINT_wJ] = FLOAT_REGS;
3387 rs6000_constraints[RS6000_CONSTRAINT_wK] = ALTIVEC_REGS;
3391 /* Set up the reload helper and direct move functions. */
3392 if (TARGET_VSX || TARGET_ALTIVEC)
3396 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3397 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3398 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3399 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3400 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3401 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3402 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3403 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3404 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3405 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3406 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3407 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3408 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3409 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3410 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3411 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3412 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3413 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3414 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3415 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3417 if (FLOAT128_VECTOR_P (KFmode))
3419 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3420 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3423 if (FLOAT128_VECTOR_P (TFmode))
3425 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3426 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3429 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3431 if (TARGET_NO_SDMODE_STACK)
3433 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3434 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3439 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3440 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3443 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3445 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3446 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3447 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3448 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3449 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3450 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3451 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3452 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3453 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3455 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3456 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3457 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3458 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3459 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3460 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3461 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3462 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3463 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3465 if (FLOAT128_VECTOR_P (KFmode))
3467 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3468 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3471 if (FLOAT128_VECTOR_P (TFmode))
3473 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3474 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3480 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3481 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3482 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3483 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3484 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3485 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3486 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3487 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3488 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3489 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3490 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3491 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3492 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3493 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3494 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3495 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3496 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3497 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3498 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3499 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3501 if (FLOAT128_VECTOR_P (KFmode))
3503 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3504 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3507 if (FLOAT128_IEEE_P (TFmode))
3509 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3510 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3513 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3515 if (TARGET_NO_SDMODE_STACK)
3517 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3518 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3523 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3524 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3527 if (TARGET_DIRECT_MOVE)
3529 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3530 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3531 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3535 reg_addr[DFmode].scalar_in_vmx_p = true;
3536 reg_addr[DImode].scalar_in_vmx_p = true;
3538 if (TARGET_P8_VECTOR)
3540 reg_addr[SFmode].scalar_in_vmx_p = true;
3541 reg_addr[SImode].scalar_in_vmx_p = true;
3543 if (TARGET_P9_VECTOR)
3545 reg_addr[HImode].scalar_in_vmx_p = true;
3546 reg_addr[QImode].scalar_in_vmx_p = true;
3551 /* Setup the fusion operations. */
3552 if (TARGET_P8_FUSION)
3554 reg_addr[QImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_qi;
3555 reg_addr[HImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_hi;
3556 reg_addr[SImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_si;
3558 reg_addr[DImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_di;
3561 if (TARGET_P9_FUSION)
3564 enum machine_mode mode; /* mode of the fused type. */
3565 enum machine_mode pmode; /* pointer mode. */
3566 enum rs6000_reload_reg_type rtype; /* register type. */
3567 enum insn_code load; /* load insn. */
3568 enum insn_code store; /* store insn. */
3571 static const struct fuse_insns addis_insns[] = {
3572 { E_SFmode, E_DImode, RELOAD_REG_FPR,
3573 CODE_FOR_fusion_vsx_di_sf_load,
3574 CODE_FOR_fusion_vsx_di_sf_store },
3576 { E_SFmode, E_SImode, RELOAD_REG_FPR,
3577 CODE_FOR_fusion_vsx_si_sf_load,
3578 CODE_FOR_fusion_vsx_si_sf_store },
3580 { E_DFmode, E_DImode, RELOAD_REG_FPR,
3581 CODE_FOR_fusion_vsx_di_df_load,
3582 CODE_FOR_fusion_vsx_di_df_store },
3584 { E_DFmode, E_SImode, RELOAD_REG_FPR,
3585 CODE_FOR_fusion_vsx_si_df_load,
3586 CODE_FOR_fusion_vsx_si_df_store },
3588 { E_DImode, E_DImode, RELOAD_REG_FPR,
3589 CODE_FOR_fusion_vsx_di_di_load,
3590 CODE_FOR_fusion_vsx_di_di_store },
3592 { E_DImode, E_SImode, RELOAD_REG_FPR,
3593 CODE_FOR_fusion_vsx_si_di_load,
3594 CODE_FOR_fusion_vsx_si_di_store },
3596 { E_QImode, E_DImode, RELOAD_REG_GPR,
3597 CODE_FOR_fusion_gpr_di_qi_load,
3598 CODE_FOR_fusion_gpr_di_qi_store },
3600 { E_QImode, E_SImode, RELOAD_REG_GPR,
3601 CODE_FOR_fusion_gpr_si_qi_load,
3602 CODE_FOR_fusion_gpr_si_qi_store },
3604 { E_HImode, E_DImode, RELOAD_REG_GPR,
3605 CODE_FOR_fusion_gpr_di_hi_load,
3606 CODE_FOR_fusion_gpr_di_hi_store },
3608 { E_HImode, E_SImode, RELOAD_REG_GPR,
3609 CODE_FOR_fusion_gpr_si_hi_load,
3610 CODE_FOR_fusion_gpr_si_hi_store },
3612 { E_SImode, E_DImode, RELOAD_REG_GPR,
3613 CODE_FOR_fusion_gpr_di_si_load,
3614 CODE_FOR_fusion_gpr_di_si_store },
3616 { E_SImode, E_SImode, RELOAD_REG_GPR,
3617 CODE_FOR_fusion_gpr_si_si_load,
3618 CODE_FOR_fusion_gpr_si_si_store },
3620 { E_SFmode, E_DImode, RELOAD_REG_GPR,
3621 CODE_FOR_fusion_gpr_di_sf_load,
3622 CODE_FOR_fusion_gpr_di_sf_store },
3624 { E_SFmode, E_SImode, RELOAD_REG_GPR,
3625 CODE_FOR_fusion_gpr_si_sf_load,
3626 CODE_FOR_fusion_gpr_si_sf_store },
3628 { E_DImode, E_DImode, RELOAD_REG_GPR,
3629 CODE_FOR_fusion_gpr_di_di_load,
3630 CODE_FOR_fusion_gpr_di_di_store },
3632 { E_DFmode, E_DImode, RELOAD_REG_GPR,
3633 CODE_FOR_fusion_gpr_di_df_load,
3634 CODE_FOR_fusion_gpr_di_df_store },
3637 machine_mode cur_pmode = Pmode;
3640 for (i = 0; i < ARRAY_SIZE (addis_insns); i++)
3642 machine_mode xmode = addis_insns[i].mode;
3643 enum rs6000_reload_reg_type rtype = addis_insns[i].rtype;
3645 if (addis_insns[i].pmode != cur_pmode)
3648 if (rtype == RELOAD_REG_FPR && !TARGET_HARD_FLOAT)
3651 reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load;
3652 reg_addr[xmode].fusion_addis_st[rtype] = addis_insns[i].store;
3654 if (rtype == RELOAD_REG_FPR && TARGET_P9_VECTOR)
3656 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX]
3657 = addis_insns[i].load;
3658 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX]
3659 = addis_insns[i].store;
3664 /* Note which types we support fusing TOC setup plus memory insn. We only do
3665 fused TOCs for medium/large code models. */
3666 if (TARGET_P8_FUSION && TARGET_TOC_FUSION && TARGET_POWERPC64
3667 && (TARGET_CMODEL != CMODEL_SMALL))
3669 reg_addr[QImode].fused_toc = true;
3670 reg_addr[HImode].fused_toc = true;
3671 reg_addr[SImode].fused_toc = true;
3672 reg_addr[DImode].fused_toc = true;
3673 if (TARGET_HARD_FLOAT)
3675 if (TARGET_SINGLE_FLOAT)
3676 reg_addr[SFmode].fused_toc = true;
3677 if (TARGET_DOUBLE_FLOAT)
3678 reg_addr[DFmode].fused_toc = true;
3682 /* Precalculate HARD_REGNO_NREGS. */
3683 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3684 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3685 rs6000_hard_regno_nregs[m][r]
3686 = rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
3688 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3689 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3690 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3691 if (rs6000_hard_regno_mode_ok_uncached (r, (machine_mode)m))
3692 rs6000_hard_regno_mode_ok_p[m][r] = true;
3694 /* Precalculate CLASS_MAX_NREGS sizes. */
3695 for (c = 0; c < LIM_REG_CLASSES; ++c)
3699 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3700 reg_size = UNITS_PER_VSX_WORD;
3702 else if (c == ALTIVEC_REGS)
3703 reg_size = UNITS_PER_ALTIVEC_WORD;
3705 else if (c == FLOAT_REGS)
3706 reg_size = UNITS_PER_FP_WORD;
3709 reg_size = UNITS_PER_WORD;
3711 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3713 machine_mode m2 = (machine_mode)m;
3714 int reg_size2 = reg_size;
3716 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3718 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3719 reg_size2 = UNITS_PER_FP_WORD;
3721 rs6000_class_max_nregs[m][c]
3722 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3726 /* Calculate which modes to automatically generate code to use a the
3727 reciprocal divide and square root instructions. In the future, possibly
3728 automatically generate the instructions even if the user did not specify
3729 -mrecip. The older machines double precision reciprocal sqrt estimate is
3730 not accurate enough. */
3731 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3733 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3735 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3736 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3737 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3738 if (VECTOR_UNIT_VSX_P (V2DFmode))
3739 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3741 if (TARGET_FRSQRTES)
3742 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3744 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3745 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3746 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3747 if (VECTOR_UNIT_VSX_P (V2DFmode))
3748 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3750 if (rs6000_recip_control)
3752 if (!flag_finite_math_only)
3753 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3755 if (flag_trapping_math)
3756 warning (0, "%qs requires %qs or %qs", "-mrecip",
3757 "-fno-trapping-math", "-ffast-math");
3758 if (!flag_reciprocal_math)
3759 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3761 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3763 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3764 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3765 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3767 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3768 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3769 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3771 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3772 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3773 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3775 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3776 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3777 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3779 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3780 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3781 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3783 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3784 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3785 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3787 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3788 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3789 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3791 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3792 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3793 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3797 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3798 legitimate address support to figure out the appropriate addressing to
3800 rs6000_setup_reg_addr_masks ();
3802 if (global_init_p || TARGET_DEBUG_TARGET)
3804 if (TARGET_DEBUG_REG)
3805 rs6000_debug_reg_global ();
3807 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3809 "SImode variable mult cost = %d\n"
3810 "SImode constant mult cost = %d\n"
3811 "SImode short constant mult cost = %d\n"
3812 "DImode multipliciation cost = %d\n"
3813 "SImode division cost = %d\n"
3814 "DImode division cost = %d\n"
3815 "Simple fp operation cost = %d\n"
3816 "DFmode multiplication cost = %d\n"
3817 "SFmode division cost = %d\n"
3818 "DFmode division cost = %d\n"
3819 "cache line size = %d\n"
3820 "l1 cache size = %d\n"
3821 "l2 cache size = %d\n"
3822 "simultaneous prefetches = %d\n"
3825 rs6000_cost->mulsi_const,
3826 rs6000_cost->mulsi_const9,
3834 rs6000_cost->cache_line_size,
3835 rs6000_cost->l1_cache_size,
3836 rs6000_cost->l2_cache_size,
3837 rs6000_cost->simultaneous_prefetches);
3842 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3845 darwin_rs6000_override_options (void)
3847 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3849 rs6000_altivec_abi = 1;
3850 TARGET_ALTIVEC_VRSAVE = 1;
3851 rs6000_current_abi = ABI_DARWIN;
3853 if (DEFAULT_ABI == ABI_DARWIN
3855 darwin_one_byte_bool = 1;
3857 if (TARGET_64BIT && ! TARGET_POWERPC64)
3859 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3860 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3864 rs6000_default_long_calls = 1;
3865 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3868 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3870 if (!flag_mkernel && !flag_apple_kext
3872 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3873 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3875 /* Unless the user (not the configurer) has explicitly overridden
3876 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3877 G4 unless targeting the kernel. */
3880 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3881 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3882 && ! global_options_set.x_rs6000_cpu_index)
3884 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3889 /* If not otherwise specified by a target, make 'long double' equivalent to
3892 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3893 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3896 /* Return the builtin mask of the various options used that could affect which
3897 builtins were used. In the past we used target_flags, but we've run out of
3898 bits, and some options like PAIRED are no longer in target_flags. */
3901 rs6000_builtin_mask_calculate (void)
3903 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3904 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3905 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3906 | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
3907 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3908 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3909 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3910 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3911 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3912 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3913 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3914 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3915 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3916 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3917 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3918 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3919 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3920 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3921 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3922 | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0)
3923 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3924 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3927 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3928 to clobber the XER[CA] bit because clobbering that bit without telling
3929 the compiler worked just fine with versions of GCC before GCC 5, and
3930 breaking a lot of older code in ways that are hard to track down is
3931 not such a great idea. */
3934 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3935 vec<const char *> &/*constraints*/,
3936 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3938 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3939 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3943 /* Override command line options.
3945 Combine build-specific configuration information with options
3946 specified on the command line to set various state variables which
3947 influence code generation, optimization, and expansion of built-in
3948 functions. Assure that command-line configuration preferences are
3949 compatible with each other and with the build configuration; issue
3950 warnings while adjusting configuration or error messages while
3951 rejecting configuration.
3953 Upon entry to this function:
3955 This function is called once at the beginning of
3956 compilation, and then again at the start and end of compiling
3957 each section of code that has a different configuration, as
3958 indicated, for example, by adding the
3960 __attribute__((__target__("cpu=power9")))
3962 qualifier to a function definition or, for example, by bracketing
3965 #pragma GCC target("altivec")
3969 #pragma GCC reset_options
3971 directives. Parameter global_init_p is true for the initial
3972 invocation, which initializes global variables, and false for all
3973 subsequent invocations.
3976 Various global state information is assumed to be valid. This
3977 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3978 default CPU specified at build configure time, TARGET_DEFAULT,
3979 representing the default set of option flags for the default
3980 target, and global_options_set.x_rs6000_isa_flags, representing
3981 which options were requested on the command line.
3983 Upon return from this function:
3985 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3986 was set by name on the command line. Additionally, if certain
3987 attributes are automatically enabled or disabled by this function
3988 in order to assure compatibility between options and
3989 configuration, the flags associated with those attributes are
3990 also set. By setting these "explicit bits", we avoid the risk
3991 that other code might accidentally overwrite these particular
3992 attributes with "default values".
3994 The various bits of rs6000_isa_flags are set to indicate the
3995 target options that have been selected for the most current
3996 compilation efforts. This has the effect of also turning on the
3997 associated TARGET_XXX values since these are macros which are
3998 generally defined to test the corresponding bit of the
3999 rs6000_isa_flags variable.
4001 The variable rs6000_builtin_mask is set to represent the target
4002 options for the most current compilation efforts, consistent with
4003 the current contents of rs6000_isa_flags. This variable controls
4004 expansion of built-in functions.
4006 Various other global variables and fields of global structures
4007 (over 50 in all) are initialized to reflect the desired options
4008 for the most current compilation efforts. */
4011 rs6000_option_override_internal (bool global_init_p)
4015 HOST_WIDE_INT set_masks;
4016 HOST_WIDE_INT ignore_masks;
4019 struct cl_target_option *main_target_opt
4020 = ((global_init_p || target_option_default_node == NULL)
4021 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
4023 /* Print defaults. */
4024 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
4025 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
4027 /* Remember the explicit arguments. */
4029 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
4031 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
4032 library functions, so warn about it. The flag may be useful for
4033 performance studies from time to time though, so don't disable it
4035 if (global_options_set.x_rs6000_alignment_flags
4036 && rs6000_alignment_flags == MASK_ALIGN_POWER
4037 && DEFAULT_ABI == ABI_DARWIN
4039 warning (0, "%qs is not supported for 64-bit Darwin;"
4040 " it is incompatible with the installed C and C++ libraries",
4043 /* Numerous experiment shows that IRA based loop pressure
4044 calculation works better for RTL loop invariant motion on targets
4045 with enough (>= 32) registers. It is an expensive optimization.
4046 So it is on only for peak performance. */
4047 if (optimize >= 3 && global_init_p
4048 && !global_options_set.x_flag_ira_loop_pressure)
4049 flag_ira_loop_pressure = 1;
4051 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
4052 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
4053 options were already specified. */
4054 if (flag_sanitize & SANITIZE_USER_ADDRESS
4055 && !global_options_set.x_flag_asynchronous_unwind_tables)
4056 flag_asynchronous_unwind_tables = 1;
4058 /* Set the pointer size. */
4061 rs6000_pmode = DImode;
4062 rs6000_pointer_size = 64;
4066 rs6000_pmode = SImode;
4067 rs6000_pointer_size = 32;
4070 /* Some OSs don't support saving the high part of 64-bit registers on context
4071 switch. Other OSs don't support saving Altivec registers. On those OSs,
4072 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
4073 if the user wants either, the user must explicitly specify them and we
4074 won't interfere with the user's specification. */
4076 set_masks = POWERPC_MASKS;
4077 #ifdef OS_MISSING_POWERPC64
4078 if (OS_MISSING_POWERPC64)
4079 set_masks &= ~OPTION_MASK_POWERPC64;
4081 #ifdef OS_MISSING_ALTIVEC
4082 if (OS_MISSING_ALTIVEC)
4083 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
4084 | OTHER_VSX_VECTOR_MASKS);
4087 /* Don't override by the processor default if given explicitly. */
4088 set_masks &= ~rs6000_isa_flags_explicit;
4090 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
4091 the cpu in a target attribute or pragma, but did not specify a tuning
4092 option, use the cpu for the tuning option rather than the option specified
4093 with -mtune on the command line. Process a '--with-cpu' configuration
4094 request as an implicit --cpu. */
4095 if (rs6000_cpu_index >= 0)
4096 cpu_index = rs6000_cpu_index;
4097 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
4098 cpu_index = main_target_opt->x_rs6000_cpu_index;
4099 else if (OPTION_TARGET_CPU_DEFAULT)
4100 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
4104 const char *unavailable_cpu = NULL;
4105 switch (processor_target_table[cpu_index].processor)
4107 #ifndef HAVE_AS_POWER9
4108 case PROCESSOR_POWER9:
4109 unavailable_cpu = "power9";
4112 #ifndef HAVE_AS_POWER8
4113 case PROCESSOR_POWER8:
4114 unavailable_cpu = "power8";
4117 #ifndef HAVE_AS_POPCNTD
4118 case PROCESSOR_POWER7:
4119 unavailable_cpu = "power7";
4123 case PROCESSOR_POWER6:
4124 unavailable_cpu = "power6";
4127 #ifndef HAVE_AS_POPCNTB
4128 case PROCESSOR_POWER5:
4129 unavailable_cpu = "power5";
4135 if (unavailable_cpu)
4138 warning (0, "will not generate %qs instructions because "
4139 "assembler lacks %qs support", unavailable_cpu,
4144 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
4145 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
4146 with those from the cpu, except for options that were explicitly set. If
4147 we don't have a cpu, do not override the target bits set in
4151 rs6000_cpu_index = cpu_index;
4152 rs6000_isa_flags &= ~set_masks;
4153 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
4158 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
4159 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
4160 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
4161 to using rs6000_isa_flags, we need to do the initialization here.
4163 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
4164 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
4165 HOST_WIDE_INT flags;
4167 flags = TARGET_DEFAULT;
4170 /* PowerPC 64-bit LE requires at least ISA 2.07. */
4171 const char *default_cpu = (!TARGET_POWERPC64
4176 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
4177 flags = processor_target_table[default_cpu_index].target_enable;
4179 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
4182 if (rs6000_tune_index >= 0)
4183 tune_index = rs6000_tune_index;
4184 else if (cpu_index >= 0)
4185 rs6000_tune_index = tune_index = cpu_index;
4189 enum processor_type tune_proc
4190 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
4193 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
4194 if (processor_target_table[i].processor == tune_proc)
4202 rs6000_cpu = processor_target_table[cpu_index].processor;
4204 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
4206 gcc_assert (tune_index >= 0);
4207 rs6000_tune = processor_target_table[tune_index].processor;
4209 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
4210 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
4211 || rs6000_cpu == PROCESSOR_PPCE5500)
4214 error ("AltiVec not supported in this target");
4217 /* If we are optimizing big endian systems for space, use the load/store
4218 multiple instructions. */
4219 if (BYTES_BIG_ENDIAN && optimize_size)
4220 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE;
4222 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
4223 because the hardware doesn't support the instructions used in little
4224 endian mode, and causes an alignment trap. The 750 does not cause an
4225 alignment trap (except when the target is unaligned). */
4227 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750 && TARGET_MULTIPLE)
4229 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
4230 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
4231 warning (0, "%qs is not supported on little endian systems",
4235 /* If little-endian, default to -mstrict-align on older processors.
4236 Testing for htm matches power8 and later. */
4237 if (!BYTES_BIG_ENDIAN
4238 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
4239 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
4241 /* -maltivec={le,be} implies -maltivec. */
4242 if (rs6000_altivec_element_order != 0)
4243 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
4245 /* Disallow -maltivec=le in big endian mode for now. This is not
4246 known to be useful for anyone. */
4247 if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1)
4249 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
4250 rs6000_altivec_element_order = 0;
4253 if (!rs6000_fold_gimple)
4255 "gimple folding of rs6000 builtins has been disabled.\n");
4257 /* Add some warnings for VSX. */
4260 const char *msg = NULL;
4261 if (!TARGET_HARD_FLOAT || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
4263 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4264 msg = N_("-mvsx requires hardware floating point");
4267 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4268 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4271 else if (TARGET_PAIRED_FLOAT)
4272 msg = N_("-mvsx and -mpaired are incompatible");
4273 else if (TARGET_AVOID_XFORM > 0)
4274 msg = N_("-mvsx needs indexed addressing");
4275 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
4276 & OPTION_MASK_ALTIVEC))
4278 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4279 msg = N_("-mvsx and -mno-altivec are incompatible");
4281 msg = N_("-mno-altivec disables vsx");
4287 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4288 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4292 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4293 the -mcpu setting to enable options that conflict. */
4294 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
4295 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
4296 | OPTION_MASK_ALTIVEC
4297 | OPTION_MASK_VSX)) != 0)
4298 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
4299 | OPTION_MASK_DIRECT_MOVE)
4300 & ~rs6000_isa_flags_explicit);
4302 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4303 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
4305 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
4306 off all of the options that depend on those flags. */
4307 ignore_masks = rs6000_disable_incompatible_switches ();
4309 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4310 unless the user explicitly used the -mno-<option> to disable the code. */
4311 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
4312 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4313 else if (TARGET_P9_MINMAX)
4317 if (cpu_index == PROCESSOR_POWER9)
4319 /* legacy behavior: allow -mcpu=power9 with certain
4320 capabilities explicitly disabled. */
4321 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4324 error ("power9 target option is incompatible with %<%s=<xxx>%> "
4325 "for <xxx> less than power9", "-mcpu");
4327 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
4328 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
4329 & rs6000_isa_flags_explicit))
4330 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
4331 were explicitly cleared. */
4332 error ("%qs incompatible with explicitly disabled options",
4335 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
4337 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
4338 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
4339 else if (TARGET_VSX)
4340 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
4341 else if (TARGET_POPCNTD)
4342 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
4343 else if (TARGET_DFP)
4344 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
4345 else if (TARGET_CMPB)
4346 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
4347 else if (TARGET_FPRND)
4348 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
4349 else if (TARGET_POPCNTB)
4350 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
4351 else if (TARGET_ALTIVEC)
4352 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
4354 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
4356 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
4357 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4358 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
4361 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
4363 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
4364 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4365 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
4368 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
4370 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4371 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4372 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4375 if (TARGET_P8_VECTOR && !TARGET_VSX)
4377 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4378 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
4379 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4380 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4382 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4383 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4384 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4388 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4390 rs6000_isa_flags |= OPTION_MASK_VSX;
4391 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4395 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4397 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4398 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4399 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4402 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4403 silently turn off quad memory mode. */
4404 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4406 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4407 warning (0, N_("-mquad-memory requires 64-bit mode"));
4409 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4410 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
4412 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4413 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4416 /* Non-atomic quad memory load/store are disabled for little endian, since
4417 the words are reversed, but atomic operations can still be done by
4418 swapping the words. */
4419 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4421 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4422 warning (0, N_("-mquad-memory is not available in little endian "
4425 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4428 /* Assume if the user asked for normal quad memory instructions, they want
4429 the atomic versions as well, unless they explicity told us not to use quad
4430 word atomic instructions. */
4431 if (TARGET_QUAD_MEMORY
4432 && !TARGET_QUAD_MEMORY_ATOMIC
4433 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4434 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4436 /* If we can shrink-wrap the TOC register save separately, then use
4437 -msave-toc-indirect unless explicitly disabled. */
4438 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4439 && flag_shrink_wrap_separate
4440 && optimize_function_for_speed_p (cfun))
4441 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4443 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4444 generating power8 instructions. */
4445 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4446 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4447 & OPTION_MASK_P8_FUSION);
4449 /* Setting additional fusion flags turns on base fusion. */
4450 if (!TARGET_P8_FUSION && (TARGET_P8_FUSION_SIGN || TARGET_TOC_FUSION))
4452 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4454 if (TARGET_P8_FUSION_SIGN)
4455 error ("%qs requires %qs", "-mpower8-fusion-sign",
4458 if (TARGET_TOC_FUSION)
4459 error ("%qs requires %qs", "-mtoc-fusion", "-mpower8-fusion");
4461 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4464 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4467 /* Power9 fusion is a superset over power8 fusion. */
4468 if (TARGET_P9_FUSION && !TARGET_P8_FUSION)
4470 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4472 /* We prefer to not mention undocumented options in
4473 error messages. However, if users have managed to select
4474 power9-fusion without selecting power8-fusion, they
4475 already know about undocumented flags. */
4476 error ("%qs requires %qs", "-mpower9-fusion", "-mpower8-fusion");
4477 rs6000_isa_flags &= ~OPTION_MASK_P9_FUSION;
4480 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4483 /* Enable power9 fusion if we are tuning for power9, even if we aren't
4484 generating power9 instructions. */
4485 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_FUSION))
4486 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4487 & OPTION_MASK_P9_FUSION);
4489 /* Power8 does not fuse sign extended loads with the addis. If we are
4490 optimizing at high levels for speed, convert a sign extended load into a
4491 zero extending load, and an explicit sign extension. */
4492 if (TARGET_P8_FUSION
4493 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4494 && optimize_function_for_speed_p (cfun)
4496 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4498 /* TOC fusion requires 64-bit and medium/large code model. */
4499 if (TARGET_TOC_FUSION && !TARGET_POWERPC64)
4501 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4502 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4503 warning (0, N_("-mtoc-fusion requires 64-bit"));
4506 if (TARGET_TOC_FUSION && (TARGET_CMODEL == CMODEL_SMALL))
4508 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4509 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4510 warning (0, N_("-mtoc-fusion requires medium/large code model"));
4513 /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
4515 if (TARGET_P8_FUSION && !TARGET_TOC_FUSION && TARGET_POWERPC64
4516 && (TARGET_CMODEL != CMODEL_SMALL)
4517 && !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION))
4518 rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
4520 /* ISA 3.0 vector instructions include ISA 2.07. */
4521 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4523 /* We prefer to not mention undocumented options in
4524 error messages. However, if users have managed to select
4525 power9-vector without selecting power8-vector, they
4526 already know about undocumented flags. */
4527 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4528 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4529 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4530 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4532 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4533 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4534 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4538 /* OPTION_MASK_P9_VECTOR is explicit and
4539 OPTION_MASK_P8_VECTOR is not explicit. */
4540 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4541 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4545 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4546 support. If we only have ISA 2.06 support, and the user did not specify
4547 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4548 but we don't enable the full vectorization support */
4549 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4550 TARGET_ALLOW_MOVMISALIGN = 1;
4552 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4554 if (TARGET_ALLOW_MOVMISALIGN > 0
4555 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4556 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4558 TARGET_ALLOW_MOVMISALIGN = 0;
4561 /* Determine when unaligned vector accesses are permitted, and when
4562 they are preferred over masked Altivec loads. Note that if
4563 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4564 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4566 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4570 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4571 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4573 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4576 else if (!TARGET_ALLOW_MOVMISALIGN)
4578 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4579 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4580 "-mallow-movmisalign");
4582 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4586 /* Set long double size before the IEEE 128-bit tests. */
4587 if (!global_options_set.x_rs6000_long_double_type_size)
4589 if (main_target_opt != NULL
4590 && (main_target_opt->x_rs6000_long_double_type_size
4591 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
4592 error ("target attribute or pragma changes long double size");
4594 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
4597 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4598 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4599 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4600 those systems will not pick up this default. Warn if the user changes the
4601 default unless either the user used the -Wno-psabi option, or the compiler
4602 was built to enable multilibs to switch between the two long double
4604 if (!global_options_set.x_rs6000_ieeequad)
4605 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4607 else if (!TARGET_IEEEQUAD_MULTILIB
4608 && rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT
4609 && TARGET_LONG_DOUBLE_128)
4611 static bool warned_change_long_double;
4612 if (!warned_change_long_double)
4614 warned_change_long_double = true;
4615 if (TARGET_IEEEQUAD)
4616 warning (OPT_Wpsabi, "Using IEEE extended precision long double");
4618 warning (OPT_Wpsabi, "Using IBM extended precision long double");
4622 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4623 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4624 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4625 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4626 the keyword as well as the type. */
4627 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4629 /* IEEE 128-bit floating point requires VSX support. */
4630 if (TARGET_FLOAT128_KEYWORD)
4634 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4635 error ("%qs requires VSX support", "-mfloat128");
4637 TARGET_FLOAT128_TYPE = 0;
4638 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4639 | OPTION_MASK_FLOAT128_HW);
4641 else if (!TARGET_FLOAT128_TYPE)
4643 TARGET_FLOAT128_TYPE = 1;
4644 warning (0, "The -mfloat128 option may not be fully supported");
4648 /* Enable the __float128 keyword under Linux by default. */
4649 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4650 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4651 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4653 /* If we have are supporting the float128 type and full ISA 3.0 support,
4654 enable -mfloat128-hardware by default. However, don't enable the
4655 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4656 because sometimes the compiler wants to put things in an integer
4657 container, and if we don't have __int128 support, it is impossible. */
4658 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4659 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4660 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4661 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4663 if (TARGET_FLOAT128_HW
4664 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4666 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4667 error ("%qs requires full ISA 3.0 support", "-mfloat128-hardware");
4669 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4672 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4674 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4675 error ("%qs requires %qs", "-mfloat128-hardware", "-m64");
4677 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4680 /* Print the options after updating the defaults. */
4681 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4682 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4684 /* E500mc does "better" if we inline more aggressively. Respect the
4685 user's opinion, though. */
4686 if (rs6000_block_move_inline_limit == 0
4687 && (rs6000_tune == PROCESSOR_PPCE500MC
4688 || rs6000_tune == PROCESSOR_PPCE500MC64
4689 || rs6000_tune == PROCESSOR_PPCE5500
4690 || rs6000_tune == PROCESSOR_PPCE6500))
4691 rs6000_block_move_inline_limit = 128;
4693 /* store_one_arg depends on expand_block_move to handle at least the
4694 size of reg_parm_stack_space. */
4695 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4696 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4700 /* If the appropriate debug option is enabled, replace the target hooks
4701 with debug versions that call the real version and then prints
4702 debugging information. */
4703 if (TARGET_DEBUG_COST)
4705 targetm.rtx_costs = rs6000_debug_rtx_costs;
4706 targetm.address_cost = rs6000_debug_address_cost;
4707 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4710 if (TARGET_DEBUG_ADDR)
4712 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4713 targetm.legitimize_address = rs6000_debug_legitimize_address;
4714 rs6000_secondary_reload_class_ptr
4715 = rs6000_debug_secondary_reload_class;
4716 targetm.secondary_memory_needed
4717 = rs6000_debug_secondary_memory_needed;
4718 targetm.can_change_mode_class
4719 = rs6000_debug_can_change_mode_class;
4720 rs6000_preferred_reload_class_ptr
4721 = rs6000_debug_preferred_reload_class;
4722 rs6000_legitimize_reload_address_ptr
4723 = rs6000_debug_legitimize_reload_address;
4724 rs6000_mode_dependent_address_ptr
4725 = rs6000_debug_mode_dependent_address;
4728 if (rs6000_veclibabi_name)
4730 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4731 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4734 error ("unknown vectorization library ABI type (%qs) for "
4735 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4741 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4742 target attribute or pragma which automatically enables both options,
4743 unless the altivec ABI was set. This is set by default for 64-bit, but
4745 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4747 TARGET_FLOAT128_TYPE = 0;
4748 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4749 | OPTION_MASK_FLOAT128_KEYWORD)
4750 & ~rs6000_isa_flags_explicit);
4753 /* Enable Altivec ABI for AIX -maltivec. */
4754 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4756 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4757 error ("target attribute or pragma changes AltiVec ABI");
4759 rs6000_altivec_abi = 1;
4762 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4763 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4764 be explicitly overridden in either case. */
4767 if (!global_options_set.x_rs6000_altivec_abi
4768 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4770 if (main_target_opt != NULL &&
4771 !main_target_opt->x_rs6000_altivec_abi)
4772 error ("target attribute or pragma changes AltiVec ABI");
4774 rs6000_altivec_abi = 1;
4778 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4779 So far, the only darwin64 targets are also MACH-O. */
4781 && DEFAULT_ABI == ABI_DARWIN
4784 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4785 error ("target attribute or pragma changes darwin64 ABI");
4788 rs6000_darwin64_abi = 1;
4789 /* Default to natural alignment, for better performance. */
4790 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4794 /* Place FP constants in the constant pool instead of TOC
4795 if section anchors enabled. */
4796 if (flag_section_anchors
4797 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4798 TARGET_NO_FP_IN_TOC = 1;
4800 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4801 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4803 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4804 SUBTARGET_OVERRIDE_OPTIONS;
4806 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4807 SUBSUBTARGET_OVERRIDE_OPTIONS;
4809 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4810 SUB3TARGET_OVERRIDE_OPTIONS;
4813 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4814 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4816 /* For the E500 family of cores, reset the single/double FP flags to let us
4817 check that they remain constant across attributes or pragmas. */
4821 case PROCESSOR_PPC8540:
4822 case PROCESSOR_PPC8548:
4823 case PROCESSOR_PPCE500MC:
4824 case PROCESSOR_PPCE500MC64:
4825 case PROCESSOR_PPCE5500:
4826 case PROCESSOR_PPCE6500:
4827 rs6000_single_float = 0;
4828 rs6000_double_float = 0;
4835 if (main_target_opt)
4837 if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
4838 error ("target attribute or pragma changes single precision floating "
4840 if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
4841 error ("target attribute or pragma changes double precision floating "
4845 rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
4846 && rs6000_tune != PROCESSOR_POWER5
4847 && rs6000_tune != PROCESSOR_POWER6
4848 && rs6000_tune != PROCESSOR_POWER7
4849 && rs6000_tune != PROCESSOR_POWER8
4850 && rs6000_tune != PROCESSOR_POWER9
4851 && rs6000_tune != PROCESSOR_PPCA2
4852 && rs6000_tune != PROCESSOR_CELL
4853 && rs6000_tune != PROCESSOR_PPC476);
4854 rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
4855 || rs6000_tune == PROCESSOR_POWER5
4856 || rs6000_tune == PROCESSOR_POWER7
4857 || rs6000_tune == PROCESSOR_POWER8);
4858 rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
4859 || rs6000_tune == PROCESSOR_POWER5
4860 || rs6000_tune == PROCESSOR_POWER6
4861 || rs6000_tune == PROCESSOR_POWER7
4862 || rs6000_tune == PROCESSOR_POWER8
4863 || rs6000_tune == PROCESSOR_POWER9
4864 || rs6000_tune == PROCESSOR_PPCE500MC
4865 || rs6000_tune == PROCESSOR_PPCE500MC64
4866 || rs6000_tune == PROCESSOR_PPCE5500
4867 || rs6000_tune == PROCESSOR_PPCE6500);
4869 /* Allow debug switches to override the above settings. These are set to -1
4870 in rs6000.opt to indicate the user hasn't directly set the switch. */
4871 if (TARGET_ALWAYS_HINT >= 0)
4872 rs6000_always_hint = TARGET_ALWAYS_HINT;
4874 if (TARGET_SCHED_GROUPS >= 0)
4875 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4877 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4878 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4880 rs6000_sched_restricted_insns_priority
4881 = (rs6000_sched_groups ? 1 : 0);
4883 /* Handle -msched-costly-dep option. */
4884 rs6000_sched_costly_dep
4885 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4887 if (rs6000_sched_costly_dep_str)
4889 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4890 rs6000_sched_costly_dep = no_dep_costly;
4891 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4892 rs6000_sched_costly_dep = all_deps_costly;
4893 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4894 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4895 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4896 rs6000_sched_costly_dep = store_to_load_dep_costly;
4898 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4899 atoi (rs6000_sched_costly_dep_str));
4902 /* Handle -minsert-sched-nops option. */
4903 rs6000_sched_insert_nops
4904 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4906 if (rs6000_sched_insert_nops_str)
4908 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4909 rs6000_sched_insert_nops = sched_finish_none;
4910 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4911 rs6000_sched_insert_nops = sched_finish_pad_groups;
4912 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4913 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4915 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4916 atoi (rs6000_sched_insert_nops_str));
4919 /* Handle stack protector */
4920 if (!global_options_set.x_rs6000_stack_protector_guard)
4921 #ifdef TARGET_THREAD_SSP_OFFSET
4922 rs6000_stack_protector_guard = SSP_TLS;
4924 rs6000_stack_protector_guard = SSP_GLOBAL;
4927 #ifdef TARGET_THREAD_SSP_OFFSET
4928 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4929 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4932 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4935 const char *str = rs6000_stack_protector_guard_offset_str;
4938 long offset = strtol (str, &endp, 0);
4939 if (!*str || *endp || errno)
4940 error ("%qs is not a valid number in %qs", str,
4941 "-mstack-protector-guard-offset=");
4943 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4944 || (TARGET_64BIT && (offset & 3)))
4945 error ("%qs is not a valid offset in %qs", str,
4946 "-mstack-protector-guard-offset=");
4948 rs6000_stack_protector_guard_offset = offset;
4951 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4953 const char *str = rs6000_stack_protector_guard_reg_str;
4954 int reg = decode_reg_name (str);
4956 if (!IN_RANGE (reg, 1, 31))
4957 error ("%qs is not a valid base register in %qs", str,
4958 "-mstack-protector-guard-reg=");
4960 rs6000_stack_protector_guard_reg = reg;
4963 if (rs6000_stack_protector_guard == SSP_TLS
4964 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4965 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4969 #ifdef TARGET_REGNAMES
4970 /* If the user desires alternate register names, copy in the
4971 alternate names now. */
4972 if (TARGET_REGNAMES)
4973 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4976 /* Set aix_struct_return last, after the ABI is determined.
4977 If -maix-struct-return or -msvr4-struct-return was explicitly
4978 used, don't override with the ABI default. */
4979 if (!global_options_set.x_aix_struct_return)
4980 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4983 /* IBM XL compiler defaults to unsigned bitfields. */
4984 if (TARGET_XL_COMPAT)
4985 flag_signed_bitfields = 0;
4988 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4989 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4991 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4993 /* We can only guarantee the availability of DI pseudo-ops when
4994 assembling for 64-bit targets. */
4997 targetm.asm_out.aligned_op.di = NULL;
4998 targetm.asm_out.unaligned_op.di = NULL;
5002 /* Set branch target alignment, if not optimizing for size. */
5005 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
5006 aligned 8byte to avoid misprediction by the branch predictor. */
5007 if (rs6000_tune == PROCESSOR_TITAN
5008 || rs6000_tune == PROCESSOR_CELL)
5010 if (align_functions <= 0)
5011 align_functions = 8;
5012 if (align_jumps <= 0)
5014 if (align_loops <= 0)
5017 if (rs6000_align_branch_targets)
5019 if (align_functions <= 0)
5020 align_functions = 16;
5021 if (align_jumps <= 0)
5023 if (align_loops <= 0)
5025 can_override_loop_align = 1;
5029 if (align_jumps_max_skip <= 0)
5030 align_jumps_max_skip = 15;
5031 if (align_loops_max_skip <= 0)
5032 align_loops_max_skip = 15;
5035 /* Arrange to save and restore machine status around nested functions. */
5036 init_machine_status = rs6000_init_machine_status;
5038 /* We should always be splitting complex arguments, but we can't break
5039 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
5040 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
5041 targetm.calls.split_complex_arg = NULL;
5043 /* The AIX and ELFv1 ABIs define standard function descriptors. */
5044 if (DEFAULT_ABI == ABI_AIX)
5045 targetm.calls.custom_function_descriptors = 0;
5048 /* Initialize rs6000_cost with the appropriate target costs. */
5050 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
5052 switch (rs6000_tune)
5054 case PROCESSOR_RS64A:
5055 rs6000_cost = &rs64a_cost;
5058 case PROCESSOR_MPCCORE:
5059 rs6000_cost = &mpccore_cost;
5062 case PROCESSOR_PPC403:
5063 rs6000_cost = &ppc403_cost;
5066 case PROCESSOR_PPC405:
5067 rs6000_cost = &ppc405_cost;
5070 case PROCESSOR_PPC440:
5071 rs6000_cost = &ppc440_cost;
5074 case PROCESSOR_PPC476:
5075 rs6000_cost = &ppc476_cost;
5078 case PROCESSOR_PPC601:
5079 rs6000_cost = &ppc601_cost;
5082 case PROCESSOR_PPC603:
5083 rs6000_cost = &ppc603_cost;
5086 case PROCESSOR_PPC604:
5087 rs6000_cost = &ppc604_cost;
5090 case PROCESSOR_PPC604e:
5091 rs6000_cost = &ppc604e_cost;
5094 case PROCESSOR_PPC620:
5095 rs6000_cost = &ppc620_cost;
5098 case PROCESSOR_PPC630:
5099 rs6000_cost = &ppc630_cost;
5102 case PROCESSOR_CELL:
5103 rs6000_cost = &ppccell_cost;
5106 case PROCESSOR_PPC750:
5107 case PROCESSOR_PPC7400:
5108 rs6000_cost = &ppc750_cost;
5111 case PROCESSOR_PPC7450:
5112 rs6000_cost = &ppc7450_cost;
5115 case PROCESSOR_PPC8540:
5116 case PROCESSOR_PPC8548:
5117 rs6000_cost = &ppc8540_cost;
5120 case PROCESSOR_PPCE300C2:
5121 case PROCESSOR_PPCE300C3:
5122 rs6000_cost = &ppce300c2c3_cost;
5125 case PROCESSOR_PPCE500MC:
5126 rs6000_cost = &ppce500mc_cost;
5129 case PROCESSOR_PPCE500MC64:
5130 rs6000_cost = &ppce500mc64_cost;
5133 case PROCESSOR_PPCE5500:
5134 rs6000_cost = &ppce5500_cost;
5137 case PROCESSOR_PPCE6500:
5138 rs6000_cost = &ppce6500_cost;
5141 case PROCESSOR_TITAN:
5142 rs6000_cost = &titan_cost;
5145 case PROCESSOR_POWER4:
5146 case PROCESSOR_POWER5:
5147 rs6000_cost = &power4_cost;
5150 case PROCESSOR_POWER6:
5151 rs6000_cost = &power6_cost;
5154 case PROCESSOR_POWER7:
5155 rs6000_cost = &power7_cost;
5158 case PROCESSOR_POWER8:
5159 rs6000_cost = &power8_cost;
5162 case PROCESSOR_POWER9:
5163 rs6000_cost = &power9_cost;
5166 case PROCESSOR_PPCA2:
5167 rs6000_cost = &ppca2_cost;
5176 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
5177 rs6000_cost->simultaneous_prefetches,
5178 global_options.x_param_values,
5179 global_options_set.x_param_values);
5180 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
5181 global_options.x_param_values,
5182 global_options_set.x_param_values);
5183 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
5184 rs6000_cost->cache_line_size,
5185 global_options.x_param_values,
5186 global_options_set.x_param_values);
5187 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
5188 global_options.x_param_values,
5189 global_options_set.x_param_values);
5191 /* Increase loop peeling limits based on performance analysis. */
5192 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
5193 global_options.x_param_values,
5194 global_options_set.x_param_values);
5195 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
5196 global_options.x_param_values,
5197 global_options_set.x_param_values);
5199 /* Use the 'model' -fsched-pressure algorithm by default. */
5200 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
5201 SCHED_PRESSURE_MODEL,
5202 global_options.x_param_values,
5203 global_options_set.x_param_values);
5205 /* If using typedef char *va_list, signal that
5206 __builtin_va_start (&ap, 0) can be optimized to
5207 ap = __builtin_next_arg (0). */
5208 if (DEFAULT_ABI != ABI_V4)
5209 targetm.expand_builtin_va_start = NULL;
5212 /* Set up single/double float flags.
5213 If TARGET_HARD_FLOAT is set, but neither single or double is set,
5214 then set both flags. */
5215 if (TARGET_HARD_FLOAT && rs6000_single_float == 0 && rs6000_double_float == 0)
5216 rs6000_single_float = rs6000_double_float = 1;
5218 /* If not explicitly specified via option, decide whether to generate indexed
5219 load/store instructions. A value of -1 indicates that the
5220 initial value of this variable has not been overwritten. During
5221 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
5222 if (TARGET_AVOID_XFORM == -1)
5223 /* Avoid indexed addressing when targeting Power6 in order to avoid the
5224 DERAT mispredict penalty. However the LVE and STVE altivec instructions
5225 need indexed accesses and the type used is the scalar type of the element
5226 being loaded or stored. */
5227 TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
5228 && !TARGET_ALTIVEC);
5230 /* Set the -mrecip options. */
5231 if (rs6000_recip_name)
5233 char *p = ASTRDUP (rs6000_recip_name);
5235 unsigned int mask, i;
5238 while ((q = strtok (p, ",")) != NULL)
5249 if (!strcmp (q, "default"))
5250 mask = ((TARGET_RECIP_PRECISION)
5251 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
5254 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
5255 if (!strcmp (q, recip_options[i].string))
5257 mask = recip_options[i].mask;
5261 if (i == ARRAY_SIZE (recip_options))
5263 error ("unknown option for %<%s=%s%>", "-mrecip", q);
5271 rs6000_recip_control &= ~mask;
5273 rs6000_recip_control |= mask;
5277 /* Set the builtin mask of the various options used that could affect which
5278 builtins were used. In the past we used target_flags, but we've run out
5279 of bits, and some options like PAIRED are no longer in target_flags. */
5280 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
5281 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
5282 rs6000_print_builtin_options (stderr, 0, "builtin mask",
5283 rs6000_builtin_mask);
5285 /* Initialize all of the registers. */
5286 rs6000_init_hard_regno_mode_ok (global_init_p);
5288 /* Save the initial options in case the user does function specific options */
5290 target_option_default_node = target_option_current_node
5291 = build_target_option_node (&global_options);
5293 /* If not explicitly specified via option, decide whether to generate the
5294 extra blr's required to preserve the link stack on some cpus (eg, 476). */
5295 if (TARGET_LINK_STACK == -1)
5296 SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
5298 /* Deprecate use of -mno-speculate-indirect-jumps. */
5299 if (!rs6000_speculate_indirect_jumps)
5300 warning (0, "%qs is deprecated and not recommended in any circumstances",
5301 "-mno-speculate-indirect-jumps");
5306 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
5307 define the target cpu type. */
5310 rs6000_option_override (void)
5312 (void) rs6000_option_override_internal (true);
5316 /* Implement targetm.vectorize.builtin_mask_for_load. */
5318 rs6000_builtin_mask_for_load (void)
5320 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
5321 if ((TARGET_ALTIVEC && !TARGET_VSX)
5322 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
5323 return altivec_builtin_mask_for_load;
5328 /* Implement LOOP_ALIGN. */
5330 rs6000_loop_align (rtx label)
5335 /* Don't override loop alignment if -falign-loops was specified. */
5336 if (!can_override_loop_align)
5337 return align_loops_log;
5339 bb = BLOCK_FOR_INSN (label);
5340 ninsns = num_loop_insns(bb->loop_father);
5342 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
5343 if (ninsns > 4 && ninsns <= 8
5344 && (rs6000_tune == PROCESSOR_POWER4
5345 || rs6000_tune == PROCESSOR_POWER5
5346 || rs6000_tune == PROCESSOR_POWER6
5347 || rs6000_tune == PROCESSOR_POWER7
5348 || rs6000_tune == PROCESSOR_POWER8
5349 || rs6000_tune == PROCESSOR_POWER9))
5352 return align_loops_log;
5355 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
5357 rs6000_loop_align_max_skip (rtx_insn *label)
5359 return (1 << rs6000_loop_align (label)) - 1;
5362 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5363 after applying N number of iterations. This routine does not determine
5364 how may iterations are required to reach desired alignment. */
5367 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
5374 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
5377 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
5387 /* Assuming that all other types are naturally aligned. CHECKME! */
5392 /* Return true if the vector misalignment factor is supported by the
5395 rs6000_builtin_support_vector_misalignment (machine_mode mode,
5402 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5405 /* Return if movmisalign pattern is not supported for this mode. */
5406 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
5409 if (misalignment == -1)
5411 /* Misalignment factor is unknown at compile time but we know
5412 it's word aligned. */
5413 if (rs6000_vector_alignment_reachable (type, is_packed))
5415 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
5417 if (element_size == 64 || element_size == 32)
5424 /* VSX supports word-aligned vector. */
5425 if (misalignment % 4 == 0)
5431 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5433 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5434 tree vectype, int misalign)
5439 switch (type_of_cost)
5449 case cond_branch_not_taken:
5458 case vec_promote_demote:
5464 case cond_branch_taken:
5467 case unaligned_load:
5468 case vector_gather_load:
5469 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5472 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5474 elements = TYPE_VECTOR_SUBPARTS (vectype);
5476 /* Double word aligned. */
5484 /* Double word aligned. */
5488 /* Unknown misalignment. */
5501 /* Misaligned loads are not supported. */
5506 case unaligned_store:
5507 case vector_scatter_store:
5508 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5511 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5513 elements = TYPE_VECTOR_SUBPARTS (vectype);
5515 /* Double word aligned. */
5523 /* Double word aligned. */
5527 /* Unknown misalignment. */
5540 /* Misaligned stores are not supported. */
5546 /* This is a rough approximation assuming non-constant elements
5547 constructed into a vector via element insertion. FIXME:
5548 vec_construct is not granular enough for uniformly good
5549 decisions. If the initialization is a splat, this is
5550 cheaper than we estimate. Improve this someday. */
5551 elem_type = TREE_TYPE (vectype);
5552 /* 32-bit vectors loaded into registers are stored as double
5553 precision, so we need 2 permutes, 2 converts, and 1 merge
5554 to construct a vector of short floats from them. */
5555 if (SCALAR_FLOAT_TYPE_P (elem_type)
5556 && TYPE_PRECISION (elem_type) == 32)
5558 /* On POWER9, integer vector types are built up in GPRs and then
5559 use a direct move (2 cycles). For POWER8 this is even worse,
5560 as we need two direct moves and a merge, and the direct moves
5562 else if (INTEGRAL_TYPE_P (elem_type))
5564 if (TARGET_P9_VECTOR)
5565 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5567 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5570 /* V2DFmode doesn't need a direct move. */
5578 /* Implement targetm.vectorize.preferred_simd_mode. */
5581 rs6000_preferred_simd_mode (scalar_mode mode)
5590 if (TARGET_ALTIVEC || TARGET_VSX)
5607 if (TARGET_PAIRED_FLOAT
5613 typedef struct _rs6000_cost_data
5615 struct loop *loop_info;
5619 /* Test for likely overcommitment of vector hardware resources. If a
5620 loop iteration is relatively large, and too large a percentage of
5621 instructions in the loop are vectorized, the cost model may not
5622 adequately reflect delays from unavailable vector resources.
5623 Penalize the loop body cost for this case. */
5626 rs6000_density_test (rs6000_cost_data *data)
5628 const int DENSITY_PCT_THRESHOLD = 85;
5629 const int DENSITY_SIZE_THRESHOLD = 70;
5630 const int DENSITY_PENALTY = 10;
5631 struct loop *loop = data->loop_info;
5632 basic_block *bbs = get_loop_body (loop);
5633 int nbbs = loop->num_nodes;
5634 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5637 for (i = 0; i < nbbs; i++)
5639 basic_block bb = bbs[i];
5640 gimple_stmt_iterator gsi;
5642 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5644 gimple *stmt = gsi_stmt (gsi);
5645 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
5647 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5648 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5654 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5656 if (density_pct > DENSITY_PCT_THRESHOLD
5657 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5659 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5660 if (dump_enabled_p ())
5661 dump_printf_loc (MSG_NOTE, vect_location,
5662 "density %d%%, cost %d exceeds threshold, penalizing "
5663 "loop body cost by %d%%", density_pct,
5664 vec_cost + not_vec_cost, DENSITY_PENALTY);
5668 /* Implement targetm.vectorize.init_cost. */
5670 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5671 instruction is needed by the vectorization. */
5672 static bool rs6000_vect_nonmem;
5675 rs6000_init_cost (struct loop *loop_info)
5677 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5678 data->loop_info = loop_info;
5679 data->cost[vect_prologue] = 0;
5680 data->cost[vect_body] = 0;
5681 data->cost[vect_epilogue] = 0;
5682 rs6000_vect_nonmem = false;
5686 /* Implement targetm.vectorize.add_stmt_cost. */
5689 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5690 struct _stmt_vec_info *stmt_info, int misalign,
5691 enum vect_cost_model_location where)
5693 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5694 unsigned retval = 0;
5696 if (flag_vect_cost_model)
5698 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5699 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5701 /* Statements in an inner loop relative to the loop being
5702 vectorized are weighted more heavily. The value here is
5703 arbitrary and could potentially be improved with analysis. */
5704 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5705 count *= 50; /* FIXME. */
5707 retval = (unsigned) (count * stmt_cost);
5708 cost_data->cost[where] += retval;
5710 /* Check whether we're doing something other than just a copy loop.
5711 Not all such loops may be profitably vectorized; see
5712 rs6000_finish_cost. */
5713 if ((kind == vec_to_scalar || kind == vec_perm
5714 || kind == vec_promote_demote || kind == vec_construct
5715 || kind == scalar_to_vec)
5716 || (where == vect_body && kind == vector_stmt))
5717 rs6000_vect_nonmem = true;
5723 /* Implement targetm.vectorize.finish_cost. */
5726 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5727 unsigned *body_cost, unsigned *epilogue_cost)
5729 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5731 if (cost_data->loop_info)
5732 rs6000_density_test (cost_data);
5734 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5735 that require versioning for any reason. The vectorization is at
5736 best a wash inside the loop, and the versioning checks make
5737 profitability highly unlikely and potentially quite harmful. */
5738 if (cost_data->loop_info)
5740 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5741 if (!rs6000_vect_nonmem
5742 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5743 && LOOP_REQUIRES_VERSIONING (vec_info))
5744 cost_data->cost[vect_body] += 10000;
5747 *prologue_cost = cost_data->cost[vect_prologue];
5748 *body_cost = cost_data->cost[vect_body];
5749 *epilogue_cost = cost_data->cost[vect_epilogue];
5752 /* Implement targetm.vectorize.destroy_cost_data. */
5755 rs6000_destroy_cost_data (void *data)
5760 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5761 library with vectorized intrinsics. */
5764 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5768 const char *suffix = NULL;
5769 tree fntype, new_fndecl, bdecl = NULL_TREE;
5772 machine_mode el_mode, in_mode;
5775 /* Libmass is suitable for unsafe math only as it does not correctly support
5776 parts of IEEE with the required precision such as denormals. Only support
5777 it if we have VSX to use the simd d2 or f4 functions.
5778 XXX: Add variable length support. */
5779 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5782 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5783 n = TYPE_VECTOR_SUBPARTS (type_out);
5784 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5785 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5786 if (el_mode != in_mode
5822 if (el_mode == DFmode && n == 2)
5824 bdecl = mathfn_built_in (double_type_node, fn);
5825 suffix = "d2"; /* pow -> powd2 */
5827 else if (el_mode == SFmode && n == 4)
5829 bdecl = mathfn_built_in (float_type_node, fn);
5830 suffix = "4"; /* powf -> powf4 */
5842 gcc_assert (suffix != NULL);
5843 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5847 strcpy (name, bname + sizeof ("__builtin_") - 1);
5848 strcat (name, suffix);
5851 fntype = build_function_type_list (type_out, type_in, NULL);
5852 else if (n_args == 2)
5853 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5857 /* Build a function declaration for the vectorized function. */
5858 new_fndecl = build_decl (BUILTINS_LOCATION,
5859 FUNCTION_DECL, get_identifier (name), fntype);
5860 TREE_PUBLIC (new_fndecl) = 1;
5861 DECL_EXTERNAL (new_fndecl) = 1;
5862 DECL_IS_NOVOPS (new_fndecl) = 1;
5863 TREE_READONLY (new_fndecl) = 1;
5868 /* Returns a function decl for a vectorized version of the builtin function
5869 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5870 if it is not available. */
5873 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5876 machine_mode in_mode, out_mode;
5879 if (TARGET_DEBUG_BUILTIN)
5880 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5881 combined_fn_name (combined_fn (fn)),
5882 GET_MODE_NAME (TYPE_MODE (type_out)),
5883 GET_MODE_NAME (TYPE_MODE (type_in)));
5885 if (TREE_CODE (type_out) != VECTOR_TYPE
5886 || TREE_CODE (type_in) != VECTOR_TYPE)
5889 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5890 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5891 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5892 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5897 if (VECTOR_UNIT_VSX_P (V2DFmode)
5898 && out_mode == DFmode && out_n == 2
5899 && in_mode == DFmode && in_n == 2)
5900 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5901 if (VECTOR_UNIT_VSX_P (V4SFmode)
5902 && out_mode == SFmode && out_n == 4
5903 && in_mode == SFmode && in_n == 4)
5904 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5905 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5906 && out_mode == SFmode && out_n == 4
5907 && in_mode == SFmode && in_n == 4)
5908 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5911 if (VECTOR_UNIT_VSX_P (V2DFmode)
5912 && out_mode == DFmode && out_n == 2
5913 && in_mode == DFmode && in_n == 2)
5914 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5915 if (VECTOR_UNIT_VSX_P (V4SFmode)
5916 && out_mode == SFmode && out_n == 4
5917 && in_mode == SFmode && in_n == 4)
5918 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5919 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5920 && out_mode == SFmode && out_n == 4
5921 && in_mode == SFmode && in_n == 4)
5922 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5925 if (VECTOR_UNIT_VSX_P (V2DFmode)
5926 && out_mode == DFmode && out_n == 2
5927 && in_mode == DFmode && in_n == 2)
5928 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5929 if (VECTOR_UNIT_VSX_P (V4SFmode)
5930 && out_mode == SFmode && out_n == 4
5931 && in_mode == SFmode && in_n == 4)
5932 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5933 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5934 && out_mode == SFmode && out_n == 4
5935 && in_mode == SFmode && in_n == 4)
5936 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5939 if (VECTOR_UNIT_VSX_P (V2DFmode)
5940 && out_mode == DFmode && out_n == 2
5941 && in_mode == DFmode && in_n == 2)
5942 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5943 if (VECTOR_UNIT_VSX_P (V4SFmode)
5944 && out_mode == SFmode && out_n == 4
5945 && in_mode == SFmode && in_n == 4)
5946 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5947 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5948 && out_mode == SFmode && out_n == 4
5949 && in_mode == SFmode && in_n == 4)
5950 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5953 if (VECTOR_UNIT_VSX_P (V2DFmode)
5954 && out_mode == DFmode && out_n == 2
5955 && in_mode == DFmode && in_n == 2)
5956 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5957 if (VECTOR_UNIT_VSX_P (V4SFmode)
5958 && out_mode == SFmode && out_n == 4
5959 && in_mode == SFmode && in_n == 4)
5960 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5961 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5962 && out_mode == SFmode && out_n == 4
5963 && in_mode == SFmode && in_n == 4)
5964 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5967 if (VECTOR_UNIT_VSX_P (V2DFmode)
5968 && flag_unsafe_math_optimizations
5969 && out_mode == DFmode && out_n == 2
5970 && in_mode == DFmode && in_n == 2)
5971 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5972 if (VECTOR_UNIT_VSX_P (V4SFmode)
5973 && flag_unsafe_math_optimizations
5974 && out_mode == SFmode && out_n == 4
5975 && in_mode == SFmode && in_n == 4)
5976 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5979 if (VECTOR_UNIT_VSX_P (V2DFmode)
5980 && !flag_trapping_math
5981 && out_mode == DFmode && out_n == 2
5982 && in_mode == DFmode && in_n == 2)
5983 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5984 if (VECTOR_UNIT_VSX_P (V4SFmode)
5985 && !flag_trapping_math
5986 && out_mode == SFmode && out_n == 4
5987 && in_mode == SFmode && in_n == 4)
5988 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5994 /* Generate calls to libmass if appropriate. */
5995 if (rs6000_veclib_handler)
5996 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
6001 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
6004 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
6007 machine_mode in_mode, out_mode;
6010 if (TARGET_DEBUG_BUILTIN)
6011 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
6012 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
6013 GET_MODE_NAME (TYPE_MODE (type_out)),
6014 GET_MODE_NAME (TYPE_MODE (type_in)));
6016 if (TREE_CODE (type_out) != VECTOR_TYPE
6017 || TREE_CODE (type_in) != VECTOR_TYPE)
6020 out_mode = TYPE_MODE (TREE_TYPE (type_out));
6021 out_n = TYPE_VECTOR_SUBPARTS (type_out);
6022 in_mode = TYPE_MODE (TREE_TYPE (type_in));
6023 in_n = TYPE_VECTOR_SUBPARTS (type_in);
6025 enum rs6000_builtins fn
6026 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
6029 case RS6000_BUILTIN_RSQRTF:
6030 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
6031 && out_mode == SFmode && out_n == 4
6032 && in_mode == SFmode && in_n == 4)
6033 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
6035 case RS6000_BUILTIN_RSQRT:
6036 if (VECTOR_UNIT_VSX_P (V2DFmode)
6037 && out_mode == DFmode && out_n == 2
6038 && in_mode == DFmode && in_n == 2)
6039 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
6041 case RS6000_BUILTIN_RECIPF:
6042 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
6043 && out_mode == SFmode && out_n == 4
6044 && in_mode == SFmode && in_n == 4)
6045 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
6047 case RS6000_BUILTIN_RECIP:
6048 if (VECTOR_UNIT_VSX_P (V2DFmode)
6049 && out_mode == DFmode && out_n == 2
6050 && in_mode == DFmode && in_n == 2)
6051 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
6059 /* Default CPU string for rs6000*_file_start functions. */
6060 static const char *rs6000_default_cpu;
6062 /* Do anything needed at the start of the asm file. */
6065 rs6000_file_start (void)
6068 const char *start = buffer;
6069 FILE *file = asm_out_file;
6071 rs6000_default_cpu = TARGET_CPU_DEFAULT;
6073 default_file_start ();
6075 if (flag_verbose_asm)
6077 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
6079 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
6081 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
6085 if (global_options_set.x_rs6000_cpu_index)
6087 fprintf (file, "%s -mcpu=%s", start,
6088 processor_target_table[rs6000_cpu_index].name);
6092 if (global_options_set.x_rs6000_tune_index)
6094 fprintf (file, "%s -mtune=%s", start,
6095 processor_target_table[rs6000_tune_index].name);
6099 if (PPC405_ERRATUM77)
6101 fprintf (file, "%s PPC405CR_ERRATUM77", start);
6105 #ifdef USING_ELFOS_H
6106 switch (rs6000_sdata)
6108 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
6109 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
6110 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
6111 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
6114 if (rs6000_sdata && g_switch_value)
6116 fprintf (file, "%s -G %d", start,
6126 #ifdef USING_ELFOS_H
6127 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
6128 && !global_options_set.x_rs6000_cpu_index)
6130 fputs ("\t.machine ", asm_out_file);
6131 if ((rs6000_isa_flags & OPTION_MASK_MODULO) != 0)
6132 fputs ("power9\n", asm_out_file);
6133 else if ((rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE) != 0)
6134 fputs ("power8\n", asm_out_file);
6135 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTD) != 0)
6136 fputs ("power7\n", asm_out_file);
6137 else if ((rs6000_isa_flags & OPTION_MASK_CMPB) != 0)
6138 fputs ("power6\n", asm_out_file);
6139 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTB) != 0)
6140 fputs ("power5\n", asm_out_file);
6141 else if ((rs6000_isa_flags & OPTION_MASK_MFCRF) != 0)
6142 fputs ("power4\n", asm_out_file);
6143 else if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
6144 fputs ("ppc64\n", asm_out_file);
6146 fputs ("ppc\n", asm_out_file);
6150 if (DEFAULT_ABI == ABI_ELFv2)
6151 fprintf (file, "\t.abiversion 2\n");
6155 /* Return nonzero if this function is known to have a null epilogue. */
6158 direct_return (void)
6160 if (reload_completed)
6162 rs6000_stack_t *info = rs6000_stack_info ();
6164 if (info->first_gp_reg_save == 32
6165 && info->first_fp_reg_save == 64
6166 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
6167 && ! info->lr_save_p
6168 && ! info->cr_save_p
6169 && info->vrsave_size == 0
6177 /* Return the number of instructions it takes to form a constant in an
6178 integer register. */
6181 num_insns_constant_wide (HOST_WIDE_INT value)
6183 /* signed constant loadable with addi */
6184 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
6187 /* constant loadable with addis */
6188 else if ((value & 0xffff) == 0
6189 && (value >> 31 == -1 || value >> 31 == 0))
6192 else if (TARGET_POWERPC64)
6194 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
6195 HOST_WIDE_INT high = value >> 31;
6197 if (high == 0 || high == -1)
6203 return num_insns_constant_wide (high) + 1;
6205 return num_insns_constant_wide (low) + 1;
6207 return (num_insns_constant_wide (high)
6208 + num_insns_constant_wide (low) + 1);
6216 num_insns_constant (rtx op, machine_mode mode)
6218 HOST_WIDE_INT low, high;
6220 switch (GET_CODE (op))
6223 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
6224 && rs6000_is_valid_and_mask (op, mode))
6227 return num_insns_constant_wide (INTVAL (op));
6229 case CONST_WIDE_INT:
6232 int ins = CONST_WIDE_INT_NUNITS (op) - 1;
6233 for (i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
6234 ins += num_insns_constant_wide (CONST_WIDE_INT_ELT (op, i));
6239 if (mode == SFmode || mode == SDmode)
6243 if (DECIMAL_FLOAT_MODE_P (mode))
6244 REAL_VALUE_TO_TARGET_DECIMAL32
6245 (*CONST_DOUBLE_REAL_VALUE (op), l);
6247 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6248 return num_insns_constant_wide ((HOST_WIDE_INT) l);
6252 if (DECIMAL_FLOAT_MODE_P (mode))
6253 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op), l);
6255 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6256 high = l[WORDS_BIG_ENDIAN == 0];
6257 low = l[WORDS_BIG_ENDIAN != 0];
6260 return (num_insns_constant_wide (low)
6261 + num_insns_constant_wide (high));
6264 if ((high == 0 && low >= 0)
6265 || (high == -1 && low < 0))
6266 return num_insns_constant_wide (low);
6268 else if (rs6000_is_valid_and_mask (op, mode))
6272 return num_insns_constant_wide (high) + 1;
6275 return (num_insns_constant_wide (high)
6276 + num_insns_constant_wide (low) + 1);
6284 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
6285 If the mode of OP is MODE_VECTOR_INT, this simply returns the
6286 corresponding element of the vector, but for V4SFmode and V2SFmode,
6287 the corresponding "float" is interpreted as an SImode integer. */
6290 const_vector_elt_as_int (rtx op, unsigned int elt)
6294 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
6295 gcc_assert (GET_MODE (op) != V2DImode
6296 && GET_MODE (op) != V2DFmode);
6298 tmp = CONST_VECTOR_ELT (op, elt);
6299 if (GET_MODE (op) == V4SFmode
6300 || GET_MODE (op) == V2SFmode)
6301 tmp = gen_lowpart (SImode, tmp);
6302 return INTVAL (tmp);
6305 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
6306 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
6307 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
6308 all items are set to the same value and contain COPIES replicas of the
6309 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
6310 operand and the others are set to the value of the operand's msb. */
6313 vspltis_constant (rtx op, unsigned step, unsigned copies)
6315 machine_mode mode = GET_MODE (op);
6316 machine_mode inner = GET_MODE_INNER (mode);
6324 HOST_WIDE_INT splat_val;
6325 HOST_WIDE_INT msb_val;
6327 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
6330 nunits = GET_MODE_NUNITS (mode);
6331 bitsize = GET_MODE_BITSIZE (inner);
6332 mask = GET_MODE_MASK (inner);
6334 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6336 msb_val = val >= 0 ? 0 : -1;
6338 /* Construct the value to be splatted, if possible. If not, return 0. */
6339 for (i = 2; i <= copies; i *= 2)
6341 HOST_WIDE_INT small_val;
6343 small_val = splat_val >> bitsize;
6345 if (splat_val != ((HOST_WIDE_INT)
6346 ((unsigned HOST_WIDE_INT) small_val << bitsize)
6347 | (small_val & mask)))
6349 splat_val = small_val;
6352 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
6353 if (EASY_VECTOR_15 (splat_val))
6356 /* Also check if we can splat, and then add the result to itself. Do so if
6357 the value is positive, of if the splat instruction is using OP's mode;
6358 for splat_val < 0, the splat and the add should use the same mode. */
6359 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
6360 && (splat_val >= 0 || (step == 1 && copies == 1)))
6363 /* Also check if are loading up the most significant bit which can be done by
6364 loading up -1 and shifting the value left by -1. */
6365 else if (EASY_VECTOR_MSB (splat_val, inner))
6371 /* Check if VAL is present in every STEP-th element, and the
6372 other elements are filled with its most significant bit. */
6373 for (i = 1; i < nunits; ++i)
6375 HOST_WIDE_INT desired_val;
6376 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
6377 if ((i & (step - 1)) == 0)
6380 desired_val = msb_val;
6382 if (desired_val != const_vector_elt_as_int (op, elt))
6389 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6390 instruction, filling in the bottom elements with 0 or -1.
6392 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6393 for the number of zeroes to shift in, or negative for the number of 0xff
6396 OP is a CONST_VECTOR. */
6399 vspltis_shifted (rtx op)
6401 machine_mode mode = GET_MODE (op);
6402 machine_mode inner = GET_MODE_INNER (mode);
6410 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6413 /* We need to create pseudo registers to do the shift, so don't recognize
6414 shift vector constants after reload. */
6415 if (!can_create_pseudo_p ())
6418 nunits = GET_MODE_NUNITS (mode);
6419 mask = GET_MODE_MASK (inner);
6421 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6423 /* Check if the value can really be the operand of a vspltis[bhw]. */
6424 if (EASY_VECTOR_15 (val))
6427 /* Also check if we are loading up the most significant bit which can be done
6428 by loading up -1 and shifting the value left by -1. */
6429 else if (EASY_VECTOR_MSB (val, inner))
6435 /* Check if VAL is present in every STEP-th element until we find elements
6436 that are 0 or all 1 bits. */
6437 for (i = 1; i < nunits; ++i)
6439 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6440 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6442 /* If the value isn't the splat value, check for the remaining elements
6448 for (j = i+1; j < nunits; ++j)
6450 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6451 if (const_vector_elt_as_int (op, elt2) != 0)
6455 return (nunits - i) * GET_MODE_SIZE (inner);
6458 else if ((elt_val & mask) == mask)
6460 for (j = i+1; j < nunits; ++j)
6462 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6463 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6467 return -((nunits - i) * GET_MODE_SIZE (inner));
6475 /* If all elements are equal, we don't need to do VLSDOI. */
6480 /* Return true if OP is of the given MODE and can be synthesized
6481 with a vspltisb, vspltish or vspltisw. */
6484 easy_altivec_constant (rtx op, machine_mode mode)
6486 unsigned step, copies;
6488 if (mode == VOIDmode)
6489 mode = GET_MODE (op);
6490 else if (mode != GET_MODE (op))
6493 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6495 if (mode == V2DFmode)
6496 return zero_constant (op, mode);
6498 else if (mode == V2DImode)
6500 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
6501 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
6504 if (zero_constant (op, mode))
6507 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6508 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6514 /* V1TImode is a special container for TImode. Ignore for now. */
6515 else if (mode == V1TImode)
6518 /* Start with a vspltisw. */
6519 step = GET_MODE_NUNITS (mode) / 4;
6522 if (vspltis_constant (op, step, copies))
6525 /* Then try with a vspltish. */
6531 if (vspltis_constant (op, step, copies))
6534 /* And finally a vspltisb. */
6540 if (vspltis_constant (op, step, copies))
6543 if (vspltis_shifted (op) != 0)
6549 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6550 result is OP. Abort if it is not possible. */
6553 gen_easy_altivec_constant (rtx op)
6555 machine_mode mode = GET_MODE (op);
6556 int nunits = GET_MODE_NUNITS (mode);
6557 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6558 unsigned step = nunits / 4;
6559 unsigned copies = 1;
6561 /* Start with a vspltisw. */
6562 if (vspltis_constant (op, step, copies))
6563 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6565 /* Then try with a vspltish. */
6571 if (vspltis_constant (op, step, copies))
6572 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6574 /* And finally a vspltisb. */
6580 if (vspltis_constant (op, step, copies))
6581 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6586 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6587 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6589 Return the number of instructions needed (1 or 2) into the address pointed
6592 Return the constant that is being split via CONSTANT_PTR. */
6595 xxspltib_constant_p (rtx op,
6600 size_t nunits = GET_MODE_NUNITS (mode);
6602 HOST_WIDE_INT value;
6605 /* Set the returned values to out of bound values. */
6606 *num_insns_ptr = -1;
6607 *constant_ptr = 256;
6609 if (!TARGET_P9_VECTOR)
6612 if (mode == VOIDmode)
6613 mode = GET_MODE (op);
6615 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6618 /* Handle (vec_duplicate <constant>). */
6619 if (GET_CODE (op) == VEC_DUPLICATE)
6621 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6622 && mode != V2DImode)
6625 element = XEXP (op, 0);
6626 if (!CONST_INT_P (element))
6629 value = INTVAL (element);
6630 if (!IN_RANGE (value, -128, 127))
6634 /* Handle (const_vector [...]). */
6635 else if (GET_CODE (op) == CONST_VECTOR)
6637 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6638 && mode != V2DImode)
6641 element = CONST_VECTOR_ELT (op, 0);
6642 if (!CONST_INT_P (element))
6645 value = INTVAL (element);
6646 if (!IN_RANGE (value, -128, 127))
6649 for (i = 1; i < nunits; i++)
6651 element = CONST_VECTOR_ELT (op, i);
6652 if (!CONST_INT_P (element))
6655 if (value != INTVAL (element))
6660 /* Handle integer constants being loaded into the upper part of the VSX
6661 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6662 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6663 else if (CONST_INT_P (op))
6665 if (!SCALAR_INT_MODE_P (mode))
6668 value = INTVAL (op);
6669 if (!IN_RANGE (value, -128, 127))
6672 if (!IN_RANGE (value, -1, 0))
6674 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6677 if (EASY_VECTOR_15 (value))
6685 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6686 sign extend. Special case 0/-1 to allow getting any VSX register instead
6687 of an Altivec register. */
6688 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6689 && EASY_VECTOR_15 (value))
6692 /* Return # of instructions and the constant byte for XXSPLTIB. */
6693 if (mode == V16QImode)
6696 else if (IN_RANGE (value, -1, 0))
6702 *constant_ptr = (int) value;
6707 output_vec_const_move (rtx *operands)
6715 mode = GET_MODE (dest);
6719 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6720 int xxspltib_value = 256;
6723 if (zero_constant (vec, mode))
6725 if (TARGET_P9_VECTOR)
6726 return "xxspltib %x0,0";
6728 else if (dest_vmx_p)
6729 return "vspltisw %0,0";
6732 return "xxlxor %x0,%x0,%x0";
6735 if (all_ones_constant (vec, mode))
6737 if (TARGET_P9_VECTOR)
6738 return "xxspltib %x0,255";
6740 else if (dest_vmx_p)
6741 return "vspltisw %0,-1";
6743 else if (TARGET_P8_VECTOR)
6744 return "xxlorc %x0,%x0,%x0";
6750 if (TARGET_P9_VECTOR
6751 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6755 operands[2] = GEN_INT (xxspltib_value & 0xff);
6756 return "xxspltib %x0,%2";
6767 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6768 if (zero_constant (vec, mode))
6769 return "vspltisw %0,0";
6771 if (all_ones_constant (vec, mode))
6772 return "vspltisw %0,-1";
6774 /* Do we need to construct a value using VSLDOI? */
6775 shift = vspltis_shifted (vec);
6779 splat_vec = gen_easy_altivec_constant (vec);
6780 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6781 operands[1] = XEXP (splat_vec, 0);
6782 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6785 switch (GET_MODE (splat_vec))
6788 return "vspltisw %0,%1";
6791 return "vspltish %0,%1";
6794 return "vspltisb %0,%1";
6804 /* Initialize TARGET of vector PAIRED to VALS. */
6807 paired_expand_vector_init (rtx target, rtx vals)
6809 machine_mode mode = GET_MODE (target);
6810 int n_elts = GET_MODE_NUNITS (mode);
6812 rtx x, new_rtx, tmp, constant_op, op1, op2;
6815 for (i = 0; i < n_elts; ++i)
6817 x = XVECEXP (vals, 0, i);
6818 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6823 /* Load from constant pool. */
6824 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
6830 /* The vector is initialized only with non-constants. */
6831 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
6832 XVECEXP (vals, 0, 1));
6834 emit_move_insn (target, new_rtx);
6838 /* One field is non-constant and the other one is a constant. Load the
6839 constant from the constant pool and use ps_merge instruction to
6840 construct the whole vector. */
6841 op1 = XVECEXP (vals, 0, 0);
6842 op2 = XVECEXP (vals, 0, 1);
6844 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
6846 tmp = gen_reg_rtx (GET_MODE (constant_op));
6847 emit_move_insn (tmp, constant_op);
6849 if (CONSTANT_P (op1))
6850 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
6852 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
6854 emit_move_insn (target, new_rtx);
6858 paired_expand_vector_move (rtx operands[])
6860 rtx op0 = operands[0], op1 = operands[1];
6862 emit_move_insn (op0, op1);
6865 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
6866 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
6867 operands for the relation operation COND. This is a recursive
6871 paired_emit_vector_compare (enum rtx_code rcode,
6872 rtx dest, rtx op0, rtx op1,
6873 rtx cc_op0, rtx cc_op1)
6875 rtx tmp = gen_reg_rtx (V2SFmode);
6878 gcc_assert (TARGET_PAIRED_FLOAT);
6879 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
6885 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
6889 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
6890 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
6894 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
6897 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
6900 tmp1 = gen_reg_rtx (V2SFmode);
6901 max = gen_reg_rtx (V2SFmode);
6902 min = gen_reg_rtx (V2SFmode);
6903 gen_reg_rtx (V2SFmode);
6905 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
6906 emit_insn (gen_selv2sf4
6907 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
6908 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
6909 emit_insn (gen_selv2sf4
6910 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
6911 emit_insn (gen_subv2sf3 (tmp1, min, max));
6912 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
6915 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
6918 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
6921 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
6924 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
6927 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
6936 /* Emit vector conditional expression.
6937 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
6938 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
6941 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
6942 rtx cond, rtx cc_op0, rtx cc_op1)
6944 enum rtx_code rcode = GET_CODE (cond);
6946 if (!TARGET_PAIRED_FLOAT)
6949 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
6954 /* Initialize vector TARGET to VALS. */
6957 rs6000_expand_vector_init (rtx target, rtx vals)
6959 machine_mode mode = GET_MODE (target);
6960 machine_mode inner_mode = GET_MODE_INNER (mode);
6961 int n_elts = GET_MODE_NUNITS (mode);
6962 int n_var = 0, one_var = -1;
6963 bool all_same = true, all_const_zero = true;
6967 for (i = 0; i < n_elts; ++i)
6969 x = XVECEXP (vals, 0, i);
6970 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6971 ++n_var, one_var = i;
6972 else if (x != CONST0_RTX (inner_mode))
6973 all_const_zero = false;
6975 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6981 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6982 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6983 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6985 /* Zero register. */
6986 emit_move_insn (target, CONST0_RTX (mode));
6989 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6991 /* Splat immediate. */
6992 emit_insn (gen_rtx_SET (target, const_vec));
6997 /* Load from constant pool. */
6998 emit_move_insn (target, const_vec);
7003 /* Double word values on VSX can use xxpermdi or lxvdsx. */
7004 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
7008 size_t num_elements = all_same ? 1 : 2;
7009 for (i = 0; i < num_elements; i++)
7011 op[i] = XVECEXP (vals, 0, i);
7012 /* Just in case there is a SUBREG with a smaller mode, do a
7014 if (GET_MODE (op[i]) != inner_mode)
7016 rtx tmp = gen_reg_rtx (inner_mode);
7017 convert_move (tmp, op[i], 0);
7020 /* Allow load with splat double word. */
7021 else if (MEM_P (op[i]))
7024 op[i] = force_reg (inner_mode, op[i]);
7026 else if (!REG_P (op[i]))
7027 op[i] = force_reg (inner_mode, op[i]);
7032 if (mode == V2DFmode)
7033 emit_insn (gen_vsx_splat_v2df (target, op[0]));
7035 emit_insn (gen_vsx_splat_v2di (target, op[0]));
7039 if (mode == V2DFmode)
7040 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
7042 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
7047 /* Special case initializing vector int if we are on 64-bit systems with
7048 direct move or we have the ISA 3.0 instructions. */
7049 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
7050 && TARGET_DIRECT_MOVE_64BIT)
7054 rtx element0 = XVECEXP (vals, 0, 0);
7055 if (MEM_P (element0))
7056 element0 = rs6000_address_for_fpconvert (element0);
7058 element0 = force_reg (SImode, element0);
7060 if (TARGET_P9_VECTOR)
7061 emit_insn (gen_vsx_splat_v4si (target, element0));
7064 rtx tmp = gen_reg_rtx (DImode);
7065 emit_insn (gen_zero_extendsidi2 (tmp, element0));
7066 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
7075 for (i = 0; i < 4; i++)
7077 elements[i] = XVECEXP (vals, 0, i);
7078 if (!CONST_INT_P (elements[i]) && !REG_P (elements[i]))
7079 elements[i] = copy_to_mode_reg (SImode, elements[i]);
7082 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
7083 elements[2], elements[3]));
7088 /* With single precision floating point on VSX, know that internally single
7089 precision is actually represented as a double, and either make 2 V2DF
7090 vectors, and convert these vectors to single precision, or do one
7091 conversion, and splat the result to the other elements. */
7092 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
7096 rtx element0 = XVECEXP (vals, 0, 0);
7098 if (TARGET_P9_VECTOR)
7100 if (MEM_P (element0))
7101 element0 = rs6000_address_for_fpconvert (element0);
7103 emit_insn (gen_vsx_splat_v4sf (target, element0));
7108 rtx freg = gen_reg_rtx (V4SFmode);
7109 rtx sreg = force_reg (SFmode, element0);
7110 rtx cvt = (TARGET_XSCVDPSPN
7111 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
7112 : gen_vsx_xscvdpsp_scalar (freg, sreg));
7115 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
7121 rtx dbl_even = gen_reg_rtx (V2DFmode);
7122 rtx dbl_odd = gen_reg_rtx (V2DFmode);
7123 rtx flt_even = gen_reg_rtx (V4SFmode);
7124 rtx flt_odd = gen_reg_rtx (V4SFmode);
7125 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
7126 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
7127 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
7128 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
7130 /* Use VMRGEW if we can instead of doing a permute. */
7131 if (TARGET_P8_VECTOR)
7133 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
7134 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
7135 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
7136 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
7137 if (BYTES_BIG_ENDIAN)
7138 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
7140 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
7144 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
7145 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
7146 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
7147 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
7148 rs6000_expand_extract_even (target, flt_even, flt_odd);
7154 /* Special case initializing vector short/char that are splats if we are on
7155 64-bit systems with direct move. */
7156 if (all_same && TARGET_DIRECT_MOVE_64BIT
7157 && (mode == V16QImode || mode == V8HImode))
7159 rtx op0 = XVECEXP (vals, 0, 0);
7160 rtx di_tmp = gen_reg_rtx (DImode);
7163 op0 = force_reg (GET_MODE_INNER (mode), op0);
7165 if (mode == V16QImode)
7167 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
7168 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
7172 if (mode == V8HImode)
7174 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
7175 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
7180 /* Store value to stack temp. Load vector element. Splat. However, splat
7181 of 64-bit items is not supported on Altivec. */
7182 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
7184 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
7185 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
7186 XVECEXP (vals, 0, 0));
7187 x = gen_rtx_UNSPEC (VOIDmode,
7188 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
7189 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7191 gen_rtx_SET (target, mem),
7193 x = gen_rtx_VEC_SELECT (inner_mode, target,
7194 gen_rtx_PARALLEL (VOIDmode,
7195 gen_rtvec (1, const0_rtx)));
7196 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
7200 /* One field is non-constant. Load constant then overwrite
7204 rtx copy = copy_rtx (vals);
7206 /* Load constant part of vector, substitute neighboring value for
7208 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
7209 rs6000_expand_vector_init (target, copy);
7211 /* Insert variable. */
7212 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
7216 /* Construct the vector in memory one field at a time
7217 and load the whole vector. */
7218 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7219 for (i = 0; i < n_elts; i++)
7220 emit_move_insn (adjust_address_nv (mem, inner_mode,
7221 i * GET_MODE_SIZE (inner_mode)),
7222 XVECEXP (vals, 0, i));
7223 emit_move_insn (target, mem);
7226 /* Set field ELT of TARGET to VAL. */
7229 rs6000_expand_vector_set (rtx target, rtx val, int elt)
7231 machine_mode mode = GET_MODE (target);
7232 machine_mode inner_mode = GET_MODE_INNER (mode);
7233 rtx reg = gen_reg_rtx (mode);
7235 int width = GET_MODE_SIZE (inner_mode);
7238 val = force_reg (GET_MODE (val), val);
7240 if (VECTOR_MEM_VSX_P (mode))
7242 rtx insn = NULL_RTX;
7243 rtx elt_rtx = GEN_INT (elt);
7245 if (mode == V2DFmode)
7246 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
7248 else if (mode == V2DImode)
7249 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
7251 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
7253 if (mode == V4SImode)
7254 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
7255 else if (mode == V8HImode)
7256 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
7257 else if (mode == V16QImode)
7258 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
7259 else if (mode == V4SFmode)
7260 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
7270 /* Simplify setting single element vectors like V1TImode. */
7271 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
7273 emit_move_insn (target, gen_lowpart (mode, val));
7277 /* Load single variable value. */
7278 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
7279 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
7280 x = gen_rtx_UNSPEC (VOIDmode,
7281 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
7282 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7284 gen_rtx_SET (reg, mem),
7287 /* Linear sequence. */
7288 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
7289 for (i = 0; i < 16; ++i)
7290 XVECEXP (mask, 0, i) = GEN_INT (i);
7292 /* Set permute mask to insert element into target. */
7293 for (i = 0; i < width; ++i)
7294 XVECEXP (mask, 0, elt*width + i)
7295 = GEN_INT (i + 0x10);
7296 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
7298 if (BYTES_BIG_ENDIAN)
7299 x = gen_rtx_UNSPEC (mode,
7300 gen_rtvec (3, target, reg,
7301 force_reg (V16QImode, x)),
7305 if (TARGET_P9_VECTOR)
7306 x = gen_rtx_UNSPEC (mode,
7307 gen_rtvec (3, reg, target,
7308 force_reg (V16QImode, x)),
7312 /* Invert selector. We prefer to generate VNAND on P8 so
7313 that future fusion opportunities can kick in, but must
7314 generate VNOR elsewhere. */
7315 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
7316 rtx iorx = (TARGET_P8_VECTOR
7317 ? gen_rtx_IOR (V16QImode, notx, notx)
7318 : gen_rtx_AND (V16QImode, notx, notx));
7319 rtx tmp = gen_reg_rtx (V16QImode);
7320 emit_insn (gen_rtx_SET (tmp, iorx));
7322 /* Permute with operands reversed and adjusted selector. */
7323 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
7328 emit_insn (gen_rtx_SET (target, x));
7331 /* Extract field ELT from VEC into TARGET. */
7334 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
7336 machine_mode mode = GET_MODE (vec);
7337 machine_mode inner_mode = GET_MODE_INNER (mode);
7340 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
7347 gcc_assert (INTVAL (elt) == 0 && inner_mode == TImode);
7348 emit_move_insn (target, gen_lowpart (TImode, vec));
7351 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
7354 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
7357 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
7360 if (TARGET_DIRECT_MOVE_64BIT)
7362 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
7368 if (TARGET_DIRECT_MOVE_64BIT)
7370 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
7376 if (TARGET_DIRECT_MOVE_64BIT)
7378 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
7384 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
7385 && TARGET_DIRECT_MOVE_64BIT)
7387 if (GET_MODE (elt) != DImode)
7389 rtx tmp = gen_reg_rtx (DImode);
7390 convert_move (tmp, elt, 0);
7393 else if (!REG_P (elt))
7394 elt = force_reg (DImode, elt);
7399 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
7403 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
7407 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
7411 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
7415 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
7419 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
7427 gcc_assert (CONST_INT_P (elt));
7429 /* Allocate mode-sized buffer. */
7430 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7432 emit_move_insn (mem, vec);
7434 /* Add offset to field within buffer matching vector element. */
7435 mem = adjust_address_nv (mem, inner_mode,
7436 INTVAL (elt) * GET_MODE_SIZE (inner_mode));
7438 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
7441 /* Helper function to return the register number of a RTX. */
7443 regno_or_subregno (rtx op)
7447 else if (SUBREG_P (op))
7448 return subreg_regno (op);
7453 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
7454 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
7455 temporary (BASE_TMP) to fixup the address. Return the new memory address
7456 that is valid for reads or writes to a given register (SCALAR_REG). */
7459 rs6000_adjust_vec_address (rtx scalar_reg,
7463 machine_mode scalar_mode)
7465 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7466 rtx addr = XEXP (mem, 0);
7471 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
7472 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
7474 /* Calculate what we need to add to the address to get the element
7476 if (CONST_INT_P (element))
7477 element_offset = GEN_INT (INTVAL (element) * scalar_size);
7480 int byte_shift = exact_log2 (scalar_size);
7481 gcc_assert (byte_shift >= 0);
7483 if (byte_shift == 0)
7484 element_offset = element;
7488 if (TARGET_POWERPC64)
7489 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
7491 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
7493 element_offset = base_tmp;
7497 /* Create the new address pointing to the element within the vector. If we
7498 are adding 0, we don't have to change the address. */
7499 if (element_offset == const0_rtx)
7502 /* A simple indirect address can be converted into a reg + offset
7504 else if (REG_P (addr) || SUBREG_P (addr))
7505 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
7507 /* Optimize D-FORM addresses with constant offset with a constant element, to
7508 include the element offset in the address directly. */
7509 else if (GET_CODE (addr) == PLUS)
7511 rtx op0 = XEXP (addr, 0);
7512 rtx op1 = XEXP (addr, 1);
7515 gcc_assert (REG_P (op0) || SUBREG_P (op0));
7516 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
7518 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
7519 rtx offset_rtx = GEN_INT (offset);
7521 if (IN_RANGE (offset, -32768, 32767)
7522 && (scalar_size < 8 || (offset & 0x3) == 0))
7523 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
7526 emit_move_insn (base_tmp, offset_rtx);
7527 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7532 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7533 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7535 /* Note, ADDI requires the register being added to be a base
7536 register. If the register was R0, load it up into the temporary
7539 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7541 insn = gen_add3_insn (base_tmp, op1, element_offset);
7542 gcc_assert (insn != NULL_RTX);
7547 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7549 insn = gen_add3_insn (base_tmp, element_offset, op1);
7550 gcc_assert (insn != NULL_RTX);
7556 emit_move_insn (base_tmp, op1);
7557 emit_insn (gen_add2_insn (base_tmp, element_offset));
7560 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7566 emit_move_insn (base_tmp, addr);
7567 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7570 /* If we have a PLUS, we need to see whether the particular register class
7571 allows for D-FORM or X-FORM addressing. */
7572 if (GET_CODE (new_addr) == PLUS)
7574 rtx op1 = XEXP (new_addr, 1);
7575 addr_mask_type addr_mask;
7576 int scalar_regno = regno_or_subregno (scalar_reg);
7578 gcc_assert (scalar_regno < FIRST_PSEUDO_REGISTER);
7579 if (INT_REGNO_P (scalar_regno))
7580 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7582 else if (FP_REGNO_P (scalar_regno))
7583 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7585 else if (ALTIVEC_REGNO_P (scalar_regno))
7586 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7591 if (REG_P (op1) || SUBREG_P (op1))
7592 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7594 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7597 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7598 valid_addr_p = true;
7601 valid_addr_p = false;
7605 emit_move_insn (base_tmp, new_addr);
7606 new_addr = base_tmp;
7609 return change_address (mem, scalar_mode, new_addr);
7612 /* Split a variable vec_extract operation into the component instructions. */
7615 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7618 machine_mode mode = GET_MODE (src);
7619 machine_mode scalar_mode = GET_MODE (dest);
7620 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7621 int byte_shift = exact_log2 (scalar_size);
7623 gcc_assert (byte_shift >= 0);
7625 /* If we are given a memory address, optimize to load just the element. We
7626 don't have to adjust the vector element number on little endian
7630 gcc_assert (REG_P (tmp_gpr));
7631 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7632 tmp_gpr, scalar_mode));
7636 else if (REG_P (src) || SUBREG_P (src))
7638 int bit_shift = byte_shift + 3;
7640 int dest_regno = regno_or_subregno (dest);
7641 int src_regno = regno_or_subregno (src);
7642 int element_regno = regno_or_subregno (element);
7644 gcc_assert (REG_P (tmp_gpr));
7646 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7647 a general purpose register. */
7648 if (TARGET_P9_VECTOR
7649 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7650 && INT_REGNO_P (dest_regno)
7651 && ALTIVEC_REGNO_P (src_regno)
7652 && INT_REGNO_P (element_regno))
7654 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7655 rtx element_si = gen_rtx_REG (SImode, element_regno);
7657 if (mode == V16QImode)
7658 emit_insn (VECTOR_ELT_ORDER_BIG
7659 ? gen_vextublx (dest_si, element_si, src)
7660 : gen_vextubrx (dest_si, element_si, src));
7662 else if (mode == V8HImode)
7664 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7665 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7666 emit_insn (VECTOR_ELT_ORDER_BIG
7667 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7668 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7674 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7675 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7676 emit_insn (VECTOR_ELT_ORDER_BIG
7677 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7678 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7685 gcc_assert (REG_P (tmp_altivec));
7687 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7688 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7689 will shift the element into the upper position (adding 3 to convert a
7690 byte shift into a bit shift). */
7691 if (scalar_size == 8)
7693 if (!VECTOR_ELT_ORDER_BIG)
7695 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7701 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7703 emit_insn (gen_rtx_SET (tmp_gpr,
7704 gen_rtx_AND (DImode,
7705 gen_rtx_ASHIFT (DImode,
7712 if (!VECTOR_ELT_ORDER_BIG)
7714 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
7716 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7717 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7723 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7726 /* Get the value into the lower byte of the Altivec register where VSLO
7728 if (TARGET_P9_VECTOR)
7729 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7730 else if (can_create_pseudo_p ())
7731 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7734 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7735 emit_move_insn (tmp_di, tmp_gpr);
7736 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7739 /* Do the VSLO to get the value into the final location. */
7743 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7747 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7752 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7753 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7754 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7755 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7758 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7766 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7767 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7768 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7769 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7771 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7772 emit_insn (gen_ashrdi3 (tmp_gpr_di, tmp_gpr_di,
7773 GEN_INT (64 - (8 * scalar_size))));
7787 /* Helper function for rs6000_split_v4si_init to build up a DImode value from
7788 two SImode values. */
7791 rs6000_split_v4si_init_di_reg (rtx dest, rtx si1, rtx si2, rtx tmp)
7793 const unsigned HOST_WIDE_INT mask_32bit = HOST_WIDE_INT_C (0xffffffff);
7795 if (CONST_INT_P (si1) && CONST_INT_P (si2))
7797 unsigned HOST_WIDE_INT const1 = (UINTVAL (si1) & mask_32bit) << 32;
7798 unsigned HOST_WIDE_INT const2 = UINTVAL (si2) & mask_32bit;
7800 emit_move_insn (dest, GEN_INT (const1 | const2));
7804 /* Put si1 into upper 32-bits of dest. */
7805 if (CONST_INT_P (si1))
7806 emit_move_insn (dest, GEN_INT ((UINTVAL (si1) & mask_32bit) << 32));
7809 /* Generate RLDIC. */
7810 rtx si1_di = gen_rtx_REG (DImode, regno_or_subregno (si1));
7811 rtx shift_rtx = gen_rtx_ASHIFT (DImode, si1_di, GEN_INT (32));
7812 rtx mask_rtx = GEN_INT (mask_32bit << 32);
7813 rtx and_rtx = gen_rtx_AND (DImode, shift_rtx, mask_rtx);
7814 gcc_assert (!reg_overlap_mentioned_p (dest, si1));
7815 emit_insn (gen_rtx_SET (dest, and_rtx));
7818 /* Put si2 into the temporary. */
7819 gcc_assert (!reg_overlap_mentioned_p (dest, tmp));
7820 if (CONST_INT_P (si2))
7821 emit_move_insn (tmp, GEN_INT (UINTVAL (si2) & mask_32bit));
7823 emit_insn (gen_zero_extendsidi2 (tmp, si2));
7825 /* Combine the two parts. */
7826 emit_insn (gen_iordi3 (dest, dest, tmp));
7830 /* Split a V4SI initialization. */
7833 rs6000_split_v4si_init (rtx operands[])
7835 rtx dest = operands[0];
7837 /* Destination is a GPR, build up the two DImode parts in place. */
7838 if (REG_P (dest) || SUBREG_P (dest))
7840 int d_regno = regno_or_subregno (dest);
7841 rtx scalar1 = operands[1];
7842 rtx scalar2 = operands[2];
7843 rtx scalar3 = operands[3];
7844 rtx scalar4 = operands[4];
7845 rtx tmp1 = operands[5];
7846 rtx tmp2 = operands[6];
7848 /* Even though we only need one temporary (plus the destination, which
7849 has an early clobber constraint, try to use two temporaries, one for
7850 each double word created. That way the 2nd insn scheduling pass can
7851 rearrange things so the two parts are done in parallel. */
7852 if (BYTES_BIG_ENDIAN)
7854 rtx di_lo = gen_rtx_REG (DImode, d_regno);
7855 rtx di_hi = gen_rtx_REG (DImode, d_regno + 1);
7856 rs6000_split_v4si_init_di_reg (di_lo, scalar1, scalar2, tmp1);
7857 rs6000_split_v4si_init_di_reg (di_hi, scalar3, scalar4, tmp2);
7861 rtx di_lo = gen_rtx_REG (DImode, d_regno + 1);
7862 rtx di_hi = gen_rtx_REG (DImode, d_regno);
7863 gcc_assert (!VECTOR_ELT_ORDER_BIG);
7864 rs6000_split_v4si_init_di_reg (di_lo, scalar4, scalar3, tmp1);
7865 rs6000_split_v4si_init_di_reg (di_hi, scalar2, scalar1, tmp2);
7874 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7875 selects whether the alignment is abi mandated, optional, or
7876 both abi and optional alignment. */
7879 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7881 if (how != align_opt)
7883 if (TREE_CODE (type) == VECTOR_TYPE)
7885 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type)))
7890 else if (align < 128)
7895 if (how != align_abi)
7897 if (TREE_CODE (type) == ARRAY_TYPE
7898 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7900 if (align < BITS_PER_WORD)
7901 align = BITS_PER_WORD;
7908 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7909 instructions simply ignore the low bits; VSX memory instructions
7910 are aligned to 4 or 8 bytes. */
7913 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7915 return (STRICT_ALIGNMENT
7916 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7917 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7918 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7919 && (int) align < VECTOR_ALIGN (mode)))));
7922 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7925 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7927 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7929 if (computed != 128)
7932 if (!warned && warn_psabi)
7935 inform (input_location,
7936 "the layout of aggregates containing vectors with"
7937 " %d-byte alignment has changed in GCC 5",
7938 computed / BITS_PER_UNIT);
7941 /* In current GCC there is no special case. */
7948 /* AIX increases natural record alignment to doubleword if the first
7949 field is an FP double while the FP fields remain word aligned. */
7952 rs6000_special_round_type_align (tree type, unsigned int computed,
7953 unsigned int specified)
7955 unsigned int align = MAX (computed, specified);
7956 tree field = TYPE_FIELDS (type);
7958 /* Skip all non field decls */
7959 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7960 field = DECL_CHAIN (field);
7962 if (field != NULL && field != type)
7964 type = TREE_TYPE (field);
7965 while (TREE_CODE (type) == ARRAY_TYPE)
7966 type = TREE_TYPE (type);
7968 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7969 align = MAX (align, 64);
7975 /* Darwin increases record alignment to the natural alignment of
7979 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7980 unsigned int specified)
7982 unsigned int align = MAX (computed, specified);
7984 if (TYPE_PACKED (type))
7987 /* Find the first field, looking down into aggregates. */
7989 tree field = TYPE_FIELDS (type);
7990 /* Skip all non field decls */
7991 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7992 field = DECL_CHAIN (field);
7995 /* A packed field does not contribute any extra alignment. */
7996 if (DECL_PACKED (field))
7998 type = TREE_TYPE (field);
7999 while (TREE_CODE (type) == ARRAY_TYPE)
8000 type = TREE_TYPE (type);
8001 } while (AGGREGATE_TYPE_P (type));
8003 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
8004 align = MAX (align, TYPE_ALIGN (type));
8009 /* Return 1 for an operand in small memory on V.4/eabi. */
8012 small_data_operand (rtx op ATTRIBUTE_UNUSED,
8013 machine_mode mode ATTRIBUTE_UNUSED)
8018 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
8021 if (DEFAULT_ABI != ABI_V4)
8024 if (GET_CODE (op) == SYMBOL_REF)
8027 else if (GET_CODE (op) != CONST
8028 || GET_CODE (XEXP (op, 0)) != PLUS
8029 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
8030 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
8035 rtx sum = XEXP (op, 0);
8036 HOST_WIDE_INT summand;
8038 /* We have to be careful here, because it is the referenced address
8039 that must be 32k from _SDA_BASE_, not just the symbol. */
8040 summand = INTVAL (XEXP (sum, 1));
8041 if (summand < 0 || summand > g_switch_value)
8044 sym_ref = XEXP (sum, 0);
8047 return SYMBOL_REF_SMALL_P (sym_ref);
8053 /* Return true if either operand is a general purpose register. */
8056 gpr_or_gpr_p (rtx op0, rtx op1)
8058 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
8059 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
8062 /* Return true if this is a move direct operation between GPR registers and
8063 floating point/VSX registers. */
8066 direct_move_p (rtx op0, rtx op1)
8070 if (!REG_P (op0) || !REG_P (op1))
8073 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
8076 regno0 = REGNO (op0);
8077 regno1 = REGNO (op1);
8078 if (regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER)
8081 if (INT_REGNO_P (regno0))
8082 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
8084 else if (INT_REGNO_P (regno1))
8086 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
8089 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
8096 /* Return true if the OFFSET is valid for the quad address instructions that
8097 use d-form (register + offset) addressing. */
8100 quad_address_offset_p (HOST_WIDE_INT offset)
8102 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
8105 /* Return true if the ADDR is an acceptable address for a quad memory
8106 operation of mode MODE (either LQ/STQ for general purpose registers, or
8107 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
8108 is intended for LQ/STQ. If it is false, the address is intended for the ISA
8109 3.0 LXV/STXV instruction. */
8112 quad_address_p (rtx addr, machine_mode mode, bool strict)
8116 if (GET_MODE_SIZE (mode) != 16)
8119 if (legitimate_indirect_address_p (addr, strict))
8122 if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode))
8125 if (GET_CODE (addr) != PLUS)
8128 op0 = XEXP (addr, 0);
8129 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
8132 op1 = XEXP (addr, 1);
8133 if (!CONST_INT_P (op1))
8136 return quad_address_offset_p (INTVAL (op1));
8139 /* Return true if this is a load or store quad operation. This function does
8140 not handle the atomic quad memory instructions. */
8143 quad_load_store_p (rtx op0, rtx op1)
8147 if (!TARGET_QUAD_MEMORY)
8150 else if (REG_P (op0) && MEM_P (op1))
8151 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
8152 && quad_memory_operand (op1, GET_MODE (op1))
8153 && !reg_overlap_mentioned_p (op0, op1));
8155 else if (MEM_P (op0) && REG_P (op1))
8156 ret = (quad_memory_operand (op0, GET_MODE (op0))
8157 && quad_int_reg_operand (op1, GET_MODE (op1)));
8162 if (TARGET_DEBUG_ADDR)
8164 fprintf (stderr, "\n========== quad_load_store, return %s\n",
8165 ret ? "true" : "false");
8166 debug_rtx (gen_rtx_SET (op0, op1));
8172 /* Given an address, return a constant offset term if one exists. */
8175 address_offset (rtx op)
8177 if (GET_CODE (op) == PRE_INC
8178 || GET_CODE (op) == PRE_DEC)
8180 else if (GET_CODE (op) == PRE_MODIFY
8181 || GET_CODE (op) == LO_SUM)
8184 if (GET_CODE (op) == CONST)
8187 if (GET_CODE (op) == PLUS)
8190 if (CONST_INT_P (op))
8196 /* Return true if the MEM operand is a memory operand suitable for use
8197 with a (full width, possibly multiple) gpr load/store. On
8198 powerpc64 this means the offset must be divisible by 4.
8199 Implements 'Y' constraint.
8201 Accept direct, indexed, offset, lo_sum and tocref. Since this is
8202 a constraint function we know the operand has satisfied a suitable
8203 memory predicate. Also accept some odd rtl generated by reload
8204 (see rs6000_legitimize_reload_address for various forms). It is
8205 important that reload rtl be accepted by appropriate constraints
8206 but not by the operand predicate.
8208 Offsetting a lo_sum should not be allowed, except where we know by
8209 alignment that a 32k boundary is not crossed, but see the ???
8210 comment in rs6000_legitimize_reload_address. Note that by
8211 "offsetting" here we mean a further offset to access parts of the
8212 MEM. It's fine to have a lo_sum where the inner address is offset
8213 from a sym, since the same sym+offset will appear in the high part
8214 of the address calculation. */
8217 mem_operand_gpr (rtx op, machine_mode mode)
8219 unsigned HOST_WIDE_INT offset;
8221 rtx addr = XEXP (op, 0);
8223 op = address_offset (addr);
8227 offset = INTVAL (op);
8228 if (TARGET_POWERPC64 && (offset & 3) != 0)
8231 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8235 if (GET_CODE (addr) == LO_SUM)
8236 /* For lo_sum addresses, we must allow any offset except one that
8237 causes a wrap, so test only the low 16 bits. */
8238 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8240 return offset + 0x8000 < 0x10000u - extra;
8243 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
8244 enforce an offset divisible by 4 even for 32-bit. */
8247 mem_operand_ds_form (rtx op, machine_mode mode)
8249 unsigned HOST_WIDE_INT offset;
8251 rtx addr = XEXP (op, 0);
8253 if (!offsettable_address_p (false, mode, addr))
8256 op = address_offset (addr);
8260 offset = INTVAL (op);
8261 if ((offset & 3) != 0)
8264 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8268 if (GET_CODE (addr) == LO_SUM)
8269 /* For lo_sum addresses, we must allow any offset except one that
8270 causes a wrap, so test only the low 16 bits. */
8271 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8273 return offset + 0x8000 < 0x10000u - extra;
8276 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
8279 reg_offset_addressing_ok_p (machine_mode mode)
8293 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
8294 ISA 3.0 vector d-form addressing mode was added. While TImode is not
8295 a vector mode, if we want to use the VSX registers to move it around,
8296 we need to restrict ourselves to reg+reg addressing. Similarly for
8297 IEEE 128-bit floating point that is passed in a single vector
8299 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
8300 return mode_supports_vsx_dform_quad (mode);
8305 /* Paired vector modes. Only reg+reg addressing is valid. */
8306 if (TARGET_PAIRED_FLOAT)
8311 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
8312 addressing for the LFIWZX and STFIWX instructions. */
8313 if (TARGET_NO_SDMODE_STACK)
8325 virtual_stack_registers_memory_p (rtx op)
8329 if (GET_CODE (op) == REG)
8330 regnum = REGNO (op);
8332 else if (GET_CODE (op) == PLUS
8333 && GET_CODE (XEXP (op, 0)) == REG
8334 && GET_CODE (XEXP (op, 1)) == CONST_INT)
8335 regnum = REGNO (XEXP (op, 0));
8340 return (regnum >= FIRST_VIRTUAL_REGISTER
8341 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
8344 /* Return true if a MODE sized memory accesses to OP plus OFFSET
8345 is known to not straddle a 32k boundary. This function is used
8346 to determine whether -mcmodel=medium code can use TOC pointer
8347 relative addressing for OP. This means the alignment of the TOC
8348 pointer must also be taken into account, and unfortunately that is
8351 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
8352 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
8356 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
8360 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
8362 if (GET_CODE (op) != SYMBOL_REF)
8365 /* ISA 3.0 vector d-form addressing is restricted, don't allow
8367 if (mode_supports_vsx_dform_quad (mode))
8370 dsize = GET_MODE_SIZE (mode);
8371 decl = SYMBOL_REF_DECL (op);
8377 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
8378 replacing memory addresses with an anchor plus offset. We
8379 could find the decl by rummaging around in the block->objects
8380 VEC for the given offset but that seems like too much work. */
8381 dalign = BITS_PER_UNIT;
8382 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
8383 && SYMBOL_REF_ANCHOR_P (op)
8384 && SYMBOL_REF_BLOCK (op) != NULL)
8386 struct object_block *block = SYMBOL_REF_BLOCK (op);
8388 dalign = block->alignment;
8389 offset += SYMBOL_REF_BLOCK_OFFSET (op);
8391 else if (CONSTANT_POOL_ADDRESS_P (op))
8393 /* It would be nice to have get_pool_align().. */
8394 machine_mode cmode = get_pool_mode (op);
8396 dalign = GET_MODE_ALIGNMENT (cmode);
8399 else if (DECL_P (decl))
8401 dalign = DECL_ALIGN (decl);
8405 /* Allow BLKmode when the entire object is known to not
8406 cross a 32k boundary. */
8407 if (!DECL_SIZE_UNIT (decl))
8410 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
8413 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
8417 dalign /= BITS_PER_UNIT;
8418 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8419 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8420 return dalign >= dsize;
8426 /* Find how many bits of the alignment we know for this access. */
8427 dalign /= BITS_PER_UNIT;
8428 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8429 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8431 lsb = offset & -offset;
8435 return dalign >= dsize;
8439 constant_pool_expr_p (rtx op)
8443 split_const (op, &base, &offset);
8444 return (GET_CODE (base) == SYMBOL_REF
8445 && CONSTANT_POOL_ADDRESS_P (base)
8446 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
8449 /* These are only used to pass through from print_operand/print_operand_address
8450 to rs6000_output_addr_const_extra over the intervening function
8451 output_addr_const which is not target code. */
8452 static const_rtx tocrel_base_oac, tocrel_offset_oac;
8454 /* Return true if OP is a toc pointer relative address (the output
8455 of create_TOC_reference). If STRICT, do not match non-split
8456 -mcmodel=large/medium toc pointer relative addresses. If the pointers
8457 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
8458 TOCREL_OFFSET_RET respectively. */
8461 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
8462 const_rtx *tocrel_offset_ret)
8467 if (TARGET_CMODEL != CMODEL_SMALL)
8469 /* When strict ensure we have everything tidy. */
8471 && !(GET_CODE (op) == LO_SUM
8472 && REG_P (XEXP (op, 0))
8473 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
8476 /* When not strict, allow non-split TOC addresses and also allow
8477 (lo_sum (high ..)) TOC addresses created during reload. */
8478 if (GET_CODE (op) == LO_SUM)
8482 const_rtx tocrel_base = op;
8483 const_rtx tocrel_offset = const0_rtx;
8485 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
8487 tocrel_base = XEXP (op, 0);
8488 tocrel_offset = XEXP (op, 1);
8491 if (tocrel_base_ret)
8492 *tocrel_base_ret = tocrel_base;
8493 if (tocrel_offset_ret)
8494 *tocrel_offset_ret = tocrel_offset;
8496 return (GET_CODE (tocrel_base) == UNSPEC
8497 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
8500 /* Return true if X is a constant pool address, and also for cmodel=medium
8501 if X is a toc-relative address known to be offsettable within MODE. */
8504 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
8507 const_rtx tocrel_base, tocrel_offset;
8508 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
8509 && (TARGET_CMODEL != CMODEL_MEDIUM
8510 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
8512 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
8513 INTVAL (tocrel_offset), mode)));
8517 legitimate_small_data_p (machine_mode mode, rtx x)
8519 return (DEFAULT_ABI == ABI_V4
8520 && !flag_pic && !TARGET_TOC
8521 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
8522 && small_data_operand (x, mode));
8526 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
8527 bool strict, bool worst_case)
8529 unsigned HOST_WIDE_INT offset;
8532 if (GET_CODE (x) != PLUS)
8534 if (!REG_P (XEXP (x, 0)))
8536 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8538 if (mode_supports_vsx_dform_quad (mode))
8539 return quad_address_p (x, mode, strict);
8540 if (!reg_offset_addressing_ok_p (mode))
8541 return virtual_stack_registers_memory_p (x);
8542 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
8544 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
8547 offset = INTVAL (XEXP (x, 1));
8553 /* Paired single modes: offset addressing isn't valid. */
8559 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
8561 if (VECTOR_MEM_VSX_P (mode))
8566 if (!TARGET_POWERPC64)
8568 else if (offset & 3)
8581 if (!TARGET_POWERPC64)
8583 else if (offset & 3)
8592 return offset < 0x10000 - extra;
8596 legitimate_indexed_address_p (rtx x, int strict)
8600 if (GET_CODE (x) != PLUS)
8606 return (REG_P (op0) && REG_P (op1)
8607 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
8608 && INT_REG_OK_FOR_INDEX_P (op1, strict))
8609 || (INT_REG_OK_FOR_BASE_P (op1, strict)
8610 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
8614 avoiding_indexed_address_p (machine_mode mode)
8616 /* Avoid indexed addressing for modes that have non-indexed
8617 load/store instruction forms. */
8618 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8622 legitimate_indirect_address_p (rtx x, int strict)
8624 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
8628 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8630 if (!TARGET_MACHO || !flag_pic
8631 || mode != SImode || GET_CODE (x) != MEM)
8635 if (GET_CODE (x) != LO_SUM)
8637 if (GET_CODE (XEXP (x, 0)) != REG)
8639 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8643 return CONSTANT_P (x);
8647 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8649 if (GET_CODE (x) != LO_SUM)
8651 if (GET_CODE (XEXP (x, 0)) != REG)
8653 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8655 /* quad word addresses are restricted, and we can't use LO_SUM. */
8656 if (mode_supports_vsx_dform_quad (mode))
8660 if (TARGET_ELF || TARGET_MACHO)
8664 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8666 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8667 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8668 recognizes some LO_SUM addresses as valid although this
8669 function says opposite. In most cases, LRA through different
8670 transformations can generate correct code for address reloads.
8671 It can not manage only some LO_SUM cases. So we need to add
8672 code analogous to one in rs6000_legitimize_reload_address for
8673 LOW_SUM here saying that some addresses are still valid. */
8674 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8675 && small_toc_ref (x, VOIDmode));
8676 if (TARGET_TOC && ! large_toc_ok)
8678 if (GET_MODE_NUNITS (mode) != 1)
8680 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8681 && !(/* ??? Assume floating point reg based on mode? */
8682 TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
8683 && (mode == DFmode || mode == DDmode)))
8686 return CONSTANT_P (x) || large_toc_ok;
8693 /* Try machine-dependent ways of modifying an illegitimate address
8694 to be legitimate. If we find one, return the new, valid address.
8695 This is used from only one place: `memory_address' in explow.c.
8697 OLDX is the address as it was before break_out_memory_refs was
8698 called. In some cases it is useful to look at this to decide what
8701 It is always safe for this function to do nothing. It exists to
8702 recognize opportunities to optimize the output.
8704 On RS/6000, first check for the sum of a register with a constant
8705 integer that is out of range. If so, generate code to add the
8706 constant with the low-order 16 bits masked to the register and force
8707 this result into another register (this can be done with `cau').
8708 Then generate an address of REG+(CONST&0xffff), allowing for the
8709 possibility of bit 16 being a one.
8711 Then check for the sum of a register and something not constant, try to
8712 load the other things into a register and return the sum. */
8715 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8720 if (!reg_offset_addressing_ok_p (mode)
8721 || mode_supports_vsx_dform_quad (mode))
8723 if (virtual_stack_registers_memory_p (x))
8726 /* In theory we should not be seeing addresses of the form reg+0,
8727 but just in case it is generated, optimize it away. */
8728 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8729 return force_reg (Pmode, XEXP (x, 0));
8731 /* For TImode with load/store quad, restrict addresses to just a single
8732 pointer, so it works with both GPRs and VSX registers. */
8733 /* Make sure both operands are registers. */
8734 else if (GET_CODE (x) == PLUS
8735 && (mode != TImode || !TARGET_VSX))
8736 return gen_rtx_PLUS (Pmode,
8737 force_reg (Pmode, XEXP (x, 0)),
8738 force_reg (Pmode, XEXP (x, 1)));
8740 return force_reg (Pmode, x);
8742 if (GET_CODE (x) == SYMBOL_REF)
8744 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8746 return rs6000_legitimize_tls_address (x, model);
8758 /* As in legitimate_offset_address_p we do not assume
8759 worst-case. The mode here is just a hint as to the registers
8760 used. A TImode is usually in gprs, but may actually be in
8761 fprs. Leave worst-case scenario for reload to handle via
8762 insn constraints. PTImode is only GPRs. */
8769 if (GET_CODE (x) == PLUS
8770 && GET_CODE (XEXP (x, 0)) == REG
8771 && GET_CODE (XEXP (x, 1)) == CONST_INT
8772 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8774 && !PAIRED_VECTOR_MODE (mode))
8776 HOST_WIDE_INT high_int, low_int;
8778 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8779 if (low_int >= 0x8000 - extra)
8781 high_int = INTVAL (XEXP (x, 1)) - low_int;
8782 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8783 GEN_INT (high_int)), 0);
8784 return plus_constant (Pmode, sum, low_int);
8786 else if (GET_CODE (x) == PLUS
8787 && GET_CODE (XEXP (x, 0)) == REG
8788 && GET_CODE (XEXP (x, 1)) != CONST_INT
8789 && GET_MODE_NUNITS (mode) == 1
8790 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8791 || (/* ??? Assume floating point reg based on mode? */
8792 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8793 && (mode == DFmode || mode == DDmode)))
8794 && !avoiding_indexed_address_p (mode))
8796 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8797 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8799 else if (PAIRED_VECTOR_MODE (mode))
8803 /* We accept [reg + reg]. */
8805 if (GET_CODE (x) == PLUS)
8807 rtx op1 = XEXP (x, 0);
8808 rtx op2 = XEXP (x, 1);
8811 op1 = force_reg (Pmode, op1);
8812 op2 = force_reg (Pmode, op2);
8814 /* We can't always do [reg + reg] for these, because [reg +
8815 reg + offset] is not a legitimate addressing mode. */
8816 y = gen_rtx_PLUS (Pmode, op1, op2);
8818 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
8819 return force_reg (Pmode, y);
8824 return force_reg (Pmode, x);
8826 else if ((TARGET_ELF
8828 || !MACHO_DYNAMIC_NO_PIC_P
8834 && GET_CODE (x) != CONST_INT
8835 && GET_CODE (x) != CONST_WIDE_INT
8836 && GET_CODE (x) != CONST_DOUBLE
8838 && GET_MODE_NUNITS (mode) == 1
8839 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8840 || (/* ??? Assume floating point reg based on mode? */
8841 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8842 && (mode == DFmode || mode == DDmode))))
8844 rtx reg = gen_reg_rtx (Pmode);
8846 emit_insn (gen_elf_high (reg, x));
8848 emit_insn (gen_macho_high (reg, x));
8849 return gen_rtx_LO_SUM (Pmode, reg, x);
8852 && GET_CODE (x) == SYMBOL_REF
8853 && constant_pool_expr_p (x)
8854 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8855 return create_TOC_reference (x, NULL_RTX);
8860 /* Debug version of rs6000_legitimize_address. */
8862 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8868 ret = rs6000_legitimize_address (x, oldx, mode);
8869 insns = get_insns ();
8875 "\nrs6000_legitimize_address: mode %s, old code %s, "
8876 "new code %s, modified\n",
8877 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8878 GET_RTX_NAME (GET_CODE (ret)));
8880 fprintf (stderr, "Original address:\n");
8883 fprintf (stderr, "oldx:\n");
8886 fprintf (stderr, "New address:\n");
8891 fprintf (stderr, "Insns added:\n");
8892 debug_rtx_list (insns, 20);
8898 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8899 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8910 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8911 We need to emit DTP-relative relocations. */
8913 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8915 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8920 fputs ("\t.long\t", file);
8923 fputs (DOUBLE_INT_ASM_OP, file);
8928 output_addr_const (file, x);
8930 fputs ("@dtprel+0x8000", file);
8931 else if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF)
8933 switch (SYMBOL_REF_TLS_MODEL (x))
8937 case TLS_MODEL_LOCAL_EXEC:
8938 fputs ("@le", file);
8940 case TLS_MODEL_INITIAL_EXEC:
8941 fputs ("@ie", file);
8943 case TLS_MODEL_GLOBAL_DYNAMIC:
8944 case TLS_MODEL_LOCAL_DYNAMIC:
8953 /* Return true if X is a symbol that refers to real (rather than emulated)
8957 rs6000_real_tls_symbol_ref_p (rtx x)
8959 return (GET_CODE (x) == SYMBOL_REF
8960 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8963 /* In the name of slightly smaller debug output, and to cater to
8964 general assembler lossage, recognize various UNSPEC sequences
8965 and turn them back into a direct symbol reference. */
8968 rs6000_delegitimize_address (rtx orig_x)
8972 orig_x = delegitimize_mem_from_attrs (orig_x);
8978 if (TARGET_CMODEL != CMODEL_SMALL
8979 && GET_CODE (y) == LO_SUM)
8983 if (GET_CODE (y) == PLUS
8984 && GET_MODE (y) == Pmode
8985 && CONST_INT_P (XEXP (y, 1)))
8987 offset = XEXP (y, 1);
8991 if (GET_CODE (y) == UNSPEC
8992 && XINT (y, 1) == UNSPEC_TOCREL)
8994 y = XVECEXP (y, 0, 0);
8997 /* Do not associate thread-local symbols with the original
8998 constant pool symbol. */
9000 && GET_CODE (y) == SYMBOL_REF
9001 && CONSTANT_POOL_ADDRESS_P (y)
9002 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
9006 if (offset != NULL_RTX)
9007 y = gen_rtx_PLUS (Pmode, y, offset);
9008 if (!MEM_P (orig_x))
9011 return replace_equiv_address_nv (orig_x, y);
9015 && GET_CODE (orig_x) == LO_SUM
9016 && GET_CODE (XEXP (orig_x, 1)) == CONST)
9018 y = XEXP (XEXP (orig_x, 1), 0);
9019 if (GET_CODE (y) == UNSPEC
9020 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
9021 return XVECEXP (y, 0, 0);
9027 /* Return true if X shouldn't be emitted into the debug info.
9028 The linker doesn't like .toc section references from
9029 .debug_* sections, so reject .toc section symbols. */
9032 rs6000_const_not_ok_for_debug_p (rtx x)
9034 if (GET_CODE (x) == UNSPEC)
9036 if (GET_CODE (x) == SYMBOL_REF
9037 && CONSTANT_POOL_ADDRESS_P (x))
9039 rtx c = get_pool_constant (x);
9040 machine_mode cmode = get_pool_mode (x);
9041 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
9049 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
9052 rs6000_legitimate_combined_insn (rtx_insn *insn)
9054 int icode = INSN_CODE (insn);
9056 /* Reject creating doloop insns. Combine should not be allowed
9057 to create these for a number of reasons:
9058 1) In a nested loop, if combine creates one of these in an
9059 outer loop and the register allocator happens to allocate ctr
9060 to the outer loop insn, then the inner loop can't use ctr.
9061 Inner loops ought to be more highly optimized.
9062 2) Combine often wants to create one of these from what was
9063 originally a three insn sequence, first combining the three
9064 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
9065 allocated ctr, the splitter takes use back to the three insn
9066 sequence. It's better to stop combine at the two insn
9068 3) Faced with not being able to allocate ctr for ctrsi/crtdi
9069 insns, the register allocator sometimes uses floating point
9070 or vector registers for the pseudo. Since ctrsi/ctrdi is a
9071 jump insn and output reloads are not implemented for jumps,
9072 the ctrsi/ctrdi splitters need to handle all possible cases.
9073 That's a pain, and it gets to be seriously difficult when a
9074 splitter that runs after reload needs memory to transfer from
9075 a gpr to fpr. See PR70098 and PR71763 which are not fixed
9076 for the difficult case. It's better to not create problems
9077 in the first place. */
9078 if (icode != CODE_FOR_nothing
9079 && (icode == CODE_FOR_bdz_si
9080 || icode == CODE_FOR_bdz_di
9081 || icode == CODE_FOR_bdnz_si
9082 || icode == CODE_FOR_bdnz_di
9083 || icode == CODE_FOR_bdztf_si
9084 || icode == CODE_FOR_bdztf_di
9085 || icode == CODE_FOR_bdnztf_si
9086 || icode == CODE_FOR_bdnztf_di))
9092 /* Construct the SYMBOL_REF for the tls_get_addr function. */
9094 static GTY(()) rtx rs6000_tls_symbol;
9096 rs6000_tls_get_addr (void)
9098 if (!rs6000_tls_symbol)
9099 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
9101 return rs6000_tls_symbol;
9104 /* Construct the SYMBOL_REF for TLS GOT references. */
9106 static GTY(()) rtx rs6000_got_symbol;
9108 rs6000_got_sym (void)
9110 if (!rs6000_got_symbol)
9112 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9113 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
9114 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
9117 return rs6000_got_symbol;
9120 /* AIX Thread-Local Address support. */
9123 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
9125 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
9129 name = XSTR (addr, 0);
9130 /* Append TLS CSECT qualifier, unless the symbol already is qualified
9131 or the symbol will be in TLS private data section. */
9132 if (name[strlen (name) - 1] != ']'
9133 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
9134 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
9136 tlsname = XALLOCAVEC (char, strlen (name) + 4);
9137 strcpy (tlsname, name);
9139 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
9140 tlsaddr = copy_rtx (addr);
9141 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
9146 /* Place addr into TOC constant pool. */
9147 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
9149 /* Output the TOC entry and create the MEM referencing the value. */
9150 if (constant_pool_expr_p (XEXP (sym, 0))
9151 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
9153 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
9154 mem = gen_const_mem (Pmode, tocref);
9155 set_mem_alias_set (mem, get_TOC_alias_set ());
9160 /* Use global-dynamic for local-dynamic. */
9161 if (model == TLS_MODEL_GLOBAL_DYNAMIC
9162 || model == TLS_MODEL_LOCAL_DYNAMIC)
9164 /* Create new TOC reference for @m symbol. */
9165 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
9166 tlsname = XALLOCAVEC (char, strlen (name) + 1);
9167 strcpy (tlsname, "*LCM");
9168 strcat (tlsname, name + 3);
9169 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
9170 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
9171 tocref = create_TOC_reference (modaddr, NULL_RTX);
9172 rtx modmem = gen_const_mem (Pmode, tocref);
9173 set_mem_alias_set (modmem, get_TOC_alias_set ());
9175 rtx modreg = gen_reg_rtx (Pmode);
9176 emit_insn (gen_rtx_SET (modreg, modmem));
9178 tmpreg = gen_reg_rtx (Pmode);
9179 emit_insn (gen_rtx_SET (tmpreg, mem));
9181 dest = gen_reg_rtx (Pmode);
9183 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
9185 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
9188 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
9189 else if (TARGET_32BIT)
9191 tlsreg = gen_reg_rtx (SImode);
9192 emit_insn (gen_tls_get_tpointer (tlsreg));
9195 tlsreg = gen_rtx_REG (DImode, 13);
9197 /* Load the TOC value into temporary register. */
9198 tmpreg = gen_reg_rtx (Pmode);
9199 emit_insn (gen_rtx_SET (tmpreg, mem));
9200 set_unique_reg_note (get_last_insn (), REG_EQUAL,
9201 gen_rtx_MINUS (Pmode, addr, tlsreg));
9203 /* Add TOC symbol value to TLS pointer. */
9204 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
9209 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
9210 this (thread-local) address. */
9213 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
9218 return rs6000_legitimize_tls_address_aix (addr, model);
9220 dest = gen_reg_rtx (Pmode);
9221 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
9227 tlsreg = gen_rtx_REG (Pmode, 13);
9228 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
9232 tlsreg = gen_rtx_REG (Pmode, 2);
9233 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
9237 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
9241 tmp = gen_reg_rtx (Pmode);
9244 tlsreg = gen_rtx_REG (Pmode, 13);
9245 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
9249 tlsreg = gen_rtx_REG (Pmode, 2);
9250 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
9254 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
9256 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
9261 rtx r3, got, tga, tmp1, tmp2, call_insn;
9263 /* We currently use relocations like @got@tlsgd for tls, which
9264 means the linker will handle allocation of tls entries, placing
9265 them in the .got section. So use a pointer to the .got section,
9266 not one to secondary TOC sections used by 64-bit -mminimal-toc,
9267 or to secondary GOT sections used by 32-bit -fPIC. */
9269 got = gen_rtx_REG (Pmode, 2);
9273 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9276 rtx gsym = rs6000_got_sym ();
9277 got = gen_reg_rtx (Pmode);
9279 rs6000_emit_move (got, gsym, Pmode);
9284 tmp1 = gen_reg_rtx (Pmode);
9285 tmp2 = gen_reg_rtx (Pmode);
9286 mem = gen_const_mem (Pmode, tmp1);
9287 lab = gen_label_rtx ();
9288 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
9289 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
9290 if (TARGET_LINK_STACK)
9291 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
9292 emit_move_insn (tmp2, mem);
9293 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
9294 set_unique_reg_note (last, REG_EQUAL, gsym);
9299 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
9301 tga = rs6000_tls_get_addr ();
9302 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
9305 r3 = gen_rtx_REG (Pmode, 3);
9306 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9309 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
9311 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
9313 else if (DEFAULT_ABI == ABI_V4)
9314 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
9317 call_insn = last_call_insn ();
9318 PATTERN (call_insn) = insn;
9319 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9320 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9321 pic_offset_table_rtx);
9323 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
9325 tga = rs6000_tls_get_addr ();
9326 tmp1 = gen_reg_rtx (Pmode);
9327 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
9330 r3 = gen_rtx_REG (Pmode, 3);
9331 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9334 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
9336 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
9338 else if (DEFAULT_ABI == ABI_V4)
9339 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
9342 call_insn = last_call_insn ();
9343 PATTERN (call_insn) = insn;
9344 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9345 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9346 pic_offset_table_rtx);
9348 if (rs6000_tls_size == 16)
9351 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
9353 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
9355 else if (rs6000_tls_size == 32)
9357 tmp2 = gen_reg_rtx (Pmode);
9359 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
9361 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
9364 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
9366 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
9370 tmp2 = gen_reg_rtx (Pmode);
9372 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
9374 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
9376 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
9382 /* IE, or 64-bit offset LE. */
9383 tmp2 = gen_reg_rtx (Pmode);
9385 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
9387 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
9390 insn = gen_tls_tls_64 (dest, tmp2, addr);
9392 insn = gen_tls_tls_32 (dest, tmp2, addr);
9400 /* Only create the global variable for the stack protect guard if we are using
9401 the global flavor of that guard. */
9403 rs6000_init_stack_protect_guard (void)
9405 if (rs6000_stack_protector_guard == SSP_GLOBAL)
9406 return default_stack_protect_guard ();
9411 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
9414 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
9416 if (GET_CODE (x) == HIGH
9417 && GET_CODE (XEXP (x, 0)) == UNSPEC)
9420 /* A TLS symbol in the TOC cannot contain a sum. */
9421 if (GET_CODE (x) == CONST
9422 && GET_CODE (XEXP (x, 0)) == PLUS
9423 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9424 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
9427 /* Do not place an ELF TLS symbol in the constant pool. */
9428 return TARGET_ELF && tls_referenced_p (x);
9431 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
9432 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
9433 can be addressed relative to the toc pointer. */
9436 use_toc_relative_ref (rtx sym, machine_mode mode)
9438 return ((constant_pool_expr_p (sym)
9439 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
9440 get_pool_mode (sym)))
9441 || (TARGET_CMODEL == CMODEL_MEDIUM
9442 && SYMBOL_REF_LOCAL_P (sym)
9443 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
9446 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
9447 replace the input X, or the original X if no replacement is called for.
9448 The output parameter *WIN is 1 if the calling macro should goto WIN,
9451 For RS/6000, we wish to handle large displacements off a base
9452 register by splitting the addend across an addiu/addis and the mem insn.
9453 This cuts number of extra insns needed from 3 to 1.
9455 On Darwin, we use this to generate code for floating point constants.
9456 A movsf_low is generated so we wind up with 2 instructions rather than 3.
9457 The Darwin code is inside #if TARGET_MACHO because only then are the
9458 machopic_* functions defined. */
9460 rs6000_legitimize_reload_address (rtx x, machine_mode mode,
9461 int opnum, int type,
9462 int ind_levels ATTRIBUTE_UNUSED, int *win)
9464 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9465 bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
9467 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
9468 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
9471 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
9472 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)
9473 || (mode == SFmode && recog_data.operand_mode[0] == V4SFmode
9474 && TARGET_P9_VECTOR)
9475 || (mode == SImode && recog_data.operand_mode[0] == V4SImode
9476 && TARGET_P9_VECTOR)))
9477 reg_offset_p = false;
9479 /* We must recognize output that we have already generated ourselves. */
9480 if (GET_CODE (x) == PLUS
9481 && GET_CODE (XEXP (x, 0)) == PLUS
9482 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9483 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9484 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9486 if (TARGET_DEBUG_ADDR)
9488 fprintf (stderr, "\nlegitimize_reload_address push_reload #1:\n");
9491 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9492 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9493 opnum, (enum reload_type) type);
9498 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
9499 if (GET_CODE (x) == LO_SUM
9500 && GET_CODE (XEXP (x, 0)) == HIGH)
9502 if (TARGET_DEBUG_ADDR)
9504 fprintf (stderr, "\nlegitimize_reload_address push_reload #2:\n");
9507 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9508 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9509 opnum, (enum reload_type) type);
9515 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
9516 && GET_CODE (x) == LO_SUM
9517 && GET_CODE (XEXP (x, 0)) == PLUS
9518 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
9519 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
9520 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
9521 && machopic_operand_p (XEXP (x, 1)))
9523 /* Result of previous invocation of this function on Darwin
9524 floating point constant. */
9525 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9526 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9527 opnum, (enum reload_type) type);
9533 if (TARGET_CMODEL != CMODEL_SMALL
9536 && small_toc_ref (x, VOIDmode))
9538 rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
9539 x = gen_rtx_LO_SUM (Pmode, hi, x);
9540 if (TARGET_DEBUG_ADDR)
9542 fprintf (stderr, "\nlegitimize_reload_address push_reload #3:\n");
9545 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9546 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9547 opnum, (enum reload_type) type);
9552 if (GET_CODE (x) == PLUS
9553 && REG_P (XEXP (x, 0))
9554 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
9555 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
9556 && CONST_INT_P (XEXP (x, 1))
9558 && !PAIRED_VECTOR_MODE (mode)
9559 && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
9561 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
9562 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
9564 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
9566 /* Check for 32-bit overflow or quad addresses with one of the
9567 four least significant bits set. */
9568 if (high + low != val
9569 || (quad_offset_p && (low & 0xf)))
9575 /* Reload the high part into a base reg; leave the low part
9576 in the mem directly. */
9578 x = gen_rtx_PLUS (GET_MODE (x),
9579 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
9583 if (TARGET_DEBUG_ADDR)
9585 fprintf (stderr, "\nlegitimize_reload_address push_reload #4:\n");
9588 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9589 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9590 opnum, (enum reload_type) type);
9595 if (GET_CODE (x) == SYMBOL_REF
9598 && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
9599 && !PAIRED_VECTOR_MODE (mode)
9601 && DEFAULT_ABI == ABI_DARWIN
9602 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
9603 && machopic_symbol_defined_p (x)
9605 && DEFAULT_ABI == ABI_V4
9608 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
9609 The same goes for DImode without 64-bit gprs and DFmode and DDmode
9611 ??? Assume floating point reg based on mode? This assumption is
9612 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
9613 where reload ends up doing a DFmode load of a constant from
9614 mem using two gprs. Unfortunately, at this point reload
9615 hasn't yet selected regs so poking around in reload data
9616 won't help and even if we could figure out the regs reliably,
9617 we'd still want to allow this transformation when the mem is
9618 naturally aligned. Since we say the address is good here, we
9619 can't disable offsets from LO_SUMs in mem_operand_gpr.
9620 FIXME: Allow offset from lo_sum for other modes too, when
9621 mem is sufficiently aligned.
9623 Also disallow this if the type can go in VMX/Altivec registers, since
9624 those registers do not have d-form (reg+offset) address modes. */
9625 && !reg_addr[mode].scalar_in_vmx_p
9630 && (mode != TImode || !TARGET_VSX)
9632 && (mode != DImode || TARGET_POWERPC64)
9633 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
9634 || (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)))
9639 rtx offset = machopic_gen_offset (x);
9640 x = gen_rtx_LO_SUM (GET_MODE (x),
9641 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
9642 gen_rtx_HIGH (Pmode, offset)), offset);
9646 x = gen_rtx_LO_SUM (GET_MODE (x),
9647 gen_rtx_HIGH (Pmode, x), x);
9649 if (TARGET_DEBUG_ADDR)
9651 fprintf (stderr, "\nlegitimize_reload_address push_reload #5:\n");
9654 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9655 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9656 opnum, (enum reload_type) type);
9661 /* Reload an offset address wrapped by an AND that represents the
9662 masking of the lower bits. Strip the outer AND and let reload
9663 convert the offset address into an indirect address. For VSX,
9664 force reload to create the address with an AND in a separate
9665 register, because we can't guarantee an altivec register will
9667 if (VECTOR_MEM_ALTIVEC_P (mode)
9668 && GET_CODE (x) == AND
9669 && GET_CODE (XEXP (x, 0)) == PLUS
9670 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9671 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9672 && GET_CODE (XEXP (x, 1)) == CONST_INT
9673 && INTVAL (XEXP (x, 1)) == -16)
9683 && GET_CODE (x) == SYMBOL_REF
9684 && use_toc_relative_ref (x, mode))
9686 x = create_TOC_reference (x, NULL_RTX);
9687 if (TARGET_CMODEL != CMODEL_SMALL)
9689 if (TARGET_DEBUG_ADDR)
9691 fprintf (stderr, "\nlegitimize_reload_address push_reload #6:\n");
9694 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9695 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9696 opnum, (enum reload_type) type);
9705 /* Debug version of rs6000_legitimize_reload_address. */
9707 rs6000_debug_legitimize_reload_address (rtx x, machine_mode mode,
9708 int opnum, int type,
9709 int ind_levels, int *win)
9711 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
9714 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9715 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9716 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
9720 fprintf (stderr, "Same address returned\n");
9722 fprintf (stderr, "NULL returned\n");
9725 fprintf (stderr, "New address:\n");
9732 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9733 that is a valid memory address for an instruction.
9734 The MODE argument is the machine mode for the MEM expression
9735 that wants to use this address.
9737 On the RS/6000, there are four valid address: a SYMBOL_REF that
9738 refers to a constant pool entry of an address (or the sum of it
9739 plus a constant), a short (16-bit signed) constant plus a register,
9740 the sum of two registers, or a register indirect, possibly with an
9741 auto-increment. For DFmode, DDmode and DImode with a constant plus
9742 register, we must ensure that both words are addressable or PowerPC64
9743 with offset word aligned.
9745 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9746 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9747 because adjacent memory cells are accessed by adding word-sized offsets
9748 during assembly output. */
9750 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
9752 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9753 bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
9755 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9756 if (VECTOR_MEM_ALTIVEC_P (mode)
9757 && GET_CODE (x) == AND
9758 && GET_CODE (XEXP (x, 1)) == CONST_INT
9759 && INTVAL (XEXP (x, 1)) == -16)
9762 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
9764 if (legitimate_indirect_address_p (x, reg_ok_strict))
9767 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
9768 && mode_supports_pre_incdec_p (mode)
9769 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
9771 /* Handle restricted vector d-form offsets in ISA 3.0. */
9774 if (quad_address_p (x, mode, reg_ok_strict))
9777 else if (virtual_stack_registers_memory_p (x))
9780 else if (reg_offset_p)
9782 if (legitimate_small_data_p (mode, x))
9784 if (legitimate_constant_pool_address_p (x, mode,
9785 reg_ok_strict || lra_in_progress))
9787 if (reg_addr[mode].fused_toc && GET_CODE (x) == UNSPEC
9788 && XINT (x, 1) == UNSPEC_FUSION_ADDIS)
9792 /* For TImode, if we have TImode in VSX registers, only allow register
9793 indirect addresses. This will allow the values to go in either GPRs
9794 or VSX registers without reloading. The vector types would tend to
9795 go into VSX registers, so we allow REG+REG, while TImode seems
9796 somewhat split, in that some uses are GPR based, and some VSX based. */
9797 /* FIXME: We could loosen this by changing the following to
9798 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
9799 but currently we cannot allow REG+REG addressing for TImode. See
9800 PR72827 for complete details on how this ends up hoodwinking DSE. */
9801 if (mode == TImode && TARGET_VSX)
9803 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9806 && GET_CODE (x) == PLUS
9807 && GET_CODE (XEXP (x, 0)) == REG
9808 && (XEXP (x, 0) == virtual_stack_vars_rtx
9809 || XEXP (x, 0) == arg_pointer_rtx)
9810 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9812 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
9814 if (!FLOAT128_2REG_P (mode)
9815 && ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9817 || (mode != DFmode && mode != DDmode))
9818 && (TARGET_POWERPC64 || mode != DImode)
9819 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
9821 && !avoiding_indexed_address_p (mode)
9822 && legitimate_indexed_address_p (x, reg_ok_strict))
9824 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
9825 && mode_supports_pre_modify_p (mode)
9826 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
9827 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
9828 reg_ok_strict, false)
9829 || (!avoiding_indexed_address_p (mode)
9830 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
9831 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
9833 if (reg_offset_p && !quad_offset_p
9834 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
9839 /* Debug version of rs6000_legitimate_address_p. */
9841 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
9844 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
9846 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9847 "strict = %d, reload = %s, code = %s\n",
9848 ret ? "true" : "false",
9849 GET_MODE_NAME (mode),
9851 (reload_completed ? "after" : "before"),
9852 GET_RTX_NAME (GET_CODE (x)));
9858 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9861 rs6000_mode_dependent_address_p (const_rtx addr,
9862 addr_space_t as ATTRIBUTE_UNUSED)
9864 return rs6000_mode_dependent_address_ptr (addr);
9867 /* Go to LABEL if ADDR (a legitimate address expression)
9868 has an effect that depends on the machine mode it is used for.
9870 On the RS/6000 this is true of all integral offsets (since AltiVec
9871 and VSX modes don't allow them) or is a pre-increment or decrement.
9873 ??? Except that due to conceptual problems in offsettable_address_p
9874 we can't really report the problems of integral offsets. So leave
9875 this assuming that the adjustable offset must be valid for the
9876 sub-words of a TFmode operand, which is what we had before. */
9879 rs6000_mode_dependent_address (const_rtx addr)
9881 switch (GET_CODE (addr))
9884 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9885 is considered a legitimate address before reload, so there
9886 are no offset restrictions in that case. Note that this
9887 condition is safe in strict mode because any address involving
9888 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9889 been rejected as illegitimate. */
9890 if (XEXP (addr, 0) != virtual_stack_vars_rtx
9891 && XEXP (addr, 0) != arg_pointer_rtx
9892 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
9894 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
9895 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
9900 /* Anything in the constant pool is sufficiently aligned that
9901 all bytes have the same high part address. */
9902 return !legitimate_constant_pool_address_p (addr, QImode, false);
9904 /* Auto-increment cases are now treated generically in recog.c. */
9906 return TARGET_UPDATE;
9908 /* AND is only allowed in Altivec loads. */
9919 /* Debug version of rs6000_mode_dependent_address. */
9921 rs6000_debug_mode_dependent_address (const_rtx addr)
9923 bool ret = rs6000_mode_dependent_address (addr);
9925 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9926 ret ? "true" : "false");
9932 /* Implement FIND_BASE_TERM. */
9935 rs6000_find_base_term (rtx op)
9940 if (GET_CODE (base) == CONST)
9941 base = XEXP (base, 0);
9942 if (GET_CODE (base) == PLUS)
9943 base = XEXP (base, 0);
9944 if (GET_CODE (base) == UNSPEC)
9945 switch (XINT (base, 1))
9948 case UNSPEC_MACHOPIC_OFFSET:
9949 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9950 for aliasing purposes. */
9951 return XVECEXP (base, 0, 0);
9957 /* More elaborate version of recog's offsettable_memref_p predicate
9958 that works around the ??? note of rs6000_mode_dependent_address.
9959 In particular it accepts
9961 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9963 in 32-bit mode, that the recog predicate rejects. */
9966 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode)
9973 /* First mimic offsettable_memref_p. */
9974 if (offsettable_address_p (true, GET_MODE (op), XEXP (op, 0)))
9977 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9978 the latter predicate knows nothing about the mode of the memory
9979 reference and, therefore, assumes that it is the largest supported
9980 mode (TFmode). As a consequence, legitimate offsettable memory
9981 references are rejected. rs6000_legitimate_offset_address_p contains
9982 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9983 at least with a little bit of help here given that we know the
9984 actual registers used. */
9985 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9986 || GET_MODE_SIZE (reg_mode) == 4);
9987 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9991 /* Determine the reassociation width to be used in reassociate_bb.
9992 This takes into account how many parallel operations we
9993 can actually do of a given type, and also the latency.
9997 vect add/sub/mul 2/cycle
9998 fp add/sub/mul 2/cycle
10003 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
10006 switch (rs6000_tune)
10008 case PROCESSOR_POWER8:
10009 case PROCESSOR_POWER9:
10010 if (DECIMAL_FLOAT_MODE_P (mode))
10012 if (VECTOR_MODE_P (mode))
10014 if (INTEGRAL_MODE_P (mode))
10015 return opc == MULT_EXPR ? 4 : 6;
10016 if (FLOAT_MODE_P (mode))
10025 /* Change register usage conditional on target flags. */
10027 rs6000_conditional_register_usage (void)
10031 if (TARGET_DEBUG_TARGET)
10032 fprintf (stderr, "rs6000_conditional_register_usage called\n");
10034 /* Set MQ register fixed (already call_used) so that it will not be
10036 fixed_regs[64] = 1;
10038 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
10040 fixed_regs[13] = call_used_regs[13]
10041 = call_really_used_regs[13] = 1;
10043 /* Conditionally disable FPRs. */
10044 if (TARGET_SOFT_FLOAT)
10045 for (i = 32; i < 64; i++)
10046 fixed_regs[i] = call_used_regs[i]
10047 = call_really_used_regs[i] = 1;
10049 /* The TOC register is not killed across calls in a way that is
10050 visible to the compiler. */
10051 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10052 call_really_used_regs[2] = 0;
10054 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
10055 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10057 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10058 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10059 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10060 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10062 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
10063 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10064 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10065 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10067 if (TARGET_TOC && TARGET_MINIMAL_TOC)
10068 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10069 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10071 if (!TARGET_ALTIVEC && !TARGET_VSX)
10073 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10074 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
10075 call_really_used_regs[VRSAVE_REGNO] = 1;
10078 if (TARGET_ALTIVEC || TARGET_VSX)
10079 global_regs[VSCR_REGNO] = 1;
10081 if (TARGET_ALTIVEC_ABI)
10083 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
10084 call_used_regs[i] = call_really_used_regs[i] = 1;
10086 /* AIX reserves VR20:31 in non-extended ABI mode. */
10088 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
10089 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
10094 /* Output insns to set DEST equal to the constant SOURCE as a series of
10095 lis, ori and shl instructions and return TRUE. */
10098 rs6000_emit_set_const (rtx dest, rtx source)
10100 machine_mode mode = GET_MODE (dest);
10105 gcc_checking_assert (CONST_INT_P (source));
10106 c = INTVAL (source);
10111 emit_insn (gen_rtx_SET (dest, source));
10115 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
10117 emit_insn (gen_rtx_SET (copy_rtx (temp),
10118 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
10119 emit_insn (gen_rtx_SET (dest,
10120 gen_rtx_IOR (SImode, copy_rtx (temp),
10121 GEN_INT (c & 0xffff))));
10125 if (!TARGET_POWERPC64)
10129 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
10131 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
10133 emit_move_insn (hi, GEN_INT (c >> 32));
10134 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
10135 emit_move_insn (lo, GEN_INT (c));
10138 rs6000_emit_set_long_const (dest, c);
10142 gcc_unreachable ();
10145 insn = get_last_insn ();
10146 set = single_set (insn);
10147 if (! CONSTANT_P (SET_SRC (set)))
10148 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
10153 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
10154 Output insns to set DEST equal to the constant C as a series of
10155 lis, ori and shl instructions. */
10158 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
10161 HOST_WIDE_INT ud1, ud2, ud3, ud4;
10171 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
10172 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
10173 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
10175 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
10176 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
10178 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10180 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10181 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
10183 emit_move_insn (dest,
10184 gen_rtx_IOR (DImode, copy_rtx (temp),
10187 else if (ud3 == 0 && ud4 == 0)
10189 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10191 gcc_assert (ud2 & 0x8000);
10192 emit_move_insn (copy_rtx (temp),
10193 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
10195 emit_move_insn (copy_rtx (temp),
10196 gen_rtx_IOR (DImode, copy_rtx (temp),
10198 emit_move_insn (dest,
10199 gen_rtx_ZERO_EXTEND (DImode,
10200 gen_lowpart (SImode,
10201 copy_rtx (temp))));
10203 else if ((ud4 == 0xffff && (ud3 & 0x8000))
10204 || (ud4 == 0 && ! (ud3 & 0x8000)))
10206 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10208 emit_move_insn (copy_rtx (temp),
10209 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
10211 emit_move_insn (copy_rtx (temp),
10212 gen_rtx_IOR (DImode, copy_rtx (temp),
10214 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10215 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
10218 emit_move_insn (dest,
10219 gen_rtx_IOR (DImode, copy_rtx (temp),
10224 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10226 emit_move_insn (copy_rtx (temp),
10227 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
10229 emit_move_insn (copy_rtx (temp),
10230 gen_rtx_IOR (DImode, copy_rtx (temp),
10233 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
10234 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
10237 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10238 gen_rtx_IOR (DImode, copy_rtx (temp),
10239 GEN_INT (ud2 << 16)));
10241 emit_move_insn (dest,
10242 gen_rtx_IOR (DImode, copy_rtx (temp),
10247 /* Helper for the following. Get rid of [r+r] memory refs
10248 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
10251 rs6000_eliminate_indexed_memrefs (rtx operands[2])
10253 if (GET_CODE (operands[0]) == MEM
10254 && GET_CODE (XEXP (operands[0], 0)) != REG
10255 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
10256 GET_MODE (operands[0]), false))
10258 = replace_equiv_address (operands[0],
10259 copy_addr_to_reg (XEXP (operands[0], 0)));
10261 if (GET_CODE (operands[1]) == MEM
10262 && GET_CODE (XEXP (operands[1], 0)) != REG
10263 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
10264 GET_MODE (operands[1]), false))
10266 = replace_equiv_address (operands[1],
10267 copy_addr_to_reg (XEXP (operands[1], 0)));
10270 /* Generate a vector of constants to permute MODE for a little-endian
10271 storage operation by swapping the two halves of a vector. */
10273 rs6000_const_vec (machine_mode mode)
10301 v = rtvec_alloc (subparts);
10303 for (i = 0; i < subparts / 2; ++i)
10304 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
10305 for (i = subparts / 2; i < subparts; ++i)
10306 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
10311 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
10312 store operation. */
10314 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
10316 /* Scalar permutations are easier to express in integer modes rather than
10317 floating-point modes, so cast them here. We use V1TImode instead
10318 of TImode to ensure that the values don't go through GPRs. */
10319 if (FLOAT128_VECTOR_P (mode))
10321 dest = gen_lowpart (V1TImode, dest);
10322 source = gen_lowpart (V1TImode, source);
10326 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
10328 if (mode == TImode || mode == V1TImode)
10329 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
10333 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
10334 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
10338 /* Emit a little-endian load from vector memory location SOURCE to VSX
10339 register DEST in mode MODE. The load is done with two permuting
10340 insn's that represent an lxvd2x and xxpermdi. */
10342 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
10344 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
10346 if (mode == TImode || mode == V1TImode)
10349 dest = gen_lowpart (V2DImode, dest);
10350 source = adjust_address (source, V2DImode, 0);
10353 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
10354 rs6000_emit_le_vsx_permute (tmp, source, mode);
10355 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10358 /* Emit a little-endian store to vector memory location DEST from VSX
10359 register SOURCE in mode MODE. The store is done with two permuting
10360 insn's that represent an xxpermdi and an stxvd2x. */
10362 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
10364 /* This should never be called during or after LRA, because it does
10365 not re-permute the source register. It is intended only for use
10367 gcc_assert (!lra_in_progress && !reload_completed);
10369 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
10371 if (mode == TImode || mode == V1TImode)
10374 dest = adjust_address (dest, V2DImode, 0);
10375 source = gen_lowpart (V2DImode, source);
10378 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
10379 rs6000_emit_le_vsx_permute (tmp, source, mode);
10380 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10383 /* Emit a sequence representing a little-endian VSX load or store,
10384 moving data from SOURCE to DEST in mode MODE. This is done
10385 separately from rs6000_emit_move to ensure it is called only
10386 during expand. LE VSX loads and stores introduced later are
10387 handled with a split. The expand-time RTL generation allows
10388 us to optimize away redundant pairs of register-permutes. */
10390 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
10392 gcc_assert (!BYTES_BIG_ENDIAN
10393 && VECTOR_MEM_VSX_P (mode)
10394 && !TARGET_P9_VECTOR
10395 && !gpr_or_gpr_p (dest, source)
10396 && (MEM_P (source) ^ MEM_P (dest)));
10398 if (MEM_P (source))
10400 gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);
10401 rs6000_emit_le_vsx_load (dest, source, mode);
10405 if (!REG_P (source))
10406 source = force_reg (mode, source);
10407 rs6000_emit_le_vsx_store (dest, source, mode);
10411 /* Return whether a SFmode or SImode move can be done without converting one
10412 mode to another. This arrises when we have:
10414 (SUBREG:SF (REG:SI ...))
10415 (SUBREG:SI (REG:SF ...))
10417 and one of the values is in a floating point/vector register, where SFmode
10418 scalars are stored in DFmode format. */
10421 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
10423 if (TARGET_ALLOW_SF_SUBREG)
10426 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
10429 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
10432 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
10433 if (SUBREG_P (dest))
10435 rtx dest_subreg = SUBREG_REG (dest);
10436 rtx src_subreg = SUBREG_REG (src);
10437 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
10444 /* Helper function to change moves with:
10446 (SUBREG:SF (REG:SI)) and
10447 (SUBREG:SI (REG:SF))
10449 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
10450 values are stored as DFmode values in the VSX registers. We need to convert
10451 the bits before we can use a direct move or operate on the bits in the
10452 vector register as an integer type.
10454 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
10457 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
10459 if (TARGET_DIRECT_MOVE_64BIT && !lra_in_progress && !reload_completed
10460 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
10461 && SUBREG_P (source) && sf_subreg_operand (source, mode))
10463 rtx inner_source = SUBREG_REG (source);
10464 machine_mode inner_mode = GET_MODE (inner_source);
10466 if (mode == SImode && inner_mode == SFmode)
10468 emit_insn (gen_movsi_from_sf (dest, inner_source));
10472 if (mode == SFmode && inner_mode == SImode)
10474 emit_insn (gen_movsf_from_si (dest, inner_source));
10482 /* Emit a move from SOURCE to DEST in mode MODE. */
10484 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
10487 operands[0] = dest;
10488 operands[1] = source;
10490 if (TARGET_DEBUG_ADDR)
10493 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
10494 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
10495 GET_MODE_NAME (mode),
10498 can_create_pseudo_p ());
10500 fprintf (stderr, "source:\n");
10501 debug_rtx (source);
10504 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
10505 if (CONST_WIDE_INT_P (operands[1])
10506 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10508 /* This should be fixed with the introduction of CONST_WIDE_INT. */
10509 gcc_unreachable ();
10512 #ifdef HAVE_AS_GNU_ATTRIBUTE
10513 /* If we use a long double type, set the flags in .gnu_attribute that say
10514 what the long double type is. This is to allow the linker's warning
10515 message for the wrong long double to be useful, even if the function does
10516 not do a call (for example, doing a 128-bit add on power9 if the long
10517 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
10518 used if they aren't the default long dobule type. */
10519 if (rs6000_gnu_attr && (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT))
10521 if (TARGET_LONG_DOUBLE_128 && (mode == TFmode || mode == TCmode))
10522 rs6000_passes_float = rs6000_passes_long_double = true;
10524 else if (!TARGET_LONG_DOUBLE_128 && (mode == DFmode || mode == DCmode))
10525 rs6000_passes_float = rs6000_passes_long_double = true;
10529 /* See if we need to special case SImode/SFmode SUBREG moves. */
10530 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
10531 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
10534 /* Check if GCC is setting up a block move that will end up using FP
10535 registers as temporaries. We must make sure this is acceptable. */
10536 if (GET_CODE (operands[0]) == MEM
10537 && GET_CODE (operands[1]) == MEM
10539 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
10540 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
10541 && ! (rs6000_slow_unaligned_access (SImode,
10542 (MEM_ALIGN (operands[0]) > 32
10543 ? 32 : MEM_ALIGN (operands[0])))
10544 || rs6000_slow_unaligned_access (SImode,
10545 (MEM_ALIGN (operands[1]) > 32
10546 ? 32 : MEM_ALIGN (operands[1]))))
10547 && ! MEM_VOLATILE_P (operands [0])
10548 && ! MEM_VOLATILE_P (operands [1]))
10550 emit_move_insn (adjust_address (operands[0], SImode, 0),
10551 adjust_address (operands[1], SImode, 0));
10552 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
10553 adjust_address (copy_rtx (operands[1]), SImode, 4));
10557 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
10558 && !gpc_reg_operand (operands[1], mode))
10559 operands[1] = force_reg (mode, operands[1]);
10561 /* Recognize the case where operand[1] is a reference to thread-local
10562 data and load its address to a register. */
10563 if (tls_referenced_p (operands[1]))
10565 enum tls_model model;
10566 rtx tmp = operands[1];
10569 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
10571 addend = XEXP (XEXP (tmp, 0), 1);
10572 tmp = XEXP (XEXP (tmp, 0), 0);
10575 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
10576 model = SYMBOL_REF_TLS_MODEL (tmp);
10577 gcc_assert (model != 0);
10579 tmp = rs6000_legitimize_tls_address (tmp, model);
10582 tmp = gen_rtx_PLUS (mode, tmp, addend);
10583 tmp = force_operand (tmp, operands[0]);
10588 /* 128-bit constant floating-point values on Darwin should really be loaded
10589 as two parts. However, this premature splitting is a problem when DFmode
10590 values can go into Altivec registers. */
10591 if (FLOAT128_IBM_P (mode) && !reg_addr[DFmode].scalar_in_vmx_p
10592 && GET_CODE (operands[1]) == CONST_DOUBLE)
10594 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
10595 simplify_gen_subreg (DFmode, operands[1], mode, 0),
10597 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
10598 GET_MODE_SIZE (DFmode)),
10599 simplify_gen_subreg (DFmode, operands[1], mode,
10600 GET_MODE_SIZE (DFmode)),
10605 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
10606 p1:SD) if p1 is not of floating point class and p0 is spilled as
10607 we can have no analogous movsd_store for this. */
10608 if (lra_in_progress && mode == DDmode
10609 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10610 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10611 && GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))
10612 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
10615 int regno = REGNO (SUBREG_REG (operands[1]));
10617 if (regno >= FIRST_PSEUDO_REGISTER)
10619 cl = reg_preferred_class (regno);
10620 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
10622 if (regno >= 0 && ! FP_REGNO_P (regno))
10625 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
10626 operands[1] = SUBREG_REG (operands[1]);
10629 if (lra_in_progress
10631 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10632 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10633 && (REG_P (operands[1])
10634 || (GET_CODE (operands[1]) == SUBREG
10635 && REG_P (SUBREG_REG (operands[1])))))
10637 int regno = REGNO (GET_CODE (operands[1]) == SUBREG
10638 ? SUBREG_REG (operands[1]) : operands[1]);
10641 if (regno >= FIRST_PSEUDO_REGISTER)
10643 cl = reg_preferred_class (regno);
10644 gcc_assert (cl != NO_REGS);
10645 regno = ira_class_hard_regs[cl][0];
10647 if (FP_REGNO_P (regno))
10649 if (GET_MODE (operands[0]) != DDmode)
10650 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
10651 emit_insn (gen_movsd_store (operands[0], operands[1]));
10653 else if (INT_REGNO_P (regno))
10654 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10659 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10660 p:DD)) if p0 is not of floating point class and p1 is spilled as
10661 we can have no analogous movsd_load for this. */
10662 if (lra_in_progress && mode == DDmode
10663 && GET_CODE (operands[0]) == SUBREG && REG_P (SUBREG_REG (operands[0]))
10664 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
10665 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10666 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10669 int regno = REGNO (SUBREG_REG (operands[0]));
10671 if (regno >= FIRST_PSEUDO_REGISTER)
10673 cl = reg_preferred_class (regno);
10674 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
10676 if (regno >= 0 && ! FP_REGNO_P (regno))
10679 operands[0] = SUBREG_REG (operands[0]);
10680 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
10683 if (lra_in_progress
10685 && (REG_P (operands[0])
10686 || (GET_CODE (operands[0]) == SUBREG
10687 && REG_P (SUBREG_REG (operands[0]))))
10688 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10689 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10691 int regno = REGNO (GET_CODE (operands[0]) == SUBREG
10692 ? SUBREG_REG (operands[0]) : operands[0]);
10695 if (regno >= FIRST_PSEUDO_REGISTER)
10697 cl = reg_preferred_class (regno);
10698 gcc_assert (cl != NO_REGS);
10699 regno = ira_class_hard_regs[cl][0];
10701 if (FP_REGNO_P (regno))
10703 if (GET_MODE (operands[1]) != DDmode)
10704 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
10705 emit_insn (gen_movsd_load (operands[0], operands[1]));
10707 else if (INT_REGNO_P (regno))
10708 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10714 /* FIXME: In the long term, this switch statement should go away
10715 and be replaced by a sequence of tests based on things like
10721 if (CONSTANT_P (operands[1])
10722 && GET_CODE (operands[1]) != CONST_INT)
10723 operands[1] = force_const_mem (mode, operands[1]);
10730 if (FLOAT128_2REG_P (mode))
10731 rs6000_eliminate_indexed_memrefs (operands);
10738 if (CONSTANT_P (operands[1])
10739 && ! easy_fp_constant (operands[1], mode))
10740 operands[1] = force_const_mem (mode, operands[1]);
10752 if (CONSTANT_P (operands[1])
10753 && !easy_vector_constant (operands[1], mode))
10754 operands[1] = force_const_mem (mode, operands[1]);
10759 /* Use default pattern for address of ELF small data */
10762 && DEFAULT_ABI == ABI_V4
10763 && (GET_CODE (operands[1]) == SYMBOL_REF
10764 || GET_CODE (operands[1]) == CONST)
10765 && small_data_operand (operands[1], mode))
10767 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10771 if (DEFAULT_ABI == ABI_V4
10772 && mode == Pmode && mode == SImode
10773 && flag_pic == 1 && got_operand (operands[1], mode))
10775 emit_insn (gen_movsi_got (operands[0], operands[1]));
10779 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
10783 && CONSTANT_P (operands[1])
10784 && GET_CODE (operands[1]) != HIGH
10785 && GET_CODE (operands[1]) != CONST_INT)
10787 rtx target = (!can_create_pseudo_p ()
10789 : gen_reg_rtx (mode));
10791 /* If this is a function address on -mcall-aixdesc,
10792 convert it to the address of the descriptor. */
10793 if (DEFAULT_ABI == ABI_AIX
10794 && GET_CODE (operands[1]) == SYMBOL_REF
10795 && XSTR (operands[1], 0)[0] == '.')
10797 const char *name = XSTR (operands[1], 0);
10799 while (*name == '.')
10801 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
10802 CONSTANT_POOL_ADDRESS_P (new_ref)
10803 = CONSTANT_POOL_ADDRESS_P (operands[1]);
10804 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
10805 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
10806 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
10807 operands[1] = new_ref;
10810 if (DEFAULT_ABI == ABI_DARWIN)
10813 if (MACHO_DYNAMIC_NO_PIC_P)
10815 /* Take care of any required data indirection. */
10816 operands[1] = rs6000_machopic_legitimize_pic_address (
10817 operands[1], mode, operands[0]);
10818 if (operands[0] != operands[1])
10819 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10823 emit_insn (gen_macho_high (target, operands[1]));
10824 emit_insn (gen_macho_low (operands[0], target, operands[1]));
10828 emit_insn (gen_elf_high (target, operands[1]));
10829 emit_insn (gen_elf_low (operands[0], target, operands[1]));
10833 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10834 and we have put it in the TOC, we just need to make a TOC-relative
10835 reference to it. */
10837 && GET_CODE (operands[1]) == SYMBOL_REF
10838 && use_toc_relative_ref (operands[1], mode))
10839 operands[1] = create_TOC_reference (operands[1], operands[0]);
10840 else if (mode == Pmode
10841 && CONSTANT_P (operands[1])
10842 && GET_CODE (operands[1]) != HIGH
10843 && ((GET_CODE (operands[1]) != CONST_INT
10844 && ! easy_fp_constant (operands[1], mode))
10845 || (GET_CODE (operands[1]) == CONST_INT
10846 && (num_insns_constant (operands[1], mode)
10847 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
10848 || (GET_CODE (operands[0]) == REG
10849 && FP_REGNO_P (REGNO (operands[0]))))
10850 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
10851 && (TARGET_CMODEL == CMODEL_SMALL
10852 || can_create_pseudo_p ()
10853 || (REG_P (operands[0])
10854 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
10858 /* Darwin uses a special PIC legitimizer. */
10859 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
10862 rs6000_machopic_legitimize_pic_address (operands[1], mode,
10864 if (operands[0] != operands[1])
10865 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10870 /* If we are to limit the number of things we put in the TOC and
10871 this is a symbol plus a constant we can add in one insn,
10872 just put the symbol in the TOC and add the constant. */
10873 if (GET_CODE (operands[1]) == CONST
10874 && TARGET_NO_SUM_IN_TOC
10875 && GET_CODE (XEXP (operands[1], 0)) == PLUS
10876 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
10877 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
10878 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
10879 && ! side_effects_p (operands[0]))
10882 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
10883 rtx other = XEXP (XEXP (operands[1], 0), 1);
10885 sym = force_reg (mode, sym);
10886 emit_insn (gen_add3_insn (operands[0], sym, other));
10890 operands[1] = force_const_mem (mode, operands[1]);
10893 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10894 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
10896 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
10898 operands[1] = gen_const_mem (mode, tocref);
10899 set_mem_alias_set (operands[1], get_TOC_alias_set ());
10905 if (!VECTOR_MEM_VSX_P (TImode))
10906 rs6000_eliminate_indexed_memrefs (operands);
10910 rs6000_eliminate_indexed_memrefs (operands);
10914 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10917 /* Above, we may have called force_const_mem which may have returned
10918 an invalid address. If we can, fix this up; otherwise, reload will
10919 have to deal with it. */
10920 if (GET_CODE (operands[1]) == MEM)
10921 operands[1] = validize_mem (operands[1]);
10923 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10926 /* Nonzero if we can use a floating-point register to pass this arg. */
10927 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10928 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10929 && (CUM)->fregno <= FP_ARG_MAX_REG \
10930 && TARGET_HARD_FLOAT)
10932 /* Nonzero if we can use an AltiVec register to pass this arg. */
10933 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10934 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10935 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10936 && TARGET_ALTIVEC_ABI \
10939 /* Walk down the type tree of TYPE counting consecutive base elements.
10940 If *MODEP is VOIDmode, then set it to the first valid floating point
10941 or vector type. If a non-floating point or vector type is found, or
10942 if a floating point or vector type that doesn't match a non-VOIDmode
10943 *MODEP is found, then return -1, otherwise return the count in the
10947 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10950 HOST_WIDE_INT size;
10952 switch (TREE_CODE (type))
10955 mode = TYPE_MODE (type);
10956 if (!SCALAR_FLOAT_MODE_P (mode))
10959 if (*modep == VOIDmode)
10962 if (*modep == mode)
10968 mode = TYPE_MODE (TREE_TYPE (type));
10969 if (!SCALAR_FLOAT_MODE_P (mode))
10972 if (*modep == VOIDmode)
10975 if (*modep == mode)
10981 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10984 /* Use V4SImode as representative of all 128-bit vector types. */
10985 size = int_size_in_bytes (type);
10995 if (*modep == VOIDmode)
10998 /* Vector modes are considered to be opaque: two vectors are
10999 equivalent for the purposes of being homogeneous aggregates
11000 if they are the same size. */
11001 if (*modep == mode)
11009 tree index = TYPE_DOMAIN (type);
11011 /* Can't handle incomplete types nor sizes that are not
11013 if (!COMPLETE_TYPE_P (type)
11014 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
11017 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
11020 || !TYPE_MAX_VALUE (index)
11021 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
11022 || !TYPE_MIN_VALUE (index)
11023 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
11027 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
11028 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
11030 /* There must be no padding. */
11031 if (wi::to_wide (TYPE_SIZE (type))
11032 != count * GET_MODE_BITSIZE (*modep))
11044 /* Can't handle incomplete types nor sizes that are not
11046 if (!COMPLETE_TYPE_P (type)
11047 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
11050 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
11052 if (TREE_CODE (field) != FIELD_DECL)
11055 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
11058 count += sub_count;
11061 /* There must be no padding. */
11062 if (wi::to_wide (TYPE_SIZE (type))
11063 != count * GET_MODE_BITSIZE (*modep))
11070 case QUAL_UNION_TYPE:
11072 /* These aren't very interesting except in a degenerate case. */
11077 /* Can't handle incomplete types nor sizes that are not
11079 if (!COMPLETE_TYPE_P (type)
11080 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
11083 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
11085 if (TREE_CODE (field) != FIELD_DECL)
11088 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
11091 count = count > sub_count ? count : sub_count;
11094 /* There must be no padding. */
11095 if (wi::to_wide (TYPE_SIZE (type))
11096 != count * GET_MODE_BITSIZE (*modep))
11109 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
11110 float or vector aggregate that shall be passed in FP/vector registers
11111 according to the ELFv2 ABI, return the homogeneous element mode in
11112 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
11114 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
11117 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
11118 machine_mode *elt_mode,
11121 /* Note that we do not accept complex types at the top level as
11122 homogeneous aggregates; these types are handled via the
11123 targetm.calls.split_complex_arg mechanism. Complex types
11124 can be elements of homogeneous aggregates, however. */
11125 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
11126 && AGGREGATE_TYPE_P (type))
11128 machine_mode field_mode = VOIDmode;
11129 int field_count = rs6000_aggregate_candidate (type, &field_mode);
11131 if (field_count > 0)
11133 int n_regs = (SCALAR_FLOAT_MODE_P (field_mode) ?
11134 (GET_MODE_SIZE (field_mode) + 7) >> 3 : 1);
11136 /* The ELFv2 ABI allows homogeneous aggregates to occupy
11137 up to AGGR_ARG_NUM_REG registers. */
11138 if (field_count * n_regs <= AGGR_ARG_NUM_REG)
11141 *elt_mode = field_mode;
11143 *n_elts = field_count;
11156 /* Return a nonzero value to say to return the function value in
11157 memory, just as large structures are always returned. TYPE will be
11158 the data type of the value, and FNTYPE will be the type of the
11159 function doing the returning, or @code{NULL} for libcalls.
11161 The AIX ABI for the RS/6000 specifies that all structures are
11162 returned in memory. The Darwin ABI does the same.
11164 For the Darwin 64 Bit ABI, a function result can be returned in
11165 registers or in memory, depending on the size of the return data
11166 type. If it is returned in registers, the value occupies the same
11167 registers as it would if it were the first and only function
11168 argument. Otherwise, the function places its result in memory at
11169 the location pointed to by GPR3.
11171 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
11172 but a draft put them in memory, and GCC used to implement the draft
11173 instead of the final standard. Therefore, aix_struct_return
11174 controls this instead of DEFAULT_ABI; V.4 targets needing backward
11175 compatibility can change DRAFT_V4_STRUCT_RET to override the
11176 default, and -m switches get the final word. See
11177 rs6000_option_override_internal for more details.
11179 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
11180 long double support is enabled. These values are returned in memory.
11182 int_size_in_bytes returns -1 for variable size objects, which go in
11183 memory always. The cast to unsigned makes -1 > 8. */
11186 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
11188 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
11190 && rs6000_darwin64_abi
11191 && TREE_CODE (type) == RECORD_TYPE
11192 && int_size_in_bytes (type) > 0)
11194 CUMULATIVE_ARGS valcum;
11198 valcum.fregno = FP_ARG_MIN_REG;
11199 valcum.vregno = ALTIVEC_ARG_MIN_REG;
11200 /* Do a trial code generation as if this were going to be passed
11201 as an argument; if any part goes in memory, we return NULL. */
11202 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
11205 /* Otherwise fall through to more conventional ABI rules. */
11208 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
11209 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
11213 /* The ELFv2 ABI returns aggregates up to 16B in registers */
11214 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
11215 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
11218 if (AGGREGATE_TYPE_P (type)
11219 && (aix_struct_return
11220 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
11223 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11224 modes only exist for GCC vector types if -maltivec. */
11225 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
11226 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
11229 /* Return synthetic vectors in memory. */
11230 if (TREE_CODE (type) == VECTOR_TYPE
11231 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
11233 static bool warned_for_return_big_vectors = false;
11234 if (!warned_for_return_big_vectors)
11236 warning (OPT_Wpsabi, "GCC vector returned by reference: "
11237 "non-standard ABI extension with no compatibility "
11239 warned_for_return_big_vectors = true;
11244 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
11245 && FLOAT128_IEEE_P (TYPE_MODE (type)))
11251 /* Specify whether values returned in registers should be at the most
11252 significant end of a register. We want aggregates returned by
11253 value to match the way aggregates are passed to functions. */
11256 rs6000_return_in_msb (const_tree valtype)
11258 return (DEFAULT_ABI == ABI_ELFv2
11259 && BYTES_BIG_ENDIAN
11260 && AGGREGATE_TYPE_P (valtype)
11261 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
11265 #ifdef HAVE_AS_GNU_ATTRIBUTE
11266 /* Return TRUE if a call to function FNDECL may be one that
11267 potentially affects the function calling ABI of the object file. */
11270 call_ABI_of_interest (tree fndecl)
11272 if (rs6000_gnu_attr && symtab->state == EXPANSION)
11274 struct cgraph_node *c_node;
11276 /* Libcalls are always interesting. */
11277 if (fndecl == NULL_TREE)
11280 /* Any call to an external function is interesting. */
11281 if (DECL_EXTERNAL (fndecl))
11284 /* Interesting functions that we are emitting in this object file. */
11285 c_node = cgraph_node::get (fndecl);
11286 c_node = c_node->ultimate_alias_target ();
11287 return !c_node->only_called_directly_p ();
11293 /* Initialize a variable CUM of type CUMULATIVE_ARGS
11294 for a call to a function whose data type is FNTYPE.
11295 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
11297 For incoming args we set the number of arguments in the prototype large
11298 so we never return a PARALLEL. */
11301 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
11302 rtx libname ATTRIBUTE_UNUSED, int incoming,
11303 int libcall, int n_named_args,
11304 tree fndecl ATTRIBUTE_UNUSED,
11305 machine_mode return_mode ATTRIBUTE_UNUSED)
11307 static CUMULATIVE_ARGS zero_cumulative;
11309 *cum = zero_cumulative;
11311 cum->fregno = FP_ARG_MIN_REG;
11312 cum->vregno = ALTIVEC_ARG_MIN_REG;
11313 cum->prototype = (fntype && prototype_p (fntype));
11314 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
11315 ? CALL_LIBCALL : CALL_NORMAL);
11316 cum->sysv_gregno = GP_ARG_MIN_REG;
11317 cum->stdarg = stdarg_p (fntype);
11318 cum->libcall = libcall;
11320 cum->nargs_prototype = 0;
11321 if (incoming || cum->prototype)
11322 cum->nargs_prototype = n_named_args;
11324 /* Check for a longcall attribute. */
11325 if ((!fntype && rs6000_default_long_calls)
11327 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
11328 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
11329 cum->call_cookie |= CALL_LONG;
11331 if (TARGET_DEBUG_ARG)
11333 fprintf (stderr, "\ninit_cumulative_args:");
11336 tree ret_type = TREE_TYPE (fntype);
11337 fprintf (stderr, " ret code = %s,",
11338 get_tree_code_name (TREE_CODE (ret_type)));
11341 if (cum->call_cookie & CALL_LONG)
11342 fprintf (stderr, " longcall,");
11344 fprintf (stderr, " proto = %d, nargs = %d\n",
11345 cum->prototype, cum->nargs_prototype);
11348 #ifdef HAVE_AS_GNU_ATTRIBUTE
11349 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
11351 cum->escapes = call_ABI_of_interest (fndecl);
11358 return_type = TREE_TYPE (fntype);
11359 return_mode = TYPE_MODE (return_type);
11362 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
11364 if (return_type != NULL)
11366 if (TREE_CODE (return_type) == RECORD_TYPE
11367 && TYPE_TRANSPARENT_AGGR (return_type))
11369 return_type = TREE_TYPE (first_field (return_type));
11370 return_mode = TYPE_MODE (return_type);
11372 if (AGGREGATE_TYPE_P (return_type)
11373 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
11375 rs6000_returns_struct = true;
11377 if (SCALAR_FLOAT_MODE_P (return_mode))
11379 rs6000_passes_float = true;
11380 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11381 && (FLOAT128_IBM_P (return_mode)
11382 || FLOAT128_IEEE_P (return_mode)
11383 || (return_type != NULL
11384 && (TYPE_MAIN_VARIANT (return_type)
11385 == long_double_type_node))))
11386 rs6000_passes_long_double = true;
11388 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
11389 || PAIRED_VECTOR_MODE (return_mode))
11390 rs6000_passes_vector = true;
11397 && TARGET_ALTIVEC_ABI
11398 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
11400 error ("cannot return value in vector register because"
11401 " altivec instructions are disabled, use %qs"
11402 " to enable them", "-maltivec");
11406 /* The mode the ABI uses for a word. This is not the same as word_mode
11407 for -m32 -mpowerpc64. This is used to implement various target hooks. */
11409 static scalar_int_mode
11410 rs6000_abi_word_mode (void)
11412 return TARGET_32BIT ? SImode : DImode;
11415 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
11417 rs6000_offload_options (void)
11420 return xstrdup ("-foffload-abi=lp64");
11422 return xstrdup ("-foffload-abi=ilp32");
11425 /* On rs6000, function arguments are promoted, as are function return
11428 static machine_mode
11429 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
11431 int *punsignedp ATTRIBUTE_UNUSED,
11434 PROMOTE_MODE (mode, *punsignedp, type);
11439 /* Return true if TYPE must be passed on the stack and not in registers. */
11442 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
11444 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
11445 return must_pass_in_stack_var_size (mode, type);
11447 return must_pass_in_stack_var_size_or_pad (mode, type);
11451 is_complex_IBM_long_double (machine_mode mode)
11453 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
11456 /* Whether ABI_V4 passes MODE args to a function in floating point
11460 abi_v4_pass_in_fpr (machine_mode mode)
11462 if (!TARGET_HARD_FLOAT)
11464 if (TARGET_SINGLE_FLOAT && mode == SFmode)
11466 if (TARGET_DOUBLE_FLOAT && mode == DFmode)
11468 /* ABI_V4 passes complex IBM long double in 8 gprs.
11469 Stupid, but we can't change the ABI now. */
11470 if (is_complex_IBM_long_double (mode))
11472 if (FLOAT128_2REG_P (mode))
11474 if (DECIMAL_FLOAT_MODE_P (mode))
11479 /* Implement TARGET_FUNCTION_ARG_PADDING.
11481 For the AIX ABI structs are always stored left shifted in their
11484 static pad_direction
11485 rs6000_function_arg_padding (machine_mode mode, const_tree type)
11487 #ifndef AGGREGATE_PADDING_FIXED
11488 #define AGGREGATE_PADDING_FIXED 0
11490 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
11491 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
11494 if (!AGGREGATE_PADDING_FIXED)
11496 /* GCC used to pass structures of the same size as integer types as
11497 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
11498 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
11499 passed padded downward, except that -mstrict-align further
11500 muddied the water in that multi-component structures of 2 and 4
11501 bytes in size were passed padded upward.
11503 The following arranges for best compatibility with previous
11504 versions of gcc, but removes the -mstrict-align dependency. */
11505 if (BYTES_BIG_ENDIAN)
11507 HOST_WIDE_INT size = 0;
11509 if (mode == BLKmode)
11511 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
11512 size = int_size_in_bytes (type);
11515 size = GET_MODE_SIZE (mode);
11517 if (size == 1 || size == 2 || size == 4)
11518 return PAD_DOWNWARD;
11523 if (AGGREGATES_PAD_UPWARD_ALWAYS)
11525 if (type != 0 && AGGREGATE_TYPE_P (type))
11529 /* Fall back to the default. */
11530 return default_function_arg_padding (mode, type);
11533 /* If defined, a C expression that gives the alignment boundary, in bits,
11534 of an argument with the specified mode and type. If it is not defined,
11535 PARM_BOUNDARY is used for all arguments.
11537 V.4 wants long longs and doubles to be double word aligned. Just
11538 testing the mode size is a boneheaded way to do this as it means
11539 that other types such as complex int are also double word aligned.
11540 However, we're stuck with this because changing the ABI might break
11541 existing library interfaces.
11543 Quadword align Altivec/VSX vectors.
11544 Quadword align large synthetic vector types. */
11546 static unsigned int
11547 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
11549 machine_mode elt_mode;
11552 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11554 if (DEFAULT_ABI == ABI_V4
11555 && (GET_MODE_SIZE (mode) == 8
11556 || (TARGET_HARD_FLOAT
11557 && !is_complex_IBM_long_double (mode)
11558 && FLOAT128_2REG_P (mode))))
11560 else if (FLOAT128_VECTOR_P (mode))
11562 else if (PAIRED_VECTOR_MODE (mode)
11563 || (type && TREE_CODE (type) == VECTOR_TYPE
11564 && int_size_in_bytes (type) >= 8
11565 && int_size_in_bytes (type) < 16))
11567 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11568 || (type && TREE_CODE (type) == VECTOR_TYPE
11569 && int_size_in_bytes (type) >= 16))
11572 /* Aggregate types that need > 8 byte alignment are quadword-aligned
11573 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
11574 -mcompat-align-parm is used. */
11575 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
11576 || DEFAULT_ABI == ABI_ELFv2)
11577 && type && TYPE_ALIGN (type) > 64)
11579 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
11580 or homogeneous float/vector aggregates here. We already handled
11581 vector aggregates above, but still need to check for float here. */
11582 bool aggregate_p = (AGGREGATE_TYPE_P (type)
11583 && !SCALAR_FLOAT_MODE_P (elt_mode));
11585 /* We used to check for BLKmode instead of the above aggregate type
11586 check. Warn when this results in any difference to the ABI. */
11587 if (aggregate_p != (mode == BLKmode))
11589 static bool warned;
11590 if (!warned && warn_psabi)
11593 inform (input_location,
11594 "the ABI of passing aggregates with %d-byte alignment"
11595 " has changed in GCC 5",
11596 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
11604 /* Similar for the Darwin64 ABI. Note that for historical reasons we
11605 implement the "aggregate type" check as a BLKmode check here; this
11606 means certain aggregate types are in fact not aligned. */
11607 if (TARGET_MACHO && rs6000_darwin64_abi
11609 && type && TYPE_ALIGN (type) > 64)
11612 return PARM_BOUNDARY;
11615 /* The offset in words to the start of the parameter save area. */
11617 static unsigned int
11618 rs6000_parm_offset (void)
11620 return (DEFAULT_ABI == ABI_V4 ? 2
11621 : DEFAULT_ABI == ABI_ELFv2 ? 4
11625 /* For a function parm of MODE and TYPE, return the starting word in
11626 the parameter area. NWORDS of the parameter area are already used. */
11628 static unsigned int
11629 rs6000_parm_start (machine_mode mode, const_tree type,
11630 unsigned int nwords)
11632 unsigned int align;
11634 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
11635 return nwords + (-(rs6000_parm_offset () + nwords) & align);
11638 /* Compute the size (in words) of a function argument. */
11640 static unsigned long
11641 rs6000_arg_size (machine_mode mode, const_tree type)
11643 unsigned long size;
11645 if (mode != BLKmode)
11646 size = GET_MODE_SIZE (mode);
11648 size = int_size_in_bytes (type);
11651 return (size + 3) >> 2;
11653 return (size + 7) >> 3;
11656 /* Use this to flush pending int fields. */
11659 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
11660 HOST_WIDE_INT bitpos, int final)
11662 unsigned int startbit, endbit;
11663 int intregs, intoffset;
11665 /* Handle the situations where a float is taking up the first half
11666 of the GPR, and the other half is empty (typically due to
11667 alignment restrictions). We can detect this by a 8-byte-aligned
11668 int field, or by seeing that this is the final flush for this
11669 argument. Count the word and continue on. */
11670 if (cum->floats_in_gpr == 1
11671 && (cum->intoffset % 64 == 0
11672 || (cum->intoffset == -1 && final)))
11675 cum->floats_in_gpr = 0;
11678 if (cum->intoffset == -1)
11681 intoffset = cum->intoffset;
11682 cum->intoffset = -1;
11683 cum->floats_in_gpr = 0;
11685 if (intoffset % BITS_PER_WORD != 0)
11687 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11688 if (!int_mode_for_size (bits, 0).exists ())
11690 /* We couldn't find an appropriate mode, which happens,
11691 e.g., in packed structs when there are 3 bytes to load.
11692 Back intoffset back to the beginning of the word in this
11694 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11698 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11699 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11700 intregs = (endbit - startbit) / BITS_PER_WORD;
11701 cum->words += intregs;
11702 /* words should be unsigned. */
11703 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
11705 int pad = (endbit/BITS_PER_WORD) - cum->words;
11710 /* The darwin64 ABI calls for us to recurse down through structs,
11711 looking for elements passed in registers. Unfortunately, we have
11712 to track int register count here also because of misalignments
11713 in powerpc alignment mode. */
11716 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
11718 HOST_WIDE_INT startbitpos)
11722 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11723 if (TREE_CODE (f) == FIELD_DECL)
11725 HOST_WIDE_INT bitpos = startbitpos;
11726 tree ftype = TREE_TYPE (f);
11728 if (ftype == error_mark_node)
11730 mode = TYPE_MODE (ftype);
11732 if (DECL_SIZE (f) != 0
11733 && tree_fits_uhwi_p (bit_position (f)))
11734 bitpos += int_bit_position (f);
11736 /* ??? FIXME: else assume zero offset. */
11738 if (TREE_CODE (ftype) == RECORD_TYPE)
11739 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
11740 else if (USE_FP_FOR_ARG_P (cum, mode))
11742 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
11743 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11744 cum->fregno += n_fpregs;
11745 /* Single-precision floats present a special problem for
11746 us, because they are smaller than an 8-byte GPR, and so
11747 the structure-packing rules combined with the standard
11748 varargs behavior mean that we want to pack float/float
11749 and float/int combinations into a single register's
11750 space. This is complicated by the arg advance flushing,
11751 which works on arbitrarily large groups of int-type
11753 if (mode == SFmode)
11755 if (cum->floats_in_gpr == 1)
11757 /* Two floats in a word; count the word and reset
11758 the float count. */
11760 cum->floats_in_gpr = 0;
11762 else if (bitpos % 64 == 0)
11764 /* A float at the beginning of an 8-byte word;
11765 count it and put off adjusting cum->words until
11766 we see if a arg advance flush is going to do it
11768 cum->floats_in_gpr++;
11772 /* The float is at the end of a word, preceded
11773 by integer fields, so the arg advance flush
11774 just above has already set cum->words and
11775 everything is taken care of. */
11779 cum->words += n_fpregs;
11781 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11783 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11787 else if (cum->intoffset == -1)
11788 cum->intoffset = bitpos;
11792 /* Check for an item that needs to be considered specially under the darwin 64
11793 bit ABI. These are record types where the mode is BLK or the structure is
11794 8 bytes in size. */
11796 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
11798 return rs6000_darwin64_abi
11799 && ((mode == BLKmode
11800 && TREE_CODE (type) == RECORD_TYPE
11801 && int_size_in_bytes (type) > 0)
11802 || (type && TREE_CODE (type) == RECORD_TYPE
11803 && int_size_in_bytes (type) == 8)) ? 1 : 0;
11806 /* Update the data in CUM to advance over an argument
11807 of mode MODE and data type TYPE.
11808 (TYPE is null for libcalls where that information may not be available.)
11810 Note that for args passed by reference, function_arg will be called
11811 with MODE and TYPE set to that of the pointer to the arg, not the arg
11815 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
11816 const_tree type, bool named, int depth)
11818 machine_mode elt_mode;
11821 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11823 /* Only tick off an argument if we're not recursing. */
11825 cum->nargs_prototype--;
11827 #ifdef HAVE_AS_GNU_ATTRIBUTE
11828 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
11831 if (SCALAR_FLOAT_MODE_P (mode))
11833 rs6000_passes_float = true;
11834 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11835 && (FLOAT128_IBM_P (mode)
11836 || FLOAT128_IEEE_P (mode)
11838 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
11839 rs6000_passes_long_double = true;
11841 if ((named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
11842 || (PAIRED_VECTOR_MODE (mode)
11844 && cum->sysv_gregno <= GP_ARG_MAX_REG))
11845 rs6000_passes_vector = true;
11849 if (TARGET_ALTIVEC_ABI
11850 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11851 || (type && TREE_CODE (type) == VECTOR_TYPE
11852 && int_size_in_bytes (type) == 16)))
11854 bool stack = false;
11856 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11858 cum->vregno += n_elts;
11860 if (!TARGET_ALTIVEC)
11861 error ("cannot pass argument in vector register because"
11862 " altivec instructions are disabled, use %qs"
11863 " to enable them", "-maltivec");
11865 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11866 even if it is going to be passed in a vector register.
11867 Darwin does the same for variable-argument functions. */
11868 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11870 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
11880 /* Vector parameters must be 16-byte aligned. In 32-bit
11881 mode this means we need to take into account the offset
11882 to the parameter save area. In 64-bit mode, they just
11883 have to start on an even word, since the parameter save
11884 area is 16-byte aligned. */
11886 align = -(rs6000_parm_offset () + cum->words) & 3;
11888 align = cum->words & 1;
11889 cum->words += align + rs6000_arg_size (mode, type);
11891 if (TARGET_DEBUG_ARG)
11893 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11894 cum->words, align);
11895 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11896 cum->nargs_prototype, cum->prototype,
11897 GET_MODE_NAME (mode));
11901 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11903 int size = int_size_in_bytes (type);
11904 /* Variable sized types have size == -1 and are
11905 treated as if consisting entirely of ints.
11906 Pad to 16 byte boundary if needed. */
11907 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11908 && (cum->words % 2) != 0)
11910 /* For varargs, we can just go up by the size of the struct. */
11912 cum->words += (size + 7) / 8;
11915 /* It is tempting to say int register count just goes up by
11916 sizeof(type)/8, but this is wrong in a case such as
11917 { int; double; int; } [powerpc alignment]. We have to
11918 grovel through the fields for these too. */
11919 cum->intoffset = 0;
11920 cum->floats_in_gpr = 0;
11921 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11922 rs6000_darwin64_record_arg_advance_flush (cum,
11923 size * BITS_PER_UNIT, 1);
11925 if (TARGET_DEBUG_ARG)
11927 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11928 cum->words, TYPE_ALIGN (type), size);
11930 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11931 cum->nargs_prototype, cum->prototype,
11932 GET_MODE_NAME (mode));
11935 else if (DEFAULT_ABI == ABI_V4)
11937 if (abi_v4_pass_in_fpr (mode))
11939 /* _Decimal128 must use an even/odd register pair. This assumes
11940 that the register number is odd when fregno is odd. */
11941 if (mode == TDmode && (cum->fregno % 2) == 1)
11944 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11945 <= FP_ARG_V4_MAX_REG)
11946 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11949 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11950 if (mode == DFmode || FLOAT128_IBM_P (mode)
11951 || mode == DDmode || mode == TDmode)
11952 cum->words += cum->words & 1;
11953 cum->words += rs6000_arg_size (mode, type);
11958 int n_words = rs6000_arg_size (mode, type);
11959 int gregno = cum->sysv_gregno;
11961 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11962 As does any other 2 word item such as complex int due to a
11963 historical mistake. */
11965 gregno += (1 - gregno) & 1;
11967 /* Multi-reg args are not split between registers and stack. */
11968 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11970 /* Long long is aligned on the stack. So are other 2 word
11971 items such as complex int due to a historical mistake. */
11973 cum->words += cum->words & 1;
11974 cum->words += n_words;
11977 /* Note: continuing to accumulate gregno past when we've started
11978 spilling to the stack indicates the fact that we've started
11979 spilling to the stack to expand_builtin_saveregs. */
11980 cum->sysv_gregno = gregno + n_words;
11983 if (TARGET_DEBUG_ARG)
11985 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11986 cum->words, cum->fregno);
11987 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11988 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11989 fprintf (stderr, "mode = %4s, named = %d\n",
11990 GET_MODE_NAME (mode), named);
11995 int n_words = rs6000_arg_size (mode, type);
11996 int start_words = cum->words;
11997 int align_words = rs6000_parm_start (mode, type, start_words);
11999 cum->words = align_words + n_words;
12001 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
12003 /* _Decimal128 must be passed in an even/odd float register pair.
12004 This assumes that the register number is odd when fregno is
12006 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
12008 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
12011 if (TARGET_DEBUG_ARG)
12013 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
12014 cum->words, cum->fregno);
12015 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
12016 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
12017 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
12018 named, align_words - start_words, depth);
12024 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
12025 const_tree type, bool named)
12027 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
12031 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
12032 structure between cum->intoffset and bitpos to integer registers. */
12035 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
12036 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
12039 unsigned int regno;
12040 unsigned int startbit, endbit;
12041 int this_regno, intregs, intoffset;
12044 if (cum->intoffset == -1)
12047 intoffset = cum->intoffset;
12048 cum->intoffset = -1;
12050 /* If this is the trailing part of a word, try to only load that
12051 much into the register. Otherwise load the whole register. Note
12052 that in the latter case we may pick up unwanted bits. It's not a
12053 problem at the moment but may wish to revisit. */
12055 if (intoffset % BITS_PER_WORD != 0)
12057 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
12058 if (!int_mode_for_size (bits, 0).exists (&mode))
12060 /* We couldn't find an appropriate mode, which happens,
12061 e.g., in packed structs when there are 3 bytes to load.
12062 Back intoffset back to the beginning of the word in this
12064 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
12071 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
12072 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
12073 intregs = (endbit - startbit) / BITS_PER_WORD;
12074 this_regno = cum->words + intoffset / BITS_PER_WORD;
12076 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
12077 cum->use_stack = 1;
12079 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
12083 intoffset /= BITS_PER_UNIT;
12086 regno = GP_ARG_MIN_REG + this_regno;
12087 reg = gen_rtx_REG (mode, regno);
12089 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
12092 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
12096 while (intregs > 0);
12099 /* Recursive workhorse for the following. */
12102 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
12103 HOST_WIDE_INT startbitpos, rtx rvec[],
12108 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
12109 if (TREE_CODE (f) == FIELD_DECL)
12111 HOST_WIDE_INT bitpos = startbitpos;
12112 tree ftype = TREE_TYPE (f);
12114 if (ftype == error_mark_node)
12116 mode = TYPE_MODE (ftype);
12118 if (DECL_SIZE (f) != 0
12119 && tree_fits_uhwi_p (bit_position (f)))
12120 bitpos += int_bit_position (f);
12122 /* ??? FIXME: else assume zero offset. */
12124 if (TREE_CODE (ftype) == RECORD_TYPE)
12125 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
12126 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
12128 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
12132 case E_SCmode: mode = SFmode; break;
12133 case E_DCmode: mode = DFmode; break;
12134 case E_TCmode: mode = TFmode; break;
12138 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
12139 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
12141 gcc_assert (cum->fregno == FP_ARG_MAX_REG
12142 && (mode == TFmode || mode == TDmode));
12143 /* Long double or _Decimal128 split over regs and memory. */
12144 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
12148 = gen_rtx_EXPR_LIST (VOIDmode,
12149 gen_rtx_REG (mode, cum->fregno++),
12150 GEN_INT (bitpos / BITS_PER_UNIT));
12151 if (FLOAT128_2REG_P (mode))
12154 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
12156 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
12158 = gen_rtx_EXPR_LIST (VOIDmode,
12159 gen_rtx_REG (mode, cum->vregno++),
12160 GEN_INT (bitpos / BITS_PER_UNIT));
12162 else if (cum->intoffset == -1)
12163 cum->intoffset = bitpos;
12167 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
12168 the register(s) to be used for each field and subfield of a struct
12169 being passed by value, along with the offset of where the
12170 register's value may be found in the block. FP fields go in FP
12171 register, vector fields go in vector registers, and everything
12172 else goes in int registers, packed as in memory.
12174 This code is also used for function return values. RETVAL indicates
12175 whether this is the case.
12177 Much of this is taken from the SPARC V9 port, which has a similar
12178 calling convention. */
12181 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
12182 bool named, bool retval)
12184 rtx rvec[FIRST_PSEUDO_REGISTER];
12185 int k = 1, kbase = 1;
12186 HOST_WIDE_INT typesize = int_size_in_bytes (type);
12187 /* This is a copy; modifications are not visible to our caller. */
12188 CUMULATIVE_ARGS copy_cum = *orig_cum;
12189 CUMULATIVE_ARGS *cum = ©_cum;
12191 /* Pad to 16 byte boundary if needed. */
12192 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
12193 && (cum->words % 2) != 0)
12196 cum->intoffset = 0;
12197 cum->use_stack = 0;
12198 cum->named = named;
12200 /* Put entries into rvec[] for individual FP and vector fields, and
12201 for the chunks of memory that go in int regs. Note we start at
12202 element 1; 0 is reserved for an indication of using memory, and
12203 may or may not be filled in below. */
12204 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
12205 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
12207 /* If any part of the struct went on the stack put all of it there.
12208 This hack is because the generic code for
12209 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
12210 parts of the struct are not at the beginning. */
12211 if (cum->use_stack)
12214 return NULL_RTX; /* doesn't go in registers at all */
12216 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12218 if (k > 1 || cum->use_stack)
12219 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
12224 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
12227 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
12232 rtx rvec[GP_ARG_NUM_REG + 1];
12234 if (align_words >= GP_ARG_NUM_REG)
12237 n_units = rs6000_arg_size (mode, type);
12239 /* Optimize the simple case where the arg fits in one gpr, except in
12240 the case of BLKmode due to assign_parms assuming that registers are
12241 BITS_PER_WORD wide. */
12243 || (n_units == 1 && mode != BLKmode))
12244 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12247 if (align_words + n_units > GP_ARG_NUM_REG)
12248 /* Not all of the arg fits in gprs. Say that it goes in memory too,
12249 using a magic NULL_RTX component.
12250 This is not strictly correct. Only some of the arg belongs in
12251 memory, not all of it. However, the normal scheme using
12252 function_arg_partial_nregs can result in unusual subregs, eg.
12253 (subreg:SI (reg:DF) 4), which are not handled well. The code to
12254 store the whole arg to memory is often more efficient than code
12255 to store pieces, and we know that space is available in the right
12256 place for the whole arg. */
12257 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12262 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
12263 rtx off = GEN_INT (i++ * 4);
12264 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12266 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
12268 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12271 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
12272 but must also be copied into the parameter save area starting at
12273 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
12274 to the GPRs and/or memory. Return the number of elements used. */
12277 rs6000_psave_function_arg (machine_mode mode, const_tree type,
12278 int align_words, rtx *rvec)
12282 if (align_words < GP_ARG_NUM_REG)
12284 int n_words = rs6000_arg_size (mode, type);
12286 if (align_words + n_words > GP_ARG_NUM_REG
12288 || (TARGET_32BIT && TARGET_POWERPC64))
12290 /* If this is partially on the stack, then we only
12291 include the portion actually in registers here. */
12292 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12295 if (align_words + n_words > GP_ARG_NUM_REG)
12297 /* Not all of the arg fits in gprs. Say that it goes in memory
12298 too, using a magic NULL_RTX component. Also see comment in
12299 rs6000_mixed_function_arg for why the normal
12300 function_arg_partial_nregs scheme doesn't work in this case. */
12301 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12306 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12307 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
12308 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12310 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12314 /* The whole arg fits in gprs. */
12315 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12316 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
12321 /* It's entirely in memory. */
12322 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12328 /* RVEC is a vector of K components of an argument of mode MODE.
12329 Construct the final function_arg return value from it. */
12332 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
12334 gcc_assert (k >= 1);
12336 /* Avoid returning a PARALLEL in the trivial cases. */
12339 if (XEXP (rvec[0], 0) == NULL_RTX)
12342 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
12343 return XEXP (rvec[0], 0);
12346 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12349 /* Determine where to put an argument to a function.
12350 Value is zero to push the argument on the stack,
12351 or a hard register in which to store the argument.
12353 MODE is the argument's machine mode.
12354 TYPE is the data type of the argument (as a tree).
12355 This is null for libcalls where that information may
12357 CUM is a variable of type CUMULATIVE_ARGS which gives info about
12358 the preceding args and about the function being called. It is
12359 not modified in this routine.
12360 NAMED is nonzero if this argument is a named parameter
12361 (otherwise it is an extra parameter matching an ellipsis).
12363 On RS/6000 the first eight words of non-FP are normally in registers
12364 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
12365 Under V.4, the first 8 FP args are in registers.
12367 If this is floating-point and no prototype is specified, we use
12368 both an FP and integer register (or possibly FP reg and stack). Library
12369 functions (when CALL_LIBCALL is set) always have the proper types for args,
12370 so we can pass the FP value just in one register. emit_library_function
12371 doesn't support PARALLEL anyway.
12373 Note that for args passed by reference, function_arg will be called
12374 with MODE and TYPE set to that of the pointer to the arg, not the arg
12378 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
12379 const_tree type, bool named)
12381 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12382 enum rs6000_abi abi = DEFAULT_ABI;
12383 machine_mode elt_mode;
12386 /* Return a marker to indicate whether CR1 needs to set or clear the
12387 bit that V.4 uses to say fp args were passed in registers.
12388 Assume that we don't need the marker for software floating point,
12389 or compiler generated library calls. */
12390 if (mode == VOIDmode)
12393 && (cum->call_cookie & CALL_LIBCALL) == 0
12395 || (cum->nargs_prototype < 0
12396 && (cum->prototype || TARGET_NO_PROTOTYPE)))
12397 && TARGET_HARD_FLOAT)
12398 return GEN_INT (cum->call_cookie
12399 | ((cum->fregno == FP_ARG_MIN_REG)
12400 ? CALL_V4_SET_FP_ARGS
12401 : CALL_V4_CLEAR_FP_ARGS));
12403 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
12406 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12408 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12410 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
12411 if (rslt != NULL_RTX)
12413 /* Else fall through to usual handling. */
12416 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12418 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12422 /* Do we also need to pass this argument in the parameter save area?
12423 Library support functions for IEEE 128-bit are assumed to not need the
12424 value passed both in GPRs and in vector registers. */
12425 if (TARGET_64BIT && !cum->prototype
12426 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12428 int align_words = ROUND_UP (cum->words, 2);
12429 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12432 /* Describe where this argument goes in the vector registers. */
12433 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
12435 r = gen_rtx_REG (elt_mode, cum->vregno + i);
12436 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12437 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12440 return rs6000_finish_function_arg (mode, rvec, k);
12442 else if (TARGET_ALTIVEC_ABI
12443 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
12444 || (type && TREE_CODE (type) == VECTOR_TYPE
12445 && int_size_in_bytes (type) == 16)))
12447 if (named || abi == ABI_V4)
12451 /* Vector parameters to varargs functions under AIX or Darwin
12452 get passed in memory and possibly also in GPRs. */
12453 int align, align_words, n_words;
12454 machine_mode part_mode;
12456 /* Vector parameters must be 16-byte aligned. In 32-bit
12457 mode this means we need to take into account the offset
12458 to the parameter save area. In 64-bit mode, they just
12459 have to start on an even word, since the parameter save
12460 area is 16-byte aligned. */
12462 align = -(rs6000_parm_offset () + cum->words) & 3;
12464 align = cum->words & 1;
12465 align_words = cum->words + align;
12467 /* Out of registers? Memory, then. */
12468 if (align_words >= GP_ARG_NUM_REG)
12471 if (TARGET_32BIT && TARGET_POWERPC64)
12472 return rs6000_mixed_function_arg (mode, type, align_words);
12474 /* The vector value goes in GPRs. Only the part of the
12475 value in GPRs is reported here. */
12477 n_words = rs6000_arg_size (mode, type);
12478 if (align_words + n_words > GP_ARG_NUM_REG)
12479 /* Fortunately, there are only two possibilities, the value
12480 is either wholly in GPRs or half in GPRs and half not. */
12481 part_mode = DImode;
12483 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
12487 else if (abi == ABI_V4)
12489 if (abi_v4_pass_in_fpr (mode))
12491 /* _Decimal128 must use an even/odd register pair. This assumes
12492 that the register number is odd when fregno is odd. */
12493 if (mode == TDmode && (cum->fregno % 2) == 1)
12496 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
12497 <= FP_ARG_V4_MAX_REG)
12498 return gen_rtx_REG (mode, cum->fregno);
12504 int n_words = rs6000_arg_size (mode, type);
12505 int gregno = cum->sysv_gregno;
12507 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
12508 As does any other 2 word item such as complex int due to a
12509 historical mistake. */
12511 gregno += (1 - gregno) & 1;
12513 /* Multi-reg args are not split between registers and stack. */
12514 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
12517 if (TARGET_32BIT && TARGET_POWERPC64)
12518 return rs6000_mixed_function_arg (mode, type,
12519 gregno - GP_ARG_MIN_REG);
12520 return gen_rtx_REG (mode, gregno);
12525 int align_words = rs6000_parm_start (mode, type, cum->words);
12527 /* _Decimal128 must be passed in an even/odd float register pair.
12528 This assumes that the register number is odd when fregno is odd. */
12529 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
12532 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12534 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12537 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12540 /* Do we also need to pass this argument in the parameter
12542 if (type && (cum->nargs_prototype <= 0
12543 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12544 && TARGET_XL_COMPAT
12545 && align_words >= GP_ARG_NUM_REG)))
12546 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12548 /* Describe where this argument goes in the fprs. */
12549 for (i = 0; i < n_elts
12550 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
12552 /* Check if the argument is split over registers and memory.
12553 This can only ever happen for long double or _Decimal128;
12554 complex types are handled via split_complex_arg. */
12555 machine_mode fmode = elt_mode;
12556 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
12558 gcc_assert (FLOAT128_2REG_P (fmode));
12559 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
12562 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
12563 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12564 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12567 /* If there were not enough FPRs to hold the argument, the rest
12568 usually goes into memory. However, if the current position
12569 is still within the register parameter area, a portion may
12570 actually have to go into GPRs.
12572 Note that it may happen that the portion of the argument
12573 passed in the first "half" of the first GPR was already
12574 passed in the last FPR as well.
12576 For unnamed arguments, we already set up GPRs to cover the
12577 whole argument in rs6000_psave_function_arg, so there is
12578 nothing further to do at this point. */
12579 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
12580 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
12581 && cum->nargs_prototype > 0)
12583 static bool warned;
12585 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12586 int n_words = rs6000_arg_size (mode, type);
12588 align_words += fpr_words;
12589 n_words -= fpr_words;
12593 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12594 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
12595 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12597 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12599 if (!warned && warn_psabi)
12602 inform (input_location,
12603 "the ABI of passing homogeneous float aggregates"
12604 " has changed in GCC 5");
12608 return rs6000_finish_function_arg (mode, rvec, k);
12610 else if (align_words < GP_ARG_NUM_REG)
12612 if (TARGET_32BIT && TARGET_POWERPC64)
12613 return rs6000_mixed_function_arg (mode, type, align_words);
12615 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12622 /* For an arg passed partly in registers and partly in memory, this is
12623 the number of bytes passed in registers. For args passed entirely in
12624 registers or entirely in memory, zero. When an arg is described by a
12625 PARALLEL, perhaps using more than one register type, this function
12626 returns the number of bytes used by the first element of the PARALLEL. */
12629 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
12630 tree type, bool named)
12632 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12633 bool passed_in_gprs = true;
12636 machine_mode elt_mode;
12639 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12641 if (DEFAULT_ABI == ABI_V4)
12644 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12646 /* If we are passing this arg in the fixed parameter save area (gprs or
12647 memory) as well as VRs, we do not use the partial bytes mechanism;
12648 instead, rs6000_function_arg will return a PARALLEL including a memory
12649 element as necessary. Library support functions for IEEE 128-bit are
12650 assumed to not need the value passed both in GPRs and in vector
12652 if (TARGET_64BIT && !cum->prototype
12653 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12656 /* Otherwise, we pass in VRs only. Check for partial copies. */
12657 passed_in_gprs = false;
12658 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
12659 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
12662 /* In this complicated case we just disable the partial_nregs code. */
12663 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12666 align_words = rs6000_parm_start (mode, type, cum->words);
12668 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12670 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12672 /* If we are passing this arg in the fixed parameter save area
12673 (gprs or memory) as well as FPRs, we do not use the partial
12674 bytes mechanism; instead, rs6000_function_arg will return a
12675 PARALLEL including a memory element as necessary. */
12677 && (cum->nargs_prototype <= 0
12678 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12679 && TARGET_XL_COMPAT
12680 && align_words >= GP_ARG_NUM_REG)))
12683 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12684 passed_in_gprs = false;
12685 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
12687 /* Compute number of bytes / words passed in FPRs. If there
12688 is still space available in the register parameter area
12689 *after* that amount, a part of the argument will be passed
12690 in GPRs. In that case, the total amount passed in any
12691 registers is equal to the amount that would have been passed
12692 in GPRs if everything were passed there, so we fall back to
12693 the GPR code below to compute the appropriate value. */
12694 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
12695 * MIN (8, GET_MODE_SIZE (elt_mode)));
12696 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
12698 if (align_words + fpr_words < GP_ARG_NUM_REG)
12699 passed_in_gprs = true;
12706 && align_words < GP_ARG_NUM_REG
12707 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
12708 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
12710 if (ret != 0 && TARGET_DEBUG_ARG)
12711 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
12716 /* A C expression that indicates when an argument must be passed by
12717 reference. If nonzero for an argument, a copy of that argument is
12718 made in memory and a pointer to the argument is passed instead of
12719 the argument itself. The pointer is passed in whatever way is
12720 appropriate for passing a pointer to that type.
12722 Under V.4, aggregates and long double are passed by reference.
12724 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12725 reference unless the AltiVec vector extension ABI is in force.
12727 As an extension to all ABIs, variable sized types are passed by
12731 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
12732 machine_mode mode, const_tree type,
12733 bool named ATTRIBUTE_UNUSED)
12738 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
12739 && FLOAT128_IEEE_P (TYPE_MODE (type)))
12741 if (TARGET_DEBUG_ARG)
12742 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12746 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
12748 if (TARGET_DEBUG_ARG)
12749 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
12753 if (int_size_in_bytes (type) < 0)
12755 if (TARGET_DEBUG_ARG)
12756 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
12760 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12761 modes only exist for GCC vector types if -maltivec. */
12762 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12764 if (TARGET_DEBUG_ARG)
12765 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
12769 /* Pass synthetic vectors in memory. */
12770 if (TREE_CODE (type) == VECTOR_TYPE
12771 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
12773 static bool warned_for_pass_big_vectors = false;
12774 if (TARGET_DEBUG_ARG)
12775 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
12776 if (!warned_for_pass_big_vectors)
12778 warning (OPT_Wpsabi, "GCC vector passed by reference: "
12779 "non-standard ABI extension with no compatibility "
12781 warned_for_pass_big_vectors = true;
12789 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12790 already processes. Return true if the parameter must be passed
12791 (fully or partially) on the stack. */
12794 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
12800 /* Catch errors. */
12801 if (type == NULL || type == error_mark_node)
12804 /* Handle types with no storage requirement. */
12805 if (TYPE_MODE (type) == VOIDmode)
12808 /* Handle complex types. */
12809 if (TREE_CODE (type) == COMPLEX_TYPE)
12810 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
12811 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
12813 /* Handle transparent aggregates. */
12814 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
12815 && TYPE_TRANSPARENT_AGGR (type))
12816 type = TREE_TYPE (first_field (type));
12818 /* See if this arg was passed by invisible reference. */
12819 if (pass_by_reference (get_cumulative_args (args_so_far),
12820 TYPE_MODE (type), type, true))
12821 type = build_pointer_type (type);
12823 /* Find mode as it is passed by the ABI. */
12824 unsignedp = TYPE_UNSIGNED (type);
12825 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
12827 /* If we must pass in stack, we need a stack. */
12828 if (rs6000_must_pass_in_stack (mode, type))
12831 /* If there is no incoming register, we need a stack. */
12832 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
12833 if (entry_parm == NULL)
12836 /* Likewise if we need to pass both in registers and on the stack. */
12837 if (GET_CODE (entry_parm) == PARALLEL
12838 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
12841 /* Also true if we're partially in registers and partially not. */
12842 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
12845 /* Update info on where next arg arrives in registers. */
12846 rs6000_function_arg_advance (args_so_far, mode, type, true);
12850 /* Return true if FUN has no prototype, has a variable argument
12851 list, or passes any parameter in memory. */
12854 rs6000_function_parms_need_stack (tree fun, bool incoming)
12856 tree fntype, result;
12857 CUMULATIVE_ARGS args_so_far_v;
12858 cumulative_args_t args_so_far;
12861 /* Must be a libcall, all of which only use reg parms. */
12866 fntype = TREE_TYPE (fun);
12868 /* Varargs functions need the parameter save area. */
12869 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
12872 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
12873 args_so_far = pack_cumulative_args (&args_so_far_v);
12875 /* When incoming, we will have been passed the function decl.
12876 It is necessary to use the decl to handle K&R style functions,
12877 where TYPE_ARG_TYPES may not be available. */
12880 gcc_assert (DECL_P (fun));
12881 result = DECL_RESULT (fun);
12884 result = TREE_TYPE (fntype);
12886 if (result && aggregate_value_p (result, fntype))
12888 if (!TYPE_P (result))
12889 result = TREE_TYPE (result);
12890 result = build_pointer_type (result);
12891 rs6000_parm_needs_stack (args_so_far, result);
12898 for (parm = DECL_ARGUMENTS (fun);
12899 parm && parm != void_list_node;
12900 parm = TREE_CHAIN (parm))
12901 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12906 function_args_iterator args_iter;
12909 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12910 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12917 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12918 usually a constant depending on the ABI. However, in the ELFv2 ABI
12919 the register parameter area is optional when calling a function that
12920 has a prototype is scope, has no variable argument list, and passes
12921 all parameters in registers. */
12924 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12926 int reg_parm_stack_space;
12928 switch (DEFAULT_ABI)
12931 reg_parm_stack_space = 0;
12936 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12940 /* ??? Recomputing this every time is a bit expensive. Is there
12941 a place to cache this information? */
12942 if (rs6000_function_parms_need_stack (fun, incoming))
12943 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12945 reg_parm_stack_space = 0;
12949 return reg_parm_stack_space;
12953 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12956 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12961 for (i = 0; i < nregs; i++)
12963 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12964 if (reload_completed)
12966 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12969 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12970 i * GET_MODE_SIZE (reg_mode));
12973 tem = replace_equiv_address (tem, XEXP (tem, 0));
12977 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12981 /* Perform any needed actions needed for a function that is receiving a
12982 variable number of arguments.
12986 MODE and TYPE are the mode and type of the current parameter.
12988 PRETEND_SIZE is a variable that should be set to the amount of stack
12989 that must be pushed by the prolog to pretend that our caller pushed
12992 Normally, this macro will push all remaining incoming registers on the
12993 stack and set PRETEND_SIZE to the length of the registers pushed. */
12996 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
12997 tree type, int *pretend_size ATTRIBUTE_UNUSED,
13000 CUMULATIVE_ARGS next_cum;
13001 int reg_size = TARGET_32BIT ? 4 : 8;
13002 rtx save_area = NULL_RTX, mem;
13003 int first_reg_offset;
13004 alias_set_type set;
13006 /* Skip the last named argument. */
13007 next_cum = *get_cumulative_args (cum);
13008 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
13010 if (DEFAULT_ABI == ABI_V4)
13012 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
13016 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
13017 HOST_WIDE_INT offset = 0;
13019 /* Try to optimize the size of the varargs save area.
13020 The ABI requires that ap.reg_save_area is doubleword
13021 aligned, but we don't need to allocate space for all
13022 the bytes, only those to which we actually will save
13024 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
13025 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
13026 if (TARGET_HARD_FLOAT
13027 && next_cum.fregno <= FP_ARG_V4_MAX_REG
13028 && cfun->va_list_fpr_size)
13031 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
13032 * UNITS_PER_FP_WORD;
13033 if (cfun->va_list_fpr_size
13034 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
13035 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
13037 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
13038 * UNITS_PER_FP_WORD;
13042 offset = -((first_reg_offset * reg_size) & ~7);
13043 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
13045 gpr_reg_num = cfun->va_list_gpr_size;
13046 if (reg_size == 4 && (first_reg_offset & 1))
13049 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
13052 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
13053 * UNITS_PER_FP_WORD
13054 - (int) (GP_ARG_NUM_REG * reg_size);
13056 if (gpr_size + fpr_size)
13059 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
13060 gcc_assert (GET_CODE (reg_save_area) == MEM);
13061 reg_save_area = XEXP (reg_save_area, 0);
13062 if (GET_CODE (reg_save_area) == PLUS)
13064 gcc_assert (XEXP (reg_save_area, 0)
13065 == virtual_stack_vars_rtx);
13066 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
13067 offset += INTVAL (XEXP (reg_save_area, 1));
13070 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
13073 cfun->machine->varargs_save_offset = offset;
13074 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
13079 first_reg_offset = next_cum.words;
13080 save_area = crtl->args.internal_arg_pointer;
13082 if (targetm.calls.must_pass_in_stack (mode, type))
13083 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
13086 set = get_varargs_alias_set ();
13087 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
13088 && cfun->va_list_gpr_size)
13090 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
13092 if (va_list_gpr_counter_field)
13093 /* V4 va_list_gpr_size counts number of registers needed. */
13094 n_gpr = cfun->va_list_gpr_size;
13096 /* char * va_list instead counts number of bytes needed. */
13097 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
13102 mem = gen_rtx_MEM (BLKmode,
13103 plus_constant (Pmode, save_area,
13104 first_reg_offset * reg_size));
13105 MEM_NOTRAP_P (mem) = 1;
13106 set_mem_alias_set (mem, set);
13107 set_mem_align (mem, BITS_PER_WORD);
13109 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
13113 /* Save FP registers if needed. */
13114 if (DEFAULT_ABI == ABI_V4
13115 && TARGET_HARD_FLOAT
13117 && next_cum.fregno <= FP_ARG_V4_MAX_REG
13118 && cfun->va_list_fpr_size)
13120 int fregno = next_cum.fregno, nregs;
13121 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
13122 rtx lab = gen_label_rtx ();
13123 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
13124 * UNITS_PER_FP_WORD);
13127 (gen_rtx_SET (pc_rtx,
13128 gen_rtx_IF_THEN_ELSE (VOIDmode,
13129 gen_rtx_NE (VOIDmode, cr1,
13131 gen_rtx_LABEL_REF (VOIDmode, lab),
13135 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
13136 fregno++, off += UNITS_PER_FP_WORD, nregs++)
13138 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13140 plus_constant (Pmode, save_area, off));
13141 MEM_NOTRAP_P (mem) = 1;
13142 set_mem_alias_set (mem, set);
13143 set_mem_align (mem, GET_MODE_ALIGNMENT (
13144 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13145 ? DFmode : SFmode));
13146 emit_move_insn (mem, gen_rtx_REG (
13147 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13148 ? DFmode : SFmode, fregno));
13155 /* Create the va_list data type. */
13158 rs6000_build_builtin_va_list (void)
13160 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
13162 /* For AIX, prefer 'char *' because that's what the system
13163 header files like. */
13164 if (DEFAULT_ABI != ABI_V4)
13165 return build_pointer_type (char_type_node);
13167 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
13168 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
13169 get_identifier ("__va_list_tag"), record);
13171 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
13172 unsigned_char_type_node);
13173 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
13174 unsigned_char_type_node);
13175 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
13176 every user file. */
13177 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13178 get_identifier ("reserved"), short_unsigned_type_node);
13179 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13180 get_identifier ("overflow_arg_area"),
13182 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13183 get_identifier ("reg_save_area"),
13186 va_list_gpr_counter_field = f_gpr;
13187 va_list_fpr_counter_field = f_fpr;
13189 DECL_FIELD_CONTEXT (f_gpr) = record;
13190 DECL_FIELD_CONTEXT (f_fpr) = record;
13191 DECL_FIELD_CONTEXT (f_res) = record;
13192 DECL_FIELD_CONTEXT (f_ovf) = record;
13193 DECL_FIELD_CONTEXT (f_sav) = record;
13195 TYPE_STUB_DECL (record) = type_decl;
13196 TYPE_NAME (record) = type_decl;
13197 TYPE_FIELDS (record) = f_gpr;
13198 DECL_CHAIN (f_gpr) = f_fpr;
13199 DECL_CHAIN (f_fpr) = f_res;
13200 DECL_CHAIN (f_res) = f_ovf;
13201 DECL_CHAIN (f_ovf) = f_sav;
13203 layout_type (record);
13205 /* The correct type is an array type of one element. */
13206 return build_array_type (record, build_index_type (size_zero_node));
13209 /* Implement va_start. */
13212 rs6000_va_start (tree valist, rtx nextarg)
13214 HOST_WIDE_INT words, n_gpr, n_fpr;
13215 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
13216 tree gpr, fpr, ovf, sav, t;
13218 /* Only SVR4 needs something special. */
13219 if (DEFAULT_ABI != ABI_V4)
13221 std_expand_builtin_va_start (valist, nextarg);
13225 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
13226 f_fpr = DECL_CHAIN (f_gpr);
13227 f_res = DECL_CHAIN (f_fpr);
13228 f_ovf = DECL_CHAIN (f_res);
13229 f_sav = DECL_CHAIN (f_ovf);
13231 valist = build_simple_mem_ref (valist);
13232 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
13233 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
13235 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
13237 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
13240 /* Count number of gp and fp argument registers used. */
13241 words = crtl->args.info.words;
13242 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
13244 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
13247 if (TARGET_DEBUG_ARG)
13248 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
13249 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
13250 words, n_gpr, n_fpr);
13252 if (cfun->va_list_gpr_size)
13254 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
13255 build_int_cst (NULL_TREE, n_gpr));
13256 TREE_SIDE_EFFECTS (t) = 1;
13257 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13260 if (cfun->va_list_fpr_size)
13262 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
13263 build_int_cst (NULL_TREE, n_fpr));
13264 TREE_SIDE_EFFECTS (t) = 1;
13265 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13267 #ifdef HAVE_AS_GNU_ATTRIBUTE
13268 if (call_ABI_of_interest (cfun->decl))
13269 rs6000_passes_float = true;
13273 /* Find the overflow area. */
13274 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
13276 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
13277 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
13278 TREE_SIDE_EFFECTS (t) = 1;
13279 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13281 /* If there were no va_arg invocations, don't set up the register
13283 if (!cfun->va_list_gpr_size
13284 && !cfun->va_list_fpr_size
13285 && n_gpr < GP_ARG_NUM_REG
13286 && n_fpr < FP_ARG_V4_MAX_REG)
13289 /* Find the register save area. */
13290 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
13291 if (cfun->machine->varargs_save_offset)
13292 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
13293 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
13294 TREE_SIDE_EFFECTS (t) = 1;
13295 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13298 /* Implement va_arg. */
13301 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
13302 gimple_seq *post_p)
13304 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
13305 tree gpr, fpr, ovf, sav, reg, t, u;
13306 int size, rsize, n_reg, sav_ofs, sav_scale;
13307 tree lab_false, lab_over, addr;
13309 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
13313 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
13315 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
13316 return build_va_arg_indirect_ref (t);
13319 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
13320 earlier version of gcc, with the property that it always applied alignment
13321 adjustments to the va-args (even for zero-sized types). The cheapest way
13322 to deal with this is to replicate the effect of the part of
13323 std_gimplify_va_arg_expr that carries out the align adjust, for the case
13325 We don't need to check for pass-by-reference because of the test above.
13326 We can return a simplifed answer, since we know there's no offset to add. */
13329 && rs6000_darwin64_abi)
13330 || DEFAULT_ABI == ABI_ELFv2
13331 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
13332 && integer_zerop (TYPE_SIZE (type)))
13334 unsigned HOST_WIDE_INT align, boundary;
13335 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
13336 align = PARM_BOUNDARY / BITS_PER_UNIT;
13337 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
13338 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
13339 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
13340 boundary /= BITS_PER_UNIT;
13341 if (boundary > align)
13344 /* This updates arg ptr by the amount that would be necessary
13345 to align the zero-sized (but not zero-alignment) item. */
13346 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13347 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
13348 gimplify_and_add (t, pre_p);
13350 t = fold_convert (sizetype, valist_tmp);
13351 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13352 fold_convert (TREE_TYPE (valist),
13353 fold_build2 (BIT_AND_EXPR, sizetype, t,
13354 size_int (-boundary))));
13355 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
13356 gimplify_and_add (t, pre_p);
13358 /* Since it is zero-sized there's no increment for the item itself. */
13359 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
13360 return build_va_arg_indirect_ref (valist_tmp);
13363 if (DEFAULT_ABI != ABI_V4)
13365 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
13367 tree elem_type = TREE_TYPE (type);
13368 machine_mode elem_mode = TYPE_MODE (elem_type);
13369 int elem_size = GET_MODE_SIZE (elem_mode);
13371 if (elem_size < UNITS_PER_WORD)
13373 tree real_part, imag_part;
13374 gimple_seq post = NULL;
13376 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13378 /* Copy the value into a temporary, lest the formal temporary
13379 be reused out from under us. */
13380 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
13381 gimple_seq_add_seq (pre_p, post);
13383 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13386 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
13390 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
13393 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
13394 f_fpr = DECL_CHAIN (f_gpr);
13395 f_res = DECL_CHAIN (f_fpr);
13396 f_ovf = DECL_CHAIN (f_res);
13397 f_sav = DECL_CHAIN (f_ovf);
13399 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
13400 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
13402 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
13404 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
13407 size = int_size_in_bytes (type);
13408 rsize = (size + 3) / 4;
13409 int pad = 4 * rsize - size;
13412 machine_mode mode = TYPE_MODE (type);
13413 if (abi_v4_pass_in_fpr (mode))
13415 /* FP args go in FP registers, if present. */
13417 n_reg = (size + 7) / 8;
13418 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
13419 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
13420 if (mode != SFmode && mode != SDmode)
13425 /* Otherwise into GP registers. */
13434 /* Pull the value out of the saved registers.... */
13437 addr = create_tmp_var (ptr_type_node, "addr");
13439 /* AltiVec vectors never go in registers when -mabi=altivec. */
13440 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13444 lab_false = create_artificial_label (input_location);
13445 lab_over = create_artificial_label (input_location);
13447 /* Long long is aligned in the registers. As are any other 2 gpr
13448 item such as complex int due to a historical mistake. */
13450 if (n_reg == 2 && reg == gpr)
13453 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13454 build_int_cst (TREE_TYPE (reg), n_reg - 1));
13455 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
13456 unshare_expr (reg), u);
13458 /* _Decimal128 is passed in even/odd fpr pairs; the stored
13459 reg number is 0 for f1, so we want to make it odd. */
13460 else if (reg == fpr && mode == TDmode)
13462 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13463 build_int_cst (TREE_TYPE (reg), 1));
13464 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
13467 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
13468 t = build2 (GE_EXPR, boolean_type_node, u, t);
13469 u = build1 (GOTO_EXPR, void_type_node, lab_false);
13470 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
13471 gimplify_and_add (t, pre_p);
13475 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
13477 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13478 build_int_cst (TREE_TYPE (reg), n_reg));
13479 u = fold_convert (sizetype, u);
13480 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
13481 t = fold_build_pointer_plus (t, u);
13483 /* _Decimal32 varargs are located in the second word of the 64-bit
13484 FP register for 32-bit binaries. */
13485 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
13486 t = fold_build_pointer_plus_hwi (t, size);
13488 /* Args are passed right-aligned. */
13489 if (BYTES_BIG_ENDIAN)
13490 t = fold_build_pointer_plus_hwi (t, pad);
13492 gimplify_assign (addr, t, pre_p);
13494 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
13496 stmt = gimple_build_label (lab_false);
13497 gimple_seq_add_stmt (pre_p, stmt);
13499 if ((n_reg == 2 && !regalign) || n_reg > 2)
13501 /* Ensure that we don't find any more args in regs.
13502 Alignment has taken care of for special cases. */
13503 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
13507 /* ... otherwise out of the overflow area. */
13509 /* Care for on-stack alignment if needed. */
13513 t = fold_build_pointer_plus_hwi (t, align - 1);
13514 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
13515 build_int_cst (TREE_TYPE (t), -align));
13518 /* Args are passed right-aligned. */
13519 if (BYTES_BIG_ENDIAN)
13520 t = fold_build_pointer_plus_hwi (t, pad);
13522 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
13524 gimplify_assign (unshare_expr (addr), t, pre_p);
13526 t = fold_build_pointer_plus_hwi (t, size);
13527 gimplify_assign (unshare_expr (ovf), t, pre_p);
13531 stmt = gimple_build_label (lab_over);
13532 gimple_seq_add_stmt (pre_p, stmt);
13535 if (STRICT_ALIGNMENT
13536 && (TYPE_ALIGN (type)
13537 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
13539 /* The value (of type complex double, for example) may not be
13540 aligned in memory in the saved registers, so copy via a
13541 temporary. (This is the same code as used for SPARC.) */
13542 tree tmp = create_tmp_var (type, "va_arg_tmp");
13543 tree dest_addr = build_fold_addr_expr (tmp);
13545 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
13546 3, dest_addr, addr, size_int (rsize * 4));
13548 gimplify_and_add (copy, pre_p);
13552 addr = fold_convert (ptrtype, addr);
13553 return build_va_arg_indirect_ref (addr);
13559 def_builtin (const char *name, tree type, enum rs6000_builtins code)
13562 unsigned classify = rs6000_builtin_info[(int)code].attr;
13563 const char *attr_string = "";
13565 gcc_assert (name != NULL);
13566 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
13568 if (rs6000_builtin_decls[(int)code])
13569 fatal_error (input_location,
13570 "internal error: builtin function %qs already processed",
13573 rs6000_builtin_decls[(int)code] = t =
13574 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
13576 /* Set any special attributes. */
13577 if ((classify & RS6000_BTC_CONST) != 0)
13579 /* const function, function only depends on the inputs. */
13580 TREE_READONLY (t) = 1;
13581 TREE_NOTHROW (t) = 1;
13582 attr_string = ", const";
13584 else if ((classify & RS6000_BTC_PURE) != 0)
13586 /* pure function, function can read global memory, but does not set any
13588 DECL_PURE_P (t) = 1;
13589 TREE_NOTHROW (t) = 1;
13590 attr_string = ", pure";
13592 else if ((classify & RS6000_BTC_FP) != 0)
13594 /* Function is a math function. If rounding mode is on, then treat the
13595 function as not reading global memory, but it can have arbitrary side
13596 effects. If it is off, then assume the function is a const function.
13597 This mimics the ATTR_MATHFN_FPROUNDING attribute in
13598 builtin-attribute.def that is used for the math functions. */
13599 TREE_NOTHROW (t) = 1;
13600 if (flag_rounding_math)
13602 DECL_PURE_P (t) = 1;
13603 DECL_IS_NOVOPS (t) = 1;
13604 attr_string = ", fp, pure";
13608 TREE_READONLY (t) = 1;
13609 attr_string = ", fp, const";
13612 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
13613 gcc_unreachable ();
13615 if (TARGET_DEBUG_BUILTIN)
13616 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
13617 (int)code, name, attr_string);
13620 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
13622 #undef RS6000_BUILTIN_0
13623 #undef RS6000_BUILTIN_1
13624 #undef RS6000_BUILTIN_2
13625 #undef RS6000_BUILTIN_3
13626 #undef RS6000_BUILTIN_A
13627 #undef RS6000_BUILTIN_D
13628 #undef RS6000_BUILTIN_H
13629 #undef RS6000_BUILTIN_P
13630 #undef RS6000_BUILTIN_Q
13631 #undef RS6000_BUILTIN_X
13633 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13634 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13635 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13636 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13637 { MASK, ICODE, NAME, ENUM },
13639 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13640 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13641 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13642 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13643 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13644 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13646 static const struct builtin_description bdesc_3arg[] =
13648 #include "rs6000-builtin.def"
13651 /* DST operations: void foo (void *, const int, const char). */
13653 #undef RS6000_BUILTIN_0
13654 #undef RS6000_BUILTIN_1
13655 #undef RS6000_BUILTIN_2
13656 #undef RS6000_BUILTIN_3
13657 #undef RS6000_BUILTIN_A
13658 #undef RS6000_BUILTIN_D
13659 #undef RS6000_BUILTIN_H
13660 #undef RS6000_BUILTIN_P
13661 #undef RS6000_BUILTIN_Q
13662 #undef RS6000_BUILTIN_X
13664 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13665 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13666 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13667 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13668 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13669 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13670 { MASK, ICODE, NAME, ENUM },
13672 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13673 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13674 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13675 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13677 static const struct builtin_description bdesc_dst[] =
13679 #include "rs6000-builtin.def"
13682 /* Simple binary operations: VECc = foo (VECa, VECb). */
13684 #undef RS6000_BUILTIN_0
13685 #undef RS6000_BUILTIN_1
13686 #undef RS6000_BUILTIN_2
13687 #undef RS6000_BUILTIN_3
13688 #undef RS6000_BUILTIN_A
13689 #undef RS6000_BUILTIN_D
13690 #undef RS6000_BUILTIN_H
13691 #undef RS6000_BUILTIN_P
13692 #undef RS6000_BUILTIN_Q
13693 #undef RS6000_BUILTIN_X
13695 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13696 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13697 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13698 { MASK, ICODE, NAME, ENUM },
13700 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13701 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13702 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13703 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13704 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13705 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13706 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13708 static const struct builtin_description bdesc_2arg[] =
13710 #include "rs6000-builtin.def"
13713 #undef RS6000_BUILTIN_0
13714 #undef RS6000_BUILTIN_1
13715 #undef RS6000_BUILTIN_2
13716 #undef RS6000_BUILTIN_3
13717 #undef RS6000_BUILTIN_A
13718 #undef RS6000_BUILTIN_D
13719 #undef RS6000_BUILTIN_H
13720 #undef RS6000_BUILTIN_P
13721 #undef RS6000_BUILTIN_Q
13722 #undef RS6000_BUILTIN_X
13724 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13725 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13726 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13727 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13728 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13729 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13730 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13731 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13732 { MASK, ICODE, NAME, ENUM },
13734 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13735 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13737 /* AltiVec predicates. */
13739 static const struct builtin_description bdesc_altivec_preds[] =
13741 #include "rs6000-builtin.def"
13744 /* PAIRED predicates. */
13745 #undef RS6000_BUILTIN_0
13746 #undef RS6000_BUILTIN_1
13747 #undef RS6000_BUILTIN_2
13748 #undef RS6000_BUILTIN_3
13749 #undef RS6000_BUILTIN_A
13750 #undef RS6000_BUILTIN_D
13751 #undef RS6000_BUILTIN_H
13752 #undef RS6000_BUILTIN_P
13753 #undef RS6000_BUILTIN_Q
13754 #undef RS6000_BUILTIN_X
13756 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13757 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13758 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13759 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13760 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13761 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13762 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13763 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13764 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
13765 { MASK, ICODE, NAME, ENUM },
13767 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13769 static const struct builtin_description bdesc_paired_preds[] =
13771 #include "rs6000-builtin.def"
13774 /* ABS* operations. */
13776 #undef RS6000_BUILTIN_0
13777 #undef RS6000_BUILTIN_1
13778 #undef RS6000_BUILTIN_2
13779 #undef RS6000_BUILTIN_3
13780 #undef RS6000_BUILTIN_A
13781 #undef RS6000_BUILTIN_D
13782 #undef RS6000_BUILTIN_H
13783 #undef RS6000_BUILTIN_P
13784 #undef RS6000_BUILTIN_Q
13785 #undef RS6000_BUILTIN_X
13787 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13788 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13789 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13790 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13791 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13792 { MASK, ICODE, NAME, ENUM },
13794 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13795 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13796 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13797 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13798 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13800 static const struct builtin_description bdesc_abs[] =
13802 #include "rs6000-builtin.def"
13805 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13808 #undef RS6000_BUILTIN_0
13809 #undef RS6000_BUILTIN_1
13810 #undef RS6000_BUILTIN_2
13811 #undef RS6000_BUILTIN_3
13812 #undef RS6000_BUILTIN_A
13813 #undef RS6000_BUILTIN_D
13814 #undef RS6000_BUILTIN_H
13815 #undef RS6000_BUILTIN_P
13816 #undef RS6000_BUILTIN_Q
13817 #undef RS6000_BUILTIN_X
13819 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13820 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13821 { MASK, ICODE, NAME, ENUM },
13823 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13824 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13825 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13826 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13827 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13828 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13829 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13830 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13832 static const struct builtin_description bdesc_1arg[] =
13834 #include "rs6000-builtin.def"
13837 /* Simple no-argument operations: result = __builtin_darn_32 () */
13839 #undef RS6000_BUILTIN_0
13840 #undef RS6000_BUILTIN_1
13841 #undef RS6000_BUILTIN_2
13842 #undef RS6000_BUILTIN_3
13843 #undef RS6000_BUILTIN_A
13844 #undef RS6000_BUILTIN_D
13845 #undef RS6000_BUILTIN_H
13846 #undef RS6000_BUILTIN_P
13847 #undef RS6000_BUILTIN_Q
13848 #undef RS6000_BUILTIN_X
13850 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13851 { MASK, ICODE, NAME, ENUM },
13853 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13854 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13855 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13856 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13857 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13858 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13859 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13860 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13861 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13863 static const struct builtin_description bdesc_0arg[] =
13865 #include "rs6000-builtin.def"
13868 /* HTM builtins. */
13869 #undef RS6000_BUILTIN_0
13870 #undef RS6000_BUILTIN_1
13871 #undef RS6000_BUILTIN_2
13872 #undef RS6000_BUILTIN_3
13873 #undef RS6000_BUILTIN_A
13874 #undef RS6000_BUILTIN_D
13875 #undef RS6000_BUILTIN_H
13876 #undef RS6000_BUILTIN_P
13877 #undef RS6000_BUILTIN_Q
13878 #undef RS6000_BUILTIN_X
13880 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13881 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13882 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13883 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13884 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13885 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13886 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13887 { MASK, ICODE, NAME, ENUM },
13889 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13890 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13891 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13893 static const struct builtin_description bdesc_htm[] =
13895 #include "rs6000-builtin.def"
13898 #undef RS6000_BUILTIN_0
13899 #undef RS6000_BUILTIN_1
13900 #undef RS6000_BUILTIN_2
13901 #undef RS6000_BUILTIN_3
13902 #undef RS6000_BUILTIN_A
13903 #undef RS6000_BUILTIN_D
13904 #undef RS6000_BUILTIN_H
13905 #undef RS6000_BUILTIN_P
13906 #undef RS6000_BUILTIN_Q
13908 /* Return true if a builtin function is overloaded. */
13910 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
13912 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
13916 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
13918 return rs6000_builtin_info[(int)fncode].name;
13921 /* Expand an expression EXP that calls a builtin without arguments. */
13923 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
13926 machine_mode tmode = insn_data[icode].operand[0].mode;
13928 if (icode == CODE_FOR_nothing)
13929 /* Builtin not supported on this processor. */
13933 || GET_MODE (target) != tmode
13934 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13935 target = gen_reg_rtx (tmode);
13937 pat = GEN_FCN (icode) (target);
13947 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13950 tree arg0 = CALL_EXPR_ARG (exp, 0);
13951 tree arg1 = CALL_EXPR_ARG (exp, 1);
13952 rtx op0 = expand_normal (arg0);
13953 rtx op1 = expand_normal (arg1);
13954 machine_mode mode0 = insn_data[icode].operand[0].mode;
13955 machine_mode mode1 = insn_data[icode].operand[1].mode;
13957 if (icode == CODE_FOR_nothing)
13958 /* Builtin not supported on this processor. */
13961 /* If we got invalid arguments bail out before generating bad rtl. */
13962 if (arg0 == error_mark_node || arg1 == error_mark_node)
13965 if (GET_CODE (op0) != CONST_INT
13966 || INTVAL (op0) > 255
13967 || INTVAL (op0) < 0)
13969 error ("argument 1 must be an 8-bit field value");
13973 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13974 op0 = copy_to_mode_reg (mode0, op0);
13976 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13977 op1 = copy_to_mode_reg (mode1, op1);
13979 pat = GEN_FCN (icode) (op0, op1);
13988 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13991 tree arg0 = CALL_EXPR_ARG (exp, 0);
13992 rtx op0 = expand_normal (arg0);
13993 machine_mode tmode = insn_data[icode].operand[0].mode;
13994 machine_mode mode0 = insn_data[icode].operand[1].mode;
13996 if (icode == CODE_FOR_nothing)
13997 /* Builtin not supported on this processor. */
14000 /* If we got invalid arguments bail out before generating bad rtl. */
14001 if (arg0 == error_mark_node)
14004 if (icode == CODE_FOR_altivec_vspltisb
14005 || icode == CODE_FOR_altivec_vspltish
14006 || icode == CODE_FOR_altivec_vspltisw)
14008 /* Only allow 5-bit *signed* literals. */
14009 if (GET_CODE (op0) != CONST_INT
14010 || INTVAL (op0) > 15
14011 || INTVAL (op0) < -16)
14013 error ("argument 1 must be a 5-bit signed literal");
14014 return CONST0_RTX (tmode);
14019 || GET_MODE (target) != tmode
14020 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14021 target = gen_reg_rtx (tmode);
14023 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14024 op0 = copy_to_mode_reg (mode0, op0);
14026 pat = GEN_FCN (icode) (target, op0);
14035 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
14037 rtx pat, scratch1, scratch2;
14038 tree arg0 = CALL_EXPR_ARG (exp, 0);
14039 rtx op0 = expand_normal (arg0);
14040 machine_mode tmode = insn_data[icode].operand[0].mode;
14041 machine_mode mode0 = insn_data[icode].operand[1].mode;
14043 /* If we have invalid arguments, bail out before generating bad rtl. */
14044 if (arg0 == error_mark_node)
14048 || GET_MODE (target) != tmode
14049 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14050 target = gen_reg_rtx (tmode);
14052 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14053 op0 = copy_to_mode_reg (mode0, op0);
14055 scratch1 = gen_reg_rtx (mode0);
14056 scratch2 = gen_reg_rtx (mode0);
14058 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
14067 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
14070 tree arg0 = CALL_EXPR_ARG (exp, 0);
14071 tree arg1 = CALL_EXPR_ARG (exp, 1);
14072 rtx op0 = expand_normal (arg0);
14073 rtx op1 = expand_normal (arg1);
14074 machine_mode tmode = insn_data[icode].operand[0].mode;
14075 machine_mode mode0 = insn_data[icode].operand[1].mode;
14076 machine_mode mode1 = insn_data[icode].operand[2].mode;
14078 if (icode == CODE_FOR_nothing)
14079 /* Builtin not supported on this processor. */
14082 /* If we got invalid arguments bail out before generating bad rtl. */
14083 if (arg0 == error_mark_node || arg1 == error_mark_node)
14086 if (icode == CODE_FOR_altivec_vcfux
14087 || icode == CODE_FOR_altivec_vcfsx
14088 || icode == CODE_FOR_altivec_vctsxs
14089 || icode == CODE_FOR_altivec_vctuxs
14090 || icode == CODE_FOR_altivec_vspltb
14091 || icode == CODE_FOR_altivec_vsplth
14092 || icode == CODE_FOR_altivec_vspltw)
14094 /* Only allow 5-bit unsigned literals. */
14096 if (TREE_CODE (arg1) != INTEGER_CST
14097 || TREE_INT_CST_LOW (arg1) & ~0x1f)
14099 error ("argument 2 must be a 5-bit unsigned literal");
14100 return CONST0_RTX (tmode);
14103 else if (icode == CODE_FOR_dfptstsfi_eq_dd
14104 || icode == CODE_FOR_dfptstsfi_lt_dd
14105 || icode == CODE_FOR_dfptstsfi_gt_dd
14106 || icode == CODE_FOR_dfptstsfi_unordered_dd
14107 || icode == CODE_FOR_dfptstsfi_eq_td
14108 || icode == CODE_FOR_dfptstsfi_lt_td
14109 || icode == CODE_FOR_dfptstsfi_gt_td
14110 || icode == CODE_FOR_dfptstsfi_unordered_td)
14112 /* Only allow 6-bit unsigned literals. */
14114 if (TREE_CODE (arg0) != INTEGER_CST
14115 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
14117 error ("argument 1 must be a 6-bit unsigned literal");
14118 return CONST0_RTX (tmode);
14121 else if (icode == CODE_FOR_xststdcqp_kf
14122 || icode == CODE_FOR_xststdcqp_tf
14123 || icode == CODE_FOR_xststdcdp
14124 || icode == CODE_FOR_xststdcsp
14125 || icode == CODE_FOR_xvtstdcdp
14126 || icode == CODE_FOR_xvtstdcsp)
14128 /* Only allow 7-bit unsigned literals. */
14130 if (TREE_CODE (arg1) != INTEGER_CST
14131 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
14133 error ("argument 2 must be a 7-bit unsigned literal");
14134 return CONST0_RTX (tmode);
14137 else if (icode == CODE_FOR_unpackv1ti
14138 || icode == CODE_FOR_unpackkf
14139 || icode == CODE_FOR_unpacktf
14140 || icode == CODE_FOR_unpackif
14141 || icode == CODE_FOR_unpacktd)
14143 /* Only allow 1-bit unsigned literals. */
14145 if (TREE_CODE (arg1) != INTEGER_CST
14146 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
14148 error ("argument 2 must be a 1-bit unsigned literal");
14149 return CONST0_RTX (tmode);
14154 || GET_MODE (target) != tmode
14155 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14156 target = gen_reg_rtx (tmode);
14158 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14159 op0 = copy_to_mode_reg (mode0, op0);
14160 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14161 op1 = copy_to_mode_reg (mode1, op1);
14163 pat = GEN_FCN (icode) (target, op0, op1);
14172 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
14175 tree cr6_form = CALL_EXPR_ARG (exp, 0);
14176 tree arg0 = CALL_EXPR_ARG (exp, 1);
14177 tree arg1 = CALL_EXPR_ARG (exp, 2);
14178 rtx op0 = expand_normal (arg0);
14179 rtx op1 = expand_normal (arg1);
14180 machine_mode tmode = SImode;
14181 machine_mode mode0 = insn_data[icode].operand[1].mode;
14182 machine_mode mode1 = insn_data[icode].operand[2].mode;
14185 if (TREE_CODE (cr6_form) != INTEGER_CST)
14187 error ("argument 1 of %qs must be a constant",
14188 "__builtin_altivec_predicate");
14192 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
14194 gcc_assert (mode0 == mode1);
14196 /* If we have invalid arguments, bail out before generating bad rtl. */
14197 if (arg0 == error_mark_node || arg1 == error_mark_node)
14201 || GET_MODE (target) != tmode
14202 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14203 target = gen_reg_rtx (tmode);
14205 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14206 op0 = copy_to_mode_reg (mode0, op0);
14207 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14208 op1 = copy_to_mode_reg (mode1, op1);
14210 /* Note that for many of the relevant operations (e.g. cmpne or
14211 cmpeq) with float or double operands, it makes more sense for the
14212 mode of the allocated scratch register to select a vector of
14213 integer. But the choice to copy the mode of operand 0 was made
14214 long ago and there are no plans to change it. */
14215 scratch = gen_reg_rtx (mode0);
14217 pat = GEN_FCN (icode) (scratch, op0, op1);
14222 /* The vec_any* and vec_all* predicates use the same opcodes for two
14223 different operations, but the bits in CR6 will be different
14224 depending on what information we want. So we have to play tricks
14225 with CR6 to get the right bits out.
14227 If you think this is disgusting, look at the specs for the
14228 AltiVec predicates. */
14230 switch (cr6_form_int)
14233 emit_insn (gen_cr6_test_for_zero (target));
14236 emit_insn (gen_cr6_test_for_zero_reverse (target));
14239 emit_insn (gen_cr6_test_for_lt (target));
14242 emit_insn (gen_cr6_test_for_lt_reverse (target));
14245 error ("argument 1 of %qs is out of range",
14246 "__builtin_altivec_predicate");
14254 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
14257 tree arg0 = CALL_EXPR_ARG (exp, 0);
14258 tree arg1 = CALL_EXPR_ARG (exp, 1);
14259 machine_mode tmode = insn_data[icode].operand[0].mode;
14260 machine_mode mode0 = Pmode;
14261 machine_mode mode1 = Pmode;
14262 rtx op0 = expand_normal (arg0);
14263 rtx op1 = expand_normal (arg1);
14265 if (icode == CODE_FOR_nothing)
14266 /* Builtin not supported on this processor. */
14269 /* If we got invalid arguments bail out before generating bad rtl. */
14270 if (arg0 == error_mark_node || arg1 == error_mark_node)
14274 || GET_MODE (target) != tmode
14275 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14276 target = gen_reg_rtx (tmode);
14278 op1 = copy_to_mode_reg (mode1, op1);
14280 if (op0 == const0_rtx)
14282 addr = gen_rtx_MEM (tmode, op1);
14286 op0 = copy_to_mode_reg (mode0, op0);
14287 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
14290 pat = GEN_FCN (icode) (target, addr);
14299 /* Return a constant vector for use as a little-endian permute control vector
14300 to reverse the order of elements of the given vector mode. */
14302 swap_selector_for_mode (machine_mode mode)
14304 /* These are little endian vectors, so their elements are reversed
14305 from what you would normally expect for a permute control vector. */
14306 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14307 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14308 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14309 unsigned int swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
14310 unsigned int *swaparray, i;
14327 swaparray = swap16;
14330 gcc_unreachable ();
14333 for (i = 0; i < 16; ++i)
14334 perm[i] = GEN_INT (swaparray[i]);
14336 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)));
14340 swap_endian_selector_for_mode (machine_mode mode)
14342 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
14343 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14344 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14345 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14347 unsigned int *swaparray, i;
14367 gcc_unreachable ();
14370 for (i = 0; i < 16; ++i)
14371 perm[i] = GEN_INT (swaparray[i]);
14373 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
14374 gen_rtvec_v (16, perm)));
14377 /* Generate code for an "lvxl", or "lve*x" built-in for a little endian target
14378 with -maltivec=be specified. Issue the load followed by an element-
14379 reversing permute. */
14381 altivec_expand_lvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14383 rtx tmp = gen_reg_rtx (mode);
14384 rtx load = gen_rtx_SET (tmp, op1);
14385 rtx lvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
14386 rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, load, lvx));
14387 rtx sel = swap_selector_for_mode (mode);
14388 rtx vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, tmp, tmp, sel), UNSPEC_VPERM);
14390 gcc_assert (REG_P (op0));
14392 emit_insn (gen_rtx_SET (op0, vperm));
14395 /* Generate code for a "stvxl" built-in for a little endian target with
14396 -maltivec=be specified. Issue the store preceded by an element-reversing
14399 altivec_expand_stvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14401 rtx tmp = gen_reg_rtx (mode);
14402 rtx store = gen_rtx_SET (op0, tmp);
14403 rtx stvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
14404 rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, store, stvx));
14405 rtx sel = swap_selector_for_mode (mode);
14408 gcc_assert (REG_P (op1));
14409 vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
14410 emit_insn (gen_rtx_SET (tmp, vperm));
14414 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
14415 specified. Issue the store preceded by an element-reversing permute. */
14417 altivec_expand_stvex_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14419 machine_mode inner_mode = GET_MODE_INNER (mode);
14420 rtx tmp = gen_reg_rtx (mode);
14421 rtx stvx = gen_rtx_UNSPEC (inner_mode, gen_rtvec (1, tmp), unspec);
14422 rtx sel = swap_selector_for_mode (mode);
14425 gcc_assert (REG_P (op1));
14426 vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
14427 emit_insn (gen_rtx_SET (tmp, vperm));
14428 emit_insn (gen_rtx_SET (op0, stvx));
14432 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
14435 tree arg0 = CALL_EXPR_ARG (exp, 0);
14436 tree arg1 = CALL_EXPR_ARG (exp, 1);
14437 machine_mode tmode = insn_data[icode].operand[0].mode;
14438 machine_mode mode0 = Pmode;
14439 machine_mode mode1 = Pmode;
14440 rtx op0 = expand_normal (arg0);
14441 rtx op1 = expand_normal (arg1);
14443 if (icode == CODE_FOR_nothing)
14444 /* Builtin not supported on this processor. */
14447 /* If we got invalid arguments bail out before generating bad rtl. */
14448 if (arg0 == error_mark_node || arg1 == error_mark_node)
14452 || GET_MODE (target) != tmode
14453 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14454 target = gen_reg_rtx (tmode);
14456 op1 = copy_to_mode_reg (mode1, op1);
14458 /* For LVX, express the RTL accurately by ANDing the address with -16.
14459 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
14460 so the raw address is fine. */
14461 if (icode == CODE_FOR_altivec_lvx_v2df_2op
14462 || icode == CODE_FOR_altivec_lvx_v2di_2op
14463 || icode == CODE_FOR_altivec_lvx_v4sf_2op
14464 || icode == CODE_FOR_altivec_lvx_v4si_2op
14465 || icode == CODE_FOR_altivec_lvx_v8hi_2op
14466 || icode == CODE_FOR_altivec_lvx_v16qi_2op)
14469 if (op0 == const0_rtx)
14473 op0 = copy_to_mode_reg (mode0, op0);
14474 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
14476 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14477 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
14479 /* For -maltivec=be, emit the load and follow it up with a
14480 permute to swap the elements. */
14481 if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
14483 rtx temp = gen_reg_rtx (tmode);
14484 emit_insn (gen_rtx_SET (temp, addr));
14486 rtx sel = swap_selector_for_mode (tmode);
14487 rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, temp, temp, sel),
14489 emit_insn (gen_rtx_SET (target, vperm));
14492 emit_insn (gen_rtx_SET (target, addr));
14496 if (op0 == const0_rtx)
14497 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
14500 op0 = copy_to_mode_reg (mode0, op0);
14501 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
14502 gen_rtx_PLUS (Pmode, op1, op0));
14505 pat = GEN_FCN (icode) (target, addr);
14515 paired_expand_stv_builtin (enum insn_code icode, tree exp)
14517 tree arg0 = CALL_EXPR_ARG (exp, 0);
14518 tree arg1 = CALL_EXPR_ARG (exp, 1);
14519 tree arg2 = CALL_EXPR_ARG (exp, 2);
14520 rtx op0 = expand_normal (arg0);
14521 rtx op1 = expand_normal (arg1);
14522 rtx op2 = expand_normal (arg2);
14524 machine_mode tmode = insn_data[icode].operand[0].mode;
14525 machine_mode mode1 = Pmode;
14526 machine_mode mode2 = Pmode;
14528 /* Invalid arguments. Bail before doing anything stoopid! */
14529 if (arg0 == error_mark_node
14530 || arg1 == error_mark_node
14531 || arg2 == error_mark_node)
14534 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
14535 op0 = copy_to_mode_reg (tmode, op0);
14537 op2 = copy_to_mode_reg (mode2, op2);
14539 if (op1 == const0_rtx)
14541 addr = gen_rtx_MEM (tmode, op2);
14545 op1 = copy_to_mode_reg (mode1, op1);
14546 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
14549 pat = GEN_FCN (icode) (addr, op0);
14556 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
14559 tree arg0 = CALL_EXPR_ARG (exp, 0);
14560 tree arg1 = CALL_EXPR_ARG (exp, 1);
14561 tree arg2 = CALL_EXPR_ARG (exp, 2);
14562 rtx op0 = expand_normal (arg0);
14563 rtx op1 = expand_normal (arg1);
14564 rtx op2 = expand_normal (arg2);
14565 machine_mode mode0 = insn_data[icode].operand[0].mode;
14566 machine_mode mode1 = insn_data[icode].operand[1].mode;
14567 machine_mode mode2 = insn_data[icode].operand[2].mode;
14569 if (icode == CODE_FOR_nothing)
14570 /* Builtin not supported on this processor. */
14573 /* If we got invalid arguments bail out before generating bad rtl. */
14574 if (arg0 == error_mark_node
14575 || arg1 == error_mark_node
14576 || arg2 == error_mark_node)
14579 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14580 op0 = copy_to_mode_reg (mode0, op0);
14581 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14582 op1 = copy_to_mode_reg (mode1, op1);
14583 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14584 op2 = copy_to_mode_reg (mode2, op2);
14586 pat = GEN_FCN (icode) (op0, op1, op2);
14594 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
14596 tree arg0 = CALL_EXPR_ARG (exp, 0);
14597 tree arg1 = CALL_EXPR_ARG (exp, 1);
14598 tree arg2 = CALL_EXPR_ARG (exp, 2);
14599 rtx op0 = expand_normal (arg0);
14600 rtx op1 = expand_normal (arg1);
14601 rtx op2 = expand_normal (arg2);
14602 rtx pat, addr, rawaddr;
14603 machine_mode tmode = insn_data[icode].operand[0].mode;
14604 machine_mode smode = insn_data[icode].operand[1].mode;
14605 machine_mode mode1 = Pmode;
14606 machine_mode mode2 = Pmode;
14608 /* Invalid arguments. Bail before doing anything stoopid! */
14609 if (arg0 == error_mark_node
14610 || arg1 == error_mark_node
14611 || arg2 == error_mark_node)
14614 op2 = copy_to_mode_reg (mode2, op2);
14616 /* For STVX, express the RTL accurately by ANDing the address with -16.
14617 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
14618 so the raw address is fine. */
14619 if (icode == CODE_FOR_altivec_stvx_v2df_2op
14620 || icode == CODE_FOR_altivec_stvx_v2di_2op
14621 || icode == CODE_FOR_altivec_stvx_v4sf_2op
14622 || icode == CODE_FOR_altivec_stvx_v4si_2op
14623 || icode == CODE_FOR_altivec_stvx_v8hi_2op
14624 || icode == CODE_FOR_altivec_stvx_v16qi_2op)
14626 if (op1 == const0_rtx)
14630 op1 = copy_to_mode_reg (mode1, op1);
14631 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
14634 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14635 addr = gen_rtx_MEM (tmode, addr);
14637 op0 = copy_to_mode_reg (tmode, op0);
14639 /* For -maltivec=be, emit a permute to swap the elements, followed
14641 if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
14643 rtx temp = gen_reg_rtx (tmode);
14644 rtx sel = swap_selector_for_mode (tmode);
14645 rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, op0, op0, sel),
14647 emit_insn (gen_rtx_SET (temp, vperm));
14648 emit_insn (gen_rtx_SET (addr, temp));
14651 emit_insn (gen_rtx_SET (addr, op0));
14655 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
14656 op0 = copy_to_mode_reg (smode, op0);
14658 if (op1 == const0_rtx)
14659 addr = gen_rtx_MEM (tmode, op2);
14662 op1 = copy_to_mode_reg (mode1, op1);
14663 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
14666 pat = GEN_FCN (icode) (addr, op0);
14674 /* Return the appropriate SPR number associated with the given builtin. */
14675 static inline HOST_WIDE_INT
14676 htm_spr_num (enum rs6000_builtins code)
14678 if (code == HTM_BUILTIN_GET_TFHAR
14679 || code == HTM_BUILTIN_SET_TFHAR)
14681 else if (code == HTM_BUILTIN_GET_TFIAR
14682 || code == HTM_BUILTIN_SET_TFIAR)
14684 else if (code == HTM_BUILTIN_GET_TEXASR
14685 || code == HTM_BUILTIN_SET_TEXASR)
14687 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
14688 || code == HTM_BUILTIN_SET_TEXASRU);
14689 return TEXASRU_SPR;
14692 /* Return the appropriate SPR regno associated with the given builtin. */
14693 static inline HOST_WIDE_INT
14694 htm_spr_regno (enum rs6000_builtins code)
14696 if (code == HTM_BUILTIN_GET_TFHAR
14697 || code == HTM_BUILTIN_SET_TFHAR)
14698 return TFHAR_REGNO;
14699 else if (code == HTM_BUILTIN_GET_TFIAR
14700 || code == HTM_BUILTIN_SET_TFIAR)
14701 return TFIAR_REGNO;
14702 gcc_assert (code == HTM_BUILTIN_GET_TEXASR
14703 || code == HTM_BUILTIN_SET_TEXASR
14704 || code == HTM_BUILTIN_GET_TEXASRU
14705 || code == HTM_BUILTIN_SET_TEXASRU);
14706 return TEXASR_REGNO;
14709 /* Return the correct ICODE value depending on whether we are
14710 setting or reading the HTM SPRs. */
14711 static inline enum insn_code
14712 rs6000_htm_spr_icode (bool nonvoid)
14715 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
14717 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
14720 /* Expand the HTM builtin in EXP and store the result in TARGET.
14721 Store true in *EXPANDEDP if we found a builtin to expand. */
14723 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
14725 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14726 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
14727 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14728 const struct builtin_description *d;
14733 if (!TARGET_POWERPC64
14734 && (fcode == HTM_BUILTIN_TABORTDC
14735 || fcode == HTM_BUILTIN_TABORTDCI))
14737 size_t uns_fcode = (size_t)fcode;
14738 const char *name = rs6000_builtin_info[uns_fcode].name;
14739 error ("builtin %qs is only valid in 64-bit mode", name);
14743 /* Expand the HTM builtins. */
14745 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
14746 if (d->code == fcode)
14748 rtx op[MAX_HTM_OPERANDS], pat;
14751 call_expr_arg_iterator iter;
14752 unsigned attr = rs6000_builtin_info[fcode].attr;
14753 enum insn_code icode = d->icode;
14754 const struct insn_operand_data *insn_op;
14755 bool uses_spr = (attr & RS6000_BTC_SPR);
14759 icode = rs6000_htm_spr_icode (nonvoid);
14760 insn_op = &insn_data[icode].operand[0];
14764 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
14766 || GET_MODE (target) != tmode
14767 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
14768 target = gen_reg_rtx (tmode);
14770 op[nopnds++] = target;
14773 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
14775 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
14778 insn_op = &insn_data[icode].operand[nopnds];
14780 op[nopnds] = expand_normal (arg);
14782 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
14784 if (!strcmp (insn_op->constraint, "n"))
14786 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
14787 if (!CONST_INT_P (op[nopnds]))
14788 error ("argument %d must be an unsigned literal", arg_num);
14790 error ("argument %d is an unsigned literal that is "
14791 "out of range", arg_num);
14794 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
14800 /* Handle the builtins for extended mnemonics. These accept
14801 no arguments, but map to builtins that take arguments. */
14804 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
14805 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
14806 op[nopnds++] = GEN_INT (1);
14808 attr |= RS6000_BTC_UNARY;
14810 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
14811 op[nopnds++] = GEN_INT (0);
14813 attr |= RS6000_BTC_UNARY;
14819 /* If this builtin accesses SPRs, then pass in the appropriate
14820 SPR number and SPR regno as the last two operands. */
14823 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
14824 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
14825 op[nopnds++] = gen_rtx_REG (mode, htm_spr_regno (fcode));
14827 /* If this builtin accesses a CR, then pass in a scratch
14828 CR as the last operand. */
14829 else if (attr & RS6000_BTC_CR)
14830 { cr = gen_reg_rtx (CCmode);
14836 int expected_nopnds = 0;
14837 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
14838 expected_nopnds = 1;
14839 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
14840 expected_nopnds = 2;
14841 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
14842 expected_nopnds = 3;
14843 if (!(attr & RS6000_BTC_VOID))
14844 expected_nopnds += 1;
14846 expected_nopnds += 2;
14848 gcc_assert (nopnds == expected_nopnds
14849 && nopnds <= MAX_HTM_OPERANDS);
14855 pat = GEN_FCN (icode) (op[0]);
14858 pat = GEN_FCN (icode) (op[0], op[1]);
14861 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
14864 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
14867 gcc_unreachable ();
14873 if (attr & RS6000_BTC_CR)
14875 if (fcode == HTM_BUILTIN_TBEGIN)
14877 /* Emit code to set TARGET to true or false depending on
14878 whether the tbegin. instruction successfully or failed
14879 to start a transaction. We do this by placing the 1's
14880 complement of CR's EQ bit into TARGET. */
14881 rtx scratch = gen_reg_rtx (SImode);
14882 emit_insn (gen_rtx_SET (scratch,
14883 gen_rtx_EQ (SImode, cr,
14885 emit_insn (gen_rtx_SET (target,
14886 gen_rtx_XOR (SImode, scratch,
14891 /* Emit code to copy the 4-bit condition register field
14892 CR into the least significant end of register TARGET. */
14893 rtx scratch1 = gen_reg_rtx (SImode);
14894 rtx scratch2 = gen_reg_rtx (SImode);
14895 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
14896 emit_insn (gen_movcc (subreg, cr));
14897 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
14898 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
14907 *expandedp = false;
14911 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14914 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
14917 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14918 if (fcode == RS6000_BUILTIN_CPU_INIT)
14921 if (target == 0 || GET_MODE (target) != SImode)
14922 target = gen_reg_rtx (SImode);
14924 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14925 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
14926 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
14927 to a STRING_CST. */
14928 if (TREE_CODE (arg) == ARRAY_REF
14929 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
14930 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
14931 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
14932 arg = TREE_OPERAND (arg, 0);
14934 if (TREE_CODE (arg) != STRING_CST)
14936 error ("builtin %qs only accepts a string argument",
14937 rs6000_builtin_info[(size_t) fcode].name);
14941 if (fcode == RS6000_BUILTIN_CPU_IS)
14943 const char *cpu = TREE_STRING_POINTER (arg);
14944 rtx cpuid = NULL_RTX;
14945 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
14946 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
14948 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14949 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
14952 if (cpuid == NULL_RTX)
14954 /* Invalid CPU argument. */
14955 error ("cpu %qs is an invalid argument to builtin %qs",
14956 cpu, rs6000_builtin_info[(size_t) fcode].name);
14960 rtx platform = gen_reg_rtx (SImode);
14961 rtx tcbmem = gen_const_mem (SImode,
14962 gen_rtx_PLUS (Pmode,
14963 gen_rtx_REG (Pmode, TLS_REGNUM),
14964 GEN_INT (TCB_PLATFORM_OFFSET)));
14965 emit_move_insn (platform, tcbmem);
14966 emit_insn (gen_eqsi3 (target, platform, cpuid));
14968 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
14970 const char *hwcap = TREE_STRING_POINTER (arg);
14971 rtx mask = NULL_RTX;
14973 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
14974 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
14976 mask = GEN_INT (cpu_supports_info[i].mask);
14977 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
14980 if (mask == NULL_RTX)
14982 /* Invalid HWCAP argument. */
14983 error ("%s %qs is an invalid argument to builtin %qs",
14984 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
14988 rtx tcb_hwcap = gen_reg_rtx (SImode);
14989 rtx tcbmem = gen_const_mem (SImode,
14990 gen_rtx_PLUS (Pmode,
14991 gen_rtx_REG (Pmode, TLS_REGNUM),
14992 GEN_INT (hwcap_offset)));
14993 emit_move_insn (tcb_hwcap, tcbmem);
14994 rtx scratch1 = gen_reg_rtx (SImode);
14995 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
14996 rtx scratch2 = gen_reg_rtx (SImode);
14997 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
14998 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
15001 gcc_unreachable ();
15003 /* Record that we have expanded a CPU builtin, so that we can later
15004 emit a reference to the special symbol exported by LIBC to ensure we
15005 do not link against an old LIBC that doesn't support this feature. */
15006 cpu_builtin_p = true;
15009 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
15010 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
15012 /* For old LIBCs, always return FALSE. */
15013 emit_move_insn (target, GEN_INT (0));
15014 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
15020 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
15023 tree arg0 = CALL_EXPR_ARG (exp, 0);
15024 tree arg1 = CALL_EXPR_ARG (exp, 1);
15025 tree arg2 = CALL_EXPR_ARG (exp, 2);
15026 rtx op0 = expand_normal (arg0);
15027 rtx op1 = expand_normal (arg1);
15028 rtx op2 = expand_normal (arg2);
15029 machine_mode tmode = insn_data[icode].operand[0].mode;
15030 machine_mode mode0 = insn_data[icode].operand[1].mode;
15031 machine_mode mode1 = insn_data[icode].operand[2].mode;
15032 machine_mode mode2 = insn_data[icode].operand[3].mode;
15034 if (icode == CODE_FOR_nothing)
15035 /* Builtin not supported on this processor. */
15038 /* If we got invalid arguments bail out before generating bad rtl. */
15039 if (arg0 == error_mark_node
15040 || arg1 == error_mark_node
15041 || arg2 == error_mark_node)
15044 /* Check and prepare argument depending on the instruction code.
15046 Note that a switch statement instead of the sequence of tests
15047 would be incorrect as many of the CODE_FOR values could be
15048 CODE_FOR_nothing and that would yield multiple alternatives
15049 with identical values. We'd never reach here at runtime in
15051 if (icode == CODE_FOR_altivec_vsldoi_v4sf
15052 || icode == CODE_FOR_altivec_vsldoi_v2df
15053 || icode == CODE_FOR_altivec_vsldoi_v4si
15054 || icode == CODE_FOR_altivec_vsldoi_v8hi
15055 || icode == CODE_FOR_altivec_vsldoi_v16qi)
15057 /* Only allow 4-bit unsigned literals. */
15059 if (TREE_CODE (arg2) != INTEGER_CST
15060 || TREE_INT_CST_LOW (arg2) & ~0xf)
15062 error ("argument 3 must be a 4-bit unsigned literal");
15063 return CONST0_RTX (tmode);
15066 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
15067 || icode == CODE_FOR_vsx_xxpermdi_v2di
15068 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
15069 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
15070 || icode == CODE_FOR_vsx_xxpermdi_v1ti
15071 || icode == CODE_FOR_vsx_xxpermdi_v4sf
15072 || icode == CODE_FOR_vsx_xxpermdi_v4si
15073 || icode == CODE_FOR_vsx_xxpermdi_v8hi
15074 || icode == CODE_FOR_vsx_xxpermdi_v16qi
15075 || icode == CODE_FOR_vsx_xxsldwi_v16qi
15076 || icode == CODE_FOR_vsx_xxsldwi_v8hi
15077 || icode == CODE_FOR_vsx_xxsldwi_v4si
15078 || icode == CODE_FOR_vsx_xxsldwi_v4sf
15079 || icode == CODE_FOR_vsx_xxsldwi_v2di
15080 || icode == CODE_FOR_vsx_xxsldwi_v2df)
15082 /* Only allow 2-bit unsigned literals. */
15084 if (TREE_CODE (arg2) != INTEGER_CST
15085 || TREE_INT_CST_LOW (arg2) & ~0x3)
15087 error ("argument 3 must be a 2-bit unsigned literal");
15088 return CONST0_RTX (tmode);
15091 else if (icode == CODE_FOR_vsx_set_v2df
15092 || icode == CODE_FOR_vsx_set_v2di
15093 || icode == CODE_FOR_bcdadd
15094 || icode == CODE_FOR_bcdadd_lt
15095 || icode == CODE_FOR_bcdadd_eq
15096 || icode == CODE_FOR_bcdadd_gt
15097 || icode == CODE_FOR_bcdsub
15098 || icode == CODE_FOR_bcdsub_lt
15099 || icode == CODE_FOR_bcdsub_eq
15100 || icode == CODE_FOR_bcdsub_gt)
15102 /* Only allow 1-bit unsigned literals. */
15104 if (TREE_CODE (arg2) != INTEGER_CST
15105 || TREE_INT_CST_LOW (arg2) & ~0x1)
15107 error ("argument 3 must be a 1-bit unsigned literal");
15108 return CONST0_RTX (tmode);
15111 else if (icode == CODE_FOR_dfp_ddedpd_dd
15112 || icode == CODE_FOR_dfp_ddedpd_td)
15114 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
15116 if (TREE_CODE (arg0) != INTEGER_CST
15117 || TREE_INT_CST_LOW (arg2) & ~0x3)
15119 error ("argument 1 must be 0 or 2");
15120 return CONST0_RTX (tmode);
15123 else if (icode == CODE_FOR_dfp_denbcd_dd
15124 || icode == CODE_FOR_dfp_denbcd_td)
15126 /* Only allow 1-bit unsigned literals. */
15128 if (TREE_CODE (arg0) != INTEGER_CST
15129 || TREE_INT_CST_LOW (arg0) & ~0x1)
15131 error ("argument 1 must be a 1-bit unsigned literal");
15132 return CONST0_RTX (tmode);
15135 else if (icode == CODE_FOR_dfp_dscli_dd
15136 || icode == CODE_FOR_dfp_dscli_td
15137 || icode == CODE_FOR_dfp_dscri_dd
15138 || icode == CODE_FOR_dfp_dscri_td)
15140 /* Only allow 6-bit unsigned literals. */
15142 if (TREE_CODE (arg1) != INTEGER_CST
15143 || TREE_INT_CST_LOW (arg1) & ~0x3f)
15145 error ("argument 2 must be a 6-bit unsigned literal");
15146 return CONST0_RTX (tmode);
15149 else if (icode == CODE_FOR_crypto_vshasigmaw
15150 || icode == CODE_FOR_crypto_vshasigmad)
15152 /* Check whether the 2nd and 3rd arguments are integer constants and in
15153 range and prepare arguments. */
15155 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
15157 error ("argument 2 must be 0 or 1");
15158 return CONST0_RTX (tmode);
15162 if (TREE_CODE (arg2) != INTEGER_CST
15163 || wi::geu_p (wi::to_wide (arg2), 16))
15165 error ("argument 3 must be in the range 0..15");
15166 return CONST0_RTX (tmode);
15171 || GET_MODE (target) != tmode
15172 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15173 target = gen_reg_rtx (tmode);
15175 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15176 op0 = copy_to_mode_reg (mode0, op0);
15177 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
15178 op1 = copy_to_mode_reg (mode1, op1);
15179 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
15180 op2 = copy_to_mode_reg (mode2, op2);
15182 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
15183 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
15185 pat = GEN_FCN (icode) (target, op0, op1, op2);
15193 /* Expand the lvx builtins. */
15195 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
15197 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15198 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15200 machine_mode tmode, mode0;
15202 enum insn_code icode;
15206 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
15207 icode = CODE_FOR_vector_altivec_load_v16qi;
15209 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
15210 icode = CODE_FOR_vector_altivec_load_v8hi;
15212 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
15213 icode = CODE_FOR_vector_altivec_load_v4si;
15215 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
15216 icode = CODE_FOR_vector_altivec_load_v4sf;
15218 case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
15219 icode = CODE_FOR_vector_altivec_load_v2df;
15221 case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
15222 icode = CODE_FOR_vector_altivec_load_v2di;
15224 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti:
15225 icode = CODE_FOR_vector_altivec_load_v1ti;
15228 *expandedp = false;
15234 arg0 = CALL_EXPR_ARG (exp, 0);
15235 op0 = expand_normal (arg0);
15236 tmode = insn_data[icode].operand[0].mode;
15237 mode0 = insn_data[icode].operand[1].mode;
15240 || GET_MODE (target) != tmode
15241 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15242 target = gen_reg_rtx (tmode);
15244 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15245 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15247 pat = GEN_FCN (icode) (target, op0);
15254 /* Expand the stvx builtins. */
15256 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
15259 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15260 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15262 machine_mode mode0, mode1;
15264 enum insn_code icode;
15268 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
15269 icode = CODE_FOR_vector_altivec_store_v16qi;
15271 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
15272 icode = CODE_FOR_vector_altivec_store_v8hi;
15274 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
15275 icode = CODE_FOR_vector_altivec_store_v4si;
15277 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
15278 icode = CODE_FOR_vector_altivec_store_v4sf;
15280 case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
15281 icode = CODE_FOR_vector_altivec_store_v2df;
15283 case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
15284 icode = CODE_FOR_vector_altivec_store_v2di;
15286 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti:
15287 icode = CODE_FOR_vector_altivec_store_v1ti;
15290 *expandedp = false;
15294 arg0 = CALL_EXPR_ARG (exp, 0);
15295 arg1 = CALL_EXPR_ARG (exp, 1);
15296 op0 = expand_normal (arg0);
15297 op1 = expand_normal (arg1);
15298 mode0 = insn_data[icode].operand[0].mode;
15299 mode1 = insn_data[icode].operand[1].mode;
15301 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15302 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15303 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
15304 op1 = copy_to_mode_reg (mode1, op1);
15306 pat = GEN_FCN (icode) (op0, op1);
15314 /* Expand the dst builtins. */
15316 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
15319 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15320 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15321 tree arg0, arg1, arg2;
15322 machine_mode mode0, mode1;
15323 rtx pat, op0, op1, op2;
15324 const struct builtin_description *d;
15327 *expandedp = false;
15329 /* Handle DST variants. */
15331 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
15332 if (d->code == fcode)
15334 arg0 = CALL_EXPR_ARG (exp, 0);
15335 arg1 = CALL_EXPR_ARG (exp, 1);
15336 arg2 = CALL_EXPR_ARG (exp, 2);
15337 op0 = expand_normal (arg0);
15338 op1 = expand_normal (arg1);
15339 op2 = expand_normal (arg2);
15340 mode0 = insn_data[d->icode].operand[0].mode;
15341 mode1 = insn_data[d->icode].operand[1].mode;
15343 /* Invalid arguments, bail out before generating bad rtl. */
15344 if (arg0 == error_mark_node
15345 || arg1 == error_mark_node
15346 || arg2 == error_mark_node)
15351 if (TREE_CODE (arg2) != INTEGER_CST
15352 || TREE_INT_CST_LOW (arg2) & ~0x3)
15354 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
15358 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
15359 op0 = copy_to_mode_reg (Pmode, op0);
15360 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
15361 op1 = copy_to_mode_reg (mode1, op1);
15363 pat = GEN_FCN (d->icode) (op0, op1, op2);
15373 /* Expand vec_init builtin. */
15375 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
15377 machine_mode tmode = TYPE_MODE (type);
15378 machine_mode inner_mode = GET_MODE_INNER (tmode);
15379 int i, n_elt = GET_MODE_NUNITS (tmode);
15381 gcc_assert (VECTOR_MODE_P (tmode));
15382 gcc_assert (n_elt == call_expr_nargs (exp));
15384 if (!target || !register_operand (target, tmode))
15385 target = gen_reg_rtx (tmode);
15387 /* If we have a vector compromised of a single element, such as V1TImode, do
15388 the initialization directly. */
15389 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
15391 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
15392 emit_move_insn (target, gen_lowpart (tmode, x));
15396 rtvec v = rtvec_alloc (n_elt);
15398 for (i = 0; i < n_elt; ++i)
15400 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
15401 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
15404 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
15410 /* Return the integer constant in ARG. Constrain it to be in the range
15411 of the subparts of VEC_TYPE; issue an error if not. */
15414 get_element_number (tree vec_type, tree arg)
15416 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
15418 if (!tree_fits_uhwi_p (arg)
15419 || (elt = tree_to_uhwi (arg), elt > max))
15421 error ("selector must be an integer constant in the range 0..%wi", max);
15428 /* Expand vec_set builtin. */
15430 altivec_expand_vec_set_builtin (tree exp)
15432 machine_mode tmode, mode1;
15433 tree arg0, arg1, arg2;
15437 arg0 = CALL_EXPR_ARG (exp, 0);
15438 arg1 = CALL_EXPR_ARG (exp, 1);
15439 arg2 = CALL_EXPR_ARG (exp, 2);
15441 tmode = TYPE_MODE (TREE_TYPE (arg0));
15442 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15443 gcc_assert (VECTOR_MODE_P (tmode));
15445 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
15446 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
15447 elt = get_element_number (TREE_TYPE (arg0), arg2);
15449 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
15450 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
15452 op0 = force_reg (tmode, op0);
15453 op1 = force_reg (mode1, op1);
15455 rs6000_expand_vector_set (op0, op1, elt);
15460 /* Expand vec_ext builtin. */
15462 altivec_expand_vec_ext_builtin (tree exp, rtx target)
15464 machine_mode tmode, mode0;
15469 arg0 = CALL_EXPR_ARG (exp, 0);
15470 arg1 = CALL_EXPR_ARG (exp, 1);
15472 op0 = expand_normal (arg0);
15473 op1 = expand_normal (arg1);
15475 /* Call get_element_number to validate arg1 if it is a constant. */
15476 if (TREE_CODE (arg1) == INTEGER_CST)
15477 (void) get_element_number (TREE_TYPE (arg0), arg1);
15479 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15480 mode0 = TYPE_MODE (TREE_TYPE (arg0));
15481 gcc_assert (VECTOR_MODE_P (mode0));
15483 op0 = force_reg (mode0, op0);
15485 if (optimize || !target || !register_operand (target, tmode))
15486 target = gen_reg_rtx (tmode);
15488 rs6000_expand_vector_extract (target, op0, op1);
15493 /* Expand the builtin in EXP and store the result in TARGET. Store
15494 true in *EXPANDEDP if we found a builtin to expand. */
15496 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
15498 const struct builtin_description *d;
15500 enum insn_code icode;
15501 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15502 tree arg0, arg1, arg2;
15504 machine_mode tmode, mode0;
15505 enum rs6000_builtins fcode
15506 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15508 if (rs6000_overloaded_builtin_p (fcode))
15511 error ("unresolved overload for Altivec builtin %qF", fndecl);
15513 /* Given it is invalid, just generate a normal call. */
15514 return expand_call (exp, target, false);
15517 target = altivec_expand_ld_builtin (exp, target, expandedp);
15521 target = altivec_expand_st_builtin (exp, target, expandedp);
15525 target = altivec_expand_dst_builtin (exp, target, expandedp);
15533 case ALTIVEC_BUILTIN_STVX_V2DF:
15534 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df_2op, exp);
15535 case ALTIVEC_BUILTIN_STVX_V2DI:
15536 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di_2op, exp);
15537 case ALTIVEC_BUILTIN_STVX_V4SF:
15538 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf_2op, exp);
15539 case ALTIVEC_BUILTIN_STVX:
15540 case ALTIVEC_BUILTIN_STVX_V4SI:
15541 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si_2op, exp);
15542 case ALTIVEC_BUILTIN_STVX_V8HI:
15543 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi_2op, exp);
15544 case ALTIVEC_BUILTIN_STVX_V16QI:
15545 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi_2op, exp);
15546 case ALTIVEC_BUILTIN_STVEBX:
15547 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
15548 case ALTIVEC_BUILTIN_STVEHX:
15549 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
15550 case ALTIVEC_BUILTIN_STVEWX:
15551 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
15552 case ALTIVEC_BUILTIN_STVXL_V2DF:
15553 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
15554 case ALTIVEC_BUILTIN_STVXL_V2DI:
15555 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
15556 case ALTIVEC_BUILTIN_STVXL_V4SF:
15557 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
15558 case ALTIVEC_BUILTIN_STVXL:
15559 case ALTIVEC_BUILTIN_STVXL_V4SI:
15560 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
15561 case ALTIVEC_BUILTIN_STVXL_V8HI:
15562 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
15563 case ALTIVEC_BUILTIN_STVXL_V16QI:
15564 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
15566 case ALTIVEC_BUILTIN_STVLX:
15567 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
15568 case ALTIVEC_BUILTIN_STVLXL:
15569 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
15570 case ALTIVEC_BUILTIN_STVRX:
15571 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
15572 case ALTIVEC_BUILTIN_STVRXL:
15573 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
15575 case P9V_BUILTIN_STXVL:
15576 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
15578 case P9V_BUILTIN_XST_LEN_R:
15579 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
15581 case VSX_BUILTIN_STXVD2X_V1TI:
15582 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
15583 case VSX_BUILTIN_STXVD2X_V2DF:
15584 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
15585 case VSX_BUILTIN_STXVD2X_V2DI:
15586 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
15587 case VSX_BUILTIN_STXVW4X_V4SF:
15588 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
15589 case VSX_BUILTIN_STXVW4X_V4SI:
15590 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
15591 case VSX_BUILTIN_STXVW4X_V8HI:
15592 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
15593 case VSX_BUILTIN_STXVW4X_V16QI:
15594 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
15596 /* For the following on big endian, it's ok to use any appropriate
15597 unaligned-supporting store, so use a generic expander. For
15598 little-endian, the exact element-reversing instruction must
15600 case VSX_BUILTIN_ST_ELEMREV_V1TI:
15602 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
15603 : CODE_FOR_vsx_st_elemrev_v1ti);
15604 return altivec_expand_stv_builtin (code, exp);
15606 case VSX_BUILTIN_ST_ELEMREV_V2DF:
15608 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
15609 : CODE_FOR_vsx_st_elemrev_v2df);
15610 return altivec_expand_stv_builtin (code, exp);
15612 case VSX_BUILTIN_ST_ELEMREV_V2DI:
15614 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
15615 : CODE_FOR_vsx_st_elemrev_v2di);
15616 return altivec_expand_stv_builtin (code, exp);
15618 case VSX_BUILTIN_ST_ELEMREV_V4SF:
15620 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
15621 : CODE_FOR_vsx_st_elemrev_v4sf);
15622 return altivec_expand_stv_builtin (code, exp);
15624 case VSX_BUILTIN_ST_ELEMREV_V4SI:
15626 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
15627 : CODE_FOR_vsx_st_elemrev_v4si);
15628 return altivec_expand_stv_builtin (code, exp);
15630 case VSX_BUILTIN_ST_ELEMREV_V8HI:
15632 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
15633 : CODE_FOR_vsx_st_elemrev_v8hi);
15634 return altivec_expand_stv_builtin (code, exp);
15636 case VSX_BUILTIN_ST_ELEMREV_V16QI:
15638 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
15639 : CODE_FOR_vsx_st_elemrev_v16qi);
15640 return altivec_expand_stv_builtin (code, exp);
15643 case ALTIVEC_BUILTIN_MFVSCR:
15644 icode = CODE_FOR_altivec_mfvscr;
15645 tmode = insn_data[icode].operand[0].mode;
15648 || GET_MODE (target) != tmode
15649 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15650 target = gen_reg_rtx (tmode);
15652 pat = GEN_FCN (icode) (target);
15658 case ALTIVEC_BUILTIN_MTVSCR:
15659 icode = CODE_FOR_altivec_mtvscr;
15660 arg0 = CALL_EXPR_ARG (exp, 0);
15661 op0 = expand_normal (arg0);
15662 mode0 = insn_data[icode].operand[0].mode;
15664 /* If we got invalid arguments bail out before generating bad rtl. */
15665 if (arg0 == error_mark_node)
15668 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15669 op0 = copy_to_mode_reg (mode0, op0);
15671 pat = GEN_FCN (icode) (op0);
15676 case ALTIVEC_BUILTIN_DSSALL:
15677 emit_insn (gen_altivec_dssall ());
15680 case ALTIVEC_BUILTIN_DSS:
15681 icode = CODE_FOR_altivec_dss;
15682 arg0 = CALL_EXPR_ARG (exp, 0);
15684 op0 = expand_normal (arg0);
15685 mode0 = insn_data[icode].operand[0].mode;
15687 /* If we got invalid arguments bail out before generating bad rtl. */
15688 if (arg0 == error_mark_node)
15691 if (TREE_CODE (arg0) != INTEGER_CST
15692 || TREE_INT_CST_LOW (arg0) & ~0x3)
15694 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
15698 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15699 op0 = copy_to_mode_reg (mode0, op0);
15701 emit_insn (gen_altivec_dss (op0));
15704 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
15705 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
15706 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
15707 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
15708 case VSX_BUILTIN_VEC_INIT_V2DF:
15709 case VSX_BUILTIN_VEC_INIT_V2DI:
15710 case VSX_BUILTIN_VEC_INIT_V1TI:
15711 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
15713 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
15714 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
15715 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
15716 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
15717 case VSX_BUILTIN_VEC_SET_V2DF:
15718 case VSX_BUILTIN_VEC_SET_V2DI:
15719 case VSX_BUILTIN_VEC_SET_V1TI:
15720 return altivec_expand_vec_set_builtin (exp);
15722 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
15723 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
15724 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
15725 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
15726 case VSX_BUILTIN_VEC_EXT_V2DF:
15727 case VSX_BUILTIN_VEC_EXT_V2DI:
15728 case VSX_BUILTIN_VEC_EXT_V1TI:
15729 return altivec_expand_vec_ext_builtin (exp, target);
15731 case P9V_BUILTIN_VEXTRACT4B:
15732 case P9V_BUILTIN_VEC_VEXTRACT4B:
15733 arg1 = CALL_EXPR_ARG (exp, 1);
15736 /* Generate a normal call if it is invalid. */
15737 if (arg1 == error_mark_node)
15738 return expand_call (exp, target, false);
15740 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
15742 error ("second argument to %qs must be 0..12", "vec_vextract4b");
15743 return expand_call (exp, target, false);
15747 case P9V_BUILTIN_VINSERT4B:
15748 case P9V_BUILTIN_VINSERT4B_DI:
15749 case P9V_BUILTIN_VEC_VINSERT4B:
15750 arg2 = CALL_EXPR_ARG (exp, 2);
15753 /* Generate a normal call if it is invalid. */
15754 if (arg2 == error_mark_node)
15755 return expand_call (exp, target, false);
15757 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
15759 error ("third argument to %qs must be 0..12", "vec_vinsert4b");
15760 return expand_call (exp, target, false);
15766 /* Fall through. */
15769 /* Expand abs* operations. */
15771 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
15772 if (d->code == fcode)
15773 return altivec_expand_abs_builtin (d->icode, exp, target);
15775 /* Expand the AltiVec predicates. */
15776 d = bdesc_altivec_preds;
15777 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
15778 if (d->code == fcode)
15779 return altivec_expand_predicate_builtin (d->icode, exp, target);
15781 /* LV* are funky. We initialized them differently. */
15784 case ALTIVEC_BUILTIN_LVSL:
15785 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
15786 exp, target, false);
15787 case ALTIVEC_BUILTIN_LVSR:
15788 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
15789 exp, target, false);
15790 case ALTIVEC_BUILTIN_LVEBX:
15791 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
15792 exp, target, false);
15793 case ALTIVEC_BUILTIN_LVEHX:
15794 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
15795 exp, target, false);
15796 case ALTIVEC_BUILTIN_LVEWX:
15797 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
15798 exp, target, false);
15799 case ALTIVEC_BUILTIN_LVXL_V2DF:
15800 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
15801 exp, target, false);
15802 case ALTIVEC_BUILTIN_LVXL_V2DI:
15803 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
15804 exp, target, false);
15805 case ALTIVEC_BUILTIN_LVXL_V4SF:
15806 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
15807 exp, target, false);
15808 case ALTIVEC_BUILTIN_LVXL:
15809 case ALTIVEC_BUILTIN_LVXL_V4SI:
15810 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
15811 exp, target, false);
15812 case ALTIVEC_BUILTIN_LVXL_V8HI:
15813 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
15814 exp, target, false);
15815 case ALTIVEC_BUILTIN_LVXL_V16QI:
15816 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
15817 exp, target, false);
15818 case ALTIVEC_BUILTIN_LVX_V2DF:
15819 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df_2op,
15820 exp, target, false);
15821 case ALTIVEC_BUILTIN_LVX_V2DI:
15822 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di_2op,
15823 exp, target, false);
15824 case ALTIVEC_BUILTIN_LVX_V4SF:
15825 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf_2op,
15826 exp, target, false);
15827 case ALTIVEC_BUILTIN_LVX:
15828 case ALTIVEC_BUILTIN_LVX_V4SI:
15829 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si_2op,
15830 exp, target, false);
15831 case ALTIVEC_BUILTIN_LVX_V8HI:
15832 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi_2op,
15833 exp, target, false);
15834 case ALTIVEC_BUILTIN_LVX_V16QI:
15835 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi_2op,
15836 exp, target, false);
15837 case ALTIVEC_BUILTIN_LVLX:
15838 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
15839 exp, target, true);
15840 case ALTIVEC_BUILTIN_LVLXL:
15841 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
15842 exp, target, true);
15843 case ALTIVEC_BUILTIN_LVRX:
15844 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
15845 exp, target, true);
15846 case ALTIVEC_BUILTIN_LVRXL:
15847 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
15848 exp, target, true);
15849 case VSX_BUILTIN_LXVD2X_V1TI:
15850 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
15851 exp, target, false);
15852 case VSX_BUILTIN_LXVD2X_V2DF:
15853 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
15854 exp, target, false);
15855 case VSX_BUILTIN_LXVD2X_V2DI:
15856 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
15857 exp, target, false);
15858 case VSX_BUILTIN_LXVW4X_V4SF:
15859 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
15860 exp, target, false);
15861 case VSX_BUILTIN_LXVW4X_V4SI:
15862 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
15863 exp, target, false);
15864 case VSX_BUILTIN_LXVW4X_V8HI:
15865 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
15866 exp, target, false);
15867 case VSX_BUILTIN_LXVW4X_V16QI:
15868 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
15869 exp, target, false);
15870 /* For the following on big endian, it's ok to use any appropriate
15871 unaligned-supporting load, so use a generic expander. For
15872 little-endian, the exact element-reversing instruction must
15874 case VSX_BUILTIN_LD_ELEMREV_V2DF:
15876 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
15877 : CODE_FOR_vsx_ld_elemrev_v2df);
15878 return altivec_expand_lv_builtin (code, exp, target, false);
15880 case VSX_BUILTIN_LD_ELEMREV_V1TI:
15882 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
15883 : CODE_FOR_vsx_ld_elemrev_v1ti);
15884 return altivec_expand_lv_builtin (code, exp, target, false);
15886 case VSX_BUILTIN_LD_ELEMREV_V2DI:
15888 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
15889 : CODE_FOR_vsx_ld_elemrev_v2di);
15890 return altivec_expand_lv_builtin (code, exp, target, false);
15892 case VSX_BUILTIN_LD_ELEMREV_V4SF:
15894 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
15895 : CODE_FOR_vsx_ld_elemrev_v4sf);
15896 return altivec_expand_lv_builtin (code, exp, target, false);
15898 case VSX_BUILTIN_LD_ELEMREV_V4SI:
15900 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
15901 : CODE_FOR_vsx_ld_elemrev_v4si);
15902 return altivec_expand_lv_builtin (code, exp, target, false);
15904 case VSX_BUILTIN_LD_ELEMREV_V8HI:
15906 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
15907 : CODE_FOR_vsx_ld_elemrev_v8hi);
15908 return altivec_expand_lv_builtin (code, exp, target, false);
15910 case VSX_BUILTIN_LD_ELEMREV_V16QI:
15912 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
15913 : CODE_FOR_vsx_ld_elemrev_v16qi);
15914 return altivec_expand_lv_builtin (code, exp, target, false);
15919 /* Fall through. */
15922 *expandedp = false;
15926 /* Expand the builtin in EXP and store the result in TARGET. Store
15927 true in *EXPANDEDP if we found a builtin to expand. */
15929 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
15931 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15932 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15933 const struct builtin_description *d;
15940 case PAIRED_BUILTIN_STX:
15941 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
15942 case PAIRED_BUILTIN_LX:
15943 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
15946 /* Fall through. */
15949 /* Expand the paired predicates. */
15950 d = bdesc_paired_preds;
15951 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
15952 if (d->code == fcode)
15953 return paired_expand_predicate_builtin (d->icode, exp, target);
15955 *expandedp = false;
15960 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
15962 rtx pat, scratch, tmp;
15963 tree form = CALL_EXPR_ARG (exp, 0);
15964 tree arg0 = CALL_EXPR_ARG (exp, 1);
15965 tree arg1 = CALL_EXPR_ARG (exp, 2);
15966 rtx op0 = expand_normal (arg0);
15967 rtx op1 = expand_normal (arg1);
15968 machine_mode mode0 = insn_data[icode].operand[1].mode;
15969 machine_mode mode1 = insn_data[icode].operand[2].mode;
15971 enum rtx_code code;
15973 if (TREE_CODE (form) != INTEGER_CST)
15975 error ("argument 1 of %s must be a constant",
15976 "__builtin_paired_predicate");
15980 form_int = TREE_INT_CST_LOW (form);
15982 gcc_assert (mode0 == mode1);
15984 if (arg0 == error_mark_node || arg1 == error_mark_node)
15988 || GET_MODE (target) != SImode
15989 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
15990 target = gen_reg_rtx (SImode);
15991 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
15992 op0 = copy_to_mode_reg (mode0, op0);
15993 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
15994 op1 = copy_to_mode_reg (mode1, op1);
15996 scratch = gen_reg_rtx (CCFPmode);
15998 pat = GEN_FCN (icode) (scratch, op0, op1);
16020 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
16023 error ("argument 1 of %qs is out of range",
16024 "__builtin_paired_predicate");
16028 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
16029 emit_move_insn (target, tmp);
16033 /* Raise an error message for a builtin function that is called without the
16034 appropriate target options being set. */
16037 rs6000_invalid_builtin (enum rs6000_builtins fncode)
16039 size_t uns_fncode = (size_t) fncode;
16040 const char *name = rs6000_builtin_info[uns_fncode].name;
16041 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
16043 gcc_assert (name != NULL);
16044 if ((fnmask & RS6000_BTM_CELL) != 0)
16045 error ("builtin function %qs is only valid for the cell processor", name);
16046 else if ((fnmask & RS6000_BTM_VSX) != 0)
16047 error ("builtin function %qs requires the %qs option", name, "-mvsx");
16048 else if ((fnmask & RS6000_BTM_HTM) != 0)
16049 error ("builtin function %qs requires the %qs option", name, "-mhtm");
16050 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
16051 error ("builtin function %qs requires the %qs option", name, "-maltivec");
16052 else if ((fnmask & RS6000_BTM_PAIRED) != 0)
16053 error ("builtin function %qs requires the %qs option", name, "-mpaired");
16054 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
16055 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
16056 error ("builtin function %qs requires the %qs and %qs options",
16057 name, "-mhard-dfp", "-mpower8-vector");
16058 else if ((fnmask & RS6000_BTM_DFP) != 0)
16059 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
16060 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
16061 error ("builtin function %qs requires the %qs option", name,
16062 "-mpower8-vector");
16063 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
16064 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
16065 error ("builtin function %qs requires the %qs and %qs options",
16066 name, "-mcpu=power9", "-m64");
16067 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
16068 error ("builtin function %qs requires the %qs option", name,
16070 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
16071 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
16072 error ("builtin function %qs requires the %qs and %qs options",
16073 name, "-mcpu=power9", "-m64");
16074 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
16075 error ("builtin function %qs requires the %qs option", name,
16077 else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
16078 == (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
16079 error ("builtin function %qs requires the %qs and %qs options",
16080 name, "-mhard-float", "-mlong-double-128");
16081 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
16082 error ("builtin function %qs requires the %qs option", name,
16084 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
16085 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
16087 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
16088 error ("builtin function %qs requires the %qs option", name, "-mfloat128");
16090 error ("builtin function %qs is not supported with the current options",
16094 /* Target hook for early folding of built-ins, shamelessly stolen
16098 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
16099 int n_args ATTRIBUTE_UNUSED,
16100 tree *args ATTRIBUTE_UNUSED,
16101 bool ignore ATTRIBUTE_UNUSED)
16103 #ifdef SUBTARGET_FOLD_BUILTIN
16104 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
16110 /* Helper function to sort out which built-ins may be valid without having
16113 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
16117 case ALTIVEC_BUILTIN_STVX_V16QI:
16118 case ALTIVEC_BUILTIN_STVX_V8HI:
16119 case ALTIVEC_BUILTIN_STVX_V4SI:
16120 case ALTIVEC_BUILTIN_STVX_V4SF:
16121 case ALTIVEC_BUILTIN_STVX_V2DI:
16122 case ALTIVEC_BUILTIN_STVX_V2DF:
16129 /* Helper function to handle the gimple folding of a vector compare
16130 operation. This sets up true/false vectors, and uses the
16131 VEC_COND_EXPR operation.
16132 CODE indicates which comparison is to be made. (EQ, GT, ...).
16133 TYPE indicates the type of the result. */
16135 fold_build_vec_cmp (tree_code code, tree type,
16136 tree arg0, tree arg1)
16138 tree cmp_type = build_same_sized_truth_vector_type (type);
16139 tree zero_vec = build_zero_cst (type);
16140 tree minus_one_vec = build_minus_one_cst (type);
16141 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
16142 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
16145 /* Helper function to handle the in-between steps for the
16146 vector compare built-ins. */
16148 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
16150 tree arg0 = gimple_call_arg (stmt, 0);
16151 tree arg1 = gimple_call_arg (stmt, 1);
16152 tree lhs = gimple_call_lhs (stmt);
16153 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
16154 gimple *g = gimple_build_assign (lhs, cmp);
16155 gimple_set_location (g, gimple_location (stmt));
16156 gsi_replace (gsi, g, true);
16159 /* Helper function to handle the vector merge[hl] built-ins. The
16160 implementation difference between h and l versions for this code are in
16161 the values used when building of the permute vector for high word versus
16162 low word merge. The variance is keyed off the use_high parameter. */
16164 fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
16166 tree arg0 = gimple_call_arg (stmt, 0);
16167 tree arg1 = gimple_call_arg (stmt, 1);
16168 tree lhs = gimple_call_lhs (stmt);
16169 tree lhs_type = TREE_TYPE (lhs);
16170 tree lhs_type_type = TREE_TYPE (lhs_type);
16171 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
16172 int midpoint = n_elts / 2;
16178 tree_vector_builder elts (lhs_type, VECTOR_CST_NELTS (arg0), 1);
16180 for (int i = 0; i < midpoint; i++)
16182 elts.safe_push (build_int_cst (lhs_type_type, offset + i));
16183 elts.safe_push (build_int_cst (lhs_type_type, offset + n_elts + i));
16186 tree permute = elts.build ();
16188 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
16189 gimple_set_location (g, gimple_location (stmt));
16190 gsi_replace (gsi, g, true);
16193 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
16194 a constant, use rs6000_fold_builtin.) */
16197 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
16199 gimple *stmt = gsi_stmt (*gsi);
16200 tree fndecl = gimple_call_fndecl (stmt);
16201 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
16202 enum rs6000_builtins fn_code
16203 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
16204 tree arg0, arg1, lhs, temp;
16207 size_t uns_fncode = (size_t) fn_code;
16208 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
16209 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
16210 const char *fn_name2 = (icode != CODE_FOR_nothing)
16211 ? get_insn_name ((int) icode)
16214 if (TARGET_DEBUG_BUILTIN)
16215 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
16216 fn_code, fn_name1, fn_name2);
16218 if (!rs6000_fold_gimple)
16221 /* Prevent gimple folding for code that does not have a LHS, unless it is
16222 allowed per the rs6000_builtin_valid_without_lhs helper function. */
16223 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
16226 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
16227 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
16228 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
16234 /* Flavors of vec_add. We deliberately don't expand
16235 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
16236 TImode, resulting in much poorer code generation. */
16237 case ALTIVEC_BUILTIN_VADDUBM:
16238 case ALTIVEC_BUILTIN_VADDUHM:
16239 case ALTIVEC_BUILTIN_VADDUWM:
16240 case P8V_BUILTIN_VADDUDM:
16241 case ALTIVEC_BUILTIN_VADDFP:
16242 case VSX_BUILTIN_XVADDDP:
16243 arg0 = gimple_call_arg (stmt, 0);
16244 arg1 = gimple_call_arg (stmt, 1);
16245 lhs = gimple_call_lhs (stmt);
16246 g = gimple_build_assign (lhs, PLUS_EXPR, arg0, arg1);
16247 gimple_set_location (g, gimple_location (stmt));
16248 gsi_replace (gsi, g, true);
16250 /* Flavors of vec_sub. We deliberately don't expand
16251 P8V_BUILTIN_VSUBUQM. */
16252 case ALTIVEC_BUILTIN_VSUBUBM:
16253 case ALTIVEC_BUILTIN_VSUBUHM:
16254 case ALTIVEC_BUILTIN_VSUBUWM:
16255 case P8V_BUILTIN_VSUBUDM:
16256 case ALTIVEC_BUILTIN_VSUBFP:
16257 case VSX_BUILTIN_XVSUBDP:
16258 arg0 = gimple_call_arg (stmt, 0);
16259 arg1 = gimple_call_arg (stmt, 1);
16260 lhs = gimple_call_lhs (stmt);
16261 g = gimple_build_assign (lhs, MINUS_EXPR, arg0, arg1);
16262 gimple_set_location (g, gimple_location (stmt));
16263 gsi_replace (gsi, g, true);
16265 case VSX_BUILTIN_XVMULSP:
16266 case VSX_BUILTIN_XVMULDP:
16267 arg0 = gimple_call_arg (stmt, 0);
16268 arg1 = gimple_call_arg (stmt, 1);
16269 lhs = gimple_call_lhs (stmt);
16270 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
16271 gimple_set_location (g, gimple_location (stmt));
16272 gsi_replace (gsi, g, true);
16274 /* Even element flavors of vec_mul (signed). */
16275 case ALTIVEC_BUILTIN_VMULESB:
16276 case ALTIVEC_BUILTIN_VMULESH:
16277 case ALTIVEC_BUILTIN_VMULESW:
16278 /* Even element flavors of vec_mul (unsigned). */
16279 case ALTIVEC_BUILTIN_VMULEUB:
16280 case ALTIVEC_BUILTIN_VMULEUH:
16281 case ALTIVEC_BUILTIN_VMULEUW:
16282 arg0 = gimple_call_arg (stmt, 0);
16283 arg1 = gimple_call_arg (stmt, 1);
16284 lhs = gimple_call_lhs (stmt);
16285 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
16286 gimple_set_location (g, gimple_location (stmt));
16287 gsi_replace (gsi, g, true);
16289 /* Odd element flavors of vec_mul (signed). */
16290 case ALTIVEC_BUILTIN_VMULOSB:
16291 case ALTIVEC_BUILTIN_VMULOSH:
16292 case ALTIVEC_BUILTIN_VMULOSW:
16293 /* Odd element flavors of vec_mul (unsigned). */
16294 case ALTIVEC_BUILTIN_VMULOUB:
16295 case ALTIVEC_BUILTIN_VMULOUH:
16296 case ALTIVEC_BUILTIN_VMULOUW:
16297 arg0 = gimple_call_arg (stmt, 0);
16298 arg1 = gimple_call_arg (stmt, 1);
16299 lhs = gimple_call_lhs (stmt);
16300 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
16301 gimple_set_location (g, gimple_location (stmt));
16302 gsi_replace (gsi, g, true);
16304 /* Flavors of vec_div (Integer). */
16305 case VSX_BUILTIN_DIV_V2DI:
16306 case VSX_BUILTIN_UDIV_V2DI:
16307 arg0 = gimple_call_arg (stmt, 0);
16308 arg1 = gimple_call_arg (stmt, 1);
16309 lhs = gimple_call_lhs (stmt);
16310 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
16311 gimple_set_location (g, gimple_location (stmt));
16312 gsi_replace (gsi, g, true);
16314 /* Flavors of vec_div (Float). */
16315 case VSX_BUILTIN_XVDIVSP:
16316 case VSX_BUILTIN_XVDIVDP:
16317 arg0 = gimple_call_arg (stmt, 0);
16318 arg1 = gimple_call_arg (stmt, 1);
16319 lhs = gimple_call_lhs (stmt);
16320 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
16321 gimple_set_location (g, gimple_location (stmt));
16322 gsi_replace (gsi, g, true);
16324 /* Flavors of vec_and. */
16325 case ALTIVEC_BUILTIN_VAND:
16326 arg0 = gimple_call_arg (stmt, 0);
16327 arg1 = gimple_call_arg (stmt, 1);
16328 lhs = gimple_call_lhs (stmt);
16329 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
16330 gimple_set_location (g, gimple_location (stmt));
16331 gsi_replace (gsi, g, true);
16333 /* Flavors of vec_andc. */
16334 case ALTIVEC_BUILTIN_VANDC:
16335 arg0 = gimple_call_arg (stmt, 0);
16336 arg1 = gimple_call_arg (stmt, 1);
16337 lhs = gimple_call_lhs (stmt);
16338 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16339 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
16340 gimple_set_location (g, gimple_location (stmt));
16341 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16342 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
16343 gimple_set_location (g, gimple_location (stmt));
16344 gsi_replace (gsi, g, true);
16346 /* Flavors of vec_nand. */
16347 case P8V_BUILTIN_VEC_NAND:
16348 case P8V_BUILTIN_NAND_V16QI:
16349 case P8V_BUILTIN_NAND_V8HI:
16350 case P8V_BUILTIN_NAND_V4SI:
16351 case P8V_BUILTIN_NAND_V4SF:
16352 case P8V_BUILTIN_NAND_V2DF:
16353 case P8V_BUILTIN_NAND_V2DI:
16354 arg0 = gimple_call_arg (stmt, 0);
16355 arg1 = gimple_call_arg (stmt, 1);
16356 lhs = gimple_call_lhs (stmt);
16357 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16358 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
16359 gimple_set_location (g, gimple_location (stmt));
16360 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16361 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16362 gimple_set_location (g, gimple_location (stmt));
16363 gsi_replace (gsi, g, true);
16365 /* Flavors of vec_or. */
16366 case ALTIVEC_BUILTIN_VOR:
16367 arg0 = gimple_call_arg (stmt, 0);
16368 arg1 = gimple_call_arg (stmt, 1);
16369 lhs = gimple_call_lhs (stmt);
16370 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
16371 gimple_set_location (g, gimple_location (stmt));
16372 gsi_replace (gsi, g, true);
16374 /* flavors of vec_orc. */
16375 case P8V_BUILTIN_ORC_V16QI:
16376 case P8V_BUILTIN_ORC_V8HI:
16377 case P8V_BUILTIN_ORC_V4SI:
16378 case P8V_BUILTIN_ORC_V4SF:
16379 case P8V_BUILTIN_ORC_V2DF:
16380 case P8V_BUILTIN_ORC_V2DI:
16381 arg0 = gimple_call_arg (stmt, 0);
16382 arg1 = gimple_call_arg (stmt, 1);
16383 lhs = gimple_call_lhs (stmt);
16384 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16385 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
16386 gimple_set_location (g, gimple_location (stmt));
16387 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16388 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
16389 gimple_set_location (g, gimple_location (stmt));
16390 gsi_replace (gsi, g, true);
16392 /* Flavors of vec_xor. */
16393 case ALTIVEC_BUILTIN_VXOR:
16394 arg0 = gimple_call_arg (stmt, 0);
16395 arg1 = gimple_call_arg (stmt, 1);
16396 lhs = gimple_call_lhs (stmt);
16397 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
16398 gimple_set_location (g, gimple_location (stmt));
16399 gsi_replace (gsi, g, true);
16401 /* Flavors of vec_nor. */
16402 case ALTIVEC_BUILTIN_VNOR:
16403 arg0 = gimple_call_arg (stmt, 0);
16404 arg1 = gimple_call_arg (stmt, 1);
16405 lhs = gimple_call_lhs (stmt);
16406 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16407 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
16408 gimple_set_location (g, gimple_location (stmt));
16409 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16410 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16411 gimple_set_location (g, gimple_location (stmt));
16412 gsi_replace (gsi, g, true);
16414 /* flavors of vec_abs. */
16415 case ALTIVEC_BUILTIN_ABS_V16QI:
16416 case ALTIVEC_BUILTIN_ABS_V8HI:
16417 case ALTIVEC_BUILTIN_ABS_V4SI:
16418 case ALTIVEC_BUILTIN_ABS_V4SF:
16419 case P8V_BUILTIN_ABS_V2DI:
16420 case VSX_BUILTIN_XVABSDP:
16421 arg0 = gimple_call_arg (stmt, 0);
16422 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
16423 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
16425 lhs = gimple_call_lhs (stmt);
16426 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
16427 gimple_set_location (g, gimple_location (stmt));
16428 gsi_replace (gsi, g, true);
16430 /* flavors of vec_min. */
16431 case VSX_BUILTIN_XVMINDP:
16432 case P8V_BUILTIN_VMINSD:
16433 case P8V_BUILTIN_VMINUD:
16434 case ALTIVEC_BUILTIN_VMINSB:
16435 case ALTIVEC_BUILTIN_VMINSH:
16436 case ALTIVEC_BUILTIN_VMINSW:
16437 case ALTIVEC_BUILTIN_VMINUB:
16438 case ALTIVEC_BUILTIN_VMINUH:
16439 case ALTIVEC_BUILTIN_VMINUW:
16440 case ALTIVEC_BUILTIN_VMINFP:
16441 arg0 = gimple_call_arg (stmt, 0);
16442 arg1 = gimple_call_arg (stmt, 1);
16443 lhs = gimple_call_lhs (stmt);
16444 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
16445 gimple_set_location (g, gimple_location (stmt));
16446 gsi_replace (gsi, g, true);
16448 /* flavors of vec_max. */
16449 case VSX_BUILTIN_XVMAXDP:
16450 case P8V_BUILTIN_VMAXSD:
16451 case P8V_BUILTIN_VMAXUD:
16452 case ALTIVEC_BUILTIN_VMAXSB:
16453 case ALTIVEC_BUILTIN_VMAXSH:
16454 case ALTIVEC_BUILTIN_VMAXSW:
16455 case ALTIVEC_BUILTIN_VMAXUB:
16456 case ALTIVEC_BUILTIN_VMAXUH:
16457 case ALTIVEC_BUILTIN_VMAXUW:
16458 case ALTIVEC_BUILTIN_VMAXFP:
16459 arg0 = gimple_call_arg (stmt, 0);
16460 arg1 = gimple_call_arg (stmt, 1);
16461 lhs = gimple_call_lhs (stmt);
16462 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
16463 gimple_set_location (g, gimple_location (stmt));
16464 gsi_replace (gsi, g, true);
16466 /* Flavors of vec_eqv. */
16467 case P8V_BUILTIN_EQV_V16QI:
16468 case P8V_BUILTIN_EQV_V8HI:
16469 case P8V_BUILTIN_EQV_V4SI:
16470 case P8V_BUILTIN_EQV_V4SF:
16471 case P8V_BUILTIN_EQV_V2DF:
16472 case P8V_BUILTIN_EQV_V2DI:
16473 arg0 = gimple_call_arg (stmt, 0);
16474 arg1 = gimple_call_arg (stmt, 1);
16475 lhs = gimple_call_lhs (stmt);
16476 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16477 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
16478 gimple_set_location (g, gimple_location (stmt));
16479 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16480 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16481 gimple_set_location (g, gimple_location (stmt));
16482 gsi_replace (gsi, g, true);
16484 /* Flavors of vec_rotate_left. */
16485 case ALTIVEC_BUILTIN_VRLB:
16486 case ALTIVEC_BUILTIN_VRLH:
16487 case ALTIVEC_BUILTIN_VRLW:
16488 case P8V_BUILTIN_VRLD:
16489 arg0 = gimple_call_arg (stmt, 0);
16490 arg1 = gimple_call_arg (stmt, 1);
16491 lhs = gimple_call_lhs (stmt);
16492 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
16493 gimple_set_location (g, gimple_location (stmt));
16494 gsi_replace (gsi, g, true);
16496 /* Flavors of vector shift right algebraic.
16497 vec_sra{b,h,w} -> vsra{b,h,w}. */
16498 case ALTIVEC_BUILTIN_VSRAB:
16499 case ALTIVEC_BUILTIN_VSRAH:
16500 case ALTIVEC_BUILTIN_VSRAW:
16501 case P8V_BUILTIN_VSRAD:
16502 arg0 = gimple_call_arg (stmt, 0);
16503 arg1 = gimple_call_arg (stmt, 1);
16504 lhs = gimple_call_lhs (stmt);
16505 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
16506 gimple_set_location (g, gimple_location (stmt));
16507 gsi_replace (gsi, g, true);
16509 /* Flavors of vector shift left.
16510 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
16511 case ALTIVEC_BUILTIN_VSLB:
16512 case ALTIVEC_BUILTIN_VSLH:
16513 case ALTIVEC_BUILTIN_VSLW:
16514 case P8V_BUILTIN_VSLD:
16515 arg0 = gimple_call_arg (stmt, 0);
16516 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
16517 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
16519 arg1 = gimple_call_arg (stmt, 1);
16520 lhs = gimple_call_lhs (stmt);
16521 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1);
16522 gimple_set_location (g, gimple_location (stmt));
16523 gsi_replace (gsi, g, true);
16525 /* Flavors of vector shift right. */
16526 case ALTIVEC_BUILTIN_VSRB:
16527 case ALTIVEC_BUILTIN_VSRH:
16528 case ALTIVEC_BUILTIN_VSRW:
16529 case P8V_BUILTIN_VSRD:
16531 arg0 = gimple_call_arg (stmt, 0);
16532 arg1 = gimple_call_arg (stmt, 1);
16533 lhs = gimple_call_lhs (stmt);
16534 gimple_seq stmts = NULL;
16535 /* Convert arg0 to unsigned. */
16537 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
16538 unsigned_type_for (TREE_TYPE (arg0)), arg0);
16540 = gimple_build (&stmts, RSHIFT_EXPR,
16541 TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1);
16542 /* Convert result back to the lhs type. */
16543 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
16544 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16545 update_call_from_tree (gsi, res);
16548 /* Vector loads. */
16549 case ALTIVEC_BUILTIN_LVX_V16QI:
16550 case ALTIVEC_BUILTIN_LVX_V8HI:
16551 case ALTIVEC_BUILTIN_LVX_V4SI:
16552 case ALTIVEC_BUILTIN_LVX_V4SF:
16553 case ALTIVEC_BUILTIN_LVX_V2DI:
16554 case ALTIVEC_BUILTIN_LVX_V2DF:
16556 arg0 = gimple_call_arg (stmt, 0); // offset
16557 arg1 = gimple_call_arg (stmt, 1); // address
16558 /* Do not fold for -maltivec=be on LE targets. */
16559 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16561 lhs = gimple_call_lhs (stmt);
16562 location_t loc = gimple_location (stmt);
16563 /* Since arg1 may be cast to a different type, just use ptr_type_node
16564 here instead of trying to enforce TBAA on pointer types. */
16565 tree arg1_type = ptr_type_node;
16566 tree lhs_type = TREE_TYPE (lhs);
16567 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
16568 the tree using the value from arg0. The resulting type will match
16569 the type of arg1. */
16570 gimple_seq stmts = NULL;
16571 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
16572 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
16573 arg1_type, arg1, temp_offset);
16574 /* Mask off any lower bits from the address. */
16575 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
16576 arg1_type, temp_addr,
16577 build_int_cst (arg1_type, -16));
16578 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16579 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
16580 take an offset, but since we've already incorporated the offset
16581 above, here we just pass in a zero. */
16583 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
16584 build_int_cst (arg1_type, 0)));
16585 gimple_set_location (g, loc);
16586 gsi_replace (gsi, g, true);
16589 /* Vector stores. */
16590 case ALTIVEC_BUILTIN_STVX_V16QI:
16591 case ALTIVEC_BUILTIN_STVX_V8HI:
16592 case ALTIVEC_BUILTIN_STVX_V4SI:
16593 case ALTIVEC_BUILTIN_STVX_V4SF:
16594 case ALTIVEC_BUILTIN_STVX_V2DI:
16595 case ALTIVEC_BUILTIN_STVX_V2DF:
16597 /* Do not fold for -maltivec=be on LE targets. */
16598 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16600 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
16601 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
16602 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
16603 location_t loc = gimple_location (stmt);
16604 tree arg0_type = TREE_TYPE (arg0);
16605 /* Use ptr_type_node (no TBAA) for the arg2_type.
16606 FIXME: (Richard) "A proper fix would be to transition this type as
16607 seen from the frontend to GIMPLE, for example in a similar way we
16608 do for MEM_REFs by piggy-backing that on an extra argument, a
16609 constant zero pointer of the alias pointer type to use (which would
16610 also serve as a type indicator of the store itself). I'd use a
16611 target specific internal function for this (not sure if we can have
16612 those target specific, but I guess if it's folded away then that's
16613 fine) and get away with the overload set." */
16614 tree arg2_type = ptr_type_node;
16615 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
16616 the tree using the value from arg0. The resulting type will match
16617 the type of arg2. */
16618 gimple_seq stmts = NULL;
16619 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
16620 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
16621 arg2_type, arg2, temp_offset);
16622 /* Mask off any lower bits from the address. */
16623 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
16624 arg2_type, temp_addr,
16625 build_int_cst (arg2_type, -16));
16626 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16627 /* The desired gimple result should be similar to:
16628 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
16630 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
16631 build_int_cst (arg2_type, 0)), arg0);
16632 gimple_set_location (g, loc);
16633 gsi_replace (gsi, g, true);
16637 /* Vector Fused multiply-add (fma). */
16638 case ALTIVEC_BUILTIN_VMADDFP:
16639 case VSX_BUILTIN_XVMADDDP:
16640 case ALTIVEC_BUILTIN_VMLADDUHM:
16642 arg0 = gimple_call_arg (stmt, 0);
16643 arg1 = gimple_call_arg (stmt, 1);
16644 tree arg2 = gimple_call_arg (stmt, 2);
16645 lhs = gimple_call_lhs (stmt);
16646 gimple *g = gimple_build_assign (lhs, FMA_EXPR, arg0, arg1, arg2);
16647 gimple_set_location (g, gimple_location (stmt));
16648 gsi_replace (gsi, g, true);
16652 /* Vector compares; EQ, NE, GE, GT, LE. */
16653 case ALTIVEC_BUILTIN_VCMPEQUB:
16654 case ALTIVEC_BUILTIN_VCMPEQUH:
16655 case ALTIVEC_BUILTIN_VCMPEQUW:
16656 case P8V_BUILTIN_VCMPEQUD:
16657 fold_compare_helper (gsi, EQ_EXPR, stmt);
16660 case P9V_BUILTIN_CMPNEB:
16661 case P9V_BUILTIN_CMPNEH:
16662 case P9V_BUILTIN_CMPNEW:
16663 fold_compare_helper (gsi, NE_EXPR, stmt);
16666 case VSX_BUILTIN_CMPGE_16QI:
16667 case VSX_BUILTIN_CMPGE_U16QI:
16668 case VSX_BUILTIN_CMPGE_8HI:
16669 case VSX_BUILTIN_CMPGE_U8HI:
16670 case VSX_BUILTIN_CMPGE_4SI:
16671 case VSX_BUILTIN_CMPGE_U4SI:
16672 case VSX_BUILTIN_CMPGE_2DI:
16673 case VSX_BUILTIN_CMPGE_U2DI:
16674 fold_compare_helper (gsi, GE_EXPR, stmt);
16677 case ALTIVEC_BUILTIN_VCMPGTSB:
16678 case ALTIVEC_BUILTIN_VCMPGTUB:
16679 case ALTIVEC_BUILTIN_VCMPGTSH:
16680 case ALTIVEC_BUILTIN_VCMPGTUH:
16681 case ALTIVEC_BUILTIN_VCMPGTSW:
16682 case ALTIVEC_BUILTIN_VCMPGTUW:
16683 case P8V_BUILTIN_VCMPGTUD:
16684 case P8V_BUILTIN_VCMPGTSD:
16685 fold_compare_helper (gsi, GT_EXPR, stmt);
16688 case VSX_BUILTIN_CMPLE_16QI:
16689 case VSX_BUILTIN_CMPLE_U16QI:
16690 case VSX_BUILTIN_CMPLE_8HI:
16691 case VSX_BUILTIN_CMPLE_U8HI:
16692 case VSX_BUILTIN_CMPLE_4SI:
16693 case VSX_BUILTIN_CMPLE_U4SI:
16694 case VSX_BUILTIN_CMPLE_2DI:
16695 case VSX_BUILTIN_CMPLE_U2DI:
16696 fold_compare_helper (gsi, LE_EXPR, stmt);
16699 /* flavors of vec_splat_[us]{8,16,32}. */
16700 case ALTIVEC_BUILTIN_VSPLTISB:
16701 case ALTIVEC_BUILTIN_VSPLTISH:
16702 case ALTIVEC_BUILTIN_VSPLTISW:
16704 arg0 = gimple_call_arg (stmt, 0);
16705 lhs = gimple_call_lhs (stmt);
16706 /* Only fold the vec_splat_*() if arg0 is constant. */
16707 if (TREE_CODE (arg0) != INTEGER_CST)
16709 gimple_seq stmts = NULL;
16710 location_t loc = gimple_location (stmt);
16711 tree splat_value = gimple_convert (&stmts, loc,
16712 TREE_TYPE (TREE_TYPE (lhs)), arg0);
16713 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16714 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
16715 g = gimple_build_assign (lhs, splat_tree);
16716 gimple_set_location (g, gimple_location (stmt));
16717 gsi_replace (gsi, g, true);
16721 /* vec_mergel (integrals). */
16722 case ALTIVEC_BUILTIN_VMRGLH:
16723 case ALTIVEC_BUILTIN_VMRGLW:
16724 case VSX_BUILTIN_XXMRGLW_4SI:
16725 case ALTIVEC_BUILTIN_VMRGLB:
16726 case VSX_BUILTIN_VEC_MERGEL_V2DI:
16727 /* Do not fold for -maltivec=be on LE targets. */
16728 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16730 fold_mergehl_helper (gsi, stmt, 1);
16732 /* vec_mergeh (integrals). */
16733 case ALTIVEC_BUILTIN_VMRGHH:
16734 case ALTIVEC_BUILTIN_VMRGHW:
16735 case VSX_BUILTIN_XXMRGHW_4SI:
16736 case ALTIVEC_BUILTIN_VMRGHB:
16737 case VSX_BUILTIN_VEC_MERGEH_V2DI:
16738 /* Do not fold for -maltivec=be on LE targets. */
16739 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16741 fold_mergehl_helper (gsi, stmt, 0);
16744 if (TARGET_DEBUG_BUILTIN)
16745 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
16746 fn_code, fn_name1, fn_name2);
16753 /* Expand an expression EXP that calls a built-in function,
16754 with result going to TARGET if that's convenient
16755 (and in mode MODE if that's convenient).
16756 SUBTARGET may be used as the target for computing one of EXP's operands.
16757 IGNORE is nonzero if the value is to be ignored. */
16760 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
16761 machine_mode mode ATTRIBUTE_UNUSED,
16762 int ignore ATTRIBUTE_UNUSED)
16764 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
16765 enum rs6000_builtins fcode
16766 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
16767 size_t uns_fcode = (size_t)fcode;
16768 const struct builtin_description *d;
16772 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
16773 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
16774 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
16776 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
16777 floating point type, depending on whether long double is the IBM extended
16778 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
16779 we only define one variant of the built-in function, and switch the code
16780 when defining it, rather than defining two built-ins and using the
16781 overload table in rs6000-c.c to switch between the two. If we don't have
16782 the proper assembler, don't do this switch because CODE_FOR_*kf* and
16783 CODE_FOR_*tf* will be CODE_FOR_nothing. */
16784 #ifdef HAVE_AS_POWER9
16785 if (FLOAT128_IEEE_P (TFmode))
16791 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
16792 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
16793 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
16794 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
16795 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
16796 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
16797 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
16798 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
16799 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
16800 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
16801 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
16802 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
16803 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
16807 if (TARGET_DEBUG_BUILTIN)
16809 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16810 const char *name2 = (icode != CODE_FOR_nothing)
16811 ? get_insn_name ((int) icode)
16815 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16817 default: name3 = "unknown"; break;
16818 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16819 case RS6000_BTC_UNARY: name3 = "unary"; break;
16820 case RS6000_BTC_BINARY: name3 = "binary"; break;
16821 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16822 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16823 case RS6000_BTC_ABS: name3 = "abs"; break;
16824 case RS6000_BTC_DST: name3 = "dst"; break;
16829 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16830 (name1) ? name1 : "---", fcode,
16831 (name2) ? name2 : "---", (int) icode,
16833 func_valid_p ? "" : ", not valid");
16838 rs6000_invalid_builtin (fcode);
16840 /* Given it is invalid, just generate a normal call. */
16841 return expand_call (exp, target, ignore);
16846 case RS6000_BUILTIN_RECIP:
16847 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16849 case RS6000_BUILTIN_RECIPF:
16850 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16852 case RS6000_BUILTIN_RSQRTF:
16853 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16855 case RS6000_BUILTIN_RSQRT:
16856 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16858 case POWER7_BUILTIN_BPERMD:
16859 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16860 ? CODE_FOR_bpermd_di
16861 : CODE_FOR_bpermd_si), exp, target);
16863 case RS6000_BUILTIN_GET_TB:
16864 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16867 case RS6000_BUILTIN_MFTB:
16868 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16869 ? CODE_FOR_rs6000_mftb_di
16870 : CODE_FOR_rs6000_mftb_si),
16873 case RS6000_BUILTIN_MFFS:
16874 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16876 case RS6000_BUILTIN_MTFSF:
16877 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16879 case RS6000_BUILTIN_CPU_INIT:
16880 case RS6000_BUILTIN_CPU_IS:
16881 case RS6000_BUILTIN_CPU_SUPPORTS:
16882 return cpu_expand_builtin (fcode, exp, target);
16884 case MISC_BUILTIN_SPEC_BARRIER:
16886 emit_insn (gen_rs6000_speculation_barrier ());
16890 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16891 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16893 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16894 : (int) CODE_FOR_altivec_lvsl_direct);
16895 machine_mode tmode = insn_data[icode2].operand[0].mode;
16896 machine_mode mode = insn_data[icode2].operand[1].mode;
16900 gcc_assert (TARGET_ALTIVEC);
16902 arg = CALL_EXPR_ARG (exp, 0);
16903 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16904 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16905 addr = memory_address (mode, op);
16906 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16910 /* For the load case need to negate the address. */
16911 op = gen_reg_rtx (GET_MODE (addr));
16912 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16914 op = gen_rtx_MEM (mode, op);
16917 || GET_MODE (target) != tmode
16918 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
16919 target = gen_reg_rtx (tmode);
16921 pat = GEN_FCN (icode2) (target, op);
16929 case ALTIVEC_BUILTIN_VCFUX:
16930 case ALTIVEC_BUILTIN_VCFSX:
16931 case ALTIVEC_BUILTIN_VCTUXS:
16932 case ALTIVEC_BUILTIN_VCTSXS:
16933 /* FIXME: There's got to be a nicer way to handle this case than
16934 constructing a new CALL_EXPR. */
16935 if (call_expr_nargs (exp) == 1)
16937 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16938 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16946 if (TARGET_ALTIVEC)
16948 ret = altivec_expand_builtin (exp, target, &success);
16953 if (TARGET_PAIRED_FLOAT)
16955 ret = paired_expand_builtin (exp, target, &success);
16962 ret = htm_expand_builtin (exp, target, &success);
16968 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16969 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16970 gcc_assert (attr == RS6000_BTC_UNARY
16971 || attr == RS6000_BTC_BINARY
16972 || attr == RS6000_BTC_TERNARY
16973 || attr == RS6000_BTC_SPECIAL);
16975 /* Handle simple unary operations. */
16977 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16978 if (d->code == fcode)
16979 return rs6000_expand_unop_builtin (icode, exp, target);
16981 /* Handle simple binary operations. */
16983 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16984 if (d->code == fcode)
16985 return rs6000_expand_binop_builtin (icode, exp, target);
16987 /* Handle simple ternary operations. */
16989 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16990 if (d->code == fcode)
16991 return rs6000_expand_ternop_builtin (icode, exp, target);
16993 /* Handle simple no-argument operations. */
16995 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
16996 if (d->code == fcode)
16997 return rs6000_expand_zeroop_builtin (icode, target);
16999 gcc_unreachable ();
17002 /* Create a builtin vector type with a name. Taking care not to give
17003 the canonical type a name. */
17006 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
17008 tree result = build_vector_type (elt_type, num_elts);
17010 /* Copy so we don't give the canonical type a name. */
17011 result = build_variant_type_copy (result);
17013 add_builtin_type (name, result);
17019 rs6000_init_builtins (void)
17025 if (TARGET_DEBUG_BUILTIN)
17026 fprintf (stderr, "rs6000_init_builtins%s%s%s\n",
17027 (TARGET_PAIRED_FLOAT) ? ", paired" : "",
17028 (TARGET_ALTIVEC) ? ", altivec" : "",
17029 (TARGET_VSX) ? ", vsx" : "");
17031 V2SI_type_node = build_vector_type (intSI_type_node, 2);
17032 V2SF_type_node = build_vector_type (float_type_node, 2);
17033 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
17034 : "__vector long long",
17035 intDI_type_node, 2);
17036 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
17037 V4SI_type_node = rs6000_vector_type ("__vector signed int",
17038 intSI_type_node, 4);
17039 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
17040 V8HI_type_node = rs6000_vector_type ("__vector signed short",
17041 intHI_type_node, 8);
17042 V16QI_type_node = rs6000_vector_type ("__vector signed char",
17043 intQI_type_node, 16);
17045 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
17046 unsigned_intQI_type_node, 16);
17047 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
17048 unsigned_intHI_type_node, 8);
17049 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
17050 unsigned_intSI_type_node, 4);
17051 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
17052 ? "__vector unsigned long"
17053 : "__vector unsigned long long",
17054 unsigned_intDI_type_node, 2);
17056 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
17057 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
17058 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
17059 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
17061 const_str_type_node
17062 = build_pointer_type (build_qualified_type (char_type_node,
17065 /* We use V1TI mode as a special container to hold __int128_t items that
17066 must live in VSX registers. */
17067 if (intTI_type_node)
17069 V1TI_type_node = rs6000_vector_type ("__vector __int128",
17070 intTI_type_node, 1);
17071 unsigned_V1TI_type_node
17072 = rs6000_vector_type ("__vector unsigned __int128",
17073 unsigned_intTI_type_node, 1);
17076 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
17077 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
17078 'vector unsigned short'. */
17080 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
17081 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
17082 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
17083 bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
17084 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
17086 long_integer_type_internal_node = long_integer_type_node;
17087 long_unsigned_type_internal_node = long_unsigned_type_node;
17088 long_long_integer_type_internal_node = long_long_integer_type_node;
17089 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
17090 intQI_type_internal_node = intQI_type_node;
17091 uintQI_type_internal_node = unsigned_intQI_type_node;
17092 intHI_type_internal_node = intHI_type_node;
17093 uintHI_type_internal_node = unsigned_intHI_type_node;
17094 intSI_type_internal_node = intSI_type_node;
17095 uintSI_type_internal_node = unsigned_intSI_type_node;
17096 intDI_type_internal_node = intDI_type_node;
17097 uintDI_type_internal_node = unsigned_intDI_type_node;
17098 intTI_type_internal_node = intTI_type_node;
17099 uintTI_type_internal_node = unsigned_intTI_type_node;
17100 float_type_internal_node = float_type_node;
17101 double_type_internal_node = double_type_node;
17102 long_double_type_internal_node = long_double_type_node;
17103 dfloat64_type_internal_node = dfloat64_type_node;
17104 dfloat128_type_internal_node = dfloat128_type_node;
17105 void_type_internal_node = void_type_node;
17107 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
17108 IFmode is the IBM extended 128-bit format that is a pair of doubles.
17109 TFmode will be either IEEE 128-bit floating point or the IBM double-double
17110 format that uses a pair of doubles, depending on the switches and
17113 If we don't support for either 128-bit IBM double double or IEEE 128-bit
17114 floating point, we need make sure the type is non-zero or else self-test
17115 fails during bootstrap.
17117 We don't register a built-in type for __ibm128 if the type is the same as
17118 long double. Instead we add a #define for __ibm128 in
17119 rs6000_cpu_cpp_builtins to long double.
17121 For IEEE 128-bit floating point, always create the type __ieee128. If the
17122 user used -mfloat128, rs6000-c.c will create a define from __float128 to
17124 if (TARGET_LONG_DOUBLE_128 && FLOAT128_IEEE_P (TFmode))
17126 ibm128_float_type_node = make_node (REAL_TYPE);
17127 TYPE_PRECISION (ibm128_float_type_node) = 128;
17128 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
17129 layout_type (ibm128_float_type_node);
17131 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
17135 ibm128_float_type_node = long_double_type_node;
17137 if (TARGET_FLOAT128_TYPE)
17139 ieee128_float_type_node = float128_type_node;
17140 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
17145 ieee128_float_type_node = long_double_type_node;
17147 /* Initialize the modes for builtin_function_type, mapping a machine mode to
17149 builtin_mode_to_type[QImode][0] = integer_type_node;
17150 builtin_mode_to_type[HImode][0] = integer_type_node;
17151 builtin_mode_to_type[SImode][0] = intSI_type_node;
17152 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
17153 builtin_mode_to_type[DImode][0] = intDI_type_node;
17154 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
17155 builtin_mode_to_type[TImode][0] = intTI_type_node;
17156 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
17157 builtin_mode_to_type[SFmode][0] = float_type_node;
17158 builtin_mode_to_type[DFmode][0] = double_type_node;
17159 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
17160 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
17161 builtin_mode_to_type[TFmode][0] = long_double_type_node;
17162 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
17163 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
17164 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
17165 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
17166 builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
17167 builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
17168 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
17169 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
17170 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
17171 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
17172 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
17173 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
17174 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
17175 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
17176 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
17177 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
17179 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
17180 TYPE_NAME (bool_char_type_node) = tdecl;
17182 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
17183 TYPE_NAME (bool_short_type_node) = tdecl;
17185 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
17186 TYPE_NAME (bool_int_type_node) = tdecl;
17188 tdecl = add_builtin_type ("__pixel", pixel_type_node);
17189 TYPE_NAME (pixel_type_node) = tdecl;
17191 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
17192 bool_char_type_node, 16);
17193 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
17194 bool_short_type_node, 8);
17195 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
17196 bool_int_type_node, 4);
17197 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
17198 ? "__vector __bool long"
17199 : "__vector __bool long long",
17200 bool_long_type_node, 2);
17201 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
17202 pixel_type_node, 8);
17204 /* Paired builtins are only available if you build a compiler with the
17205 appropriate options, so only create those builtins with the appropriate
17206 compiler option. Create Altivec and VSX builtins on machines with at
17207 least the general purpose extensions (970 and newer) to allow the use of
17208 the target attribute. */
17209 if (TARGET_PAIRED_FLOAT)
17210 paired_init_builtins ();
17211 if (TARGET_EXTRA_BUILTINS)
17212 altivec_init_builtins ();
17214 htm_init_builtins ();
17216 if (TARGET_EXTRA_BUILTINS || TARGET_PAIRED_FLOAT)
17217 rs6000_common_init_builtins ();
17219 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
17220 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
17221 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
17223 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
17224 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
17225 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
17227 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
17228 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
17229 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
17231 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
17232 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
17233 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
17235 mode = (TARGET_64BIT) ? DImode : SImode;
17236 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
17237 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
17238 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
17240 ftype = build_function_type_list (unsigned_intDI_type_node,
17242 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
17245 ftype = build_function_type_list (unsigned_intDI_type_node,
17248 ftype = build_function_type_list (unsigned_intSI_type_node,
17250 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
17252 ftype = build_function_type_list (double_type_node, NULL_TREE);
17253 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
17255 ftype = build_function_type_list (void_type_node,
17256 intSI_type_node, double_type_node,
17258 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
17260 ftype = build_function_type_list (void_type_node, NULL_TREE);
17261 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
17262 def_builtin ("__builtin_rs6000_speculation_barrier", ftype,
17263 MISC_BUILTIN_SPEC_BARRIER);
17265 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
17267 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
17268 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
17270 /* AIX libm provides clog as __clog. */
17271 if (TARGET_XCOFF &&
17272 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
17273 set_user_assembler_name (tdecl, "__clog");
17275 #ifdef SUBTARGET_INIT_BUILTINS
17276 SUBTARGET_INIT_BUILTINS;
17280 /* Returns the rs6000 builtin decl for CODE. */
17283 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
17285 HOST_WIDE_INT fnmask;
17287 if (code >= RS6000_BUILTIN_COUNT)
17288 return error_mark_node;
17290 fnmask = rs6000_builtin_info[code].mask;
17291 if ((fnmask & rs6000_builtin_mask) != fnmask)
17293 rs6000_invalid_builtin ((enum rs6000_builtins)code);
17294 return error_mark_node;
17297 return rs6000_builtin_decls[code];
17301 paired_init_builtins (void)
17303 const struct builtin_description *d;
17305 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17307 tree int_ftype_int_v2sf_v2sf
17308 = build_function_type_list (integer_type_node,
17313 tree pcfloat_type_node =
17314 build_pointer_type (build_qualified_type
17315 (float_type_node, TYPE_QUAL_CONST));
17317 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
17318 long_integer_type_node,
17321 tree void_ftype_v2sf_long_pcfloat =
17322 build_function_type_list (void_type_node,
17324 long_integer_type_node,
17329 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
17330 PAIRED_BUILTIN_LX);
17333 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
17334 PAIRED_BUILTIN_STX);
17337 d = bdesc_paired_preds;
17338 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
17341 HOST_WIDE_INT mask = d->mask;
17343 if ((mask & builtin_mask) != mask)
17345 if (TARGET_DEBUG_BUILTIN)
17346 fprintf (stderr, "paired_init_builtins, skip predicate %s\n",
17351 /* Cannot define builtin if the instruction is disabled. */
17352 gcc_assert (d->icode != CODE_FOR_nothing);
17354 if (TARGET_DEBUG_BUILTIN)
17355 fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
17356 (int)i, get_insn_name (d->icode), (int)d->icode,
17357 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
17359 switch (insn_data[d->icode].operand[1].mode)
17362 type = int_ftype_int_v2sf_v2sf;
17365 gcc_unreachable ();
17368 def_builtin (d->name, type, d->code);
17373 altivec_init_builtins (void)
17375 const struct builtin_description *d;
17379 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17381 tree pvoid_type_node = build_pointer_type (void_type_node);
17383 tree pcvoid_type_node
17384 = build_pointer_type (build_qualified_type (void_type_node,
17387 tree int_ftype_opaque
17388 = build_function_type_list (integer_type_node,
17389 opaque_V4SI_type_node, NULL_TREE);
17390 tree opaque_ftype_opaque
17391 = build_function_type_list (integer_type_node, NULL_TREE);
17392 tree opaque_ftype_opaque_int
17393 = build_function_type_list (opaque_V4SI_type_node,
17394 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
17395 tree opaque_ftype_opaque_opaque_int
17396 = build_function_type_list (opaque_V4SI_type_node,
17397 opaque_V4SI_type_node, opaque_V4SI_type_node,
17398 integer_type_node, NULL_TREE);
17399 tree opaque_ftype_opaque_opaque_opaque
17400 = build_function_type_list (opaque_V4SI_type_node,
17401 opaque_V4SI_type_node, opaque_V4SI_type_node,
17402 opaque_V4SI_type_node, NULL_TREE);
17403 tree opaque_ftype_opaque_opaque
17404 = build_function_type_list (opaque_V4SI_type_node,
17405 opaque_V4SI_type_node, opaque_V4SI_type_node,
17407 tree int_ftype_int_opaque_opaque
17408 = build_function_type_list (integer_type_node,
17409 integer_type_node, opaque_V4SI_type_node,
17410 opaque_V4SI_type_node, NULL_TREE);
17411 tree int_ftype_int_v4si_v4si
17412 = build_function_type_list (integer_type_node,
17413 integer_type_node, V4SI_type_node,
17414 V4SI_type_node, NULL_TREE);
17415 tree int_ftype_int_v2di_v2di
17416 = build_function_type_list (integer_type_node,
17417 integer_type_node, V2DI_type_node,
17418 V2DI_type_node, NULL_TREE);
17419 tree void_ftype_v4si
17420 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
17421 tree v8hi_ftype_void
17422 = build_function_type_list (V8HI_type_node, NULL_TREE);
17423 tree void_ftype_void
17424 = build_function_type_list (void_type_node, NULL_TREE);
17425 tree void_ftype_int
17426 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
17428 tree opaque_ftype_long_pcvoid
17429 = build_function_type_list (opaque_V4SI_type_node,
17430 long_integer_type_node, pcvoid_type_node,
17432 tree v16qi_ftype_long_pcvoid
17433 = build_function_type_list (V16QI_type_node,
17434 long_integer_type_node, pcvoid_type_node,
17436 tree v8hi_ftype_long_pcvoid
17437 = build_function_type_list (V8HI_type_node,
17438 long_integer_type_node, pcvoid_type_node,
17440 tree v4si_ftype_long_pcvoid
17441 = build_function_type_list (V4SI_type_node,
17442 long_integer_type_node, pcvoid_type_node,
17444 tree v4sf_ftype_long_pcvoid
17445 = build_function_type_list (V4SF_type_node,
17446 long_integer_type_node, pcvoid_type_node,
17448 tree v2df_ftype_long_pcvoid
17449 = build_function_type_list (V2DF_type_node,
17450 long_integer_type_node, pcvoid_type_node,
17452 tree v2di_ftype_long_pcvoid
17453 = build_function_type_list (V2DI_type_node,
17454 long_integer_type_node, pcvoid_type_node,
17457 tree void_ftype_opaque_long_pvoid
17458 = build_function_type_list (void_type_node,
17459 opaque_V4SI_type_node, long_integer_type_node,
17460 pvoid_type_node, NULL_TREE);
17461 tree void_ftype_v4si_long_pvoid
17462 = build_function_type_list (void_type_node,
17463 V4SI_type_node, long_integer_type_node,
17464 pvoid_type_node, NULL_TREE);
17465 tree void_ftype_v16qi_long_pvoid
17466 = build_function_type_list (void_type_node,
17467 V16QI_type_node, long_integer_type_node,
17468 pvoid_type_node, NULL_TREE);
17470 tree void_ftype_v16qi_pvoid_long
17471 = build_function_type_list (void_type_node,
17472 V16QI_type_node, pvoid_type_node,
17473 long_integer_type_node, NULL_TREE);
17475 tree void_ftype_v8hi_long_pvoid
17476 = build_function_type_list (void_type_node,
17477 V8HI_type_node, long_integer_type_node,
17478 pvoid_type_node, NULL_TREE);
17479 tree void_ftype_v4sf_long_pvoid
17480 = build_function_type_list (void_type_node,
17481 V4SF_type_node, long_integer_type_node,
17482 pvoid_type_node, NULL_TREE);
17483 tree void_ftype_v2df_long_pvoid
17484 = build_function_type_list (void_type_node,
17485 V2DF_type_node, long_integer_type_node,
17486 pvoid_type_node, NULL_TREE);
17487 tree void_ftype_v1ti_long_pvoid
17488 = build_function_type_list (void_type_node,
17489 V1TI_type_node, long_integer_type_node,
17490 pvoid_type_node, NULL_TREE);
17491 tree void_ftype_v2di_long_pvoid
17492 = build_function_type_list (void_type_node,
17493 V2DI_type_node, long_integer_type_node,
17494 pvoid_type_node, NULL_TREE);
17495 tree int_ftype_int_v8hi_v8hi
17496 = build_function_type_list (integer_type_node,
17497 integer_type_node, V8HI_type_node,
17498 V8HI_type_node, NULL_TREE);
17499 tree int_ftype_int_v16qi_v16qi
17500 = build_function_type_list (integer_type_node,
17501 integer_type_node, V16QI_type_node,
17502 V16QI_type_node, NULL_TREE);
17503 tree int_ftype_int_v4sf_v4sf
17504 = build_function_type_list (integer_type_node,
17505 integer_type_node, V4SF_type_node,
17506 V4SF_type_node, NULL_TREE);
17507 tree int_ftype_int_v2df_v2df
17508 = build_function_type_list (integer_type_node,
17509 integer_type_node, V2DF_type_node,
17510 V2DF_type_node, NULL_TREE);
17511 tree v2di_ftype_v2di
17512 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
17513 tree v4si_ftype_v4si
17514 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
17515 tree v8hi_ftype_v8hi
17516 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
17517 tree v16qi_ftype_v16qi
17518 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
17519 tree v4sf_ftype_v4sf
17520 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
17521 tree v2df_ftype_v2df
17522 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
17523 tree void_ftype_pcvoid_int_int
17524 = build_function_type_list (void_type_node,
17525 pcvoid_type_node, integer_type_node,
17526 integer_type_node, NULL_TREE);
17528 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
17529 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
17530 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
17531 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
17532 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
17533 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
17534 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
17535 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
17536 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
17537 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
17538 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
17539 ALTIVEC_BUILTIN_LVXL_V2DF);
17540 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
17541 ALTIVEC_BUILTIN_LVXL_V2DI);
17542 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
17543 ALTIVEC_BUILTIN_LVXL_V4SF);
17544 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
17545 ALTIVEC_BUILTIN_LVXL_V4SI);
17546 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
17547 ALTIVEC_BUILTIN_LVXL_V8HI);
17548 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
17549 ALTIVEC_BUILTIN_LVXL_V16QI);
17550 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
17551 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
17552 ALTIVEC_BUILTIN_LVX_V2DF);
17553 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
17554 ALTIVEC_BUILTIN_LVX_V2DI);
17555 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
17556 ALTIVEC_BUILTIN_LVX_V4SF);
17557 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
17558 ALTIVEC_BUILTIN_LVX_V4SI);
17559 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
17560 ALTIVEC_BUILTIN_LVX_V8HI);
17561 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
17562 ALTIVEC_BUILTIN_LVX_V16QI);
17563 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
17564 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
17565 ALTIVEC_BUILTIN_STVX_V2DF);
17566 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
17567 ALTIVEC_BUILTIN_STVX_V2DI);
17568 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
17569 ALTIVEC_BUILTIN_STVX_V4SF);
17570 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
17571 ALTIVEC_BUILTIN_STVX_V4SI);
17572 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
17573 ALTIVEC_BUILTIN_STVX_V8HI);
17574 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
17575 ALTIVEC_BUILTIN_STVX_V16QI);
17576 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
17577 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
17578 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
17579 ALTIVEC_BUILTIN_STVXL_V2DF);
17580 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
17581 ALTIVEC_BUILTIN_STVXL_V2DI);
17582 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
17583 ALTIVEC_BUILTIN_STVXL_V4SF);
17584 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
17585 ALTIVEC_BUILTIN_STVXL_V4SI);
17586 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
17587 ALTIVEC_BUILTIN_STVXL_V8HI);
17588 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
17589 ALTIVEC_BUILTIN_STVXL_V16QI);
17590 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
17591 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
17592 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
17593 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
17594 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
17595 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
17596 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
17597 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
17598 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
17599 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
17600 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
17601 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
17602 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
17603 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
17604 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
17605 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
17607 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
17608 VSX_BUILTIN_LXVD2X_V2DF);
17609 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
17610 VSX_BUILTIN_LXVD2X_V2DI);
17611 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
17612 VSX_BUILTIN_LXVW4X_V4SF);
17613 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
17614 VSX_BUILTIN_LXVW4X_V4SI);
17615 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
17616 VSX_BUILTIN_LXVW4X_V8HI);
17617 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
17618 VSX_BUILTIN_LXVW4X_V16QI);
17619 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
17620 VSX_BUILTIN_STXVD2X_V2DF);
17621 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
17622 VSX_BUILTIN_STXVD2X_V2DI);
17623 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
17624 VSX_BUILTIN_STXVW4X_V4SF);
17625 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
17626 VSX_BUILTIN_STXVW4X_V4SI);
17627 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
17628 VSX_BUILTIN_STXVW4X_V8HI);
17629 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
17630 VSX_BUILTIN_STXVW4X_V16QI);
17632 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
17633 VSX_BUILTIN_LD_ELEMREV_V2DF);
17634 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
17635 VSX_BUILTIN_LD_ELEMREV_V2DI);
17636 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
17637 VSX_BUILTIN_LD_ELEMREV_V4SF);
17638 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
17639 VSX_BUILTIN_LD_ELEMREV_V4SI);
17640 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
17641 VSX_BUILTIN_LD_ELEMREV_V8HI);
17642 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
17643 VSX_BUILTIN_LD_ELEMREV_V16QI);
17644 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
17645 VSX_BUILTIN_ST_ELEMREV_V2DF);
17646 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
17647 VSX_BUILTIN_ST_ELEMREV_V1TI);
17648 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
17649 VSX_BUILTIN_ST_ELEMREV_V2DI);
17650 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
17651 VSX_BUILTIN_ST_ELEMREV_V4SF);
17652 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
17653 VSX_BUILTIN_ST_ELEMREV_V4SI);
17654 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
17655 VSX_BUILTIN_ST_ELEMREV_V8HI);
17656 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
17657 VSX_BUILTIN_ST_ELEMREV_V16QI);
17659 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
17660 VSX_BUILTIN_VEC_LD);
17661 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
17662 VSX_BUILTIN_VEC_ST);
17663 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
17664 VSX_BUILTIN_VEC_XL);
17665 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
17666 VSX_BUILTIN_VEC_XL_BE);
17667 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
17668 VSX_BUILTIN_VEC_XST);
17669 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
17670 VSX_BUILTIN_VEC_XST_BE);
17672 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
17673 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
17674 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
17676 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
17677 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
17678 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
17679 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
17680 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
17681 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
17682 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
17683 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
17684 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
17685 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
17686 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
17687 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
17689 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
17690 ALTIVEC_BUILTIN_VEC_ADDE);
17691 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
17692 ALTIVEC_BUILTIN_VEC_ADDEC);
17693 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
17694 ALTIVEC_BUILTIN_VEC_CMPNE);
17695 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
17696 ALTIVEC_BUILTIN_VEC_MUL);
17697 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
17698 ALTIVEC_BUILTIN_VEC_SUBE);
17699 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
17700 ALTIVEC_BUILTIN_VEC_SUBEC);
17702 /* Cell builtins. */
17703 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
17704 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
17705 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
17706 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
17708 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
17709 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
17710 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
17711 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
17713 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
17714 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
17715 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
17716 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
17718 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
17719 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
17720 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
17721 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
17723 if (TARGET_P9_VECTOR)
17725 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
17726 P9V_BUILTIN_STXVL);
17727 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
17728 P9V_BUILTIN_XST_LEN_R);
17731 /* Add the DST variants. */
17733 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
17735 HOST_WIDE_INT mask = d->mask;
17737 /* It is expected that these dst built-in functions may have
17738 d->icode equal to CODE_FOR_nothing. */
17739 if ((mask & builtin_mask) != mask)
17741 if (TARGET_DEBUG_BUILTIN)
17742 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
17746 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
17749 /* Initialize the predicates. */
17750 d = bdesc_altivec_preds;
17751 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
17753 machine_mode mode1;
17755 HOST_WIDE_INT mask = d->mask;
17757 if ((mask & builtin_mask) != mask)
17759 if (TARGET_DEBUG_BUILTIN)
17760 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
17765 if (rs6000_overloaded_builtin_p (d->code))
17769 /* Cannot define builtin if the instruction is disabled. */
17770 gcc_assert (d->icode != CODE_FOR_nothing);
17771 mode1 = insn_data[d->icode].operand[1].mode;
17777 type = int_ftype_int_opaque_opaque;
17780 type = int_ftype_int_v2di_v2di;
17783 type = int_ftype_int_v4si_v4si;
17786 type = int_ftype_int_v8hi_v8hi;
17789 type = int_ftype_int_v16qi_v16qi;
17792 type = int_ftype_int_v4sf_v4sf;
17795 type = int_ftype_int_v2df_v2df;
17798 gcc_unreachable ();
17801 def_builtin (d->name, type, d->code);
17804 /* Initialize the abs* operators. */
17806 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
17808 machine_mode mode0;
17810 HOST_WIDE_INT mask = d->mask;
17812 if ((mask & builtin_mask) != mask)
17814 if (TARGET_DEBUG_BUILTIN)
17815 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
17820 /* Cannot define builtin if the instruction is disabled. */
17821 gcc_assert (d->icode != CODE_FOR_nothing);
17822 mode0 = insn_data[d->icode].operand[0].mode;
17827 type = v2di_ftype_v2di;
17830 type = v4si_ftype_v4si;
17833 type = v8hi_ftype_v8hi;
17836 type = v16qi_ftype_v16qi;
17839 type = v4sf_ftype_v4sf;
17842 type = v2df_ftype_v2df;
17845 gcc_unreachable ();
17848 def_builtin (d->name, type, d->code);
17851 /* Initialize target builtin that implements
17852 targetm.vectorize.builtin_mask_for_load. */
17854 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17855 v16qi_ftype_long_pcvoid,
17856 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17857 BUILT_IN_MD, NULL, NULL_TREE);
17858 TREE_READONLY (decl) = 1;
17859 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17860 altivec_builtin_mask_for_load = decl;
17862 /* Access to the vec_init patterns. */
17863 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17864 integer_type_node, integer_type_node,
17865 integer_type_node, NULL_TREE);
17866 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17868 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17869 short_integer_type_node,
17870 short_integer_type_node,
17871 short_integer_type_node,
17872 short_integer_type_node,
17873 short_integer_type_node,
17874 short_integer_type_node,
17875 short_integer_type_node, NULL_TREE);
17876 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17878 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17879 char_type_node, char_type_node,
17880 char_type_node, char_type_node,
17881 char_type_node, char_type_node,
17882 char_type_node, char_type_node,
17883 char_type_node, char_type_node,
17884 char_type_node, char_type_node,
17885 char_type_node, char_type_node,
17886 char_type_node, NULL_TREE);
17887 def_builtin ("__builtin_vec_init_v16qi", ftype,
17888 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17890 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17891 float_type_node, float_type_node,
17892 float_type_node, NULL_TREE);
17893 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17895 /* VSX builtins. */
17896 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17897 double_type_node, NULL_TREE);
17898 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17900 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17901 intDI_type_node, NULL_TREE);
17902 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17904 /* Access to the vec_set patterns. */
17905 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17907 integer_type_node, NULL_TREE);
17908 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17910 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17912 integer_type_node, NULL_TREE);
17913 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17915 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17917 integer_type_node, NULL_TREE);
17918 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17920 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17922 integer_type_node, NULL_TREE);
17923 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17925 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17927 integer_type_node, NULL_TREE);
17928 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17930 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17932 integer_type_node, NULL_TREE);
17933 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17935 /* Access to the vec_extract patterns. */
17936 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17937 integer_type_node, NULL_TREE);
17938 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17940 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17941 integer_type_node, NULL_TREE);
17942 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17944 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17945 integer_type_node, NULL_TREE);
17946 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17948 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17949 integer_type_node, NULL_TREE);
17950 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17952 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17953 integer_type_node, NULL_TREE);
17954 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17956 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17957 integer_type_node, NULL_TREE);
17958 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17961 if (V1TI_type_node)
17963 tree v1ti_ftype_long_pcvoid
17964 = build_function_type_list (V1TI_type_node,
17965 long_integer_type_node, pcvoid_type_node,
17967 tree void_ftype_v1ti_long_pvoid
17968 = build_function_type_list (void_type_node,
17969 V1TI_type_node, long_integer_type_node,
17970 pvoid_type_node, NULL_TREE);
17971 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
17972 VSX_BUILTIN_LD_ELEMREV_V1TI);
17973 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17974 VSX_BUILTIN_LXVD2X_V1TI);
17975 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17976 VSX_BUILTIN_STXVD2X_V1TI);
17977 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17978 NULL_TREE, NULL_TREE);
17979 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17980 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17982 integer_type_node, NULL_TREE);
17983 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17984 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17985 integer_type_node, NULL_TREE);
17986 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17992 htm_init_builtins (void)
17994 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17995 const struct builtin_description *d;
17999 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
18001 tree op[MAX_HTM_OPERANDS], type;
18002 HOST_WIDE_INT mask = d->mask;
18003 unsigned attr = rs6000_builtin_info[d->code].attr;
18004 bool void_func = (attr & RS6000_BTC_VOID);
18005 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
18007 tree gpr_type_node;
18011 /* It is expected that these htm built-in functions may have
18012 d->icode equal to CODE_FOR_nothing. */
18014 if (TARGET_32BIT && TARGET_POWERPC64)
18015 gpr_type_node = long_long_unsigned_type_node;
18017 gpr_type_node = long_unsigned_type_node;
18019 if (attr & RS6000_BTC_SPR)
18021 rettype = gpr_type_node;
18022 argtype = gpr_type_node;
18024 else if (d->code == HTM_BUILTIN_TABORTDC
18025 || d->code == HTM_BUILTIN_TABORTDCI)
18027 rettype = unsigned_type_node;
18028 argtype = gpr_type_node;
18032 rettype = unsigned_type_node;
18033 argtype = unsigned_type_node;
18036 if ((mask & builtin_mask) != mask)
18038 if (TARGET_DEBUG_BUILTIN)
18039 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
18045 if (TARGET_DEBUG_BUILTIN)
18046 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
18047 (long unsigned) i);
18051 op[nopnds++] = (void_func) ? void_type_node : rettype;
18053 if (attr_args == RS6000_BTC_UNARY)
18054 op[nopnds++] = argtype;
18055 else if (attr_args == RS6000_BTC_BINARY)
18057 op[nopnds++] = argtype;
18058 op[nopnds++] = argtype;
18060 else if (attr_args == RS6000_BTC_TERNARY)
18062 op[nopnds++] = argtype;
18063 op[nopnds++] = argtype;
18064 op[nopnds++] = argtype;
18070 type = build_function_type_list (op[0], NULL_TREE);
18073 type = build_function_type_list (op[0], op[1], NULL_TREE);
18076 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
18079 type = build_function_type_list (op[0], op[1], op[2], op[3],
18083 gcc_unreachable ();
18086 def_builtin (d->name, type, d->code);
18090 /* Hash function for builtin functions with up to 3 arguments and a return
18093 builtin_hasher::hash (builtin_hash_struct *bh)
18098 for (i = 0; i < 4; i++)
18100 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
18101 ret = (ret * 2) + bh->uns_p[i];
18107 /* Compare builtin hash entries H1 and H2 for equivalence. */
18109 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
18111 return ((p1->mode[0] == p2->mode[0])
18112 && (p1->mode[1] == p2->mode[1])
18113 && (p1->mode[2] == p2->mode[2])
18114 && (p1->mode[3] == p2->mode[3])
18115 && (p1->uns_p[0] == p2->uns_p[0])
18116 && (p1->uns_p[1] == p2->uns_p[1])
18117 && (p1->uns_p[2] == p2->uns_p[2])
18118 && (p1->uns_p[3] == p2->uns_p[3]));
18121 /* Map types for builtin functions with an explicit return type and up to 3
18122 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
18123 of the argument. */
18125 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
18126 machine_mode mode_arg1, machine_mode mode_arg2,
18127 enum rs6000_builtins builtin, const char *name)
18129 struct builtin_hash_struct h;
18130 struct builtin_hash_struct *h2;
18133 tree ret_type = NULL_TREE;
18134 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
18136 /* Create builtin_hash_table. */
18137 if (builtin_hash_table == NULL)
18138 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
18140 h.type = NULL_TREE;
18141 h.mode[0] = mode_ret;
18142 h.mode[1] = mode_arg0;
18143 h.mode[2] = mode_arg1;
18144 h.mode[3] = mode_arg2;
18150 /* If the builtin is a type that produces unsigned results or takes unsigned
18151 arguments, and it is returned as a decl for the vectorizer (such as
18152 widening multiplies, permute), make sure the arguments and return value
18153 are type correct. */
18156 /* unsigned 1 argument functions. */
18157 case CRYPTO_BUILTIN_VSBOX:
18158 case P8V_BUILTIN_VGBBD:
18159 case MISC_BUILTIN_CDTBCD:
18160 case MISC_BUILTIN_CBCDTD:
18165 /* unsigned 2 argument functions. */
18166 case ALTIVEC_BUILTIN_VMULEUB:
18167 case ALTIVEC_BUILTIN_VMULEUH:
18168 case ALTIVEC_BUILTIN_VMULEUW:
18169 case ALTIVEC_BUILTIN_VMULOUB:
18170 case ALTIVEC_BUILTIN_VMULOUH:
18171 case ALTIVEC_BUILTIN_VMULOUW:
18172 case CRYPTO_BUILTIN_VCIPHER:
18173 case CRYPTO_BUILTIN_VCIPHERLAST:
18174 case CRYPTO_BUILTIN_VNCIPHER:
18175 case CRYPTO_BUILTIN_VNCIPHERLAST:
18176 case CRYPTO_BUILTIN_VPMSUMB:
18177 case CRYPTO_BUILTIN_VPMSUMH:
18178 case CRYPTO_BUILTIN_VPMSUMW:
18179 case CRYPTO_BUILTIN_VPMSUMD:
18180 case CRYPTO_BUILTIN_VPMSUM:
18181 case MISC_BUILTIN_ADDG6S:
18182 case MISC_BUILTIN_DIVWEU:
18183 case MISC_BUILTIN_DIVWEUO:
18184 case MISC_BUILTIN_DIVDEU:
18185 case MISC_BUILTIN_DIVDEUO:
18186 case VSX_BUILTIN_UDIV_V2DI:
18187 case ALTIVEC_BUILTIN_VMAXUB:
18188 case ALTIVEC_BUILTIN_VMINUB:
18189 case ALTIVEC_BUILTIN_VMAXUH:
18190 case ALTIVEC_BUILTIN_VMINUH:
18191 case ALTIVEC_BUILTIN_VMAXUW:
18192 case ALTIVEC_BUILTIN_VMINUW:
18193 case P8V_BUILTIN_VMAXUD:
18194 case P8V_BUILTIN_VMINUD:
18200 /* unsigned 3 argument functions. */
18201 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
18202 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
18203 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
18204 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
18205 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
18206 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
18207 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
18208 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
18209 case VSX_BUILTIN_VPERM_16QI_UNS:
18210 case VSX_BUILTIN_VPERM_8HI_UNS:
18211 case VSX_BUILTIN_VPERM_4SI_UNS:
18212 case VSX_BUILTIN_VPERM_2DI_UNS:
18213 case VSX_BUILTIN_XXSEL_16QI_UNS:
18214 case VSX_BUILTIN_XXSEL_8HI_UNS:
18215 case VSX_BUILTIN_XXSEL_4SI_UNS:
18216 case VSX_BUILTIN_XXSEL_2DI_UNS:
18217 case CRYPTO_BUILTIN_VPERMXOR:
18218 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
18219 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
18220 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
18221 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
18222 case CRYPTO_BUILTIN_VSHASIGMAW:
18223 case CRYPTO_BUILTIN_VSHASIGMAD:
18224 case CRYPTO_BUILTIN_VSHASIGMA:
18231 /* signed permute functions with unsigned char mask. */
18232 case ALTIVEC_BUILTIN_VPERM_16QI:
18233 case ALTIVEC_BUILTIN_VPERM_8HI:
18234 case ALTIVEC_BUILTIN_VPERM_4SI:
18235 case ALTIVEC_BUILTIN_VPERM_4SF:
18236 case ALTIVEC_BUILTIN_VPERM_2DI:
18237 case ALTIVEC_BUILTIN_VPERM_2DF:
18238 case VSX_BUILTIN_VPERM_16QI:
18239 case VSX_BUILTIN_VPERM_8HI:
18240 case VSX_BUILTIN_VPERM_4SI:
18241 case VSX_BUILTIN_VPERM_4SF:
18242 case VSX_BUILTIN_VPERM_2DI:
18243 case VSX_BUILTIN_VPERM_2DF:
18247 /* unsigned args, signed return. */
18248 case VSX_BUILTIN_XVCVUXDSP:
18249 case VSX_BUILTIN_XVCVUXDDP_UNS:
18250 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
18254 /* signed args, unsigned return. */
18255 case VSX_BUILTIN_XVCVDPUXDS_UNS:
18256 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
18257 case MISC_BUILTIN_UNPACK_TD:
18258 case MISC_BUILTIN_UNPACK_V1TI:
18262 /* unsigned arguments, bool return (compares). */
18263 case ALTIVEC_BUILTIN_VCMPEQUB:
18264 case ALTIVEC_BUILTIN_VCMPEQUH:
18265 case ALTIVEC_BUILTIN_VCMPEQUW:
18266 case P8V_BUILTIN_VCMPEQUD:
18267 case VSX_BUILTIN_CMPGE_U16QI:
18268 case VSX_BUILTIN_CMPGE_U8HI:
18269 case VSX_BUILTIN_CMPGE_U4SI:
18270 case VSX_BUILTIN_CMPGE_U2DI:
18271 case ALTIVEC_BUILTIN_VCMPGTUB:
18272 case ALTIVEC_BUILTIN_VCMPGTUH:
18273 case ALTIVEC_BUILTIN_VCMPGTUW:
18274 case P8V_BUILTIN_VCMPGTUD:
18279 /* unsigned arguments for 128-bit pack instructions. */
18280 case MISC_BUILTIN_PACK_TD:
18281 case MISC_BUILTIN_PACK_V1TI:
18286 /* unsigned second arguments (vector shift right). */
18287 case ALTIVEC_BUILTIN_VSRB:
18288 case ALTIVEC_BUILTIN_VSRH:
18289 case ALTIVEC_BUILTIN_VSRW:
18290 case P8V_BUILTIN_VSRD:
18298 /* Figure out how many args are present. */
18299 while (num_args > 0 && h.mode[num_args] == VOIDmode)
18302 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
18303 if (!ret_type && h.uns_p[0])
18304 ret_type = builtin_mode_to_type[h.mode[0]][0];
18307 fatal_error (input_location,
18308 "internal error: builtin function %qs had an unexpected "
18309 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
18311 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
18312 arg_type[i] = NULL_TREE;
18314 for (i = 0; i < num_args; i++)
18316 int m = (int) h.mode[i+1];
18317 int uns_p = h.uns_p[i+1];
18319 arg_type[i] = builtin_mode_to_type[m][uns_p];
18320 if (!arg_type[i] && uns_p)
18321 arg_type[i] = builtin_mode_to_type[m][0];
18324 fatal_error (input_location,
18325 "internal error: builtin function %qs, argument %d "
18326 "had unexpected argument type %qs", name, i,
18327 GET_MODE_NAME (m));
18330 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
18331 if (*found == NULL)
18333 h2 = ggc_alloc<builtin_hash_struct> ();
18337 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
18338 arg_type[2], NULL_TREE);
18341 return (*found)->type;
18345 rs6000_common_init_builtins (void)
18347 const struct builtin_description *d;
18350 tree opaque_ftype_opaque = NULL_TREE;
18351 tree opaque_ftype_opaque_opaque = NULL_TREE;
18352 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
18353 tree v2si_ftype = NULL_TREE;
18354 tree v2si_ftype_qi = NULL_TREE;
18355 tree v2si_ftype_v2si_qi = NULL_TREE;
18356 tree v2si_ftype_int_qi = NULL_TREE;
18357 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
18359 if (!TARGET_PAIRED_FLOAT)
18361 builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
18362 builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
18365 /* Paired builtins are only available if you build a compiler with the
18366 appropriate options, so only create those builtins with the appropriate
18367 compiler option. Create Altivec and VSX builtins on machines with at
18368 least the general purpose extensions (970 and newer) to allow the use of
18369 the target attribute.. */
18371 if (TARGET_EXTRA_BUILTINS)
18372 builtin_mask |= RS6000_BTM_COMMON;
18374 /* Add the ternary operators. */
18376 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
18379 HOST_WIDE_INT mask = d->mask;
18381 if ((mask & builtin_mask) != mask)
18383 if (TARGET_DEBUG_BUILTIN)
18384 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
18388 if (rs6000_overloaded_builtin_p (d->code))
18390 if (! (type = opaque_ftype_opaque_opaque_opaque))
18391 type = opaque_ftype_opaque_opaque_opaque
18392 = build_function_type_list (opaque_V4SI_type_node,
18393 opaque_V4SI_type_node,
18394 opaque_V4SI_type_node,
18395 opaque_V4SI_type_node,
18400 enum insn_code icode = d->icode;
18403 if (TARGET_DEBUG_BUILTIN)
18404 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
18410 if (icode == CODE_FOR_nothing)
18412 if (TARGET_DEBUG_BUILTIN)
18413 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
18419 type = builtin_function_type (insn_data[icode].operand[0].mode,
18420 insn_data[icode].operand[1].mode,
18421 insn_data[icode].operand[2].mode,
18422 insn_data[icode].operand[3].mode,
18426 def_builtin (d->name, type, d->code);
18429 /* Add the binary operators. */
18431 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
18433 machine_mode mode0, mode1, mode2;
18435 HOST_WIDE_INT mask = d->mask;
18437 if ((mask & builtin_mask) != mask)
18439 if (TARGET_DEBUG_BUILTIN)
18440 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
18444 if (rs6000_overloaded_builtin_p (d->code))
18446 if (! (type = opaque_ftype_opaque_opaque))
18447 type = opaque_ftype_opaque_opaque
18448 = build_function_type_list (opaque_V4SI_type_node,
18449 opaque_V4SI_type_node,
18450 opaque_V4SI_type_node,
18455 enum insn_code icode = d->icode;
18458 if (TARGET_DEBUG_BUILTIN)
18459 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
18465 if (icode == CODE_FOR_nothing)
18467 if (TARGET_DEBUG_BUILTIN)
18468 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
18474 mode0 = insn_data[icode].operand[0].mode;
18475 mode1 = insn_data[icode].operand[1].mode;
18476 mode2 = insn_data[icode].operand[2].mode;
18478 if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
18480 if (! (type = v2si_ftype_v2si_qi))
18481 type = v2si_ftype_v2si_qi
18482 = build_function_type_list (opaque_V2SI_type_node,
18483 opaque_V2SI_type_node,
18488 else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
18489 && mode2 == QImode)
18491 if (! (type = v2si_ftype_int_qi))
18492 type = v2si_ftype_int_qi
18493 = build_function_type_list (opaque_V2SI_type_node,
18500 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
18504 def_builtin (d->name, type, d->code);
18507 /* Add the simple unary operators. */
18509 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
18511 machine_mode mode0, mode1;
18513 HOST_WIDE_INT mask = d->mask;
18515 if ((mask & builtin_mask) != mask)
18517 if (TARGET_DEBUG_BUILTIN)
18518 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
18522 if (rs6000_overloaded_builtin_p (d->code))
18524 if (! (type = opaque_ftype_opaque))
18525 type = opaque_ftype_opaque
18526 = build_function_type_list (opaque_V4SI_type_node,
18527 opaque_V4SI_type_node,
18532 enum insn_code icode = d->icode;
18535 if (TARGET_DEBUG_BUILTIN)
18536 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
18542 if (icode == CODE_FOR_nothing)
18544 if (TARGET_DEBUG_BUILTIN)
18545 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
18551 mode0 = insn_data[icode].operand[0].mode;
18552 mode1 = insn_data[icode].operand[1].mode;
18554 if (mode0 == V2SImode && mode1 == QImode)
18556 if (! (type = v2si_ftype_qi))
18557 type = v2si_ftype_qi
18558 = build_function_type_list (opaque_V2SI_type_node,
18564 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
18568 def_builtin (d->name, type, d->code);
18571 /* Add the simple no-argument operators. */
18573 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
18575 machine_mode mode0;
18577 HOST_WIDE_INT mask = d->mask;
18579 if ((mask & builtin_mask) != mask)
18581 if (TARGET_DEBUG_BUILTIN)
18582 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
18585 if (rs6000_overloaded_builtin_p (d->code))
18587 if (!opaque_ftype_opaque)
18588 opaque_ftype_opaque
18589 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
18590 type = opaque_ftype_opaque;
18594 enum insn_code icode = d->icode;
18597 if (TARGET_DEBUG_BUILTIN)
18598 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
18599 (long unsigned) i);
18602 if (icode == CODE_FOR_nothing)
18604 if (TARGET_DEBUG_BUILTIN)
18606 "rs6000_builtin, skip no-argument %s (no code)\n",
18610 mode0 = insn_data[icode].operand[0].mode;
18611 if (mode0 == V2SImode)
18613 /* code for paired single */
18614 if (! (type = v2si_ftype))
18617 = build_function_type_list (opaque_V2SI_type_node,
18623 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
18626 def_builtin (d->name, type, d->code);
18630 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
18632 init_float128_ibm (machine_mode mode)
18634 if (!TARGET_XL_COMPAT)
18636 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
18637 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
18638 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
18639 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
18641 if (!TARGET_HARD_FLOAT)
18643 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
18644 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
18645 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
18646 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
18647 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
18648 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
18649 set_optab_libfunc (le_optab, mode, "__gcc_qle");
18650 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
18652 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
18653 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
18654 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
18655 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
18656 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
18657 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
18658 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
18659 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
18664 set_optab_libfunc (add_optab, mode, "_xlqadd");
18665 set_optab_libfunc (sub_optab, mode, "_xlqsub");
18666 set_optab_libfunc (smul_optab, mode, "_xlqmul");
18667 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
18670 /* Add various conversions for IFmode to use the traditional TFmode
18672 if (mode == IFmode)
18674 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf2");
18675 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf2");
18676 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctftd2");
18677 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd2");
18678 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd2");
18679 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdtf2");
18681 if (TARGET_POWERPC64)
18683 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
18684 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
18685 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
18686 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
18691 /* Set up IEEE 128-bit floating point routines. Use different names if the
18692 arguments can be passed in a vector register. The historical PowerPC
18693 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
18694 continue to use that if we aren't using vector registers to pass IEEE
18695 128-bit floating point. */
18698 init_float128_ieee (machine_mode mode)
18700 if (FLOAT128_VECTOR_P (mode))
18702 set_optab_libfunc (add_optab, mode, "__addkf3");
18703 set_optab_libfunc (sub_optab, mode, "__subkf3");
18704 set_optab_libfunc (neg_optab, mode, "__negkf2");
18705 set_optab_libfunc (smul_optab, mode, "__mulkf3");
18706 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
18707 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
18708 set_optab_libfunc (abs_optab, mode, "__abstkf2");
18710 set_optab_libfunc (eq_optab, mode, "__eqkf2");
18711 set_optab_libfunc (ne_optab, mode, "__nekf2");
18712 set_optab_libfunc (gt_optab, mode, "__gtkf2");
18713 set_optab_libfunc (ge_optab, mode, "__gekf2");
18714 set_optab_libfunc (lt_optab, mode, "__ltkf2");
18715 set_optab_libfunc (le_optab, mode, "__lekf2");
18716 set_optab_libfunc (unord_optab, mode, "__unordkf2");
18718 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
18719 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
18720 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
18721 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
18723 set_conv_libfunc (sext_optab, mode, IFmode, "__extendtfkf2");
18724 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
18725 set_conv_libfunc (sext_optab, mode, TFmode, "__extendtfkf2");
18727 set_conv_libfunc (trunc_optab, IFmode, mode, "__trunckftf2");
18728 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
18729 set_conv_libfunc (trunc_optab, TFmode, mode, "__trunckftf2");
18731 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf2");
18732 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf2");
18733 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunckftd2");
18734 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd2");
18735 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd2");
18736 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdkf2");
18738 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
18739 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
18740 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
18741 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
18743 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
18744 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
18745 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
18746 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
18748 if (TARGET_POWERPC64)
18750 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
18751 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
18752 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
18753 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
18759 set_optab_libfunc (add_optab, mode, "_q_add");
18760 set_optab_libfunc (sub_optab, mode, "_q_sub");
18761 set_optab_libfunc (neg_optab, mode, "_q_neg");
18762 set_optab_libfunc (smul_optab, mode, "_q_mul");
18763 set_optab_libfunc (sdiv_optab, mode, "_q_div");
18764 if (TARGET_PPC_GPOPT)
18765 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
18767 set_optab_libfunc (eq_optab, mode, "_q_feq");
18768 set_optab_libfunc (ne_optab, mode, "_q_fne");
18769 set_optab_libfunc (gt_optab, mode, "_q_fgt");
18770 set_optab_libfunc (ge_optab, mode, "_q_fge");
18771 set_optab_libfunc (lt_optab, mode, "_q_flt");
18772 set_optab_libfunc (le_optab, mode, "_q_fle");
18774 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
18775 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
18776 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
18777 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
18778 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
18779 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
18780 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
18781 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
18786 rs6000_init_libfuncs (void)
18788 /* __float128 support. */
18789 if (TARGET_FLOAT128_TYPE)
18791 init_float128_ibm (IFmode);
18792 init_float128_ieee (KFmode);
18795 /* AIX/Darwin/64-bit Linux quad floating point routines. */
18796 if (TARGET_LONG_DOUBLE_128)
18798 if (!TARGET_IEEEQUAD)
18799 init_float128_ibm (TFmode);
18801 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18803 init_float128_ieee (TFmode);
18807 /* Emit a potentially record-form instruction, setting DST from SRC.
18808 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18809 signed comparison of DST with zero. If DOT is 1, the generated RTL
18810 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18811 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18812 a separate COMPARE. */
18815 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
18819 emit_move_insn (dst, src);
18823 if (cc_reg_not_cr0_operand (ccreg, CCmode))
18825 emit_move_insn (dst, src);
18826 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18830 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18833 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18834 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18838 rtx set = gen_rtx_SET (dst, src);
18839 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18844 /* A validation routine: say whether CODE, a condition code, and MODE
18845 match. The other alternatives either don't make sense or should
18846 never be generated. */
18849 validate_condition_mode (enum rtx_code code, machine_mode mode)
18851 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18852 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18853 && GET_MODE_CLASS (mode) == MODE_CC);
18855 /* These don't make sense. */
18856 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18857 || mode != CCUNSmode);
18859 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18860 || mode == CCUNSmode);
18862 gcc_assert (mode == CCFPmode
18863 || (code != ORDERED && code != UNORDERED
18864 && code != UNEQ && code != LTGT
18865 && code != UNGT && code != UNLT
18866 && code != UNGE && code != UNLE));
18868 /* These should never be generated except for
18869 flag_finite_math_only. */
18870 gcc_assert (mode != CCFPmode
18871 || flag_finite_math_only
18872 || (code != LE && code != GE
18873 && code != UNEQ && code != LTGT
18874 && code != UNGT && code != UNLT));
18876 /* These are invalid; the information is not there. */
18877 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18881 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18882 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18883 not zero, store there the bit offset (counted from the right) where
18884 the single stretch of 1 bits begins; and similarly for B, the bit
18885 offset where it ends. */
18888 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18890 unsigned HOST_WIDE_INT val = INTVAL (mask);
18891 unsigned HOST_WIDE_INT bit;
18893 int n = GET_MODE_PRECISION (mode);
18895 if (mode != DImode && mode != SImode)
18898 if (INTVAL (mask) >= 0)
18901 ne = exact_log2 (bit);
18902 nb = exact_log2 (val + bit);
18904 else if (val + 1 == 0)
18913 nb = exact_log2 (bit);
18914 ne = exact_log2 (val + bit);
18919 ne = exact_log2 (bit);
18920 if (val + bit == 0)
18928 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18939 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18940 or rldicr instruction, to implement an AND with it in mode MODE. */
18943 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18947 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18950 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18952 if (mode == DImode)
18953 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18955 /* For SImode, rlwinm can do everything. */
18956 if (mode == SImode)
18957 return (nb < 32 && ne < 32);
18962 /* Return the instruction template for an AND with mask in mode MODE, with
18963 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18966 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18970 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18971 gcc_unreachable ();
18973 if (mode == DImode && ne == 0)
18975 operands[3] = GEN_INT (63 - nb);
18977 return "rldicl. %0,%1,0,%3";
18978 return "rldicl %0,%1,0,%3";
18981 if (mode == DImode && nb == 63)
18983 operands[3] = GEN_INT (63 - ne);
18985 return "rldicr. %0,%1,0,%3";
18986 return "rldicr %0,%1,0,%3";
18989 if (nb < 32 && ne < 32)
18991 operands[3] = GEN_INT (31 - nb);
18992 operands[4] = GEN_INT (31 - ne);
18994 return "rlwinm. %0,%1,0,%3,%4";
18995 return "rlwinm %0,%1,0,%3,%4";
18998 gcc_unreachable ();
19001 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
19002 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
19003 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
19006 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
19010 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
19013 int n = GET_MODE_PRECISION (mode);
19016 if (CONST_INT_P (XEXP (shift, 1)))
19018 sh = INTVAL (XEXP (shift, 1));
19019 if (sh < 0 || sh >= n)
19023 rtx_code code = GET_CODE (shift);
19025 /* Convert any shift by 0 to a rotate, to simplify below code. */
19029 /* Convert rotate to simple shift if we can, to make analysis simpler. */
19030 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
19032 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
19038 /* DImode rotates need rld*. */
19039 if (mode == DImode && code == ROTATE)
19040 return (nb == 63 || ne == 0 || ne == sh);
19042 /* SImode rotates need rlw*. */
19043 if (mode == SImode && code == ROTATE)
19044 return (nb < 32 && ne < 32 && sh < 32);
19046 /* Wrap-around masks are only okay for rotates. */
19050 /* Variable shifts are only okay for rotates. */
19054 /* Don't allow ASHIFT if the mask is wrong for that. */
19055 if (code == ASHIFT && ne < sh)
19058 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
19059 if the mask is wrong for that. */
19060 if (nb < 32 && ne < 32 && sh < 32
19061 && !(code == LSHIFTRT && nb >= 32 - sh))
19064 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
19065 if the mask is wrong for that. */
19066 if (code == LSHIFTRT)
19068 if (nb == 63 || ne == 0 || ne == sh)
19069 return !(code == LSHIFTRT && nb >= sh);
19074 /* Return the instruction template for a shift with mask in mode MODE, with
19075 operands OPERANDS. If DOT is true, make it a record-form instruction. */
19078 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
19082 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
19083 gcc_unreachable ();
19085 if (mode == DImode && ne == 0)
19087 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19088 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
19089 operands[3] = GEN_INT (63 - nb);
19091 return "rld%I2cl. %0,%1,%2,%3";
19092 return "rld%I2cl %0,%1,%2,%3";
19095 if (mode == DImode && nb == 63)
19097 operands[3] = GEN_INT (63 - ne);
19099 return "rld%I2cr. %0,%1,%2,%3";
19100 return "rld%I2cr %0,%1,%2,%3";
19104 && GET_CODE (operands[4]) != LSHIFTRT
19105 && CONST_INT_P (operands[2])
19106 && ne == INTVAL (operands[2]))
19108 operands[3] = GEN_INT (63 - nb);
19110 return "rld%I2c. %0,%1,%2,%3";
19111 return "rld%I2c %0,%1,%2,%3";
19114 if (nb < 32 && ne < 32)
19116 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19117 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
19118 operands[3] = GEN_INT (31 - nb);
19119 operands[4] = GEN_INT (31 - ne);
19120 /* This insn can also be a 64-bit rotate with mask that really makes
19121 it just a shift right (with mask); the %h below are to adjust for
19122 that situation (shift count is >= 32 in that case). */
19124 return "rlw%I2nm. %0,%1,%h2,%3,%4";
19125 return "rlw%I2nm %0,%1,%h2,%3,%4";
19128 gcc_unreachable ();
19131 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
19132 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
19133 ASHIFT, or LSHIFTRT) in mode MODE. */
19136 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
19140 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
19143 int n = GET_MODE_PRECISION (mode);
19145 int sh = INTVAL (XEXP (shift, 1));
19146 if (sh < 0 || sh >= n)
19149 rtx_code code = GET_CODE (shift);
19151 /* Convert any shift by 0 to a rotate, to simplify below code. */
19155 /* Convert rotate to simple shift if we can, to make analysis simpler. */
19156 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
19158 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
19164 /* DImode rotates need rldimi. */
19165 if (mode == DImode && code == ROTATE)
19168 /* SImode rotates need rlwimi. */
19169 if (mode == SImode && code == ROTATE)
19170 return (nb < 32 && ne < 32 && sh < 32);
19172 /* Wrap-around masks are only okay for rotates. */
19176 /* Don't allow ASHIFT if the mask is wrong for that. */
19177 if (code == ASHIFT && ne < sh)
19180 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
19181 if the mask is wrong for that. */
19182 if (nb < 32 && ne < 32 && sh < 32
19183 && !(code == LSHIFTRT && nb >= 32 - sh))
19186 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
19187 if the mask is wrong for that. */
19188 if (code == LSHIFTRT)
19191 return !(code == LSHIFTRT && nb >= sh);
19196 /* Return the instruction template for an insert with mask in mode MODE, with
19197 operands OPERANDS. If DOT is true, make it a record-form instruction. */
19200 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
19204 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
19205 gcc_unreachable ();
19207 /* Prefer rldimi because rlwimi is cracked. */
19208 if (TARGET_POWERPC64
19209 && (!dot || mode == DImode)
19210 && GET_CODE (operands[4]) != LSHIFTRT
19211 && ne == INTVAL (operands[2]))
19213 operands[3] = GEN_INT (63 - nb);
19215 return "rldimi. %0,%1,%2,%3";
19216 return "rldimi %0,%1,%2,%3";
19219 if (nb < 32 && ne < 32)
19221 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19222 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
19223 operands[3] = GEN_INT (31 - nb);
19224 operands[4] = GEN_INT (31 - ne);
19226 return "rlwimi. %0,%1,%2,%3,%4";
19227 return "rlwimi %0,%1,%2,%3,%4";
19230 gcc_unreachable ();
19233 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
19234 using two machine instructions. */
19237 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
19239 /* There are two kinds of AND we can handle with two insns:
19240 1) those we can do with two rl* insn;
19243 We do not handle that last case yet. */
19245 /* If there is just one stretch of ones, we can do it. */
19246 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
19249 /* Otherwise, fill in the lowest "hole"; if we can do the result with
19250 one insn, we can do the whole thing with two. */
19251 unsigned HOST_WIDE_INT val = INTVAL (c);
19252 unsigned HOST_WIDE_INT bit1 = val & -val;
19253 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
19254 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
19255 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
19256 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
19259 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
19260 If EXPAND is true, split rotate-and-mask instructions we generate to
19261 their constituent parts as well (this is used during expand); if DOT
19262 is 1, make the last insn a record-form instruction clobbering the
19263 destination GPR and setting the CC reg (from operands[3]); if 2, set
19264 that GPR as well as the CC reg. */
19267 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
19269 gcc_assert (!(expand && dot));
19271 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
19273 /* If it is one stretch of ones, it is DImode; shift left, mask, then
19274 shift right. This generates better code than doing the masks without
19275 shifts, or shifting first right and then left. */
19277 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
19279 gcc_assert (mode == DImode);
19281 int shift = 63 - nb;
19284 rtx tmp1 = gen_reg_rtx (DImode);
19285 rtx tmp2 = gen_reg_rtx (DImode);
19286 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
19287 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
19288 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
19292 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
19293 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
19294 emit_move_insn (operands[0], tmp);
19295 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
19296 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19301 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
19302 that does the rest. */
19303 unsigned HOST_WIDE_INT bit1 = val & -val;
19304 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
19305 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
19306 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
19308 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
19309 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
19311 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
19313 /* Two "no-rotate"-and-mask instructions, for SImode. */
19314 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
19316 gcc_assert (mode == SImode);
19318 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
19319 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
19320 emit_move_insn (reg, tmp);
19321 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
19322 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19326 gcc_assert (mode == DImode);
19328 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
19329 insns; we have to do the first in SImode, because it wraps. */
19330 if (mask2 <= 0xffffffff
19331 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
19333 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
19334 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
19336 rtx reg_low = gen_lowpart (SImode, reg);
19337 emit_move_insn (reg_low, tmp);
19338 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
19339 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19343 /* Two rld* insns: rotate, clear the hole in the middle (which now is
19344 at the top end), rotate back and clear the other hole. */
19345 int right = exact_log2 (bit3);
19346 int left = 64 - right;
19348 /* Rotate the mask too. */
19349 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
19353 rtx tmp1 = gen_reg_rtx (DImode);
19354 rtx tmp2 = gen_reg_rtx (DImode);
19355 rtx tmp3 = gen_reg_rtx (DImode);
19356 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
19357 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
19358 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
19359 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
19363 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
19364 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
19365 emit_move_insn (operands[0], tmp);
19366 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
19367 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
19368 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19372 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
19373 for lfq and stfq insns iff the registers are hard registers. */
19376 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
19378 /* We might have been passed a SUBREG. */
19379 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
19382 /* We might have been passed non floating point registers. */
19383 if (!FP_REGNO_P (REGNO (reg1))
19384 || !FP_REGNO_P (REGNO (reg2)))
19387 return (REGNO (reg1) == REGNO (reg2) - 1);
19390 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
19391 addr1 and addr2 must be in consecutive memory locations
19392 (addr2 == addr1 + 8). */
19395 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
19398 unsigned int reg1, reg2;
19399 int offset1, offset2;
19401 /* The mems cannot be volatile. */
19402 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
19405 addr1 = XEXP (mem1, 0);
19406 addr2 = XEXP (mem2, 0);
19408 /* Extract an offset (if used) from the first addr. */
19409 if (GET_CODE (addr1) == PLUS)
19411 /* If not a REG, return zero. */
19412 if (GET_CODE (XEXP (addr1, 0)) != REG)
19416 reg1 = REGNO (XEXP (addr1, 0));
19417 /* The offset must be constant! */
19418 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
19420 offset1 = INTVAL (XEXP (addr1, 1));
19423 else if (GET_CODE (addr1) != REG)
19427 reg1 = REGNO (addr1);
19428 /* This was a simple (mem (reg)) expression. Offset is 0. */
19432 /* And now for the second addr. */
19433 if (GET_CODE (addr2) == PLUS)
19435 /* If not a REG, return zero. */
19436 if (GET_CODE (XEXP (addr2, 0)) != REG)
19440 reg2 = REGNO (XEXP (addr2, 0));
19441 /* The offset must be constant. */
19442 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
19444 offset2 = INTVAL (XEXP (addr2, 1));
19447 else if (GET_CODE (addr2) != REG)
19451 reg2 = REGNO (addr2);
19452 /* This was a simple (mem (reg)) expression. Offset is 0. */
19456 /* Both of these must have the same base register. */
19460 /* The offset for the second addr must be 8 more than the first addr. */
19461 if (offset2 != offset1 + 8)
19464 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
19469 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
19470 need to use DDmode, in all other cases we can use the same mode. */
19471 static machine_mode
19472 rs6000_secondary_memory_needed_mode (machine_mode mode)
19474 if (lra_in_progress && mode == SDmode)
19479 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
19480 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
19481 only work on the traditional altivec registers, note if an altivec register
19484 static enum rs6000_reg_type
19485 register_to_reg_type (rtx reg, bool *is_altivec)
19487 HOST_WIDE_INT regno;
19488 enum reg_class rclass;
19490 if (GET_CODE (reg) == SUBREG)
19491 reg = SUBREG_REG (reg);
19494 return NO_REG_TYPE;
19496 regno = REGNO (reg);
19497 if (regno >= FIRST_PSEUDO_REGISTER)
19499 if (!lra_in_progress && !reload_completed)
19500 return PSEUDO_REG_TYPE;
19502 regno = true_regnum (reg);
19503 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
19504 return PSEUDO_REG_TYPE;
19507 gcc_assert (regno >= 0);
19509 if (is_altivec && ALTIVEC_REGNO_P (regno))
19510 *is_altivec = true;
19512 rclass = rs6000_regno_regclass[regno];
19513 return reg_class_to_reg_type[(int)rclass];
19516 /* Helper function to return the cost of adding a TOC entry address. */
19519 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
19523 if (TARGET_CMODEL != CMODEL_SMALL)
19524 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
19527 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
19532 /* Helper function for rs6000_secondary_reload to determine whether the memory
19533 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
19534 needs reloading. Return negative if the memory is not handled by the memory
19535 helper functions and to try a different reload method, 0 if no additional
19536 instructions are need, and positive to give the extra cost for the
19540 rs6000_secondary_reload_memory (rtx addr,
19541 enum reg_class rclass,
19544 int extra_cost = 0;
19545 rtx reg, and_arg, plus_arg0, plus_arg1;
19546 addr_mask_type addr_mask;
19547 const char *type = NULL;
19548 const char *fail_msg = NULL;
19550 if (GPR_REG_CLASS_P (rclass))
19551 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19553 else if (rclass == FLOAT_REGS)
19554 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19556 else if (rclass == ALTIVEC_REGS)
19557 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19559 /* For the combined VSX_REGS, turn off Altivec AND -16. */
19560 else if (rclass == VSX_REGS)
19561 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
19562 & ~RELOAD_REG_AND_M16);
19564 /* If the register allocator hasn't made up its mind yet on the register
19565 class to use, settle on defaults to use. */
19566 else if (rclass == NO_REGS)
19568 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
19569 & ~RELOAD_REG_AND_M16);
19571 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
19572 addr_mask &= ~(RELOAD_REG_INDEXED
19573 | RELOAD_REG_PRE_INCDEC
19574 | RELOAD_REG_PRE_MODIFY);
19580 /* If the register isn't valid in this register class, just return now. */
19581 if ((addr_mask & RELOAD_REG_VALID) == 0)
19583 if (TARGET_DEBUG_ADDR)
19586 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19587 "not valid in class\n",
19588 GET_MODE_NAME (mode), reg_class_names[rclass]);
19595 switch (GET_CODE (addr))
19597 /* Does the register class supports auto update forms for this mode? We
19598 don't need a scratch register, since the powerpc only supports
19599 PRE_INC, PRE_DEC, and PRE_MODIFY. */
19602 reg = XEXP (addr, 0);
19603 if (!base_reg_operand (addr, GET_MODE (reg)))
19605 fail_msg = "no base register #1";
19609 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19617 reg = XEXP (addr, 0);
19618 plus_arg1 = XEXP (addr, 1);
19619 if (!base_reg_operand (reg, GET_MODE (reg))
19620 || GET_CODE (plus_arg1) != PLUS
19621 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
19623 fail_msg = "bad PRE_MODIFY";
19627 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19634 /* Do we need to simulate AND -16 to clear the bottom address bits used
19635 in VMX load/stores? Only allow the AND for vector sizes. */
19637 and_arg = XEXP (addr, 0);
19638 if (GET_MODE_SIZE (mode) != 16
19639 || GET_CODE (XEXP (addr, 1)) != CONST_INT
19640 || INTVAL (XEXP (addr, 1)) != -16)
19642 fail_msg = "bad Altivec AND #1";
19646 if (rclass != ALTIVEC_REGS)
19648 if (legitimate_indirect_address_p (and_arg, false))
19651 else if (legitimate_indexed_address_p (and_arg, false))
19656 fail_msg = "bad Altivec AND #2";
19664 /* If this is an indirect address, make sure it is a base register. */
19667 if (!legitimate_indirect_address_p (addr, false))
19674 /* If this is an indexed address, make sure the register class can handle
19675 indexed addresses for this mode. */
19677 plus_arg0 = XEXP (addr, 0);
19678 plus_arg1 = XEXP (addr, 1);
19680 /* (plus (plus (reg) (constant)) (constant)) is generated during
19681 push_reload processing, so handle it now. */
19682 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
19684 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19691 /* (plus (plus (reg) (constant)) (reg)) is also generated during
19692 push_reload processing, so handle it now. */
19693 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
19695 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19698 type = "indexed #2";
19702 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
19704 fail_msg = "no base register #2";
19708 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
19710 if ((addr_mask & RELOAD_REG_INDEXED) == 0
19711 || !legitimate_indexed_address_p (addr, false))
19718 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
19719 && CONST_INT_P (plus_arg1))
19721 if (!quad_address_offset_p (INTVAL (plus_arg1)))
19724 type = "vector d-form offset";
19728 /* Make sure the register class can handle offset addresses. */
19729 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19731 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19734 type = "offset #2";
19740 fail_msg = "bad PLUS";
19747 /* Quad offsets are restricted and can't handle normal addresses. */
19748 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19751 type = "vector d-form lo_sum";
19754 else if (!legitimate_lo_sum_address_p (mode, addr, false))
19756 fail_msg = "bad LO_SUM";
19760 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19767 /* Static addresses need to create a TOC entry. */
19771 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19774 type = "vector d-form lo_sum #2";
19780 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
19784 /* TOC references look like offsetable memory. */
19786 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
19788 fail_msg = "bad UNSPEC";
19792 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19795 type = "vector d-form lo_sum #3";
19798 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19801 type = "toc reference";
19807 fail_msg = "bad address";
19812 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
19814 if (extra_cost < 0)
19816 "rs6000_secondary_reload_memory error: mode = %s, "
19817 "class = %s, addr_mask = '%s', %s\n",
19818 GET_MODE_NAME (mode),
19819 reg_class_names[rclass],
19820 rs6000_debug_addr_mask (addr_mask, false),
19821 (fail_msg != NULL) ? fail_msg : "<bad address>");
19825 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19826 "addr_mask = '%s', extra cost = %d, %s\n",
19827 GET_MODE_NAME (mode),
19828 reg_class_names[rclass],
19829 rs6000_debug_addr_mask (addr_mask, false),
19831 (type) ? type : "<none>");
19839 /* Helper function for rs6000_secondary_reload to return true if a move to a
19840 different register classe is really a simple move. */
19843 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19844 enum rs6000_reg_type from_type,
19847 int size = GET_MODE_SIZE (mode);
19849 /* Add support for various direct moves available. In this function, we only
19850 look at cases where we don't need any extra registers, and one or more
19851 simple move insns are issued. Originally small integers are not allowed
19852 in FPR/VSX registers. Single precision binary floating is not a simple
19853 move because we need to convert to the single precision memory layout.
19854 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19855 need special direct move handling, which we do not support yet. */
19856 if (TARGET_DIRECT_MOVE
19857 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19858 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19860 if (TARGET_POWERPC64)
19862 /* ISA 2.07: MTVSRD or MVFVSRD. */
19866 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19867 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19871 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19872 if (TARGET_P8_VECTOR)
19874 if (mode == SImode)
19877 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19881 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19882 if (mode == SDmode)
19886 /* Power6+: MFTGPR or MFFGPR. */
19887 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
19888 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
19889 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19892 /* Move to/from SPR. */
19893 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19894 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19895 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19901 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19902 special direct moves that involve allocating an extra register, return the
19903 insn code of the helper function if there is such a function or
19904 CODE_FOR_nothing if not. */
19907 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19908 enum rs6000_reg_type from_type,
19910 secondary_reload_info *sri,
19914 enum insn_code icode = CODE_FOR_nothing;
19916 int size = GET_MODE_SIZE (mode);
19918 if (TARGET_POWERPC64 && size == 16)
19920 /* Handle moving 128-bit values from GPRs to VSX point registers on
19921 ISA 2.07 (power8, power9) when running in 64-bit mode using
19922 XXPERMDI to glue the two 64-bit values back together. */
19923 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19925 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19926 icode = reg_addr[mode].reload_vsx_gpr;
19929 /* Handle moving 128-bit values from VSX point registers to GPRs on
19930 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19931 bottom 64-bit value. */
19932 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19934 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19935 icode = reg_addr[mode].reload_gpr_vsx;
19939 else if (TARGET_POWERPC64 && mode == SFmode)
19941 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19943 cost = 3; /* xscvdpspn, mfvsrd, and. */
19944 icode = reg_addr[mode].reload_gpr_vsx;
19947 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19949 cost = 2; /* mtvsrz, xscvspdpn. */
19950 icode = reg_addr[mode].reload_vsx_gpr;
19954 else if (!TARGET_POWERPC64 && size == 8)
19956 /* Handle moving 64-bit values from GPRs to floating point registers on
19957 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19958 32-bit values back together. Altivec register classes must be handled
19959 specially since a different instruction is used, and the secondary
19960 reload support requires a single instruction class in the scratch
19961 register constraint. However, right now TFmode is not allowed in
19962 Altivec registers, so the pattern will never match. */
19963 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19965 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19966 icode = reg_addr[mode].reload_fpr_gpr;
19970 if (icode != CODE_FOR_nothing)
19975 sri->icode = icode;
19976 sri->extra_cost = cost;
19983 /* Return whether a move between two register classes can be done either
19984 directly (simple move) or via a pattern that uses a single extra temporary
19985 (using ISA 2.07's direct move in this case. */
19988 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19989 enum rs6000_reg_type from_type,
19991 secondary_reload_info *sri,
19994 /* Fall back to load/store reloads if either type is not a register. */
19995 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
19998 /* If we haven't allocated registers yet, assume the move can be done for the
19999 standard register types. */
20000 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
20001 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
20002 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
20005 /* Moves to the same set of registers is a simple move for non-specialized
20007 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
20010 /* Check whether a simple move can be done directly. */
20011 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
20015 sri->icode = CODE_FOR_nothing;
20016 sri->extra_cost = 0;
20021 /* Now check if we can do it in a few steps. */
20022 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
20026 /* Inform reload about cases where moving X with a mode MODE to a register in
20027 RCLASS requires an extra scratch or immediate register. Return the class
20028 needed for the immediate register.
20030 For VSX and Altivec, we may need a register to convert sp+offset into
20033 For misaligned 64-bit gpr loads and stores we need a register to
20034 convert an offset address to indirect. */
20037 rs6000_secondary_reload (bool in_p,
20039 reg_class_t rclass_i,
20041 secondary_reload_info *sri)
20043 enum reg_class rclass = (enum reg_class) rclass_i;
20044 reg_class_t ret = ALL_REGS;
20045 enum insn_code icode;
20046 bool default_p = false;
20047 bool done_p = false;
20049 /* Allow subreg of memory before/during reload. */
20050 bool memory_p = (MEM_P (x)
20051 || (!reload_completed && GET_CODE (x) == SUBREG
20052 && MEM_P (SUBREG_REG (x))));
20054 sri->icode = CODE_FOR_nothing;
20055 sri->t_icode = CODE_FOR_nothing;
20056 sri->extra_cost = 0;
20058 ? reg_addr[mode].reload_load
20059 : reg_addr[mode].reload_store);
20061 if (REG_P (x) || register_operand (x, mode))
20063 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
20064 bool altivec_p = (rclass == ALTIVEC_REGS);
20065 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
20068 std::swap (to_type, from_type);
20070 /* Can we do a direct move of some sort? */
20071 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
20074 icode = (enum insn_code)sri->icode;
20081 /* Make sure 0.0 is not reloaded or forced into memory. */
20082 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
20089 /* If this is a scalar floating point value and we want to load it into the
20090 traditional Altivec registers, do it via a move via a traditional floating
20091 point register, unless we have D-form addressing. Also make sure that
20092 non-zero constants use a FPR. */
20093 if (!done_p && reg_addr[mode].scalar_in_vmx_p
20094 && !mode_supports_vmx_dform (mode)
20095 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
20096 && (memory_p || (GET_CODE (x) == CONST_DOUBLE)))
20103 /* Handle reload of load/stores if we have reload helper functions. */
20104 if (!done_p && icode != CODE_FOR_nothing && memory_p)
20106 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
20109 if (extra_cost >= 0)
20113 if (extra_cost > 0)
20115 sri->extra_cost = extra_cost;
20116 sri->icode = icode;
20121 /* Handle unaligned loads and stores of integer registers. */
20122 if (!done_p && TARGET_POWERPC64
20123 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
20125 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
20127 rtx addr = XEXP (x, 0);
20128 rtx off = address_offset (addr);
20130 if (off != NULL_RTX)
20132 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
20133 unsigned HOST_WIDE_INT offset = INTVAL (off);
20135 /* We need a secondary reload when our legitimate_address_p
20136 says the address is good (as otherwise the entire address
20137 will be reloaded), and the offset is not a multiple of
20138 four or we have an address wrap. Address wrap will only
20139 occur for LO_SUMs since legitimate_offset_address_p
20140 rejects addresses for 16-byte mems that will wrap. */
20141 if (GET_CODE (addr) == LO_SUM
20142 ? (1 /* legitimate_address_p allows any offset for lo_sum */
20143 && ((offset & 3) != 0
20144 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
20145 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
20146 && (offset & 3) != 0))
20148 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
20150 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
20151 : CODE_FOR_reload_di_load);
20153 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
20154 : CODE_FOR_reload_di_store);
20155 sri->extra_cost = 2;
20166 if (!done_p && !TARGET_POWERPC64
20167 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
20169 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
20171 rtx addr = XEXP (x, 0);
20172 rtx off = address_offset (addr);
20174 if (off != NULL_RTX)
20176 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
20177 unsigned HOST_WIDE_INT offset = INTVAL (off);
20179 /* We need a secondary reload when our legitimate_address_p
20180 says the address is good (as otherwise the entire address
20181 will be reloaded), and we have a wrap.
20183 legitimate_lo_sum_address_p allows LO_SUM addresses to
20184 have any offset so test for wrap in the low 16 bits.
20186 legitimate_offset_address_p checks for the range
20187 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
20188 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
20189 [0x7ff4,0x7fff] respectively, so test for the
20190 intersection of these ranges, [0x7ffc,0x7fff] and
20191 [0x7ff4,0x7ff7] respectively.
20193 Note that the address we see here may have been
20194 manipulated by legitimize_reload_address. */
20195 if (GET_CODE (addr) == LO_SUM
20196 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
20197 : offset - (0x8000 - extra) < UNITS_PER_WORD)
20200 sri->icode = CODE_FOR_reload_si_load;
20202 sri->icode = CODE_FOR_reload_si_store;
20203 sri->extra_cost = 2;
20218 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
20220 gcc_assert (ret != ALL_REGS);
20222 if (TARGET_DEBUG_ADDR)
20225 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
20227 reg_class_names[ret],
20228 in_p ? "true" : "false",
20229 reg_class_names[rclass],
20230 GET_MODE_NAME (mode));
20232 if (reload_completed)
20233 fputs (", after reload", stderr);
20236 fputs (", done_p not set", stderr);
20239 fputs (", default secondary reload", stderr);
20241 if (sri->icode != CODE_FOR_nothing)
20242 fprintf (stderr, ", reload func = %s, extra cost = %d",
20243 insn_data[sri->icode].name, sri->extra_cost);
20245 else if (sri->extra_cost > 0)
20246 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
20248 fputs ("\n", stderr);
20255 /* Better tracing for rs6000_secondary_reload_inner. */
20258 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
20263 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
20265 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
20266 store_p ? "store" : "load");
20269 set = gen_rtx_SET (mem, reg);
20271 set = gen_rtx_SET (reg, mem);
20273 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
20274 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
20277 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
20278 ATTRIBUTE_NORETURN;
20281 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
20284 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
20285 gcc_unreachable ();
20288 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
20289 reload helper functions. These were identified in
20290 rs6000_secondary_reload_memory, and if reload decided to use the secondary
20291 reload, it calls the insns:
20292 reload_<RELOAD:mode>_<P:mptrsize>_store
20293 reload_<RELOAD:mode>_<P:mptrsize>_load
20295 which in turn calls this function, to do whatever is necessary to create
20296 valid addresses. */
20299 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
20301 int regno = true_regnum (reg);
20302 machine_mode mode = GET_MODE (reg);
20303 addr_mask_type addr_mask;
20306 rtx op_reg, op0, op1;
20311 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER || !MEM_P (mem)
20312 || !base_reg_operand (scratch, GET_MODE (scratch)))
20313 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20315 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
20316 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
20318 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
20319 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
20321 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
20322 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
20325 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20327 /* Make sure the mode is valid in this register class. */
20328 if ((addr_mask & RELOAD_REG_VALID) == 0)
20329 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20331 if (TARGET_DEBUG_ADDR)
20332 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
20334 new_addr = addr = XEXP (mem, 0);
20335 switch (GET_CODE (addr))
20337 /* Does the register class support auto update forms for this mode? If
20338 not, do the update now. We don't need a scratch register, since the
20339 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
20342 op_reg = XEXP (addr, 0);
20343 if (!base_reg_operand (op_reg, Pmode))
20344 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20346 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
20348 emit_insn (gen_add2_insn (op_reg, GEN_INT (GET_MODE_SIZE (mode))));
20354 op0 = XEXP (addr, 0);
20355 op1 = XEXP (addr, 1);
20356 if (!base_reg_operand (op0, Pmode)
20357 || GET_CODE (op1) != PLUS
20358 || !rtx_equal_p (op0, XEXP (op1, 0)))
20359 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20361 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
20363 emit_insn (gen_rtx_SET (op0, op1));
20368 /* Do we need to simulate AND -16 to clear the bottom address bits used
20369 in VMX load/stores? */
20371 op0 = XEXP (addr, 0);
20372 op1 = XEXP (addr, 1);
20373 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
20375 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
20378 else if (GET_CODE (op1) == PLUS)
20380 emit_insn (gen_rtx_SET (scratch, op1));
20385 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20387 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
20388 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
20389 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
20390 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
20391 new_addr = scratch;
20395 /* If this is an indirect address, make sure it is a base register. */
20398 if (!base_reg_operand (addr, GET_MODE (addr)))
20400 emit_insn (gen_rtx_SET (scratch, addr));
20401 new_addr = scratch;
20405 /* If this is an indexed address, make sure the register class can handle
20406 indexed addresses for this mode. */
20408 op0 = XEXP (addr, 0);
20409 op1 = XEXP (addr, 1);
20410 if (!base_reg_operand (op0, Pmode))
20411 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20413 else if (int_reg_operand (op1, Pmode))
20415 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
20417 emit_insn (gen_rtx_SET (scratch, addr));
20418 new_addr = scratch;
20422 else if (mode_supports_vsx_dform_quad (mode) && CONST_INT_P (op1))
20424 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
20425 || !quad_address_p (addr, mode, false))
20427 emit_insn (gen_rtx_SET (scratch, addr));
20428 new_addr = scratch;
20432 /* Make sure the register class can handle offset addresses. */
20433 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
20435 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
20437 emit_insn (gen_rtx_SET (scratch, addr));
20438 new_addr = scratch;
20443 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20448 op0 = XEXP (addr, 0);
20449 op1 = XEXP (addr, 1);
20450 if (!base_reg_operand (op0, Pmode))
20451 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20453 else if (int_reg_operand (op1, Pmode))
20455 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
20457 emit_insn (gen_rtx_SET (scratch, addr));
20458 new_addr = scratch;
20462 /* Quad offsets are restricted and can't handle normal addresses. */
20463 else if (mode_supports_vsx_dform_quad (mode))
20465 emit_insn (gen_rtx_SET (scratch, addr));
20466 new_addr = scratch;
20469 /* Make sure the register class can handle offset addresses. */
20470 else if (legitimate_lo_sum_address_p (mode, addr, false))
20472 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
20474 emit_insn (gen_rtx_SET (scratch, addr));
20475 new_addr = scratch;
20480 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20487 rs6000_emit_move (scratch, addr, Pmode);
20488 new_addr = scratch;
20492 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20495 /* Adjust the address if it changed. */
20496 if (addr != new_addr)
20498 mem = replace_equiv_address_nv (mem, new_addr);
20499 if (TARGET_DEBUG_ADDR)
20500 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
20503 /* Now create the move. */
20505 emit_insn (gen_rtx_SET (mem, reg));
20507 emit_insn (gen_rtx_SET (reg, mem));
20512 /* Convert reloads involving 64-bit gprs and misaligned offset
20513 addressing, or multiple 32-bit gprs and offsets that are too large,
20514 to use indirect addressing. */
20517 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
20519 int regno = true_regnum (reg);
20520 enum reg_class rclass;
20522 rtx scratch_or_premodify = scratch;
20524 if (TARGET_DEBUG_ADDR)
20526 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
20527 store_p ? "store" : "load");
20528 fprintf (stderr, "reg:\n");
20530 fprintf (stderr, "mem:\n");
20532 fprintf (stderr, "scratch:\n");
20533 debug_rtx (scratch);
20536 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
20537 gcc_assert (GET_CODE (mem) == MEM);
20538 rclass = REGNO_REG_CLASS (regno);
20539 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
20540 addr = XEXP (mem, 0);
20542 if (GET_CODE (addr) == PRE_MODIFY)
20544 gcc_assert (REG_P (XEXP (addr, 0))
20545 && GET_CODE (XEXP (addr, 1)) == PLUS
20546 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
20547 scratch_or_premodify = XEXP (addr, 0);
20548 if (!HARD_REGISTER_P (scratch_or_premodify))
20549 /* If we have a pseudo here then reload will have arranged
20550 to have it replaced, but only in the original insn.
20551 Use the replacement here too. */
20552 scratch_or_premodify = find_replacement (&XEXP (addr, 0));
20554 /* RTL emitted by rs6000_secondary_reload_gpr uses RTL
20555 expressions from the original insn, without unsharing them.
20556 Any RTL that points into the original insn will of course
20557 have register replacements applied. That is why we don't
20558 need to look for replacements under the PLUS. */
20559 addr = XEXP (addr, 1);
20561 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
20563 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
20565 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
20567 /* Now create the move. */
20569 emit_insn (gen_rtx_SET (mem, reg));
20571 emit_insn (gen_rtx_SET (reg, mem));
20576 /* Given an rtx X being reloaded into a reg required to be
20577 in class CLASS, return the class of reg to actually use.
20578 In general this is just CLASS; but on some machines
20579 in some cases it is preferable to use a more restrictive class.
20581 On the RS/6000, we have to return NO_REGS when we want to reload a
20582 floating-point CONST_DOUBLE to force it to be copied to memory.
20584 We also don't want to reload integer values into floating-point
20585 registers if we can at all help it. In fact, this can
20586 cause reload to die, if it tries to generate a reload of CTR
20587 into a FP register and discovers it doesn't have the memory location
20590 ??? Would it be a good idea to have reload do the converse, that is
20591 try to reload floating modes into FP registers if possible?
20594 static enum reg_class
20595 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
20597 machine_mode mode = GET_MODE (x);
20598 bool is_constant = CONSTANT_P (x);
20600 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
20601 reload class for it. */
20602 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
20603 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
20606 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
20607 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
20610 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
20611 the reloading of address expressions using PLUS into floating point
20613 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
20617 /* Zero is always allowed in all VSX registers. */
20618 if (x == CONST0_RTX (mode))
20621 /* If this is a vector constant that can be formed with a few Altivec
20622 instructions, we want altivec registers. */
20623 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
20624 return ALTIVEC_REGS;
20626 /* If this is an integer constant that can easily be loaded into
20627 vector registers, allow it. */
20628 if (CONST_INT_P (x))
20630 HOST_WIDE_INT value = INTVAL (x);
20632 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
20633 2.06 can generate it in the Altivec registers with
20637 if (TARGET_P8_VECTOR)
20639 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
20640 return ALTIVEC_REGS;
20645 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
20646 a sign extend in the Altivec registers. */
20647 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
20648 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
20649 return ALTIVEC_REGS;
20652 /* Force constant to memory. */
20656 /* D-form addressing can easily reload the value. */
20657 if (mode_supports_vmx_dform (mode)
20658 || mode_supports_vsx_dform_quad (mode))
20661 /* If this is a scalar floating point value and we don't have D-form
20662 addressing, prefer the traditional floating point registers so that we
20663 can use D-form (register+offset) addressing. */
20664 if (rclass == VSX_REGS
20665 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
20668 /* Prefer the Altivec registers if Altivec is handling the vector
20669 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
20671 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
20672 || mode == V1TImode)
20673 return ALTIVEC_REGS;
20678 if (is_constant || GET_CODE (x) == PLUS)
20680 if (reg_class_subset_p (GENERAL_REGS, rclass))
20681 return GENERAL_REGS;
20682 if (reg_class_subset_p (BASE_REGS, rclass))
20687 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
20688 return GENERAL_REGS;
20693 /* Debug version of rs6000_preferred_reload_class. */
20694 static enum reg_class
20695 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
20697 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
20700 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
20702 reg_class_names[ret], reg_class_names[rclass],
20703 GET_MODE_NAME (GET_MODE (x)));
20709 /* If we are copying between FP or AltiVec registers and anything else, we need
20710 a memory location. The exception is when we are targeting ppc64 and the
20711 move to/from fpr to gpr instructions are available. Also, under VSX, you
20712 can copy vector registers from the FP register set to the Altivec register
20713 set and vice versa. */
20716 rs6000_secondary_memory_needed (machine_mode mode,
20717 reg_class_t from_class,
20718 reg_class_t to_class)
20720 enum rs6000_reg_type from_type, to_type;
20721 bool altivec_p = ((from_class == ALTIVEC_REGS)
20722 || (to_class == ALTIVEC_REGS));
20724 /* If a simple/direct move is available, we don't need secondary memory */
20725 from_type = reg_class_to_reg_type[(int)from_class];
20726 to_type = reg_class_to_reg_type[(int)to_class];
20728 if (rs6000_secondary_reload_move (to_type, from_type, mode,
20729 (secondary_reload_info *)0, altivec_p))
20732 /* If we have a floating point or vector register class, we need to use
20733 memory to transfer the data. */
20734 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
20740 /* Debug version of rs6000_secondary_memory_needed. */
20742 rs6000_debug_secondary_memory_needed (machine_mode mode,
20743 reg_class_t from_class,
20744 reg_class_t to_class)
20746 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
20749 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
20750 "to_class = %s, mode = %s\n",
20751 ret ? "true" : "false",
20752 reg_class_names[from_class],
20753 reg_class_names[to_class],
20754 GET_MODE_NAME (mode));
20759 /* Return the register class of a scratch register needed to copy IN into
20760 or out of a register in RCLASS in MODE. If it can be done directly,
20761 NO_REGS is returned. */
20763 static enum reg_class
20764 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
20769 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
20771 && MACHOPIC_INDIRECT
20775 /* We cannot copy a symbolic operand directly into anything
20776 other than BASE_REGS for TARGET_ELF. So indicate that a
20777 register from BASE_REGS is needed as an intermediate
20780 On Darwin, pic addresses require a load from memory, which
20781 needs a base register. */
20782 if (rclass != BASE_REGS
20783 && (GET_CODE (in) == SYMBOL_REF
20784 || GET_CODE (in) == HIGH
20785 || GET_CODE (in) == LABEL_REF
20786 || GET_CODE (in) == CONST))
20790 if (GET_CODE (in) == REG)
20792 regno = REGNO (in);
20793 if (regno >= FIRST_PSEUDO_REGISTER)
20795 regno = true_regnum (in);
20796 if (regno >= FIRST_PSEUDO_REGISTER)
20800 else if (GET_CODE (in) == SUBREG)
20802 regno = true_regnum (in);
20803 if (regno >= FIRST_PSEUDO_REGISTER)
20809 /* If we have VSX register moves, prefer moving scalar values between
20810 Altivec registers and GPR by going via an FPR (and then via memory)
20811 instead of reloading the secondary memory address for Altivec moves. */
20813 && GET_MODE_SIZE (mode) < 16
20814 && !mode_supports_vmx_dform (mode)
20815 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
20816 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
20817 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
20818 && (regno >= 0 && INT_REGNO_P (regno)))))
20821 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20823 if (rclass == GENERAL_REGS || rclass == BASE_REGS
20824 || (regno >= 0 && INT_REGNO_P (regno)))
20827 /* Constants, memory, and VSX registers can go into VSX registers (both the
20828 traditional floating point and the altivec registers). */
20829 if (rclass == VSX_REGS
20830 && (regno == -1 || VSX_REGNO_P (regno)))
20833 /* Constants, memory, and FP registers can go into FP registers. */
20834 if ((regno == -1 || FP_REGNO_P (regno))
20835 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
20836 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
20838 /* Memory, and AltiVec registers can go into AltiVec registers. */
20839 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
20840 && rclass == ALTIVEC_REGS)
20843 /* We can copy among the CR registers. */
20844 if ((rclass == CR_REGS || rclass == CR0_REGS)
20845 && regno >= 0 && CR_REGNO_P (regno))
20848 /* Otherwise, we need GENERAL_REGS. */
20849 return GENERAL_REGS;
20852 /* Debug version of rs6000_secondary_reload_class. */
20853 static enum reg_class
20854 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20855 machine_mode mode, rtx in)
20857 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20859 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20860 "mode = %s, input rtx:\n",
20861 reg_class_names[ret], reg_class_names[rclass],
20862 GET_MODE_NAME (mode));
20868 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20871 rs6000_can_change_mode_class (machine_mode from,
20873 reg_class_t rclass)
20875 unsigned from_size = GET_MODE_SIZE (from);
20876 unsigned to_size = GET_MODE_SIZE (to);
20878 if (from_size != to_size)
20880 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20882 if (reg_classes_intersect_p (xclass, rclass))
20884 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20885 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20886 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20887 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20889 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20890 single register under VSX because the scalar part of the register
20891 is in the upper 64-bits, and not the lower 64-bits. Types like
20892 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20893 IEEE floating point can't overlap, and neither can small
20896 if (to_float128_vector_p && from_float128_vector_p)
20899 else if (to_float128_vector_p || from_float128_vector_p)
20902 /* TDmode in floating-mode registers must always go into a register
20903 pair with the most significant word in the even-numbered register
20904 to match ISA requirements. In little-endian mode, this does not
20905 match subreg numbering, so we cannot allow subregs. */
20906 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20909 if (from_size < 8 || to_size < 8)
20912 if (from_size == 8 && (8 * to_nregs) != to_size)
20915 if (to_size == 8 && (8 * from_nregs) != from_size)
20924 /* Since the VSX register set includes traditional floating point registers
20925 and altivec registers, just check for the size being different instead of
20926 trying to check whether the modes are vector modes. Otherwise it won't
20927 allow say DF and DI to change classes. For types like TFmode and TDmode
20928 that take 2 64-bit registers, rather than a single 128-bit register, don't
20929 allow subregs of those types to other 128 bit types. */
20930 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20932 unsigned num_regs = (from_size + 15) / 16;
20933 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20934 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20937 return (from_size == 8 || from_size == 16);
20940 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20941 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20947 /* Debug version of rs6000_can_change_mode_class. */
20949 rs6000_debug_can_change_mode_class (machine_mode from,
20951 reg_class_t rclass)
20953 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20956 "rs6000_can_change_mode_class, return %s, from = %s, "
20957 "to = %s, rclass = %s\n",
20958 ret ? "true" : "false",
20959 GET_MODE_NAME (from), GET_MODE_NAME (to),
20960 reg_class_names[rclass]);
20965 /* Return a string to do a move operation of 128 bits of data. */
20968 rs6000_output_move_128bit (rtx operands[])
20970 rtx dest = operands[0];
20971 rtx src = operands[1];
20972 machine_mode mode = GET_MODE (dest);
20975 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20976 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20980 dest_regno = REGNO (dest);
20981 dest_gpr_p = INT_REGNO_P (dest_regno);
20982 dest_fp_p = FP_REGNO_P (dest_regno);
20983 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20984 dest_vsx_p = dest_fp_p | dest_vmx_p;
20989 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
20994 src_regno = REGNO (src);
20995 src_gpr_p = INT_REGNO_P (src_regno);
20996 src_fp_p = FP_REGNO_P (src_regno);
20997 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
20998 src_vsx_p = src_fp_p | src_vmx_p;
21003 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
21006 /* Register moves. */
21007 if (dest_regno >= 0 && src_regno >= 0)
21014 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
21015 return (WORDS_BIG_ENDIAN
21016 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
21017 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
21019 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
21023 else if (TARGET_VSX && dest_vsx_p)
21026 return "xxlor %x0,%x1,%x1";
21028 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
21029 return (WORDS_BIG_ENDIAN
21030 ? "mtvsrdd %x0,%1,%L1"
21031 : "mtvsrdd %x0,%L1,%1");
21033 else if (TARGET_DIRECT_MOVE && src_gpr_p)
21037 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
21038 return "vor %0,%1,%1";
21040 else if (dest_fp_p && src_fp_p)
21045 else if (dest_regno >= 0 && MEM_P (src))
21049 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
21055 else if (TARGET_ALTIVEC && dest_vmx_p
21056 && altivec_indexed_or_indirect_operand (src, mode))
21057 return "lvx %0,%y1";
21059 else if (TARGET_VSX && dest_vsx_p)
21061 if (mode_supports_vsx_dform_quad (mode)
21062 && quad_address_p (XEXP (src, 0), mode, true))
21063 return "lxv %x0,%1";
21065 else if (TARGET_P9_VECTOR)
21066 return "lxvx %x0,%y1";
21068 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
21069 return "lxvw4x %x0,%y1";
21072 return "lxvd2x %x0,%y1";
21075 else if (TARGET_ALTIVEC && dest_vmx_p)
21076 return "lvx %0,%y1";
21078 else if (dest_fp_p)
21083 else if (src_regno >= 0 && MEM_P (dest))
21087 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
21088 return "stq %1,%0";
21093 else if (TARGET_ALTIVEC && src_vmx_p
21094 && altivec_indexed_or_indirect_operand (src, mode))
21095 return "stvx %1,%y0";
21097 else if (TARGET_VSX && src_vsx_p)
21099 if (mode_supports_vsx_dform_quad (mode)
21100 && quad_address_p (XEXP (dest, 0), mode, true))
21101 return "stxv %x1,%0";
21103 else if (TARGET_P9_VECTOR)
21104 return "stxvx %x1,%y0";
21106 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
21107 return "stxvw4x %x1,%y0";
21110 return "stxvd2x %x1,%y0";
21113 else if (TARGET_ALTIVEC && src_vmx_p)
21114 return "stvx %1,%y0";
21121 else if (dest_regno >= 0
21122 && (GET_CODE (src) == CONST_INT
21123 || GET_CODE (src) == CONST_WIDE_INT
21124 || GET_CODE (src) == CONST_DOUBLE
21125 || GET_CODE (src) == CONST_VECTOR))
21130 else if ((dest_vmx_p && TARGET_ALTIVEC)
21131 || (dest_vsx_p && TARGET_VSX))
21132 return output_vec_const_move (operands);
21135 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
21138 /* Validate a 128-bit move. */
21140 rs6000_move_128bit_ok_p (rtx operands[])
21142 machine_mode mode = GET_MODE (operands[0]);
21143 return (gpc_reg_operand (operands[0], mode)
21144 || gpc_reg_operand (operands[1], mode));
21147 /* Return true if a 128-bit move needs to be split. */
21149 rs6000_split_128bit_ok_p (rtx operands[])
21151 if (!reload_completed)
21154 if (!gpr_or_gpr_p (operands[0], operands[1]))
21157 if (quad_load_store_p (operands[0], operands[1]))
21164 /* Given a comparison operation, return the bit number in CCR to test. We
21165 know this is a valid comparison.
21167 SCC_P is 1 if this is for an scc. That means that %D will have been
21168 used instead of %C, so the bits will be in different places.
21170 Return -1 if OP isn't a valid comparison for some reason. */
21173 ccr_bit (rtx op, int scc_p)
21175 enum rtx_code code = GET_CODE (op);
21176 machine_mode cc_mode;
21181 if (!COMPARISON_P (op))
21184 reg = XEXP (op, 0);
21186 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
21188 cc_mode = GET_MODE (reg);
21189 cc_regnum = REGNO (reg);
21190 base_bit = 4 * (cc_regnum - CR0_REGNO);
21192 validate_condition_mode (code, cc_mode);
21194 /* When generating a sCOND operation, only positive conditions are
21197 || code == EQ || code == GT || code == LT || code == UNORDERED
21198 || code == GTU || code == LTU);
21203 return scc_p ? base_bit + 3 : base_bit + 2;
21205 return base_bit + 2;
21206 case GT: case GTU: case UNLE:
21207 return base_bit + 1;
21208 case LT: case LTU: case UNGE:
21210 case ORDERED: case UNORDERED:
21211 return base_bit + 3;
21214 /* If scc, we will have done a cror to put the bit in the
21215 unordered position. So test that bit. For integer, this is ! LT
21216 unless this is an scc insn. */
21217 return scc_p ? base_bit + 3 : base_bit;
21220 return scc_p ? base_bit + 3 : base_bit + 1;
21223 gcc_unreachable ();
21227 /* Return the GOT register. */
21230 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
21232 /* The second flow pass currently (June 1999) can't update
21233 regs_ever_live without disturbing other parts of the compiler, so
21234 update it here to make the prolog/epilogue code happy. */
21235 if (!can_create_pseudo_p ()
21236 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
21237 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
21239 crtl->uses_pic_offset_table = 1;
21241 return pic_offset_table_rtx;
21244 static rs6000_stack_t stack_info;
21246 /* Function to init struct machine_function.
21247 This will be called, via a pointer variable,
21248 from push_function_context. */
21250 static struct machine_function *
21251 rs6000_init_machine_status (void)
21253 stack_info.reload_completed = 0;
21254 return ggc_cleared_alloc<machine_function> ();
21257 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
21259 /* Write out a function code label. */
21262 rs6000_output_function_entry (FILE *file, const char *fname)
21264 if (fname[0] != '.')
21266 switch (DEFAULT_ABI)
21269 gcc_unreachable ();
21275 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
21285 RS6000_OUTPUT_BASENAME (file, fname);
21288 /* Print an operand. Recognize special options, documented below. */
21291 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
21292 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
21294 #define SMALL_DATA_RELOC "sda21"
21295 #define SMALL_DATA_REG 0
21299 print_operand (FILE *file, rtx x, int code)
21302 unsigned HOST_WIDE_INT uval;
21306 /* %a is output_address. */
21308 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
21312 /* Like 'J' but get to the GT bit only. */
21313 gcc_assert (REG_P (x));
21315 /* Bit 1 is GT bit. */
21316 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
21318 /* Add one for shift count in rlinm for scc. */
21319 fprintf (file, "%d", i + 1);
21323 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
21326 output_operand_lossage ("invalid %%e value");
21331 if ((uval & 0xffff) == 0 && uval != 0)
21336 /* X is a CR register. Print the number of the EQ bit of the CR */
21337 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21338 output_operand_lossage ("invalid %%E value");
21340 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
21344 /* X is a CR register. Print the shift count needed to move it
21345 to the high-order four bits. */
21346 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21347 output_operand_lossage ("invalid %%f value");
21349 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
21353 /* Similar, but print the count for the rotate in the opposite
21355 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21356 output_operand_lossage ("invalid %%F value");
21358 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
21362 /* X is a constant integer. If it is negative, print "m",
21363 otherwise print "z". This is to make an aze or ame insn. */
21364 if (GET_CODE (x) != CONST_INT)
21365 output_operand_lossage ("invalid %%G value");
21366 else if (INTVAL (x) >= 0)
21373 /* If constant, output low-order five bits. Otherwise, write
21376 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
21378 print_operand (file, x, 0);
21382 /* If constant, output low-order six bits. Otherwise, write
21385 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
21387 print_operand (file, x, 0);
21391 /* Print `i' if this is a constant, else nothing. */
21397 /* Write the bit number in CCR for jump. */
21398 i = ccr_bit (x, 0);
21400 output_operand_lossage ("invalid %%j code");
21402 fprintf (file, "%d", i);
21406 /* Similar, but add one for shift count in rlinm for scc and pass
21407 scc flag to `ccr_bit'. */
21408 i = ccr_bit (x, 1);
21410 output_operand_lossage ("invalid %%J code");
21412 /* If we want bit 31, write a shift count of zero, not 32. */
21413 fprintf (file, "%d", i == 31 ? 0 : i + 1);
21417 /* X must be a constant. Write the 1's complement of the
21420 output_operand_lossage ("invalid %%k value");
21422 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
21426 /* X must be a symbolic constant on ELF. Write an
21427 expression suitable for an 'addi' that adds in the low 16
21428 bits of the MEM. */
21429 if (GET_CODE (x) == CONST)
21431 if (GET_CODE (XEXP (x, 0)) != PLUS
21432 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
21433 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
21434 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
21435 output_operand_lossage ("invalid %%K value");
21437 print_operand_address (file, x);
21438 fputs ("@l", file);
21441 /* %l is output_asm_label. */
21444 /* Write second word of DImode or DFmode reference. Works on register
21445 or non-indexed memory only. */
21447 fputs (reg_names[REGNO (x) + 1], file);
21448 else if (MEM_P (x))
21450 machine_mode mode = GET_MODE (x);
21451 /* Handle possible auto-increment. Since it is pre-increment and
21452 we have already done it, we can just use an offset of word. */
21453 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21454 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21455 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
21457 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21458 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
21461 output_address (mode, XEXP (adjust_address_nv (x, SImode,
21465 if (small_data_operand (x, GET_MODE (x)))
21466 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21467 reg_names[SMALL_DATA_REG]);
21471 case 'N': /* Unused */
21472 /* Write the number of elements in the vector times 4. */
21473 if (GET_CODE (x) != PARALLEL)
21474 output_operand_lossage ("invalid %%N value");
21476 fprintf (file, "%d", XVECLEN (x, 0) * 4);
21479 case 'O': /* Unused */
21480 /* Similar, but subtract 1 first. */
21481 if (GET_CODE (x) != PARALLEL)
21482 output_operand_lossage ("invalid %%O value");
21484 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
21488 /* X is a CONST_INT that is a power of two. Output the logarithm. */
21491 || (i = exact_log2 (INTVAL (x))) < 0)
21492 output_operand_lossage ("invalid %%p value");
21494 fprintf (file, "%d", i);
21498 /* The operand must be an indirect memory reference. The result
21499 is the register name. */
21500 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
21501 || REGNO (XEXP (x, 0)) >= 32)
21502 output_operand_lossage ("invalid %%P value");
21504 fputs (reg_names[REGNO (XEXP (x, 0))], file);
21508 /* This outputs the logical code corresponding to a boolean
21509 expression. The expression may have one or both operands
21510 negated (if one, only the first one). For condition register
21511 logical operations, it will also treat the negated
21512 CR codes as NOTs, but not handle NOTs of them. */
21514 const char *const *t = 0;
21516 enum rtx_code code = GET_CODE (x);
21517 static const char * const tbl[3][3] = {
21518 { "and", "andc", "nor" },
21519 { "or", "orc", "nand" },
21520 { "xor", "eqv", "xor" } };
21524 else if (code == IOR)
21526 else if (code == XOR)
21529 output_operand_lossage ("invalid %%q value");
21531 if (GET_CODE (XEXP (x, 0)) != NOT)
21535 if (GET_CODE (XEXP (x, 1)) == NOT)
21546 if (! TARGET_MFCRF)
21552 /* X is a CR register. Print the mask for `mtcrf'. */
21553 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21554 output_operand_lossage ("invalid %%R value");
21556 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
21560 /* Low 5 bits of 32 - value */
21562 output_operand_lossage ("invalid %%s value");
21564 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
21568 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
21569 gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
21571 /* Bit 3 is OV bit. */
21572 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
21574 /* If we want bit 31, write a shift count of zero, not 32. */
21575 fprintf (file, "%d", i == 31 ? 0 : i + 1);
21579 /* Print the symbolic name of a branch target register. */
21580 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
21581 && REGNO (x) != CTR_REGNO))
21582 output_operand_lossage ("invalid %%T value");
21583 else if (REGNO (x) == LR_REGNO)
21584 fputs ("lr", file);
21586 fputs ("ctr", file);
21590 /* High-order or low-order 16 bits of constant, whichever is non-zero,
21591 for use in unsigned operand. */
21594 output_operand_lossage ("invalid %%u value");
21599 if ((uval & 0xffff) == 0)
21602 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
21606 /* High-order 16 bits of constant for use in signed operand. */
21608 output_operand_lossage ("invalid %%v value");
21610 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
21611 (INTVAL (x) >> 16) & 0xffff);
21615 /* Print `u' if this has an auto-increment or auto-decrement. */
21617 && (GET_CODE (XEXP (x, 0)) == PRE_INC
21618 || GET_CODE (XEXP (x, 0)) == PRE_DEC
21619 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
21624 /* Print the trap code for this operand. */
21625 switch (GET_CODE (x))
21628 fputs ("eq", file); /* 4 */
21631 fputs ("ne", file); /* 24 */
21634 fputs ("lt", file); /* 16 */
21637 fputs ("le", file); /* 20 */
21640 fputs ("gt", file); /* 8 */
21643 fputs ("ge", file); /* 12 */
21646 fputs ("llt", file); /* 2 */
21649 fputs ("lle", file); /* 6 */
21652 fputs ("lgt", file); /* 1 */
21655 fputs ("lge", file); /* 5 */
21658 gcc_unreachable ();
21663 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
21666 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
21667 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
21669 print_operand (file, x, 0);
21673 /* X is a FPR or Altivec register used in a VSX context. */
21674 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
21675 output_operand_lossage ("invalid %%x value");
21678 int reg = REGNO (x);
21679 int vsx_reg = (FP_REGNO_P (reg)
21681 : reg - FIRST_ALTIVEC_REGNO + 32);
21683 #ifdef TARGET_REGNAMES
21684 if (TARGET_REGNAMES)
21685 fprintf (file, "%%vs%d", vsx_reg);
21688 fprintf (file, "%d", vsx_reg);
21694 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
21695 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
21696 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
21701 /* Like 'L', for third word of TImode/PTImode */
21703 fputs (reg_names[REGNO (x) + 2], file);
21704 else if (MEM_P (x))
21706 machine_mode mode = GET_MODE (x);
21707 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21708 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21709 output_address (mode, plus_constant (Pmode,
21710 XEXP (XEXP (x, 0), 0), 8));
21711 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21712 output_address (mode, plus_constant (Pmode,
21713 XEXP (XEXP (x, 0), 0), 8));
21715 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
21716 if (small_data_operand (x, GET_MODE (x)))
21717 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21718 reg_names[SMALL_DATA_REG]);
21723 /* X is a SYMBOL_REF. Write out the name preceded by a
21724 period and without any trailing data in brackets. Used for function
21725 names. If we are configured for System V (or the embedded ABI) on
21726 the PowerPC, do not emit the period, since those systems do not use
21727 TOCs and the like. */
21728 gcc_assert (GET_CODE (x) == SYMBOL_REF);
21730 /* For macho, check to see if we need a stub. */
21733 const char *name = XSTR (x, 0);
21735 if (darwin_emit_branch_islands
21736 && MACHOPIC_INDIRECT
21737 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
21738 name = machopic_indirection_name (x, /*stub_p=*/true);
21740 assemble_name (file, name);
21742 else if (!DOT_SYMBOLS)
21743 assemble_name (file, XSTR (x, 0));
21745 rs6000_output_function_entry (file, XSTR (x, 0));
21749 /* Like 'L', for last word of TImode/PTImode. */
21751 fputs (reg_names[REGNO (x) + 3], file);
21752 else if (MEM_P (x))
21754 machine_mode mode = GET_MODE (x);
21755 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21756 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21757 output_address (mode, plus_constant (Pmode,
21758 XEXP (XEXP (x, 0), 0), 12));
21759 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21760 output_address (mode, plus_constant (Pmode,
21761 XEXP (XEXP (x, 0), 0), 12));
21763 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
21764 if (small_data_operand (x, GET_MODE (x)))
21765 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21766 reg_names[SMALL_DATA_REG]);
21770 /* Print AltiVec memory operand. */
21775 gcc_assert (MEM_P (x));
21779 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
21780 && GET_CODE (tmp) == AND
21781 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
21782 && INTVAL (XEXP (tmp, 1)) == -16)
21783 tmp = XEXP (tmp, 0);
21784 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
21785 && GET_CODE (tmp) == PRE_MODIFY)
21786 tmp = XEXP (tmp, 1);
21788 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
21791 if (GET_CODE (tmp) != PLUS
21792 || !REG_P (XEXP (tmp, 0))
21793 || !REG_P (XEXP (tmp, 1)))
21795 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
21799 if (REGNO (XEXP (tmp, 0)) == 0)
21800 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
21801 reg_names[ REGNO (XEXP (tmp, 0)) ]);
21803 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
21804 reg_names[ REGNO (XEXP (tmp, 1)) ]);
21811 fprintf (file, "%s", reg_names[REGNO (x)]);
21812 else if (MEM_P (x))
21814 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21815 know the width from the mode. */
21816 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21817 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21818 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21819 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21820 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21821 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21822 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21823 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21825 output_address (GET_MODE (x), XEXP (x, 0));
21829 if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21830 /* This hack along with a corresponding hack in
21831 rs6000_output_addr_const_extra arranges to output addends
21832 where the assembler expects to find them. eg.
21833 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21834 without this hack would be output as "x@toc+4". We
21836 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21838 output_addr_const (file, x);
21843 if (const char *name = get_some_local_dynamic_name ())
21844 assemble_name (file, name);
21846 output_operand_lossage ("'%%&' used without any "
21847 "local dynamic TLS references");
21851 output_operand_lossage ("invalid %%xn code");
21855 /* Print the address of an operand. */
21858 print_operand_address (FILE *file, rtx x)
21861 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21862 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
21863 || GET_CODE (x) == LABEL_REF)
21865 output_addr_const (file, x);
21866 if (small_data_operand (x, GET_MODE (x)))
21867 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21868 reg_names[SMALL_DATA_REG]);
21870 gcc_assert (!TARGET_TOC);
21872 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21873 && REG_P (XEXP (x, 1)))
21875 if (REGNO (XEXP (x, 0)) == 0)
21876 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21877 reg_names[ REGNO (XEXP (x, 0)) ]);
21879 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21880 reg_names[ REGNO (XEXP (x, 1)) ]);
21882 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21883 && GET_CODE (XEXP (x, 1)) == CONST_INT)
21884 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21885 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21887 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21888 && CONSTANT_P (XEXP (x, 1)))
21890 fprintf (file, "lo16(");
21891 output_addr_const (file, XEXP (x, 1));
21892 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21896 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21897 && CONSTANT_P (XEXP (x, 1)))
21899 output_addr_const (file, XEXP (x, 1));
21900 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21903 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21905 /* This hack along with a corresponding hack in
21906 rs6000_output_addr_const_extra arranges to output addends
21907 where the assembler expects to find them. eg.
21909 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21910 without this hack would be output as "x@toc+8@l(9)". We
21911 want "x+8@toc@l(9)". */
21912 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21913 if (GET_CODE (x) == LO_SUM)
21914 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21916 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21919 gcc_unreachable ();
21922 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21925 rs6000_output_addr_const_extra (FILE *file, rtx x)
21927 if (GET_CODE (x) == UNSPEC)
21928 switch (XINT (x, 1))
21930 case UNSPEC_TOCREL:
21931 gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
21932 && REG_P (XVECEXP (x, 0, 1))
21933 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21934 output_addr_const (file, XVECEXP (x, 0, 0));
21935 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21937 if (INTVAL (tocrel_offset_oac) >= 0)
21938 fprintf (file, "+");
21939 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21941 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21944 assemble_name (file, toc_label_name);
21947 else if (TARGET_ELF)
21948 fputs ("@toc", file);
21952 case UNSPEC_MACHOPIC_OFFSET:
21953 output_addr_const (file, XVECEXP (x, 0, 0));
21955 machopic_output_function_base_name (file);
21962 /* Target hook for assembling integer objects. The PowerPC version has
21963 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21964 is defined. It also needs to handle DI-mode objects on 64-bit
21968 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21970 #ifdef RELOCATABLE_NEEDS_FIXUP
21971 /* Special handling for SI values. */
21972 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21974 static int recurse = 0;
21976 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21977 the .fixup section. Since the TOC section is already relocated, we
21978 don't need to mark it here. We used to skip the text section, but it
21979 should never be valid for relocated addresses to be placed in the text
21981 if (DEFAULT_ABI == ABI_V4
21982 && (TARGET_RELOCATABLE || flag_pic > 1)
21983 && in_section != toc_section
21985 && !CONST_SCALAR_INT_P (x)
21991 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21993 ASM_OUTPUT_LABEL (asm_out_file, buf);
21994 fprintf (asm_out_file, "\t.long\t(");
21995 output_addr_const (asm_out_file, x);
21996 fprintf (asm_out_file, ")@fixup\n");
21997 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
21998 ASM_OUTPUT_ALIGN (asm_out_file, 2);
21999 fprintf (asm_out_file, "\t.long\t");
22000 assemble_name (asm_out_file, buf);
22001 fprintf (asm_out_file, "\n\t.previous\n");
22005 /* Remove initial .'s to turn a -mcall-aixdesc function
22006 address into the address of the descriptor, not the function
22008 else if (GET_CODE (x) == SYMBOL_REF
22009 && XSTR (x, 0)[0] == '.'
22010 && DEFAULT_ABI == ABI_AIX)
22012 const char *name = XSTR (x, 0);
22013 while (*name == '.')
22016 fprintf (asm_out_file, "\t.long\t%s\n", name);
22020 #endif /* RELOCATABLE_NEEDS_FIXUP */
22021 return default_assemble_integer (x, size, aligned_p);
22024 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
22025 /* Emit an assembler directive to set symbol visibility for DECL to
22026 VISIBILITY_TYPE. */
22029 rs6000_assemble_visibility (tree decl, int vis)
22034 /* Functions need to have their entry point symbol visibility set as
22035 well as their descriptor symbol visibility. */
22036 if (DEFAULT_ABI == ABI_AIX
22038 && TREE_CODE (decl) == FUNCTION_DECL)
22040 static const char * const visibility_types[] = {
22041 NULL, "protected", "hidden", "internal"
22044 const char *name, *type;
22046 name = ((* targetm.strip_name_encoding)
22047 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
22048 type = visibility_types[vis];
22050 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
22051 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
22054 default_assemble_visibility (decl, vis);
22059 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
22061 /* Reversal of FP compares takes care -- an ordered compare
22062 becomes an unordered compare and vice versa. */
22063 if (mode == CCFPmode
22064 && (!flag_finite_math_only
22065 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
22066 || code == UNEQ || code == LTGT))
22067 return reverse_condition_maybe_unordered (code);
22069 return reverse_condition (code);
22072 /* Generate a compare for CODE. Return a brand-new rtx that
22073 represents the result of the compare. */
22076 rs6000_generate_compare (rtx cmp, machine_mode mode)
22078 machine_mode comp_mode;
22079 rtx compare_result;
22080 enum rtx_code code = GET_CODE (cmp);
22081 rtx op0 = XEXP (cmp, 0);
22082 rtx op1 = XEXP (cmp, 1);
22084 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
22085 comp_mode = CCmode;
22086 else if (FLOAT_MODE_P (mode))
22087 comp_mode = CCFPmode;
22088 else if (code == GTU || code == LTU
22089 || code == GEU || code == LEU)
22090 comp_mode = CCUNSmode;
22091 else if ((code == EQ || code == NE)
22092 && unsigned_reg_p (op0)
22093 && (unsigned_reg_p (op1)
22094 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
22095 /* These are unsigned values, perhaps there will be a later
22096 ordering compare that can be shared with this one. */
22097 comp_mode = CCUNSmode;
22099 comp_mode = CCmode;
22101 /* If we have an unsigned compare, make sure we don't have a signed value as
22103 if (comp_mode == CCUNSmode && GET_CODE (op1) == CONST_INT
22104 && INTVAL (op1) < 0)
22106 op0 = copy_rtx_if_shared (op0);
22107 op1 = force_reg (GET_MODE (op0), op1);
22108 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
22111 /* First, the compare. */
22112 compare_result = gen_reg_rtx (comp_mode);
22114 /* IEEE 128-bit support in VSX registers when we do not have hardware
22116 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
22118 rtx libfunc = NULL_RTX;
22119 bool check_nan = false;
22126 libfunc = optab_libfunc (eq_optab, mode);
22131 libfunc = optab_libfunc (ge_optab, mode);
22136 libfunc = optab_libfunc (le_optab, mode);
22141 libfunc = optab_libfunc (unord_optab, mode);
22142 code = (code == UNORDERED) ? NE : EQ;
22148 libfunc = optab_libfunc (ge_optab, mode);
22149 code = (code == UNGE) ? GE : GT;
22155 libfunc = optab_libfunc (le_optab, mode);
22156 code = (code == UNLE) ? LE : LT;
22162 libfunc = optab_libfunc (eq_optab, mode);
22163 code = (code = UNEQ) ? EQ : NE;
22167 gcc_unreachable ();
22170 gcc_assert (libfunc);
22173 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
22174 SImode, op0, mode, op1, mode);
22176 /* The library signals an exception for signalling NaNs, so we need to
22177 handle isgreater, etc. by first checking isordered. */
22180 rtx ne_rtx, normal_dest, unord_dest;
22181 rtx unord_func = optab_libfunc (unord_optab, mode);
22182 rtx join_label = gen_label_rtx ();
22183 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
22184 rtx unord_cmp = gen_reg_rtx (comp_mode);
22187 /* Test for either value being a NaN. */
22188 gcc_assert (unord_func);
22189 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
22190 SImode, op0, mode, op1, mode);
22192 /* Set value (0) if either value is a NaN, and jump to the join
22194 dest = gen_reg_rtx (SImode);
22195 emit_move_insn (dest, const1_rtx);
22196 emit_insn (gen_rtx_SET (unord_cmp,
22197 gen_rtx_COMPARE (comp_mode, unord_dest,
22200 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
22201 emit_jump_insn (gen_rtx_SET (pc_rtx,
22202 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
22206 /* Do the normal comparison, knowing that the values are not
22208 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
22209 SImode, op0, mode, op1, mode);
22211 emit_insn (gen_cstoresi4 (dest,
22212 gen_rtx_fmt_ee (code, SImode, normal_dest,
22214 normal_dest, const0_rtx));
22216 /* Join NaN and non-Nan paths. Compare dest against 0. */
22217 emit_label (join_label);
22221 emit_insn (gen_rtx_SET (compare_result,
22222 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
22227 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
22228 CLOBBERs to match cmptf_internal2 pattern. */
22229 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
22230 && FLOAT128_IBM_P (GET_MODE (op0))
22231 && TARGET_HARD_FLOAT)
22232 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22234 gen_rtx_SET (compare_result,
22235 gen_rtx_COMPARE (comp_mode, op0, op1)),
22236 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22237 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22238 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22239 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22240 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22241 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22242 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22243 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22244 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
22245 else if (GET_CODE (op1) == UNSPEC
22246 && XINT (op1, 1) == UNSPEC_SP_TEST)
22248 rtx op1b = XVECEXP (op1, 0, 0);
22249 comp_mode = CCEQmode;
22250 compare_result = gen_reg_rtx (CCEQmode);
22252 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
22254 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
22257 emit_insn (gen_rtx_SET (compare_result,
22258 gen_rtx_COMPARE (comp_mode, op0, op1)));
22261 /* Some kinds of FP comparisons need an OR operation;
22262 under flag_finite_math_only we don't bother. */
22263 if (FLOAT_MODE_P (mode)
22264 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
22265 && !flag_finite_math_only
22266 && (code == LE || code == GE
22267 || code == UNEQ || code == LTGT
22268 || code == UNGT || code == UNLT))
22270 enum rtx_code or1, or2;
22271 rtx or1_rtx, or2_rtx, compare2_rtx;
22272 rtx or_result = gen_reg_rtx (CCEQmode);
22276 case LE: or1 = LT; or2 = EQ; break;
22277 case GE: or1 = GT; or2 = EQ; break;
22278 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
22279 case LTGT: or1 = LT; or2 = GT; break;
22280 case UNGT: or1 = UNORDERED; or2 = GT; break;
22281 case UNLT: or1 = UNORDERED; or2 = LT; break;
22282 default: gcc_unreachable ();
22284 validate_condition_mode (or1, comp_mode);
22285 validate_condition_mode (or2, comp_mode);
22286 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
22287 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
22288 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
22289 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
22291 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
22293 compare_result = or_result;
22297 validate_condition_mode (code, GET_MODE (compare_result));
22299 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
22303 /* Return the diagnostic message string if the binary operation OP is
22304 not permitted on TYPE1 and TYPE2, NULL otherwise. */
22307 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
22311 machine_mode mode1 = TYPE_MODE (type1);
22312 machine_mode mode2 = TYPE_MODE (type2);
22314 /* For complex modes, use the inner type. */
22315 if (COMPLEX_MODE_P (mode1))
22316 mode1 = GET_MODE_INNER (mode1);
22318 if (COMPLEX_MODE_P (mode2))
22319 mode2 = GET_MODE_INNER (mode2);
22321 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
22322 double to intermix unless -mfloat128-convert. */
22323 if (mode1 == mode2)
22326 if (!TARGET_FLOAT128_CVT)
22328 if ((mode1 == KFmode && mode2 == IFmode)
22329 || (mode1 == IFmode && mode2 == KFmode))
22330 return N_("__float128 and __ibm128 cannot be used in the same "
22333 if (TARGET_IEEEQUAD
22334 && ((mode1 == IFmode && mode2 == TFmode)
22335 || (mode1 == TFmode && mode2 == IFmode)))
22336 return N_("__ibm128 and long double cannot be used in the same "
22339 if (!TARGET_IEEEQUAD
22340 && ((mode1 == KFmode && mode2 == TFmode)
22341 || (mode1 == TFmode && mode2 == KFmode)))
22342 return N_("__float128 and long double cannot be used in the same "
22350 /* Expand floating point conversion to/from __float128 and __ibm128. */
22353 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
22355 machine_mode dest_mode = GET_MODE (dest);
22356 machine_mode src_mode = GET_MODE (src);
22357 convert_optab cvt = unknown_optab;
22358 bool do_move = false;
22359 rtx libfunc = NULL_RTX;
22361 typedef rtx (*rtx_2func_t) (rtx, rtx);
22362 rtx_2func_t hw_convert = (rtx_2func_t)0;
22366 rtx_2func_t from_df;
22367 rtx_2func_t from_sf;
22368 rtx_2func_t from_si_sign;
22369 rtx_2func_t from_si_uns;
22370 rtx_2func_t from_di_sign;
22371 rtx_2func_t from_di_uns;
22374 rtx_2func_t to_si_sign;
22375 rtx_2func_t to_si_uns;
22376 rtx_2func_t to_di_sign;
22377 rtx_2func_t to_di_uns;
22378 } hw_conversions[2] = {
22379 /* convertions to/from KFmode */
22381 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
22382 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
22383 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
22384 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
22385 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
22386 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
22387 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
22388 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
22389 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
22390 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
22391 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
22392 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
22395 /* convertions to/from TFmode */
22397 gen_extenddftf2_hw, /* TFmode <- DFmode. */
22398 gen_extendsftf2_hw, /* TFmode <- SFmode. */
22399 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
22400 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
22401 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
22402 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
22403 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
22404 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
22405 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
22406 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
22407 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
22408 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
22412 if (dest_mode == src_mode)
22413 gcc_unreachable ();
22415 /* Eliminate memory operations. */
22417 src = force_reg (src_mode, src);
22421 rtx tmp = gen_reg_rtx (dest_mode);
22422 rs6000_expand_float128_convert (tmp, src, unsigned_p);
22423 rs6000_emit_move (dest, tmp, dest_mode);
22427 /* Convert to IEEE 128-bit floating point. */
22428 if (FLOAT128_IEEE_P (dest_mode))
22430 if (dest_mode == KFmode)
22432 else if (dest_mode == TFmode)
22435 gcc_unreachable ();
22441 hw_convert = hw_conversions[kf_or_tf].from_df;
22446 hw_convert = hw_conversions[kf_or_tf].from_sf;
22452 if (FLOAT128_IBM_P (src_mode))
22461 cvt = ufloat_optab;
22462 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
22466 cvt = sfloat_optab;
22467 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
22474 cvt = ufloat_optab;
22475 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
22479 cvt = sfloat_optab;
22480 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
22485 gcc_unreachable ();
22489 /* Convert from IEEE 128-bit floating point. */
22490 else if (FLOAT128_IEEE_P (src_mode))
22492 if (src_mode == KFmode)
22494 else if (src_mode == TFmode)
22497 gcc_unreachable ();
22503 hw_convert = hw_conversions[kf_or_tf].to_df;
22508 hw_convert = hw_conversions[kf_or_tf].to_sf;
22514 if (FLOAT128_IBM_P (dest_mode))
22524 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
22529 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
22537 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
22542 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
22547 gcc_unreachable ();
22551 /* Both IBM format. */
22552 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
22556 gcc_unreachable ();
22558 /* Handle conversion between TFmode/KFmode. */
22560 emit_move_insn (dest, gen_lowpart (dest_mode, src));
22562 /* Handle conversion if we have hardware support. */
22563 else if (TARGET_FLOAT128_HW && hw_convert)
22564 emit_insn ((hw_convert) (dest, src));
22566 /* Call an external function to do the conversion. */
22567 else if (cvt != unknown_optab)
22569 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
22570 gcc_assert (libfunc != NULL_RTX);
22572 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
22575 gcc_assert (dest2 != NULL_RTX);
22576 if (!rtx_equal_p (dest, dest2))
22577 emit_move_insn (dest, dest2);
22581 gcc_unreachable ();
22587 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22588 can be used as that dest register. Return the dest register. */
22591 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
22593 if (op2 == const0_rtx)
22596 if (GET_CODE (scratch) == SCRATCH)
22597 scratch = gen_reg_rtx (mode);
22599 if (logical_operand (op2, mode))
22600 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
22602 emit_insn (gen_rtx_SET (scratch,
22603 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
22609 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
22612 machine_mode op_mode;
22613 enum rtx_code cond_code;
22614 rtx result = operands[0];
22616 condition_rtx = rs6000_generate_compare (operands[1], mode);
22617 cond_code = GET_CODE (condition_rtx);
22619 if (cond_code == NE
22620 || cond_code == GE || cond_code == LE
22621 || cond_code == GEU || cond_code == LEU
22622 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
22624 rtx not_result = gen_reg_rtx (CCEQmode);
22625 rtx not_op, rev_cond_rtx;
22626 machine_mode cc_mode;
22628 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
22630 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
22631 SImode, XEXP (condition_rtx, 0), const0_rtx);
22632 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
22633 emit_insn (gen_rtx_SET (not_result, not_op));
22634 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
22637 op_mode = GET_MODE (XEXP (operands[1], 0));
22638 if (op_mode == VOIDmode)
22639 op_mode = GET_MODE (XEXP (operands[1], 1));
22641 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
22643 PUT_MODE (condition_rtx, DImode);
22644 convert_move (result, condition_rtx, 0);
22648 PUT_MODE (condition_rtx, SImode);
22649 emit_insn (gen_rtx_SET (result, condition_rtx));
22653 /* Emit a branch of kind CODE to location LOC. */
22656 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
22658 rtx condition_rtx, loc_ref;
22660 condition_rtx = rs6000_generate_compare (operands[0], mode);
22661 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
22662 emit_jump_insn (gen_rtx_SET (pc_rtx,
22663 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
22664 loc_ref, pc_rtx)));
22667 /* Return the string to output a conditional branch to LABEL, which is
22668 the operand template of the label, or NULL if the branch is really a
22669 conditional return.
22671 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22672 condition code register and its mode specifies what kind of
22673 comparison we made.
22675 REVERSED is nonzero if we should reverse the sense of the comparison.
22677 INSN is the insn. */
22680 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
22682 static char string[64];
22683 enum rtx_code code = GET_CODE (op);
22684 rtx cc_reg = XEXP (op, 0);
22685 machine_mode mode = GET_MODE (cc_reg);
22686 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
22687 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
22688 int really_reversed = reversed ^ need_longbranch;
22694 validate_condition_mode (code, mode);
22696 /* Work out which way this really branches. We could use
22697 reverse_condition_maybe_unordered here always but this
22698 makes the resulting assembler clearer. */
22699 if (really_reversed)
22701 /* Reversal of FP compares takes care -- an ordered compare
22702 becomes an unordered compare and vice versa. */
22703 if (mode == CCFPmode)
22704 code = reverse_condition_maybe_unordered (code);
22706 code = reverse_condition (code);
22711 /* Not all of these are actually distinct opcodes, but
22712 we distinguish them for clarity of the resulting assembler. */
22713 case NE: case LTGT:
22714 ccode = "ne"; break;
22715 case EQ: case UNEQ:
22716 ccode = "eq"; break;
22718 ccode = "ge"; break;
22719 case GT: case GTU: case UNGT:
22720 ccode = "gt"; break;
22722 ccode = "le"; break;
22723 case LT: case LTU: case UNLT:
22724 ccode = "lt"; break;
22725 case UNORDERED: ccode = "un"; break;
22726 case ORDERED: ccode = "nu"; break;
22727 case UNGE: ccode = "nl"; break;
22728 case UNLE: ccode = "ng"; break;
22730 gcc_unreachable ();
22733 /* Maybe we have a guess as to how likely the branch is. */
22735 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
22736 if (note != NULL_RTX)
22738 /* PROB is the difference from 50%. */
22739 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
22740 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
22742 /* Only hint for highly probable/improbable branches on newer cpus when
22743 we have real profile data, as static prediction overrides processor
22744 dynamic prediction. For older cpus we may as well always hint, but
22745 assume not taken for branches that are very close to 50% as a
22746 mispredicted taken branch is more expensive than a
22747 mispredicted not-taken branch. */
22748 if (rs6000_always_hint
22749 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
22750 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
22751 && br_prob_note_reliable_p (note)))
22753 if (abs (prob) > REG_BR_PROB_BASE / 20
22754 && ((prob > 0) ^ need_longbranch))
22762 s += sprintf (s, "b%slr%s ", ccode, pred);
22764 s += sprintf (s, "b%s%s ", ccode, pred);
22766 /* We need to escape any '%' characters in the reg_names string.
22767 Assume they'd only be the first character.... */
22768 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
22770 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
22774 /* If the branch distance was too far, we may have to use an
22775 unconditional branch to go the distance. */
22776 if (need_longbranch)
22777 s += sprintf (s, ",$+8\n\tb %s", label);
22779 s += sprintf (s, ",%s", label);
22785 /* Return insn for VSX or Altivec comparisons. */
22788 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
22791 machine_mode mode = GET_MODE (op0);
22799 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22810 mask = gen_reg_rtx (mode);
22811 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22818 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22819 DMODE is expected destination mode. This is a recursive function. */
22822 rs6000_emit_vector_compare (enum rtx_code rcode,
22824 machine_mode dmode)
22827 bool swap_operands = false;
22828 bool try_again = false;
22830 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22831 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22833 /* See if the comparison works as is. */
22834 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22842 swap_operands = true;
22847 swap_operands = true;
22855 /* Invert condition and try again.
22856 e.g., A != B becomes ~(A==B). */
22858 enum rtx_code rev_code;
22859 enum insn_code nor_code;
22862 rev_code = reverse_condition_maybe_unordered (rcode);
22863 if (rev_code == UNKNOWN)
22866 nor_code = optab_handler (one_cmpl_optab, dmode);
22867 if (nor_code == CODE_FOR_nothing)
22870 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22874 mask = gen_reg_rtx (dmode);
22875 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22883 /* Try GT/GTU/LT/LTU OR EQ */
22886 enum insn_code ior_code;
22887 enum rtx_code new_code;
22908 gcc_unreachable ();
22911 ior_code = optab_handler (ior_optab, dmode);
22912 if (ior_code == CODE_FOR_nothing)
22915 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22919 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22923 mask = gen_reg_rtx (dmode);
22924 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22935 std::swap (op0, op1);
22937 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22942 /* You only get two chances. */
22946 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22947 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22948 operands for the relation operation COND. */
22951 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22952 rtx cond, rtx cc_op0, rtx cc_op1)
22954 machine_mode dest_mode = GET_MODE (dest);
22955 machine_mode mask_mode = GET_MODE (cc_op0);
22956 enum rtx_code rcode = GET_CODE (cond);
22957 machine_mode cc_mode = CCmode;
22960 bool invert_move = false;
22962 if (VECTOR_UNIT_NONE_P (dest_mode))
22965 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22966 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22970 /* Swap operands if we can, and fall back to doing the operation as
22971 specified, and doing a NOR to invert the test. */
22977 /* Invert condition and try again.
22978 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22979 invert_move = true;
22980 rcode = reverse_condition_maybe_unordered (rcode);
22981 if (rcode == UNKNOWN)
22987 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22989 /* Invert condition to avoid compound test. */
22990 invert_move = true;
22991 rcode = reverse_condition (rcode);
22999 /* Mark unsigned tests with CCUNSmode. */
23000 cc_mode = CCUNSmode;
23002 /* Invert condition to avoid compound test if necessary. */
23003 if (rcode == GEU || rcode == LEU)
23005 invert_move = true;
23006 rcode = reverse_condition (rcode);
23014 /* Get the vector mask for the given relational operations. */
23015 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
23021 std::swap (op_true, op_false);
23023 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
23024 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
23025 && (GET_CODE (op_true) == CONST_VECTOR
23026 || GET_CODE (op_false) == CONST_VECTOR))
23028 rtx constant_0 = CONST0_RTX (dest_mode);
23029 rtx constant_m1 = CONSTM1_RTX (dest_mode);
23031 if (op_true == constant_m1 && op_false == constant_0)
23033 emit_move_insn (dest, mask);
23037 else if (op_true == constant_0 && op_false == constant_m1)
23039 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
23043 /* If we can't use the vector comparison directly, perhaps we can use
23044 the mask for the true or false fields, instead of loading up a
23046 if (op_true == constant_m1)
23049 if (op_false == constant_0)
23053 if (!REG_P (op_true) && !SUBREG_P (op_true))
23054 op_true = force_reg (dest_mode, op_true);
23056 if (!REG_P (op_false) && !SUBREG_P (op_false))
23057 op_false = force_reg (dest_mode, op_false);
23059 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
23060 CONST0_RTX (dest_mode));
23061 emit_insn (gen_rtx_SET (dest,
23062 gen_rtx_IF_THEN_ELSE (dest_mode,
23069 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
23070 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
23071 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
23072 hardware has no such operation. */
23075 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23077 enum rtx_code code = GET_CODE (op);
23078 rtx op0 = XEXP (op, 0);
23079 rtx op1 = XEXP (op, 1);
23080 machine_mode compare_mode = GET_MODE (op0);
23081 machine_mode result_mode = GET_MODE (dest);
23082 bool max_p = false;
23084 if (result_mode != compare_mode)
23087 if (code == GE || code == GT)
23089 else if (code == LE || code == LT)
23094 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
23097 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
23103 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
23107 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
23108 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
23109 operands of the last comparison is nonzero/true, FALSE_COND if it is
23110 zero/false. Return 0 if the hardware has no such operation. */
23113 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23115 enum rtx_code code = GET_CODE (op);
23116 rtx op0 = XEXP (op, 0);
23117 rtx op1 = XEXP (op, 1);
23118 machine_mode result_mode = GET_MODE (dest);
23123 if (!can_create_pseudo_p ())
23136 code = swap_condition (code);
23137 std::swap (op0, op1);
23144 /* Generate: [(parallel [(set (dest)
23145 (if_then_else (op (cmp1) (cmp2))
23148 (clobber (scratch))])]. */
23150 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
23151 cmove_rtx = gen_rtx_SET (dest,
23152 gen_rtx_IF_THEN_ELSE (result_mode,
23157 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
23158 emit_insn (gen_rtx_PARALLEL (VOIDmode,
23159 gen_rtvec (2, cmove_rtx, clobber_rtx)));
23164 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
23165 operands of the last comparison is nonzero/true, FALSE_COND if it
23166 is zero/false. Return 0 if the hardware has no such operation. */
23169 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23171 enum rtx_code code = GET_CODE (op);
23172 rtx op0 = XEXP (op, 0);
23173 rtx op1 = XEXP (op, 1);
23174 machine_mode compare_mode = GET_MODE (op0);
23175 machine_mode result_mode = GET_MODE (dest);
23177 bool is_against_zero;
23179 /* These modes should always match. */
23180 if (GET_MODE (op1) != compare_mode
23181 /* In the isel case however, we can use a compare immediate, so
23182 op1 may be a small constant. */
23183 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
23185 if (GET_MODE (true_cond) != result_mode)
23187 if (GET_MODE (false_cond) != result_mode)
23190 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
23191 if (TARGET_P9_MINMAX
23192 && (compare_mode == SFmode || compare_mode == DFmode)
23193 && (result_mode == SFmode || result_mode == DFmode))
23195 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
23198 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
23202 /* Don't allow using floating point comparisons for integer results for
23204 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
23207 /* First, work out if the hardware can do this at all, or
23208 if it's too slow.... */
23209 if (!FLOAT_MODE_P (compare_mode))
23212 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
23216 is_against_zero = op1 == CONST0_RTX (compare_mode);
23218 /* A floating-point subtract might overflow, underflow, or produce
23219 an inexact result, thus changing the floating-point flags, so it
23220 can't be generated if we care about that. It's safe if one side
23221 of the construct is zero, since then no subtract will be
23223 if (SCALAR_FLOAT_MODE_P (compare_mode)
23224 && flag_trapping_math && ! is_against_zero)
23227 /* Eliminate half of the comparisons by switching operands, this
23228 makes the remaining code simpler. */
23229 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
23230 || code == LTGT || code == LT || code == UNLE)
23232 code = reverse_condition_maybe_unordered (code);
23234 true_cond = false_cond;
23238 /* UNEQ and LTGT take four instructions for a comparison with zero,
23239 it'll probably be faster to use a branch here too. */
23240 if (code == UNEQ && HONOR_NANS (compare_mode))
23243 /* We're going to try to implement comparisons by performing
23244 a subtract, then comparing against zero. Unfortunately,
23245 Inf - Inf is NaN which is not zero, and so if we don't
23246 know that the operand is finite and the comparison
23247 would treat EQ different to UNORDERED, we can't do it. */
23248 if (HONOR_INFINITIES (compare_mode)
23249 && code != GT && code != UNGE
23250 && (GET_CODE (op1) != CONST_DOUBLE
23251 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
23252 /* Constructs of the form (a OP b ? a : b) are safe. */
23253 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
23254 || (! rtx_equal_p (op0, true_cond)
23255 && ! rtx_equal_p (op1, true_cond))))
23258 /* At this point we know we can use fsel. */
23260 /* Reduce the comparison to a comparison against zero. */
23261 if (! is_against_zero)
23263 temp = gen_reg_rtx (compare_mode);
23264 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
23266 op1 = CONST0_RTX (compare_mode);
23269 /* If we don't care about NaNs we can reduce some of the comparisons
23270 down to faster ones. */
23271 if (! HONOR_NANS (compare_mode))
23277 true_cond = false_cond;
23290 /* Now, reduce everything down to a GE. */
23297 temp = gen_reg_rtx (compare_mode);
23298 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23303 temp = gen_reg_rtx (compare_mode);
23304 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
23309 temp = gen_reg_rtx (compare_mode);
23310 emit_insn (gen_rtx_SET (temp,
23311 gen_rtx_NEG (compare_mode,
23312 gen_rtx_ABS (compare_mode, op0))));
23317 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
23318 temp = gen_reg_rtx (result_mode);
23319 emit_insn (gen_rtx_SET (temp,
23320 gen_rtx_IF_THEN_ELSE (result_mode,
23321 gen_rtx_GE (VOIDmode,
23323 true_cond, false_cond)));
23324 false_cond = true_cond;
23327 temp = gen_reg_rtx (compare_mode);
23328 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23333 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
23334 temp = gen_reg_rtx (result_mode);
23335 emit_insn (gen_rtx_SET (temp,
23336 gen_rtx_IF_THEN_ELSE (result_mode,
23337 gen_rtx_GE (VOIDmode,
23339 true_cond, false_cond)));
23340 true_cond = false_cond;
23343 temp = gen_reg_rtx (compare_mode);
23344 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23349 gcc_unreachable ();
23352 emit_insn (gen_rtx_SET (dest,
23353 gen_rtx_IF_THEN_ELSE (result_mode,
23354 gen_rtx_GE (VOIDmode,
23356 true_cond, false_cond)));
23360 /* Same as above, but for ints (isel). */
23363 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23365 rtx condition_rtx, cr;
23366 machine_mode mode = GET_MODE (dest);
23367 enum rtx_code cond_code;
23368 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
23371 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
23374 /* We still have to do the compare, because isel doesn't do a
23375 compare, it just looks at the CRx bits set by a previous compare
23377 condition_rtx = rs6000_generate_compare (op, mode);
23378 cond_code = GET_CODE (condition_rtx);
23379 cr = XEXP (condition_rtx, 0);
23380 signedp = GET_MODE (cr) == CCmode;
23382 isel_func = (mode == SImode
23383 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
23384 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
23388 case LT: case GT: case LTU: case GTU: case EQ:
23389 /* isel handles these directly. */
23393 /* We need to swap the sense of the comparison. */
23395 std::swap (false_cond, true_cond);
23396 PUT_CODE (condition_rtx, reverse_condition (cond_code));
23401 false_cond = force_reg (mode, false_cond);
23402 if (true_cond != const0_rtx)
23403 true_cond = force_reg (mode, true_cond);
23405 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
23411 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
23413 machine_mode mode = GET_MODE (op0);
23417 /* VSX/altivec have direct min/max insns. */
23418 if ((code == SMAX || code == SMIN)
23419 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
23420 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
23422 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
23426 if (code == SMAX || code == SMIN)
23431 if (code == SMAX || code == UMAX)
23432 target = emit_conditional_move (dest, c, op0, op1, mode,
23433 op0, op1, mode, 0);
23435 target = emit_conditional_move (dest, c, op0, op1, mode,
23436 op1, op0, mode, 0);
23437 gcc_assert (target);
23438 if (target != dest)
23439 emit_move_insn (dest, target);
23442 /* A subroutine of the atomic operation splitters. Jump to LABEL if
23443 COND is true. Mark the jump as unlikely to be taken. */
23446 emit_unlikely_jump (rtx cond, rtx label)
23448 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
23449 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
23450 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
23453 /* A subroutine of the atomic operation splitters. Emit a load-locked
23454 instruction in MODE. For QI/HImode, possibly use a pattern than includes
23455 the zero_extend operation. */
23458 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
23460 rtx (*fn) (rtx, rtx) = NULL;
23465 fn = gen_load_lockedqi;
23468 fn = gen_load_lockedhi;
23471 if (GET_MODE (mem) == QImode)
23472 fn = gen_load_lockedqi_si;
23473 else if (GET_MODE (mem) == HImode)
23474 fn = gen_load_lockedhi_si;
23476 fn = gen_load_lockedsi;
23479 fn = gen_load_lockeddi;
23482 fn = gen_load_lockedti;
23485 gcc_unreachable ();
23487 emit_insn (fn (reg, mem));
23490 /* A subroutine of the atomic operation splitters. Emit a store-conditional
23491 instruction in MODE. */
23494 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
23496 rtx (*fn) (rtx, rtx, rtx) = NULL;
23501 fn = gen_store_conditionalqi;
23504 fn = gen_store_conditionalhi;
23507 fn = gen_store_conditionalsi;
23510 fn = gen_store_conditionaldi;
23513 fn = gen_store_conditionalti;
23516 gcc_unreachable ();
23519 /* Emit sync before stwcx. to address PPC405 Erratum. */
23520 if (PPC405_ERRATUM77)
23521 emit_insn (gen_hwsync ());
23523 emit_insn (fn (res, mem, val));
23526 /* Expand barriers before and after a load_locked/store_cond sequence. */
23529 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
23531 rtx addr = XEXP (mem, 0);
23533 if (!legitimate_indirect_address_p (addr, reload_completed)
23534 && !legitimate_indexed_address_p (addr, reload_completed))
23536 addr = force_reg (Pmode, addr);
23537 mem = replace_equiv_address_nv (mem, addr);
23542 case MEMMODEL_RELAXED:
23543 case MEMMODEL_CONSUME:
23544 case MEMMODEL_ACQUIRE:
23546 case MEMMODEL_RELEASE:
23547 case MEMMODEL_ACQ_REL:
23548 emit_insn (gen_lwsync ());
23550 case MEMMODEL_SEQ_CST:
23551 emit_insn (gen_hwsync ());
23554 gcc_unreachable ();
23560 rs6000_post_atomic_barrier (enum memmodel model)
23564 case MEMMODEL_RELAXED:
23565 case MEMMODEL_CONSUME:
23566 case MEMMODEL_RELEASE:
23568 case MEMMODEL_ACQUIRE:
23569 case MEMMODEL_ACQ_REL:
23570 case MEMMODEL_SEQ_CST:
23571 emit_insn (gen_isync ());
23574 gcc_unreachable ();
23578 /* A subroutine of the various atomic expanders. For sub-word operations,
23579 we must adjust things to operate on SImode. Given the original MEM,
23580 return a new aligned memory. Also build and return the quantities by
23581 which to shift and mask. */
23584 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
23586 rtx addr, align, shift, mask, mem;
23587 HOST_WIDE_INT shift_mask;
23588 machine_mode mode = GET_MODE (orig_mem);
23590 /* For smaller modes, we have to implement this via SImode. */
23591 shift_mask = (mode == QImode ? 0x18 : 0x10);
23593 addr = XEXP (orig_mem, 0);
23594 addr = force_reg (GET_MODE (addr), addr);
23596 /* Aligned memory containing subword. Generate a new memory. We
23597 do not want any of the existing MEM_ATTR data, as we're now
23598 accessing memory outside the original object. */
23599 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
23600 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23601 mem = gen_rtx_MEM (SImode, align);
23602 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
23603 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
23604 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
23606 /* Shift amount for subword relative to aligned word. */
23607 shift = gen_reg_rtx (SImode);
23608 addr = gen_lowpart (SImode, addr);
23609 rtx tmp = gen_reg_rtx (SImode);
23610 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
23611 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
23612 if (BYTES_BIG_ENDIAN)
23613 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
23614 shift, 1, OPTAB_LIB_WIDEN);
23617 /* Mask for insertion. */
23618 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
23619 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
23625 /* A subroutine of the various atomic expanders. For sub-word operands,
23626 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23629 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
23633 x = gen_reg_rtx (SImode);
23634 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
23635 gen_rtx_NOT (SImode, mask),
23638 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
23643 /* A subroutine of the various atomic expanders. For sub-word operands,
23644 extract WIDE to NARROW via SHIFT. */
23647 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
23649 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
23650 wide, 1, OPTAB_LIB_WIDEN);
23651 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
23654 /* Expand an atomic compare and swap operation. */
23657 rs6000_expand_atomic_compare_and_swap (rtx operands[])
23659 rtx boolval, retval, mem, oldval, newval, cond;
23660 rtx label1, label2, x, mask, shift;
23661 machine_mode mode, orig_mode;
23662 enum memmodel mod_s, mod_f;
23665 boolval = operands[0];
23666 retval = operands[1];
23668 oldval = operands[3];
23669 newval = operands[4];
23670 is_weak = (INTVAL (operands[5]) != 0);
23671 mod_s = memmodel_base (INTVAL (operands[6]));
23672 mod_f = memmodel_base (INTVAL (operands[7]));
23673 orig_mode = mode = GET_MODE (mem);
23675 mask = shift = NULL_RTX;
23676 if (mode == QImode || mode == HImode)
23678 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23679 lwarx and shift/mask operations. With power8, we need to do the
23680 comparison in SImode, but the store is still done in QI/HImode. */
23681 oldval = convert_modes (SImode, mode, oldval, 1);
23683 if (!TARGET_SYNC_HI_QI)
23685 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23687 /* Shift and mask OLDVAL into position with the word. */
23688 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
23689 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23691 /* Shift and mask NEWVAL into position within the word. */
23692 newval = convert_modes (SImode, mode, newval, 1);
23693 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
23694 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23697 /* Prepare to adjust the return value. */
23698 retval = gen_reg_rtx (SImode);
23701 else if (reg_overlap_mentioned_p (retval, oldval))
23702 oldval = copy_to_reg (oldval);
23704 if (mode != TImode && !reg_or_short_operand (oldval, mode))
23705 oldval = copy_to_mode_reg (mode, oldval);
23707 if (reg_overlap_mentioned_p (retval, newval))
23708 newval = copy_to_reg (newval);
23710 mem = rs6000_pre_atomic_barrier (mem, mod_s);
23715 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23716 emit_label (XEXP (label1, 0));
23718 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23720 emit_load_locked (mode, retval, mem);
23724 x = expand_simple_binop (SImode, AND, retval, mask,
23725 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23727 cond = gen_reg_rtx (CCmode);
23728 /* If we have TImode, synthesize a comparison. */
23729 if (mode != TImode)
23730 x = gen_rtx_COMPARE (CCmode, x, oldval);
23733 rtx xor1_result = gen_reg_rtx (DImode);
23734 rtx xor2_result = gen_reg_rtx (DImode);
23735 rtx or_result = gen_reg_rtx (DImode);
23736 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
23737 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
23738 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
23739 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
23741 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
23742 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
23743 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
23744 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
23747 emit_insn (gen_rtx_SET (cond, x));
23749 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23750 emit_unlikely_jump (x, label2);
23754 x = rs6000_mask_atomic_subword (retval, newval, mask);
23756 emit_store_conditional (orig_mode, cond, mem, x);
23760 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23761 emit_unlikely_jump (x, label1);
23764 if (!is_mm_relaxed (mod_f))
23765 emit_label (XEXP (label2, 0));
23767 rs6000_post_atomic_barrier (mod_s);
23769 if (is_mm_relaxed (mod_f))
23770 emit_label (XEXP (label2, 0));
23773 rs6000_finish_atomic_subword (operands[1], retval, shift);
23774 else if (mode != GET_MODE (operands[1]))
23775 convert_move (operands[1], retval, 1);
23777 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23778 x = gen_rtx_EQ (SImode, cond, const0_rtx);
23779 emit_insn (gen_rtx_SET (boolval, x));
23782 /* Expand an atomic exchange operation. */
23785 rs6000_expand_atomic_exchange (rtx operands[])
23787 rtx retval, mem, val, cond;
23789 enum memmodel model;
23790 rtx label, x, mask, shift;
23792 retval = operands[0];
23795 model = memmodel_base (INTVAL (operands[3]));
23796 mode = GET_MODE (mem);
23798 mask = shift = NULL_RTX;
23799 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
23801 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23803 /* Shift and mask VAL into position with the word. */
23804 val = convert_modes (SImode, mode, val, 1);
23805 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23806 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23808 /* Prepare to adjust the return value. */
23809 retval = gen_reg_rtx (SImode);
23813 mem = rs6000_pre_atomic_barrier (mem, model);
23815 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23816 emit_label (XEXP (label, 0));
23818 emit_load_locked (mode, retval, mem);
23822 x = rs6000_mask_atomic_subword (retval, val, mask);
23824 cond = gen_reg_rtx (CCmode);
23825 emit_store_conditional (mode, cond, mem, x);
23827 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23828 emit_unlikely_jump (x, label);
23830 rs6000_post_atomic_barrier (model);
23833 rs6000_finish_atomic_subword (operands[0], retval, shift);
23836 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23837 to perform. MEM is the memory on which to operate. VAL is the second
23838 operand of the binary operator. BEFORE and AFTER are optional locations to
23839 return the value of MEM either before of after the operation. MODEL_RTX
23840 is a CONST_INT containing the memory model to use. */
23843 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23844 rtx orig_before, rtx orig_after, rtx model_rtx)
23846 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23847 machine_mode mode = GET_MODE (mem);
23848 machine_mode store_mode = mode;
23849 rtx label, x, cond, mask, shift;
23850 rtx before = orig_before, after = orig_after;
23852 mask = shift = NULL_RTX;
23853 /* On power8, we want to use SImode for the operation. On previous systems,
23854 use the operation in a subword and shift/mask to get the proper byte or
23856 if (mode == QImode || mode == HImode)
23858 if (TARGET_SYNC_HI_QI)
23860 val = convert_modes (SImode, mode, val, 1);
23862 /* Prepare to adjust the return value. */
23863 before = gen_reg_rtx (SImode);
23865 after = gen_reg_rtx (SImode);
23870 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23872 /* Shift and mask VAL into position with the word. */
23873 val = convert_modes (SImode, mode, val, 1);
23874 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23875 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23881 /* We've already zero-extended VAL. That is sufficient to
23882 make certain that it does not affect other bits. */
23887 /* If we make certain that all of the other bits in VAL are
23888 set, that will be sufficient to not affect other bits. */
23889 x = gen_rtx_NOT (SImode, mask);
23890 x = gen_rtx_IOR (SImode, x, val);
23891 emit_insn (gen_rtx_SET (val, x));
23898 /* These will all affect bits outside the field and need
23899 adjustment via MASK within the loop. */
23903 gcc_unreachable ();
23906 /* Prepare to adjust the return value. */
23907 before = gen_reg_rtx (SImode);
23909 after = gen_reg_rtx (SImode);
23910 store_mode = mode = SImode;
23914 mem = rs6000_pre_atomic_barrier (mem, model);
23916 label = gen_label_rtx ();
23917 emit_label (label);
23918 label = gen_rtx_LABEL_REF (VOIDmode, label);
23920 if (before == NULL_RTX)
23921 before = gen_reg_rtx (mode);
23923 emit_load_locked (mode, before, mem);
23927 x = expand_simple_binop (mode, AND, before, val,
23928 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23929 after = expand_simple_unop (mode, NOT, x, after, 1);
23933 after = expand_simple_binop (mode, code, before, val,
23934 after, 1, OPTAB_LIB_WIDEN);
23940 x = expand_simple_binop (SImode, AND, after, mask,
23941 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23942 x = rs6000_mask_atomic_subword (before, x, mask);
23944 else if (store_mode != mode)
23945 x = convert_modes (store_mode, mode, x, 1);
23947 cond = gen_reg_rtx (CCmode);
23948 emit_store_conditional (store_mode, cond, mem, x);
23950 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23951 emit_unlikely_jump (x, label);
23953 rs6000_post_atomic_barrier (model);
23957 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23958 then do the calcuations in a SImode register. */
23960 rs6000_finish_atomic_subword (orig_before, before, shift);
23962 rs6000_finish_atomic_subword (orig_after, after, shift);
23964 else if (store_mode != mode)
23966 /* QImode/HImode on machines with lbarx/lharx where we do the native
23967 operation and then do the calcuations in a SImode register. */
23969 convert_move (orig_before, before, 1);
23971 convert_move (orig_after, after, 1);
23973 else if (orig_after && after != orig_after)
23974 emit_move_insn (orig_after, after);
23977 /* Emit instructions to move SRC to DST. Called by splitters for
23978 multi-register moves. It will emit at most one instruction for
23979 each register that is accessed; that is, it won't emit li/lis pairs
23980 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23984 rs6000_split_multireg_move (rtx dst, rtx src)
23986 /* The register number of the first register being moved. */
23988 /* The mode that is to be moved. */
23990 /* The mode that the move is being done in, and its size. */
23991 machine_mode reg_mode;
23993 /* The number of registers that will be moved. */
23996 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
23997 mode = GET_MODE (dst);
23998 nregs = hard_regno_nregs (reg, mode);
23999 if (FP_REGNO_P (reg))
24000 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
24001 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
24002 else if (ALTIVEC_REGNO_P (reg))
24003 reg_mode = V16QImode;
24005 reg_mode = word_mode;
24006 reg_mode_size = GET_MODE_SIZE (reg_mode);
24008 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
24010 /* TDmode residing in FP registers is special, since the ISA requires that
24011 the lower-numbered word of a register pair is always the most significant
24012 word, even in little-endian mode. This does not match the usual subreg
24013 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
24014 the appropriate constituent registers "by hand" in little-endian mode.
24016 Note we do not need to check for destructive overlap here since TDmode
24017 can only reside in even/odd register pairs. */
24018 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
24023 for (i = 0; i < nregs; i++)
24025 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
24026 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
24028 p_src = simplify_gen_subreg (reg_mode, src, mode,
24029 i * reg_mode_size);
24031 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
24032 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
24034 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
24035 i * reg_mode_size);
24037 emit_insn (gen_rtx_SET (p_dst, p_src));
24043 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
24045 /* Move register range backwards, if we might have destructive
24048 for (i = nregs - 1; i >= 0; i--)
24049 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
24050 i * reg_mode_size),
24051 simplify_gen_subreg (reg_mode, src, mode,
24052 i * reg_mode_size)));
24058 bool used_update = false;
24059 rtx restore_basereg = NULL_RTX;
24061 if (MEM_P (src) && INT_REGNO_P (reg))
24065 if (GET_CODE (XEXP (src, 0)) == PRE_INC
24066 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
24069 breg = XEXP (XEXP (src, 0), 0);
24070 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
24071 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
24072 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
24073 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
24074 src = replace_equiv_address (src, breg);
24076 else if (! rs6000_offsettable_memref_p (src, reg_mode))
24078 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
24080 rtx basereg = XEXP (XEXP (src, 0), 0);
24083 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
24084 emit_insn (gen_rtx_SET (ndst,
24085 gen_rtx_MEM (reg_mode,
24087 used_update = true;
24090 emit_insn (gen_rtx_SET (basereg,
24091 XEXP (XEXP (src, 0), 1)));
24092 src = replace_equiv_address (src, basereg);
24096 rtx basereg = gen_rtx_REG (Pmode, reg);
24097 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
24098 src = replace_equiv_address (src, basereg);
24102 breg = XEXP (src, 0);
24103 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
24104 breg = XEXP (breg, 0);
24106 /* If the base register we are using to address memory is
24107 also a destination reg, then change that register last. */
24109 && REGNO (breg) >= REGNO (dst)
24110 && REGNO (breg) < REGNO (dst) + nregs)
24111 j = REGNO (breg) - REGNO (dst);
24113 else if (MEM_P (dst) && INT_REGNO_P (reg))
24117 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
24118 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
24121 breg = XEXP (XEXP (dst, 0), 0);
24122 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
24123 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
24124 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
24126 /* We have to update the breg before doing the store.
24127 Use store with update, if available. */
24131 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
24132 emit_insn (TARGET_32BIT
24133 ? (TARGET_POWERPC64
24134 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
24135 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
24136 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
24137 used_update = true;
24140 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
24141 dst = replace_equiv_address (dst, breg);
24143 else if (!rs6000_offsettable_memref_p (dst, reg_mode)
24144 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
24146 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
24148 rtx basereg = XEXP (XEXP (dst, 0), 0);
24151 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
24152 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
24155 used_update = true;
24158 emit_insn (gen_rtx_SET (basereg,
24159 XEXP (XEXP (dst, 0), 1)));
24160 dst = replace_equiv_address (dst, basereg);
24164 rtx basereg = XEXP (XEXP (dst, 0), 0);
24165 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
24166 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
24168 && REG_P (offsetreg)
24169 && REGNO (basereg) != REGNO (offsetreg));
24170 if (REGNO (basereg) == 0)
24172 rtx tmp = offsetreg;
24173 offsetreg = basereg;
24176 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
24177 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
24178 dst = replace_equiv_address (dst, basereg);
24181 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
24182 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode));
24185 for (i = 0; i < nregs; i++)
24187 /* Calculate index to next subword. */
24192 /* If compiler already emitted move of first word by
24193 store with update, no need to do anything. */
24194 if (j == 0 && used_update)
24197 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
24198 j * reg_mode_size),
24199 simplify_gen_subreg (reg_mode, src, mode,
24200 j * reg_mode_size)));
24202 if (restore_basereg != NULL_RTX)
24203 emit_insn (restore_basereg);
24208 /* This page contains routines that are used to determine what the
24209 function prologue and epilogue code will do and write them out. */
24211 /* Determine whether the REG is really used. */
24214 save_reg_p (int reg)
24216 /* We need to mark the PIC offset register live for the same conditions
24217 as it is set up, or otherwise it won't be saved before we clobber it. */
24219 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
24221 /* When calling eh_return, we must return true for all the cases
24222 where conditional_register_usage marks the PIC offset reg
24224 if (TARGET_TOC && TARGET_MINIMAL_TOC
24225 && (crtl->calls_eh_return
24226 || df_regs_ever_live_p (reg)
24227 || !constant_pool_empty_p ()))
24230 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
24235 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
24238 /* Return the first fixed-point register that is required to be
24239 saved. 32 if none. */
24242 first_reg_to_save (void)
24246 /* Find lowest numbered live register. */
24247 for (first_reg = 13; first_reg <= 31; first_reg++)
24248 if (save_reg_p (first_reg))
24253 && crtl->uses_pic_offset_table
24254 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
24255 return RS6000_PIC_OFFSET_TABLE_REGNUM;
24261 /* Similar, for FP regs. */
24264 first_fp_reg_to_save (void)
24268 /* Find lowest numbered live register. */
24269 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
24270 if (save_reg_p (first_reg))
24276 /* Similar, for AltiVec regs. */
24279 first_altivec_reg_to_save (void)
24283 /* Stack frame remains as is unless we are in AltiVec ABI. */
24284 if (! TARGET_ALTIVEC_ABI)
24285 return LAST_ALTIVEC_REGNO + 1;
24287 /* On Darwin, the unwind routines are compiled without
24288 TARGET_ALTIVEC, and use save_world to save/restore the
24289 altivec registers when necessary. */
24290 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
24291 && ! TARGET_ALTIVEC)
24292 return FIRST_ALTIVEC_REGNO + 20;
24294 /* Find lowest numbered live register. */
24295 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
24296 if (save_reg_p (i))
24302 /* Return a 32-bit mask of the AltiVec registers we need to set in
24303 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
24304 the 32-bit word is 0. */
24306 static unsigned int
24307 compute_vrsave_mask (void)
24309 unsigned int i, mask = 0;
24311 /* On Darwin, the unwind routines are compiled without
24312 TARGET_ALTIVEC, and use save_world to save/restore the
24313 call-saved altivec registers when necessary. */
24314 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
24315 && ! TARGET_ALTIVEC)
24318 /* First, find out if we use _any_ altivec registers. */
24319 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
24320 if (df_regs_ever_live_p (i))
24321 mask |= ALTIVEC_REG_BIT (i);
24326 /* Next, remove the argument registers from the set. These must
24327 be in the VRSAVE mask set by the caller, so we don't need to add
24328 them in again. More importantly, the mask we compute here is
24329 used to generate CLOBBERs in the set_vrsave insn, and we do not
24330 wish the argument registers to die. */
24331 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
24332 mask &= ~ALTIVEC_REG_BIT (i);
24334 /* Similarly, remove the return value from the set. */
24337 diddle_return_value (is_altivec_return_reg, &yes);
24339 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
24345 /* For a very restricted set of circumstances, we can cut down the
24346 size of prologues/epilogues by calling our own save/restore-the-world
24350 compute_save_world_info (rs6000_stack_t *info)
24352 info->world_save_p = 1;
24354 = (WORLD_SAVE_P (info)
24355 && DEFAULT_ABI == ABI_DARWIN
24356 && !cfun->has_nonlocal_label
24357 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
24358 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
24359 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
24360 && info->cr_save_p);
24362 /* This will not work in conjunction with sibcalls. Make sure there
24363 are none. (This check is expensive, but seldom executed.) */
24364 if (WORLD_SAVE_P (info))
24367 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
24368 if (CALL_P (insn) && SIBLING_CALL_P (insn))
24370 info->world_save_p = 0;
24375 if (WORLD_SAVE_P (info))
24377 /* Even if we're not touching VRsave, make sure there's room on the
24378 stack for it, if it looks like we're calling SAVE_WORLD, which
24379 will attempt to save it. */
24380 info->vrsave_size = 4;
24382 /* If we are going to save the world, we need to save the link register too. */
24383 info->lr_save_p = 1;
24385 /* "Save" the VRsave register too if we're saving the world. */
24386 if (info->vrsave_mask == 0)
24387 info->vrsave_mask = compute_vrsave_mask ();
24389 /* Because the Darwin register save/restore routines only handle
24390 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
24392 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
24393 && (info->first_altivec_reg_save
24394 >= FIRST_SAVED_ALTIVEC_REGNO));
24402 is_altivec_return_reg (rtx reg, void *xyes)
24404 bool *yes = (bool *) xyes;
24405 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
24410 /* Return whether REG is a global user reg or has been specifed by
24411 -ffixed-REG. We should not restore these, and so cannot use
24412 lmw or out-of-line restore functions if there are any. We also
24413 can't save them (well, emit frame notes for them), because frame
24414 unwinding during exception handling will restore saved registers. */
24417 fixed_reg_p (int reg)
24419 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
24420 backend sets it, overriding anything the user might have given. */
24421 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
24422 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
24423 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
24424 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
24427 return fixed_regs[reg];
24430 /* Determine the strategy for savings/restoring registers. */
24433 SAVE_MULTIPLE = 0x1,
24434 SAVE_INLINE_GPRS = 0x2,
24435 SAVE_INLINE_FPRS = 0x4,
24436 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
24437 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
24438 SAVE_INLINE_VRS = 0x20,
24439 REST_MULTIPLE = 0x100,
24440 REST_INLINE_GPRS = 0x200,
24441 REST_INLINE_FPRS = 0x400,
24442 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
24443 REST_INLINE_VRS = 0x1000
24447 rs6000_savres_strategy (rs6000_stack_t *info,
24448 bool using_static_chain_p)
24452 /* Select between in-line and out-of-line save and restore of regs.
24453 First, all the obvious cases where we don't use out-of-line. */
24454 if (crtl->calls_eh_return
24455 || cfun->machine->ra_need_lr)
24456 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
24457 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
24458 | SAVE_INLINE_VRS | REST_INLINE_VRS);
24460 if (info->first_gp_reg_save == 32)
24461 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24463 if (info->first_fp_reg_save == 64
24464 /* The out-of-line FP routines use double-precision stores;
24465 we can't use those routines if we don't have such stores. */
24466 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
24467 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24469 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
24470 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24472 /* Define cutoff for using out-of-line functions to save registers. */
24473 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
24475 if (!optimize_size)
24477 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24478 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24479 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24483 /* Prefer out-of-line restore if it will exit. */
24484 if (info->first_fp_reg_save > 61)
24485 strategy |= SAVE_INLINE_FPRS;
24486 if (info->first_gp_reg_save > 29)
24488 if (info->first_fp_reg_save == 64)
24489 strategy |= SAVE_INLINE_GPRS;
24491 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24493 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
24494 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24497 else if (DEFAULT_ABI == ABI_DARWIN)
24499 if (info->first_fp_reg_save > 60)
24500 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24501 if (info->first_gp_reg_save > 29)
24502 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24503 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24507 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24508 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
24509 || info->first_fp_reg_save > 61)
24510 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24511 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24512 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24515 /* Don't bother to try to save things out-of-line if r11 is occupied
24516 by the static chain. It would require too much fiddling and the
24517 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24518 pointer on Darwin, and AIX uses r1 or r12. */
24519 if (using_static_chain_p
24520 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
24521 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
24523 | SAVE_INLINE_VRS);
24525 /* Don't ever restore fixed regs. That means we can't use the
24526 out-of-line register restore functions if a fixed reg is in the
24527 range of regs restored. */
24528 if (!(strategy & REST_INLINE_FPRS))
24529 for (int i = info->first_fp_reg_save; i < 64; i++)
24532 strategy |= REST_INLINE_FPRS;
24536 /* We can only use the out-of-line routines to restore fprs if we've
24537 saved all the registers from first_fp_reg_save in the prologue.
24538 Otherwise, we risk loading garbage. Of course, if we have saved
24539 out-of-line then we know we haven't skipped any fprs. */
24540 if ((strategy & SAVE_INLINE_FPRS)
24541 && !(strategy & REST_INLINE_FPRS))
24542 for (int i = info->first_fp_reg_save; i < 64; i++)
24543 if (!save_reg_p (i))
24545 strategy |= REST_INLINE_FPRS;
24549 /* Similarly, for altivec regs. */
24550 if (!(strategy & REST_INLINE_VRS))
24551 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24554 strategy |= REST_INLINE_VRS;
24558 if ((strategy & SAVE_INLINE_VRS)
24559 && !(strategy & REST_INLINE_VRS))
24560 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24561 if (!save_reg_p (i))
24563 strategy |= REST_INLINE_VRS;
24567 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24568 saved is an out-of-line save or restore. Set up the value for
24569 the next test (excluding out-of-line gprs). */
24570 bool lr_save_p = (info->lr_save_p
24571 || !(strategy & SAVE_INLINE_FPRS)
24572 || !(strategy & SAVE_INLINE_VRS)
24573 || !(strategy & REST_INLINE_FPRS)
24574 || !(strategy & REST_INLINE_VRS));
24576 if (TARGET_MULTIPLE
24577 && !TARGET_POWERPC64
24578 && info->first_gp_reg_save < 31
24579 && !(flag_shrink_wrap
24580 && flag_shrink_wrap_separate
24581 && optimize_function_for_speed_p (cfun)))
24584 for (int i = info->first_gp_reg_save; i < 32; i++)
24585 if (save_reg_p (i))
24589 /* Don't use store multiple if only one reg needs to be
24590 saved. This can occur for example when the ABI_V4 pic reg
24591 (r30) needs to be saved to make calls, but r31 is not
24593 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24596 /* Prefer store multiple for saves over out-of-line
24597 routines, since the store-multiple instruction will
24598 always be smaller. */
24599 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
24601 /* The situation is more complicated with load multiple.
24602 We'd prefer to use the out-of-line routines for restores,
24603 since the "exit" out-of-line routines can handle the
24604 restore of LR and the frame teardown. However if doesn't
24605 make sense to use the out-of-line routine if that is the
24606 only reason we'd need to save LR, and we can't use the
24607 "exit" out-of-line gpr restore if we have saved some
24608 fprs; In those cases it is advantageous to use load
24609 multiple when available. */
24610 if (info->first_fp_reg_save != 64 || !lr_save_p)
24611 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
24615 /* Using the "exit" out-of-line routine does not improve code size
24616 if using it would require lr to be saved and if only saving one
24618 else if (!lr_save_p && info->first_gp_reg_save > 29)
24619 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24621 /* Don't ever restore fixed regs. */
24622 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24623 for (int i = info->first_gp_reg_save; i < 32; i++)
24624 if (fixed_reg_p (i))
24626 strategy |= REST_INLINE_GPRS;
24627 strategy &= ~REST_MULTIPLE;
24631 /* We can only use load multiple or the out-of-line routines to
24632 restore gprs if we've saved all the registers from
24633 first_gp_reg_save. Otherwise, we risk loading garbage.
24634 Of course, if we have saved out-of-line or used stmw then we know
24635 we haven't skipped any gprs. */
24636 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
24637 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24638 for (int i = info->first_gp_reg_save; i < 32; i++)
24639 if (!save_reg_p (i))
24641 strategy |= REST_INLINE_GPRS;
24642 strategy &= ~REST_MULTIPLE;
24646 if (TARGET_ELF && TARGET_64BIT)
24648 if (!(strategy & SAVE_INLINE_FPRS))
24649 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24650 else if (!(strategy & SAVE_INLINE_GPRS)
24651 && info->first_fp_reg_save == 64)
24652 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
24654 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
24655 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
24657 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
24658 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24663 /* Calculate the stack information for the current function. This is
24664 complicated by having two separate calling sequences, the AIX calling
24665 sequence and the V.4 calling sequence.
24667 AIX (and Darwin/Mac OS X) stack frames look like:
24669 SP----> +---------------------------------------+
24670 | back chain to caller | 0 0
24671 +---------------------------------------+
24672 | saved CR | 4 8 (8-11)
24673 +---------------------------------------+
24675 +---------------------------------------+
24676 | reserved for compilers | 12 24
24677 +---------------------------------------+
24678 | reserved for binders | 16 32
24679 +---------------------------------------+
24680 | saved TOC pointer | 20 40
24681 +---------------------------------------+
24682 | Parameter save area (+padding*) (P) | 24 48
24683 +---------------------------------------+
24684 | Alloca space (A) | 24+P etc.
24685 +---------------------------------------+
24686 | Local variable space (L) | 24+P+A
24687 +---------------------------------------+
24688 | Float/int conversion temporary (X) | 24+P+A+L
24689 +---------------------------------------+
24690 | Save area for AltiVec registers (W) | 24+P+A+L+X
24691 +---------------------------------------+
24692 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24693 +---------------------------------------+
24694 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24695 +---------------------------------------+
24696 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24697 +---------------------------------------+
24698 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24699 +---------------------------------------+
24700 old SP->| back chain to caller's caller |
24701 +---------------------------------------+
24703 * If the alloca area is present, the parameter save area is
24704 padded so that the former starts 16-byte aligned.
24706 The required alignment for AIX configurations is two words (i.e., 8
24709 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24711 SP----> +---------------------------------------+
24712 | Back chain to caller | 0
24713 +---------------------------------------+
24714 | Save area for CR | 8
24715 +---------------------------------------+
24717 +---------------------------------------+
24718 | Saved TOC pointer | 24
24719 +---------------------------------------+
24720 | Parameter save area (+padding*) (P) | 32
24721 +---------------------------------------+
24722 | Alloca space (A) | 32+P
24723 +---------------------------------------+
24724 | Local variable space (L) | 32+P+A
24725 +---------------------------------------+
24726 | Save area for AltiVec registers (W) | 32+P+A+L
24727 +---------------------------------------+
24728 | AltiVec alignment padding (Y) | 32+P+A+L+W
24729 +---------------------------------------+
24730 | Save area for GP registers (G) | 32+P+A+L+W+Y
24731 +---------------------------------------+
24732 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24733 +---------------------------------------+
24734 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24735 +---------------------------------------+
24737 * If the alloca area is present, the parameter save area is
24738 padded so that the former starts 16-byte aligned.
24740 V.4 stack frames look like:
24742 SP----> +---------------------------------------+
24743 | back chain to caller | 0
24744 +---------------------------------------+
24745 | caller's saved LR | 4
24746 +---------------------------------------+
24747 | Parameter save area (+padding*) (P) | 8
24748 +---------------------------------------+
24749 | Alloca space (A) | 8+P
24750 +---------------------------------------+
24751 | Varargs save area (V) | 8+P+A
24752 +---------------------------------------+
24753 | Local variable space (L) | 8+P+A+V
24754 +---------------------------------------+
24755 | Float/int conversion temporary (X) | 8+P+A+V+L
24756 +---------------------------------------+
24757 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24758 +---------------------------------------+
24759 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24760 +---------------------------------------+
24761 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24762 +---------------------------------------+
24763 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24764 +---------------------------------------+
24765 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24766 +---------------------------------------+
24767 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24768 +---------------------------------------+
24769 old SP->| back chain to caller's caller |
24770 +---------------------------------------+
24772 * If the alloca area is present and the required alignment is
24773 16 bytes, the parameter save area is padded so that the
24774 alloca area starts 16-byte aligned.
24776 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24777 given. (But note below and in sysv4.h that we require only 8 and
24778 may round up the size of our stack frame anyways. The historical
24779 reason is early versions of powerpc-linux which didn't properly
24780 align the stack at program startup. A happy side-effect is that
24781 -mno-eabi libraries can be used with -meabi programs.)
24783 The EABI configuration defaults to the V.4 layout. However,
24784 the stack alignment requirements may differ. If -mno-eabi is not
24785 given, the required stack alignment is 8 bytes; if -mno-eabi is
24786 given, the required alignment is 16 bytes. (But see V.4 comment
24789 #ifndef ABI_STACK_BOUNDARY
24790 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24793 static rs6000_stack_t *
24794 rs6000_stack_info (void)
24796 /* We should never be called for thunks, we are not set up for that. */
24797 gcc_assert (!cfun->is_thunk);
24799 rs6000_stack_t *info = &stack_info;
24800 int reg_size = TARGET_32BIT ? 4 : 8;
24805 HOST_WIDE_INT non_fixed_size;
24806 bool using_static_chain_p;
24808 if (reload_completed && info->reload_completed)
24811 memset (info, 0, sizeof (*info));
24812 info->reload_completed = reload_completed;
24814 /* Select which calling sequence. */
24815 info->abi = DEFAULT_ABI;
24817 /* Calculate which registers need to be saved & save area size. */
24818 info->first_gp_reg_save = first_reg_to_save ();
24819 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24820 even if it currently looks like we won't. Reload may need it to
24821 get at a constant; if so, it will have already created a constant
24822 pool entry for it. */
24823 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24824 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24825 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24826 && crtl->uses_const_pool
24827 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24828 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24830 first_gp = info->first_gp_reg_save;
24832 info->gp_size = reg_size * (32 - first_gp);
24834 info->first_fp_reg_save = first_fp_reg_to_save ();
24835 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24837 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24838 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24839 - info->first_altivec_reg_save);
24841 /* Does this function call anything? */
24842 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24844 /* Determine if we need to save the condition code registers. */
24845 if (save_reg_p (CR2_REGNO)
24846 || save_reg_p (CR3_REGNO)
24847 || save_reg_p (CR4_REGNO))
24849 info->cr_save_p = 1;
24850 if (DEFAULT_ABI == ABI_V4)
24851 info->cr_size = reg_size;
24854 /* If the current function calls __builtin_eh_return, then we need
24855 to allocate stack space for registers that will hold data for
24856 the exception handler. */
24857 if (crtl->calls_eh_return)
24860 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24863 ehrd_size = i * UNITS_PER_WORD;
24868 /* In the ELFv2 ABI, we also need to allocate space for separate
24869 CR field save areas if the function calls __builtin_eh_return. */
24870 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24872 /* This hard-codes that we have three call-saved CR fields. */
24873 ehcr_size = 3 * reg_size;
24874 /* We do *not* use the regular CR save mechanism. */
24875 info->cr_save_p = 0;
24880 /* Determine various sizes. */
24881 info->reg_size = reg_size;
24882 info->fixed_size = RS6000_SAVE_AREA;
24883 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24884 if (cfun->calls_alloca)
24886 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24887 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24889 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24890 TARGET_ALTIVEC ? 16 : 8);
24891 if (FRAME_GROWS_DOWNWARD)
24893 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24894 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24895 - (info->fixed_size + info->vars_size + info->parm_size);
24897 if (TARGET_ALTIVEC_ABI)
24898 info->vrsave_mask = compute_vrsave_mask ();
24900 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24901 info->vrsave_size = 4;
24903 compute_save_world_info (info);
24905 /* Calculate the offsets. */
24906 switch (DEFAULT_ABI)
24910 gcc_unreachable ();
24915 info->fp_save_offset = -info->fp_size;
24916 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24918 if (TARGET_ALTIVEC_ABI)
24920 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24922 /* Align stack so vector save area is on a quadword boundary.
24923 The padding goes above the vectors. */
24924 if (info->altivec_size != 0)
24925 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24927 info->altivec_save_offset = info->vrsave_save_offset
24928 - info->altivec_padding_size
24929 - info->altivec_size;
24930 gcc_assert (info->altivec_size == 0
24931 || info->altivec_save_offset % 16 == 0);
24933 /* Adjust for AltiVec case. */
24934 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24937 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24939 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24940 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24941 info->lr_save_offset = 2*reg_size;
24945 info->fp_save_offset = -info->fp_size;
24946 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24947 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24949 if (TARGET_ALTIVEC_ABI)
24951 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24953 /* Align stack so vector save area is on a quadword boundary. */
24954 if (info->altivec_size != 0)
24955 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24957 info->altivec_save_offset = info->vrsave_save_offset
24958 - info->altivec_padding_size
24959 - info->altivec_size;
24961 /* Adjust for AltiVec case. */
24962 info->ehrd_offset = info->altivec_save_offset;
24965 info->ehrd_offset = info->cr_save_offset;
24967 info->ehrd_offset -= ehrd_size;
24968 info->lr_save_offset = reg_size;
24971 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
24972 info->save_size = RS6000_ALIGN (info->fp_size
24974 + info->altivec_size
24975 + info->altivec_padding_size
24979 + info->vrsave_size,
24982 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
24984 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
24985 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
24987 /* Determine if we need to save the link register. */
24989 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24991 && !TARGET_PROFILE_KERNEL)
24992 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
24993 #ifdef TARGET_RELOCATABLE
24994 || (DEFAULT_ABI == ABI_V4
24995 && (TARGET_RELOCATABLE || flag_pic > 1)
24996 && !constant_pool_empty_p ())
24998 || rs6000_ra_ever_killed ())
24999 info->lr_save_p = 1;
25001 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
25002 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
25003 && call_used_regs[STATIC_CHAIN_REGNUM]);
25004 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
25006 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
25007 || !(info->savres_strategy & SAVE_INLINE_FPRS)
25008 || !(info->savres_strategy & SAVE_INLINE_VRS)
25009 || !(info->savres_strategy & REST_INLINE_GPRS)
25010 || !(info->savres_strategy & REST_INLINE_FPRS)
25011 || !(info->savres_strategy & REST_INLINE_VRS))
25012 info->lr_save_p = 1;
25014 if (info->lr_save_p)
25015 df_set_regs_ever_live (LR_REGNO, true);
25017 /* Determine if we need to allocate any stack frame:
25019 For AIX we need to push the stack if a frame pointer is needed
25020 (because the stack might be dynamically adjusted), if we are
25021 debugging, if we make calls, or if the sum of fp_save, gp_save,
25022 and local variables are more than the space needed to save all
25023 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
25024 + 18*8 = 288 (GPR13 reserved).
25026 For V.4 we don't have the stack cushion that AIX uses, but assume
25027 that the debugger can handle stackless frames. */
25032 else if (DEFAULT_ABI == ABI_V4)
25033 info->push_p = non_fixed_size != 0;
25035 else if (frame_pointer_needed)
25038 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
25042 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
25048 debug_stack_info (rs6000_stack_t *info)
25050 const char *abi_string;
25053 info = rs6000_stack_info ();
25055 fprintf (stderr, "\nStack information for function %s:\n",
25056 ((current_function_decl && DECL_NAME (current_function_decl))
25057 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
25062 default: abi_string = "Unknown"; break;
25063 case ABI_NONE: abi_string = "NONE"; break;
25064 case ABI_AIX: abi_string = "AIX"; break;
25065 case ABI_ELFv2: abi_string = "ELFv2"; break;
25066 case ABI_DARWIN: abi_string = "Darwin"; break;
25067 case ABI_V4: abi_string = "V.4"; break;
25070 fprintf (stderr, "\tABI = %5s\n", abi_string);
25072 if (TARGET_ALTIVEC_ABI)
25073 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
25075 if (info->first_gp_reg_save != 32)
25076 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
25078 if (info->first_fp_reg_save != 64)
25079 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
25081 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
25082 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
25083 info->first_altivec_reg_save);
25085 if (info->lr_save_p)
25086 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
25088 if (info->cr_save_p)
25089 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
25091 if (info->vrsave_mask)
25092 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
25095 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
25098 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
25101 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
25104 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
25106 if (info->altivec_size)
25107 fprintf (stderr, "\taltivec_save_offset = %5d\n",
25108 info->altivec_save_offset);
25110 if (info->vrsave_size)
25111 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
25112 info->vrsave_save_offset);
25114 if (info->lr_save_p)
25115 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
25117 if (info->cr_save_p)
25118 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
25120 if (info->varargs_save_offset)
25121 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
25123 if (info->total_size)
25124 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
25127 if (info->vars_size)
25128 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
25131 if (info->parm_size)
25132 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
25134 if (info->fixed_size)
25135 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
25138 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
25141 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
25143 if (info->altivec_size)
25144 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
25146 if (info->vrsave_size)
25147 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
25149 if (info->altivec_padding_size)
25150 fprintf (stderr, "\taltivec_padding_size= %5d\n",
25151 info->altivec_padding_size);
25154 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
25156 if (info->save_size)
25157 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
25159 if (info->reg_size != 4)
25160 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
25162 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
25164 fprintf (stderr, "\n");
25168 rs6000_return_addr (int count, rtx frame)
25170 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
25171 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
25173 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
25175 cfun->machine->ra_needs_full_frame = 1;
25178 /* FRAME is set to frame_pointer_rtx by the generic code, but that
25179 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
25180 frame = stack_pointer_rtx;
25181 rtx prev_frame_addr = memory_address (Pmode, frame);
25182 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
25183 rtx lr_save_off = plus_constant (Pmode,
25184 prev_frame, RETURN_ADDRESS_OFFSET);
25185 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
25186 return gen_rtx_MEM (Pmode, lr_save_addr);
25189 cfun->machine->ra_need_lr = 1;
25190 return get_hard_reg_initial_val (Pmode, LR_REGNO);
25193 /* Say whether a function is a candidate for sibcall handling or not. */
25196 rs6000_function_ok_for_sibcall (tree decl, tree exp)
25201 fntype = TREE_TYPE (decl);
25203 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
25205 /* We can't do it if the called function has more vector parameters
25206 than the current function; there's nowhere to put the VRsave code. */
25207 if (TARGET_ALTIVEC_ABI
25208 && TARGET_ALTIVEC_VRSAVE
25209 && !(decl && decl == current_function_decl))
25211 function_args_iterator args_iter;
25215 /* Functions with vector parameters are required to have a
25216 prototype, so the argument type info must be available
25218 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
25219 if (TREE_CODE (type) == VECTOR_TYPE
25220 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
25223 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
25224 if (TREE_CODE (type) == VECTOR_TYPE
25225 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
25232 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
25233 functions, because the callee may have a different TOC pointer to
25234 the caller and there's no way to ensure we restore the TOC when
25235 we return. With the secure-plt SYSV ABI we can't make non-local
25236 calls when -fpic/PIC because the plt call stubs use r30. */
25237 if (DEFAULT_ABI == ABI_DARWIN
25238 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25240 && !DECL_EXTERNAL (decl)
25241 && !DECL_WEAK (decl)
25242 && (*targetm.binds_local_p) (decl))
25243 || (DEFAULT_ABI == ABI_V4
25244 && (!TARGET_SECURE_PLT
25247 && (*targetm.binds_local_p) (decl)))))
25249 tree attr_list = TYPE_ATTRIBUTES (fntype);
25251 if (!lookup_attribute ("longcall", attr_list)
25252 || lookup_attribute ("shortcall", attr_list))
25260 rs6000_ra_ever_killed (void)
25266 if (cfun->is_thunk)
25269 if (cfun->machine->lr_save_state)
25270 return cfun->machine->lr_save_state - 1;
25272 /* regs_ever_live has LR marked as used if any sibcalls are present,
25273 but this should not force saving and restoring in the
25274 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
25275 clobbers LR, so that is inappropriate. */
25277 /* Also, the prologue can generate a store into LR that
25278 doesn't really count, like this:
25281 bcl to set PIC register
25285 When we're called from the epilogue, we need to avoid counting
25286 this as a store. */
25288 push_topmost_sequence ();
25289 top = get_insns ();
25290 pop_topmost_sequence ();
25291 reg = gen_rtx_REG (Pmode, LR_REGNO);
25293 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
25299 if (!SIBLING_CALL_P (insn))
25302 else if (find_regno_note (insn, REG_INC, LR_REGNO))
25304 else if (set_of (reg, insn) != NULL_RTX
25305 && !prologue_epilogue_contains (insn))
25312 /* Emit instructions needed to load the TOC register.
25313 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
25314 a constant pool; or for SVR4 -fpic. */
25317 rs6000_emit_load_toc_table (int fromprolog)
25320 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
25322 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
25325 rtx lab, tmp1, tmp2, got;
25327 lab = gen_label_rtx ();
25328 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
25329 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25332 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25336 got = rs6000_got_sym ();
25337 tmp1 = tmp2 = dest;
25340 tmp1 = gen_reg_rtx (Pmode);
25341 tmp2 = gen_reg_rtx (Pmode);
25343 emit_insn (gen_load_toc_v4_PIC_1 (lab));
25344 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
25345 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
25346 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
25348 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
25350 emit_insn (gen_load_toc_v4_pic_si ());
25351 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25353 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
25356 rtx temp0 = (fromprolog
25357 ? gen_rtx_REG (Pmode, 0)
25358 : gen_reg_rtx (Pmode));
25364 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
25365 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25367 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
25368 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25370 emit_insn (gen_load_toc_v4_PIC_1 (symF));
25371 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25372 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
25378 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25380 lab = gen_label_rtx ();
25381 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
25382 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25383 if (TARGET_LINK_STACK)
25384 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
25385 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
25387 emit_insn (gen_addsi3 (dest, temp0, dest));
25389 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
25391 /* This is for AIX code running in non-PIC ELF32. */
25392 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25395 emit_insn (gen_elf_high (dest, realsym));
25396 emit_insn (gen_elf_low (dest, dest, realsym));
25400 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
25403 emit_insn (gen_load_toc_aix_si (dest));
25405 emit_insn (gen_load_toc_aix_di (dest));
25409 /* Emit instructions to restore the link register after determining where
25410 its value has been stored. */
25413 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
25415 rs6000_stack_t *info = rs6000_stack_info ();
25418 operands[0] = source;
25419 operands[1] = scratch;
25421 if (info->lr_save_p)
25423 rtx frame_rtx = stack_pointer_rtx;
25424 HOST_WIDE_INT sp_offset = 0;
25427 if (frame_pointer_needed
25428 || cfun->calls_alloca
25429 || info->total_size > 32767)
25431 tmp = gen_frame_mem (Pmode, frame_rtx);
25432 emit_move_insn (operands[1], tmp);
25433 frame_rtx = operands[1];
25435 else if (info->push_p)
25436 sp_offset = info->total_size;
25438 tmp = plus_constant (Pmode, frame_rtx,
25439 info->lr_save_offset + sp_offset);
25440 tmp = gen_frame_mem (Pmode, tmp);
25441 emit_move_insn (tmp, operands[0]);
25444 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
25446 /* Freeze lr_save_p. We've just emitted rtl that depends on the
25447 state of lr_save_p so any change from here on would be a bug. In
25448 particular, stop rs6000_ra_ever_killed from considering the SET
25449 of lr we may have added just above. */
25450 cfun->machine->lr_save_state = info->lr_save_p + 1;
25453 static GTY(()) alias_set_type set = -1;
25456 get_TOC_alias_set (void)
25459 set = new_alias_set ();
25463 /* This returns nonzero if the current function uses the TOC. This is
25464 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
25465 is generated by the ABI_V4 load_toc_* patterns.
25466 Return 2 instead of 1 if the load_toc_* pattern is in the function
25467 partition that doesn't start the function. */
25475 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
25479 rtx pat = PATTERN (insn);
25482 if (GET_CODE (pat) == PARALLEL)
25483 for (i = 0; i < XVECLEN (pat, 0); i++)
25485 rtx sub = XVECEXP (pat, 0, i);
25486 if (GET_CODE (sub) == USE)
25488 sub = XEXP (sub, 0);
25489 if (GET_CODE (sub) == UNSPEC
25490 && XINT (sub, 1) == UNSPEC_TOC)
25495 else if (crtl->has_bb_partition
25497 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
25505 create_TOC_reference (rtx symbol, rtx largetoc_reg)
25507 rtx tocrel, tocreg, hi;
25509 if (TARGET_DEBUG_ADDR)
25511 if (GET_CODE (symbol) == SYMBOL_REF)
25512 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25516 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
25517 GET_RTX_NAME (GET_CODE (symbol)));
25518 debug_rtx (symbol);
25522 if (!can_create_pseudo_p ())
25523 df_set_regs_ever_live (TOC_REGISTER, true);
25525 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
25526 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
25527 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
25530 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
25531 if (largetoc_reg != NULL)
25533 emit_move_insn (largetoc_reg, hi);
25536 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
25539 /* Issue assembly directives that create a reference to the given DWARF
25540 FRAME_TABLE_LABEL from the current function section. */
25542 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
25544 fprintf (asm_out_file, "\t.ref %s\n",
25545 (* targetm.strip_name_encoding) (frame_table_label));
25548 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25549 and the change to the stack pointer. */
25552 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
25559 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25560 if (hard_frame_needed)
25561 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
25562 if (!(REGNO (fp) == STACK_POINTER_REGNUM
25563 || (hard_frame_needed
25564 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
25567 p = rtvec_alloc (i);
25570 rtx mem = gen_frame_mem (BLKmode, regs[i]);
25571 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
25574 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
25577 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
25578 and set the appropriate attributes for the generated insn. Return the
25579 first insn which adjusts the stack pointer or the last insn before
25580 the stack adjustment loop.
25582 SIZE_INT is used to create the CFI note for the allocation.
25584 SIZE_RTX is an rtx containing the size of the adjustment. Note that
25585 since stacks grow to lower addresses its runtime value is -SIZE_INT.
25587 ORIG_SP contains the backchain value that must be stored at *sp. */
25590 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
25594 rtx size_rtx = GEN_INT (-size_int);
25595 if (size_int > 32767)
25597 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25598 /* Need a note here so that try_split doesn't get confused. */
25599 if (get_last_insn () == NULL_RTX)
25600 emit_note (NOTE_INSN_DELETED);
25601 insn = emit_move_insn (tmp_reg, size_rtx);
25602 try_split (PATTERN (insn), insn, 0);
25603 size_rtx = tmp_reg;
25606 if (Pmode == SImode)
25607 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
25612 insn = emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx,
25616 rtx par = PATTERN (insn);
25617 gcc_assert (GET_CODE (par) == PARALLEL);
25618 rtx set = XVECEXP (par, 0, 0);
25619 gcc_assert (GET_CODE (set) == SET);
25620 rtx mem = SET_DEST (set);
25621 gcc_assert (MEM_P (mem));
25622 MEM_NOTRAP_P (mem) = 1;
25623 set_mem_alias_set (mem, get_frame_alias_set ());
25625 RTX_FRAME_RELATED_P (insn) = 1;
25626 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25627 gen_rtx_SET (stack_pointer_rtx,
25628 gen_rtx_PLUS (Pmode,
25630 GEN_INT (-size_int))));
25632 /* Emit a blockage to ensure the allocation/probing insns are
25633 not optimized, combined, removed, etc. Add REG_STACK_CHECK
25634 note for similar reasons. */
25635 if (flag_stack_clash_protection)
25637 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
25638 emit_insn (gen_blockage ());
25644 static HOST_WIDE_INT
25645 get_stack_clash_protection_probe_interval (void)
25647 return (HOST_WIDE_INT_1U
25648 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
25651 static HOST_WIDE_INT
25652 get_stack_clash_protection_guard_size (void)
25654 return (HOST_WIDE_INT_1U
25655 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
25658 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25659 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25661 COPY_REG, if non-null, should contain a copy of the original
25662 stack pointer at exit from this function.
25664 This is subtly different than the Ada probing in that it tries hard to
25665 prevent attacks that jump the stack guard. Thus it is never allowed to
25666 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25667 space without a suitable probe. */
25669 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
25672 rtx orig_sp = copy_reg;
25674 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25676 /* Round the size down to a multiple of PROBE_INTERVAL. */
25677 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
25679 /* If explicitly requested,
25680 or the rounded size is not the same as the original size
25681 or the the rounded size is greater than a page,
25682 then we will need a copy of the original stack pointer. */
25683 if (rounded_size != orig_size
25684 || rounded_size > probe_interval
25687 /* If the caller did not request a copy of the incoming stack
25688 pointer, then we use r0 to hold the copy. */
25690 orig_sp = gen_rtx_REG (Pmode, 0);
25691 emit_move_insn (orig_sp, stack_pointer_rtx);
25694 /* There's three cases here.
25696 One is a single probe which is the most common and most efficiently
25697 implemented as it does not have to have a copy of the original
25698 stack pointer if there are no residuals.
25700 Second is unrolled allocation/probes which we use if there's just
25701 a few of them. It needs to save the original stack pointer into a
25702 temporary for use as a source register in the allocation/probe.
25704 Last is a loop. This is the most uncommon case and least efficient. */
25705 rtx_insn *retval = NULL;
25706 if (rounded_size == probe_interval)
25708 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
25710 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25712 else if (rounded_size <= 8 * probe_interval)
25714 /* The ABI requires using the store with update insns to allocate
25715 space and store the backchain into the stack
25717 So we save the current stack pointer into a temporary, then
25718 emit the store-with-update insns to store the saved stack pointer
25719 into the right location in each new page. */
25720 for (int i = 0; i < rounded_size; i += probe_interval)
25723 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
25725 /* Save the first stack adjustment in RETVAL. */
25730 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25734 /* Compute the ending address. */
25736 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
25737 rtx rs = GEN_INT (-rounded_size);
25739 if (add_operand (rs, Pmode))
25740 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
25743 emit_move_insn (end_addr, GEN_INT (-rounded_size));
25744 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
25745 stack_pointer_rtx));
25746 /* Describe the effect of INSN to the CFI engine. */
25747 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25748 gen_rtx_SET (end_addr,
25749 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25752 RTX_FRAME_RELATED_P (insn) = 1;
25754 /* Emit the loop. */
25756 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
25757 stack_pointer_rtx, orig_sp,
25760 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
25761 stack_pointer_rtx, orig_sp,
25763 RTX_FRAME_RELATED_P (retval) = 1;
25764 /* Describe the effect of INSN to the CFI engine. */
25765 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
25766 gen_rtx_SET (stack_pointer_rtx, end_addr));
25768 /* Emit a blockage to ensure the allocation/probing insns are
25769 not optimized, combined, removed, etc. Other cases handle this
25770 within their call to rs6000_emit_allocate_stack_1. */
25771 emit_insn (gen_blockage ());
25773 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
25776 if (orig_size != rounded_size)
25778 /* Allocate (and implicitly probe) any residual space. */
25779 HOST_WIDE_INT residual = orig_size - rounded_size;
25781 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
25783 /* If the residual was the only allocation, then we can return the
25784 allocating insn. */
25792 /* Emit the correct code for allocating stack space, as insns.
25793 If COPY_REG, make sure a copy of the old frame is left there.
25794 The generated code may use hard register 0 as a temporary. */
25797 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
25800 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25801 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25802 rtx todec = gen_int_mode (-size, Pmode);
25804 if (INTVAL (todec) != -size)
25806 warning (0, "stack frame too large");
25807 emit_insn (gen_trap ());
25811 if (crtl->limit_stack)
25813 if (REG_P (stack_limit_rtx)
25814 && REGNO (stack_limit_rtx) > 1
25815 && REGNO (stack_limit_rtx) <= 31)
25818 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25821 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25823 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
25825 && DEFAULT_ABI == ABI_V4
25828 rtx toload = gen_rtx_CONST (VOIDmode,
25829 gen_rtx_PLUS (Pmode,
25833 emit_insn (gen_elf_high (tmp_reg, toload));
25834 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25835 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25839 warning (0, "stack limit expression is not supported");
25842 if (flag_stack_clash_protection)
25844 if (size < get_stack_clash_protection_guard_size ())
25845 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25848 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25851 /* If we asked for a copy with an offset, then we still need add in
25853 if (copy_reg && copy_off)
25854 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25862 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25864 emit_move_insn (copy_reg, stack_reg);
25867 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25868 it now and set the alias set/attributes. The above gen_*_update
25869 calls will generate a PARALLEL with the MEM set being the first
25871 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25875 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25877 #if PROBE_INTERVAL > 32768
25878 #error Cannot use indexed addressing mode for stack probing
25881 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25882 inclusive. These are offsets from the current stack pointer. */
25885 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25887 /* See if we have a constant small number of probes to generate. If so,
25888 that's the easy case. */
25889 if (first + size <= 32768)
25893 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25894 it exceeds SIZE. If only one probe is needed, this will not
25895 generate any code. Then probe at FIRST + SIZE. */
25896 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25897 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25900 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25904 /* Otherwise, do the same as above, but in a loop. Note that we must be
25905 extra careful with variables wrapping around because we might be at
25906 the very top (or the very bottom) of the address space and we have
25907 to be able to handle this case properly; in particular, we use an
25908 equality test for the loop condition. */
25911 HOST_WIDE_INT rounded_size;
25912 rtx r12 = gen_rtx_REG (Pmode, 12);
25913 rtx r0 = gen_rtx_REG (Pmode, 0);
25915 /* Sanity check for the addressing mode we're going to use. */
25916 gcc_assert (first <= 32768);
25918 /* Step 1: round SIZE to the previous multiple of the interval. */
25920 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25923 /* Step 2: compute initial and final value of the loop counter. */
25925 /* TEST_ADDR = SP + FIRST. */
25926 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25929 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25930 if (rounded_size > 32768)
25932 emit_move_insn (r0, GEN_INT (-rounded_size));
25933 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25936 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25940 /* Step 3: the loop
25944 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25947 while (TEST_ADDR != LAST_ADDR)
25949 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25950 until it is equal to ROUNDED_SIZE. */
25953 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25955 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25958 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25959 that SIZE is equal to ROUNDED_SIZE. */
25961 if (size != rounded_size)
25962 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25966 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25967 addresses, not offsets. */
25969 static const char *
25970 output_probe_stack_range_1 (rtx reg1, rtx reg2)
25972 static int labelno = 0;
25976 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25979 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25981 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25983 xops[1] = GEN_INT (-PROBE_INTERVAL);
25984 output_asm_insn ("addi %0,%0,%1", xops);
25986 /* Probe at TEST_ADDR. */
25987 xops[1] = gen_rtx_REG (Pmode, 0);
25988 output_asm_insn ("stw %1,0(%0)", xops);
25990 /* Test if TEST_ADDR == LAST_ADDR. */
25993 output_asm_insn ("cmpd 0,%0,%1", xops);
25995 output_asm_insn ("cmpw 0,%0,%1", xops);
25998 fputs ("\tbne 0,", asm_out_file);
25999 assemble_name_raw (asm_out_file, loop_lab);
26000 fputc ('\n', asm_out_file);
26005 /* This function is called when rs6000_frame_related is processing
26006 SETs within a PARALLEL, and returns whether the REGNO save ought to
26007 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
26008 for out-of-line register save functions, store multiple, and the
26009 Darwin world_save. They may contain registers that don't really
26013 interesting_frame_related_regno (unsigned int regno)
26015 /* Saves apparently of r0 are actually saving LR. It doesn't make
26016 sense to substitute the regno here to test save_reg_p (LR_REGNO).
26017 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
26018 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
26019 as frame related. */
26022 /* If we see CR2 then we are here on a Darwin world save. Saves of
26023 CR2 signify the whole CR is being saved. This is a long-standing
26024 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
26025 that CR needs to be saved. */
26026 if (regno == CR2_REGNO)
26028 /* Omit frame info for any user-defined global regs. If frame info
26029 is supplied for them, frame unwinding will restore a user reg.
26030 Also omit frame info for any reg we don't need to save, as that
26031 bloats frame info and can cause problems with shrink wrapping.
26032 Since global regs won't be seen as needing to be saved, both of
26033 these conditions are covered by save_reg_p. */
26034 return save_reg_p (regno);
26037 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
26038 addresses, not offsets.
26040 REG2 contains the backchain that must be stored into *sp at each allocation.
26042 This is subtly different than the Ada probing above in that it tries hard
26043 to prevent attacks that jump the stack guard. Thus, it is never allowed
26044 to allocate more than PROBE_INTERVAL bytes of stack space without a
26047 static const char *
26048 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
26050 static int labelno = 0;
26054 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
26056 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
26058 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
26060 /* This allocates and probes. */
26063 xops[2] = GEN_INT (-probe_interval);
26065 output_asm_insn ("stdu %1,%2(%0)", xops);
26067 output_asm_insn ("stwu %1,%2(%0)", xops);
26069 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
26073 output_asm_insn ("cmpd 0,%0,%1", xops);
26075 output_asm_insn ("cmpw 0,%0,%1", xops);
26077 fputs ("\tbne 0,", asm_out_file);
26078 assemble_name_raw (asm_out_file, loop_lab);
26079 fputc ('\n', asm_out_file);
26084 /* Wrapper around the output_probe_stack_range routines. */
26086 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
26088 if (flag_stack_clash_protection)
26089 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
26091 return output_probe_stack_range_1 (reg1, reg3);
26094 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
26095 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
26096 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
26097 deduce these equivalences by itself so it wasn't necessary to hold
26098 its hand so much. Don't be tempted to always supply d2_f_d_e with
26099 the actual cfa register, ie. r31 when we are using a hard frame
26100 pointer. That fails when saving regs off r1, and sched moves the
26101 r31 setup past the reg saves. */
26104 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
26105 rtx reg2, rtx repl2)
26109 if (REGNO (reg) == STACK_POINTER_REGNUM)
26111 gcc_checking_assert (val == 0);
26115 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
26118 rtx pat = PATTERN (insn);
26119 if (!repl && !reg2)
26121 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
26122 if (GET_CODE (pat) == PARALLEL)
26123 for (int i = 0; i < XVECLEN (pat, 0); i++)
26124 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
26126 rtx set = XVECEXP (pat, 0, i);
26128 if (!REG_P (SET_SRC (set))
26129 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
26130 RTX_FRAME_RELATED_P (set) = 1;
26132 RTX_FRAME_RELATED_P (insn) = 1;
26136 /* We expect that 'pat' is either a SET or a PARALLEL containing
26137 SETs (and possibly other stuff). In a PARALLEL, all the SETs
26138 are important so they all have to be marked RTX_FRAME_RELATED_P.
26139 Call simplify_replace_rtx on the SETs rather than the whole insn
26140 so as to leave the other stuff alone (for example USE of r12). */
26142 set_used_flags (pat);
26143 if (GET_CODE (pat) == SET)
26146 pat = simplify_replace_rtx (pat, reg, repl);
26148 pat = simplify_replace_rtx (pat, reg2, repl2);
26150 else if (GET_CODE (pat) == PARALLEL)
26152 pat = shallow_copy_rtx (pat);
26153 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
26155 for (int i = 0; i < XVECLEN (pat, 0); i++)
26156 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
26158 rtx set = XVECEXP (pat, 0, i);
26161 set = simplify_replace_rtx (set, reg, repl);
26163 set = simplify_replace_rtx (set, reg2, repl2);
26164 XVECEXP (pat, 0, i) = set;
26166 if (!REG_P (SET_SRC (set))
26167 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
26168 RTX_FRAME_RELATED_P (set) = 1;
26172 gcc_unreachable ();
26174 RTX_FRAME_RELATED_P (insn) = 1;
26175 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
26180 /* Returns an insn that has a vrsave set operation with the
26181 appropriate CLOBBERs. */
26184 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
26187 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
26188 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26191 = gen_rtx_SET (vrsave,
26192 gen_rtx_UNSPEC_VOLATILE (SImode,
26193 gen_rtvec (2, reg, vrsave),
26194 UNSPECV_SET_VRSAVE));
26198 /* We need to clobber the registers in the mask so the scheduler
26199 does not move sets to VRSAVE before sets of AltiVec registers.
26201 However, if the function receives nonlocal gotos, reload will set
26202 all call saved registers live. We will end up with:
26204 (set (reg 999) (mem))
26205 (parallel [ (set (reg vrsave) (unspec blah))
26206 (clobber (reg 999))])
26208 The clobber will cause the store into reg 999 to be dead, and
26209 flow will attempt to delete an epilogue insn. In this case, we
26210 need an unspec use/set of the register. */
26212 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
26213 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
26215 if (!epiloguep || call_used_regs [i])
26216 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
26217 gen_rtx_REG (V4SImode, i));
26220 rtx reg = gen_rtx_REG (V4SImode, i);
26223 = gen_rtx_SET (reg,
26224 gen_rtx_UNSPEC (V4SImode,
26225 gen_rtvec (1, reg), 27));
26229 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
26231 for (i = 0; i < nclobs; ++i)
26232 XVECEXP (insn, 0, i) = clobs[i];
26238 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
26242 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
26243 mem = gen_frame_mem (GET_MODE (reg), addr);
26244 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
26248 gen_frame_load (rtx reg, rtx frame_reg, int offset)
26250 return gen_frame_set (reg, frame_reg, offset, false);
26254 gen_frame_store (rtx reg, rtx frame_reg, int offset)
26256 return gen_frame_set (reg, frame_reg, offset, true);
26259 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
26260 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
26263 emit_frame_save (rtx frame_reg, machine_mode mode,
26264 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
26268 /* Some cases that need register indexed addressing. */
26269 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
26270 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
26272 reg = gen_rtx_REG (mode, regno);
26273 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
26274 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
26275 NULL_RTX, NULL_RTX);
26278 /* Emit an offset memory reference suitable for a frame store, while
26279 converting to a valid addressing mode. */
26282 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
26284 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
26287 #ifndef TARGET_FIX_AND_CONTINUE
26288 #define TARGET_FIX_AND_CONTINUE 0
26291 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
26292 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
26293 #define LAST_SAVRES_REGISTER 31
26294 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
26305 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
26307 /* Temporary holding space for an out-of-line register save/restore
26309 static char savres_routine_name[30];
26311 /* Return the name for an out-of-line register save/restore routine.
26312 We are saving/restoring GPRs if GPR is true. */
26315 rs6000_savres_routine_name (int regno, int sel)
26317 const char *prefix = "";
26318 const char *suffix = "";
26320 /* Different targets are supposed to define
26321 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
26322 routine name could be defined with:
26324 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
26326 This is a nice idea in practice, but in reality, things are
26327 complicated in several ways:
26329 - ELF targets have save/restore routines for GPRs.
26331 - PPC64 ELF targets have routines for save/restore of GPRs that
26332 differ in what they do with the link register, so having a set
26333 prefix doesn't work. (We only use one of the save routines at
26334 the moment, though.)
26336 - PPC32 elf targets have "exit" versions of the restore routines
26337 that restore the link register and can save some extra space.
26338 These require an extra suffix. (There are also "tail" versions
26339 of the restore routines and "GOT" versions of the save routines,
26340 but we don't generate those at present. Same problems apply,
26343 We deal with all this by synthesizing our own prefix/suffix and
26344 using that for the simple sprintf call shown above. */
26345 if (DEFAULT_ABI == ABI_V4)
26350 if ((sel & SAVRES_REG) == SAVRES_GPR)
26351 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
26352 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26353 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
26354 else if ((sel & SAVRES_REG) == SAVRES_VR)
26355 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
26359 if ((sel & SAVRES_LR))
26362 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26364 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
26365 /* No out-of-line save/restore routines for GPRs on AIX. */
26366 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
26370 if ((sel & SAVRES_REG) == SAVRES_GPR)
26371 prefix = ((sel & SAVRES_SAVE)
26372 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
26373 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
26374 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26376 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
26377 if ((sel & SAVRES_LR))
26378 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
26382 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
26383 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
26386 else if ((sel & SAVRES_REG) == SAVRES_VR)
26387 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
26392 if (DEFAULT_ABI == ABI_DARWIN)
26394 /* The Darwin approach is (slightly) different, in order to be
26395 compatible with code generated by the system toolchain. There is a
26396 single symbol for the start of save sequence, and the code here
26397 embeds an offset into that code on the basis of the first register
26399 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
26400 if ((sel & SAVRES_REG) == SAVRES_GPR)
26401 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
26402 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
26403 (regno - 13) * 4, prefix, regno);
26404 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26405 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
26406 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
26407 else if ((sel & SAVRES_REG) == SAVRES_VR)
26408 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
26409 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
26414 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
26416 return savres_routine_name;
26419 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
26420 We are saving/restoring GPRs if GPR is true. */
26423 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
26425 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
26426 ? info->first_gp_reg_save
26427 : (sel & SAVRES_REG) == SAVRES_FPR
26428 ? info->first_fp_reg_save - 32
26429 : (sel & SAVRES_REG) == SAVRES_VR
26430 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
26435 /* Don't generate bogus routine names. */
26436 gcc_assert (FIRST_SAVRES_REGISTER <= regno
26437 && regno <= LAST_SAVRES_REGISTER
26438 && select >= 0 && select <= 12);
26440 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
26446 name = rs6000_savres_routine_name (regno, sel);
26448 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
26449 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
26450 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
26456 /* Emit a sequence of insns, including a stack tie if needed, for
26457 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
26458 reset the stack pointer, but move the base of the frame into
26459 reg UPDT_REGNO for use by out-of-line register restore routines. */
26462 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
26463 unsigned updt_regno)
26465 /* If there is nothing to do, don't do anything. */
26466 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
26469 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
26471 /* This blockage is needed so that sched doesn't decide to move
26472 the sp change before the register restores. */
26473 if (DEFAULT_ABI == ABI_V4)
26474 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
26475 GEN_INT (frame_off)));
26477 /* If we are restoring registers out-of-line, we will be using the
26478 "exit" variants of the restore routines, which will reset the
26479 stack for us. But we do need to point updt_reg into the
26480 right place for those routines. */
26481 if (frame_off != 0)
26482 return emit_insn (gen_add3_insn (updt_reg_rtx,
26483 frame_reg_rtx, GEN_INT (frame_off)));
26485 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
26490 /* Return the register number used as a pointer by out-of-line
26491 save/restore functions. */
26493 static inline unsigned
26494 ptr_regno_for_savres (int sel)
26496 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26497 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
26498 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
26501 /* Construct a parallel rtx describing the effect of a call to an
26502 out-of-line register save/restore routine, and emit the insn
26503 or jump_insn as appropriate. */
26506 rs6000_emit_savres_rtx (rs6000_stack_t *info,
26507 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
26508 machine_mode reg_mode, int sel)
26511 int offset, start_reg, end_reg, n_regs, use_reg;
26512 int reg_size = GET_MODE_SIZE (reg_mode);
26519 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26520 ? info->first_gp_reg_save
26521 : (sel & SAVRES_REG) == SAVRES_FPR
26522 ? info->first_fp_reg_save
26523 : (sel & SAVRES_REG) == SAVRES_VR
26524 ? info->first_altivec_reg_save
26526 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26528 : (sel & SAVRES_REG) == SAVRES_FPR
26530 : (sel & SAVRES_REG) == SAVRES_VR
26531 ? LAST_ALTIVEC_REGNO + 1
26533 n_regs = end_reg - start_reg;
26534 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
26535 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
26538 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26539 RTVEC_ELT (p, offset++) = ret_rtx;
26541 RTVEC_ELT (p, offset++)
26542 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
26544 sym = rs6000_savres_routine_sym (info, sel);
26545 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
26547 use_reg = ptr_regno_for_savres (sel);
26548 if ((sel & SAVRES_REG) == SAVRES_VR)
26550 /* Vector regs are saved/restored using [reg+reg] addressing. */
26551 RTVEC_ELT (p, offset++)
26552 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26553 RTVEC_ELT (p, offset++)
26554 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
26557 RTVEC_ELT (p, offset++)
26558 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26560 for (i = 0; i < end_reg - start_reg; i++)
26561 RTVEC_ELT (p, i + offset)
26562 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
26563 frame_reg_rtx, save_area_offset + reg_size * i,
26564 (sel & SAVRES_SAVE) != 0);
26566 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26567 RTVEC_ELT (p, i + offset)
26568 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
26570 par = gen_rtx_PARALLEL (VOIDmode, p);
26572 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26574 insn = emit_jump_insn (par);
26575 JUMP_LABEL (insn) = ret_rtx;
26578 insn = emit_insn (par);
26582 /* Emit prologue code to store CR fields that need to be saved into REG. This
26583 function should only be called when moving the non-volatile CRs to REG, it
26584 is not a general purpose routine to move the entire set of CRs to REG.
26585 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
26589 rs6000_emit_prologue_move_from_cr (rtx reg)
26591 /* Only the ELFv2 ABI allows storing only selected fields. */
26592 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
26594 int i, cr_reg[8], count = 0;
26596 /* Collect CR fields that must be saved. */
26597 for (i = 0; i < 8; i++)
26598 if (save_reg_p (CR0_REGNO + i))
26599 cr_reg[count++] = i;
26601 /* If it's just a single one, use mfcrf. */
26604 rtvec p = rtvec_alloc (1);
26605 rtvec r = rtvec_alloc (2);
26606 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
26607 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
26609 = gen_rtx_SET (reg,
26610 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
26612 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26616 /* ??? It might be better to handle count == 2 / 3 cases here
26617 as well, using logical operations to combine the values. */
26620 emit_insn (gen_prologue_movesi_from_cr (reg));
26623 /* Return whether the split-stack arg pointer (r12) is used. */
26626 split_stack_arg_pointer_used_p (void)
26628 /* If the pseudo holding the arg pointer is no longer a pseudo,
26629 then the arg pointer is used. */
26630 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
26631 && (!REG_P (cfun->machine->split_stack_arg_pointer)
26632 || (REGNO (cfun->machine->split_stack_arg_pointer)
26633 < FIRST_PSEUDO_REGISTER)))
26636 /* Unfortunately we also need to do some code scanning, since
26637 r12 may have been substituted for the pseudo. */
26639 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
26640 FOR_BB_INSNS (bb, insn)
26641 if (NONDEBUG_INSN_P (insn))
26643 /* A call destroys r12. */
26648 FOR_EACH_INSN_USE (use, insn)
26650 rtx x = DF_REF_REG (use);
26651 if (REG_P (x) && REGNO (x) == 12)
26655 FOR_EACH_INSN_DEF (def, insn)
26657 rtx x = DF_REF_REG (def);
26658 if (REG_P (x) && REGNO (x) == 12)
26662 return bitmap_bit_p (DF_LR_OUT (bb), 12);
26665 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26668 rs6000_global_entry_point_needed_p (void)
26670 /* Only needed for the ELFv2 ABI. */
26671 if (DEFAULT_ABI != ABI_ELFv2)
26674 /* With -msingle-pic-base, we assume the whole program shares the same
26675 TOC, so no global entry point prologues are needed anywhere. */
26676 if (TARGET_SINGLE_PIC_BASE)
26679 /* Ensure we have a global entry point for thunks. ??? We could
26680 avoid that if the target routine doesn't need a global entry point,
26681 but we do not know whether this is the case at this point. */
26682 if (cfun->is_thunk)
26685 /* For regular functions, rs6000_emit_prologue sets this flag if the
26686 routine ever uses the TOC pointer. */
26687 return cfun->machine->r2_setup_needed;
26690 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26692 rs6000_get_separate_components (void)
26694 rs6000_stack_t *info = rs6000_stack_info ();
26696 if (WORLD_SAVE_P (info))
26699 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
26700 && !(info->savres_strategy & REST_MULTIPLE));
26702 /* Component 0 is the save/restore of LR (done via GPR0).
26703 Component 2 is the save of the TOC (GPR2).
26704 Components 13..31 are the save/restore of GPR13..GPR31.
26705 Components 46..63 are the save/restore of FPR14..FPR31. */
26707 cfun->machine->n_components = 64;
26709 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26710 bitmap_clear (components);
26712 int reg_size = TARGET_32BIT ? 4 : 8;
26713 int fp_reg_size = 8;
26715 /* The GPRs we need saved to the frame. */
26716 if ((info->savres_strategy & SAVE_INLINE_GPRS)
26717 && (info->savres_strategy & REST_INLINE_GPRS))
26719 int offset = info->gp_save_offset;
26721 offset += info->total_size;
26723 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26725 if (IN_RANGE (offset, -0x8000, 0x7fff)
26726 && save_reg_p (regno))
26727 bitmap_set_bit (components, regno);
26729 offset += reg_size;
26733 /* Don't mess with the hard frame pointer. */
26734 if (frame_pointer_needed)
26735 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
26737 /* Don't mess with the fixed TOC register. */
26738 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
26739 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
26740 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
26741 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
26743 /* The FPRs we need saved to the frame. */
26744 if ((info->savres_strategy & SAVE_INLINE_FPRS)
26745 && (info->savres_strategy & REST_INLINE_FPRS))
26747 int offset = info->fp_save_offset;
26749 offset += info->total_size;
26751 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26753 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
26754 bitmap_set_bit (components, regno);
26756 offset += fp_reg_size;
26760 /* Optimize LR save and restore if we can. This is component 0. Any
26761 out-of-line register save/restore routines need LR. */
26762 if (info->lr_save_p
26763 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
26764 && (info->savres_strategy & SAVE_INLINE_GPRS)
26765 && (info->savres_strategy & REST_INLINE_GPRS)
26766 && (info->savres_strategy & SAVE_INLINE_FPRS)
26767 && (info->savres_strategy & REST_INLINE_FPRS)
26768 && (info->savres_strategy & SAVE_INLINE_VRS)
26769 && (info->savres_strategy & REST_INLINE_VRS))
26771 int offset = info->lr_save_offset;
26773 offset += info->total_size;
26774 if (IN_RANGE (offset, -0x8000, 0x7fff))
26775 bitmap_set_bit (components, 0);
26778 /* Optimize saving the TOC. This is component 2. */
26779 if (cfun->machine->save_toc_in_prologue)
26780 bitmap_set_bit (components, 2);
26785 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26787 rs6000_components_for_bb (basic_block bb)
26789 rs6000_stack_t *info = rs6000_stack_info ();
26791 bitmap in = DF_LIVE_IN (bb);
26792 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
26793 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
26795 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26796 bitmap_clear (components);
26798 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26801 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26802 if (bitmap_bit_p (in, regno)
26803 || bitmap_bit_p (gen, regno)
26804 || bitmap_bit_p (kill, regno))
26805 bitmap_set_bit (components, regno);
26808 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26809 if (bitmap_bit_p (in, regno)
26810 || bitmap_bit_p (gen, regno)
26811 || bitmap_bit_p (kill, regno))
26812 bitmap_set_bit (components, regno);
26814 /* The link register. */
26815 if (bitmap_bit_p (in, LR_REGNO)
26816 || bitmap_bit_p (gen, LR_REGNO)
26817 || bitmap_bit_p (kill, LR_REGNO))
26818 bitmap_set_bit (components, 0);
26820 /* The TOC save. */
26821 if (bitmap_bit_p (in, TOC_REGNUM)
26822 || bitmap_bit_p (gen, TOC_REGNUM)
26823 || bitmap_bit_p (kill, TOC_REGNUM))
26824 bitmap_set_bit (components, 2);
26829 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26831 rs6000_disqualify_components (sbitmap components, edge e,
26832 sbitmap edge_components, bool /*is_prologue*/)
26834 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26835 live where we want to place that code. */
26836 if (bitmap_bit_p (edge_components, 0)
26837 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26840 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26841 "on entry to bb %d\n", e->dest->index);
26842 bitmap_clear_bit (components, 0);
26846 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26848 rs6000_emit_prologue_components (sbitmap components)
26850 rs6000_stack_t *info = rs6000_stack_info ();
26851 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26852 ? HARD_FRAME_POINTER_REGNUM
26853 : STACK_POINTER_REGNUM);
26855 machine_mode reg_mode = Pmode;
26856 int reg_size = TARGET_32BIT ? 4 : 8;
26857 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
26859 int fp_reg_size = 8;
26861 /* Prologue for LR. */
26862 if (bitmap_bit_p (components, 0))
26864 rtx reg = gen_rtx_REG (reg_mode, 0);
26865 rtx_insn *insn = emit_move_insn (reg, gen_rtx_REG (reg_mode, LR_REGNO));
26866 RTX_FRAME_RELATED_P (insn) = 1;
26867 add_reg_note (insn, REG_CFA_REGISTER, NULL);
26869 int offset = info->lr_save_offset;
26871 offset += info->total_size;
26873 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26874 RTX_FRAME_RELATED_P (insn) = 1;
26875 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26876 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26877 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26880 /* Prologue for TOC. */
26881 if (bitmap_bit_p (components, 2))
26883 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26884 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26885 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26888 /* Prologue for the GPRs. */
26889 int offset = info->gp_save_offset;
26891 offset += info->total_size;
26893 for (int i = info->first_gp_reg_save; i < 32; i++)
26895 if (bitmap_bit_p (components, i))
26897 rtx reg = gen_rtx_REG (reg_mode, i);
26898 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26899 RTX_FRAME_RELATED_P (insn) = 1;
26900 rtx set = copy_rtx (single_set (insn));
26901 add_reg_note (insn, REG_CFA_OFFSET, set);
26904 offset += reg_size;
26907 /* Prologue for the FPRs. */
26908 offset = info->fp_save_offset;
26910 offset += info->total_size;
26912 for (int i = info->first_fp_reg_save; i < 64; i++)
26914 if (bitmap_bit_p (components, i))
26916 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26917 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26918 RTX_FRAME_RELATED_P (insn) = 1;
26919 rtx set = copy_rtx (single_set (insn));
26920 add_reg_note (insn, REG_CFA_OFFSET, set);
26923 offset += fp_reg_size;
26927 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26929 rs6000_emit_epilogue_components (sbitmap components)
26931 rs6000_stack_t *info = rs6000_stack_info ();
26932 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26933 ? HARD_FRAME_POINTER_REGNUM
26934 : STACK_POINTER_REGNUM);
26936 machine_mode reg_mode = Pmode;
26937 int reg_size = TARGET_32BIT ? 4 : 8;
26939 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
26941 int fp_reg_size = 8;
26943 /* Epilogue for the FPRs. */
26944 int offset = info->fp_save_offset;
26946 offset += info->total_size;
26948 for (int i = info->first_fp_reg_save; i < 64; i++)
26950 if (bitmap_bit_p (components, i))
26952 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26953 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26954 RTX_FRAME_RELATED_P (insn) = 1;
26955 add_reg_note (insn, REG_CFA_RESTORE, reg);
26958 offset += fp_reg_size;
26961 /* Epilogue for the GPRs. */
26962 offset = info->gp_save_offset;
26964 offset += info->total_size;
26966 for (int i = info->first_gp_reg_save; i < 32; i++)
26968 if (bitmap_bit_p (components, i))
26970 rtx reg = gen_rtx_REG (reg_mode, i);
26971 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26972 RTX_FRAME_RELATED_P (insn) = 1;
26973 add_reg_note (insn, REG_CFA_RESTORE, reg);
26976 offset += reg_size;
26979 /* Epilogue for LR. */
26980 if (bitmap_bit_p (components, 0))
26982 int offset = info->lr_save_offset;
26984 offset += info->total_size;
26986 rtx reg = gen_rtx_REG (reg_mode, 0);
26987 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26989 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
26990 insn = emit_move_insn (lr, reg);
26991 RTX_FRAME_RELATED_P (insn) = 1;
26992 add_reg_note (insn, REG_CFA_RESTORE, lr);
26996 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26998 rs6000_set_handled_components (sbitmap components)
27000 rs6000_stack_t *info = rs6000_stack_info ();
27002 for (int i = info->first_gp_reg_save; i < 32; i++)
27003 if (bitmap_bit_p (components, i))
27004 cfun->machine->gpr_is_wrapped_separately[i] = true;
27006 for (int i = info->first_fp_reg_save; i < 64; i++)
27007 if (bitmap_bit_p (components, i))
27008 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
27010 if (bitmap_bit_p (components, 0))
27011 cfun->machine->lr_is_wrapped_separately = true;
27013 if (bitmap_bit_p (components, 2))
27014 cfun->machine->toc_is_wrapped_separately = true;
27017 /* VRSAVE is a bit vector representing which AltiVec registers
27018 are used. The OS uses this to determine which vector
27019 registers to save on a context switch. We need to save
27020 VRSAVE on the stack frame, add whatever AltiVec registers we
27021 used in this function, and do the corresponding magic in the
27024 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
27025 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
27027 /* Get VRSAVE into a GPR. */
27028 rtx reg = gen_rtx_REG (SImode, save_regno);
27029 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
27031 emit_insn (gen_get_vrsave_internal (reg));
27033 emit_insn (gen_rtx_SET (reg, vrsave));
27036 int offset = info->vrsave_save_offset + frame_off;
27037 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
27039 /* Include the registers in the mask. */
27040 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
27042 emit_insn (generate_set_vrsave (reg, info, 0));
27045 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
27046 called, it left the arg pointer to the old stack in r29. Otherwise, the
27047 arg pointer is the top of the current frame. */
27049 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
27050 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
27052 cfun->machine->split_stack_argp_used = true;
27056 rtx r12 = gen_rtx_REG (Pmode, 12);
27057 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
27058 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
27059 emit_insn_before (set_r12, sp_adjust);
27061 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
27063 rtx r12 = gen_rtx_REG (Pmode, 12);
27064 if (frame_off == 0)
27065 emit_move_insn (r12, frame_reg_rtx);
27067 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
27072 rtx r12 = gen_rtx_REG (Pmode, 12);
27073 rtx r29 = gen_rtx_REG (Pmode, 29);
27074 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
27075 rtx not_more = gen_label_rtx ();
27078 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27079 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
27080 gen_rtx_LABEL_REF (VOIDmode, not_more),
27082 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27083 JUMP_LABEL (jump) = not_more;
27084 LABEL_NUSES (not_more) += 1;
27085 emit_move_insn (r12, r29);
27086 emit_label (not_more);
27090 /* Emit function prologue as insns. */
27093 rs6000_emit_prologue (void)
27095 rs6000_stack_t *info = rs6000_stack_info ();
27096 machine_mode reg_mode = Pmode;
27097 int reg_size = TARGET_32BIT ? 4 : 8;
27098 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
27100 int fp_reg_size = 8;
27101 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
27102 rtx frame_reg_rtx = sp_reg_rtx;
27103 unsigned int cr_save_regno;
27104 rtx cr_save_rtx = NULL_RTX;
27107 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
27108 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
27109 && call_used_regs[STATIC_CHAIN_REGNUM]);
27110 int using_split_stack = (flag_split_stack
27111 && (lookup_attribute ("no_split_stack",
27112 DECL_ATTRIBUTES (cfun->decl))
27115 /* Offset to top of frame for frame_reg and sp respectively. */
27116 HOST_WIDE_INT frame_off = 0;
27117 HOST_WIDE_INT sp_off = 0;
27118 /* sp_adjust is the stack adjusting instruction, tracked so that the
27119 insn setting up the split-stack arg pointer can be emitted just
27120 prior to it, when r12 is not used here for other purposes. */
27121 rtx_insn *sp_adjust = 0;
27124 /* Track and check usage of r0, r11, r12. */
27125 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
27126 #define START_USE(R) do \
27128 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27129 reg_inuse |= 1 << (R); \
27131 #define END_USE(R) do \
27133 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
27134 reg_inuse &= ~(1 << (R)); \
27136 #define NOT_INUSE(R) do \
27138 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27141 #define START_USE(R) do {} while (0)
27142 #define END_USE(R) do {} while (0)
27143 #define NOT_INUSE(R) do {} while (0)
27146 if (DEFAULT_ABI == ABI_ELFv2
27147 && !TARGET_SINGLE_PIC_BASE)
27149 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
27151 /* With -mminimal-toc we may generate an extra use of r2 below. */
27152 if (TARGET_TOC && TARGET_MINIMAL_TOC
27153 && !constant_pool_empty_p ())
27154 cfun->machine->r2_setup_needed = true;
27158 if (flag_stack_usage_info)
27159 current_function_static_stack_size = info->total_size;
27161 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
27163 HOST_WIDE_INT size = info->total_size;
27165 if (crtl->is_leaf && !cfun->calls_alloca)
27167 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
27168 rs6000_emit_probe_stack_range (get_stack_check_protect (),
27169 size - get_stack_check_protect ());
27172 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
27175 if (TARGET_FIX_AND_CONTINUE)
27177 /* gdb on darwin arranges to forward a function from the old
27178 address by modifying the first 5 instructions of the function
27179 to branch to the overriding function. This is necessary to
27180 permit function pointers that point to the old function to
27181 actually forward to the new function. */
27182 emit_insn (gen_nop ());
27183 emit_insn (gen_nop ());
27184 emit_insn (gen_nop ());
27185 emit_insn (gen_nop ());
27186 emit_insn (gen_nop ());
27189 /* Handle world saves specially here. */
27190 if (WORLD_SAVE_P (info))
27197 /* save_world expects lr in r0. */
27198 reg0 = gen_rtx_REG (Pmode, 0);
27199 if (info->lr_save_p)
27201 insn = emit_move_insn (reg0,
27202 gen_rtx_REG (Pmode, LR_REGNO));
27203 RTX_FRAME_RELATED_P (insn) = 1;
27206 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
27207 assumptions about the offsets of various bits of the stack
27209 gcc_assert (info->gp_save_offset == -220
27210 && info->fp_save_offset == -144
27211 && info->lr_save_offset == 8
27212 && info->cr_save_offset == 4
27215 && (!crtl->calls_eh_return
27216 || info->ehrd_offset == -432)
27217 && info->vrsave_save_offset == -224
27218 && info->altivec_save_offset == -416);
27220 treg = gen_rtx_REG (SImode, 11);
27221 emit_move_insn (treg, GEN_INT (-info->total_size));
27223 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
27224 in R11. It also clobbers R12, so beware! */
27226 /* Preserve CR2 for save_world prologues */
27228 sz += 32 - info->first_gp_reg_save;
27229 sz += 64 - info->first_fp_reg_save;
27230 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
27231 p = rtvec_alloc (sz);
27233 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
27234 gen_rtx_REG (SImode,
27236 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
27237 gen_rtx_SYMBOL_REF (Pmode,
27239 /* We do floats first so that the instruction pattern matches
27241 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
27243 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
27245 info->first_fp_reg_save + i),
27247 info->fp_save_offset + frame_off + 8 * i);
27248 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
27250 = gen_frame_store (gen_rtx_REG (V4SImode,
27251 info->first_altivec_reg_save + i),
27253 info->altivec_save_offset + frame_off + 16 * i);
27254 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27256 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
27258 info->gp_save_offset + frame_off + reg_size * i);
27260 /* CR register traditionally saved as CR2. */
27262 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
27263 frame_reg_rtx, info->cr_save_offset + frame_off);
27264 /* Explain about use of R0. */
27265 if (info->lr_save_p)
27267 = gen_frame_store (reg0,
27268 frame_reg_rtx, info->lr_save_offset + frame_off);
27269 /* Explain what happens to the stack pointer. */
27271 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
27272 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
27275 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27276 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27277 treg, GEN_INT (-info->total_size));
27278 sp_off = frame_off = info->total_size;
27281 strategy = info->savres_strategy;
27283 /* For V.4, update stack before we do any saving and set back pointer. */
27284 if (! WORLD_SAVE_P (info)
27286 && (DEFAULT_ABI == ABI_V4
27287 || crtl->calls_eh_return))
27289 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
27290 || !(strategy & SAVE_INLINE_GPRS)
27291 || !(strategy & SAVE_INLINE_VRS));
27292 int ptr_regno = -1;
27293 rtx ptr_reg = NULL_RTX;
27296 if (info->total_size < 32767)
27297 frame_off = info->total_size;
27300 else if (info->cr_save_p
27302 || info->first_fp_reg_save < 64
27303 || info->first_gp_reg_save < 32
27304 || info->altivec_size != 0
27305 || info->vrsave_size != 0
27306 || crtl->calls_eh_return)
27310 /* The prologue won't be saving any regs so there is no need
27311 to set up a frame register to access any frame save area.
27312 We also won't be using frame_off anywhere below, but set
27313 the correct value anyway to protect against future
27314 changes to this function. */
27315 frame_off = info->total_size;
27317 if (ptr_regno != -1)
27319 /* Set up the frame offset to that needed by the first
27320 out-of-line save function. */
27321 START_USE (ptr_regno);
27322 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27323 frame_reg_rtx = ptr_reg;
27324 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
27325 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
27326 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
27327 ptr_off = info->gp_save_offset + info->gp_size;
27328 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
27329 ptr_off = info->altivec_save_offset + info->altivec_size;
27330 frame_off = -ptr_off;
27332 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27334 if (REGNO (frame_reg_rtx) == 12)
27336 sp_off = info->total_size;
27337 if (frame_reg_rtx != sp_reg_rtx)
27338 rs6000_emit_stack_tie (frame_reg_rtx, false);
27341 /* If we use the link register, get it into r0. */
27342 if (!WORLD_SAVE_P (info) && info->lr_save_p
27343 && !cfun->machine->lr_is_wrapped_separately)
27345 rtx addr, reg, mem;
27347 reg = gen_rtx_REG (Pmode, 0);
27349 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
27350 RTX_FRAME_RELATED_P (insn) = 1;
27352 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
27353 | SAVE_NOINLINE_FPRS_SAVES_LR)))
27355 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27356 GEN_INT (info->lr_save_offset + frame_off));
27357 mem = gen_rtx_MEM (Pmode, addr);
27358 /* This should not be of rs6000_sr_alias_set, because of
27359 __builtin_return_address. */
27361 insn = emit_move_insn (mem, reg);
27362 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27363 NULL_RTX, NULL_RTX);
27368 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
27369 r12 will be needed by out-of-line gpr restore. */
27370 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27371 && !(strategy & (SAVE_INLINE_GPRS
27372 | SAVE_NOINLINE_GPRS_SAVES_LR))
27374 if (!WORLD_SAVE_P (info)
27376 && REGNO (frame_reg_rtx) != cr_save_regno
27377 && !(using_static_chain_p && cr_save_regno == 11)
27378 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
27380 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
27381 START_USE (cr_save_regno);
27382 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27385 /* Do any required saving of fpr's. If only one or two to save, do
27386 it ourselves. Otherwise, call function. */
27387 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
27389 int offset = info->fp_save_offset + frame_off;
27390 for (int i = info->first_fp_reg_save; i < 64; i++)
27393 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
27394 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
27395 sp_off - frame_off);
27397 offset += fp_reg_size;
27400 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
27402 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27403 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27404 unsigned ptr_regno = ptr_regno_for_savres (sel);
27405 rtx ptr_reg = frame_reg_rtx;
27407 if (REGNO (frame_reg_rtx) == ptr_regno)
27408 gcc_checking_assert (frame_off == 0);
27411 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27412 NOT_INUSE (ptr_regno);
27413 emit_insn (gen_add3_insn (ptr_reg,
27414 frame_reg_rtx, GEN_INT (frame_off)));
27416 insn = rs6000_emit_savres_rtx (info, ptr_reg,
27417 info->fp_save_offset,
27418 info->lr_save_offset,
27420 rs6000_frame_related (insn, ptr_reg, sp_off,
27421 NULL_RTX, NULL_RTX);
27426 /* Save GPRs. This is done as a PARALLEL if we are using
27427 the store-multiple instructions. */
27428 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
27430 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
27431 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
27432 unsigned ptr_regno = ptr_regno_for_savres (sel);
27433 rtx ptr_reg = frame_reg_rtx;
27434 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
27435 int end_save = info->gp_save_offset + info->gp_size;
27438 if (ptr_regno == 12)
27441 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27443 /* Need to adjust r11 (r12) if we saved any FPRs. */
27444 if (end_save + frame_off != 0)
27446 rtx offset = GEN_INT (end_save + frame_off);
27449 frame_off = -end_save;
27451 NOT_INUSE (ptr_regno);
27452 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27454 else if (!ptr_set_up)
27456 NOT_INUSE (ptr_regno);
27457 emit_move_insn (ptr_reg, frame_reg_rtx);
27459 ptr_off = -end_save;
27460 insn = rs6000_emit_savres_rtx (info, ptr_reg,
27461 info->gp_save_offset + ptr_off,
27462 info->lr_save_offset + ptr_off,
27464 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
27465 NULL_RTX, NULL_RTX);
27469 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
27473 p = rtvec_alloc (32 - info->first_gp_reg_save);
27474 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27476 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
27478 info->gp_save_offset + frame_off + reg_size * i);
27479 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27480 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27481 NULL_RTX, NULL_RTX);
27483 else if (!WORLD_SAVE_P (info))
27485 int offset = info->gp_save_offset + frame_off;
27486 for (int i = info->first_gp_reg_save; i < 32; i++)
27489 && !cfun->machine->gpr_is_wrapped_separately[i])
27490 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
27491 sp_off - frame_off);
27493 offset += reg_size;
27497 if (crtl->calls_eh_return)
27504 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27505 if (regno == INVALID_REGNUM)
27509 p = rtvec_alloc (i);
27513 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27514 if (regno == INVALID_REGNUM)
27518 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
27520 info->ehrd_offset + sp_off + reg_size * (int) i);
27521 RTVEC_ELT (p, i) = set;
27522 RTX_FRAME_RELATED_P (set) = 1;
27525 insn = emit_insn (gen_blockage ());
27526 RTX_FRAME_RELATED_P (insn) = 1;
27527 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
27530 /* In AIX ABI we need to make sure r2 is really saved. */
27531 if (TARGET_AIX && crtl->calls_eh_return)
27533 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
27534 rtx join_insn, note;
27535 rtx_insn *save_insn;
27536 long toc_restore_insn;
27538 tmp_reg = gen_rtx_REG (Pmode, 11);
27539 tmp_reg_si = gen_rtx_REG (SImode, 11);
27540 if (using_static_chain_p)
27543 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
27547 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
27548 /* Peek at instruction to which this function returns. If it's
27549 restoring r2, then we know we've already saved r2. We can't
27550 unconditionally save r2 because the value we have will already
27551 be updated if we arrived at this function via a plt call or
27552 toc adjusting stub. */
27553 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
27554 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
27555 + RS6000_TOC_SAVE_SLOT);
27556 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
27557 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
27558 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
27559 validate_condition_mode (EQ, CCUNSmode);
27560 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
27561 emit_insn (gen_rtx_SET (compare_result,
27562 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
27563 toc_save_done = gen_label_rtx ();
27564 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27565 gen_rtx_EQ (VOIDmode, compare_result,
27567 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
27569 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27570 JUMP_LABEL (jump) = toc_save_done;
27571 LABEL_NUSES (toc_save_done) += 1;
27573 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
27574 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
27575 sp_off - frame_off);
27577 emit_label (toc_save_done);
27579 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27580 have a CFG that has different saves along different paths.
27581 Move the note to a dummy blockage insn, which describes that
27582 R2 is unconditionally saved after the label. */
27583 /* ??? An alternate representation might be a special insn pattern
27584 containing both the branch and the store. That might let the
27585 code that minimizes the number of DW_CFA_advance opcodes better
27586 freedom in placing the annotations. */
27587 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
27589 remove_note (save_insn, note);
27591 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
27592 copy_rtx (PATTERN (save_insn)), NULL_RTX);
27593 RTX_FRAME_RELATED_P (save_insn) = 0;
27595 join_insn = emit_insn (gen_blockage ());
27596 REG_NOTES (join_insn) = note;
27597 RTX_FRAME_RELATED_P (join_insn) = 1;
27599 if (using_static_chain_p)
27601 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
27608 /* Save CR if we use any that must be preserved. */
27609 if (!WORLD_SAVE_P (info) && info->cr_save_p)
27611 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27612 GEN_INT (info->cr_save_offset + frame_off));
27613 rtx mem = gen_frame_mem (SImode, addr);
27615 /* If we didn't copy cr before, do so now using r0. */
27616 if (cr_save_rtx == NULL_RTX)
27619 cr_save_rtx = gen_rtx_REG (SImode, 0);
27620 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27623 /* Saving CR requires a two-instruction sequence: one instruction
27624 to move the CR to a general-purpose register, and a second
27625 instruction that stores the GPR to memory.
27627 We do not emit any DWARF CFI records for the first of these,
27628 because we cannot properly represent the fact that CR is saved in
27629 a register. One reason is that we cannot express that multiple
27630 CR fields are saved; another reason is that on 64-bit, the size
27631 of the CR register in DWARF (4 bytes) differs from the size of
27632 a general-purpose register.
27634 This means if any intervening instruction were to clobber one of
27635 the call-saved CR fields, we'd have incorrect CFI. To prevent
27636 this from happening, we mark the store to memory as a use of
27637 those CR fields, which prevents any such instruction from being
27638 scheduled in between the two instructions. */
27643 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
27644 for (i = 0; i < 8; i++)
27645 if (save_reg_p (CR0_REGNO + i))
27646 crsave_v[n_crsave++]
27647 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27649 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
27650 gen_rtvec_v (n_crsave, crsave_v)));
27651 END_USE (REGNO (cr_save_rtx));
27653 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27654 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27655 so we need to construct a frame expression manually. */
27656 RTX_FRAME_RELATED_P (insn) = 1;
27658 /* Update address to be stack-pointer relative, like
27659 rs6000_frame_related would do. */
27660 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
27661 GEN_INT (info->cr_save_offset + sp_off));
27662 mem = gen_frame_mem (SImode, addr);
27664 if (DEFAULT_ABI == ABI_ELFv2)
27666 /* In the ELFv2 ABI we generate separate CFI records for each
27667 CR field that was actually saved. They all point to the
27668 same 32-bit stack slot. */
27672 for (i = 0; i < 8; i++)
27673 if (save_reg_p (CR0_REGNO + i))
27676 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
27678 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
27682 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27683 gen_rtx_PARALLEL (VOIDmode,
27684 gen_rtvec_v (n_crframe, crframe)));
27688 /* In other ABIs, by convention, we use a single CR regnum to
27689 represent the fact that all call-saved CR fields are saved.
27690 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27691 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
27692 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
27696 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27697 *separate* slots if the routine calls __builtin_eh_return, so
27698 that they can be independently restored by the unwinder. */
27699 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
27701 int i, cr_off = info->ehcr_offset;
27704 /* ??? We might get better performance by using multiple mfocrf
27706 crsave = gen_rtx_REG (SImode, 0);
27707 emit_insn (gen_prologue_movesi_from_cr (crsave));
27709 for (i = 0; i < 8; i++)
27710 if (!call_used_regs[CR0_REGNO + i])
27712 rtvec p = rtvec_alloc (2);
27714 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
27716 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27718 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27720 RTX_FRAME_RELATED_P (insn) = 1;
27721 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27722 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
27723 sp_reg_rtx, cr_off + sp_off));
27725 cr_off += reg_size;
27729 /* If we are emitting stack probes, but allocate no stack, then
27730 just note that in the dump file. */
27731 if (flag_stack_clash_protection
27734 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
27736 /* Update stack and set back pointer unless this is V.4,
27737 for which it was done previously. */
27738 if (!WORLD_SAVE_P (info) && info->push_p
27739 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
27741 rtx ptr_reg = NULL;
27744 /* If saving altivec regs we need to be able to address all save
27745 locations using a 16-bit offset. */
27746 if ((strategy & SAVE_INLINE_VRS) == 0
27747 || (info->altivec_size != 0
27748 && (info->altivec_save_offset + info->altivec_size - 16
27749 + info->total_size - frame_off) > 32767)
27750 || (info->vrsave_size != 0
27751 && (info->vrsave_save_offset
27752 + info->total_size - frame_off) > 32767))
27754 int sel = SAVRES_SAVE | SAVRES_VR;
27755 unsigned ptr_regno = ptr_regno_for_savres (sel);
27757 if (using_static_chain_p
27758 && ptr_regno == STATIC_CHAIN_REGNUM)
27760 if (REGNO (frame_reg_rtx) != ptr_regno)
27761 START_USE (ptr_regno);
27762 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27763 frame_reg_rtx = ptr_reg;
27764 ptr_off = info->altivec_save_offset + info->altivec_size;
27765 frame_off = -ptr_off;
27767 else if (REGNO (frame_reg_rtx) == 1)
27768 frame_off = info->total_size;
27769 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27771 if (REGNO (frame_reg_rtx) == 12)
27773 sp_off = info->total_size;
27774 if (frame_reg_rtx != sp_reg_rtx)
27775 rs6000_emit_stack_tie (frame_reg_rtx, false);
27778 /* Set frame pointer, if needed. */
27779 if (frame_pointer_needed)
27781 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
27783 RTX_FRAME_RELATED_P (insn) = 1;
27786 /* Save AltiVec registers if needed. Save here because the red zone does
27787 not always include AltiVec registers. */
27788 if (!WORLD_SAVE_P (info)
27789 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
27791 int end_save = info->altivec_save_offset + info->altivec_size;
27793 /* Oddly, the vector save/restore functions point r0 at the end
27794 of the save area, then use r11 or r12 to load offsets for
27795 [reg+reg] addressing. */
27796 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27797 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
27798 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27800 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27802 if (scratch_regno == 12)
27804 if (end_save + frame_off != 0)
27806 rtx offset = GEN_INT (end_save + frame_off);
27808 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27811 emit_move_insn (ptr_reg, frame_reg_rtx);
27813 ptr_off = -end_save;
27814 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27815 info->altivec_save_offset + ptr_off,
27816 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27817 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27818 NULL_RTX, NULL_RTX);
27819 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27821 /* The oddity mentioned above clobbered our frame reg. */
27822 emit_move_insn (frame_reg_rtx, ptr_reg);
27823 frame_off = ptr_off;
27826 else if (!WORLD_SAVE_P (info)
27827 && info->altivec_size != 0)
27831 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27832 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27834 rtx areg, savereg, mem;
27835 HOST_WIDE_INT offset;
27837 offset = (info->altivec_save_offset + frame_off
27838 + 16 * (i - info->first_altivec_reg_save));
27840 savereg = gen_rtx_REG (V4SImode, i);
27842 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27844 mem = gen_frame_mem (V4SImode,
27845 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27846 GEN_INT (offset)));
27847 insn = emit_insn (gen_rtx_SET (mem, savereg));
27853 areg = gen_rtx_REG (Pmode, 0);
27854 emit_move_insn (areg, GEN_INT (offset));
27856 /* AltiVec addressing mode is [reg+reg]. */
27857 mem = gen_frame_mem (V4SImode,
27858 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27860 /* Rather than emitting a generic move, force use of the stvx
27861 instruction, which we always want on ISA 2.07 (power8) systems.
27862 In particular we don't want xxpermdi/stxvd2x for little
27864 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27867 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27868 areg, GEN_INT (offset));
27872 /* VRSAVE is a bit vector representing which AltiVec registers
27873 are used. The OS uses this to determine which vector
27874 registers to save on a context switch. We need to save
27875 VRSAVE on the stack frame, add whatever AltiVec registers we
27876 used in this function, and do the corresponding magic in the
27879 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27881 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27882 be using r12 as frame_reg_rtx and r11 as the static chain
27883 pointer for nested functions. */
27884 int save_regno = 12;
27885 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27886 && !using_static_chain_p)
27888 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27891 if (using_static_chain_p)
27894 NOT_INUSE (save_regno);
27896 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27899 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27900 if (!TARGET_SINGLE_PIC_BASE
27901 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27902 && !constant_pool_empty_p ())
27903 || (DEFAULT_ABI == ABI_V4
27904 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27905 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27907 /* If emit_load_toc_table will use the link register, we need to save
27908 it. We use R12 for this purpose because emit_load_toc_table
27909 can use register 0. This allows us to use a plain 'blr' to return
27910 from the procedure more often. */
27911 int save_LR_around_toc_setup = (TARGET_ELF
27912 && DEFAULT_ABI == ABI_V4
27914 && ! info->lr_save_p
27915 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27916 if (save_LR_around_toc_setup)
27918 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27919 rtx tmp = gen_rtx_REG (Pmode, 12);
27922 insn = emit_move_insn (tmp, lr);
27923 RTX_FRAME_RELATED_P (insn) = 1;
27925 rs6000_emit_load_toc_table (TRUE);
27927 insn = emit_move_insn (lr, tmp);
27928 add_reg_note (insn, REG_CFA_RESTORE, lr);
27929 RTX_FRAME_RELATED_P (insn) = 1;
27932 rs6000_emit_load_toc_table (TRUE);
27936 if (!TARGET_SINGLE_PIC_BASE
27937 && DEFAULT_ABI == ABI_DARWIN
27938 && flag_pic && crtl->uses_pic_offset_table)
27940 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27941 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27943 /* Save and restore LR locally around this call (in R0). */
27944 if (!info->lr_save_p)
27945 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27947 emit_insn (gen_load_macho_picbase (src));
27949 emit_move_insn (gen_rtx_REG (Pmode,
27950 RS6000_PIC_OFFSET_TABLE_REGNUM),
27953 if (!info->lr_save_p)
27954 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27958 /* If we need to, save the TOC register after doing the stack setup.
27959 Do not emit eh frame info for this save. The unwinder wants info,
27960 conceptually attached to instructions in this function, about
27961 register values in the caller of this function. This R2 may have
27962 already been changed from the value in the caller.
27963 We don't attempt to write accurate DWARF EH frame info for R2
27964 because code emitted by gcc for a (non-pointer) function call
27965 doesn't save and restore R2. Instead, R2 is managed out-of-line
27966 by a linker generated plt call stub when the function resides in
27967 a shared library. This behavior is costly to describe in DWARF,
27968 both in terms of the size of DWARF info and the time taken in the
27969 unwinder to interpret it. R2 changes, apart from the
27970 calls_eh_return case earlier in this function, are handled by
27971 linux-unwind.h frob_update_context. */
27972 if (rs6000_save_toc_in_prologue_p ()
27973 && !cfun->machine->toc_is_wrapped_separately)
27975 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
27976 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
27979 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27980 if (using_split_stack && split_stack_arg_pointer_used_p ())
27981 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
27984 /* Output .extern statements for the save/restore routines we use. */
27987 rs6000_output_savres_externs (FILE *file)
27989 rs6000_stack_t *info = rs6000_stack_info ();
27991 if (TARGET_DEBUG_STACK)
27992 debug_stack_info (info);
27994 /* Write .extern for any function we will call to save and restore
27996 if (info->first_fp_reg_save < 64
28001 int regno = info->first_fp_reg_save - 32;
28003 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
28005 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
28006 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
28007 name = rs6000_savres_routine_name (regno, sel);
28008 fprintf (file, "\t.extern %s\n", name);
28010 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
28012 bool lr = (info->savres_strategy
28013 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28014 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28015 name = rs6000_savres_routine_name (regno, sel);
28016 fprintf (file, "\t.extern %s\n", name);
28021 /* Write function prologue. */
28024 rs6000_output_function_prologue (FILE *file)
28026 if (!cfun->is_thunk)
28027 rs6000_output_savres_externs (file);
28029 /* ELFv2 ABI r2 setup code and local entry point. This must follow
28030 immediately after the global entry point label. */
28031 if (rs6000_global_entry_point_needed_p ())
28033 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
28035 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
28037 if (TARGET_CMODEL != CMODEL_LARGE)
28039 /* In the small and medium code models, we assume the TOC is less
28040 2 GB away from the text section, so it can be computed via the
28041 following two-instruction sequence. */
28044 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
28045 fprintf (file, "0:\taddis 2,12,.TOC.-");
28046 assemble_name (file, buf);
28047 fprintf (file, "@ha\n");
28048 fprintf (file, "\taddi 2,2,.TOC.-");
28049 assemble_name (file, buf);
28050 fprintf (file, "@l\n");
28054 /* In the large code model, we allow arbitrary offsets between the
28055 TOC and the text section, so we have to load the offset from
28056 memory. The data field is emitted directly before the global
28057 entry point in rs6000_elf_declare_function_name. */
28060 #ifdef HAVE_AS_ENTRY_MARKERS
28061 /* If supported by the linker, emit a marker relocation. If the
28062 total code size of the final executable or shared library
28063 happens to fit into 2 GB after all, the linker will replace
28064 this code sequence with the sequence for the small or medium
28066 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
28068 fprintf (file, "\tld 2,");
28069 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
28070 assemble_name (file, buf);
28071 fprintf (file, "-");
28072 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
28073 assemble_name (file, buf);
28074 fprintf (file, "(12)\n");
28075 fprintf (file, "\tadd 2,2,12\n");
28078 fputs ("\t.localentry\t", file);
28079 assemble_name (file, name);
28080 fputs (",.-", file);
28081 assemble_name (file, name);
28082 fputs ("\n", file);
28085 /* Output -mprofile-kernel code. This needs to be done here instead of
28086 in output_function_profile since it must go after the ELFv2 ABI
28087 local entry point. */
28088 if (TARGET_PROFILE_KERNEL && crtl->profile)
28090 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
28091 gcc_assert (!TARGET_32BIT);
28093 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
28095 /* In the ELFv2 ABI we have no compiler stack word. It must be
28096 the resposibility of _mcount to preserve the static chain
28097 register if required. */
28098 if (DEFAULT_ABI != ABI_ELFv2
28099 && cfun->static_chain_decl != NULL)
28101 asm_fprintf (file, "\tstd %s,24(%s)\n",
28102 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
28103 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
28104 asm_fprintf (file, "\tld %s,24(%s)\n",
28105 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
28108 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
28111 rs6000_pic_labelno++;
28114 /* -mprofile-kernel code calls mcount before the function prolog,
28115 so a profiled leaf function should stay a leaf function. */
28117 rs6000_keep_leaf_when_profiled ()
28119 return TARGET_PROFILE_KERNEL;
28122 /* Non-zero if vmx regs are restored before the frame pop, zero if
28123 we restore after the pop when possible. */
28124 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
28126 /* Restoring cr is a two step process: loading a reg from the frame
28127 save, then moving the reg to cr. For ABI_V4 we must let the
28128 unwinder know that the stack location is no longer valid at or
28129 before the stack deallocation, but we can't emit a cfa_restore for
28130 cr at the stack deallocation like we do for other registers.
28131 The trouble is that it is possible for the move to cr to be
28132 scheduled after the stack deallocation. So say exactly where cr
28133 is located on each of the two insns. */
28136 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
28138 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
28139 rtx reg = gen_rtx_REG (SImode, regno);
28140 rtx_insn *insn = emit_move_insn (reg, mem);
28142 if (!exit_func && DEFAULT_ABI == ABI_V4)
28144 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
28145 rtx set = gen_rtx_SET (reg, cr);
28147 add_reg_note (insn, REG_CFA_REGISTER, set);
28148 RTX_FRAME_RELATED_P (insn) = 1;
28153 /* Reload CR from REG. */
28156 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
28161 if (using_mfcr_multiple)
28163 for (i = 0; i < 8; i++)
28164 if (save_reg_p (CR0_REGNO + i))
28166 gcc_assert (count);
28169 if (using_mfcr_multiple && count > 1)
28175 p = rtvec_alloc (count);
28178 for (i = 0; i < 8; i++)
28179 if (save_reg_p (CR0_REGNO + i))
28181 rtvec r = rtvec_alloc (2);
28182 RTVEC_ELT (r, 0) = reg;
28183 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
28184 RTVEC_ELT (p, ndx) =
28185 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
28186 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
28189 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28190 gcc_assert (ndx == count);
28192 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
28193 CR field separately. */
28194 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
28196 for (i = 0; i < 8; i++)
28197 if (save_reg_p (CR0_REGNO + i))
28198 add_reg_note (insn, REG_CFA_RESTORE,
28199 gen_rtx_REG (SImode, CR0_REGNO + i));
28201 RTX_FRAME_RELATED_P (insn) = 1;
28205 for (i = 0; i < 8; i++)
28206 if (save_reg_p (CR0_REGNO + i))
28208 rtx insn = emit_insn (gen_movsi_to_cr_one
28209 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28211 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
28212 CR field separately, attached to the insn that in fact
28213 restores this particular CR field. */
28214 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
28216 add_reg_note (insn, REG_CFA_RESTORE,
28217 gen_rtx_REG (SImode, CR0_REGNO + i));
28219 RTX_FRAME_RELATED_P (insn) = 1;
28223 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
28224 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
28225 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
28227 rtx_insn *insn = get_last_insn ();
28228 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
28230 add_reg_note (insn, REG_CFA_RESTORE, cr);
28231 RTX_FRAME_RELATED_P (insn) = 1;
28235 /* Like cr, the move to lr instruction can be scheduled after the
28236 stack deallocation, but unlike cr, its stack frame save is still
28237 valid. So we only need to emit the cfa_restore on the correct
28241 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
28243 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
28244 rtx reg = gen_rtx_REG (Pmode, regno);
28246 emit_move_insn (reg, mem);
28250 restore_saved_lr (int regno, bool exit_func)
28252 rtx reg = gen_rtx_REG (Pmode, regno);
28253 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
28254 rtx_insn *insn = emit_move_insn (lr, reg);
28256 if (!exit_func && flag_shrink_wrap)
28258 add_reg_note (insn, REG_CFA_RESTORE, lr);
28259 RTX_FRAME_RELATED_P (insn) = 1;
28264 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
28266 if (DEFAULT_ABI == ABI_ELFv2)
28269 for (i = 0; i < 8; i++)
28270 if (save_reg_p (CR0_REGNO + i))
28272 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
28273 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
28277 else if (info->cr_save_p)
28278 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28279 gen_rtx_REG (SImode, CR2_REGNO),
28282 if (info->lr_save_p)
28283 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28284 gen_rtx_REG (Pmode, LR_REGNO),
28286 return cfa_restores;
28289 /* Return true if OFFSET from stack pointer can be clobbered by signals.
28290 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
28291 below stack pointer not cloberred by signals. */
28294 offset_below_red_zone_p (HOST_WIDE_INT offset)
28296 return offset < (DEFAULT_ABI == ABI_V4
28298 : TARGET_32BIT ? -220 : -288);
28301 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
28304 emit_cfa_restores (rtx cfa_restores)
28306 rtx_insn *insn = get_last_insn ();
28307 rtx *loc = ®_NOTES (insn);
28310 loc = &XEXP (*loc, 1);
28311 *loc = cfa_restores;
28312 RTX_FRAME_RELATED_P (insn) = 1;
28315 /* Emit function epilogue as insns. */
28318 rs6000_emit_epilogue (int sibcall)
28320 rs6000_stack_t *info;
28321 int restoring_GPRs_inline;
28322 int restoring_FPRs_inline;
28323 int using_load_multiple;
28324 int using_mtcr_multiple;
28325 int use_backchain_to_restore_sp;
28328 HOST_WIDE_INT frame_off = 0;
28329 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
28330 rtx frame_reg_rtx = sp_reg_rtx;
28331 rtx cfa_restores = NULL_RTX;
28333 rtx cr_save_reg = NULL_RTX;
28334 machine_mode reg_mode = Pmode;
28335 int reg_size = TARGET_32BIT ? 4 : 8;
28336 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
28338 int fp_reg_size = 8;
28341 unsigned ptr_regno;
28343 info = rs6000_stack_info ();
28345 strategy = info->savres_strategy;
28346 using_load_multiple = strategy & REST_MULTIPLE;
28347 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
28348 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
28349 using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
28350 || rs6000_tune == PROCESSOR_PPC603
28351 || rs6000_tune == PROCESSOR_PPC750
28353 /* Restore via the backchain when we have a large frame, since this
28354 is more efficient than an addis, addi pair. The second condition
28355 here will not trigger at the moment; We don't actually need a
28356 frame pointer for alloca, but the generic parts of the compiler
28357 give us one anyway. */
28358 use_backchain_to_restore_sp = (info->total_size + (info->lr_save_p
28359 ? info->lr_save_offset
28361 || (cfun->calls_alloca
28362 && !frame_pointer_needed));
28363 restore_lr = (info->lr_save_p
28364 && (restoring_FPRs_inline
28365 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
28366 && (restoring_GPRs_inline
28367 || info->first_fp_reg_save < 64)
28368 && !cfun->machine->lr_is_wrapped_separately);
28371 if (WORLD_SAVE_P (info))
28375 const char *alloc_rname;
28378 /* eh_rest_world_r10 will return to the location saved in the LR
28379 stack slot (which is not likely to be our caller.)
28380 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
28381 rest_world is similar, except any R10 parameter is ignored.
28382 The exception-handling stuff that was here in 2.95 is no
28383 longer necessary. */
28386 + 32 - info->first_gp_reg_save
28387 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
28388 + 63 + 1 - info->first_fp_reg_save);
28390 strcpy (rname, ((crtl->calls_eh_return) ?
28391 "*eh_rest_world_r10" : "*rest_world"));
28392 alloc_rname = ggc_strdup (rname);
28395 RTVEC_ELT (p, j++) = ret_rtx;
28397 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
28398 /* The instruction pattern requires a clobber here;
28399 it is shared with the restVEC helper. */
28401 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
28404 /* CR register traditionally saved as CR2. */
28405 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
28407 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
28408 if (flag_shrink_wrap)
28410 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28411 gen_rtx_REG (Pmode, LR_REGNO),
28413 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28417 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28419 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
28421 = gen_frame_load (reg,
28422 frame_reg_rtx, info->gp_save_offset + reg_size * i);
28423 if (flag_shrink_wrap
28424 && save_reg_p (info->first_gp_reg_save + i))
28425 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28427 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
28429 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
28431 = gen_frame_load (reg,
28432 frame_reg_rtx, info->altivec_save_offset + 16 * i);
28433 if (flag_shrink_wrap
28434 && save_reg_p (info->first_altivec_reg_save + i))
28435 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28437 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
28439 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
28440 ? DFmode : SFmode),
28441 info->first_fp_reg_save + i);
28443 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
28444 if (flag_shrink_wrap
28445 && save_reg_p (info->first_fp_reg_save + i))
28446 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28449 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
28451 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
28453 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
28455 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
28457 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
28458 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28460 if (flag_shrink_wrap)
28462 REG_NOTES (insn) = cfa_restores;
28463 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28464 RTX_FRAME_RELATED_P (insn) = 1;
28469 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
28471 frame_off = info->total_size;
28473 /* Restore AltiVec registers if we must do so before adjusting the
28475 if (info->altivec_size != 0
28476 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28477 || (DEFAULT_ABI != ABI_V4
28478 && offset_below_red_zone_p (info->altivec_save_offset))))
28481 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28483 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
28484 if (use_backchain_to_restore_sp)
28486 int frame_regno = 11;
28488 if ((strategy & REST_INLINE_VRS) == 0)
28490 /* Of r11 and r12, select the one not clobbered by an
28491 out-of-line restore function for the frame register. */
28492 frame_regno = 11 + 12 - scratch_regno;
28494 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
28495 emit_move_insn (frame_reg_rtx,
28496 gen_rtx_MEM (Pmode, sp_reg_rtx));
28499 else if (frame_pointer_needed)
28500 frame_reg_rtx = hard_frame_pointer_rtx;
28502 if ((strategy & REST_INLINE_VRS) == 0)
28504 int end_save = info->altivec_save_offset + info->altivec_size;
28506 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28507 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28509 if (end_save + frame_off != 0)
28511 rtx offset = GEN_INT (end_save + frame_off);
28513 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28516 emit_move_insn (ptr_reg, frame_reg_rtx);
28518 ptr_off = -end_save;
28519 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28520 info->altivec_save_offset + ptr_off,
28521 0, V4SImode, SAVRES_VR);
28525 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28526 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28528 rtx addr, areg, mem, insn;
28529 rtx reg = gen_rtx_REG (V4SImode, i);
28530 HOST_WIDE_INT offset
28531 = (info->altivec_save_offset + frame_off
28532 + 16 * (i - info->first_altivec_reg_save));
28534 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28536 mem = gen_frame_mem (V4SImode,
28537 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28538 GEN_INT (offset)));
28539 insn = gen_rtx_SET (reg, mem);
28543 areg = gen_rtx_REG (Pmode, 0);
28544 emit_move_insn (areg, GEN_INT (offset));
28546 /* AltiVec addressing mode is [reg+reg]. */
28547 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28548 mem = gen_frame_mem (V4SImode, addr);
28550 /* Rather than emitting a generic move, force use of the
28551 lvx instruction, which we always want. In particular we
28552 don't want lxvd2x/xxpermdi for little endian. */
28553 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28556 (void) emit_insn (insn);
28560 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28561 if (((strategy & REST_INLINE_VRS) == 0
28562 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28563 && (flag_shrink_wrap
28564 || (offset_below_red_zone_p
28565 (info->altivec_save_offset
28566 + 16 * (i - info->first_altivec_reg_save))))
28569 rtx reg = gen_rtx_REG (V4SImode, i);
28570 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28574 /* Restore VRSAVE if we must do so before adjusting the stack. */
28575 if (info->vrsave_size != 0
28576 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28577 || (DEFAULT_ABI != ABI_V4
28578 && offset_below_red_zone_p (info->vrsave_save_offset))))
28582 if (frame_reg_rtx == sp_reg_rtx)
28584 if (use_backchain_to_restore_sp)
28586 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28587 emit_move_insn (frame_reg_rtx,
28588 gen_rtx_MEM (Pmode, sp_reg_rtx));
28591 else if (frame_pointer_needed)
28592 frame_reg_rtx = hard_frame_pointer_rtx;
28595 reg = gen_rtx_REG (SImode, 12);
28596 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28597 info->vrsave_save_offset + frame_off));
28599 emit_insn (generate_set_vrsave (reg, info, 1));
28603 /* If we have a large stack frame, restore the old stack pointer
28604 using the backchain. */
28605 if (use_backchain_to_restore_sp)
28607 if (frame_reg_rtx == sp_reg_rtx)
28609 /* Under V.4, don't reset the stack pointer until after we're done
28610 loading the saved registers. */
28611 if (DEFAULT_ABI == ABI_V4)
28612 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28614 insn = emit_move_insn (frame_reg_rtx,
28615 gen_rtx_MEM (Pmode, sp_reg_rtx));
28618 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28619 && DEFAULT_ABI == ABI_V4)
28620 /* frame_reg_rtx has been set up by the altivec restore. */
28624 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
28625 frame_reg_rtx = sp_reg_rtx;
28628 /* If we have a frame pointer, we can restore the old stack pointer
28630 else if (frame_pointer_needed)
28632 frame_reg_rtx = sp_reg_rtx;
28633 if (DEFAULT_ABI == ABI_V4)
28634 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28635 /* Prevent reordering memory accesses against stack pointer restore. */
28636 else if (cfun->calls_alloca
28637 || offset_below_red_zone_p (-info->total_size))
28638 rs6000_emit_stack_tie (frame_reg_rtx, true);
28640 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
28641 GEN_INT (info->total_size)));
28644 else if (info->push_p
28645 && DEFAULT_ABI != ABI_V4
28646 && !crtl->calls_eh_return)
28648 /* Prevent reordering memory accesses against stack pointer restore. */
28649 if (cfun->calls_alloca
28650 || offset_below_red_zone_p (-info->total_size))
28651 rs6000_emit_stack_tie (frame_reg_rtx, false);
28652 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
28653 GEN_INT (info->total_size)));
28656 if (insn && frame_reg_rtx == sp_reg_rtx)
28660 REG_NOTES (insn) = cfa_restores;
28661 cfa_restores = NULL_RTX;
28663 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28664 RTX_FRAME_RELATED_P (insn) = 1;
28667 /* Restore AltiVec registers if we have not done so already. */
28668 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28669 && info->altivec_size != 0
28670 && (DEFAULT_ABI == ABI_V4
28671 || !offset_below_red_zone_p (info->altivec_save_offset)))
28675 if ((strategy & REST_INLINE_VRS) == 0)
28677 int end_save = info->altivec_save_offset + info->altivec_size;
28679 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28680 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28681 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28683 if (end_save + frame_off != 0)
28685 rtx offset = GEN_INT (end_save + frame_off);
28687 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28690 emit_move_insn (ptr_reg, frame_reg_rtx);
28692 ptr_off = -end_save;
28693 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28694 info->altivec_save_offset + ptr_off,
28695 0, V4SImode, SAVRES_VR);
28696 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
28698 /* Frame reg was clobbered by out-of-line save. Restore it
28699 from ptr_reg, and if we are calling out-of-line gpr or
28700 fpr restore set up the correct pointer and offset. */
28701 unsigned newptr_regno = 1;
28702 if (!restoring_GPRs_inline)
28704 bool lr = info->gp_save_offset + info->gp_size == 0;
28705 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28706 newptr_regno = ptr_regno_for_savres (sel);
28707 end_save = info->gp_save_offset + info->gp_size;
28709 else if (!restoring_FPRs_inline)
28711 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
28712 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28713 newptr_regno = ptr_regno_for_savres (sel);
28714 end_save = info->fp_save_offset + info->fp_size;
28717 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
28718 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
28720 if (end_save + ptr_off != 0)
28722 rtx offset = GEN_INT (end_save + ptr_off);
28724 frame_off = -end_save;
28726 emit_insn (gen_addsi3_carry (frame_reg_rtx,
28729 emit_insn (gen_adddi3_carry (frame_reg_rtx,
28734 frame_off = ptr_off;
28735 emit_move_insn (frame_reg_rtx, ptr_reg);
28741 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28742 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28744 rtx addr, areg, mem, insn;
28745 rtx reg = gen_rtx_REG (V4SImode, i);
28746 HOST_WIDE_INT offset
28747 = (info->altivec_save_offset + frame_off
28748 + 16 * (i - info->first_altivec_reg_save));
28750 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28752 mem = gen_frame_mem (V4SImode,
28753 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28754 GEN_INT (offset)));
28755 insn = gen_rtx_SET (reg, mem);
28759 areg = gen_rtx_REG (Pmode, 0);
28760 emit_move_insn (areg, GEN_INT (offset));
28762 /* AltiVec addressing mode is [reg+reg]. */
28763 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28764 mem = gen_frame_mem (V4SImode, addr);
28766 /* Rather than emitting a generic move, force use of the
28767 lvx instruction, which we always want. In particular we
28768 don't want lxvd2x/xxpermdi for little endian. */
28769 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28772 (void) emit_insn (insn);
28776 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28777 if (((strategy & REST_INLINE_VRS) == 0
28778 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28779 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28782 rtx reg = gen_rtx_REG (V4SImode, i);
28783 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28787 /* Restore VRSAVE if we have not done so already. */
28788 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28789 && info->vrsave_size != 0
28790 && (DEFAULT_ABI == ABI_V4
28791 || !offset_below_red_zone_p (info->vrsave_save_offset)))
28795 reg = gen_rtx_REG (SImode, 12);
28796 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28797 info->vrsave_save_offset + frame_off));
28799 emit_insn (generate_set_vrsave (reg, info, 1));
28802 /* If we exit by an out-of-line restore function on ABI_V4 then that
28803 function will deallocate the stack, so we don't need to worry
28804 about the unwinder restoring cr from an invalid stack frame
28806 exit_func = (!restoring_FPRs_inline
28807 || (!restoring_GPRs_inline
28808 && info->first_fp_reg_save == 64));
28810 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28811 *separate* slots if the routine calls __builtin_eh_return, so
28812 that they can be independently restored by the unwinder. */
28813 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28815 int i, cr_off = info->ehcr_offset;
28817 for (i = 0; i < 8; i++)
28818 if (!call_used_regs[CR0_REGNO + i])
28820 rtx reg = gen_rtx_REG (SImode, 0);
28821 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28822 cr_off + frame_off));
28824 insn = emit_insn (gen_movsi_to_cr_one
28825 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28827 if (!exit_func && flag_shrink_wrap)
28829 add_reg_note (insn, REG_CFA_RESTORE,
28830 gen_rtx_REG (SImode, CR0_REGNO + i));
28832 RTX_FRAME_RELATED_P (insn) = 1;
28835 cr_off += reg_size;
28839 /* Get the old lr if we saved it. If we are restoring registers
28840 out-of-line, then the out-of-line routines can do this for us. */
28841 if (restore_lr && restoring_GPRs_inline)
28842 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28844 /* Get the old cr if we saved it. */
28845 if (info->cr_save_p)
28847 unsigned cr_save_regno = 12;
28849 if (!restoring_GPRs_inline)
28851 /* Ensure we don't use the register used by the out-of-line
28852 gpr register restore below. */
28853 bool lr = info->gp_save_offset + info->gp_size == 0;
28854 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28855 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28857 if (gpr_ptr_regno == 12)
28858 cr_save_regno = 11;
28859 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28861 else if (REGNO (frame_reg_rtx) == 12)
28862 cr_save_regno = 11;
28864 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28865 info->cr_save_offset + frame_off,
28869 /* Set LR here to try to overlap restores below. */
28870 if (restore_lr && restoring_GPRs_inline)
28871 restore_saved_lr (0, exit_func);
28873 /* Load exception handler data registers, if needed. */
28874 if (crtl->calls_eh_return)
28876 unsigned int i, regno;
28880 rtx reg = gen_rtx_REG (reg_mode, 2);
28881 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28882 frame_off + RS6000_TOC_SAVE_SLOT));
28889 regno = EH_RETURN_DATA_REGNO (i);
28890 if (regno == INVALID_REGNUM)
28893 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28894 info->ehrd_offset + frame_off
28895 + reg_size * (int) i);
28897 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28901 /* Restore GPRs. This is done as a PARALLEL if we are using
28902 the load-multiple instructions. */
28903 if (!restoring_GPRs_inline)
28905 /* We are jumping to an out-of-line function. */
28907 int end_save = info->gp_save_offset + info->gp_size;
28908 bool can_use_exit = end_save == 0;
28909 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28912 /* Emit stack reset code if we need it. */
28913 ptr_regno = ptr_regno_for_savres (sel);
28914 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28916 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28917 else if (end_save + frame_off != 0)
28918 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28919 GEN_INT (end_save + frame_off)));
28920 else if (REGNO (frame_reg_rtx) != ptr_regno)
28921 emit_move_insn (ptr_reg, frame_reg_rtx);
28922 if (REGNO (frame_reg_rtx) == ptr_regno)
28923 frame_off = -end_save;
28925 if (can_use_exit && info->cr_save_p)
28926 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28928 ptr_off = -end_save;
28929 rs6000_emit_savres_rtx (info, ptr_reg,
28930 info->gp_save_offset + ptr_off,
28931 info->lr_save_offset + ptr_off,
28934 else if (using_load_multiple)
28937 p = rtvec_alloc (32 - info->first_gp_reg_save);
28938 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28940 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28942 info->gp_save_offset + frame_off + reg_size * i);
28943 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28947 int offset = info->gp_save_offset + frame_off;
28948 for (i = info->first_gp_reg_save; i < 32; i++)
28951 && !cfun->machine->gpr_is_wrapped_separately[i])
28953 rtx reg = gen_rtx_REG (reg_mode, i);
28954 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28957 offset += reg_size;
28961 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28963 /* If the frame pointer was used then we can't delay emitting
28964 a REG_CFA_DEF_CFA note. This must happen on the insn that
28965 restores the frame pointer, r31. We may have already emitted
28966 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28967 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28968 be harmless if emitted. */
28969 if (frame_pointer_needed)
28971 insn = get_last_insn ();
28972 add_reg_note (insn, REG_CFA_DEF_CFA,
28973 plus_constant (Pmode, frame_reg_rtx, frame_off));
28974 RTX_FRAME_RELATED_P (insn) = 1;
28977 /* Set up cfa_restores. We always need these when
28978 shrink-wrapping. If not shrink-wrapping then we only need
28979 the cfa_restore when the stack location is no longer valid.
28980 The cfa_restores must be emitted on or before the insn that
28981 invalidates the stack, and of course must not be emitted
28982 before the insn that actually does the restore. The latter
28983 is why it is a bad idea to emit the cfa_restores as a group
28984 on the last instruction here that actually does a restore:
28985 That insn may be reordered with respect to others doing
28987 if (flag_shrink_wrap
28988 && !restoring_GPRs_inline
28989 && info->first_fp_reg_save == 64)
28990 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28992 for (i = info->first_gp_reg_save; i < 32; i++)
28994 && !cfun->machine->gpr_is_wrapped_separately[i])
28996 rtx reg = gen_rtx_REG (reg_mode, i);
28997 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
29001 if (!restoring_GPRs_inline
29002 && info->first_fp_reg_save == 64)
29004 /* We are jumping to an out-of-line function. */
29006 emit_cfa_restores (cfa_restores);
29010 if (restore_lr && !restoring_GPRs_inline)
29012 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
29013 restore_saved_lr (0, exit_func);
29016 /* Restore fpr's if we need to do it without calling a function. */
29017 if (restoring_FPRs_inline)
29019 int offset = info->fp_save_offset + frame_off;
29020 for (i = info->first_fp_reg_save; i < 64; i++)
29023 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
29025 rtx reg = gen_rtx_REG (fp_reg_mode, i);
29026 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
29027 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
29028 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
29032 offset += fp_reg_size;
29036 /* If we saved cr, restore it here. Just those that were used. */
29037 if (info->cr_save_p)
29038 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
29040 /* If this is V.4, unwind the stack pointer after all of the loads
29041 have been done, or set up r11 if we are restoring fp out of line. */
29043 if (!restoring_FPRs_inline)
29045 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
29046 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
29047 ptr_regno = ptr_regno_for_savres (sel);
29050 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
29051 if (REGNO (frame_reg_rtx) == ptr_regno)
29054 if (insn && restoring_FPRs_inline)
29058 REG_NOTES (insn) = cfa_restores;
29059 cfa_restores = NULL_RTX;
29061 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
29062 RTX_FRAME_RELATED_P (insn) = 1;
29065 if (crtl->calls_eh_return)
29067 rtx sa = EH_RETURN_STACKADJ_RTX;
29068 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
29071 if (!sibcall && restoring_FPRs_inline)
29075 /* We can't hang the cfa_restores off a simple return,
29076 since the shrink-wrap code sometimes uses an existing
29077 return. This means there might be a path from
29078 pre-prologue code to this return, and dwarf2cfi code
29079 wants the eh_frame unwinder state to be the same on
29080 all paths to any point. So we need to emit the
29081 cfa_restores before the return. For -m64 we really
29082 don't need epilogue cfa_restores at all, except for
29083 this irritating dwarf2cfi with shrink-wrap
29084 requirement; The stack red-zone means eh_frame info
29085 from the prologue telling the unwinder to restore
29086 from the stack is perfectly good right to the end of
29088 emit_insn (gen_blockage ());
29089 emit_cfa_restores (cfa_restores);
29090 cfa_restores = NULL_RTX;
29093 emit_jump_insn (targetm.gen_simple_return ());
29096 if (!sibcall && !restoring_FPRs_inline)
29098 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
29099 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
29101 RTVEC_ELT (p, elt++) = ret_rtx;
29103 RTVEC_ELT (p, elt++)
29104 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
29106 /* We have to restore more than two FP registers, so branch to the
29107 restore function. It will return to our caller. */
29112 if (flag_shrink_wrap)
29113 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
29115 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
29116 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
29117 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
29118 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
29120 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
29122 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
29124 RTVEC_ELT (p, elt++)
29125 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
29126 if (flag_shrink_wrap
29127 && save_reg_p (info->first_fp_reg_save + i))
29128 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
29131 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
29137 /* Ensure the cfa_restores are hung off an insn that won't
29138 be reordered above other restores. */
29139 emit_insn (gen_blockage ());
29141 emit_cfa_restores (cfa_restores);
29145 /* Write function epilogue. */
29148 rs6000_output_function_epilogue (FILE *file)
29151 macho_branch_islands ();
29154 rtx_insn *insn = get_last_insn ();
29155 rtx_insn *deleted_debug_label = NULL;
29157 /* Mach-O doesn't support labels at the end of objects, so if
29158 it looks like we might want one, take special action.
29160 First, collect any sequence of deleted debug labels. */
29163 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
29165 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
29166 notes only, instead set their CODE_LABEL_NUMBER to -1,
29167 otherwise there would be code generation differences
29168 in between -g and -g0. */
29169 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
29170 deleted_debug_label = insn;
29171 insn = PREV_INSN (insn);
29174 /* Second, if we have:
29177 then this needs to be detected, so skip past the barrier. */
29179 if (insn && BARRIER_P (insn))
29180 insn = PREV_INSN (insn);
29182 /* Up to now we've only seen notes or barriers. */
29187 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
29188 /* Trailing label: <barrier>. */
29189 fputs ("\tnop\n", file);
29192 /* Lastly, see if we have a completely empty function body. */
29193 while (insn && ! INSN_P (insn))
29194 insn = PREV_INSN (insn);
29195 /* If we don't find any insns, we've got an empty function body;
29196 I.e. completely empty - without a return or branch. This is
29197 taken as the case where a function body has been removed
29198 because it contains an inline __builtin_unreachable(). GCC
29199 states that reaching __builtin_unreachable() means UB so we're
29200 not obliged to do anything special; however, we want
29201 non-zero-sized function bodies. To meet this, and help the
29202 user out, let's trap the case. */
29204 fputs ("\ttrap\n", file);
29207 else if (deleted_debug_label)
29208 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
29209 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
29210 CODE_LABEL_NUMBER (insn) = -1;
29214 /* Output a traceback table here. See /usr/include/sys/debug.h for info
29217 We don't output a traceback table if -finhibit-size-directive was
29218 used. The documentation for -finhibit-size-directive reads
29219 ``don't output a @code{.size} assembler directive, or anything
29220 else that would cause trouble if the function is split in the
29221 middle, and the two halves are placed at locations far apart in
29222 memory.'' The traceback table has this property, since it
29223 includes the offset from the start of the function to the
29224 traceback table itself.
29226 System V.4 Powerpc's (and the embedded ABI derived from it) use a
29227 different traceback table. */
29228 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29229 && ! flag_inhibit_size_directive
29230 && rs6000_traceback != traceback_none && !cfun->is_thunk)
29232 const char *fname = NULL;
29233 const char *language_string = lang_hooks.name;
29234 int fixed_parms = 0, float_parms = 0, parm_info = 0;
29236 int optional_tbtab;
29237 rs6000_stack_t *info = rs6000_stack_info ();
29239 if (rs6000_traceback == traceback_full)
29240 optional_tbtab = 1;
29241 else if (rs6000_traceback == traceback_part)
29242 optional_tbtab = 0;
29244 optional_tbtab = !optimize_size && !TARGET_ELF;
29246 if (optional_tbtab)
29248 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
29249 while (*fname == '.') /* V.4 encodes . in the name */
29252 /* Need label immediately before tbtab, so we can compute
29253 its offset from the function start. */
29254 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
29255 ASM_OUTPUT_LABEL (file, fname);
29258 /* The .tbtab pseudo-op can only be used for the first eight
29259 expressions, since it can't handle the possibly variable
29260 length fields that follow. However, if you omit the optional
29261 fields, the assembler outputs zeros for all optional fields
29262 anyways, giving each variable length field is minimum length
29263 (as defined in sys/debug.h). Thus we can not use the .tbtab
29264 pseudo-op at all. */
29266 /* An all-zero word flags the start of the tbtab, for debuggers
29267 that have to find it by searching forward from the entry
29268 point or from the current pc. */
29269 fputs ("\t.long 0\n", file);
29271 /* Tbtab format type. Use format type 0. */
29272 fputs ("\t.byte 0,", file);
29274 /* Language type. Unfortunately, there does not seem to be any
29275 official way to discover the language being compiled, so we
29276 use language_string.
29277 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
29278 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
29279 a number, so for now use 9. LTO, Go and JIT aren't assigned numbers
29280 either, so for now use 0. */
29282 || ! strcmp (language_string, "GNU GIMPLE")
29283 || ! strcmp (language_string, "GNU Go")
29284 || ! strcmp (language_string, "libgccjit"))
29286 else if (! strcmp (language_string, "GNU F77")
29287 || lang_GNU_Fortran ())
29289 else if (! strcmp (language_string, "GNU Pascal"))
29291 else if (! strcmp (language_string, "GNU Ada"))
29293 else if (lang_GNU_CXX ()
29294 || ! strcmp (language_string, "GNU Objective-C++"))
29296 else if (! strcmp (language_string, "GNU Java"))
29298 else if (! strcmp (language_string, "GNU Objective-C"))
29301 gcc_unreachable ();
29302 fprintf (file, "%d,", i);
29304 /* 8 single bit fields: global linkage (not set for C extern linkage,
29305 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
29306 from start of procedure stored in tbtab, internal function, function
29307 has controlled storage, function has no toc, function uses fp,
29308 function logs/aborts fp operations. */
29309 /* Assume that fp operations are used if any fp reg must be saved. */
29310 fprintf (file, "%d,",
29311 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
29313 /* 6 bitfields: function is interrupt handler, name present in
29314 proc table, function calls alloca, on condition directives
29315 (controls stack walks, 3 bits), saves condition reg, saves
29317 /* The `function calls alloca' bit seems to be set whenever reg 31 is
29318 set up as a frame pointer, even when there is no alloca call. */
29319 fprintf (file, "%d,",
29320 ((optional_tbtab << 6)
29321 | ((optional_tbtab & frame_pointer_needed) << 5)
29322 | (info->cr_save_p << 1)
29323 | (info->lr_save_p)));
29325 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
29327 fprintf (file, "%d,",
29328 (info->push_p << 7) | (64 - info->first_fp_reg_save));
29330 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
29331 fprintf (file, "%d,", (32 - first_reg_to_save ()));
29333 if (optional_tbtab)
29335 /* Compute the parameter info from the function decl argument
29338 int next_parm_info_bit = 31;
29340 for (decl = DECL_ARGUMENTS (current_function_decl);
29341 decl; decl = DECL_CHAIN (decl))
29343 rtx parameter = DECL_INCOMING_RTL (decl);
29344 machine_mode mode = GET_MODE (parameter);
29346 if (GET_CODE (parameter) == REG)
29348 if (SCALAR_FLOAT_MODE_P (mode))
29371 gcc_unreachable ();
29374 /* If only one bit will fit, don't or in this entry. */
29375 if (next_parm_info_bit > 0)
29376 parm_info |= (bits << (next_parm_info_bit - 1));
29377 next_parm_info_bit -= 2;
29381 fixed_parms += ((GET_MODE_SIZE (mode)
29382 + (UNITS_PER_WORD - 1))
29384 next_parm_info_bit -= 1;
29390 /* Number of fixed point parameters. */
29391 /* This is actually the number of words of fixed point parameters; thus
29392 an 8 byte struct counts as 2; and thus the maximum value is 8. */
29393 fprintf (file, "%d,", fixed_parms);
29395 /* 2 bitfields: number of floating point parameters (7 bits), parameters
29397 /* This is actually the number of fp registers that hold parameters;
29398 and thus the maximum value is 13. */
29399 /* Set parameters on stack bit if parameters are not in their original
29400 registers, regardless of whether they are on the stack? Xlc
29401 seems to set the bit when not optimizing. */
29402 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
29404 if (optional_tbtab)
29406 /* Optional fields follow. Some are variable length. */
29408 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
29409 float, 11 double float. */
29410 /* There is an entry for each parameter in a register, in the order
29411 that they occur in the parameter list. Any intervening arguments
29412 on the stack are ignored. If the list overflows a long (max
29413 possible length 34 bits) then completely leave off all elements
29415 /* Only emit this long if there was at least one parameter. */
29416 if (fixed_parms || float_parms)
29417 fprintf (file, "\t.long %d\n", parm_info);
29419 /* Offset from start of code to tb table. */
29420 fputs ("\t.long ", file);
29421 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
29422 RS6000_OUTPUT_BASENAME (file, fname);
29424 rs6000_output_function_entry (file, fname);
29427 /* Interrupt handler mask. */
29428 /* Omit this long, since we never set the interrupt handler bit
29431 /* Number of CTL (controlled storage) anchors. */
29432 /* Omit this long, since the has_ctl bit is never set above. */
29434 /* Displacement into stack of each CTL anchor. */
29435 /* Omit this list of longs, because there are no CTL anchors. */
29437 /* Length of function name. */
29440 fprintf (file, "\t.short %d\n", (int) strlen (fname));
29442 /* Function name. */
29443 assemble_string (fname, strlen (fname));
29445 /* Register for alloca automatic storage; this is always reg 31.
29446 Only emit this if the alloca bit was set above. */
29447 if (frame_pointer_needed)
29448 fputs ("\t.byte 31\n", file);
29450 fputs ("\t.align 2\n", file);
29454 /* Arrange to define .LCTOC1 label, if not already done. */
29458 if (!toc_initialized)
29460 switch_to_section (toc_section);
29461 switch_to_section (current_function_section ());
29466 /* -fsplit-stack support. */
29468 /* A SYMBOL_REF for __morestack. */
29469 static GTY(()) rtx morestack_ref;
29472 gen_add3_const (rtx rt, rtx ra, long c)
29475 return gen_adddi3 (rt, ra, GEN_INT (c));
29477 return gen_addsi3 (rt, ra, GEN_INT (c));
29480 /* Emit -fsplit-stack prologue, which goes before the regular function
29481 prologue (at local entry point in the case of ELFv2). */
29484 rs6000_expand_split_stack_prologue (void)
29486 rs6000_stack_t *info = rs6000_stack_info ();
29487 unsigned HOST_WIDE_INT allocate;
29488 long alloc_hi, alloc_lo;
29489 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
29492 gcc_assert (flag_split_stack && reload_completed);
29497 if (global_regs[29])
29499 error ("%qs uses register r29", "-fsplit-stack");
29500 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
29501 "conflicts with %qD", global_regs_decl[29]);
29504 allocate = info->total_size;
29505 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
29507 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
29510 if (morestack_ref == NULL_RTX)
29512 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
29513 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
29514 | SYMBOL_FLAG_FUNCTION);
29517 r0 = gen_rtx_REG (Pmode, 0);
29518 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29519 r12 = gen_rtx_REG (Pmode, 12);
29520 emit_insn (gen_load_split_stack_limit (r0));
29521 /* Always emit two insns here to calculate the requested stack,
29522 so that the linker can edit them when adjusting size for calling
29523 non-split-stack code. */
29524 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
29525 alloc_lo = -allocate - alloc_hi;
29528 emit_insn (gen_add3_const (r12, r1, alloc_hi));
29530 emit_insn (gen_add3_const (r12, r12, alloc_lo));
29532 emit_insn (gen_nop ());
29536 emit_insn (gen_add3_const (r12, r1, alloc_lo));
29537 emit_insn (gen_nop ());
29540 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
29541 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
29542 ok_label = gen_label_rtx ();
29543 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29544 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
29545 gen_rtx_LABEL_REF (VOIDmode, ok_label),
29547 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29548 JUMP_LABEL (insn) = ok_label;
29549 /* Mark the jump as very likely to be taken. */
29550 add_reg_br_prob_note (insn, profile_probability::very_likely ());
29552 lr = gen_rtx_REG (Pmode, LR_REGNO);
29553 insn = emit_move_insn (r0, lr);
29554 RTX_FRAME_RELATED_P (insn) = 1;
29555 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
29556 RTX_FRAME_RELATED_P (insn) = 1;
29558 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
29559 const0_rtx, const0_rtx));
29560 call_fusage = NULL_RTX;
29561 use_reg (&call_fusage, r12);
29562 /* Say the call uses r0, even though it doesn't, to stop regrename
29563 from twiddling with the insns saving lr, trashing args for cfun.
29564 The insns restoring lr are similarly protected by making
29565 split_stack_return use r0. */
29566 use_reg (&call_fusage, r0);
29567 add_function_usage_to (insn, call_fusage);
29568 /* Indicate that this function can't jump to non-local gotos. */
29569 make_reg_eh_region_note_nothrow_nononlocal (insn);
29570 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
29571 insn = emit_move_insn (lr, r0);
29572 add_reg_note (insn, REG_CFA_RESTORE, lr);
29573 RTX_FRAME_RELATED_P (insn) = 1;
29574 emit_insn (gen_split_stack_return ());
29576 emit_label (ok_label);
29577 LABEL_NUSES (ok_label) = 1;
29580 /* Return the internal arg pointer used for function incoming
29581 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29582 to copy it to a pseudo in order for it to be preserved over calls
29583 and suchlike. We'd really like to use a pseudo here for the
29584 internal arg pointer but data-flow analysis is not prepared to
29585 accept pseudos as live at the beginning of a function. */
29588 rs6000_internal_arg_pointer (void)
29590 if (flag_split_stack
29591 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
29595 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
29599 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
29600 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
29602 /* Put the pseudo initialization right after the note at the
29603 beginning of the function. */
29604 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
29605 gen_rtx_REG (Pmode, 12));
29606 push_topmost_sequence ();
29607 emit_insn_after (pat, get_insns ());
29608 pop_topmost_sequence ();
29610 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
29611 FIRST_PARM_OFFSET (current_function_decl));
29612 return copy_to_reg (ret);
29614 return virtual_incoming_args_rtx;
29617 /* We may have to tell the dataflow pass that the split stack prologue
29618 is initializing a register. */
29621 rs6000_live_on_entry (bitmap regs)
29623 if (flag_split_stack)
29624 bitmap_set_bit (regs, 12);
29627 /* Emit -fsplit-stack dynamic stack allocation space check. */
29630 rs6000_split_stack_space_check (rtx size, rtx label)
29632 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29633 rtx limit = gen_reg_rtx (Pmode);
29634 rtx requested = gen_reg_rtx (Pmode);
29635 rtx cmp = gen_reg_rtx (CCUNSmode);
29638 emit_insn (gen_load_split_stack_limit (limit));
29639 if (CONST_INT_P (size))
29640 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
29643 size = force_reg (Pmode, size);
29644 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
29646 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
29647 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29648 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
29649 gen_rtx_LABEL_REF (VOIDmode, label),
29651 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29652 JUMP_LABEL (jump) = label;
29655 /* A C compound statement that outputs the assembler code for a thunk
29656 function, used to implement C++ virtual function calls with
29657 multiple inheritance. The thunk acts as a wrapper around a virtual
29658 function, adjusting the implicit object parameter before handing
29659 control off to the real function.
29661 First, emit code to add the integer DELTA to the location that
29662 contains the incoming first argument. Assume that this argument
29663 contains a pointer, and is the one used to pass the `this' pointer
29664 in C++. This is the incoming argument *before* the function
29665 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29666 values of all other incoming arguments.
29668 After the addition, emit code to jump to FUNCTION, which is a
29669 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29670 not touch the return address. Hence returning from FUNCTION will
29671 return to whoever called the current `thunk'.
29673 The effect must be as if FUNCTION had been called directly with the
29674 adjusted first argument. This macro is responsible for emitting
29675 all of the code for a thunk function; output_function_prologue()
29676 and output_function_epilogue() are not invoked.
29678 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29679 been extracted from it.) It might possibly be useful on some
29680 targets, but probably not.
29682 If you do not define this macro, the target-independent code in the
29683 C++ frontend will generate a less efficient heavyweight thunk that
29684 calls FUNCTION instead of jumping to it. The generic approach does
29685 not support varargs. */
29688 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
29689 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
29692 rtx this_rtx, funexp;
29695 reload_completed = 1;
29696 epilogue_completed = 1;
29698 /* Mark the end of the (empty) prologue. */
29699 emit_note (NOTE_INSN_PROLOGUE_END);
29701 /* Find the "this" pointer. If the function returns a structure,
29702 the structure return pointer is in r3. */
29703 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
29704 this_rtx = gen_rtx_REG (Pmode, 4);
29706 this_rtx = gen_rtx_REG (Pmode, 3);
29708 /* Apply the constant offset, if required. */
29710 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
29712 /* Apply the offset from the vtable, if required. */
29715 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
29716 rtx tmp = gen_rtx_REG (Pmode, 12);
29718 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
29719 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
29721 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
29722 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
29726 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
29728 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
29730 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
29733 /* Generate a tail call to the target function. */
29734 if (!TREE_USED (function))
29736 assemble_external (function);
29737 TREE_USED (function) = 1;
29739 funexp = XEXP (DECL_RTL (function), 0);
29740 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
29743 if (MACHOPIC_INDIRECT)
29744 funexp = machopic_indirect_call_target (funexp);
29747 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29748 generate sibcall RTL explicitly. */
29749 insn = emit_call_insn (
29750 gen_rtx_PARALLEL (VOIDmode,
29752 gen_rtx_CALL (VOIDmode,
29753 funexp, const0_rtx),
29754 gen_rtx_USE (VOIDmode, const0_rtx),
29755 simple_return_rtx)));
29756 SIBLING_CALL_P (insn) = 1;
29759 /* Run just enough of rest_of_compilation to get the insns emitted.
29760 There's not really enough bulk here to make other passes such as
29761 instruction scheduling worth while. Note that use_thunk calls
29762 assemble_start_function and assemble_end_function. */
29763 insn = get_insns ();
29764 shorten_branches (insn);
29765 final_start_function (insn, file, 1);
29766 final (insn, file, 1);
29767 final_end_function ();
29769 reload_completed = 0;
29770 epilogue_completed = 0;
29773 /* A quick summary of the various types of 'constant-pool tables'
29776 Target Flags Name One table per
29777 AIX (none) AIX TOC object file
29778 AIX -mfull-toc AIX TOC object file
29779 AIX -mminimal-toc AIX minimal TOC translation unit
29780 SVR4/EABI (none) SVR4 SDATA object file
29781 SVR4/EABI -fpic SVR4 pic object file
29782 SVR4/EABI -fPIC SVR4 PIC translation unit
29783 SVR4/EABI -mrelocatable EABI TOC function
29784 SVR4/EABI -maix AIX TOC object file
29785 SVR4/EABI -maix -mminimal-toc
29786 AIX minimal TOC translation unit
29788 Name Reg. Set by entries contains:
29789 made by addrs? fp? sum?
29791 AIX TOC 2 crt0 as Y option option
29792 AIX minimal TOC 30 prolog gcc Y Y option
29793 SVR4 SDATA 13 crt0 gcc N Y N
29794 SVR4 pic 30 prolog ld Y not yet N
29795 SVR4 PIC 30 prolog gcc Y option option
29796 EABI TOC 30 prolog gcc Y option option
29800 /* Hash functions for the hash table. */
29803 rs6000_hash_constant (rtx k)
29805 enum rtx_code code = GET_CODE (k);
29806 machine_mode mode = GET_MODE (k);
29807 unsigned result = (code << 3) ^ mode;
29808 const char *format;
29811 format = GET_RTX_FORMAT (code);
29812 flen = strlen (format);
29818 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29820 case CONST_WIDE_INT:
29823 flen = CONST_WIDE_INT_NUNITS (k);
29824 for (i = 0; i < flen; i++)
29825 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29830 if (mode != VOIDmode)
29831 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29843 for (; fidx < flen; fidx++)
29844 switch (format[fidx])
29849 const char *str = XSTR (k, fidx);
29850 len = strlen (str);
29851 result = result * 613 + len;
29852 for (i = 0; i < len; i++)
29853 result = result * 613 + (unsigned) str[i];
29858 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29862 result = result * 613 + (unsigned) XINT (k, fidx);
29865 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29866 result = result * 613 + (unsigned) XWINT (k, fidx);
29870 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29871 result = result * 613 + (unsigned) (XWINT (k, fidx)
29878 gcc_unreachable ();
29885 toc_hasher::hash (toc_hash_struct *thc)
29887 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29890 /* Compare H1 and H2 for equivalence. */
29893 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29898 if (h1->key_mode != h2->key_mode)
29901 return rtx_equal_p (r1, r2);
29904 /* These are the names given by the C++ front-end to vtables, and
29905 vtable-like objects. Ideally, this logic should not be here;
29906 instead, there should be some programmatic way of inquiring as
29907 to whether or not an object is a vtable. */
29909 #define VTABLE_NAME_P(NAME) \
29910 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29911 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29912 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29913 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29914 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29916 #ifdef NO_DOLLAR_IN_LABEL
29917 /* Return a GGC-allocated character string translating dollar signs in
29918 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29921 rs6000_xcoff_strip_dollar (const char *name)
29927 q = (const char *) strchr (name, '$');
29929 if (q == 0 || q == name)
29932 len = strlen (name);
29933 strip = XALLOCAVEC (char, len + 1);
29934 strcpy (strip, name);
29935 p = strip + (q - name);
29939 p = strchr (p + 1, '$');
29942 return ggc_alloc_string (strip, len);
29947 rs6000_output_symbol_ref (FILE *file, rtx x)
29949 const char *name = XSTR (x, 0);
29951 /* Currently C++ toc references to vtables can be emitted before it
29952 is decided whether the vtable is public or private. If this is
29953 the case, then the linker will eventually complain that there is
29954 a reference to an unknown section. Thus, for vtables only,
29955 we emit the TOC reference to reference the identifier and not the
29957 if (VTABLE_NAME_P (name))
29959 RS6000_OUTPUT_BASENAME (file, name);
29962 assemble_name (file, name);
29965 /* Output a TOC entry. We derive the entry name from what is being
29969 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
29972 const char *name = buf;
29974 HOST_WIDE_INT offset = 0;
29976 gcc_assert (!TARGET_NO_TOC);
29978 /* When the linker won't eliminate them, don't output duplicate
29979 TOC entries (this happens on AIX if there is any kind of TOC,
29980 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29982 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
29984 struct toc_hash_struct *h;
29986 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29987 time because GGC is not initialized at that point. */
29988 if (toc_hash_table == NULL)
29989 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
29991 h = ggc_alloc<toc_hash_struct> ();
29993 h->key_mode = mode;
29994 h->labelno = labelno;
29996 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
29997 if (*found == NULL)
29999 else /* This is indeed a duplicate.
30000 Set this label equal to that label. */
30002 fputs ("\t.set ", file);
30003 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
30004 fprintf (file, "%d,", labelno);
30005 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
30006 fprintf (file, "%d\n", ((*found)->labelno));
30009 if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF
30010 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
30011 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
30013 fputs ("\t.set ", file);
30014 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
30015 fprintf (file, "%d,", labelno);
30016 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
30017 fprintf (file, "%d\n", ((*found)->labelno));
30024 /* If we're going to put a double constant in the TOC, make sure it's
30025 aligned properly when strict alignment is on. */
30026 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
30027 && STRICT_ALIGNMENT
30028 && GET_MODE_BITSIZE (mode) >= 64
30029 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
30030 ASM_OUTPUT_ALIGN (file, 3);
30033 (*targetm.asm_out.internal_label) (file, "LC", labelno);
30035 /* Handle FP constants specially. Note that if we have a minimal
30036 TOC, things we put here aren't actually in the TOC, so we can allow
30038 if (GET_CODE (x) == CONST_DOUBLE &&
30039 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
30040 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
30044 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30045 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
30047 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
30051 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30052 fputs (DOUBLE_INT_ASM_OP, file);
30054 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
30055 k[0] & 0xffffffff, k[1] & 0xffffffff,
30056 k[2] & 0xffffffff, k[3] & 0xffffffff);
30057 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
30058 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
30059 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
30060 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
30061 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
30066 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30067 fputs ("\t.long ", file);
30069 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
30070 k[0] & 0xffffffff, k[1] & 0xffffffff,
30071 k[2] & 0xffffffff, k[3] & 0xffffffff);
30072 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
30073 k[0] & 0xffffffff, k[1] & 0xffffffff,
30074 k[2] & 0xffffffff, k[3] & 0xffffffff);
30078 else if (GET_CODE (x) == CONST_DOUBLE &&
30079 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
30083 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30084 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
30086 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
30090 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30091 fputs (DOUBLE_INT_ASM_OP, file);
30093 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
30094 k[0] & 0xffffffff, k[1] & 0xffffffff);
30095 fprintf (file, "0x%lx%08lx\n",
30096 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
30097 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
30102 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30103 fputs ("\t.long ", file);
30105 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
30106 k[0] & 0xffffffff, k[1] & 0xffffffff);
30107 fprintf (file, "0x%lx,0x%lx\n",
30108 k[0] & 0xffffffff, k[1] & 0xffffffff);
30112 else if (GET_CODE (x) == CONST_DOUBLE &&
30113 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
30117 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30118 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
30120 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
30124 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30125 fputs (DOUBLE_INT_ASM_OP, file);
30127 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
30128 if (WORDS_BIG_ENDIAN)
30129 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
30131 fprintf (file, "0x%lx\n", l & 0xffffffff);
30136 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30137 fputs ("\t.long ", file);
30139 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
30140 fprintf (file, "0x%lx\n", l & 0xffffffff);
30144 else if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT)
30146 unsigned HOST_WIDE_INT low;
30147 HOST_WIDE_INT high;
30149 low = INTVAL (x) & 0xffffffff;
30150 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
30152 /* TOC entries are always Pmode-sized, so when big-endian
30153 smaller integer constants in the TOC need to be padded.
30154 (This is still a win over putting the constants in
30155 a separate constant pool, because then we'd have
30156 to have both a TOC entry _and_ the actual constant.)
30158 For a 32-bit target, CONST_INT values are loaded and shifted
30159 entirely within `low' and can be stored in one TOC entry. */
30161 /* It would be easy to make this work, but it doesn't now. */
30162 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
30164 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
30167 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
30168 high = (HOST_WIDE_INT) low >> 32;
30174 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30175 fputs (DOUBLE_INT_ASM_OP, file);
30177 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
30178 (long) high & 0xffffffff, (long) low & 0xffffffff);
30179 fprintf (file, "0x%lx%08lx\n",
30180 (long) high & 0xffffffff, (long) low & 0xffffffff);
30185 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
30187 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30188 fputs ("\t.long ", file);
30190 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
30191 (long) high & 0xffffffff, (long) low & 0xffffffff);
30192 fprintf (file, "0x%lx,0x%lx\n",
30193 (long) high & 0xffffffff, (long) low & 0xffffffff);
30197 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30198 fputs ("\t.long ", file);
30200 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
30201 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
30207 if (GET_CODE (x) == CONST)
30209 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
30210 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
30212 base = XEXP (XEXP (x, 0), 0);
30213 offset = INTVAL (XEXP (XEXP (x, 0), 1));
30216 switch (GET_CODE (base))
30219 name = XSTR (base, 0);
30223 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
30224 CODE_LABEL_NUMBER (XEXP (base, 0)));
30228 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
30232 gcc_unreachable ();
30235 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30236 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
30239 fputs ("\t.tc ", file);
30240 RS6000_OUTPUT_BASENAME (file, name);
30243 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
30245 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
30247 /* Mark large TOC symbols on AIX with [TE] so they are mapped
30248 after other TOC symbols, reducing overflow of small TOC access
30249 to [TC] symbols. */
30250 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
30251 ? "[TE]," : "[TC],", file);
30254 /* Currently C++ toc references to vtables can be emitted before it
30255 is decided whether the vtable is public or private. If this is
30256 the case, then the linker will eventually complain that there is
30257 a TOC reference to an unknown section. Thus, for vtables only,
30258 we emit the TOC reference to reference the symbol and not the
30260 if (VTABLE_NAME_P (name))
30262 RS6000_OUTPUT_BASENAME (file, name);
30264 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
30265 else if (offset > 0)
30266 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
30269 output_addr_const (file, x);
30272 if (TARGET_XCOFF && GET_CODE (base) == SYMBOL_REF)
30274 switch (SYMBOL_REF_TLS_MODEL (base))
30278 case TLS_MODEL_LOCAL_EXEC:
30279 fputs ("@le", file);
30281 case TLS_MODEL_INITIAL_EXEC:
30282 fputs ("@ie", file);
30284 /* Use global-dynamic for local-dynamic. */
30285 case TLS_MODEL_GLOBAL_DYNAMIC:
30286 case TLS_MODEL_LOCAL_DYNAMIC:
30288 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
30289 fputs ("\t.tc .", file);
30290 RS6000_OUTPUT_BASENAME (file, name);
30291 fputs ("[TC],", file);
30292 output_addr_const (file, x);
30293 fputs ("@m", file);
30296 gcc_unreachable ();
30304 /* Output an assembler pseudo-op to write an ASCII string of N characters
30305 starting at P to FILE.
30307 On the RS/6000, we have to do this using the .byte operation and
30308 write out special characters outside the quoted string.
30309 Also, the assembler is broken; very long strings are truncated,
30310 so we must artificially break them up early. */
30313 output_ascii (FILE *file, const char *p, int n)
30316 int i, count_string;
30317 const char *for_string = "\t.byte \"";
30318 const char *for_decimal = "\t.byte ";
30319 const char *to_close = NULL;
30322 for (i = 0; i < n; i++)
30325 if (c >= ' ' && c < 0177)
30328 fputs (for_string, file);
30331 /* Write two quotes to get one. */
30339 for_decimal = "\"\n\t.byte ";
30343 if (count_string >= 512)
30345 fputs (to_close, file);
30347 for_string = "\t.byte \"";
30348 for_decimal = "\t.byte ";
30356 fputs (for_decimal, file);
30357 fprintf (file, "%d", c);
30359 for_string = "\n\t.byte \"";
30360 for_decimal = ", ";
30366 /* Now close the string if we have written one. Then end the line. */
30368 fputs (to_close, file);
30371 /* Generate a unique section name for FILENAME for a section type
30372 represented by SECTION_DESC. Output goes into BUF.
30374 SECTION_DESC can be any string, as long as it is different for each
30375 possible section type.
30377 We name the section in the same manner as xlc. The name begins with an
30378 underscore followed by the filename (after stripping any leading directory
30379 names) with the last period replaced by the string SECTION_DESC. If
30380 FILENAME does not contain a period, SECTION_DESC is appended to the end of
30384 rs6000_gen_section_name (char **buf, const char *filename,
30385 const char *section_desc)
30387 const char *q, *after_last_slash, *last_period = 0;
30391 after_last_slash = filename;
30392 for (q = filename; *q; q++)
30395 after_last_slash = q + 1;
30396 else if (*q == '.')
30400 len = strlen (after_last_slash) + strlen (section_desc) + 2;
30401 *buf = (char *) xmalloc (len);
30406 for (q = after_last_slash; *q; q++)
30408 if (q == last_period)
30410 strcpy (p, section_desc);
30411 p += strlen (section_desc);
30415 else if (ISALNUM (*q))
30419 if (last_period == 0)
30420 strcpy (p, section_desc);
30425 /* Emit profile function. */
30428 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
30430 /* Non-standard profiling for kernels, which just saves LR then calls
30431 _mcount without worrying about arg saves. The idea is to change
30432 the function prologue as little as possible as it isn't easy to
30433 account for arg save/restore code added just for _mcount. */
30434 if (TARGET_PROFILE_KERNEL)
30437 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
30439 #ifndef NO_PROFILE_COUNTERS
30440 # define NO_PROFILE_COUNTERS 0
30442 if (NO_PROFILE_COUNTERS)
30443 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
30444 LCT_NORMAL, VOIDmode);
30448 const char *label_name;
30451 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30452 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
30453 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
30455 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
30456 LCT_NORMAL, VOIDmode, fun, Pmode);
30459 else if (DEFAULT_ABI == ABI_DARWIN)
30461 const char *mcount_name = RS6000_MCOUNT;
30462 int caller_addr_regno = LR_REGNO;
30464 /* Be conservative and always set this, at least for now. */
30465 crtl->uses_pic_offset_table = 1;
30468 /* For PIC code, set up a stub and collect the caller's address
30469 from r0, which is where the prologue puts it. */
30470 if (MACHOPIC_INDIRECT
30471 && crtl->uses_pic_offset_table)
30472 caller_addr_regno = 0;
30474 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
30475 LCT_NORMAL, VOIDmode,
30476 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
30480 /* Write function profiler code. */
30483 output_function_profiler (FILE *file, int labelno)
30487 switch (DEFAULT_ABI)
30490 gcc_unreachable ();
30495 warning (0, "no profiling of 64-bit code for this ABI");
30498 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30499 fprintf (file, "\tmflr %s\n", reg_names[0]);
30500 if (NO_PROFILE_COUNTERS)
30502 asm_fprintf (file, "\tstw %s,4(%s)\n",
30503 reg_names[0], reg_names[1]);
30505 else if (TARGET_SECURE_PLT && flag_pic)
30507 if (TARGET_LINK_STACK)
30510 get_ppc476_thunk_name (name);
30511 asm_fprintf (file, "\tbl %s\n", name);
30514 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
30515 asm_fprintf (file, "\tstw %s,4(%s)\n",
30516 reg_names[0], reg_names[1]);
30517 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30518 asm_fprintf (file, "\taddis %s,%s,",
30519 reg_names[12], reg_names[12]);
30520 assemble_name (file, buf);
30521 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
30522 assemble_name (file, buf);
30523 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
30525 else if (flag_pic == 1)
30527 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
30528 asm_fprintf (file, "\tstw %s,4(%s)\n",
30529 reg_names[0], reg_names[1]);
30530 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30531 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
30532 assemble_name (file, buf);
30533 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
30535 else if (flag_pic > 1)
30537 asm_fprintf (file, "\tstw %s,4(%s)\n",
30538 reg_names[0], reg_names[1]);
30539 /* Now, we need to get the address of the label. */
30540 if (TARGET_LINK_STACK)
30543 get_ppc476_thunk_name (name);
30544 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
30545 assemble_name (file, buf);
30546 fputs ("-.\n1:", file);
30547 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30548 asm_fprintf (file, "\taddi %s,%s,4\n",
30549 reg_names[11], reg_names[11]);
30553 fputs ("\tbcl 20,31,1f\n\t.long ", file);
30554 assemble_name (file, buf);
30555 fputs ("-.\n1:", file);
30556 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30558 asm_fprintf (file, "\tlwz %s,0(%s)\n",
30559 reg_names[0], reg_names[11]);
30560 asm_fprintf (file, "\tadd %s,%s,%s\n",
30561 reg_names[0], reg_names[0], reg_names[11]);
30565 asm_fprintf (file, "\tlis %s,", reg_names[12]);
30566 assemble_name (file, buf);
30567 fputs ("@ha\n", file);
30568 asm_fprintf (file, "\tstw %s,4(%s)\n",
30569 reg_names[0], reg_names[1]);
30570 asm_fprintf (file, "\tla %s,", reg_names[0]);
30571 assemble_name (file, buf);
30572 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
30575 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30576 fprintf (file, "\tbl %s%s\n",
30577 RS6000_MCOUNT, flag_pic ? "@plt" : "");
30583 /* Don't do anything, done in output_profile_hook (). */
30590 /* The following variable value is the last issued insn. */
30592 static rtx_insn *last_scheduled_insn;
30594 /* The following variable helps to balance issuing of load and
30595 store instructions */
30597 static int load_store_pendulum;
30599 /* The following variable helps pair divide insns during scheduling. */
30600 static int divide_cnt;
30601 /* The following variable helps pair and alternate vector and vector load
30602 insns during scheduling. */
30603 static int vec_pairing;
30606 /* Power4 load update and store update instructions are cracked into a
30607 load or store and an integer insn which are executed in the same cycle.
30608 Branches have their own dispatch slot which does not count against the
30609 GCC issue rate, but it changes the program flow so there are no other
30610 instructions to issue in this cycle. */
30613 rs6000_variable_issue_1 (rtx_insn *insn, int more)
30615 last_scheduled_insn = insn;
30616 if (GET_CODE (PATTERN (insn)) == USE
30617 || GET_CODE (PATTERN (insn)) == CLOBBER)
30619 cached_can_issue_more = more;
30620 return cached_can_issue_more;
30623 if (insn_terminates_group_p (insn, current_group))
30625 cached_can_issue_more = 0;
30626 return cached_can_issue_more;
30629 /* If no reservation, but reach here */
30630 if (recog_memoized (insn) < 0)
30633 if (rs6000_sched_groups)
30635 if (is_microcoded_insn (insn))
30636 cached_can_issue_more = 0;
30637 else if (is_cracked_insn (insn))
30638 cached_can_issue_more = more > 2 ? more - 2 : 0;
30640 cached_can_issue_more = more - 1;
30642 return cached_can_issue_more;
30645 if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
30648 cached_can_issue_more = more - 1;
30649 return cached_can_issue_more;
30653 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
30655 int r = rs6000_variable_issue_1 (insn, more);
30657 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
30661 /* Adjust the cost of a scheduling dependency. Return the new cost of
30662 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30665 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
30668 enum attr_type attr_type;
30670 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
30677 /* Data dependency; DEP_INSN writes a register that INSN reads
30678 some cycles later. */
30680 /* Separate a load from a narrower, dependent store. */
30681 if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9)
30682 && GET_CODE (PATTERN (insn)) == SET
30683 && GET_CODE (PATTERN (dep_insn)) == SET
30684 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
30685 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
30686 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
30687 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
30690 attr_type = get_attr_type (insn);
30695 /* Tell the first scheduling pass about the latency between
30696 a mtctr and bctr (and mtlr and br/blr). The first
30697 scheduling pass will not know about this latency since
30698 the mtctr instruction, which has the latency associated
30699 to it, will be generated by reload. */
30702 /* Leave some extra cycles between a compare and its
30703 dependent branch, to inhibit expensive mispredicts. */
30704 if ((rs6000_tune == PROCESSOR_PPC603
30705 || rs6000_tune == PROCESSOR_PPC604
30706 || rs6000_tune == PROCESSOR_PPC604e
30707 || rs6000_tune == PROCESSOR_PPC620
30708 || rs6000_tune == PROCESSOR_PPC630
30709 || rs6000_tune == PROCESSOR_PPC750
30710 || rs6000_tune == PROCESSOR_PPC7400
30711 || rs6000_tune == PROCESSOR_PPC7450
30712 || rs6000_tune == PROCESSOR_PPCE5500
30713 || rs6000_tune == PROCESSOR_PPCE6500
30714 || rs6000_tune == PROCESSOR_POWER4
30715 || rs6000_tune == PROCESSOR_POWER5
30716 || rs6000_tune == PROCESSOR_POWER7
30717 || rs6000_tune == PROCESSOR_POWER8
30718 || rs6000_tune == PROCESSOR_POWER9
30719 || rs6000_tune == PROCESSOR_CELL)
30720 && recog_memoized (dep_insn)
30721 && (INSN_CODE (dep_insn) >= 0))
30723 switch (get_attr_type (dep_insn))
30726 case TYPE_FPCOMPARE:
30727 case TYPE_CR_LOGICAL:
30731 if (get_attr_dot (dep_insn) == DOT_YES)
30736 if (get_attr_dot (dep_insn) == DOT_YES
30737 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
30748 if ((rs6000_tune == PROCESSOR_POWER6)
30749 && recog_memoized (dep_insn)
30750 && (INSN_CODE (dep_insn) >= 0))
30753 if (GET_CODE (PATTERN (insn)) != SET)
30754 /* If this happens, we have to extend this to schedule
30755 optimally. Return default for now. */
30758 /* Adjust the cost for the case where the value written
30759 by a fixed point operation is used as the address
30760 gen value on a store. */
30761 switch (get_attr_type (dep_insn))
30766 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30767 return get_attr_sign_extend (dep_insn)
30768 == SIGN_EXTEND_YES ? 6 : 4;
30773 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30774 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30784 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30792 if (get_attr_update (dep_insn) == UPDATE_YES
30793 && ! rs6000_store_data_bypass_p (dep_insn, insn))
30799 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30805 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30806 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30816 if ((rs6000_tune == PROCESSOR_POWER6)
30817 && recog_memoized (dep_insn)
30818 && (INSN_CODE (dep_insn) >= 0))
30821 /* Adjust the cost for the case where the value written
30822 by a fixed point instruction is used within the address
30823 gen portion of a subsequent load(u)(x) */
30824 switch (get_attr_type (dep_insn))
30829 if (set_to_load_agen (dep_insn, insn))
30830 return get_attr_sign_extend (dep_insn)
30831 == SIGN_EXTEND_YES ? 6 : 4;
30836 if (set_to_load_agen (dep_insn, insn))
30837 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30847 if (set_to_load_agen (dep_insn, insn))
30855 if (get_attr_update (dep_insn) == UPDATE_YES
30856 && set_to_load_agen (dep_insn, insn))
30862 if (set_to_load_agen (dep_insn, insn))
30868 if (set_to_load_agen (dep_insn, insn))
30869 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30879 if ((rs6000_tune == PROCESSOR_POWER6)
30880 && get_attr_update (insn) == UPDATE_NO
30881 && recog_memoized (dep_insn)
30882 && (INSN_CODE (dep_insn) >= 0)
30883 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30890 /* Fall out to return default cost. */
30894 case REG_DEP_OUTPUT:
30895 /* Output dependency; DEP_INSN writes a register that INSN writes some
30897 if ((rs6000_tune == PROCESSOR_POWER6)
30898 && recog_memoized (dep_insn)
30899 && (INSN_CODE (dep_insn) >= 0))
30901 attr_type = get_attr_type (insn);
30906 case TYPE_FPSIMPLE:
30907 if (get_attr_type (dep_insn) == TYPE_FP
30908 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30912 if (get_attr_update (insn) == UPDATE_NO
30913 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30920 /* Fall through, no cost for output dependency. */
30924 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30929 gcc_unreachable ();
30935 /* Debug version of rs6000_adjust_cost. */
30938 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30939 int cost, unsigned int dw)
30941 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30949 default: dep = "unknown depencency"; break;
30950 case REG_DEP_TRUE: dep = "data dependency"; break;
30951 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30952 case REG_DEP_ANTI: dep = "anti depencency"; break;
30956 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30957 "%s, insn:\n", ret, cost, dep);
30965 /* The function returns a true if INSN is microcoded.
30966 Return false otherwise. */
30969 is_microcoded_insn (rtx_insn *insn)
30971 if (!insn || !NONDEBUG_INSN_P (insn)
30972 || GET_CODE (PATTERN (insn)) == USE
30973 || GET_CODE (PATTERN (insn)) == CLOBBER)
30976 if (rs6000_tune == PROCESSOR_CELL)
30977 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
30979 if (rs6000_sched_groups
30980 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30982 enum attr_type type = get_attr_type (insn);
30983 if ((type == TYPE_LOAD
30984 && get_attr_update (insn) == UPDATE_YES
30985 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
30986 || ((type == TYPE_LOAD || type == TYPE_STORE)
30987 && get_attr_update (insn) == UPDATE_YES
30988 && get_attr_indexed (insn) == INDEXED_YES)
30989 || type == TYPE_MFCR)
30996 /* The function returns true if INSN is cracked into 2 instructions
30997 by the processor (and therefore occupies 2 issue slots). */
31000 is_cracked_insn (rtx_insn *insn)
31002 if (!insn || !NONDEBUG_INSN_P (insn)
31003 || GET_CODE (PATTERN (insn)) == USE
31004 || GET_CODE (PATTERN (insn)) == CLOBBER)
31007 if (rs6000_sched_groups
31008 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
31010 enum attr_type type = get_attr_type (insn);
31011 if ((type == TYPE_LOAD
31012 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31013 && get_attr_update (insn) == UPDATE_NO)
31014 || (type == TYPE_LOAD
31015 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
31016 && get_attr_update (insn) == UPDATE_YES
31017 && get_attr_indexed (insn) == INDEXED_NO)
31018 || (type == TYPE_STORE
31019 && get_attr_update (insn) == UPDATE_YES
31020 && get_attr_indexed (insn) == INDEXED_NO)
31021 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
31022 && get_attr_update (insn) == UPDATE_YES)
31023 || (type == TYPE_CR_LOGICAL
31024 && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
31025 || (type == TYPE_EXTS
31026 && get_attr_dot (insn) == DOT_YES)
31027 || (type == TYPE_SHIFT
31028 && get_attr_dot (insn) == DOT_YES
31029 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
31030 || (type == TYPE_MUL
31031 && get_attr_dot (insn) == DOT_YES)
31032 || type == TYPE_DIV
31033 || (type == TYPE_INSERT
31034 && get_attr_size (insn) == SIZE_32))
31041 /* The function returns true if INSN can be issued only from
31042 the branch slot. */
31045 is_branch_slot_insn (rtx_insn *insn)
31047 if (!insn || !NONDEBUG_INSN_P (insn)
31048 || GET_CODE (PATTERN (insn)) == USE
31049 || GET_CODE (PATTERN (insn)) == CLOBBER)
31052 if (rs6000_sched_groups)
31054 enum attr_type type = get_attr_type (insn);
31055 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
31063 /* The function returns true if out_inst sets a value that is
31064 used in the address generation computation of in_insn */
31066 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
31068 rtx out_set, in_set;
31070 /* For performance reasons, only handle the simple case where
31071 both loads are a single_set. */
31072 out_set = single_set (out_insn);
31075 in_set = single_set (in_insn);
31077 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
31083 /* Try to determine base/offset/size parts of the given MEM.
31084 Return true if successful, false if all the values couldn't
31087 This function only looks for REG or REG+CONST address forms.
31088 REG+REG address form will return false. */
31091 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
31092 HOST_WIDE_INT *size)
31095 if MEM_SIZE_KNOWN_P (mem)
31096 *size = MEM_SIZE (mem);
31100 addr_rtx = (XEXP (mem, 0));
31101 if (GET_CODE (addr_rtx) == PRE_MODIFY)
31102 addr_rtx = XEXP (addr_rtx, 1);
31105 while (GET_CODE (addr_rtx) == PLUS
31106 && CONST_INT_P (XEXP (addr_rtx, 1)))
31108 *offset += INTVAL (XEXP (addr_rtx, 1));
31109 addr_rtx = XEXP (addr_rtx, 0);
31111 if (!REG_P (addr_rtx))
31118 /* The function returns true if the target storage location of
31119 mem1 is adjacent to the target storage location of mem2 */
31120 /* Return 1 if memory locations are adjacent. */
31123 adjacent_mem_locations (rtx mem1, rtx mem2)
31126 HOST_WIDE_INT off1, size1, off2, size2;
31128 if (get_memref_parts (mem1, ®1, &off1, &size1)
31129 && get_memref_parts (mem2, ®2, &off2, &size2))
31130 return ((REGNO (reg1) == REGNO (reg2))
31131 && ((off1 + size1 == off2)
31132 || (off2 + size2 == off1)));
31137 /* This function returns true if it can be determined that the two MEM
31138 locations overlap by at least 1 byte based on base reg/offset/size. */
31141 mem_locations_overlap (rtx mem1, rtx mem2)
31144 HOST_WIDE_INT off1, size1, off2, size2;
31146 if (get_memref_parts (mem1, ®1, &off1, &size1)
31147 && get_memref_parts (mem2, ®2, &off2, &size2))
31148 return ((REGNO (reg1) == REGNO (reg2))
31149 && (((off1 <= off2) && (off1 + size1 > off2))
31150 || ((off2 <= off1) && (off2 + size2 > off1))));
31155 /* A C statement (sans semicolon) to update the integer scheduling
31156 priority INSN_PRIORITY (INSN). Increase the priority to execute the
31157 INSN earlier, reduce the priority to execute INSN later. Do not
31158 define this macro if you do not need to adjust the scheduling
31159 priorities of insns. */
31162 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
31164 rtx load_mem, str_mem;
31165 /* On machines (like the 750) which have asymmetric integer units,
31166 where one integer unit can do multiply and divides and the other
31167 can't, reduce the priority of multiply/divide so it is scheduled
31168 before other integer operations. */
31171 if (! INSN_P (insn))
31174 if (GET_CODE (PATTERN (insn)) == USE)
31177 switch (rs6000_tune) {
31178 case PROCESSOR_PPC750:
31179 switch (get_attr_type (insn))
31186 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
31187 priority, priority);
31188 if (priority >= 0 && priority < 0x01000000)
31195 if (insn_must_be_first_in_group (insn)
31196 && reload_completed
31197 && current_sched_info->sched_max_insns_priority
31198 && rs6000_sched_restricted_insns_priority)
31201 /* Prioritize insns that can be dispatched only in the first
31203 if (rs6000_sched_restricted_insns_priority == 1)
31204 /* Attach highest priority to insn. This means that in
31205 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
31206 precede 'priority' (critical path) considerations. */
31207 return current_sched_info->sched_max_insns_priority;
31208 else if (rs6000_sched_restricted_insns_priority == 2)
31209 /* Increase priority of insn by a minimal amount. This means that in
31210 haifa-sched.c:ready_sort(), only 'priority' (critical path)
31211 considerations precede dispatch-slot restriction considerations. */
31212 return (priority + 1);
31215 if (rs6000_tune == PROCESSOR_POWER6
31216 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
31217 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
31218 /* Attach highest priority to insn if the scheduler has just issued two
31219 stores and this instruction is a load, or two loads and this instruction
31220 is a store. Power6 wants loads and stores scheduled alternately
31222 return current_sched_info->sched_max_insns_priority;
31227 /* Return true if the instruction is nonpipelined on the Cell. */
31229 is_nonpipeline_insn (rtx_insn *insn)
31231 enum attr_type type;
31232 if (!insn || !NONDEBUG_INSN_P (insn)
31233 || GET_CODE (PATTERN (insn)) == USE
31234 || GET_CODE (PATTERN (insn)) == CLOBBER)
31237 type = get_attr_type (insn);
31238 if (type == TYPE_MUL
31239 || type == TYPE_DIV
31240 || type == TYPE_SDIV
31241 || type == TYPE_DDIV
31242 || type == TYPE_SSQRT
31243 || type == TYPE_DSQRT
31244 || type == TYPE_MFCR
31245 || type == TYPE_MFCRF
31246 || type == TYPE_MFJMPR)
31254 /* Return how many instructions the machine can issue per cycle. */
31257 rs6000_issue_rate (void)
31259 /* Unless scheduling for register pressure, use issue rate of 1 for
31260 first scheduling pass to decrease degradation. */
31261 if (!reload_completed && !flag_sched_pressure)
31264 switch (rs6000_tune) {
31265 case PROCESSOR_RS64A:
31266 case PROCESSOR_PPC601: /* ? */
31267 case PROCESSOR_PPC7450:
31269 case PROCESSOR_PPC440:
31270 case PROCESSOR_PPC603:
31271 case PROCESSOR_PPC750:
31272 case PROCESSOR_PPC7400:
31273 case PROCESSOR_PPC8540:
31274 case PROCESSOR_PPC8548:
31275 case PROCESSOR_CELL:
31276 case PROCESSOR_PPCE300C2:
31277 case PROCESSOR_PPCE300C3:
31278 case PROCESSOR_PPCE500MC:
31279 case PROCESSOR_PPCE500MC64:
31280 case PROCESSOR_PPCE5500:
31281 case PROCESSOR_PPCE6500:
31282 case PROCESSOR_TITAN:
31284 case PROCESSOR_PPC476:
31285 case PROCESSOR_PPC604:
31286 case PROCESSOR_PPC604e:
31287 case PROCESSOR_PPC620:
31288 case PROCESSOR_PPC630:
31290 case PROCESSOR_POWER4:
31291 case PROCESSOR_POWER5:
31292 case PROCESSOR_POWER6:
31293 case PROCESSOR_POWER7:
31295 case PROCESSOR_POWER8:
31297 case PROCESSOR_POWER9:
31304 /* Return how many instructions to look ahead for better insn
31308 rs6000_use_sched_lookahead (void)
31310 switch (rs6000_tune)
31312 case PROCESSOR_PPC8540:
31313 case PROCESSOR_PPC8548:
31316 case PROCESSOR_CELL:
31317 return (reload_completed ? 8 : 0);
31324 /* We are choosing insn from the ready queue. Return zero if INSN can be
31327 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
31329 if (ready_index == 0)
31332 if (rs6000_tune != PROCESSOR_CELL)
31335 gcc_assert (insn != NULL_RTX && INSN_P (insn));
31337 if (!reload_completed
31338 || is_nonpipeline_insn (insn)
31339 || is_microcoded_insn (insn))
31345 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
31346 and return true. */
31349 find_mem_ref (rtx pat, rtx *mem_ref)
31354 /* stack_tie does not produce any real memory traffic. */
31355 if (tie_operand (pat, VOIDmode))
31358 if (GET_CODE (pat) == MEM)
31364 /* Recursively process the pattern. */
31365 fmt = GET_RTX_FORMAT (GET_CODE (pat));
31367 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
31371 if (find_mem_ref (XEXP (pat, i), mem_ref))
31374 else if (fmt[i] == 'E')
31375 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
31377 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
31385 /* Determine if PAT is a PATTERN of a load insn. */
31388 is_load_insn1 (rtx pat, rtx *load_mem)
31390 if (!pat || pat == NULL_RTX)
31393 if (GET_CODE (pat) == SET)
31394 return find_mem_ref (SET_SRC (pat), load_mem);
31396 if (GET_CODE (pat) == PARALLEL)
31400 for (i = 0; i < XVECLEN (pat, 0); i++)
31401 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
31408 /* Determine if INSN loads from memory. */
31411 is_load_insn (rtx insn, rtx *load_mem)
31413 if (!insn || !INSN_P (insn))
31419 return is_load_insn1 (PATTERN (insn), load_mem);
31422 /* Determine if PAT is a PATTERN of a store insn. */
31425 is_store_insn1 (rtx pat, rtx *str_mem)
31427 if (!pat || pat == NULL_RTX)
31430 if (GET_CODE (pat) == SET)
31431 return find_mem_ref (SET_DEST (pat), str_mem);
31433 if (GET_CODE (pat) == PARALLEL)
31437 for (i = 0; i < XVECLEN (pat, 0); i++)
31438 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
31445 /* Determine if INSN stores to memory. */
31448 is_store_insn (rtx insn, rtx *str_mem)
31450 if (!insn || !INSN_P (insn))
31453 return is_store_insn1 (PATTERN (insn), str_mem);
31456 /* Return whether TYPE is a Power9 pairable vector instruction type. */
31459 is_power9_pairable_vec_type (enum attr_type type)
31463 case TYPE_VECSIMPLE:
31464 case TYPE_VECCOMPLEX:
31468 case TYPE_VECFLOAT:
31470 case TYPE_VECDOUBLE:
31478 /* Returns whether the dependence between INSN and NEXT is considered
31479 costly by the given target. */
31482 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
31486 rtx load_mem, str_mem;
31488 /* If the flag is not enabled - no dependence is considered costly;
31489 allow all dependent insns in the same group.
31490 This is the most aggressive option. */
31491 if (rs6000_sched_costly_dep == no_dep_costly)
31494 /* If the flag is set to 1 - a dependence is always considered costly;
31495 do not allow dependent instructions in the same group.
31496 This is the most conservative option. */
31497 if (rs6000_sched_costly_dep == all_deps_costly)
31500 insn = DEP_PRO (dep);
31501 next = DEP_CON (dep);
31503 if (rs6000_sched_costly_dep == store_to_load_dep_costly
31504 && is_load_insn (next, &load_mem)
31505 && is_store_insn (insn, &str_mem))
31506 /* Prevent load after store in the same group. */
31509 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
31510 && is_load_insn (next, &load_mem)
31511 && is_store_insn (insn, &str_mem)
31512 && DEP_TYPE (dep) == REG_DEP_TRUE
31513 && mem_locations_overlap(str_mem, load_mem))
31514 /* Prevent load after store in the same group if it is a true
31518 /* The flag is set to X; dependences with latency >= X are considered costly,
31519 and will not be scheduled in the same group. */
31520 if (rs6000_sched_costly_dep <= max_dep_latency
31521 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
31527 /* Return the next insn after INSN that is found before TAIL is reached,
31528 skipping any "non-active" insns - insns that will not actually occupy
31529 an issue slot. Return NULL_RTX if such an insn is not found. */
31532 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
31534 if (insn == NULL_RTX || insn == tail)
31539 insn = NEXT_INSN (insn);
31540 if (insn == NULL_RTX || insn == tail)
31544 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
31545 || (NONJUMP_INSN_P (insn)
31546 && GET_CODE (PATTERN (insn)) != USE
31547 && GET_CODE (PATTERN (insn)) != CLOBBER
31548 && INSN_CODE (insn) != CODE_FOR_stack_tie))
31554 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31557 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
31562 enum attr_type type, type2;
31564 type = get_attr_type (last_scheduled_insn);
31566 /* Try to issue fixed point divides back-to-back in pairs so they will be
31567 routed to separate execution units and execute in parallel. */
31568 if (type == TYPE_DIV && divide_cnt == 0)
31570 /* First divide has been scheduled. */
31573 /* Scan the ready list looking for another divide, if found move it
31574 to the end of the list so it is chosen next. */
31578 if (recog_memoized (ready[pos]) >= 0
31579 && get_attr_type (ready[pos]) == TYPE_DIV)
31582 for (i = pos; i < lastpos; i++)
31583 ready[i] = ready[i + 1];
31584 ready[lastpos] = tmp;
31592 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31595 /* The best dispatch throughput for vector and vector load insns can be
31596 achieved by interleaving a vector and vector load such that they'll
31597 dispatch to the same superslice. If this pairing cannot be achieved
31598 then it is best to pair vector insns together and vector load insns
31601 To aid in this pairing, vec_pairing maintains the current state with
31602 the following values:
31604 0 : Initial state, no vecload/vector pairing has been started.
31606 1 : A vecload or vector insn has been issued and a candidate for
31607 pairing has been found and moved to the end of the ready
31609 if (type == TYPE_VECLOAD)
31611 /* Issued a vecload. */
31612 if (vec_pairing == 0)
31614 int vecload_pos = -1;
31615 /* We issued a single vecload, look for a vector insn to pair it
31616 with. If one isn't found, try to pair another vecload. */
31620 if (recog_memoized (ready[pos]) >= 0)
31622 type2 = get_attr_type (ready[pos]);
31623 if (is_power9_pairable_vec_type (type2))
31625 /* Found a vector insn to pair with, move it to the
31626 end of the ready list so it is scheduled next. */
31628 for (i = pos; i < lastpos; i++)
31629 ready[i] = ready[i + 1];
31630 ready[lastpos] = tmp;
31632 return cached_can_issue_more;
31634 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
31635 /* Remember position of first vecload seen. */
31640 if (vecload_pos >= 0)
31642 /* Didn't find a vector to pair with but did find a vecload,
31643 move it to the end of the ready list. */
31644 tmp = ready[vecload_pos];
31645 for (i = vecload_pos; i < lastpos; i++)
31646 ready[i] = ready[i + 1];
31647 ready[lastpos] = tmp;
31649 return cached_can_issue_more;
31653 else if (is_power9_pairable_vec_type (type))
31655 /* Issued a vector operation. */
31656 if (vec_pairing == 0)
31659 /* We issued a single vector insn, look for a vecload to pair it
31660 with. If one isn't found, try to pair another vector. */
31664 if (recog_memoized (ready[pos]) >= 0)
31666 type2 = get_attr_type (ready[pos]);
31667 if (type2 == TYPE_VECLOAD)
31669 /* Found a vecload insn to pair with, move it to the
31670 end of the ready list so it is scheduled next. */
31672 for (i = pos; i < lastpos; i++)
31673 ready[i] = ready[i + 1];
31674 ready[lastpos] = tmp;
31676 return cached_can_issue_more;
31678 else if (is_power9_pairable_vec_type (type2)
31680 /* Remember position of first vector insn seen. */
31687 /* Didn't find a vecload to pair with but did find a vector
31688 insn, move it to the end of the ready list. */
31689 tmp = ready[vec_pos];
31690 for (i = vec_pos; i < lastpos; i++)
31691 ready[i] = ready[i + 1];
31692 ready[lastpos] = tmp;
31694 return cached_can_issue_more;
31699 /* We've either finished a vec/vecload pair, couldn't find an insn to
31700 continue the current pair, or the last insn had nothing to do with
31701 with pairing. In any case, reset the state. */
31705 return cached_can_issue_more;
31708 /* We are about to begin issuing insns for this clock cycle. */
31711 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
31712 rtx_insn **ready ATTRIBUTE_UNUSED,
31713 int *pn_ready ATTRIBUTE_UNUSED,
31714 int clock_var ATTRIBUTE_UNUSED)
31716 int n_ready = *pn_ready;
31719 fprintf (dump, "// rs6000_sched_reorder :\n");
31721 /* Reorder the ready list, if the second to last ready insn
31722 is a nonepipeline insn. */
31723 if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
31725 if (is_nonpipeline_insn (ready[n_ready - 1])
31726 && (recog_memoized (ready[n_ready - 2]) > 0))
31727 /* Simply swap first two insns. */
31728 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
31731 if (rs6000_tune == PROCESSOR_POWER6)
31732 load_store_pendulum = 0;
31734 return rs6000_issue_rate ();
31737 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31740 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
31741 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
31744 fprintf (dump, "// rs6000_sched_reorder2 :\n");
31746 /* For Power6, we need to handle some special cases to try and keep the
31747 store queue from overflowing and triggering expensive flushes.
31749 This code monitors how load and store instructions are being issued
31750 and skews the ready list one way or the other to increase the likelihood
31751 that a desired instruction is issued at the proper time.
31753 A couple of things are done. First, we maintain a "load_store_pendulum"
31754 to track the current state of load/store issue.
31756 - If the pendulum is at zero, then no loads or stores have been
31757 issued in the current cycle so we do nothing.
31759 - If the pendulum is 1, then a single load has been issued in this
31760 cycle and we attempt to locate another load in the ready list to
31763 - If the pendulum is -2, then two stores have already been
31764 issued in this cycle, so we increase the priority of the first load
31765 in the ready list to increase it's likelihood of being chosen first
31768 - If the pendulum is -1, then a single store has been issued in this
31769 cycle and we attempt to locate another store in the ready list to
31770 issue with it, preferring a store to an adjacent memory location to
31771 facilitate store pairing in the store queue.
31773 - If the pendulum is 2, then two loads have already been
31774 issued in this cycle, so we increase the priority of the first store
31775 in the ready list to increase it's likelihood of being chosen first
31778 - If the pendulum < -2 or > 2, then do nothing.
31780 Note: This code covers the most common scenarios. There exist non
31781 load/store instructions which make use of the LSU and which
31782 would need to be accounted for to strictly model the behavior
31783 of the machine. Those instructions are currently unaccounted
31784 for to help minimize compile time overhead of this code.
31786 if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
31791 rtx load_mem, str_mem;
31793 if (is_store_insn (last_scheduled_insn, &str_mem))
31794 /* Issuing a store, swing the load_store_pendulum to the left */
31795 load_store_pendulum--;
31796 else if (is_load_insn (last_scheduled_insn, &load_mem))
31797 /* Issuing a load, swing the load_store_pendulum to the right */
31798 load_store_pendulum++;
31800 return cached_can_issue_more;
31802 /* If the pendulum is balanced, or there is only one instruction on
31803 the ready list, then all is well, so return. */
31804 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
31805 return cached_can_issue_more;
31807 if (load_store_pendulum == 1)
31809 /* A load has been issued in this cycle. Scan the ready list
31810 for another load to issue with it */
31815 if (is_load_insn (ready[pos], &load_mem))
31817 /* Found a load. Move it to the head of the ready list,
31818 and adjust it's priority so that it is more likely to
31821 for (i=pos; i<*pn_ready-1; i++)
31822 ready[i] = ready[i + 1];
31823 ready[*pn_ready-1] = tmp;
31825 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31826 INSN_PRIORITY (tmp)++;
31832 else if (load_store_pendulum == -2)
31834 /* Two stores have been issued in this cycle. Increase the
31835 priority of the first load in the ready list to favor it for
31836 issuing in the next cycle. */
31841 if (is_load_insn (ready[pos], &load_mem)
31843 && INSN_PRIORITY_KNOWN (ready[pos]))
31845 INSN_PRIORITY (ready[pos])++;
31847 /* Adjust the pendulum to account for the fact that a load
31848 was found and increased in priority. This is to prevent
31849 increasing the priority of multiple loads */
31850 load_store_pendulum--;
31857 else if (load_store_pendulum == -1)
31859 /* A store has been issued in this cycle. Scan the ready list for
31860 another store to issue with it, preferring a store to an adjacent
31862 int first_store_pos = -1;
31868 if (is_store_insn (ready[pos], &str_mem))
31871 /* Maintain the index of the first store found on the
31873 if (first_store_pos == -1)
31874 first_store_pos = pos;
31876 if (is_store_insn (last_scheduled_insn, &str_mem2)
31877 && adjacent_mem_locations (str_mem, str_mem2))
31879 /* Found an adjacent store. Move it to the head of the
31880 ready list, and adjust it's priority so that it is
31881 more likely to stay there */
31883 for (i=pos; i<*pn_ready-1; i++)
31884 ready[i] = ready[i + 1];
31885 ready[*pn_ready-1] = tmp;
31887 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31888 INSN_PRIORITY (tmp)++;
31890 first_store_pos = -1;
31898 if (first_store_pos >= 0)
31900 /* An adjacent store wasn't found, but a non-adjacent store was,
31901 so move the non-adjacent store to the front of the ready
31902 list, and adjust its priority so that it is more likely to
31904 tmp = ready[first_store_pos];
31905 for (i=first_store_pos; i<*pn_ready-1; i++)
31906 ready[i] = ready[i + 1];
31907 ready[*pn_ready-1] = tmp;
31908 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31909 INSN_PRIORITY (tmp)++;
31912 else if (load_store_pendulum == 2)
31914 /* Two loads have been issued in this cycle. Increase the priority
31915 of the first store in the ready list to favor it for issuing in
31921 if (is_store_insn (ready[pos], &str_mem)
31923 && INSN_PRIORITY_KNOWN (ready[pos]))
31925 INSN_PRIORITY (ready[pos])++;
31927 /* Adjust the pendulum to account for the fact that a store
31928 was found and increased in priority. This is to prevent
31929 increasing the priority of multiple stores */
31930 load_store_pendulum++;
31939 /* Do Power9 dependent reordering if necessary. */
31940 if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
31941 && recog_memoized (last_scheduled_insn) >= 0)
31942 return power9_sched_reorder2 (ready, *pn_ready - 1);
31944 return cached_can_issue_more;
31947 /* Return whether the presence of INSN causes a dispatch group termination
31948 of group WHICH_GROUP.
31950 If WHICH_GROUP == current_group, this function will return true if INSN
31951 causes the termination of the current group (i.e, the dispatch group to
31952 which INSN belongs). This means that INSN will be the last insn in the
31953 group it belongs to.
31955 If WHICH_GROUP == previous_group, this function will return true if INSN
31956 causes the termination of the previous group (i.e, the dispatch group that
31957 precedes the group to which INSN belongs). This means that INSN will be
31958 the first insn in the group it belongs to). */
31961 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31968 first = insn_must_be_first_in_group (insn);
31969 last = insn_must_be_last_in_group (insn);
31974 if (which_group == current_group)
31976 else if (which_group == previous_group)
31984 insn_must_be_first_in_group (rtx_insn *insn)
31986 enum attr_type type;
31990 || DEBUG_INSN_P (insn)
31991 || GET_CODE (PATTERN (insn)) == USE
31992 || GET_CODE (PATTERN (insn)) == CLOBBER)
31995 switch (rs6000_tune)
31997 case PROCESSOR_POWER5:
31998 if (is_cracked_insn (insn))
32001 case PROCESSOR_POWER4:
32002 if (is_microcoded_insn (insn))
32005 if (!rs6000_sched_groups)
32008 type = get_attr_type (insn);
32015 case TYPE_CR_LOGICAL:
32028 case PROCESSOR_POWER6:
32029 type = get_attr_type (insn);
32038 case TYPE_FPCOMPARE:
32049 if (get_attr_dot (insn) == DOT_NO
32050 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
32055 if (get_attr_size (insn) == SIZE_32)
32063 if (get_attr_update (insn) == UPDATE_YES)
32071 case PROCESSOR_POWER7:
32072 type = get_attr_type (insn);
32076 case TYPE_CR_LOGICAL:
32090 if (get_attr_dot (insn) == DOT_YES)
32095 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32096 || get_attr_update (insn) == UPDATE_YES)
32103 if (get_attr_update (insn) == UPDATE_YES)
32111 case PROCESSOR_POWER8:
32112 type = get_attr_type (insn);
32116 case TYPE_CR_LOGICAL:
32124 case TYPE_VECSTORE:
32131 if (get_attr_dot (insn) == DOT_YES)
32136 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32137 || get_attr_update (insn) == UPDATE_YES)
32142 if (get_attr_update (insn) == UPDATE_YES
32143 && get_attr_indexed (insn) == INDEXED_YES)
32159 insn_must_be_last_in_group (rtx_insn *insn)
32161 enum attr_type type;
32165 || DEBUG_INSN_P (insn)
32166 || GET_CODE (PATTERN (insn)) == USE
32167 || GET_CODE (PATTERN (insn)) == CLOBBER)
32170 switch (rs6000_tune) {
32171 case PROCESSOR_POWER4:
32172 case PROCESSOR_POWER5:
32173 if (is_microcoded_insn (insn))
32176 if (is_branch_slot_insn (insn))
32180 case PROCESSOR_POWER6:
32181 type = get_attr_type (insn);
32189 case TYPE_FPCOMPARE:
32200 if (get_attr_dot (insn) == DOT_NO
32201 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
32206 if (get_attr_size (insn) == SIZE_32)
32214 case PROCESSOR_POWER7:
32215 type = get_attr_type (insn);
32225 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32226 && get_attr_update (insn) == UPDATE_YES)
32231 if (get_attr_update (insn) == UPDATE_YES
32232 && get_attr_indexed (insn) == INDEXED_YES)
32240 case PROCESSOR_POWER8:
32241 type = get_attr_type (insn);
32253 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32254 && get_attr_update (insn) == UPDATE_YES)
32259 if (get_attr_update (insn) == UPDATE_YES
32260 && get_attr_indexed (insn) == INDEXED_YES)
32275 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
32276 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
32279 is_costly_group (rtx *group_insns, rtx next_insn)
32282 int issue_rate = rs6000_issue_rate ();
32284 for (i = 0; i < issue_rate; i++)
32286 sd_iterator_def sd_it;
32288 rtx insn = group_insns[i];
32293 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
32295 rtx next = DEP_CON (dep);
32297 if (next == next_insn
32298 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
32306 /* Utility of the function redefine_groups.
32307 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
32308 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
32309 to keep it "far" (in a separate group) from GROUP_INSNS, following
32310 one of the following schemes, depending on the value of the flag
32311 -minsert_sched_nops = X:
32312 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
32313 in order to force NEXT_INSN into a separate group.
32314 (2) X < sched_finish_regroup_exact: insert exactly X nops.
32315 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
32316 insertion (has a group just ended, how many vacant issue slots remain in the
32317 last group, and how many dispatch groups were encountered so far). */
32320 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
32321 rtx_insn *next_insn, bool *group_end, int can_issue_more,
32326 int issue_rate = rs6000_issue_rate ();
32327 bool end = *group_end;
32330 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
32331 return can_issue_more;
32333 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
32334 return can_issue_more;
32336 force = is_costly_group (group_insns, next_insn);
32338 return can_issue_more;
32340 if (sched_verbose > 6)
32341 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
32342 *group_count ,can_issue_more);
32344 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
32347 can_issue_more = 0;
32349 /* Since only a branch can be issued in the last issue_slot, it is
32350 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
32351 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
32352 in this case the last nop will start a new group and the branch
32353 will be forced to the new group. */
32354 if (can_issue_more && !is_branch_slot_insn (next_insn))
32357 /* Do we have a special group ending nop? */
32358 if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
32359 || rs6000_tune == PROCESSOR_POWER8)
32361 nop = gen_group_ending_nop ();
32362 emit_insn_before (nop, next_insn);
32363 can_issue_more = 0;
32366 while (can_issue_more > 0)
32369 emit_insn_before (nop, next_insn);
32377 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
32379 int n_nops = rs6000_sched_insert_nops;
32381 /* Nops can't be issued from the branch slot, so the effective
32382 issue_rate for nops is 'issue_rate - 1'. */
32383 if (can_issue_more == 0)
32384 can_issue_more = issue_rate;
32386 if (can_issue_more == 0)
32388 can_issue_more = issue_rate - 1;
32391 for (i = 0; i < issue_rate; i++)
32393 group_insns[i] = 0;
32400 emit_insn_before (nop, next_insn);
32401 if (can_issue_more == issue_rate - 1) /* new group begins */
32404 if (can_issue_more == 0)
32406 can_issue_more = issue_rate - 1;
32409 for (i = 0; i < issue_rate; i++)
32411 group_insns[i] = 0;
32417 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
32420 /* Is next_insn going to start a new group? */
32423 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32424 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32425 || (can_issue_more < issue_rate &&
32426 insn_terminates_group_p (next_insn, previous_group)));
32427 if (*group_end && end)
32430 if (sched_verbose > 6)
32431 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
32432 *group_count, can_issue_more);
32433 return can_issue_more;
32436 return can_issue_more;
32439 /* This function tries to synch the dispatch groups that the compiler "sees"
32440 with the dispatch groups that the processor dispatcher is expected to
32441 form in practice. It tries to achieve this synchronization by forcing the
32442 estimated processor grouping on the compiler (as opposed to the function
32443 'pad_goups' which tries to force the scheduler's grouping on the processor).
32445 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
32446 examines the (estimated) dispatch groups that will be formed by the processor
32447 dispatcher. It marks these group boundaries to reflect the estimated
32448 processor grouping, overriding the grouping that the scheduler had marked.
32449 Depending on the value of the flag '-minsert-sched-nops' this function can
32450 force certain insns into separate groups or force a certain distance between
32451 them by inserting nops, for example, if there exists a "costly dependence"
32454 The function estimates the group boundaries that the processor will form as
32455 follows: It keeps track of how many vacant issue slots are available after
32456 each insn. A subsequent insn will start a new group if one of the following
32458 - no more vacant issue slots remain in the current dispatch group.
32459 - only the last issue slot, which is the branch slot, is vacant, but the next
32460 insn is not a branch.
32461 - only the last 2 or less issue slots, including the branch slot, are vacant,
32462 which means that a cracked insn (which occupies two issue slots) can't be
32463 issued in this group.
32464 - less than 'issue_rate' slots are vacant, and the next insn always needs to
32465 start a new group. */
32468 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32471 rtx_insn *insn, *next_insn;
32473 int can_issue_more;
32476 int group_count = 0;
32480 issue_rate = rs6000_issue_rate ();
32481 group_insns = XALLOCAVEC (rtx, issue_rate);
32482 for (i = 0; i < issue_rate; i++)
32484 group_insns[i] = 0;
32486 can_issue_more = issue_rate;
32488 insn = get_next_active_insn (prev_head_insn, tail);
32491 while (insn != NULL_RTX)
32493 slot = (issue_rate - can_issue_more);
32494 group_insns[slot] = insn;
32496 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32497 if (insn_terminates_group_p (insn, current_group))
32498 can_issue_more = 0;
32500 next_insn = get_next_active_insn (insn, tail);
32501 if (next_insn == NULL_RTX)
32502 return group_count + 1;
32504 /* Is next_insn going to start a new group? */
32506 = (can_issue_more == 0
32507 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32508 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32509 || (can_issue_more < issue_rate &&
32510 insn_terminates_group_p (next_insn, previous_group)));
32512 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
32513 next_insn, &group_end, can_issue_more,
32519 can_issue_more = 0;
32520 for (i = 0; i < issue_rate; i++)
32522 group_insns[i] = 0;
32526 if (GET_MODE (next_insn) == TImode && can_issue_more)
32527 PUT_MODE (next_insn, VOIDmode);
32528 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
32529 PUT_MODE (next_insn, TImode);
32532 if (can_issue_more == 0)
32533 can_issue_more = issue_rate;
32536 return group_count;
32539 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32540 dispatch group boundaries that the scheduler had marked. Pad with nops
32541 any dispatch groups which have vacant issue slots, in order to force the
32542 scheduler's grouping on the processor dispatcher. The function
32543 returns the number of dispatch groups found. */
32546 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32549 rtx_insn *insn, *next_insn;
32552 int can_issue_more;
32554 int group_count = 0;
32556 /* Initialize issue_rate. */
32557 issue_rate = rs6000_issue_rate ();
32558 can_issue_more = issue_rate;
32560 insn = get_next_active_insn (prev_head_insn, tail);
32561 next_insn = get_next_active_insn (insn, tail);
32563 while (insn != NULL_RTX)
32566 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32568 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
32570 if (next_insn == NULL_RTX)
32575 /* If the scheduler had marked group termination at this location
32576 (between insn and next_insn), and neither insn nor next_insn will
32577 force group termination, pad the group with nops to force group
32580 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
32581 && !insn_terminates_group_p (insn, current_group)
32582 && !insn_terminates_group_p (next_insn, previous_group))
32584 if (!is_branch_slot_insn (next_insn))
32587 while (can_issue_more)
32590 emit_insn_before (nop, next_insn);
32595 can_issue_more = issue_rate;
32600 next_insn = get_next_active_insn (insn, tail);
32603 return group_count;
32606 /* We're beginning a new block. Initialize data structures as necessary. */
32609 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
32610 int sched_verbose ATTRIBUTE_UNUSED,
32611 int max_ready ATTRIBUTE_UNUSED)
32613 last_scheduled_insn = NULL;
32614 load_store_pendulum = 0;
32619 /* The following function is called at the end of scheduling BB.
32620 After reload, it inserts nops at insn group bundling. */
32623 rs6000_sched_finish (FILE *dump, int sched_verbose)
32628 fprintf (dump, "=== Finishing schedule.\n");
32630 if (reload_completed && rs6000_sched_groups)
32632 /* Do not run sched_finish hook when selective scheduling enabled. */
32633 if (sel_sched_p ())
32636 if (rs6000_sched_insert_nops == sched_finish_none)
32639 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
32640 n_groups = pad_groups (dump, sched_verbose,
32641 current_sched_info->prev_head,
32642 current_sched_info->next_tail);
32644 n_groups = redefine_groups (dump, sched_verbose,
32645 current_sched_info->prev_head,
32646 current_sched_info->next_tail);
32648 if (sched_verbose >= 6)
32650 fprintf (dump, "ngroups = %d\n", n_groups);
32651 print_rtl (dump, current_sched_info->prev_head);
32652 fprintf (dump, "Done finish_sched\n");
32657 struct rs6000_sched_context
32659 short cached_can_issue_more;
32660 rtx_insn *last_scheduled_insn;
32661 int load_store_pendulum;
32666 typedef struct rs6000_sched_context rs6000_sched_context_def;
32667 typedef rs6000_sched_context_def *rs6000_sched_context_t;
32669 /* Allocate store for new scheduling context. */
32671 rs6000_alloc_sched_context (void)
32673 return xmalloc (sizeof (rs6000_sched_context_def));
32676 /* If CLEAN_P is true then initializes _SC with clean data,
32677 and from the global context otherwise. */
32679 rs6000_init_sched_context (void *_sc, bool clean_p)
32681 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32685 sc->cached_can_issue_more = 0;
32686 sc->last_scheduled_insn = NULL;
32687 sc->load_store_pendulum = 0;
32688 sc->divide_cnt = 0;
32689 sc->vec_pairing = 0;
32693 sc->cached_can_issue_more = cached_can_issue_more;
32694 sc->last_scheduled_insn = last_scheduled_insn;
32695 sc->load_store_pendulum = load_store_pendulum;
32696 sc->divide_cnt = divide_cnt;
32697 sc->vec_pairing = vec_pairing;
32701 /* Sets the global scheduling context to the one pointed to by _SC. */
32703 rs6000_set_sched_context (void *_sc)
32705 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32707 gcc_assert (sc != NULL);
32709 cached_can_issue_more = sc->cached_can_issue_more;
32710 last_scheduled_insn = sc->last_scheduled_insn;
32711 load_store_pendulum = sc->load_store_pendulum;
32712 divide_cnt = sc->divide_cnt;
32713 vec_pairing = sc->vec_pairing;
32718 rs6000_free_sched_context (void *_sc)
32720 gcc_assert (_sc != NULL);
32726 rs6000_sched_can_speculate_insn (rtx_insn *insn)
32728 switch (get_attr_type (insn))
32743 /* Length in units of the trampoline for entering a nested function. */
32746 rs6000_trampoline_size (void)
32750 switch (DEFAULT_ABI)
32753 gcc_unreachable ();
32756 ret = (TARGET_32BIT) ? 12 : 24;
32760 gcc_assert (!TARGET_32BIT);
32766 ret = (TARGET_32BIT) ? 40 : 48;
32773 /* Emit RTL insns to initialize the variable parts of a trampoline.
32774 FNADDR is an RTX for the address of the function's pure code.
32775 CXT is an RTX for the static chain value for the function. */
32778 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
32780 int regsize = (TARGET_32BIT) ? 4 : 8;
32781 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
32782 rtx ctx_reg = force_reg (Pmode, cxt);
32783 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
32785 switch (DEFAULT_ABI)
32788 gcc_unreachable ();
32790 /* Under AIX, just build the 3 word function descriptor */
32793 rtx fnmem, fn_reg, toc_reg;
32795 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
32796 error ("you cannot take the address of a nested function if you use "
32797 "the %qs option", "-mno-pointers-to-nested-functions");
32799 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
32800 fn_reg = gen_reg_rtx (Pmode);
32801 toc_reg = gen_reg_rtx (Pmode);
32803 /* Macro to shorten the code expansions below. */
32804 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32806 m_tramp = replace_equiv_address (m_tramp, addr);
32808 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
32809 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
32810 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
32811 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32812 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32818 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32822 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32823 LCT_NORMAL, VOIDmode,
32825 GEN_INT (rs6000_trampoline_size ()), SImode,
32833 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32834 identifier as an argument, so the front end shouldn't look it up. */
32837 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32839 return is_attribute_p ("altivec", attr_id);
32842 /* Handle the "altivec" attribute. The attribute may have
32843 arguments as follows:
32845 __attribute__((altivec(vector__)))
32846 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32847 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32849 and may appear more than once (e.g., 'vector bool char') in a
32850 given declaration. */
32853 rs6000_handle_altivec_attribute (tree *node,
32854 tree name ATTRIBUTE_UNUSED,
32856 int flags ATTRIBUTE_UNUSED,
32857 bool *no_add_attrs)
32859 tree type = *node, result = NULL_TREE;
32863 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32864 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32865 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32868 while (POINTER_TYPE_P (type)
32869 || TREE_CODE (type) == FUNCTION_TYPE
32870 || TREE_CODE (type) == METHOD_TYPE
32871 || TREE_CODE (type) == ARRAY_TYPE)
32872 type = TREE_TYPE (type);
32874 mode = TYPE_MODE (type);
32876 /* Check for invalid AltiVec type qualifiers. */
32877 if (type == long_double_type_node)
32878 error ("use of %<long double%> in AltiVec types is invalid");
32879 else if (type == boolean_type_node)
32880 error ("use of boolean types in AltiVec types is invalid");
32881 else if (TREE_CODE (type) == COMPLEX_TYPE)
32882 error ("use of %<complex%> in AltiVec types is invalid");
32883 else if (DECIMAL_FLOAT_MODE_P (mode))
32884 error ("use of decimal floating point types in AltiVec types is invalid");
32885 else if (!TARGET_VSX)
32887 if (type == long_unsigned_type_node || type == long_integer_type_node)
32890 error ("use of %<long%> in AltiVec types is invalid for "
32891 "64-bit code without %qs", "-mvsx");
32892 else if (rs6000_warn_altivec_long)
32893 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32896 else if (type == long_long_unsigned_type_node
32897 || type == long_long_integer_type_node)
32898 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32900 else if (type == double_type_node)
32901 error ("use of %<double%> in AltiVec types is invalid without %qs",
32905 switch (altivec_type)
32908 unsigned_p = TYPE_UNSIGNED (type);
32912 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32915 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32918 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32921 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32924 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32926 case E_SFmode: result = V4SF_type_node; break;
32927 case E_DFmode: result = V2DF_type_node; break;
32928 /* If the user says 'vector int bool', we may be handed the 'bool'
32929 attribute _before_ the 'vector' attribute, and so select the
32930 proper type in the 'b' case below. */
32931 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32932 case E_V2DImode: case E_V2DFmode:
32940 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32941 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32942 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32943 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32950 case E_V8HImode: result = pixel_V8HI_type_node;
32956 /* Propagate qualifiers attached to the element type
32957 onto the vector type. */
32958 if (result && result != type && TYPE_QUALS (type))
32959 result = build_qualified_type (result, TYPE_QUALS (type));
32961 *no_add_attrs = true; /* No need to hang on to the attribute. */
32964 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32969 /* AltiVec defines four built-in scalar types that serve as vector
32970 elements; we must teach the compiler how to mangle them. */
32972 static const char *
32973 rs6000_mangle_type (const_tree type)
32975 type = TYPE_MAIN_VARIANT (type);
32977 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
32978 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
32981 if (type == bool_char_type_node) return "U6__boolc";
32982 if (type == bool_short_type_node) return "U6__bools";
32983 if (type == pixel_type_node) return "u7__pixel";
32984 if (type == bool_int_type_node) return "U6__booli";
32985 if (type == bool_long_type_node) return "U6__booll";
32987 /* Use a unique name for __float128 rather than trying to use "e" or "g". Use
32988 "g" for IBM extended double, no matter whether it is long double (using
32989 -mabi=ibmlongdouble) or the distinct __ibm128 type. */
32990 if (TARGET_FLOAT128_TYPE)
32992 if (type == ieee128_float_type_node)
32993 return "U10__float128";
32995 if (TARGET_LONG_DOUBLE_128)
32997 if (type == long_double_type_node)
32998 return (TARGET_IEEEQUAD) ? "U10__float128" : "g";
33000 if (type == ibm128_float_type_node)
33005 /* Mangle IBM extended float long double as `g' (__float128) on
33006 powerpc*-linux where long-double-64 previously was the default. */
33007 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
33009 && TARGET_LONG_DOUBLE_128
33010 && !TARGET_IEEEQUAD)
33013 /* For all other types, use normal C++ mangling. */
33017 /* Handle a "longcall" or "shortcall" attribute; arguments as in
33018 struct attribute_spec.handler. */
33021 rs6000_handle_longcall_attribute (tree *node, tree name,
33022 tree args ATTRIBUTE_UNUSED,
33023 int flags ATTRIBUTE_UNUSED,
33024 bool *no_add_attrs)
33026 if (TREE_CODE (*node) != FUNCTION_TYPE
33027 && TREE_CODE (*node) != FIELD_DECL
33028 && TREE_CODE (*node) != TYPE_DECL)
33030 warning (OPT_Wattributes, "%qE attribute only applies to functions",
33032 *no_add_attrs = true;
33038 /* Set longcall attributes on all functions declared when
33039 rs6000_default_long_calls is true. */
33041 rs6000_set_default_type_attributes (tree type)
33043 if (rs6000_default_long_calls
33044 && (TREE_CODE (type) == FUNCTION_TYPE
33045 || TREE_CODE (type) == METHOD_TYPE))
33046 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
33048 TYPE_ATTRIBUTES (type));
33051 darwin_set_default_type_attributes (type);
33055 /* Return a reference suitable for calling a function with the
33056 longcall attribute. */
33059 rs6000_longcall_ref (rtx call_ref)
33061 const char *call_name;
33064 if (GET_CODE (call_ref) != SYMBOL_REF)
33067 /* System V adds '.' to the internal name, so skip them. */
33068 call_name = XSTR (call_ref, 0);
33069 if (*call_name == '.')
33071 while (*call_name == '.')
33074 node = get_identifier (call_name);
33075 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
33078 return force_reg (Pmode, call_ref);
33081 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
33082 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
33085 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
33086 struct attribute_spec.handler. */
33088 rs6000_handle_struct_attribute (tree *node, tree name,
33089 tree args ATTRIBUTE_UNUSED,
33090 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
33093 if (DECL_P (*node))
33095 if (TREE_CODE (*node) == TYPE_DECL)
33096 type = &TREE_TYPE (*node);
33101 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
33102 || TREE_CODE (*type) == UNION_TYPE)))
33104 warning (OPT_Wattributes, "%qE attribute ignored", name);
33105 *no_add_attrs = true;
33108 else if ((is_attribute_p ("ms_struct", name)
33109 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
33110 || ((is_attribute_p ("gcc_struct", name)
33111 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
33113 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
33115 *no_add_attrs = true;
33122 rs6000_ms_bitfield_layout_p (const_tree record_type)
33124 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
33125 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
33126 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
33129 #ifdef USING_ELFOS_H
33131 /* A get_unnamed_section callback, used for switching to toc_section. */
33134 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33136 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33137 && TARGET_MINIMAL_TOC)
33139 if (!toc_initialized)
33141 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
33142 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33143 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
33144 fprintf (asm_out_file, "\t.tc ");
33145 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
33146 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33147 fprintf (asm_out_file, "\n");
33149 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33150 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33151 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33152 fprintf (asm_out_file, " = .+32768\n");
33153 toc_initialized = 1;
33156 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33158 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33160 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
33161 if (!toc_initialized)
33163 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33164 toc_initialized = 1;
33169 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33170 if (!toc_initialized)
33172 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33173 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33174 fprintf (asm_out_file, " = .+32768\n");
33175 toc_initialized = 1;
33180 /* Implement TARGET_ASM_INIT_SECTIONS. */
33183 rs6000_elf_asm_init_sections (void)
33186 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
33189 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
33190 SDATA2_SECTION_ASM_OP);
33193 /* Implement TARGET_SELECT_RTX_SECTION. */
33196 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
33197 unsigned HOST_WIDE_INT align)
33199 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33200 return toc_section;
33202 return default_elf_select_rtx_section (mode, x, align);
33205 /* For a SYMBOL_REF, set generic flags and then perform some
33206 target-specific processing.
33208 When the AIX ABI is requested on a non-AIX system, replace the
33209 function name with the real name (with a leading .) rather than the
33210 function descriptor name. This saves a lot of overriding code to
33211 read the prefixes. */
33213 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
33215 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
33217 default_encode_section_info (decl, rtl, first);
33220 && TREE_CODE (decl) == FUNCTION_DECL
33222 && DEFAULT_ABI == ABI_AIX)
33224 rtx sym_ref = XEXP (rtl, 0);
33225 size_t len = strlen (XSTR (sym_ref, 0));
33226 char *str = XALLOCAVEC (char, len + 2);
33228 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
33229 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
33234 compare_section_name (const char *section, const char *templ)
33238 len = strlen (templ);
33239 return (strncmp (section, templ, len) == 0
33240 && (section[len] == 0 || section[len] == '.'));
33244 rs6000_elf_in_small_data_p (const_tree decl)
33246 if (rs6000_sdata == SDATA_NONE)
33249 /* We want to merge strings, so we never consider them small data. */
33250 if (TREE_CODE (decl) == STRING_CST)
33253 /* Functions are never in the small data area. */
33254 if (TREE_CODE (decl) == FUNCTION_DECL)
33257 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
33259 const char *section = DECL_SECTION_NAME (decl);
33260 if (compare_section_name (section, ".sdata")
33261 || compare_section_name (section, ".sdata2")
33262 || compare_section_name (section, ".gnu.linkonce.s")
33263 || compare_section_name (section, ".sbss")
33264 || compare_section_name (section, ".sbss2")
33265 || compare_section_name (section, ".gnu.linkonce.sb")
33266 || strcmp (section, ".PPC.EMB.sdata0") == 0
33267 || strcmp (section, ".PPC.EMB.sbss0") == 0)
33272 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
33275 && size <= g_switch_value
33276 /* If it's not public, and we're not going to reference it there,
33277 there's no need to put it in the small data section. */
33278 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
33285 #endif /* USING_ELFOS_H */
33287 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
33290 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
33292 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
33295 /* Do not place thread-local symbols refs in the object blocks. */
33298 rs6000_use_blocks_for_decl_p (const_tree decl)
33300 return !DECL_THREAD_LOCAL_P (decl);
33303 /* Return a REG that occurs in ADDR with coefficient 1.
33304 ADDR can be effectively incremented by incrementing REG.
33306 r0 is special and we must not select it as an address
33307 register by this routine since our caller will try to
33308 increment the returned register via an "la" instruction. */
33311 find_addr_reg (rtx addr)
33313 while (GET_CODE (addr) == PLUS)
33315 if (GET_CODE (XEXP (addr, 0)) == REG
33316 && REGNO (XEXP (addr, 0)) != 0)
33317 addr = XEXP (addr, 0);
33318 else if (GET_CODE (XEXP (addr, 1)) == REG
33319 && REGNO (XEXP (addr, 1)) != 0)
33320 addr = XEXP (addr, 1);
33321 else if (CONSTANT_P (XEXP (addr, 0)))
33322 addr = XEXP (addr, 1);
33323 else if (CONSTANT_P (XEXP (addr, 1)))
33324 addr = XEXP (addr, 0);
33326 gcc_unreachable ();
33328 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
33333 rs6000_fatal_bad_address (rtx op)
33335 fatal_insn ("bad address", op);
33340 typedef struct branch_island_d {
33341 tree function_name;
33347 static vec<branch_island, va_gc> *branch_islands;
33349 /* Remember to generate a branch island for far calls to the given
33353 add_compiler_branch_island (tree label_name, tree function_name,
33356 branch_island bi = {function_name, label_name, line_number};
33357 vec_safe_push (branch_islands, bi);
33360 /* Generate far-jump branch islands for everything recorded in
33361 branch_islands. Invoked immediately after the last instruction of
33362 the epilogue has been emitted; the branch islands must be appended
33363 to, and contiguous with, the function body. Mach-O stubs are
33364 generated in machopic_output_stub(). */
33367 macho_branch_islands (void)
33371 while (!vec_safe_is_empty (branch_islands))
33373 branch_island *bi = &branch_islands->last ();
33374 const char *label = IDENTIFIER_POINTER (bi->label_name);
33375 const char *name = IDENTIFIER_POINTER (bi->function_name);
33376 char name_buf[512];
33377 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
33378 if (name[0] == '*' || name[0] == '&')
33379 strcpy (name_buf, name+1);
33383 strcpy (name_buf+1, name);
33385 strcpy (tmp_buf, "\n");
33386 strcat (tmp_buf, label);
33387 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33388 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33389 dbxout_stabd (N_SLINE, bi->line_number);
33390 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33393 if (TARGET_LINK_STACK)
33396 get_ppc476_thunk_name (name);
33397 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
33398 strcat (tmp_buf, name);
33399 strcat (tmp_buf, "\n");
33400 strcat (tmp_buf, label);
33401 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
33405 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
33406 strcat (tmp_buf, label);
33407 strcat (tmp_buf, "_pic\n");
33408 strcat (tmp_buf, label);
33409 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
33412 strcat (tmp_buf, "\taddis r11,r11,ha16(");
33413 strcat (tmp_buf, name_buf);
33414 strcat (tmp_buf, " - ");
33415 strcat (tmp_buf, label);
33416 strcat (tmp_buf, "_pic)\n");
33418 strcat (tmp_buf, "\tmtlr r0\n");
33420 strcat (tmp_buf, "\taddi r12,r11,lo16(");
33421 strcat (tmp_buf, name_buf);
33422 strcat (tmp_buf, " - ");
33423 strcat (tmp_buf, label);
33424 strcat (tmp_buf, "_pic)\n");
33426 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
33430 strcat (tmp_buf, ":\nlis r12,hi16(");
33431 strcat (tmp_buf, name_buf);
33432 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
33433 strcat (tmp_buf, name_buf);
33434 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
33436 output_asm_insn (tmp_buf, 0);
33437 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33438 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33439 dbxout_stabd (N_SLINE, bi->line_number);
33440 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33441 branch_islands->pop ();
33445 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
33446 already there or not. */
33449 no_previous_def (tree function_name)
33454 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33455 if (function_name == bi->function_name)
33460 /* GET_PREV_LABEL gets the label name from the previous definition of
33464 get_prev_label (tree function_name)
33469 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33470 if (function_name == bi->function_name)
33471 return bi->label_name;
33475 /* INSN is either a function call or a millicode call. It may have an
33476 unconditional jump in its delay slot.
33478 CALL_DEST is the routine we are calling. */
33481 output_call (rtx_insn *insn, rtx *operands, int dest_operand_number,
33482 int cookie_operand_number)
33484 static char buf[256];
33485 if (darwin_emit_branch_islands
33486 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
33487 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
33490 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
33492 if (no_previous_def (funname))
33494 rtx label_rtx = gen_label_rtx ();
33495 char *label_buf, temp_buf[256];
33496 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
33497 CODE_LABEL_NUMBER (label_rtx));
33498 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
33499 labelname = get_identifier (label_buf);
33500 add_compiler_branch_island (labelname, funname, insn_line (insn));
33503 labelname = get_prev_label (funname);
33505 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
33506 instruction will reach 'foo', otherwise link as 'bl L42'".
33507 "L42" should be a 'branch island', that will do a far jump to
33508 'foo'. Branch islands are generated in
33509 macho_branch_islands(). */
33510 sprintf (buf, "jbsr %%z%d,%.246s",
33511 dest_operand_number, IDENTIFIER_POINTER (labelname));
33514 sprintf (buf, "bl %%z%d", dest_operand_number);
33518 /* Generate PIC and indirect symbol stubs. */
33521 machopic_output_stub (FILE *file, const char *symb, const char *stub)
33523 unsigned int length;
33524 char *symbol_name, *lazy_ptr_name;
33525 char *local_label_0;
33526 static int label = 0;
33528 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
33529 symb = (*targetm.strip_name_encoding) (symb);
33532 length = strlen (symb);
33533 symbol_name = XALLOCAVEC (char, length + 32);
33534 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
33536 lazy_ptr_name = XALLOCAVEC (char, length + 32);
33537 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
33540 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
33542 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
33546 fprintf (file, "\t.align 5\n");
33548 fprintf (file, "%s:\n", stub);
33549 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33552 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
33553 sprintf (local_label_0, "\"L%011d$spb\"", label);
33555 fprintf (file, "\tmflr r0\n");
33556 if (TARGET_LINK_STACK)
33559 get_ppc476_thunk_name (name);
33560 fprintf (file, "\tbl %s\n", name);
33561 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33565 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
33566 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33568 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
33569 lazy_ptr_name, local_label_0);
33570 fprintf (file, "\tmtlr r0\n");
33571 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
33572 (TARGET_64BIT ? "ldu" : "lwzu"),
33573 lazy_ptr_name, local_label_0);
33574 fprintf (file, "\tmtctr r12\n");
33575 fprintf (file, "\tbctr\n");
33579 fprintf (file, "\t.align 4\n");
33581 fprintf (file, "%s:\n", stub);
33582 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33584 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
33585 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
33586 (TARGET_64BIT ? "ldu" : "lwzu"),
33588 fprintf (file, "\tmtctr r12\n");
33589 fprintf (file, "\tbctr\n");
33592 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
33593 fprintf (file, "%s:\n", lazy_ptr_name);
33594 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33595 fprintf (file, "%sdyld_stub_binding_helper\n",
33596 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
33599 /* Legitimize PIC addresses. If the address is already
33600 position-independent, we return ORIG. Newly generated
33601 position-independent addresses go into a reg. This is REG if non
33602 zero, otherwise we allocate register(s) as necessary. */
33604 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33607 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
33612 if (reg == NULL && !reload_completed)
33613 reg = gen_reg_rtx (Pmode);
33615 if (GET_CODE (orig) == CONST)
33619 if (GET_CODE (XEXP (orig, 0)) == PLUS
33620 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
33623 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
33625 /* Use a different reg for the intermediate value, as
33626 it will be marked UNCHANGING. */
33627 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
33628 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
33631 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
33634 if (GET_CODE (offset) == CONST_INT)
33636 if (SMALL_INT (offset))
33637 return plus_constant (Pmode, base, INTVAL (offset));
33638 else if (!reload_completed)
33639 offset = force_reg (Pmode, offset);
33642 rtx mem = force_const_mem (Pmode, orig);
33643 return machopic_legitimize_pic_address (mem, Pmode, reg);
33646 return gen_rtx_PLUS (Pmode, base, offset);
33649 /* Fall back on generic machopic code. */
33650 return machopic_legitimize_pic_address (orig, mode, reg);
33653 /* Output a .machine directive for the Darwin assembler, and call
33654 the generic start_file routine. */
33657 rs6000_darwin_file_start (void)
33659 static const struct
33663 HOST_WIDE_INT if_set;
33665 { "ppc64", "ppc64", MASK_64BIT },
33666 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
33667 { "power4", "ppc970", 0 },
33668 { "G5", "ppc970", 0 },
33669 { "7450", "ppc7450", 0 },
33670 { "7400", "ppc7400", MASK_ALTIVEC },
33671 { "G4", "ppc7400", 0 },
33672 { "750", "ppc750", 0 },
33673 { "740", "ppc750", 0 },
33674 { "G3", "ppc750", 0 },
33675 { "604e", "ppc604e", 0 },
33676 { "604", "ppc604", 0 },
33677 { "603e", "ppc603", 0 },
33678 { "603", "ppc603", 0 },
33679 { "601", "ppc601", 0 },
33680 { NULL, "ppc", 0 } };
33681 const char *cpu_id = "";
33684 rs6000_file_start ();
33685 darwin_file_start ();
33687 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33689 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
33690 cpu_id = rs6000_default_cpu;
33692 if (global_options_set.x_rs6000_cpu_index)
33693 cpu_id = processor_target_table[rs6000_cpu_index].name;
33695 /* Look through the mapping array. Pick the first name that either
33696 matches the argument, has a bit set in IF_SET that is also set
33697 in the target flags, or has a NULL name. */
33700 while (mapping[i].arg != NULL
33701 && strcmp (mapping[i].arg, cpu_id) != 0
33702 && (mapping[i].if_set & rs6000_isa_flags) == 0)
33705 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
33708 #endif /* TARGET_MACHO */
33712 rs6000_elf_reloc_rw_mask (void)
33716 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33722 /* Record an element in the table of global constructors. SYMBOL is
33723 a SYMBOL_REF of the function to be called; PRIORITY is a number
33724 between 0 and MAX_INIT_PRIORITY.
33726 This differs from default_named_section_asm_out_constructor in
33727 that we have special handling for -mrelocatable. */
33729 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
33731 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
33733 const char *section = ".ctors";
33736 if (priority != DEFAULT_INIT_PRIORITY)
33738 sprintf (buf, ".ctors.%.5u",
33739 /* Invert the numbering so the linker puts us in the proper
33740 order; constructors are run from right to left, and the
33741 linker sorts in increasing order. */
33742 MAX_INIT_PRIORITY - priority);
33746 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33747 assemble_align (POINTER_SIZE);
33749 if (DEFAULT_ABI == ABI_V4
33750 && (TARGET_RELOCATABLE || flag_pic > 1))
33752 fputs ("\t.long (", asm_out_file);
33753 output_addr_const (asm_out_file, symbol);
33754 fputs (")@fixup\n", asm_out_file);
33757 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33760 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
33762 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
33764 const char *section = ".dtors";
33767 if (priority != DEFAULT_INIT_PRIORITY)
33769 sprintf (buf, ".dtors.%.5u",
33770 /* Invert the numbering so the linker puts us in the proper
33771 order; constructors are run from right to left, and the
33772 linker sorts in increasing order. */
33773 MAX_INIT_PRIORITY - priority);
33777 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33778 assemble_align (POINTER_SIZE);
33780 if (DEFAULT_ABI == ABI_V4
33781 && (TARGET_RELOCATABLE || flag_pic > 1))
33783 fputs ("\t.long (", asm_out_file);
33784 output_addr_const (asm_out_file, symbol);
33785 fputs (")@fixup\n", asm_out_file);
33788 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33792 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
33794 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
33796 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
33797 ASM_OUTPUT_LABEL (file, name);
33798 fputs (DOUBLE_INT_ASM_OP, file);
33799 rs6000_output_function_entry (file, name);
33800 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
33803 fputs ("\t.size\t", file);
33804 assemble_name (file, name);
33805 fputs (",24\n\t.type\t.", file);
33806 assemble_name (file, name);
33807 fputs (",@function\n", file);
33808 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
33810 fputs ("\t.globl\t.", file);
33811 assemble_name (file, name);
33816 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33817 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33818 rs6000_output_function_entry (file, name);
33819 fputs (":\n", file);
33824 if (DEFAULT_ABI == ABI_V4
33825 && (TARGET_RELOCATABLE || flag_pic > 1)
33826 && !TARGET_SECURE_PLT
33827 && (!constant_pool_empty_p () || crtl->profile)
33828 && (uses_toc = uses_TOC ()))
33833 switch_to_other_text_partition ();
33834 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33836 fprintf (file, "\t.long ");
33837 assemble_name (file, toc_label_name);
33840 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33841 assemble_name (file, buf);
33844 switch_to_other_text_partition ();
33847 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33848 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33850 if (TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ())
33854 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33856 fprintf (file, "\t.quad .TOC.-");
33857 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33858 assemble_name (file, buf);
33862 if (DEFAULT_ABI == ABI_AIX)
33864 const char *desc_name, *orig_name;
33866 orig_name = (*targetm.strip_name_encoding) (name);
33867 desc_name = orig_name;
33868 while (*desc_name == '.')
33871 if (TREE_PUBLIC (decl))
33872 fprintf (file, "\t.globl %s\n", desc_name);
33874 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33875 fprintf (file, "%s:\n", desc_name);
33876 fprintf (file, "\t.long %s\n", orig_name);
33877 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33878 fputs ("\t.long 0\n", file);
33879 fprintf (file, "\t.previous\n");
33881 ASM_OUTPUT_LABEL (file, name);
33884 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33886 rs6000_elf_file_end (void)
33888 #ifdef HAVE_AS_GNU_ATTRIBUTE
33889 /* ??? The value emitted depends on options active at file end.
33890 Assume anyone using #pragma or attributes that might change
33891 options knows what they are doing. */
33892 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33893 && rs6000_passes_float)
33899 else if (TARGET_SF_FPR)
33903 if (rs6000_passes_long_double)
33905 if (!TARGET_LONG_DOUBLE_128)
33907 else if (TARGET_IEEEQUAD)
33912 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33914 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33916 if (rs6000_passes_vector)
33917 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33918 (TARGET_ALTIVEC_ABI ? 2 : 1));
33919 if (rs6000_returns_struct)
33920 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33921 aix_struct_return ? 2 : 1);
33924 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33925 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33926 file_end_indicate_exec_stack ();
33929 if (flag_split_stack)
33930 file_end_indicate_split_stack ();
33934 /* We have expanded a CPU builtin, so we need to emit a reference to
33935 the special symbol that LIBC uses to declare it supports the
33936 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33937 switch_to_section (data_section);
33938 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33939 fprintf (asm_out_file, "\t%s %s\n",
33940 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33947 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33948 #define HAVE_XCOFF_DWARF_EXTRAS 0
33951 static enum unwind_info_type
33952 rs6000_xcoff_debug_unwind_info (void)
33958 rs6000_xcoff_asm_output_anchor (rtx symbol)
33962 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33963 SYMBOL_REF_BLOCK_OFFSET (symbol));
33964 fprintf (asm_out_file, "%s", SET_ASM_OP);
33965 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33966 fprintf (asm_out_file, ",");
33967 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33968 fprintf (asm_out_file, "\n");
33972 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
33974 fputs (GLOBAL_ASM_OP, stream);
33975 RS6000_OUTPUT_BASENAME (stream, name);
33976 putc ('\n', stream);
33979 /* A get_unnamed_decl callback, used for read-only sections. PTR
33980 points to the section string variable. */
33983 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
33985 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
33986 *(const char *const *) directive,
33987 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33990 /* Likewise for read-write sections. */
33993 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
33995 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
33996 *(const char *const *) directive,
33997 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
34001 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
34003 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
34004 *(const char *const *) directive,
34005 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
34008 /* A get_unnamed_section callback, used for switching to toc_section. */
34011 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
34013 if (TARGET_MINIMAL_TOC)
34015 /* toc_section is always selected at least once from
34016 rs6000_xcoff_file_start, so this is guaranteed to
34017 always be defined once and only once in each file. */
34018 if (!toc_initialized)
34020 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
34021 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
34022 toc_initialized = 1;
34024 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
34025 (TARGET_32BIT ? "" : ",3"));
34028 fputs ("\t.toc\n", asm_out_file);
34031 /* Implement TARGET_ASM_INIT_SECTIONS. */
34034 rs6000_xcoff_asm_init_sections (void)
34036 read_only_data_section
34037 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
34038 &xcoff_read_only_section_name);
34040 private_data_section
34041 = get_unnamed_section (SECTION_WRITE,
34042 rs6000_xcoff_output_readwrite_section_asm_op,
34043 &xcoff_private_data_section_name);
34046 = get_unnamed_section (SECTION_TLS,
34047 rs6000_xcoff_output_tls_section_asm_op,
34048 &xcoff_tls_data_section_name);
34050 tls_private_data_section
34051 = get_unnamed_section (SECTION_TLS,
34052 rs6000_xcoff_output_tls_section_asm_op,
34053 &xcoff_private_data_section_name);
34055 read_only_private_data_section
34056 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
34057 &xcoff_private_data_section_name);
34060 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
34062 readonly_data_section = read_only_data_section;
34066 rs6000_xcoff_reloc_rw_mask (void)
34072 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
34073 tree decl ATTRIBUTE_UNUSED)
34076 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
34078 if (flags & SECTION_EXCLUDE)
34080 else if (flags & SECTION_DEBUG)
34082 fprintf (asm_out_file, "\t.dwsect %s\n", name);
34085 else if (flags & SECTION_CODE)
34087 else if (flags & SECTION_TLS)
34089 else if (flags & SECTION_WRITE)
34094 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
34095 (flags & SECTION_CODE) ? "." : "",
34096 name, suffix[smclass], flags & SECTION_ENTSIZE);
34099 #define IN_NAMED_SECTION(DECL) \
34100 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
34101 && DECL_SECTION_NAME (DECL) != NULL)
34104 rs6000_xcoff_select_section (tree decl, int reloc,
34105 unsigned HOST_WIDE_INT align)
34107 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
34109 if (align > BIGGEST_ALIGNMENT)
34111 resolve_unique_section (decl, reloc, true);
34112 if (IN_NAMED_SECTION (decl))
34113 return get_named_section (decl, NULL, reloc);
34116 if (decl_readonly_section (decl, reloc))
34118 if (TREE_PUBLIC (decl))
34119 return read_only_data_section;
34121 return read_only_private_data_section;
34126 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34128 if (TREE_PUBLIC (decl))
34129 return tls_data_section;
34130 else if (bss_initializer_p (decl))
34132 /* Convert to COMMON to emit in BSS. */
34133 DECL_COMMON (decl) = 1;
34134 return tls_comm_section;
34137 return tls_private_data_section;
34141 if (TREE_PUBLIC (decl))
34142 return data_section;
34144 return private_data_section;
34149 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
34153 /* Use select_section for private data and uninitialized data with
34154 alignment <= BIGGEST_ALIGNMENT. */
34155 if (!TREE_PUBLIC (decl)
34156 || DECL_COMMON (decl)
34157 || (DECL_INITIAL (decl) == NULL_TREE
34158 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
34159 || DECL_INITIAL (decl) == error_mark_node
34160 || (flag_zero_initialized_in_bss
34161 && initializer_zerop (DECL_INITIAL (decl))))
34164 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
34165 name = (*targetm.strip_name_encoding) (name);
34166 set_decl_section_name (decl, name);
34169 /* Select section for constant in constant pool.
34171 On RS/6000, all constants are in the private read-only data area.
34172 However, if this is being placed in the TOC it must be output as a
34176 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
34177 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
34179 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
34180 return toc_section;
34182 return read_only_private_data_section;
34185 /* Remove any trailing [DS] or the like from the symbol name. */
34187 static const char *
34188 rs6000_xcoff_strip_name_encoding (const char *name)
34193 len = strlen (name);
34194 if (name[len - 1] == ']')
34195 return ggc_alloc_string (name, len - 4);
34200 /* Section attributes. AIX is always PIC. */
34202 static unsigned int
34203 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
34205 unsigned int align;
34206 unsigned int flags = default_section_type_flags (decl, name, reloc);
34208 /* Align to at least UNIT size. */
34209 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
34210 align = MIN_UNITS_PER_WORD;
34212 /* Increase alignment of large objects if not already stricter. */
34213 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
34214 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
34215 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
34217 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
34220 /* Output at beginning of assembler file.
34222 Initialize the section names for the RS/6000 at this point.
34224 Specify filename, including full path, to assembler.
34226 We want to go into the TOC section so at least one .toc will be emitted.
34227 Also, in order to output proper .bs/.es pairs, we need at least one static
34228 [RW] section emitted.
34230 Finally, declare mcount when profiling to make the assembler happy. */
34233 rs6000_xcoff_file_start (void)
34235 rs6000_gen_section_name (&xcoff_bss_section_name,
34236 main_input_filename, ".bss_");
34237 rs6000_gen_section_name (&xcoff_private_data_section_name,
34238 main_input_filename, ".rw_");
34239 rs6000_gen_section_name (&xcoff_read_only_section_name,
34240 main_input_filename, ".ro_");
34241 rs6000_gen_section_name (&xcoff_tls_data_section_name,
34242 main_input_filename, ".tls_");
34243 rs6000_gen_section_name (&xcoff_tbss_section_name,
34244 main_input_filename, ".tbss_[UL]");
34246 fputs ("\t.file\t", asm_out_file);
34247 output_quoted_string (asm_out_file, main_input_filename);
34248 fputc ('\n', asm_out_file);
34249 if (write_symbols != NO_DEBUG)
34250 switch_to_section (private_data_section);
34251 switch_to_section (toc_section);
34252 switch_to_section (text_section);
34254 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
34255 rs6000_file_start ();
34258 /* Output at end of assembler file.
34259 On the RS/6000, referencing data should automatically pull in text. */
34262 rs6000_xcoff_file_end (void)
34264 switch_to_section (text_section);
34265 fputs ("_section_.text:\n", asm_out_file);
34266 switch_to_section (data_section);
34267 fputs (TARGET_32BIT
34268 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
34272 struct declare_alias_data
34275 bool function_descriptor;
34278 /* Declare alias N. A helper function for for_node_and_aliases. */
34281 rs6000_declare_alias (struct symtab_node *n, void *d)
34283 struct declare_alias_data *data = (struct declare_alias_data *)d;
34284 /* Main symbol is output specially, because varasm machinery does part of
34285 the job for us - we do not need to declare .globl/lglobs and such. */
34286 if (!n->alias || n->weakref)
34289 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
34292 /* Prevent assemble_alias from trying to use .set pseudo operation
34293 that does not behave as expected by the middle-end. */
34294 TREE_ASM_WRITTEN (n->decl) = true;
34296 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
34297 char *buffer = (char *) alloca (strlen (name) + 2);
34299 int dollar_inside = 0;
34301 strcpy (buffer, name);
34302 p = strchr (buffer, '$');
34306 p = strchr (p + 1, '$');
34308 if (TREE_PUBLIC (n->decl))
34310 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
34312 if (dollar_inside) {
34313 if (data->function_descriptor)
34314 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
34315 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
34317 if (data->function_descriptor)
34319 fputs ("\t.globl .", data->file);
34320 RS6000_OUTPUT_BASENAME (data->file, buffer);
34321 putc ('\n', data->file);
34323 fputs ("\t.globl ", data->file);
34324 RS6000_OUTPUT_BASENAME (data->file, buffer);
34325 putc ('\n', data->file);
34327 #ifdef ASM_WEAKEN_DECL
34328 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
34329 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
34336 if (data->function_descriptor)
34337 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
34338 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
34340 if (data->function_descriptor)
34342 fputs ("\t.lglobl .", data->file);
34343 RS6000_OUTPUT_BASENAME (data->file, buffer);
34344 putc ('\n', data->file);
34346 fputs ("\t.lglobl ", data->file);
34347 RS6000_OUTPUT_BASENAME (data->file, buffer);
34348 putc ('\n', data->file);
34350 if (data->function_descriptor)
34351 fputs (".", data->file);
34352 RS6000_OUTPUT_BASENAME (data->file, buffer);
34353 fputs (":\n", data->file);
34358 #ifdef HAVE_GAS_HIDDEN
34359 /* Helper function to calculate visibility of a DECL
34360 and return the value as a const string. */
34362 static const char *
34363 rs6000_xcoff_visibility (tree decl)
34365 static const char * const visibility_types[] = {
34366 "", ",protected", ",hidden", ",internal"
34369 enum symbol_visibility vis = DECL_VISIBILITY (decl);
34371 if (TREE_CODE (decl) == FUNCTION_DECL
34372 && cgraph_node::get (decl)
34373 && cgraph_node::get (decl)->instrumentation_clone
34374 && cgraph_node::get (decl)->instrumented_version)
34375 vis = DECL_VISIBILITY (cgraph_node::get (decl)->instrumented_version->decl);
34377 return visibility_types[vis];
34382 /* This macro produces the initial definition of a function name.
34383 On the RS/6000, we need to place an extra '.' in the function name and
34384 output the function descriptor.
34385 Dollar signs are converted to underscores.
34387 The csect for the function will have already been created when
34388 text_section was selected. We do have to go back to that csect, however.
34390 The third and fourth parameters to the .function pseudo-op (16 and 044)
34391 are placeholders which no longer have any use.
34393 Because AIX assembler's .set command has unexpected semantics, we output
34394 all aliases as alternative labels in front of the definition. */
34397 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
34399 char *buffer = (char *) alloca (strlen (name) + 1);
34401 int dollar_inside = 0;
34402 struct declare_alias_data data = {file, false};
34404 strcpy (buffer, name);
34405 p = strchr (buffer, '$');
34409 p = strchr (p + 1, '$');
34411 if (TREE_PUBLIC (decl))
34413 if (!RS6000_WEAK || !DECL_WEAK (decl))
34415 if (dollar_inside) {
34416 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
34417 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
34419 fputs ("\t.globl .", file);
34420 RS6000_OUTPUT_BASENAME (file, buffer);
34421 #ifdef HAVE_GAS_HIDDEN
34422 fputs (rs6000_xcoff_visibility (decl), file);
34429 if (dollar_inside) {
34430 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
34431 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
34433 fputs ("\t.lglobl .", file);
34434 RS6000_OUTPUT_BASENAME (file, buffer);
34437 fputs ("\t.csect ", file);
34438 RS6000_OUTPUT_BASENAME (file, buffer);
34439 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
34440 RS6000_OUTPUT_BASENAME (file, buffer);
34441 fputs (":\n", file);
34442 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34444 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
34445 RS6000_OUTPUT_BASENAME (file, buffer);
34446 fputs (", TOC[tc0], 0\n", file);
34448 switch_to_section (function_section (decl));
34450 RS6000_OUTPUT_BASENAME (file, buffer);
34451 fputs (":\n", file);
34452 data.function_descriptor = true;
34453 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34455 if (!DECL_IGNORED_P (decl))
34457 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
34458 xcoffout_declare_function (file, decl, buffer);
34459 else if (write_symbols == DWARF2_DEBUG)
34461 name = (*targetm.strip_name_encoding) (name);
34462 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
34469 /* Output assembly language to globalize a symbol from a DECL,
34470 possibly with visibility. */
34473 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
34475 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
34476 fputs (GLOBAL_ASM_OP, stream);
34477 RS6000_OUTPUT_BASENAME (stream, name);
34478 #ifdef HAVE_GAS_HIDDEN
34479 fputs (rs6000_xcoff_visibility (decl), stream);
34481 putc ('\n', stream);
34484 /* Output assembly language to define a symbol as COMMON from a DECL,
34485 possibly with visibility. */
34488 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
34489 tree decl ATTRIBUTE_UNUSED,
34491 unsigned HOST_WIDE_INT size,
34492 unsigned HOST_WIDE_INT align)
34494 unsigned HOST_WIDE_INT align2 = 2;
34497 align2 = floor_log2 (align / BITS_PER_UNIT);
34501 fputs (COMMON_ASM_OP, stream);
34502 RS6000_OUTPUT_BASENAME (stream, name);
34505 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
34508 #ifdef HAVE_GAS_HIDDEN
34510 fputs (rs6000_xcoff_visibility (decl), stream);
34512 putc ('\n', stream);
34515 /* This macro produces the initial definition of a object (variable) name.
34516 Because AIX assembler's .set command has unexpected semantics, we output
34517 all aliases as alternative labels in front of the definition. */
34520 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
34522 struct declare_alias_data data = {file, false};
34523 RS6000_OUTPUT_BASENAME (file, name);
34524 fputs (":\n", file);
34525 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34529 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
34532 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
34534 fputs (integer_asm_op (size, FALSE), file);
34535 assemble_name (file, label);
34536 fputs ("-$", file);
34539 /* Output a symbol offset relative to the dbase for the current object.
34540 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
34543 __gcc_unwind_dbase is embedded in all executables/libraries through
34544 libgcc/config/rs6000/crtdbase.S. */
34547 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
34549 fputs (integer_asm_op (size, FALSE), file);
34550 assemble_name (file, label);
34551 fputs("-__gcc_unwind_dbase", file);
34556 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
34560 const char *symname;
34562 default_encode_section_info (decl, rtl, first);
34564 /* Careful not to prod global register variables. */
34567 symbol = XEXP (rtl, 0);
34568 if (GET_CODE (symbol) != SYMBOL_REF)
34571 flags = SYMBOL_REF_FLAGS (symbol);
34573 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34574 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
34576 SYMBOL_REF_FLAGS (symbol) = flags;
34578 /* Append mapping class to extern decls. */
34579 symname = XSTR (symbol, 0);
34580 if (decl /* sync condition with assemble_external () */
34581 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
34582 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
34583 || TREE_CODE (decl) == FUNCTION_DECL)
34584 && symname[strlen (symname) - 1] != ']')
34586 char *newname = (char *) alloca (strlen (symname) + 5);
34587 strcpy (newname, symname);
34588 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
34589 ? "[DS]" : "[UA]"));
34590 XSTR (symbol, 0) = ggc_strdup (newname);
34593 #endif /* HAVE_AS_TLS */
34594 #endif /* TARGET_XCOFF */
34597 rs6000_asm_weaken_decl (FILE *stream, tree decl,
34598 const char *name, const char *val)
34600 fputs ("\t.weak\t", stream);
34601 RS6000_OUTPUT_BASENAME (stream, name);
34602 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34603 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34606 fputs ("[DS]", stream);
34607 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34609 fputs (rs6000_xcoff_visibility (decl), stream);
34611 fputs ("\n\t.weak\t.", stream);
34612 RS6000_OUTPUT_BASENAME (stream, name);
34614 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34616 fputs (rs6000_xcoff_visibility (decl), stream);
34618 fputc ('\n', stream);
34621 #ifdef ASM_OUTPUT_DEF
34622 ASM_OUTPUT_DEF (stream, name, val);
34624 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34625 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34627 fputs ("\t.set\t.", stream);
34628 RS6000_OUTPUT_BASENAME (stream, name);
34629 fputs (",.", stream);
34630 RS6000_OUTPUT_BASENAME (stream, val);
34631 fputc ('\n', stream);
34637 /* Return true if INSN should not be copied. */
34640 rs6000_cannot_copy_insn_p (rtx_insn *insn)
34642 return recog_memoized (insn) >= 0
34643 && get_attr_cannot_copy (insn);
34646 /* Compute a (partial) cost for rtx X. Return true if the complete
34647 cost has been computed, and false if subexpressions should be
34648 scanned. In either case, *TOTAL contains the cost result. */
34651 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
34652 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
34654 int code = GET_CODE (x);
34658 /* On the RS/6000, if it is valid in the insn, it is free. */
34660 if (((outer_code == SET
34661 || outer_code == PLUS
34662 || outer_code == MINUS)
34663 && (satisfies_constraint_I (x)
34664 || satisfies_constraint_L (x)))
34665 || (outer_code == AND
34666 && (satisfies_constraint_K (x)
34668 ? satisfies_constraint_L (x)
34669 : satisfies_constraint_J (x))))
34670 || ((outer_code == IOR || outer_code == XOR)
34671 && (satisfies_constraint_K (x)
34673 ? satisfies_constraint_L (x)
34674 : satisfies_constraint_J (x))))
34675 || outer_code == ASHIFT
34676 || outer_code == ASHIFTRT
34677 || outer_code == LSHIFTRT
34678 || outer_code == ROTATE
34679 || outer_code == ROTATERT
34680 || outer_code == ZERO_EXTRACT
34681 || (outer_code == MULT
34682 && satisfies_constraint_I (x))
34683 || ((outer_code == DIV || outer_code == UDIV
34684 || outer_code == MOD || outer_code == UMOD)
34685 && exact_log2 (INTVAL (x)) >= 0)
34686 || (outer_code == COMPARE
34687 && (satisfies_constraint_I (x)
34688 || satisfies_constraint_K (x)))
34689 || ((outer_code == EQ || outer_code == NE)
34690 && (satisfies_constraint_I (x)
34691 || satisfies_constraint_K (x)
34693 ? satisfies_constraint_L (x)
34694 : satisfies_constraint_J (x))))
34695 || (outer_code == GTU
34696 && satisfies_constraint_I (x))
34697 || (outer_code == LTU
34698 && satisfies_constraint_P (x)))
34703 else if ((outer_code == PLUS
34704 && reg_or_add_cint_operand (x, VOIDmode))
34705 || (outer_code == MINUS
34706 && reg_or_sub_cint_operand (x, VOIDmode))
34707 || ((outer_code == SET
34708 || outer_code == IOR
34709 || outer_code == XOR)
34711 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
34713 *total = COSTS_N_INSNS (1);
34719 case CONST_WIDE_INT:
34723 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34727 /* When optimizing for size, MEM should be slightly more expensive
34728 than generating address, e.g., (plus (reg) (const)).
34729 L1 cache latency is about two instructions. */
34730 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34731 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
34732 *total += COSTS_N_INSNS (100);
34741 if (FLOAT_MODE_P (mode))
34742 *total = rs6000_cost->fp;
34744 *total = COSTS_N_INSNS (1);
34748 if (GET_CODE (XEXP (x, 1)) == CONST_INT
34749 && satisfies_constraint_I (XEXP (x, 1)))
34751 if (INTVAL (XEXP (x, 1)) >= -256
34752 && INTVAL (XEXP (x, 1)) <= 255)
34753 *total = rs6000_cost->mulsi_const9;
34755 *total = rs6000_cost->mulsi_const;
34757 else if (mode == SFmode)
34758 *total = rs6000_cost->fp;
34759 else if (FLOAT_MODE_P (mode))
34760 *total = rs6000_cost->dmul;
34761 else if (mode == DImode)
34762 *total = rs6000_cost->muldi;
34764 *total = rs6000_cost->mulsi;
34768 if (mode == SFmode)
34769 *total = rs6000_cost->fp;
34771 *total = rs6000_cost->dmul;
34776 if (FLOAT_MODE_P (mode))
34778 *total = mode == DFmode ? rs6000_cost->ddiv
34779 : rs6000_cost->sdiv;
34786 if (GET_CODE (XEXP (x, 1)) == CONST_INT
34787 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
34789 if (code == DIV || code == MOD)
34791 *total = COSTS_N_INSNS (2);
34794 *total = COSTS_N_INSNS (1);
34798 if (GET_MODE (XEXP (x, 1)) == DImode)
34799 *total = rs6000_cost->divdi;
34801 *total = rs6000_cost->divsi;
34803 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34804 if (!TARGET_MODULO && (code == MOD || code == UMOD))
34805 *total += COSTS_N_INSNS (2);
34809 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
34813 *total = COSTS_N_INSNS (4);
34817 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
34821 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
34825 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
34828 *total = COSTS_N_INSNS (1);
34832 if (CONST_INT_P (XEXP (x, 1)))
34834 rtx left = XEXP (x, 0);
34835 rtx_code left_code = GET_CODE (left);
34837 /* rotate-and-mask: 1 insn. */
34838 if ((left_code == ROTATE
34839 || left_code == ASHIFT
34840 || left_code == LSHIFTRT)
34841 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34843 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34844 if (!CONST_INT_P (XEXP (left, 1)))
34845 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34846 *total += COSTS_N_INSNS (1);
34850 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34851 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34852 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34853 || (val & 0xffff) == val
34854 || (val & 0xffff0000) == val
34855 || ((val & 0xffff) == 0 && mode == SImode))
34857 *total = rtx_cost (left, mode, AND, 0, speed);
34858 *total += COSTS_N_INSNS (1);
34863 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34865 *total = rtx_cost (left, mode, AND, 0, speed);
34866 *total += COSTS_N_INSNS (2);
34871 *total = COSTS_N_INSNS (1);
34876 *total = COSTS_N_INSNS (1);
34882 *total = COSTS_N_INSNS (1);
34886 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34887 the sign extend and shift separately within the insn. */
34888 if (TARGET_EXTSWSLI && mode == DImode
34889 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34890 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34901 /* Handle mul_highpart. */
34902 if (outer_code == TRUNCATE
34903 && GET_CODE (XEXP (x, 0)) == MULT)
34905 if (mode == DImode)
34906 *total = rs6000_cost->muldi;
34908 *total = rs6000_cost->mulsi;
34911 else if (outer_code == AND)
34914 *total = COSTS_N_INSNS (1);
34919 if (GET_CODE (XEXP (x, 0)) == MEM)
34922 *total = COSTS_N_INSNS (1);
34928 if (!FLOAT_MODE_P (mode))
34930 *total = COSTS_N_INSNS (1);
34936 case UNSIGNED_FLOAT:
34939 case FLOAT_TRUNCATE:
34940 *total = rs6000_cost->fp;
34944 if (mode == DFmode)
34945 *total = rs6000_cost->sfdf_convert;
34947 *total = rs6000_cost->fp;
34951 switch (XINT (x, 1))
34954 *total = rs6000_cost->fp;
34966 *total = COSTS_N_INSNS (1);
34969 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
34971 *total = rs6000_cost->fp;
34980 /* Carry bit requires mode == Pmode.
34981 NEG or PLUS already counted so only add one. */
34983 && (outer_code == NEG || outer_code == PLUS))
34985 *total = COSTS_N_INSNS (1);
34993 if (outer_code == SET)
34995 if (XEXP (x, 1) == const0_rtx)
34997 *total = COSTS_N_INSNS (2);
35002 *total = COSTS_N_INSNS (3);
35007 if (outer_code == COMPARE)
35021 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
35024 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
35025 int opno, int *total, bool speed)
35027 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
35030 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
35031 "opno = %d, total = %d, speed = %s, x:\n",
35032 ret ? "complete" : "scan inner",
35033 GET_MODE_NAME (mode),
35034 GET_RTX_NAME (outer_code),
35037 speed ? "true" : "false");
35045 rs6000_insn_cost (rtx_insn *insn, bool speed)
35047 if (recog_memoized (insn) < 0)
35051 return get_attr_length (insn);
35053 int cost = get_attr_cost (insn);
35057 int n = get_attr_length (insn) / 4;
35058 enum attr_type type = get_attr_type (insn);
35065 cost = COSTS_N_INSNS (n + 1);
35069 switch (get_attr_size (insn))
35072 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
35075 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
35078 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
35081 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
35084 gcc_unreachable ();
35088 switch (get_attr_size (insn))
35091 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
35094 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
35097 gcc_unreachable ();
35102 cost = n * rs6000_cost->fp;
35105 cost = n * rs6000_cost->dmul;
35108 cost = n * rs6000_cost->sdiv;
35111 cost = n * rs6000_cost->ddiv;
35118 cost = COSTS_N_INSNS (n + 2);
35122 cost = COSTS_N_INSNS (n);
35128 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
35131 rs6000_debug_address_cost (rtx x, machine_mode mode,
35132 addr_space_t as, bool speed)
35134 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
35136 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
35137 ret, speed ? "true" : "false");
35144 /* A C expression returning the cost of moving data from a register of class
35145 CLASS1 to one of CLASS2. */
35148 rs6000_register_move_cost (machine_mode mode,
35149 reg_class_t from, reg_class_t to)
35153 if (TARGET_DEBUG_COST)
35156 /* Moves from/to GENERAL_REGS. */
35157 if (reg_classes_intersect_p (to, GENERAL_REGS)
35158 || reg_classes_intersect_p (from, GENERAL_REGS))
35160 reg_class_t rclass = from;
35162 if (! reg_classes_intersect_p (to, GENERAL_REGS))
35165 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
35166 ret = (rs6000_memory_move_cost (mode, rclass, false)
35167 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
35169 /* It's more expensive to move CR_REGS than CR0_REGS because of the
35171 else if (rclass == CR_REGS)
35174 /* For those processors that have slow LR/CTR moves, make them more
35175 expensive than memory in order to bias spills to memory .*/
35176 else if ((rs6000_tune == PROCESSOR_POWER6
35177 || rs6000_tune == PROCESSOR_POWER7
35178 || rs6000_tune == PROCESSOR_POWER8
35179 || rs6000_tune == PROCESSOR_POWER9)
35180 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
35181 ret = 6 * hard_regno_nregs (0, mode);
35184 /* A move will cost one instruction per GPR moved. */
35185 ret = 2 * hard_regno_nregs (0, mode);
35188 /* If we have VSX, we can easily move between FPR or Altivec registers. */
35189 else if (VECTOR_MEM_VSX_P (mode)
35190 && reg_classes_intersect_p (to, VSX_REGS)
35191 && reg_classes_intersect_p (from, VSX_REGS))
35192 ret = 2 * hard_regno_nregs (FIRST_FPR_REGNO, mode);
35194 /* Moving between two similar registers is just one instruction. */
35195 else if (reg_classes_intersect_p (to, from))
35196 ret = (FLOAT128_2REG_P (mode)) ? 4 : 2;
35198 /* Everything else has to go through GENERAL_REGS. */
35200 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
35201 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
35203 if (TARGET_DEBUG_COST)
35205 if (dbg_cost_ctrl == 1)
35207 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
35208 ret, GET_MODE_NAME (mode), reg_class_names[from],
35209 reg_class_names[to]);
35216 /* A C expressions returning the cost of moving data of MODE from a register to
35220 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
35221 bool in ATTRIBUTE_UNUSED)
35225 if (TARGET_DEBUG_COST)
35228 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
35229 ret = 4 * hard_regno_nregs (0, mode);
35230 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
35231 || reg_classes_intersect_p (rclass, VSX_REGS)))
35232 ret = 4 * hard_regno_nregs (32, mode);
35233 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
35234 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
35236 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
35238 if (TARGET_DEBUG_COST)
35240 if (dbg_cost_ctrl == 1)
35242 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
35243 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
35250 /* Returns a code for a target-specific builtin that implements
35251 reciprocal of the function, or NULL_TREE if not available. */
35254 rs6000_builtin_reciprocal (tree fndecl)
35256 switch (DECL_FUNCTION_CODE (fndecl))
35258 case VSX_BUILTIN_XVSQRTDP:
35259 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
35262 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
35264 case VSX_BUILTIN_XVSQRTSP:
35265 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
35268 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
35275 /* Load up a constant. If the mode is a vector mode, splat the value across
35276 all of the vector elements. */
35279 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
35283 if (mode == SFmode || mode == DFmode)
35285 rtx d = const_double_from_real_value (dconst, mode);
35286 reg = force_reg (mode, d);
35288 else if (mode == V4SFmode)
35290 rtx d = const_double_from_real_value (dconst, SFmode);
35291 rtvec v = gen_rtvec (4, d, d, d, d);
35292 reg = gen_reg_rtx (mode);
35293 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
35295 else if (mode == V2DFmode)
35297 rtx d = const_double_from_real_value (dconst, DFmode);
35298 rtvec v = gen_rtvec (2, d, d);
35299 reg = gen_reg_rtx (mode);
35300 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
35303 gcc_unreachable ();
35308 /* Generate an FMA instruction. */
35311 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
35313 machine_mode mode = GET_MODE (target);
35316 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
35317 gcc_assert (dst != NULL);
35320 emit_move_insn (target, dst);
35323 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
35326 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
35328 machine_mode mode = GET_MODE (dst);
35331 /* This is a tad more complicated, since the fnma_optab is for
35332 a different expression: fma(-m1, m2, a), which is the same
35333 thing except in the case of signed zeros.
35335 Fortunately we know that if FMA is supported that FNMSUB is
35336 also supported in the ISA. Just expand it directly. */
35338 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
35340 r = gen_rtx_NEG (mode, a);
35341 r = gen_rtx_FMA (mode, m1, m2, r);
35342 r = gen_rtx_NEG (mode, r);
35343 emit_insn (gen_rtx_SET (dst, r));
35346 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
35347 add a reg_note saying that this was a division. Support both scalar and
35348 vector divide. Assumes no trapping math and finite arguments. */
35351 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
35353 machine_mode mode = GET_MODE (dst);
35354 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
35357 /* Low precision estimates guarantee 5 bits of accuracy. High
35358 precision estimates guarantee 14 bits of accuracy. SFmode
35359 requires 23 bits of accuracy. DFmode requires 52 bits of
35360 accuracy. Each pass at least doubles the accuracy, leading
35361 to the following. */
35362 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35363 if (mode == DFmode || mode == V2DFmode)
35366 enum insn_code code = optab_handler (smul_optab, mode);
35367 insn_gen_fn gen_mul = GEN_FCN (code);
35369 gcc_assert (code != CODE_FOR_nothing);
35371 one = rs6000_load_constant_and_splat (mode, dconst1);
35373 /* x0 = 1./d estimate */
35374 x0 = gen_reg_rtx (mode);
35375 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
35378 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
35381 /* e0 = 1. - d * x0 */
35382 e0 = gen_reg_rtx (mode);
35383 rs6000_emit_nmsub (e0, d, x0, one);
35385 /* x1 = x0 + e0 * x0 */
35386 x1 = gen_reg_rtx (mode);
35387 rs6000_emit_madd (x1, e0, x0, x0);
35389 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
35390 ++i, xprev = xnext, eprev = enext) {
35392 /* enext = eprev * eprev */
35393 enext = gen_reg_rtx (mode);
35394 emit_insn (gen_mul (enext, eprev, eprev));
35396 /* xnext = xprev + enext * xprev */
35397 xnext = gen_reg_rtx (mode);
35398 rs6000_emit_madd (xnext, enext, xprev, xprev);
35404 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
35406 /* u = n * xprev */
35407 u = gen_reg_rtx (mode);
35408 emit_insn (gen_mul (u, n, xprev));
35410 /* v = n - (d * u) */
35411 v = gen_reg_rtx (mode);
35412 rs6000_emit_nmsub (v, d, u, n);
35414 /* dst = (v * xprev) + u */
35415 rs6000_emit_madd (dst, v, xprev, u);
35418 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
35421 /* Goldschmidt's Algorithm for single/double-precision floating point
35422 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
35425 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
35427 machine_mode mode = GET_MODE (src);
35428 rtx e = gen_reg_rtx (mode);
35429 rtx g = gen_reg_rtx (mode);
35430 rtx h = gen_reg_rtx (mode);
35432 /* Low precision estimates guarantee 5 bits of accuracy. High
35433 precision estimates guarantee 14 bits of accuracy. SFmode
35434 requires 23 bits of accuracy. DFmode requires 52 bits of
35435 accuracy. Each pass at least doubles the accuracy, leading
35436 to the following. */
35437 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35438 if (mode == DFmode || mode == V2DFmode)
35443 enum insn_code code = optab_handler (smul_optab, mode);
35444 insn_gen_fn gen_mul = GEN_FCN (code);
35446 gcc_assert (code != CODE_FOR_nothing);
35448 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
35450 /* e = rsqrt estimate */
35451 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
35454 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
35457 rtx zero = force_reg (mode, CONST0_RTX (mode));
35459 if (mode == SFmode)
35461 rtx target = emit_conditional_move (e, GT, src, zero, mode,
35464 emit_move_insn (e, target);
35468 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
35469 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
35473 /* g = sqrt estimate. */
35474 emit_insn (gen_mul (g, e, src));
35475 /* h = 1/(2*sqrt) estimate. */
35476 emit_insn (gen_mul (h, e, mhalf));
35482 rtx t = gen_reg_rtx (mode);
35483 rs6000_emit_nmsub (t, g, h, mhalf);
35484 /* Apply correction directly to 1/rsqrt estimate. */
35485 rs6000_emit_madd (dst, e, t, e);
35489 for (i = 0; i < passes; i++)
35491 rtx t1 = gen_reg_rtx (mode);
35492 rtx g1 = gen_reg_rtx (mode);
35493 rtx h1 = gen_reg_rtx (mode);
35495 rs6000_emit_nmsub (t1, g, h, mhalf);
35496 rs6000_emit_madd (g1, g, t1, g);
35497 rs6000_emit_madd (h1, h, t1, h);
35502 /* Multiply by 2 for 1/rsqrt. */
35503 emit_insn (gen_add3_insn (dst, h, h));
35508 rtx t = gen_reg_rtx (mode);
35509 rs6000_emit_nmsub (t, g, h, mhalf);
35510 rs6000_emit_madd (dst, g, t, g);
35516 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
35517 (Power7) targets. DST is the target, and SRC is the argument operand. */
35520 rs6000_emit_popcount (rtx dst, rtx src)
35522 machine_mode mode = GET_MODE (dst);
35525 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
35526 if (TARGET_POPCNTD)
35528 if (mode == SImode)
35529 emit_insn (gen_popcntdsi2 (dst, src));
35531 emit_insn (gen_popcntddi2 (dst, src));
35535 tmp1 = gen_reg_rtx (mode);
35537 if (mode == SImode)
35539 emit_insn (gen_popcntbsi2 (tmp1, src));
35540 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
35542 tmp2 = force_reg (SImode, tmp2);
35543 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
35547 emit_insn (gen_popcntbdi2 (tmp1, src));
35548 tmp2 = expand_mult (DImode, tmp1,
35549 GEN_INT ((HOST_WIDE_INT)
35550 0x01010101 << 32 | 0x01010101),
35552 tmp2 = force_reg (DImode, tmp2);
35553 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
35558 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35559 target, and SRC is the argument operand. */
35562 rs6000_emit_parity (rtx dst, rtx src)
35564 machine_mode mode = GET_MODE (dst);
35567 tmp = gen_reg_rtx (mode);
35569 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35572 if (mode == SImode)
35574 emit_insn (gen_popcntbsi2 (tmp, src));
35575 emit_insn (gen_paritysi2_cmpb (dst, tmp));
35579 emit_insn (gen_popcntbdi2 (tmp, src));
35580 emit_insn (gen_paritydi2_cmpb (dst, tmp));
35585 if (mode == SImode)
35587 /* Is mult+shift >= shift+xor+shift+xor? */
35588 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
35590 rtx tmp1, tmp2, tmp3, tmp4;
35592 tmp1 = gen_reg_rtx (SImode);
35593 emit_insn (gen_popcntbsi2 (tmp1, src));
35595 tmp2 = gen_reg_rtx (SImode);
35596 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
35597 tmp3 = gen_reg_rtx (SImode);
35598 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
35600 tmp4 = gen_reg_rtx (SImode);
35601 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
35602 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
35605 rs6000_emit_popcount (tmp, src);
35606 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
35610 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35611 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
35613 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
35615 tmp1 = gen_reg_rtx (DImode);
35616 emit_insn (gen_popcntbdi2 (tmp1, src));
35618 tmp2 = gen_reg_rtx (DImode);
35619 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
35620 tmp3 = gen_reg_rtx (DImode);
35621 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
35623 tmp4 = gen_reg_rtx (DImode);
35624 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
35625 tmp5 = gen_reg_rtx (DImode);
35626 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
35628 tmp6 = gen_reg_rtx (DImode);
35629 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
35630 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
35633 rs6000_emit_popcount (tmp, src);
35634 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
35638 /* Expand an Altivec constant permutation for little endian mode.
35639 OP0 and OP1 are the input vectors and TARGET is the output vector.
35640 SEL specifies the constant permutation vector.
35642 There are two issues: First, the two input operands must be
35643 swapped so that together they form a double-wide array in LE
35644 order. Second, the vperm instruction has surprising behavior
35645 in LE mode: it interprets the elements of the source vectors
35646 in BE mode ("left to right") and interprets the elements of
35647 the destination vector in LE mode ("right to left"). To
35648 correct for this, we must subtract each element of the permute
35649 control vector from 31.
35651 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35652 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35653 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35654 serve as the permute control vector. Then, in BE mode,
35658 places the desired result in vr9. However, in LE mode the
35659 vector contents will be
35661 vr10 = 00000003 00000002 00000001 00000000
35662 vr11 = 00000007 00000006 00000005 00000004
35664 The result of the vperm using the same permute control vector is
35666 vr9 = 05000000 07000000 01000000 03000000
35668 That is, the leftmost 4 bytes of vr10 are interpreted as the
35669 source for the rightmost 4 bytes of vr9, and so on.
35671 If we change the permute control vector to
35673 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35681 vr9 = 00000006 00000004 00000002 00000000. */
35684 altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
35685 const vec_perm_indices &sel)
35689 rtx constv, unspec;
35691 /* Unpack and adjust the constant selector. */
35692 for (i = 0; i < 16; ++i)
35694 unsigned int elt = 31 - (sel[i] & 31);
35695 perm[i] = GEN_INT (elt);
35698 /* Expand to a permute, swapping the inputs and using the
35699 adjusted selector. */
35701 op0 = force_reg (V16QImode, op0);
35703 op1 = force_reg (V16QImode, op1);
35705 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
35706 constv = force_reg (V16QImode, constv);
35707 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
35709 if (!REG_P (target))
35711 rtx tmp = gen_reg_rtx (V16QImode);
35712 emit_move_insn (tmp, unspec);
35716 emit_move_insn (target, unspec);
35719 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35720 permute control vector. But here it's not a constant, so we must
35721 generate a vector NAND or NOR to do the adjustment. */
35724 altivec_expand_vec_perm_le (rtx operands[4])
35726 rtx notx, iorx, unspec;
35727 rtx target = operands[0];
35728 rtx op0 = operands[1];
35729 rtx op1 = operands[2];
35730 rtx sel = operands[3];
35732 rtx norreg = gen_reg_rtx (V16QImode);
35733 machine_mode mode = GET_MODE (target);
35735 /* Get everything in regs so the pattern matches. */
35737 op0 = force_reg (mode, op0);
35739 op1 = force_reg (mode, op1);
35741 sel = force_reg (V16QImode, sel);
35742 if (!REG_P (target))
35743 tmp = gen_reg_rtx (mode);
35745 if (TARGET_P9_VECTOR)
35747 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
35752 /* Invert the selector with a VNAND if available, else a VNOR.
35753 The VNAND is preferred for future fusion opportunities. */
35754 notx = gen_rtx_NOT (V16QImode, sel);
35755 iorx = (TARGET_P8_VECTOR
35756 ? gen_rtx_IOR (V16QImode, notx, notx)
35757 : gen_rtx_AND (V16QImode, notx, notx));
35758 emit_insn (gen_rtx_SET (norreg, iorx));
35760 /* Permute with operands reversed and adjusted selector. */
35761 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
35765 /* Copy into target, possibly by way of a register. */
35766 if (!REG_P (target))
35768 emit_move_insn (tmp, unspec);
35772 emit_move_insn (target, unspec);
35775 /* Expand an Altivec constant permutation. Return true if we match
35776 an efficient implementation; false to fall back to VPERM.
35778 OP0 and OP1 are the input vectors and TARGET is the output vector.
35779 SEL specifies the constant permutation vector. */
35782 altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
35783 const vec_perm_indices &sel)
35785 struct altivec_perm_insn {
35786 HOST_WIDE_INT mask;
35787 enum insn_code impl;
35788 unsigned char perm[16];
35790 static const struct altivec_perm_insn patterns[] = {
35791 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
35792 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35793 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
35794 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35795 { OPTION_MASK_ALTIVEC,
35796 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
35797 : CODE_FOR_altivec_vmrglb_direct),
35798 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35799 { OPTION_MASK_ALTIVEC,
35800 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
35801 : CODE_FOR_altivec_vmrglh_direct),
35802 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35803 { OPTION_MASK_ALTIVEC,
35804 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
35805 : CODE_FOR_altivec_vmrglw_direct),
35806 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35807 { OPTION_MASK_ALTIVEC,
35808 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
35809 : CODE_FOR_altivec_vmrghb_direct),
35810 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35811 { OPTION_MASK_ALTIVEC,
35812 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
35813 : CODE_FOR_altivec_vmrghh_direct),
35814 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35815 { OPTION_MASK_ALTIVEC,
35816 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
35817 : CODE_FOR_altivec_vmrghw_direct),
35818 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35819 { OPTION_MASK_P8_VECTOR,
35820 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
35821 : CODE_FOR_p8_vmrgow_v4sf_direct),
35822 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35823 { OPTION_MASK_P8_VECTOR,
35824 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
35825 : CODE_FOR_p8_vmrgew_v4sf_direct),
35826 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35829 unsigned int i, j, elt, which;
35830 unsigned char perm[16];
35834 /* Unpack the constant selector. */
35835 for (i = which = 0; i < 16; ++i)
35838 which |= (elt < 16 ? 1 : 2);
35842 /* Simplify the constant selector based on operands. */
35846 gcc_unreachable ();
35850 if (!rtx_equal_p (op0, op1))
35855 for (i = 0; i < 16; ++i)
35867 /* Look for splat patterns. */
35872 for (i = 0; i < 16; ++i)
35873 if (perm[i] != elt)
35877 if (!BYTES_BIG_ENDIAN)
35879 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35885 for (i = 0; i < 16; i += 2)
35886 if (perm[i] != elt || perm[i + 1] != elt + 1)
35890 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35891 x = gen_reg_rtx (V8HImode);
35892 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35894 emit_move_insn (target, gen_lowpart (V16QImode, x));
35901 for (i = 0; i < 16; i += 4)
35903 || perm[i + 1] != elt + 1
35904 || perm[i + 2] != elt + 2
35905 || perm[i + 3] != elt + 3)
35909 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35910 x = gen_reg_rtx (V4SImode);
35911 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35913 emit_move_insn (target, gen_lowpart (V16QImode, x));
35919 /* Look for merge and pack patterns. */
35920 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35924 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35927 elt = patterns[j].perm[0];
35928 if (perm[0] == elt)
35930 else if (perm[0] == elt + 16)
35934 for (i = 1; i < 16; ++i)
35936 elt = patterns[j].perm[i];
35938 elt = (elt >= 16 ? elt - 16 : elt + 16);
35939 else if (one_vec && elt >= 16)
35941 if (perm[i] != elt)
35946 enum insn_code icode = patterns[j].impl;
35947 machine_mode omode = insn_data[icode].operand[0].mode;
35948 machine_mode imode = insn_data[icode].operand[1].mode;
35950 /* For little-endian, don't use vpkuwum and vpkuhum if the
35951 underlying vector type is not V4SI and V8HI, respectively.
35952 For example, using vpkuwum with a V8HI picks up the even
35953 halfwords (BE numbering) when the even halfwords (LE
35954 numbering) are what we need. */
35955 if (!BYTES_BIG_ENDIAN
35956 && icode == CODE_FOR_altivec_vpkuwum_direct
35957 && ((GET_CODE (op0) == REG
35958 && GET_MODE (op0) != V4SImode)
35959 || (GET_CODE (op0) == SUBREG
35960 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
35962 if (!BYTES_BIG_ENDIAN
35963 && icode == CODE_FOR_altivec_vpkuhum_direct
35964 && ((GET_CODE (op0) == REG
35965 && GET_MODE (op0) != V8HImode)
35966 || (GET_CODE (op0) == SUBREG
35967 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
35970 /* For little-endian, the two input operands must be swapped
35971 (or swapped back) to ensure proper right-to-left numbering
35973 if (swapped ^ !BYTES_BIG_ENDIAN)
35974 std::swap (op0, op1);
35975 if (imode != V16QImode)
35977 op0 = gen_lowpart (imode, op0);
35978 op1 = gen_lowpart (imode, op1);
35980 if (omode == V16QImode)
35983 x = gen_reg_rtx (omode);
35984 emit_insn (GEN_FCN (icode) (x, op0, op1));
35985 if (omode != V16QImode)
35986 emit_move_insn (target, gen_lowpart (V16QImode, x));
35991 if (!BYTES_BIG_ENDIAN)
35993 altivec_expand_vec_perm_const_le (target, op0, op1, sel);
36000 /* Expand a Paired Single or VSX Permute Doubleword constant permutation.
36001 Return true if we match an efficient implementation. */
36004 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
36005 unsigned char perm0, unsigned char perm1)
36009 /* If both selectors come from the same operand, fold to single op. */
36010 if ((perm0 & 2) == (perm1 & 2))
36017 /* If both operands are equal, fold to simpler permutation. */
36018 if (rtx_equal_p (op0, op1))
36021 perm1 = (perm1 & 1) + 2;
36023 /* If the first selector comes from the second operand, swap. */
36024 else if (perm0 & 2)
36030 std::swap (op0, op1);
36032 /* If the second selector does not come from the second operand, fail. */
36033 else if ((perm1 & 2) == 0)
36037 if (target != NULL)
36039 machine_mode vmode, dmode;
36042 vmode = GET_MODE (target);
36043 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
36044 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
36045 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
36046 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
36047 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
36048 emit_insn (gen_rtx_SET (target, x));
36053 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
36056 rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
36057 rtx op1, const vec_perm_indices &sel)
36059 bool testing_p = !target;
36061 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
36062 if (TARGET_ALTIVEC && testing_p)
36065 /* Check for ps_merge* or xxpermdi insns. */
36066 if ((vmode == V2SFmode && TARGET_PAIRED_FLOAT)
36067 || ((vmode == V2DFmode || vmode == V2DImode)
36068 && VECTOR_MEM_VSX_P (vmode)))
36072 op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
36073 op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
36075 if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
36079 if (TARGET_ALTIVEC)
36081 /* Force the target-independent code to lower to V16QImode. */
36082 if (vmode != V16QImode)
36084 if (altivec_expand_vec_perm_const (target, op0, op1, sel))
36091 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
36092 OP0 and OP1 are the input vectors and TARGET is the output vector.
36093 PERM specifies the constant permutation vector. */
36096 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
36097 machine_mode vmode, const vec_perm_builder &perm)
36099 rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
36101 emit_move_insn (target, x);
36104 /* Expand an extract even operation. */
36107 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
36109 machine_mode vmode = GET_MODE (target);
36110 unsigned i, nelt = GET_MODE_NUNITS (vmode);
36111 vec_perm_builder perm (nelt, nelt, 1);
36113 for (i = 0; i < nelt; i++)
36114 perm.quick_push (i * 2);
36116 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
36119 /* Expand a vector interleave operation. */
36122 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
36124 machine_mode vmode = GET_MODE (target);
36125 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
36126 vec_perm_builder perm (nelt, nelt, 1);
36128 high = (highp ? 0 : nelt / 2);
36129 for (i = 0; i < nelt / 2; i++)
36131 perm.quick_push (i + high);
36132 perm.quick_push (i + nelt + high);
36135 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
36138 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
36140 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
36142 HOST_WIDE_INT hwi_scale (scale);
36143 REAL_VALUE_TYPE r_pow;
36144 rtvec v = rtvec_alloc (2);
36146 rtx scale_vec = gen_reg_rtx (V2DFmode);
36147 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
36148 elt = const_double_from_real_value (r_pow, DFmode);
36149 RTVEC_ELT (v, 0) = elt;
36150 RTVEC_ELT (v, 1) = elt;
36151 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
36152 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
36155 /* Return an RTX representing where to find the function value of a
36156 function returning MODE. */
36158 rs6000_complex_function_value (machine_mode mode)
36160 unsigned int regno;
36162 machine_mode inner = GET_MODE_INNER (mode);
36163 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
36165 if (TARGET_FLOAT128_TYPE
36167 || (mode == TCmode && TARGET_IEEEQUAD)))
36168 regno = ALTIVEC_ARG_RETURN;
36170 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36171 regno = FP_ARG_RETURN;
36175 regno = GP_ARG_RETURN;
36177 /* 32-bit is OK since it'll go in r3/r4. */
36178 if (TARGET_32BIT && inner_bytes >= 4)
36179 return gen_rtx_REG (mode, regno);
36182 if (inner_bytes >= 8)
36183 return gen_rtx_REG (mode, regno);
36185 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
36187 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
36188 GEN_INT (inner_bytes));
36189 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
36192 /* Return an rtx describing a return value of MODE as a PARALLEL
36193 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
36194 stride REG_STRIDE. */
36197 rs6000_parallel_return (machine_mode mode,
36198 int n_elts, machine_mode elt_mode,
36199 unsigned int regno, unsigned int reg_stride)
36201 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
36204 for (i = 0; i < n_elts; i++)
36206 rtx r = gen_rtx_REG (elt_mode, regno);
36207 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
36208 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
36209 regno += reg_stride;
36215 /* Target hook for TARGET_FUNCTION_VALUE.
36217 An integer value is in r3 and a floating-point value is in fp1,
36218 unless -msoft-float. */
36221 rs6000_function_value (const_tree valtype,
36222 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
36223 bool outgoing ATTRIBUTE_UNUSED)
36226 unsigned int regno;
36227 machine_mode elt_mode;
36230 /* Special handling for structs in darwin64. */
36232 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
36234 CUMULATIVE_ARGS valcum;
36238 valcum.fregno = FP_ARG_MIN_REG;
36239 valcum.vregno = ALTIVEC_ARG_MIN_REG;
36240 /* Do a trial code generation as if this were going to be passed as
36241 an argument; if any part goes in memory, we return NULL. */
36242 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
36245 /* Otherwise fall through to standard ABI rules. */
36248 mode = TYPE_MODE (valtype);
36250 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
36251 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
36253 int first_reg, n_regs;
36255 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
36257 /* _Decimal128 must use even/odd register pairs. */
36258 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36259 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
36263 first_reg = ALTIVEC_ARG_RETURN;
36267 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
36270 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
36271 if (TARGET_32BIT && TARGET_POWERPC64)
36280 int count = GET_MODE_SIZE (mode) / 4;
36281 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
36284 if ((INTEGRAL_TYPE_P (valtype)
36285 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
36286 || POINTER_TYPE_P (valtype))
36287 mode = TARGET_32BIT ? SImode : DImode;
36289 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36290 /* _Decimal128 must use an even/odd register pair. */
36291 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36292 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
36293 && !FLOAT128_VECTOR_P (mode)
36294 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
36295 regno = FP_ARG_RETURN;
36296 else if (TREE_CODE (valtype) == COMPLEX_TYPE
36297 && targetm.calls.split_complex_arg)
36298 return rs6000_complex_function_value (mode);
36299 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36300 return register is used in both cases, and we won't see V2DImode/V2DFmode
36301 for pure altivec, combine the two cases. */
36302 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
36303 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
36304 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
36305 regno = ALTIVEC_ARG_RETURN;
36307 regno = GP_ARG_RETURN;
36309 return gen_rtx_REG (mode, regno);
36312 /* Define how to find the value returned by a library function
36313 assuming the value has mode MODE. */
36315 rs6000_libcall_value (machine_mode mode)
36317 unsigned int regno;
36319 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
36320 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
36321 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
36323 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36324 /* _Decimal128 must use an even/odd register pair. */
36325 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36326 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode)
36327 && TARGET_HARD_FLOAT
36328 && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
36329 regno = FP_ARG_RETURN;
36330 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36331 return register is used in both cases, and we won't see V2DImode/V2DFmode
36332 for pure altivec, combine the two cases. */
36333 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
36334 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
36335 regno = ALTIVEC_ARG_RETURN;
36336 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
36337 return rs6000_complex_function_value (mode);
36339 regno = GP_ARG_RETURN;
36341 return gen_rtx_REG (mode, regno);
36344 /* Compute register pressure classes. We implement the target hook to avoid
36345 IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
36346 lead to incorrect estimates of number of available registers and therefor
36347 increased register pressure/spill. */
36349 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
36354 pressure_classes[n++] = GENERAL_REGS;
36356 pressure_classes[n++] = VSX_REGS;
36359 if (TARGET_ALTIVEC)
36360 pressure_classes[n++] = ALTIVEC_REGS;
36361 if (TARGET_HARD_FLOAT)
36362 pressure_classes[n++] = FLOAT_REGS;
36364 pressure_classes[n++] = CR_REGS;
36365 pressure_classes[n++] = SPECIAL_REGS;
36370 /* Given FROM and TO register numbers, say whether this elimination is allowed.
36371 Frame pointer elimination is automatically handled.
36373 For the RS/6000, if frame pointer elimination is being done, we would like
36374 to convert ap into fp, not sp.
36376 We need r30 if -mminimal-toc was specified, and there are constant pool
36380 rs6000_can_eliminate (const int from, const int to)
36382 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
36383 ? ! frame_pointer_needed
36384 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
36385 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
36386 || constant_pool_empty_p ()
36390 /* Define the offset between two registers, FROM to be eliminated and its
36391 replacement TO, at the start of a routine. */
36393 rs6000_initial_elimination_offset (int from, int to)
36395 rs6000_stack_t *info = rs6000_stack_info ();
36396 HOST_WIDE_INT offset;
36398 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36399 offset = info->push_p ? 0 : -info->total_size;
36400 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36402 offset = info->push_p ? 0 : -info->total_size;
36403 if (FRAME_GROWS_DOWNWARD)
36404 offset += info->fixed_size + info->vars_size + info->parm_size;
36406 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
36407 offset = FRAME_GROWS_DOWNWARD
36408 ? info->fixed_size + info->vars_size + info->parm_size
36410 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
36411 offset = info->total_size;
36412 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36413 offset = info->push_p ? info->total_size : 0;
36414 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
36417 gcc_unreachable ();
36422 /* Fill in sizes of registers used by unwinder. */
36425 rs6000_init_dwarf_reg_sizes_extra (tree address)
36427 if (TARGET_MACHO && ! TARGET_ALTIVEC)
36430 machine_mode mode = TYPE_MODE (char_type_node);
36431 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
36432 rtx mem = gen_rtx_MEM (BLKmode, addr);
36433 rtx value = gen_int_mode (16, mode);
36435 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
36436 The unwinder still needs to know the size of Altivec registers. */
36438 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
36440 int column = DWARF_REG_TO_UNWIND_COLUMN
36441 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
36442 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
36444 emit_move_insn (adjust_address (mem, mode, offset), value);
36449 /* Map internal gcc register numbers to debug format register numbers.
36450 FORMAT specifies the type of debug register number to use:
36451 0 -- debug information, except for frame-related sections
36452 1 -- DWARF .debug_frame section
36453 2 -- DWARF .eh_frame section */
36456 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
36458 /* Except for the above, we use the internal number for non-DWARF
36459 debug information, and also for .eh_frame. */
36460 if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2)
36463 /* On some platforms, we use the standard DWARF register
36464 numbering for .debug_info and .debug_frame. */
36465 #ifdef RS6000_USE_DWARF_NUMBERING
36468 if (regno == LR_REGNO)
36470 if (regno == CTR_REGNO)
36472 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
36473 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
36474 The actual code emitted saves the whole of CR, so we map CR2_REGNO
36475 to the DWARF reg for CR. */
36476 if (format == 1 && regno == CR2_REGNO)
36478 if (CR_REGNO_P (regno))
36479 return regno - CR0_REGNO + 86;
36480 if (regno == CA_REGNO)
36481 return 101; /* XER */
36482 if (ALTIVEC_REGNO_P (regno))
36483 return regno - FIRST_ALTIVEC_REGNO + 1124;
36484 if (regno == VRSAVE_REGNO)
36486 if (regno == VSCR_REGNO)
36492 /* target hook eh_return_filter_mode */
36493 static scalar_int_mode
36494 rs6000_eh_return_filter_mode (void)
36496 return TARGET_32BIT ? SImode : word_mode;
36499 /* Target hook for scalar_mode_supported_p. */
36501 rs6000_scalar_mode_supported_p (scalar_mode mode)
36503 /* -m32 does not support TImode. This is the default, from
36504 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
36505 same ABI as for -m32. But default_scalar_mode_supported_p allows
36506 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
36507 for -mpowerpc64. */
36508 if (TARGET_32BIT && mode == TImode)
36511 if (DECIMAL_FLOAT_MODE_P (mode))
36512 return default_decimal_float_supported_p ();
36513 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
36516 return default_scalar_mode_supported_p (mode);
36519 /* Target hook for vector_mode_supported_p. */
36521 rs6000_vector_mode_supported_p (machine_mode mode)
36524 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
36527 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36528 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36530 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
36537 /* Target hook for floatn_mode. */
36538 static opt_scalar_float_mode
36539 rs6000_floatn_mode (int n, bool extended)
36549 if (TARGET_FLOAT128_TYPE)
36550 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36552 return opt_scalar_float_mode ();
36555 return opt_scalar_float_mode ();
36558 /* Those are the only valid _FloatNx types. */
36559 gcc_unreachable ();
36573 if (TARGET_FLOAT128_TYPE)
36574 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36576 return opt_scalar_float_mode ();
36579 return opt_scalar_float_mode ();
36585 /* Target hook for c_mode_for_suffix. */
36586 static machine_mode
36587 rs6000_c_mode_for_suffix (char suffix)
36589 if (TARGET_FLOAT128_TYPE)
36591 if (suffix == 'q' || suffix == 'Q')
36592 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36594 /* At the moment, we are not defining a suffix for IBM extended double.
36595 If/when the default for -mabi=ieeelongdouble is changed, and we want
36596 to support __ibm128 constants in legacy library code, we may need to
36597 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36598 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36599 __float80 constants. */
36605 /* Target hook for invalid_arg_for_unprototyped_fn. */
36606 static const char *
36607 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
36609 return (!rs6000_darwin64_abi
36611 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
36612 && (funcdecl == NULL_TREE
36613 || (TREE_CODE (funcdecl) == FUNCTION_DECL
36614 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
36615 ? N_("AltiVec argument passed to unprototyped function")
36619 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36620 setup by using __stack_chk_fail_local hidden function instead of
36621 calling __stack_chk_fail directly. Otherwise it is better to call
36622 __stack_chk_fail directly. */
36624 static tree ATTRIBUTE_UNUSED
36625 rs6000_stack_protect_fail (void)
36627 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
36628 ? default_hidden_stack_protect_fail ()
36629 : default_external_stack_protect_fail ();
36632 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36635 static unsigned HOST_WIDE_INT
36636 rs6000_asan_shadow_offset (void)
36638 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
36642 /* Mask options that we want to support inside of attribute((target)) and
36643 #pragma GCC target operations. Note, we do not include things like
36644 64/32-bit, endianness, hard/soft floating point, etc. that would have
36645 different calling sequences. */
36647 struct rs6000_opt_mask {
36648 const char *name; /* option name */
36649 HOST_WIDE_INT mask; /* mask to set */
36650 bool invert; /* invert sense of mask */
36651 bool valid_target; /* option is a target option */
36654 static struct rs6000_opt_mask const rs6000_opt_masks[] =
36656 { "altivec", OPTION_MASK_ALTIVEC, false, true },
36657 { "cmpb", OPTION_MASK_CMPB, false, true },
36658 { "crypto", OPTION_MASK_CRYPTO, false, true },
36659 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
36660 { "dlmzb", OPTION_MASK_DLMZB, false, true },
36661 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
36663 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
36664 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
36665 { "fprnd", OPTION_MASK_FPRND, false, true },
36666 { "hard-dfp", OPTION_MASK_DFP, false, true },
36667 { "htm", OPTION_MASK_HTM, false, true },
36668 { "isel", OPTION_MASK_ISEL, false, true },
36669 { "mfcrf", OPTION_MASK_MFCRF, false, true },
36670 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
36671 { "modulo", OPTION_MASK_MODULO, false, true },
36672 { "mulhw", OPTION_MASK_MULHW, false, true },
36673 { "multiple", OPTION_MASK_MULTIPLE, false, true },
36674 { "popcntb", OPTION_MASK_POPCNTB, false, true },
36675 { "popcntd", OPTION_MASK_POPCNTD, false, true },
36676 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
36677 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
36678 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
36679 { "power9-fusion", OPTION_MASK_P9_FUSION, false, true },
36680 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
36681 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
36682 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
36683 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
36684 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
36685 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
36686 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
36687 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
36688 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
36689 { "string", 0, false, true },
36690 { "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
36691 { "update", OPTION_MASK_NO_UPDATE, true , true },
36692 { "vsx", OPTION_MASK_VSX, false, true },
36693 #ifdef OPTION_MASK_64BIT
36695 { "aix64", OPTION_MASK_64BIT, false, false },
36696 { "aix32", OPTION_MASK_64BIT, true, false },
36698 { "64", OPTION_MASK_64BIT, false, false },
36699 { "32", OPTION_MASK_64BIT, true, false },
36702 #ifdef OPTION_MASK_EABI
36703 { "eabi", OPTION_MASK_EABI, false, false },
36705 #ifdef OPTION_MASK_LITTLE_ENDIAN
36706 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
36707 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
36709 #ifdef OPTION_MASK_RELOCATABLE
36710 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
36712 #ifdef OPTION_MASK_STRICT_ALIGN
36713 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
36715 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
36716 { "string", 0, false, false },
36719 /* Builtin mask mapping for printing the flags. */
36720 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
36722 { "altivec", RS6000_BTM_ALTIVEC, false, false },
36723 { "vsx", RS6000_BTM_VSX, false, false },
36724 { "paired", RS6000_BTM_PAIRED, false, false },
36725 { "fre", RS6000_BTM_FRE, false, false },
36726 { "fres", RS6000_BTM_FRES, false, false },
36727 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
36728 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
36729 { "popcntd", RS6000_BTM_POPCNTD, false, false },
36730 { "cell", RS6000_BTM_CELL, false, false },
36731 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
36732 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
36733 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
36734 { "crypto", RS6000_BTM_CRYPTO, false, false },
36735 { "htm", RS6000_BTM_HTM, false, false },
36736 { "hard-dfp", RS6000_BTM_DFP, false, false },
36737 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
36738 { "long-double-128", RS6000_BTM_LDBL128, false, false },
36739 { "float128", RS6000_BTM_FLOAT128, false, false },
36740 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
36743 /* Option variables that we want to support inside attribute((target)) and
36744 #pragma GCC target operations. */
36746 struct rs6000_opt_var {
36747 const char *name; /* option name */
36748 size_t global_offset; /* offset of the option in global_options. */
36749 size_t target_offset; /* offset of the option in target options. */
36752 static struct rs6000_opt_var const rs6000_opt_vars[] =
36755 offsetof (struct gcc_options, x_TARGET_FRIZ),
36756 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
36757 { "avoid-indexed-addresses",
36758 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
36759 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
36761 offsetof (struct gcc_options, x_rs6000_paired_float),
36762 offsetof (struct cl_target_option, x_rs6000_paired_float), },
36764 offsetof (struct gcc_options, x_rs6000_default_long_calls),
36765 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
36766 { "optimize-swaps",
36767 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
36768 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
36769 { "allow-movmisalign",
36770 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
36771 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
36773 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
36774 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
36776 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
36777 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
36778 { "align-branch-targets",
36779 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
36780 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
36782 offsetof (struct gcc_options, x_tls_markers),
36783 offsetof (struct cl_target_option, x_tls_markers), },
36785 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36786 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36788 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36789 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36790 { "speculate-indirect-jumps",
36791 offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
36792 offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
36795 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36796 parsing. Return true if there were no errors. */
36799 rs6000_inner_target_options (tree args, bool attr_p)
36803 if (args == NULL_TREE)
36806 else if (TREE_CODE (args) == STRING_CST)
36808 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36811 while ((q = strtok (p, ",")) != NULL)
36813 bool error_p = false;
36814 bool not_valid_p = false;
36815 const char *cpu_opt = NULL;
36818 if (strncmp (q, "cpu=", 4) == 0)
36820 int cpu_index = rs6000_cpu_name_lookup (q+4);
36821 if (cpu_index >= 0)
36822 rs6000_cpu_index = cpu_index;
36829 else if (strncmp (q, "tune=", 5) == 0)
36831 int tune_index = rs6000_cpu_name_lookup (q+5);
36832 if (tune_index >= 0)
36833 rs6000_tune_index = tune_index;
36843 bool invert = false;
36847 if (strncmp (r, "no-", 3) == 0)
36853 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36854 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36856 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36858 if (!rs6000_opt_masks[i].valid_target)
36859 not_valid_p = true;
36863 rs6000_isa_flags_explicit |= mask;
36865 /* VSX needs altivec, so -mvsx automagically sets
36866 altivec and disables -mavoid-indexed-addresses. */
36869 if (mask == OPTION_MASK_VSX)
36871 mask |= OPTION_MASK_ALTIVEC;
36872 TARGET_AVOID_XFORM = 0;
36876 if (rs6000_opt_masks[i].invert)
36880 rs6000_isa_flags &= ~mask;
36882 rs6000_isa_flags |= mask;
36887 if (error_p && !not_valid_p)
36889 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36890 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36892 size_t j = rs6000_opt_vars[i].global_offset;
36893 *((int *) ((char *)&global_options + j)) = !invert;
36895 not_valid_p = false;
36903 const char *eprefix, *esuffix;
36908 eprefix = "__attribute__((__target__(";
36913 eprefix = "#pragma GCC target ";
36918 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36920 else if (not_valid_p)
36921 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36923 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36928 else if (TREE_CODE (args) == TREE_LIST)
36932 tree value = TREE_VALUE (args);
36935 bool ret2 = rs6000_inner_target_options (value, attr_p);
36939 args = TREE_CHAIN (args);
36941 while (args != NULL_TREE);
36946 error ("attribute %<target%> argument not a string");
36953 /* Print out the target options as a list for -mdebug=target. */
36956 rs6000_debug_target_options (tree args, const char *prefix)
36958 if (args == NULL_TREE)
36959 fprintf (stderr, "%s<NULL>", prefix);
36961 else if (TREE_CODE (args) == STRING_CST)
36963 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36966 while ((q = strtok (p, ",")) != NULL)
36969 fprintf (stderr, "%s\"%s\"", prefix, q);
36974 else if (TREE_CODE (args) == TREE_LIST)
36978 tree value = TREE_VALUE (args);
36981 rs6000_debug_target_options (value, prefix);
36984 args = TREE_CHAIN (args);
36986 while (args != NULL_TREE);
36990 gcc_unreachable ();
36996 /* Hook to validate attribute((target("..."))). */
36999 rs6000_valid_attribute_p (tree fndecl,
37000 tree ARG_UNUSED (name),
37004 struct cl_target_option cur_target;
37007 tree new_target, new_optimize;
37008 tree func_optimize;
37010 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
37012 if (TARGET_DEBUG_TARGET)
37014 tree tname = DECL_NAME (fndecl);
37015 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
37017 fprintf (stderr, "function: %.*s\n",
37018 (int) IDENTIFIER_LENGTH (tname),
37019 IDENTIFIER_POINTER (tname));
37021 fprintf (stderr, "function: unknown\n");
37023 fprintf (stderr, "args:");
37024 rs6000_debug_target_options (args, " ");
37025 fprintf (stderr, "\n");
37028 fprintf (stderr, "flags: 0x%x\n", flags);
37030 fprintf (stderr, "--------------------\n");
37033 /* attribute((target("default"))) does nothing, beyond
37034 affecting multi-versioning. */
37035 if (TREE_VALUE (args)
37036 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
37037 && TREE_CHAIN (args) == NULL_TREE
37038 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
37041 old_optimize = build_optimization_node (&global_options);
37042 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
37044 /* If the function changed the optimization levels as well as setting target
37045 options, start with the optimizations specified. */
37046 if (func_optimize && func_optimize != old_optimize)
37047 cl_optimization_restore (&global_options,
37048 TREE_OPTIMIZATION (func_optimize));
37050 /* The target attributes may also change some optimization flags, so update
37051 the optimization options if necessary. */
37052 cl_target_option_save (&cur_target, &global_options);
37053 rs6000_cpu_index = rs6000_tune_index = -1;
37054 ret = rs6000_inner_target_options (args, true);
37056 /* Set up any additional state. */
37059 ret = rs6000_option_override_internal (false);
37060 new_target = build_target_option_node (&global_options);
37065 new_optimize = build_optimization_node (&global_options);
37072 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
37074 if (old_optimize != new_optimize)
37075 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
37078 cl_target_option_restore (&global_options, &cur_target);
37080 if (old_optimize != new_optimize)
37081 cl_optimization_restore (&global_options,
37082 TREE_OPTIMIZATION (old_optimize));
37088 /* Hook to validate the current #pragma GCC target and set the state, and
37089 update the macros based on what was changed. If ARGS is NULL, then
37090 POP_TARGET is used to reset the options. */
37093 rs6000_pragma_target_parse (tree args, tree pop_target)
37095 tree prev_tree = build_target_option_node (&global_options);
37097 struct cl_target_option *prev_opt, *cur_opt;
37098 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
37099 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
37101 if (TARGET_DEBUG_TARGET)
37103 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
37104 fprintf (stderr, "args:");
37105 rs6000_debug_target_options (args, " ");
37106 fprintf (stderr, "\n");
37110 fprintf (stderr, "pop_target:\n");
37111 debug_tree (pop_target);
37114 fprintf (stderr, "pop_target: <NULL>\n");
37116 fprintf (stderr, "--------------------\n");
37121 cur_tree = ((pop_target)
37123 : target_option_default_node);
37124 cl_target_option_restore (&global_options,
37125 TREE_TARGET_OPTION (cur_tree));
37129 rs6000_cpu_index = rs6000_tune_index = -1;
37130 if (!rs6000_inner_target_options (args, false)
37131 || !rs6000_option_override_internal (false)
37132 || (cur_tree = build_target_option_node (&global_options))
37135 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
37136 fprintf (stderr, "invalid pragma\n");
37142 target_option_current_node = cur_tree;
37143 rs6000_activate_target_options (target_option_current_node);
37145 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
37146 change the macros that are defined. */
37147 if (rs6000_target_modify_macros_ptr)
37149 prev_opt = TREE_TARGET_OPTION (prev_tree);
37150 prev_bumask = prev_opt->x_rs6000_builtin_mask;
37151 prev_flags = prev_opt->x_rs6000_isa_flags;
37153 cur_opt = TREE_TARGET_OPTION (cur_tree);
37154 cur_flags = cur_opt->x_rs6000_isa_flags;
37155 cur_bumask = cur_opt->x_rs6000_builtin_mask;
37157 diff_bumask = (prev_bumask ^ cur_bumask);
37158 diff_flags = (prev_flags ^ cur_flags);
37160 if ((diff_flags != 0) || (diff_bumask != 0))
37162 /* Delete old macros. */
37163 rs6000_target_modify_macros_ptr (false,
37164 prev_flags & diff_flags,
37165 prev_bumask & diff_bumask);
37167 /* Define new macros. */
37168 rs6000_target_modify_macros_ptr (true,
37169 cur_flags & diff_flags,
37170 cur_bumask & diff_bumask);
37178 /* Remember the last target of rs6000_set_current_function. */
37179 static GTY(()) tree rs6000_previous_fndecl;
37181 /* Restore target's globals from NEW_TREE and invalidate the
37182 rs6000_previous_fndecl cache. */
37185 rs6000_activate_target_options (tree new_tree)
37187 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
37188 if (TREE_TARGET_GLOBALS (new_tree))
37189 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
37190 else if (new_tree == target_option_default_node)
37191 restore_target_globals (&default_target_globals);
37193 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
37194 rs6000_previous_fndecl = NULL_TREE;
37197 /* Establish appropriate back-end context for processing the function
37198 FNDECL. The argument might be NULL to indicate processing at top
37199 level, outside of any function scope. */
37201 rs6000_set_current_function (tree fndecl)
37203 if (TARGET_DEBUG_TARGET)
37205 fprintf (stderr, "\n==================== rs6000_set_current_function");
37208 fprintf (stderr, ", fndecl %s (%p)",
37209 (DECL_NAME (fndecl)
37210 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
37211 : "<unknown>"), (void *)fndecl);
37213 if (rs6000_previous_fndecl)
37214 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
37216 fprintf (stderr, "\n");
37219 /* Only change the context if the function changes. This hook is called
37220 several times in the course of compiling a function, and we don't want to
37221 slow things down too much or call target_reinit when it isn't safe. */
37222 if (fndecl == rs6000_previous_fndecl)
37226 if (rs6000_previous_fndecl == NULL_TREE)
37227 old_tree = target_option_current_node;
37228 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
37229 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
37231 old_tree = target_option_default_node;
37234 if (fndecl == NULL_TREE)
37236 if (old_tree != target_option_current_node)
37237 new_tree = target_option_current_node;
37239 new_tree = NULL_TREE;
37243 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37244 if (new_tree == NULL_TREE)
37245 new_tree = target_option_default_node;
37248 if (TARGET_DEBUG_TARGET)
37252 fprintf (stderr, "\nnew fndecl target specific options:\n");
37253 debug_tree (new_tree);
37258 fprintf (stderr, "\nold fndecl target specific options:\n");
37259 debug_tree (old_tree);
37262 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
37263 fprintf (stderr, "--------------------\n");
37266 if (new_tree && old_tree != new_tree)
37267 rs6000_activate_target_options (new_tree);
37270 rs6000_previous_fndecl = fndecl;
37274 /* Save the current options */
37277 rs6000_function_specific_save (struct cl_target_option *ptr,
37278 struct gcc_options *opts)
37280 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
37281 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
37284 /* Restore the current options */
37287 rs6000_function_specific_restore (struct gcc_options *opts,
37288 struct cl_target_option *ptr)
37291 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
37292 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
37293 (void) rs6000_option_override_internal (false);
37296 /* Print the current options */
37299 rs6000_function_specific_print (FILE *file, int indent,
37300 struct cl_target_option *ptr)
37302 rs6000_print_isa_options (file, indent, "Isa options set",
37303 ptr->x_rs6000_isa_flags);
37305 rs6000_print_isa_options (file, indent, "Isa options explicit",
37306 ptr->x_rs6000_isa_flags_explicit);
37309 /* Helper function to print the current isa or misc options on a line. */
37312 rs6000_print_options_internal (FILE *file,
37314 const char *string,
37315 HOST_WIDE_INT flags,
37316 const char *prefix,
37317 const struct rs6000_opt_mask *opts,
37318 size_t num_elements)
37321 size_t start_column = 0;
37323 size_t max_column = 120;
37324 size_t prefix_len = strlen (prefix);
37325 size_t comma_len = 0;
37326 const char *comma = "";
37329 start_column += fprintf (file, "%*s", indent, "");
37333 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
37337 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
37339 /* Print the various mask options. */
37340 cur_column = start_column;
37341 for (i = 0; i < num_elements; i++)
37343 bool invert = opts[i].invert;
37344 const char *name = opts[i].name;
37345 const char *no_str = "";
37346 HOST_WIDE_INT mask = opts[i].mask;
37347 size_t len = comma_len + prefix_len + strlen (name);
37351 if ((flags & mask) == 0)
37354 len += sizeof ("no-") - 1;
37362 if ((flags & mask) != 0)
37365 len += sizeof ("no-") - 1;
37372 if (cur_column > max_column)
37374 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
37375 cur_column = start_column + len;
37379 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
37381 comma_len = sizeof (", ") - 1;
37384 fputs ("\n", file);
37387 /* Helper function to print the current isa options on a line. */
37390 rs6000_print_isa_options (FILE *file, int indent, const char *string,
37391 HOST_WIDE_INT flags)
37393 rs6000_print_options_internal (file, indent, string, flags, "-m",
37394 &rs6000_opt_masks[0],
37395 ARRAY_SIZE (rs6000_opt_masks));
37399 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
37400 HOST_WIDE_INT flags)
37402 rs6000_print_options_internal (file, indent, string, flags, "",
37403 &rs6000_builtin_mask_names[0],
37404 ARRAY_SIZE (rs6000_builtin_mask_names));
37407 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
37408 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
37409 -mupper-regs-df, etc.).
37411 If the user used -mno-power8-vector, we need to turn off all of the implicit
37412 ISA 2.07 and 3.0 options that relate to the vector unit.
37414 If the user used -mno-power9-vector, we need to turn off all of the implicit
37415 ISA 3.0 options that relate to the vector unit.
37417 This function does not handle explicit options such as the user specifying
37418 -mdirect-move. These are handled in rs6000_option_override_internal, and
37419 the appropriate error is given if needed.
37421 We return a mask of all of the implicit options that should not be enabled
37424 static HOST_WIDE_INT
37425 rs6000_disable_incompatible_switches (void)
37427 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
37430 static const struct {
37431 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
37432 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
37433 const char *const name; /* name of the switch. */
37435 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
37436 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
37437 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
37440 for (i = 0; i < ARRAY_SIZE (flags); i++)
37442 HOST_WIDE_INT no_flag = flags[i].no_flag;
37444 if ((rs6000_isa_flags & no_flag) == 0
37445 && (rs6000_isa_flags_explicit & no_flag) != 0)
37447 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
37448 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
37454 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
37455 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
37457 set_flags &= ~rs6000_opt_masks[j].mask;
37458 error ("%<-mno-%s%> turns off %<-m%s%>",
37460 rs6000_opt_masks[j].name);
37463 gcc_assert (!set_flags);
37466 rs6000_isa_flags &= ~dep_flags;
37467 ignore_masks |= no_flag | dep_flags;
37471 return ignore_masks;
37475 /* Helper function for printing the function name when debugging. */
37477 static const char *
37478 get_decl_name (tree fn)
37485 name = DECL_NAME (fn);
37487 return "<no-name>";
37489 return IDENTIFIER_POINTER (name);
37492 /* Return the clone id of the target we are compiling code for in a target
37493 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
37494 the priority list for the target clones (ordered from lowest to
37498 rs6000_clone_priority (tree fndecl)
37500 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37501 HOST_WIDE_INT isa_masks;
37502 int ret = CLONE_DEFAULT;
37503 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
37504 const char *attrs_str = NULL;
37506 attrs = TREE_VALUE (TREE_VALUE (attrs));
37507 attrs_str = TREE_STRING_POINTER (attrs);
37509 /* Return priority zero for default function. Return the ISA needed for the
37510 function if it is not the default. */
37511 if (strcmp (attrs_str, "default") != 0)
37513 if (fn_opts == NULL_TREE)
37514 fn_opts = target_option_default_node;
37516 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
37517 isa_masks = rs6000_isa_flags;
37519 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
37521 for (ret = CLONE_MAX - 1; ret != 0; ret--)
37522 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
37526 if (TARGET_DEBUG_TARGET)
37527 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
37528 get_decl_name (fndecl), ret);
37533 /* This compares the priority of target features in function DECL1 and DECL2.
37534 It returns positive value if DECL1 is higher priority, negative value if
37535 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37536 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37539 rs6000_compare_version_priority (tree decl1, tree decl2)
37541 int priority1 = rs6000_clone_priority (decl1);
37542 int priority2 = rs6000_clone_priority (decl2);
37543 int ret = priority1 - priority2;
37545 if (TARGET_DEBUG_TARGET)
37546 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
37547 get_decl_name (decl1), get_decl_name (decl2), ret);
37552 /* Make a dispatcher declaration for the multi-versioned function DECL.
37553 Calls to DECL function will be replaced with calls to the dispatcher
37554 by the front-end. Returns the decl of the dispatcher function. */
37557 rs6000_get_function_versions_dispatcher (void *decl)
37559 tree fn = (tree) decl;
37560 struct cgraph_node *node = NULL;
37561 struct cgraph_node *default_node = NULL;
37562 struct cgraph_function_version_info *node_v = NULL;
37563 struct cgraph_function_version_info *first_v = NULL;
37565 tree dispatch_decl = NULL;
37567 struct cgraph_function_version_info *default_version_info = NULL;
37568 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
37570 if (TARGET_DEBUG_TARGET)
37571 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
37572 get_decl_name (fn));
37574 node = cgraph_node::get (fn);
37575 gcc_assert (node != NULL);
37577 node_v = node->function_version ();
37578 gcc_assert (node_v != NULL);
37580 if (node_v->dispatcher_resolver != NULL)
37581 return node_v->dispatcher_resolver;
37583 /* Find the default version and make it the first node. */
37585 /* Go to the beginning of the chain. */
37586 while (first_v->prev != NULL)
37587 first_v = first_v->prev;
37589 default_version_info = first_v;
37590 while (default_version_info != NULL)
37592 const tree decl2 = default_version_info->this_node->decl;
37593 if (is_function_default_version (decl2))
37595 default_version_info = default_version_info->next;
37598 /* If there is no default node, just return NULL. */
37599 if (default_version_info == NULL)
37602 /* Make default info the first node. */
37603 if (first_v != default_version_info)
37605 default_version_info->prev->next = default_version_info->next;
37606 if (default_version_info->next)
37607 default_version_info->next->prev = default_version_info->prev;
37608 first_v->prev = default_version_info;
37609 default_version_info->next = first_v;
37610 default_version_info->prev = NULL;
37613 default_node = default_version_info->this_node;
37615 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37616 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37617 "target_clones attribute needs GLIBC (2.23 and newer) that "
37618 "exports hardware capability bits");
37621 if (targetm.has_ifunc_p ())
37623 struct cgraph_function_version_info *it_v = NULL;
37624 struct cgraph_node *dispatcher_node = NULL;
37625 struct cgraph_function_version_info *dispatcher_version_info = NULL;
37627 /* Right now, the dispatching is done via ifunc. */
37628 dispatch_decl = make_dispatcher_decl (default_node->decl);
37630 dispatcher_node = cgraph_node::get_create (dispatch_decl);
37631 gcc_assert (dispatcher_node != NULL);
37632 dispatcher_node->dispatcher_function = 1;
37633 dispatcher_version_info
37634 = dispatcher_node->insert_new_function_version ();
37635 dispatcher_version_info->next = default_version_info;
37636 dispatcher_node->definition = 1;
37638 /* Set the dispatcher for all the versions. */
37639 it_v = default_version_info;
37640 while (it_v != NULL)
37642 it_v->dispatcher_resolver = dispatch_decl;
37648 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37649 "multiversioning needs ifunc which is not supported "
37654 return dispatch_decl;
37657 /* Make the resolver function decl to dispatch the versions of a multi-
37658 versioned function, DEFAULT_DECL. Create an empty basic block in the
37659 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37663 make_resolver_func (const tree default_decl,
37664 const tree dispatch_decl,
37665 basic_block *empty_bb)
37667 /* Make the resolver function static. The resolver function returns
37669 tree decl_name = clone_function_name (default_decl, "resolver");
37670 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
37671 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
37672 tree decl = build_fn_decl (resolver_name, type);
37673 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
37675 DECL_NAME (decl) = decl_name;
37676 TREE_USED (decl) = 1;
37677 DECL_ARTIFICIAL (decl) = 1;
37678 DECL_IGNORED_P (decl) = 0;
37679 TREE_PUBLIC (decl) = 0;
37680 DECL_UNINLINABLE (decl) = 1;
37682 /* Resolver is not external, body is generated. */
37683 DECL_EXTERNAL (decl) = 0;
37684 DECL_EXTERNAL (dispatch_decl) = 0;
37686 DECL_CONTEXT (decl) = NULL_TREE;
37687 DECL_INITIAL (decl) = make_node (BLOCK);
37688 DECL_STATIC_CONSTRUCTOR (decl) = 0;
37690 /* Build result decl and add to function_decl. */
37691 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
37692 DECL_ARTIFICIAL (t) = 1;
37693 DECL_IGNORED_P (t) = 1;
37694 DECL_RESULT (decl) = t;
37696 gimplify_function_tree (decl);
37697 push_cfun (DECL_STRUCT_FUNCTION (decl));
37698 *empty_bb = init_lowered_empty_function (decl, false,
37699 profile_count::uninitialized ());
37701 cgraph_node::add_new_function (decl, true);
37702 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
37706 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37707 DECL_ATTRIBUTES (dispatch_decl)
37708 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
37710 cgraph_node::create_same_body_alias (dispatch_decl, decl);
37715 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37716 return a pointer to VERSION_DECL if we are running on a machine that
37717 supports the index CLONE_ISA hardware architecture bits. This function will
37718 be called during version dispatch to decide which function version to
37719 execute. It returns the basic block at the end, to which more conditions
37723 add_condition_to_bb (tree function_decl, tree version_decl,
37724 int clone_isa, basic_block new_bb)
37726 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
37728 gcc_assert (new_bb != NULL);
37729 gimple_seq gseq = bb_seq (new_bb);
37732 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
37733 build_fold_addr_expr (version_decl));
37734 tree result_var = create_tmp_var (ptr_type_node);
37735 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
37736 gimple *return_stmt = gimple_build_return (result_var);
37738 if (clone_isa == CLONE_DEFAULT)
37740 gimple_seq_add_stmt (&gseq, convert_stmt);
37741 gimple_seq_add_stmt (&gseq, return_stmt);
37742 set_bb_seq (new_bb, gseq);
37743 gimple_set_bb (convert_stmt, new_bb);
37744 gimple_set_bb (return_stmt, new_bb);
37749 tree bool_zero = build_int_cst (bool_int_type_node, 0);
37750 tree cond_var = create_tmp_var (bool_int_type_node);
37751 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
37752 const char *arg_str = rs6000_clone_map[clone_isa].name;
37753 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
37754 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
37755 gimple_call_set_lhs (call_cond_stmt, cond_var);
37757 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
37758 gimple_set_bb (call_cond_stmt, new_bb);
37759 gimple_seq_add_stmt (&gseq, call_cond_stmt);
37761 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
37762 NULL_TREE, NULL_TREE);
37763 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
37764 gimple_set_bb (if_else_stmt, new_bb);
37765 gimple_seq_add_stmt (&gseq, if_else_stmt);
37767 gimple_seq_add_stmt (&gseq, convert_stmt);
37768 gimple_seq_add_stmt (&gseq, return_stmt);
37769 set_bb_seq (new_bb, gseq);
37771 basic_block bb1 = new_bb;
37772 edge e12 = split_block (bb1, if_else_stmt);
37773 basic_block bb2 = e12->dest;
37774 e12->flags &= ~EDGE_FALLTHRU;
37775 e12->flags |= EDGE_TRUE_VALUE;
37777 edge e23 = split_block (bb2, return_stmt);
37778 gimple_set_bb (convert_stmt, bb2);
37779 gimple_set_bb (return_stmt, bb2);
37781 basic_block bb3 = e23->dest;
37782 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
37785 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
37791 /* This function generates the dispatch function for multi-versioned functions.
37792 DISPATCH_DECL is the function which will contain the dispatch logic.
37793 FNDECLS are the function choices for dispatch, and is a tree chain.
37794 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37795 code is generated. */
37798 dispatch_function_versions (tree dispatch_decl,
37800 basic_block *empty_bb)
37804 vec<tree> *fndecls;
37805 tree clones[CLONE_MAX];
37807 if (TARGET_DEBUG_TARGET)
37808 fputs ("dispatch_function_versions, top\n", stderr);
37810 gcc_assert (dispatch_decl != NULL
37811 && fndecls_p != NULL
37812 && empty_bb != NULL);
37814 /* fndecls_p is actually a vector. */
37815 fndecls = static_cast<vec<tree> *> (fndecls_p);
37817 /* At least one more version other than the default. */
37818 gcc_assert (fndecls->length () >= 2);
37820 /* The first version in the vector is the default decl. */
37821 memset ((void *) clones, '\0', sizeof (clones));
37822 clones[CLONE_DEFAULT] = (*fndecls)[0];
37824 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37825 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37826 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37827 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37828 to insert the code here to do the call. */
37830 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
37832 int priority = rs6000_clone_priority (ele);
37833 if (!clones[priority])
37834 clones[priority] = ele;
37837 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
37840 if (TARGET_DEBUG_TARGET)
37841 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
37842 ix, get_decl_name (clones[ix]));
37844 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37851 /* Generate the dispatching code body to dispatch multi-versioned function
37852 DECL. The target hook is called to process the "target" attributes and
37853 provide the code to dispatch the right function at run-time. NODE points
37854 to the dispatcher decl whose body will be created. */
37857 rs6000_generate_version_dispatcher_body (void *node_p)
37860 basic_block empty_bb;
37861 struct cgraph_node *node = (cgraph_node *) node_p;
37862 struct cgraph_function_version_info *ninfo = node->function_version ();
37864 if (ninfo->dispatcher_resolver)
37865 return ninfo->dispatcher_resolver;
37867 /* node is going to be an alias, so remove the finalized bit. */
37868 node->definition = false;
37870 /* The first version in the chain corresponds to the default version. */
37871 ninfo->dispatcher_resolver = resolver
37872 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37874 if (TARGET_DEBUG_TARGET)
37875 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37876 get_decl_name (resolver));
37878 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37879 auto_vec<tree, 2> fn_ver_vec;
37881 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37883 vinfo = vinfo->next)
37885 struct cgraph_node *version = vinfo->this_node;
37886 /* Check for virtual functions here again, as by this time it should
37887 have been determined if this function needs a vtable index or
37888 not. This happens for methods in derived classes that override
37889 virtual methods in base classes but are not explicitly marked as
37891 if (DECL_VINDEX (version->decl))
37892 sorry ("Virtual function multiversioning not supported");
37894 fn_ver_vec.safe_push (version->decl);
37897 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37898 cgraph_edge::rebuild_edges ();
37904 /* Hook to determine if one function can safely inline another. */
37907 rs6000_can_inline_p (tree caller, tree callee)
37910 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37911 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37913 /* If callee has no option attributes, then it is ok to inline. */
37917 /* If caller has no option attributes, but callee does then it is not ok to
37919 else if (!caller_tree)
37924 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37925 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37927 /* Callee's options should a subset of the caller's, i.e. a vsx function
37928 can inline an altivec function but a non-vsx function can't inline a
37930 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37931 == callee_opts->x_rs6000_isa_flags)
37935 if (TARGET_DEBUG_TARGET)
37936 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37937 get_decl_name (caller), get_decl_name (callee),
37938 (ret ? "can" : "cannot"));
37943 /* Allocate a stack temp and fixup the address so it meets the particular
37944 memory requirements (either offetable or REG+REG addressing). */
37947 rs6000_allocate_stack_temp (machine_mode mode,
37948 bool offsettable_p,
37951 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37952 rtx addr = XEXP (stack, 0);
37953 int strict_p = reload_completed;
37955 if (!legitimate_indirect_address_p (addr, strict_p))
37958 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
37959 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37961 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
37962 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37968 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
37969 to such a form to deal with memory reference instructions like STFIWX that
37970 only take reg+reg addressing. */
37973 rs6000_address_for_fpconvert (rtx x)
37977 gcc_assert (MEM_P (x));
37978 addr = XEXP (x, 0);
37979 if (can_create_pseudo_p ()
37980 && ! legitimate_indirect_address_p (addr, reload_completed)
37981 && ! legitimate_indexed_address_p (addr, reload_completed))
37983 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
37985 rtx reg = XEXP (addr, 0);
37986 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
37987 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
37988 gcc_assert (REG_P (reg));
37989 emit_insn (gen_add3_insn (reg, reg, size_rtx));
37992 else if (GET_CODE (addr) == PRE_MODIFY)
37994 rtx reg = XEXP (addr, 0);
37995 rtx expr = XEXP (addr, 1);
37996 gcc_assert (REG_P (reg));
37997 gcc_assert (GET_CODE (expr) == PLUS);
37998 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
38002 x = replace_equiv_address (x, copy_addr_to_reg (addr));
38008 /* Given a memory reference, if it is not in the form for altivec memory
38009 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
38010 convert to the altivec format. */
38013 rs6000_address_for_altivec (rtx x)
38015 gcc_assert (MEM_P (x));
38016 if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
38018 rtx addr = XEXP (x, 0);
38020 if (!legitimate_indexed_address_p (addr, reload_completed)
38021 && !legitimate_indirect_address_p (addr, reload_completed))
38022 addr = copy_to_mode_reg (Pmode, addr);
38024 addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
38025 x = change_address (x, GET_MODE (x), addr);
38031 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
38033 On the RS/6000, all integer constants are acceptable, most won't be valid
38034 for particular insns, though. Only easy FP constants are acceptable. */
38037 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
38039 if (TARGET_ELF && tls_referenced_p (x))
38042 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
38043 || GET_MODE (x) == VOIDmode
38044 || (TARGET_POWERPC64 && mode == DImode)
38045 || easy_fp_constant (x, mode)
38046 || easy_vector_constant (x, mode));
38050 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
38053 chain_already_loaded (rtx_insn *last)
38055 for (; last != NULL; last = PREV_INSN (last))
38057 if (NONJUMP_INSN_P (last))
38059 rtx patt = PATTERN (last);
38061 if (GET_CODE (patt) == SET)
38063 rtx lhs = XEXP (patt, 0);
38065 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
38073 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
38076 rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
38078 const bool direct_call_p
38079 = GET_CODE (func_desc) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (func_desc);
38080 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
38081 rtx toc_load = NULL_RTX;
38082 rtx toc_restore = NULL_RTX;
38084 rtx abi_reg = NULL_RTX;
38089 /* Handle longcall attributes. */
38090 if (INTVAL (cookie) & CALL_LONG)
38091 func_desc = rs6000_longcall_ref (func_desc);
38093 /* Handle indirect calls. */
38094 if (GET_CODE (func_desc) != SYMBOL_REF
38095 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc)))
38097 /* Save the TOC into its reserved slot before the call,
38098 and prepare to restore it after the call. */
38099 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
38100 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
38101 rtx stack_toc_mem = gen_frame_mem (Pmode,
38102 gen_rtx_PLUS (Pmode, stack_ptr,
38103 stack_toc_offset));
38104 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
38105 gen_rtvec (1, stack_toc_offset),
38107 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
38109 /* Can we optimize saving the TOC in the prologue or
38110 do we need to do it at every call? */
38111 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
38112 cfun->machine->save_toc_in_prologue = true;
38115 MEM_VOLATILE_P (stack_toc_mem) = 1;
38116 emit_move_insn (stack_toc_mem, toc_reg);
38119 if (DEFAULT_ABI == ABI_ELFv2)
38121 /* A function pointer in the ELFv2 ABI is just a plain address, but
38122 the ABI requires it to be loaded into r12 before the call. */
38123 func_addr = gen_rtx_REG (Pmode, 12);
38124 emit_move_insn (func_addr, func_desc);
38125 abi_reg = func_addr;
38129 /* A function pointer under AIX is a pointer to a data area whose
38130 first word contains the actual address of the function, whose
38131 second word contains a pointer to its TOC, and whose third word
38132 contains a value to place in the static chain register (r11).
38133 Note that if we load the static chain, our "trampoline" need
38134 not have any executable code. */
38136 /* Load up address of the actual function. */
38137 func_desc = force_reg (Pmode, func_desc);
38138 func_addr = gen_reg_rtx (Pmode);
38139 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
38141 /* Prepare to load the TOC of the called function. Note that the
38142 TOC load must happen immediately before the actual call so
38143 that unwinding the TOC registers works correctly. See the
38144 comment in frob_update_context. */
38145 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
38146 rtx func_toc_mem = gen_rtx_MEM (Pmode,
38147 gen_rtx_PLUS (Pmode, func_desc,
38149 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
38151 /* If we have a static chain, load it up. But, if the call was
38152 originally direct, the 3rd word has not been written since no
38153 trampoline has been built, so we ought not to load it, lest we
38154 override a static chain value. */
38156 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
38157 && !chain_already_loaded (get_current_sequence ()->next->last))
38159 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
38160 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
38161 rtx func_sc_mem = gen_rtx_MEM (Pmode,
38162 gen_rtx_PLUS (Pmode, func_desc,
38164 emit_move_insn (sc_reg, func_sc_mem);
38171 /* Direct calls use the TOC: for local calls, the callee will
38172 assume the TOC register is set; for non-local calls, the
38173 PLT stub needs the TOC register. */
38175 func_addr = func_desc;
38178 /* Create the call. */
38179 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag);
38180 if (value != NULL_RTX)
38181 call[0] = gen_rtx_SET (value, call[0]);
38185 call[n_call++] = toc_load;
38187 call[n_call++] = toc_restore;
38189 call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
38191 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
38192 insn = emit_call_insn (insn);
38194 /* Mention all registers defined by the ABI to hold information
38195 as uses in CALL_INSN_FUNCTION_USAGE. */
38197 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
38200 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
38203 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
38208 gcc_assert (INTVAL (cookie) == 0);
38210 /* Create the call. */
38211 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag);
38212 if (value != NULL_RTX)
38213 call[0] = gen_rtx_SET (value, call[0]);
38215 call[1] = simple_return_rtx;
38217 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
38218 insn = emit_call_insn (insn);
38220 /* Note use of the TOC register. */
38221 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
38224 /* Return whether we need to always update the saved TOC pointer when we update
38225 the stack pointer. */
38228 rs6000_save_toc_in_prologue_p (void)
38230 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
38233 #ifdef HAVE_GAS_HIDDEN
38234 # define USE_HIDDEN_LINKONCE 1
38236 # define USE_HIDDEN_LINKONCE 0
38239 /* Fills in the label name that should be used for a 476 link stack thunk. */
38242 get_ppc476_thunk_name (char name[32])
38244 gcc_assert (TARGET_LINK_STACK);
38246 if (USE_HIDDEN_LINKONCE)
38247 sprintf (name, "__ppc476.get_thunk");
38249 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
38252 /* This function emits the simple thunk routine that is used to preserve
38253 the link stack on the 476 cpu. */
38255 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
38257 rs6000_code_end (void)
38262 if (!TARGET_LINK_STACK)
38265 get_ppc476_thunk_name (name);
38267 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
38268 build_function_type_list (void_type_node, NULL_TREE));
38269 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
38270 NULL_TREE, void_type_node);
38271 TREE_PUBLIC (decl) = 1;
38272 TREE_STATIC (decl) = 1;
38275 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
38277 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
38278 targetm.asm_out.unique_section (decl, 0);
38279 switch_to_section (get_named_section (decl, NULL, 0));
38280 DECL_WEAK (decl) = 1;
38281 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
38282 targetm.asm_out.globalize_label (asm_out_file, name);
38283 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
38284 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
38289 switch_to_section (text_section);
38290 ASM_OUTPUT_LABEL (asm_out_file, name);
38293 DECL_INITIAL (decl) = make_node (BLOCK);
38294 current_function_decl = decl;
38295 allocate_struct_function (decl, false);
38296 init_function_start (decl);
38297 first_function_block_is_cold = false;
38298 /* Make sure unwind info is emitted for the thunk if needed. */
38299 final_start_function (emit_barrier (), asm_out_file, 1);
38301 fputs ("\tblr\n", asm_out_file);
38303 final_end_function ();
38304 init_insn_lengths ();
38305 free_after_compilation (cfun);
38307 current_function_decl = NULL;
38310 /* Add r30 to hard reg set if the prologue sets it up and it is not
38311 pic_offset_table_rtx. */
38314 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
38316 if (!TARGET_SINGLE_PIC_BASE
38318 && TARGET_MINIMAL_TOC
38319 && !constant_pool_empty_p ())
38320 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
38321 if (cfun->machine->split_stack_argp_used)
38322 add_to_hard_reg_set (&set->set, Pmode, 12);
38324 /* Make sure the hard reg set doesn't include r2, which was possibly added
38325 via PIC_OFFSET_TABLE_REGNUM. */
38327 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
38331 /* Helper function for rs6000_split_logical to emit a logical instruction after
38332 spliting the operation to single GPR registers.
38334 DEST is the destination register.
38335 OP1 and OP2 are the input source registers.
38336 CODE is the base operation (AND, IOR, XOR, NOT).
38337 MODE is the machine mode.
38338 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38339 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38340 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38343 rs6000_split_logical_inner (rtx dest,
38346 enum rtx_code code,
38348 bool complement_final_p,
38349 bool complement_op1_p,
38350 bool complement_op2_p)
38354 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38355 if (op2 && GET_CODE (op2) == CONST_INT
38356 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
38357 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38359 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
38360 HOST_WIDE_INT value = INTVAL (op2) & mask;
38362 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38367 emit_insn (gen_rtx_SET (dest, const0_rtx));
38371 else if (value == mask)
38373 if (!rtx_equal_p (dest, op1))
38374 emit_insn (gen_rtx_SET (dest, op1));
38379 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38380 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38381 else if (code == IOR || code == XOR)
38385 if (!rtx_equal_p (dest, op1))
38386 emit_insn (gen_rtx_SET (dest, op1));
38392 if (code == AND && mode == SImode
38393 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38395 emit_insn (gen_andsi3 (dest, op1, op2));
38399 if (complement_op1_p)
38400 op1 = gen_rtx_NOT (mode, op1);
38402 if (complement_op2_p)
38403 op2 = gen_rtx_NOT (mode, op2);
38405 /* For canonical RTL, if only one arm is inverted it is the first. */
38406 if (!complement_op1_p && complement_op2_p)
38407 std::swap (op1, op2);
38409 bool_rtx = ((code == NOT)
38410 ? gen_rtx_NOT (mode, op1)
38411 : gen_rtx_fmt_ee (code, mode, op1, op2));
38413 if (complement_final_p)
38414 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
38416 emit_insn (gen_rtx_SET (dest, bool_rtx));
38419 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38420 operations are split immediately during RTL generation to allow for more
38421 optimizations of the AND/IOR/XOR.
38423 OPERANDS is an array containing the destination and two input operands.
38424 CODE is the base operation (AND, IOR, XOR, NOT).
38425 MODE is the machine mode.
38426 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38427 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38428 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38429 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38430 formation of the AND instructions. */
38433 rs6000_split_logical_di (rtx operands[3],
38434 enum rtx_code code,
38435 bool complement_final_p,
38436 bool complement_op1_p,
38437 bool complement_op2_p)
38439 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
38440 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
38441 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
38442 enum hi_lo { hi = 0, lo = 1 };
38443 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
38446 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
38447 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
38448 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
38449 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
38452 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
38455 if (GET_CODE (operands[2]) != CONST_INT)
38457 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
38458 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
38462 HOST_WIDE_INT value = INTVAL (operands[2]);
38463 HOST_WIDE_INT value_hi_lo[2];
38465 gcc_assert (!complement_final_p);
38466 gcc_assert (!complement_op1_p);
38467 gcc_assert (!complement_op2_p);
38469 value_hi_lo[hi] = value >> 32;
38470 value_hi_lo[lo] = value & lower_32bits;
38472 for (i = 0; i < 2; i++)
38474 HOST_WIDE_INT sub_value = value_hi_lo[i];
38476 if (sub_value & sign_bit)
38477 sub_value |= upper_32bits;
38479 op2_hi_lo[i] = GEN_INT (sub_value);
38481 /* If this is an AND instruction, check to see if we need to load
38482 the value in a register. */
38483 if (code == AND && sub_value != -1 && sub_value != 0
38484 && !and_operand (op2_hi_lo[i], SImode))
38485 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
38490 for (i = 0; i < 2; i++)
38492 /* Split large IOR/XOR operations. */
38493 if ((code == IOR || code == XOR)
38494 && GET_CODE (op2_hi_lo[i]) == CONST_INT
38495 && !complement_final_p
38496 && !complement_op1_p
38497 && !complement_op2_p
38498 && !logical_const_operand (op2_hi_lo[i], SImode))
38500 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
38501 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
38502 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
38503 rtx tmp = gen_reg_rtx (SImode);
38505 /* Make sure the constant is sign extended. */
38506 if ((hi_16bits & sign_bit) != 0)
38507 hi_16bits |= upper_32bits;
38509 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
38510 code, SImode, false, false, false);
38512 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
38513 code, SImode, false, false, false);
38516 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
38517 code, SImode, complement_final_p,
38518 complement_op1_p, complement_op2_p);
38524 /* Split the insns that make up boolean operations operating on multiple GPR
38525 registers. The boolean MD patterns ensure that the inputs either are
38526 exactly the same as the output registers, or there is no overlap.
38528 OPERANDS is an array containing the destination and two input operands.
38529 CODE is the base operation (AND, IOR, XOR, NOT).
38530 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38531 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38532 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38535 rs6000_split_logical (rtx operands[3],
38536 enum rtx_code code,
38537 bool complement_final_p,
38538 bool complement_op1_p,
38539 bool complement_op2_p)
38541 machine_mode mode = GET_MODE (operands[0]);
38542 machine_mode sub_mode;
38544 int sub_size, regno0, regno1, nregs, i;
38546 /* If this is DImode, use the specialized version that can run before
38547 register allocation. */
38548 if (mode == DImode && !TARGET_POWERPC64)
38550 rs6000_split_logical_di (operands, code, complement_final_p,
38551 complement_op1_p, complement_op2_p);
38557 op2 = (code == NOT) ? NULL_RTX : operands[2];
38558 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
38559 sub_size = GET_MODE_SIZE (sub_mode);
38560 regno0 = REGNO (op0);
38561 regno1 = REGNO (op1);
38563 gcc_assert (reload_completed);
38564 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38565 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38567 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
38568 gcc_assert (nregs > 1);
38570 if (op2 && REG_P (op2))
38571 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
38573 for (i = 0; i < nregs; i++)
38575 int offset = i * sub_size;
38576 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
38577 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
38578 rtx sub_op2 = ((code == NOT)
38580 : simplify_subreg (sub_mode, op2, mode, offset));
38582 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
38583 complement_final_p, complement_op1_p,
38591 /* Return true if the peephole2 can combine a load involving a combination of
38592 an addis instruction and a load with an offset that can be fused together on
38596 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
38597 rtx addis_value, /* addis value. */
38598 rtx target, /* target register that is loaded. */
38599 rtx mem) /* bottom part of the memory addr. */
38604 /* Validate arguments. */
38605 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38608 if (!base_reg_operand (target, GET_MODE (target)))
38611 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38614 /* Allow sign/zero extension. */
38615 if (GET_CODE (mem) == ZERO_EXTEND
38616 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
38617 mem = XEXP (mem, 0);
38622 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
38625 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38626 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
38629 /* Validate that the register used to load the high value is either the
38630 register being loaded, or we can safely replace its use.
38632 This function is only called from the peephole2 pass and we assume that
38633 there are 2 instructions in the peephole (addis and load), so we want to
38634 check if the target register was not used in the memory address and the
38635 register to hold the addis result is dead after the peephole. */
38636 if (REGNO (addis_reg) != REGNO (target))
38638 if (reg_mentioned_p (target, mem))
38641 if (!peep2_reg_dead_p (2, addis_reg))
38644 /* If the target register being loaded is the stack pointer, we must
38645 avoid loading any other value into it, even temporarily. */
38646 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
38650 base_reg = XEXP (addr, 0);
38651 return REGNO (addis_reg) == REGNO (base_reg);
38654 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38655 sequence. We adjust the addis register to use the target register. If the
38656 load sign extends, we adjust the code to do the zero extending load, and an
38657 explicit sign extension later since the fusion only covers zero extending
38661 operands[0] register set with addis (to be replaced with target)
38662 operands[1] value set via addis
38663 operands[2] target register being loaded
38664 operands[3] D-form memory reference using operands[0]. */
38667 expand_fusion_gpr_load (rtx *operands)
38669 rtx addis_value = operands[1];
38670 rtx target = operands[2];
38671 rtx orig_mem = operands[3];
38672 rtx new_addr, new_mem, orig_addr, offset;
38673 enum rtx_code plus_or_lo_sum;
38674 machine_mode target_mode = GET_MODE (target);
38675 machine_mode extend_mode = target_mode;
38676 machine_mode ptr_mode = Pmode;
38677 enum rtx_code extend = UNKNOWN;
38679 if (GET_CODE (orig_mem) == ZERO_EXTEND
38680 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
38682 extend = GET_CODE (orig_mem);
38683 orig_mem = XEXP (orig_mem, 0);
38684 target_mode = GET_MODE (orig_mem);
38687 gcc_assert (MEM_P (orig_mem));
38689 orig_addr = XEXP (orig_mem, 0);
38690 plus_or_lo_sum = GET_CODE (orig_addr);
38691 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38693 offset = XEXP (orig_addr, 1);
38694 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38695 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38697 if (extend != UNKNOWN)
38698 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
38700 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
38701 UNSPEC_FUSION_GPR);
38702 emit_insn (gen_rtx_SET (target, new_mem));
38704 if (extend == SIGN_EXTEND)
38706 int sub_off = ((BYTES_BIG_ENDIAN)
38707 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
38710 = simplify_subreg (target_mode, target, extend_mode, sub_off);
38712 emit_insn (gen_rtx_SET (target,
38713 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
38719 /* Emit the addis instruction that will be part of a fused instruction
38723 emit_fusion_addis (rtx target, rtx addis_value)
38726 const char *addis_str = NULL;
38728 /* Emit the addis instruction. */
38729 fuse_ops[0] = target;
38730 if (satisfies_constraint_L (addis_value))
38732 fuse_ops[1] = addis_value;
38733 addis_str = "lis %0,%v1";
38736 else if (GET_CODE (addis_value) == PLUS)
38738 rtx op0 = XEXP (addis_value, 0);
38739 rtx op1 = XEXP (addis_value, 1);
38741 if (REG_P (op0) && CONST_INT_P (op1)
38742 && satisfies_constraint_L (op1))
38746 addis_str = "addis %0,%1,%v2";
38750 else if (GET_CODE (addis_value) == HIGH)
38752 rtx value = XEXP (addis_value, 0);
38753 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
38755 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
38756 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
38758 addis_str = "addis %0,%2,%1@toc@ha";
38760 else if (TARGET_XCOFF)
38761 addis_str = "addis %0,%1@u(%2)";
38764 gcc_unreachable ();
38767 else if (GET_CODE (value) == PLUS)
38769 rtx op0 = XEXP (value, 0);
38770 rtx op1 = XEXP (value, 1);
38772 if (GET_CODE (op0) == UNSPEC
38773 && XINT (op0, 1) == UNSPEC_TOCREL
38774 && CONST_INT_P (op1))
38776 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
38777 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
38780 addis_str = "addis %0,%2,%1+%3@toc@ha";
38782 else if (TARGET_XCOFF)
38783 addis_str = "addis %0,%1+%3@u(%2)";
38786 gcc_unreachable ();
38790 else if (satisfies_constraint_L (value))
38792 fuse_ops[1] = value;
38793 addis_str = "lis %0,%v1";
38796 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
38798 fuse_ops[1] = value;
38799 addis_str = "lis %0,%1@ha";
38804 fatal_insn ("Could not generate addis value for fusion", addis_value);
38806 output_asm_insn (addis_str, fuse_ops);
38809 /* Emit a D-form load or store instruction that is the second instruction
38810 of a fusion sequence. */
38813 emit_fusion_load_store (rtx load_store_reg, rtx addis_reg, rtx offset,
38814 const char *insn_str)
38817 char insn_template[80];
38819 fuse_ops[0] = load_store_reg;
38820 fuse_ops[1] = addis_reg;
38822 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
38824 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
38825 fuse_ops[2] = offset;
38826 output_asm_insn (insn_template, fuse_ops);
38829 else if (GET_CODE (offset) == UNSPEC
38830 && XINT (offset, 1) == UNSPEC_TOCREL)
38833 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
38835 else if (TARGET_XCOFF)
38836 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38839 gcc_unreachable ();
38841 fuse_ops[2] = XVECEXP (offset, 0, 0);
38842 output_asm_insn (insn_template, fuse_ops);
38845 else if (GET_CODE (offset) == PLUS
38846 && GET_CODE (XEXP (offset, 0)) == UNSPEC
38847 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
38848 && CONST_INT_P (XEXP (offset, 1)))
38850 rtx tocrel_unspec = XEXP (offset, 0);
38852 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
38854 else if (TARGET_XCOFF)
38855 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
38858 gcc_unreachable ();
38860 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
38861 fuse_ops[3] = XEXP (offset, 1);
38862 output_asm_insn (insn_template, fuse_ops);
38865 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
38867 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38869 fuse_ops[2] = offset;
38870 output_asm_insn (insn_template, fuse_ops);
38874 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38879 /* Wrap a TOC address that can be fused to indicate that special fusion
38880 processing is needed. */
38883 fusion_wrap_memory_address (rtx old_mem)
38885 rtx old_addr = XEXP (old_mem, 0);
38886 rtvec v = gen_rtvec (1, old_addr);
38887 rtx new_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_FUSION_ADDIS);
38888 return replace_equiv_address_nv (old_mem, new_addr, false);
38891 /* Given an address, convert it into the addis and load offset parts. Addresses
38892 created during the peephole2 process look like:
38893 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38894 (unspec [(...)] UNSPEC_TOCREL))
38896 Addresses created via toc fusion look like:
38897 (unspec [(unspec [(...)] UNSPEC_TOCREL)] UNSPEC_FUSION_ADDIS)) */
38900 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38904 if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS)
38906 lo = XVECEXP (addr, 0, 0);
38907 hi = gen_rtx_HIGH (Pmode, lo);
38909 else if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38911 hi = XEXP (addr, 0);
38912 lo = XEXP (addr, 1);
38915 gcc_unreachable ();
38921 /* Return a string to fuse an addis instruction with a gpr load to the same
38922 register that we loaded up the addis instruction. The address that is used
38923 is the logical address that was formed during peephole2:
38924 (lo_sum (high) (low-part))
38926 Or the address is the TOC address that is wrapped before register allocation:
38927 (unspec [(addr) (toc-reg)] UNSPEC_FUSION_ADDIS)
38929 The code is complicated, so we call output_asm_insn directly, and just
38933 emit_fusion_gpr_load (rtx target, rtx mem)
38938 const char *load_str = NULL;
38941 if (GET_CODE (mem) == ZERO_EXTEND)
38942 mem = XEXP (mem, 0);
38944 gcc_assert (REG_P (target) && MEM_P (mem));
38946 addr = XEXP (mem, 0);
38947 fusion_split_address (addr, &addis_value, &load_offset);
38949 /* Now emit the load instruction to the same register. */
38950 mode = GET_MODE (mem);
38968 gcc_assert (TARGET_POWERPC64);
38973 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
38976 /* Emit the addis instruction. */
38977 emit_fusion_addis (target, addis_value);
38979 /* Emit the D-form load instruction. */
38980 emit_fusion_load_store (target, target, load_offset, load_str);
38986 /* Return true if the peephole2 can combine a load/store involving a
38987 combination of an addis instruction and the memory operation. This was
38988 added to the ISA 3.0 (power9) hardware. */
38991 fusion_p9_p (rtx addis_reg, /* register set via addis. */
38992 rtx addis_value, /* addis value. */
38993 rtx dest, /* destination (memory or register). */
38994 rtx src) /* source (register or memory). */
38996 rtx addr, mem, offset;
38997 machine_mode mode = GET_MODE (src);
38999 /* Validate arguments. */
39000 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
39003 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
39006 /* Ignore extend operations that are part of the load. */
39007 if (GET_CODE (src) == FLOAT_EXTEND || GET_CODE (src) == ZERO_EXTEND)
39008 src = XEXP (src, 0);
39010 /* Test for memory<-register or register<-memory. */
39011 if (fpr_reg_operand (src, mode) || int_reg_operand (src, mode))
39019 else if (MEM_P (src))
39021 if (!fpr_reg_operand (dest, mode) && !int_reg_operand (dest, mode))
39030 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
39031 if (GET_CODE (addr) == PLUS)
39033 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
39036 return satisfies_constraint_I (XEXP (addr, 1));
39039 else if (GET_CODE (addr) == LO_SUM)
39041 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
39044 offset = XEXP (addr, 1);
39045 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
39046 return small_toc_ref (offset, GET_MODE (offset));
39048 else if (TARGET_ELF && !TARGET_POWERPC64)
39049 return CONSTANT_P (offset);
39055 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
39059 operands[0] register set with addis
39060 operands[1] value set via addis
39061 operands[2] target register being loaded
39062 operands[3] D-form memory reference using operands[0].
39064 This is similar to the fusion introduced with power8, except it scales to
39065 both loads/stores and does not require the result register to be the same as
39066 the base register. At the moment, we only do this if register set with addis
39070 expand_fusion_p9_load (rtx *operands)
39072 rtx tmp_reg = operands[0];
39073 rtx addis_value = operands[1];
39074 rtx target = operands[2];
39075 rtx orig_mem = operands[3];
39076 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn;
39077 enum rtx_code plus_or_lo_sum;
39078 machine_mode target_mode = GET_MODE (target);
39079 machine_mode extend_mode = target_mode;
39080 machine_mode ptr_mode = Pmode;
39081 enum rtx_code extend = UNKNOWN;
39083 if (GET_CODE (orig_mem) == FLOAT_EXTEND || GET_CODE (orig_mem) == ZERO_EXTEND)
39085 extend = GET_CODE (orig_mem);
39086 orig_mem = XEXP (orig_mem, 0);
39087 target_mode = GET_MODE (orig_mem);
39090 gcc_assert (MEM_P (orig_mem));
39092 orig_addr = XEXP (orig_mem, 0);
39093 plus_or_lo_sum = GET_CODE (orig_addr);
39094 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
39096 offset = XEXP (orig_addr, 1);
39097 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
39098 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
39100 if (extend != UNKNOWN)
39101 new_mem = gen_rtx_fmt_e (extend, extend_mode, new_mem);
39103 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
39106 set = gen_rtx_SET (target, new_mem);
39107 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
39108 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
39114 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
39118 operands[0] register set with addis
39119 operands[1] value set via addis
39120 operands[2] target D-form memory being stored to
39121 operands[3] register being stored
39123 This is similar to the fusion introduced with power8, except it scales to
39124 both loads/stores and does not require the result register to be the same as
39125 the base register. At the moment, we only do this if register set with addis
39129 expand_fusion_p9_store (rtx *operands)
39131 rtx tmp_reg = operands[0];
39132 rtx addis_value = operands[1];
39133 rtx orig_mem = operands[2];
39134 rtx src = operands[3];
39135 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn, new_src;
39136 enum rtx_code plus_or_lo_sum;
39137 machine_mode target_mode = GET_MODE (orig_mem);
39138 machine_mode ptr_mode = Pmode;
39140 gcc_assert (MEM_P (orig_mem));
39142 orig_addr = XEXP (orig_mem, 0);
39143 plus_or_lo_sum = GET_CODE (orig_addr);
39144 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
39146 offset = XEXP (orig_addr, 1);
39147 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
39148 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
39150 new_src = gen_rtx_UNSPEC (target_mode, gen_rtvec (1, src),
39153 set = gen_rtx_SET (new_mem, new_src);
39154 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
39155 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
39161 /* Return a string to fuse an addis instruction with a load using extended
39162 fusion. The address that is used is the logical address that was formed
39163 during peephole2: (lo_sum (high) (low-part))
39165 The code is complicated, so we call output_asm_insn directly, and just
39169 emit_fusion_p9_load (rtx reg, rtx mem, rtx tmp_reg)
39171 machine_mode mode = GET_MODE (reg);
39175 const char *load_string;
39178 if (GET_CODE (mem) == FLOAT_EXTEND || GET_CODE (mem) == ZERO_EXTEND)
39180 mem = XEXP (mem, 0);
39181 mode = GET_MODE (mem);
39184 if (GET_CODE (reg) == SUBREG)
39186 gcc_assert (SUBREG_BYTE (reg) == 0);
39187 reg = SUBREG_REG (reg);
39191 fatal_insn ("emit_fusion_p9_load, bad reg #1", reg);
39194 if (FP_REGNO_P (r))
39196 if (mode == SFmode)
39197 load_string = "lfs";
39198 else if (mode == DFmode || mode == DImode)
39199 load_string = "lfd";
39201 gcc_unreachable ();
39203 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
39205 if (mode == SFmode)
39206 load_string = "lxssp";
39207 else if (mode == DFmode || mode == DImode)
39208 load_string = "lxsd";
39210 gcc_unreachable ();
39212 else if (INT_REGNO_P (r))
39217 load_string = "lbz";
39220 load_string = "lhz";
39224 load_string = "lwz";
39228 if (!TARGET_POWERPC64)
39229 gcc_unreachable ();
39230 load_string = "ld";
39233 gcc_unreachable ();
39237 fatal_insn ("emit_fusion_p9_load, bad reg #2", reg);
39240 fatal_insn ("emit_fusion_p9_load not MEM", mem);
39242 addr = XEXP (mem, 0);
39243 fusion_split_address (addr, &hi, &lo);
39245 /* Emit the addis instruction. */
39246 emit_fusion_addis (tmp_reg, hi);
39248 /* Emit the D-form load instruction. */
39249 emit_fusion_load_store (reg, tmp_reg, lo, load_string);
39254 /* Return a string to fuse an addis instruction with a store using extended
39255 fusion. The address that is used is the logical address that was formed
39256 during peephole2: (lo_sum (high) (low-part))
39258 The code is complicated, so we call output_asm_insn directly, and just
39262 emit_fusion_p9_store (rtx mem, rtx reg, rtx tmp_reg)
39264 machine_mode mode = GET_MODE (reg);
39268 const char *store_string;
39271 if (GET_CODE (reg) == SUBREG)
39273 gcc_assert (SUBREG_BYTE (reg) == 0);
39274 reg = SUBREG_REG (reg);
39278 fatal_insn ("emit_fusion_p9_store, bad reg #1", reg);
39281 if (FP_REGNO_P (r))
39283 if (mode == SFmode)
39284 store_string = "stfs";
39285 else if (mode == DFmode)
39286 store_string = "stfd";
39288 gcc_unreachable ();
39290 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
39292 if (mode == SFmode)
39293 store_string = "stxssp";
39294 else if (mode == DFmode || mode == DImode)
39295 store_string = "stxsd";
39297 gcc_unreachable ();
39299 else if (INT_REGNO_P (r))
39304 store_string = "stb";
39307 store_string = "sth";
39311 store_string = "stw";
39315 if (!TARGET_POWERPC64)
39316 gcc_unreachable ();
39317 store_string = "std";
39320 gcc_unreachable ();
39324 fatal_insn ("emit_fusion_p9_store, bad reg #2", reg);
39327 fatal_insn ("emit_fusion_p9_store not MEM", mem);
39329 addr = XEXP (mem, 0);
39330 fusion_split_address (addr, &hi, &lo);
39332 /* Emit the addis instruction. */
39333 emit_fusion_addis (tmp_reg, hi);
39335 /* Emit the D-form load instruction. */
39336 emit_fusion_load_store (reg, tmp_reg, lo, store_string);
39341 #ifdef RS6000_GLIBC_ATOMIC_FENV
39342 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
39343 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
39346 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
39349 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
39351 if (!TARGET_HARD_FLOAT)
39353 #ifdef RS6000_GLIBC_ATOMIC_FENV
39354 if (atomic_hold_decl == NULL_TREE)
39357 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39358 get_identifier ("__atomic_feholdexcept"),
39359 build_function_type_list (void_type_node,
39360 double_ptr_type_node,
39362 TREE_PUBLIC (atomic_hold_decl) = 1;
39363 DECL_EXTERNAL (atomic_hold_decl) = 1;
39366 if (atomic_clear_decl == NULL_TREE)
39369 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39370 get_identifier ("__atomic_feclearexcept"),
39371 build_function_type_list (void_type_node,
39373 TREE_PUBLIC (atomic_clear_decl) = 1;
39374 DECL_EXTERNAL (atomic_clear_decl) = 1;
39377 tree const_double = build_qualified_type (double_type_node,
39379 tree const_double_ptr = build_pointer_type (const_double);
39380 if (atomic_update_decl == NULL_TREE)
39383 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39384 get_identifier ("__atomic_feupdateenv"),
39385 build_function_type_list (void_type_node,
39388 TREE_PUBLIC (atomic_update_decl) = 1;
39389 DECL_EXTERNAL (atomic_update_decl) = 1;
39392 tree fenv_var = create_tmp_var_raw (double_type_node);
39393 TREE_ADDRESSABLE (fenv_var) = 1;
39394 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
39396 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
39397 *clear = build_call_expr (atomic_clear_decl, 0);
39398 *update = build_call_expr (atomic_update_decl, 1,
39399 fold_convert (const_double_ptr, fenv_addr));
39404 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
39405 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
39406 tree call_mffs = build_call_expr (mffs, 0);
39408 /* Generates the equivalent of feholdexcept (&fenv_var)
39410 *fenv_var = __builtin_mffs ();
39412 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
39413 __builtin_mtfsf (0xff, fenv_hold); */
39415 /* Mask to clear everything except for the rounding modes and non-IEEE
39416 arithmetic flag. */
39417 const unsigned HOST_WIDE_INT hold_exception_mask =
39418 HOST_WIDE_INT_C (0xffffffff00000007);
39420 tree fenv_var = create_tmp_var_raw (double_type_node);
39422 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
39424 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
39425 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39426 build_int_cst (uint64_type_node,
39427 hold_exception_mask));
39429 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39432 tree hold_mtfsf = build_call_expr (mtfsf, 2,
39433 build_int_cst (unsigned_type_node, 0xff),
39436 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
39438 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
39440 double fenv_clear = __builtin_mffs ();
39441 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
39442 __builtin_mtfsf (0xff, fenv_clear); */
39444 /* Mask to clear everything except for the rounding modes and non-IEEE
39445 arithmetic flag. */
39446 const unsigned HOST_WIDE_INT clear_exception_mask =
39447 HOST_WIDE_INT_C (0xffffffff00000000);
39449 tree fenv_clear = create_tmp_var_raw (double_type_node);
39451 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
39453 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
39454 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
39456 build_int_cst (uint64_type_node,
39457 clear_exception_mask));
39459 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39460 fenv_clear_llu_and);
39462 tree clear_mtfsf = build_call_expr (mtfsf, 2,
39463 build_int_cst (unsigned_type_node, 0xff),
39466 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
39468 /* Generates the equivalent of feupdateenv (&fenv_var)
39470 double old_fenv = __builtin_mffs ();
39471 double fenv_update;
39472 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
39473 (*(uint64_t*)fenv_var 0x1ff80fff);
39474 __builtin_mtfsf (0xff, fenv_update); */
39476 const unsigned HOST_WIDE_INT update_exception_mask =
39477 HOST_WIDE_INT_C (0xffffffff1fffff00);
39478 const unsigned HOST_WIDE_INT new_exception_mask =
39479 HOST_WIDE_INT_C (0x1ff80fff);
39481 tree old_fenv = create_tmp_var_raw (double_type_node);
39482 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
39484 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
39485 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
39486 build_int_cst (uint64_type_node,
39487 update_exception_mask));
39489 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39490 build_int_cst (uint64_type_node,
39491 new_exception_mask));
39493 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
39494 old_llu_and, new_llu_and);
39496 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39499 tree update_mtfsf = build_call_expr (mtfsf, 2,
39500 build_int_cst (unsigned_type_node, 0xff),
39501 fenv_update_mtfsf);
39503 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
39507 rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
39509 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39511 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39512 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39514 /* The destination of the vmrgew instruction layout is:
39515 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39516 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39517 vmrgew instruction will be correct. */
39518 if (VECTOR_ELT_ORDER_BIG)
39520 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
39522 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
39527 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
39528 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
39531 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39532 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39534 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
39535 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
39537 if (VECTOR_ELT_ORDER_BIG)
39538 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39540 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39544 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
39546 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39548 rtx_tmp0 = gen_reg_rtx (V2DImode);
39549 rtx_tmp1 = gen_reg_rtx (V2DImode);
39551 /* The destination of the vmrgew instruction layout is:
39552 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39553 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39554 vmrgew instruction will be correct. */
39555 if (VECTOR_ELT_ORDER_BIG)
39557 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
39558 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
39562 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
39563 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
39566 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39567 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39569 if (signed_convert)
39571 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
39572 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
39576 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
39577 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
39580 if (VECTOR_ELT_ORDER_BIG)
39581 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39583 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39587 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
39590 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39592 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39593 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39595 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
39596 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
39598 rtx_tmp2 = gen_reg_rtx (V4SImode);
39599 rtx_tmp3 = gen_reg_rtx (V4SImode);
39601 if (signed_convert)
39603 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
39604 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
39608 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
39609 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
39612 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
39615 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39618 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
39619 optimization_type opt_type)
39624 return (opt_type == OPTIMIZE_FOR_SPEED
39625 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
39632 /* Implement TARGET_CONSTANT_ALIGNMENT. */
39634 static HOST_WIDE_INT
39635 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
39637 if (TREE_CODE (exp) == STRING_CST
39638 && (STRICT_ALIGNMENT || !optimize_size))
39639 return MAX (align, BITS_PER_WORD);
39643 /* Implement TARGET_STARTING_FRAME_OFFSET. */
39645 static HOST_WIDE_INT
39646 rs6000_starting_frame_offset (void)
39648 if (FRAME_GROWS_DOWNWARD)
39650 return RS6000_STARTING_FRAME_OFFSET;
39653 struct gcc_target targetm = TARGET_INITIALIZER;
39655 #include "gt-rs6000.h"