1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 /* This file should be included last. */
86 #include "target-def.h"
88 #ifndef TARGET_NO_PROTOTYPE
89 #define TARGET_NO_PROTOTYPE 0
92 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
93 systems will also set long double to be IEEE 128-bit. AIX and Darwin
94 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
95 those systems will not pick up this default. This needs to be after all
96 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
98 #ifndef TARGET_IEEEQUAD_DEFAULT
99 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
100 #define TARGET_IEEEQUAD_DEFAULT 1
102 #define TARGET_IEEEQUAD_DEFAULT 0
106 #define min(A,B) ((A) < (B) ? (A) : (B))
107 #define max(A,B) ((A) > (B) ? (A) : (B))
109 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
111 /* Structure used to define the rs6000 stack */
112 typedef struct rs6000_stack {
113 int reload_completed; /* stack info won't change from here on */
114 int first_gp_reg_save; /* first callee saved GP register used */
115 int first_fp_reg_save; /* first callee saved FP register used */
116 int first_altivec_reg_save; /* first callee saved AltiVec register used */
117 int lr_save_p; /* true if the link reg needs to be saved */
118 int cr_save_p; /* true if the CR reg needs to be saved */
119 unsigned int vrsave_mask; /* mask of vec registers to save */
120 int push_p; /* true if we need to allocate stack space */
121 int calls_p; /* true if the function makes any calls */
122 int world_save_p; /* true if we're saving *everything*:
123 r13-r31, cr, f14-f31, vrsave, v20-v31 */
124 enum rs6000_abi abi; /* which ABI to use */
125 int gp_save_offset; /* offset to save GP regs from initial SP */
126 int fp_save_offset; /* offset to save FP regs from initial SP */
127 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
128 int lr_save_offset; /* offset to save LR from initial SP */
129 int cr_save_offset; /* offset to save CR from initial SP */
130 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
131 int varargs_save_offset; /* offset to save the varargs registers */
132 int ehrd_offset; /* offset to EH return data */
133 int ehcr_offset; /* offset to EH CR field data */
134 int reg_size; /* register size (4 or 8) */
135 HOST_WIDE_INT vars_size; /* variable save area size */
136 int parm_size; /* outgoing parameter size */
137 int save_size; /* save area size */
138 int fixed_size; /* fixed size of stack frame */
139 int gp_size; /* size of saved GP registers */
140 int fp_size; /* size of saved FP registers */
141 int altivec_size; /* size of saved AltiVec registers */
142 int cr_size; /* size to hold CR if not in fixed area */
143 int vrsave_size; /* size to hold VRSAVE */
144 int altivec_padding_size; /* size of altivec alignment padding */
145 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
149 /* A C structure for machine-specific, per-function data.
150 This is added to the cfun structure. */
151 typedef struct GTY(()) machine_function
153 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
154 int ra_needs_full_frame;
155 /* Flags if __builtin_return_address (0) was used. */
157 /* Cache lr_save_p after expansion of builtin_eh_return. */
159 /* Whether we need to save the TOC to the reserved stack location in the
160 function prologue. */
161 bool save_toc_in_prologue;
162 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
163 varargs save area. */
164 HOST_WIDE_INT varargs_save_offset;
165 /* Alternative internal arg pointer for -fsplit-stack. */
166 rtx split_stack_arg_pointer;
167 bool split_stack_argp_used;
168 /* Flag if r2 setup is needed with ELFv2 ABI. */
169 bool r2_setup_needed;
170 /* The number of components we use for separate shrink-wrapping. */
172 /* The components already handled by separate shrink-wrapping, which should
173 not be considered by the prologue and epilogue. */
174 bool gpr_is_wrapped_separately[32];
175 bool fpr_is_wrapped_separately[32];
176 bool lr_is_wrapped_separately;
177 bool toc_is_wrapped_separately;
180 /* Support targetm.vectorize.builtin_mask_for_load. */
181 static GTY(()) tree altivec_builtin_mask_for_load;
183 /* Set to nonzero once AIX common-mode calls have been defined. */
184 static GTY(()) int common_mode_defined;
186 /* Label number of label created for -mrelocatable, to call to so we can
187 get the address of the GOT section */
188 static int rs6000_pic_labelno;
191 /* Counter for labels which are to be placed in .fixup. */
192 int fixuplabelno = 0;
195 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
198 /* Specify the machine mode that pointers have. After generation of rtl, the
199 compiler makes no further distinction between pointers and any other objects
200 of this machine mode. */
201 scalar_int_mode rs6000_pmode;
203 /* Width in bits of a pointer. */
204 unsigned rs6000_pointer_size;
206 #ifdef HAVE_AS_GNU_ATTRIBUTE
207 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
208 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
210 /* Flag whether floating point values have been passed/returned.
211 Note that this doesn't say whether fprs are used, since the
212 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
213 should be set for soft-float values passed in gprs and ieee128
214 values passed in vsx registers. */
215 static bool rs6000_passes_float;
216 static bool rs6000_passes_long_double;
217 /* Flag whether vector values have been passed/returned. */
218 static bool rs6000_passes_vector;
219 /* Flag whether small (<= 8 byte) structures have been returned. */
220 static bool rs6000_returns_struct;
223 /* Value is TRUE if register/mode pair is acceptable. */
224 static bool rs6000_hard_regno_mode_ok_p
225 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
227 /* Maximum number of registers needed for a given register class and mode. */
228 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
230 /* How many registers are needed for a given register and mode. */
231 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
233 /* Map register number to register class. */
234 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
236 static int dbg_cost_ctrl;
238 /* Built in types. */
239 tree rs6000_builtin_types[RS6000_BTI_MAX];
240 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
242 /* Flag to say the TOC is initialized */
243 int toc_initialized, need_toc_init;
244 char toc_label_name[10];
246 /* Cached value of rs6000_variable_issue. This is cached in
247 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
248 static short cached_can_issue_more;
250 static GTY(()) section *read_only_data_section;
251 static GTY(()) section *private_data_section;
252 static GTY(()) section *tls_data_section;
253 static GTY(()) section *tls_private_data_section;
254 static GTY(()) section *read_only_private_data_section;
255 static GTY(()) section *sdata2_section;
256 static GTY(()) section *toc_section;
258 struct builtin_description
260 const HOST_WIDE_INT mask;
261 const enum insn_code icode;
262 const char *const name;
263 const enum rs6000_builtins code;
266 /* Describe the vector unit used for modes. */
267 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
268 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
270 /* Register classes for various constraints that are based on the target
272 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
274 /* Describe the alignment of a vector. */
275 int rs6000_vector_align[NUM_MACHINE_MODES];
277 /* Map selected modes to types for builtins. */
278 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
280 /* What modes to automatically generate reciprocal divide estimate (fre) and
281 reciprocal sqrt (frsqrte) for. */
282 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
284 /* Masks to determine which reciprocal esitmate instructions to generate
286 enum rs6000_recip_mask {
287 RECIP_SF_DIV = 0x001, /* Use divide estimate */
288 RECIP_DF_DIV = 0x002,
289 RECIP_V4SF_DIV = 0x004,
290 RECIP_V2DF_DIV = 0x008,
292 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
293 RECIP_DF_RSQRT = 0x020,
294 RECIP_V4SF_RSQRT = 0x040,
295 RECIP_V2DF_RSQRT = 0x080,
297 /* Various combination of flags for -mrecip=xxx. */
299 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
300 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
301 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
303 RECIP_HIGH_PRECISION = RECIP_ALL,
305 /* On low precision machines like the power5, don't enable double precision
306 reciprocal square root estimate, since it isn't accurate enough. */
307 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
310 /* -mrecip options. */
313 const char *string; /* option name */
314 unsigned int mask; /* mask bits to set */
315 } recip_options[] = {
316 { "all", RECIP_ALL },
317 { "none", RECIP_NONE },
318 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
320 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
321 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
322 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
323 | RECIP_V2DF_RSQRT) },
324 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
325 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
328 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
334 { "power9", PPC_PLATFORM_POWER9 },
335 { "power8", PPC_PLATFORM_POWER8 },
336 { "power7", PPC_PLATFORM_POWER7 },
337 { "power6x", PPC_PLATFORM_POWER6X },
338 { "power6", PPC_PLATFORM_POWER6 },
339 { "power5+", PPC_PLATFORM_POWER5_PLUS },
340 { "power5", PPC_PLATFORM_POWER5 },
341 { "ppc970", PPC_PLATFORM_PPC970 },
342 { "power4", PPC_PLATFORM_POWER4 },
343 { "ppca2", PPC_PLATFORM_PPCA2 },
344 { "ppc476", PPC_PLATFORM_PPC476 },
345 { "ppc464", PPC_PLATFORM_PPC464 },
346 { "ppc440", PPC_PLATFORM_PPC440 },
347 { "ppc405", PPC_PLATFORM_PPC405 },
348 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
351 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
357 } cpu_supports_info[] = {
358 /* AT_HWCAP masks. */
359 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
360 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
361 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
362 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
363 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
364 { "booke", PPC_FEATURE_BOOKE, 0 },
365 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
366 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
367 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
368 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
369 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
370 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
371 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
372 { "notb", PPC_FEATURE_NO_TB, 0 },
373 { "pa6t", PPC_FEATURE_PA6T, 0 },
374 { "power4", PPC_FEATURE_POWER4, 0 },
375 { "power5", PPC_FEATURE_POWER5, 0 },
376 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
377 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
378 { "ppc32", PPC_FEATURE_32, 0 },
379 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
380 { "ppc64", PPC_FEATURE_64, 0 },
381 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
382 { "smt", PPC_FEATURE_SMT, 0 },
383 { "spe", PPC_FEATURE_HAS_SPE, 0 },
384 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
385 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
386 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
388 /* AT_HWCAP2 masks. */
389 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
390 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
391 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
392 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
393 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
394 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
395 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
396 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
397 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
398 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
399 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
400 { "darn", PPC_FEATURE2_DARN, 1 },
401 { "scv", PPC_FEATURE2_SCV, 1 }
404 /* On PowerPC, we have a limited number of target clones that we care about
405 which means we can use an array to hold the options, rather than having more
406 elaborate data structures to identify each possible variation. Order the
407 clones from the default to the highest ISA. */
409 CLONE_DEFAULT = 0, /* default clone. */
410 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
411 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
412 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
413 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
417 /* Map compiler ISA bits into HWCAP names. */
419 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
420 const char *name; /* name to use in __builtin_cpu_supports. */
423 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
424 { 0, "" }, /* Default options. */
425 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
426 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
427 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
428 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
432 /* Newer LIBCs explicitly export this symbol to declare that they provide
433 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
434 reference to this symbol whenever we expand a CPU builtin, so that
435 we never link against an old LIBC. */
436 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
438 /* True if we have expanded a CPU builtin. */
441 /* Pointer to function (in rs6000-c.c) that can define or undefine target
442 macros that have changed. Languages that don't support the preprocessor
443 don't link in rs6000-c.c, so we can't call it directly. */
444 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
446 /* Simplfy register classes into simpler classifications. We assume
447 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
448 check for standard register classes (gpr/floating/altivec/vsx) and
449 floating/vector classes (float/altivec/vsx). */
451 enum rs6000_reg_type {
462 /* Map register class to register type. */
463 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
465 /* First/last register type for the 'normal' register types (i.e. general
466 purpose, floating point, altivec, and VSX registers). */
467 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
469 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
472 /* Register classes we care about in secondary reload or go if legitimate
473 address. We only need to worry about GPR, FPR, and Altivec registers here,
474 along an ANY field that is the OR of the 3 register classes. */
476 enum rs6000_reload_reg_type {
477 RELOAD_REG_GPR, /* General purpose registers. */
478 RELOAD_REG_FPR, /* Traditional floating point regs. */
479 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
480 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
484 /* For setting up register classes, loop through the 3 register classes mapping
485 into real registers, and skip the ANY class, which is just an OR of the
487 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
488 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
490 /* Map reload register type to a register in the register class. */
491 struct reload_reg_map_type {
492 const char *name; /* Register class name. */
493 int reg; /* Register in the register class. */
496 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
497 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
498 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
499 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
500 { "Any", -1 }, /* RELOAD_REG_ANY. */
503 /* Mask bits for each register class, indexed per mode. Historically the
504 compiler has been more restrictive which types can do PRE_MODIFY instead of
505 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
506 typedef unsigned char addr_mask_type;
508 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
509 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
510 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
511 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
512 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
513 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
514 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
515 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
517 /* Register type masks based on the type, of valid addressing modes. */
518 struct rs6000_reg_addr {
519 enum insn_code reload_load; /* INSN to reload for loading. */
520 enum insn_code reload_store; /* INSN to reload for storing. */
521 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
522 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
523 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
524 enum insn_code fusion_gpr_ld; /* INSN for fusing gpr ADDIS/loads. */
525 /* INSNs for fusing addi with loads
526 or stores for each reg. class. */
527 enum insn_code fusion_addi_ld[(int)N_RELOAD_REG];
528 enum insn_code fusion_addi_st[(int)N_RELOAD_REG];
529 /* INSNs for fusing addis with loads
530 or stores for each reg. class. */
531 enum insn_code fusion_addis_ld[(int)N_RELOAD_REG];
532 enum insn_code fusion_addis_st[(int)N_RELOAD_REG];
533 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
534 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
535 bool fused_toc; /* Mode supports TOC fusion. */
538 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
540 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
542 mode_supports_pre_incdec_p (machine_mode mode)
544 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
548 /* Helper function to say whether a mode supports PRE_MODIFY. */
550 mode_supports_pre_modify_p (machine_mode mode)
552 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
556 /* Given that there exists at least one variable that is set (produced)
557 by OUT_INSN and read (consumed) by IN_INSN, return true iff
558 IN_INSN represents one or more memory store operations and none of
559 the variables set by OUT_INSN is used by IN_INSN as the address of a
560 store operation. If either IN_INSN or OUT_INSN does not represent
561 a "single" RTL SET expression (as loosely defined by the
562 implementation of the single_set function) or a PARALLEL with only
563 SETs, CLOBBERs, and USEs inside, this function returns false.
565 This rs6000-specific version of store_data_bypass_p checks for
566 certain conditions that result in assertion failures (and internal
567 compiler errors) in the generic store_data_bypass_p function and
568 returns false rather than calling store_data_bypass_p if one of the
569 problematic conditions is detected. */
572 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
579 in_set = single_set (in_insn);
582 if (MEM_P (SET_DEST (in_set)))
584 out_set = single_set (out_insn);
587 out_pat = PATTERN (out_insn);
588 if (GET_CODE (out_pat) == PARALLEL)
590 for (i = 0; i < XVECLEN (out_pat, 0); i++)
592 out_exp = XVECEXP (out_pat, 0, i);
593 if ((GET_CODE (out_exp) == CLOBBER)
594 || (GET_CODE (out_exp) == USE))
596 else if (GET_CODE (out_exp) != SET)
605 in_pat = PATTERN (in_insn);
606 if (GET_CODE (in_pat) != PARALLEL)
609 for (i = 0; i < XVECLEN (in_pat, 0); i++)
611 in_exp = XVECEXP (in_pat, 0, i);
612 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
614 else if (GET_CODE (in_exp) != SET)
617 if (MEM_P (SET_DEST (in_exp)))
619 out_set = single_set (out_insn);
622 out_pat = PATTERN (out_insn);
623 if (GET_CODE (out_pat) != PARALLEL)
625 for (j = 0; j < XVECLEN (out_pat, 0); j++)
627 out_exp = XVECEXP (out_pat, 0, j);
628 if ((GET_CODE (out_exp) == CLOBBER)
629 || (GET_CODE (out_exp) == USE))
631 else if (GET_CODE (out_exp) != SET)
638 return store_data_bypass_p (out_insn, in_insn);
641 /* Return true if we have D-form addressing in altivec registers. */
643 mode_supports_vmx_dform (machine_mode mode)
645 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
648 /* Return true if we have D-form addressing in VSX registers. This addressing
649 is more limited than normal d-form addressing in that the offset must be
650 aligned on a 16-byte boundary. */
652 mode_supports_vsx_dform_quad (machine_mode mode)
654 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
659 /* Processor costs (relative to an add) */
661 const struct processor_costs *rs6000_cost;
663 /* Instruction size costs on 32bit processors. */
665 struct processor_costs size32_cost = {
666 COSTS_N_INSNS (1), /* mulsi */
667 COSTS_N_INSNS (1), /* mulsi_const */
668 COSTS_N_INSNS (1), /* mulsi_const9 */
669 COSTS_N_INSNS (1), /* muldi */
670 COSTS_N_INSNS (1), /* divsi */
671 COSTS_N_INSNS (1), /* divdi */
672 COSTS_N_INSNS (1), /* fp */
673 COSTS_N_INSNS (1), /* dmul */
674 COSTS_N_INSNS (1), /* sdiv */
675 COSTS_N_INSNS (1), /* ddiv */
676 32, /* cache line size */
680 0, /* SF->DF convert */
683 /* Instruction size costs on 64bit processors. */
685 struct processor_costs size64_cost = {
686 COSTS_N_INSNS (1), /* mulsi */
687 COSTS_N_INSNS (1), /* mulsi_const */
688 COSTS_N_INSNS (1), /* mulsi_const9 */
689 COSTS_N_INSNS (1), /* muldi */
690 COSTS_N_INSNS (1), /* divsi */
691 COSTS_N_INSNS (1), /* divdi */
692 COSTS_N_INSNS (1), /* fp */
693 COSTS_N_INSNS (1), /* dmul */
694 COSTS_N_INSNS (1), /* sdiv */
695 COSTS_N_INSNS (1), /* ddiv */
696 128, /* cache line size */
700 0, /* SF->DF convert */
703 /* Instruction costs on RS64A processors. */
705 struct processor_costs rs64a_cost = {
706 COSTS_N_INSNS (20), /* mulsi */
707 COSTS_N_INSNS (12), /* mulsi_const */
708 COSTS_N_INSNS (8), /* mulsi_const9 */
709 COSTS_N_INSNS (34), /* muldi */
710 COSTS_N_INSNS (65), /* divsi */
711 COSTS_N_INSNS (67), /* divdi */
712 COSTS_N_INSNS (4), /* fp */
713 COSTS_N_INSNS (4), /* dmul */
714 COSTS_N_INSNS (31), /* sdiv */
715 COSTS_N_INSNS (31), /* ddiv */
716 128, /* cache line size */
720 0, /* SF->DF convert */
723 /* Instruction costs on MPCCORE processors. */
725 struct processor_costs mpccore_cost = {
726 COSTS_N_INSNS (2), /* mulsi */
727 COSTS_N_INSNS (2), /* mulsi_const */
728 COSTS_N_INSNS (2), /* mulsi_const9 */
729 COSTS_N_INSNS (2), /* muldi */
730 COSTS_N_INSNS (6), /* divsi */
731 COSTS_N_INSNS (6), /* divdi */
732 COSTS_N_INSNS (4), /* fp */
733 COSTS_N_INSNS (5), /* dmul */
734 COSTS_N_INSNS (10), /* sdiv */
735 COSTS_N_INSNS (17), /* ddiv */
736 32, /* cache line size */
740 0, /* SF->DF convert */
743 /* Instruction costs on PPC403 processors. */
745 struct processor_costs ppc403_cost = {
746 COSTS_N_INSNS (4), /* mulsi */
747 COSTS_N_INSNS (4), /* mulsi_const */
748 COSTS_N_INSNS (4), /* mulsi_const9 */
749 COSTS_N_INSNS (4), /* muldi */
750 COSTS_N_INSNS (33), /* divsi */
751 COSTS_N_INSNS (33), /* divdi */
752 COSTS_N_INSNS (11), /* fp */
753 COSTS_N_INSNS (11), /* dmul */
754 COSTS_N_INSNS (11), /* sdiv */
755 COSTS_N_INSNS (11), /* ddiv */
756 32, /* cache line size */
760 0, /* SF->DF convert */
763 /* Instruction costs on PPC405 processors. */
765 struct processor_costs ppc405_cost = {
766 COSTS_N_INSNS (5), /* mulsi */
767 COSTS_N_INSNS (4), /* mulsi_const */
768 COSTS_N_INSNS (3), /* mulsi_const9 */
769 COSTS_N_INSNS (5), /* muldi */
770 COSTS_N_INSNS (35), /* divsi */
771 COSTS_N_INSNS (35), /* divdi */
772 COSTS_N_INSNS (11), /* fp */
773 COSTS_N_INSNS (11), /* dmul */
774 COSTS_N_INSNS (11), /* sdiv */
775 COSTS_N_INSNS (11), /* ddiv */
776 32, /* cache line size */
780 0, /* SF->DF convert */
783 /* Instruction costs on PPC440 processors. */
785 struct processor_costs ppc440_cost = {
786 COSTS_N_INSNS (3), /* mulsi */
787 COSTS_N_INSNS (2), /* mulsi_const */
788 COSTS_N_INSNS (2), /* mulsi_const9 */
789 COSTS_N_INSNS (3), /* muldi */
790 COSTS_N_INSNS (34), /* divsi */
791 COSTS_N_INSNS (34), /* divdi */
792 COSTS_N_INSNS (5), /* fp */
793 COSTS_N_INSNS (5), /* dmul */
794 COSTS_N_INSNS (19), /* sdiv */
795 COSTS_N_INSNS (33), /* ddiv */
796 32, /* cache line size */
800 0, /* SF->DF convert */
803 /* Instruction costs on PPC476 processors. */
805 struct processor_costs ppc476_cost = {
806 COSTS_N_INSNS (4), /* mulsi */
807 COSTS_N_INSNS (4), /* mulsi_const */
808 COSTS_N_INSNS (4), /* mulsi_const9 */
809 COSTS_N_INSNS (4), /* muldi */
810 COSTS_N_INSNS (11), /* divsi */
811 COSTS_N_INSNS (11), /* divdi */
812 COSTS_N_INSNS (6), /* fp */
813 COSTS_N_INSNS (6), /* dmul */
814 COSTS_N_INSNS (19), /* sdiv */
815 COSTS_N_INSNS (33), /* ddiv */
816 32, /* l1 cache line size */
820 0, /* SF->DF convert */
823 /* Instruction costs on PPC601 processors. */
825 struct processor_costs ppc601_cost = {
826 COSTS_N_INSNS (5), /* mulsi */
827 COSTS_N_INSNS (5), /* mulsi_const */
828 COSTS_N_INSNS (5), /* mulsi_const9 */
829 COSTS_N_INSNS (5), /* muldi */
830 COSTS_N_INSNS (36), /* divsi */
831 COSTS_N_INSNS (36), /* divdi */
832 COSTS_N_INSNS (4), /* fp */
833 COSTS_N_INSNS (5), /* dmul */
834 COSTS_N_INSNS (17), /* sdiv */
835 COSTS_N_INSNS (31), /* ddiv */
836 32, /* cache line size */
840 0, /* SF->DF convert */
843 /* Instruction costs on PPC603 processors. */
845 struct processor_costs ppc603_cost = {
846 COSTS_N_INSNS (5), /* mulsi */
847 COSTS_N_INSNS (3), /* mulsi_const */
848 COSTS_N_INSNS (2), /* mulsi_const9 */
849 COSTS_N_INSNS (5), /* muldi */
850 COSTS_N_INSNS (37), /* divsi */
851 COSTS_N_INSNS (37), /* divdi */
852 COSTS_N_INSNS (3), /* fp */
853 COSTS_N_INSNS (4), /* dmul */
854 COSTS_N_INSNS (18), /* sdiv */
855 COSTS_N_INSNS (33), /* ddiv */
856 32, /* cache line size */
860 0, /* SF->DF convert */
863 /* Instruction costs on PPC604 processors. */
865 struct processor_costs ppc604_cost = {
866 COSTS_N_INSNS (4), /* mulsi */
867 COSTS_N_INSNS (4), /* mulsi_const */
868 COSTS_N_INSNS (4), /* mulsi_const9 */
869 COSTS_N_INSNS (4), /* muldi */
870 COSTS_N_INSNS (20), /* divsi */
871 COSTS_N_INSNS (20), /* divdi */
872 COSTS_N_INSNS (3), /* fp */
873 COSTS_N_INSNS (3), /* dmul */
874 COSTS_N_INSNS (18), /* sdiv */
875 COSTS_N_INSNS (32), /* ddiv */
876 32, /* cache line size */
880 0, /* SF->DF convert */
883 /* Instruction costs on PPC604e processors. */
885 struct processor_costs ppc604e_cost = {
886 COSTS_N_INSNS (2), /* mulsi */
887 COSTS_N_INSNS (2), /* mulsi_const */
888 COSTS_N_INSNS (2), /* mulsi_const9 */
889 COSTS_N_INSNS (2), /* muldi */
890 COSTS_N_INSNS (20), /* divsi */
891 COSTS_N_INSNS (20), /* divdi */
892 COSTS_N_INSNS (3), /* fp */
893 COSTS_N_INSNS (3), /* dmul */
894 COSTS_N_INSNS (18), /* sdiv */
895 COSTS_N_INSNS (32), /* ddiv */
896 32, /* cache line size */
900 0, /* SF->DF convert */
903 /* Instruction costs on PPC620 processors. */
905 struct processor_costs ppc620_cost = {
906 COSTS_N_INSNS (5), /* mulsi */
907 COSTS_N_INSNS (4), /* mulsi_const */
908 COSTS_N_INSNS (3), /* mulsi_const9 */
909 COSTS_N_INSNS (7), /* muldi */
910 COSTS_N_INSNS (21), /* divsi */
911 COSTS_N_INSNS (37), /* divdi */
912 COSTS_N_INSNS (3), /* fp */
913 COSTS_N_INSNS (3), /* dmul */
914 COSTS_N_INSNS (18), /* sdiv */
915 COSTS_N_INSNS (32), /* ddiv */
916 128, /* cache line size */
920 0, /* SF->DF convert */
923 /* Instruction costs on PPC630 processors. */
925 struct processor_costs ppc630_cost = {
926 COSTS_N_INSNS (5), /* mulsi */
927 COSTS_N_INSNS (4), /* mulsi_const */
928 COSTS_N_INSNS (3), /* mulsi_const9 */
929 COSTS_N_INSNS (7), /* muldi */
930 COSTS_N_INSNS (21), /* divsi */
931 COSTS_N_INSNS (37), /* divdi */
932 COSTS_N_INSNS (3), /* fp */
933 COSTS_N_INSNS (3), /* dmul */
934 COSTS_N_INSNS (17), /* sdiv */
935 COSTS_N_INSNS (21), /* ddiv */
936 128, /* cache line size */
940 0, /* SF->DF convert */
943 /* Instruction costs on Cell processor. */
944 /* COSTS_N_INSNS (1) ~ one add. */
946 struct processor_costs ppccell_cost = {
947 COSTS_N_INSNS (9/2)+2, /* mulsi */
948 COSTS_N_INSNS (6/2), /* mulsi_const */
949 COSTS_N_INSNS (6/2), /* mulsi_const9 */
950 COSTS_N_INSNS (15/2)+2, /* muldi */
951 COSTS_N_INSNS (38/2), /* divsi */
952 COSTS_N_INSNS (70/2), /* divdi */
953 COSTS_N_INSNS (10/2), /* fp */
954 COSTS_N_INSNS (10/2), /* dmul */
955 COSTS_N_INSNS (74/2), /* sdiv */
956 COSTS_N_INSNS (74/2), /* ddiv */
957 128, /* cache line size */
961 0, /* SF->DF convert */
964 /* Instruction costs on PPC750 and PPC7400 processors. */
966 struct processor_costs ppc750_cost = {
967 COSTS_N_INSNS (5), /* mulsi */
968 COSTS_N_INSNS (3), /* mulsi_const */
969 COSTS_N_INSNS (2), /* mulsi_const9 */
970 COSTS_N_INSNS (5), /* muldi */
971 COSTS_N_INSNS (17), /* divsi */
972 COSTS_N_INSNS (17), /* divdi */
973 COSTS_N_INSNS (3), /* fp */
974 COSTS_N_INSNS (3), /* dmul */
975 COSTS_N_INSNS (17), /* sdiv */
976 COSTS_N_INSNS (31), /* ddiv */
977 32, /* cache line size */
981 0, /* SF->DF convert */
984 /* Instruction costs on PPC7450 processors. */
986 struct processor_costs ppc7450_cost = {
987 COSTS_N_INSNS (4), /* mulsi */
988 COSTS_N_INSNS (3), /* mulsi_const */
989 COSTS_N_INSNS (3), /* mulsi_const9 */
990 COSTS_N_INSNS (4), /* muldi */
991 COSTS_N_INSNS (23), /* divsi */
992 COSTS_N_INSNS (23), /* divdi */
993 COSTS_N_INSNS (5), /* fp */
994 COSTS_N_INSNS (5), /* dmul */
995 COSTS_N_INSNS (21), /* sdiv */
996 COSTS_N_INSNS (35), /* ddiv */
997 32, /* cache line size */
1001 0, /* SF->DF convert */
1004 /* Instruction costs on PPC8540 processors. */
1006 struct processor_costs ppc8540_cost = {
1007 COSTS_N_INSNS (4), /* mulsi */
1008 COSTS_N_INSNS (4), /* mulsi_const */
1009 COSTS_N_INSNS (4), /* mulsi_const9 */
1010 COSTS_N_INSNS (4), /* muldi */
1011 COSTS_N_INSNS (19), /* divsi */
1012 COSTS_N_INSNS (19), /* divdi */
1013 COSTS_N_INSNS (4), /* fp */
1014 COSTS_N_INSNS (4), /* dmul */
1015 COSTS_N_INSNS (29), /* sdiv */
1016 COSTS_N_INSNS (29), /* ddiv */
1017 32, /* cache line size */
1020 1, /* prefetch streams /*/
1021 0, /* SF->DF convert */
1024 /* Instruction costs on E300C2 and E300C3 cores. */
1026 struct processor_costs ppce300c2c3_cost = {
1027 COSTS_N_INSNS (4), /* mulsi */
1028 COSTS_N_INSNS (4), /* mulsi_const */
1029 COSTS_N_INSNS (4), /* mulsi_const9 */
1030 COSTS_N_INSNS (4), /* muldi */
1031 COSTS_N_INSNS (19), /* divsi */
1032 COSTS_N_INSNS (19), /* divdi */
1033 COSTS_N_INSNS (3), /* fp */
1034 COSTS_N_INSNS (4), /* dmul */
1035 COSTS_N_INSNS (18), /* sdiv */
1036 COSTS_N_INSNS (33), /* ddiv */
1040 1, /* prefetch streams /*/
1041 0, /* SF->DF convert */
1044 /* Instruction costs on PPCE500MC processors. */
1046 struct processor_costs ppce500mc_cost = {
1047 COSTS_N_INSNS (4), /* mulsi */
1048 COSTS_N_INSNS (4), /* mulsi_const */
1049 COSTS_N_INSNS (4), /* mulsi_const9 */
1050 COSTS_N_INSNS (4), /* muldi */
1051 COSTS_N_INSNS (14), /* divsi */
1052 COSTS_N_INSNS (14), /* divdi */
1053 COSTS_N_INSNS (8), /* fp */
1054 COSTS_N_INSNS (10), /* dmul */
1055 COSTS_N_INSNS (36), /* sdiv */
1056 COSTS_N_INSNS (66), /* ddiv */
1057 64, /* cache line size */
1060 1, /* prefetch streams /*/
1061 0, /* SF->DF convert */
1064 /* Instruction costs on PPCE500MC64 processors. */
1066 struct processor_costs ppce500mc64_cost = {
1067 COSTS_N_INSNS (4), /* mulsi */
1068 COSTS_N_INSNS (4), /* mulsi_const */
1069 COSTS_N_INSNS (4), /* mulsi_const9 */
1070 COSTS_N_INSNS (4), /* muldi */
1071 COSTS_N_INSNS (14), /* divsi */
1072 COSTS_N_INSNS (14), /* divdi */
1073 COSTS_N_INSNS (4), /* fp */
1074 COSTS_N_INSNS (10), /* dmul */
1075 COSTS_N_INSNS (36), /* sdiv */
1076 COSTS_N_INSNS (66), /* ddiv */
1077 64, /* cache line size */
1080 1, /* prefetch streams /*/
1081 0, /* SF->DF convert */
1084 /* Instruction costs on PPCE5500 processors. */
1086 struct processor_costs ppce5500_cost = {
1087 COSTS_N_INSNS (5), /* mulsi */
1088 COSTS_N_INSNS (5), /* mulsi_const */
1089 COSTS_N_INSNS (4), /* mulsi_const9 */
1090 COSTS_N_INSNS (5), /* muldi */
1091 COSTS_N_INSNS (14), /* divsi */
1092 COSTS_N_INSNS (14), /* divdi */
1093 COSTS_N_INSNS (7), /* fp */
1094 COSTS_N_INSNS (10), /* dmul */
1095 COSTS_N_INSNS (36), /* sdiv */
1096 COSTS_N_INSNS (66), /* ddiv */
1097 64, /* cache line size */
1100 1, /* prefetch streams /*/
1101 0, /* SF->DF convert */
1104 /* Instruction costs on PPCE6500 processors. */
1106 struct processor_costs ppce6500_cost = {
1107 COSTS_N_INSNS (5), /* mulsi */
1108 COSTS_N_INSNS (5), /* mulsi_const */
1109 COSTS_N_INSNS (4), /* mulsi_const9 */
1110 COSTS_N_INSNS (5), /* muldi */
1111 COSTS_N_INSNS (14), /* divsi */
1112 COSTS_N_INSNS (14), /* divdi */
1113 COSTS_N_INSNS (7), /* fp */
1114 COSTS_N_INSNS (10), /* dmul */
1115 COSTS_N_INSNS (36), /* sdiv */
1116 COSTS_N_INSNS (66), /* ddiv */
1117 64, /* cache line size */
1120 1, /* prefetch streams /*/
1121 0, /* SF->DF convert */
1124 /* Instruction costs on AppliedMicro Titan processors. */
1126 struct processor_costs titan_cost = {
1127 COSTS_N_INSNS (5), /* mulsi */
1128 COSTS_N_INSNS (5), /* mulsi_const */
1129 COSTS_N_INSNS (5), /* mulsi_const9 */
1130 COSTS_N_INSNS (5), /* muldi */
1131 COSTS_N_INSNS (18), /* divsi */
1132 COSTS_N_INSNS (18), /* divdi */
1133 COSTS_N_INSNS (10), /* fp */
1134 COSTS_N_INSNS (10), /* dmul */
1135 COSTS_N_INSNS (46), /* sdiv */
1136 COSTS_N_INSNS (72), /* ddiv */
1137 32, /* cache line size */
1140 1, /* prefetch streams /*/
1141 0, /* SF->DF convert */
1144 /* Instruction costs on POWER4 and POWER5 processors. */
1146 struct processor_costs power4_cost = {
1147 COSTS_N_INSNS (3), /* mulsi */
1148 COSTS_N_INSNS (2), /* mulsi_const */
1149 COSTS_N_INSNS (2), /* mulsi_const9 */
1150 COSTS_N_INSNS (4), /* muldi */
1151 COSTS_N_INSNS (18), /* divsi */
1152 COSTS_N_INSNS (34), /* divdi */
1153 COSTS_N_INSNS (3), /* fp */
1154 COSTS_N_INSNS (3), /* dmul */
1155 COSTS_N_INSNS (17), /* sdiv */
1156 COSTS_N_INSNS (17), /* ddiv */
1157 128, /* cache line size */
1159 1024, /* l2 cache */
1160 8, /* prefetch streams /*/
1161 0, /* SF->DF convert */
1164 /* Instruction costs on POWER6 processors. */
1166 struct processor_costs power6_cost = {
1167 COSTS_N_INSNS (8), /* mulsi */
1168 COSTS_N_INSNS (8), /* mulsi_const */
1169 COSTS_N_INSNS (8), /* mulsi_const9 */
1170 COSTS_N_INSNS (8), /* muldi */
1171 COSTS_N_INSNS (22), /* divsi */
1172 COSTS_N_INSNS (28), /* divdi */
1173 COSTS_N_INSNS (3), /* fp */
1174 COSTS_N_INSNS (3), /* dmul */
1175 COSTS_N_INSNS (13), /* sdiv */
1176 COSTS_N_INSNS (16), /* ddiv */
1177 128, /* cache line size */
1179 2048, /* l2 cache */
1180 16, /* prefetch streams */
1181 0, /* SF->DF convert */
1184 /* Instruction costs on POWER7 processors. */
1186 struct processor_costs power7_cost = {
1187 COSTS_N_INSNS (2), /* mulsi */
1188 COSTS_N_INSNS (2), /* mulsi_const */
1189 COSTS_N_INSNS (2), /* mulsi_const9 */
1190 COSTS_N_INSNS (2), /* muldi */
1191 COSTS_N_INSNS (18), /* divsi */
1192 COSTS_N_INSNS (34), /* divdi */
1193 COSTS_N_INSNS (3), /* fp */
1194 COSTS_N_INSNS (3), /* dmul */
1195 COSTS_N_INSNS (13), /* sdiv */
1196 COSTS_N_INSNS (16), /* ddiv */
1197 128, /* cache line size */
1200 12, /* prefetch streams */
1201 COSTS_N_INSNS (3), /* SF->DF convert */
1204 /* Instruction costs on POWER8 processors. */
1206 struct processor_costs power8_cost = {
1207 COSTS_N_INSNS (3), /* mulsi */
1208 COSTS_N_INSNS (3), /* mulsi_const */
1209 COSTS_N_INSNS (3), /* mulsi_const9 */
1210 COSTS_N_INSNS (3), /* muldi */
1211 COSTS_N_INSNS (19), /* divsi */
1212 COSTS_N_INSNS (35), /* divdi */
1213 COSTS_N_INSNS (3), /* fp */
1214 COSTS_N_INSNS (3), /* dmul */
1215 COSTS_N_INSNS (14), /* sdiv */
1216 COSTS_N_INSNS (17), /* ddiv */
1217 128, /* cache line size */
1220 12, /* prefetch streams */
1221 COSTS_N_INSNS (3), /* SF->DF convert */
1224 /* Instruction costs on POWER9 processors. */
1226 struct processor_costs power9_cost = {
1227 COSTS_N_INSNS (3), /* mulsi */
1228 COSTS_N_INSNS (3), /* mulsi_const */
1229 COSTS_N_INSNS (3), /* mulsi_const9 */
1230 COSTS_N_INSNS (3), /* muldi */
1231 COSTS_N_INSNS (8), /* divsi */
1232 COSTS_N_INSNS (12), /* divdi */
1233 COSTS_N_INSNS (3), /* fp */
1234 COSTS_N_INSNS (3), /* dmul */
1235 COSTS_N_INSNS (13), /* sdiv */
1236 COSTS_N_INSNS (18), /* ddiv */
1237 128, /* cache line size */
1240 8, /* prefetch streams */
1241 COSTS_N_INSNS (3), /* SF->DF convert */
1244 /* Instruction costs on POWER A2 processors. */
1246 struct processor_costs ppca2_cost = {
1247 COSTS_N_INSNS (16), /* mulsi */
1248 COSTS_N_INSNS (16), /* mulsi_const */
1249 COSTS_N_INSNS (16), /* mulsi_const9 */
1250 COSTS_N_INSNS (16), /* muldi */
1251 COSTS_N_INSNS (22), /* divsi */
1252 COSTS_N_INSNS (28), /* divdi */
1253 COSTS_N_INSNS (3), /* fp */
1254 COSTS_N_INSNS (3), /* dmul */
1255 COSTS_N_INSNS (59), /* sdiv */
1256 COSTS_N_INSNS (72), /* ddiv */
1259 2048, /* l2 cache */
1260 16, /* prefetch streams */
1261 0, /* SF->DF convert */
1265 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1266 #undef RS6000_BUILTIN_0
1267 #undef RS6000_BUILTIN_1
1268 #undef RS6000_BUILTIN_2
1269 #undef RS6000_BUILTIN_3
1270 #undef RS6000_BUILTIN_A
1271 #undef RS6000_BUILTIN_D
1272 #undef RS6000_BUILTIN_H
1273 #undef RS6000_BUILTIN_P
1274 #undef RS6000_BUILTIN_Q
1275 #undef RS6000_BUILTIN_X
1277 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1278 { NAME, ICODE, MASK, ATTR },
1280 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1281 { NAME, ICODE, MASK, ATTR },
1283 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1284 { NAME, ICODE, MASK, ATTR },
1286 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1287 { NAME, ICODE, MASK, ATTR },
1289 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1290 { NAME, ICODE, MASK, ATTR },
1292 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1293 { NAME, ICODE, MASK, ATTR },
1295 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1296 { NAME, ICODE, MASK, ATTR },
1298 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1299 { NAME, ICODE, MASK, ATTR },
1301 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1302 { NAME, ICODE, MASK, ATTR },
1304 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1305 { NAME, ICODE, MASK, ATTR },
1307 struct rs6000_builtin_info_type {
1309 const enum insn_code icode;
1310 const HOST_WIDE_INT mask;
1311 const unsigned attr;
1314 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1316 #include "rs6000-builtin.def"
1319 #undef RS6000_BUILTIN_0
1320 #undef RS6000_BUILTIN_1
1321 #undef RS6000_BUILTIN_2
1322 #undef RS6000_BUILTIN_3
1323 #undef RS6000_BUILTIN_A
1324 #undef RS6000_BUILTIN_D
1325 #undef RS6000_BUILTIN_H
1326 #undef RS6000_BUILTIN_P
1327 #undef RS6000_BUILTIN_Q
1328 #undef RS6000_BUILTIN_X
1330 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1331 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1334 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1335 static struct machine_function * rs6000_init_machine_status (void);
1336 static int rs6000_ra_ever_killed (void);
1337 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1338 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1339 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1340 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1341 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1342 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1343 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1344 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1346 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1348 static bool is_microcoded_insn (rtx_insn *);
1349 static bool is_nonpipeline_insn (rtx_insn *);
1350 static bool is_cracked_insn (rtx_insn *);
1351 static bool is_load_insn (rtx, rtx *);
1352 static bool is_store_insn (rtx, rtx *);
1353 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1354 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1355 static bool insn_must_be_first_in_group (rtx_insn *);
1356 static bool insn_must_be_last_in_group (rtx_insn *);
1357 static void altivec_init_builtins (void);
1358 static tree builtin_function_type (machine_mode, machine_mode,
1359 machine_mode, machine_mode,
1360 enum rs6000_builtins, const char *name);
1361 static void rs6000_common_init_builtins (void);
1362 static void paired_init_builtins (void);
1363 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
1364 static void htm_init_builtins (void);
1365 static rs6000_stack_t *rs6000_stack_info (void);
1366 static void is_altivec_return_reg (rtx, void *);
1367 int easy_vector_constant (rtx, machine_mode);
1368 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1369 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1370 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1373 static void macho_branch_islands (void);
1375 static rtx rs6000_legitimize_reload_address (rtx, machine_mode, int, int,
1377 static rtx rs6000_debug_legitimize_reload_address (rtx, machine_mode, int,
1379 static bool rs6000_mode_dependent_address (const_rtx);
1380 static bool rs6000_debug_mode_dependent_address (const_rtx);
1381 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1383 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1386 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1387 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1389 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1392 static bool rs6000_debug_can_change_mode_class (machine_mode,
1395 static bool rs6000_save_toc_in_prologue_p (void);
1396 static rtx rs6000_internal_arg_pointer (void);
1398 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode, int, int,
1400 = rs6000_legitimize_reload_address;
1402 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1403 = rs6000_mode_dependent_address;
1405 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1407 = rs6000_secondary_reload_class;
1409 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1410 = rs6000_preferred_reload_class;
1412 const int INSN_NOT_AVAILABLE = -1;
1414 static void rs6000_print_isa_options (FILE *, int, const char *,
1416 static void rs6000_print_builtin_options (FILE *, int, const char *,
1418 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1420 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1421 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1422 enum rs6000_reg_type,
1424 secondary_reload_info *,
1426 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1427 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1428 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1430 /* Hash table stuff for keeping track of TOC entries. */
1432 struct GTY((for_user)) toc_hash_struct
1434 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1435 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1437 machine_mode key_mode;
1441 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1443 static hashval_t hash (toc_hash_struct *);
1444 static bool equal (toc_hash_struct *, toc_hash_struct *);
1447 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1449 /* Hash table to keep track of the argument types for builtin functions. */
1451 struct GTY((for_user)) builtin_hash_struct
1454 machine_mode mode[4]; /* return value + 3 arguments. */
1455 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1458 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1460 static hashval_t hash (builtin_hash_struct *);
1461 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1464 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1467 /* Default register names. */
1468 char rs6000_reg_names[][8] =
1470 "0", "1", "2", "3", "4", "5", "6", "7",
1471 "8", "9", "10", "11", "12", "13", "14", "15",
1472 "16", "17", "18", "19", "20", "21", "22", "23",
1473 "24", "25", "26", "27", "28", "29", "30", "31",
1474 "0", "1", "2", "3", "4", "5", "6", "7",
1475 "8", "9", "10", "11", "12", "13", "14", "15",
1476 "16", "17", "18", "19", "20", "21", "22", "23",
1477 "24", "25", "26", "27", "28", "29", "30", "31",
1478 "mq", "lr", "ctr","ap",
1479 "0", "1", "2", "3", "4", "5", "6", "7",
1481 /* AltiVec registers. */
1482 "0", "1", "2", "3", "4", "5", "6", "7",
1483 "8", "9", "10", "11", "12", "13", "14", "15",
1484 "16", "17", "18", "19", "20", "21", "22", "23",
1485 "24", "25", "26", "27", "28", "29", "30", "31",
1487 /* Soft frame pointer. */
1489 /* HTM SPR registers. */
1490 "tfhar", "tfiar", "texasr"
1493 #ifdef TARGET_REGNAMES
1494 static const char alt_reg_names[][8] =
1496 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1497 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1498 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1499 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1500 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1501 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1502 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1503 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1504 "mq", "lr", "ctr", "ap",
1505 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1507 /* AltiVec registers. */
1508 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1509 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1510 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1511 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1513 /* Soft frame pointer. */
1515 /* HTM SPR registers. */
1516 "tfhar", "tfiar", "texasr"
1520 /* Table of valid machine attributes. */
1522 static const struct attribute_spec rs6000_attribute_table[] =
1524 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1525 affects_type_identity, handler, exclude } */
1526 { "altivec", 1, 1, false, true, false, false,
1527 rs6000_handle_altivec_attribute, NULL },
1528 { "longcall", 0, 0, false, true, true, false,
1529 rs6000_handle_longcall_attribute, NULL },
1530 { "shortcall", 0, 0, false, true, true, false,
1531 rs6000_handle_longcall_attribute, NULL },
1532 { "ms_struct", 0, 0, false, false, false, false,
1533 rs6000_handle_struct_attribute, NULL },
1534 { "gcc_struct", 0, 0, false, false, false, false,
1535 rs6000_handle_struct_attribute, NULL },
1536 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1537 SUBTARGET_ATTRIBUTE_TABLE,
1539 { NULL, 0, 0, false, false, false, false, NULL, NULL }
1542 #ifndef TARGET_PROFILE_KERNEL
1543 #define TARGET_PROFILE_KERNEL 0
1546 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1547 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1549 /* Initialize the GCC target structure. */
1550 #undef TARGET_ATTRIBUTE_TABLE
1551 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1552 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1553 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1554 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1555 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1557 #undef TARGET_ASM_ALIGNED_DI_OP
1558 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1560 /* Default unaligned ops are only provided for ELF. Find the ops needed
1561 for non-ELF systems. */
1562 #ifndef OBJECT_FORMAT_ELF
1564 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1566 #undef TARGET_ASM_UNALIGNED_HI_OP
1567 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1568 #undef TARGET_ASM_UNALIGNED_SI_OP
1569 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1570 #undef TARGET_ASM_UNALIGNED_DI_OP
1571 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1574 #undef TARGET_ASM_UNALIGNED_HI_OP
1575 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1576 #undef TARGET_ASM_UNALIGNED_SI_OP
1577 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1578 #undef TARGET_ASM_UNALIGNED_DI_OP
1579 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1580 #undef TARGET_ASM_ALIGNED_DI_OP
1581 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1585 /* This hook deals with fixups for relocatable code and DI-mode objects
1587 #undef TARGET_ASM_INTEGER
1588 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1590 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1591 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1592 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1595 #undef TARGET_SET_UP_BY_PROLOGUE
1596 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1598 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1599 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1600 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1601 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1602 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1603 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1604 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1605 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1606 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1607 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1608 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1609 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1611 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1612 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1614 #undef TARGET_INTERNAL_ARG_POINTER
1615 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1617 #undef TARGET_HAVE_TLS
1618 #define TARGET_HAVE_TLS HAVE_AS_TLS
1620 #undef TARGET_CANNOT_FORCE_CONST_MEM
1621 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1623 #undef TARGET_DELEGITIMIZE_ADDRESS
1624 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1626 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1627 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1629 #undef TARGET_LEGITIMATE_COMBINED_INSN
1630 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1632 #undef TARGET_ASM_FUNCTION_PROLOGUE
1633 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1634 #undef TARGET_ASM_FUNCTION_EPILOGUE
1635 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1637 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1638 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1640 #undef TARGET_LEGITIMIZE_ADDRESS
1641 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1643 #undef TARGET_SCHED_VARIABLE_ISSUE
1644 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1646 #undef TARGET_SCHED_ISSUE_RATE
1647 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1648 #undef TARGET_SCHED_ADJUST_COST
1649 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1650 #undef TARGET_SCHED_ADJUST_PRIORITY
1651 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1652 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1653 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1654 #undef TARGET_SCHED_INIT
1655 #define TARGET_SCHED_INIT rs6000_sched_init
1656 #undef TARGET_SCHED_FINISH
1657 #define TARGET_SCHED_FINISH rs6000_sched_finish
1658 #undef TARGET_SCHED_REORDER
1659 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1660 #undef TARGET_SCHED_REORDER2
1661 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1663 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1664 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1666 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1667 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1669 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1670 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1671 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1672 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1673 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1674 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1675 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1676 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1678 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1679 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1681 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1682 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1683 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1684 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1685 rs6000_builtin_support_vector_misalignment
1686 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1687 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1688 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1689 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1690 rs6000_builtin_vectorization_cost
1691 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1692 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1693 rs6000_preferred_simd_mode
1694 #undef TARGET_VECTORIZE_INIT_COST
1695 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1696 #undef TARGET_VECTORIZE_ADD_STMT_COST
1697 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1698 #undef TARGET_VECTORIZE_FINISH_COST
1699 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1700 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1701 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1703 #undef TARGET_INIT_BUILTINS
1704 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1705 #undef TARGET_BUILTIN_DECL
1706 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1708 #undef TARGET_FOLD_BUILTIN
1709 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1710 #undef TARGET_GIMPLE_FOLD_BUILTIN
1711 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1713 #undef TARGET_EXPAND_BUILTIN
1714 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1716 #undef TARGET_MANGLE_TYPE
1717 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1719 #undef TARGET_INIT_LIBFUNCS
1720 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1723 #undef TARGET_BINDS_LOCAL_P
1724 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1727 #undef TARGET_MS_BITFIELD_LAYOUT_P
1728 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1730 #undef TARGET_ASM_OUTPUT_MI_THUNK
1731 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1733 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1734 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1736 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1737 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1739 #undef TARGET_REGISTER_MOVE_COST
1740 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1741 #undef TARGET_MEMORY_MOVE_COST
1742 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1743 #undef TARGET_CANNOT_COPY_INSN_P
1744 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1745 #undef TARGET_RTX_COSTS
1746 #define TARGET_RTX_COSTS rs6000_rtx_costs
1747 #undef TARGET_ADDRESS_COST
1748 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1749 #undef TARGET_INSN_COST
1750 #define TARGET_INSN_COST rs6000_insn_cost
1752 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1753 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1755 #undef TARGET_PROMOTE_FUNCTION_MODE
1756 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1758 #undef TARGET_RETURN_IN_MEMORY
1759 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1761 #undef TARGET_RETURN_IN_MSB
1762 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1764 #undef TARGET_SETUP_INCOMING_VARARGS
1765 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1767 /* Always strict argument naming on rs6000. */
1768 #undef TARGET_STRICT_ARGUMENT_NAMING
1769 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1770 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1771 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1772 #undef TARGET_SPLIT_COMPLEX_ARG
1773 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1774 #undef TARGET_MUST_PASS_IN_STACK
1775 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1776 #undef TARGET_PASS_BY_REFERENCE
1777 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1778 #undef TARGET_ARG_PARTIAL_BYTES
1779 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1780 #undef TARGET_FUNCTION_ARG_ADVANCE
1781 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1782 #undef TARGET_FUNCTION_ARG
1783 #define TARGET_FUNCTION_ARG rs6000_function_arg
1784 #undef TARGET_FUNCTION_ARG_PADDING
1785 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1786 #undef TARGET_FUNCTION_ARG_BOUNDARY
1787 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1789 #undef TARGET_BUILD_BUILTIN_VA_LIST
1790 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1792 #undef TARGET_EXPAND_BUILTIN_VA_START
1793 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1795 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1796 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1798 #undef TARGET_EH_RETURN_FILTER_MODE
1799 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1801 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1802 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1804 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1805 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1807 #undef TARGET_FLOATN_MODE
1808 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1810 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1811 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1813 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1814 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1816 #undef TARGET_MD_ASM_ADJUST
1817 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1819 #undef TARGET_OPTION_OVERRIDE
1820 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1822 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1823 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1824 rs6000_builtin_vectorized_function
1826 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1827 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1828 rs6000_builtin_md_vectorized_function
1830 #undef TARGET_STACK_PROTECT_GUARD
1831 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1834 #undef TARGET_STACK_PROTECT_FAIL
1835 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1839 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1840 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1843 /* Use a 32-bit anchor range. This leads to sequences like:
1845 addis tmp,anchor,high
1848 where tmp itself acts as an anchor, and can be shared between
1849 accesses to the same 64k page. */
1850 #undef TARGET_MIN_ANCHOR_OFFSET
1851 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1852 #undef TARGET_MAX_ANCHOR_OFFSET
1853 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1854 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1855 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1856 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1857 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1859 #undef TARGET_BUILTIN_RECIPROCAL
1860 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1862 #undef TARGET_SECONDARY_RELOAD
1863 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1864 #undef TARGET_SECONDARY_MEMORY_NEEDED
1865 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1866 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1867 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1869 #undef TARGET_LEGITIMATE_ADDRESS_P
1870 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1872 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1873 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1875 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1876 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1878 #undef TARGET_CAN_ELIMINATE
1879 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1881 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1882 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1884 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1885 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1887 #undef TARGET_TRAMPOLINE_INIT
1888 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1890 #undef TARGET_FUNCTION_VALUE
1891 #define TARGET_FUNCTION_VALUE rs6000_function_value
1893 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1894 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1896 #undef TARGET_OPTION_SAVE
1897 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1899 #undef TARGET_OPTION_RESTORE
1900 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1902 #undef TARGET_OPTION_PRINT
1903 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1905 #undef TARGET_CAN_INLINE_P
1906 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1908 #undef TARGET_SET_CURRENT_FUNCTION
1909 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1911 #undef TARGET_LEGITIMATE_CONSTANT_P
1912 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1914 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1915 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1917 #undef TARGET_CAN_USE_DOLOOP_P
1918 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1920 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1921 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1923 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1924 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1925 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1926 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1927 #undef TARGET_UNWIND_WORD_MODE
1928 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1930 #undef TARGET_OFFLOAD_OPTIONS
1931 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1933 #undef TARGET_C_MODE_FOR_SUFFIX
1934 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1936 #undef TARGET_INVALID_BINARY_OP
1937 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1939 #undef TARGET_OPTAB_SUPPORTED_P
1940 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1942 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1943 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1945 #undef TARGET_COMPARE_VERSION_PRIORITY
1946 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1948 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1949 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1950 rs6000_generate_version_dispatcher_body
1952 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1953 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1954 rs6000_get_function_versions_dispatcher
1956 #undef TARGET_OPTION_FUNCTION_VERSIONS
1957 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1959 #undef TARGET_HARD_REGNO_NREGS
1960 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1961 #undef TARGET_HARD_REGNO_MODE_OK
1962 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1964 #undef TARGET_MODES_TIEABLE_P
1965 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1967 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1968 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1969 rs6000_hard_regno_call_part_clobbered
1971 #undef TARGET_SLOW_UNALIGNED_ACCESS
1972 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1974 #undef TARGET_CAN_CHANGE_MODE_CLASS
1975 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1977 #undef TARGET_CONSTANT_ALIGNMENT
1978 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1980 #undef TARGET_STARTING_FRAME_OFFSET
1981 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1984 /* Processor table. */
1987 const char *const name; /* Canonical processor name. */
1988 const enum processor_type processor; /* Processor type enum value. */
1989 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1992 static struct rs6000_ptt const processor_target_table[] =
1994 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1995 #include "rs6000-cpus.def"
1999 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2003 rs6000_cpu_name_lookup (const char *name)
2009 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2010 if (! strcmp (name, processor_target_table[i].name))
2018 /* Return number of consecutive hard regs needed starting at reg REGNO
2019 to hold something of mode MODE.
2020 This is ordinarily the length in words of a value of mode MODE
2021 but can be less for certain modes in special long registers.
2023 POWER and PowerPC GPRs hold 32 bits worth;
2024 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2027 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2029 unsigned HOST_WIDE_INT reg_size;
2031 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2032 128-bit floating point that can go in vector registers, which has VSX
2033 memory addressing. */
2034 if (FP_REGNO_P (regno))
2035 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2036 ? UNITS_PER_VSX_WORD
2037 : UNITS_PER_FP_WORD);
2039 else if (ALTIVEC_REGNO_P (regno))
2040 reg_size = UNITS_PER_ALTIVEC_WORD;
2043 reg_size = UNITS_PER_WORD;
2045 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2048 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2051 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2053 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2055 if (COMPLEX_MODE_P (mode))
2056 mode = GET_MODE_INNER (mode);
2058 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2059 register combinations, and use PTImode where we need to deal with quad
2060 word memory operations. Don't allow quad words in the argument or frame
2061 pointer registers, just registers 0..31. */
2062 if (mode == PTImode)
2063 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2064 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2065 && ((regno & 1) == 0));
2067 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2068 implementations. Don't allow an item to be split between a FP register
2069 and an Altivec register. Allow TImode in all VSX registers if the user
2071 if (TARGET_VSX && VSX_REGNO_P (regno)
2072 && (VECTOR_MEM_VSX_P (mode)
2073 || FLOAT128_VECTOR_P (mode)
2074 || reg_addr[mode].scalar_in_vmx_p
2076 || (TARGET_VADDUQM && mode == V1TImode)))
2078 if (FP_REGNO_P (regno))
2079 return FP_REGNO_P (last_regno);
2081 if (ALTIVEC_REGNO_P (regno))
2083 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2086 return ALTIVEC_REGNO_P (last_regno);
2090 /* The GPRs can hold any mode, but values bigger than one register
2091 cannot go past R31. */
2092 if (INT_REGNO_P (regno))
2093 return INT_REGNO_P (last_regno);
2095 /* The float registers (except for VSX vector modes) can only hold floating
2096 modes and DImode. */
2097 if (FP_REGNO_P (regno))
2099 if (FLOAT128_VECTOR_P (mode))
2102 if (SCALAR_FLOAT_MODE_P (mode)
2103 && (mode != TDmode || (regno % 2) == 0)
2104 && FP_REGNO_P (last_regno))
2107 if (GET_MODE_CLASS (mode) == MODE_INT)
2109 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2112 if (TARGET_P8_VECTOR && (mode == SImode))
2115 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2119 if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
2120 && PAIRED_VECTOR_MODE (mode))
2126 /* The CR register can only hold CC modes. */
2127 if (CR_REGNO_P (regno))
2128 return GET_MODE_CLASS (mode) == MODE_CC;
2130 if (CA_REGNO_P (regno))
2131 return mode == Pmode || mode == SImode;
2133 /* AltiVec only in AldyVec registers. */
2134 if (ALTIVEC_REGNO_P (regno))
2135 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2136 || mode == V1TImode);
2138 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2139 and it must be able to fit within the register set. */
2141 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2144 /* Implement TARGET_HARD_REGNO_NREGS. */
2147 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2149 return rs6000_hard_regno_nregs[mode][regno];
2152 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2155 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2157 return rs6000_hard_regno_mode_ok_p[mode][regno];
2160 /* Implement TARGET_MODES_TIEABLE_P.
2162 PTImode cannot tie with other modes because PTImode is restricted to even
2163 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2166 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2167 128-bit floating point on VSX systems ties with other vectors. */
2170 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2172 if (mode1 == PTImode)
2173 return mode2 == PTImode;
2174 if (mode2 == PTImode)
2177 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2178 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2179 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2182 if (SCALAR_FLOAT_MODE_P (mode1))
2183 return SCALAR_FLOAT_MODE_P (mode2);
2184 if (SCALAR_FLOAT_MODE_P (mode2))
2187 if (GET_MODE_CLASS (mode1) == MODE_CC)
2188 return GET_MODE_CLASS (mode2) == MODE_CC;
2189 if (GET_MODE_CLASS (mode2) == MODE_CC)
2192 if (PAIRED_VECTOR_MODE (mode1))
2193 return PAIRED_VECTOR_MODE (mode2);
2194 if (PAIRED_VECTOR_MODE (mode2))
2200 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2203 rs6000_hard_regno_call_part_clobbered (unsigned int regno, machine_mode mode)
2207 && GET_MODE_SIZE (mode) > 4
2208 && INT_REGNO_P (regno))
2212 && FP_REGNO_P (regno)
2213 && GET_MODE_SIZE (mode) > 8
2214 && !FLOAT128_2REG_P (mode))
2220 /* Print interesting facts about registers. */
2222 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2226 for (r = first_regno; r <= last_regno; ++r)
2228 const char *comma = "";
2231 if (first_regno == last_regno)
2232 fprintf (stderr, "%s:\t", reg_name);
2234 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2237 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2238 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2242 fprintf (stderr, ",\n\t");
2247 if (rs6000_hard_regno_nregs[m][r] > 1)
2248 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2249 rs6000_hard_regno_nregs[m][r]);
2251 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2256 if (call_used_regs[r])
2260 fprintf (stderr, ",\n\t");
2265 len += fprintf (stderr, "%s%s", comma, "call-used");
2273 fprintf (stderr, ",\n\t");
2278 len += fprintf (stderr, "%s%s", comma, "fixed");
2284 fprintf (stderr, ",\n\t");
2288 len += fprintf (stderr, "%sreg-class = %s", comma,
2289 reg_class_names[(int)rs6000_regno_regclass[r]]);
2294 fprintf (stderr, ",\n\t");
2298 fprintf (stderr, "%sregno = %d\n", comma, r);
2303 rs6000_debug_vector_unit (enum rs6000_vector v)
2309 case VECTOR_NONE: ret = "none"; break;
2310 case VECTOR_ALTIVEC: ret = "altivec"; break;
2311 case VECTOR_VSX: ret = "vsx"; break;
2312 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2313 case VECTOR_PAIRED: ret = "paired"; break;
2314 case VECTOR_OTHER: ret = "other"; break;
2315 default: ret = "unknown"; break;
2321 /* Inner function printing just the address mask for a particular reload
2323 DEBUG_FUNCTION char *
2324 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2329 if ((mask & RELOAD_REG_VALID) != 0)
2331 else if (keep_spaces)
2334 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2336 else if (keep_spaces)
2339 if ((mask & RELOAD_REG_INDEXED) != 0)
2341 else if (keep_spaces)
2344 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2346 else if ((mask & RELOAD_REG_OFFSET) != 0)
2348 else if (keep_spaces)
2351 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2353 else if (keep_spaces)
2356 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2358 else if (keep_spaces)
2361 if ((mask & RELOAD_REG_AND_M16) != 0)
2363 else if (keep_spaces)
2371 /* Print the address masks in a human readble fashion. */
2373 rs6000_debug_print_mode (ssize_t m)
2379 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2380 for (rc = 0; rc < N_RELOAD_REG; rc++)
2381 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2382 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2384 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2385 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2386 fprintf (stderr, " Reload=%c%c",
2387 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2388 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2390 spaces += sizeof (" Reload=sl") - 1;
2392 if (reg_addr[m].scalar_in_vmx_p)
2394 fprintf (stderr, "%*s Upper=y", spaces, "");
2398 spaces += sizeof (" Upper=y") - 1;
2400 fuse_extra_p = ((reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2401 || reg_addr[m].fused_toc);
2404 for (rc = 0; rc < N_RELOAD_REG; rc++)
2406 if (rc != RELOAD_REG_ANY)
2408 if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2409 || reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing
2410 || reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing
2411 || reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing
2412 || reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2414 fuse_extra_p = true;
2423 fprintf (stderr, "%*s Fuse:", spaces, "");
2426 for (rc = 0; rc < N_RELOAD_REG; rc++)
2428 if (rc != RELOAD_REG_ANY)
2432 if (reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing)
2434 else if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing)
2439 if (reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
2441 else if (reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing)
2446 if (load == '-' && store == '-')
2450 fprintf (stderr, "%*s%c=%c%c", (spaces + 1), "",
2451 reload_reg_map[rc].name[0], load, store);
2457 if (reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
2459 fprintf (stderr, "%*sP8gpr", (spaces + 1), "");
2463 spaces += sizeof (" P8gpr") - 1;
2465 if (reg_addr[m].fused_toc)
2467 fprintf (stderr, "%*sToc", (spaces + 1), "");
2471 spaces += sizeof (" Toc") - 1;
2474 spaces += sizeof (" Fuse: G=ls F=ls v=ls P8gpr Toc") - 1;
2476 if (rs6000_vector_unit[m] != VECTOR_NONE
2477 || rs6000_vector_mem[m] != VECTOR_NONE)
2479 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2481 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2482 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2485 fputs ("\n", stderr);
2488 #define DEBUG_FMT_ID "%-32s= "
2489 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2490 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2491 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2493 /* Print various interesting information with -mdebug=reg. */
2495 rs6000_debug_reg_global (void)
2497 static const char *const tf[2] = { "false", "true" };
2498 const char *nl = (const char *)0;
2501 char costly_num[20];
2503 char flags_buffer[40];
2504 const char *costly_str;
2505 const char *nop_str;
2506 const char *trace_str;
2507 const char *abi_str;
2508 const char *cmodel_str;
2509 struct cl_target_option cl_opts;
2511 /* Modes we want tieable information on. */
2512 static const machine_mode print_tieable_modes[] = {
2548 /* Virtual regs we are interested in. */
2549 const static struct {
2550 int regno; /* register number. */
2551 const char *name; /* register name. */
2552 } virtual_regs[] = {
2553 { STACK_POINTER_REGNUM, "stack pointer:" },
2554 { TOC_REGNUM, "toc: " },
2555 { STATIC_CHAIN_REGNUM, "static chain: " },
2556 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2557 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2558 { ARG_POINTER_REGNUM, "arg pointer: " },
2559 { FRAME_POINTER_REGNUM, "frame pointer:" },
2560 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2561 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2562 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2563 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2564 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2565 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2566 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2567 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2568 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2571 fputs ("\nHard register information:\n", stderr);
2572 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2573 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2574 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2577 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2578 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2579 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2580 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2581 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2582 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2584 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2585 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2586 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2590 "d reg_class = %s\n"
2591 "f reg_class = %s\n"
2592 "v reg_class = %s\n"
2593 "wa reg_class = %s\n"
2594 "wb reg_class = %s\n"
2595 "wd reg_class = %s\n"
2596 "we reg_class = %s\n"
2597 "wf reg_class = %s\n"
2598 "wg reg_class = %s\n"
2599 "wh reg_class = %s\n"
2600 "wi reg_class = %s\n"
2601 "wj reg_class = %s\n"
2602 "wk reg_class = %s\n"
2603 "wl reg_class = %s\n"
2604 "wm reg_class = %s\n"
2605 "wo reg_class = %s\n"
2606 "wp reg_class = %s\n"
2607 "wq reg_class = %s\n"
2608 "wr reg_class = %s\n"
2609 "ws reg_class = %s\n"
2610 "wt reg_class = %s\n"
2611 "wu reg_class = %s\n"
2612 "wv reg_class = %s\n"
2613 "ww reg_class = %s\n"
2614 "wx reg_class = %s\n"
2615 "wy reg_class = %s\n"
2616 "wz reg_class = %s\n"
2617 "wA reg_class = %s\n"
2618 "wH reg_class = %s\n"
2619 "wI reg_class = %s\n"
2620 "wJ reg_class = %s\n"
2621 "wK reg_class = %s\n"
2623 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2624 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2625 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2626 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2627 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wb]],
2628 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2629 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2630 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2631 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2632 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]],
2633 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2634 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
2635 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
2636 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
2637 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
2638 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wo]],
2639 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2640 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2641 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2642 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2643 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2644 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],
2645 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2646 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2647 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2648 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
2649 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
2650 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
2651 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
2652 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
2653 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
2654 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wK]]);
2657 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2658 rs6000_debug_print_mode (m);
2660 fputs ("\n", stderr);
2662 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2664 machine_mode mode1 = print_tieable_modes[m1];
2665 bool first_time = true;
2667 nl = (const char *)0;
2668 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2670 machine_mode mode2 = print_tieable_modes[m2];
2671 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2675 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2680 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2685 fputs ("\n", stderr);
2691 if (rs6000_recip_control)
2693 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2695 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2696 if (rs6000_recip_bits[m])
2699 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2701 (RS6000_RECIP_AUTO_RE_P (m)
2703 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2704 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2706 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2709 fputs ("\n", stderr);
2712 if (rs6000_cpu_index >= 0)
2714 const char *name = processor_target_table[rs6000_cpu_index].name;
2716 = processor_target_table[rs6000_cpu_index].target_enable;
2718 sprintf (flags_buffer, "-mcpu=%s flags", name);
2719 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2722 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2724 if (rs6000_tune_index >= 0)
2726 const char *name = processor_target_table[rs6000_tune_index].name;
2728 = processor_target_table[rs6000_tune_index].target_enable;
2730 sprintf (flags_buffer, "-mtune=%s flags", name);
2731 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2734 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2736 cl_target_option_save (&cl_opts, &global_options);
2737 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2740 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2741 rs6000_isa_flags_explicit);
2743 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2744 rs6000_builtin_mask);
2746 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2748 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2749 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2751 switch (rs6000_sched_costly_dep)
2753 case max_dep_latency:
2754 costly_str = "max_dep_latency";
2758 costly_str = "no_dep_costly";
2761 case all_deps_costly:
2762 costly_str = "all_deps_costly";
2765 case true_store_to_load_dep_costly:
2766 costly_str = "true_store_to_load_dep_costly";
2769 case store_to_load_dep_costly:
2770 costly_str = "store_to_load_dep_costly";
2774 costly_str = costly_num;
2775 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2779 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2781 switch (rs6000_sched_insert_nops)
2783 case sched_finish_regroup_exact:
2784 nop_str = "sched_finish_regroup_exact";
2787 case sched_finish_pad_groups:
2788 nop_str = "sched_finish_pad_groups";
2791 case sched_finish_none:
2792 nop_str = "sched_finish_none";
2797 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2801 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2803 switch (rs6000_sdata)
2810 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2814 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2818 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2823 switch (rs6000_traceback)
2825 case traceback_default: trace_str = "default"; break;
2826 case traceback_none: trace_str = "none"; break;
2827 case traceback_part: trace_str = "part"; break;
2828 case traceback_full: trace_str = "full"; break;
2829 default: trace_str = "unknown"; break;
2832 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2834 switch (rs6000_current_cmodel)
2836 case CMODEL_SMALL: cmodel_str = "small"; break;
2837 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2838 case CMODEL_LARGE: cmodel_str = "large"; break;
2839 default: cmodel_str = "unknown"; break;
2842 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2844 switch (rs6000_current_abi)
2846 case ABI_NONE: abi_str = "none"; break;
2847 case ABI_AIX: abi_str = "aix"; break;
2848 case ABI_ELFv2: abi_str = "ELFv2"; break;
2849 case ABI_V4: abi_str = "V4"; break;
2850 case ABI_DARWIN: abi_str = "darwin"; break;
2851 default: abi_str = "unknown"; break;
2854 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2856 if (rs6000_altivec_abi)
2857 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2859 if (rs6000_darwin64_abi)
2860 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2862 fprintf (stderr, DEBUG_FMT_S, "single_float",
2863 (TARGET_SINGLE_FLOAT ? "true" : "false"));
2865 fprintf (stderr, DEBUG_FMT_S, "double_float",
2866 (TARGET_DOUBLE_FLOAT ? "true" : "false"));
2868 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2869 (TARGET_SOFT_FLOAT ? "true" : "false"));
2871 if (TARGET_LINK_STACK)
2872 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2874 if (TARGET_P8_FUSION)
2878 strcpy (options, (TARGET_P9_FUSION) ? "power9" : "power8");
2879 if (TARGET_TOC_FUSION)
2880 strcat (options, ", toc");
2882 if (TARGET_P8_FUSION_SIGN)
2883 strcat (options, ", sign");
2885 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2888 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2889 TARGET_SECURE_PLT ? "secure" : "bss");
2890 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2891 aix_struct_return ? "aix" : "sysv");
2892 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2893 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2894 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2895 tf[!!rs6000_align_branch_targets]);
2896 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2897 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2898 rs6000_long_double_type_size);
2899 if (rs6000_long_double_type_size == 128)
2901 fprintf (stderr, DEBUG_FMT_S, "long double type",
2902 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2903 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2904 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2906 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2907 (int)rs6000_sched_restricted_insns_priority);
2908 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2910 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2911 (int)RS6000_BUILTIN_COUNT);
2913 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2914 (int)TARGET_FLOAT128_ENABLE_TYPE);
2917 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2918 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2920 if (TARGET_DIRECT_MOVE_128)
2921 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2922 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2926 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2927 legitimate address support to figure out the appropriate addressing to
2931 rs6000_setup_reg_addr_masks (void)
2933 ssize_t rc, reg, m, nregs;
2934 addr_mask_type any_addr_mask, addr_mask;
2936 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2938 machine_mode m2 = (machine_mode) m;
2939 bool complex_p = false;
2940 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2943 if (COMPLEX_MODE_P (m2))
2946 m2 = GET_MODE_INNER (m2);
2949 msize = GET_MODE_SIZE (m2);
2951 /* SDmode is special in that we want to access it only via REG+REG
2952 addressing on power7 and above, since we want to use the LFIWZX and
2953 STFIWZX instructions to load it. */
2954 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2957 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2960 reg = reload_reg_map[rc].reg;
2962 /* Can mode values go in the GPR/FPR/Altivec registers? */
2963 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2965 bool small_int_vsx_p = (small_int_p
2966 && (rc == RELOAD_REG_FPR
2967 || rc == RELOAD_REG_VMX));
2969 nregs = rs6000_hard_regno_nregs[m][reg];
2970 addr_mask |= RELOAD_REG_VALID;
2972 /* Indicate if the mode takes more than 1 physical register. If
2973 it takes a single register, indicate it can do REG+REG
2974 addressing. Small integers in VSX registers can only do
2975 REG+REG addressing. */
2976 if (small_int_vsx_p)
2977 addr_mask |= RELOAD_REG_INDEXED;
2978 else if (nregs > 1 || m == BLKmode || complex_p)
2979 addr_mask |= RELOAD_REG_MULTIPLE;
2981 addr_mask |= RELOAD_REG_INDEXED;
2983 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2984 addressing. If we allow scalars into Altivec registers,
2985 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2987 For VSX systems, we don't allow update addressing for
2988 DFmode/SFmode if those registers can go in both the
2989 traditional floating point registers and Altivec registers.
2990 The load/store instructions for the Altivec registers do not
2991 have update forms. If we allowed update addressing, it seems
2992 to break IV-OPT code using floating point if the index type is
2993 int instead of long (PR target/81550 and target/84042). */
2996 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2998 && !VECTOR_MODE_P (m2)
2999 && !FLOAT128_VECTOR_P (m2)
3001 && (m != E_DFmode || !TARGET_VSX)
3002 && (m != E_SFmode || !TARGET_P8_VECTOR)
3003 && !small_int_vsx_p)
3005 addr_mask |= RELOAD_REG_PRE_INCDEC;
3007 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
3008 we don't allow PRE_MODIFY for some multi-register
3013 addr_mask |= RELOAD_REG_PRE_MODIFY;
3017 if (TARGET_POWERPC64)
3018 addr_mask |= RELOAD_REG_PRE_MODIFY;
3024 addr_mask |= RELOAD_REG_PRE_MODIFY;
3030 /* GPR and FPR registers can do REG+OFFSET addressing, except
3031 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
3032 for 64-bit scalars and 32-bit SFmode to altivec registers. */
3033 if ((addr_mask != 0) && !indexed_only_p
3035 && (rc == RELOAD_REG_GPR
3036 || ((msize == 8 || m2 == SFmode)
3037 && (rc == RELOAD_REG_FPR
3038 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
3039 addr_mask |= RELOAD_REG_OFFSET;
3041 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
3042 instructions are enabled. The offset for 128-bit VSX registers is
3043 only 12-bits. While GPRs can handle the full offset range, VSX
3044 registers can only handle the restricted range. */
3045 else if ((addr_mask != 0) && !indexed_only_p
3046 && msize == 16 && TARGET_P9_VECTOR
3047 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
3048 || (m2 == TImode && TARGET_VSX)))
3050 addr_mask |= RELOAD_REG_OFFSET;
3051 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
3052 addr_mask |= RELOAD_REG_QUAD_OFFSET;
3055 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
3056 addressing on 128-bit types. */
3057 if (rc == RELOAD_REG_VMX && msize == 16
3058 && (addr_mask & RELOAD_REG_VALID) != 0)
3059 addr_mask |= RELOAD_REG_AND_M16;
3061 reg_addr[m].addr_mask[rc] = addr_mask;
3062 any_addr_mask |= addr_mask;
3065 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
3070 /* Initialize the various global tables that are based on register size. */
3072 rs6000_init_hard_regno_mode_ok (bool global_init_p)
3078 /* Precalculate REGNO_REG_CLASS. */
3079 rs6000_regno_regclass[0] = GENERAL_REGS;
3080 for (r = 1; r < 32; ++r)
3081 rs6000_regno_regclass[r] = BASE_REGS;
3083 for (r = 32; r < 64; ++r)
3084 rs6000_regno_regclass[r] = FLOAT_REGS;
3086 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
3087 rs6000_regno_regclass[r] = NO_REGS;
3089 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
3090 rs6000_regno_regclass[r] = ALTIVEC_REGS;
3092 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
3093 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
3094 rs6000_regno_regclass[r] = CR_REGS;
3096 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
3097 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
3098 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
3099 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
3100 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
3101 rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
3102 rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
3103 rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
3104 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
3105 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
3107 /* Precalculate register class to simpler reload register class. We don't
3108 need all of the register classes that are combinations of different
3109 classes, just the simple ones that have constraint letters. */
3110 for (c = 0; c < N_REG_CLASSES; c++)
3111 reg_class_to_reg_type[c] = NO_REG_TYPE;
3113 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
3114 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
3115 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
3116 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
3117 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
3118 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
3119 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
3120 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
3121 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
3122 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
3126 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
3127 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
3131 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
3132 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3135 /* Precalculate the valid memory formats as well as the vector information,
3136 this must be set up before the rs6000_hard_regno_nregs_internal calls
3138 gcc_assert ((int)VECTOR_NONE == 0);
3139 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3140 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit));
3142 gcc_assert ((int)CODE_FOR_nothing == 0);
3143 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3145 gcc_assert ((int)NO_REGS == 0);
3146 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3148 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3149 believes it can use native alignment or still uses 128-bit alignment. */
3150 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3161 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3162 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3163 if (TARGET_FLOAT128_TYPE)
3165 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3166 rs6000_vector_align[KFmode] = 128;
3168 if (FLOAT128_IEEE_P (TFmode))
3170 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3171 rs6000_vector_align[TFmode] = 128;
3175 /* V2DF mode, VSX only. */
3178 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3179 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3180 rs6000_vector_align[V2DFmode] = align64;
3183 /* V4SF mode, either VSX or Altivec. */
3186 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3187 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3188 rs6000_vector_align[V4SFmode] = align32;
3190 else if (TARGET_ALTIVEC)
3192 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3193 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3194 rs6000_vector_align[V4SFmode] = align32;
3197 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3201 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3202 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3203 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3204 rs6000_vector_align[V4SImode] = align32;
3205 rs6000_vector_align[V8HImode] = align32;
3206 rs6000_vector_align[V16QImode] = align32;
3210 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3211 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3212 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3216 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3217 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3218 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3222 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3223 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3226 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3227 rs6000_vector_unit[V2DImode]
3228 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3229 rs6000_vector_align[V2DImode] = align64;
3231 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3232 rs6000_vector_unit[V1TImode]
3233 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3234 rs6000_vector_align[V1TImode] = 128;
3237 /* DFmode, see if we want to use the VSX unit. Memory is handled
3238 differently, so don't set rs6000_vector_mem. */
3241 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3242 rs6000_vector_align[DFmode] = 64;
3245 /* SFmode, see if we want to use the VSX unit. */
3246 if (TARGET_P8_VECTOR)
3248 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3249 rs6000_vector_align[SFmode] = 32;
3252 /* Allow TImode in VSX register and set the VSX memory macros. */
3255 rs6000_vector_mem[TImode] = VECTOR_VSX;
3256 rs6000_vector_align[TImode] = align64;
3259 /* TODO add paired floating point vector support. */
3261 /* Register class constraints for the constraints that depend on compile
3262 switches. When the VSX code was added, different constraints were added
3263 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3264 of the VSX registers are used. The register classes for scalar floating
3265 point types is set, based on whether we allow that type into the upper
3266 (Altivec) registers. GCC has register classes to target the Altivec
3267 registers for load/store operations, to select using a VSX memory
3268 operation instead of the traditional floating point operation. The
3271 d - Register class to use with traditional DFmode instructions.
3272 f - Register class to use with traditional SFmode instructions.
3273 v - Altivec register.
3274 wa - Any VSX register.
3275 wc - Reserved to represent individual CR bits (used in LLVM).
3276 wd - Preferred register class for V2DFmode.
3277 wf - Preferred register class for V4SFmode.
3278 wg - Float register for power6x move insns.
3279 wh - FP register for direct move instructions.
3280 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3281 wj - FP or VSX register to hold 64-bit integers for direct moves.
3282 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3283 wl - Float register if we can do 32-bit signed int loads.
3284 wm - VSX register for ISA 2.07 direct move operations.
3285 wn - always NO_REGS.
3286 wr - GPR if 64-bit mode is permitted.
3287 ws - Register class to do ISA 2.06 DF operations.
3288 wt - VSX register for TImode in VSX registers.
3289 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3290 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3291 ww - Register class to do SF conversions in with VSX operations.
3292 wx - Float register if we can do 32-bit int stores.
3293 wy - Register class to do ISA 2.07 SF operations.
3294 wz - Float register if we can do 32-bit unsigned int loads.
3295 wH - Altivec register if SImode is allowed in VSX registers.
3296 wI - VSX register if SImode is allowed in VSX registers.
3297 wJ - VSX register if QImode/HImode are allowed in VSX registers.
3298 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3300 if (TARGET_HARD_FLOAT)
3301 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3303 if (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
3304 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3308 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3309 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3310 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3311 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
3312 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
3313 rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
3314 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
3317 /* Add conditional constraints based on various options, to allow us to
3318 collapse multiple insn patterns. */
3320 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3322 if (TARGET_MFPGPR) /* DFmode */
3323 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
3326 rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
3328 if (TARGET_DIRECT_MOVE)
3330 rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS;
3331 rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */
3332 = rs6000_constraints[RS6000_CONSTRAINT_wi];
3333 rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
3334 = rs6000_constraints[RS6000_CONSTRAINT_ws];
3335 rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
3338 if (TARGET_POWERPC64)
3340 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3341 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3344 if (TARGET_P8_VECTOR) /* SFmode */
3346 rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
3347 rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
3348 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3350 else if (TARGET_VSX)
3351 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3354 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3357 rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */
3359 if (TARGET_FLOAT128_TYPE)
3361 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3362 if (FLOAT128_IEEE_P (TFmode))
3363 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3366 if (TARGET_P9_VECTOR)
3368 /* Support for new D-form instructions. */
3369 rs6000_constraints[RS6000_CONSTRAINT_wb] = ALTIVEC_REGS;
3371 /* Support for ISA 3.0 (power9) vectors. */
3372 rs6000_constraints[RS6000_CONSTRAINT_wo] = VSX_REGS;
3375 /* Support for new direct moves (ISA 3.0 + 64bit). */
3376 if (TARGET_DIRECT_MOVE_128)
3377 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3379 /* Support small integers in VSX registers. */
3380 if (TARGET_P8_VECTOR)
3382 rs6000_constraints[RS6000_CONSTRAINT_wH] = ALTIVEC_REGS;
3383 rs6000_constraints[RS6000_CONSTRAINT_wI] = FLOAT_REGS;
3384 if (TARGET_P9_VECTOR)
3386 rs6000_constraints[RS6000_CONSTRAINT_wJ] = FLOAT_REGS;
3387 rs6000_constraints[RS6000_CONSTRAINT_wK] = ALTIVEC_REGS;
3391 /* Set up the reload helper and direct move functions. */
3392 if (TARGET_VSX || TARGET_ALTIVEC)
3396 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3397 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3398 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3399 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3400 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3401 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3402 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3403 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3404 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3405 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3406 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3407 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3408 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3409 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3410 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3411 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3412 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3413 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3414 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3415 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3417 if (FLOAT128_VECTOR_P (KFmode))
3419 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3420 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3423 if (FLOAT128_VECTOR_P (TFmode))
3425 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3426 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3429 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3431 if (TARGET_NO_SDMODE_STACK)
3433 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3434 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3439 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3440 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3443 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3445 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3446 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3447 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3448 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3449 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3450 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3451 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3452 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3453 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3455 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3456 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3457 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3458 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3459 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3460 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3461 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3462 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3463 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3465 if (FLOAT128_VECTOR_P (KFmode))
3467 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3468 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3471 if (FLOAT128_VECTOR_P (TFmode))
3473 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3474 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3480 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3481 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3482 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3483 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3484 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3485 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3486 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3487 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3488 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3489 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3490 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3491 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3492 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3493 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3494 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3495 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3496 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3497 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3498 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3499 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3501 if (FLOAT128_VECTOR_P (KFmode))
3503 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3504 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3507 if (FLOAT128_IEEE_P (TFmode))
3509 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3510 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3513 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3515 if (TARGET_NO_SDMODE_STACK)
3517 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3518 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3523 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3524 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3527 if (TARGET_DIRECT_MOVE)
3529 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3530 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3531 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3535 reg_addr[DFmode].scalar_in_vmx_p = true;
3536 reg_addr[DImode].scalar_in_vmx_p = true;
3538 if (TARGET_P8_VECTOR)
3540 reg_addr[SFmode].scalar_in_vmx_p = true;
3541 reg_addr[SImode].scalar_in_vmx_p = true;
3543 if (TARGET_P9_VECTOR)
3545 reg_addr[HImode].scalar_in_vmx_p = true;
3546 reg_addr[QImode].scalar_in_vmx_p = true;
3551 /* Setup the fusion operations. */
3552 if (TARGET_P8_FUSION)
3554 reg_addr[QImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_qi;
3555 reg_addr[HImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_hi;
3556 reg_addr[SImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_si;
3558 reg_addr[DImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_di;
3561 if (TARGET_P9_FUSION)
3564 enum machine_mode mode; /* mode of the fused type. */
3565 enum machine_mode pmode; /* pointer mode. */
3566 enum rs6000_reload_reg_type rtype; /* register type. */
3567 enum insn_code load; /* load insn. */
3568 enum insn_code store; /* store insn. */
3571 static const struct fuse_insns addis_insns[] = {
3572 { E_SFmode, E_DImode, RELOAD_REG_FPR,
3573 CODE_FOR_fusion_vsx_di_sf_load,
3574 CODE_FOR_fusion_vsx_di_sf_store },
3576 { E_SFmode, E_SImode, RELOAD_REG_FPR,
3577 CODE_FOR_fusion_vsx_si_sf_load,
3578 CODE_FOR_fusion_vsx_si_sf_store },
3580 { E_DFmode, E_DImode, RELOAD_REG_FPR,
3581 CODE_FOR_fusion_vsx_di_df_load,
3582 CODE_FOR_fusion_vsx_di_df_store },
3584 { E_DFmode, E_SImode, RELOAD_REG_FPR,
3585 CODE_FOR_fusion_vsx_si_df_load,
3586 CODE_FOR_fusion_vsx_si_df_store },
3588 { E_DImode, E_DImode, RELOAD_REG_FPR,
3589 CODE_FOR_fusion_vsx_di_di_load,
3590 CODE_FOR_fusion_vsx_di_di_store },
3592 { E_DImode, E_SImode, RELOAD_REG_FPR,
3593 CODE_FOR_fusion_vsx_si_di_load,
3594 CODE_FOR_fusion_vsx_si_di_store },
3596 { E_QImode, E_DImode, RELOAD_REG_GPR,
3597 CODE_FOR_fusion_gpr_di_qi_load,
3598 CODE_FOR_fusion_gpr_di_qi_store },
3600 { E_QImode, E_SImode, RELOAD_REG_GPR,
3601 CODE_FOR_fusion_gpr_si_qi_load,
3602 CODE_FOR_fusion_gpr_si_qi_store },
3604 { E_HImode, E_DImode, RELOAD_REG_GPR,
3605 CODE_FOR_fusion_gpr_di_hi_load,
3606 CODE_FOR_fusion_gpr_di_hi_store },
3608 { E_HImode, E_SImode, RELOAD_REG_GPR,
3609 CODE_FOR_fusion_gpr_si_hi_load,
3610 CODE_FOR_fusion_gpr_si_hi_store },
3612 { E_SImode, E_DImode, RELOAD_REG_GPR,
3613 CODE_FOR_fusion_gpr_di_si_load,
3614 CODE_FOR_fusion_gpr_di_si_store },
3616 { E_SImode, E_SImode, RELOAD_REG_GPR,
3617 CODE_FOR_fusion_gpr_si_si_load,
3618 CODE_FOR_fusion_gpr_si_si_store },
3620 { E_SFmode, E_DImode, RELOAD_REG_GPR,
3621 CODE_FOR_fusion_gpr_di_sf_load,
3622 CODE_FOR_fusion_gpr_di_sf_store },
3624 { E_SFmode, E_SImode, RELOAD_REG_GPR,
3625 CODE_FOR_fusion_gpr_si_sf_load,
3626 CODE_FOR_fusion_gpr_si_sf_store },
3628 { E_DImode, E_DImode, RELOAD_REG_GPR,
3629 CODE_FOR_fusion_gpr_di_di_load,
3630 CODE_FOR_fusion_gpr_di_di_store },
3632 { E_DFmode, E_DImode, RELOAD_REG_GPR,
3633 CODE_FOR_fusion_gpr_di_df_load,
3634 CODE_FOR_fusion_gpr_di_df_store },
3637 machine_mode cur_pmode = Pmode;
3640 for (i = 0; i < ARRAY_SIZE (addis_insns); i++)
3642 machine_mode xmode = addis_insns[i].mode;
3643 enum rs6000_reload_reg_type rtype = addis_insns[i].rtype;
3645 if (addis_insns[i].pmode != cur_pmode)
3648 if (rtype == RELOAD_REG_FPR && !TARGET_HARD_FLOAT)
3651 reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load;
3652 reg_addr[xmode].fusion_addis_st[rtype] = addis_insns[i].store;
3654 if (rtype == RELOAD_REG_FPR && TARGET_P9_VECTOR)
3656 reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX]
3657 = addis_insns[i].load;
3658 reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX]
3659 = addis_insns[i].store;
3664 /* Note which types we support fusing TOC setup plus memory insn. We only do
3665 fused TOCs for medium/large code models. */
3666 if (TARGET_P8_FUSION && TARGET_TOC_FUSION && TARGET_POWERPC64
3667 && (TARGET_CMODEL != CMODEL_SMALL))
3669 reg_addr[QImode].fused_toc = true;
3670 reg_addr[HImode].fused_toc = true;
3671 reg_addr[SImode].fused_toc = true;
3672 reg_addr[DImode].fused_toc = true;
3673 if (TARGET_HARD_FLOAT)
3675 if (TARGET_SINGLE_FLOAT)
3676 reg_addr[SFmode].fused_toc = true;
3677 if (TARGET_DOUBLE_FLOAT)
3678 reg_addr[DFmode].fused_toc = true;
3682 /* Precalculate HARD_REGNO_NREGS. */
3683 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3684 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3685 rs6000_hard_regno_nregs[m][r]
3686 = rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
3688 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3689 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
3690 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3691 if (rs6000_hard_regno_mode_ok_uncached (r, (machine_mode)m))
3692 rs6000_hard_regno_mode_ok_p[m][r] = true;
3694 /* Precalculate CLASS_MAX_NREGS sizes. */
3695 for (c = 0; c < LIM_REG_CLASSES; ++c)
3699 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3700 reg_size = UNITS_PER_VSX_WORD;
3702 else if (c == ALTIVEC_REGS)
3703 reg_size = UNITS_PER_ALTIVEC_WORD;
3705 else if (c == FLOAT_REGS)
3706 reg_size = UNITS_PER_FP_WORD;
3709 reg_size = UNITS_PER_WORD;
3711 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3713 machine_mode m2 = (machine_mode)m;
3714 int reg_size2 = reg_size;
3716 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3718 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3719 reg_size2 = UNITS_PER_FP_WORD;
3721 rs6000_class_max_nregs[m][c]
3722 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3726 /* Calculate which modes to automatically generate code to use a the
3727 reciprocal divide and square root instructions. In the future, possibly
3728 automatically generate the instructions even if the user did not specify
3729 -mrecip. The older machines double precision reciprocal sqrt estimate is
3730 not accurate enough. */
3731 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3733 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3735 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3736 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3737 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3738 if (VECTOR_UNIT_VSX_P (V2DFmode))
3739 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3741 if (TARGET_FRSQRTES)
3742 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3744 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3745 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3746 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3747 if (VECTOR_UNIT_VSX_P (V2DFmode))
3748 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3750 if (rs6000_recip_control)
3752 if (!flag_finite_math_only)
3753 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3755 if (flag_trapping_math)
3756 warning (0, "%qs requires %qs or %qs", "-mrecip",
3757 "-fno-trapping-math", "-ffast-math");
3758 if (!flag_reciprocal_math)
3759 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3761 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3763 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3764 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3765 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3767 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3768 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3769 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3771 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3772 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3773 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3775 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3776 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3777 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3779 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3780 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3781 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3783 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3784 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3785 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3787 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3788 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3789 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3791 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3792 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3793 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3797 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3798 legitimate address support to figure out the appropriate addressing to
3800 rs6000_setup_reg_addr_masks ();
3802 if (global_init_p || TARGET_DEBUG_TARGET)
3804 if (TARGET_DEBUG_REG)
3805 rs6000_debug_reg_global ();
3807 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3809 "SImode variable mult cost = %d\n"
3810 "SImode constant mult cost = %d\n"
3811 "SImode short constant mult cost = %d\n"
3812 "DImode multipliciation cost = %d\n"
3813 "SImode division cost = %d\n"
3814 "DImode division cost = %d\n"
3815 "Simple fp operation cost = %d\n"
3816 "DFmode multiplication cost = %d\n"
3817 "SFmode division cost = %d\n"
3818 "DFmode division cost = %d\n"
3819 "cache line size = %d\n"
3820 "l1 cache size = %d\n"
3821 "l2 cache size = %d\n"
3822 "simultaneous prefetches = %d\n"
3825 rs6000_cost->mulsi_const,
3826 rs6000_cost->mulsi_const9,
3834 rs6000_cost->cache_line_size,
3835 rs6000_cost->l1_cache_size,
3836 rs6000_cost->l2_cache_size,
3837 rs6000_cost->simultaneous_prefetches);
3842 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3845 darwin_rs6000_override_options (void)
3847 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3849 rs6000_altivec_abi = 1;
3850 TARGET_ALTIVEC_VRSAVE = 1;
3851 rs6000_current_abi = ABI_DARWIN;
3853 if (DEFAULT_ABI == ABI_DARWIN
3855 darwin_one_byte_bool = 1;
3857 if (TARGET_64BIT && ! TARGET_POWERPC64)
3859 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3860 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3864 rs6000_default_long_calls = 1;
3865 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3868 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3870 if (!flag_mkernel && !flag_apple_kext
3872 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3873 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3875 /* Unless the user (not the configurer) has explicitly overridden
3876 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3877 G4 unless targeting the kernel. */
3880 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3881 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3882 && ! global_options_set.x_rs6000_cpu_index)
3884 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3889 /* If not otherwise specified by a target, make 'long double' equivalent to
3892 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3893 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3896 /* Return the builtin mask of the various options used that could affect which
3897 builtins were used. In the past we used target_flags, but we've run out of
3898 bits, and some options like PAIRED are no longer in target_flags. */
3901 rs6000_builtin_mask_calculate (void)
3903 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3904 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3905 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3906 | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
3907 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3908 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3909 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3910 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3911 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3912 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3913 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3914 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3915 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3916 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3917 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3918 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3919 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3920 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3921 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3922 | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0)
3923 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3924 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3927 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3928 to clobber the XER[CA] bit because clobbering that bit without telling
3929 the compiler worked just fine with versions of GCC before GCC 5, and
3930 breaking a lot of older code in ways that are hard to track down is
3931 not such a great idea. */
3934 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3935 vec<const char *> &/*constraints*/,
3936 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3938 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3939 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3943 /* Override command line options.
3945 Combine build-specific configuration information with options
3946 specified on the command line to set various state variables which
3947 influence code generation, optimization, and expansion of built-in
3948 functions. Assure that command-line configuration preferences are
3949 compatible with each other and with the build configuration; issue
3950 warnings while adjusting configuration or error messages while
3951 rejecting configuration.
3953 Upon entry to this function:
3955 This function is called once at the beginning of
3956 compilation, and then again at the start and end of compiling
3957 each section of code that has a different configuration, as
3958 indicated, for example, by adding the
3960 __attribute__((__target__("cpu=power9")))
3962 qualifier to a function definition or, for example, by bracketing
3965 #pragma GCC target("altivec")
3969 #pragma GCC reset_options
3971 directives. Parameter global_init_p is true for the initial
3972 invocation, which initializes global variables, and false for all
3973 subsequent invocations.
3976 Various global state information is assumed to be valid. This
3977 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3978 default CPU specified at build configure time, TARGET_DEFAULT,
3979 representing the default set of option flags for the default
3980 target, and global_options_set.x_rs6000_isa_flags, representing
3981 which options were requested on the command line.
3983 Upon return from this function:
3985 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3986 was set by name on the command line. Additionally, if certain
3987 attributes are automatically enabled or disabled by this function
3988 in order to assure compatibility between options and
3989 configuration, the flags associated with those attributes are
3990 also set. By setting these "explicit bits", we avoid the risk
3991 that other code might accidentally overwrite these particular
3992 attributes with "default values".
3994 The various bits of rs6000_isa_flags are set to indicate the
3995 target options that have been selected for the most current
3996 compilation efforts. This has the effect of also turning on the
3997 associated TARGET_XXX values since these are macros which are
3998 generally defined to test the corresponding bit of the
3999 rs6000_isa_flags variable.
4001 The variable rs6000_builtin_mask is set to represent the target
4002 options for the most current compilation efforts, consistent with
4003 the current contents of rs6000_isa_flags. This variable controls
4004 expansion of built-in functions.
4006 Various other global variables and fields of global structures
4007 (over 50 in all) are initialized to reflect the desired options
4008 for the most current compilation efforts. */
4011 rs6000_option_override_internal (bool global_init_p)
4015 HOST_WIDE_INT set_masks;
4016 HOST_WIDE_INT ignore_masks;
4019 struct cl_target_option *main_target_opt
4020 = ((global_init_p || target_option_default_node == NULL)
4021 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
4023 /* Print defaults. */
4024 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
4025 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
4027 /* Remember the explicit arguments. */
4029 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
4031 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
4032 library functions, so warn about it. The flag may be useful for
4033 performance studies from time to time though, so don't disable it
4035 if (global_options_set.x_rs6000_alignment_flags
4036 && rs6000_alignment_flags == MASK_ALIGN_POWER
4037 && DEFAULT_ABI == ABI_DARWIN
4039 warning (0, "%qs is not supported for 64-bit Darwin;"
4040 " it is incompatible with the installed C and C++ libraries",
4043 /* Numerous experiment shows that IRA based loop pressure
4044 calculation works better for RTL loop invariant motion on targets
4045 with enough (>= 32) registers. It is an expensive optimization.
4046 So it is on only for peak performance. */
4047 if (optimize >= 3 && global_init_p
4048 && !global_options_set.x_flag_ira_loop_pressure)
4049 flag_ira_loop_pressure = 1;
4051 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
4052 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
4053 options were already specified. */
4054 if (flag_sanitize & SANITIZE_USER_ADDRESS
4055 && !global_options_set.x_flag_asynchronous_unwind_tables)
4056 flag_asynchronous_unwind_tables = 1;
4058 /* Set the pointer size. */
4061 rs6000_pmode = DImode;
4062 rs6000_pointer_size = 64;
4066 rs6000_pmode = SImode;
4067 rs6000_pointer_size = 32;
4070 /* Some OSs don't support saving the high part of 64-bit registers on context
4071 switch. Other OSs don't support saving Altivec registers. On those OSs,
4072 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
4073 if the user wants either, the user must explicitly specify them and we
4074 won't interfere with the user's specification. */
4076 set_masks = POWERPC_MASKS;
4077 #ifdef OS_MISSING_POWERPC64
4078 if (OS_MISSING_POWERPC64)
4079 set_masks &= ~OPTION_MASK_POWERPC64;
4081 #ifdef OS_MISSING_ALTIVEC
4082 if (OS_MISSING_ALTIVEC)
4083 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
4084 | OTHER_VSX_VECTOR_MASKS);
4087 /* Don't override by the processor default if given explicitly. */
4088 set_masks &= ~rs6000_isa_flags_explicit;
4090 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
4091 the cpu in a target attribute or pragma, but did not specify a tuning
4092 option, use the cpu for the tuning option rather than the option specified
4093 with -mtune on the command line. Process a '--with-cpu' configuration
4094 request as an implicit --cpu. */
4095 if (rs6000_cpu_index >= 0)
4096 cpu_index = rs6000_cpu_index;
4097 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
4098 cpu_index = main_target_opt->x_rs6000_cpu_index;
4099 else if (OPTION_TARGET_CPU_DEFAULT)
4100 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
4104 const char *unavailable_cpu = NULL;
4105 switch (processor_target_table[cpu_index].processor)
4107 #ifndef HAVE_AS_POWER9
4108 case PROCESSOR_POWER9:
4109 unavailable_cpu = "power9";
4112 #ifndef HAVE_AS_POWER8
4113 case PROCESSOR_POWER8:
4114 unavailable_cpu = "power8";
4117 #ifndef HAVE_AS_POPCNTD
4118 case PROCESSOR_POWER7:
4119 unavailable_cpu = "power7";
4123 case PROCESSOR_POWER6:
4124 unavailable_cpu = "power6";
4127 #ifndef HAVE_AS_POPCNTB
4128 case PROCESSOR_POWER5:
4129 unavailable_cpu = "power5";
4135 if (unavailable_cpu)
4138 warning (0, "will not generate %qs instructions because "
4139 "assembler lacks %qs support", unavailable_cpu,
4144 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
4145 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
4146 with those from the cpu, except for options that were explicitly set. If
4147 we don't have a cpu, do not override the target bits set in
4151 rs6000_cpu_index = cpu_index;
4152 rs6000_isa_flags &= ~set_masks;
4153 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
4158 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
4159 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
4160 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
4161 to using rs6000_isa_flags, we need to do the initialization here.
4163 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
4164 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
4165 HOST_WIDE_INT flags;
4167 flags = TARGET_DEFAULT;
4170 /* PowerPC 64-bit LE requires at least ISA 2.07. */
4171 const char *default_cpu = (!TARGET_POWERPC64
4176 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
4177 flags = processor_target_table[default_cpu_index].target_enable;
4179 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
4182 if (rs6000_tune_index >= 0)
4183 tune_index = rs6000_tune_index;
4184 else if (cpu_index >= 0)
4185 rs6000_tune_index = tune_index = cpu_index;
4189 enum processor_type tune_proc
4190 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
4193 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
4194 if (processor_target_table[i].processor == tune_proc)
4202 rs6000_cpu = processor_target_table[cpu_index].processor;
4204 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
4206 gcc_assert (tune_index >= 0);
4207 rs6000_tune = processor_target_table[tune_index].processor;
4209 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
4210 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
4211 || rs6000_cpu == PROCESSOR_PPCE5500)
4214 error ("AltiVec not supported in this target");
4217 /* If we are optimizing big endian systems for space, use the load/store
4218 multiple instructions. */
4219 if (BYTES_BIG_ENDIAN && optimize_size)
4220 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE;
4222 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
4223 because the hardware doesn't support the instructions used in little
4224 endian mode, and causes an alignment trap. The 750 does not cause an
4225 alignment trap (except when the target is unaligned). */
4227 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750 && TARGET_MULTIPLE)
4229 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
4230 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
4231 warning (0, "%qs is not supported on little endian systems",
4235 /* If little-endian, default to -mstrict-align on older processors.
4236 Testing for htm matches power8 and later. */
4237 if (!BYTES_BIG_ENDIAN
4238 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
4239 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
4241 /* -maltivec={le,be} implies -maltivec. */
4242 if (rs6000_altivec_element_order != 0)
4243 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
4245 /* Disallow -maltivec=le in big endian mode for now. This is not
4246 known to be useful for anyone. */
4247 if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1)
4249 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
4250 rs6000_altivec_element_order = 0;
4253 if (!rs6000_fold_gimple)
4255 "gimple folding of rs6000 builtins has been disabled.\n");
4257 /* Add some warnings for VSX. */
4260 const char *msg = NULL;
4261 if (!TARGET_HARD_FLOAT || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
4263 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4264 msg = N_("-mvsx requires hardware floating point");
4267 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4268 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4271 else if (TARGET_PAIRED_FLOAT)
4272 msg = N_("-mvsx and -mpaired are incompatible");
4273 else if (TARGET_AVOID_XFORM > 0)
4274 msg = N_("-mvsx needs indexed addressing");
4275 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
4276 & OPTION_MASK_ALTIVEC))
4278 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4279 msg = N_("-mvsx and -mno-altivec are incompatible");
4281 msg = N_("-mno-altivec disables vsx");
4287 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
4288 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4292 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4293 the -mcpu setting to enable options that conflict. */
4294 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
4295 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
4296 | OPTION_MASK_ALTIVEC
4297 | OPTION_MASK_VSX)) != 0)
4298 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
4299 | OPTION_MASK_DIRECT_MOVE)
4300 & ~rs6000_isa_flags_explicit);
4302 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4303 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
4305 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
4306 off all of the options that depend on those flags. */
4307 ignore_masks = rs6000_disable_incompatible_switches ();
4309 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4310 unless the user explicitly used the -mno-<option> to disable the code. */
4311 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
4312 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4313 else if (TARGET_P9_MINMAX)
4317 if (cpu_index == PROCESSOR_POWER9)
4319 /* legacy behavior: allow -mcpu=power9 with certain
4320 capabilities explicitly disabled. */
4321 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
4324 error ("power9 target option is incompatible with %<%s=<xxx>%> "
4325 "for <xxx> less than power9", "-mcpu");
4327 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
4328 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
4329 & rs6000_isa_flags_explicit))
4330 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
4331 were explicitly cleared. */
4332 error ("%qs incompatible with explicitly disabled options",
4335 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
4337 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
4338 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
4339 else if (TARGET_VSX)
4340 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
4341 else if (TARGET_POPCNTD)
4342 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
4343 else if (TARGET_DFP)
4344 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
4345 else if (TARGET_CMPB)
4346 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
4347 else if (TARGET_FPRND)
4348 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
4349 else if (TARGET_POPCNTB)
4350 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
4351 else if (TARGET_ALTIVEC)
4352 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
4354 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
4356 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
4357 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4358 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
4361 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
4363 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
4364 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4365 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
4368 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
4370 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4371 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4372 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4375 if (TARGET_P8_VECTOR && !TARGET_VSX)
4377 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4378 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
4379 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4380 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4382 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4383 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4384 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4388 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4390 rs6000_isa_flags |= OPTION_MASK_VSX;
4391 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4395 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4397 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4398 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4399 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4402 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4403 silently turn off quad memory mode. */
4404 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4406 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4407 warning (0, N_("-mquad-memory requires 64-bit mode"));
4409 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4410 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
4412 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4413 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4416 /* Non-atomic quad memory load/store are disabled for little endian, since
4417 the words are reversed, but atomic operations can still be done by
4418 swapping the words. */
4419 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4421 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4422 warning (0, N_("-mquad-memory is not available in little endian "
4425 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4428 /* Assume if the user asked for normal quad memory instructions, they want
4429 the atomic versions as well, unless they explicity told us not to use quad
4430 word atomic instructions. */
4431 if (TARGET_QUAD_MEMORY
4432 && !TARGET_QUAD_MEMORY_ATOMIC
4433 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4434 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4436 /* If we can shrink-wrap the TOC register save separately, then use
4437 -msave-toc-indirect unless explicitly disabled. */
4438 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4439 && flag_shrink_wrap_separate
4440 && optimize_function_for_speed_p (cfun))
4441 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4443 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4444 generating power8 instructions. */
4445 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4446 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4447 & OPTION_MASK_P8_FUSION);
4449 /* Setting additional fusion flags turns on base fusion. */
4450 if (!TARGET_P8_FUSION && (TARGET_P8_FUSION_SIGN || TARGET_TOC_FUSION))
4452 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4454 if (TARGET_P8_FUSION_SIGN)
4455 error ("%qs requires %qs", "-mpower8-fusion-sign",
4458 if (TARGET_TOC_FUSION)
4459 error ("%qs requires %qs", "-mtoc-fusion", "-mpower8-fusion");
4461 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4464 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4467 /* Power9 fusion is a superset over power8 fusion. */
4468 if (TARGET_P9_FUSION && !TARGET_P8_FUSION)
4470 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4472 /* We prefer to not mention undocumented options in
4473 error messages. However, if users have managed to select
4474 power9-fusion without selecting power8-fusion, they
4475 already know about undocumented flags. */
4476 error ("%qs requires %qs", "-mpower9-fusion", "-mpower8-fusion");
4477 rs6000_isa_flags &= ~OPTION_MASK_P9_FUSION;
4480 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4483 /* Enable power9 fusion if we are tuning for power9, even if we aren't
4484 generating power9 instructions. */
4485 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P9_FUSION))
4486 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
4487 & OPTION_MASK_P9_FUSION);
4489 /* Power8 does not fuse sign extended loads with the addis. If we are
4490 optimizing at high levels for speed, convert a sign extended load into a
4491 zero extending load, and an explicit sign extension. */
4492 if (TARGET_P8_FUSION
4493 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4494 && optimize_function_for_speed_p (cfun)
4496 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4498 /* TOC fusion requires 64-bit and medium/large code model. */
4499 if (TARGET_TOC_FUSION && !TARGET_POWERPC64)
4501 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4502 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4503 warning (0, N_("-mtoc-fusion requires 64-bit"));
4506 if (TARGET_TOC_FUSION && (TARGET_CMODEL == CMODEL_SMALL))
4508 rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
4509 if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
4510 warning (0, N_("-mtoc-fusion requires medium/large code model"));
4513 /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
4515 if (TARGET_P8_FUSION && !TARGET_TOC_FUSION && TARGET_POWERPC64
4516 && (TARGET_CMODEL != CMODEL_SMALL)
4517 && !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION))
4518 rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
4520 /* ISA 3.0 vector instructions include ISA 2.07. */
4521 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4523 /* We prefer to not mention undocumented options in
4524 error messages. However, if users have managed to select
4525 power9-vector without selecting power8-vector, they
4526 already know about undocumented flags. */
4527 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4528 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4529 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4530 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4532 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4533 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4534 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4538 /* OPTION_MASK_P9_VECTOR is explicit and
4539 OPTION_MASK_P8_VECTOR is not explicit. */
4540 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4541 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4545 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4546 support. If we only have ISA 2.06 support, and the user did not specify
4547 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4548 but we don't enable the full vectorization support */
4549 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4550 TARGET_ALLOW_MOVMISALIGN = 1;
4552 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4554 if (TARGET_ALLOW_MOVMISALIGN > 0
4555 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4556 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4558 TARGET_ALLOW_MOVMISALIGN = 0;
4561 /* Determine when unaligned vector accesses are permitted, and when
4562 they are preferred over masked Altivec loads. Note that if
4563 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4564 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4566 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4570 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4571 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4573 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4576 else if (!TARGET_ALLOW_MOVMISALIGN)
4578 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4579 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4580 "-mallow-movmisalign");
4582 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4586 /* Set long double size before the IEEE 128-bit tests. */
4587 if (!global_options_set.x_rs6000_long_double_type_size)
4589 if (main_target_opt != NULL
4590 && (main_target_opt->x_rs6000_long_double_type_size
4591 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
4592 error ("target attribute or pragma changes long double size");
4594 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
4597 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4598 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4599 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4600 those systems will not pick up this default. Warn if the user changes the
4601 default unless either the user used the -Wno-psabi option, or the compiler
4602 was built to enable multilibs to switch between the two long double
4604 if (!global_options_set.x_rs6000_ieeequad)
4605 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4607 else if (!TARGET_IEEEQUAD_MULTILIB
4608 && rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT
4609 && TARGET_LONG_DOUBLE_128)
4611 static bool warned_change_long_double;
4612 if (!warned_change_long_double)
4614 warned_change_long_double = true;
4615 if (TARGET_IEEEQUAD)
4616 warning (OPT_Wpsabi, "Using IEEE extended precision long double");
4618 warning (OPT_Wpsabi, "Using IBM extended precision long double");
4622 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4623 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4624 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4625 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4626 the keyword as well as the type. */
4627 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4629 /* IEEE 128-bit floating point requires VSX support. */
4630 if (TARGET_FLOAT128_KEYWORD)
4634 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4635 error ("%qs requires VSX support", "-mfloat128");
4637 TARGET_FLOAT128_TYPE = 0;
4638 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4639 | OPTION_MASK_FLOAT128_HW);
4641 else if (!TARGET_FLOAT128_TYPE)
4643 TARGET_FLOAT128_TYPE = 1;
4644 warning (0, "The -mfloat128 option may not be fully supported");
4648 /* Enable the __float128 keyword under Linux by default. */
4649 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4650 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4651 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4653 /* If we have are supporting the float128 type and full ISA 3.0 support,
4654 enable -mfloat128-hardware by default. However, don't enable the
4655 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4656 because sometimes the compiler wants to put things in an integer
4657 container, and if we don't have __int128 support, it is impossible. */
4658 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4659 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4660 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4661 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4663 if (TARGET_FLOAT128_HW
4664 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4666 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4667 error ("%qs requires full ISA 3.0 support", "-mfloat128-hardware");
4669 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4672 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4674 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4675 error ("%qs requires %qs", "-mfloat128-hardware", "-m64");
4677 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4680 /* Print the options after updating the defaults. */
4681 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4682 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4684 /* E500mc does "better" if we inline more aggressively. Respect the
4685 user's opinion, though. */
4686 if (rs6000_block_move_inline_limit == 0
4687 && (rs6000_tune == PROCESSOR_PPCE500MC
4688 || rs6000_tune == PROCESSOR_PPCE500MC64
4689 || rs6000_tune == PROCESSOR_PPCE5500
4690 || rs6000_tune == PROCESSOR_PPCE6500))
4691 rs6000_block_move_inline_limit = 128;
4693 /* store_one_arg depends on expand_block_move to handle at least the
4694 size of reg_parm_stack_space. */
4695 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4696 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4700 /* If the appropriate debug option is enabled, replace the target hooks
4701 with debug versions that call the real version and then prints
4702 debugging information. */
4703 if (TARGET_DEBUG_COST)
4705 targetm.rtx_costs = rs6000_debug_rtx_costs;
4706 targetm.address_cost = rs6000_debug_address_cost;
4707 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4710 if (TARGET_DEBUG_ADDR)
4712 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4713 targetm.legitimize_address = rs6000_debug_legitimize_address;
4714 rs6000_secondary_reload_class_ptr
4715 = rs6000_debug_secondary_reload_class;
4716 targetm.secondary_memory_needed
4717 = rs6000_debug_secondary_memory_needed;
4718 targetm.can_change_mode_class
4719 = rs6000_debug_can_change_mode_class;
4720 rs6000_preferred_reload_class_ptr
4721 = rs6000_debug_preferred_reload_class;
4722 rs6000_legitimize_reload_address_ptr
4723 = rs6000_debug_legitimize_reload_address;
4724 rs6000_mode_dependent_address_ptr
4725 = rs6000_debug_mode_dependent_address;
4728 if (rs6000_veclibabi_name)
4730 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4731 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4734 error ("unknown vectorization library ABI type (%qs) for "
4735 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4741 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4742 target attribute or pragma which automatically enables both options,
4743 unless the altivec ABI was set. This is set by default for 64-bit, but
4745 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4747 TARGET_FLOAT128_TYPE = 0;
4748 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4749 | OPTION_MASK_FLOAT128_KEYWORD)
4750 & ~rs6000_isa_flags_explicit);
4753 /* Enable Altivec ABI for AIX -maltivec. */
4754 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4756 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4757 error ("target attribute or pragma changes AltiVec ABI");
4759 rs6000_altivec_abi = 1;
4762 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4763 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4764 be explicitly overridden in either case. */
4767 if (!global_options_set.x_rs6000_altivec_abi
4768 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4770 if (main_target_opt != NULL &&
4771 !main_target_opt->x_rs6000_altivec_abi)
4772 error ("target attribute or pragma changes AltiVec ABI");
4774 rs6000_altivec_abi = 1;
4778 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4779 So far, the only darwin64 targets are also MACH-O. */
4781 && DEFAULT_ABI == ABI_DARWIN
4784 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4785 error ("target attribute or pragma changes darwin64 ABI");
4788 rs6000_darwin64_abi = 1;
4789 /* Default to natural alignment, for better performance. */
4790 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4794 /* Place FP constants in the constant pool instead of TOC
4795 if section anchors enabled. */
4796 if (flag_section_anchors
4797 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4798 TARGET_NO_FP_IN_TOC = 1;
4800 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4801 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4803 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4804 SUBTARGET_OVERRIDE_OPTIONS;
4806 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4807 SUBSUBTARGET_OVERRIDE_OPTIONS;
4809 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4810 SUB3TARGET_OVERRIDE_OPTIONS;
4813 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4814 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4816 /* For the E500 family of cores, reset the single/double FP flags to let us
4817 check that they remain constant across attributes or pragmas. */
4821 case PROCESSOR_PPC8540:
4822 case PROCESSOR_PPC8548:
4823 case PROCESSOR_PPCE500MC:
4824 case PROCESSOR_PPCE500MC64:
4825 case PROCESSOR_PPCE5500:
4826 case PROCESSOR_PPCE6500:
4827 rs6000_single_float = 0;
4828 rs6000_double_float = 0;
4835 if (main_target_opt)
4837 if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
4838 error ("target attribute or pragma changes single precision floating "
4840 if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
4841 error ("target attribute or pragma changes double precision floating "
4845 rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
4846 && rs6000_tune != PROCESSOR_POWER5
4847 && rs6000_tune != PROCESSOR_POWER6
4848 && rs6000_tune != PROCESSOR_POWER7
4849 && rs6000_tune != PROCESSOR_POWER8
4850 && rs6000_tune != PROCESSOR_POWER9
4851 && rs6000_tune != PROCESSOR_PPCA2
4852 && rs6000_tune != PROCESSOR_CELL
4853 && rs6000_tune != PROCESSOR_PPC476);
4854 rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
4855 || rs6000_tune == PROCESSOR_POWER5
4856 || rs6000_tune == PROCESSOR_POWER7
4857 || rs6000_tune == PROCESSOR_POWER8);
4858 rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
4859 || rs6000_tune == PROCESSOR_POWER5
4860 || rs6000_tune == PROCESSOR_POWER6
4861 || rs6000_tune == PROCESSOR_POWER7
4862 || rs6000_tune == PROCESSOR_POWER8
4863 || rs6000_tune == PROCESSOR_POWER9
4864 || rs6000_tune == PROCESSOR_PPCE500MC
4865 || rs6000_tune == PROCESSOR_PPCE500MC64
4866 || rs6000_tune == PROCESSOR_PPCE5500
4867 || rs6000_tune == PROCESSOR_PPCE6500);
4869 /* Allow debug switches to override the above settings. These are set to -1
4870 in rs6000.opt to indicate the user hasn't directly set the switch. */
4871 if (TARGET_ALWAYS_HINT >= 0)
4872 rs6000_always_hint = TARGET_ALWAYS_HINT;
4874 if (TARGET_SCHED_GROUPS >= 0)
4875 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4877 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4878 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4880 rs6000_sched_restricted_insns_priority
4881 = (rs6000_sched_groups ? 1 : 0);
4883 /* Handle -msched-costly-dep option. */
4884 rs6000_sched_costly_dep
4885 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4887 if (rs6000_sched_costly_dep_str)
4889 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4890 rs6000_sched_costly_dep = no_dep_costly;
4891 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4892 rs6000_sched_costly_dep = all_deps_costly;
4893 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4894 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4895 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4896 rs6000_sched_costly_dep = store_to_load_dep_costly;
4898 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4899 atoi (rs6000_sched_costly_dep_str));
4902 /* Handle -minsert-sched-nops option. */
4903 rs6000_sched_insert_nops
4904 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4906 if (rs6000_sched_insert_nops_str)
4908 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4909 rs6000_sched_insert_nops = sched_finish_none;
4910 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4911 rs6000_sched_insert_nops = sched_finish_pad_groups;
4912 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4913 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4915 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4916 atoi (rs6000_sched_insert_nops_str));
4919 /* Handle stack protector */
4920 if (!global_options_set.x_rs6000_stack_protector_guard)
4921 #ifdef TARGET_THREAD_SSP_OFFSET
4922 rs6000_stack_protector_guard = SSP_TLS;
4924 rs6000_stack_protector_guard = SSP_GLOBAL;
4927 #ifdef TARGET_THREAD_SSP_OFFSET
4928 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4929 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4932 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4935 const char *str = rs6000_stack_protector_guard_offset_str;
4938 long offset = strtol (str, &endp, 0);
4939 if (!*str || *endp || errno)
4940 error ("%qs is not a valid number in %qs", str,
4941 "-mstack-protector-guard-offset=");
4943 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4944 || (TARGET_64BIT && (offset & 3)))
4945 error ("%qs is not a valid offset in %qs", str,
4946 "-mstack-protector-guard-offset=");
4948 rs6000_stack_protector_guard_offset = offset;
4951 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4953 const char *str = rs6000_stack_protector_guard_reg_str;
4954 int reg = decode_reg_name (str);
4956 if (!IN_RANGE (reg, 1, 31))
4957 error ("%qs is not a valid base register in %qs", str,
4958 "-mstack-protector-guard-reg=");
4960 rs6000_stack_protector_guard_reg = reg;
4963 if (rs6000_stack_protector_guard == SSP_TLS
4964 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4965 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4969 #ifdef TARGET_REGNAMES
4970 /* If the user desires alternate register names, copy in the
4971 alternate names now. */
4972 if (TARGET_REGNAMES)
4973 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4976 /* Set aix_struct_return last, after the ABI is determined.
4977 If -maix-struct-return or -msvr4-struct-return was explicitly
4978 used, don't override with the ABI default. */
4979 if (!global_options_set.x_aix_struct_return)
4980 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4983 /* IBM XL compiler defaults to unsigned bitfields. */
4984 if (TARGET_XL_COMPAT)
4985 flag_signed_bitfields = 0;
4988 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4989 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4991 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4993 /* We can only guarantee the availability of DI pseudo-ops when
4994 assembling for 64-bit targets. */
4997 targetm.asm_out.aligned_op.di = NULL;
4998 targetm.asm_out.unaligned_op.di = NULL;
5002 /* Set branch target alignment, if not optimizing for size. */
5005 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
5006 aligned 8byte to avoid misprediction by the branch predictor. */
5007 if (rs6000_tune == PROCESSOR_TITAN
5008 || rs6000_tune == PROCESSOR_CELL)
5010 if (align_functions <= 0)
5011 align_functions = 8;
5012 if (align_jumps <= 0)
5014 if (align_loops <= 0)
5017 if (rs6000_align_branch_targets)
5019 if (align_functions <= 0)
5020 align_functions = 16;
5021 if (align_jumps <= 0)
5023 if (align_loops <= 0)
5025 can_override_loop_align = 1;
5029 if (align_jumps_max_skip <= 0)
5030 align_jumps_max_skip = 15;
5031 if (align_loops_max_skip <= 0)
5032 align_loops_max_skip = 15;
5035 /* Arrange to save and restore machine status around nested functions. */
5036 init_machine_status = rs6000_init_machine_status;
5038 /* We should always be splitting complex arguments, but we can't break
5039 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
5040 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
5041 targetm.calls.split_complex_arg = NULL;
5043 /* The AIX and ELFv1 ABIs define standard function descriptors. */
5044 if (DEFAULT_ABI == ABI_AIX)
5045 targetm.calls.custom_function_descriptors = 0;
5048 /* Initialize rs6000_cost with the appropriate target costs. */
5050 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
5052 switch (rs6000_tune)
5054 case PROCESSOR_RS64A:
5055 rs6000_cost = &rs64a_cost;
5058 case PROCESSOR_MPCCORE:
5059 rs6000_cost = &mpccore_cost;
5062 case PROCESSOR_PPC403:
5063 rs6000_cost = &ppc403_cost;
5066 case PROCESSOR_PPC405:
5067 rs6000_cost = &ppc405_cost;
5070 case PROCESSOR_PPC440:
5071 rs6000_cost = &ppc440_cost;
5074 case PROCESSOR_PPC476:
5075 rs6000_cost = &ppc476_cost;
5078 case PROCESSOR_PPC601:
5079 rs6000_cost = &ppc601_cost;
5082 case PROCESSOR_PPC603:
5083 rs6000_cost = &ppc603_cost;
5086 case PROCESSOR_PPC604:
5087 rs6000_cost = &ppc604_cost;
5090 case PROCESSOR_PPC604e:
5091 rs6000_cost = &ppc604e_cost;
5094 case PROCESSOR_PPC620:
5095 rs6000_cost = &ppc620_cost;
5098 case PROCESSOR_PPC630:
5099 rs6000_cost = &ppc630_cost;
5102 case PROCESSOR_CELL:
5103 rs6000_cost = &ppccell_cost;
5106 case PROCESSOR_PPC750:
5107 case PROCESSOR_PPC7400:
5108 rs6000_cost = &ppc750_cost;
5111 case PROCESSOR_PPC7450:
5112 rs6000_cost = &ppc7450_cost;
5115 case PROCESSOR_PPC8540:
5116 case PROCESSOR_PPC8548:
5117 rs6000_cost = &ppc8540_cost;
5120 case PROCESSOR_PPCE300C2:
5121 case PROCESSOR_PPCE300C3:
5122 rs6000_cost = &ppce300c2c3_cost;
5125 case PROCESSOR_PPCE500MC:
5126 rs6000_cost = &ppce500mc_cost;
5129 case PROCESSOR_PPCE500MC64:
5130 rs6000_cost = &ppce500mc64_cost;
5133 case PROCESSOR_PPCE5500:
5134 rs6000_cost = &ppce5500_cost;
5137 case PROCESSOR_PPCE6500:
5138 rs6000_cost = &ppce6500_cost;
5141 case PROCESSOR_TITAN:
5142 rs6000_cost = &titan_cost;
5145 case PROCESSOR_POWER4:
5146 case PROCESSOR_POWER5:
5147 rs6000_cost = &power4_cost;
5150 case PROCESSOR_POWER6:
5151 rs6000_cost = &power6_cost;
5154 case PROCESSOR_POWER7:
5155 rs6000_cost = &power7_cost;
5158 case PROCESSOR_POWER8:
5159 rs6000_cost = &power8_cost;
5162 case PROCESSOR_POWER9:
5163 rs6000_cost = &power9_cost;
5166 case PROCESSOR_PPCA2:
5167 rs6000_cost = &ppca2_cost;
5176 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
5177 rs6000_cost->simultaneous_prefetches,
5178 global_options.x_param_values,
5179 global_options_set.x_param_values);
5180 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
5181 global_options.x_param_values,
5182 global_options_set.x_param_values);
5183 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
5184 rs6000_cost->cache_line_size,
5185 global_options.x_param_values,
5186 global_options_set.x_param_values);
5187 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
5188 global_options.x_param_values,
5189 global_options_set.x_param_values);
5191 /* Increase loop peeling limits based on performance analysis. */
5192 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
5193 global_options.x_param_values,
5194 global_options_set.x_param_values);
5195 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
5196 global_options.x_param_values,
5197 global_options_set.x_param_values);
5199 /* Use the 'model' -fsched-pressure algorithm by default. */
5200 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
5201 SCHED_PRESSURE_MODEL,
5202 global_options.x_param_values,
5203 global_options_set.x_param_values);
5205 /* If using typedef char *va_list, signal that
5206 __builtin_va_start (&ap, 0) can be optimized to
5207 ap = __builtin_next_arg (0). */
5208 if (DEFAULT_ABI != ABI_V4)
5209 targetm.expand_builtin_va_start = NULL;
5212 /* Set up single/double float flags.
5213 If TARGET_HARD_FLOAT is set, but neither single or double is set,
5214 then set both flags. */
5215 if (TARGET_HARD_FLOAT && rs6000_single_float == 0 && rs6000_double_float == 0)
5216 rs6000_single_float = rs6000_double_float = 1;
5218 /* If not explicitly specified via option, decide whether to generate indexed
5219 load/store instructions. A value of -1 indicates that the
5220 initial value of this variable has not been overwritten. During
5221 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
5222 if (TARGET_AVOID_XFORM == -1)
5223 /* Avoid indexed addressing when targeting Power6 in order to avoid the
5224 DERAT mispredict penalty. However the LVE and STVE altivec instructions
5225 need indexed accesses and the type used is the scalar type of the element
5226 being loaded or stored. */
5227 TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
5228 && !TARGET_ALTIVEC);
5230 /* Set the -mrecip options. */
5231 if (rs6000_recip_name)
5233 char *p = ASTRDUP (rs6000_recip_name);
5235 unsigned int mask, i;
5238 while ((q = strtok (p, ",")) != NULL)
5249 if (!strcmp (q, "default"))
5250 mask = ((TARGET_RECIP_PRECISION)
5251 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
5254 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
5255 if (!strcmp (q, recip_options[i].string))
5257 mask = recip_options[i].mask;
5261 if (i == ARRAY_SIZE (recip_options))
5263 error ("unknown option for %<%s=%s%>", "-mrecip", q);
5271 rs6000_recip_control &= ~mask;
5273 rs6000_recip_control |= mask;
5277 /* Set the builtin mask of the various options used that could affect which
5278 builtins were used. In the past we used target_flags, but we've run out
5279 of bits, and some options like PAIRED are no longer in target_flags. */
5280 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
5281 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
5282 rs6000_print_builtin_options (stderr, 0, "builtin mask",
5283 rs6000_builtin_mask);
5285 /* Initialize all of the registers. */
5286 rs6000_init_hard_regno_mode_ok (global_init_p);
5288 /* Save the initial options in case the user does function specific options */
5290 target_option_default_node = target_option_current_node
5291 = build_target_option_node (&global_options);
5293 /* If not explicitly specified via option, decide whether to generate the
5294 extra blr's required to preserve the link stack on some cpus (eg, 476). */
5295 if (TARGET_LINK_STACK == -1)
5296 SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
5298 /* Deprecate use of -mno-speculate-indirect-jumps. */
5299 if (!rs6000_speculate_indirect_jumps)
5300 warning (0, "%qs is deprecated and not recommended in any circumstances",
5301 "-mno-speculate-indirect-jumps");
5306 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
5307 define the target cpu type. */
5310 rs6000_option_override (void)
5312 (void) rs6000_option_override_internal (true);
5316 /* Implement targetm.vectorize.builtin_mask_for_load. */
5318 rs6000_builtin_mask_for_load (void)
5320 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
5321 if ((TARGET_ALTIVEC && !TARGET_VSX)
5322 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
5323 return altivec_builtin_mask_for_load;
5328 /* Implement LOOP_ALIGN. */
5330 rs6000_loop_align (rtx label)
5335 /* Don't override loop alignment if -falign-loops was specified. */
5336 if (!can_override_loop_align)
5337 return align_loops_log;
5339 bb = BLOCK_FOR_INSN (label);
5340 ninsns = num_loop_insns(bb->loop_father);
5342 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
5343 if (ninsns > 4 && ninsns <= 8
5344 && (rs6000_tune == PROCESSOR_POWER4
5345 || rs6000_tune == PROCESSOR_POWER5
5346 || rs6000_tune == PROCESSOR_POWER6
5347 || rs6000_tune == PROCESSOR_POWER7
5348 || rs6000_tune == PROCESSOR_POWER8
5349 || rs6000_tune == PROCESSOR_POWER9))
5352 return align_loops_log;
5355 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
5357 rs6000_loop_align_max_skip (rtx_insn *label)
5359 return (1 << rs6000_loop_align (label)) - 1;
5362 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5363 after applying N number of iterations. This routine does not determine
5364 how may iterations are required to reach desired alignment. */
5367 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
5374 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
5377 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
5387 /* Assuming that all other types are naturally aligned. CHECKME! */
5392 /* Return true if the vector misalignment factor is supported by the
5395 rs6000_builtin_support_vector_misalignment (machine_mode mode,
5402 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5405 /* Return if movmisalign pattern is not supported for this mode. */
5406 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
5409 if (misalignment == -1)
5411 /* Misalignment factor is unknown at compile time but we know
5412 it's word aligned. */
5413 if (rs6000_vector_alignment_reachable (type, is_packed))
5415 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
5417 if (element_size == 64 || element_size == 32)
5424 /* VSX supports word-aligned vector. */
5425 if (misalignment % 4 == 0)
5431 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5433 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5434 tree vectype, int misalign)
5439 switch (type_of_cost)
5449 case cond_branch_not_taken:
5458 case vec_promote_demote:
5464 case cond_branch_taken:
5467 case unaligned_load:
5468 case vector_gather_load:
5469 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5472 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5474 elements = TYPE_VECTOR_SUBPARTS (vectype);
5476 /* Double word aligned. */
5484 /* Double word aligned. */
5488 /* Unknown misalignment. */
5501 /* Misaligned loads are not supported. */
5506 case unaligned_store:
5507 case vector_scatter_store:
5508 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5511 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5513 elements = TYPE_VECTOR_SUBPARTS (vectype);
5515 /* Double word aligned. */
5523 /* Double word aligned. */
5527 /* Unknown misalignment. */
5540 /* Misaligned stores are not supported. */
5546 /* This is a rough approximation assuming non-constant elements
5547 constructed into a vector via element insertion. FIXME:
5548 vec_construct is not granular enough for uniformly good
5549 decisions. If the initialization is a splat, this is
5550 cheaper than we estimate. Improve this someday. */
5551 elem_type = TREE_TYPE (vectype);
5552 /* 32-bit vectors loaded into registers are stored as double
5553 precision, so we need 2 permutes, 2 converts, and 1 merge
5554 to construct a vector of short floats from them. */
5555 if (SCALAR_FLOAT_TYPE_P (elem_type)
5556 && TYPE_PRECISION (elem_type) == 32)
5558 /* On POWER9, integer vector types are built up in GPRs and then
5559 use a direct move (2 cycles). For POWER8 this is even worse,
5560 as we need two direct moves and a merge, and the direct moves
5562 else if (INTEGRAL_TYPE_P (elem_type))
5564 if (TARGET_P9_VECTOR)
5565 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5567 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5570 /* V2DFmode doesn't need a direct move. */
5578 /* Implement targetm.vectorize.preferred_simd_mode. */
5581 rs6000_preferred_simd_mode (scalar_mode mode)
5590 if (TARGET_ALTIVEC || TARGET_VSX)
5607 if (TARGET_PAIRED_FLOAT
5613 typedef struct _rs6000_cost_data
5615 struct loop *loop_info;
5619 /* Test for likely overcommitment of vector hardware resources. If a
5620 loop iteration is relatively large, and too large a percentage of
5621 instructions in the loop are vectorized, the cost model may not
5622 adequately reflect delays from unavailable vector resources.
5623 Penalize the loop body cost for this case. */
5626 rs6000_density_test (rs6000_cost_data *data)
5628 const int DENSITY_PCT_THRESHOLD = 85;
5629 const int DENSITY_SIZE_THRESHOLD = 70;
5630 const int DENSITY_PENALTY = 10;
5631 struct loop *loop = data->loop_info;
5632 basic_block *bbs = get_loop_body (loop);
5633 int nbbs = loop->num_nodes;
5634 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5637 for (i = 0; i < nbbs; i++)
5639 basic_block bb = bbs[i];
5640 gimple_stmt_iterator gsi;
5642 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5644 gimple *stmt = gsi_stmt (gsi);
5645 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
5647 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5648 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5654 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5656 if (density_pct > DENSITY_PCT_THRESHOLD
5657 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5659 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5660 if (dump_enabled_p ())
5661 dump_printf_loc (MSG_NOTE, vect_location,
5662 "density %d%%, cost %d exceeds threshold, penalizing "
5663 "loop body cost by %d%%", density_pct,
5664 vec_cost + not_vec_cost, DENSITY_PENALTY);
5668 /* Implement targetm.vectorize.init_cost. */
5670 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5671 instruction is needed by the vectorization. */
5672 static bool rs6000_vect_nonmem;
5675 rs6000_init_cost (struct loop *loop_info)
5677 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5678 data->loop_info = loop_info;
5679 data->cost[vect_prologue] = 0;
5680 data->cost[vect_body] = 0;
5681 data->cost[vect_epilogue] = 0;
5682 rs6000_vect_nonmem = false;
5686 /* Implement targetm.vectorize.add_stmt_cost. */
5689 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5690 struct _stmt_vec_info *stmt_info, int misalign,
5691 enum vect_cost_model_location where)
5693 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5694 unsigned retval = 0;
5696 if (flag_vect_cost_model)
5698 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5699 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5701 /* Statements in an inner loop relative to the loop being
5702 vectorized are weighted more heavily. The value here is
5703 arbitrary and could potentially be improved with analysis. */
5704 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5705 count *= 50; /* FIXME. */
5707 retval = (unsigned) (count * stmt_cost);
5708 cost_data->cost[where] += retval;
5710 /* Check whether we're doing something other than just a copy loop.
5711 Not all such loops may be profitably vectorized; see
5712 rs6000_finish_cost. */
5713 if ((kind == vec_to_scalar || kind == vec_perm
5714 || kind == vec_promote_demote || kind == vec_construct
5715 || kind == scalar_to_vec)
5716 || (where == vect_body && kind == vector_stmt))
5717 rs6000_vect_nonmem = true;
5723 /* Implement targetm.vectorize.finish_cost. */
5726 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5727 unsigned *body_cost, unsigned *epilogue_cost)
5729 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5731 if (cost_data->loop_info)
5732 rs6000_density_test (cost_data);
5734 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5735 that require versioning for any reason. The vectorization is at
5736 best a wash inside the loop, and the versioning checks make
5737 profitability highly unlikely and potentially quite harmful. */
5738 if (cost_data->loop_info)
5740 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5741 if (!rs6000_vect_nonmem
5742 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5743 && LOOP_REQUIRES_VERSIONING (vec_info))
5744 cost_data->cost[vect_body] += 10000;
5747 *prologue_cost = cost_data->cost[vect_prologue];
5748 *body_cost = cost_data->cost[vect_body];
5749 *epilogue_cost = cost_data->cost[vect_epilogue];
5752 /* Implement targetm.vectorize.destroy_cost_data. */
5755 rs6000_destroy_cost_data (void *data)
5760 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5761 library with vectorized intrinsics. */
5764 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5768 const char *suffix = NULL;
5769 tree fntype, new_fndecl, bdecl = NULL_TREE;
5772 machine_mode el_mode, in_mode;
5775 /* Libmass is suitable for unsafe math only as it does not correctly support
5776 parts of IEEE with the required precision such as denormals. Only support
5777 it if we have VSX to use the simd d2 or f4 functions.
5778 XXX: Add variable length support. */
5779 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5782 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5783 n = TYPE_VECTOR_SUBPARTS (type_out);
5784 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5785 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5786 if (el_mode != in_mode
5822 if (el_mode == DFmode && n == 2)
5824 bdecl = mathfn_built_in (double_type_node, fn);
5825 suffix = "d2"; /* pow -> powd2 */
5827 else if (el_mode == SFmode && n == 4)
5829 bdecl = mathfn_built_in (float_type_node, fn);
5830 suffix = "4"; /* powf -> powf4 */
5842 gcc_assert (suffix != NULL);
5843 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5847 strcpy (name, bname + sizeof ("__builtin_") - 1);
5848 strcat (name, suffix);
5851 fntype = build_function_type_list (type_out, type_in, NULL);
5852 else if (n_args == 2)
5853 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5857 /* Build a function declaration for the vectorized function. */
5858 new_fndecl = build_decl (BUILTINS_LOCATION,
5859 FUNCTION_DECL, get_identifier (name), fntype);
5860 TREE_PUBLIC (new_fndecl) = 1;
5861 DECL_EXTERNAL (new_fndecl) = 1;
5862 DECL_IS_NOVOPS (new_fndecl) = 1;
5863 TREE_READONLY (new_fndecl) = 1;
5868 /* Returns a function decl for a vectorized version of the builtin function
5869 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5870 if it is not available. */
5873 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5876 machine_mode in_mode, out_mode;
5879 if (TARGET_DEBUG_BUILTIN)
5880 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5881 combined_fn_name (combined_fn (fn)),
5882 GET_MODE_NAME (TYPE_MODE (type_out)),
5883 GET_MODE_NAME (TYPE_MODE (type_in)));
5885 if (TREE_CODE (type_out) != VECTOR_TYPE
5886 || TREE_CODE (type_in) != VECTOR_TYPE)
5889 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5890 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5891 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5892 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5897 if (VECTOR_UNIT_VSX_P (V2DFmode)
5898 && out_mode == DFmode && out_n == 2
5899 && in_mode == DFmode && in_n == 2)
5900 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5901 if (VECTOR_UNIT_VSX_P (V4SFmode)
5902 && out_mode == SFmode && out_n == 4
5903 && in_mode == SFmode && in_n == 4)
5904 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5905 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5906 && out_mode == SFmode && out_n == 4
5907 && in_mode == SFmode && in_n == 4)
5908 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5911 if (VECTOR_UNIT_VSX_P (V2DFmode)
5912 && out_mode == DFmode && out_n == 2
5913 && in_mode == DFmode && in_n == 2)
5914 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5915 if (VECTOR_UNIT_VSX_P (V4SFmode)
5916 && out_mode == SFmode && out_n == 4
5917 && in_mode == SFmode && in_n == 4)
5918 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5919 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5920 && out_mode == SFmode && out_n == 4
5921 && in_mode == SFmode && in_n == 4)
5922 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5925 if (VECTOR_UNIT_VSX_P (V2DFmode)
5926 && out_mode == DFmode && out_n == 2
5927 && in_mode == DFmode && in_n == 2)
5928 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5929 if (VECTOR_UNIT_VSX_P (V4SFmode)
5930 && out_mode == SFmode && out_n == 4
5931 && in_mode == SFmode && in_n == 4)
5932 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5933 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5934 && out_mode == SFmode && out_n == 4
5935 && in_mode == SFmode && in_n == 4)
5936 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5939 if (VECTOR_UNIT_VSX_P (V2DFmode)
5940 && out_mode == DFmode && out_n == 2
5941 && in_mode == DFmode && in_n == 2)
5942 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5943 if (VECTOR_UNIT_VSX_P (V4SFmode)
5944 && out_mode == SFmode && out_n == 4
5945 && in_mode == SFmode && in_n == 4)
5946 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5947 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5948 && out_mode == SFmode && out_n == 4
5949 && in_mode == SFmode && in_n == 4)
5950 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5953 if (VECTOR_UNIT_VSX_P (V2DFmode)
5954 && out_mode == DFmode && out_n == 2
5955 && in_mode == DFmode && in_n == 2)
5956 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5957 if (VECTOR_UNIT_VSX_P (V4SFmode)
5958 && out_mode == SFmode && out_n == 4
5959 && in_mode == SFmode && in_n == 4)
5960 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5961 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5962 && out_mode == SFmode && out_n == 4
5963 && in_mode == SFmode && in_n == 4)
5964 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5967 if (VECTOR_UNIT_VSX_P (V2DFmode)
5968 && flag_unsafe_math_optimizations
5969 && out_mode == DFmode && out_n == 2
5970 && in_mode == DFmode && in_n == 2)
5971 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5972 if (VECTOR_UNIT_VSX_P (V4SFmode)
5973 && flag_unsafe_math_optimizations
5974 && out_mode == SFmode && out_n == 4
5975 && in_mode == SFmode && in_n == 4)
5976 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5979 if (VECTOR_UNIT_VSX_P (V2DFmode)
5980 && !flag_trapping_math
5981 && out_mode == DFmode && out_n == 2
5982 && in_mode == DFmode && in_n == 2)
5983 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5984 if (VECTOR_UNIT_VSX_P (V4SFmode)
5985 && !flag_trapping_math
5986 && out_mode == SFmode && out_n == 4
5987 && in_mode == SFmode && in_n == 4)
5988 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5994 /* Generate calls to libmass if appropriate. */
5995 if (rs6000_veclib_handler)
5996 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
6001 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
6004 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
6007 machine_mode in_mode, out_mode;
6010 if (TARGET_DEBUG_BUILTIN)
6011 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
6012 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
6013 GET_MODE_NAME (TYPE_MODE (type_out)),
6014 GET_MODE_NAME (TYPE_MODE (type_in)));
6016 if (TREE_CODE (type_out) != VECTOR_TYPE
6017 || TREE_CODE (type_in) != VECTOR_TYPE)
6020 out_mode = TYPE_MODE (TREE_TYPE (type_out));
6021 out_n = TYPE_VECTOR_SUBPARTS (type_out);
6022 in_mode = TYPE_MODE (TREE_TYPE (type_in));
6023 in_n = TYPE_VECTOR_SUBPARTS (type_in);
6025 enum rs6000_builtins fn
6026 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
6029 case RS6000_BUILTIN_RSQRTF:
6030 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
6031 && out_mode == SFmode && out_n == 4
6032 && in_mode == SFmode && in_n == 4)
6033 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
6035 case RS6000_BUILTIN_RSQRT:
6036 if (VECTOR_UNIT_VSX_P (V2DFmode)
6037 && out_mode == DFmode && out_n == 2
6038 && in_mode == DFmode && in_n == 2)
6039 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
6041 case RS6000_BUILTIN_RECIPF:
6042 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
6043 && out_mode == SFmode && out_n == 4
6044 && in_mode == SFmode && in_n == 4)
6045 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
6047 case RS6000_BUILTIN_RECIP:
6048 if (VECTOR_UNIT_VSX_P (V2DFmode)
6049 && out_mode == DFmode && out_n == 2
6050 && in_mode == DFmode && in_n == 2)
6051 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
6059 /* Default CPU string for rs6000*_file_start functions. */
6060 static const char *rs6000_default_cpu;
6062 /* Do anything needed at the start of the asm file. */
6065 rs6000_file_start (void)
6068 const char *start = buffer;
6069 FILE *file = asm_out_file;
6071 rs6000_default_cpu = TARGET_CPU_DEFAULT;
6073 default_file_start ();
6075 if (flag_verbose_asm)
6077 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
6079 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
6081 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
6085 if (global_options_set.x_rs6000_cpu_index)
6087 fprintf (file, "%s -mcpu=%s", start,
6088 processor_target_table[rs6000_cpu_index].name);
6092 if (global_options_set.x_rs6000_tune_index)
6094 fprintf (file, "%s -mtune=%s", start,
6095 processor_target_table[rs6000_tune_index].name);
6099 if (PPC405_ERRATUM77)
6101 fprintf (file, "%s PPC405CR_ERRATUM77", start);
6105 #ifdef USING_ELFOS_H
6106 switch (rs6000_sdata)
6108 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
6109 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
6110 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
6111 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
6114 if (rs6000_sdata && g_switch_value)
6116 fprintf (file, "%s -G %d", start,
6126 #ifdef USING_ELFOS_H
6127 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
6128 && !global_options_set.x_rs6000_cpu_index)
6130 fputs ("\t.machine ", asm_out_file);
6131 if ((rs6000_isa_flags & OPTION_MASK_MODULO) != 0)
6132 fputs ("power9\n", asm_out_file);
6133 else if ((rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE) != 0)
6134 fputs ("power8\n", asm_out_file);
6135 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTD) != 0)
6136 fputs ("power7\n", asm_out_file);
6137 else if ((rs6000_isa_flags & OPTION_MASK_CMPB) != 0)
6138 fputs ("power6\n", asm_out_file);
6139 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTB) != 0)
6140 fputs ("power5\n", asm_out_file);
6141 else if ((rs6000_isa_flags & OPTION_MASK_MFCRF) != 0)
6142 fputs ("power4\n", asm_out_file);
6143 else if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
6144 fputs ("ppc64\n", asm_out_file);
6146 fputs ("ppc\n", asm_out_file);
6150 if (DEFAULT_ABI == ABI_ELFv2)
6151 fprintf (file, "\t.abiversion 2\n");
6155 /* Return nonzero if this function is known to have a null epilogue. */
6158 direct_return (void)
6160 if (reload_completed)
6162 rs6000_stack_t *info = rs6000_stack_info ();
6164 if (info->first_gp_reg_save == 32
6165 && info->first_fp_reg_save == 64
6166 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
6167 && ! info->lr_save_p
6168 && ! info->cr_save_p
6169 && info->vrsave_size == 0
6177 /* Return the number of instructions it takes to form a constant in an
6178 integer register. */
6181 num_insns_constant_wide (HOST_WIDE_INT value)
6183 /* signed constant loadable with addi */
6184 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
6187 /* constant loadable with addis */
6188 else if ((value & 0xffff) == 0
6189 && (value >> 31 == -1 || value >> 31 == 0))
6192 else if (TARGET_POWERPC64)
6194 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
6195 HOST_WIDE_INT high = value >> 31;
6197 if (high == 0 || high == -1)
6203 return num_insns_constant_wide (high) + 1;
6205 return num_insns_constant_wide (low) + 1;
6207 return (num_insns_constant_wide (high)
6208 + num_insns_constant_wide (low) + 1);
6216 num_insns_constant (rtx op, machine_mode mode)
6218 HOST_WIDE_INT low, high;
6220 switch (GET_CODE (op))
6223 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
6224 && rs6000_is_valid_and_mask (op, mode))
6227 return num_insns_constant_wide (INTVAL (op));
6229 case CONST_WIDE_INT:
6232 int ins = CONST_WIDE_INT_NUNITS (op) - 1;
6233 for (i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
6234 ins += num_insns_constant_wide (CONST_WIDE_INT_ELT (op, i));
6239 if (mode == SFmode || mode == SDmode)
6243 if (DECIMAL_FLOAT_MODE_P (mode))
6244 REAL_VALUE_TO_TARGET_DECIMAL32
6245 (*CONST_DOUBLE_REAL_VALUE (op), l);
6247 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6248 return num_insns_constant_wide ((HOST_WIDE_INT) l);
6252 if (DECIMAL_FLOAT_MODE_P (mode))
6253 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op), l);
6255 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
6256 high = l[WORDS_BIG_ENDIAN == 0];
6257 low = l[WORDS_BIG_ENDIAN != 0];
6260 return (num_insns_constant_wide (low)
6261 + num_insns_constant_wide (high));
6264 if ((high == 0 && low >= 0)
6265 || (high == -1 && low < 0))
6266 return num_insns_constant_wide (low);
6268 else if (rs6000_is_valid_and_mask (op, mode))
6272 return num_insns_constant_wide (high) + 1;
6275 return (num_insns_constant_wide (high)
6276 + num_insns_constant_wide (low) + 1);
6284 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
6285 If the mode of OP is MODE_VECTOR_INT, this simply returns the
6286 corresponding element of the vector, but for V4SFmode and V2SFmode,
6287 the corresponding "float" is interpreted as an SImode integer. */
6290 const_vector_elt_as_int (rtx op, unsigned int elt)
6294 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
6295 gcc_assert (GET_MODE (op) != V2DImode
6296 && GET_MODE (op) != V2DFmode);
6298 tmp = CONST_VECTOR_ELT (op, elt);
6299 if (GET_MODE (op) == V4SFmode
6300 || GET_MODE (op) == V2SFmode)
6301 tmp = gen_lowpart (SImode, tmp);
6302 return INTVAL (tmp);
6305 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
6306 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
6307 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
6308 all items are set to the same value and contain COPIES replicas of the
6309 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
6310 operand and the others are set to the value of the operand's msb. */
6313 vspltis_constant (rtx op, unsigned step, unsigned copies)
6315 machine_mode mode = GET_MODE (op);
6316 machine_mode inner = GET_MODE_INNER (mode);
6324 HOST_WIDE_INT splat_val;
6325 HOST_WIDE_INT msb_val;
6327 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
6330 nunits = GET_MODE_NUNITS (mode);
6331 bitsize = GET_MODE_BITSIZE (inner);
6332 mask = GET_MODE_MASK (inner);
6334 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6336 msb_val = val >= 0 ? 0 : -1;
6338 /* Construct the value to be splatted, if possible. If not, return 0. */
6339 for (i = 2; i <= copies; i *= 2)
6341 HOST_WIDE_INT small_val;
6343 small_val = splat_val >> bitsize;
6345 if (splat_val != ((HOST_WIDE_INT)
6346 ((unsigned HOST_WIDE_INT) small_val << bitsize)
6347 | (small_val & mask)))
6349 splat_val = small_val;
6352 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
6353 if (EASY_VECTOR_15 (splat_val))
6356 /* Also check if we can splat, and then add the result to itself. Do so if
6357 the value is positive, of if the splat instruction is using OP's mode;
6358 for splat_val < 0, the splat and the add should use the same mode. */
6359 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
6360 && (splat_val >= 0 || (step == 1 && copies == 1)))
6363 /* Also check if are loading up the most significant bit which can be done by
6364 loading up -1 and shifting the value left by -1. */
6365 else if (EASY_VECTOR_MSB (splat_val, inner))
6371 /* Check if VAL is present in every STEP-th element, and the
6372 other elements are filled with its most significant bit. */
6373 for (i = 1; i < nunits; ++i)
6375 HOST_WIDE_INT desired_val;
6376 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
6377 if ((i & (step - 1)) == 0)
6380 desired_val = msb_val;
6382 if (desired_val != const_vector_elt_as_int (op, elt))
6389 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6390 instruction, filling in the bottom elements with 0 or -1.
6392 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6393 for the number of zeroes to shift in, or negative for the number of 0xff
6396 OP is a CONST_VECTOR. */
6399 vspltis_shifted (rtx op)
6401 machine_mode mode = GET_MODE (op);
6402 machine_mode inner = GET_MODE_INNER (mode);
6410 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6413 /* We need to create pseudo registers to do the shift, so don't recognize
6414 shift vector constants after reload. */
6415 if (!can_create_pseudo_p ())
6418 nunits = GET_MODE_NUNITS (mode);
6419 mask = GET_MODE_MASK (inner);
6421 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6423 /* Check if the value can really be the operand of a vspltis[bhw]. */
6424 if (EASY_VECTOR_15 (val))
6427 /* Also check if we are loading up the most significant bit which can be done
6428 by loading up -1 and shifting the value left by -1. */
6429 else if (EASY_VECTOR_MSB (val, inner))
6435 /* Check if VAL is present in every STEP-th element until we find elements
6436 that are 0 or all 1 bits. */
6437 for (i = 1; i < nunits; ++i)
6439 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6440 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6442 /* If the value isn't the splat value, check for the remaining elements
6448 for (j = i+1; j < nunits; ++j)
6450 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6451 if (const_vector_elt_as_int (op, elt2) != 0)
6455 return (nunits - i) * GET_MODE_SIZE (inner);
6458 else if ((elt_val & mask) == mask)
6460 for (j = i+1; j < nunits; ++j)
6462 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6463 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6467 return -((nunits - i) * GET_MODE_SIZE (inner));
6475 /* If all elements are equal, we don't need to do VLSDOI. */
6480 /* Return true if OP is of the given MODE and can be synthesized
6481 with a vspltisb, vspltish or vspltisw. */
6484 easy_altivec_constant (rtx op, machine_mode mode)
6486 unsigned step, copies;
6488 if (mode == VOIDmode)
6489 mode = GET_MODE (op);
6490 else if (mode != GET_MODE (op))
6493 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6495 if (mode == V2DFmode)
6496 return zero_constant (op, mode);
6498 else if (mode == V2DImode)
6500 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
6501 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
6504 if (zero_constant (op, mode))
6507 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6508 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6514 /* V1TImode is a special container for TImode. Ignore for now. */
6515 else if (mode == V1TImode)
6518 /* Start with a vspltisw. */
6519 step = GET_MODE_NUNITS (mode) / 4;
6522 if (vspltis_constant (op, step, copies))
6525 /* Then try with a vspltish. */
6531 if (vspltis_constant (op, step, copies))
6534 /* And finally a vspltisb. */
6540 if (vspltis_constant (op, step, copies))
6543 if (vspltis_shifted (op) != 0)
6549 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6550 result is OP. Abort if it is not possible. */
6553 gen_easy_altivec_constant (rtx op)
6555 machine_mode mode = GET_MODE (op);
6556 int nunits = GET_MODE_NUNITS (mode);
6557 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6558 unsigned step = nunits / 4;
6559 unsigned copies = 1;
6561 /* Start with a vspltisw. */
6562 if (vspltis_constant (op, step, copies))
6563 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6565 /* Then try with a vspltish. */
6571 if (vspltis_constant (op, step, copies))
6572 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6574 /* And finally a vspltisb. */
6580 if (vspltis_constant (op, step, copies))
6581 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6586 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6587 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6589 Return the number of instructions needed (1 or 2) into the address pointed
6592 Return the constant that is being split via CONSTANT_PTR. */
6595 xxspltib_constant_p (rtx op,
6600 size_t nunits = GET_MODE_NUNITS (mode);
6602 HOST_WIDE_INT value;
6605 /* Set the returned values to out of bound values. */
6606 *num_insns_ptr = -1;
6607 *constant_ptr = 256;
6609 if (!TARGET_P9_VECTOR)
6612 if (mode == VOIDmode)
6613 mode = GET_MODE (op);
6615 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6618 /* Handle (vec_duplicate <constant>). */
6619 if (GET_CODE (op) == VEC_DUPLICATE)
6621 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6622 && mode != V2DImode)
6625 element = XEXP (op, 0);
6626 if (!CONST_INT_P (element))
6629 value = INTVAL (element);
6630 if (!IN_RANGE (value, -128, 127))
6634 /* Handle (const_vector [...]). */
6635 else if (GET_CODE (op) == CONST_VECTOR)
6637 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6638 && mode != V2DImode)
6641 element = CONST_VECTOR_ELT (op, 0);
6642 if (!CONST_INT_P (element))
6645 value = INTVAL (element);
6646 if (!IN_RANGE (value, -128, 127))
6649 for (i = 1; i < nunits; i++)
6651 element = CONST_VECTOR_ELT (op, i);
6652 if (!CONST_INT_P (element))
6655 if (value != INTVAL (element))
6660 /* Handle integer constants being loaded into the upper part of the VSX
6661 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6662 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6663 else if (CONST_INT_P (op))
6665 if (!SCALAR_INT_MODE_P (mode))
6668 value = INTVAL (op);
6669 if (!IN_RANGE (value, -128, 127))
6672 if (!IN_RANGE (value, -1, 0))
6674 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6677 if (EASY_VECTOR_15 (value))
6685 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6686 sign extend. Special case 0/-1 to allow getting any VSX register instead
6687 of an Altivec register. */
6688 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6689 && EASY_VECTOR_15 (value))
6692 /* Return # of instructions and the constant byte for XXSPLTIB. */
6693 if (mode == V16QImode)
6696 else if (IN_RANGE (value, -1, 0))
6702 *constant_ptr = (int) value;
6707 output_vec_const_move (rtx *operands)
6715 mode = GET_MODE (dest);
6719 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6720 int xxspltib_value = 256;
6723 if (zero_constant (vec, mode))
6725 if (TARGET_P9_VECTOR)
6726 return "xxspltib %x0,0";
6728 else if (dest_vmx_p)
6729 return "vspltisw %0,0";
6732 return "xxlxor %x0,%x0,%x0";
6735 if (all_ones_constant (vec, mode))
6737 if (TARGET_P9_VECTOR)
6738 return "xxspltib %x0,255";
6740 else if (dest_vmx_p)
6741 return "vspltisw %0,-1";
6743 else if (TARGET_P8_VECTOR)
6744 return "xxlorc %x0,%x0,%x0";
6750 if (TARGET_P9_VECTOR
6751 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6755 operands[2] = GEN_INT (xxspltib_value & 0xff);
6756 return "xxspltib %x0,%2";
6767 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6768 if (zero_constant (vec, mode))
6769 return "vspltisw %0,0";
6771 if (all_ones_constant (vec, mode))
6772 return "vspltisw %0,-1";
6774 /* Do we need to construct a value using VSLDOI? */
6775 shift = vspltis_shifted (vec);
6779 splat_vec = gen_easy_altivec_constant (vec);
6780 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6781 operands[1] = XEXP (splat_vec, 0);
6782 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6785 switch (GET_MODE (splat_vec))
6788 return "vspltisw %0,%1";
6791 return "vspltish %0,%1";
6794 return "vspltisb %0,%1";
6804 /* Initialize TARGET of vector PAIRED to VALS. */
6807 paired_expand_vector_init (rtx target, rtx vals)
6809 machine_mode mode = GET_MODE (target);
6810 int n_elts = GET_MODE_NUNITS (mode);
6812 rtx x, new_rtx, tmp, constant_op, op1, op2;
6815 for (i = 0; i < n_elts; ++i)
6817 x = XVECEXP (vals, 0, i);
6818 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6823 /* Load from constant pool. */
6824 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
6830 /* The vector is initialized only with non-constants. */
6831 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
6832 XVECEXP (vals, 0, 1));
6834 emit_move_insn (target, new_rtx);
6838 /* One field is non-constant and the other one is a constant. Load the
6839 constant from the constant pool and use ps_merge instruction to
6840 construct the whole vector. */
6841 op1 = XVECEXP (vals, 0, 0);
6842 op2 = XVECEXP (vals, 0, 1);
6844 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
6846 tmp = gen_reg_rtx (GET_MODE (constant_op));
6847 emit_move_insn (tmp, constant_op);
6849 if (CONSTANT_P (op1))
6850 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
6852 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
6854 emit_move_insn (target, new_rtx);
6858 paired_expand_vector_move (rtx operands[])
6860 rtx op0 = operands[0], op1 = operands[1];
6862 emit_move_insn (op0, op1);
6865 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
6866 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
6867 operands for the relation operation COND. This is a recursive
6871 paired_emit_vector_compare (enum rtx_code rcode,
6872 rtx dest, rtx op0, rtx op1,
6873 rtx cc_op0, rtx cc_op1)
6875 rtx tmp = gen_reg_rtx (V2SFmode);
6878 gcc_assert (TARGET_PAIRED_FLOAT);
6879 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
6885 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
6889 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
6890 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
6894 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
6897 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
6900 tmp1 = gen_reg_rtx (V2SFmode);
6901 max = gen_reg_rtx (V2SFmode);
6902 min = gen_reg_rtx (V2SFmode);
6903 gen_reg_rtx (V2SFmode);
6905 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
6906 emit_insn (gen_selv2sf4
6907 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
6908 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
6909 emit_insn (gen_selv2sf4
6910 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
6911 emit_insn (gen_subv2sf3 (tmp1, min, max));
6912 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
6915 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
6918 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
6921 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
6924 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
6927 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
6936 /* Emit vector conditional expression.
6937 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
6938 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
6941 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
6942 rtx cond, rtx cc_op0, rtx cc_op1)
6944 enum rtx_code rcode = GET_CODE (cond);
6946 if (!TARGET_PAIRED_FLOAT)
6949 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
6954 /* Initialize vector TARGET to VALS. */
6957 rs6000_expand_vector_init (rtx target, rtx vals)
6959 machine_mode mode = GET_MODE (target);
6960 machine_mode inner_mode = GET_MODE_INNER (mode);
6961 int n_elts = GET_MODE_NUNITS (mode);
6962 int n_var = 0, one_var = -1;
6963 bool all_same = true, all_const_zero = true;
6967 for (i = 0; i < n_elts; ++i)
6969 x = XVECEXP (vals, 0, i);
6970 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6971 ++n_var, one_var = i;
6972 else if (x != CONST0_RTX (inner_mode))
6973 all_const_zero = false;
6975 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6981 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6982 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6983 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6985 /* Zero register. */
6986 emit_move_insn (target, CONST0_RTX (mode));
6989 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6991 /* Splat immediate. */
6992 emit_insn (gen_rtx_SET (target, const_vec));
6997 /* Load from constant pool. */
6998 emit_move_insn (target, const_vec);
7003 /* Double word values on VSX can use xxpermdi or lxvdsx. */
7004 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
7008 size_t num_elements = all_same ? 1 : 2;
7009 for (i = 0; i < num_elements; i++)
7011 op[i] = XVECEXP (vals, 0, i);
7012 /* Just in case there is a SUBREG with a smaller mode, do a
7014 if (GET_MODE (op[i]) != inner_mode)
7016 rtx tmp = gen_reg_rtx (inner_mode);
7017 convert_move (tmp, op[i], 0);
7020 /* Allow load with splat double word. */
7021 else if (MEM_P (op[i]))
7024 op[i] = force_reg (inner_mode, op[i]);
7026 else if (!REG_P (op[i]))
7027 op[i] = force_reg (inner_mode, op[i]);
7032 if (mode == V2DFmode)
7033 emit_insn (gen_vsx_splat_v2df (target, op[0]));
7035 emit_insn (gen_vsx_splat_v2di (target, op[0]));
7039 if (mode == V2DFmode)
7040 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
7042 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
7047 /* Special case initializing vector int if we are on 64-bit systems with
7048 direct move or we have the ISA 3.0 instructions. */
7049 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
7050 && TARGET_DIRECT_MOVE_64BIT)
7054 rtx element0 = XVECEXP (vals, 0, 0);
7055 if (MEM_P (element0))
7056 element0 = rs6000_address_for_fpconvert (element0);
7058 element0 = force_reg (SImode, element0);
7060 if (TARGET_P9_VECTOR)
7061 emit_insn (gen_vsx_splat_v4si (target, element0));
7064 rtx tmp = gen_reg_rtx (DImode);
7065 emit_insn (gen_zero_extendsidi2 (tmp, element0));
7066 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
7075 for (i = 0; i < 4; i++)
7077 elements[i] = XVECEXP (vals, 0, i);
7078 if (!CONST_INT_P (elements[i]) && !REG_P (elements[i]))
7079 elements[i] = copy_to_mode_reg (SImode, elements[i]);
7082 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
7083 elements[2], elements[3]));
7088 /* With single precision floating point on VSX, know that internally single
7089 precision is actually represented as a double, and either make 2 V2DF
7090 vectors, and convert these vectors to single precision, or do one
7091 conversion, and splat the result to the other elements. */
7092 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
7096 rtx element0 = XVECEXP (vals, 0, 0);
7098 if (TARGET_P9_VECTOR)
7100 if (MEM_P (element0))
7101 element0 = rs6000_address_for_fpconvert (element0);
7103 emit_insn (gen_vsx_splat_v4sf (target, element0));
7108 rtx freg = gen_reg_rtx (V4SFmode);
7109 rtx sreg = force_reg (SFmode, element0);
7110 rtx cvt = (TARGET_XSCVDPSPN
7111 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
7112 : gen_vsx_xscvdpsp_scalar (freg, sreg));
7115 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
7121 rtx dbl_even = gen_reg_rtx (V2DFmode);
7122 rtx dbl_odd = gen_reg_rtx (V2DFmode);
7123 rtx flt_even = gen_reg_rtx (V4SFmode);
7124 rtx flt_odd = gen_reg_rtx (V4SFmode);
7125 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
7126 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
7127 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
7128 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
7130 /* Use VMRGEW if we can instead of doing a permute. */
7131 if (TARGET_P8_VECTOR)
7133 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
7134 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
7135 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
7136 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
7137 if (BYTES_BIG_ENDIAN)
7138 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
7140 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
7144 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
7145 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
7146 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
7147 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
7148 rs6000_expand_extract_even (target, flt_even, flt_odd);
7154 /* Special case initializing vector short/char that are splats if we are on
7155 64-bit systems with direct move. */
7156 if (all_same && TARGET_DIRECT_MOVE_64BIT
7157 && (mode == V16QImode || mode == V8HImode))
7159 rtx op0 = XVECEXP (vals, 0, 0);
7160 rtx di_tmp = gen_reg_rtx (DImode);
7163 op0 = force_reg (GET_MODE_INNER (mode), op0);
7165 if (mode == V16QImode)
7167 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
7168 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
7172 if (mode == V8HImode)
7174 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
7175 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
7180 /* Store value to stack temp. Load vector element. Splat. However, splat
7181 of 64-bit items is not supported on Altivec. */
7182 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
7184 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
7185 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
7186 XVECEXP (vals, 0, 0));
7187 x = gen_rtx_UNSPEC (VOIDmode,
7188 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
7189 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7191 gen_rtx_SET (target, mem),
7193 x = gen_rtx_VEC_SELECT (inner_mode, target,
7194 gen_rtx_PARALLEL (VOIDmode,
7195 gen_rtvec (1, const0_rtx)));
7196 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
7200 /* One field is non-constant. Load constant then overwrite
7204 rtx copy = copy_rtx (vals);
7206 /* Load constant part of vector, substitute neighboring value for
7208 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
7209 rs6000_expand_vector_init (target, copy);
7211 /* Insert variable. */
7212 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
7216 /* Construct the vector in memory one field at a time
7217 and load the whole vector. */
7218 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7219 for (i = 0; i < n_elts; i++)
7220 emit_move_insn (adjust_address_nv (mem, inner_mode,
7221 i * GET_MODE_SIZE (inner_mode)),
7222 XVECEXP (vals, 0, i));
7223 emit_move_insn (target, mem);
7226 /* Set field ELT of TARGET to VAL. */
7229 rs6000_expand_vector_set (rtx target, rtx val, int elt)
7231 machine_mode mode = GET_MODE (target);
7232 machine_mode inner_mode = GET_MODE_INNER (mode);
7233 rtx reg = gen_reg_rtx (mode);
7235 int width = GET_MODE_SIZE (inner_mode);
7238 val = force_reg (GET_MODE (val), val);
7240 if (VECTOR_MEM_VSX_P (mode))
7242 rtx insn = NULL_RTX;
7243 rtx elt_rtx = GEN_INT (elt);
7245 if (mode == V2DFmode)
7246 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
7248 else if (mode == V2DImode)
7249 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
7251 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
7253 if (mode == V4SImode)
7254 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
7255 else if (mode == V8HImode)
7256 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
7257 else if (mode == V16QImode)
7258 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
7259 else if (mode == V4SFmode)
7260 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
7270 /* Simplify setting single element vectors like V1TImode. */
7271 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
7273 emit_move_insn (target, gen_lowpart (mode, val));
7277 /* Load single variable value. */
7278 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
7279 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
7280 x = gen_rtx_UNSPEC (VOIDmode,
7281 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
7282 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7284 gen_rtx_SET (reg, mem),
7287 /* Linear sequence. */
7288 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
7289 for (i = 0; i < 16; ++i)
7290 XVECEXP (mask, 0, i) = GEN_INT (i);
7292 /* Set permute mask to insert element into target. */
7293 for (i = 0; i < width; ++i)
7294 XVECEXP (mask, 0, elt*width + i)
7295 = GEN_INT (i + 0x10);
7296 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
7298 if (BYTES_BIG_ENDIAN)
7299 x = gen_rtx_UNSPEC (mode,
7300 gen_rtvec (3, target, reg,
7301 force_reg (V16QImode, x)),
7305 if (TARGET_P9_VECTOR)
7306 x = gen_rtx_UNSPEC (mode,
7307 gen_rtvec (3, reg, target,
7308 force_reg (V16QImode, x)),
7312 /* Invert selector. We prefer to generate VNAND on P8 so
7313 that future fusion opportunities can kick in, but must
7314 generate VNOR elsewhere. */
7315 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
7316 rtx iorx = (TARGET_P8_VECTOR
7317 ? gen_rtx_IOR (V16QImode, notx, notx)
7318 : gen_rtx_AND (V16QImode, notx, notx));
7319 rtx tmp = gen_reg_rtx (V16QImode);
7320 emit_insn (gen_rtx_SET (tmp, iorx));
7322 /* Permute with operands reversed and adjusted selector. */
7323 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
7328 emit_insn (gen_rtx_SET (target, x));
7331 /* Extract field ELT from VEC into TARGET. */
7334 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
7336 machine_mode mode = GET_MODE (vec);
7337 machine_mode inner_mode = GET_MODE_INNER (mode);
7340 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
7347 gcc_assert (INTVAL (elt) == 0 && inner_mode == TImode);
7348 emit_move_insn (target, gen_lowpart (TImode, vec));
7351 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
7354 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
7357 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
7360 if (TARGET_DIRECT_MOVE_64BIT)
7362 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
7368 if (TARGET_DIRECT_MOVE_64BIT)
7370 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
7376 if (TARGET_DIRECT_MOVE_64BIT)
7378 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
7384 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
7385 && TARGET_DIRECT_MOVE_64BIT)
7387 if (GET_MODE (elt) != DImode)
7389 rtx tmp = gen_reg_rtx (DImode);
7390 convert_move (tmp, elt, 0);
7393 else if (!REG_P (elt))
7394 elt = force_reg (DImode, elt);
7399 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
7403 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
7407 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
7411 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
7415 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
7419 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
7427 gcc_assert (CONST_INT_P (elt));
7429 /* Allocate mode-sized buffer. */
7430 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
7432 emit_move_insn (mem, vec);
7434 /* Add offset to field within buffer matching vector element. */
7435 mem = adjust_address_nv (mem, inner_mode,
7436 INTVAL (elt) * GET_MODE_SIZE (inner_mode));
7438 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
7441 /* Helper function to return the register number of a RTX. */
7443 regno_or_subregno (rtx op)
7447 else if (SUBREG_P (op))
7448 return subreg_regno (op);
7453 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
7454 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
7455 temporary (BASE_TMP) to fixup the address. Return the new memory address
7456 that is valid for reads or writes to a given register (SCALAR_REG). */
7459 rs6000_adjust_vec_address (rtx scalar_reg,
7463 machine_mode scalar_mode)
7465 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7466 rtx addr = XEXP (mem, 0);
7471 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
7472 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
7474 /* Calculate what we need to add to the address to get the element
7476 if (CONST_INT_P (element))
7477 element_offset = GEN_INT (INTVAL (element) * scalar_size);
7480 int byte_shift = exact_log2 (scalar_size);
7481 gcc_assert (byte_shift >= 0);
7483 if (byte_shift == 0)
7484 element_offset = element;
7488 if (TARGET_POWERPC64)
7489 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
7491 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
7493 element_offset = base_tmp;
7497 /* Create the new address pointing to the element within the vector. If we
7498 are adding 0, we don't have to change the address. */
7499 if (element_offset == const0_rtx)
7502 /* A simple indirect address can be converted into a reg + offset
7504 else if (REG_P (addr) || SUBREG_P (addr))
7505 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
7507 /* Optimize D-FORM addresses with constant offset with a constant element, to
7508 include the element offset in the address directly. */
7509 else if (GET_CODE (addr) == PLUS)
7511 rtx op0 = XEXP (addr, 0);
7512 rtx op1 = XEXP (addr, 1);
7515 gcc_assert (REG_P (op0) || SUBREG_P (op0));
7516 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
7518 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
7519 rtx offset_rtx = GEN_INT (offset);
7521 if (IN_RANGE (offset, -32768, 32767)
7522 && (scalar_size < 8 || (offset & 0x3) == 0))
7523 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
7526 emit_move_insn (base_tmp, offset_rtx);
7527 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7532 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7533 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7535 /* Note, ADDI requires the register being added to be a base
7536 register. If the register was R0, load it up into the temporary
7539 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7541 insn = gen_add3_insn (base_tmp, op1, element_offset);
7542 gcc_assert (insn != NULL_RTX);
7547 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7549 insn = gen_add3_insn (base_tmp, element_offset, op1);
7550 gcc_assert (insn != NULL_RTX);
7556 emit_move_insn (base_tmp, op1);
7557 emit_insn (gen_add2_insn (base_tmp, element_offset));
7560 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7566 emit_move_insn (base_tmp, addr);
7567 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7570 /* If we have a PLUS, we need to see whether the particular register class
7571 allows for D-FORM or X-FORM addressing. */
7572 if (GET_CODE (new_addr) == PLUS)
7574 rtx op1 = XEXP (new_addr, 1);
7575 addr_mask_type addr_mask;
7576 int scalar_regno = regno_or_subregno (scalar_reg);
7578 gcc_assert (scalar_regno < FIRST_PSEUDO_REGISTER);
7579 if (INT_REGNO_P (scalar_regno))
7580 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7582 else if (FP_REGNO_P (scalar_regno))
7583 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7585 else if (ALTIVEC_REGNO_P (scalar_regno))
7586 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7591 if (REG_P (op1) || SUBREG_P (op1))
7592 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7594 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7597 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7598 valid_addr_p = true;
7601 valid_addr_p = false;
7605 emit_move_insn (base_tmp, new_addr);
7606 new_addr = base_tmp;
7609 return change_address (mem, scalar_mode, new_addr);
7612 /* Split a variable vec_extract operation into the component instructions. */
7615 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7618 machine_mode mode = GET_MODE (src);
7619 machine_mode scalar_mode = GET_MODE (dest);
7620 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7621 int byte_shift = exact_log2 (scalar_size);
7623 gcc_assert (byte_shift >= 0);
7625 /* If we are given a memory address, optimize to load just the element. We
7626 don't have to adjust the vector element number on little endian
7630 gcc_assert (REG_P (tmp_gpr));
7631 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7632 tmp_gpr, scalar_mode));
7636 else if (REG_P (src) || SUBREG_P (src))
7638 int bit_shift = byte_shift + 3;
7640 int dest_regno = regno_or_subregno (dest);
7641 int src_regno = regno_or_subregno (src);
7642 int element_regno = regno_or_subregno (element);
7644 gcc_assert (REG_P (tmp_gpr));
7646 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7647 a general purpose register. */
7648 if (TARGET_P9_VECTOR
7649 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7650 && INT_REGNO_P (dest_regno)
7651 && ALTIVEC_REGNO_P (src_regno)
7652 && INT_REGNO_P (element_regno))
7654 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7655 rtx element_si = gen_rtx_REG (SImode, element_regno);
7657 if (mode == V16QImode)
7658 emit_insn (VECTOR_ELT_ORDER_BIG
7659 ? gen_vextublx (dest_si, element_si, src)
7660 : gen_vextubrx (dest_si, element_si, src));
7662 else if (mode == V8HImode)
7664 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7665 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7666 emit_insn (VECTOR_ELT_ORDER_BIG
7667 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7668 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7674 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7675 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7676 emit_insn (VECTOR_ELT_ORDER_BIG
7677 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7678 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7685 gcc_assert (REG_P (tmp_altivec));
7687 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7688 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7689 will shift the element into the upper position (adding 3 to convert a
7690 byte shift into a bit shift). */
7691 if (scalar_size == 8)
7693 if (!VECTOR_ELT_ORDER_BIG)
7695 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7701 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7703 emit_insn (gen_rtx_SET (tmp_gpr,
7704 gen_rtx_AND (DImode,
7705 gen_rtx_ASHIFT (DImode,
7712 if (!VECTOR_ELT_ORDER_BIG)
7714 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
7716 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7717 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7723 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7726 /* Get the value into the lower byte of the Altivec register where VSLO
7728 if (TARGET_P9_VECTOR)
7729 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7730 else if (can_create_pseudo_p ())
7731 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7734 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7735 emit_move_insn (tmp_di, tmp_gpr);
7736 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7739 /* Do the VSLO to get the value into the final location. */
7743 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7747 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7752 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7753 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7754 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7755 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7758 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7766 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7767 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7768 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7769 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7771 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7772 emit_insn (gen_ashrdi3 (tmp_gpr_di, tmp_gpr_di,
7773 GEN_INT (64 - (8 * scalar_size))));
7787 /* Helper function for rs6000_split_v4si_init to build up a DImode value from
7788 two SImode values. */
7791 rs6000_split_v4si_init_di_reg (rtx dest, rtx si1, rtx si2, rtx tmp)
7793 const unsigned HOST_WIDE_INT mask_32bit = HOST_WIDE_INT_C (0xffffffff);
7795 if (CONST_INT_P (si1) && CONST_INT_P (si2))
7797 unsigned HOST_WIDE_INT const1 = (UINTVAL (si1) & mask_32bit) << 32;
7798 unsigned HOST_WIDE_INT const2 = UINTVAL (si2) & mask_32bit;
7800 emit_move_insn (dest, GEN_INT (const1 | const2));
7804 /* Put si1 into upper 32-bits of dest. */
7805 if (CONST_INT_P (si1))
7806 emit_move_insn (dest, GEN_INT ((UINTVAL (si1) & mask_32bit) << 32));
7809 /* Generate RLDIC. */
7810 rtx si1_di = gen_rtx_REG (DImode, regno_or_subregno (si1));
7811 rtx shift_rtx = gen_rtx_ASHIFT (DImode, si1_di, GEN_INT (32));
7812 rtx mask_rtx = GEN_INT (mask_32bit << 32);
7813 rtx and_rtx = gen_rtx_AND (DImode, shift_rtx, mask_rtx);
7814 gcc_assert (!reg_overlap_mentioned_p (dest, si1));
7815 emit_insn (gen_rtx_SET (dest, and_rtx));
7818 /* Put si2 into the temporary. */
7819 gcc_assert (!reg_overlap_mentioned_p (dest, tmp));
7820 if (CONST_INT_P (si2))
7821 emit_move_insn (tmp, GEN_INT (UINTVAL (si2) & mask_32bit));
7823 emit_insn (gen_zero_extendsidi2 (tmp, si2));
7825 /* Combine the two parts. */
7826 emit_insn (gen_iordi3 (dest, dest, tmp));
7830 /* Split a V4SI initialization. */
7833 rs6000_split_v4si_init (rtx operands[])
7835 rtx dest = operands[0];
7837 /* Destination is a GPR, build up the two DImode parts in place. */
7838 if (REG_P (dest) || SUBREG_P (dest))
7840 int d_regno = regno_or_subregno (dest);
7841 rtx scalar1 = operands[1];
7842 rtx scalar2 = operands[2];
7843 rtx scalar3 = operands[3];
7844 rtx scalar4 = operands[4];
7845 rtx tmp1 = operands[5];
7846 rtx tmp2 = operands[6];
7848 /* Even though we only need one temporary (plus the destination, which
7849 has an early clobber constraint, try to use two temporaries, one for
7850 each double word created. That way the 2nd insn scheduling pass can
7851 rearrange things so the two parts are done in parallel. */
7852 if (BYTES_BIG_ENDIAN)
7854 rtx di_lo = gen_rtx_REG (DImode, d_regno);
7855 rtx di_hi = gen_rtx_REG (DImode, d_regno + 1);
7856 rs6000_split_v4si_init_di_reg (di_lo, scalar1, scalar2, tmp1);
7857 rs6000_split_v4si_init_di_reg (di_hi, scalar3, scalar4, tmp2);
7861 rtx di_lo = gen_rtx_REG (DImode, d_regno + 1);
7862 rtx di_hi = gen_rtx_REG (DImode, d_regno);
7863 gcc_assert (!VECTOR_ELT_ORDER_BIG);
7864 rs6000_split_v4si_init_di_reg (di_lo, scalar4, scalar3, tmp1);
7865 rs6000_split_v4si_init_di_reg (di_hi, scalar2, scalar1, tmp2);
7874 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7875 selects whether the alignment is abi mandated, optional, or
7876 both abi and optional alignment. */
7879 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7881 if (how != align_opt)
7883 if (TREE_CODE (type) == VECTOR_TYPE)
7885 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type)))
7890 else if (align < 128)
7895 if (how != align_abi)
7897 if (TREE_CODE (type) == ARRAY_TYPE
7898 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7900 if (align < BITS_PER_WORD)
7901 align = BITS_PER_WORD;
7908 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7909 instructions simply ignore the low bits; VSX memory instructions
7910 are aligned to 4 or 8 bytes. */
7913 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7915 return (STRICT_ALIGNMENT
7916 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7917 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7918 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7919 && (int) align < VECTOR_ALIGN (mode)))));
7922 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7925 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7927 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7929 if (computed != 128)
7932 if (!warned && warn_psabi)
7935 inform (input_location,
7936 "the layout of aggregates containing vectors with"
7937 " %d-byte alignment has changed in GCC 5",
7938 computed / BITS_PER_UNIT);
7941 /* In current GCC there is no special case. */
7948 /* AIX increases natural record alignment to doubleword if the first
7949 field is an FP double while the FP fields remain word aligned. */
7952 rs6000_special_round_type_align (tree type, unsigned int computed,
7953 unsigned int specified)
7955 unsigned int align = MAX (computed, specified);
7956 tree field = TYPE_FIELDS (type);
7958 /* Skip all non field decls */
7959 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7960 field = DECL_CHAIN (field);
7962 if (field != NULL && field != type)
7964 type = TREE_TYPE (field);
7965 while (TREE_CODE (type) == ARRAY_TYPE)
7966 type = TREE_TYPE (type);
7968 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7969 align = MAX (align, 64);
7975 /* Darwin increases record alignment to the natural alignment of
7979 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7980 unsigned int specified)
7982 unsigned int align = MAX (computed, specified);
7984 if (TYPE_PACKED (type))
7987 /* Find the first field, looking down into aggregates. */
7989 tree field = TYPE_FIELDS (type);
7990 /* Skip all non field decls */
7991 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7992 field = DECL_CHAIN (field);
7995 /* A packed field does not contribute any extra alignment. */
7996 if (DECL_PACKED (field))
7998 type = TREE_TYPE (field);
7999 while (TREE_CODE (type) == ARRAY_TYPE)
8000 type = TREE_TYPE (type);
8001 } while (AGGREGATE_TYPE_P (type));
8003 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
8004 align = MAX (align, TYPE_ALIGN (type));
8009 /* Return 1 for an operand in small memory on V.4/eabi. */
8012 small_data_operand (rtx op ATTRIBUTE_UNUSED,
8013 machine_mode mode ATTRIBUTE_UNUSED)
8018 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
8021 if (DEFAULT_ABI != ABI_V4)
8024 if (GET_CODE (op) == SYMBOL_REF)
8027 else if (GET_CODE (op) != CONST
8028 || GET_CODE (XEXP (op, 0)) != PLUS
8029 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
8030 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
8035 rtx sum = XEXP (op, 0);
8036 HOST_WIDE_INT summand;
8038 /* We have to be careful here, because it is the referenced address
8039 that must be 32k from _SDA_BASE_, not just the symbol. */
8040 summand = INTVAL (XEXP (sum, 1));
8041 if (summand < 0 || summand > g_switch_value)
8044 sym_ref = XEXP (sum, 0);
8047 return SYMBOL_REF_SMALL_P (sym_ref);
8053 /* Return true if either operand is a general purpose register. */
8056 gpr_or_gpr_p (rtx op0, rtx op1)
8058 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
8059 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
8062 /* Return true if this is a move direct operation between GPR registers and
8063 floating point/VSX registers. */
8066 direct_move_p (rtx op0, rtx op1)
8070 if (!REG_P (op0) || !REG_P (op1))
8073 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
8076 regno0 = REGNO (op0);
8077 regno1 = REGNO (op1);
8078 if (regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER)
8081 if (INT_REGNO_P (regno0))
8082 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
8084 else if (INT_REGNO_P (regno1))
8086 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
8089 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
8096 /* Return true if the OFFSET is valid for the quad address instructions that
8097 use d-form (register + offset) addressing. */
8100 quad_address_offset_p (HOST_WIDE_INT offset)
8102 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
8105 /* Return true if the ADDR is an acceptable address for a quad memory
8106 operation of mode MODE (either LQ/STQ for general purpose registers, or
8107 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
8108 is intended for LQ/STQ. If it is false, the address is intended for the ISA
8109 3.0 LXV/STXV instruction. */
8112 quad_address_p (rtx addr, machine_mode mode, bool strict)
8116 if (GET_MODE_SIZE (mode) != 16)
8119 if (legitimate_indirect_address_p (addr, strict))
8122 if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode))
8125 if (GET_CODE (addr) != PLUS)
8128 op0 = XEXP (addr, 0);
8129 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
8132 op1 = XEXP (addr, 1);
8133 if (!CONST_INT_P (op1))
8136 return quad_address_offset_p (INTVAL (op1));
8139 /* Return true if this is a load or store quad operation. This function does
8140 not handle the atomic quad memory instructions. */
8143 quad_load_store_p (rtx op0, rtx op1)
8147 if (!TARGET_QUAD_MEMORY)
8150 else if (REG_P (op0) && MEM_P (op1))
8151 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
8152 && quad_memory_operand (op1, GET_MODE (op1))
8153 && !reg_overlap_mentioned_p (op0, op1));
8155 else if (MEM_P (op0) && REG_P (op1))
8156 ret = (quad_memory_operand (op0, GET_MODE (op0))
8157 && quad_int_reg_operand (op1, GET_MODE (op1)));
8162 if (TARGET_DEBUG_ADDR)
8164 fprintf (stderr, "\n========== quad_load_store, return %s\n",
8165 ret ? "true" : "false");
8166 debug_rtx (gen_rtx_SET (op0, op1));
8172 /* Given an address, return a constant offset term if one exists. */
8175 address_offset (rtx op)
8177 if (GET_CODE (op) == PRE_INC
8178 || GET_CODE (op) == PRE_DEC)
8180 else if (GET_CODE (op) == PRE_MODIFY
8181 || GET_CODE (op) == LO_SUM)
8184 if (GET_CODE (op) == CONST)
8187 if (GET_CODE (op) == PLUS)
8190 if (CONST_INT_P (op))
8196 /* Return true if the MEM operand is a memory operand suitable for use
8197 with a (full width, possibly multiple) gpr load/store. On
8198 powerpc64 this means the offset must be divisible by 4.
8199 Implements 'Y' constraint.
8201 Accept direct, indexed, offset, lo_sum and tocref. Since this is
8202 a constraint function we know the operand has satisfied a suitable
8203 memory predicate. Also accept some odd rtl generated by reload
8204 (see rs6000_legitimize_reload_address for various forms). It is
8205 important that reload rtl be accepted by appropriate constraints
8206 but not by the operand predicate.
8208 Offsetting a lo_sum should not be allowed, except where we know by
8209 alignment that a 32k boundary is not crossed, but see the ???
8210 comment in rs6000_legitimize_reload_address. Note that by
8211 "offsetting" here we mean a further offset to access parts of the
8212 MEM. It's fine to have a lo_sum where the inner address is offset
8213 from a sym, since the same sym+offset will appear in the high part
8214 of the address calculation. */
8217 mem_operand_gpr (rtx op, machine_mode mode)
8219 unsigned HOST_WIDE_INT offset;
8221 rtx addr = XEXP (op, 0);
8223 /* Don't allow altivec type addresses like (mem (and (plus ...))).
8224 See PR target/84279. */
8226 if (GET_CODE (addr) == AND)
8229 op = address_offset (addr);
8233 offset = INTVAL (op);
8234 if (TARGET_POWERPC64 && (offset & 3) != 0)
8237 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8241 if (GET_CODE (addr) == LO_SUM)
8242 /* For lo_sum addresses, we must allow any offset except one that
8243 causes a wrap, so test only the low 16 bits. */
8244 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8246 return offset + 0x8000 < 0x10000u - extra;
8249 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
8250 enforce an offset divisible by 4 even for 32-bit. */
8253 mem_operand_ds_form (rtx op, machine_mode mode)
8255 unsigned HOST_WIDE_INT offset;
8257 rtx addr = XEXP (op, 0);
8259 if (!offsettable_address_p (false, mode, addr))
8262 op = address_offset (addr);
8266 offset = INTVAL (op);
8267 if ((offset & 3) != 0)
8270 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
8274 if (GET_CODE (addr) == LO_SUM)
8275 /* For lo_sum addresses, we must allow any offset except one that
8276 causes a wrap, so test only the low 16 bits. */
8277 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
8279 return offset + 0x8000 < 0x10000u - extra;
8282 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
8285 reg_offset_addressing_ok_p (machine_mode mode)
8299 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
8300 ISA 3.0 vector d-form addressing mode was added. While TImode is not
8301 a vector mode, if we want to use the VSX registers to move it around,
8302 we need to restrict ourselves to reg+reg addressing. Similarly for
8303 IEEE 128-bit floating point that is passed in a single vector
8305 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
8306 return mode_supports_vsx_dform_quad (mode);
8311 /* Paired vector modes. Only reg+reg addressing is valid. */
8312 if (TARGET_PAIRED_FLOAT)
8317 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
8318 addressing for the LFIWZX and STFIWX instructions. */
8319 if (TARGET_NO_SDMODE_STACK)
8331 virtual_stack_registers_memory_p (rtx op)
8335 if (GET_CODE (op) == REG)
8336 regnum = REGNO (op);
8338 else if (GET_CODE (op) == PLUS
8339 && GET_CODE (XEXP (op, 0)) == REG
8340 && GET_CODE (XEXP (op, 1)) == CONST_INT)
8341 regnum = REGNO (XEXP (op, 0));
8346 return (regnum >= FIRST_VIRTUAL_REGISTER
8347 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
8350 /* Return true if a MODE sized memory accesses to OP plus OFFSET
8351 is known to not straddle a 32k boundary. This function is used
8352 to determine whether -mcmodel=medium code can use TOC pointer
8353 relative addressing for OP. This means the alignment of the TOC
8354 pointer must also be taken into account, and unfortunately that is
8357 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
8358 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
8362 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
8366 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
8368 if (GET_CODE (op) != SYMBOL_REF)
8371 /* ISA 3.0 vector d-form addressing is restricted, don't allow
8373 if (mode_supports_vsx_dform_quad (mode))
8376 dsize = GET_MODE_SIZE (mode);
8377 decl = SYMBOL_REF_DECL (op);
8383 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
8384 replacing memory addresses with an anchor plus offset. We
8385 could find the decl by rummaging around in the block->objects
8386 VEC for the given offset but that seems like too much work. */
8387 dalign = BITS_PER_UNIT;
8388 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
8389 && SYMBOL_REF_ANCHOR_P (op)
8390 && SYMBOL_REF_BLOCK (op) != NULL)
8392 struct object_block *block = SYMBOL_REF_BLOCK (op);
8394 dalign = block->alignment;
8395 offset += SYMBOL_REF_BLOCK_OFFSET (op);
8397 else if (CONSTANT_POOL_ADDRESS_P (op))
8399 /* It would be nice to have get_pool_align().. */
8400 machine_mode cmode = get_pool_mode (op);
8402 dalign = GET_MODE_ALIGNMENT (cmode);
8405 else if (DECL_P (decl))
8407 dalign = DECL_ALIGN (decl);
8411 /* Allow BLKmode when the entire object is known to not
8412 cross a 32k boundary. */
8413 if (!DECL_SIZE_UNIT (decl))
8416 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
8419 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
8423 dalign /= BITS_PER_UNIT;
8424 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8425 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8426 return dalign >= dsize;
8432 /* Find how many bits of the alignment we know for this access. */
8433 dalign /= BITS_PER_UNIT;
8434 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
8435 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
8437 lsb = offset & -offset;
8441 return dalign >= dsize;
8445 constant_pool_expr_p (rtx op)
8449 split_const (op, &base, &offset);
8450 return (GET_CODE (base) == SYMBOL_REF
8451 && CONSTANT_POOL_ADDRESS_P (base)
8452 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
8455 /* These are only used to pass through from print_operand/print_operand_address
8456 to rs6000_output_addr_const_extra over the intervening function
8457 output_addr_const which is not target code. */
8458 static const_rtx tocrel_base_oac, tocrel_offset_oac;
8460 /* Return true if OP is a toc pointer relative address (the output
8461 of create_TOC_reference). If STRICT, do not match non-split
8462 -mcmodel=large/medium toc pointer relative addresses. If the pointers
8463 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
8464 TOCREL_OFFSET_RET respectively. */
8467 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
8468 const_rtx *tocrel_offset_ret)
8473 if (TARGET_CMODEL != CMODEL_SMALL)
8475 /* When strict ensure we have everything tidy. */
8477 && !(GET_CODE (op) == LO_SUM
8478 && REG_P (XEXP (op, 0))
8479 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
8482 /* When not strict, allow non-split TOC addresses and also allow
8483 (lo_sum (high ..)) TOC addresses created during reload. */
8484 if (GET_CODE (op) == LO_SUM)
8488 const_rtx tocrel_base = op;
8489 const_rtx tocrel_offset = const0_rtx;
8491 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
8493 tocrel_base = XEXP (op, 0);
8494 tocrel_offset = XEXP (op, 1);
8497 if (tocrel_base_ret)
8498 *tocrel_base_ret = tocrel_base;
8499 if (tocrel_offset_ret)
8500 *tocrel_offset_ret = tocrel_offset;
8502 return (GET_CODE (tocrel_base) == UNSPEC
8503 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
8506 /* Return true if X is a constant pool address, and also for cmodel=medium
8507 if X is a toc-relative address known to be offsettable within MODE. */
8510 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
8513 const_rtx tocrel_base, tocrel_offset;
8514 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
8515 && (TARGET_CMODEL != CMODEL_MEDIUM
8516 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
8518 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
8519 INTVAL (tocrel_offset), mode)));
8523 legitimate_small_data_p (machine_mode mode, rtx x)
8525 return (DEFAULT_ABI == ABI_V4
8526 && !flag_pic && !TARGET_TOC
8527 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
8528 && small_data_operand (x, mode));
8532 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
8533 bool strict, bool worst_case)
8535 unsigned HOST_WIDE_INT offset;
8538 if (GET_CODE (x) != PLUS)
8540 if (!REG_P (XEXP (x, 0)))
8542 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8544 if (mode_supports_vsx_dform_quad (mode))
8545 return quad_address_p (x, mode, strict);
8546 if (!reg_offset_addressing_ok_p (mode))
8547 return virtual_stack_registers_memory_p (x);
8548 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
8550 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
8553 offset = INTVAL (XEXP (x, 1));
8559 /* Paired single modes: offset addressing isn't valid. */
8565 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
8567 if (VECTOR_MEM_VSX_P (mode))
8572 if (!TARGET_POWERPC64)
8574 else if (offset & 3)
8587 if (!TARGET_POWERPC64)
8589 else if (offset & 3)
8598 return offset < 0x10000 - extra;
8602 legitimate_indexed_address_p (rtx x, int strict)
8606 if (GET_CODE (x) != PLUS)
8612 return (REG_P (op0) && REG_P (op1)
8613 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
8614 && INT_REG_OK_FOR_INDEX_P (op1, strict))
8615 || (INT_REG_OK_FOR_BASE_P (op1, strict)
8616 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
8620 avoiding_indexed_address_p (machine_mode mode)
8622 /* Avoid indexed addressing for modes that have non-indexed
8623 load/store instruction forms. */
8624 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8628 legitimate_indirect_address_p (rtx x, int strict)
8630 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
8634 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8636 if (!TARGET_MACHO || !flag_pic
8637 || mode != SImode || GET_CODE (x) != MEM)
8641 if (GET_CODE (x) != LO_SUM)
8643 if (GET_CODE (XEXP (x, 0)) != REG)
8645 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8649 return CONSTANT_P (x);
8653 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8655 if (GET_CODE (x) != LO_SUM)
8657 if (GET_CODE (XEXP (x, 0)) != REG)
8659 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8661 /* quad word addresses are restricted, and we can't use LO_SUM. */
8662 if (mode_supports_vsx_dform_quad (mode))
8666 if (TARGET_ELF || TARGET_MACHO)
8670 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8672 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8673 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8674 recognizes some LO_SUM addresses as valid although this
8675 function says opposite. In most cases, LRA through different
8676 transformations can generate correct code for address reloads.
8677 It can not manage only some LO_SUM cases. So we need to add
8678 code analogous to one in rs6000_legitimize_reload_address for
8679 LOW_SUM here saying that some addresses are still valid. */
8680 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8681 && small_toc_ref (x, VOIDmode));
8682 if (TARGET_TOC && ! large_toc_ok)
8684 if (GET_MODE_NUNITS (mode) != 1)
8686 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8687 && !(/* ??? Assume floating point reg based on mode? */
8688 TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
8689 && (mode == DFmode || mode == DDmode)))
8692 return CONSTANT_P (x) || large_toc_ok;
8699 /* Try machine-dependent ways of modifying an illegitimate address
8700 to be legitimate. If we find one, return the new, valid address.
8701 This is used from only one place: `memory_address' in explow.c.
8703 OLDX is the address as it was before break_out_memory_refs was
8704 called. In some cases it is useful to look at this to decide what
8707 It is always safe for this function to do nothing. It exists to
8708 recognize opportunities to optimize the output.
8710 On RS/6000, first check for the sum of a register with a constant
8711 integer that is out of range. If so, generate code to add the
8712 constant with the low-order 16 bits masked to the register and force
8713 this result into another register (this can be done with `cau').
8714 Then generate an address of REG+(CONST&0xffff), allowing for the
8715 possibility of bit 16 being a one.
8717 Then check for the sum of a register and something not constant, try to
8718 load the other things into a register and return the sum. */
8721 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8726 if (!reg_offset_addressing_ok_p (mode)
8727 || mode_supports_vsx_dform_quad (mode))
8729 if (virtual_stack_registers_memory_p (x))
8732 /* In theory we should not be seeing addresses of the form reg+0,
8733 but just in case it is generated, optimize it away. */
8734 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8735 return force_reg (Pmode, XEXP (x, 0));
8737 /* For TImode with load/store quad, restrict addresses to just a single
8738 pointer, so it works with both GPRs and VSX registers. */
8739 /* Make sure both operands are registers. */
8740 else if (GET_CODE (x) == PLUS
8741 && (mode != TImode || !TARGET_VSX))
8742 return gen_rtx_PLUS (Pmode,
8743 force_reg (Pmode, XEXP (x, 0)),
8744 force_reg (Pmode, XEXP (x, 1)));
8746 return force_reg (Pmode, x);
8748 if (GET_CODE (x) == SYMBOL_REF)
8750 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8752 return rs6000_legitimize_tls_address (x, model);
8764 /* As in legitimate_offset_address_p we do not assume
8765 worst-case. The mode here is just a hint as to the registers
8766 used. A TImode is usually in gprs, but may actually be in
8767 fprs. Leave worst-case scenario for reload to handle via
8768 insn constraints. PTImode is only GPRs. */
8775 if (GET_CODE (x) == PLUS
8776 && GET_CODE (XEXP (x, 0)) == REG
8777 && GET_CODE (XEXP (x, 1)) == CONST_INT
8778 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8780 && !PAIRED_VECTOR_MODE (mode))
8782 HOST_WIDE_INT high_int, low_int;
8784 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8785 if (low_int >= 0x8000 - extra)
8787 high_int = INTVAL (XEXP (x, 1)) - low_int;
8788 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8789 GEN_INT (high_int)), 0);
8790 return plus_constant (Pmode, sum, low_int);
8792 else if (GET_CODE (x) == PLUS
8793 && GET_CODE (XEXP (x, 0)) == REG
8794 && GET_CODE (XEXP (x, 1)) != CONST_INT
8795 && GET_MODE_NUNITS (mode) == 1
8796 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8797 || (/* ??? Assume floating point reg based on mode? */
8798 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8799 && (mode == DFmode || mode == DDmode)))
8800 && !avoiding_indexed_address_p (mode))
8802 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8803 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8805 else if (PAIRED_VECTOR_MODE (mode))
8809 /* We accept [reg + reg]. */
8811 if (GET_CODE (x) == PLUS)
8813 rtx op1 = XEXP (x, 0);
8814 rtx op2 = XEXP (x, 1);
8817 op1 = force_reg (Pmode, op1);
8818 op2 = force_reg (Pmode, op2);
8820 /* We can't always do [reg + reg] for these, because [reg +
8821 reg + offset] is not a legitimate addressing mode. */
8822 y = gen_rtx_PLUS (Pmode, op1, op2);
8824 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
8825 return force_reg (Pmode, y);
8830 return force_reg (Pmode, x);
8832 else if ((TARGET_ELF
8834 || !MACHO_DYNAMIC_NO_PIC_P
8840 && GET_CODE (x) != CONST_INT
8841 && GET_CODE (x) != CONST_WIDE_INT
8842 && GET_CODE (x) != CONST_DOUBLE
8844 && GET_MODE_NUNITS (mode) == 1
8845 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8846 || (/* ??? Assume floating point reg based on mode? */
8847 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8848 && (mode == DFmode || mode == DDmode))))
8850 rtx reg = gen_reg_rtx (Pmode);
8852 emit_insn (gen_elf_high (reg, x));
8854 emit_insn (gen_macho_high (reg, x));
8855 return gen_rtx_LO_SUM (Pmode, reg, x);
8858 && GET_CODE (x) == SYMBOL_REF
8859 && constant_pool_expr_p (x)
8860 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8861 return create_TOC_reference (x, NULL_RTX);
8866 /* Debug version of rs6000_legitimize_address. */
8868 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8874 ret = rs6000_legitimize_address (x, oldx, mode);
8875 insns = get_insns ();
8881 "\nrs6000_legitimize_address: mode %s, old code %s, "
8882 "new code %s, modified\n",
8883 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8884 GET_RTX_NAME (GET_CODE (ret)));
8886 fprintf (stderr, "Original address:\n");
8889 fprintf (stderr, "oldx:\n");
8892 fprintf (stderr, "New address:\n");
8897 fprintf (stderr, "Insns added:\n");
8898 debug_rtx_list (insns, 20);
8904 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8905 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8916 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8917 We need to emit DTP-relative relocations. */
8919 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8921 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8926 fputs ("\t.long\t", file);
8929 fputs (DOUBLE_INT_ASM_OP, file);
8934 output_addr_const (file, x);
8936 fputs ("@dtprel+0x8000", file);
8937 else if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF)
8939 switch (SYMBOL_REF_TLS_MODEL (x))
8943 case TLS_MODEL_LOCAL_EXEC:
8944 fputs ("@le", file);
8946 case TLS_MODEL_INITIAL_EXEC:
8947 fputs ("@ie", file);
8949 case TLS_MODEL_GLOBAL_DYNAMIC:
8950 case TLS_MODEL_LOCAL_DYNAMIC:
8959 /* Return true if X is a symbol that refers to real (rather than emulated)
8963 rs6000_real_tls_symbol_ref_p (rtx x)
8965 return (GET_CODE (x) == SYMBOL_REF
8966 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8969 /* In the name of slightly smaller debug output, and to cater to
8970 general assembler lossage, recognize various UNSPEC sequences
8971 and turn them back into a direct symbol reference. */
8974 rs6000_delegitimize_address (rtx orig_x)
8978 orig_x = delegitimize_mem_from_attrs (orig_x);
8984 if (TARGET_CMODEL != CMODEL_SMALL
8985 && GET_CODE (y) == LO_SUM)
8989 if (GET_CODE (y) == PLUS
8990 && GET_MODE (y) == Pmode
8991 && CONST_INT_P (XEXP (y, 1)))
8993 offset = XEXP (y, 1);
8997 if (GET_CODE (y) == UNSPEC
8998 && XINT (y, 1) == UNSPEC_TOCREL)
9000 y = XVECEXP (y, 0, 0);
9003 /* Do not associate thread-local symbols with the original
9004 constant pool symbol. */
9006 && GET_CODE (y) == SYMBOL_REF
9007 && CONSTANT_POOL_ADDRESS_P (y)
9008 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
9012 if (offset != NULL_RTX)
9013 y = gen_rtx_PLUS (Pmode, y, offset);
9014 if (!MEM_P (orig_x))
9017 return replace_equiv_address_nv (orig_x, y);
9021 && GET_CODE (orig_x) == LO_SUM
9022 && GET_CODE (XEXP (orig_x, 1)) == CONST)
9024 y = XEXP (XEXP (orig_x, 1), 0);
9025 if (GET_CODE (y) == UNSPEC
9026 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
9027 return XVECEXP (y, 0, 0);
9033 /* Return true if X shouldn't be emitted into the debug info.
9034 The linker doesn't like .toc section references from
9035 .debug_* sections, so reject .toc section symbols. */
9038 rs6000_const_not_ok_for_debug_p (rtx x)
9040 if (GET_CODE (x) == UNSPEC)
9042 if (GET_CODE (x) == SYMBOL_REF
9043 && CONSTANT_POOL_ADDRESS_P (x))
9045 rtx c = get_pool_constant (x);
9046 machine_mode cmode = get_pool_mode (x);
9047 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
9055 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
9058 rs6000_legitimate_combined_insn (rtx_insn *insn)
9060 int icode = INSN_CODE (insn);
9062 /* Reject creating doloop insns. Combine should not be allowed
9063 to create these for a number of reasons:
9064 1) In a nested loop, if combine creates one of these in an
9065 outer loop and the register allocator happens to allocate ctr
9066 to the outer loop insn, then the inner loop can't use ctr.
9067 Inner loops ought to be more highly optimized.
9068 2) Combine often wants to create one of these from what was
9069 originally a three insn sequence, first combining the three
9070 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
9071 allocated ctr, the splitter takes use back to the three insn
9072 sequence. It's better to stop combine at the two insn
9074 3) Faced with not being able to allocate ctr for ctrsi/crtdi
9075 insns, the register allocator sometimes uses floating point
9076 or vector registers for the pseudo. Since ctrsi/ctrdi is a
9077 jump insn and output reloads are not implemented for jumps,
9078 the ctrsi/ctrdi splitters need to handle all possible cases.
9079 That's a pain, and it gets to be seriously difficult when a
9080 splitter that runs after reload needs memory to transfer from
9081 a gpr to fpr. See PR70098 and PR71763 which are not fixed
9082 for the difficult case. It's better to not create problems
9083 in the first place. */
9084 if (icode != CODE_FOR_nothing
9085 && (icode == CODE_FOR_bdz_si
9086 || icode == CODE_FOR_bdz_di
9087 || icode == CODE_FOR_bdnz_si
9088 || icode == CODE_FOR_bdnz_di
9089 || icode == CODE_FOR_bdztf_si
9090 || icode == CODE_FOR_bdztf_di
9091 || icode == CODE_FOR_bdnztf_si
9092 || icode == CODE_FOR_bdnztf_di))
9098 /* Construct the SYMBOL_REF for the tls_get_addr function. */
9100 static GTY(()) rtx rs6000_tls_symbol;
9102 rs6000_tls_get_addr (void)
9104 if (!rs6000_tls_symbol)
9105 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
9107 return rs6000_tls_symbol;
9110 /* Construct the SYMBOL_REF for TLS GOT references. */
9112 static GTY(()) rtx rs6000_got_symbol;
9114 rs6000_got_sym (void)
9116 if (!rs6000_got_symbol)
9118 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
9119 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
9120 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
9123 return rs6000_got_symbol;
9126 /* AIX Thread-Local Address support. */
9129 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
9131 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
9135 name = XSTR (addr, 0);
9136 /* Append TLS CSECT qualifier, unless the symbol already is qualified
9137 or the symbol will be in TLS private data section. */
9138 if (name[strlen (name) - 1] != ']'
9139 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
9140 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
9142 tlsname = XALLOCAVEC (char, strlen (name) + 4);
9143 strcpy (tlsname, name);
9145 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
9146 tlsaddr = copy_rtx (addr);
9147 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
9152 /* Place addr into TOC constant pool. */
9153 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
9155 /* Output the TOC entry and create the MEM referencing the value. */
9156 if (constant_pool_expr_p (XEXP (sym, 0))
9157 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
9159 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
9160 mem = gen_const_mem (Pmode, tocref);
9161 set_mem_alias_set (mem, get_TOC_alias_set ());
9166 /* Use global-dynamic for local-dynamic. */
9167 if (model == TLS_MODEL_GLOBAL_DYNAMIC
9168 || model == TLS_MODEL_LOCAL_DYNAMIC)
9170 /* Create new TOC reference for @m symbol. */
9171 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
9172 tlsname = XALLOCAVEC (char, strlen (name) + 1);
9173 strcpy (tlsname, "*LCM");
9174 strcat (tlsname, name + 3);
9175 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
9176 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
9177 tocref = create_TOC_reference (modaddr, NULL_RTX);
9178 rtx modmem = gen_const_mem (Pmode, tocref);
9179 set_mem_alias_set (modmem, get_TOC_alias_set ());
9181 rtx modreg = gen_reg_rtx (Pmode);
9182 emit_insn (gen_rtx_SET (modreg, modmem));
9184 tmpreg = gen_reg_rtx (Pmode);
9185 emit_insn (gen_rtx_SET (tmpreg, mem));
9187 dest = gen_reg_rtx (Pmode);
9189 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
9191 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
9194 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
9195 else if (TARGET_32BIT)
9197 tlsreg = gen_reg_rtx (SImode);
9198 emit_insn (gen_tls_get_tpointer (tlsreg));
9201 tlsreg = gen_rtx_REG (DImode, 13);
9203 /* Load the TOC value into temporary register. */
9204 tmpreg = gen_reg_rtx (Pmode);
9205 emit_insn (gen_rtx_SET (tmpreg, mem));
9206 set_unique_reg_note (get_last_insn (), REG_EQUAL,
9207 gen_rtx_MINUS (Pmode, addr, tlsreg));
9209 /* Add TOC symbol value to TLS pointer. */
9210 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
9215 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
9216 this (thread-local) address. */
9219 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
9224 return rs6000_legitimize_tls_address_aix (addr, model);
9226 dest = gen_reg_rtx (Pmode);
9227 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
9233 tlsreg = gen_rtx_REG (Pmode, 13);
9234 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
9238 tlsreg = gen_rtx_REG (Pmode, 2);
9239 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
9243 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
9247 tmp = gen_reg_rtx (Pmode);
9250 tlsreg = gen_rtx_REG (Pmode, 13);
9251 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
9255 tlsreg = gen_rtx_REG (Pmode, 2);
9256 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
9260 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
9262 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
9267 rtx r3, got, tga, tmp1, tmp2, call_insn;
9269 /* We currently use relocations like @got@tlsgd for tls, which
9270 means the linker will handle allocation of tls entries, placing
9271 them in the .got section. So use a pointer to the .got section,
9272 not one to secondary TOC sections used by 64-bit -mminimal-toc,
9273 or to secondary GOT sections used by 32-bit -fPIC. */
9275 got = gen_rtx_REG (Pmode, 2);
9279 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9282 rtx gsym = rs6000_got_sym ();
9283 got = gen_reg_rtx (Pmode);
9285 rs6000_emit_move (got, gsym, Pmode);
9290 tmp1 = gen_reg_rtx (Pmode);
9291 tmp2 = gen_reg_rtx (Pmode);
9292 mem = gen_const_mem (Pmode, tmp1);
9293 lab = gen_label_rtx ();
9294 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
9295 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
9296 if (TARGET_LINK_STACK)
9297 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
9298 emit_move_insn (tmp2, mem);
9299 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
9300 set_unique_reg_note (last, REG_EQUAL, gsym);
9305 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
9307 tga = rs6000_tls_get_addr ();
9308 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
9311 r3 = gen_rtx_REG (Pmode, 3);
9312 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9315 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
9317 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
9319 else if (DEFAULT_ABI == ABI_V4)
9320 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
9323 call_insn = last_call_insn ();
9324 PATTERN (call_insn) = insn;
9325 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9326 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9327 pic_offset_table_rtx);
9329 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
9331 tga = rs6000_tls_get_addr ();
9332 tmp1 = gen_reg_rtx (Pmode);
9333 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
9336 r3 = gen_rtx_REG (Pmode, 3);
9337 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9340 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
9342 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
9344 else if (DEFAULT_ABI == ABI_V4)
9345 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
9348 call_insn = last_call_insn ();
9349 PATTERN (call_insn) = insn;
9350 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
9351 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
9352 pic_offset_table_rtx);
9354 if (rs6000_tls_size == 16)
9357 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
9359 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
9361 else if (rs6000_tls_size == 32)
9363 tmp2 = gen_reg_rtx (Pmode);
9365 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
9367 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
9370 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
9372 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
9376 tmp2 = gen_reg_rtx (Pmode);
9378 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
9380 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
9382 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
9388 /* IE, or 64-bit offset LE. */
9389 tmp2 = gen_reg_rtx (Pmode);
9391 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
9393 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
9396 insn = gen_tls_tls_64 (dest, tmp2, addr);
9398 insn = gen_tls_tls_32 (dest, tmp2, addr);
9406 /* Only create the global variable for the stack protect guard if we are using
9407 the global flavor of that guard. */
9409 rs6000_init_stack_protect_guard (void)
9411 if (rs6000_stack_protector_guard == SSP_GLOBAL)
9412 return default_stack_protect_guard ();
9417 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
9420 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
9422 if (GET_CODE (x) == HIGH
9423 && GET_CODE (XEXP (x, 0)) == UNSPEC)
9426 /* A TLS symbol in the TOC cannot contain a sum. */
9427 if (GET_CODE (x) == CONST
9428 && GET_CODE (XEXP (x, 0)) == PLUS
9429 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
9430 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
9433 /* Do not place an ELF TLS symbol in the constant pool. */
9434 return TARGET_ELF && tls_referenced_p (x);
9437 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
9438 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
9439 can be addressed relative to the toc pointer. */
9442 use_toc_relative_ref (rtx sym, machine_mode mode)
9444 return ((constant_pool_expr_p (sym)
9445 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
9446 get_pool_mode (sym)))
9447 || (TARGET_CMODEL == CMODEL_MEDIUM
9448 && SYMBOL_REF_LOCAL_P (sym)
9449 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
9452 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
9453 replace the input X, or the original X if no replacement is called for.
9454 The output parameter *WIN is 1 if the calling macro should goto WIN,
9457 For RS/6000, we wish to handle large displacements off a base
9458 register by splitting the addend across an addiu/addis and the mem insn.
9459 This cuts number of extra insns needed from 3 to 1.
9461 On Darwin, we use this to generate code for floating point constants.
9462 A movsf_low is generated so we wind up with 2 instructions rather than 3.
9463 The Darwin code is inside #if TARGET_MACHO because only then are the
9464 machopic_* functions defined. */
9466 rs6000_legitimize_reload_address (rtx x, machine_mode mode,
9467 int opnum, int type,
9468 int ind_levels ATTRIBUTE_UNUSED, int *win)
9470 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9471 bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
9473 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
9474 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
9477 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
9478 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)
9479 || (mode == SFmode && recog_data.operand_mode[0] == V4SFmode
9480 && TARGET_P9_VECTOR)
9481 || (mode == SImode && recog_data.operand_mode[0] == V4SImode
9482 && TARGET_P9_VECTOR)))
9483 reg_offset_p = false;
9485 /* We must recognize output that we have already generated ourselves. */
9486 if (GET_CODE (x) == PLUS
9487 && GET_CODE (XEXP (x, 0)) == PLUS
9488 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9489 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9490 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9492 if (TARGET_DEBUG_ADDR)
9494 fprintf (stderr, "\nlegitimize_reload_address push_reload #1:\n");
9497 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9498 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9499 opnum, (enum reload_type) type);
9504 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
9505 if (GET_CODE (x) == LO_SUM
9506 && GET_CODE (XEXP (x, 0)) == HIGH)
9508 if (TARGET_DEBUG_ADDR)
9510 fprintf (stderr, "\nlegitimize_reload_address push_reload #2:\n");
9513 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9514 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9515 opnum, (enum reload_type) type);
9521 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
9522 && GET_CODE (x) == LO_SUM
9523 && GET_CODE (XEXP (x, 0)) == PLUS
9524 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
9525 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
9526 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
9527 && machopic_operand_p (XEXP (x, 1)))
9529 /* Result of previous invocation of this function on Darwin
9530 floating point constant. */
9531 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9532 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9533 opnum, (enum reload_type) type);
9539 if (TARGET_CMODEL != CMODEL_SMALL
9542 && small_toc_ref (x, VOIDmode))
9544 rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
9545 x = gen_rtx_LO_SUM (Pmode, hi, x);
9546 if (TARGET_DEBUG_ADDR)
9548 fprintf (stderr, "\nlegitimize_reload_address push_reload #3:\n");
9551 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9552 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9553 opnum, (enum reload_type) type);
9558 if (GET_CODE (x) == PLUS
9559 && REG_P (XEXP (x, 0))
9560 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
9561 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
9562 && CONST_INT_P (XEXP (x, 1))
9564 && !PAIRED_VECTOR_MODE (mode)
9565 && (quad_offset_p || !VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
9567 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
9568 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
9570 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
9572 /* Check for 32-bit overflow or quad addresses with one of the
9573 four least significant bits set. */
9574 if (high + low != val
9575 || (quad_offset_p && (low & 0xf)))
9581 /* Reload the high part into a base reg; leave the low part
9582 in the mem directly. */
9584 x = gen_rtx_PLUS (GET_MODE (x),
9585 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
9589 if (TARGET_DEBUG_ADDR)
9591 fprintf (stderr, "\nlegitimize_reload_address push_reload #4:\n");
9594 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9595 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
9596 opnum, (enum reload_type) type);
9601 if (GET_CODE (x) == SYMBOL_REF
9604 && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
9605 && !PAIRED_VECTOR_MODE (mode)
9607 && DEFAULT_ABI == ABI_DARWIN
9608 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
9609 && machopic_symbol_defined_p (x)
9611 && DEFAULT_ABI == ABI_V4
9614 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
9615 The same goes for DImode without 64-bit gprs and DFmode and DDmode
9617 ??? Assume floating point reg based on mode? This assumption is
9618 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
9619 where reload ends up doing a DFmode load of a constant from
9620 mem using two gprs. Unfortunately, at this point reload
9621 hasn't yet selected regs so poking around in reload data
9622 won't help and even if we could figure out the regs reliably,
9623 we'd still want to allow this transformation when the mem is
9624 naturally aligned. Since we say the address is good here, we
9625 can't disable offsets from LO_SUMs in mem_operand_gpr.
9626 FIXME: Allow offset from lo_sum for other modes too, when
9627 mem is sufficiently aligned.
9629 Also disallow this if the type can go in VMX/Altivec registers, since
9630 those registers do not have d-form (reg+offset) address modes. */
9631 && !reg_addr[mode].scalar_in_vmx_p
9636 && (mode != TImode || !TARGET_VSX)
9638 && (mode != DImode || TARGET_POWERPC64)
9639 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
9640 || (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)))
9645 rtx offset = machopic_gen_offset (x);
9646 x = gen_rtx_LO_SUM (GET_MODE (x),
9647 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
9648 gen_rtx_HIGH (Pmode, offset)), offset);
9652 x = gen_rtx_LO_SUM (GET_MODE (x),
9653 gen_rtx_HIGH (Pmode, x), x);
9655 if (TARGET_DEBUG_ADDR)
9657 fprintf (stderr, "\nlegitimize_reload_address push_reload #5:\n");
9660 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9661 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9662 opnum, (enum reload_type) type);
9667 /* Reload an offset address wrapped by an AND that represents the
9668 masking of the lower bits. Strip the outer AND and let reload
9669 convert the offset address into an indirect address. For VSX,
9670 force reload to create the address with an AND in a separate
9671 register, because we can't guarantee an altivec register will
9673 if (VECTOR_MEM_ALTIVEC_P (mode)
9674 && GET_CODE (x) == AND
9675 && GET_CODE (XEXP (x, 0)) == PLUS
9676 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
9677 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
9678 && GET_CODE (XEXP (x, 1)) == CONST_INT
9679 && INTVAL (XEXP (x, 1)) == -16)
9689 && GET_CODE (x) == SYMBOL_REF
9690 && use_toc_relative_ref (x, mode))
9692 x = create_TOC_reference (x, NULL_RTX);
9693 if (TARGET_CMODEL != CMODEL_SMALL)
9695 if (TARGET_DEBUG_ADDR)
9697 fprintf (stderr, "\nlegitimize_reload_address push_reload #6:\n");
9700 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
9701 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
9702 opnum, (enum reload_type) type);
9711 /* Debug version of rs6000_legitimize_reload_address. */
9713 rs6000_debug_legitimize_reload_address (rtx x, machine_mode mode,
9714 int opnum, int type,
9715 int ind_levels, int *win)
9717 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
9720 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9721 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9722 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
9726 fprintf (stderr, "Same address returned\n");
9728 fprintf (stderr, "NULL returned\n");
9731 fprintf (stderr, "New address:\n");
9738 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9739 that is a valid memory address for an instruction.
9740 The MODE argument is the machine mode for the MEM expression
9741 that wants to use this address.
9743 On the RS/6000, there are four valid address: a SYMBOL_REF that
9744 refers to a constant pool entry of an address (or the sum of it
9745 plus a constant), a short (16-bit signed) constant plus a register,
9746 the sum of two registers, or a register indirect, possibly with an
9747 auto-increment. For DFmode, DDmode and DImode with a constant plus
9748 register, we must ensure that both words are addressable or PowerPC64
9749 with offset word aligned.
9751 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9752 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9753 because adjacent memory cells are accessed by adding word-sized offsets
9754 during assembly output. */
9756 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
9758 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
9759 bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
9761 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9762 if (VECTOR_MEM_ALTIVEC_P (mode)
9763 && GET_CODE (x) == AND
9764 && GET_CODE (XEXP (x, 1)) == CONST_INT
9765 && INTVAL (XEXP (x, 1)) == -16)
9768 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
9770 if (legitimate_indirect_address_p (x, reg_ok_strict))
9773 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
9774 && mode_supports_pre_incdec_p (mode)
9775 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
9777 /* Handle restricted vector d-form offsets in ISA 3.0. */
9780 if (quad_address_p (x, mode, reg_ok_strict))
9783 else if (virtual_stack_registers_memory_p (x))
9786 else if (reg_offset_p)
9788 if (legitimate_small_data_p (mode, x))
9790 if (legitimate_constant_pool_address_p (x, mode,
9791 reg_ok_strict || lra_in_progress))
9793 if (reg_addr[mode].fused_toc && GET_CODE (x) == UNSPEC
9794 && XINT (x, 1) == UNSPEC_FUSION_ADDIS)
9798 /* For TImode, if we have TImode in VSX registers, only allow register
9799 indirect addresses. This will allow the values to go in either GPRs
9800 or VSX registers without reloading. The vector types would tend to
9801 go into VSX registers, so we allow REG+REG, while TImode seems
9802 somewhat split, in that some uses are GPR based, and some VSX based. */
9803 /* FIXME: We could loosen this by changing the following to
9804 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
9805 but currently we cannot allow REG+REG addressing for TImode. See
9806 PR72827 for complete details on how this ends up hoodwinking DSE. */
9807 if (mode == TImode && TARGET_VSX)
9809 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9812 && GET_CODE (x) == PLUS
9813 && GET_CODE (XEXP (x, 0)) == REG
9814 && (XEXP (x, 0) == virtual_stack_vars_rtx
9815 || XEXP (x, 0) == arg_pointer_rtx)
9816 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9818 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
9820 if (!FLOAT128_2REG_P (mode)
9821 && ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
9823 || (mode != DFmode && mode != DDmode))
9824 && (TARGET_POWERPC64 || mode != DImode)
9825 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
9827 && !avoiding_indexed_address_p (mode)
9828 && legitimate_indexed_address_p (x, reg_ok_strict))
9830 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
9831 && mode_supports_pre_modify_p (mode)
9832 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
9833 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
9834 reg_ok_strict, false)
9835 || (!avoiding_indexed_address_p (mode)
9836 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
9837 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
9839 if (reg_offset_p && !quad_offset_p
9840 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
9845 /* Debug version of rs6000_legitimate_address_p. */
9847 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
9850 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
9852 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9853 "strict = %d, reload = %s, code = %s\n",
9854 ret ? "true" : "false",
9855 GET_MODE_NAME (mode),
9857 (reload_completed ? "after" : "before"),
9858 GET_RTX_NAME (GET_CODE (x)));
9864 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9867 rs6000_mode_dependent_address_p (const_rtx addr,
9868 addr_space_t as ATTRIBUTE_UNUSED)
9870 return rs6000_mode_dependent_address_ptr (addr);
9873 /* Go to LABEL if ADDR (a legitimate address expression)
9874 has an effect that depends on the machine mode it is used for.
9876 On the RS/6000 this is true of all integral offsets (since AltiVec
9877 and VSX modes don't allow them) or is a pre-increment or decrement.
9879 ??? Except that due to conceptual problems in offsettable_address_p
9880 we can't really report the problems of integral offsets. So leave
9881 this assuming that the adjustable offset must be valid for the
9882 sub-words of a TFmode operand, which is what we had before. */
9885 rs6000_mode_dependent_address (const_rtx addr)
9887 switch (GET_CODE (addr))
9890 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9891 is considered a legitimate address before reload, so there
9892 are no offset restrictions in that case. Note that this
9893 condition is safe in strict mode because any address involving
9894 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9895 been rejected as illegitimate. */
9896 if (XEXP (addr, 0) != virtual_stack_vars_rtx
9897 && XEXP (addr, 0) != arg_pointer_rtx
9898 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
9900 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
9901 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
9906 /* Anything in the constant pool is sufficiently aligned that
9907 all bytes have the same high part address. */
9908 return !legitimate_constant_pool_address_p (addr, QImode, false);
9910 /* Auto-increment cases are now treated generically in recog.c. */
9912 return TARGET_UPDATE;
9914 /* AND is only allowed in Altivec loads. */
9925 /* Debug version of rs6000_mode_dependent_address. */
9927 rs6000_debug_mode_dependent_address (const_rtx addr)
9929 bool ret = rs6000_mode_dependent_address (addr);
9931 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9932 ret ? "true" : "false");
9938 /* Implement FIND_BASE_TERM. */
9941 rs6000_find_base_term (rtx op)
9946 if (GET_CODE (base) == CONST)
9947 base = XEXP (base, 0);
9948 if (GET_CODE (base) == PLUS)
9949 base = XEXP (base, 0);
9950 if (GET_CODE (base) == UNSPEC)
9951 switch (XINT (base, 1))
9954 case UNSPEC_MACHOPIC_OFFSET:
9955 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9956 for aliasing purposes. */
9957 return XVECEXP (base, 0, 0);
9963 /* More elaborate version of recog's offsettable_memref_p predicate
9964 that works around the ??? note of rs6000_mode_dependent_address.
9965 In particular it accepts
9967 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9969 in 32-bit mode, that the recog predicate rejects. */
9972 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode)
9979 /* First mimic offsettable_memref_p. */
9980 if (offsettable_address_p (true, GET_MODE (op), XEXP (op, 0)))
9983 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9984 the latter predicate knows nothing about the mode of the memory
9985 reference and, therefore, assumes that it is the largest supported
9986 mode (TFmode). As a consequence, legitimate offsettable memory
9987 references are rejected. rs6000_legitimate_offset_address_p contains
9988 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9989 at least with a little bit of help here given that we know the
9990 actual registers used. */
9991 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9992 || GET_MODE_SIZE (reg_mode) == 4);
9993 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9997 /* Determine the reassociation width to be used in reassociate_bb.
9998 This takes into account how many parallel operations we
9999 can actually do of a given type, and also the latency.
10001 int add/sub 6/cycle
10003 vect add/sub/mul 2/cycle
10004 fp add/sub/mul 2/cycle
10009 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
10012 switch (rs6000_tune)
10014 case PROCESSOR_POWER8:
10015 case PROCESSOR_POWER9:
10016 if (DECIMAL_FLOAT_MODE_P (mode))
10018 if (VECTOR_MODE_P (mode))
10020 if (INTEGRAL_MODE_P (mode))
10021 return opc == MULT_EXPR ? 4 : 6;
10022 if (FLOAT_MODE_P (mode))
10031 /* Change register usage conditional on target flags. */
10033 rs6000_conditional_register_usage (void)
10037 if (TARGET_DEBUG_TARGET)
10038 fprintf (stderr, "rs6000_conditional_register_usage called\n");
10040 /* Set MQ register fixed (already call_used) so that it will not be
10042 fixed_regs[64] = 1;
10044 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
10046 fixed_regs[13] = call_used_regs[13]
10047 = call_really_used_regs[13] = 1;
10049 /* Conditionally disable FPRs. */
10050 if (TARGET_SOFT_FLOAT)
10051 for (i = 32; i < 64; i++)
10052 fixed_regs[i] = call_used_regs[i]
10053 = call_really_used_regs[i] = 1;
10055 /* The TOC register is not killed across calls in a way that is
10056 visible to the compiler. */
10057 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10058 call_really_used_regs[2] = 0;
10060 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
10061 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10063 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10064 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10065 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10066 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10068 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
10069 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10070 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10071 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10073 if (TARGET_TOC && TARGET_MINIMAL_TOC)
10074 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
10075 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10077 if (!TARGET_ALTIVEC && !TARGET_VSX)
10079 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10080 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
10081 call_really_used_regs[VRSAVE_REGNO] = 1;
10084 if (TARGET_ALTIVEC || TARGET_VSX)
10085 global_regs[VSCR_REGNO] = 1;
10087 if (TARGET_ALTIVEC_ABI)
10089 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
10090 call_used_regs[i] = call_really_used_regs[i] = 1;
10092 /* AIX reserves VR20:31 in non-extended ABI mode. */
10094 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
10095 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
10100 /* Output insns to set DEST equal to the constant SOURCE as a series of
10101 lis, ori and shl instructions and return TRUE. */
10104 rs6000_emit_set_const (rtx dest, rtx source)
10106 machine_mode mode = GET_MODE (dest);
10111 gcc_checking_assert (CONST_INT_P (source));
10112 c = INTVAL (source);
10117 emit_insn (gen_rtx_SET (dest, source));
10121 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
10123 emit_insn (gen_rtx_SET (copy_rtx (temp),
10124 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
10125 emit_insn (gen_rtx_SET (dest,
10126 gen_rtx_IOR (SImode, copy_rtx (temp),
10127 GEN_INT (c & 0xffff))));
10131 if (!TARGET_POWERPC64)
10135 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
10137 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
10139 emit_move_insn (hi, GEN_INT (c >> 32));
10140 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
10141 emit_move_insn (lo, GEN_INT (c));
10144 rs6000_emit_set_long_const (dest, c);
10148 gcc_unreachable ();
10151 insn = get_last_insn ();
10152 set = single_set (insn);
10153 if (! CONSTANT_P (SET_SRC (set)))
10154 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
10159 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
10160 Output insns to set DEST equal to the constant C as a series of
10161 lis, ori and shl instructions. */
10164 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
10167 HOST_WIDE_INT ud1, ud2, ud3, ud4;
10177 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
10178 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
10179 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
10181 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
10182 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
10184 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10186 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10187 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
10189 emit_move_insn (dest,
10190 gen_rtx_IOR (DImode, copy_rtx (temp),
10193 else if (ud3 == 0 && ud4 == 0)
10195 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10197 gcc_assert (ud2 & 0x8000);
10198 emit_move_insn (copy_rtx (temp),
10199 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
10201 emit_move_insn (copy_rtx (temp),
10202 gen_rtx_IOR (DImode, copy_rtx (temp),
10204 emit_move_insn (dest,
10205 gen_rtx_ZERO_EXTEND (DImode,
10206 gen_lowpart (SImode,
10207 copy_rtx (temp))));
10209 else if ((ud4 == 0xffff && (ud3 & 0x8000))
10210 || (ud4 == 0 && ! (ud3 & 0x8000)))
10212 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10214 emit_move_insn (copy_rtx (temp),
10215 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
10217 emit_move_insn (copy_rtx (temp),
10218 gen_rtx_IOR (DImode, copy_rtx (temp),
10220 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10221 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
10224 emit_move_insn (dest,
10225 gen_rtx_IOR (DImode, copy_rtx (temp),
10230 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
10232 emit_move_insn (copy_rtx (temp),
10233 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
10235 emit_move_insn (copy_rtx (temp),
10236 gen_rtx_IOR (DImode, copy_rtx (temp),
10239 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
10240 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
10243 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
10244 gen_rtx_IOR (DImode, copy_rtx (temp),
10245 GEN_INT (ud2 << 16)));
10247 emit_move_insn (dest,
10248 gen_rtx_IOR (DImode, copy_rtx (temp),
10253 /* Helper for the following. Get rid of [r+r] memory refs
10254 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
10257 rs6000_eliminate_indexed_memrefs (rtx operands[2])
10259 if (GET_CODE (operands[0]) == MEM
10260 && GET_CODE (XEXP (operands[0], 0)) != REG
10261 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
10262 GET_MODE (operands[0]), false))
10264 = replace_equiv_address (operands[0],
10265 copy_addr_to_reg (XEXP (operands[0], 0)));
10267 if (GET_CODE (operands[1]) == MEM
10268 && GET_CODE (XEXP (operands[1], 0)) != REG
10269 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
10270 GET_MODE (operands[1]), false))
10272 = replace_equiv_address (operands[1],
10273 copy_addr_to_reg (XEXP (operands[1], 0)));
10276 /* Generate a vector of constants to permute MODE for a little-endian
10277 storage operation by swapping the two halves of a vector. */
10279 rs6000_const_vec (machine_mode mode)
10307 v = rtvec_alloc (subparts);
10309 for (i = 0; i < subparts / 2; ++i)
10310 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
10311 for (i = subparts / 2; i < subparts; ++i)
10312 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
10317 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
10318 store operation. */
10320 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
10322 /* Scalar permutations are easier to express in integer modes rather than
10323 floating-point modes, so cast them here. We use V1TImode instead
10324 of TImode to ensure that the values don't go through GPRs. */
10325 if (FLOAT128_VECTOR_P (mode))
10327 dest = gen_lowpart (V1TImode, dest);
10328 source = gen_lowpart (V1TImode, source);
10332 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
10334 if (mode == TImode || mode == V1TImode)
10335 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
10339 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
10340 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
10344 /* Emit a little-endian load from vector memory location SOURCE to VSX
10345 register DEST in mode MODE. The load is done with two permuting
10346 insn's that represent an lxvd2x and xxpermdi. */
10348 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
10350 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
10352 if (mode == TImode || mode == V1TImode)
10355 dest = gen_lowpart (V2DImode, dest);
10356 source = adjust_address (source, V2DImode, 0);
10359 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
10360 rs6000_emit_le_vsx_permute (tmp, source, mode);
10361 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10364 /* Emit a little-endian store to vector memory location DEST from VSX
10365 register SOURCE in mode MODE. The store is done with two permuting
10366 insn's that represent an xxpermdi and an stxvd2x. */
10368 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
10370 /* This should never be called during or after LRA, because it does
10371 not re-permute the source register. It is intended only for use
10373 gcc_assert (!lra_in_progress && !reload_completed);
10375 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
10377 if (mode == TImode || mode == V1TImode)
10380 dest = adjust_address (dest, V2DImode, 0);
10381 source = gen_lowpart (V2DImode, source);
10384 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
10385 rs6000_emit_le_vsx_permute (tmp, source, mode);
10386 rs6000_emit_le_vsx_permute (dest, tmp, mode);
10389 /* Emit a sequence representing a little-endian VSX load or store,
10390 moving data from SOURCE to DEST in mode MODE. This is done
10391 separately from rs6000_emit_move to ensure it is called only
10392 during expand. LE VSX loads and stores introduced later are
10393 handled with a split. The expand-time RTL generation allows
10394 us to optimize away redundant pairs of register-permutes. */
10396 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
10398 gcc_assert (!BYTES_BIG_ENDIAN
10399 && VECTOR_MEM_VSX_P (mode)
10400 && !TARGET_P9_VECTOR
10401 && !gpr_or_gpr_p (dest, source)
10402 && (MEM_P (source) ^ MEM_P (dest)));
10404 if (MEM_P (source))
10406 gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);
10407 rs6000_emit_le_vsx_load (dest, source, mode);
10411 if (!REG_P (source))
10412 source = force_reg (mode, source);
10413 rs6000_emit_le_vsx_store (dest, source, mode);
10417 /* Return whether a SFmode or SImode move can be done without converting one
10418 mode to another. This arrises when we have:
10420 (SUBREG:SF (REG:SI ...))
10421 (SUBREG:SI (REG:SF ...))
10423 and one of the values is in a floating point/vector register, where SFmode
10424 scalars are stored in DFmode format. */
10427 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
10429 if (TARGET_ALLOW_SF_SUBREG)
10432 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
10435 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
10438 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
10439 if (SUBREG_P (dest))
10441 rtx dest_subreg = SUBREG_REG (dest);
10442 rtx src_subreg = SUBREG_REG (src);
10443 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
10450 /* Helper function to change moves with:
10452 (SUBREG:SF (REG:SI)) and
10453 (SUBREG:SI (REG:SF))
10455 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
10456 values are stored as DFmode values in the VSX registers. We need to convert
10457 the bits before we can use a direct move or operate on the bits in the
10458 vector register as an integer type.
10460 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
10463 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
10465 if (TARGET_DIRECT_MOVE_64BIT && !lra_in_progress && !reload_completed
10466 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
10467 && SUBREG_P (source) && sf_subreg_operand (source, mode))
10469 rtx inner_source = SUBREG_REG (source);
10470 machine_mode inner_mode = GET_MODE (inner_source);
10472 if (mode == SImode && inner_mode == SFmode)
10474 emit_insn (gen_movsi_from_sf (dest, inner_source));
10478 if (mode == SFmode && inner_mode == SImode)
10480 emit_insn (gen_movsf_from_si (dest, inner_source));
10488 /* Emit a move from SOURCE to DEST in mode MODE. */
10490 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
10493 operands[0] = dest;
10494 operands[1] = source;
10496 if (TARGET_DEBUG_ADDR)
10499 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
10500 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
10501 GET_MODE_NAME (mode),
10504 can_create_pseudo_p ());
10506 fprintf (stderr, "source:\n");
10507 debug_rtx (source);
10510 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
10511 if (CONST_WIDE_INT_P (operands[1])
10512 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10514 /* This should be fixed with the introduction of CONST_WIDE_INT. */
10515 gcc_unreachable ();
10518 #ifdef HAVE_AS_GNU_ATTRIBUTE
10519 /* If we use a long double type, set the flags in .gnu_attribute that say
10520 what the long double type is. This is to allow the linker's warning
10521 message for the wrong long double to be useful, even if the function does
10522 not do a call (for example, doing a 128-bit add on power9 if the long
10523 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
10524 used if they aren't the default long dobule type. */
10525 if (rs6000_gnu_attr && (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT))
10527 if (TARGET_LONG_DOUBLE_128 && (mode == TFmode || mode == TCmode))
10528 rs6000_passes_float = rs6000_passes_long_double = true;
10530 else if (!TARGET_LONG_DOUBLE_128 && (mode == DFmode || mode == DCmode))
10531 rs6000_passes_float = rs6000_passes_long_double = true;
10535 /* See if we need to special case SImode/SFmode SUBREG moves. */
10536 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
10537 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
10540 /* Check if GCC is setting up a block move that will end up using FP
10541 registers as temporaries. We must make sure this is acceptable. */
10542 if (GET_CODE (operands[0]) == MEM
10543 && GET_CODE (operands[1]) == MEM
10545 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
10546 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
10547 && ! (rs6000_slow_unaligned_access (SImode,
10548 (MEM_ALIGN (operands[0]) > 32
10549 ? 32 : MEM_ALIGN (operands[0])))
10550 || rs6000_slow_unaligned_access (SImode,
10551 (MEM_ALIGN (operands[1]) > 32
10552 ? 32 : MEM_ALIGN (operands[1]))))
10553 && ! MEM_VOLATILE_P (operands [0])
10554 && ! MEM_VOLATILE_P (operands [1]))
10556 emit_move_insn (adjust_address (operands[0], SImode, 0),
10557 adjust_address (operands[1], SImode, 0));
10558 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
10559 adjust_address (copy_rtx (operands[1]), SImode, 4));
10563 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
10564 && !gpc_reg_operand (operands[1], mode))
10565 operands[1] = force_reg (mode, operands[1]);
10567 /* Recognize the case where operand[1] is a reference to thread-local
10568 data and load its address to a register. */
10569 if (tls_referenced_p (operands[1]))
10571 enum tls_model model;
10572 rtx tmp = operands[1];
10575 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
10577 addend = XEXP (XEXP (tmp, 0), 1);
10578 tmp = XEXP (XEXP (tmp, 0), 0);
10581 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
10582 model = SYMBOL_REF_TLS_MODEL (tmp);
10583 gcc_assert (model != 0);
10585 tmp = rs6000_legitimize_tls_address (tmp, model);
10588 tmp = gen_rtx_PLUS (mode, tmp, addend);
10589 tmp = force_operand (tmp, operands[0]);
10594 /* 128-bit constant floating-point values on Darwin should really be loaded
10595 as two parts. However, this premature splitting is a problem when DFmode
10596 values can go into Altivec registers. */
10597 if (FLOAT128_IBM_P (mode) && !reg_addr[DFmode].scalar_in_vmx_p
10598 && GET_CODE (operands[1]) == CONST_DOUBLE)
10600 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
10601 simplify_gen_subreg (DFmode, operands[1], mode, 0),
10603 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
10604 GET_MODE_SIZE (DFmode)),
10605 simplify_gen_subreg (DFmode, operands[1], mode,
10606 GET_MODE_SIZE (DFmode)),
10611 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
10612 p1:SD) if p1 is not of floating point class and p0 is spilled as
10613 we can have no analogous movsd_store for this. */
10614 if (lra_in_progress && mode == DDmode
10615 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10616 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10617 && GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))
10618 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
10621 int regno = REGNO (SUBREG_REG (operands[1]));
10623 if (regno >= FIRST_PSEUDO_REGISTER)
10625 cl = reg_preferred_class (regno);
10626 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
10628 if (regno >= 0 && ! FP_REGNO_P (regno))
10631 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
10632 operands[1] = SUBREG_REG (operands[1]);
10635 if (lra_in_progress
10637 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
10638 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
10639 && (REG_P (operands[1])
10640 || (GET_CODE (operands[1]) == SUBREG
10641 && REG_P (SUBREG_REG (operands[1])))))
10643 int regno = REGNO (GET_CODE (operands[1]) == SUBREG
10644 ? SUBREG_REG (operands[1]) : operands[1]);
10647 if (regno >= FIRST_PSEUDO_REGISTER)
10649 cl = reg_preferred_class (regno);
10650 gcc_assert (cl != NO_REGS);
10651 regno = ira_class_hard_regs[cl][0];
10653 if (FP_REGNO_P (regno))
10655 if (GET_MODE (operands[0]) != DDmode)
10656 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
10657 emit_insn (gen_movsd_store (operands[0], operands[1]));
10659 else if (INT_REGNO_P (regno))
10660 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10665 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10666 p:DD)) if p0 is not of floating point class and p1 is spilled as
10667 we can have no analogous movsd_load for this. */
10668 if (lra_in_progress && mode == DDmode
10669 && GET_CODE (operands[0]) == SUBREG && REG_P (SUBREG_REG (operands[0]))
10670 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
10671 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10672 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10675 int regno = REGNO (SUBREG_REG (operands[0]));
10677 if (regno >= FIRST_PSEUDO_REGISTER)
10679 cl = reg_preferred_class (regno);
10680 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
10682 if (regno >= 0 && ! FP_REGNO_P (regno))
10685 operands[0] = SUBREG_REG (operands[0]);
10686 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
10689 if (lra_in_progress
10691 && (REG_P (operands[0])
10692 || (GET_CODE (operands[0]) == SUBREG
10693 && REG_P (SUBREG_REG (operands[0]))))
10694 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
10695 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
10697 int regno = REGNO (GET_CODE (operands[0]) == SUBREG
10698 ? SUBREG_REG (operands[0]) : operands[0]);
10701 if (regno >= FIRST_PSEUDO_REGISTER)
10703 cl = reg_preferred_class (regno);
10704 gcc_assert (cl != NO_REGS);
10705 regno = ira_class_hard_regs[cl][0];
10707 if (FP_REGNO_P (regno))
10709 if (GET_MODE (operands[1]) != DDmode)
10710 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
10711 emit_insn (gen_movsd_load (operands[0], operands[1]));
10713 else if (INT_REGNO_P (regno))
10714 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
10720 /* FIXME: In the long term, this switch statement should go away
10721 and be replaced by a sequence of tests based on things like
10727 if (CONSTANT_P (operands[1])
10728 && GET_CODE (operands[1]) != CONST_INT)
10729 operands[1] = force_const_mem (mode, operands[1]);
10736 if (FLOAT128_2REG_P (mode))
10737 rs6000_eliminate_indexed_memrefs (operands);
10744 if (CONSTANT_P (operands[1])
10745 && ! easy_fp_constant (operands[1], mode))
10746 operands[1] = force_const_mem (mode, operands[1]);
10758 if (CONSTANT_P (operands[1])
10759 && !easy_vector_constant (operands[1], mode))
10760 operands[1] = force_const_mem (mode, operands[1]);
10765 /* Use default pattern for address of ELF small data */
10768 && DEFAULT_ABI == ABI_V4
10769 && (GET_CODE (operands[1]) == SYMBOL_REF
10770 || GET_CODE (operands[1]) == CONST)
10771 && small_data_operand (operands[1], mode))
10773 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10777 if (DEFAULT_ABI == ABI_V4
10778 && mode == Pmode && mode == SImode
10779 && flag_pic == 1 && got_operand (operands[1], mode))
10781 emit_insn (gen_movsi_got (operands[0], operands[1]));
10785 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
10789 && CONSTANT_P (operands[1])
10790 && GET_CODE (operands[1]) != HIGH
10791 && GET_CODE (operands[1]) != CONST_INT)
10793 rtx target = (!can_create_pseudo_p ()
10795 : gen_reg_rtx (mode));
10797 /* If this is a function address on -mcall-aixdesc,
10798 convert it to the address of the descriptor. */
10799 if (DEFAULT_ABI == ABI_AIX
10800 && GET_CODE (operands[1]) == SYMBOL_REF
10801 && XSTR (operands[1], 0)[0] == '.')
10803 const char *name = XSTR (operands[1], 0);
10805 while (*name == '.')
10807 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
10808 CONSTANT_POOL_ADDRESS_P (new_ref)
10809 = CONSTANT_POOL_ADDRESS_P (operands[1]);
10810 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
10811 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
10812 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
10813 operands[1] = new_ref;
10816 if (DEFAULT_ABI == ABI_DARWIN)
10819 if (MACHO_DYNAMIC_NO_PIC_P)
10821 /* Take care of any required data indirection. */
10822 operands[1] = rs6000_machopic_legitimize_pic_address (
10823 operands[1], mode, operands[0]);
10824 if (operands[0] != operands[1])
10825 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10829 emit_insn (gen_macho_high (target, operands[1]));
10830 emit_insn (gen_macho_low (operands[0], target, operands[1]));
10834 emit_insn (gen_elf_high (target, operands[1]));
10835 emit_insn (gen_elf_low (operands[0], target, operands[1]));
10839 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10840 and we have put it in the TOC, we just need to make a TOC-relative
10841 reference to it. */
10843 && GET_CODE (operands[1]) == SYMBOL_REF
10844 && use_toc_relative_ref (operands[1], mode))
10845 operands[1] = create_TOC_reference (operands[1], operands[0]);
10846 else if (mode == Pmode
10847 && CONSTANT_P (operands[1])
10848 && GET_CODE (operands[1]) != HIGH
10849 && ((GET_CODE (operands[1]) != CONST_INT
10850 && ! easy_fp_constant (operands[1], mode))
10851 || (GET_CODE (operands[1]) == CONST_INT
10852 && (num_insns_constant (operands[1], mode)
10853 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
10854 || (GET_CODE (operands[0]) == REG
10855 && FP_REGNO_P (REGNO (operands[0]))))
10856 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
10857 && (TARGET_CMODEL == CMODEL_SMALL
10858 || can_create_pseudo_p ()
10859 || (REG_P (operands[0])
10860 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
10864 /* Darwin uses a special PIC legitimizer. */
10865 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
10868 rs6000_machopic_legitimize_pic_address (operands[1], mode,
10870 if (operands[0] != operands[1])
10871 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10876 /* If we are to limit the number of things we put in the TOC and
10877 this is a symbol plus a constant we can add in one insn,
10878 just put the symbol in the TOC and add the constant. */
10879 if (GET_CODE (operands[1]) == CONST
10880 && TARGET_NO_SUM_IN_TOC
10881 && GET_CODE (XEXP (operands[1], 0)) == PLUS
10882 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
10883 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
10884 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
10885 && ! side_effects_p (operands[0]))
10888 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
10889 rtx other = XEXP (XEXP (operands[1], 0), 1);
10891 sym = force_reg (mode, sym);
10892 emit_insn (gen_add3_insn (operands[0], sym, other));
10896 operands[1] = force_const_mem (mode, operands[1]);
10899 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
10900 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
10902 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
10904 operands[1] = gen_const_mem (mode, tocref);
10905 set_mem_alias_set (operands[1], get_TOC_alias_set ());
10911 if (!VECTOR_MEM_VSX_P (TImode))
10912 rs6000_eliminate_indexed_memrefs (operands);
10916 rs6000_eliminate_indexed_memrefs (operands);
10920 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10923 /* Above, we may have called force_const_mem which may have returned
10924 an invalid address. If we can, fix this up; otherwise, reload will
10925 have to deal with it. */
10926 if (GET_CODE (operands[1]) == MEM)
10927 operands[1] = validize_mem (operands[1]);
10929 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10932 /* Nonzero if we can use a floating-point register to pass this arg. */
10933 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10934 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10935 && (CUM)->fregno <= FP_ARG_MAX_REG \
10936 && TARGET_HARD_FLOAT)
10938 /* Nonzero if we can use an AltiVec register to pass this arg. */
10939 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10940 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10941 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10942 && TARGET_ALTIVEC_ABI \
10945 /* Walk down the type tree of TYPE counting consecutive base elements.
10946 If *MODEP is VOIDmode, then set it to the first valid floating point
10947 or vector type. If a non-floating point or vector type is found, or
10948 if a floating point or vector type that doesn't match a non-VOIDmode
10949 *MODEP is found, then return -1, otherwise return the count in the
10953 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10956 HOST_WIDE_INT size;
10958 switch (TREE_CODE (type))
10961 mode = TYPE_MODE (type);
10962 if (!SCALAR_FLOAT_MODE_P (mode))
10965 if (*modep == VOIDmode)
10968 if (*modep == mode)
10974 mode = TYPE_MODE (TREE_TYPE (type));
10975 if (!SCALAR_FLOAT_MODE_P (mode))
10978 if (*modep == VOIDmode)
10981 if (*modep == mode)
10987 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10990 /* Use V4SImode as representative of all 128-bit vector types. */
10991 size = int_size_in_bytes (type);
11001 if (*modep == VOIDmode)
11004 /* Vector modes are considered to be opaque: two vectors are
11005 equivalent for the purposes of being homogeneous aggregates
11006 if they are the same size. */
11007 if (*modep == mode)
11015 tree index = TYPE_DOMAIN (type);
11017 /* Can't handle incomplete types nor sizes that are not
11019 if (!COMPLETE_TYPE_P (type)
11020 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
11023 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
11026 || !TYPE_MAX_VALUE (index)
11027 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
11028 || !TYPE_MIN_VALUE (index)
11029 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
11033 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
11034 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
11036 /* There must be no padding. */
11037 if (wi::to_wide (TYPE_SIZE (type))
11038 != count * GET_MODE_BITSIZE (*modep))
11050 /* Can't handle incomplete types nor sizes that are not
11052 if (!COMPLETE_TYPE_P (type)
11053 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
11056 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
11058 if (TREE_CODE (field) != FIELD_DECL)
11061 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
11064 count += sub_count;
11067 /* There must be no padding. */
11068 if (wi::to_wide (TYPE_SIZE (type))
11069 != count * GET_MODE_BITSIZE (*modep))
11076 case QUAL_UNION_TYPE:
11078 /* These aren't very interesting except in a degenerate case. */
11083 /* Can't handle incomplete types nor sizes that are not
11085 if (!COMPLETE_TYPE_P (type)
11086 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
11089 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
11091 if (TREE_CODE (field) != FIELD_DECL)
11094 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
11097 count = count > sub_count ? count : sub_count;
11100 /* There must be no padding. */
11101 if (wi::to_wide (TYPE_SIZE (type))
11102 != count * GET_MODE_BITSIZE (*modep))
11115 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
11116 float or vector aggregate that shall be passed in FP/vector registers
11117 according to the ELFv2 ABI, return the homogeneous element mode in
11118 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
11120 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
11123 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
11124 machine_mode *elt_mode,
11127 /* Note that we do not accept complex types at the top level as
11128 homogeneous aggregates; these types are handled via the
11129 targetm.calls.split_complex_arg mechanism. Complex types
11130 can be elements of homogeneous aggregates, however. */
11131 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
11132 && AGGREGATE_TYPE_P (type))
11134 machine_mode field_mode = VOIDmode;
11135 int field_count = rs6000_aggregate_candidate (type, &field_mode);
11137 if (field_count > 0)
11139 int n_regs = (SCALAR_FLOAT_MODE_P (field_mode) ?
11140 (GET_MODE_SIZE (field_mode) + 7) >> 3 : 1);
11142 /* The ELFv2 ABI allows homogeneous aggregates to occupy
11143 up to AGGR_ARG_NUM_REG registers. */
11144 if (field_count * n_regs <= AGGR_ARG_NUM_REG)
11147 *elt_mode = field_mode;
11149 *n_elts = field_count;
11162 /* Return a nonzero value to say to return the function value in
11163 memory, just as large structures are always returned. TYPE will be
11164 the data type of the value, and FNTYPE will be the type of the
11165 function doing the returning, or @code{NULL} for libcalls.
11167 The AIX ABI for the RS/6000 specifies that all structures are
11168 returned in memory. The Darwin ABI does the same.
11170 For the Darwin 64 Bit ABI, a function result can be returned in
11171 registers or in memory, depending on the size of the return data
11172 type. If it is returned in registers, the value occupies the same
11173 registers as it would if it were the first and only function
11174 argument. Otherwise, the function places its result in memory at
11175 the location pointed to by GPR3.
11177 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
11178 but a draft put them in memory, and GCC used to implement the draft
11179 instead of the final standard. Therefore, aix_struct_return
11180 controls this instead of DEFAULT_ABI; V.4 targets needing backward
11181 compatibility can change DRAFT_V4_STRUCT_RET to override the
11182 default, and -m switches get the final word. See
11183 rs6000_option_override_internal for more details.
11185 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
11186 long double support is enabled. These values are returned in memory.
11188 int_size_in_bytes returns -1 for variable size objects, which go in
11189 memory always. The cast to unsigned makes -1 > 8. */
11192 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
11194 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
11196 && rs6000_darwin64_abi
11197 && TREE_CODE (type) == RECORD_TYPE
11198 && int_size_in_bytes (type) > 0)
11200 CUMULATIVE_ARGS valcum;
11204 valcum.fregno = FP_ARG_MIN_REG;
11205 valcum.vregno = ALTIVEC_ARG_MIN_REG;
11206 /* Do a trial code generation as if this were going to be passed
11207 as an argument; if any part goes in memory, we return NULL. */
11208 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
11211 /* Otherwise fall through to more conventional ABI rules. */
11214 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
11215 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
11219 /* The ELFv2 ABI returns aggregates up to 16B in registers */
11220 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
11221 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
11224 if (AGGREGATE_TYPE_P (type)
11225 && (aix_struct_return
11226 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
11229 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11230 modes only exist for GCC vector types if -maltivec. */
11231 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
11232 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
11235 /* Return synthetic vectors in memory. */
11236 if (TREE_CODE (type) == VECTOR_TYPE
11237 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
11239 static bool warned_for_return_big_vectors = false;
11240 if (!warned_for_return_big_vectors)
11242 warning (OPT_Wpsabi, "GCC vector returned by reference: "
11243 "non-standard ABI extension with no compatibility "
11245 warned_for_return_big_vectors = true;
11250 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
11251 && FLOAT128_IEEE_P (TYPE_MODE (type)))
11257 /* Specify whether values returned in registers should be at the most
11258 significant end of a register. We want aggregates returned by
11259 value to match the way aggregates are passed to functions. */
11262 rs6000_return_in_msb (const_tree valtype)
11264 return (DEFAULT_ABI == ABI_ELFv2
11265 && BYTES_BIG_ENDIAN
11266 && AGGREGATE_TYPE_P (valtype)
11267 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
11271 #ifdef HAVE_AS_GNU_ATTRIBUTE
11272 /* Return TRUE if a call to function FNDECL may be one that
11273 potentially affects the function calling ABI of the object file. */
11276 call_ABI_of_interest (tree fndecl)
11278 if (rs6000_gnu_attr && symtab->state == EXPANSION)
11280 struct cgraph_node *c_node;
11282 /* Libcalls are always interesting. */
11283 if (fndecl == NULL_TREE)
11286 /* Any call to an external function is interesting. */
11287 if (DECL_EXTERNAL (fndecl))
11290 /* Interesting functions that we are emitting in this object file. */
11291 c_node = cgraph_node::get (fndecl);
11292 c_node = c_node->ultimate_alias_target ();
11293 return !c_node->only_called_directly_p ();
11299 /* Initialize a variable CUM of type CUMULATIVE_ARGS
11300 for a call to a function whose data type is FNTYPE.
11301 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
11303 For incoming args we set the number of arguments in the prototype large
11304 so we never return a PARALLEL. */
11307 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
11308 rtx libname ATTRIBUTE_UNUSED, int incoming,
11309 int libcall, int n_named_args,
11310 tree fndecl ATTRIBUTE_UNUSED,
11311 machine_mode return_mode ATTRIBUTE_UNUSED)
11313 static CUMULATIVE_ARGS zero_cumulative;
11315 *cum = zero_cumulative;
11317 cum->fregno = FP_ARG_MIN_REG;
11318 cum->vregno = ALTIVEC_ARG_MIN_REG;
11319 cum->prototype = (fntype && prototype_p (fntype));
11320 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
11321 ? CALL_LIBCALL : CALL_NORMAL);
11322 cum->sysv_gregno = GP_ARG_MIN_REG;
11323 cum->stdarg = stdarg_p (fntype);
11324 cum->libcall = libcall;
11326 cum->nargs_prototype = 0;
11327 if (incoming || cum->prototype)
11328 cum->nargs_prototype = n_named_args;
11330 /* Check for a longcall attribute. */
11331 if ((!fntype && rs6000_default_long_calls)
11333 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
11334 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
11335 cum->call_cookie |= CALL_LONG;
11337 if (TARGET_DEBUG_ARG)
11339 fprintf (stderr, "\ninit_cumulative_args:");
11342 tree ret_type = TREE_TYPE (fntype);
11343 fprintf (stderr, " ret code = %s,",
11344 get_tree_code_name (TREE_CODE (ret_type)));
11347 if (cum->call_cookie & CALL_LONG)
11348 fprintf (stderr, " longcall,");
11350 fprintf (stderr, " proto = %d, nargs = %d\n",
11351 cum->prototype, cum->nargs_prototype);
11354 #ifdef HAVE_AS_GNU_ATTRIBUTE
11355 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
11357 cum->escapes = call_ABI_of_interest (fndecl);
11364 return_type = TREE_TYPE (fntype);
11365 return_mode = TYPE_MODE (return_type);
11368 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
11370 if (return_type != NULL)
11372 if (TREE_CODE (return_type) == RECORD_TYPE
11373 && TYPE_TRANSPARENT_AGGR (return_type))
11375 return_type = TREE_TYPE (first_field (return_type));
11376 return_mode = TYPE_MODE (return_type);
11378 if (AGGREGATE_TYPE_P (return_type)
11379 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
11381 rs6000_returns_struct = true;
11383 if (SCALAR_FLOAT_MODE_P (return_mode))
11385 rs6000_passes_float = true;
11386 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11387 && (FLOAT128_IBM_P (return_mode)
11388 || FLOAT128_IEEE_P (return_mode)
11389 || (return_type != NULL
11390 && (TYPE_MAIN_VARIANT (return_type)
11391 == long_double_type_node))))
11392 rs6000_passes_long_double = true;
11394 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
11395 || PAIRED_VECTOR_MODE (return_mode))
11396 rs6000_passes_vector = true;
11403 && TARGET_ALTIVEC_ABI
11404 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
11406 error ("cannot return value in vector register because"
11407 " altivec instructions are disabled, use %qs"
11408 " to enable them", "-maltivec");
11412 /* The mode the ABI uses for a word. This is not the same as word_mode
11413 for -m32 -mpowerpc64. This is used to implement various target hooks. */
11415 static scalar_int_mode
11416 rs6000_abi_word_mode (void)
11418 return TARGET_32BIT ? SImode : DImode;
11421 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
11423 rs6000_offload_options (void)
11426 return xstrdup ("-foffload-abi=lp64");
11428 return xstrdup ("-foffload-abi=ilp32");
11431 /* On rs6000, function arguments are promoted, as are function return
11434 static machine_mode
11435 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
11437 int *punsignedp ATTRIBUTE_UNUSED,
11440 PROMOTE_MODE (mode, *punsignedp, type);
11445 /* Return true if TYPE must be passed on the stack and not in registers. */
11448 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
11450 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
11451 return must_pass_in_stack_var_size (mode, type);
11453 return must_pass_in_stack_var_size_or_pad (mode, type);
11457 is_complex_IBM_long_double (machine_mode mode)
11459 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
11462 /* Whether ABI_V4 passes MODE args to a function in floating point
11466 abi_v4_pass_in_fpr (machine_mode mode)
11468 if (!TARGET_HARD_FLOAT)
11470 if (TARGET_SINGLE_FLOAT && mode == SFmode)
11472 if (TARGET_DOUBLE_FLOAT && mode == DFmode)
11474 /* ABI_V4 passes complex IBM long double in 8 gprs.
11475 Stupid, but we can't change the ABI now. */
11476 if (is_complex_IBM_long_double (mode))
11478 if (FLOAT128_2REG_P (mode))
11480 if (DECIMAL_FLOAT_MODE_P (mode))
11485 /* Implement TARGET_FUNCTION_ARG_PADDING.
11487 For the AIX ABI structs are always stored left shifted in their
11490 static pad_direction
11491 rs6000_function_arg_padding (machine_mode mode, const_tree type)
11493 #ifndef AGGREGATE_PADDING_FIXED
11494 #define AGGREGATE_PADDING_FIXED 0
11496 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
11497 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
11500 if (!AGGREGATE_PADDING_FIXED)
11502 /* GCC used to pass structures of the same size as integer types as
11503 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
11504 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
11505 passed padded downward, except that -mstrict-align further
11506 muddied the water in that multi-component structures of 2 and 4
11507 bytes in size were passed padded upward.
11509 The following arranges for best compatibility with previous
11510 versions of gcc, but removes the -mstrict-align dependency. */
11511 if (BYTES_BIG_ENDIAN)
11513 HOST_WIDE_INT size = 0;
11515 if (mode == BLKmode)
11517 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
11518 size = int_size_in_bytes (type);
11521 size = GET_MODE_SIZE (mode);
11523 if (size == 1 || size == 2 || size == 4)
11524 return PAD_DOWNWARD;
11529 if (AGGREGATES_PAD_UPWARD_ALWAYS)
11531 if (type != 0 && AGGREGATE_TYPE_P (type))
11535 /* Fall back to the default. */
11536 return default_function_arg_padding (mode, type);
11539 /* If defined, a C expression that gives the alignment boundary, in bits,
11540 of an argument with the specified mode and type. If it is not defined,
11541 PARM_BOUNDARY is used for all arguments.
11543 V.4 wants long longs and doubles to be double word aligned. Just
11544 testing the mode size is a boneheaded way to do this as it means
11545 that other types such as complex int are also double word aligned.
11546 However, we're stuck with this because changing the ABI might break
11547 existing library interfaces.
11549 Quadword align Altivec/VSX vectors.
11550 Quadword align large synthetic vector types. */
11552 static unsigned int
11553 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
11555 machine_mode elt_mode;
11558 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11560 if (DEFAULT_ABI == ABI_V4
11561 && (GET_MODE_SIZE (mode) == 8
11562 || (TARGET_HARD_FLOAT
11563 && !is_complex_IBM_long_double (mode)
11564 && FLOAT128_2REG_P (mode))))
11566 else if (FLOAT128_VECTOR_P (mode))
11568 else if (PAIRED_VECTOR_MODE (mode)
11569 || (type && TREE_CODE (type) == VECTOR_TYPE
11570 && int_size_in_bytes (type) >= 8
11571 && int_size_in_bytes (type) < 16))
11573 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11574 || (type && TREE_CODE (type) == VECTOR_TYPE
11575 && int_size_in_bytes (type) >= 16))
11578 /* Aggregate types that need > 8 byte alignment are quadword-aligned
11579 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
11580 -mcompat-align-parm is used. */
11581 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
11582 || DEFAULT_ABI == ABI_ELFv2)
11583 && type && TYPE_ALIGN (type) > 64)
11585 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
11586 or homogeneous float/vector aggregates here. We already handled
11587 vector aggregates above, but still need to check for float here. */
11588 bool aggregate_p = (AGGREGATE_TYPE_P (type)
11589 && !SCALAR_FLOAT_MODE_P (elt_mode));
11591 /* We used to check for BLKmode instead of the above aggregate type
11592 check. Warn when this results in any difference to the ABI. */
11593 if (aggregate_p != (mode == BLKmode))
11595 static bool warned;
11596 if (!warned && warn_psabi)
11599 inform (input_location,
11600 "the ABI of passing aggregates with %d-byte alignment"
11601 " has changed in GCC 5",
11602 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
11610 /* Similar for the Darwin64 ABI. Note that for historical reasons we
11611 implement the "aggregate type" check as a BLKmode check here; this
11612 means certain aggregate types are in fact not aligned. */
11613 if (TARGET_MACHO && rs6000_darwin64_abi
11615 && type && TYPE_ALIGN (type) > 64)
11618 return PARM_BOUNDARY;
11621 /* The offset in words to the start of the parameter save area. */
11623 static unsigned int
11624 rs6000_parm_offset (void)
11626 return (DEFAULT_ABI == ABI_V4 ? 2
11627 : DEFAULT_ABI == ABI_ELFv2 ? 4
11631 /* For a function parm of MODE and TYPE, return the starting word in
11632 the parameter area. NWORDS of the parameter area are already used. */
11634 static unsigned int
11635 rs6000_parm_start (machine_mode mode, const_tree type,
11636 unsigned int nwords)
11638 unsigned int align;
11640 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
11641 return nwords + (-(rs6000_parm_offset () + nwords) & align);
11644 /* Compute the size (in words) of a function argument. */
11646 static unsigned long
11647 rs6000_arg_size (machine_mode mode, const_tree type)
11649 unsigned long size;
11651 if (mode != BLKmode)
11652 size = GET_MODE_SIZE (mode);
11654 size = int_size_in_bytes (type);
11657 return (size + 3) >> 2;
11659 return (size + 7) >> 3;
11662 /* Use this to flush pending int fields. */
11665 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
11666 HOST_WIDE_INT bitpos, int final)
11668 unsigned int startbit, endbit;
11669 int intregs, intoffset;
11671 /* Handle the situations where a float is taking up the first half
11672 of the GPR, and the other half is empty (typically due to
11673 alignment restrictions). We can detect this by a 8-byte-aligned
11674 int field, or by seeing that this is the final flush for this
11675 argument. Count the word and continue on. */
11676 if (cum->floats_in_gpr == 1
11677 && (cum->intoffset % 64 == 0
11678 || (cum->intoffset == -1 && final)))
11681 cum->floats_in_gpr = 0;
11684 if (cum->intoffset == -1)
11687 intoffset = cum->intoffset;
11688 cum->intoffset = -1;
11689 cum->floats_in_gpr = 0;
11691 if (intoffset % BITS_PER_WORD != 0)
11693 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11694 if (!int_mode_for_size (bits, 0).exists ())
11696 /* We couldn't find an appropriate mode, which happens,
11697 e.g., in packed structs when there are 3 bytes to load.
11698 Back intoffset back to the beginning of the word in this
11700 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11704 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11705 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11706 intregs = (endbit - startbit) / BITS_PER_WORD;
11707 cum->words += intregs;
11708 /* words should be unsigned. */
11709 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
11711 int pad = (endbit/BITS_PER_WORD) - cum->words;
11716 /* The darwin64 ABI calls for us to recurse down through structs,
11717 looking for elements passed in registers. Unfortunately, we have
11718 to track int register count here also because of misalignments
11719 in powerpc alignment mode. */
11722 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
11724 HOST_WIDE_INT startbitpos)
11728 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11729 if (TREE_CODE (f) == FIELD_DECL)
11731 HOST_WIDE_INT bitpos = startbitpos;
11732 tree ftype = TREE_TYPE (f);
11734 if (ftype == error_mark_node)
11736 mode = TYPE_MODE (ftype);
11738 if (DECL_SIZE (f) != 0
11739 && tree_fits_uhwi_p (bit_position (f)))
11740 bitpos += int_bit_position (f);
11742 /* ??? FIXME: else assume zero offset. */
11744 if (TREE_CODE (ftype) == RECORD_TYPE)
11745 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
11746 else if (USE_FP_FOR_ARG_P (cum, mode))
11748 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
11749 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11750 cum->fregno += n_fpregs;
11751 /* Single-precision floats present a special problem for
11752 us, because they are smaller than an 8-byte GPR, and so
11753 the structure-packing rules combined with the standard
11754 varargs behavior mean that we want to pack float/float
11755 and float/int combinations into a single register's
11756 space. This is complicated by the arg advance flushing,
11757 which works on arbitrarily large groups of int-type
11759 if (mode == SFmode)
11761 if (cum->floats_in_gpr == 1)
11763 /* Two floats in a word; count the word and reset
11764 the float count. */
11766 cum->floats_in_gpr = 0;
11768 else if (bitpos % 64 == 0)
11770 /* A float at the beginning of an 8-byte word;
11771 count it and put off adjusting cum->words until
11772 we see if a arg advance flush is going to do it
11774 cum->floats_in_gpr++;
11778 /* The float is at the end of a word, preceded
11779 by integer fields, so the arg advance flush
11780 just above has already set cum->words and
11781 everything is taken care of. */
11785 cum->words += n_fpregs;
11787 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11789 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
11793 else if (cum->intoffset == -1)
11794 cum->intoffset = bitpos;
11798 /* Check for an item that needs to be considered specially under the darwin 64
11799 bit ABI. These are record types where the mode is BLK or the structure is
11800 8 bytes in size. */
11802 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
11804 return rs6000_darwin64_abi
11805 && ((mode == BLKmode
11806 && TREE_CODE (type) == RECORD_TYPE
11807 && int_size_in_bytes (type) > 0)
11808 || (type && TREE_CODE (type) == RECORD_TYPE
11809 && int_size_in_bytes (type) == 8)) ? 1 : 0;
11812 /* Update the data in CUM to advance over an argument
11813 of mode MODE and data type TYPE.
11814 (TYPE is null for libcalls where that information may not be available.)
11816 Note that for args passed by reference, function_arg will be called
11817 with MODE and TYPE set to that of the pointer to the arg, not the arg
11821 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
11822 const_tree type, bool named, int depth)
11824 machine_mode elt_mode;
11827 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11829 /* Only tick off an argument if we're not recursing. */
11831 cum->nargs_prototype--;
11833 #ifdef HAVE_AS_GNU_ATTRIBUTE
11834 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
11837 if (SCALAR_FLOAT_MODE_P (mode))
11839 rs6000_passes_float = true;
11840 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
11841 && (FLOAT128_IBM_P (mode)
11842 || FLOAT128_IEEE_P (mode)
11844 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
11845 rs6000_passes_long_double = true;
11847 if ((named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
11848 || (PAIRED_VECTOR_MODE (mode)
11850 && cum->sysv_gregno <= GP_ARG_MAX_REG))
11851 rs6000_passes_vector = true;
11855 if (TARGET_ALTIVEC_ABI
11856 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
11857 || (type && TREE_CODE (type) == VECTOR_TYPE
11858 && int_size_in_bytes (type) == 16)))
11860 bool stack = false;
11862 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11864 cum->vregno += n_elts;
11866 if (!TARGET_ALTIVEC)
11867 error ("cannot pass argument in vector register because"
11868 " altivec instructions are disabled, use %qs"
11869 " to enable them", "-maltivec");
11871 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11872 even if it is going to be passed in a vector register.
11873 Darwin does the same for variable-argument functions. */
11874 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11876 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
11886 /* Vector parameters must be 16-byte aligned. In 32-bit
11887 mode this means we need to take into account the offset
11888 to the parameter save area. In 64-bit mode, they just
11889 have to start on an even word, since the parameter save
11890 area is 16-byte aligned. */
11892 align = -(rs6000_parm_offset () + cum->words) & 3;
11894 align = cum->words & 1;
11895 cum->words += align + rs6000_arg_size (mode, type);
11897 if (TARGET_DEBUG_ARG)
11899 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11900 cum->words, align);
11901 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11902 cum->nargs_prototype, cum->prototype,
11903 GET_MODE_NAME (mode));
11907 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11909 int size = int_size_in_bytes (type);
11910 /* Variable sized types have size == -1 and are
11911 treated as if consisting entirely of ints.
11912 Pad to 16 byte boundary if needed. */
11913 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11914 && (cum->words % 2) != 0)
11916 /* For varargs, we can just go up by the size of the struct. */
11918 cum->words += (size + 7) / 8;
11921 /* It is tempting to say int register count just goes up by
11922 sizeof(type)/8, but this is wrong in a case such as
11923 { int; double; int; } [powerpc alignment]. We have to
11924 grovel through the fields for these too. */
11925 cum->intoffset = 0;
11926 cum->floats_in_gpr = 0;
11927 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11928 rs6000_darwin64_record_arg_advance_flush (cum,
11929 size * BITS_PER_UNIT, 1);
11931 if (TARGET_DEBUG_ARG)
11933 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11934 cum->words, TYPE_ALIGN (type), size);
11936 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11937 cum->nargs_prototype, cum->prototype,
11938 GET_MODE_NAME (mode));
11941 else if (DEFAULT_ABI == ABI_V4)
11943 if (abi_v4_pass_in_fpr (mode))
11945 /* _Decimal128 must use an even/odd register pair. This assumes
11946 that the register number is odd when fregno is odd. */
11947 if (mode == TDmode && (cum->fregno % 2) == 1)
11950 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11951 <= FP_ARG_V4_MAX_REG)
11952 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11955 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11956 if (mode == DFmode || FLOAT128_IBM_P (mode)
11957 || mode == DDmode || mode == TDmode)
11958 cum->words += cum->words & 1;
11959 cum->words += rs6000_arg_size (mode, type);
11964 int n_words = rs6000_arg_size (mode, type);
11965 int gregno = cum->sysv_gregno;
11967 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11968 As does any other 2 word item such as complex int due to a
11969 historical mistake. */
11971 gregno += (1 - gregno) & 1;
11973 /* Multi-reg args are not split between registers and stack. */
11974 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11976 /* Long long is aligned on the stack. So are other 2 word
11977 items such as complex int due to a historical mistake. */
11979 cum->words += cum->words & 1;
11980 cum->words += n_words;
11983 /* Note: continuing to accumulate gregno past when we've started
11984 spilling to the stack indicates the fact that we've started
11985 spilling to the stack to expand_builtin_saveregs. */
11986 cum->sysv_gregno = gregno + n_words;
11989 if (TARGET_DEBUG_ARG)
11991 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11992 cum->words, cum->fregno);
11993 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11994 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11995 fprintf (stderr, "mode = %4s, named = %d\n",
11996 GET_MODE_NAME (mode), named);
12001 int n_words = rs6000_arg_size (mode, type);
12002 int start_words = cum->words;
12003 int align_words = rs6000_parm_start (mode, type, start_words);
12005 cum->words = align_words + n_words;
12007 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
12009 /* _Decimal128 must be passed in an even/odd float register pair.
12010 This assumes that the register number is odd when fregno is
12012 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
12014 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
12017 if (TARGET_DEBUG_ARG)
12019 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
12020 cum->words, cum->fregno);
12021 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
12022 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
12023 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
12024 named, align_words - start_words, depth);
12030 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
12031 const_tree type, bool named)
12033 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
12037 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
12038 structure between cum->intoffset and bitpos to integer registers. */
12041 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
12042 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
12045 unsigned int regno;
12046 unsigned int startbit, endbit;
12047 int this_regno, intregs, intoffset;
12050 if (cum->intoffset == -1)
12053 intoffset = cum->intoffset;
12054 cum->intoffset = -1;
12056 /* If this is the trailing part of a word, try to only load that
12057 much into the register. Otherwise load the whole register. Note
12058 that in the latter case we may pick up unwanted bits. It's not a
12059 problem at the moment but may wish to revisit. */
12061 if (intoffset % BITS_PER_WORD != 0)
12063 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
12064 if (!int_mode_for_size (bits, 0).exists (&mode))
12066 /* We couldn't find an appropriate mode, which happens,
12067 e.g., in packed structs when there are 3 bytes to load.
12068 Back intoffset back to the beginning of the word in this
12070 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
12077 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
12078 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
12079 intregs = (endbit - startbit) / BITS_PER_WORD;
12080 this_regno = cum->words + intoffset / BITS_PER_WORD;
12082 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
12083 cum->use_stack = 1;
12085 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
12089 intoffset /= BITS_PER_UNIT;
12092 regno = GP_ARG_MIN_REG + this_regno;
12093 reg = gen_rtx_REG (mode, regno);
12095 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
12098 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
12102 while (intregs > 0);
12105 /* Recursive workhorse for the following. */
12108 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
12109 HOST_WIDE_INT startbitpos, rtx rvec[],
12114 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
12115 if (TREE_CODE (f) == FIELD_DECL)
12117 HOST_WIDE_INT bitpos = startbitpos;
12118 tree ftype = TREE_TYPE (f);
12120 if (ftype == error_mark_node)
12122 mode = TYPE_MODE (ftype);
12124 if (DECL_SIZE (f) != 0
12125 && tree_fits_uhwi_p (bit_position (f)))
12126 bitpos += int_bit_position (f);
12128 /* ??? FIXME: else assume zero offset. */
12130 if (TREE_CODE (ftype) == RECORD_TYPE)
12131 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
12132 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
12134 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
12138 case E_SCmode: mode = SFmode; break;
12139 case E_DCmode: mode = DFmode; break;
12140 case E_TCmode: mode = TFmode; break;
12144 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
12145 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
12147 gcc_assert (cum->fregno == FP_ARG_MAX_REG
12148 && (mode == TFmode || mode == TDmode));
12149 /* Long double or _Decimal128 split over regs and memory. */
12150 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
12154 = gen_rtx_EXPR_LIST (VOIDmode,
12155 gen_rtx_REG (mode, cum->fregno++),
12156 GEN_INT (bitpos / BITS_PER_UNIT));
12157 if (FLOAT128_2REG_P (mode))
12160 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
12162 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
12164 = gen_rtx_EXPR_LIST (VOIDmode,
12165 gen_rtx_REG (mode, cum->vregno++),
12166 GEN_INT (bitpos / BITS_PER_UNIT));
12168 else if (cum->intoffset == -1)
12169 cum->intoffset = bitpos;
12173 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
12174 the register(s) to be used for each field and subfield of a struct
12175 being passed by value, along with the offset of where the
12176 register's value may be found in the block. FP fields go in FP
12177 register, vector fields go in vector registers, and everything
12178 else goes in int registers, packed as in memory.
12180 This code is also used for function return values. RETVAL indicates
12181 whether this is the case.
12183 Much of this is taken from the SPARC V9 port, which has a similar
12184 calling convention. */
12187 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
12188 bool named, bool retval)
12190 rtx rvec[FIRST_PSEUDO_REGISTER];
12191 int k = 1, kbase = 1;
12192 HOST_WIDE_INT typesize = int_size_in_bytes (type);
12193 /* This is a copy; modifications are not visible to our caller. */
12194 CUMULATIVE_ARGS copy_cum = *orig_cum;
12195 CUMULATIVE_ARGS *cum = ©_cum;
12197 /* Pad to 16 byte boundary if needed. */
12198 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
12199 && (cum->words % 2) != 0)
12202 cum->intoffset = 0;
12203 cum->use_stack = 0;
12204 cum->named = named;
12206 /* Put entries into rvec[] for individual FP and vector fields, and
12207 for the chunks of memory that go in int regs. Note we start at
12208 element 1; 0 is reserved for an indication of using memory, and
12209 may or may not be filled in below. */
12210 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
12211 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
12213 /* If any part of the struct went on the stack put all of it there.
12214 This hack is because the generic code for
12215 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
12216 parts of the struct are not at the beginning. */
12217 if (cum->use_stack)
12220 return NULL_RTX; /* doesn't go in registers at all */
12222 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12224 if (k > 1 || cum->use_stack)
12225 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
12230 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
12233 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
12238 rtx rvec[GP_ARG_NUM_REG + 1];
12240 if (align_words >= GP_ARG_NUM_REG)
12243 n_units = rs6000_arg_size (mode, type);
12245 /* Optimize the simple case where the arg fits in one gpr, except in
12246 the case of BLKmode due to assign_parms assuming that registers are
12247 BITS_PER_WORD wide. */
12249 || (n_units == 1 && mode != BLKmode))
12250 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12253 if (align_words + n_units > GP_ARG_NUM_REG)
12254 /* Not all of the arg fits in gprs. Say that it goes in memory too,
12255 using a magic NULL_RTX component.
12256 This is not strictly correct. Only some of the arg belongs in
12257 memory, not all of it. However, the normal scheme using
12258 function_arg_partial_nregs can result in unusual subregs, eg.
12259 (subreg:SI (reg:DF) 4), which are not handled well. The code to
12260 store the whole arg to memory is often more efficient than code
12261 to store pieces, and we know that space is available in the right
12262 place for the whole arg. */
12263 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12268 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
12269 rtx off = GEN_INT (i++ * 4);
12270 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12272 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
12274 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12277 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
12278 but must also be copied into the parameter save area starting at
12279 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
12280 to the GPRs and/or memory. Return the number of elements used. */
12283 rs6000_psave_function_arg (machine_mode mode, const_tree type,
12284 int align_words, rtx *rvec)
12288 if (align_words < GP_ARG_NUM_REG)
12290 int n_words = rs6000_arg_size (mode, type);
12292 if (align_words + n_words > GP_ARG_NUM_REG
12294 || (TARGET_32BIT && TARGET_POWERPC64))
12296 /* If this is partially on the stack, then we only
12297 include the portion actually in registers here. */
12298 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12301 if (align_words + n_words > GP_ARG_NUM_REG)
12303 /* Not all of the arg fits in gprs. Say that it goes in memory
12304 too, using a magic NULL_RTX component. Also see comment in
12305 rs6000_mixed_function_arg for why the normal
12306 function_arg_partial_nregs scheme doesn't work in this case. */
12307 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12312 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12313 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
12314 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12316 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12320 /* The whole arg fits in gprs. */
12321 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12322 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
12327 /* It's entirely in memory. */
12328 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
12334 /* RVEC is a vector of K components of an argument of mode MODE.
12335 Construct the final function_arg return value from it. */
12338 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
12340 gcc_assert (k >= 1);
12342 /* Avoid returning a PARALLEL in the trivial cases. */
12345 if (XEXP (rvec[0], 0) == NULL_RTX)
12348 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
12349 return XEXP (rvec[0], 0);
12352 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
12355 /* Determine where to put an argument to a function.
12356 Value is zero to push the argument on the stack,
12357 or a hard register in which to store the argument.
12359 MODE is the argument's machine mode.
12360 TYPE is the data type of the argument (as a tree).
12361 This is null for libcalls where that information may
12363 CUM is a variable of type CUMULATIVE_ARGS which gives info about
12364 the preceding args and about the function being called. It is
12365 not modified in this routine.
12366 NAMED is nonzero if this argument is a named parameter
12367 (otherwise it is an extra parameter matching an ellipsis).
12369 On RS/6000 the first eight words of non-FP are normally in registers
12370 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
12371 Under V.4, the first 8 FP args are in registers.
12373 If this is floating-point and no prototype is specified, we use
12374 both an FP and integer register (or possibly FP reg and stack). Library
12375 functions (when CALL_LIBCALL is set) always have the proper types for args,
12376 so we can pass the FP value just in one register. emit_library_function
12377 doesn't support PARALLEL anyway.
12379 Note that for args passed by reference, function_arg will be called
12380 with MODE and TYPE set to that of the pointer to the arg, not the arg
12384 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
12385 const_tree type, bool named)
12387 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12388 enum rs6000_abi abi = DEFAULT_ABI;
12389 machine_mode elt_mode;
12392 /* Return a marker to indicate whether CR1 needs to set or clear the
12393 bit that V.4 uses to say fp args were passed in registers.
12394 Assume that we don't need the marker for software floating point,
12395 or compiler generated library calls. */
12396 if (mode == VOIDmode)
12399 && (cum->call_cookie & CALL_LIBCALL) == 0
12401 || (cum->nargs_prototype < 0
12402 && (cum->prototype || TARGET_NO_PROTOTYPE)))
12403 && TARGET_HARD_FLOAT)
12404 return GEN_INT (cum->call_cookie
12405 | ((cum->fregno == FP_ARG_MIN_REG)
12406 ? CALL_V4_SET_FP_ARGS
12407 : CALL_V4_CLEAR_FP_ARGS));
12409 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
12412 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12414 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12416 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
12417 if (rslt != NULL_RTX)
12419 /* Else fall through to usual handling. */
12422 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12424 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12428 /* Do we also need to pass this argument in the parameter save area?
12429 Library support functions for IEEE 128-bit are assumed to not need the
12430 value passed both in GPRs and in vector registers. */
12431 if (TARGET_64BIT && !cum->prototype
12432 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12434 int align_words = ROUND_UP (cum->words, 2);
12435 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12438 /* Describe where this argument goes in the vector registers. */
12439 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
12441 r = gen_rtx_REG (elt_mode, cum->vregno + i);
12442 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12443 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12446 return rs6000_finish_function_arg (mode, rvec, k);
12448 else if (TARGET_ALTIVEC_ABI
12449 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
12450 || (type && TREE_CODE (type) == VECTOR_TYPE
12451 && int_size_in_bytes (type) == 16)))
12453 if (named || abi == ABI_V4)
12457 /* Vector parameters to varargs functions under AIX or Darwin
12458 get passed in memory and possibly also in GPRs. */
12459 int align, align_words, n_words;
12460 machine_mode part_mode;
12462 /* Vector parameters must be 16-byte aligned. In 32-bit
12463 mode this means we need to take into account the offset
12464 to the parameter save area. In 64-bit mode, they just
12465 have to start on an even word, since the parameter save
12466 area is 16-byte aligned. */
12468 align = -(rs6000_parm_offset () + cum->words) & 3;
12470 align = cum->words & 1;
12471 align_words = cum->words + align;
12473 /* Out of registers? Memory, then. */
12474 if (align_words >= GP_ARG_NUM_REG)
12477 if (TARGET_32BIT && TARGET_POWERPC64)
12478 return rs6000_mixed_function_arg (mode, type, align_words);
12480 /* The vector value goes in GPRs. Only the part of the
12481 value in GPRs is reported here. */
12483 n_words = rs6000_arg_size (mode, type);
12484 if (align_words + n_words > GP_ARG_NUM_REG)
12485 /* Fortunately, there are only two possibilities, the value
12486 is either wholly in GPRs or half in GPRs and half not. */
12487 part_mode = DImode;
12489 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
12493 else if (abi == ABI_V4)
12495 if (abi_v4_pass_in_fpr (mode))
12497 /* _Decimal128 must use an even/odd register pair. This assumes
12498 that the register number is odd when fregno is odd. */
12499 if (mode == TDmode && (cum->fregno % 2) == 1)
12502 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
12503 <= FP_ARG_V4_MAX_REG)
12504 return gen_rtx_REG (mode, cum->fregno);
12510 int n_words = rs6000_arg_size (mode, type);
12511 int gregno = cum->sysv_gregno;
12513 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
12514 As does any other 2 word item such as complex int due to a
12515 historical mistake. */
12517 gregno += (1 - gregno) & 1;
12519 /* Multi-reg args are not split between registers and stack. */
12520 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
12523 if (TARGET_32BIT && TARGET_POWERPC64)
12524 return rs6000_mixed_function_arg (mode, type,
12525 gregno - GP_ARG_MIN_REG);
12526 return gen_rtx_REG (mode, gregno);
12531 int align_words = rs6000_parm_start (mode, type, cum->words);
12533 /* _Decimal128 must be passed in an even/odd float register pair.
12534 This assumes that the register number is odd when fregno is odd. */
12535 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
12538 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12540 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
12543 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12546 /* Do we also need to pass this argument in the parameter
12548 if (type && (cum->nargs_prototype <= 0
12549 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12550 && TARGET_XL_COMPAT
12551 && align_words >= GP_ARG_NUM_REG)))
12552 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
12554 /* Describe where this argument goes in the fprs. */
12555 for (i = 0; i < n_elts
12556 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
12558 /* Check if the argument is split over registers and memory.
12559 This can only ever happen for long double or _Decimal128;
12560 complex types are handled via split_complex_arg. */
12561 machine_mode fmode = elt_mode;
12562 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
12564 gcc_assert (FLOAT128_2REG_P (fmode));
12565 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
12568 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
12569 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
12570 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12573 /* If there were not enough FPRs to hold the argument, the rest
12574 usually goes into memory. However, if the current position
12575 is still within the register parameter area, a portion may
12576 actually have to go into GPRs.
12578 Note that it may happen that the portion of the argument
12579 passed in the first "half" of the first GPR was already
12580 passed in the last FPR as well.
12582 For unnamed arguments, we already set up GPRs to cover the
12583 whole argument in rs6000_psave_function_arg, so there is
12584 nothing further to do at this point. */
12585 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
12586 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
12587 && cum->nargs_prototype > 0)
12589 static bool warned;
12591 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
12592 int n_words = rs6000_arg_size (mode, type);
12594 align_words += fpr_words;
12595 n_words -= fpr_words;
12599 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
12600 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
12601 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
12603 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
12605 if (!warned && warn_psabi)
12608 inform (input_location,
12609 "the ABI of passing homogeneous float aggregates"
12610 " has changed in GCC 5");
12614 return rs6000_finish_function_arg (mode, rvec, k);
12616 else if (align_words < GP_ARG_NUM_REG)
12618 if (TARGET_32BIT && TARGET_POWERPC64)
12619 return rs6000_mixed_function_arg (mode, type, align_words);
12621 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
12628 /* For an arg passed partly in registers and partly in memory, this is
12629 the number of bytes passed in registers. For args passed entirely in
12630 registers or entirely in memory, zero. When an arg is described by a
12631 PARALLEL, perhaps using more than one register type, this function
12632 returns the number of bytes used by the first element of the PARALLEL. */
12635 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
12636 tree type, bool named)
12638 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
12639 bool passed_in_gprs = true;
12642 machine_mode elt_mode;
12645 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
12647 if (DEFAULT_ABI == ABI_V4)
12650 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
12652 /* If we are passing this arg in the fixed parameter save area (gprs or
12653 memory) as well as VRs, we do not use the partial bytes mechanism;
12654 instead, rs6000_function_arg will return a PARALLEL including a memory
12655 element as necessary. Library support functions for IEEE 128-bit are
12656 assumed to not need the value passed both in GPRs and in vector
12658 if (TARGET_64BIT && !cum->prototype
12659 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
12662 /* Otherwise, we pass in VRs only. Check for partial copies. */
12663 passed_in_gprs = false;
12664 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
12665 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
12668 /* In this complicated case we just disable the partial_nregs code. */
12669 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
12672 align_words = rs6000_parm_start (mode, type, cum->words);
12674 if (USE_FP_FOR_ARG_P (cum, elt_mode))
12676 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
12678 /* If we are passing this arg in the fixed parameter save area
12679 (gprs or memory) as well as FPRs, we do not use the partial
12680 bytes mechanism; instead, rs6000_function_arg will return a
12681 PARALLEL including a memory element as necessary. */
12683 && (cum->nargs_prototype <= 0
12684 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12685 && TARGET_XL_COMPAT
12686 && align_words >= GP_ARG_NUM_REG)))
12689 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12690 passed_in_gprs = false;
12691 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
12693 /* Compute number of bytes / words passed in FPRs. If there
12694 is still space available in the register parameter area
12695 *after* that amount, a part of the argument will be passed
12696 in GPRs. In that case, the total amount passed in any
12697 registers is equal to the amount that would have been passed
12698 in GPRs if everything were passed there, so we fall back to
12699 the GPR code below to compute the appropriate value. */
12700 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
12701 * MIN (8, GET_MODE_SIZE (elt_mode)));
12702 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
12704 if (align_words + fpr_words < GP_ARG_NUM_REG)
12705 passed_in_gprs = true;
12712 && align_words < GP_ARG_NUM_REG
12713 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
12714 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
12716 if (ret != 0 && TARGET_DEBUG_ARG)
12717 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
12722 /* A C expression that indicates when an argument must be passed by
12723 reference. If nonzero for an argument, a copy of that argument is
12724 made in memory and a pointer to the argument is passed instead of
12725 the argument itself. The pointer is passed in whatever way is
12726 appropriate for passing a pointer to that type.
12728 Under V.4, aggregates and long double are passed by reference.
12730 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12731 reference unless the AltiVec vector extension ABI is in force.
12733 As an extension to all ABIs, variable sized types are passed by
12737 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
12738 machine_mode mode, const_tree type,
12739 bool named ATTRIBUTE_UNUSED)
12744 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
12745 && FLOAT128_IEEE_P (TYPE_MODE (type)))
12747 if (TARGET_DEBUG_ARG)
12748 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12752 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
12754 if (TARGET_DEBUG_ARG)
12755 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
12759 if (int_size_in_bytes (type) < 0)
12761 if (TARGET_DEBUG_ARG)
12762 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
12766 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12767 modes only exist for GCC vector types if -maltivec. */
12768 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12770 if (TARGET_DEBUG_ARG)
12771 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
12775 /* Pass synthetic vectors in memory. */
12776 if (TREE_CODE (type) == VECTOR_TYPE
12777 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
12779 static bool warned_for_pass_big_vectors = false;
12780 if (TARGET_DEBUG_ARG)
12781 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
12782 if (!warned_for_pass_big_vectors)
12784 warning (OPT_Wpsabi, "GCC vector passed by reference: "
12785 "non-standard ABI extension with no compatibility "
12787 warned_for_pass_big_vectors = true;
12795 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12796 already processes. Return true if the parameter must be passed
12797 (fully or partially) on the stack. */
12800 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
12806 /* Catch errors. */
12807 if (type == NULL || type == error_mark_node)
12810 /* Handle types with no storage requirement. */
12811 if (TYPE_MODE (type) == VOIDmode)
12814 /* Handle complex types. */
12815 if (TREE_CODE (type) == COMPLEX_TYPE)
12816 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
12817 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
12819 /* Handle transparent aggregates. */
12820 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
12821 && TYPE_TRANSPARENT_AGGR (type))
12822 type = TREE_TYPE (first_field (type));
12824 /* See if this arg was passed by invisible reference. */
12825 if (pass_by_reference (get_cumulative_args (args_so_far),
12826 TYPE_MODE (type), type, true))
12827 type = build_pointer_type (type);
12829 /* Find mode as it is passed by the ABI. */
12830 unsignedp = TYPE_UNSIGNED (type);
12831 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
12833 /* If we must pass in stack, we need a stack. */
12834 if (rs6000_must_pass_in_stack (mode, type))
12837 /* If there is no incoming register, we need a stack. */
12838 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
12839 if (entry_parm == NULL)
12842 /* Likewise if we need to pass both in registers and on the stack. */
12843 if (GET_CODE (entry_parm) == PARALLEL
12844 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
12847 /* Also true if we're partially in registers and partially not. */
12848 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
12851 /* Update info on where next arg arrives in registers. */
12852 rs6000_function_arg_advance (args_so_far, mode, type, true);
12856 /* Return true if FUN has no prototype, has a variable argument
12857 list, or passes any parameter in memory. */
12860 rs6000_function_parms_need_stack (tree fun, bool incoming)
12862 tree fntype, result;
12863 CUMULATIVE_ARGS args_so_far_v;
12864 cumulative_args_t args_so_far;
12867 /* Must be a libcall, all of which only use reg parms. */
12872 fntype = TREE_TYPE (fun);
12874 /* Varargs functions need the parameter save area. */
12875 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
12878 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
12879 args_so_far = pack_cumulative_args (&args_so_far_v);
12881 /* When incoming, we will have been passed the function decl.
12882 It is necessary to use the decl to handle K&R style functions,
12883 where TYPE_ARG_TYPES may not be available. */
12886 gcc_assert (DECL_P (fun));
12887 result = DECL_RESULT (fun);
12890 result = TREE_TYPE (fntype);
12892 if (result && aggregate_value_p (result, fntype))
12894 if (!TYPE_P (result))
12895 result = TREE_TYPE (result);
12896 result = build_pointer_type (result);
12897 rs6000_parm_needs_stack (args_so_far, result);
12904 for (parm = DECL_ARGUMENTS (fun);
12905 parm && parm != void_list_node;
12906 parm = TREE_CHAIN (parm))
12907 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12912 function_args_iterator args_iter;
12915 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12916 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12923 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12924 usually a constant depending on the ABI. However, in the ELFv2 ABI
12925 the register parameter area is optional when calling a function that
12926 has a prototype is scope, has no variable argument list, and passes
12927 all parameters in registers. */
12930 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12932 int reg_parm_stack_space;
12934 switch (DEFAULT_ABI)
12937 reg_parm_stack_space = 0;
12942 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12946 /* ??? Recomputing this every time is a bit expensive. Is there
12947 a place to cache this information? */
12948 if (rs6000_function_parms_need_stack (fun, incoming))
12949 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12951 reg_parm_stack_space = 0;
12955 return reg_parm_stack_space;
12959 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12962 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12967 for (i = 0; i < nregs; i++)
12969 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12970 if (reload_completed)
12972 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12975 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12976 i * GET_MODE_SIZE (reg_mode));
12979 tem = replace_equiv_address (tem, XEXP (tem, 0));
12983 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12987 /* Perform any needed actions needed for a function that is receiving a
12988 variable number of arguments.
12992 MODE and TYPE are the mode and type of the current parameter.
12994 PRETEND_SIZE is a variable that should be set to the amount of stack
12995 that must be pushed by the prolog to pretend that our caller pushed
12998 Normally, this macro will push all remaining incoming registers on the
12999 stack and set PRETEND_SIZE to the length of the registers pushed. */
13002 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
13003 tree type, int *pretend_size ATTRIBUTE_UNUSED,
13006 CUMULATIVE_ARGS next_cum;
13007 int reg_size = TARGET_32BIT ? 4 : 8;
13008 rtx save_area = NULL_RTX, mem;
13009 int first_reg_offset;
13010 alias_set_type set;
13012 /* Skip the last named argument. */
13013 next_cum = *get_cumulative_args (cum);
13014 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
13016 if (DEFAULT_ABI == ABI_V4)
13018 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
13022 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
13023 HOST_WIDE_INT offset = 0;
13025 /* Try to optimize the size of the varargs save area.
13026 The ABI requires that ap.reg_save_area is doubleword
13027 aligned, but we don't need to allocate space for all
13028 the bytes, only those to which we actually will save
13030 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
13031 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
13032 if (TARGET_HARD_FLOAT
13033 && next_cum.fregno <= FP_ARG_V4_MAX_REG
13034 && cfun->va_list_fpr_size)
13037 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
13038 * UNITS_PER_FP_WORD;
13039 if (cfun->va_list_fpr_size
13040 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
13041 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
13043 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
13044 * UNITS_PER_FP_WORD;
13048 offset = -((first_reg_offset * reg_size) & ~7);
13049 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
13051 gpr_reg_num = cfun->va_list_gpr_size;
13052 if (reg_size == 4 && (first_reg_offset & 1))
13055 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
13058 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
13059 * UNITS_PER_FP_WORD
13060 - (int) (GP_ARG_NUM_REG * reg_size);
13062 if (gpr_size + fpr_size)
13065 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
13066 gcc_assert (GET_CODE (reg_save_area) == MEM);
13067 reg_save_area = XEXP (reg_save_area, 0);
13068 if (GET_CODE (reg_save_area) == PLUS)
13070 gcc_assert (XEXP (reg_save_area, 0)
13071 == virtual_stack_vars_rtx);
13072 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
13073 offset += INTVAL (XEXP (reg_save_area, 1));
13076 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
13079 cfun->machine->varargs_save_offset = offset;
13080 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
13085 first_reg_offset = next_cum.words;
13086 save_area = crtl->args.internal_arg_pointer;
13088 if (targetm.calls.must_pass_in_stack (mode, type))
13089 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
13092 set = get_varargs_alias_set ();
13093 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
13094 && cfun->va_list_gpr_size)
13096 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
13098 if (va_list_gpr_counter_field)
13099 /* V4 va_list_gpr_size counts number of registers needed. */
13100 n_gpr = cfun->va_list_gpr_size;
13102 /* char * va_list instead counts number of bytes needed. */
13103 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
13108 mem = gen_rtx_MEM (BLKmode,
13109 plus_constant (Pmode, save_area,
13110 first_reg_offset * reg_size));
13111 MEM_NOTRAP_P (mem) = 1;
13112 set_mem_alias_set (mem, set);
13113 set_mem_align (mem, BITS_PER_WORD);
13115 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
13119 /* Save FP registers if needed. */
13120 if (DEFAULT_ABI == ABI_V4
13121 && TARGET_HARD_FLOAT
13123 && next_cum.fregno <= FP_ARG_V4_MAX_REG
13124 && cfun->va_list_fpr_size)
13126 int fregno = next_cum.fregno, nregs;
13127 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
13128 rtx lab = gen_label_rtx ();
13129 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
13130 * UNITS_PER_FP_WORD);
13133 (gen_rtx_SET (pc_rtx,
13134 gen_rtx_IF_THEN_ELSE (VOIDmode,
13135 gen_rtx_NE (VOIDmode, cr1,
13137 gen_rtx_LABEL_REF (VOIDmode, lab),
13141 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
13142 fregno++, off += UNITS_PER_FP_WORD, nregs++)
13144 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13146 plus_constant (Pmode, save_area, off));
13147 MEM_NOTRAP_P (mem) = 1;
13148 set_mem_alias_set (mem, set);
13149 set_mem_align (mem, GET_MODE_ALIGNMENT (
13150 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13151 ? DFmode : SFmode));
13152 emit_move_insn (mem, gen_rtx_REG (
13153 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
13154 ? DFmode : SFmode, fregno));
13161 /* Create the va_list data type. */
13164 rs6000_build_builtin_va_list (void)
13166 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
13168 /* For AIX, prefer 'char *' because that's what the system
13169 header files like. */
13170 if (DEFAULT_ABI != ABI_V4)
13171 return build_pointer_type (char_type_node);
13173 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
13174 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
13175 get_identifier ("__va_list_tag"), record);
13177 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
13178 unsigned_char_type_node);
13179 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
13180 unsigned_char_type_node);
13181 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
13182 every user file. */
13183 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13184 get_identifier ("reserved"), short_unsigned_type_node);
13185 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13186 get_identifier ("overflow_arg_area"),
13188 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
13189 get_identifier ("reg_save_area"),
13192 va_list_gpr_counter_field = f_gpr;
13193 va_list_fpr_counter_field = f_fpr;
13195 DECL_FIELD_CONTEXT (f_gpr) = record;
13196 DECL_FIELD_CONTEXT (f_fpr) = record;
13197 DECL_FIELD_CONTEXT (f_res) = record;
13198 DECL_FIELD_CONTEXT (f_ovf) = record;
13199 DECL_FIELD_CONTEXT (f_sav) = record;
13201 TYPE_STUB_DECL (record) = type_decl;
13202 TYPE_NAME (record) = type_decl;
13203 TYPE_FIELDS (record) = f_gpr;
13204 DECL_CHAIN (f_gpr) = f_fpr;
13205 DECL_CHAIN (f_fpr) = f_res;
13206 DECL_CHAIN (f_res) = f_ovf;
13207 DECL_CHAIN (f_ovf) = f_sav;
13209 layout_type (record);
13211 /* The correct type is an array type of one element. */
13212 return build_array_type (record, build_index_type (size_zero_node));
13215 /* Implement va_start. */
13218 rs6000_va_start (tree valist, rtx nextarg)
13220 HOST_WIDE_INT words, n_gpr, n_fpr;
13221 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
13222 tree gpr, fpr, ovf, sav, t;
13224 /* Only SVR4 needs something special. */
13225 if (DEFAULT_ABI != ABI_V4)
13227 std_expand_builtin_va_start (valist, nextarg);
13231 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
13232 f_fpr = DECL_CHAIN (f_gpr);
13233 f_res = DECL_CHAIN (f_fpr);
13234 f_ovf = DECL_CHAIN (f_res);
13235 f_sav = DECL_CHAIN (f_ovf);
13237 valist = build_simple_mem_ref (valist);
13238 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
13239 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
13241 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
13243 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
13246 /* Count number of gp and fp argument registers used. */
13247 words = crtl->args.info.words;
13248 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
13250 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
13253 if (TARGET_DEBUG_ARG)
13254 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
13255 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
13256 words, n_gpr, n_fpr);
13258 if (cfun->va_list_gpr_size)
13260 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
13261 build_int_cst (NULL_TREE, n_gpr));
13262 TREE_SIDE_EFFECTS (t) = 1;
13263 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13266 if (cfun->va_list_fpr_size)
13268 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
13269 build_int_cst (NULL_TREE, n_fpr));
13270 TREE_SIDE_EFFECTS (t) = 1;
13271 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13273 #ifdef HAVE_AS_GNU_ATTRIBUTE
13274 if (call_ABI_of_interest (cfun->decl))
13275 rs6000_passes_float = true;
13279 /* Find the overflow area. */
13280 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
13282 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
13283 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
13284 TREE_SIDE_EFFECTS (t) = 1;
13285 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13287 /* If there were no va_arg invocations, don't set up the register
13289 if (!cfun->va_list_gpr_size
13290 && !cfun->va_list_fpr_size
13291 && n_gpr < GP_ARG_NUM_REG
13292 && n_fpr < FP_ARG_V4_MAX_REG)
13295 /* Find the register save area. */
13296 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
13297 if (cfun->machine->varargs_save_offset)
13298 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
13299 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
13300 TREE_SIDE_EFFECTS (t) = 1;
13301 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
13304 /* Implement va_arg. */
13307 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
13308 gimple_seq *post_p)
13310 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
13311 tree gpr, fpr, ovf, sav, reg, t, u;
13312 int size, rsize, n_reg, sav_ofs, sav_scale;
13313 tree lab_false, lab_over, addr;
13315 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
13319 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
13321 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
13322 return build_va_arg_indirect_ref (t);
13325 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
13326 earlier version of gcc, with the property that it always applied alignment
13327 adjustments to the va-args (even for zero-sized types). The cheapest way
13328 to deal with this is to replicate the effect of the part of
13329 std_gimplify_va_arg_expr that carries out the align adjust, for the case
13331 We don't need to check for pass-by-reference because of the test above.
13332 We can return a simplifed answer, since we know there's no offset to add. */
13335 && rs6000_darwin64_abi)
13336 || DEFAULT_ABI == ABI_ELFv2
13337 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
13338 && integer_zerop (TYPE_SIZE (type)))
13340 unsigned HOST_WIDE_INT align, boundary;
13341 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
13342 align = PARM_BOUNDARY / BITS_PER_UNIT;
13343 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
13344 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
13345 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
13346 boundary /= BITS_PER_UNIT;
13347 if (boundary > align)
13350 /* This updates arg ptr by the amount that would be necessary
13351 to align the zero-sized (but not zero-alignment) item. */
13352 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13353 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
13354 gimplify_and_add (t, pre_p);
13356 t = fold_convert (sizetype, valist_tmp);
13357 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
13358 fold_convert (TREE_TYPE (valist),
13359 fold_build2 (BIT_AND_EXPR, sizetype, t,
13360 size_int (-boundary))));
13361 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
13362 gimplify_and_add (t, pre_p);
13364 /* Since it is zero-sized there's no increment for the item itself. */
13365 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
13366 return build_va_arg_indirect_ref (valist_tmp);
13369 if (DEFAULT_ABI != ABI_V4)
13371 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
13373 tree elem_type = TREE_TYPE (type);
13374 machine_mode elem_mode = TYPE_MODE (elem_type);
13375 int elem_size = GET_MODE_SIZE (elem_mode);
13377 if (elem_size < UNITS_PER_WORD)
13379 tree real_part, imag_part;
13380 gimple_seq post = NULL;
13382 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13384 /* Copy the value into a temporary, lest the formal temporary
13385 be reused out from under us. */
13386 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
13387 gimple_seq_add_seq (pre_p, post);
13389 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
13392 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
13396 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
13399 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
13400 f_fpr = DECL_CHAIN (f_gpr);
13401 f_res = DECL_CHAIN (f_fpr);
13402 f_ovf = DECL_CHAIN (f_res);
13403 f_sav = DECL_CHAIN (f_ovf);
13405 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
13406 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
13408 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
13410 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
13413 size = int_size_in_bytes (type);
13414 rsize = (size + 3) / 4;
13415 int pad = 4 * rsize - size;
13418 machine_mode mode = TYPE_MODE (type);
13419 if (abi_v4_pass_in_fpr (mode))
13421 /* FP args go in FP registers, if present. */
13423 n_reg = (size + 7) / 8;
13424 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
13425 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
13426 if (mode != SFmode && mode != SDmode)
13431 /* Otherwise into GP registers. */
13440 /* Pull the value out of the saved registers.... */
13443 addr = create_tmp_var (ptr_type_node, "addr");
13445 /* AltiVec vectors never go in registers when -mabi=altivec. */
13446 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13450 lab_false = create_artificial_label (input_location);
13451 lab_over = create_artificial_label (input_location);
13453 /* Long long is aligned in the registers. As are any other 2 gpr
13454 item such as complex int due to a historical mistake. */
13456 if (n_reg == 2 && reg == gpr)
13459 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13460 build_int_cst (TREE_TYPE (reg), n_reg - 1));
13461 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
13462 unshare_expr (reg), u);
13464 /* _Decimal128 is passed in even/odd fpr pairs; the stored
13465 reg number is 0 for f1, so we want to make it odd. */
13466 else if (reg == fpr && mode == TDmode)
13468 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13469 build_int_cst (TREE_TYPE (reg), 1));
13470 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
13473 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
13474 t = build2 (GE_EXPR, boolean_type_node, u, t);
13475 u = build1 (GOTO_EXPR, void_type_node, lab_false);
13476 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
13477 gimplify_and_add (t, pre_p);
13481 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
13483 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
13484 build_int_cst (TREE_TYPE (reg), n_reg));
13485 u = fold_convert (sizetype, u);
13486 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
13487 t = fold_build_pointer_plus (t, u);
13489 /* _Decimal32 varargs are located in the second word of the 64-bit
13490 FP register for 32-bit binaries. */
13491 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
13492 t = fold_build_pointer_plus_hwi (t, size);
13494 /* Args are passed right-aligned. */
13495 if (BYTES_BIG_ENDIAN)
13496 t = fold_build_pointer_plus_hwi (t, pad);
13498 gimplify_assign (addr, t, pre_p);
13500 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
13502 stmt = gimple_build_label (lab_false);
13503 gimple_seq_add_stmt (pre_p, stmt);
13505 if ((n_reg == 2 && !regalign) || n_reg > 2)
13507 /* Ensure that we don't find any more args in regs.
13508 Alignment has taken care of for special cases. */
13509 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
13513 /* ... otherwise out of the overflow area. */
13515 /* Care for on-stack alignment if needed. */
13519 t = fold_build_pointer_plus_hwi (t, align - 1);
13520 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
13521 build_int_cst (TREE_TYPE (t), -align));
13524 /* Args are passed right-aligned. */
13525 if (BYTES_BIG_ENDIAN)
13526 t = fold_build_pointer_plus_hwi (t, pad);
13528 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
13530 gimplify_assign (unshare_expr (addr), t, pre_p);
13532 t = fold_build_pointer_plus_hwi (t, size);
13533 gimplify_assign (unshare_expr (ovf), t, pre_p);
13537 stmt = gimple_build_label (lab_over);
13538 gimple_seq_add_stmt (pre_p, stmt);
13541 if (STRICT_ALIGNMENT
13542 && (TYPE_ALIGN (type)
13543 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
13545 /* The value (of type complex double, for example) may not be
13546 aligned in memory in the saved registers, so copy via a
13547 temporary. (This is the same code as used for SPARC.) */
13548 tree tmp = create_tmp_var (type, "va_arg_tmp");
13549 tree dest_addr = build_fold_addr_expr (tmp);
13551 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
13552 3, dest_addr, addr, size_int (rsize * 4));
13554 gimplify_and_add (copy, pre_p);
13558 addr = fold_convert (ptrtype, addr);
13559 return build_va_arg_indirect_ref (addr);
13565 def_builtin (const char *name, tree type, enum rs6000_builtins code)
13568 unsigned classify = rs6000_builtin_info[(int)code].attr;
13569 const char *attr_string = "";
13571 gcc_assert (name != NULL);
13572 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
13574 if (rs6000_builtin_decls[(int)code])
13575 fatal_error (input_location,
13576 "internal error: builtin function %qs already processed",
13579 rs6000_builtin_decls[(int)code] = t =
13580 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
13582 /* Set any special attributes. */
13583 if ((classify & RS6000_BTC_CONST) != 0)
13585 /* const function, function only depends on the inputs. */
13586 TREE_READONLY (t) = 1;
13587 TREE_NOTHROW (t) = 1;
13588 attr_string = ", const";
13590 else if ((classify & RS6000_BTC_PURE) != 0)
13592 /* pure function, function can read global memory, but does not set any
13594 DECL_PURE_P (t) = 1;
13595 TREE_NOTHROW (t) = 1;
13596 attr_string = ", pure";
13598 else if ((classify & RS6000_BTC_FP) != 0)
13600 /* Function is a math function. If rounding mode is on, then treat the
13601 function as not reading global memory, but it can have arbitrary side
13602 effects. If it is off, then assume the function is a const function.
13603 This mimics the ATTR_MATHFN_FPROUNDING attribute in
13604 builtin-attribute.def that is used for the math functions. */
13605 TREE_NOTHROW (t) = 1;
13606 if (flag_rounding_math)
13608 DECL_PURE_P (t) = 1;
13609 DECL_IS_NOVOPS (t) = 1;
13610 attr_string = ", fp, pure";
13614 TREE_READONLY (t) = 1;
13615 attr_string = ", fp, const";
13618 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
13619 gcc_unreachable ();
13621 if (TARGET_DEBUG_BUILTIN)
13622 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
13623 (int)code, name, attr_string);
13626 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
13628 #undef RS6000_BUILTIN_0
13629 #undef RS6000_BUILTIN_1
13630 #undef RS6000_BUILTIN_2
13631 #undef RS6000_BUILTIN_3
13632 #undef RS6000_BUILTIN_A
13633 #undef RS6000_BUILTIN_D
13634 #undef RS6000_BUILTIN_H
13635 #undef RS6000_BUILTIN_P
13636 #undef RS6000_BUILTIN_Q
13637 #undef RS6000_BUILTIN_X
13639 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13640 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13641 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13642 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13643 { MASK, ICODE, NAME, ENUM },
13645 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13646 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13647 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13648 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13649 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13650 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13652 static const struct builtin_description bdesc_3arg[] =
13654 #include "rs6000-builtin.def"
13657 /* DST operations: void foo (void *, const int, const char). */
13659 #undef RS6000_BUILTIN_0
13660 #undef RS6000_BUILTIN_1
13661 #undef RS6000_BUILTIN_2
13662 #undef RS6000_BUILTIN_3
13663 #undef RS6000_BUILTIN_A
13664 #undef RS6000_BUILTIN_D
13665 #undef RS6000_BUILTIN_H
13666 #undef RS6000_BUILTIN_P
13667 #undef RS6000_BUILTIN_Q
13668 #undef RS6000_BUILTIN_X
13670 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13671 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13672 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13673 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13674 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13675 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13676 { MASK, ICODE, NAME, ENUM },
13678 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13679 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13680 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13681 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13683 static const struct builtin_description bdesc_dst[] =
13685 #include "rs6000-builtin.def"
13688 /* Simple binary operations: VECc = foo (VECa, VECb). */
13690 #undef RS6000_BUILTIN_0
13691 #undef RS6000_BUILTIN_1
13692 #undef RS6000_BUILTIN_2
13693 #undef RS6000_BUILTIN_3
13694 #undef RS6000_BUILTIN_A
13695 #undef RS6000_BUILTIN_D
13696 #undef RS6000_BUILTIN_H
13697 #undef RS6000_BUILTIN_P
13698 #undef RS6000_BUILTIN_Q
13699 #undef RS6000_BUILTIN_X
13701 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13702 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13703 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13704 { MASK, ICODE, NAME, ENUM },
13706 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13707 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13708 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13709 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13710 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13711 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13712 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13714 static const struct builtin_description bdesc_2arg[] =
13716 #include "rs6000-builtin.def"
13719 #undef RS6000_BUILTIN_0
13720 #undef RS6000_BUILTIN_1
13721 #undef RS6000_BUILTIN_2
13722 #undef RS6000_BUILTIN_3
13723 #undef RS6000_BUILTIN_A
13724 #undef RS6000_BUILTIN_D
13725 #undef RS6000_BUILTIN_H
13726 #undef RS6000_BUILTIN_P
13727 #undef RS6000_BUILTIN_Q
13728 #undef RS6000_BUILTIN_X
13730 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13731 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13732 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13733 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13734 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13735 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13736 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13737 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13738 { MASK, ICODE, NAME, ENUM },
13740 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13741 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13743 /* AltiVec predicates. */
13745 static const struct builtin_description bdesc_altivec_preds[] =
13747 #include "rs6000-builtin.def"
13750 /* PAIRED predicates. */
13751 #undef RS6000_BUILTIN_0
13752 #undef RS6000_BUILTIN_1
13753 #undef RS6000_BUILTIN_2
13754 #undef RS6000_BUILTIN_3
13755 #undef RS6000_BUILTIN_A
13756 #undef RS6000_BUILTIN_D
13757 #undef RS6000_BUILTIN_H
13758 #undef RS6000_BUILTIN_P
13759 #undef RS6000_BUILTIN_Q
13760 #undef RS6000_BUILTIN_X
13762 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13763 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13764 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13765 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13766 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13767 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13768 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13769 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13770 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
13771 { MASK, ICODE, NAME, ENUM },
13773 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13775 static const struct builtin_description bdesc_paired_preds[] =
13777 #include "rs6000-builtin.def"
13780 /* ABS* operations. */
13782 #undef RS6000_BUILTIN_0
13783 #undef RS6000_BUILTIN_1
13784 #undef RS6000_BUILTIN_2
13785 #undef RS6000_BUILTIN_3
13786 #undef RS6000_BUILTIN_A
13787 #undef RS6000_BUILTIN_D
13788 #undef RS6000_BUILTIN_H
13789 #undef RS6000_BUILTIN_P
13790 #undef RS6000_BUILTIN_Q
13791 #undef RS6000_BUILTIN_X
13793 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13794 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13795 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13796 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13797 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13798 { MASK, ICODE, NAME, ENUM },
13800 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13801 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13802 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13803 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13804 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13806 static const struct builtin_description bdesc_abs[] =
13808 #include "rs6000-builtin.def"
13811 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13814 #undef RS6000_BUILTIN_0
13815 #undef RS6000_BUILTIN_1
13816 #undef RS6000_BUILTIN_2
13817 #undef RS6000_BUILTIN_3
13818 #undef RS6000_BUILTIN_A
13819 #undef RS6000_BUILTIN_D
13820 #undef RS6000_BUILTIN_H
13821 #undef RS6000_BUILTIN_P
13822 #undef RS6000_BUILTIN_Q
13823 #undef RS6000_BUILTIN_X
13825 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13826 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13827 { MASK, ICODE, NAME, ENUM },
13829 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13830 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13831 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13832 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13833 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13834 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13835 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13836 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13838 static const struct builtin_description bdesc_1arg[] =
13840 #include "rs6000-builtin.def"
13843 /* Simple no-argument operations: result = __builtin_darn_32 () */
13845 #undef RS6000_BUILTIN_0
13846 #undef RS6000_BUILTIN_1
13847 #undef RS6000_BUILTIN_2
13848 #undef RS6000_BUILTIN_3
13849 #undef RS6000_BUILTIN_A
13850 #undef RS6000_BUILTIN_D
13851 #undef RS6000_BUILTIN_H
13852 #undef RS6000_BUILTIN_P
13853 #undef RS6000_BUILTIN_Q
13854 #undef RS6000_BUILTIN_X
13856 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13857 { MASK, ICODE, NAME, ENUM },
13859 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13860 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13861 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13862 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13863 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13864 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13865 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13866 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13867 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13869 static const struct builtin_description bdesc_0arg[] =
13871 #include "rs6000-builtin.def"
13874 /* HTM builtins. */
13875 #undef RS6000_BUILTIN_0
13876 #undef RS6000_BUILTIN_1
13877 #undef RS6000_BUILTIN_2
13878 #undef RS6000_BUILTIN_3
13879 #undef RS6000_BUILTIN_A
13880 #undef RS6000_BUILTIN_D
13881 #undef RS6000_BUILTIN_H
13882 #undef RS6000_BUILTIN_P
13883 #undef RS6000_BUILTIN_Q
13884 #undef RS6000_BUILTIN_X
13886 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13887 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13888 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13889 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13890 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13891 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13892 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13893 { MASK, ICODE, NAME, ENUM },
13895 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13896 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13897 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13899 static const struct builtin_description bdesc_htm[] =
13901 #include "rs6000-builtin.def"
13904 #undef RS6000_BUILTIN_0
13905 #undef RS6000_BUILTIN_1
13906 #undef RS6000_BUILTIN_2
13907 #undef RS6000_BUILTIN_3
13908 #undef RS6000_BUILTIN_A
13909 #undef RS6000_BUILTIN_D
13910 #undef RS6000_BUILTIN_H
13911 #undef RS6000_BUILTIN_P
13912 #undef RS6000_BUILTIN_Q
13914 /* Return true if a builtin function is overloaded. */
13916 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
13918 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
13922 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
13924 return rs6000_builtin_info[(int)fncode].name;
13927 /* Expand an expression EXP that calls a builtin without arguments. */
13929 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
13932 machine_mode tmode = insn_data[icode].operand[0].mode;
13934 if (icode == CODE_FOR_nothing)
13935 /* Builtin not supported on this processor. */
13939 || GET_MODE (target) != tmode
13940 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13941 target = gen_reg_rtx (tmode);
13943 pat = GEN_FCN (icode) (target);
13953 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13956 tree arg0 = CALL_EXPR_ARG (exp, 0);
13957 tree arg1 = CALL_EXPR_ARG (exp, 1);
13958 rtx op0 = expand_normal (arg0);
13959 rtx op1 = expand_normal (arg1);
13960 machine_mode mode0 = insn_data[icode].operand[0].mode;
13961 machine_mode mode1 = insn_data[icode].operand[1].mode;
13963 if (icode == CODE_FOR_nothing)
13964 /* Builtin not supported on this processor. */
13967 /* If we got invalid arguments bail out before generating bad rtl. */
13968 if (arg0 == error_mark_node || arg1 == error_mark_node)
13971 if (GET_CODE (op0) != CONST_INT
13972 || INTVAL (op0) > 255
13973 || INTVAL (op0) < 0)
13975 error ("argument 1 must be an 8-bit field value");
13979 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13980 op0 = copy_to_mode_reg (mode0, op0);
13982 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13983 op1 = copy_to_mode_reg (mode1, op1);
13985 pat = GEN_FCN (icode) (op0, op1);
13994 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13997 tree arg0 = CALL_EXPR_ARG (exp, 0);
13998 rtx op0 = expand_normal (arg0);
13999 machine_mode tmode = insn_data[icode].operand[0].mode;
14000 machine_mode mode0 = insn_data[icode].operand[1].mode;
14002 if (icode == CODE_FOR_nothing)
14003 /* Builtin not supported on this processor. */
14006 /* If we got invalid arguments bail out before generating bad rtl. */
14007 if (arg0 == error_mark_node)
14010 if (icode == CODE_FOR_altivec_vspltisb
14011 || icode == CODE_FOR_altivec_vspltish
14012 || icode == CODE_FOR_altivec_vspltisw)
14014 /* Only allow 5-bit *signed* literals. */
14015 if (GET_CODE (op0) != CONST_INT
14016 || INTVAL (op0) > 15
14017 || INTVAL (op0) < -16)
14019 error ("argument 1 must be a 5-bit signed literal");
14020 return CONST0_RTX (tmode);
14025 || GET_MODE (target) != tmode
14026 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14027 target = gen_reg_rtx (tmode);
14029 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14030 op0 = copy_to_mode_reg (mode0, op0);
14032 pat = GEN_FCN (icode) (target, op0);
14041 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
14043 rtx pat, scratch1, scratch2;
14044 tree arg0 = CALL_EXPR_ARG (exp, 0);
14045 rtx op0 = expand_normal (arg0);
14046 machine_mode tmode = insn_data[icode].operand[0].mode;
14047 machine_mode mode0 = insn_data[icode].operand[1].mode;
14049 /* If we have invalid arguments, bail out before generating bad rtl. */
14050 if (arg0 == error_mark_node)
14054 || GET_MODE (target) != tmode
14055 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14056 target = gen_reg_rtx (tmode);
14058 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14059 op0 = copy_to_mode_reg (mode0, op0);
14061 scratch1 = gen_reg_rtx (mode0);
14062 scratch2 = gen_reg_rtx (mode0);
14064 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
14073 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
14076 tree arg0 = CALL_EXPR_ARG (exp, 0);
14077 tree arg1 = CALL_EXPR_ARG (exp, 1);
14078 rtx op0 = expand_normal (arg0);
14079 rtx op1 = expand_normal (arg1);
14080 machine_mode tmode = insn_data[icode].operand[0].mode;
14081 machine_mode mode0 = insn_data[icode].operand[1].mode;
14082 machine_mode mode1 = insn_data[icode].operand[2].mode;
14084 if (icode == CODE_FOR_nothing)
14085 /* Builtin not supported on this processor. */
14088 /* If we got invalid arguments bail out before generating bad rtl. */
14089 if (arg0 == error_mark_node || arg1 == error_mark_node)
14092 if (icode == CODE_FOR_altivec_vcfux
14093 || icode == CODE_FOR_altivec_vcfsx
14094 || icode == CODE_FOR_altivec_vctsxs
14095 || icode == CODE_FOR_altivec_vctuxs
14096 || icode == CODE_FOR_altivec_vspltb
14097 || icode == CODE_FOR_altivec_vsplth
14098 || icode == CODE_FOR_altivec_vspltw)
14100 /* Only allow 5-bit unsigned literals. */
14102 if (TREE_CODE (arg1) != INTEGER_CST
14103 || TREE_INT_CST_LOW (arg1) & ~0x1f)
14105 error ("argument 2 must be a 5-bit unsigned literal");
14106 return CONST0_RTX (tmode);
14109 else if (icode == CODE_FOR_dfptstsfi_eq_dd
14110 || icode == CODE_FOR_dfptstsfi_lt_dd
14111 || icode == CODE_FOR_dfptstsfi_gt_dd
14112 || icode == CODE_FOR_dfptstsfi_unordered_dd
14113 || icode == CODE_FOR_dfptstsfi_eq_td
14114 || icode == CODE_FOR_dfptstsfi_lt_td
14115 || icode == CODE_FOR_dfptstsfi_gt_td
14116 || icode == CODE_FOR_dfptstsfi_unordered_td)
14118 /* Only allow 6-bit unsigned literals. */
14120 if (TREE_CODE (arg0) != INTEGER_CST
14121 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
14123 error ("argument 1 must be a 6-bit unsigned literal");
14124 return CONST0_RTX (tmode);
14127 else if (icode == CODE_FOR_xststdcqp_kf
14128 || icode == CODE_FOR_xststdcqp_tf
14129 || icode == CODE_FOR_xststdcdp
14130 || icode == CODE_FOR_xststdcsp
14131 || icode == CODE_FOR_xvtstdcdp
14132 || icode == CODE_FOR_xvtstdcsp)
14134 /* Only allow 7-bit unsigned literals. */
14136 if (TREE_CODE (arg1) != INTEGER_CST
14137 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
14139 error ("argument 2 must be a 7-bit unsigned literal");
14140 return CONST0_RTX (tmode);
14143 else if (icode == CODE_FOR_unpackv1ti
14144 || icode == CODE_FOR_unpackkf
14145 || icode == CODE_FOR_unpacktf
14146 || icode == CODE_FOR_unpackif
14147 || icode == CODE_FOR_unpacktd)
14149 /* Only allow 1-bit unsigned literals. */
14151 if (TREE_CODE (arg1) != INTEGER_CST
14152 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
14154 error ("argument 2 must be a 1-bit unsigned literal");
14155 return CONST0_RTX (tmode);
14160 || GET_MODE (target) != tmode
14161 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14162 target = gen_reg_rtx (tmode);
14164 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14165 op0 = copy_to_mode_reg (mode0, op0);
14166 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14167 op1 = copy_to_mode_reg (mode1, op1);
14169 pat = GEN_FCN (icode) (target, op0, op1);
14178 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
14181 tree cr6_form = CALL_EXPR_ARG (exp, 0);
14182 tree arg0 = CALL_EXPR_ARG (exp, 1);
14183 tree arg1 = CALL_EXPR_ARG (exp, 2);
14184 rtx op0 = expand_normal (arg0);
14185 rtx op1 = expand_normal (arg1);
14186 machine_mode tmode = SImode;
14187 machine_mode mode0 = insn_data[icode].operand[1].mode;
14188 machine_mode mode1 = insn_data[icode].operand[2].mode;
14191 if (TREE_CODE (cr6_form) != INTEGER_CST)
14193 error ("argument 1 of %qs must be a constant",
14194 "__builtin_altivec_predicate");
14198 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
14200 gcc_assert (mode0 == mode1);
14202 /* If we have invalid arguments, bail out before generating bad rtl. */
14203 if (arg0 == error_mark_node || arg1 == error_mark_node)
14207 || GET_MODE (target) != tmode
14208 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14209 target = gen_reg_rtx (tmode);
14211 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14212 op0 = copy_to_mode_reg (mode0, op0);
14213 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14214 op1 = copy_to_mode_reg (mode1, op1);
14216 /* Note that for many of the relevant operations (e.g. cmpne or
14217 cmpeq) with float or double operands, it makes more sense for the
14218 mode of the allocated scratch register to select a vector of
14219 integer. But the choice to copy the mode of operand 0 was made
14220 long ago and there are no plans to change it. */
14221 scratch = gen_reg_rtx (mode0);
14223 pat = GEN_FCN (icode) (scratch, op0, op1);
14228 /* The vec_any* and vec_all* predicates use the same opcodes for two
14229 different operations, but the bits in CR6 will be different
14230 depending on what information we want. So we have to play tricks
14231 with CR6 to get the right bits out.
14233 If you think this is disgusting, look at the specs for the
14234 AltiVec predicates. */
14236 switch (cr6_form_int)
14239 emit_insn (gen_cr6_test_for_zero (target));
14242 emit_insn (gen_cr6_test_for_zero_reverse (target));
14245 emit_insn (gen_cr6_test_for_lt (target));
14248 emit_insn (gen_cr6_test_for_lt_reverse (target));
14251 error ("argument 1 of %qs is out of range",
14252 "__builtin_altivec_predicate");
14260 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
14263 tree arg0 = CALL_EXPR_ARG (exp, 0);
14264 tree arg1 = CALL_EXPR_ARG (exp, 1);
14265 machine_mode tmode = insn_data[icode].operand[0].mode;
14266 machine_mode mode0 = Pmode;
14267 machine_mode mode1 = Pmode;
14268 rtx op0 = expand_normal (arg0);
14269 rtx op1 = expand_normal (arg1);
14271 if (icode == CODE_FOR_nothing)
14272 /* Builtin not supported on this processor. */
14275 /* If we got invalid arguments bail out before generating bad rtl. */
14276 if (arg0 == error_mark_node || arg1 == error_mark_node)
14280 || GET_MODE (target) != tmode
14281 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14282 target = gen_reg_rtx (tmode);
14284 op1 = copy_to_mode_reg (mode1, op1);
14286 if (op0 == const0_rtx)
14288 addr = gen_rtx_MEM (tmode, op1);
14292 op0 = copy_to_mode_reg (mode0, op0);
14293 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
14296 pat = GEN_FCN (icode) (target, addr);
14305 /* Return a constant vector for use as a little-endian permute control vector
14306 to reverse the order of elements of the given vector mode. */
14308 swap_selector_for_mode (machine_mode mode)
14310 /* These are little endian vectors, so their elements are reversed
14311 from what you would normally expect for a permute control vector. */
14312 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14313 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14314 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14315 unsigned int swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
14316 unsigned int *swaparray, i;
14333 swaparray = swap16;
14336 gcc_unreachable ();
14339 for (i = 0; i < 16; ++i)
14340 perm[i] = GEN_INT (swaparray[i]);
14342 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)));
14346 swap_endian_selector_for_mode (machine_mode mode)
14348 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
14349 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14350 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14351 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14353 unsigned int *swaparray, i;
14373 gcc_unreachable ();
14376 for (i = 0; i < 16; ++i)
14377 perm[i] = GEN_INT (swaparray[i]);
14379 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
14380 gen_rtvec_v (16, perm)));
14383 /* Generate code for an "lvxl", or "lve*x" built-in for a little endian target
14384 with -maltivec=be specified. Issue the load followed by an element-
14385 reversing permute. */
14387 altivec_expand_lvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14389 rtx tmp = gen_reg_rtx (mode);
14390 rtx load = gen_rtx_SET (tmp, op1);
14391 rtx lvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
14392 rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, load, lvx));
14393 rtx sel = swap_selector_for_mode (mode);
14394 rtx vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, tmp, tmp, sel), UNSPEC_VPERM);
14396 gcc_assert (REG_P (op0));
14398 emit_insn (gen_rtx_SET (op0, vperm));
14401 /* Generate code for a "stvxl" built-in for a little endian target with
14402 -maltivec=be specified. Issue the store preceded by an element-reversing
14405 altivec_expand_stvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14407 rtx tmp = gen_reg_rtx (mode);
14408 rtx store = gen_rtx_SET (op0, tmp);
14409 rtx stvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
14410 rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, store, stvx));
14411 rtx sel = swap_selector_for_mode (mode);
14414 gcc_assert (REG_P (op1));
14415 vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
14416 emit_insn (gen_rtx_SET (tmp, vperm));
14420 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
14421 specified. Issue the store preceded by an element-reversing permute. */
14423 altivec_expand_stvex_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
14425 machine_mode inner_mode = GET_MODE_INNER (mode);
14426 rtx tmp = gen_reg_rtx (mode);
14427 rtx stvx = gen_rtx_UNSPEC (inner_mode, gen_rtvec (1, tmp), unspec);
14428 rtx sel = swap_selector_for_mode (mode);
14431 gcc_assert (REG_P (op1));
14432 vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
14433 emit_insn (gen_rtx_SET (tmp, vperm));
14434 emit_insn (gen_rtx_SET (op0, stvx));
14438 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
14441 tree arg0 = CALL_EXPR_ARG (exp, 0);
14442 tree arg1 = CALL_EXPR_ARG (exp, 1);
14443 machine_mode tmode = insn_data[icode].operand[0].mode;
14444 machine_mode mode0 = Pmode;
14445 machine_mode mode1 = Pmode;
14446 rtx op0 = expand_normal (arg0);
14447 rtx op1 = expand_normal (arg1);
14449 if (icode == CODE_FOR_nothing)
14450 /* Builtin not supported on this processor. */
14453 /* If we got invalid arguments bail out before generating bad rtl. */
14454 if (arg0 == error_mark_node || arg1 == error_mark_node)
14458 || GET_MODE (target) != tmode
14459 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14460 target = gen_reg_rtx (tmode);
14462 op1 = copy_to_mode_reg (mode1, op1);
14464 /* For LVX, express the RTL accurately by ANDing the address with -16.
14465 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
14466 so the raw address is fine. */
14467 if (icode == CODE_FOR_altivec_lvx_v2df_2op
14468 || icode == CODE_FOR_altivec_lvx_v2di_2op
14469 || icode == CODE_FOR_altivec_lvx_v4sf_2op
14470 || icode == CODE_FOR_altivec_lvx_v4si_2op
14471 || icode == CODE_FOR_altivec_lvx_v8hi_2op
14472 || icode == CODE_FOR_altivec_lvx_v16qi_2op)
14475 if (op0 == const0_rtx)
14479 op0 = copy_to_mode_reg (mode0, op0);
14480 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
14482 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14483 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
14485 /* For -maltivec=be, emit the load and follow it up with a
14486 permute to swap the elements. */
14487 if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
14489 rtx temp = gen_reg_rtx (tmode);
14490 emit_insn (gen_rtx_SET (temp, addr));
14492 rtx sel = swap_selector_for_mode (tmode);
14493 rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, temp, temp, sel),
14495 emit_insn (gen_rtx_SET (target, vperm));
14498 emit_insn (gen_rtx_SET (target, addr));
14502 if (op0 == const0_rtx)
14503 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
14506 op0 = copy_to_mode_reg (mode0, op0);
14507 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
14508 gen_rtx_PLUS (Pmode, op1, op0));
14511 pat = GEN_FCN (icode) (target, addr);
14521 paired_expand_stv_builtin (enum insn_code icode, tree exp)
14523 tree arg0 = CALL_EXPR_ARG (exp, 0);
14524 tree arg1 = CALL_EXPR_ARG (exp, 1);
14525 tree arg2 = CALL_EXPR_ARG (exp, 2);
14526 rtx op0 = expand_normal (arg0);
14527 rtx op1 = expand_normal (arg1);
14528 rtx op2 = expand_normal (arg2);
14530 machine_mode tmode = insn_data[icode].operand[0].mode;
14531 machine_mode mode1 = Pmode;
14532 machine_mode mode2 = Pmode;
14534 /* Invalid arguments. Bail before doing anything stoopid! */
14535 if (arg0 == error_mark_node
14536 || arg1 == error_mark_node
14537 || arg2 == error_mark_node)
14540 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
14541 op0 = copy_to_mode_reg (tmode, op0);
14543 op2 = copy_to_mode_reg (mode2, op2);
14545 if (op1 == const0_rtx)
14547 addr = gen_rtx_MEM (tmode, op2);
14551 op1 = copy_to_mode_reg (mode1, op1);
14552 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
14555 pat = GEN_FCN (icode) (addr, op0);
14562 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
14565 tree arg0 = CALL_EXPR_ARG (exp, 0);
14566 tree arg1 = CALL_EXPR_ARG (exp, 1);
14567 tree arg2 = CALL_EXPR_ARG (exp, 2);
14568 rtx op0 = expand_normal (arg0);
14569 rtx op1 = expand_normal (arg1);
14570 rtx op2 = expand_normal (arg2);
14571 machine_mode mode0 = insn_data[icode].operand[0].mode;
14572 machine_mode mode1 = insn_data[icode].operand[1].mode;
14573 machine_mode mode2 = insn_data[icode].operand[2].mode;
14575 if (icode == CODE_FOR_nothing)
14576 /* Builtin not supported on this processor. */
14579 /* If we got invalid arguments bail out before generating bad rtl. */
14580 if (arg0 == error_mark_node
14581 || arg1 == error_mark_node
14582 || arg2 == error_mark_node)
14585 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14586 op0 = copy_to_mode_reg (mode0, op0);
14587 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14588 op1 = copy_to_mode_reg (mode1, op1);
14589 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14590 op2 = copy_to_mode_reg (mode2, op2);
14592 pat = GEN_FCN (icode) (op0, op1, op2);
14600 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
14602 tree arg0 = CALL_EXPR_ARG (exp, 0);
14603 tree arg1 = CALL_EXPR_ARG (exp, 1);
14604 tree arg2 = CALL_EXPR_ARG (exp, 2);
14605 rtx op0 = expand_normal (arg0);
14606 rtx op1 = expand_normal (arg1);
14607 rtx op2 = expand_normal (arg2);
14608 rtx pat, addr, rawaddr;
14609 machine_mode tmode = insn_data[icode].operand[0].mode;
14610 machine_mode smode = insn_data[icode].operand[1].mode;
14611 machine_mode mode1 = Pmode;
14612 machine_mode mode2 = Pmode;
14614 /* Invalid arguments. Bail before doing anything stoopid! */
14615 if (arg0 == error_mark_node
14616 || arg1 == error_mark_node
14617 || arg2 == error_mark_node)
14620 op2 = copy_to_mode_reg (mode2, op2);
14622 /* For STVX, express the RTL accurately by ANDing the address with -16.
14623 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
14624 so the raw address is fine. */
14625 if (icode == CODE_FOR_altivec_stvx_v2df_2op
14626 || icode == CODE_FOR_altivec_stvx_v2di_2op
14627 || icode == CODE_FOR_altivec_stvx_v4sf_2op
14628 || icode == CODE_FOR_altivec_stvx_v4si_2op
14629 || icode == CODE_FOR_altivec_stvx_v8hi_2op
14630 || icode == CODE_FOR_altivec_stvx_v16qi_2op)
14632 if (op1 == const0_rtx)
14636 op1 = copy_to_mode_reg (mode1, op1);
14637 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
14640 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
14641 addr = gen_rtx_MEM (tmode, addr);
14643 op0 = copy_to_mode_reg (tmode, op0);
14645 /* For -maltivec=be, emit a permute to swap the elements, followed
14647 if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG)
14649 rtx temp = gen_reg_rtx (tmode);
14650 rtx sel = swap_selector_for_mode (tmode);
14651 rtx vperm = gen_rtx_UNSPEC (tmode, gen_rtvec (3, op0, op0, sel),
14653 emit_insn (gen_rtx_SET (temp, vperm));
14654 emit_insn (gen_rtx_SET (addr, temp));
14657 emit_insn (gen_rtx_SET (addr, op0));
14661 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
14662 op0 = copy_to_mode_reg (smode, op0);
14664 if (op1 == const0_rtx)
14665 addr = gen_rtx_MEM (tmode, op2);
14668 op1 = copy_to_mode_reg (mode1, op1);
14669 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
14672 pat = GEN_FCN (icode) (addr, op0);
14680 /* Return the appropriate SPR number associated with the given builtin. */
14681 static inline HOST_WIDE_INT
14682 htm_spr_num (enum rs6000_builtins code)
14684 if (code == HTM_BUILTIN_GET_TFHAR
14685 || code == HTM_BUILTIN_SET_TFHAR)
14687 else if (code == HTM_BUILTIN_GET_TFIAR
14688 || code == HTM_BUILTIN_SET_TFIAR)
14690 else if (code == HTM_BUILTIN_GET_TEXASR
14691 || code == HTM_BUILTIN_SET_TEXASR)
14693 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
14694 || code == HTM_BUILTIN_SET_TEXASRU);
14695 return TEXASRU_SPR;
14698 /* Return the appropriate SPR regno associated with the given builtin. */
14699 static inline HOST_WIDE_INT
14700 htm_spr_regno (enum rs6000_builtins code)
14702 if (code == HTM_BUILTIN_GET_TFHAR
14703 || code == HTM_BUILTIN_SET_TFHAR)
14704 return TFHAR_REGNO;
14705 else if (code == HTM_BUILTIN_GET_TFIAR
14706 || code == HTM_BUILTIN_SET_TFIAR)
14707 return TFIAR_REGNO;
14708 gcc_assert (code == HTM_BUILTIN_GET_TEXASR
14709 || code == HTM_BUILTIN_SET_TEXASR
14710 || code == HTM_BUILTIN_GET_TEXASRU
14711 || code == HTM_BUILTIN_SET_TEXASRU);
14712 return TEXASR_REGNO;
14715 /* Return the correct ICODE value depending on whether we are
14716 setting or reading the HTM SPRs. */
14717 static inline enum insn_code
14718 rs6000_htm_spr_icode (bool nonvoid)
14721 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
14723 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
14726 /* Expand the HTM builtin in EXP and store the result in TARGET.
14727 Store true in *EXPANDEDP if we found a builtin to expand. */
14729 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
14731 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14732 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
14733 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14734 const struct builtin_description *d;
14739 if (!TARGET_POWERPC64
14740 && (fcode == HTM_BUILTIN_TABORTDC
14741 || fcode == HTM_BUILTIN_TABORTDCI))
14743 size_t uns_fcode = (size_t)fcode;
14744 const char *name = rs6000_builtin_info[uns_fcode].name;
14745 error ("builtin %qs is only valid in 64-bit mode", name);
14749 /* Expand the HTM builtins. */
14751 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
14752 if (d->code == fcode)
14754 rtx op[MAX_HTM_OPERANDS], pat;
14757 call_expr_arg_iterator iter;
14758 unsigned attr = rs6000_builtin_info[fcode].attr;
14759 enum insn_code icode = d->icode;
14760 const struct insn_operand_data *insn_op;
14761 bool uses_spr = (attr & RS6000_BTC_SPR);
14765 icode = rs6000_htm_spr_icode (nonvoid);
14766 insn_op = &insn_data[icode].operand[0];
14770 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
14772 || GET_MODE (target) != tmode
14773 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
14774 target = gen_reg_rtx (tmode);
14776 op[nopnds++] = target;
14779 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
14781 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
14784 insn_op = &insn_data[icode].operand[nopnds];
14786 op[nopnds] = expand_normal (arg);
14788 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
14790 if (!strcmp (insn_op->constraint, "n"))
14792 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
14793 if (!CONST_INT_P (op[nopnds]))
14794 error ("argument %d must be an unsigned literal", arg_num);
14796 error ("argument %d is an unsigned literal that is "
14797 "out of range", arg_num);
14800 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
14806 /* Handle the builtins for extended mnemonics. These accept
14807 no arguments, but map to builtins that take arguments. */
14810 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
14811 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
14812 op[nopnds++] = GEN_INT (1);
14814 attr |= RS6000_BTC_UNARY;
14816 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
14817 op[nopnds++] = GEN_INT (0);
14819 attr |= RS6000_BTC_UNARY;
14825 /* If this builtin accesses SPRs, then pass in the appropriate
14826 SPR number and SPR regno as the last two operands. */
14829 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
14830 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
14831 op[nopnds++] = gen_rtx_REG (mode, htm_spr_regno (fcode));
14833 /* If this builtin accesses a CR, then pass in a scratch
14834 CR as the last operand. */
14835 else if (attr & RS6000_BTC_CR)
14836 { cr = gen_reg_rtx (CCmode);
14842 int expected_nopnds = 0;
14843 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
14844 expected_nopnds = 1;
14845 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
14846 expected_nopnds = 2;
14847 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
14848 expected_nopnds = 3;
14849 if (!(attr & RS6000_BTC_VOID))
14850 expected_nopnds += 1;
14852 expected_nopnds += 2;
14854 gcc_assert (nopnds == expected_nopnds
14855 && nopnds <= MAX_HTM_OPERANDS);
14861 pat = GEN_FCN (icode) (op[0]);
14864 pat = GEN_FCN (icode) (op[0], op[1]);
14867 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
14870 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
14873 gcc_unreachable ();
14879 if (attr & RS6000_BTC_CR)
14881 if (fcode == HTM_BUILTIN_TBEGIN)
14883 /* Emit code to set TARGET to true or false depending on
14884 whether the tbegin. instruction successfully or failed
14885 to start a transaction. We do this by placing the 1's
14886 complement of CR's EQ bit into TARGET. */
14887 rtx scratch = gen_reg_rtx (SImode);
14888 emit_insn (gen_rtx_SET (scratch,
14889 gen_rtx_EQ (SImode, cr,
14891 emit_insn (gen_rtx_SET (target,
14892 gen_rtx_XOR (SImode, scratch,
14897 /* Emit code to copy the 4-bit condition register field
14898 CR into the least significant end of register TARGET. */
14899 rtx scratch1 = gen_reg_rtx (SImode);
14900 rtx scratch2 = gen_reg_rtx (SImode);
14901 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
14902 emit_insn (gen_movcc (subreg, cr));
14903 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
14904 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
14913 *expandedp = false;
14917 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14920 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
14923 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14924 if (fcode == RS6000_BUILTIN_CPU_INIT)
14927 if (target == 0 || GET_MODE (target) != SImode)
14928 target = gen_reg_rtx (SImode);
14930 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14931 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
14932 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
14933 to a STRING_CST. */
14934 if (TREE_CODE (arg) == ARRAY_REF
14935 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
14936 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
14937 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
14938 arg = TREE_OPERAND (arg, 0);
14940 if (TREE_CODE (arg) != STRING_CST)
14942 error ("builtin %qs only accepts a string argument",
14943 rs6000_builtin_info[(size_t) fcode].name);
14947 if (fcode == RS6000_BUILTIN_CPU_IS)
14949 const char *cpu = TREE_STRING_POINTER (arg);
14950 rtx cpuid = NULL_RTX;
14951 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
14952 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
14954 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14955 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
14958 if (cpuid == NULL_RTX)
14960 /* Invalid CPU argument. */
14961 error ("cpu %qs is an invalid argument to builtin %qs",
14962 cpu, rs6000_builtin_info[(size_t) fcode].name);
14966 rtx platform = gen_reg_rtx (SImode);
14967 rtx tcbmem = gen_const_mem (SImode,
14968 gen_rtx_PLUS (Pmode,
14969 gen_rtx_REG (Pmode, TLS_REGNUM),
14970 GEN_INT (TCB_PLATFORM_OFFSET)));
14971 emit_move_insn (platform, tcbmem);
14972 emit_insn (gen_eqsi3 (target, platform, cpuid));
14974 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
14976 const char *hwcap = TREE_STRING_POINTER (arg);
14977 rtx mask = NULL_RTX;
14979 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
14980 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
14982 mask = GEN_INT (cpu_supports_info[i].mask);
14983 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
14986 if (mask == NULL_RTX)
14988 /* Invalid HWCAP argument. */
14989 error ("%s %qs is an invalid argument to builtin %qs",
14990 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
14994 rtx tcb_hwcap = gen_reg_rtx (SImode);
14995 rtx tcbmem = gen_const_mem (SImode,
14996 gen_rtx_PLUS (Pmode,
14997 gen_rtx_REG (Pmode, TLS_REGNUM),
14998 GEN_INT (hwcap_offset)));
14999 emit_move_insn (tcb_hwcap, tcbmem);
15000 rtx scratch1 = gen_reg_rtx (SImode);
15001 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
15002 rtx scratch2 = gen_reg_rtx (SImode);
15003 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
15004 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
15007 gcc_unreachable ();
15009 /* Record that we have expanded a CPU builtin, so that we can later
15010 emit a reference to the special symbol exported by LIBC to ensure we
15011 do not link against an old LIBC that doesn't support this feature. */
15012 cpu_builtin_p = true;
15015 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
15016 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
15018 /* For old LIBCs, always return FALSE. */
15019 emit_move_insn (target, GEN_INT (0));
15020 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
15026 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
15029 tree arg0 = CALL_EXPR_ARG (exp, 0);
15030 tree arg1 = CALL_EXPR_ARG (exp, 1);
15031 tree arg2 = CALL_EXPR_ARG (exp, 2);
15032 rtx op0 = expand_normal (arg0);
15033 rtx op1 = expand_normal (arg1);
15034 rtx op2 = expand_normal (arg2);
15035 machine_mode tmode = insn_data[icode].operand[0].mode;
15036 machine_mode mode0 = insn_data[icode].operand[1].mode;
15037 machine_mode mode1 = insn_data[icode].operand[2].mode;
15038 machine_mode mode2 = insn_data[icode].operand[3].mode;
15040 if (icode == CODE_FOR_nothing)
15041 /* Builtin not supported on this processor. */
15044 /* If we got invalid arguments bail out before generating bad rtl. */
15045 if (arg0 == error_mark_node
15046 || arg1 == error_mark_node
15047 || arg2 == error_mark_node)
15050 /* Check and prepare argument depending on the instruction code.
15052 Note that a switch statement instead of the sequence of tests
15053 would be incorrect as many of the CODE_FOR values could be
15054 CODE_FOR_nothing and that would yield multiple alternatives
15055 with identical values. We'd never reach here at runtime in
15057 if (icode == CODE_FOR_altivec_vsldoi_v4sf
15058 || icode == CODE_FOR_altivec_vsldoi_v2df
15059 || icode == CODE_FOR_altivec_vsldoi_v4si
15060 || icode == CODE_FOR_altivec_vsldoi_v8hi
15061 || icode == CODE_FOR_altivec_vsldoi_v16qi)
15063 /* Only allow 4-bit unsigned literals. */
15065 if (TREE_CODE (arg2) != INTEGER_CST
15066 || TREE_INT_CST_LOW (arg2) & ~0xf)
15068 error ("argument 3 must be a 4-bit unsigned literal");
15069 return CONST0_RTX (tmode);
15072 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
15073 || icode == CODE_FOR_vsx_xxpermdi_v2di
15074 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
15075 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
15076 || icode == CODE_FOR_vsx_xxpermdi_v1ti
15077 || icode == CODE_FOR_vsx_xxpermdi_v4sf
15078 || icode == CODE_FOR_vsx_xxpermdi_v4si
15079 || icode == CODE_FOR_vsx_xxpermdi_v8hi
15080 || icode == CODE_FOR_vsx_xxpermdi_v16qi
15081 || icode == CODE_FOR_vsx_xxsldwi_v16qi
15082 || icode == CODE_FOR_vsx_xxsldwi_v8hi
15083 || icode == CODE_FOR_vsx_xxsldwi_v4si
15084 || icode == CODE_FOR_vsx_xxsldwi_v4sf
15085 || icode == CODE_FOR_vsx_xxsldwi_v2di
15086 || icode == CODE_FOR_vsx_xxsldwi_v2df)
15088 /* Only allow 2-bit unsigned literals. */
15090 if (TREE_CODE (arg2) != INTEGER_CST
15091 || TREE_INT_CST_LOW (arg2) & ~0x3)
15093 error ("argument 3 must be a 2-bit unsigned literal");
15094 return CONST0_RTX (tmode);
15097 else if (icode == CODE_FOR_vsx_set_v2df
15098 || icode == CODE_FOR_vsx_set_v2di
15099 || icode == CODE_FOR_bcdadd
15100 || icode == CODE_FOR_bcdadd_lt
15101 || icode == CODE_FOR_bcdadd_eq
15102 || icode == CODE_FOR_bcdadd_gt
15103 || icode == CODE_FOR_bcdsub
15104 || icode == CODE_FOR_bcdsub_lt
15105 || icode == CODE_FOR_bcdsub_eq
15106 || icode == CODE_FOR_bcdsub_gt)
15108 /* Only allow 1-bit unsigned literals. */
15110 if (TREE_CODE (arg2) != INTEGER_CST
15111 || TREE_INT_CST_LOW (arg2) & ~0x1)
15113 error ("argument 3 must be a 1-bit unsigned literal");
15114 return CONST0_RTX (tmode);
15117 else if (icode == CODE_FOR_dfp_ddedpd_dd
15118 || icode == CODE_FOR_dfp_ddedpd_td)
15120 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
15122 if (TREE_CODE (arg0) != INTEGER_CST
15123 || TREE_INT_CST_LOW (arg2) & ~0x3)
15125 error ("argument 1 must be 0 or 2");
15126 return CONST0_RTX (tmode);
15129 else if (icode == CODE_FOR_dfp_denbcd_dd
15130 || icode == CODE_FOR_dfp_denbcd_td)
15132 /* Only allow 1-bit unsigned literals. */
15134 if (TREE_CODE (arg0) != INTEGER_CST
15135 || TREE_INT_CST_LOW (arg0) & ~0x1)
15137 error ("argument 1 must be a 1-bit unsigned literal");
15138 return CONST0_RTX (tmode);
15141 else if (icode == CODE_FOR_dfp_dscli_dd
15142 || icode == CODE_FOR_dfp_dscli_td
15143 || icode == CODE_FOR_dfp_dscri_dd
15144 || icode == CODE_FOR_dfp_dscri_td)
15146 /* Only allow 6-bit unsigned literals. */
15148 if (TREE_CODE (arg1) != INTEGER_CST
15149 || TREE_INT_CST_LOW (arg1) & ~0x3f)
15151 error ("argument 2 must be a 6-bit unsigned literal");
15152 return CONST0_RTX (tmode);
15155 else if (icode == CODE_FOR_crypto_vshasigmaw
15156 || icode == CODE_FOR_crypto_vshasigmad)
15158 /* Check whether the 2nd and 3rd arguments are integer constants and in
15159 range and prepare arguments. */
15161 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
15163 error ("argument 2 must be 0 or 1");
15164 return CONST0_RTX (tmode);
15168 if (TREE_CODE (arg2) != INTEGER_CST
15169 || wi::geu_p (wi::to_wide (arg2), 16))
15171 error ("argument 3 must be in the range 0..15");
15172 return CONST0_RTX (tmode);
15177 || GET_MODE (target) != tmode
15178 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15179 target = gen_reg_rtx (tmode);
15181 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15182 op0 = copy_to_mode_reg (mode0, op0);
15183 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
15184 op1 = copy_to_mode_reg (mode1, op1);
15185 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
15186 op2 = copy_to_mode_reg (mode2, op2);
15188 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
15189 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
15191 pat = GEN_FCN (icode) (target, op0, op1, op2);
15199 /* Expand the lvx builtins. */
15201 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
15203 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15204 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15206 machine_mode tmode, mode0;
15208 enum insn_code icode;
15212 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
15213 icode = CODE_FOR_vector_altivec_load_v16qi;
15215 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
15216 icode = CODE_FOR_vector_altivec_load_v8hi;
15218 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
15219 icode = CODE_FOR_vector_altivec_load_v4si;
15221 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
15222 icode = CODE_FOR_vector_altivec_load_v4sf;
15224 case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
15225 icode = CODE_FOR_vector_altivec_load_v2df;
15227 case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
15228 icode = CODE_FOR_vector_altivec_load_v2di;
15230 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti:
15231 icode = CODE_FOR_vector_altivec_load_v1ti;
15234 *expandedp = false;
15240 arg0 = CALL_EXPR_ARG (exp, 0);
15241 op0 = expand_normal (arg0);
15242 tmode = insn_data[icode].operand[0].mode;
15243 mode0 = insn_data[icode].operand[1].mode;
15246 || GET_MODE (target) != tmode
15247 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15248 target = gen_reg_rtx (tmode);
15250 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
15251 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15253 pat = GEN_FCN (icode) (target, op0);
15260 /* Expand the stvx builtins. */
15262 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
15265 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15266 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
15268 machine_mode mode0, mode1;
15270 enum insn_code icode;
15274 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
15275 icode = CODE_FOR_vector_altivec_store_v16qi;
15277 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
15278 icode = CODE_FOR_vector_altivec_store_v8hi;
15280 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
15281 icode = CODE_FOR_vector_altivec_store_v4si;
15283 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
15284 icode = CODE_FOR_vector_altivec_store_v4sf;
15286 case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
15287 icode = CODE_FOR_vector_altivec_store_v2df;
15289 case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
15290 icode = CODE_FOR_vector_altivec_store_v2di;
15292 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti:
15293 icode = CODE_FOR_vector_altivec_store_v1ti;
15296 *expandedp = false;
15300 arg0 = CALL_EXPR_ARG (exp, 0);
15301 arg1 = CALL_EXPR_ARG (exp, 1);
15302 op0 = expand_normal (arg0);
15303 op1 = expand_normal (arg1);
15304 mode0 = insn_data[icode].operand[0].mode;
15305 mode1 = insn_data[icode].operand[1].mode;
15307 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15308 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
15309 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
15310 op1 = copy_to_mode_reg (mode1, op1);
15312 pat = GEN_FCN (icode) (op0, op1);
15320 /* Expand the dst builtins. */
15322 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
15325 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15326 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15327 tree arg0, arg1, arg2;
15328 machine_mode mode0, mode1;
15329 rtx pat, op0, op1, op2;
15330 const struct builtin_description *d;
15333 *expandedp = false;
15335 /* Handle DST variants. */
15337 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
15338 if (d->code == fcode)
15340 arg0 = CALL_EXPR_ARG (exp, 0);
15341 arg1 = CALL_EXPR_ARG (exp, 1);
15342 arg2 = CALL_EXPR_ARG (exp, 2);
15343 op0 = expand_normal (arg0);
15344 op1 = expand_normal (arg1);
15345 op2 = expand_normal (arg2);
15346 mode0 = insn_data[d->icode].operand[0].mode;
15347 mode1 = insn_data[d->icode].operand[1].mode;
15349 /* Invalid arguments, bail out before generating bad rtl. */
15350 if (arg0 == error_mark_node
15351 || arg1 == error_mark_node
15352 || arg2 == error_mark_node)
15357 if (TREE_CODE (arg2) != INTEGER_CST
15358 || TREE_INT_CST_LOW (arg2) & ~0x3)
15360 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
15364 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
15365 op0 = copy_to_mode_reg (Pmode, op0);
15366 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
15367 op1 = copy_to_mode_reg (mode1, op1);
15369 pat = GEN_FCN (d->icode) (op0, op1, op2);
15379 /* Expand vec_init builtin. */
15381 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
15383 machine_mode tmode = TYPE_MODE (type);
15384 machine_mode inner_mode = GET_MODE_INNER (tmode);
15385 int i, n_elt = GET_MODE_NUNITS (tmode);
15387 gcc_assert (VECTOR_MODE_P (tmode));
15388 gcc_assert (n_elt == call_expr_nargs (exp));
15390 if (!target || !register_operand (target, tmode))
15391 target = gen_reg_rtx (tmode);
15393 /* If we have a vector compromised of a single element, such as V1TImode, do
15394 the initialization directly. */
15395 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
15397 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
15398 emit_move_insn (target, gen_lowpart (tmode, x));
15402 rtvec v = rtvec_alloc (n_elt);
15404 for (i = 0; i < n_elt; ++i)
15406 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
15407 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
15410 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
15416 /* Return the integer constant in ARG. Constrain it to be in the range
15417 of the subparts of VEC_TYPE; issue an error if not. */
15420 get_element_number (tree vec_type, tree arg)
15422 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
15424 if (!tree_fits_uhwi_p (arg)
15425 || (elt = tree_to_uhwi (arg), elt > max))
15427 error ("selector must be an integer constant in the range 0..%wi", max);
15434 /* Expand vec_set builtin. */
15436 altivec_expand_vec_set_builtin (tree exp)
15438 machine_mode tmode, mode1;
15439 tree arg0, arg1, arg2;
15443 arg0 = CALL_EXPR_ARG (exp, 0);
15444 arg1 = CALL_EXPR_ARG (exp, 1);
15445 arg2 = CALL_EXPR_ARG (exp, 2);
15447 tmode = TYPE_MODE (TREE_TYPE (arg0));
15448 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15449 gcc_assert (VECTOR_MODE_P (tmode));
15451 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
15452 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
15453 elt = get_element_number (TREE_TYPE (arg0), arg2);
15455 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
15456 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
15458 op0 = force_reg (tmode, op0);
15459 op1 = force_reg (mode1, op1);
15461 rs6000_expand_vector_set (op0, op1, elt);
15466 /* Expand vec_ext builtin. */
15468 altivec_expand_vec_ext_builtin (tree exp, rtx target)
15470 machine_mode tmode, mode0;
15475 arg0 = CALL_EXPR_ARG (exp, 0);
15476 arg1 = CALL_EXPR_ARG (exp, 1);
15478 op0 = expand_normal (arg0);
15479 op1 = expand_normal (arg1);
15481 /* Call get_element_number to validate arg1 if it is a constant. */
15482 if (TREE_CODE (arg1) == INTEGER_CST)
15483 (void) get_element_number (TREE_TYPE (arg0), arg1);
15485 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
15486 mode0 = TYPE_MODE (TREE_TYPE (arg0));
15487 gcc_assert (VECTOR_MODE_P (mode0));
15489 op0 = force_reg (mode0, op0);
15491 if (optimize || !target || !register_operand (target, tmode))
15492 target = gen_reg_rtx (tmode);
15494 rs6000_expand_vector_extract (target, op0, op1);
15499 /* Expand the builtin in EXP and store the result in TARGET. Store
15500 true in *EXPANDEDP if we found a builtin to expand. */
15502 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
15504 const struct builtin_description *d;
15506 enum insn_code icode;
15507 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15508 tree arg0, arg1, arg2;
15510 machine_mode tmode, mode0;
15511 enum rs6000_builtins fcode
15512 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15514 if (rs6000_overloaded_builtin_p (fcode))
15517 error ("unresolved overload for Altivec builtin %qF", fndecl);
15519 /* Given it is invalid, just generate a normal call. */
15520 return expand_call (exp, target, false);
15523 target = altivec_expand_ld_builtin (exp, target, expandedp);
15527 target = altivec_expand_st_builtin (exp, target, expandedp);
15531 target = altivec_expand_dst_builtin (exp, target, expandedp);
15539 case ALTIVEC_BUILTIN_STVX_V2DF:
15540 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df_2op, exp);
15541 case ALTIVEC_BUILTIN_STVX_V2DI:
15542 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di_2op, exp);
15543 case ALTIVEC_BUILTIN_STVX_V4SF:
15544 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf_2op, exp);
15545 case ALTIVEC_BUILTIN_STVX:
15546 case ALTIVEC_BUILTIN_STVX_V4SI:
15547 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si_2op, exp);
15548 case ALTIVEC_BUILTIN_STVX_V8HI:
15549 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi_2op, exp);
15550 case ALTIVEC_BUILTIN_STVX_V16QI:
15551 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi_2op, exp);
15552 case ALTIVEC_BUILTIN_STVEBX:
15553 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
15554 case ALTIVEC_BUILTIN_STVEHX:
15555 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
15556 case ALTIVEC_BUILTIN_STVEWX:
15557 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
15558 case ALTIVEC_BUILTIN_STVXL_V2DF:
15559 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
15560 case ALTIVEC_BUILTIN_STVXL_V2DI:
15561 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
15562 case ALTIVEC_BUILTIN_STVXL_V4SF:
15563 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
15564 case ALTIVEC_BUILTIN_STVXL:
15565 case ALTIVEC_BUILTIN_STVXL_V4SI:
15566 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
15567 case ALTIVEC_BUILTIN_STVXL_V8HI:
15568 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
15569 case ALTIVEC_BUILTIN_STVXL_V16QI:
15570 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
15572 case ALTIVEC_BUILTIN_STVLX:
15573 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
15574 case ALTIVEC_BUILTIN_STVLXL:
15575 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
15576 case ALTIVEC_BUILTIN_STVRX:
15577 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
15578 case ALTIVEC_BUILTIN_STVRXL:
15579 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
15581 case P9V_BUILTIN_STXVL:
15582 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
15584 case P9V_BUILTIN_XST_LEN_R:
15585 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
15587 case VSX_BUILTIN_STXVD2X_V1TI:
15588 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
15589 case VSX_BUILTIN_STXVD2X_V2DF:
15590 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
15591 case VSX_BUILTIN_STXVD2X_V2DI:
15592 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
15593 case VSX_BUILTIN_STXVW4X_V4SF:
15594 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
15595 case VSX_BUILTIN_STXVW4X_V4SI:
15596 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
15597 case VSX_BUILTIN_STXVW4X_V8HI:
15598 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
15599 case VSX_BUILTIN_STXVW4X_V16QI:
15600 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
15602 /* For the following on big endian, it's ok to use any appropriate
15603 unaligned-supporting store, so use a generic expander. For
15604 little-endian, the exact element-reversing instruction must
15606 case VSX_BUILTIN_ST_ELEMREV_V1TI:
15608 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
15609 : CODE_FOR_vsx_st_elemrev_v1ti);
15610 return altivec_expand_stv_builtin (code, exp);
15612 case VSX_BUILTIN_ST_ELEMREV_V2DF:
15614 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
15615 : CODE_FOR_vsx_st_elemrev_v2df);
15616 return altivec_expand_stv_builtin (code, exp);
15618 case VSX_BUILTIN_ST_ELEMREV_V2DI:
15620 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
15621 : CODE_FOR_vsx_st_elemrev_v2di);
15622 return altivec_expand_stv_builtin (code, exp);
15624 case VSX_BUILTIN_ST_ELEMREV_V4SF:
15626 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
15627 : CODE_FOR_vsx_st_elemrev_v4sf);
15628 return altivec_expand_stv_builtin (code, exp);
15630 case VSX_BUILTIN_ST_ELEMREV_V4SI:
15632 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
15633 : CODE_FOR_vsx_st_elemrev_v4si);
15634 return altivec_expand_stv_builtin (code, exp);
15636 case VSX_BUILTIN_ST_ELEMREV_V8HI:
15638 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
15639 : CODE_FOR_vsx_st_elemrev_v8hi);
15640 return altivec_expand_stv_builtin (code, exp);
15642 case VSX_BUILTIN_ST_ELEMREV_V16QI:
15644 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
15645 : CODE_FOR_vsx_st_elemrev_v16qi);
15646 return altivec_expand_stv_builtin (code, exp);
15649 case ALTIVEC_BUILTIN_MFVSCR:
15650 icode = CODE_FOR_altivec_mfvscr;
15651 tmode = insn_data[icode].operand[0].mode;
15654 || GET_MODE (target) != tmode
15655 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
15656 target = gen_reg_rtx (tmode);
15658 pat = GEN_FCN (icode) (target);
15664 case ALTIVEC_BUILTIN_MTVSCR:
15665 icode = CODE_FOR_altivec_mtvscr;
15666 arg0 = CALL_EXPR_ARG (exp, 0);
15667 op0 = expand_normal (arg0);
15668 mode0 = insn_data[icode].operand[0].mode;
15670 /* If we got invalid arguments bail out before generating bad rtl. */
15671 if (arg0 == error_mark_node)
15674 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15675 op0 = copy_to_mode_reg (mode0, op0);
15677 pat = GEN_FCN (icode) (op0);
15682 case ALTIVEC_BUILTIN_DSSALL:
15683 emit_insn (gen_altivec_dssall ());
15686 case ALTIVEC_BUILTIN_DSS:
15687 icode = CODE_FOR_altivec_dss;
15688 arg0 = CALL_EXPR_ARG (exp, 0);
15690 op0 = expand_normal (arg0);
15691 mode0 = insn_data[icode].operand[0].mode;
15693 /* If we got invalid arguments bail out before generating bad rtl. */
15694 if (arg0 == error_mark_node)
15697 if (TREE_CODE (arg0) != INTEGER_CST
15698 || TREE_INT_CST_LOW (arg0) & ~0x3)
15700 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
15704 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
15705 op0 = copy_to_mode_reg (mode0, op0);
15707 emit_insn (gen_altivec_dss (op0));
15710 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
15711 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
15712 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
15713 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
15714 case VSX_BUILTIN_VEC_INIT_V2DF:
15715 case VSX_BUILTIN_VEC_INIT_V2DI:
15716 case VSX_BUILTIN_VEC_INIT_V1TI:
15717 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
15719 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
15720 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
15721 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
15722 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
15723 case VSX_BUILTIN_VEC_SET_V2DF:
15724 case VSX_BUILTIN_VEC_SET_V2DI:
15725 case VSX_BUILTIN_VEC_SET_V1TI:
15726 return altivec_expand_vec_set_builtin (exp);
15728 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
15729 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
15730 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
15731 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
15732 case VSX_BUILTIN_VEC_EXT_V2DF:
15733 case VSX_BUILTIN_VEC_EXT_V2DI:
15734 case VSX_BUILTIN_VEC_EXT_V1TI:
15735 return altivec_expand_vec_ext_builtin (exp, target);
15737 case P9V_BUILTIN_VEXTRACT4B:
15738 case P9V_BUILTIN_VEC_VEXTRACT4B:
15739 arg1 = CALL_EXPR_ARG (exp, 1);
15742 /* Generate a normal call if it is invalid. */
15743 if (arg1 == error_mark_node)
15744 return expand_call (exp, target, false);
15746 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
15748 error ("second argument to %qs must be 0..12", "vec_vextract4b");
15749 return expand_call (exp, target, false);
15753 case P9V_BUILTIN_VINSERT4B:
15754 case P9V_BUILTIN_VINSERT4B_DI:
15755 case P9V_BUILTIN_VEC_VINSERT4B:
15756 arg2 = CALL_EXPR_ARG (exp, 2);
15759 /* Generate a normal call if it is invalid. */
15760 if (arg2 == error_mark_node)
15761 return expand_call (exp, target, false);
15763 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
15765 error ("third argument to %qs must be 0..12", "vec_vinsert4b");
15766 return expand_call (exp, target, false);
15772 /* Fall through. */
15775 /* Expand abs* operations. */
15777 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
15778 if (d->code == fcode)
15779 return altivec_expand_abs_builtin (d->icode, exp, target);
15781 /* Expand the AltiVec predicates. */
15782 d = bdesc_altivec_preds;
15783 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
15784 if (d->code == fcode)
15785 return altivec_expand_predicate_builtin (d->icode, exp, target);
15787 /* LV* are funky. We initialized them differently. */
15790 case ALTIVEC_BUILTIN_LVSL:
15791 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
15792 exp, target, false);
15793 case ALTIVEC_BUILTIN_LVSR:
15794 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
15795 exp, target, false);
15796 case ALTIVEC_BUILTIN_LVEBX:
15797 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
15798 exp, target, false);
15799 case ALTIVEC_BUILTIN_LVEHX:
15800 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
15801 exp, target, false);
15802 case ALTIVEC_BUILTIN_LVEWX:
15803 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
15804 exp, target, false);
15805 case ALTIVEC_BUILTIN_LVXL_V2DF:
15806 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
15807 exp, target, false);
15808 case ALTIVEC_BUILTIN_LVXL_V2DI:
15809 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
15810 exp, target, false);
15811 case ALTIVEC_BUILTIN_LVXL_V4SF:
15812 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
15813 exp, target, false);
15814 case ALTIVEC_BUILTIN_LVXL:
15815 case ALTIVEC_BUILTIN_LVXL_V4SI:
15816 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
15817 exp, target, false);
15818 case ALTIVEC_BUILTIN_LVXL_V8HI:
15819 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
15820 exp, target, false);
15821 case ALTIVEC_BUILTIN_LVXL_V16QI:
15822 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
15823 exp, target, false);
15824 case ALTIVEC_BUILTIN_LVX_V2DF:
15825 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df_2op,
15826 exp, target, false);
15827 case ALTIVEC_BUILTIN_LVX_V2DI:
15828 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di_2op,
15829 exp, target, false);
15830 case ALTIVEC_BUILTIN_LVX_V4SF:
15831 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf_2op,
15832 exp, target, false);
15833 case ALTIVEC_BUILTIN_LVX:
15834 case ALTIVEC_BUILTIN_LVX_V4SI:
15835 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si_2op,
15836 exp, target, false);
15837 case ALTIVEC_BUILTIN_LVX_V8HI:
15838 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi_2op,
15839 exp, target, false);
15840 case ALTIVEC_BUILTIN_LVX_V16QI:
15841 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi_2op,
15842 exp, target, false);
15843 case ALTIVEC_BUILTIN_LVLX:
15844 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
15845 exp, target, true);
15846 case ALTIVEC_BUILTIN_LVLXL:
15847 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
15848 exp, target, true);
15849 case ALTIVEC_BUILTIN_LVRX:
15850 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
15851 exp, target, true);
15852 case ALTIVEC_BUILTIN_LVRXL:
15853 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
15854 exp, target, true);
15855 case VSX_BUILTIN_LXVD2X_V1TI:
15856 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
15857 exp, target, false);
15858 case VSX_BUILTIN_LXVD2X_V2DF:
15859 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
15860 exp, target, false);
15861 case VSX_BUILTIN_LXVD2X_V2DI:
15862 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
15863 exp, target, false);
15864 case VSX_BUILTIN_LXVW4X_V4SF:
15865 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
15866 exp, target, false);
15867 case VSX_BUILTIN_LXVW4X_V4SI:
15868 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
15869 exp, target, false);
15870 case VSX_BUILTIN_LXVW4X_V8HI:
15871 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
15872 exp, target, false);
15873 case VSX_BUILTIN_LXVW4X_V16QI:
15874 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
15875 exp, target, false);
15876 /* For the following on big endian, it's ok to use any appropriate
15877 unaligned-supporting load, so use a generic expander. For
15878 little-endian, the exact element-reversing instruction must
15880 case VSX_BUILTIN_LD_ELEMREV_V2DF:
15882 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
15883 : CODE_FOR_vsx_ld_elemrev_v2df);
15884 return altivec_expand_lv_builtin (code, exp, target, false);
15886 case VSX_BUILTIN_LD_ELEMREV_V1TI:
15888 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
15889 : CODE_FOR_vsx_ld_elemrev_v1ti);
15890 return altivec_expand_lv_builtin (code, exp, target, false);
15892 case VSX_BUILTIN_LD_ELEMREV_V2DI:
15894 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
15895 : CODE_FOR_vsx_ld_elemrev_v2di);
15896 return altivec_expand_lv_builtin (code, exp, target, false);
15898 case VSX_BUILTIN_LD_ELEMREV_V4SF:
15900 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
15901 : CODE_FOR_vsx_ld_elemrev_v4sf);
15902 return altivec_expand_lv_builtin (code, exp, target, false);
15904 case VSX_BUILTIN_LD_ELEMREV_V4SI:
15906 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
15907 : CODE_FOR_vsx_ld_elemrev_v4si);
15908 return altivec_expand_lv_builtin (code, exp, target, false);
15910 case VSX_BUILTIN_LD_ELEMREV_V8HI:
15912 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
15913 : CODE_FOR_vsx_ld_elemrev_v8hi);
15914 return altivec_expand_lv_builtin (code, exp, target, false);
15916 case VSX_BUILTIN_LD_ELEMREV_V16QI:
15918 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
15919 : CODE_FOR_vsx_ld_elemrev_v16qi);
15920 return altivec_expand_lv_builtin (code, exp, target, false);
15925 /* Fall through. */
15928 *expandedp = false;
15932 /* Expand the builtin in EXP and store the result in TARGET. Store
15933 true in *EXPANDEDP if we found a builtin to expand. */
15935 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
15937 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15938 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15939 const struct builtin_description *d;
15946 case PAIRED_BUILTIN_STX:
15947 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
15948 case PAIRED_BUILTIN_LX:
15949 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
15952 /* Fall through. */
15955 /* Expand the paired predicates. */
15956 d = bdesc_paired_preds;
15957 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
15958 if (d->code == fcode)
15959 return paired_expand_predicate_builtin (d->icode, exp, target);
15961 *expandedp = false;
15966 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
15968 rtx pat, scratch, tmp;
15969 tree form = CALL_EXPR_ARG (exp, 0);
15970 tree arg0 = CALL_EXPR_ARG (exp, 1);
15971 tree arg1 = CALL_EXPR_ARG (exp, 2);
15972 rtx op0 = expand_normal (arg0);
15973 rtx op1 = expand_normal (arg1);
15974 machine_mode mode0 = insn_data[icode].operand[1].mode;
15975 machine_mode mode1 = insn_data[icode].operand[2].mode;
15977 enum rtx_code code;
15979 if (TREE_CODE (form) != INTEGER_CST)
15981 error ("argument 1 of %s must be a constant",
15982 "__builtin_paired_predicate");
15986 form_int = TREE_INT_CST_LOW (form);
15988 gcc_assert (mode0 == mode1);
15990 if (arg0 == error_mark_node || arg1 == error_mark_node)
15994 || GET_MODE (target) != SImode
15995 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
15996 target = gen_reg_rtx (SImode);
15997 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
15998 op0 = copy_to_mode_reg (mode0, op0);
15999 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
16000 op1 = copy_to_mode_reg (mode1, op1);
16002 scratch = gen_reg_rtx (CCFPmode);
16004 pat = GEN_FCN (icode) (scratch, op0, op1);
16026 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
16029 error ("argument 1 of %qs is out of range",
16030 "__builtin_paired_predicate");
16034 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
16035 emit_move_insn (target, tmp);
16039 /* Raise an error message for a builtin function that is called without the
16040 appropriate target options being set. */
16043 rs6000_invalid_builtin (enum rs6000_builtins fncode)
16045 size_t uns_fncode = (size_t) fncode;
16046 const char *name = rs6000_builtin_info[uns_fncode].name;
16047 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
16049 gcc_assert (name != NULL);
16050 if ((fnmask & RS6000_BTM_CELL) != 0)
16051 error ("builtin function %qs is only valid for the cell processor", name);
16052 else if ((fnmask & RS6000_BTM_VSX) != 0)
16053 error ("builtin function %qs requires the %qs option", name, "-mvsx");
16054 else if ((fnmask & RS6000_BTM_HTM) != 0)
16055 error ("builtin function %qs requires the %qs option", name, "-mhtm");
16056 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
16057 error ("builtin function %qs requires the %qs option", name, "-maltivec");
16058 else if ((fnmask & RS6000_BTM_PAIRED) != 0)
16059 error ("builtin function %qs requires the %qs option", name, "-mpaired");
16060 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
16061 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
16062 error ("builtin function %qs requires the %qs and %qs options",
16063 name, "-mhard-dfp", "-mpower8-vector");
16064 else if ((fnmask & RS6000_BTM_DFP) != 0)
16065 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
16066 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
16067 error ("builtin function %qs requires the %qs option", name,
16068 "-mpower8-vector");
16069 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
16070 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
16071 error ("builtin function %qs requires the %qs and %qs options",
16072 name, "-mcpu=power9", "-m64");
16073 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
16074 error ("builtin function %qs requires the %qs option", name,
16076 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
16077 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
16078 error ("builtin function %qs requires the %qs and %qs options",
16079 name, "-mcpu=power9", "-m64");
16080 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
16081 error ("builtin function %qs requires the %qs option", name,
16083 else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
16084 == (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
16085 error ("builtin function %qs requires the %qs and %qs options",
16086 name, "-mhard-float", "-mlong-double-128");
16087 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
16088 error ("builtin function %qs requires the %qs option", name,
16090 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
16091 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
16093 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
16094 error ("builtin function %qs requires the %qs option", name, "-mfloat128");
16096 error ("builtin function %qs is not supported with the current options",
16100 /* Target hook for early folding of built-ins, shamelessly stolen
16104 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
16105 int n_args ATTRIBUTE_UNUSED,
16106 tree *args ATTRIBUTE_UNUSED,
16107 bool ignore ATTRIBUTE_UNUSED)
16109 #ifdef SUBTARGET_FOLD_BUILTIN
16110 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
16116 /* Helper function to sort out which built-ins may be valid without having
16119 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
16123 case ALTIVEC_BUILTIN_STVX_V16QI:
16124 case ALTIVEC_BUILTIN_STVX_V8HI:
16125 case ALTIVEC_BUILTIN_STVX_V4SI:
16126 case ALTIVEC_BUILTIN_STVX_V4SF:
16127 case ALTIVEC_BUILTIN_STVX_V2DI:
16128 case ALTIVEC_BUILTIN_STVX_V2DF:
16135 /* Helper function to handle the gimple folding of a vector compare
16136 operation. This sets up true/false vectors, and uses the
16137 VEC_COND_EXPR operation.
16138 CODE indicates which comparison is to be made. (EQ, GT, ...).
16139 TYPE indicates the type of the result. */
16141 fold_build_vec_cmp (tree_code code, tree type,
16142 tree arg0, tree arg1)
16144 tree cmp_type = build_same_sized_truth_vector_type (type);
16145 tree zero_vec = build_zero_cst (type);
16146 tree minus_one_vec = build_minus_one_cst (type);
16147 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
16148 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
16151 /* Helper function to handle the in-between steps for the
16152 vector compare built-ins. */
16154 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
16156 tree arg0 = gimple_call_arg (stmt, 0);
16157 tree arg1 = gimple_call_arg (stmt, 1);
16158 tree lhs = gimple_call_lhs (stmt);
16159 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
16160 gimple *g = gimple_build_assign (lhs, cmp);
16161 gimple_set_location (g, gimple_location (stmt));
16162 gsi_replace (gsi, g, true);
16165 /* Helper function to handle the vector merge[hl] built-ins. The
16166 implementation difference between h and l versions for this code are in
16167 the values used when building of the permute vector for high word versus
16168 low word merge. The variance is keyed off the use_high parameter. */
16170 fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
16172 tree arg0 = gimple_call_arg (stmt, 0);
16173 tree arg1 = gimple_call_arg (stmt, 1);
16174 tree lhs = gimple_call_lhs (stmt);
16175 tree lhs_type = TREE_TYPE (lhs);
16176 tree lhs_type_type = TREE_TYPE (lhs_type);
16177 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
16178 int midpoint = n_elts / 2;
16184 tree_vector_builder elts (lhs_type, VECTOR_CST_NELTS (arg0), 1);
16186 for (int i = 0; i < midpoint; i++)
16188 elts.safe_push (build_int_cst (lhs_type_type, offset + i));
16189 elts.safe_push (build_int_cst (lhs_type_type, offset + n_elts + i));
16192 tree permute = elts.build ();
16194 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
16195 gimple_set_location (g, gimple_location (stmt));
16196 gsi_replace (gsi, g, true);
16199 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
16200 a constant, use rs6000_fold_builtin.) */
16203 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
16205 gimple *stmt = gsi_stmt (*gsi);
16206 tree fndecl = gimple_call_fndecl (stmt);
16207 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
16208 enum rs6000_builtins fn_code
16209 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
16210 tree arg0, arg1, lhs, temp;
16213 size_t uns_fncode = (size_t) fn_code;
16214 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
16215 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
16216 const char *fn_name2 = (icode != CODE_FOR_nothing)
16217 ? get_insn_name ((int) icode)
16220 if (TARGET_DEBUG_BUILTIN)
16221 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
16222 fn_code, fn_name1, fn_name2);
16224 if (!rs6000_fold_gimple)
16227 /* Prevent gimple folding for code that does not have a LHS, unless it is
16228 allowed per the rs6000_builtin_valid_without_lhs helper function. */
16229 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
16232 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
16233 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
16234 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
16240 /* Flavors of vec_add. We deliberately don't expand
16241 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
16242 TImode, resulting in much poorer code generation. */
16243 case ALTIVEC_BUILTIN_VADDUBM:
16244 case ALTIVEC_BUILTIN_VADDUHM:
16245 case ALTIVEC_BUILTIN_VADDUWM:
16246 case P8V_BUILTIN_VADDUDM:
16247 case ALTIVEC_BUILTIN_VADDFP:
16248 case VSX_BUILTIN_XVADDDP:
16249 arg0 = gimple_call_arg (stmt, 0);
16250 arg1 = gimple_call_arg (stmt, 1);
16251 lhs = gimple_call_lhs (stmt);
16252 g = gimple_build_assign (lhs, PLUS_EXPR, arg0, arg1);
16253 gimple_set_location (g, gimple_location (stmt));
16254 gsi_replace (gsi, g, true);
16256 /* Flavors of vec_sub. We deliberately don't expand
16257 P8V_BUILTIN_VSUBUQM. */
16258 case ALTIVEC_BUILTIN_VSUBUBM:
16259 case ALTIVEC_BUILTIN_VSUBUHM:
16260 case ALTIVEC_BUILTIN_VSUBUWM:
16261 case P8V_BUILTIN_VSUBUDM:
16262 case ALTIVEC_BUILTIN_VSUBFP:
16263 case VSX_BUILTIN_XVSUBDP:
16264 arg0 = gimple_call_arg (stmt, 0);
16265 arg1 = gimple_call_arg (stmt, 1);
16266 lhs = gimple_call_lhs (stmt);
16267 g = gimple_build_assign (lhs, MINUS_EXPR, arg0, arg1);
16268 gimple_set_location (g, gimple_location (stmt));
16269 gsi_replace (gsi, g, true);
16271 case VSX_BUILTIN_XVMULSP:
16272 case VSX_BUILTIN_XVMULDP:
16273 arg0 = gimple_call_arg (stmt, 0);
16274 arg1 = gimple_call_arg (stmt, 1);
16275 lhs = gimple_call_lhs (stmt);
16276 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
16277 gimple_set_location (g, gimple_location (stmt));
16278 gsi_replace (gsi, g, true);
16280 /* Even element flavors of vec_mul (signed). */
16281 case ALTIVEC_BUILTIN_VMULESB:
16282 case ALTIVEC_BUILTIN_VMULESH:
16283 case ALTIVEC_BUILTIN_VMULESW:
16284 /* Even element flavors of vec_mul (unsigned). */
16285 case ALTIVEC_BUILTIN_VMULEUB:
16286 case ALTIVEC_BUILTIN_VMULEUH:
16287 case ALTIVEC_BUILTIN_VMULEUW:
16288 arg0 = gimple_call_arg (stmt, 0);
16289 arg1 = gimple_call_arg (stmt, 1);
16290 lhs = gimple_call_lhs (stmt);
16291 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
16292 gimple_set_location (g, gimple_location (stmt));
16293 gsi_replace (gsi, g, true);
16295 /* Odd element flavors of vec_mul (signed). */
16296 case ALTIVEC_BUILTIN_VMULOSB:
16297 case ALTIVEC_BUILTIN_VMULOSH:
16298 case ALTIVEC_BUILTIN_VMULOSW:
16299 /* Odd element flavors of vec_mul (unsigned). */
16300 case ALTIVEC_BUILTIN_VMULOUB:
16301 case ALTIVEC_BUILTIN_VMULOUH:
16302 case ALTIVEC_BUILTIN_VMULOUW:
16303 arg0 = gimple_call_arg (stmt, 0);
16304 arg1 = gimple_call_arg (stmt, 1);
16305 lhs = gimple_call_lhs (stmt);
16306 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
16307 gimple_set_location (g, gimple_location (stmt));
16308 gsi_replace (gsi, g, true);
16310 /* Flavors of vec_div (Integer). */
16311 case VSX_BUILTIN_DIV_V2DI:
16312 case VSX_BUILTIN_UDIV_V2DI:
16313 arg0 = gimple_call_arg (stmt, 0);
16314 arg1 = gimple_call_arg (stmt, 1);
16315 lhs = gimple_call_lhs (stmt);
16316 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
16317 gimple_set_location (g, gimple_location (stmt));
16318 gsi_replace (gsi, g, true);
16320 /* Flavors of vec_div (Float). */
16321 case VSX_BUILTIN_XVDIVSP:
16322 case VSX_BUILTIN_XVDIVDP:
16323 arg0 = gimple_call_arg (stmt, 0);
16324 arg1 = gimple_call_arg (stmt, 1);
16325 lhs = gimple_call_lhs (stmt);
16326 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
16327 gimple_set_location (g, gimple_location (stmt));
16328 gsi_replace (gsi, g, true);
16330 /* Flavors of vec_and. */
16331 case ALTIVEC_BUILTIN_VAND:
16332 arg0 = gimple_call_arg (stmt, 0);
16333 arg1 = gimple_call_arg (stmt, 1);
16334 lhs = gimple_call_lhs (stmt);
16335 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
16336 gimple_set_location (g, gimple_location (stmt));
16337 gsi_replace (gsi, g, true);
16339 /* Flavors of vec_andc. */
16340 case ALTIVEC_BUILTIN_VANDC:
16341 arg0 = gimple_call_arg (stmt, 0);
16342 arg1 = gimple_call_arg (stmt, 1);
16343 lhs = gimple_call_lhs (stmt);
16344 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16345 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
16346 gimple_set_location (g, gimple_location (stmt));
16347 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16348 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
16349 gimple_set_location (g, gimple_location (stmt));
16350 gsi_replace (gsi, g, true);
16352 /* Flavors of vec_nand. */
16353 case P8V_BUILTIN_VEC_NAND:
16354 case P8V_BUILTIN_NAND_V16QI:
16355 case P8V_BUILTIN_NAND_V8HI:
16356 case P8V_BUILTIN_NAND_V4SI:
16357 case P8V_BUILTIN_NAND_V4SF:
16358 case P8V_BUILTIN_NAND_V2DF:
16359 case P8V_BUILTIN_NAND_V2DI:
16360 arg0 = gimple_call_arg (stmt, 0);
16361 arg1 = gimple_call_arg (stmt, 1);
16362 lhs = gimple_call_lhs (stmt);
16363 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16364 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
16365 gimple_set_location (g, gimple_location (stmt));
16366 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16367 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16368 gimple_set_location (g, gimple_location (stmt));
16369 gsi_replace (gsi, g, true);
16371 /* Flavors of vec_or. */
16372 case ALTIVEC_BUILTIN_VOR:
16373 arg0 = gimple_call_arg (stmt, 0);
16374 arg1 = gimple_call_arg (stmt, 1);
16375 lhs = gimple_call_lhs (stmt);
16376 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
16377 gimple_set_location (g, gimple_location (stmt));
16378 gsi_replace (gsi, g, true);
16380 /* flavors of vec_orc. */
16381 case P8V_BUILTIN_ORC_V16QI:
16382 case P8V_BUILTIN_ORC_V8HI:
16383 case P8V_BUILTIN_ORC_V4SI:
16384 case P8V_BUILTIN_ORC_V4SF:
16385 case P8V_BUILTIN_ORC_V2DF:
16386 case P8V_BUILTIN_ORC_V2DI:
16387 arg0 = gimple_call_arg (stmt, 0);
16388 arg1 = gimple_call_arg (stmt, 1);
16389 lhs = gimple_call_lhs (stmt);
16390 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16391 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
16392 gimple_set_location (g, gimple_location (stmt));
16393 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16394 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
16395 gimple_set_location (g, gimple_location (stmt));
16396 gsi_replace (gsi, g, true);
16398 /* Flavors of vec_xor. */
16399 case ALTIVEC_BUILTIN_VXOR:
16400 arg0 = gimple_call_arg (stmt, 0);
16401 arg1 = gimple_call_arg (stmt, 1);
16402 lhs = gimple_call_lhs (stmt);
16403 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
16404 gimple_set_location (g, gimple_location (stmt));
16405 gsi_replace (gsi, g, true);
16407 /* Flavors of vec_nor. */
16408 case ALTIVEC_BUILTIN_VNOR:
16409 arg0 = gimple_call_arg (stmt, 0);
16410 arg1 = gimple_call_arg (stmt, 1);
16411 lhs = gimple_call_lhs (stmt);
16412 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16413 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
16414 gimple_set_location (g, gimple_location (stmt));
16415 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16416 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16417 gimple_set_location (g, gimple_location (stmt));
16418 gsi_replace (gsi, g, true);
16420 /* flavors of vec_abs. */
16421 case ALTIVEC_BUILTIN_ABS_V16QI:
16422 case ALTIVEC_BUILTIN_ABS_V8HI:
16423 case ALTIVEC_BUILTIN_ABS_V4SI:
16424 case ALTIVEC_BUILTIN_ABS_V4SF:
16425 case P8V_BUILTIN_ABS_V2DI:
16426 case VSX_BUILTIN_XVABSDP:
16427 arg0 = gimple_call_arg (stmt, 0);
16428 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
16429 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
16431 lhs = gimple_call_lhs (stmt);
16432 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
16433 gimple_set_location (g, gimple_location (stmt));
16434 gsi_replace (gsi, g, true);
16436 /* flavors of vec_min. */
16437 case VSX_BUILTIN_XVMINDP:
16438 case P8V_BUILTIN_VMINSD:
16439 case P8V_BUILTIN_VMINUD:
16440 case ALTIVEC_BUILTIN_VMINSB:
16441 case ALTIVEC_BUILTIN_VMINSH:
16442 case ALTIVEC_BUILTIN_VMINSW:
16443 case ALTIVEC_BUILTIN_VMINUB:
16444 case ALTIVEC_BUILTIN_VMINUH:
16445 case ALTIVEC_BUILTIN_VMINUW:
16446 case ALTIVEC_BUILTIN_VMINFP:
16447 arg0 = gimple_call_arg (stmt, 0);
16448 arg1 = gimple_call_arg (stmt, 1);
16449 lhs = gimple_call_lhs (stmt);
16450 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
16451 gimple_set_location (g, gimple_location (stmt));
16452 gsi_replace (gsi, g, true);
16454 /* flavors of vec_max. */
16455 case VSX_BUILTIN_XVMAXDP:
16456 case P8V_BUILTIN_VMAXSD:
16457 case P8V_BUILTIN_VMAXUD:
16458 case ALTIVEC_BUILTIN_VMAXSB:
16459 case ALTIVEC_BUILTIN_VMAXSH:
16460 case ALTIVEC_BUILTIN_VMAXSW:
16461 case ALTIVEC_BUILTIN_VMAXUB:
16462 case ALTIVEC_BUILTIN_VMAXUH:
16463 case ALTIVEC_BUILTIN_VMAXUW:
16464 case ALTIVEC_BUILTIN_VMAXFP:
16465 arg0 = gimple_call_arg (stmt, 0);
16466 arg1 = gimple_call_arg (stmt, 1);
16467 lhs = gimple_call_lhs (stmt);
16468 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
16469 gimple_set_location (g, gimple_location (stmt));
16470 gsi_replace (gsi, g, true);
16472 /* Flavors of vec_eqv. */
16473 case P8V_BUILTIN_EQV_V16QI:
16474 case P8V_BUILTIN_EQV_V8HI:
16475 case P8V_BUILTIN_EQV_V4SI:
16476 case P8V_BUILTIN_EQV_V4SF:
16477 case P8V_BUILTIN_EQV_V2DF:
16478 case P8V_BUILTIN_EQV_V2DI:
16479 arg0 = gimple_call_arg (stmt, 0);
16480 arg1 = gimple_call_arg (stmt, 1);
16481 lhs = gimple_call_lhs (stmt);
16482 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
16483 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
16484 gimple_set_location (g, gimple_location (stmt));
16485 gsi_insert_before (gsi, g, GSI_SAME_STMT);
16486 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
16487 gimple_set_location (g, gimple_location (stmt));
16488 gsi_replace (gsi, g, true);
16490 /* Flavors of vec_rotate_left. */
16491 case ALTIVEC_BUILTIN_VRLB:
16492 case ALTIVEC_BUILTIN_VRLH:
16493 case ALTIVEC_BUILTIN_VRLW:
16494 case P8V_BUILTIN_VRLD:
16495 arg0 = gimple_call_arg (stmt, 0);
16496 arg1 = gimple_call_arg (stmt, 1);
16497 lhs = gimple_call_lhs (stmt);
16498 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
16499 gimple_set_location (g, gimple_location (stmt));
16500 gsi_replace (gsi, g, true);
16502 /* Flavors of vector shift right algebraic.
16503 vec_sra{b,h,w} -> vsra{b,h,w}. */
16504 case ALTIVEC_BUILTIN_VSRAB:
16505 case ALTIVEC_BUILTIN_VSRAH:
16506 case ALTIVEC_BUILTIN_VSRAW:
16507 case P8V_BUILTIN_VSRAD:
16508 arg0 = gimple_call_arg (stmt, 0);
16509 arg1 = gimple_call_arg (stmt, 1);
16510 lhs = gimple_call_lhs (stmt);
16511 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
16512 gimple_set_location (g, gimple_location (stmt));
16513 gsi_replace (gsi, g, true);
16515 /* Flavors of vector shift left.
16516 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
16517 case ALTIVEC_BUILTIN_VSLB:
16518 case ALTIVEC_BUILTIN_VSLH:
16519 case ALTIVEC_BUILTIN_VSLW:
16520 case P8V_BUILTIN_VSLD:
16521 arg0 = gimple_call_arg (stmt, 0);
16522 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
16523 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
16525 arg1 = gimple_call_arg (stmt, 1);
16526 lhs = gimple_call_lhs (stmt);
16527 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1);
16528 gimple_set_location (g, gimple_location (stmt));
16529 gsi_replace (gsi, g, true);
16531 /* Flavors of vector shift right. */
16532 case ALTIVEC_BUILTIN_VSRB:
16533 case ALTIVEC_BUILTIN_VSRH:
16534 case ALTIVEC_BUILTIN_VSRW:
16535 case P8V_BUILTIN_VSRD:
16537 arg0 = gimple_call_arg (stmt, 0);
16538 arg1 = gimple_call_arg (stmt, 1);
16539 lhs = gimple_call_lhs (stmt);
16540 gimple_seq stmts = NULL;
16541 /* Convert arg0 to unsigned. */
16543 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
16544 unsigned_type_for (TREE_TYPE (arg0)), arg0);
16546 = gimple_build (&stmts, RSHIFT_EXPR,
16547 TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1);
16548 /* Convert result back to the lhs type. */
16549 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
16550 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16551 update_call_from_tree (gsi, res);
16554 /* Vector loads. */
16555 case ALTIVEC_BUILTIN_LVX_V16QI:
16556 case ALTIVEC_BUILTIN_LVX_V8HI:
16557 case ALTIVEC_BUILTIN_LVX_V4SI:
16558 case ALTIVEC_BUILTIN_LVX_V4SF:
16559 case ALTIVEC_BUILTIN_LVX_V2DI:
16560 case ALTIVEC_BUILTIN_LVX_V2DF:
16562 arg0 = gimple_call_arg (stmt, 0); // offset
16563 arg1 = gimple_call_arg (stmt, 1); // address
16564 /* Do not fold for -maltivec=be on LE targets. */
16565 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16567 lhs = gimple_call_lhs (stmt);
16568 location_t loc = gimple_location (stmt);
16569 /* Since arg1 may be cast to a different type, just use ptr_type_node
16570 here instead of trying to enforce TBAA on pointer types. */
16571 tree arg1_type = ptr_type_node;
16572 tree lhs_type = TREE_TYPE (lhs);
16573 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
16574 the tree using the value from arg0. The resulting type will match
16575 the type of arg1. */
16576 gimple_seq stmts = NULL;
16577 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
16578 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
16579 arg1_type, arg1, temp_offset);
16580 /* Mask off any lower bits from the address. */
16581 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
16582 arg1_type, temp_addr,
16583 build_int_cst (arg1_type, -16));
16584 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16585 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
16586 take an offset, but since we've already incorporated the offset
16587 above, here we just pass in a zero. */
16589 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
16590 build_int_cst (arg1_type, 0)));
16591 gimple_set_location (g, loc);
16592 gsi_replace (gsi, g, true);
16595 /* Vector stores. */
16596 case ALTIVEC_BUILTIN_STVX_V16QI:
16597 case ALTIVEC_BUILTIN_STVX_V8HI:
16598 case ALTIVEC_BUILTIN_STVX_V4SI:
16599 case ALTIVEC_BUILTIN_STVX_V4SF:
16600 case ALTIVEC_BUILTIN_STVX_V2DI:
16601 case ALTIVEC_BUILTIN_STVX_V2DF:
16603 /* Do not fold for -maltivec=be on LE targets. */
16604 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16606 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
16607 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
16608 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
16609 location_t loc = gimple_location (stmt);
16610 tree arg0_type = TREE_TYPE (arg0);
16611 /* Use ptr_type_node (no TBAA) for the arg2_type.
16612 FIXME: (Richard) "A proper fix would be to transition this type as
16613 seen from the frontend to GIMPLE, for example in a similar way we
16614 do for MEM_REFs by piggy-backing that on an extra argument, a
16615 constant zero pointer of the alias pointer type to use (which would
16616 also serve as a type indicator of the store itself). I'd use a
16617 target specific internal function for this (not sure if we can have
16618 those target specific, but I guess if it's folded away then that's
16619 fine) and get away with the overload set." */
16620 tree arg2_type = ptr_type_node;
16621 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
16622 the tree using the value from arg0. The resulting type will match
16623 the type of arg2. */
16624 gimple_seq stmts = NULL;
16625 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
16626 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
16627 arg2_type, arg2, temp_offset);
16628 /* Mask off any lower bits from the address. */
16629 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
16630 arg2_type, temp_addr,
16631 build_int_cst (arg2_type, -16));
16632 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16633 /* The desired gimple result should be similar to:
16634 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
16636 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
16637 build_int_cst (arg2_type, 0)), arg0);
16638 gimple_set_location (g, loc);
16639 gsi_replace (gsi, g, true);
16643 /* Vector Fused multiply-add (fma). */
16644 case ALTIVEC_BUILTIN_VMADDFP:
16645 case VSX_BUILTIN_XVMADDDP:
16646 case ALTIVEC_BUILTIN_VMLADDUHM:
16648 arg0 = gimple_call_arg (stmt, 0);
16649 arg1 = gimple_call_arg (stmt, 1);
16650 tree arg2 = gimple_call_arg (stmt, 2);
16651 lhs = gimple_call_lhs (stmt);
16652 gimple *g = gimple_build_assign (lhs, FMA_EXPR, arg0, arg1, arg2);
16653 gimple_set_location (g, gimple_location (stmt));
16654 gsi_replace (gsi, g, true);
16658 /* Vector compares; EQ, NE, GE, GT, LE. */
16659 case ALTIVEC_BUILTIN_VCMPEQUB:
16660 case ALTIVEC_BUILTIN_VCMPEQUH:
16661 case ALTIVEC_BUILTIN_VCMPEQUW:
16662 case P8V_BUILTIN_VCMPEQUD:
16663 fold_compare_helper (gsi, EQ_EXPR, stmt);
16666 case P9V_BUILTIN_CMPNEB:
16667 case P9V_BUILTIN_CMPNEH:
16668 case P9V_BUILTIN_CMPNEW:
16669 fold_compare_helper (gsi, NE_EXPR, stmt);
16672 case VSX_BUILTIN_CMPGE_16QI:
16673 case VSX_BUILTIN_CMPGE_U16QI:
16674 case VSX_BUILTIN_CMPGE_8HI:
16675 case VSX_BUILTIN_CMPGE_U8HI:
16676 case VSX_BUILTIN_CMPGE_4SI:
16677 case VSX_BUILTIN_CMPGE_U4SI:
16678 case VSX_BUILTIN_CMPGE_2DI:
16679 case VSX_BUILTIN_CMPGE_U2DI:
16680 fold_compare_helper (gsi, GE_EXPR, stmt);
16683 case ALTIVEC_BUILTIN_VCMPGTSB:
16684 case ALTIVEC_BUILTIN_VCMPGTUB:
16685 case ALTIVEC_BUILTIN_VCMPGTSH:
16686 case ALTIVEC_BUILTIN_VCMPGTUH:
16687 case ALTIVEC_BUILTIN_VCMPGTSW:
16688 case ALTIVEC_BUILTIN_VCMPGTUW:
16689 case P8V_BUILTIN_VCMPGTUD:
16690 case P8V_BUILTIN_VCMPGTSD:
16691 fold_compare_helper (gsi, GT_EXPR, stmt);
16694 case VSX_BUILTIN_CMPLE_16QI:
16695 case VSX_BUILTIN_CMPLE_U16QI:
16696 case VSX_BUILTIN_CMPLE_8HI:
16697 case VSX_BUILTIN_CMPLE_U8HI:
16698 case VSX_BUILTIN_CMPLE_4SI:
16699 case VSX_BUILTIN_CMPLE_U4SI:
16700 case VSX_BUILTIN_CMPLE_2DI:
16701 case VSX_BUILTIN_CMPLE_U2DI:
16702 fold_compare_helper (gsi, LE_EXPR, stmt);
16705 /* flavors of vec_splat_[us]{8,16,32}. */
16706 case ALTIVEC_BUILTIN_VSPLTISB:
16707 case ALTIVEC_BUILTIN_VSPLTISH:
16708 case ALTIVEC_BUILTIN_VSPLTISW:
16710 arg0 = gimple_call_arg (stmt, 0);
16711 lhs = gimple_call_lhs (stmt);
16712 /* Only fold the vec_splat_*() if arg0 is constant. */
16713 if (TREE_CODE (arg0) != INTEGER_CST)
16715 gimple_seq stmts = NULL;
16716 location_t loc = gimple_location (stmt);
16717 tree splat_value = gimple_convert (&stmts, loc,
16718 TREE_TYPE (TREE_TYPE (lhs)), arg0);
16719 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
16720 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
16721 g = gimple_build_assign (lhs, splat_tree);
16722 gimple_set_location (g, gimple_location (stmt));
16723 gsi_replace (gsi, g, true);
16727 /* vec_mergel (integrals). */
16728 case ALTIVEC_BUILTIN_VMRGLH:
16729 case ALTIVEC_BUILTIN_VMRGLW:
16730 case VSX_BUILTIN_XXMRGLW_4SI:
16731 case ALTIVEC_BUILTIN_VMRGLB:
16732 case VSX_BUILTIN_VEC_MERGEL_V2DI:
16733 /* Do not fold for -maltivec=be on LE targets. */
16734 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16736 fold_mergehl_helper (gsi, stmt, 1);
16738 /* vec_mergeh (integrals). */
16739 case ALTIVEC_BUILTIN_VMRGHH:
16740 case ALTIVEC_BUILTIN_VMRGHW:
16741 case VSX_BUILTIN_XXMRGHW_4SI:
16742 case ALTIVEC_BUILTIN_VMRGHB:
16743 case VSX_BUILTIN_VEC_MERGEH_V2DI:
16744 /* Do not fold for -maltivec=be on LE targets. */
16745 if (VECTOR_ELT_ORDER_BIG && !BYTES_BIG_ENDIAN)
16747 fold_mergehl_helper (gsi, stmt, 0);
16750 if (TARGET_DEBUG_BUILTIN)
16751 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
16752 fn_code, fn_name1, fn_name2);
16759 /* Expand an expression EXP that calls a built-in function,
16760 with result going to TARGET if that's convenient
16761 (and in mode MODE if that's convenient).
16762 SUBTARGET may be used as the target for computing one of EXP's operands.
16763 IGNORE is nonzero if the value is to be ignored. */
16766 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
16767 machine_mode mode ATTRIBUTE_UNUSED,
16768 int ignore ATTRIBUTE_UNUSED)
16770 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
16771 enum rs6000_builtins fcode
16772 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
16773 size_t uns_fcode = (size_t)fcode;
16774 const struct builtin_description *d;
16778 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
16779 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
16780 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
16782 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
16783 floating point type, depending on whether long double is the IBM extended
16784 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
16785 we only define one variant of the built-in function, and switch the code
16786 when defining it, rather than defining two built-ins and using the
16787 overload table in rs6000-c.c to switch between the two. If we don't have
16788 the proper assembler, don't do this switch because CODE_FOR_*kf* and
16789 CODE_FOR_*tf* will be CODE_FOR_nothing. */
16790 #ifdef HAVE_AS_POWER9
16791 if (FLOAT128_IEEE_P (TFmode))
16797 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
16798 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
16799 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
16800 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
16801 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
16802 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
16803 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
16804 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
16805 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
16806 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
16807 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
16808 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
16809 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
16813 if (TARGET_DEBUG_BUILTIN)
16815 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16816 const char *name2 = (icode != CODE_FOR_nothing)
16817 ? get_insn_name ((int) icode)
16821 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16823 default: name3 = "unknown"; break;
16824 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16825 case RS6000_BTC_UNARY: name3 = "unary"; break;
16826 case RS6000_BTC_BINARY: name3 = "binary"; break;
16827 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16828 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16829 case RS6000_BTC_ABS: name3 = "abs"; break;
16830 case RS6000_BTC_DST: name3 = "dst"; break;
16835 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16836 (name1) ? name1 : "---", fcode,
16837 (name2) ? name2 : "---", (int) icode,
16839 func_valid_p ? "" : ", not valid");
16844 rs6000_invalid_builtin (fcode);
16846 /* Given it is invalid, just generate a normal call. */
16847 return expand_call (exp, target, ignore);
16852 case RS6000_BUILTIN_RECIP:
16853 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16855 case RS6000_BUILTIN_RECIPF:
16856 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16858 case RS6000_BUILTIN_RSQRTF:
16859 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16861 case RS6000_BUILTIN_RSQRT:
16862 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16864 case POWER7_BUILTIN_BPERMD:
16865 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16866 ? CODE_FOR_bpermd_di
16867 : CODE_FOR_bpermd_si), exp, target);
16869 case RS6000_BUILTIN_GET_TB:
16870 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16873 case RS6000_BUILTIN_MFTB:
16874 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16875 ? CODE_FOR_rs6000_mftb_di
16876 : CODE_FOR_rs6000_mftb_si),
16879 case RS6000_BUILTIN_MFFS:
16880 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16882 case RS6000_BUILTIN_MTFSF:
16883 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16885 case RS6000_BUILTIN_CPU_INIT:
16886 case RS6000_BUILTIN_CPU_IS:
16887 case RS6000_BUILTIN_CPU_SUPPORTS:
16888 return cpu_expand_builtin (fcode, exp, target);
16890 case MISC_BUILTIN_SPEC_BARRIER:
16892 emit_insn (gen_rs6000_speculation_barrier ());
16896 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16897 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16899 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16900 : (int) CODE_FOR_altivec_lvsl_direct);
16901 machine_mode tmode = insn_data[icode2].operand[0].mode;
16902 machine_mode mode = insn_data[icode2].operand[1].mode;
16906 gcc_assert (TARGET_ALTIVEC);
16908 arg = CALL_EXPR_ARG (exp, 0);
16909 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16910 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16911 addr = memory_address (mode, op);
16912 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16916 /* For the load case need to negate the address. */
16917 op = gen_reg_rtx (GET_MODE (addr));
16918 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16920 op = gen_rtx_MEM (mode, op);
16923 || GET_MODE (target) != tmode
16924 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
16925 target = gen_reg_rtx (tmode);
16927 pat = GEN_FCN (icode2) (target, op);
16935 case ALTIVEC_BUILTIN_VCFUX:
16936 case ALTIVEC_BUILTIN_VCFSX:
16937 case ALTIVEC_BUILTIN_VCTUXS:
16938 case ALTIVEC_BUILTIN_VCTSXS:
16939 /* FIXME: There's got to be a nicer way to handle this case than
16940 constructing a new CALL_EXPR. */
16941 if (call_expr_nargs (exp) == 1)
16943 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16944 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16952 if (TARGET_ALTIVEC)
16954 ret = altivec_expand_builtin (exp, target, &success);
16959 if (TARGET_PAIRED_FLOAT)
16961 ret = paired_expand_builtin (exp, target, &success);
16968 ret = htm_expand_builtin (exp, target, &success);
16974 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16975 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16976 gcc_assert (attr == RS6000_BTC_UNARY
16977 || attr == RS6000_BTC_BINARY
16978 || attr == RS6000_BTC_TERNARY
16979 || attr == RS6000_BTC_SPECIAL);
16981 /* Handle simple unary operations. */
16983 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16984 if (d->code == fcode)
16985 return rs6000_expand_unop_builtin (icode, exp, target);
16987 /* Handle simple binary operations. */
16989 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16990 if (d->code == fcode)
16991 return rs6000_expand_binop_builtin (icode, exp, target);
16993 /* Handle simple ternary operations. */
16995 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16996 if (d->code == fcode)
16997 return rs6000_expand_ternop_builtin (icode, exp, target);
16999 /* Handle simple no-argument operations. */
17001 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
17002 if (d->code == fcode)
17003 return rs6000_expand_zeroop_builtin (icode, target);
17005 gcc_unreachable ();
17008 /* Create a builtin vector type with a name. Taking care not to give
17009 the canonical type a name. */
17012 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
17014 tree result = build_vector_type (elt_type, num_elts);
17016 /* Copy so we don't give the canonical type a name. */
17017 result = build_variant_type_copy (result);
17019 add_builtin_type (name, result);
17025 rs6000_init_builtins (void)
17031 if (TARGET_DEBUG_BUILTIN)
17032 fprintf (stderr, "rs6000_init_builtins%s%s%s\n",
17033 (TARGET_PAIRED_FLOAT) ? ", paired" : "",
17034 (TARGET_ALTIVEC) ? ", altivec" : "",
17035 (TARGET_VSX) ? ", vsx" : "");
17037 V2SI_type_node = build_vector_type (intSI_type_node, 2);
17038 V2SF_type_node = build_vector_type (float_type_node, 2);
17039 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
17040 : "__vector long long",
17041 intDI_type_node, 2);
17042 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
17043 V4SI_type_node = rs6000_vector_type ("__vector signed int",
17044 intSI_type_node, 4);
17045 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
17046 V8HI_type_node = rs6000_vector_type ("__vector signed short",
17047 intHI_type_node, 8);
17048 V16QI_type_node = rs6000_vector_type ("__vector signed char",
17049 intQI_type_node, 16);
17051 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
17052 unsigned_intQI_type_node, 16);
17053 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
17054 unsigned_intHI_type_node, 8);
17055 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
17056 unsigned_intSI_type_node, 4);
17057 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
17058 ? "__vector unsigned long"
17059 : "__vector unsigned long long",
17060 unsigned_intDI_type_node, 2);
17062 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
17063 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
17064 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
17065 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
17067 const_str_type_node
17068 = build_pointer_type (build_qualified_type (char_type_node,
17071 /* We use V1TI mode as a special container to hold __int128_t items that
17072 must live in VSX registers. */
17073 if (intTI_type_node)
17075 V1TI_type_node = rs6000_vector_type ("__vector __int128",
17076 intTI_type_node, 1);
17077 unsigned_V1TI_type_node
17078 = rs6000_vector_type ("__vector unsigned __int128",
17079 unsigned_intTI_type_node, 1);
17082 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
17083 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
17084 'vector unsigned short'. */
17086 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
17087 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
17088 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
17089 bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
17090 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
17092 long_integer_type_internal_node = long_integer_type_node;
17093 long_unsigned_type_internal_node = long_unsigned_type_node;
17094 long_long_integer_type_internal_node = long_long_integer_type_node;
17095 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
17096 intQI_type_internal_node = intQI_type_node;
17097 uintQI_type_internal_node = unsigned_intQI_type_node;
17098 intHI_type_internal_node = intHI_type_node;
17099 uintHI_type_internal_node = unsigned_intHI_type_node;
17100 intSI_type_internal_node = intSI_type_node;
17101 uintSI_type_internal_node = unsigned_intSI_type_node;
17102 intDI_type_internal_node = intDI_type_node;
17103 uintDI_type_internal_node = unsigned_intDI_type_node;
17104 intTI_type_internal_node = intTI_type_node;
17105 uintTI_type_internal_node = unsigned_intTI_type_node;
17106 float_type_internal_node = float_type_node;
17107 double_type_internal_node = double_type_node;
17108 long_double_type_internal_node = long_double_type_node;
17109 dfloat64_type_internal_node = dfloat64_type_node;
17110 dfloat128_type_internal_node = dfloat128_type_node;
17111 void_type_internal_node = void_type_node;
17113 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
17114 IFmode is the IBM extended 128-bit format that is a pair of doubles.
17115 TFmode will be either IEEE 128-bit floating point or the IBM double-double
17116 format that uses a pair of doubles, depending on the switches and
17119 If we don't support for either 128-bit IBM double double or IEEE 128-bit
17120 floating point, we need make sure the type is non-zero or else self-test
17121 fails during bootstrap.
17123 We don't register a built-in type for __ibm128 if the type is the same as
17124 long double. Instead we add a #define for __ibm128 in
17125 rs6000_cpu_cpp_builtins to long double.
17127 For IEEE 128-bit floating point, always create the type __ieee128. If the
17128 user used -mfloat128, rs6000-c.c will create a define from __float128 to
17130 if (TARGET_LONG_DOUBLE_128 && FLOAT128_IEEE_P (TFmode))
17132 ibm128_float_type_node = make_node (REAL_TYPE);
17133 TYPE_PRECISION (ibm128_float_type_node) = 128;
17134 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
17135 layout_type (ibm128_float_type_node);
17137 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
17141 ibm128_float_type_node = long_double_type_node;
17143 if (TARGET_FLOAT128_TYPE)
17145 ieee128_float_type_node = float128_type_node;
17146 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
17151 ieee128_float_type_node = long_double_type_node;
17153 /* Initialize the modes for builtin_function_type, mapping a machine mode to
17155 builtin_mode_to_type[QImode][0] = integer_type_node;
17156 builtin_mode_to_type[HImode][0] = integer_type_node;
17157 builtin_mode_to_type[SImode][0] = intSI_type_node;
17158 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
17159 builtin_mode_to_type[DImode][0] = intDI_type_node;
17160 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
17161 builtin_mode_to_type[TImode][0] = intTI_type_node;
17162 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
17163 builtin_mode_to_type[SFmode][0] = float_type_node;
17164 builtin_mode_to_type[DFmode][0] = double_type_node;
17165 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
17166 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
17167 builtin_mode_to_type[TFmode][0] = long_double_type_node;
17168 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
17169 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
17170 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
17171 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
17172 builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
17173 builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
17174 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
17175 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
17176 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
17177 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
17178 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
17179 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
17180 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
17181 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
17182 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
17183 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
17185 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
17186 TYPE_NAME (bool_char_type_node) = tdecl;
17188 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
17189 TYPE_NAME (bool_short_type_node) = tdecl;
17191 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
17192 TYPE_NAME (bool_int_type_node) = tdecl;
17194 tdecl = add_builtin_type ("__pixel", pixel_type_node);
17195 TYPE_NAME (pixel_type_node) = tdecl;
17197 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
17198 bool_char_type_node, 16);
17199 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
17200 bool_short_type_node, 8);
17201 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
17202 bool_int_type_node, 4);
17203 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
17204 ? "__vector __bool long"
17205 : "__vector __bool long long",
17206 bool_long_type_node, 2);
17207 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
17208 pixel_type_node, 8);
17210 /* Paired builtins are only available if you build a compiler with the
17211 appropriate options, so only create those builtins with the appropriate
17212 compiler option. Create Altivec and VSX builtins on machines with at
17213 least the general purpose extensions (970 and newer) to allow the use of
17214 the target attribute. */
17215 if (TARGET_PAIRED_FLOAT)
17216 paired_init_builtins ();
17217 if (TARGET_EXTRA_BUILTINS)
17218 altivec_init_builtins ();
17220 htm_init_builtins ();
17222 if (TARGET_EXTRA_BUILTINS || TARGET_PAIRED_FLOAT)
17223 rs6000_common_init_builtins ();
17225 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
17226 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
17227 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
17229 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
17230 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
17231 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
17233 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
17234 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
17235 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
17237 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
17238 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
17239 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
17241 mode = (TARGET_64BIT) ? DImode : SImode;
17242 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
17243 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
17244 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
17246 ftype = build_function_type_list (unsigned_intDI_type_node,
17248 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
17251 ftype = build_function_type_list (unsigned_intDI_type_node,
17254 ftype = build_function_type_list (unsigned_intSI_type_node,
17256 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
17258 ftype = build_function_type_list (double_type_node, NULL_TREE);
17259 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
17261 ftype = build_function_type_list (void_type_node,
17262 intSI_type_node, double_type_node,
17264 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
17266 ftype = build_function_type_list (void_type_node, NULL_TREE);
17267 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
17268 def_builtin ("__builtin_rs6000_speculation_barrier", ftype,
17269 MISC_BUILTIN_SPEC_BARRIER);
17271 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
17273 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
17274 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
17276 /* AIX libm provides clog as __clog. */
17277 if (TARGET_XCOFF &&
17278 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
17279 set_user_assembler_name (tdecl, "__clog");
17281 #ifdef SUBTARGET_INIT_BUILTINS
17282 SUBTARGET_INIT_BUILTINS;
17286 /* Returns the rs6000 builtin decl for CODE. */
17289 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
17291 HOST_WIDE_INT fnmask;
17293 if (code >= RS6000_BUILTIN_COUNT)
17294 return error_mark_node;
17296 fnmask = rs6000_builtin_info[code].mask;
17297 if ((fnmask & rs6000_builtin_mask) != fnmask)
17299 rs6000_invalid_builtin ((enum rs6000_builtins)code);
17300 return error_mark_node;
17303 return rs6000_builtin_decls[code];
17307 paired_init_builtins (void)
17309 const struct builtin_description *d;
17311 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17313 tree int_ftype_int_v2sf_v2sf
17314 = build_function_type_list (integer_type_node,
17319 tree pcfloat_type_node =
17320 build_pointer_type (build_qualified_type
17321 (float_type_node, TYPE_QUAL_CONST));
17323 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
17324 long_integer_type_node,
17327 tree void_ftype_v2sf_long_pcfloat =
17328 build_function_type_list (void_type_node,
17330 long_integer_type_node,
17335 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
17336 PAIRED_BUILTIN_LX);
17339 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
17340 PAIRED_BUILTIN_STX);
17343 d = bdesc_paired_preds;
17344 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
17347 HOST_WIDE_INT mask = d->mask;
17349 if ((mask & builtin_mask) != mask)
17351 if (TARGET_DEBUG_BUILTIN)
17352 fprintf (stderr, "paired_init_builtins, skip predicate %s\n",
17357 /* Cannot define builtin if the instruction is disabled. */
17358 gcc_assert (d->icode != CODE_FOR_nothing);
17360 if (TARGET_DEBUG_BUILTIN)
17361 fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
17362 (int)i, get_insn_name (d->icode), (int)d->icode,
17363 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
17365 switch (insn_data[d->icode].operand[1].mode)
17368 type = int_ftype_int_v2sf_v2sf;
17371 gcc_unreachable ();
17374 def_builtin (d->name, type, d->code);
17379 altivec_init_builtins (void)
17381 const struct builtin_description *d;
17385 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17387 tree pvoid_type_node = build_pointer_type (void_type_node);
17389 tree pcvoid_type_node
17390 = build_pointer_type (build_qualified_type (void_type_node,
17393 tree int_ftype_opaque
17394 = build_function_type_list (integer_type_node,
17395 opaque_V4SI_type_node, NULL_TREE);
17396 tree opaque_ftype_opaque
17397 = build_function_type_list (integer_type_node, NULL_TREE);
17398 tree opaque_ftype_opaque_int
17399 = build_function_type_list (opaque_V4SI_type_node,
17400 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
17401 tree opaque_ftype_opaque_opaque_int
17402 = build_function_type_list (opaque_V4SI_type_node,
17403 opaque_V4SI_type_node, opaque_V4SI_type_node,
17404 integer_type_node, NULL_TREE);
17405 tree opaque_ftype_opaque_opaque_opaque
17406 = build_function_type_list (opaque_V4SI_type_node,
17407 opaque_V4SI_type_node, opaque_V4SI_type_node,
17408 opaque_V4SI_type_node, NULL_TREE);
17409 tree opaque_ftype_opaque_opaque
17410 = build_function_type_list (opaque_V4SI_type_node,
17411 opaque_V4SI_type_node, opaque_V4SI_type_node,
17413 tree int_ftype_int_opaque_opaque
17414 = build_function_type_list (integer_type_node,
17415 integer_type_node, opaque_V4SI_type_node,
17416 opaque_V4SI_type_node, NULL_TREE);
17417 tree int_ftype_int_v4si_v4si
17418 = build_function_type_list (integer_type_node,
17419 integer_type_node, V4SI_type_node,
17420 V4SI_type_node, NULL_TREE);
17421 tree int_ftype_int_v2di_v2di
17422 = build_function_type_list (integer_type_node,
17423 integer_type_node, V2DI_type_node,
17424 V2DI_type_node, NULL_TREE);
17425 tree void_ftype_v4si
17426 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
17427 tree v8hi_ftype_void
17428 = build_function_type_list (V8HI_type_node, NULL_TREE);
17429 tree void_ftype_void
17430 = build_function_type_list (void_type_node, NULL_TREE);
17431 tree void_ftype_int
17432 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
17434 tree opaque_ftype_long_pcvoid
17435 = build_function_type_list (opaque_V4SI_type_node,
17436 long_integer_type_node, pcvoid_type_node,
17438 tree v16qi_ftype_long_pcvoid
17439 = build_function_type_list (V16QI_type_node,
17440 long_integer_type_node, pcvoid_type_node,
17442 tree v8hi_ftype_long_pcvoid
17443 = build_function_type_list (V8HI_type_node,
17444 long_integer_type_node, pcvoid_type_node,
17446 tree v4si_ftype_long_pcvoid
17447 = build_function_type_list (V4SI_type_node,
17448 long_integer_type_node, pcvoid_type_node,
17450 tree v4sf_ftype_long_pcvoid
17451 = build_function_type_list (V4SF_type_node,
17452 long_integer_type_node, pcvoid_type_node,
17454 tree v2df_ftype_long_pcvoid
17455 = build_function_type_list (V2DF_type_node,
17456 long_integer_type_node, pcvoid_type_node,
17458 tree v2di_ftype_long_pcvoid
17459 = build_function_type_list (V2DI_type_node,
17460 long_integer_type_node, pcvoid_type_node,
17463 tree void_ftype_opaque_long_pvoid
17464 = build_function_type_list (void_type_node,
17465 opaque_V4SI_type_node, long_integer_type_node,
17466 pvoid_type_node, NULL_TREE);
17467 tree void_ftype_v4si_long_pvoid
17468 = build_function_type_list (void_type_node,
17469 V4SI_type_node, long_integer_type_node,
17470 pvoid_type_node, NULL_TREE);
17471 tree void_ftype_v16qi_long_pvoid
17472 = build_function_type_list (void_type_node,
17473 V16QI_type_node, long_integer_type_node,
17474 pvoid_type_node, NULL_TREE);
17476 tree void_ftype_v16qi_pvoid_long
17477 = build_function_type_list (void_type_node,
17478 V16QI_type_node, pvoid_type_node,
17479 long_integer_type_node, NULL_TREE);
17481 tree void_ftype_v8hi_long_pvoid
17482 = build_function_type_list (void_type_node,
17483 V8HI_type_node, long_integer_type_node,
17484 pvoid_type_node, NULL_TREE);
17485 tree void_ftype_v4sf_long_pvoid
17486 = build_function_type_list (void_type_node,
17487 V4SF_type_node, long_integer_type_node,
17488 pvoid_type_node, NULL_TREE);
17489 tree void_ftype_v2df_long_pvoid
17490 = build_function_type_list (void_type_node,
17491 V2DF_type_node, long_integer_type_node,
17492 pvoid_type_node, NULL_TREE);
17493 tree void_ftype_v1ti_long_pvoid
17494 = build_function_type_list (void_type_node,
17495 V1TI_type_node, long_integer_type_node,
17496 pvoid_type_node, NULL_TREE);
17497 tree void_ftype_v2di_long_pvoid
17498 = build_function_type_list (void_type_node,
17499 V2DI_type_node, long_integer_type_node,
17500 pvoid_type_node, NULL_TREE);
17501 tree int_ftype_int_v8hi_v8hi
17502 = build_function_type_list (integer_type_node,
17503 integer_type_node, V8HI_type_node,
17504 V8HI_type_node, NULL_TREE);
17505 tree int_ftype_int_v16qi_v16qi
17506 = build_function_type_list (integer_type_node,
17507 integer_type_node, V16QI_type_node,
17508 V16QI_type_node, NULL_TREE);
17509 tree int_ftype_int_v4sf_v4sf
17510 = build_function_type_list (integer_type_node,
17511 integer_type_node, V4SF_type_node,
17512 V4SF_type_node, NULL_TREE);
17513 tree int_ftype_int_v2df_v2df
17514 = build_function_type_list (integer_type_node,
17515 integer_type_node, V2DF_type_node,
17516 V2DF_type_node, NULL_TREE);
17517 tree v2di_ftype_v2di
17518 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
17519 tree v4si_ftype_v4si
17520 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
17521 tree v8hi_ftype_v8hi
17522 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
17523 tree v16qi_ftype_v16qi
17524 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
17525 tree v4sf_ftype_v4sf
17526 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
17527 tree v2df_ftype_v2df
17528 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
17529 tree void_ftype_pcvoid_int_int
17530 = build_function_type_list (void_type_node,
17531 pcvoid_type_node, integer_type_node,
17532 integer_type_node, NULL_TREE);
17534 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
17535 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
17536 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
17537 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
17538 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
17539 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
17540 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
17541 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
17542 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
17543 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
17544 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
17545 ALTIVEC_BUILTIN_LVXL_V2DF);
17546 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
17547 ALTIVEC_BUILTIN_LVXL_V2DI);
17548 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
17549 ALTIVEC_BUILTIN_LVXL_V4SF);
17550 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
17551 ALTIVEC_BUILTIN_LVXL_V4SI);
17552 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
17553 ALTIVEC_BUILTIN_LVXL_V8HI);
17554 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
17555 ALTIVEC_BUILTIN_LVXL_V16QI);
17556 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
17557 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
17558 ALTIVEC_BUILTIN_LVX_V2DF);
17559 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
17560 ALTIVEC_BUILTIN_LVX_V2DI);
17561 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
17562 ALTIVEC_BUILTIN_LVX_V4SF);
17563 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
17564 ALTIVEC_BUILTIN_LVX_V4SI);
17565 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
17566 ALTIVEC_BUILTIN_LVX_V8HI);
17567 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
17568 ALTIVEC_BUILTIN_LVX_V16QI);
17569 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
17570 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
17571 ALTIVEC_BUILTIN_STVX_V2DF);
17572 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
17573 ALTIVEC_BUILTIN_STVX_V2DI);
17574 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
17575 ALTIVEC_BUILTIN_STVX_V4SF);
17576 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
17577 ALTIVEC_BUILTIN_STVX_V4SI);
17578 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
17579 ALTIVEC_BUILTIN_STVX_V8HI);
17580 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
17581 ALTIVEC_BUILTIN_STVX_V16QI);
17582 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
17583 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
17584 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
17585 ALTIVEC_BUILTIN_STVXL_V2DF);
17586 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
17587 ALTIVEC_BUILTIN_STVXL_V2DI);
17588 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
17589 ALTIVEC_BUILTIN_STVXL_V4SF);
17590 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
17591 ALTIVEC_BUILTIN_STVXL_V4SI);
17592 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
17593 ALTIVEC_BUILTIN_STVXL_V8HI);
17594 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
17595 ALTIVEC_BUILTIN_STVXL_V16QI);
17596 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
17597 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
17598 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
17599 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
17600 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
17601 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
17602 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
17603 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
17604 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
17605 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
17606 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
17607 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
17608 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
17609 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
17610 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
17611 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
17613 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
17614 VSX_BUILTIN_LXVD2X_V2DF);
17615 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
17616 VSX_BUILTIN_LXVD2X_V2DI);
17617 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
17618 VSX_BUILTIN_LXVW4X_V4SF);
17619 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
17620 VSX_BUILTIN_LXVW4X_V4SI);
17621 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
17622 VSX_BUILTIN_LXVW4X_V8HI);
17623 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
17624 VSX_BUILTIN_LXVW4X_V16QI);
17625 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
17626 VSX_BUILTIN_STXVD2X_V2DF);
17627 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
17628 VSX_BUILTIN_STXVD2X_V2DI);
17629 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
17630 VSX_BUILTIN_STXVW4X_V4SF);
17631 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
17632 VSX_BUILTIN_STXVW4X_V4SI);
17633 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
17634 VSX_BUILTIN_STXVW4X_V8HI);
17635 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
17636 VSX_BUILTIN_STXVW4X_V16QI);
17638 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
17639 VSX_BUILTIN_LD_ELEMREV_V2DF);
17640 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
17641 VSX_BUILTIN_LD_ELEMREV_V2DI);
17642 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
17643 VSX_BUILTIN_LD_ELEMREV_V4SF);
17644 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
17645 VSX_BUILTIN_LD_ELEMREV_V4SI);
17646 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
17647 VSX_BUILTIN_LD_ELEMREV_V8HI);
17648 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
17649 VSX_BUILTIN_LD_ELEMREV_V16QI);
17650 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
17651 VSX_BUILTIN_ST_ELEMREV_V2DF);
17652 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
17653 VSX_BUILTIN_ST_ELEMREV_V1TI);
17654 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
17655 VSX_BUILTIN_ST_ELEMREV_V2DI);
17656 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
17657 VSX_BUILTIN_ST_ELEMREV_V4SF);
17658 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
17659 VSX_BUILTIN_ST_ELEMREV_V4SI);
17660 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
17661 VSX_BUILTIN_ST_ELEMREV_V8HI);
17662 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
17663 VSX_BUILTIN_ST_ELEMREV_V16QI);
17665 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
17666 VSX_BUILTIN_VEC_LD);
17667 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
17668 VSX_BUILTIN_VEC_ST);
17669 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
17670 VSX_BUILTIN_VEC_XL);
17671 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
17672 VSX_BUILTIN_VEC_XL_BE);
17673 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
17674 VSX_BUILTIN_VEC_XST);
17675 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
17676 VSX_BUILTIN_VEC_XST_BE);
17678 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
17679 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
17680 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
17682 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
17683 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
17684 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
17685 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
17686 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
17687 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
17688 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
17689 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
17690 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
17691 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
17692 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
17693 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
17695 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
17696 ALTIVEC_BUILTIN_VEC_ADDE);
17697 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
17698 ALTIVEC_BUILTIN_VEC_ADDEC);
17699 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
17700 ALTIVEC_BUILTIN_VEC_CMPNE);
17701 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
17702 ALTIVEC_BUILTIN_VEC_MUL);
17703 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
17704 ALTIVEC_BUILTIN_VEC_SUBE);
17705 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
17706 ALTIVEC_BUILTIN_VEC_SUBEC);
17708 /* Cell builtins. */
17709 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
17710 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
17711 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
17712 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
17714 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
17715 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
17716 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
17717 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
17719 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
17720 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
17721 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
17722 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
17724 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
17725 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
17726 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
17727 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
17729 if (TARGET_P9_VECTOR)
17731 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
17732 P9V_BUILTIN_STXVL);
17733 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
17734 P9V_BUILTIN_XST_LEN_R);
17737 /* Add the DST variants. */
17739 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
17741 HOST_WIDE_INT mask = d->mask;
17743 /* It is expected that these dst built-in functions may have
17744 d->icode equal to CODE_FOR_nothing. */
17745 if ((mask & builtin_mask) != mask)
17747 if (TARGET_DEBUG_BUILTIN)
17748 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
17752 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
17755 /* Initialize the predicates. */
17756 d = bdesc_altivec_preds;
17757 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
17759 machine_mode mode1;
17761 HOST_WIDE_INT mask = d->mask;
17763 if ((mask & builtin_mask) != mask)
17765 if (TARGET_DEBUG_BUILTIN)
17766 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
17771 if (rs6000_overloaded_builtin_p (d->code))
17775 /* Cannot define builtin if the instruction is disabled. */
17776 gcc_assert (d->icode != CODE_FOR_nothing);
17777 mode1 = insn_data[d->icode].operand[1].mode;
17783 type = int_ftype_int_opaque_opaque;
17786 type = int_ftype_int_v2di_v2di;
17789 type = int_ftype_int_v4si_v4si;
17792 type = int_ftype_int_v8hi_v8hi;
17795 type = int_ftype_int_v16qi_v16qi;
17798 type = int_ftype_int_v4sf_v4sf;
17801 type = int_ftype_int_v2df_v2df;
17804 gcc_unreachable ();
17807 def_builtin (d->name, type, d->code);
17810 /* Initialize the abs* operators. */
17812 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
17814 machine_mode mode0;
17816 HOST_WIDE_INT mask = d->mask;
17818 if ((mask & builtin_mask) != mask)
17820 if (TARGET_DEBUG_BUILTIN)
17821 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
17826 /* Cannot define builtin if the instruction is disabled. */
17827 gcc_assert (d->icode != CODE_FOR_nothing);
17828 mode0 = insn_data[d->icode].operand[0].mode;
17833 type = v2di_ftype_v2di;
17836 type = v4si_ftype_v4si;
17839 type = v8hi_ftype_v8hi;
17842 type = v16qi_ftype_v16qi;
17845 type = v4sf_ftype_v4sf;
17848 type = v2df_ftype_v2df;
17851 gcc_unreachable ();
17854 def_builtin (d->name, type, d->code);
17857 /* Initialize target builtin that implements
17858 targetm.vectorize.builtin_mask_for_load. */
17860 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17861 v16qi_ftype_long_pcvoid,
17862 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17863 BUILT_IN_MD, NULL, NULL_TREE);
17864 TREE_READONLY (decl) = 1;
17865 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17866 altivec_builtin_mask_for_load = decl;
17868 /* Access to the vec_init patterns. */
17869 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17870 integer_type_node, integer_type_node,
17871 integer_type_node, NULL_TREE);
17872 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17874 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17875 short_integer_type_node,
17876 short_integer_type_node,
17877 short_integer_type_node,
17878 short_integer_type_node,
17879 short_integer_type_node,
17880 short_integer_type_node,
17881 short_integer_type_node, NULL_TREE);
17882 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17884 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17885 char_type_node, char_type_node,
17886 char_type_node, char_type_node,
17887 char_type_node, char_type_node,
17888 char_type_node, char_type_node,
17889 char_type_node, char_type_node,
17890 char_type_node, char_type_node,
17891 char_type_node, char_type_node,
17892 char_type_node, NULL_TREE);
17893 def_builtin ("__builtin_vec_init_v16qi", ftype,
17894 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17896 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17897 float_type_node, float_type_node,
17898 float_type_node, NULL_TREE);
17899 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17901 /* VSX builtins. */
17902 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17903 double_type_node, NULL_TREE);
17904 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17906 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17907 intDI_type_node, NULL_TREE);
17908 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17910 /* Access to the vec_set patterns. */
17911 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17913 integer_type_node, NULL_TREE);
17914 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17916 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17918 integer_type_node, NULL_TREE);
17919 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17921 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17923 integer_type_node, NULL_TREE);
17924 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17926 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17928 integer_type_node, NULL_TREE);
17929 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17931 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17933 integer_type_node, NULL_TREE);
17934 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17936 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17938 integer_type_node, NULL_TREE);
17939 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17941 /* Access to the vec_extract patterns. */
17942 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17943 integer_type_node, NULL_TREE);
17944 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17946 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17947 integer_type_node, NULL_TREE);
17948 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17950 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17951 integer_type_node, NULL_TREE);
17952 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17954 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17955 integer_type_node, NULL_TREE);
17956 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17958 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17959 integer_type_node, NULL_TREE);
17960 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17962 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17963 integer_type_node, NULL_TREE);
17964 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17967 if (V1TI_type_node)
17969 tree v1ti_ftype_long_pcvoid
17970 = build_function_type_list (V1TI_type_node,
17971 long_integer_type_node, pcvoid_type_node,
17973 tree void_ftype_v1ti_long_pvoid
17974 = build_function_type_list (void_type_node,
17975 V1TI_type_node, long_integer_type_node,
17976 pvoid_type_node, NULL_TREE);
17977 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
17978 VSX_BUILTIN_LD_ELEMREV_V1TI);
17979 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17980 VSX_BUILTIN_LXVD2X_V1TI);
17981 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17982 VSX_BUILTIN_STXVD2X_V1TI);
17983 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17984 NULL_TREE, NULL_TREE);
17985 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17986 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17988 integer_type_node, NULL_TREE);
17989 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17990 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17991 integer_type_node, NULL_TREE);
17992 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17998 htm_init_builtins (void)
18000 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
18001 const struct builtin_description *d;
18005 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
18007 tree op[MAX_HTM_OPERANDS], type;
18008 HOST_WIDE_INT mask = d->mask;
18009 unsigned attr = rs6000_builtin_info[d->code].attr;
18010 bool void_func = (attr & RS6000_BTC_VOID);
18011 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
18013 tree gpr_type_node;
18017 /* It is expected that these htm built-in functions may have
18018 d->icode equal to CODE_FOR_nothing. */
18020 if (TARGET_32BIT && TARGET_POWERPC64)
18021 gpr_type_node = long_long_unsigned_type_node;
18023 gpr_type_node = long_unsigned_type_node;
18025 if (attr & RS6000_BTC_SPR)
18027 rettype = gpr_type_node;
18028 argtype = gpr_type_node;
18030 else if (d->code == HTM_BUILTIN_TABORTDC
18031 || d->code == HTM_BUILTIN_TABORTDCI)
18033 rettype = unsigned_type_node;
18034 argtype = gpr_type_node;
18038 rettype = unsigned_type_node;
18039 argtype = unsigned_type_node;
18042 if ((mask & builtin_mask) != mask)
18044 if (TARGET_DEBUG_BUILTIN)
18045 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
18051 if (TARGET_DEBUG_BUILTIN)
18052 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
18053 (long unsigned) i);
18057 op[nopnds++] = (void_func) ? void_type_node : rettype;
18059 if (attr_args == RS6000_BTC_UNARY)
18060 op[nopnds++] = argtype;
18061 else if (attr_args == RS6000_BTC_BINARY)
18063 op[nopnds++] = argtype;
18064 op[nopnds++] = argtype;
18066 else if (attr_args == RS6000_BTC_TERNARY)
18068 op[nopnds++] = argtype;
18069 op[nopnds++] = argtype;
18070 op[nopnds++] = argtype;
18076 type = build_function_type_list (op[0], NULL_TREE);
18079 type = build_function_type_list (op[0], op[1], NULL_TREE);
18082 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
18085 type = build_function_type_list (op[0], op[1], op[2], op[3],
18089 gcc_unreachable ();
18092 def_builtin (d->name, type, d->code);
18096 /* Hash function for builtin functions with up to 3 arguments and a return
18099 builtin_hasher::hash (builtin_hash_struct *bh)
18104 for (i = 0; i < 4; i++)
18106 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
18107 ret = (ret * 2) + bh->uns_p[i];
18113 /* Compare builtin hash entries H1 and H2 for equivalence. */
18115 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
18117 return ((p1->mode[0] == p2->mode[0])
18118 && (p1->mode[1] == p2->mode[1])
18119 && (p1->mode[2] == p2->mode[2])
18120 && (p1->mode[3] == p2->mode[3])
18121 && (p1->uns_p[0] == p2->uns_p[0])
18122 && (p1->uns_p[1] == p2->uns_p[1])
18123 && (p1->uns_p[2] == p2->uns_p[2])
18124 && (p1->uns_p[3] == p2->uns_p[3]));
18127 /* Map types for builtin functions with an explicit return type and up to 3
18128 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
18129 of the argument. */
18131 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
18132 machine_mode mode_arg1, machine_mode mode_arg2,
18133 enum rs6000_builtins builtin, const char *name)
18135 struct builtin_hash_struct h;
18136 struct builtin_hash_struct *h2;
18139 tree ret_type = NULL_TREE;
18140 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
18142 /* Create builtin_hash_table. */
18143 if (builtin_hash_table == NULL)
18144 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
18146 h.type = NULL_TREE;
18147 h.mode[0] = mode_ret;
18148 h.mode[1] = mode_arg0;
18149 h.mode[2] = mode_arg1;
18150 h.mode[3] = mode_arg2;
18156 /* If the builtin is a type that produces unsigned results or takes unsigned
18157 arguments, and it is returned as a decl for the vectorizer (such as
18158 widening multiplies, permute), make sure the arguments and return value
18159 are type correct. */
18162 /* unsigned 1 argument functions. */
18163 case CRYPTO_BUILTIN_VSBOX:
18164 case P8V_BUILTIN_VGBBD:
18165 case MISC_BUILTIN_CDTBCD:
18166 case MISC_BUILTIN_CBCDTD:
18171 /* unsigned 2 argument functions. */
18172 case ALTIVEC_BUILTIN_VMULEUB:
18173 case ALTIVEC_BUILTIN_VMULEUH:
18174 case ALTIVEC_BUILTIN_VMULEUW:
18175 case ALTIVEC_BUILTIN_VMULOUB:
18176 case ALTIVEC_BUILTIN_VMULOUH:
18177 case ALTIVEC_BUILTIN_VMULOUW:
18178 case CRYPTO_BUILTIN_VCIPHER:
18179 case CRYPTO_BUILTIN_VCIPHERLAST:
18180 case CRYPTO_BUILTIN_VNCIPHER:
18181 case CRYPTO_BUILTIN_VNCIPHERLAST:
18182 case CRYPTO_BUILTIN_VPMSUMB:
18183 case CRYPTO_BUILTIN_VPMSUMH:
18184 case CRYPTO_BUILTIN_VPMSUMW:
18185 case CRYPTO_BUILTIN_VPMSUMD:
18186 case CRYPTO_BUILTIN_VPMSUM:
18187 case MISC_BUILTIN_ADDG6S:
18188 case MISC_BUILTIN_DIVWEU:
18189 case MISC_BUILTIN_DIVWEUO:
18190 case MISC_BUILTIN_DIVDEU:
18191 case MISC_BUILTIN_DIVDEUO:
18192 case VSX_BUILTIN_UDIV_V2DI:
18193 case ALTIVEC_BUILTIN_VMAXUB:
18194 case ALTIVEC_BUILTIN_VMINUB:
18195 case ALTIVEC_BUILTIN_VMAXUH:
18196 case ALTIVEC_BUILTIN_VMINUH:
18197 case ALTIVEC_BUILTIN_VMAXUW:
18198 case ALTIVEC_BUILTIN_VMINUW:
18199 case P8V_BUILTIN_VMAXUD:
18200 case P8V_BUILTIN_VMINUD:
18206 /* unsigned 3 argument functions. */
18207 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
18208 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
18209 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
18210 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
18211 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
18212 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
18213 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
18214 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
18215 case VSX_BUILTIN_VPERM_16QI_UNS:
18216 case VSX_BUILTIN_VPERM_8HI_UNS:
18217 case VSX_BUILTIN_VPERM_4SI_UNS:
18218 case VSX_BUILTIN_VPERM_2DI_UNS:
18219 case VSX_BUILTIN_XXSEL_16QI_UNS:
18220 case VSX_BUILTIN_XXSEL_8HI_UNS:
18221 case VSX_BUILTIN_XXSEL_4SI_UNS:
18222 case VSX_BUILTIN_XXSEL_2DI_UNS:
18223 case CRYPTO_BUILTIN_VPERMXOR:
18224 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
18225 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
18226 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
18227 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
18228 case CRYPTO_BUILTIN_VSHASIGMAW:
18229 case CRYPTO_BUILTIN_VSHASIGMAD:
18230 case CRYPTO_BUILTIN_VSHASIGMA:
18237 /* signed permute functions with unsigned char mask. */
18238 case ALTIVEC_BUILTIN_VPERM_16QI:
18239 case ALTIVEC_BUILTIN_VPERM_8HI:
18240 case ALTIVEC_BUILTIN_VPERM_4SI:
18241 case ALTIVEC_BUILTIN_VPERM_4SF:
18242 case ALTIVEC_BUILTIN_VPERM_2DI:
18243 case ALTIVEC_BUILTIN_VPERM_2DF:
18244 case VSX_BUILTIN_VPERM_16QI:
18245 case VSX_BUILTIN_VPERM_8HI:
18246 case VSX_BUILTIN_VPERM_4SI:
18247 case VSX_BUILTIN_VPERM_4SF:
18248 case VSX_BUILTIN_VPERM_2DI:
18249 case VSX_BUILTIN_VPERM_2DF:
18253 /* unsigned args, signed return. */
18254 case VSX_BUILTIN_XVCVUXDSP:
18255 case VSX_BUILTIN_XVCVUXDDP_UNS:
18256 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
18260 /* signed args, unsigned return. */
18261 case VSX_BUILTIN_XVCVDPUXDS_UNS:
18262 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
18263 case MISC_BUILTIN_UNPACK_TD:
18264 case MISC_BUILTIN_UNPACK_V1TI:
18268 /* unsigned arguments, bool return (compares). */
18269 case ALTIVEC_BUILTIN_VCMPEQUB:
18270 case ALTIVEC_BUILTIN_VCMPEQUH:
18271 case ALTIVEC_BUILTIN_VCMPEQUW:
18272 case P8V_BUILTIN_VCMPEQUD:
18273 case VSX_BUILTIN_CMPGE_U16QI:
18274 case VSX_BUILTIN_CMPGE_U8HI:
18275 case VSX_BUILTIN_CMPGE_U4SI:
18276 case VSX_BUILTIN_CMPGE_U2DI:
18277 case ALTIVEC_BUILTIN_VCMPGTUB:
18278 case ALTIVEC_BUILTIN_VCMPGTUH:
18279 case ALTIVEC_BUILTIN_VCMPGTUW:
18280 case P8V_BUILTIN_VCMPGTUD:
18285 /* unsigned arguments for 128-bit pack instructions. */
18286 case MISC_BUILTIN_PACK_TD:
18287 case MISC_BUILTIN_PACK_V1TI:
18292 /* unsigned second arguments (vector shift right). */
18293 case ALTIVEC_BUILTIN_VSRB:
18294 case ALTIVEC_BUILTIN_VSRH:
18295 case ALTIVEC_BUILTIN_VSRW:
18296 case P8V_BUILTIN_VSRD:
18304 /* Figure out how many args are present. */
18305 while (num_args > 0 && h.mode[num_args] == VOIDmode)
18308 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
18309 if (!ret_type && h.uns_p[0])
18310 ret_type = builtin_mode_to_type[h.mode[0]][0];
18313 fatal_error (input_location,
18314 "internal error: builtin function %qs had an unexpected "
18315 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
18317 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
18318 arg_type[i] = NULL_TREE;
18320 for (i = 0; i < num_args; i++)
18322 int m = (int) h.mode[i+1];
18323 int uns_p = h.uns_p[i+1];
18325 arg_type[i] = builtin_mode_to_type[m][uns_p];
18326 if (!arg_type[i] && uns_p)
18327 arg_type[i] = builtin_mode_to_type[m][0];
18330 fatal_error (input_location,
18331 "internal error: builtin function %qs, argument %d "
18332 "had unexpected argument type %qs", name, i,
18333 GET_MODE_NAME (m));
18336 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
18337 if (*found == NULL)
18339 h2 = ggc_alloc<builtin_hash_struct> ();
18343 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
18344 arg_type[2], NULL_TREE);
18347 return (*found)->type;
18351 rs6000_common_init_builtins (void)
18353 const struct builtin_description *d;
18356 tree opaque_ftype_opaque = NULL_TREE;
18357 tree opaque_ftype_opaque_opaque = NULL_TREE;
18358 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
18359 tree v2si_ftype = NULL_TREE;
18360 tree v2si_ftype_qi = NULL_TREE;
18361 tree v2si_ftype_v2si_qi = NULL_TREE;
18362 tree v2si_ftype_int_qi = NULL_TREE;
18363 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
18365 if (!TARGET_PAIRED_FLOAT)
18367 builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
18368 builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
18371 /* Paired builtins are only available if you build a compiler with the
18372 appropriate options, so only create those builtins with the appropriate
18373 compiler option. Create Altivec and VSX builtins on machines with at
18374 least the general purpose extensions (970 and newer) to allow the use of
18375 the target attribute.. */
18377 if (TARGET_EXTRA_BUILTINS)
18378 builtin_mask |= RS6000_BTM_COMMON;
18380 /* Add the ternary operators. */
18382 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
18385 HOST_WIDE_INT mask = d->mask;
18387 if ((mask & builtin_mask) != mask)
18389 if (TARGET_DEBUG_BUILTIN)
18390 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
18394 if (rs6000_overloaded_builtin_p (d->code))
18396 if (! (type = opaque_ftype_opaque_opaque_opaque))
18397 type = opaque_ftype_opaque_opaque_opaque
18398 = build_function_type_list (opaque_V4SI_type_node,
18399 opaque_V4SI_type_node,
18400 opaque_V4SI_type_node,
18401 opaque_V4SI_type_node,
18406 enum insn_code icode = d->icode;
18409 if (TARGET_DEBUG_BUILTIN)
18410 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
18416 if (icode == CODE_FOR_nothing)
18418 if (TARGET_DEBUG_BUILTIN)
18419 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
18425 type = builtin_function_type (insn_data[icode].operand[0].mode,
18426 insn_data[icode].operand[1].mode,
18427 insn_data[icode].operand[2].mode,
18428 insn_data[icode].operand[3].mode,
18432 def_builtin (d->name, type, d->code);
18435 /* Add the binary operators. */
18437 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
18439 machine_mode mode0, mode1, mode2;
18441 HOST_WIDE_INT mask = d->mask;
18443 if ((mask & builtin_mask) != mask)
18445 if (TARGET_DEBUG_BUILTIN)
18446 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
18450 if (rs6000_overloaded_builtin_p (d->code))
18452 if (! (type = opaque_ftype_opaque_opaque))
18453 type = opaque_ftype_opaque_opaque
18454 = build_function_type_list (opaque_V4SI_type_node,
18455 opaque_V4SI_type_node,
18456 opaque_V4SI_type_node,
18461 enum insn_code icode = d->icode;
18464 if (TARGET_DEBUG_BUILTIN)
18465 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
18471 if (icode == CODE_FOR_nothing)
18473 if (TARGET_DEBUG_BUILTIN)
18474 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
18480 mode0 = insn_data[icode].operand[0].mode;
18481 mode1 = insn_data[icode].operand[1].mode;
18482 mode2 = insn_data[icode].operand[2].mode;
18484 if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
18486 if (! (type = v2si_ftype_v2si_qi))
18487 type = v2si_ftype_v2si_qi
18488 = build_function_type_list (opaque_V2SI_type_node,
18489 opaque_V2SI_type_node,
18494 else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
18495 && mode2 == QImode)
18497 if (! (type = v2si_ftype_int_qi))
18498 type = v2si_ftype_int_qi
18499 = build_function_type_list (opaque_V2SI_type_node,
18506 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
18510 def_builtin (d->name, type, d->code);
18513 /* Add the simple unary operators. */
18515 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
18517 machine_mode mode0, mode1;
18519 HOST_WIDE_INT mask = d->mask;
18521 if ((mask & builtin_mask) != mask)
18523 if (TARGET_DEBUG_BUILTIN)
18524 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
18528 if (rs6000_overloaded_builtin_p (d->code))
18530 if (! (type = opaque_ftype_opaque))
18531 type = opaque_ftype_opaque
18532 = build_function_type_list (opaque_V4SI_type_node,
18533 opaque_V4SI_type_node,
18538 enum insn_code icode = d->icode;
18541 if (TARGET_DEBUG_BUILTIN)
18542 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
18548 if (icode == CODE_FOR_nothing)
18550 if (TARGET_DEBUG_BUILTIN)
18551 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
18557 mode0 = insn_data[icode].operand[0].mode;
18558 mode1 = insn_data[icode].operand[1].mode;
18560 if (mode0 == V2SImode && mode1 == QImode)
18562 if (! (type = v2si_ftype_qi))
18563 type = v2si_ftype_qi
18564 = build_function_type_list (opaque_V2SI_type_node,
18570 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
18574 def_builtin (d->name, type, d->code);
18577 /* Add the simple no-argument operators. */
18579 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
18581 machine_mode mode0;
18583 HOST_WIDE_INT mask = d->mask;
18585 if ((mask & builtin_mask) != mask)
18587 if (TARGET_DEBUG_BUILTIN)
18588 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
18591 if (rs6000_overloaded_builtin_p (d->code))
18593 if (!opaque_ftype_opaque)
18594 opaque_ftype_opaque
18595 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
18596 type = opaque_ftype_opaque;
18600 enum insn_code icode = d->icode;
18603 if (TARGET_DEBUG_BUILTIN)
18604 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
18605 (long unsigned) i);
18608 if (icode == CODE_FOR_nothing)
18610 if (TARGET_DEBUG_BUILTIN)
18612 "rs6000_builtin, skip no-argument %s (no code)\n",
18616 mode0 = insn_data[icode].operand[0].mode;
18617 if (mode0 == V2SImode)
18619 /* code for paired single */
18620 if (! (type = v2si_ftype))
18623 = build_function_type_list (opaque_V2SI_type_node,
18629 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
18632 def_builtin (d->name, type, d->code);
18636 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
18638 init_float128_ibm (machine_mode mode)
18640 if (!TARGET_XL_COMPAT)
18642 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
18643 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
18644 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
18645 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
18647 if (!TARGET_HARD_FLOAT)
18649 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
18650 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
18651 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
18652 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
18653 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
18654 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
18655 set_optab_libfunc (le_optab, mode, "__gcc_qle");
18656 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
18658 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
18659 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
18660 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
18661 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
18662 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
18663 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
18664 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
18665 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
18670 set_optab_libfunc (add_optab, mode, "_xlqadd");
18671 set_optab_libfunc (sub_optab, mode, "_xlqsub");
18672 set_optab_libfunc (smul_optab, mode, "_xlqmul");
18673 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
18676 /* Add various conversions for IFmode to use the traditional TFmode
18678 if (mode == IFmode)
18680 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf2");
18681 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf2");
18682 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctftd2");
18683 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd2");
18684 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd2");
18685 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdtf2");
18687 if (TARGET_POWERPC64)
18689 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
18690 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
18691 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
18692 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
18697 /* Set up IEEE 128-bit floating point routines. Use different names if the
18698 arguments can be passed in a vector register. The historical PowerPC
18699 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
18700 continue to use that if we aren't using vector registers to pass IEEE
18701 128-bit floating point. */
18704 init_float128_ieee (machine_mode mode)
18706 if (FLOAT128_VECTOR_P (mode))
18708 set_optab_libfunc (add_optab, mode, "__addkf3");
18709 set_optab_libfunc (sub_optab, mode, "__subkf3");
18710 set_optab_libfunc (neg_optab, mode, "__negkf2");
18711 set_optab_libfunc (smul_optab, mode, "__mulkf3");
18712 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
18713 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
18714 set_optab_libfunc (abs_optab, mode, "__abstkf2");
18716 set_optab_libfunc (eq_optab, mode, "__eqkf2");
18717 set_optab_libfunc (ne_optab, mode, "__nekf2");
18718 set_optab_libfunc (gt_optab, mode, "__gtkf2");
18719 set_optab_libfunc (ge_optab, mode, "__gekf2");
18720 set_optab_libfunc (lt_optab, mode, "__ltkf2");
18721 set_optab_libfunc (le_optab, mode, "__lekf2");
18722 set_optab_libfunc (unord_optab, mode, "__unordkf2");
18724 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
18725 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
18726 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
18727 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
18729 set_conv_libfunc (sext_optab, mode, IFmode, "__extendtfkf2");
18730 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
18731 set_conv_libfunc (sext_optab, mode, TFmode, "__extendtfkf2");
18733 set_conv_libfunc (trunc_optab, IFmode, mode, "__trunckftf2");
18734 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
18735 set_conv_libfunc (trunc_optab, TFmode, mode, "__trunckftf2");
18737 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf2");
18738 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf2");
18739 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunckftd2");
18740 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd2");
18741 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd2");
18742 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtdkf2");
18744 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
18745 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
18746 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
18747 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
18749 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
18750 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
18751 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
18752 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
18754 if (TARGET_POWERPC64)
18756 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
18757 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
18758 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
18759 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
18765 set_optab_libfunc (add_optab, mode, "_q_add");
18766 set_optab_libfunc (sub_optab, mode, "_q_sub");
18767 set_optab_libfunc (neg_optab, mode, "_q_neg");
18768 set_optab_libfunc (smul_optab, mode, "_q_mul");
18769 set_optab_libfunc (sdiv_optab, mode, "_q_div");
18770 if (TARGET_PPC_GPOPT)
18771 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
18773 set_optab_libfunc (eq_optab, mode, "_q_feq");
18774 set_optab_libfunc (ne_optab, mode, "_q_fne");
18775 set_optab_libfunc (gt_optab, mode, "_q_fgt");
18776 set_optab_libfunc (ge_optab, mode, "_q_fge");
18777 set_optab_libfunc (lt_optab, mode, "_q_flt");
18778 set_optab_libfunc (le_optab, mode, "_q_fle");
18780 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
18781 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
18782 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
18783 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
18784 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
18785 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
18786 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
18787 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
18792 rs6000_init_libfuncs (void)
18794 /* __float128 support. */
18795 if (TARGET_FLOAT128_TYPE)
18797 init_float128_ibm (IFmode);
18798 init_float128_ieee (KFmode);
18801 /* AIX/Darwin/64-bit Linux quad floating point routines. */
18802 if (TARGET_LONG_DOUBLE_128)
18804 if (!TARGET_IEEEQUAD)
18805 init_float128_ibm (TFmode);
18807 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18809 init_float128_ieee (TFmode);
18813 /* Emit a potentially record-form instruction, setting DST from SRC.
18814 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18815 signed comparison of DST with zero. If DOT is 1, the generated RTL
18816 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18817 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18818 a separate COMPARE. */
18821 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
18825 emit_move_insn (dst, src);
18829 if (cc_reg_not_cr0_operand (ccreg, CCmode))
18831 emit_move_insn (dst, src);
18832 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18836 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18839 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18840 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18844 rtx set = gen_rtx_SET (dst, src);
18845 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18850 /* A validation routine: say whether CODE, a condition code, and MODE
18851 match. The other alternatives either don't make sense or should
18852 never be generated. */
18855 validate_condition_mode (enum rtx_code code, machine_mode mode)
18857 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18858 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18859 && GET_MODE_CLASS (mode) == MODE_CC);
18861 /* These don't make sense. */
18862 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18863 || mode != CCUNSmode);
18865 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18866 || mode == CCUNSmode);
18868 gcc_assert (mode == CCFPmode
18869 || (code != ORDERED && code != UNORDERED
18870 && code != UNEQ && code != LTGT
18871 && code != UNGT && code != UNLT
18872 && code != UNGE && code != UNLE));
18874 /* These should never be generated except for
18875 flag_finite_math_only. */
18876 gcc_assert (mode != CCFPmode
18877 || flag_finite_math_only
18878 || (code != LE && code != GE
18879 && code != UNEQ && code != LTGT
18880 && code != UNGT && code != UNLT));
18882 /* These are invalid; the information is not there. */
18883 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18887 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18888 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18889 not zero, store there the bit offset (counted from the right) where
18890 the single stretch of 1 bits begins; and similarly for B, the bit
18891 offset where it ends. */
18894 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18896 unsigned HOST_WIDE_INT val = INTVAL (mask);
18897 unsigned HOST_WIDE_INT bit;
18899 int n = GET_MODE_PRECISION (mode);
18901 if (mode != DImode && mode != SImode)
18904 if (INTVAL (mask) >= 0)
18907 ne = exact_log2 (bit);
18908 nb = exact_log2 (val + bit);
18910 else if (val + 1 == 0)
18919 nb = exact_log2 (bit);
18920 ne = exact_log2 (val + bit);
18925 ne = exact_log2 (bit);
18926 if (val + bit == 0)
18934 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18945 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18946 or rldicr instruction, to implement an AND with it in mode MODE. */
18949 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18953 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18956 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18958 if (mode == DImode)
18959 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18961 /* For SImode, rlwinm can do everything. */
18962 if (mode == SImode)
18963 return (nb < 32 && ne < 32);
18968 /* Return the instruction template for an AND with mask in mode MODE, with
18969 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18972 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18976 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18977 gcc_unreachable ();
18979 if (mode == DImode && ne == 0)
18981 operands[3] = GEN_INT (63 - nb);
18983 return "rldicl. %0,%1,0,%3";
18984 return "rldicl %0,%1,0,%3";
18987 if (mode == DImode && nb == 63)
18989 operands[3] = GEN_INT (63 - ne);
18991 return "rldicr. %0,%1,0,%3";
18992 return "rldicr %0,%1,0,%3";
18995 if (nb < 32 && ne < 32)
18997 operands[3] = GEN_INT (31 - nb);
18998 operands[4] = GEN_INT (31 - ne);
19000 return "rlwinm. %0,%1,0,%3,%4";
19001 return "rlwinm %0,%1,0,%3,%4";
19004 gcc_unreachable ();
19007 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
19008 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
19009 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
19012 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
19016 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
19019 int n = GET_MODE_PRECISION (mode);
19022 if (CONST_INT_P (XEXP (shift, 1)))
19024 sh = INTVAL (XEXP (shift, 1));
19025 if (sh < 0 || sh >= n)
19029 rtx_code code = GET_CODE (shift);
19031 /* Convert any shift by 0 to a rotate, to simplify below code. */
19035 /* Convert rotate to simple shift if we can, to make analysis simpler. */
19036 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
19038 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
19044 /* DImode rotates need rld*. */
19045 if (mode == DImode && code == ROTATE)
19046 return (nb == 63 || ne == 0 || ne == sh);
19048 /* SImode rotates need rlw*. */
19049 if (mode == SImode && code == ROTATE)
19050 return (nb < 32 && ne < 32 && sh < 32);
19052 /* Wrap-around masks are only okay for rotates. */
19056 /* Variable shifts are only okay for rotates. */
19060 /* Don't allow ASHIFT if the mask is wrong for that. */
19061 if (code == ASHIFT && ne < sh)
19064 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
19065 if the mask is wrong for that. */
19066 if (nb < 32 && ne < 32 && sh < 32
19067 && !(code == LSHIFTRT && nb >= 32 - sh))
19070 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
19071 if the mask is wrong for that. */
19072 if (code == LSHIFTRT)
19074 if (nb == 63 || ne == 0 || ne == sh)
19075 return !(code == LSHIFTRT && nb >= sh);
19080 /* Return the instruction template for a shift with mask in mode MODE, with
19081 operands OPERANDS. If DOT is true, make it a record-form instruction. */
19084 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
19088 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
19089 gcc_unreachable ();
19091 if (mode == DImode && ne == 0)
19093 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19094 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
19095 operands[3] = GEN_INT (63 - nb);
19097 return "rld%I2cl. %0,%1,%2,%3";
19098 return "rld%I2cl %0,%1,%2,%3";
19101 if (mode == DImode && nb == 63)
19103 operands[3] = GEN_INT (63 - ne);
19105 return "rld%I2cr. %0,%1,%2,%3";
19106 return "rld%I2cr %0,%1,%2,%3";
19110 && GET_CODE (operands[4]) != LSHIFTRT
19111 && CONST_INT_P (operands[2])
19112 && ne == INTVAL (operands[2]))
19114 operands[3] = GEN_INT (63 - nb);
19116 return "rld%I2c. %0,%1,%2,%3";
19117 return "rld%I2c %0,%1,%2,%3";
19120 if (nb < 32 && ne < 32)
19122 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19123 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
19124 operands[3] = GEN_INT (31 - nb);
19125 operands[4] = GEN_INT (31 - ne);
19126 /* This insn can also be a 64-bit rotate with mask that really makes
19127 it just a shift right (with mask); the %h below are to adjust for
19128 that situation (shift count is >= 32 in that case). */
19130 return "rlw%I2nm. %0,%1,%h2,%3,%4";
19131 return "rlw%I2nm %0,%1,%h2,%3,%4";
19134 gcc_unreachable ();
19137 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
19138 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
19139 ASHIFT, or LSHIFTRT) in mode MODE. */
19142 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
19146 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
19149 int n = GET_MODE_PRECISION (mode);
19151 int sh = INTVAL (XEXP (shift, 1));
19152 if (sh < 0 || sh >= n)
19155 rtx_code code = GET_CODE (shift);
19157 /* Convert any shift by 0 to a rotate, to simplify below code. */
19161 /* Convert rotate to simple shift if we can, to make analysis simpler. */
19162 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
19164 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
19170 /* DImode rotates need rldimi. */
19171 if (mode == DImode && code == ROTATE)
19174 /* SImode rotates need rlwimi. */
19175 if (mode == SImode && code == ROTATE)
19176 return (nb < 32 && ne < 32 && sh < 32);
19178 /* Wrap-around masks are only okay for rotates. */
19182 /* Don't allow ASHIFT if the mask is wrong for that. */
19183 if (code == ASHIFT && ne < sh)
19186 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
19187 if the mask is wrong for that. */
19188 if (nb < 32 && ne < 32 && sh < 32
19189 && !(code == LSHIFTRT && nb >= 32 - sh))
19192 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
19193 if the mask is wrong for that. */
19194 if (code == LSHIFTRT)
19197 return !(code == LSHIFTRT && nb >= sh);
19202 /* Return the instruction template for an insert with mask in mode MODE, with
19203 operands OPERANDS. If DOT is true, make it a record-form instruction. */
19206 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
19210 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
19211 gcc_unreachable ();
19213 /* Prefer rldimi because rlwimi is cracked. */
19214 if (TARGET_POWERPC64
19215 && (!dot || mode == DImode)
19216 && GET_CODE (operands[4]) != LSHIFTRT
19217 && ne == INTVAL (operands[2]))
19219 operands[3] = GEN_INT (63 - nb);
19221 return "rldimi. %0,%1,%2,%3";
19222 return "rldimi %0,%1,%2,%3";
19225 if (nb < 32 && ne < 32)
19227 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
19228 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
19229 operands[3] = GEN_INT (31 - nb);
19230 operands[4] = GEN_INT (31 - ne);
19232 return "rlwimi. %0,%1,%2,%3,%4";
19233 return "rlwimi %0,%1,%2,%3,%4";
19236 gcc_unreachable ();
19239 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
19240 using two machine instructions. */
19243 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
19245 /* There are two kinds of AND we can handle with two insns:
19246 1) those we can do with two rl* insn;
19249 We do not handle that last case yet. */
19251 /* If there is just one stretch of ones, we can do it. */
19252 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
19255 /* Otherwise, fill in the lowest "hole"; if we can do the result with
19256 one insn, we can do the whole thing with two. */
19257 unsigned HOST_WIDE_INT val = INTVAL (c);
19258 unsigned HOST_WIDE_INT bit1 = val & -val;
19259 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
19260 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
19261 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
19262 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
19265 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
19266 If EXPAND is true, split rotate-and-mask instructions we generate to
19267 their constituent parts as well (this is used during expand); if DOT
19268 is 1, make the last insn a record-form instruction clobbering the
19269 destination GPR and setting the CC reg (from operands[3]); if 2, set
19270 that GPR as well as the CC reg. */
19273 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
19275 gcc_assert (!(expand && dot));
19277 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
19279 /* If it is one stretch of ones, it is DImode; shift left, mask, then
19280 shift right. This generates better code than doing the masks without
19281 shifts, or shifting first right and then left. */
19283 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
19285 gcc_assert (mode == DImode);
19287 int shift = 63 - nb;
19290 rtx tmp1 = gen_reg_rtx (DImode);
19291 rtx tmp2 = gen_reg_rtx (DImode);
19292 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
19293 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
19294 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
19298 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
19299 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
19300 emit_move_insn (operands[0], tmp);
19301 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
19302 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19307 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
19308 that does the rest. */
19309 unsigned HOST_WIDE_INT bit1 = val & -val;
19310 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
19311 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
19312 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
19314 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
19315 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
19317 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
19319 /* Two "no-rotate"-and-mask instructions, for SImode. */
19320 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
19322 gcc_assert (mode == SImode);
19324 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
19325 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
19326 emit_move_insn (reg, tmp);
19327 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
19328 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19332 gcc_assert (mode == DImode);
19334 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
19335 insns; we have to do the first in SImode, because it wraps. */
19336 if (mask2 <= 0xffffffff
19337 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
19339 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
19340 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
19342 rtx reg_low = gen_lowpart (SImode, reg);
19343 emit_move_insn (reg_low, tmp);
19344 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
19345 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19349 /* Two rld* insns: rotate, clear the hole in the middle (which now is
19350 at the top end), rotate back and clear the other hole. */
19351 int right = exact_log2 (bit3);
19352 int left = 64 - right;
19354 /* Rotate the mask too. */
19355 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
19359 rtx tmp1 = gen_reg_rtx (DImode);
19360 rtx tmp2 = gen_reg_rtx (DImode);
19361 rtx tmp3 = gen_reg_rtx (DImode);
19362 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
19363 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
19364 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
19365 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
19369 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
19370 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
19371 emit_move_insn (operands[0], tmp);
19372 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
19373 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
19374 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
19378 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
19379 for lfq and stfq insns iff the registers are hard registers. */
19382 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
19384 /* We might have been passed a SUBREG. */
19385 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
19388 /* We might have been passed non floating point registers. */
19389 if (!FP_REGNO_P (REGNO (reg1))
19390 || !FP_REGNO_P (REGNO (reg2)))
19393 return (REGNO (reg1) == REGNO (reg2) - 1);
19396 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
19397 addr1 and addr2 must be in consecutive memory locations
19398 (addr2 == addr1 + 8). */
19401 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
19404 unsigned int reg1, reg2;
19405 int offset1, offset2;
19407 /* The mems cannot be volatile. */
19408 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
19411 addr1 = XEXP (mem1, 0);
19412 addr2 = XEXP (mem2, 0);
19414 /* Extract an offset (if used) from the first addr. */
19415 if (GET_CODE (addr1) == PLUS)
19417 /* If not a REG, return zero. */
19418 if (GET_CODE (XEXP (addr1, 0)) != REG)
19422 reg1 = REGNO (XEXP (addr1, 0));
19423 /* The offset must be constant! */
19424 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
19426 offset1 = INTVAL (XEXP (addr1, 1));
19429 else if (GET_CODE (addr1) != REG)
19433 reg1 = REGNO (addr1);
19434 /* This was a simple (mem (reg)) expression. Offset is 0. */
19438 /* And now for the second addr. */
19439 if (GET_CODE (addr2) == PLUS)
19441 /* If not a REG, return zero. */
19442 if (GET_CODE (XEXP (addr2, 0)) != REG)
19446 reg2 = REGNO (XEXP (addr2, 0));
19447 /* The offset must be constant. */
19448 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
19450 offset2 = INTVAL (XEXP (addr2, 1));
19453 else if (GET_CODE (addr2) != REG)
19457 reg2 = REGNO (addr2);
19458 /* This was a simple (mem (reg)) expression. Offset is 0. */
19462 /* Both of these must have the same base register. */
19466 /* The offset for the second addr must be 8 more than the first addr. */
19467 if (offset2 != offset1 + 8)
19470 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
19475 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
19476 need to use DDmode, in all other cases we can use the same mode. */
19477 static machine_mode
19478 rs6000_secondary_memory_needed_mode (machine_mode mode)
19480 if (lra_in_progress && mode == SDmode)
19485 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
19486 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
19487 only work on the traditional altivec registers, note if an altivec register
19490 static enum rs6000_reg_type
19491 register_to_reg_type (rtx reg, bool *is_altivec)
19493 HOST_WIDE_INT regno;
19494 enum reg_class rclass;
19496 if (GET_CODE (reg) == SUBREG)
19497 reg = SUBREG_REG (reg);
19500 return NO_REG_TYPE;
19502 regno = REGNO (reg);
19503 if (regno >= FIRST_PSEUDO_REGISTER)
19505 if (!lra_in_progress && !reload_completed)
19506 return PSEUDO_REG_TYPE;
19508 regno = true_regnum (reg);
19509 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
19510 return PSEUDO_REG_TYPE;
19513 gcc_assert (regno >= 0);
19515 if (is_altivec && ALTIVEC_REGNO_P (regno))
19516 *is_altivec = true;
19518 rclass = rs6000_regno_regclass[regno];
19519 return reg_class_to_reg_type[(int)rclass];
19522 /* Helper function to return the cost of adding a TOC entry address. */
19525 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
19529 if (TARGET_CMODEL != CMODEL_SMALL)
19530 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
19533 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
19538 /* Helper function for rs6000_secondary_reload to determine whether the memory
19539 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
19540 needs reloading. Return negative if the memory is not handled by the memory
19541 helper functions and to try a different reload method, 0 if no additional
19542 instructions are need, and positive to give the extra cost for the
19546 rs6000_secondary_reload_memory (rtx addr,
19547 enum reg_class rclass,
19550 int extra_cost = 0;
19551 rtx reg, and_arg, plus_arg0, plus_arg1;
19552 addr_mask_type addr_mask;
19553 const char *type = NULL;
19554 const char *fail_msg = NULL;
19556 if (GPR_REG_CLASS_P (rclass))
19557 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19559 else if (rclass == FLOAT_REGS)
19560 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19562 else if (rclass == ALTIVEC_REGS)
19563 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19565 /* For the combined VSX_REGS, turn off Altivec AND -16. */
19566 else if (rclass == VSX_REGS)
19567 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
19568 & ~RELOAD_REG_AND_M16);
19570 /* If the register allocator hasn't made up its mind yet on the register
19571 class to use, settle on defaults to use. */
19572 else if (rclass == NO_REGS)
19574 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
19575 & ~RELOAD_REG_AND_M16);
19577 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
19578 addr_mask &= ~(RELOAD_REG_INDEXED
19579 | RELOAD_REG_PRE_INCDEC
19580 | RELOAD_REG_PRE_MODIFY);
19586 /* If the register isn't valid in this register class, just return now. */
19587 if ((addr_mask & RELOAD_REG_VALID) == 0)
19589 if (TARGET_DEBUG_ADDR)
19592 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19593 "not valid in class\n",
19594 GET_MODE_NAME (mode), reg_class_names[rclass]);
19601 switch (GET_CODE (addr))
19603 /* Does the register class supports auto update forms for this mode? We
19604 don't need a scratch register, since the powerpc only supports
19605 PRE_INC, PRE_DEC, and PRE_MODIFY. */
19608 reg = XEXP (addr, 0);
19609 if (!base_reg_operand (addr, GET_MODE (reg)))
19611 fail_msg = "no base register #1";
19615 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19623 reg = XEXP (addr, 0);
19624 plus_arg1 = XEXP (addr, 1);
19625 if (!base_reg_operand (reg, GET_MODE (reg))
19626 || GET_CODE (plus_arg1) != PLUS
19627 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
19629 fail_msg = "bad PRE_MODIFY";
19633 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19640 /* Do we need to simulate AND -16 to clear the bottom address bits used
19641 in VMX load/stores? Only allow the AND for vector sizes. */
19643 and_arg = XEXP (addr, 0);
19644 if (GET_MODE_SIZE (mode) != 16
19645 || GET_CODE (XEXP (addr, 1)) != CONST_INT
19646 || INTVAL (XEXP (addr, 1)) != -16)
19648 fail_msg = "bad Altivec AND #1";
19652 if (rclass != ALTIVEC_REGS)
19654 if (legitimate_indirect_address_p (and_arg, false))
19657 else if (legitimate_indexed_address_p (and_arg, false))
19662 fail_msg = "bad Altivec AND #2";
19670 /* If this is an indirect address, make sure it is a base register. */
19673 if (!legitimate_indirect_address_p (addr, false))
19680 /* If this is an indexed address, make sure the register class can handle
19681 indexed addresses for this mode. */
19683 plus_arg0 = XEXP (addr, 0);
19684 plus_arg1 = XEXP (addr, 1);
19686 /* (plus (plus (reg) (constant)) (constant)) is generated during
19687 push_reload processing, so handle it now. */
19688 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
19690 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19697 /* (plus (plus (reg) (constant)) (reg)) is also generated during
19698 push_reload processing, so handle it now. */
19699 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
19701 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19704 type = "indexed #2";
19708 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
19710 fail_msg = "no base register #2";
19714 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
19716 if ((addr_mask & RELOAD_REG_INDEXED) == 0
19717 || !legitimate_indexed_address_p (addr, false))
19724 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
19725 && CONST_INT_P (plus_arg1))
19727 if (!quad_address_offset_p (INTVAL (plus_arg1)))
19730 type = "vector d-form offset";
19734 /* Make sure the register class can handle offset addresses. */
19735 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19737 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19740 type = "offset #2";
19746 fail_msg = "bad PLUS";
19753 /* Quad offsets are restricted and can't handle normal addresses. */
19754 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19757 type = "vector d-form lo_sum";
19760 else if (!legitimate_lo_sum_address_p (mode, addr, false))
19762 fail_msg = "bad LO_SUM";
19766 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19773 /* Static addresses need to create a TOC entry. */
19777 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19780 type = "vector d-form lo_sum #2";
19786 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
19790 /* TOC references look like offsetable memory. */
19792 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
19794 fail_msg = "bad UNSPEC";
19798 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
19801 type = "vector d-form lo_sum #3";
19804 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19807 type = "toc reference";
19813 fail_msg = "bad address";
19818 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
19820 if (extra_cost < 0)
19822 "rs6000_secondary_reload_memory error: mode = %s, "
19823 "class = %s, addr_mask = '%s', %s\n",
19824 GET_MODE_NAME (mode),
19825 reg_class_names[rclass],
19826 rs6000_debug_addr_mask (addr_mask, false),
19827 (fail_msg != NULL) ? fail_msg : "<bad address>");
19831 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19832 "addr_mask = '%s', extra cost = %d, %s\n",
19833 GET_MODE_NAME (mode),
19834 reg_class_names[rclass],
19835 rs6000_debug_addr_mask (addr_mask, false),
19837 (type) ? type : "<none>");
19845 /* Helper function for rs6000_secondary_reload to return true if a move to a
19846 different register classe is really a simple move. */
19849 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19850 enum rs6000_reg_type from_type,
19853 int size = GET_MODE_SIZE (mode);
19855 /* Add support for various direct moves available. In this function, we only
19856 look at cases where we don't need any extra registers, and one or more
19857 simple move insns are issued. Originally small integers are not allowed
19858 in FPR/VSX registers. Single precision binary floating is not a simple
19859 move because we need to convert to the single precision memory layout.
19860 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19861 need special direct move handling, which we do not support yet. */
19862 if (TARGET_DIRECT_MOVE
19863 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19864 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19866 if (TARGET_POWERPC64)
19868 /* ISA 2.07: MTVSRD or MVFVSRD. */
19872 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19873 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19877 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19878 if (TARGET_P8_VECTOR)
19880 if (mode == SImode)
19883 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19887 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19888 if (mode == SDmode)
19892 /* Power6+: MFTGPR or MFFGPR. */
19893 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
19894 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
19895 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19898 /* Move to/from SPR. */
19899 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19900 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19901 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19907 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19908 special direct moves that involve allocating an extra register, return the
19909 insn code of the helper function if there is such a function or
19910 CODE_FOR_nothing if not. */
19913 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19914 enum rs6000_reg_type from_type,
19916 secondary_reload_info *sri,
19920 enum insn_code icode = CODE_FOR_nothing;
19922 int size = GET_MODE_SIZE (mode);
19924 if (TARGET_POWERPC64 && size == 16)
19926 /* Handle moving 128-bit values from GPRs to VSX point registers on
19927 ISA 2.07 (power8, power9) when running in 64-bit mode using
19928 XXPERMDI to glue the two 64-bit values back together. */
19929 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19931 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19932 icode = reg_addr[mode].reload_vsx_gpr;
19935 /* Handle moving 128-bit values from VSX point registers to GPRs on
19936 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19937 bottom 64-bit value. */
19938 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19940 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19941 icode = reg_addr[mode].reload_gpr_vsx;
19945 else if (TARGET_POWERPC64 && mode == SFmode)
19947 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19949 cost = 3; /* xscvdpspn, mfvsrd, and. */
19950 icode = reg_addr[mode].reload_gpr_vsx;
19953 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19955 cost = 2; /* mtvsrz, xscvspdpn. */
19956 icode = reg_addr[mode].reload_vsx_gpr;
19960 else if (!TARGET_POWERPC64 && size == 8)
19962 /* Handle moving 64-bit values from GPRs to floating point registers on
19963 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19964 32-bit values back together. Altivec register classes must be handled
19965 specially since a different instruction is used, and the secondary
19966 reload support requires a single instruction class in the scratch
19967 register constraint. However, right now TFmode is not allowed in
19968 Altivec registers, so the pattern will never match. */
19969 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19971 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19972 icode = reg_addr[mode].reload_fpr_gpr;
19976 if (icode != CODE_FOR_nothing)
19981 sri->icode = icode;
19982 sri->extra_cost = cost;
19989 /* Return whether a move between two register classes can be done either
19990 directly (simple move) or via a pattern that uses a single extra temporary
19991 (using ISA 2.07's direct move in this case. */
19994 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19995 enum rs6000_reg_type from_type,
19997 secondary_reload_info *sri,
20000 /* Fall back to load/store reloads if either type is not a register. */
20001 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
20004 /* If we haven't allocated registers yet, assume the move can be done for the
20005 standard register types. */
20006 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
20007 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
20008 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
20011 /* Moves to the same set of registers is a simple move for non-specialized
20013 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
20016 /* Check whether a simple move can be done directly. */
20017 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
20021 sri->icode = CODE_FOR_nothing;
20022 sri->extra_cost = 0;
20027 /* Now check if we can do it in a few steps. */
20028 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
20032 /* Inform reload about cases where moving X with a mode MODE to a register in
20033 RCLASS requires an extra scratch or immediate register. Return the class
20034 needed for the immediate register.
20036 For VSX and Altivec, we may need a register to convert sp+offset into
20039 For misaligned 64-bit gpr loads and stores we need a register to
20040 convert an offset address to indirect. */
20043 rs6000_secondary_reload (bool in_p,
20045 reg_class_t rclass_i,
20047 secondary_reload_info *sri)
20049 enum reg_class rclass = (enum reg_class) rclass_i;
20050 reg_class_t ret = ALL_REGS;
20051 enum insn_code icode;
20052 bool default_p = false;
20053 bool done_p = false;
20055 /* Allow subreg of memory before/during reload. */
20056 bool memory_p = (MEM_P (x)
20057 || (!reload_completed && GET_CODE (x) == SUBREG
20058 && MEM_P (SUBREG_REG (x))));
20060 sri->icode = CODE_FOR_nothing;
20061 sri->t_icode = CODE_FOR_nothing;
20062 sri->extra_cost = 0;
20064 ? reg_addr[mode].reload_load
20065 : reg_addr[mode].reload_store);
20067 if (REG_P (x) || register_operand (x, mode))
20069 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
20070 bool altivec_p = (rclass == ALTIVEC_REGS);
20071 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
20074 std::swap (to_type, from_type);
20076 /* Can we do a direct move of some sort? */
20077 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
20080 icode = (enum insn_code)sri->icode;
20087 /* Make sure 0.0 is not reloaded or forced into memory. */
20088 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
20095 /* If this is a scalar floating point value and we want to load it into the
20096 traditional Altivec registers, do it via a move via a traditional floating
20097 point register, unless we have D-form addressing. Also make sure that
20098 non-zero constants use a FPR. */
20099 if (!done_p && reg_addr[mode].scalar_in_vmx_p
20100 && !mode_supports_vmx_dform (mode)
20101 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
20102 && (memory_p || (GET_CODE (x) == CONST_DOUBLE)))
20109 /* Handle reload of load/stores if we have reload helper functions. */
20110 if (!done_p && icode != CODE_FOR_nothing && memory_p)
20112 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
20115 if (extra_cost >= 0)
20119 if (extra_cost > 0)
20121 sri->extra_cost = extra_cost;
20122 sri->icode = icode;
20127 /* Handle unaligned loads and stores of integer registers. */
20128 if (!done_p && TARGET_POWERPC64
20129 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
20131 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
20133 rtx addr = XEXP (x, 0);
20134 rtx off = address_offset (addr);
20136 if (off != NULL_RTX)
20138 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
20139 unsigned HOST_WIDE_INT offset = INTVAL (off);
20141 /* We need a secondary reload when our legitimate_address_p
20142 says the address is good (as otherwise the entire address
20143 will be reloaded), and the offset is not a multiple of
20144 four or we have an address wrap. Address wrap will only
20145 occur for LO_SUMs since legitimate_offset_address_p
20146 rejects addresses for 16-byte mems that will wrap. */
20147 if (GET_CODE (addr) == LO_SUM
20148 ? (1 /* legitimate_address_p allows any offset for lo_sum */
20149 && ((offset & 3) != 0
20150 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
20151 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
20152 && (offset & 3) != 0))
20154 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
20156 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
20157 : CODE_FOR_reload_di_load);
20159 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
20160 : CODE_FOR_reload_di_store);
20161 sri->extra_cost = 2;
20172 if (!done_p && !TARGET_POWERPC64
20173 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
20175 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
20177 rtx addr = XEXP (x, 0);
20178 rtx off = address_offset (addr);
20180 if (off != NULL_RTX)
20182 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
20183 unsigned HOST_WIDE_INT offset = INTVAL (off);
20185 /* We need a secondary reload when our legitimate_address_p
20186 says the address is good (as otherwise the entire address
20187 will be reloaded), and we have a wrap.
20189 legitimate_lo_sum_address_p allows LO_SUM addresses to
20190 have any offset so test for wrap in the low 16 bits.
20192 legitimate_offset_address_p checks for the range
20193 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
20194 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
20195 [0x7ff4,0x7fff] respectively, so test for the
20196 intersection of these ranges, [0x7ffc,0x7fff] and
20197 [0x7ff4,0x7ff7] respectively.
20199 Note that the address we see here may have been
20200 manipulated by legitimize_reload_address. */
20201 if (GET_CODE (addr) == LO_SUM
20202 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
20203 : offset - (0x8000 - extra) < UNITS_PER_WORD)
20206 sri->icode = CODE_FOR_reload_si_load;
20208 sri->icode = CODE_FOR_reload_si_store;
20209 sri->extra_cost = 2;
20224 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
20226 gcc_assert (ret != ALL_REGS);
20228 if (TARGET_DEBUG_ADDR)
20231 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
20233 reg_class_names[ret],
20234 in_p ? "true" : "false",
20235 reg_class_names[rclass],
20236 GET_MODE_NAME (mode));
20238 if (reload_completed)
20239 fputs (", after reload", stderr);
20242 fputs (", done_p not set", stderr);
20245 fputs (", default secondary reload", stderr);
20247 if (sri->icode != CODE_FOR_nothing)
20248 fprintf (stderr, ", reload func = %s, extra cost = %d",
20249 insn_data[sri->icode].name, sri->extra_cost);
20251 else if (sri->extra_cost > 0)
20252 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
20254 fputs ("\n", stderr);
20261 /* Better tracing for rs6000_secondary_reload_inner. */
20264 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
20269 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
20271 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
20272 store_p ? "store" : "load");
20275 set = gen_rtx_SET (mem, reg);
20277 set = gen_rtx_SET (reg, mem);
20279 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
20280 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
20283 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
20284 ATTRIBUTE_NORETURN;
20287 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
20290 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
20291 gcc_unreachable ();
20294 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
20295 reload helper functions. These were identified in
20296 rs6000_secondary_reload_memory, and if reload decided to use the secondary
20297 reload, it calls the insns:
20298 reload_<RELOAD:mode>_<P:mptrsize>_store
20299 reload_<RELOAD:mode>_<P:mptrsize>_load
20301 which in turn calls this function, to do whatever is necessary to create
20302 valid addresses. */
20305 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
20307 int regno = true_regnum (reg);
20308 machine_mode mode = GET_MODE (reg);
20309 addr_mask_type addr_mask;
20312 rtx op_reg, op0, op1;
20317 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER || !MEM_P (mem)
20318 || !base_reg_operand (scratch, GET_MODE (scratch)))
20319 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20321 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
20322 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
20324 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
20325 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
20327 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
20328 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
20331 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20333 /* Make sure the mode is valid in this register class. */
20334 if ((addr_mask & RELOAD_REG_VALID) == 0)
20335 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20337 if (TARGET_DEBUG_ADDR)
20338 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
20340 new_addr = addr = XEXP (mem, 0);
20341 switch (GET_CODE (addr))
20343 /* Does the register class support auto update forms for this mode? If
20344 not, do the update now. We don't need a scratch register, since the
20345 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
20348 op_reg = XEXP (addr, 0);
20349 if (!base_reg_operand (op_reg, Pmode))
20350 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20352 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
20354 emit_insn (gen_add2_insn (op_reg, GEN_INT (GET_MODE_SIZE (mode))));
20360 op0 = XEXP (addr, 0);
20361 op1 = XEXP (addr, 1);
20362 if (!base_reg_operand (op0, Pmode)
20363 || GET_CODE (op1) != PLUS
20364 || !rtx_equal_p (op0, XEXP (op1, 0)))
20365 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20367 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
20369 emit_insn (gen_rtx_SET (op0, op1));
20374 /* Do we need to simulate AND -16 to clear the bottom address bits used
20375 in VMX load/stores? */
20377 op0 = XEXP (addr, 0);
20378 op1 = XEXP (addr, 1);
20379 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
20381 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
20384 else if (GET_CODE (op1) == PLUS)
20386 emit_insn (gen_rtx_SET (scratch, op1));
20391 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20393 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
20394 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
20395 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
20396 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
20397 new_addr = scratch;
20401 /* If this is an indirect address, make sure it is a base register. */
20404 if (!base_reg_operand (addr, GET_MODE (addr)))
20406 emit_insn (gen_rtx_SET (scratch, addr));
20407 new_addr = scratch;
20411 /* If this is an indexed address, make sure the register class can handle
20412 indexed addresses for this mode. */
20414 op0 = XEXP (addr, 0);
20415 op1 = XEXP (addr, 1);
20416 if (!base_reg_operand (op0, Pmode))
20417 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20419 else if (int_reg_operand (op1, Pmode))
20421 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
20423 emit_insn (gen_rtx_SET (scratch, addr));
20424 new_addr = scratch;
20428 else if (mode_supports_vsx_dform_quad (mode) && CONST_INT_P (op1))
20430 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
20431 || !quad_address_p (addr, mode, false))
20433 emit_insn (gen_rtx_SET (scratch, addr));
20434 new_addr = scratch;
20438 /* Make sure the register class can handle offset addresses. */
20439 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
20441 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
20443 emit_insn (gen_rtx_SET (scratch, addr));
20444 new_addr = scratch;
20449 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20454 op0 = XEXP (addr, 0);
20455 op1 = XEXP (addr, 1);
20456 if (!base_reg_operand (op0, Pmode))
20457 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20459 else if (int_reg_operand (op1, Pmode))
20461 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
20463 emit_insn (gen_rtx_SET (scratch, addr));
20464 new_addr = scratch;
20468 /* Quad offsets are restricted and can't handle normal addresses. */
20469 else if (mode_supports_vsx_dform_quad (mode))
20471 emit_insn (gen_rtx_SET (scratch, addr));
20472 new_addr = scratch;
20475 /* Make sure the register class can handle offset addresses. */
20476 else if (legitimate_lo_sum_address_p (mode, addr, false))
20478 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
20480 emit_insn (gen_rtx_SET (scratch, addr));
20481 new_addr = scratch;
20486 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20493 rs6000_emit_move (scratch, addr, Pmode);
20494 new_addr = scratch;
20498 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
20501 /* Adjust the address if it changed. */
20502 if (addr != new_addr)
20504 mem = replace_equiv_address_nv (mem, new_addr);
20505 if (TARGET_DEBUG_ADDR)
20506 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
20509 /* Now create the move. */
20511 emit_insn (gen_rtx_SET (mem, reg));
20513 emit_insn (gen_rtx_SET (reg, mem));
20518 /* Convert reloads involving 64-bit gprs and misaligned offset
20519 addressing, or multiple 32-bit gprs and offsets that are too large,
20520 to use indirect addressing. */
20523 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
20525 int regno = true_regnum (reg);
20526 enum reg_class rclass;
20528 rtx scratch_or_premodify = scratch;
20530 if (TARGET_DEBUG_ADDR)
20532 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
20533 store_p ? "store" : "load");
20534 fprintf (stderr, "reg:\n");
20536 fprintf (stderr, "mem:\n");
20538 fprintf (stderr, "scratch:\n");
20539 debug_rtx (scratch);
20542 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
20543 gcc_assert (GET_CODE (mem) == MEM);
20544 rclass = REGNO_REG_CLASS (regno);
20545 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
20546 addr = XEXP (mem, 0);
20548 if (GET_CODE (addr) == PRE_MODIFY)
20550 gcc_assert (REG_P (XEXP (addr, 0))
20551 && GET_CODE (XEXP (addr, 1)) == PLUS
20552 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
20553 scratch_or_premodify = XEXP (addr, 0);
20554 if (!HARD_REGISTER_P (scratch_or_premodify))
20555 /* If we have a pseudo here then reload will have arranged
20556 to have it replaced, but only in the original insn.
20557 Use the replacement here too. */
20558 scratch_or_premodify = find_replacement (&XEXP (addr, 0));
20560 /* RTL emitted by rs6000_secondary_reload_gpr uses RTL
20561 expressions from the original insn, without unsharing them.
20562 Any RTL that points into the original insn will of course
20563 have register replacements applied. That is why we don't
20564 need to look for replacements under the PLUS. */
20565 addr = XEXP (addr, 1);
20567 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
20569 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
20571 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
20573 /* Now create the move. */
20575 emit_insn (gen_rtx_SET (mem, reg));
20577 emit_insn (gen_rtx_SET (reg, mem));
20582 /* Given an rtx X being reloaded into a reg required to be
20583 in class CLASS, return the class of reg to actually use.
20584 In general this is just CLASS; but on some machines
20585 in some cases it is preferable to use a more restrictive class.
20587 On the RS/6000, we have to return NO_REGS when we want to reload a
20588 floating-point CONST_DOUBLE to force it to be copied to memory.
20590 We also don't want to reload integer values into floating-point
20591 registers if we can at all help it. In fact, this can
20592 cause reload to die, if it tries to generate a reload of CTR
20593 into a FP register and discovers it doesn't have the memory location
20596 ??? Would it be a good idea to have reload do the converse, that is
20597 try to reload floating modes into FP registers if possible?
20600 static enum reg_class
20601 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
20603 machine_mode mode = GET_MODE (x);
20604 bool is_constant = CONSTANT_P (x);
20606 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
20607 reload class for it. */
20608 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
20609 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
20612 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
20613 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
20616 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
20617 the reloading of address expressions using PLUS into floating point
20619 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
20623 /* Zero is always allowed in all VSX registers. */
20624 if (x == CONST0_RTX (mode))
20627 /* If this is a vector constant that can be formed with a few Altivec
20628 instructions, we want altivec registers. */
20629 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
20630 return ALTIVEC_REGS;
20632 /* If this is an integer constant that can easily be loaded into
20633 vector registers, allow it. */
20634 if (CONST_INT_P (x))
20636 HOST_WIDE_INT value = INTVAL (x);
20638 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
20639 2.06 can generate it in the Altivec registers with
20643 if (TARGET_P8_VECTOR)
20645 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
20646 return ALTIVEC_REGS;
20651 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
20652 a sign extend in the Altivec registers. */
20653 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
20654 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
20655 return ALTIVEC_REGS;
20658 /* Force constant to memory. */
20662 /* D-form addressing can easily reload the value. */
20663 if (mode_supports_vmx_dform (mode)
20664 || mode_supports_vsx_dform_quad (mode))
20667 /* If this is a scalar floating point value and we don't have D-form
20668 addressing, prefer the traditional floating point registers so that we
20669 can use D-form (register+offset) addressing. */
20670 if (rclass == VSX_REGS
20671 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
20674 /* Prefer the Altivec registers if Altivec is handling the vector
20675 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
20677 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
20678 || mode == V1TImode)
20679 return ALTIVEC_REGS;
20684 if (is_constant || GET_CODE (x) == PLUS)
20686 if (reg_class_subset_p (GENERAL_REGS, rclass))
20687 return GENERAL_REGS;
20688 if (reg_class_subset_p (BASE_REGS, rclass))
20693 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
20694 return GENERAL_REGS;
20699 /* Debug version of rs6000_preferred_reload_class. */
20700 static enum reg_class
20701 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
20703 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
20706 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
20708 reg_class_names[ret], reg_class_names[rclass],
20709 GET_MODE_NAME (GET_MODE (x)));
20715 /* If we are copying between FP or AltiVec registers and anything else, we need
20716 a memory location. The exception is when we are targeting ppc64 and the
20717 move to/from fpr to gpr instructions are available. Also, under VSX, you
20718 can copy vector registers from the FP register set to the Altivec register
20719 set and vice versa. */
20722 rs6000_secondary_memory_needed (machine_mode mode,
20723 reg_class_t from_class,
20724 reg_class_t to_class)
20726 enum rs6000_reg_type from_type, to_type;
20727 bool altivec_p = ((from_class == ALTIVEC_REGS)
20728 || (to_class == ALTIVEC_REGS));
20730 /* If a simple/direct move is available, we don't need secondary memory */
20731 from_type = reg_class_to_reg_type[(int)from_class];
20732 to_type = reg_class_to_reg_type[(int)to_class];
20734 if (rs6000_secondary_reload_move (to_type, from_type, mode,
20735 (secondary_reload_info *)0, altivec_p))
20738 /* If we have a floating point or vector register class, we need to use
20739 memory to transfer the data. */
20740 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
20746 /* Debug version of rs6000_secondary_memory_needed. */
20748 rs6000_debug_secondary_memory_needed (machine_mode mode,
20749 reg_class_t from_class,
20750 reg_class_t to_class)
20752 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
20755 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
20756 "to_class = %s, mode = %s\n",
20757 ret ? "true" : "false",
20758 reg_class_names[from_class],
20759 reg_class_names[to_class],
20760 GET_MODE_NAME (mode));
20765 /* Return the register class of a scratch register needed to copy IN into
20766 or out of a register in RCLASS in MODE. If it can be done directly,
20767 NO_REGS is returned. */
20769 static enum reg_class
20770 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
20775 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
20777 && MACHOPIC_INDIRECT
20781 /* We cannot copy a symbolic operand directly into anything
20782 other than BASE_REGS for TARGET_ELF. So indicate that a
20783 register from BASE_REGS is needed as an intermediate
20786 On Darwin, pic addresses require a load from memory, which
20787 needs a base register. */
20788 if (rclass != BASE_REGS
20789 && (GET_CODE (in) == SYMBOL_REF
20790 || GET_CODE (in) == HIGH
20791 || GET_CODE (in) == LABEL_REF
20792 || GET_CODE (in) == CONST))
20796 if (GET_CODE (in) == REG)
20798 regno = REGNO (in);
20799 if (regno >= FIRST_PSEUDO_REGISTER)
20801 regno = true_regnum (in);
20802 if (regno >= FIRST_PSEUDO_REGISTER)
20806 else if (GET_CODE (in) == SUBREG)
20808 regno = true_regnum (in);
20809 if (regno >= FIRST_PSEUDO_REGISTER)
20815 /* If we have VSX register moves, prefer moving scalar values between
20816 Altivec registers and GPR by going via an FPR (and then via memory)
20817 instead of reloading the secondary memory address for Altivec moves. */
20819 && GET_MODE_SIZE (mode) < 16
20820 && !mode_supports_vmx_dform (mode)
20821 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
20822 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
20823 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
20824 && (regno >= 0 && INT_REGNO_P (regno)))))
20827 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20829 if (rclass == GENERAL_REGS || rclass == BASE_REGS
20830 || (regno >= 0 && INT_REGNO_P (regno)))
20833 /* Constants, memory, and VSX registers can go into VSX registers (both the
20834 traditional floating point and the altivec registers). */
20835 if (rclass == VSX_REGS
20836 && (regno == -1 || VSX_REGNO_P (regno)))
20839 /* Constants, memory, and FP registers can go into FP registers. */
20840 if ((regno == -1 || FP_REGNO_P (regno))
20841 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
20842 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
20844 /* Memory, and AltiVec registers can go into AltiVec registers. */
20845 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
20846 && rclass == ALTIVEC_REGS)
20849 /* We can copy among the CR registers. */
20850 if ((rclass == CR_REGS || rclass == CR0_REGS)
20851 && regno >= 0 && CR_REGNO_P (regno))
20854 /* Otherwise, we need GENERAL_REGS. */
20855 return GENERAL_REGS;
20858 /* Debug version of rs6000_secondary_reload_class. */
20859 static enum reg_class
20860 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20861 machine_mode mode, rtx in)
20863 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20865 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20866 "mode = %s, input rtx:\n",
20867 reg_class_names[ret], reg_class_names[rclass],
20868 GET_MODE_NAME (mode));
20874 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20877 rs6000_can_change_mode_class (machine_mode from,
20879 reg_class_t rclass)
20881 unsigned from_size = GET_MODE_SIZE (from);
20882 unsigned to_size = GET_MODE_SIZE (to);
20884 if (from_size != to_size)
20886 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20888 if (reg_classes_intersect_p (xclass, rclass))
20890 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20891 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20892 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20893 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20895 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20896 single register under VSX because the scalar part of the register
20897 is in the upper 64-bits, and not the lower 64-bits. Types like
20898 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20899 IEEE floating point can't overlap, and neither can small
20902 if (to_float128_vector_p && from_float128_vector_p)
20905 else if (to_float128_vector_p || from_float128_vector_p)
20908 /* TDmode in floating-mode registers must always go into a register
20909 pair with the most significant word in the even-numbered register
20910 to match ISA requirements. In little-endian mode, this does not
20911 match subreg numbering, so we cannot allow subregs. */
20912 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20915 if (from_size < 8 || to_size < 8)
20918 if (from_size == 8 && (8 * to_nregs) != to_size)
20921 if (to_size == 8 && (8 * from_nregs) != from_size)
20930 /* Since the VSX register set includes traditional floating point registers
20931 and altivec registers, just check for the size being different instead of
20932 trying to check whether the modes are vector modes. Otherwise it won't
20933 allow say DF and DI to change classes. For types like TFmode and TDmode
20934 that take 2 64-bit registers, rather than a single 128-bit register, don't
20935 allow subregs of those types to other 128 bit types. */
20936 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20938 unsigned num_regs = (from_size + 15) / 16;
20939 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20940 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20943 return (from_size == 8 || from_size == 16);
20946 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20947 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20953 /* Debug version of rs6000_can_change_mode_class. */
20955 rs6000_debug_can_change_mode_class (machine_mode from,
20957 reg_class_t rclass)
20959 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20962 "rs6000_can_change_mode_class, return %s, from = %s, "
20963 "to = %s, rclass = %s\n",
20964 ret ? "true" : "false",
20965 GET_MODE_NAME (from), GET_MODE_NAME (to),
20966 reg_class_names[rclass]);
20971 /* Return a string to do a move operation of 128 bits of data. */
20974 rs6000_output_move_128bit (rtx operands[])
20976 rtx dest = operands[0];
20977 rtx src = operands[1];
20978 machine_mode mode = GET_MODE (dest);
20981 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20982 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20986 dest_regno = REGNO (dest);
20987 dest_gpr_p = INT_REGNO_P (dest_regno);
20988 dest_fp_p = FP_REGNO_P (dest_regno);
20989 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20990 dest_vsx_p = dest_fp_p | dest_vmx_p;
20995 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
21000 src_regno = REGNO (src);
21001 src_gpr_p = INT_REGNO_P (src_regno);
21002 src_fp_p = FP_REGNO_P (src_regno);
21003 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
21004 src_vsx_p = src_fp_p | src_vmx_p;
21009 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
21012 /* Register moves. */
21013 if (dest_regno >= 0 && src_regno >= 0)
21020 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
21021 return (WORDS_BIG_ENDIAN
21022 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
21023 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
21025 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
21029 else if (TARGET_VSX && dest_vsx_p)
21032 return "xxlor %x0,%x1,%x1";
21034 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
21035 return (WORDS_BIG_ENDIAN
21036 ? "mtvsrdd %x0,%1,%L1"
21037 : "mtvsrdd %x0,%L1,%1");
21039 else if (TARGET_DIRECT_MOVE && src_gpr_p)
21043 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
21044 return "vor %0,%1,%1";
21046 else if (dest_fp_p && src_fp_p)
21051 else if (dest_regno >= 0 && MEM_P (src))
21055 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
21061 else if (TARGET_ALTIVEC && dest_vmx_p
21062 && altivec_indexed_or_indirect_operand (src, mode))
21063 return "lvx %0,%y1";
21065 else if (TARGET_VSX && dest_vsx_p)
21067 if (mode_supports_vsx_dform_quad (mode)
21068 && quad_address_p (XEXP (src, 0), mode, true))
21069 return "lxv %x0,%1";
21071 else if (TARGET_P9_VECTOR)
21072 return "lxvx %x0,%y1";
21074 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
21075 return "lxvw4x %x0,%y1";
21078 return "lxvd2x %x0,%y1";
21081 else if (TARGET_ALTIVEC && dest_vmx_p)
21082 return "lvx %0,%y1";
21084 else if (dest_fp_p)
21089 else if (src_regno >= 0 && MEM_P (dest))
21093 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
21094 return "stq %1,%0";
21099 else if (TARGET_ALTIVEC && src_vmx_p
21100 && altivec_indexed_or_indirect_operand (src, mode))
21101 return "stvx %1,%y0";
21103 else if (TARGET_VSX && src_vsx_p)
21105 if (mode_supports_vsx_dform_quad (mode)
21106 && quad_address_p (XEXP (dest, 0), mode, true))
21107 return "stxv %x1,%0";
21109 else if (TARGET_P9_VECTOR)
21110 return "stxvx %x1,%y0";
21112 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
21113 return "stxvw4x %x1,%y0";
21116 return "stxvd2x %x1,%y0";
21119 else if (TARGET_ALTIVEC && src_vmx_p)
21120 return "stvx %1,%y0";
21127 else if (dest_regno >= 0
21128 && (GET_CODE (src) == CONST_INT
21129 || GET_CODE (src) == CONST_WIDE_INT
21130 || GET_CODE (src) == CONST_DOUBLE
21131 || GET_CODE (src) == CONST_VECTOR))
21136 else if ((dest_vmx_p && TARGET_ALTIVEC)
21137 || (dest_vsx_p && TARGET_VSX))
21138 return output_vec_const_move (operands);
21141 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
21144 /* Validate a 128-bit move. */
21146 rs6000_move_128bit_ok_p (rtx operands[])
21148 machine_mode mode = GET_MODE (operands[0]);
21149 return (gpc_reg_operand (operands[0], mode)
21150 || gpc_reg_operand (operands[1], mode));
21153 /* Return true if a 128-bit move needs to be split. */
21155 rs6000_split_128bit_ok_p (rtx operands[])
21157 if (!reload_completed)
21160 if (!gpr_or_gpr_p (operands[0], operands[1]))
21163 if (quad_load_store_p (operands[0], operands[1]))
21170 /* Given a comparison operation, return the bit number in CCR to test. We
21171 know this is a valid comparison.
21173 SCC_P is 1 if this is for an scc. That means that %D will have been
21174 used instead of %C, so the bits will be in different places.
21176 Return -1 if OP isn't a valid comparison for some reason. */
21179 ccr_bit (rtx op, int scc_p)
21181 enum rtx_code code = GET_CODE (op);
21182 machine_mode cc_mode;
21187 if (!COMPARISON_P (op))
21190 reg = XEXP (op, 0);
21192 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
21194 cc_mode = GET_MODE (reg);
21195 cc_regnum = REGNO (reg);
21196 base_bit = 4 * (cc_regnum - CR0_REGNO);
21198 validate_condition_mode (code, cc_mode);
21200 /* When generating a sCOND operation, only positive conditions are
21203 || code == EQ || code == GT || code == LT || code == UNORDERED
21204 || code == GTU || code == LTU);
21209 return scc_p ? base_bit + 3 : base_bit + 2;
21211 return base_bit + 2;
21212 case GT: case GTU: case UNLE:
21213 return base_bit + 1;
21214 case LT: case LTU: case UNGE:
21216 case ORDERED: case UNORDERED:
21217 return base_bit + 3;
21220 /* If scc, we will have done a cror to put the bit in the
21221 unordered position. So test that bit. For integer, this is ! LT
21222 unless this is an scc insn. */
21223 return scc_p ? base_bit + 3 : base_bit;
21226 return scc_p ? base_bit + 3 : base_bit + 1;
21229 gcc_unreachable ();
21233 /* Return the GOT register. */
21236 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
21238 /* The second flow pass currently (June 1999) can't update
21239 regs_ever_live without disturbing other parts of the compiler, so
21240 update it here to make the prolog/epilogue code happy. */
21241 if (!can_create_pseudo_p ()
21242 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
21243 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
21245 crtl->uses_pic_offset_table = 1;
21247 return pic_offset_table_rtx;
21250 static rs6000_stack_t stack_info;
21252 /* Function to init struct machine_function.
21253 This will be called, via a pointer variable,
21254 from push_function_context. */
21256 static struct machine_function *
21257 rs6000_init_machine_status (void)
21259 stack_info.reload_completed = 0;
21260 return ggc_cleared_alloc<machine_function> ();
21263 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
21265 /* Write out a function code label. */
21268 rs6000_output_function_entry (FILE *file, const char *fname)
21270 if (fname[0] != '.')
21272 switch (DEFAULT_ABI)
21275 gcc_unreachable ();
21281 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
21291 RS6000_OUTPUT_BASENAME (file, fname);
21294 /* Print an operand. Recognize special options, documented below. */
21297 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
21298 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
21300 #define SMALL_DATA_RELOC "sda21"
21301 #define SMALL_DATA_REG 0
21305 print_operand (FILE *file, rtx x, int code)
21308 unsigned HOST_WIDE_INT uval;
21312 /* %a is output_address. */
21314 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
21318 /* Like 'J' but get to the GT bit only. */
21319 gcc_assert (REG_P (x));
21321 /* Bit 1 is GT bit. */
21322 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
21324 /* Add one for shift count in rlinm for scc. */
21325 fprintf (file, "%d", i + 1);
21329 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
21332 output_operand_lossage ("invalid %%e value");
21337 if ((uval & 0xffff) == 0 && uval != 0)
21342 /* X is a CR register. Print the number of the EQ bit of the CR */
21343 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21344 output_operand_lossage ("invalid %%E value");
21346 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
21350 /* X is a CR register. Print the shift count needed to move it
21351 to the high-order four bits. */
21352 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21353 output_operand_lossage ("invalid %%f value");
21355 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
21359 /* Similar, but print the count for the rotate in the opposite
21361 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21362 output_operand_lossage ("invalid %%F value");
21364 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
21368 /* X is a constant integer. If it is negative, print "m",
21369 otherwise print "z". This is to make an aze or ame insn. */
21370 if (GET_CODE (x) != CONST_INT)
21371 output_operand_lossage ("invalid %%G value");
21372 else if (INTVAL (x) >= 0)
21379 /* If constant, output low-order five bits. Otherwise, write
21382 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
21384 print_operand (file, x, 0);
21388 /* If constant, output low-order six bits. Otherwise, write
21391 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
21393 print_operand (file, x, 0);
21397 /* Print `i' if this is a constant, else nothing. */
21403 /* Write the bit number in CCR for jump. */
21404 i = ccr_bit (x, 0);
21406 output_operand_lossage ("invalid %%j code");
21408 fprintf (file, "%d", i);
21412 /* Similar, but add one for shift count in rlinm for scc and pass
21413 scc flag to `ccr_bit'. */
21414 i = ccr_bit (x, 1);
21416 output_operand_lossage ("invalid %%J code");
21418 /* If we want bit 31, write a shift count of zero, not 32. */
21419 fprintf (file, "%d", i == 31 ? 0 : i + 1);
21423 /* X must be a constant. Write the 1's complement of the
21426 output_operand_lossage ("invalid %%k value");
21428 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
21432 /* X must be a symbolic constant on ELF. Write an
21433 expression suitable for an 'addi' that adds in the low 16
21434 bits of the MEM. */
21435 if (GET_CODE (x) == CONST)
21437 if (GET_CODE (XEXP (x, 0)) != PLUS
21438 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
21439 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
21440 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
21441 output_operand_lossage ("invalid %%K value");
21443 print_operand_address (file, x);
21444 fputs ("@l", file);
21447 /* %l is output_asm_label. */
21450 /* Write second word of DImode or DFmode reference. Works on register
21451 or non-indexed memory only. */
21453 fputs (reg_names[REGNO (x) + 1], file);
21454 else if (MEM_P (x))
21456 machine_mode mode = GET_MODE (x);
21457 /* Handle possible auto-increment. Since it is pre-increment and
21458 we have already done it, we can just use an offset of word. */
21459 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21460 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21461 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
21463 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21464 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
21467 output_address (mode, XEXP (adjust_address_nv (x, SImode,
21471 if (small_data_operand (x, GET_MODE (x)))
21472 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21473 reg_names[SMALL_DATA_REG]);
21477 case 'N': /* Unused */
21478 /* Write the number of elements in the vector times 4. */
21479 if (GET_CODE (x) != PARALLEL)
21480 output_operand_lossage ("invalid %%N value");
21482 fprintf (file, "%d", XVECLEN (x, 0) * 4);
21485 case 'O': /* Unused */
21486 /* Similar, but subtract 1 first. */
21487 if (GET_CODE (x) != PARALLEL)
21488 output_operand_lossage ("invalid %%O value");
21490 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
21494 /* X is a CONST_INT that is a power of two. Output the logarithm. */
21497 || (i = exact_log2 (INTVAL (x))) < 0)
21498 output_operand_lossage ("invalid %%p value");
21500 fprintf (file, "%d", i);
21504 /* The operand must be an indirect memory reference. The result
21505 is the register name. */
21506 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
21507 || REGNO (XEXP (x, 0)) >= 32)
21508 output_operand_lossage ("invalid %%P value");
21510 fputs (reg_names[REGNO (XEXP (x, 0))], file);
21514 /* This outputs the logical code corresponding to a boolean
21515 expression. The expression may have one or both operands
21516 negated (if one, only the first one). For condition register
21517 logical operations, it will also treat the negated
21518 CR codes as NOTs, but not handle NOTs of them. */
21520 const char *const *t = 0;
21522 enum rtx_code code = GET_CODE (x);
21523 static const char * const tbl[3][3] = {
21524 { "and", "andc", "nor" },
21525 { "or", "orc", "nand" },
21526 { "xor", "eqv", "xor" } };
21530 else if (code == IOR)
21532 else if (code == XOR)
21535 output_operand_lossage ("invalid %%q value");
21537 if (GET_CODE (XEXP (x, 0)) != NOT)
21541 if (GET_CODE (XEXP (x, 1)) == NOT)
21552 if (! TARGET_MFCRF)
21558 /* X is a CR register. Print the mask for `mtcrf'. */
21559 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
21560 output_operand_lossage ("invalid %%R value");
21562 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
21566 /* Low 5 bits of 32 - value */
21568 output_operand_lossage ("invalid %%s value");
21570 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
21574 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
21575 gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
21577 /* Bit 3 is OV bit. */
21578 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
21580 /* If we want bit 31, write a shift count of zero, not 32. */
21581 fprintf (file, "%d", i == 31 ? 0 : i + 1);
21585 /* Print the symbolic name of a branch target register. */
21586 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
21587 && REGNO (x) != CTR_REGNO))
21588 output_operand_lossage ("invalid %%T value");
21589 else if (REGNO (x) == LR_REGNO)
21590 fputs ("lr", file);
21592 fputs ("ctr", file);
21596 /* High-order or low-order 16 bits of constant, whichever is non-zero,
21597 for use in unsigned operand. */
21600 output_operand_lossage ("invalid %%u value");
21605 if ((uval & 0xffff) == 0)
21608 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
21612 /* High-order 16 bits of constant for use in signed operand. */
21614 output_operand_lossage ("invalid %%v value");
21616 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
21617 (INTVAL (x) >> 16) & 0xffff);
21621 /* Print `u' if this has an auto-increment or auto-decrement. */
21623 && (GET_CODE (XEXP (x, 0)) == PRE_INC
21624 || GET_CODE (XEXP (x, 0)) == PRE_DEC
21625 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
21630 /* Print the trap code for this operand. */
21631 switch (GET_CODE (x))
21634 fputs ("eq", file); /* 4 */
21637 fputs ("ne", file); /* 24 */
21640 fputs ("lt", file); /* 16 */
21643 fputs ("le", file); /* 20 */
21646 fputs ("gt", file); /* 8 */
21649 fputs ("ge", file); /* 12 */
21652 fputs ("llt", file); /* 2 */
21655 fputs ("lle", file); /* 6 */
21658 fputs ("lgt", file); /* 1 */
21661 fputs ("lge", file); /* 5 */
21664 gcc_unreachable ();
21669 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
21672 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
21673 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
21675 print_operand (file, x, 0);
21679 /* X is a FPR or Altivec register used in a VSX context. */
21680 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
21681 output_operand_lossage ("invalid %%x value");
21684 int reg = REGNO (x);
21685 int vsx_reg = (FP_REGNO_P (reg)
21687 : reg - FIRST_ALTIVEC_REGNO + 32);
21689 #ifdef TARGET_REGNAMES
21690 if (TARGET_REGNAMES)
21691 fprintf (file, "%%vs%d", vsx_reg);
21694 fprintf (file, "%d", vsx_reg);
21700 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
21701 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
21702 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
21707 /* Like 'L', for third word of TImode/PTImode */
21709 fputs (reg_names[REGNO (x) + 2], file);
21710 else if (MEM_P (x))
21712 machine_mode mode = GET_MODE (x);
21713 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21714 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21715 output_address (mode, plus_constant (Pmode,
21716 XEXP (XEXP (x, 0), 0), 8));
21717 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21718 output_address (mode, plus_constant (Pmode,
21719 XEXP (XEXP (x, 0), 0), 8));
21721 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
21722 if (small_data_operand (x, GET_MODE (x)))
21723 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21724 reg_names[SMALL_DATA_REG]);
21729 /* X is a SYMBOL_REF. Write out the name preceded by a
21730 period and without any trailing data in brackets. Used for function
21731 names. If we are configured for System V (or the embedded ABI) on
21732 the PowerPC, do not emit the period, since those systems do not use
21733 TOCs and the like. */
21734 gcc_assert (GET_CODE (x) == SYMBOL_REF);
21736 /* For macho, check to see if we need a stub. */
21739 const char *name = XSTR (x, 0);
21741 if (darwin_emit_branch_islands
21742 && MACHOPIC_INDIRECT
21743 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
21744 name = machopic_indirection_name (x, /*stub_p=*/true);
21746 assemble_name (file, name);
21748 else if (!DOT_SYMBOLS)
21749 assemble_name (file, XSTR (x, 0));
21751 rs6000_output_function_entry (file, XSTR (x, 0));
21755 /* Like 'L', for last word of TImode/PTImode. */
21757 fputs (reg_names[REGNO (x) + 3], file);
21758 else if (MEM_P (x))
21760 machine_mode mode = GET_MODE (x);
21761 if (GET_CODE (XEXP (x, 0)) == PRE_INC
21762 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
21763 output_address (mode, plus_constant (Pmode,
21764 XEXP (XEXP (x, 0), 0), 12));
21765 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21766 output_address (mode, plus_constant (Pmode,
21767 XEXP (XEXP (x, 0), 0), 12));
21769 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
21770 if (small_data_operand (x, GET_MODE (x)))
21771 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21772 reg_names[SMALL_DATA_REG]);
21776 /* Print AltiVec memory operand. */
21781 gcc_assert (MEM_P (x));
21785 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
21786 && GET_CODE (tmp) == AND
21787 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
21788 && INTVAL (XEXP (tmp, 1)) == -16)
21789 tmp = XEXP (tmp, 0);
21790 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
21791 && GET_CODE (tmp) == PRE_MODIFY)
21792 tmp = XEXP (tmp, 1);
21794 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
21797 if (GET_CODE (tmp) != PLUS
21798 || !REG_P (XEXP (tmp, 0))
21799 || !REG_P (XEXP (tmp, 1)))
21801 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
21805 if (REGNO (XEXP (tmp, 0)) == 0)
21806 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
21807 reg_names[ REGNO (XEXP (tmp, 0)) ]);
21809 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
21810 reg_names[ REGNO (XEXP (tmp, 1)) ]);
21817 fprintf (file, "%s", reg_names[REGNO (x)]);
21818 else if (MEM_P (x))
21820 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21821 know the width from the mode. */
21822 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21823 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21824 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21825 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21826 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21827 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21828 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21829 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21831 output_address (GET_MODE (x), XEXP (x, 0));
21835 if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21836 /* This hack along with a corresponding hack in
21837 rs6000_output_addr_const_extra arranges to output addends
21838 where the assembler expects to find them. eg.
21839 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21840 without this hack would be output as "x@toc+4". We
21842 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21844 output_addr_const (file, x);
21849 if (const char *name = get_some_local_dynamic_name ())
21850 assemble_name (file, name);
21852 output_operand_lossage ("'%%&' used without any "
21853 "local dynamic TLS references");
21857 output_operand_lossage ("invalid %%xn code");
21861 /* Print the address of an operand. */
21864 print_operand_address (FILE *file, rtx x)
21867 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21868 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
21869 || GET_CODE (x) == LABEL_REF)
21871 output_addr_const (file, x);
21872 if (small_data_operand (x, GET_MODE (x)))
21873 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21874 reg_names[SMALL_DATA_REG]);
21876 gcc_assert (!TARGET_TOC);
21878 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21879 && REG_P (XEXP (x, 1)))
21881 if (REGNO (XEXP (x, 0)) == 0)
21882 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21883 reg_names[ REGNO (XEXP (x, 0)) ]);
21885 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21886 reg_names[ REGNO (XEXP (x, 1)) ]);
21888 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21889 && GET_CODE (XEXP (x, 1)) == CONST_INT)
21890 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21891 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21893 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21894 && CONSTANT_P (XEXP (x, 1)))
21896 fprintf (file, "lo16(");
21897 output_addr_const (file, XEXP (x, 1));
21898 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21902 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21903 && CONSTANT_P (XEXP (x, 1)))
21905 output_addr_const (file, XEXP (x, 1));
21906 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21909 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21911 /* This hack along with a corresponding hack in
21912 rs6000_output_addr_const_extra arranges to output addends
21913 where the assembler expects to find them. eg.
21915 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21916 without this hack would be output as "x@toc+8@l(9)". We
21917 want "x+8@toc@l(9)". */
21918 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21919 if (GET_CODE (x) == LO_SUM)
21920 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21922 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21925 gcc_unreachable ();
21928 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21931 rs6000_output_addr_const_extra (FILE *file, rtx x)
21933 if (GET_CODE (x) == UNSPEC)
21934 switch (XINT (x, 1))
21936 case UNSPEC_TOCREL:
21937 gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
21938 && REG_P (XVECEXP (x, 0, 1))
21939 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21940 output_addr_const (file, XVECEXP (x, 0, 0));
21941 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21943 if (INTVAL (tocrel_offset_oac) >= 0)
21944 fprintf (file, "+");
21945 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21947 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21950 assemble_name (file, toc_label_name);
21953 else if (TARGET_ELF)
21954 fputs ("@toc", file);
21958 case UNSPEC_MACHOPIC_OFFSET:
21959 output_addr_const (file, XVECEXP (x, 0, 0));
21961 machopic_output_function_base_name (file);
21968 /* Target hook for assembling integer objects. The PowerPC version has
21969 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21970 is defined. It also needs to handle DI-mode objects on 64-bit
21974 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21976 #ifdef RELOCATABLE_NEEDS_FIXUP
21977 /* Special handling for SI values. */
21978 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21980 static int recurse = 0;
21982 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21983 the .fixup section. Since the TOC section is already relocated, we
21984 don't need to mark it here. We used to skip the text section, but it
21985 should never be valid for relocated addresses to be placed in the text
21987 if (DEFAULT_ABI == ABI_V4
21988 && (TARGET_RELOCATABLE || flag_pic > 1)
21989 && in_section != toc_section
21991 && !CONST_SCALAR_INT_P (x)
21997 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21999 ASM_OUTPUT_LABEL (asm_out_file, buf);
22000 fprintf (asm_out_file, "\t.long\t(");
22001 output_addr_const (asm_out_file, x);
22002 fprintf (asm_out_file, ")@fixup\n");
22003 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
22004 ASM_OUTPUT_ALIGN (asm_out_file, 2);
22005 fprintf (asm_out_file, "\t.long\t");
22006 assemble_name (asm_out_file, buf);
22007 fprintf (asm_out_file, "\n\t.previous\n");
22011 /* Remove initial .'s to turn a -mcall-aixdesc function
22012 address into the address of the descriptor, not the function
22014 else if (GET_CODE (x) == SYMBOL_REF
22015 && XSTR (x, 0)[0] == '.'
22016 && DEFAULT_ABI == ABI_AIX)
22018 const char *name = XSTR (x, 0);
22019 while (*name == '.')
22022 fprintf (asm_out_file, "\t.long\t%s\n", name);
22026 #endif /* RELOCATABLE_NEEDS_FIXUP */
22027 return default_assemble_integer (x, size, aligned_p);
22030 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
22031 /* Emit an assembler directive to set symbol visibility for DECL to
22032 VISIBILITY_TYPE. */
22035 rs6000_assemble_visibility (tree decl, int vis)
22040 /* Functions need to have their entry point symbol visibility set as
22041 well as their descriptor symbol visibility. */
22042 if (DEFAULT_ABI == ABI_AIX
22044 && TREE_CODE (decl) == FUNCTION_DECL)
22046 static const char * const visibility_types[] = {
22047 NULL, "protected", "hidden", "internal"
22050 const char *name, *type;
22052 name = ((* targetm.strip_name_encoding)
22053 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
22054 type = visibility_types[vis];
22056 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
22057 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
22060 default_assemble_visibility (decl, vis);
22065 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
22067 /* Reversal of FP compares takes care -- an ordered compare
22068 becomes an unordered compare and vice versa. */
22069 if (mode == CCFPmode
22070 && (!flag_finite_math_only
22071 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
22072 || code == UNEQ || code == LTGT))
22073 return reverse_condition_maybe_unordered (code);
22075 return reverse_condition (code);
22078 /* Generate a compare for CODE. Return a brand-new rtx that
22079 represents the result of the compare. */
22082 rs6000_generate_compare (rtx cmp, machine_mode mode)
22084 machine_mode comp_mode;
22085 rtx compare_result;
22086 enum rtx_code code = GET_CODE (cmp);
22087 rtx op0 = XEXP (cmp, 0);
22088 rtx op1 = XEXP (cmp, 1);
22090 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
22091 comp_mode = CCmode;
22092 else if (FLOAT_MODE_P (mode))
22093 comp_mode = CCFPmode;
22094 else if (code == GTU || code == LTU
22095 || code == GEU || code == LEU)
22096 comp_mode = CCUNSmode;
22097 else if ((code == EQ || code == NE)
22098 && unsigned_reg_p (op0)
22099 && (unsigned_reg_p (op1)
22100 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
22101 /* These are unsigned values, perhaps there will be a later
22102 ordering compare that can be shared with this one. */
22103 comp_mode = CCUNSmode;
22105 comp_mode = CCmode;
22107 /* If we have an unsigned compare, make sure we don't have a signed value as
22109 if (comp_mode == CCUNSmode && GET_CODE (op1) == CONST_INT
22110 && INTVAL (op1) < 0)
22112 op0 = copy_rtx_if_shared (op0);
22113 op1 = force_reg (GET_MODE (op0), op1);
22114 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
22117 /* First, the compare. */
22118 compare_result = gen_reg_rtx (comp_mode);
22120 /* IEEE 128-bit support in VSX registers when we do not have hardware
22122 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
22124 rtx libfunc = NULL_RTX;
22125 bool check_nan = false;
22132 libfunc = optab_libfunc (eq_optab, mode);
22137 libfunc = optab_libfunc (ge_optab, mode);
22142 libfunc = optab_libfunc (le_optab, mode);
22147 libfunc = optab_libfunc (unord_optab, mode);
22148 code = (code == UNORDERED) ? NE : EQ;
22154 libfunc = optab_libfunc (ge_optab, mode);
22155 code = (code == UNGE) ? GE : GT;
22161 libfunc = optab_libfunc (le_optab, mode);
22162 code = (code == UNLE) ? LE : LT;
22168 libfunc = optab_libfunc (eq_optab, mode);
22169 code = (code = UNEQ) ? EQ : NE;
22173 gcc_unreachable ();
22176 gcc_assert (libfunc);
22179 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
22180 SImode, op0, mode, op1, mode);
22182 /* The library signals an exception for signalling NaNs, so we need to
22183 handle isgreater, etc. by first checking isordered. */
22186 rtx ne_rtx, normal_dest, unord_dest;
22187 rtx unord_func = optab_libfunc (unord_optab, mode);
22188 rtx join_label = gen_label_rtx ();
22189 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
22190 rtx unord_cmp = gen_reg_rtx (comp_mode);
22193 /* Test for either value being a NaN. */
22194 gcc_assert (unord_func);
22195 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
22196 SImode, op0, mode, op1, mode);
22198 /* Set value (0) if either value is a NaN, and jump to the join
22200 dest = gen_reg_rtx (SImode);
22201 emit_move_insn (dest, const1_rtx);
22202 emit_insn (gen_rtx_SET (unord_cmp,
22203 gen_rtx_COMPARE (comp_mode, unord_dest,
22206 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
22207 emit_jump_insn (gen_rtx_SET (pc_rtx,
22208 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
22212 /* Do the normal comparison, knowing that the values are not
22214 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
22215 SImode, op0, mode, op1, mode);
22217 emit_insn (gen_cstoresi4 (dest,
22218 gen_rtx_fmt_ee (code, SImode, normal_dest,
22220 normal_dest, const0_rtx));
22222 /* Join NaN and non-Nan paths. Compare dest against 0. */
22223 emit_label (join_label);
22227 emit_insn (gen_rtx_SET (compare_result,
22228 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
22233 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
22234 CLOBBERs to match cmptf_internal2 pattern. */
22235 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
22236 && FLOAT128_IBM_P (GET_MODE (op0))
22237 && TARGET_HARD_FLOAT)
22238 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22240 gen_rtx_SET (compare_result,
22241 gen_rtx_COMPARE (comp_mode, op0, op1)),
22242 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22243 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22244 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22245 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22246 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22247 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22248 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22249 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
22250 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
22251 else if (GET_CODE (op1) == UNSPEC
22252 && XINT (op1, 1) == UNSPEC_SP_TEST)
22254 rtx op1b = XVECEXP (op1, 0, 0);
22255 comp_mode = CCEQmode;
22256 compare_result = gen_reg_rtx (CCEQmode);
22258 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
22260 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
22263 emit_insn (gen_rtx_SET (compare_result,
22264 gen_rtx_COMPARE (comp_mode, op0, op1)));
22267 /* Some kinds of FP comparisons need an OR operation;
22268 under flag_finite_math_only we don't bother. */
22269 if (FLOAT_MODE_P (mode)
22270 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
22271 && !flag_finite_math_only
22272 && (code == LE || code == GE
22273 || code == UNEQ || code == LTGT
22274 || code == UNGT || code == UNLT))
22276 enum rtx_code or1, or2;
22277 rtx or1_rtx, or2_rtx, compare2_rtx;
22278 rtx or_result = gen_reg_rtx (CCEQmode);
22282 case LE: or1 = LT; or2 = EQ; break;
22283 case GE: or1 = GT; or2 = EQ; break;
22284 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
22285 case LTGT: or1 = LT; or2 = GT; break;
22286 case UNGT: or1 = UNORDERED; or2 = GT; break;
22287 case UNLT: or1 = UNORDERED; or2 = LT; break;
22288 default: gcc_unreachable ();
22290 validate_condition_mode (or1, comp_mode);
22291 validate_condition_mode (or2, comp_mode);
22292 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
22293 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
22294 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
22295 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
22297 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
22299 compare_result = or_result;
22303 validate_condition_mode (code, GET_MODE (compare_result));
22305 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
22309 /* Return the diagnostic message string if the binary operation OP is
22310 not permitted on TYPE1 and TYPE2, NULL otherwise. */
22313 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
22317 machine_mode mode1 = TYPE_MODE (type1);
22318 machine_mode mode2 = TYPE_MODE (type2);
22320 /* For complex modes, use the inner type. */
22321 if (COMPLEX_MODE_P (mode1))
22322 mode1 = GET_MODE_INNER (mode1);
22324 if (COMPLEX_MODE_P (mode2))
22325 mode2 = GET_MODE_INNER (mode2);
22327 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
22328 double to intermix unless -mfloat128-convert. */
22329 if (mode1 == mode2)
22332 if (!TARGET_FLOAT128_CVT)
22334 if ((mode1 == KFmode && mode2 == IFmode)
22335 || (mode1 == IFmode && mode2 == KFmode))
22336 return N_("__float128 and __ibm128 cannot be used in the same "
22339 if (TARGET_IEEEQUAD
22340 && ((mode1 == IFmode && mode2 == TFmode)
22341 || (mode1 == TFmode && mode2 == IFmode)))
22342 return N_("__ibm128 and long double cannot be used in the same "
22345 if (!TARGET_IEEEQUAD
22346 && ((mode1 == KFmode && mode2 == TFmode)
22347 || (mode1 == TFmode && mode2 == KFmode)))
22348 return N_("__float128 and long double cannot be used in the same "
22356 /* Expand floating point conversion to/from __float128 and __ibm128. */
22359 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
22361 machine_mode dest_mode = GET_MODE (dest);
22362 machine_mode src_mode = GET_MODE (src);
22363 convert_optab cvt = unknown_optab;
22364 bool do_move = false;
22365 rtx libfunc = NULL_RTX;
22367 typedef rtx (*rtx_2func_t) (rtx, rtx);
22368 rtx_2func_t hw_convert = (rtx_2func_t)0;
22372 rtx_2func_t from_df;
22373 rtx_2func_t from_sf;
22374 rtx_2func_t from_si_sign;
22375 rtx_2func_t from_si_uns;
22376 rtx_2func_t from_di_sign;
22377 rtx_2func_t from_di_uns;
22380 rtx_2func_t to_si_sign;
22381 rtx_2func_t to_si_uns;
22382 rtx_2func_t to_di_sign;
22383 rtx_2func_t to_di_uns;
22384 } hw_conversions[2] = {
22385 /* convertions to/from KFmode */
22387 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
22388 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
22389 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
22390 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
22391 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
22392 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
22393 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
22394 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
22395 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
22396 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
22397 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
22398 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
22401 /* convertions to/from TFmode */
22403 gen_extenddftf2_hw, /* TFmode <- DFmode. */
22404 gen_extendsftf2_hw, /* TFmode <- SFmode. */
22405 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
22406 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
22407 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
22408 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
22409 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
22410 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
22411 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
22412 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
22413 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
22414 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
22418 if (dest_mode == src_mode)
22419 gcc_unreachable ();
22421 /* Eliminate memory operations. */
22423 src = force_reg (src_mode, src);
22427 rtx tmp = gen_reg_rtx (dest_mode);
22428 rs6000_expand_float128_convert (tmp, src, unsigned_p);
22429 rs6000_emit_move (dest, tmp, dest_mode);
22433 /* Convert to IEEE 128-bit floating point. */
22434 if (FLOAT128_IEEE_P (dest_mode))
22436 if (dest_mode == KFmode)
22438 else if (dest_mode == TFmode)
22441 gcc_unreachable ();
22447 hw_convert = hw_conversions[kf_or_tf].from_df;
22452 hw_convert = hw_conversions[kf_or_tf].from_sf;
22458 if (FLOAT128_IBM_P (src_mode))
22467 cvt = ufloat_optab;
22468 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
22472 cvt = sfloat_optab;
22473 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
22480 cvt = ufloat_optab;
22481 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
22485 cvt = sfloat_optab;
22486 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
22491 gcc_unreachable ();
22495 /* Convert from IEEE 128-bit floating point. */
22496 else if (FLOAT128_IEEE_P (src_mode))
22498 if (src_mode == KFmode)
22500 else if (src_mode == TFmode)
22503 gcc_unreachable ();
22509 hw_convert = hw_conversions[kf_or_tf].to_df;
22514 hw_convert = hw_conversions[kf_or_tf].to_sf;
22520 if (FLOAT128_IBM_P (dest_mode))
22530 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
22535 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
22543 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
22548 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
22553 gcc_unreachable ();
22557 /* Both IBM format. */
22558 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
22562 gcc_unreachable ();
22564 /* Handle conversion between TFmode/KFmode. */
22566 emit_move_insn (dest, gen_lowpart (dest_mode, src));
22568 /* Handle conversion if we have hardware support. */
22569 else if (TARGET_FLOAT128_HW && hw_convert)
22570 emit_insn ((hw_convert) (dest, src));
22572 /* Call an external function to do the conversion. */
22573 else if (cvt != unknown_optab)
22575 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
22576 gcc_assert (libfunc != NULL_RTX);
22578 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
22581 gcc_assert (dest2 != NULL_RTX);
22582 if (!rtx_equal_p (dest, dest2))
22583 emit_move_insn (dest, dest2);
22587 gcc_unreachable ();
22593 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22594 can be used as that dest register. Return the dest register. */
22597 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
22599 if (op2 == const0_rtx)
22602 if (GET_CODE (scratch) == SCRATCH)
22603 scratch = gen_reg_rtx (mode);
22605 if (logical_operand (op2, mode))
22606 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
22608 emit_insn (gen_rtx_SET (scratch,
22609 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
22615 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
22618 machine_mode op_mode;
22619 enum rtx_code cond_code;
22620 rtx result = operands[0];
22622 condition_rtx = rs6000_generate_compare (operands[1], mode);
22623 cond_code = GET_CODE (condition_rtx);
22625 if (cond_code == NE
22626 || cond_code == GE || cond_code == LE
22627 || cond_code == GEU || cond_code == LEU
22628 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
22630 rtx not_result = gen_reg_rtx (CCEQmode);
22631 rtx not_op, rev_cond_rtx;
22632 machine_mode cc_mode;
22634 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
22636 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
22637 SImode, XEXP (condition_rtx, 0), const0_rtx);
22638 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
22639 emit_insn (gen_rtx_SET (not_result, not_op));
22640 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
22643 op_mode = GET_MODE (XEXP (operands[1], 0));
22644 if (op_mode == VOIDmode)
22645 op_mode = GET_MODE (XEXP (operands[1], 1));
22647 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
22649 PUT_MODE (condition_rtx, DImode);
22650 convert_move (result, condition_rtx, 0);
22654 PUT_MODE (condition_rtx, SImode);
22655 emit_insn (gen_rtx_SET (result, condition_rtx));
22659 /* Emit a branch of kind CODE to location LOC. */
22662 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
22664 rtx condition_rtx, loc_ref;
22666 condition_rtx = rs6000_generate_compare (operands[0], mode);
22667 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
22668 emit_jump_insn (gen_rtx_SET (pc_rtx,
22669 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
22670 loc_ref, pc_rtx)));
22673 /* Return the string to output a conditional branch to LABEL, which is
22674 the operand template of the label, or NULL if the branch is really a
22675 conditional return.
22677 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22678 condition code register and its mode specifies what kind of
22679 comparison we made.
22681 REVERSED is nonzero if we should reverse the sense of the comparison.
22683 INSN is the insn. */
22686 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
22688 static char string[64];
22689 enum rtx_code code = GET_CODE (op);
22690 rtx cc_reg = XEXP (op, 0);
22691 machine_mode mode = GET_MODE (cc_reg);
22692 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
22693 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
22694 int really_reversed = reversed ^ need_longbranch;
22700 validate_condition_mode (code, mode);
22702 /* Work out which way this really branches. We could use
22703 reverse_condition_maybe_unordered here always but this
22704 makes the resulting assembler clearer. */
22705 if (really_reversed)
22707 /* Reversal of FP compares takes care -- an ordered compare
22708 becomes an unordered compare and vice versa. */
22709 if (mode == CCFPmode)
22710 code = reverse_condition_maybe_unordered (code);
22712 code = reverse_condition (code);
22717 /* Not all of these are actually distinct opcodes, but
22718 we distinguish them for clarity of the resulting assembler. */
22719 case NE: case LTGT:
22720 ccode = "ne"; break;
22721 case EQ: case UNEQ:
22722 ccode = "eq"; break;
22724 ccode = "ge"; break;
22725 case GT: case GTU: case UNGT:
22726 ccode = "gt"; break;
22728 ccode = "le"; break;
22729 case LT: case LTU: case UNLT:
22730 ccode = "lt"; break;
22731 case UNORDERED: ccode = "un"; break;
22732 case ORDERED: ccode = "nu"; break;
22733 case UNGE: ccode = "nl"; break;
22734 case UNLE: ccode = "ng"; break;
22736 gcc_unreachable ();
22739 /* Maybe we have a guess as to how likely the branch is. */
22741 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
22742 if (note != NULL_RTX)
22744 /* PROB is the difference from 50%. */
22745 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
22746 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
22748 /* Only hint for highly probable/improbable branches on newer cpus when
22749 we have real profile data, as static prediction overrides processor
22750 dynamic prediction. For older cpus we may as well always hint, but
22751 assume not taken for branches that are very close to 50% as a
22752 mispredicted taken branch is more expensive than a
22753 mispredicted not-taken branch. */
22754 if (rs6000_always_hint
22755 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
22756 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
22757 && br_prob_note_reliable_p (note)))
22759 if (abs (prob) > REG_BR_PROB_BASE / 20
22760 && ((prob > 0) ^ need_longbranch))
22768 s += sprintf (s, "b%slr%s ", ccode, pred);
22770 s += sprintf (s, "b%s%s ", ccode, pred);
22772 /* We need to escape any '%' characters in the reg_names string.
22773 Assume they'd only be the first character.... */
22774 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
22776 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
22780 /* If the branch distance was too far, we may have to use an
22781 unconditional branch to go the distance. */
22782 if (need_longbranch)
22783 s += sprintf (s, ",$+8\n\tb %s", label);
22785 s += sprintf (s, ",%s", label);
22791 /* Return insn for VSX or Altivec comparisons. */
22794 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
22797 machine_mode mode = GET_MODE (op0);
22805 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22816 mask = gen_reg_rtx (mode);
22817 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22824 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22825 DMODE is expected destination mode. This is a recursive function. */
22828 rs6000_emit_vector_compare (enum rtx_code rcode,
22830 machine_mode dmode)
22833 bool swap_operands = false;
22834 bool try_again = false;
22836 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22837 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22839 /* See if the comparison works as is. */
22840 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22848 swap_operands = true;
22853 swap_operands = true;
22861 /* Invert condition and try again.
22862 e.g., A != B becomes ~(A==B). */
22864 enum rtx_code rev_code;
22865 enum insn_code nor_code;
22868 rev_code = reverse_condition_maybe_unordered (rcode);
22869 if (rev_code == UNKNOWN)
22872 nor_code = optab_handler (one_cmpl_optab, dmode);
22873 if (nor_code == CODE_FOR_nothing)
22876 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22880 mask = gen_reg_rtx (dmode);
22881 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22889 /* Try GT/GTU/LT/LTU OR EQ */
22892 enum insn_code ior_code;
22893 enum rtx_code new_code;
22914 gcc_unreachable ();
22917 ior_code = optab_handler (ior_optab, dmode);
22918 if (ior_code == CODE_FOR_nothing)
22921 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22925 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22929 mask = gen_reg_rtx (dmode);
22930 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22941 std::swap (op0, op1);
22943 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22948 /* You only get two chances. */
22952 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22953 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22954 operands for the relation operation COND. */
22957 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22958 rtx cond, rtx cc_op0, rtx cc_op1)
22960 machine_mode dest_mode = GET_MODE (dest);
22961 machine_mode mask_mode = GET_MODE (cc_op0);
22962 enum rtx_code rcode = GET_CODE (cond);
22963 machine_mode cc_mode = CCmode;
22966 bool invert_move = false;
22968 if (VECTOR_UNIT_NONE_P (dest_mode))
22971 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22972 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22976 /* Swap operands if we can, and fall back to doing the operation as
22977 specified, and doing a NOR to invert the test. */
22983 /* Invert condition and try again.
22984 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22985 invert_move = true;
22986 rcode = reverse_condition_maybe_unordered (rcode);
22987 if (rcode == UNKNOWN)
22993 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22995 /* Invert condition to avoid compound test. */
22996 invert_move = true;
22997 rcode = reverse_condition (rcode);
23005 /* Mark unsigned tests with CCUNSmode. */
23006 cc_mode = CCUNSmode;
23008 /* Invert condition to avoid compound test if necessary. */
23009 if (rcode == GEU || rcode == LEU)
23011 invert_move = true;
23012 rcode = reverse_condition (rcode);
23020 /* Get the vector mask for the given relational operations. */
23021 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
23027 std::swap (op_true, op_false);
23029 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
23030 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
23031 && (GET_CODE (op_true) == CONST_VECTOR
23032 || GET_CODE (op_false) == CONST_VECTOR))
23034 rtx constant_0 = CONST0_RTX (dest_mode);
23035 rtx constant_m1 = CONSTM1_RTX (dest_mode);
23037 if (op_true == constant_m1 && op_false == constant_0)
23039 emit_move_insn (dest, mask);
23043 else if (op_true == constant_0 && op_false == constant_m1)
23045 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
23049 /* If we can't use the vector comparison directly, perhaps we can use
23050 the mask for the true or false fields, instead of loading up a
23052 if (op_true == constant_m1)
23055 if (op_false == constant_0)
23059 if (!REG_P (op_true) && !SUBREG_P (op_true))
23060 op_true = force_reg (dest_mode, op_true);
23062 if (!REG_P (op_false) && !SUBREG_P (op_false))
23063 op_false = force_reg (dest_mode, op_false);
23065 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
23066 CONST0_RTX (dest_mode));
23067 emit_insn (gen_rtx_SET (dest,
23068 gen_rtx_IF_THEN_ELSE (dest_mode,
23075 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
23076 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
23077 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
23078 hardware has no such operation. */
23081 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23083 enum rtx_code code = GET_CODE (op);
23084 rtx op0 = XEXP (op, 0);
23085 rtx op1 = XEXP (op, 1);
23086 machine_mode compare_mode = GET_MODE (op0);
23087 machine_mode result_mode = GET_MODE (dest);
23088 bool max_p = false;
23090 if (result_mode != compare_mode)
23093 if (code == GE || code == GT)
23095 else if (code == LE || code == LT)
23100 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
23103 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
23109 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
23113 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
23114 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
23115 operands of the last comparison is nonzero/true, FALSE_COND if it is
23116 zero/false. Return 0 if the hardware has no such operation. */
23119 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23121 enum rtx_code code = GET_CODE (op);
23122 rtx op0 = XEXP (op, 0);
23123 rtx op1 = XEXP (op, 1);
23124 machine_mode result_mode = GET_MODE (dest);
23129 if (!can_create_pseudo_p ())
23142 code = swap_condition (code);
23143 std::swap (op0, op1);
23150 /* Generate: [(parallel [(set (dest)
23151 (if_then_else (op (cmp1) (cmp2))
23154 (clobber (scratch))])]. */
23156 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
23157 cmove_rtx = gen_rtx_SET (dest,
23158 gen_rtx_IF_THEN_ELSE (result_mode,
23163 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
23164 emit_insn (gen_rtx_PARALLEL (VOIDmode,
23165 gen_rtvec (2, cmove_rtx, clobber_rtx)));
23170 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
23171 operands of the last comparison is nonzero/true, FALSE_COND if it
23172 is zero/false. Return 0 if the hardware has no such operation. */
23175 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23177 enum rtx_code code = GET_CODE (op);
23178 rtx op0 = XEXP (op, 0);
23179 rtx op1 = XEXP (op, 1);
23180 machine_mode compare_mode = GET_MODE (op0);
23181 machine_mode result_mode = GET_MODE (dest);
23183 bool is_against_zero;
23185 /* These modes should always match. */
23186 if (GET_MODE (op1) != compare_mode
23187 /* In the isel case however, we can use a compare immediate, so
23188 op1 may be a small constant. */
23189 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
23191 if (GET_MODE (true_cond) != result_mode)
23193 if (GET_MODE (false_cond) != result_mode)
23196 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
23197 if (TARGET_P9_MINMAX
23198 && (compare_mode == SFmode || compare_mode == DFmode)
23199 && (result_mode == SFmode || result_mode == DFmode))
23201 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
23204 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
23208 /* Don't allow using floating point comparisons for integer results for
23210 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
23213 /* First, work out if the hardware can do this at all, or
23214 if it's too slow.... */
23215 if (!FLOAT_MODE_P (compare_mode))
23218 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
23222 is_against_zero = op1 == CONST0_RTX (compare_mode);
23224 /* A floating-point subtract might overflow, underflow, or produce
23225 an inexact result, thus changing the floating-point flags, so it
23226 can't be generated if we care about that. It's safe if one side
23227 of the construct is zero, since then no subtract will be
23229 if (SCALAR_FLOAT_MODE_P (compare_mode)
23230 && flag_trapping_math && ! is_against_zero)
23233 /* Eliminate half of the comparisons by switching operands, this
23234 makes the remaining code simpler. */
23235 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
23236 || code == LTGT || code == LT || code == UNLE)
23238 code = reverse_condition_maybe_unordered (code);
23240 true_cond = false_cond;
23244 /* UNEQ and LTGT take four instructions for a comparison with zero,
23245 it'll probably be faster to use a branch here too. */
23246 if (code == UNEQ && HONOR_NANS (compare_mode))
23249 /* We're going to try to implement comparisons by performing
23250 a subtract, then comparing against zero. Unfortunately,
23251 Inf - Inf is NaN which is not zero, and so if we don't
23252 know that the operand is finite and the comparison
23253 would treat EQ different to UNORDERED, we can't do it. */
23254 if (HONOR_INFINITIES (compare_mode)
23255 && code != GT && code != UNGE
23256 && (GET_CODE (op1) != CONST_DOUBLE
23257 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
23258 /* Constructs of the form (a OP b ? a : b) are safe. */
23259 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
23260 || (! rtx_equal_p (op0, true_cond)
23261 && ! rtx_equal_p (op1, true_cond))))
23264 /* At this point we know we can use fsel. */
23266 /* Reduce the comparison to a comparison against zero. */
23267 if (! is_against_zero)
23269 temp = gen_reg_rtx (compare_mode);
23270 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
23272 op1 = CONST0_RTX (compare_mode);
23275 /* If we don't care about NaNs we can reduce some of the comparisons
23276 down to faster ones. */
23277 if (! HONOR_NANS (compare_mode))
23283 true_cond = false_cond;
23296 /* Now, reduce everything down to a GE. */
23303 temp = gen_reg_rtx (compare_mode);
23304 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23309 temp = gen_reg_rtx (compare_mode);
23310 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
23315 temp = gen_reg_rtx (compare_mode);
23316 emit_insn (gen_rtx_SET (temp,
23317 gen_rtx_NEG (compare_mode,
23318 gen_rtx_ABS (compare_mode, op0))));
23323 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
23324 temp = gen_reg_rtx (result_mode);
23325 emit_insn (gen_rtx_SET (temp,
23326 gen_rtx_IF_THEN_ELSE (result_mode,
23327 gen_rtx_GE (VOIDmode,
23329 true_cond, false_cond)));
23330 false_cond = true_cond;
23333 temp = gen_reg_rtx (compare_mode);
23334 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23339 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
23340 temp = gen_reg_rtx (result_mode);
23341 emit_insn (gen_rtx_SET (temp,
23342 gen_rtx_IF_THEN_ELSE (result_mode,
23343 gen_rtx_GE (VOIDmode,
23345 true_cond, false_cond)));
23346 true_cond = false_cond;
23349 temp = gen_reg_rtx (compare_mode);
23350 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
23355 gcc_unreachable ();
23358 emit_insn (gen_rtx_SET (dest,
23359 gen_rtx_IF_THEN_ELSE (result_mode,
23360 gen_rtx_GE (VOIDmode,
23362 true_cond, false_cond)));
23366 /* Same as above, but for ints (isel). */
23369 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
23371 rtx condition_rtx, cr;
23372 machine_mode mode = GET_MODE (dest);
23373 enum rtx_code cond_code;
23374 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
23377 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
23380 /* We still have to do the compare, because isel doesn't do a
23381 compare, it just looks at the CRx bits set by a previous compare
23383 condition_rtx = rs6000_generate_compare (op, mode);
23384 cond_code = GET_CODE (condition_rtx);
23385 cr = XEXP (condition_rtx, 0);
23386 signedp = GET_MODE (cr) == CCmode;
23388 isel_func = (mode == SImode
23389 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
23390 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
23394 case LT: case GT: case LTU: case GTU: case EQ:
23395 /* isel handles these directly. */
23399 /* We need to swap the sense of the comparison. */
23401 std::swap (false_cond, true_cond);
23402 PUT_CODE (condition_rtx, reverse_condition (cond_code));
23407 false_cond = force_reg (mode, false_cond);
23408 if (true_cond != const0_rtx)
23409 true_cond = force_reg (mode, true_cond);
23411 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
23417 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
23419 machine_mode mode = GET_MODE (op0);
23423 /* VSX/altivec have direct min/max insns. */
23424 if ((code == SMAX || code == SMIN)
23425 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
23426 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
23428 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
23432 if (code == SMAX || code == SMIN)
23437 if (code == SMAX || code == UMAX)
23438 target = emit_conditional_move (dest, c, op0, op1, mode,
23439 op0, op1, mode, 0);
23441 target = emit_conditional_move (dest, c, op0, op1, mode,
23442 op1, op0, mode, 0);
23443 gcc_assert (target);
23444 if (target != dest)
23445 emit_move_insn (dest, target);
23448 /* A subroutine of the atomic operation splitters. Jump to LABEL if
23449 COND is true. Mark the jump as unlikely to be taken. */
23452 emit_unlikely_jump (rtx cond, rtx label)
23454 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
23455 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
23456 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
23459 /* A subroutine of the atomic operation splitters. Emit a load-locked
23460 instruction in MODE. For QI/HImode, possibly use a pattern than includes
23461 the zero_extend operation. */
23464 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
23466 rtx (*fn) (rtx, rtx) = NULL;
23471 fn = gen_load_lockedqi;
23474 fn = gen_load_lockedhi;
23477 if (GET_MODE (mem) == QImode)
23478 fn = gen_load_lockedqi_si;
23479 else if (GET_MODE (mem) == HImode)
23480 fn = gen_load_lockedhi_si;
23482 fn = gen_load_lockedsi;
23485 fn = gen_load_lockeddi;
23488 fn = gen_load_lockedti;
23491 gcc_unreachable ();
23493 emit_insn (fn (reg, mem));
23496 /* A subroutine of the atomic operation splitters. Emit a store-conditional
23497 instruction in MODE. */
23500 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
23502 rtx (*fn) (rtx, rtx, rtx) = NULL;
23507 fn = gen_store_conditionalqi;
23510 fn = gen_store_conditionalhi;
23513 fn = gen_store_conditionalsi;
23516 fn = gen_store_conditionaldi;
23519 fn = gen_store_conditionalti;
23522 gcc_unreachable ();
23525 /* Emit sync before stwcx. to address PPC405 Erratum. */
23526 if (PPC405_ERRATUM77)
23527 emit_insn (gen_hwsync ());
23529 emit_insn (fn (res, mem, val));
23532 /* Expand barriers before and after a load_locked/store_cond sequence. */
23535 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
23537 rtx addr = XEXP (mem, 0);
23539 if (!legitimate_indirect_address_p (addr, reload_completed)
23540 && !legitimate_indexed_address_p (addr, reload_completed))
23542 addr = force_reg (Pmode, addr);
23543 mem = replace_equiv_address_nv (mem, addr);
23548 case MEMMODEL_RELAXED:
23549 case MEMMODEL_CONSUME:
23550 case MEMMODEL_ACQUIRE:
23552 case MEMMODEL_RELEASE:
23553 case MEMMODEL_ACQ_REL:
23554 emit_insn (gen_lwsync ());
23556 case MEMMODEL_SEQ_CST:
23557 emit_insn (gen_hwsync ());
23560 gcc_unreachable ();
23566 rs6000_post_atomic_barrier (enum memmodel model)
23570 case MEMMODEL_RELAXED:
23571 case MEMMODEL_CONSUME:
23572 case MEMMODEL_RELEASE:
23574 case MEMMODEL_ACQUIRE:
23575 case MEMMODEL_ACQ_REL:
23576 case MEMMODEL_SEQ_CST:
23577 emit_insn (gen_isync ());
23580 gcc_unreachable ();
23584 /* A subroutine of the various atomic expanders. For sub-word operations,
23585 we must adjust things to operate on SImode. Given the original MEM,
23586 return a new aligned memory. Also build and return the quantities by
23587 which to shift and mask. */
23590 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
23592 rtx addr, align, shift, mask, mem;
23593 HOST_WIDE_INT shift_mask;
23594 machine_mode mode = GET_MODE (orig_mem);
23596 /* For smaller modes, we have to implement this via SImode. */
23597 shift_mask = (mode == QImode ? 0x18 : 0x10);
23599 addr = XEXP (orig_mem, 0);
23600 addr = force_reg (GET_MODE (addr), addr);
23602 /* Aligned memory containing subword. Generate a new memory. We
23603 do not want any of the existing MEM_ATTR data, as we're now
23604 accessing memory outside the original object. */
23605 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
23606 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23607 mem = gen_rtx_MEM (SImode, align);
23608 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
23609 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
23610 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
23612 /* Shift amount for subword relative to aligned word. */
23613 shift = gen_reg_rtx (SImode);
23614 addr = gen_lowpart (SImode, addr);
23615 rtx tmp = gen_reg_rtx (SImode);
23616 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
23617 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
23618 if (BYTES_BIG_ENDIAN)
23619 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
23620 shift, 1, OPTAB_LIB_WIDEN);
23623 /* Mask for insertion. */
23624 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
23625 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
23631 /* A subroutine of the various atomic expanders. For sub-word operands,
23632 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23635 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
23639 x = gen_reg_rtx (SImode);
23640 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
23641 gen_rtx_NOT (SImode, mask),
23644 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
23649 /* A subroutine of the various atomic expanders. For sub-word operands,
23650 extract WIDE to NARROW via SHIFT. */
23653 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
23655 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
23656 wide, 1, OPTAB_LIB_WIDEN);
23657 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
23660 /* Expand an atomic compare and swap operation. */
23663 rs6000_expand_atomic_compare_and_swap (rtx operands[])
23665 rtx boolval, retval, mem, oldval, newval, cond;
23666 rtx label1, label2, x, mask, shift;
23667 machine_mode mode, orig_mode;
23668 enum memmodel mod_s, mod_f;
23671 boolval = operands[0];
23672 retval = operands[1];
23674 oldval = operands[3];
23675 newval = operands[4];
23676 is_weak = (INTVAL (operands[5]) != 0);
23677 mod_s = memmodel_base (INTVAL (operands[6]));
23678 mod_f = memmodel_base (INTVAL (operands[7]));
23679 orig_mode = mode = GET_MODE (mem);
23681 mask = shift = NULL_RTX;
23682 if (mode == QImode || mode == HImode)
23684 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23685 lwarx and shift/mask operations. With power8, we need to do the
23686 comparison in SImode, but the store is still done in QI/HImode. */
23687 oldval = convert_modes (SImode, mode, oldval, 1);
23689 if (!TARGET_SYNC_HI_QI)
23691 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23693 /* Shift and mask OLDVAL into position with the word. */
23694 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
23695 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23697 /* Shift and mask NEWVAL into position within the word. */
23698 newval = convert_modes (SImode, mode, newval, 1);
23699 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
23700 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23703 /* Prepare to adjust the return value. */
23704 retval = gen_reg_rtx (SImode);
23707 else if (reg_overlap_mentioned_p (retval, oldval))
23708 oldval = copy_to_reg (oldval);
23710 if (mode != TImode && !reg_or_short_operand (oldval, mode))
23711 oldval = copy_to_mode_reg (mode, oldval);
23713 if (reg_overlap_mentioned_p (retval, newval))
23714 newval = copy_to_reg (newval);
23716 mem = rs6000_pre_atomic_barrier (mem, mod_s);
23721 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23722 emit_label (XEXP (label1, 0));
23724 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23726 emit_load_locked (mode, retval, mem);
23730 x = expand_simple_binop (SImode, AND, retval, mask,
23731 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23733 cond = gen_reg_rtx (CCmode);
23734 /* If we have TImode, synthesize a comparison. */
23735 if (mode != TImode)
23736 x = gen_rtx_COMPARE (CCmode, x, oldval);
23739 rtx xor1_result = gen_reg_rtx (DImode);
23740 rtx xor2_result = gen_reg_rtx (DImode);
23741 rtx or_result = gen_reg_rtx (DImode);
23742 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
23743 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
23744 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
23745 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
23747 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
23748 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
23749 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
23750 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
23753 emit_insn (gen_rtx_SET (cond, x));
23755 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23756 emit_unlikely_jump (x, label2);
23760 x = rs6000_mask_atomic_subword (retval, newval, mask);
23762 emit_store_conditional (orig_mode, cond, mem, x);
23766 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23767 emit_unlikely_jump (x, label1);
23770 if (!is_mm_relaxed (mod_f))
23771 emit_label (XEXP (label2, 0));
23773 rs6000_post_atomic_barrier (mod_s);
23775 if (is_mm_relaxed (mod_f))
23776 emit_label (XEXP (label2, 0));
23779 rs6000_finish_atomic_subword (operands[1], retval, shift);
23780 else if (mode != GET_MODE (operands[1]))
23781 convert_move (operands[1], retval, 1);
23783 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23784 x = gen_rtx_EQ (SImode, cond, const0_rtx);
23785 emit_insn (gen_rtx_SET (boolval, x));
23788 /* Expand an atomic exchange operation. */
23791 rs6000_expand_atomic_exchange (rtx operands[])
23793 rtx retval, mem, val, cond;
23795 enum memmodel model;
23796 rtx label, x, mask, shift;
23798 retval = operands[0];
23801 model = memmodel_base (INTVAL (operands[3]));
23802 mode = GET_MODE (mem);
23804 mask = shift = NULL_RTX;
23805 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
23807 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23809 /* Shift and mask VAL into position with the word. */
23810 val = convert_modes (SImode, mode, val, 1);
23811 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23812 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23814 /* Prepare to adjust the return value. */
23815 retval = gen_reg_rtx (SImode);
23819 mem = rs6000_pre_atomic_barrier (mem, model);
23821 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23822 emit_label (XEXP (label, 0));
23824 emit_load_locked (mode, retval, mem);
23828 x = rs6000_mask_atomic_subword (retval, val, mask);
23830 cond = gen_reg_rtx (CCmode);
23831 emit_store_conditional (mode, cond, mem, x);
23833 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23834 emit_unlikely_jump (x, label);
23836 rs6000_post_atomic_barrier (model);
23839 rs6000_finish_atomic_subword (operands[0], retval, shift);
23842 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23843 to perform. MEM is the memory on which to operate. VAL is the second
23844 operand of the binary operator. BEFORE and AFTER are optional locations to
23845 return the value of MEM either before of after the operation. MODEL_RTX
23846 is a CONST_INT containing the memory model to use. */
23849 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23850 rtx orig_before, rtx orig_after, rtx model_rtx)
23852 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23853 machine_mode mode = GET_MODE (mem);
23854 machine_mode store_mode = mode;
23855 rtx label, x, cond, mask, shift;
23856 rtx before = orig_before, after = orig_after;
23858 mask = shift = NULL_RTX;
23859 /* On power8, we want to use SImode for the operation. On previous systems,
23860 use the operation in a subword and shift/mask to get the proper byte or
23862 if (mode == QImode || mode == HImode)
23864 if (TARGET_SYNC_HI_QI)
23866 val = convert_modes (SImode, mode, val, 1);
23868 /* Prepare to adjust the return value. */
23869 before = gen_reg_rtx (SImode);
23871 after = gen_reg_rtx (SImode);
23876 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23878 /* Shift and mask VAL into position with the word. */
23879 val = convert_modes (SImode, mode, val, 1);
23880 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23881 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23887 /* We've already zero-extended VAL. That is sufficient to
23888 make certain that it does not affect other bits. */
23893 /* If we make certain that all of the other bits in VAL are
23894 set, that will be sufficient to not affect other bits. */
23895 x = gen_rtx_NOT (SImode, mask);
23896 x = gen_rtx_IOR (SImode, x, val);
23897 emit_insn (gen_rtx_SET (val, x));
23904 /* These will all affect bits outside the field and need
23905 adjustment via MASK within the loop. */
23909 gcc_unreachable ();
23912 /* Prepare to adjust the return value. */
23913 before = gen_reg_rtx (SImode);
23915 after = gen_reg_rtx (SImode);
23916 store_mode = mode = SImode;
23920 mem = rs6000_pre_atomic_barrier (mem, model);
23922 label = gen_label_rtx ();
23923 emit_label (label);
23924 label = gen_rtx_LABEL_REF (VOIDmode, label);
23926 if (before == NULL_RTX)
23927 before = gen_reg_rtx (mode);
23929 emit_load_locked (mode, before, mem);
23933 x = expand_simple_binop (mode, AND, before, val,
23934 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23935 after = expand_simple_unop (mode, NOT, x, after, 1);
23939 after = expand_simple_binop (mode, code, before, val,
23940 after, 1, OPTAB_LIB_WIDEN);
23946 x = expand_simple_binop (SImode, AND, after, mask,
23947 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23948 x = rs6000_mask_atomic_subword (before, x, mask);
23950 else if (store_mode != mode)
23951 x = convert_modes (store_mode, mode, x, 1);
23953 cond = gen_reg_rtx (CCmode);
23954 emit_store_conditional (store_mode, cond, mem, x);
23956 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23957 emit_unlikely_jump (x, label);
23959 rs6000_post_atomic_barrier (model);
23963 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23964 then do the calcuations in a SImode register. */
23966 rs6000_finish_atomic_subword (orig_before, before, shift);
23968 rs6000_finish_atomic_subword (orig_after, after, shift);
23970 else if (store_mode != mode)
23972 /* QImode/HImode on machines with lbarx/lharx where we do the native
23973 operation and then do the calcuations in a SImode register. */
23975 convert_move (orig_before, before, 1);
23977 convert_move (orig_after, after, 1);
23979 else if (orig_after && after != orig_after)
23980 emit_move_insn (orig_after, after);
23983 /* Emit instructions to move SRC to DST. Called by splitters for
23984 multi-register moves. It will emit at most one instruction for
23985 each register that is accessed; that is, it won't emit li/lis pairs
23986 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23990 rs6000_split_multireg_move (rtx dst, rtx src)
23992 /* The register number of the first register being moved. */
23994 /* The mode that is to be moved. */
23996 /* The mode that the move is being done in, and its size. */
23997 machine_mode reg_mode;
23999 /* The number of registers that will be moved. */
24002 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
24003 mode = GET_MODE (dst);
24004 nregs = hard_regno_nregs (reg, mode);
24005 if (FP_REGNO_P (reg))
24006 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
24007 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
24008 else if (ALTIVEC_REGNO_P (reg))
24009 reg_mode = V16QImode;
24011 reg_mode = word_mode;
24012 reg_mode_size = GET_MODE_SIZE (reg_mode);
24014 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
24016 /* TDmode residing in FP registers is special, since the ISA requires that
24017 the lower-numbered word of a register pair is always the most significant
24018 word, even in little-endian mode. This does not match the usual subreg
24019 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
24020 the appropriate constituent registers "by hand" in little-endian mode.
24022 Note we do not need to check for destructive overlap here since TDmode
24023 can only reside in even/odd register pairs. */
24024 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
24029 for (i = 0; i < nregs; i++)
24031 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
24032 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
24034 p_src = simplify_gen_subreg (reg_mode, src, mode,
24035 i * reg_mode_size);
24037 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
24038 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
24040 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
24041 i * reg_mode_size);
24043 emit_insn (gen_rtx_SET (p_dst, p_src));
24049 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
24051 /* Move register range backwards, if we might have destructive
24054 for (i = nregs - 1; i >= 0; i--)
24055 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
24056 i * reg_mode_size),
24057 simplify_gen_subreg (reg_mode, src, mode,
24058 i * reg_mode_size)));
24064 bool used_update = false;
24065 rtx restore_basereg = NULL_RTX;
24067 if (MEM_P (src) && INT_REGNO_P (reg))
24071 if (GET_CODE (XEXP (src, 0)) == PRE_INC
24072 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
24075 breg = XEXP (XEXP (src, 0), 0);
24076 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
24077 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
24078 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
24079 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
24080 src = replace_equiv_address (src, breg);
24082 else if (! rs6000_offsettable_memref_p (src, reg_mode))
24084 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
24086 rtx basereg = XEXP (XEXP (src, 0), 0);
24089 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
24090 emit_insn (gen_rtx_SET (ndst,
24091 gen_rtx_MEM (reg_mode,
24093 used_update = true;
24096 emit_insn (gen_rtx_SET (basereg,
24097 XEXP (XEXP (src, 0), 1)));
24098 src = replace_equiv_address (src, basereg);
24102 rtx basereg = gen_rtx_REG (Pmode, reg);
24103 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
24104 src = replace_equiv_address (src, basereg);
24108 breg = XEXP (src, 0);
24109 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
24110 breg = XEXP (breg, 0);
24112 /* If the base register we are using to address memory is
24113 also a destination reg, then change that register last. */
24115 && REGNO (breg) >= REGNO (dst)
24116 && REGNO (breg) < REGNO (dst) + nregs)
24117 j = REGNO (breg) - REGNO (dst);
24119 else if (MEM_P (dst) && INT_REGNO_P (reg))
24123 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
24124 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
24127 breg = XEXP (XEXP (dst, 0), 0);
24128 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
24129 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
24130 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
24132 /* We have to update the breg before doing the store.
24133 Use store with update, if available. */
24137 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
24138 emit_insn (TARGET_32BIT
24139 ? (TARGET_POWERPC64
24140 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
24141 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
24142 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
24143 used_update = true;
24146 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
24147 dst = replace_equiv_address (dst, breg);
24149 else if (!rs6000_offsettable_memref_p (dst, reg_mode)
24150 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
24152 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
24154 rtx basereg = XEXP (XEXP (dst, 0), 0);
24157 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
24158 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
24161 used_update = true;
24164 emit_insn (gen_rtx_SET (basereg,
24165 XEXP (XEXP (dst, 0), 1)));
24166 dst = replace_equiv_address (dst, basereg);
24170 rtx basereg = XEXP (XEXP (dst, 0), 0);
24171 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
24172 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
24174 && REG_P (offsetreg)
24175 && REGNO (basereg) != REGNO (offsetreg));
24176 if (REGNO (basereg) == 0)
24178 rtx tmp = offsetreg;
24179 offsetreg = basereg;
24182 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
24183 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
24184 dst = replace_equiv_address (dst, basereg);
24187 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
24188 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode));
24191 for (i = 0; i < nregs; i++)
24193 /* Calculate index to next subword. */
24198 /* If compiler already emitted move of first word by
24199 store with update, no need to do anything. */
24200 if (j == 0 && used_update)
24203 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
24204 j * reg_mode_size),
24205 simplify_gen_subreg (reg_mode, src, mode,
24206 j * reg_mode_size)));
24208 if (restore_basereg != NULL_RTX)
24209 emit_insn (restore_basereg);
24214 /* This page contains routines that are used to determine what the
24215 function prologue and epilogue code will do and write them out. */
24217 /* Determine whether the REG is really used. */
24220 save_reg_p (int reg)
24222 /* We need to mark the PIC offset register live for the same conditions
24223 as it is set up, or otherwise it won't be saved before we clobber it. */
24225 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
24227 /* When calling eh_return, we must return true for all the cases
24228 where conditional_register_usage marks the PIC offset reg
24230 if (TARGET_TOC && TARGET_MINIMAL_TOC
24231 && (crtl->calls_eh_return
24232 || df_regs_ever_live_p (reg)
24233 || !constant_pool_empty_p ()))
24236 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
24241 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
24244 /* Return the first fixed-point register that is required to be
24245 saved. 32 if none. */
24248 first_reg_to_save (void)
24252 /* Find lowest numbered live register. */
24253 for (first_reg = 13; first_reg <= 31; first_reg++)
24254 if (save_reg_p (first_reg))
24259 && crtl->uses_pic_offset_table
24260 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
24261 return RS6000_PIC_OFFSET_TABLE_REGNUM;
24267 /* Similar, for FP regs. */
24270 first_fp_reg_to_save (void)
24274 /* Find lowest numbered live register. */
24275 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
24276 if (save_reg_p (first_reg))
24282 /* Similar, for AltiVec regs. */
24285 first_altivec_reg_to_save (void)
24289 /* Stack frame remains as is unless we are in AltiVec ABI. */
24290 if (! TARGET_ALTIVEC_ABI)
24291 return LAST_ALTIVEC_REGNO + 1;
24293 /* On Darwin, the unwind routines are compiled without
24294 TARGET_ALTIVEC, and use save_world to save/restore the
24295 altivec registers when necessary. */
24296 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
24297 && ! TARGET_ALTIVEC)
24298 return FIRST_ALTIVEC_REGNO + 20;
24300 /* Find lowest numbered live register. */
24301 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
24302 if (save_reg_p (i))
24308 /* Return a 32-bit mask of the AltiVec registers we need to set in
24309 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
24310 the 32-bit word is 0. */
24312 static unsigned int
24313 compute_vrsave_mask (void)
24315 unsigned int i, mask = 0;
24317 /* On Darwin, the unwind routines are compiled without
24318 TARGET_ALTIVEC, and use save_world to save/restore the
24319 call-saved altivec registers when necessary. */
24320 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
24321 && ! TARGET_ALTIVEC)
24324 /* First, find out if we use _any_ altivec registers. */
24325 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
24326 if (df_regs_ever_live_p (i))
24327 mask |= ALTIVEC_REG_BIT (i);
24332 /* Next, remove the argument registers from the set. These must
24333 be in the VRSAVE mask set by the caller, so we don't need to add
24334 them in again. More importantly, the mask we compute here is
24335 used to generate CLOBBERs in the set_vrsave insn, and we do not
24336 wish the argument registers to die. */
24337 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
24338 mask &= ~ALTIVEC_REG_BIT (i);
24340 /* Similarly, remove the return value from the set. */
24343 diddle_return_value (is_altivec_return_reg, &yes);
24345 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
24351 /* For a very restricted set of circumstances, we can cut down the
24352 size of prologues/epilogues by calling our own save/restore-the-world
24356 compute_save_world_info (rs6000_stack_t *info)
24358 info->world_save_p = 1;
24360 = (WORLD_SAVE_P (info)
24361 && DEFAULT_ABI == ABI_DARWIN
24362 && !cfun->has_nonlocal_label
24363 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
24364 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
24365 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
24366 && info->cr_save_p);
24368 /* This will not work in conjunction with sibcalls. Make sure there
24369 are none. (This check is expensive, but seldom executed.) */
24370 if (WORLD_SAVE_P (info))
24373 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
24374 if (CALL_P (insn) && SIBLING_CALL_P (insn))
24376 info->world_save_p = 0;
24381 if (WORLD_SAVE_P (info))
24383 /* Even if we're not touching VRsave, make sure there's room on the
24384 stack for it, if it looks like we're calling SAVE_WORLD, which
24385 will attempt to save it. */
24386 info->vrsave_size = 4;
24388 /* If we are going to save the world, we need to save the link register too. */
24389 info->lr_save_p = 1;
24391 /* "Save" the VRsave register too if we're saving the world. */
24392 if (info->vrsave_mask == 0)
24393 info->vrsave_mask = compute_vrsave_mask ();
24395 /* Because the Darwin register save/restore routines only handle
24396 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
24398 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
24399 && (info->first_altivec_reg_save
24400 >= FIRST_SAVED_ALTIVEC_REGNO));
24408 is_altivec_return_reg (rtx reg, void *xyes)
24410 bool *yes = (bool *) xyes;
24411 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
24416 /* Return whether REG is a global user reg or has been specifed by
24417 -ffixed-REG. We should not restore these, and so cannot use
24418 lmw or out-of-line restore functions if there are any. We also
24419 can't save them (well, emit frame notes for them), because frame
24420 unwinding during exception handling will restore saved registers. */
24423 fixed_reg_p (int reg)
24425 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
24426 backend sets it, overriding anything the user might have given. */
24427 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
24428 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
24429 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
24430 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
24433 return fixed_regs[reg];
24436 /* Determine the strategy for savings/restoring registers. */
24439 SAVE_MULTIPLE = 0x1,
24440 SAVE_INLINE_GPRS = 0x2,
24441 SAVE_INLINE_FPRS = 0x4,
24442 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
24443 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
24444 SAVE_INLINE_VRS = 0x20,
24445 REST_MULTIPLE = 0x100,
24446 REST_INLINE_GPRS = 0x200,
24447 REST_INLINE_FPRS = 0x400,
24448 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
24449 REST_INLINE_VRS = 0x1000
24453 rs6000_savres_strategy (rs6000_stack_t *info,
24454 bool using_static_chain_p)
24458 /* Select between in-line and out-of-line save and restore of regs.
24459 First, all the obvious cases where we don't use out-of-line. */
24460 if (crtl->calls_eh_return
24461 || cfun->machine->ra_need_lr)
24462 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
24463 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
24464 | SAVE_INLINE_VRS | REST_INLINE_VRS);
24466 if (info->first_gp_reg_save == 32)
24467 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24469 if (info->first_fp_reg_save == 64
24470 /* The out-of-line FP routines use double-precision stores;
24471 we can't use those routines if we don't have such stores. */
24472 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT))
24473 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24475 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
24476 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24478 /* Define cutoff for using out-of-line functions to save registers. */
24479 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
24481 if (!optimize_size)
24483 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24484 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24485 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24489 /* Prefer out-of-line restore if it will exit. */
24490 if (info->first_fp_reg_save > 61)
24491 strategy |= SAVE_INLINE_FPRS;
24492 if (info->first_gp_reg_save > 29)
24494 if (info->first_fp_reg_save == 64)
24495 strategy |= SAVE_INLINE_GPRS;
24497 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24499 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
24500 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24503 else if (DEFAULT_ABI == ABI_DARWIN)
24505 if (info->first_fp_reg_save > 60)
24506 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24507 if (info->first_gp_reg_save > 29)
24508 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24509 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24513 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24514 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
24515 || info->first_fp_reg_save > 61)
24516 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24517 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24518 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24521 /* Don't bother to try to save things out-of-line if r11 is occupied
24522 by the static chain. It would require too much fiddling and the
24523 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24524 pointer on Darwin, and AIX uses r1 or r12. */
24525 if (using_static_chain_p
24526 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
24527 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
24529 | SAVE_INLINE_VRS);
24531 /* Don't ever restore fixed regs. That means we can't use the
24532 out-of-line register restore functions if a fixed reg is in the
24533 range of regs restored. */
24534 if (!(strategy & REST_INLINE_FPRS))
24535 for (int i = info->first_fp_reg_save; i < 64; i++)
24538 strategy |= REST_INLINE_FPRS;
24542 /* We can only use the out-of-line routines to restore fprs if we've
24543 saved all the registers from first_fp_reg_save in the prologue.
24544 Otherwise, we risk loading garbage. Of course, if we have saved
24545 out-of-line then we know we haven't skipped any fprs. */
24546 if ((strategy & SAVE_INLINE_FPRS)
24547 && !(strategy & REST_INLINE_FPRS))
24548 for (int i = info->first_fp_reg_save; i < 64; i++)
24549 if (!save_reg_p (i))
24551 strategy |= REST_INLINE_FPRS;
24555 /* Similarly, for altivec regs. */
24556 if (!(strategy & REST_INLINE_VRS))
24557 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24560 strategy |= REST_INLINE_VRS;
24564 if ((strategy & SAVE_INLINE_VRS)
24565 && !(strategy & REST_INLINE_VRS))
24566 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24567 if (!save_reg_p (i))
24569 strategy |= REST_INLINE_VRS;
24573 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24574 saved is an out-of-line save or restore. Set up the value for
24575 the next test (excluding out-of-line gprs). */
24576 bool lr_save_p = (info->lr_save_p
24577 || !(strategy & SAVE_INLINE_FPRS)
24578 || !(strategy & SAVE_INLINE_VRS)
24579 || !(strategy & REST_INLINE_FPRS)
24580 || !(strategy & REST_INLINE_VRS));
24582 if (TARGET_MULTIPLE
24583 && !TARGET_POWERPC64
24584 && info->first_gp_reg_save < 31
24585 && !(flag_shrink_wrap
24586 && flag_shrink_wrap_separate
24587 && optimize_function_for_speed_p (cfun)))
24590 for (int i = info->first_gp_reg_save; i < 32; i++)
24591 if (save_reg_p (i))
24595 /* Don't use store multiple if only one reg needs to be
24596 saved. This can occur for example when the ABI_V4 pic reg
24597 (r30) needs to be saved to make calls, but r31 is not
24599 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24602 /* Prefer store multiple for saves over out-of-line
24603 routines, since the store-multiple instruction will
24604 always be smaller. */
24605 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
24607 /* The situation is more complicated with load multiple.
24608 We'd prefer to use the out-of-line routines for restores,
24609 since the "exit" out-of-line routines can handle the
24610 restore of LR and the frame teardown. However if doesn't
24611 make sense to use the out-of-line routine if that is the
24612 only reason we'd need to save LR, and we can't use the
24613 "exit" out-of-line gpr restore if we have saved some
24614 fprs; In those cases it is advantageous to use load
24615 multiple when available. */
24616 if (info->first_fp_reg_save != 64 || !lr_save_p)
24617 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
24621 /* Using the "exit" out-of-line routine does not improve code size
24622 if using it would require lr to be saved and if only saving one
24624 else if (!lr_save_p && info->first_gp_reg_save > 29)
24625 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24627 /* Don't ever restore fixed regs. */
24628 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24629 for (int i = info->first_gp_reg_save; i < 32; i++)
24630 if (fixed_reg_p (i))
24632 strategy |= REST_INLINE_GPRS;
24633 strategy &= ~REST_MULTIPLE;
24637 /* We can only use load multiple or the out-of-line routines to
24638 restore gprs if we've saved all the registers from
24639 first_gp_reg_save. Otherwise, we risk loading garbage.
24640 Of course, if we have saved out-of-line or used stmw then we know
24641 we haven't skipped any gprs. */
24642 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
24643 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24644 for (int i = info->first_gp_reg_save; i < 32; i++)
24645 if (!save_reg_p (i))
24647 strategy |= REST_INLINE_GPRS;
24648 strategy &= ~REST_MULTIPLE;
24652 if (TARGET_ELF && TARGET_64BIT)
24654 if (!(strategy & SAVE_INLINE_FPRS))
24655 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24656 else if (!(strategy & SAVE_INLINE_GPRS)
24657 && info->first_fp_reg_save == 64)
24658 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
24660 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
24661 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
24663 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
24664 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24669 /* Calculate the stack information for the current function. This is
24670 complicated by having two separate calling sequences, the AIX calling
24671 sequence and the V.4 calling sequence.
24673 AIX (and Darwin/Mac OS X) stack frames look like:
24675 SP----> +---------------------------------------+
24676 | back chain to caller | 0 0
24677 +---------------------------------------+
24678 | saved CR | 4 8 (8-11)
24679 +---------------------------------------+
24681 +---------------------------------------+
24682 | reserved for compilers | 12 24
24683 +---------------------------------------+
24684 | reserved for binders | 16 32
24685 +---------------------------------------+
24686 | saved TOC pointer | 20 40
24687 +---------------------------------------+
24688 | Parameter save area (+padding*) (P) | 24 48
24689 +---------------------------------------+
24690 | Alloca space (A) | 24+P etc.
24691 +---------------------------------------+
24692 | Local variable space (L) | 24+P+A
24693 +---------------------------------------+
24694 | Float/int conversion temporary (X) | 24+P+A+L
24695 +---------------------------------------+
24696 | Save area for AltiVec registers (W) | 24+P+A+L+X
24697 +---------------------------------------+
24698 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24699 +---------------------------------------+
24700 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24701 +---------------------------------------+
24702 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24703 +---------------------------------------+
24704 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24705 +---------------------------------------+
24706 old SP->| back chain to caller's caller |
24707 +---------------------------------------+
24709 * If the alloca area is present, the parameter save area is
24710 padded so that the former starts 16-byte aligned.
24712 The required alignment for AIX configurations is two words (i.e., 8
24715 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24717 SP----> +---------------------------------------+
24718 | Back chain to caller | 0
24719 +---------------------------------------+
24720 | Save area for CR | 8
24721 +---------------------------------------+
24723 +---------------------------------------+
24724 | Saved TOC pointer | 24
24725 +---------------------------------------+
24726 | Parameter save area (+padding*) (P) | 32
24727 +---------------------------------------+
24728 | Alloca space (A) | 32+P
24729 +---------------------------------------+
24730 | Local variable space (L) | 32+P+A
24731 +---------------------------------------+
24732 | Save area for AltiVec registers (W) | 32+P+A+L
24733 +---------------------------------------+
24734 | AltiVec alignment padding (Y) | 32+P+A+L+W
24735 +---------------------------------------+
24736 | Save area for GP registers (G) | 32+P+A+L+W+Y
24737 +---------------------------------------+
24738 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24739 +---------------------------------------+
24740 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24741 +---------------------------------------+
24743 * If the alloca area is present, the parameter save area is
24744 padded so that the former starts 16-byte aligned.
24746 V.4 stack frames look like:
24748 SP----> +---------------------------------------+
24749 | back chain to caller | 0
24750 +---------------------------------------+
24751 | caller's saved LR | 4
24752 +---------------------------------------+
24753 | Parameter save area (+padding*) (P) | 8
24754 +---------------------------------------+
24755 | Alloca space (A) | 8+P
24756 +---------------------------------------+
24757 | Varargs save area (V) | 8+P+A
24758 +---------------------------------------+
24759 | Local variable space (L) | 8+P+A+V
24760 +---------------------------------------+
24761 | Float/int conversion temporary (X) | 8+P+A+V+L
24762 +---------------------------------------+
24763 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24764 +---------------------------------------+
24765 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24766 +---------------------------------------+
24767 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24768 +---------------------------------------+
24769 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24770 +---------------------------------------+
24771 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24772 +---------------------------------------+
24773 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24774 +---------------------------------------+
24775 old SP->| back chain to caller's caller |
24776 +---------------------------------------+
24778 * If the alloca area is present and the required alignment is
24779 16 bytes, the parameter save area is padded so that the
24780 alloca area starts 16-byte aligned.
24782 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24783 given. (But note below and in sysv4.h that we require only 8 and
24784 may round up the size of our stack frame anyways. The historical
24785 reason is early versions of powerpc-linux which didn't properly
24786 align the stack at program startup. A happy side-effect is that
24787 -mno-eabi libraries can be used with -meabi programs.)
24789 The EABI configuration defaults to the V.4 layout. However,
24790 the stack alignment requirements may differ. If -mno-eabi is not
24791 given, the required stack alignment is 8 bytes; if -mno-eabi is
24792 given, the required alignment is 16 bytes. (But see V.4 comment
24795 #ifndef ABI_STACK_BOUNDARY
24796 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24799 static rs6000_stack_t *
24800 rs6000_stack_info (void)
24802 /* We should never be called for thunks, we are not set up for that. */
24803 gcc_assert (!cfun->is_thunk);
24805 rs6000_stack_t *info = &stack_info;
24806 int reg_size = TARGET_32BIT ? 4 : 8;
24811 HOST_WIDE_INT non_fixed_size;
24812 bool using_static_chain_p;
24814 if (reload_completed && info->reload_completed)
24817 memset (info, 0, sizeof (*info));
24818 info->reload_completed = reload_completed;
24820 /* Select which calling sequence. */
24821 info->abi = DEFAULT_ABI;
24823 /* Calculate which registers need to be saved & save area size. */
24824 info->first_gp_reg_save = first_reg_to_save ();
24825 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24826 even if it currently looks like we won't. Reload may need it to
24827 get at a constant; if so, it will have already created a constant
24828 pool entry for it. */
24829 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24830 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24831 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24832 && crtl->uses_const_pool
24833 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24834 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24836 first_gp = info->first_gp_reg_save;
24838 info->gp_size = reg_size * (32 - first_gp);
24840 info->first_fp_reg_save = first_fp_reg_to_save ();
24841 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24843 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24844 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24845 - info->first_altivec_reg_save);
24847 /* Does this function call anything? */
24848 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24850 /* Determine if we need to save the condition code registers. */
24851 if (save_reg_p (CR2_REGNO)
24852 || save_reg_p (CR3_REGNO)
24853 || save_reg_p (CR4_REGNO))
24855 info->cr_save_p = 1;
24856 if (DEFAULT_ABI == ABI_V4)
24857 info->cr_size = reg_size;
24860 /* If the current function calls __builtin_eh_return, then we need
24861 to allocate stack space for registers that will hold data for
24862 the exception handler. */
24863 if (crtl->calls_eh_return)
24866 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24869 ehrd_size = i * UNITS_PER_WORD;
24874 /* In the ELFv2 ABI, we also need to allocate space for separate
24875 CR field save areas if the function calls __builtin_eh_return. */
24876 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24878 /* This hard-codes that we have three call-saved CR fields. */
24879 ehcr_size = 3 * reg_size;
24880 /* We do *not* use the regular CR save mechanism. */
24881 info->cr_save_p = 0;
24886 /* Determine various sizes. */
24887 info->reg_size = reg_size;
24888 info->fixed_size = RS6000_SAVE_AREA;
24889 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24890 if (cfun->calls_alloca)
24892 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24893 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24895 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24896 TARGET_ALTIVEC ? 16 : 8);
24897 if (FRAME_GROWS_DOWNWARD)
24899 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24900 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24901 - (info->fixed_size + info->vars_size + info->parm_size);
24903 if (TARGET_ALTIVEC_ABI)
24904 info->vrsave_mask = compute_vrsave_mask ();
24906 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24907 info->vrsave_size = 4;
24909 compute_save_world_info (info);
24911 /* Calculate the offsets. */
24912 switch (DEFAULT_ABI)
24916 gcc_unreachable ();
24921 info->fp_save_offset = -info->fp_size;
24922 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24924 if (TARGET_ALTIVEC_ABI)
24926 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24928 /* Align stack so vector save area is on a quadword boundary.
24929 The padding goes above the vectors. */
24930 if (info->altivec_size != 0)
24931 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24933 info->altivec_save_offset = info->vrsave_save_offset
24934 - info->altivec_padding_size
24935 - info->altivec_size;
24936 gcc_assert (info->altivec_size == 0
24937 || info->altivec_save_offset % 16 == 0);
24939 /* Adjust for AltiVec case. */
24940 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24943 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24945 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24946 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24947 info->lr_save_offset = 2*reg_size;
24951 info->fp_save_offset = -info->fp_size;
24952 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24953 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24955 if (TARGET_ALTIVEC_ABI)
24957 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24959 /* Align stack so vector save area is on a quadword boundary. */
24960 if (info->altivec_size != 0)
24961 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24963 info->altivec_save_offset = info->vrsave_save_offset
24964 - info->altivec_padding_size
24965 - info->altivec_size;
24967 /* Adjust for AltiVec case. */
24968 info->ehrd_offset = info->altivec_save_offset;
24971 info->ehrd_offset = info->cr_save_offset;
24973 info->ehrd_offset -= ehrd_size;
24974 info->lr_save_offset = reg_size;
24977 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
24978 info->save_size = RS6000_ALIGN (info->fp_size
24980 + info->altivec_size
24981 + info->altivec_padding_size
24985 + info->vrsave_size,
24988 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
24990 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
24991 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
24993 /* Determine if we need to save the link register. */
24995 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24997 && !TARGET_PROFILE_KERNEL)
24998 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
24999 #ifdef TARGET_RELOCATABLE
25000 || (DEFAULT_ABI == ABI_V4
25001 && (TARGET_RELOCATABLE || flag_pic > 1)
25002 && !constant_pool_empty_p ())
25004 || rs6000_ra_ever_killed ())
25005 info->lr_save_p = 1;
25007 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
25008 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
25009 && call_used_regs[STATIC_CHAIN_REGNUM]);
25010 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
25012 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
25013 || !(info->savres_strategy & SAVE_INLINE_FPRS)
25014 || !(info->savres_strategy & SAVE_INLINE_VRS)
25015 || !(info->savres_strategy & REST_INLINE_GPRS)
25016 || !(info->savres_strategy & REST_INLINE_FPRS)
25017 || !(info->savres_strategy & REST_INLINE_VRS))
25018 info->lr_save_p = 1;
25020 if (info->lr_save_p)
25021 df_set_regs_ever_live (LR_REGNO, true);
25023 /* Determine if we need to allocate any stack frame:
25025 For AIX we need to push the stack if a frame pointer is needed
25026 (because the stack might be dynamically adjusted), if we are
25027 debugging, if we make calls, or if the sum of fp_save, gp_save,
25028 and local variables are more than the space needed to save all
25029 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
25030 + 18*8 = 288 (GPR13 reserved).
25032 For V.4 we don't have the stack cushion that AIX uses, but assume
25033 that the debugger can handle stackless frames. */
25038 else if (DEFAULT_ABI == ABI_V4)
25039 info->push_p = non_fixed_size != 0;
25041 else if (frame_pointer_needed)
25044 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
25048 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
25054 debug_stack_info (rs6000_stack_t *info)
25056 const char *abi_string;
25059 info = rs6000_stack_info ();
25061 fprintf (stderr, "\nStack information for function %s:\n",
25062 ((current_function_decl && DECL_NAME (current_function_decl))
25063 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
25068 default: abi_string = "Unknown"; break;
25069 case ABI_NONE: abi_string = "NONE"; break;
25070 case ABI_AIX: abi_string = "AIX"; break;
25071 case ABI_ELFv2: abi_string = "ELFv2"; break;
25072 case ABI_DARWIN: abi_string = "Darwin"; break;
25073 case ABI_V4: abi_string = "V.4"; break;
25076 fprintf (stderr, "\tABI = %5s\n", abi_string);
25078 if (TARGET_ALTIVEC_ABI)
25079 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
25081 if (info->first_gp_reg_save != 32)
25082 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
25084 if (info->first_fp_reg_save != 64)
25085 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
25087 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
25088 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
25089 info->first_altivec_reg_save);
25091 if (info->lr_save_p)
25092 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
25094 if (info->cr_save_p)
25095 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
25097 if (info->vrsave_mask)
25098 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
25101 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
25104 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
25107 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
25110 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
25112 if (info->altivec_size)
25113 fprintf (stderr, "\taltivec_save_offset = %5d\n",
25114 info->altivec_save_offset);
25116 if (info->vrsave_size)
25117 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
25118 info->vrsave_save_offset);
25120 if (info->lr_save_p)
25121 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
25123 if (info->cr_save_p)
25124 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
25126 if (info->varargs_save_offset)
25127 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
25129 if (info->total_size)
25130 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
25133 if (info->vars_size)
25134 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
25137 if (info->parm_size)
25138 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
25140 if (info->fixed_size)
25141 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
25144 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
25147 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
25149 if (info->altivec_size)
25150 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
25152 if (info->vrsave_size)
25153 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
25155 if (info->altivec_padding_size)
25156 fprintf (stderr, "\taltivec_padding_size= %5d\n",
25157 info->altivec_padding_size);
25160 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
25162 if (info->save_size)
25163 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
25165 if (info->reg_size != 4)
25166 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
25168 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
25170 fprintf (stderr, "\n");
25174 rs6000_return_addr (int count, rtx frame)
25176 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
25177 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
25179 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
25181 cfun->machine->ra_needs_full_frame = 1;
25184 /* FRAME is set to frame_pointer_rtx by the generic code, but that
25185 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
25186 frame = stack_pointer_rtx;
25187 rtx prev_frame_addr = memory_address (Pmode, frame);
25188 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
25189 rtx lr_save_off = plus_constant (Pmode,
25190 prev_frame, RETURN_ADDRESS_OFFSET);
25191 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
25192 return gen_rtx_MEM (Pmode, lr_save_addr);
25195 cfun->machine->ra_need_lr = 1;
25196 return get_hard_reg_initial_val (Pmode, LR_REGNO);
25199 /* Say whether a function is a candidate for sibcall handling or not. */
25202 rs6000_function_ok_for_sibcall (tree decl, tree exp)
25207 fntype = TREE_TYPE (decl);
25209 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
25211 /* We can't do it if the called function has more vector parameters
25212 than the current function; there's nowhere to put the VRsave code. */
25213 if (TARGET_ALTIVEC_ABI
25214 && TARGET_ALTIVEC_VRSAVE
25215 && !(decl && decl == current_function_decl))
25217 function_args_iterator args_iter;
25221 /* Functions with vector parameters are required to have a
25222 prototype, so the argument type info must be available
25224 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
25225 if (TREE_CODE (type) == VECTOR_TYPE
25226 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
25229 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
25230 if (TREE_CODE (type) == VECTOR_TYPE
25231 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
25238 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
25239 functions, because the callee may have a different TOC pointer to
25240 the caller and there's no way to ensure we restore the TOC when
25241 we return. With the secure-plt SYSV ABI we can't make non-local
25242 calls when -fpic/PIC because the plt call stubs use r30. */
25243 if (DEFAULT_ABI == ABI_DARWIN
25244 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25246 && !DECL_EXTERNAL (decl)
25247 && !DECL_WEAK (decl)
25248 && (*targetm.binds_local_p) (decl))
25249 || (DEFAULT_ABI == ABI_V4
25250 && (!TARGET_SECURE_PLT
25253 && (*targetm.binds_local_p) (decl)))))
25255 tree attr_list = TYPE_ATTRIBUTES (fntype);
25257 if (!lookup_attribute ("longcall", attr_list)
25258 || lookup_attribute ("shortcall", attr_list))
25266 rs6000_ra_ever_killed (void)
25272 if (cfun->is_thunk)
25275 if (cfun->machine->lr_save_state)
25276 return cfun->machine->lr_save_state - 1;
25278 /* regs_ever_live has LR marked as used if any sibcalls are present,
25279 but this should not force saving and restoring in the
25280 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
25281 clobbers LR, so that is inappropriate. */
25283 /* Also, the prologue can generate a store into LR that
25284 doesn't really count, like this:
25287 bcl to set PIC register
25291 When we're called from the epilogue, we need to avoid counting
25292 this as a store. */
25294 push_topmost_sequence ();
25295 top = get_insns ();
25296 pop_topmost_sequence ();
25297 reg = gen_rtx_REG (Pmode, LR_REGNO);
25299 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
25305 if (!SIBLING_CALL_P (insn))
25308 else if (find_regno_note (insn, REG_INC, LR_REGNO))
25310 else if (set_of (reg, insn) != NULL_RTX
25311 && !prologue_epilogue_contains (insn))
25318 /* Emit instructions needed to load the TOC register.
25319 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
25320 a constant pool; or for SVR4 -fpic. */
25323 rs6000_emit_load_toc_table (int fromprolog)
25326 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
25328 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
25331 rtx lab, tmp1, tmp2, got;
25333 lab = gen_label_rtx ();
25334 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
25335 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25338 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25342 got = rs6000_got_sym ();
25343 tmp1 = tmp2 = dest;
25346 tmp1 = gen_reg_rtx (Pmode);
25347 tmp2 = gen_reg_rtx (Pmode);
25349 emit_insn (gen_load_toc_v4_PIC_1 (lab));
25350 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
25351 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
25352 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
25354 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
25356 emit_insn (gen_load_toc_v4_pic_si ());
25357 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25359 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
25362 rtx temp0 = (fromprolog
25363 ? gen_rtx_REG (Pmode, 0)
25364 : gen_reg_rtx (Pmode));
25370 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
25371 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25373 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
25374 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
25376 emit_insn (gen_load_toc_v4_PIC_1 (symF));
25377 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25378 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
25384 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25386 lab = gen_label_rtx ();
25387 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
25388 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
25389 if (TARGET_LINK_STACK)
25390 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
25391 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
25393 emit_insn (gen_addsi3 (dest, temp0, dest));
25395 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
25397 /* This is for AIX code running in non-PIC ELF32. */
25398 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
25401 emit_insn (gen_elf_high (dest, realsym));
25402 emit_insn (gen_elf_low (dest, dest, realsym));
25406 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
25409 emit_insn (gen_load_toc_aix_si (dest));
25411 emit_insn (gen_load_toc_aix_di (dest));
25415 /* Emit instructions to restore the link register after determining where
25416 its value has been stored. */
25419 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
25421 rs6000_stack_t *info = rs6000_stack_info ();
25424 operands[0] = source;
25425 operands[1] = scratch;
25427 if (info->lr_save_p)
25429 rtx frame_rtx = stack_pointer_rtx;
25430 HOST_WIDE_INT sp_offset = 0;
25433 if (frame_pointer_needed
25434 || cfun->calls_alloca
25435 || info->total_size > 32767)
25437 tmp = gen_frame_mem (Pmode, frame_rtx);
25438 emit_move_insn (operands[1], tmp);
25439 frame_rtx = operands[1];
25441 else if (info->push_p)
25442 sp_offset = info->total_size;
25444 tmp = plus_constant (Pmode, frame_rtx,
25445 info->lr_save_offset + sp_offset);
25446 tmp = gen_frame_mem (Pmode, tmp);
25447 emit_move_insn (tmp, operands[0]);
25450 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
25452 /* Freeze lr_save_p. We've just emitted rtl that depends on the
25453 state of lr_save_p so any change from here on would be a bug. In
25454 particular, stop rs6000_ra_ever_killed from considering the SET
25455 of lr we may have added just above. */
25456 cfun->machine->lr_save_state = info->lr_save_p + 1;
25459 static GTY(()) alias_set_type set = -1;
25462 get_TOC_alias_set (void)
25465 set = new_alias_set ();
25469 /* This returns nonzero if the current function uses the TOC. This is
25470 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
25471 is generated by the ABI_V4 load_toc_* patterns.
25472 Return 2 instead of 1 if the load_toc_* pattern is in the function
25473 partition that doesn't start the function. */
25481 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
25485 rtx pat = PATTERN (insn);
25488 if (GET_CODE (pat) == PARALLEL)
25489 for (i = 0; i < XVECLEN (pat, 0); i++)
25491 rtx sub = XVECEXP (pat, 0, i);
25492 if (GET_CODE (sub) == USE)
25494 sub = XEXP (sub, 0);
25495 if (GET_CODE (sub) == UNSPEC
25496 && XINT (sub, 1) == UNSPEC_TOC)
25501 else if (crtl->has_bb_partition
25503 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
25511 create_TOC_reference (rtx symbol, rtx largetoc_reg)
25513 rtx tocrel, tocreg, hi;
25515 if (TARGET_DEBUG_ADDR)
25517 if (GET_CODE (symbol) == SYMBOL_REF)
25518 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25522 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
25523 GET_RTX_NAME (GET_CODE (symbol)));
25524 debug_rtx (symbol);
25528 if (!can_create_pseudo_p ())
25529 df_set_regs_ever_live (TOC_REGISTER, true);
25531 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
25532 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
25533 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
25536 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
25537 if (largetoc_reg != NULL)
25539 emit_move_insn (largetoc_reg, hi);
25542 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
25545 /* Issue assembly directives that create a reference to the given DWARF
25546 FRAME_TABLE_LABEL from the current function section. */
25548 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
25550 fprintf (asm_out_file, "\t.ref %s\n",
25551 (* targetm.strip_name_encoding) (frame_table_label));
25554 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25555 and the change to the stack pointer. */
25558 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
25565 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25566 if (hard_frame_needed)
25567 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
25568 if (!(REGNO (fp) == STACK_POINTER_REGNUM
25569 || (hard_frame_needed
25570 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
25573 p = rtvec_alloc (i);
25576 rtx mem = gen_frame_mem (BLKmode, regs[i]);
25577 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
25580 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
25583 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
25584 and set the appropriate attributes for the generated insn. Return the
25585 first insn which adjusts the stack pointer or the last insn before
25586 the stack adjustment loop.
25588 SIZE_INT is used to create the CFI note for the allocation.
25590 SIZE_RTX is an rtx containing the size of the adjustment. Note that
25591 since stacks grow to lower addresses its runtime value is -SIZE_INT.
25593 ORIG_SP contains the backchain value that must be stored at *sp. */
25596 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
25600 rtx size_rtx = GEN_INT (-size_int);
25601 if (size_int > 32767)
25603 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25604 /* Need a note here so that try_split doesn't get confused. */
25605 if (get_last_insn () == NULL_RTX)
25606 emit_note (NOTE_INSN_DELETED);
25607 insn = emit_move_insn (tmp_reg, size_rtx);
25608 try_split (PATTERN (insn), insn, 0);
25609 size_rtx = tmp_reg;
25612 if (Pmode == SImode)
25613 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
25618 insn = emit_insn (gen_movdi_di_update_stack (stack_pointer_rtx,
25622 rtx par = PATTERN (insn);
25623 gcc_assert (GET_CODE (par) == PARALLEL);
25624 rtx set = XVECEXP (par, 0, 0);
25625 gcc_assert (GET_CODE (set) == SET);
25626 rtx mem = SET_DEST (set);
25627 gcc_assert (MEM_P (mem));
25628 MEM_NOTRAP_P (mem) = 1;
25629 set_mem_alias_set (mem, get_frame_alias_set ());
25631 RTX_FRAME_RELATED_P (insn) = 1;
25632 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25633 gen_rtx_SET (stack_pointer_rtx,
25634 gen_rtx_PLUS (Pmode,
25636 GEN_INT (-size_int))));
25638 /* Emit a blockage to ensure the allocation/probing insns are
25639 not optimized, combined, removed, etc. Add REG_STACK_CHECK
25640 note for similar reasons. */
25641 if (flag_stack_clash_protection)
25643 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
25644 emit_insn (gen_blockage ());
25650 static HOST_WIDE_INT
25651 get_stack_clash_protection_probe_interval (void)
25653 return (HOST_WIDE_INT_1U
25654 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
25657 static HOST_WIDE_INT
25658 get_stack_clash_protection_guard_size (void)
25660 return (HOST_WIDE_INT_1U
25661 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
25664 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25665 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25667 COPY_REG, if non-null, should contain a copy of the original
25668 stack pointer at exit from this function.
25670 This is subtly different than the Ada probing in that it tries hard to
25671 prevent attacks that jump the stack guard. Thus it is never allowed to
25672 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25673 space without a suitable probe. */
25675 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
25678 rtx orig_sp = copy_reg;
25680 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25682 /* Round the size down to a multiple of PROBE_INTERVAL. */
25683 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
25685 /* If explicitly requested,
25686 or the rounded size is not the same as the original size
25687 or the the rounded size is greater than a page,
25688 then we will need a copy of the original stack pointer. */
25689 if (rounded_size != orig_size
25690 || rounded_size > probe_interval
25693 /* If the caller did not request a copy of the incoming stack
25694 pointer, then we use r0 to hold the copy. */
25696 orig_sp = gen_rtx_REG (Pmode, 0);
25697 emit_move_insn (orig_sp, stack_pointer_rtx);
25700 /* There's three cases here.
25702 One is a single probe which is the most common and most efficiently
25703 implemented as it does not have to have a copy of the original
25704 stack pointer if there are no residuals.
25706 Second is unrolled allocation/probes which we use if there's just
25707 a few of them. It needs to save the original stack pointer into a
25708 temporary for use as a source register in the allocation/probe.
25710 Last is a loop. This is the most uncommon case and least efficient. */
25711 rtx_insn *retval = NULL;
25712 if (rounded_size == probe_interval)
25714 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
25716 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25718 else if (rounded_size <= 8 * probe_interval)
25720 /* The ABI requires using the store with update insns to allocate
25721 space and store the backchain into the stack
25723 So we save the current stack pointer into a temporary, then
25724 emit the store-with-update insns to store the saved stack pointer
25725 into the right location in each new page. */
25726 for (int i = 0; i < rounded_size; i += probe_interval)
25729 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
25731 /* Save the first stack adjustment in RETVAL. */
25736 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25740 /* Compute the ending address. */
25742 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
25743 rtx rs = GEN_INT (-rounded_size);
25745 if (add_operand (rs, Pmode))
25746 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
25749 emit_move_insn (end_addr, GEN_INT (-rounded_size));
25750 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
25751 stack_pointer_rtx));
25752 /* Describe the effect of INSN to the CFI engine. */
25753 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25754 gen_rtx_SET (end_addr,
25755 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25758 RTX_FRAME_RELATED_P (insn) = 1;
25760 /* Emit the loop. */
25762 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
25763 stack_pointer_rtx, orig_sp,
25766 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
25767 stack_pointer_rtx, orig_sp,
25769 RTX_FRAME_RELATED_P (retval) = 1;
25770 /* Describe the effect of INSN to the CFI engine. */
25771 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
25772 gen_rtx_SET (stack_pointer_rtx, end_addr));
25774 /* Emit a blockage to ensure the allocation/probing insns are
25775 not optimized, combined, removed, etc. Other cases handle this
25776 within their call to rs6000_emit_allocate_stack_1. */
25777 emit_insn (gen_blockage ());
25779 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
25782 if (orig_size != rounded_size)
25784 /* Allocate (and implicitly probe) any residual space. */
25785 HOST_WIDE_INT residual = orig_size - rounded_size;
25787 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
25789 /* If the residual was the only allocation, then we can return the
25790 allocating insn. */
25798 /* Emit the correct code for allocating stack space, as insns.
25799 If COPY_REG, make sure a copy of the old frame is left there.
25800 The generated code may use hard register 0 as a temporary. */
25803 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
25806 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25807 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25808 rtx todec = gen_int_mode (-size, Pmode);
25810 if (INTVAL (todec) != -size)
25812 warning (0, "stack frame too large");
25813 emit_insn (gen_trap ());
25817 if (crtl->limit_stack)
25819 if (REG_P (stack_limit_rtx)
25820 && REGNO (stack_limit_rtx) > 1
25821 && REGNO (stack_limit_rtx) <= 31)
25824 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25827 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25829 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
25831 && DEFAULT_ABI == ABI_V4
25834 rtx toload = gen_rtx_CONST (VOIDmode,
25835 gen_rtx_PLUS (Pmode,
25839 emit_insn (gen_elf_high (tmp_reg, toload));
25840 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25841 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25845 warning (0, "stack limit expression is not supported");
25848 if (flag_stack_clash_protection)
25850 if (size < get_stack_clash_protection_guard_size ())
25851 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25854 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25857 /* If we asked for a copy with an offset, then we still need add in
25859 if (copy_reg && copy_off)
25860 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25868 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25870 emit_move_insn (copy_reg, stack_reg);
25873 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25874 it now and set the alias set/attributes. The above gen_*_update
25875 calls will generate a PARALLEL with the MEM set being the first
25877 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25881 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25883 #if PROBE_INTERVAL > 32768
25884 #error Cannot use indexed addressing mode for stack probing
25887 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25888 inclusive. These are offsets from the current stack pointer. */
25891 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25893 /* See if we have a constant small number of probes to generate. If so,
25894 that's the easy case. */
25895 if (first + size <= 32768)
25899 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25900 it exceeds SIZE. If only one probe is needed, this will not
25901 generate any code. Then probe at FIRST + SIZE. */
25902 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25903 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25906 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25910 /* Otherwise, do the same as above, but in a loop. Note that we must be
25911 extra careful with variables wrapping around because we might be at
25912 the very top (or the very bottom) of the address space and we have
25913 to be able to handle this case properly; in particular, we use an
25914 equality test for the loop condition. */
25917 HOST_WIDE_INT rounded_size;
25918 rtx r12 = gen_rtx_REG (Pmode, 12);
25919 rtx r0 = gen_rtx_REG (Pmode, 0);
25921 /* Sanity check for the addressing mode we're going to use. */
25922 gcc_assert (first <= 32768);
25924 /* Step 1: round SIZE to the previous multiple of the interval. */
25926 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25929 /* Step 2: compute initial and final value of the loop counter. */
25931 /* TEST_ADDR = SP + FIRST. */
25932 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25935 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25936 if (rounded_size > 32768)
25938 emit_move_insn (r0, GEN_INT (-rounded_size));
25939 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25942 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25946 /* Step 3: the loop
25950 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25953 while (TEST_ADDR != LAST_ADDR)
25955 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25956 until it is equal to ROUNDED_SIZE. */
25959 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25961 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25964 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25965 that SIZE is equal to ROUNDED_SIZE. */
25967 if (size != rounded_size)
25968 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25972 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25973 addresses, not offsets. */
25975 static const char *
25976 output_probe_stack_range_1 (rtx reg1, rtx reg2)
25978 static int labelno = 0;
25982 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25985 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25987 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25989 xops[1] = GEN_INT (-PROBE_INTERVAL);
25990 output_asm_insn ("addi %0,%0,%1", xops);
25992 /* Probe at TEST_ADDR. */
25993 xops[1] = gen_rtx_REG (Pmode, 0);
25994 output_asm_insn ("stw %1,0(%0)", xops);
25996 /* Test if TEST_ADDR == LAST_ADDR. */
25999 output_asm_insn ("cmpd 0,%0,%1", xops);
26001 output_asm_insn ("cmpw 0,%0,%1", xops);
26004 fputs ("\tbne 0,", asm_out_file);
26005 assemble_name_raw (asm_out_file, loop_lab);
26006 fputc ('\n', asm_out_file);
26011 /* This function is called when rs6000_frame_related is processing
26012 SETs within a PARALLEL, and returns whether the REGNO save ought to
26013 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
26014 for out-of-line register save functions, store multiple, and the
26015 Darwin world_save. They may contain registers that don't really
26019 interesting_frame_related_regno (unsigned int regno)
26021 /* Saves apparently of r0 are actually saving LR. It doesn't make
26022 sense to substitute the regno here to test save_reg_p (LR_REGNO).
26023 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
26024 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
26025 as frame related. */
26028 /* If we see CR2 then we are here on a Darwin world save. Saves of
26029 CR2 signify the whole CR is being saved. This is a long-standing
26030 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
26031 that CR needs to be saved. */
26032 if (regno == CR2_REGNO)
26034 /* Omit frame info for any user-defined global regs. If frame info
26035 is supplied for them, frame unwinding will restore a user reg.
26036 Also omit frame info for any reg we don't need to save, as that
26037 bloats frame info and can cause problems with shrink wrapping.
26038 Since global regs won't be seen as needing to be saved, both of
26039 these conditions are covered by save_reg_p. */
26040 return save_reg_p (regno);
26043 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
26044 addresses, not offsets.
26046 REG2 contains the backchain that must be stored into *sp at each allocation.
26048 This is subtly different than the Ada probing above in that it tries hard
26049 to prevent attacks that jump the stack guard. Thus, it is never allowed
26050 to allocate more than PROBE_INTERVAL bytes of stack space without a
26053 static const char *
26054 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
26056 static int labelno = 0;
26060 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
26062 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
26064 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
26066 /* This allocates and probes. */
26069 xops[2] = GEN_INT (-probe_interval);
26071 output_asm_insn ("stdu %1,%2(%0)", xops);
26073 output_asm_insn ("stwu %1,%2(%0)", xops);
26075 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
26079 output_asm_insn ("cmpd 0,%0,%1", xops);
26081 output_asm_insn ("cmpw 0,%0,%1", xops);
26083 fputs ("\tbne 0,", asm_out_file);
26084 assemble_name_raw (asm_out_file, loop_lab);
26085 fputc ('\n', asm_out_file);
26090 /* Wrapper around the output_probe_stack_range routines. */
26092 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
26094 if (flag_stack_clash_protection)
26095 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
26097 return output_probe_stack_range_1 (reg1, reg3);
26100 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
26101 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
26102 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
26103 deduce these equivalences by itself so it wasn't necessary to hold
26104 its hand so much. Don't be tempted to always supply d2_f_d_e with
26105 the actual cfa register, ie. r31 when we are using a hard frame
26106 pointer. That fails when saving regs off r1, and sched moves the
26107 r31 setup past the reg saves. */
26110 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
26111 rtx reg2, rtx repl2)
26115 if (REGNO (reg) == STACK_POINTER_REGNUM)
26117 gcc_checking_assert (val == 0);
26121 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
26124 rtx pat = PATTERN (insn);
26125 if (!repl && !reg2)
26127 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
26128 if (GET_CODE (pat) == PARALLEL)
26129 for (int i = 0; i < XVECLEN (pat, 0); i++)
26130 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
26132 rtx set = XVECEXP (pat, 0, i);
26134 if (!REG_P (SET_SRC (set))
26135 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
26136 RTX_FRAME_RELATED_P (set) = 1;
26138 RTX_FRAME_RELATED_P (insn) = 1;
26142 /* We expect that 'pat' is either a SET or a PARALLEL containing
26143 SETs (and possibly other stuff). In a PARALLEL, all the SETs
26144 are important so they all have to be marked RTX_FRAME_RELATED_P.
26145 Call simplify_replace_rtx on the SETs rather than the whole insn
26146 so as to leave the other stuff alone (for example USE of r12). */
26148 set_used_flags (pat);
26149 if (GET_CODE (pat) == SET)
26152 pat = simplify_replace_rtx (pat, reg, repl);
26154 pat = simplify_replace_rtx (pat, reg2, repl2);
26156 else if (GET_CODE (pat) == PARALLEL)
26158 pat = shallow_copy_rtx (pat);
26159 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
26161 for (int i = 0; i < XVECLEN (pat, 0); i++)
26162 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
26164 rtx set = XVECEXP (pat, 0, i);
26167 set = simplify_replace_rtx (set, reg, repl);
26169 set = simplify_replace_rtx (set, reg2, repl2);
26170 XVECEXP (pat, 0, i) = set;
26172 if (!REG_P (SET_SRC (set))
26173 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
26174 RTX_FRAME_RELATED_P (set) = 1;
26178 gcc_unreachable ();
26180 RTX_FRAME_RELATED_P (insn) = 1;
26181 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
26186 /* Returns an insn that has a vrsave set operation with the
26187 appropriate CLOBBERs. */
26190 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
26193 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
26194 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26197 = gen_rtx_SET (vrsave,
26198 gen_rtx_UNSPEC_VOLATILE (SImode,
26199 gen_rtvec (2, reg, vrsave),
26200 UNSPECV_SET_VRSAVE));
26204 /* We need to clobber the registers in the mask so the scheduler
26205 does not move sets to VRSAVE before sets of AltiVec registers.
26207 However, if the function receives nonlocal gotos, reload will set
26208 all call saved registers live. We will end up with:
26210 (set (reg 999) (mem))
26211 (parallel [ (set (reg vrsave) (unspec blah))
26212 (clobber (reg 999))])
26214 The clobber will cause the store into reg 999 to be dead, and
26215 flow will attempt to delete an epilogue insn. In this case, we
26216 need an unspec use/set of the register. */
26218 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
26219 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
26221 if (!epiloguep || call_used_regs [i])
26222 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
26223 gen_rtx_REG (V4SImode, i));
26226 rtx reg = gen_rtx_REG (V4SImode, i);
26229 = gen_rtx_SET (reg,
26230 gen_rtx_UNSPEC (V4SImode,
26231 gen_rtvec (1, reg), 27));
26235 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
26237 for (i = 0; i < nclobs; ++i)
26238 XVECEXP (insn, 0, i) = clobs[i];
26244 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
26248 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
26249 mem = gen_frame_mem (GET_MODE (reg), addr);
26250 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
26254 gen_frame_load (rtx reg, rtx frame_reg, int offset)
26256 return gen_frame_set (reg, frame_reg, offset, false);
26260 gen_frame_store (rtx reg, rtx frame_reg, int offset)
26262 return gen_frame_set (reg, frame_reg, offset, true);
26265 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
26266 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
26269 emit_frame_save (rtx frame_reg, machine_mode mode,
26270 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
26274 /* Some cases that need register indexed addressing. */
26275 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
26276 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
26278 reg = gen_rtx_REG (mode, regno);
26279 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
26280 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
26281 NULL_RTX, NULL_RTX);
26284 /* Emit an offset memory reference suitable for a frame store, while
26285 converting to a valid addressing mode. */
26288 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
26290 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
26293 #ifndef TARGET_FIX_AND_CONTINUE
26294 #define TARGET_FIX_AND_CONTINUE 0
26297 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
26298 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
26299 #define LAST_SAVRES_REGISTER 31
26300 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
26311 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
26313 /* Temporary holding space for an out-of-line register save/restore
26315 static char savres_routine_name[30];
26317 /* Return the name for an out-of-line register save/restore routine.
26318 We are saving/restoring GPRs if GPR is true. */
26321 rs6000_savres_routine_name (int regno, int sel)
26323 const char *prefix = "";
26324 const char *suffix = "";
26326 /* Different targets are supposed to define
26327 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
26328 routine name could be defined with:
26330 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
26332 This is a nice idea in practice, but in reality, things are
26333 complicated in several ways:
26335 - ELF targets have save/restore routines for GPRs.
26337 - PPC64 ELF targets have routines for save/restore of GPRs that
26338 differ in what they do with the link register, so having a set
26339 prefix doesn't work. (We only use one of the save routines at
26340 the moment, though.)
26342 - PPC32 elf targets have "exit" versions of the restore routines
26343 that restore the link register and can save some extra space.
26344 These require an extra suffix. (There are also "tail" versions
26345 of the restore routines and "GOT" versions of the save routines,
26346 but we don't generate those at present. Same problems apply,
26349 We deal with all this by synthesizing our own prefix/suffix and
26350 using that for the simple sprintf call shown above. */
26351 if (DEFAULT_ABI == ABI_V4)
26356 if ((sel & SAVRES_REG) == SAVRES_GPR)
26357 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
26358 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26359 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
26360 else if ((sel & SAVRES_REG) == SAVRES_VR)
26361 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
26365 if ((sel & SAVRES_LR))
26368 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26370 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
26371 /* No out-of-line save/restore routines for GPRs on AIX. */
26372 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
26376 if ((sel & SAVRES_REG) == SAVRES_GPR)
26377 prefix = ((sel & SAVRES_SAVE)
26378 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
26379 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
26380 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26382 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
26383 if ((sel & SAVRES_LR))
26384 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
26388 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
26389 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
26392 else if ((sel & SAVRES_REG) == SAVRES_VR)
26393 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
26398 if (DEFAULT_ABI == ABI_DARWIN)
26400 /* The Darwin approach is (slightly) different, in order to be
26401 compatible with code generated by the system toolchain. There is a
26402 single symbol for the start of save sequence, and the code here
26403 embeds an offset into that code on the basis of the first register
26405 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
26406 if ((sel & SAVRES_REG) == SAVRES_GPR)
26407 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
26408 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
26409 (regno - 13) * 4, prefix, regno);
26410 else if ((sel & SAVRES_REG) == SAVRES_FPR)
26411 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
26412 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
26413 else if ((sel & SAVRES_REG) == SAVRES_VR)
26414 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
26415 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
26420 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
26422 return savres_routine_name;
26425 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
26426 We are saving/restoring GPRs if GPR is true. */
26429 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
26431 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
26432 ? info->first_gp_reg_save
26433 : (sel & SAVRES_REG) == SAVRES_FPR
26434 ? info->first_fp_reg_save - 32
26435 : (sel & SAVRES_REG) == SAVRES_VR
26436 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
26441 /* Don't generate bogus routine names. */
26442 gcc_assert (FIRST_SAVRES_REGISTER <= regno
26443 && regno <= LAST_SAVRES_REGISTER
26444 && select >= 0 && select <= 12);
26446 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
26452 name = rs6000_savres_routine_name (regno, sel);
26454 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
26455 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
26456 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
26462 /* Emit a sequence of insns, including a stack tie if needed, for
26463 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
26464 reset the stack pointer, but move the base of the frame into
26465 reg UPDT_REGNO for use by out-of-line register restore routines. */
26468 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
26469 unsigned updt_regno)
26471 /* If there is nothing to do, don't do anything. */
26472 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
26475 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
26477 /* This blockage is needed so that sched doesn't decide to move
26478 the sp change before the register restores. */
26479 if (DEFAULT_ABI == ABI_V4)
26480 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
26481 GEN_INT (frame_off)));
26483 /* If we are restoring registers out-of-line, we will be using the
26484 "exit" variants of the restore routines, which will reset the
26485 stack for us. But we do need to point updt_reg into the
26486 right place for those routines. */
26487 if (frame_off != 0)
26488 return emit_insn (gen_add3_insn (updt_reg_rtx,
26489 frame_reg_rtx, GEN_INT (frame_off)));
26491 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
26496 /* Return the register number used as a pointer by out-of-line
26497 save/restore functions. */
26499 static inline unsigned
26500 ptr_regno_for_savres (int sel)
26502 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26503 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
26504 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
26507 /* Construct a parallel rtx describing the effect of a call to an
26508 out-of-line register save/restore routine, and emit the insn
26509 or jump_insn as appropriate. */
26512 rs6000_emit_savres_rtx (rs6000_stack_t *info,
26513 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
26514 machine_mode reg_mode, int sel)
26517 int offset, start_reg, end_reg, n_regs, use_reg;
26518 int reg_size = GET_MODE_SIZE (reg_mode);
26525 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26526 ? info->first_gp_reg_save
26527 : (sel & SAVRES_REG) == SAVRES_FPR
26528 ? info->first_fp_reg_save
26529 : (sel & SAVRES_REG) == SAVRES_VR
26530 ? info->first_altivec_reg_save
26532 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26534 : (sel & SAVRES_REG) == SAVRES_FPR
26536 : (sel & SAVRES_REG) == SAVRES_VR
26537 ? LAST_ALTIVEC_REGNO + 1
26539 n_regs = end_reg - start_reg;
26540 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
26541 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
26544 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26545 RTVEC_ELT (p, offset++) = ret_rtx;
26547 RTVEC_ELT (p, offset++)
26548 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
26550 sym = rs6000_savres_routine_sym (info, sel);
26551 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
26553 use_reg = ptr_regno_for_savres (sel);
26554 if ((sel & SAVRES_REG) == SAVRES_VR)
26556 /* Vector regs are saved/restored using [reg+reg] addressing. */
26557 RTVEC_ELT (p, offset++)
26558 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26559 RTVEC_ELT (p, offset++)
26560 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
26563 RTVEC_ELT (p, offset++)
26564 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26566 for (i = 0; i < end_reg - start_reg; i++)
26567 RTVEC_ELT (p, i + offset)
26568 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
26569 frame_reg_rtx, save_area_offset + reg_size * i,
26570 (sel & SAVRES_SAVE) != 0);
26572 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26573 RTVEC_ELT (p, i + offset)
26574 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
26576 par = gen_rtx_PARALLEL (VOIDmode, p);
26578 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26580 insn = emit_jump_insn (par);
26581 JUMP_LABEL (insn) = ret_rtx;
26584 insn = emit_insn (par);
26588 /* Emit prologue code to store CR fields that need to be saved into REG. This
26589 function should only be called when moving the non-volatile CRs to REG, it
26590 is not a general purpose routine to move the entire set of CRs to REG.
26591 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
26595 rs6000_emit_prologue_move_from_cr (rtx reg)
26597 /* Only the ELFv2 ABI allows storing only selected fields. */
26598 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
26600 int i, cr_reg[8], count = 0;
26602 /* Collect CR fields that must be saved. */
26603 for (i = 0; i < 8; i++)
26604 if (save_reg_p (CR0_REGNO + i))
26605 cr_reg[count++] = i;
26607 /* If it's just a single one, use mfcrf. */
26610 rtvec p = rtvec_alloc (1);
26611 rtvec r = rtvec_alloc (2);
26612 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
26613 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
26615 = gen_rtx_SET (reg,
26616 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
26618 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26622 /* ??? It might be better to handle count == 2 / 3 cases here
26623 as well, using logical operations to combine the values. */
26626 emit_insn (gen_prologue_movesi_from_cr (reg));
26629 /* Return whether the split-stack arg pointer (r12) is used. */
26632 split_stack_arg_pointer_used_p (void)
26634 /* If the pseudo holding the arg pointer is no longer a pseudo,
26635 then the arg pointer is used. */
26636 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
26637 && (!REG_P (cfun->machine->split_stack_arg_pointer)
26638 || (REGNO (cfun->machine->split_stack_arg_pointer)
26639 < FIRST_PSEUDO_REGISTER)))
26642 /* Unfortunately we also need to do some code scanning, since
26643 r12 may have been substituted for the pseudo. */
26645 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
26646 FOR_BB_INSNS (bb, insn)
26647 if (NONDEBUG_INSN_P (insn))
26649 /* A call destroys r12. */
26654 FOR_EACH_INSN_USE (use, insn)
26656 rtx x = DF_REF_REG (use);
26657 if (REG_P (x) && REGNO (x) == 12)
26661 FOR_EACH_INSN_DEF (def, insn)
26663 rtx x = DF_REF_REG (def);
26664 if (REG_P (x) && REGNO (x) == 12)
26668 return bitmap_bit_p (DF_LR_OUT (bb), 12);
26671 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26674 rs6000_global_entry_point_needed_p (void)
26676 /* Only needed for the ELFv2 ABI. */
26677 if (DEFAULT_ABI != ABI_ELFv2)
26680 /* With -msingle-pic-base, we assume the whole program shares the same
26681 TOC, so no global entry point prologues are needed anywhere. */
26682 if (TARGET_SINGLE_PIC_BASE)
26685 /* Ensure we have a global entry point for thunks. ??? We could
26686 avoid that if the target routine doesn't need a global entry point,
26687 but we do not know whether this is the case at this point. */
26688 if (cfun->is_thunk)
26691 /* For regular functions, rs6000_emit_prologue sets this flag if the
26692 routine ever uses the TOC pointer. */
26693 return cfun->machine->r2_setup_needed;
26696 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26698 rs6000_get_separate_components (void)
26700 rs6000_stack_t *info = rs6000_stack_info ();
26702 if (WORLD_SAVE_P (info))
26705 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
26706 && !(info->savres_strategy & REST_MULTIPLE));
26708 /* Component 0 is the save/restore of LR (done via GPR0).
26709 Component 2 is the save of the TOC (GPR2).
26710 Components 13..31 are the save/restore of GPR13..GPR31.
26711 Components 46..63 are the save/restore of FPR14..FPR31. */
26713 cfun->machine->n_components = 64;
26715 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26716 bitmap_clear (components);
26718 int reg_size = TARGET_32BIT ? 4 : 8;
26719 int fp_reg_size = 8;
26721 /* The GPRs we need saved to the frame. */
26722 if ((info->savres_strategy & SAVE_INLINE_GPRS)
26723 && (info->savres_strategy & REST_INLINE_GPRS))
26725 int offset = info->gp_save_offset;
26727 offset += info->total_size;
26729 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26731 if (IN_RANGE (offset, -0x8000, 0x7fff)
26732 && save_reg_p (regno))
26733 bitmap_set_bit (components, regno);
26735 offset += reg_size;
26739 /* Don't mess with the hard frame pointer. */
26740 if (frame_pointer_needed)
26741 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
26743 /* Don't mess with the fixed TOC register. */
26744 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
26745 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
26746 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
26747 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
26749 /* The FPRs we need saved to the frame. */
26750 if ((info->savres_strategy & SAVE_INLINE_FPRS)
26751 && (info->savres_strategy & REST_INLINE_FPRS))
26753 int offset = info->fp_save_offset;
26755 offset += info->total_size;
26757 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26759 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
26760 bitmap_set_bit (components, regno);
26762 offset += fp_reg_size;
26766 /* Optimize LR save and restore if we can. This is component 0. Any
26767 out-of-line register save/restore routines need LR. */
26768 if (info->lr_save_p
26769 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
26770 && (info->savres_strategy & SAVE_INLINE_GPRS)
26771 && (info->savres_strategy & REST_INLINE_GPRS)
26772 && (info->savres_strategy & SAVE_INLINE_FPRS)
26773 && (info->savres_strategy & REST_INLINE_FPRS)
26774 && (info->savres_strategy & SAVE_INLINE_VRS)
26775 && (info->savres_strategy & REST_INLINE_VRS))
26777 int offset = info->lr_save_offset;
26779 offset += info->total_size;
26780 if (IN_RANGE (offset, -0x8000, 0x7fff))
26781 bitmap_set_bit (components, 0);
26784 /* Optimize saving the TOC. This is component 2. */
26785 if (cfun->machine->save_toc_in_prologue)
26786 bitmap_set_bit (components, 2);
26791 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26793 rs6000_components_for_bb (basic_block bb)
26795 rs6000_stack_t *info = rs6000_stack_info ();
26797 bitmap in = DF_LIVE_IN (bb);
26798 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
26799 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
26801 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26802 bitmap_clear (components);
26804 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26807 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26808 if (bitmap_bit_p (in, regno)
26809 || bitmap_bit_p (gen, regno)
26810 || bitmap_bit_p (kill, regno))
26811 bitmap_set_bit (components, regno);
26814 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26815 if (bitmap_bit_p (in, regno)
26816 || bitmap_bit_p (gen, regno)
26817 || bitmap_bit_p (kill, regno))
26818 bitmap_set_bit (components, regno);
26820 /* The link register. */
26821 if (bitmap_bit_p (in, LR_REGNO)
26822 || bitmap_bit_p (gen, LR_REGNO)
26823 || bitmap_bit_p (kill, LR_REGNO))
26824 bitmap_set_bit (components, 0);
26826 /* The TOC save. */
26827 if (bitmap_bit_p (in, TOC_REGNUM)
26828 || bitmap_bit_p (gen, TOC_REGNUM)
26829 || bitmap_bit_p (kill, TOC_REGNUM))
26830 bitmap_set_bit (components, 2);
26835 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26837 rs6000_disqualify_components (sbitmap components, edge e,
26838 sbitmap edge_components, bool /*is_prologue*/)
26840 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26841 live where we want to place that code. */
26842 if (bitmap_bit_p (edge_components, 0)
26843 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26846 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26847 "on entry to bb %d\n", e->dest->index);
26848 bitmap_clear_bit (components, 0);
26852 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26854 rs6000_emit_prologue_components (sbitmap components)
26856 rs6000_stack_t *info = rs6000_stack_info ();
26857 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26858 ? HARD_FRAME_POINTER_REGNUM
26859 : STACK_POINTER_REGNUM);
26861 machine_mode reg_mode = Pmode;
26862 int reg_size = TARGET_32BIT ? 4 : 8;
26863 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
26865 int fp_reg_size = 8;
26867 /* Prologue for LR. */
26868 if (bitmap_bit_p (components, 0))
26870 rtx reg = gen_rtx_REG (reg_mode, 0);
26871 rtx_insn *insn = emit_move_insn (reg, gen_rtx_REG (reg_mode, LR_REGNO));
26872 RTX_FRAME_RELATED_P (insn) = 1;
26873 add_reg_note (insn, REG_CFA_REGISTER, NULL);
26875 int offset = info->lr_save_offset;
26877 offset += info->total_size;
26879 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26880 RTX_FRAME_RELATED_P (insn) = 1;
26881 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26882 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26883 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26886 /* Prologue for TOC. */
26887 if (bitmap_bit_p (components, 2))
26889 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26890 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26891 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26894 /* Prologue for the GPRs. */
26895 int offset = info->gp_save_offset;
26897 offset += info->total_size;
26899 for (int i = info->first_gp_reg_save; i < 32; i++)
26901 if (bitmap_bit_p (components, i))
26903 rtx reg = gen_rtx_REG (reg_mode, i);
26904 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26905 RTX_FRAME_RELATED_P (insn) = 1;
26906 rtx set = copy_rtx (single_set (insn));
26907 add_reg_note (insn, REG_CFA_OFFSET, set);
26910 offset += reg_size;
26913 /* Prologue for the FPRs. */
26914 offset = info->fp_save_offset;
26916 offset += info->total_size;
26918 for (int i = info->first_fp_reg_save; i < 64; i++)
26920 if (bitmap_bit_p (components, i))
26922 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26923 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26924 RTX_FRAME_RELATED_P (insn) = 1;
26925 rtx set = copy_rtx (single_set (insn));
26926 add_reg_note (insn, REG_CFA_OFFSET, set);
26929 offset += fp_reg_size;
26933 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26935 rs6000_emit_epilogue_components (sbitmap components)
26937 rs6000_stack_t *info = rs6000_stack_info ();
26938 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26939 ? HARD_FRAME_POINTER_REGNUM
26940 : STACK_POINTER_REGNUM);
26942 machine_mode reg_mode = Pmode;
26943 int reg_size = TARGET_32BIT ? 4 : 8;
26945 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
26947 int fp_reg_size = 8;
26949 /* Epilogue for the FPRs. */
26950 int offset = info->fp_save_offset;
26952 offset += info->total_size;
26954 for (int i = info->first_fp_reg_save; i < 64; i++)
26956 if (bitmap_bit_p (components, i))
26958 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26959 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26960 RTX_FRAME_RELATED_P (insn) = 1;
26961 add_reg_note (insn, REG_CFA_RESTORE, reg);
26964 offset += fp_reg_size;
26967 /* Epilogue for the GPRs. */
26968 offset = info->gp_save_offset;
26970 offset += info->total_size;
26972 for (int i = info->first_gp_reg_save; i < 32; i++)
26974 if (bitmap_bit_p (components, i))
26976 rtx reg = gen_rtx_REG (reg_mode, i);
26977 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26978 RTX_FRAME_RELATED_P (insn) = 1;
26979 add_reg_note (insn, REG_CFA_RESTORE, reg);
26982 offset += reg_size;
26985 /* Epilogue for LR. */
26986 if (bitmap_bit_p (components, 0))
26988 int offset = info->lr_save_offset;
26990 offset += info->total_size;
26992 rtx reg = gen_rtx_REG (reg_mode, 0);
26993 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26995 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
26996 insn = emit_move_insn (lr, reg);
26997 RTX_FRAME_RELATED_P (insn) = 1;
26998 add_reg_note (insn, REG_CFA_RESTORE, lr);
27002 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
27004 rs6000_set_handled_components (sbitmap components)
27006 rs6000_stack_t *info = rs6000_stack_info ();
27008 for (int i = info->first_gp_reg_save; i < 32; i++)
27009 if (bitmap_bit_p (components, i))
27010 cfun->machine->gpr_is_wrapped_separately[i] = true;
27012 for (int i = info->first_fp_reg_save; i < 64; i++)
27013 if (bitmap_bit_p (components, i))
27014 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
27016 if (bitmap_bit_p (components, 0))
27017 cfun->machine->lr_is_wrapped_separately = true;
27019 if (bitmap_bit_p (components, 2))
27020 cfun->machine->toc_is_wrapped_separately = true;
27023 /* VRSAVE is a bit vector representing which AltiVec registers
27024 are used. The OS uses this to determine which vector
27025 registers to save on a context switch. We need to save
27026 VRSAVE on the stack frame, add whatever AltiVec registers we
27027 used in this function, and do the corresponding magic in the
27030 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
27031 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
27033 /* Get VRSAVE into a GPR. */
27034 rtx reg = gen_rtx_REG (SImode, save_regno);
27035 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
27037 emit_insn (gen_get_vrsave_internal (reg));
27039 emit_insn (gen_rtx_SET (reg, vrsave));
27042 int offset = info->vrsave_save_offset + frame_off;
27043 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
27045 /* Include the registers in the mask. */
27046 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
27048 emit_insn (generate_set_vrsave (reg, info, 0));
27051 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
27052 called, it left the arg pointer to the old stack in r29. Otherwise, the
27053 arg pointer is the top of the current frame. */
27055 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
27056 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
27058 cfun->machine->split_stack_argp_used = true;
27062 rtx r12 = gen_rtx_REG (Pmode, 12);
27063 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
27064 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
27065 emit_insn_before (set_r12, sp_adjust);
27067 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
27069 rtx r12 = gen_rtx_REG (Pmode, 12);
27070 if (frame_off == 0)
27071 emit_move_insn (r12, frame_reg_rtx);
27073 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
27078 rtx r12 = gen_rtx_REG (Pmode, 12);
27079 rtx r29 = gen_rtx_REG (Pmode, 29);
27080 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
27081 rtx not_more = gen_label_rtx ();
27084 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27085 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
27086 gen_rtx_LABEL_REF (VOIDmode, not_more),
27088 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27089 JUMP_LABEL (jump) = not_more;
27090 LABEL_NUSES (not_more) += 1;
27091 emit_move_insn (r12, r29);
27092 emit_label (not_more);
27096 /* Emit function prologue as insns. */
27099 rs6000_emit_prologue (void)
27101 rs6000_stack_t *info = rs6000_stack_info ();
27102 machine_mode reg_mode = Pmode;
27103 int reg_size = TARGET_32BIT ? 4 : 8;
27104 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
27106 int fp_reg_size = 8;
27107 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
27108 rtx frame_reg_rtx = sp_reg_rtx;
27109 unsigned int cr_save_regno;
27110 rtx cr_save_rtx = NULL_RTX;
27113 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
27114 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
27115 && call_used_regs[STATIC_CHAIN_REGNUM]);
27116 int using_split_stack = (flag_split_stack
27117 && (lookup_attribute ("no_split_stack",
27118 DECL_ATTRIBUTES (cfun->decl))
27121 /* Offset to top of frame for frame_reg and sp respectively. */
27122 HOST_WIDE_INT frame_off = 0;
27123 HOST_WIDE_INT sp_off = 0;
27124 /* sp_adjust is the stack adjusting instruction, tracked so that the
27125 insn setting up the split-stack arg pointer can be emitted just
27126 prior to it, when r12 is not used here for other purposes. */
27127 rtx_insn *sp_adjust = 0;
27130 /* Track and check usage of r0, r11, r12. */
27131 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
27132 #define START_USE(R) do \
27134 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27135 reg_inuse |= 1 << (R); \
27137 #define END_USE(R) do \
27139 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
27140 reg_inuse &= ~(1 << (R)); \
27142 #define NOT_INUSE(R) do \
27144 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27147 #define START_USE(R) do {} while (0)
27148 #define END_USE(R) do {} while (0)
27149 #define NOT_INUSE(R) do {} while (0)
27152 if (DEFAULT_ABI == ABI_ELFv2
27153 && !TARGET_SINGLE_PIC_BASE)
27155 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
27157 /* With -mminimal-toc we may generate an extra use of r2 below. */
27158 if (TARGET_TOC && TARGET_MINIMAL_TOC
27159 && !constant_pool_empty_p ())
27160 cfun->machine->r2_setup_needed = true;
27164 if (flag_stack_usage_info)
27165 current_function_static_stack_size = info->total_size;
27167 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
27169 HOST_WIDE_INT size = info->total_size;
27171 if (crtl->is_leaf && !cfun->calls_alloca)
27173 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
27174 rs6000_emit_probe_stack_range (get_stack_check_protect (),
27175 size - get_stack_check_protect ());
27178 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
27181 if (TARGET_FIX_AND_CONTINUE)
27183 /* gdb on darwin arranges to forward a function from the old
27184 address by modifying the first 5 instructions of the function
27185 to branch to the overriding function. This is necessary to
27186 permit function pointers that point to the old function to
27187 actually forward to the new function. */
27188 emit_insn (gen_nop ());
27189 emit_insn (gen_nop ());
27190 emit_insn (gen_nop ());
27191 emit_insn (gen_nop ());
27192 emit_insn (gen_nop ());
27195 /* Handle world saves specially here. */
27196 if (WORLD_SAVE_P (info))
27203 /* save_world expects lr in r0. */
27204 reg0 = gen_rtx_REG (Pmode, 0);
27205 if (info->lr_save_p)
27207 insn = emit_move_insn (reg0,
27208 gen_rtx_REG (Pmode, LR_REGNO));
27209 RTX_FRAME_RELATED_P (insn) = 1;
27212 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
27213 assumptions about the offsets of various bits of the stack
27215 gcc_assert (info->gp_save_offset == -220
27216 && info->fp_save_offset == -144
27217 && info->lr_save_offset == 8
27218 && info->cr_save_offset == 4
27221 && (!crtl->calls_eh_return
27222 || info->ehrd_offset == -432)
27223 && info->vrsave_save_offset == -224
27224 && info->altivec_save_offset == -416);
27226 treg = gen_rtx_REG (SImode, 11);
27227 emit_move_insn (treg, GEN_INT (-info->total_size));
27229 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
27230 in R11. It also clobbers R12, so beware! */
27232 /* Preserve CR2 for save_world prologues */
27234 sz += 32 - info->first_gp_reg_save;
27235 sz += 64 - info->first_fp_reg_save;
27236 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
27237 p = rtvec_alloc (sz);
27239 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
27240 gen_rtx_REG (SImode,
27242 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
27243 gen_rtx_SYMBOL_REF (Pmode,
27245 /* We do floats first so that the instruction pattern matches
27247 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
27249 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
27251 info->first_fp_reg_save + i),
27253 info->fp_save_offset + frame_off + 8 * i);
27254 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
27256 = gen_frame_store (gen_rtx_REG (V4SImode,
27257 info->first_altivec_reg_save + i),
27259 info->altivec_save_offset + frame_off + 16 * i);
27260 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27262 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
27264 info->gp_save_offset + frame_off + reg_size * i);
27266 /* CR register traditionally saved as CR2. */
27268 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
27269 frame_reg_rtx, info->cr_save_offset + frame_off);
27270 /* Explain about use of R0. */
27271 if (info->lr_save_p)
27273 = gen_frame_store (reg0,
27274 frame_reg_rtx, info->lr_save_offset + frame_off);
27275 /* Explain what happens to the stack pointer. */
27277 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
27278 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
27281 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27282 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27283 treg, GEN_INT (-info->total_size));
27284 sp_off = frame_off = info->total_size;
27287 strategy = info->savres_strategy;
27289 /* For V.4, update stack before we do any saving and set back pointer. */
27290 if (! WORLD_SAVE_P (info)
27292 && (DEFAULT_ABI == ABI_V4
27293 || crtl->calls_eh_return))
27295 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
27296 || !(strategy & SAVE_INLINE_GPRS)
27297 || !(strategy & SAVE_INLINE_VRS));
27298 int ptr_regno = -1;
27299 rtx ptr_reg = NULL_RTX;
27302 if (info->total_size < 32767)
27303 frame_off = info->total_size;
27306 else if (info->cr_save_p
27308 || info->first_fp_reg_save < 64
27309 || info->first_gp_reg_save < 32
27310 || info->altivec_size != 0
27311 || info->vrsave_size != 0
27312 || crtl->calls_eh_return)
27316 /* The prologue won't be saving any regs so there is no need
27317 to set up a frame register to access any frame save area.
27318 We also won't be using frame_off anywhere below, but set
27319 the correct value anyway to protect against future
27320 changes to this function. */
27321 frame_off = info->total_size;
27323 if (ptr_regno != -1)
27325 /* Set up the frame offset to that needed by the first
27326 out-of-line save function. */
27327 START_USE (ptr_regno);
27328 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27329 frame_reg_rtx = ptr_reg;
27330 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
27331 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
27332 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
27333 ptr_off = info->gp_save_offset + info->gp_size;
27334 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
27335 ptr_off = info->altivec_save_offset + info->altivec_size;
27336 frame_off = -ptr_off;
27338 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27340 if (REGNO (frame_reg_rtx) == 12)
27342 sp_off = info->total_size;
27343 if (frame_reg_rtx != sp_reg_rtx)
27344 rs6000_emit_stack_tie (frame_reg_rtx, false);
27347 /* If we use the link register, get it into r0. */
27348 if (!WORLD_SAVE_P (info) && info->lr_save_p
27349 && !cfun->machine->lr_is_wrapped_separately)
27351 rtx addr, reg, mem;
27353 reg = gen_rtx_REG (Pmode, 0);
27355 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
27356 RTX_FRAME_RELATED_P (insn) = 1;
27358 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
27359 | SAVE_NOINLINE_FPRS_SAVES_LR)))
27361 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27362 GEN_INT (info->lr_save_offset + frame_off));
27363 mem = gen_rtx_MEM (Pmode, addr);
27364 /* This should not be of rs6000_sr_alias_set, because of
27365 __builtin_return_address. */
27367 insn = emit_move_insn (mem, reg);
27368 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27369 NULL_RTX, NULL_RTX);
27374 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
27375 r12 will be needed by out-of-line gpr restore. */
27376 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27377 && !(strategy & (SAVE_INLINE_GPRS
27378 | SAVE_NOINLINE_GPRS_SAVES_LR))
27380 if (!WORLD_SAVE_P (info)
27382 && REGNO (frame_reg_rtx) != cr_save_regno
27383 && !(using_static_chain_p && cr_save_regno == 11)
27384 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
27386 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
27387 START_USE (cr_save_regno);
27388 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27391 /* Do any required saving of fpr's. If only one or two to save, do
27392 it ourselves. Otherwise, call function. */
27393 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
27395 int offset = info->fp_save_offset + frame_off;
27396 for (int i = info->first_fp_reg_save; i < 64; i++)
27399 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
27400 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
27401 sp_off - frame_off);
27403 offset += fp_reg_size;
27406 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
27408 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27409 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27410 unsigned ptr_regno = ptr_regno_for_savres (sel);
27411 rtx ptr_reg = frame_reg_rtx;
27413 if (REGNO (frame_reg_rtx) == ptr_regno)
27414 gcc_checking_assert (frame_off == 0);
27417 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27418 NOT_INUSE (ptr_regno);
27419 emit_insn (gen_add3_insn (ptr_reg,
27420 frame_reg_rtx, GEN_INT (frame_off)));
27422 insn = rs6000_emit_savres_rtx (info, ptr_reg,
27423 info->fp_save_offset,
27424 info->lr_save_offset,
27426 rs6000_frame_related (insn, ptr_reg, sp_off,
27427 NULL_RTX, NULL_RTX);
27432 /* Save GPRs. This is done as a PARALLEL if we are using
27433 the store-multiple instructions. */
27434 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
27436 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
27437 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
27438 unsigned ptr_regno = ptr_regno_for_savres (sel);
27439 rtx ptr_reg = frame_reg_rtx;
27440 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
27441 int end_save = info->gp_save_offset + info->gp_size;
27444 if (ptr_regno == 12)
27447 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27449 /* Need to adjust r11 (r12) if we saved any FPRs. */
27450 if (end_save + frame_off != 0)
27452 rtx offset = GEN_INT (end_save + frame_off);
27455 frame_off = -end_save;
27457 NOT_INUSE (ptr_regno);
27458 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27460 else if (!ptr_set_up)
27462 NOT_INUSE (ptr_regno);
27463 emit_move_insn (ptr_reg, frame_reg_rtx);
27465 ptr_off = -end_save;
27466 insn = rs6000_emit_savres_rtx (info, ptr_reg,
27467 info->gp_save_offset + ptr_off,
27468 info->lr_save_offset + ptr_off,
27470 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
27471 NULL_RTX, NULL_RTX);
27475 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
27479 p = rtvec_alloc (32 - info->first_gp_reg_save);
27480 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27482 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
27484 info->gp_save_offset + frame_off + reg_size * i);
27485 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27486 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27487 NULL_RTX, NULL_RTX);
27489 else if (!WORLD_SAVE_P (info))
27491 int offset = info->gp_save_offset + frame_off;
27492 for (int i = info->first_gp_reg_save; i < 32; i++)
27495 && !cfun->machine->gpr_is_wrapped_separately[i])
27496 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
27497 sp_off - frame_off);
27499 offset += reg_size;
27503 if (crtl->calls_eh_return)
27510 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27511 if (regno == INVALID_REGNUM)
27515 p = rtvec_alloc (i);
27519 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27520 if (regno == INVALID_REGNUM)
27524 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
27526 info->ehrd_offset + sp_off + reg_size * (int) i);
27527 RTVEC_ELT (p, i) = set;
27528 RTX_FRAME_RELATED_P (set) = 1;
27531 insn = emit_insn (gen_blockage ());
27532 RTX_FRAME_RELATED_P (insn) = 1;
27533 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
27536 /* In AIX ABI we need to make sure r2 is really saved. */
27537 if (TARGET_AIX && crtl->calls_eh_return)
27539 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
27540 rtx join_insn, note;
27541 rtx_insn *save_insn;
27542 long toc_restore_insn;
27544 tmp_reg = gen_rtx_REG (Pmode, 11);
27545 tmp_reg_si = gen_rtx_REG (SImode, 11);
27546 if (using_static_chain_p)
27549 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
27553 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
27554 /* Peek at instruction to which this function returns. If it's
27555 restoring r2, then we know we've already saved r2. We can't
27556 unconditionally save r2 because the value we have will already
27557 be updated if we arrived at this function via a plt call or
27558 toc adjusting stub. */
27559 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
27560 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
27561 + RS6000_TOC_SAVE_SLOT);
27562 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
27563 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
27564 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
27565 validate_condition_mode (EQ, CCUNSmode);
27566 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
27567 emit_insn (gen_rtx_SET (compare_result,
27568 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
27569 toc_save_done = gen_label_rtx ();
27570 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27571 gen_rtx_EQ (VOIDmode, compare_result,
27573 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
27575 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27576 JUMP_LABEL (jump) = toc_save_done;
27577 LABEL_NUSES (toc_save_done) += 1;
27579 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
27580 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
27581 sp_off - frame_off);
27583 emit_label (toc_save_done);
27585 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27586 have a CFG that has different saves along different paths.
27587 Move the note to a dummy blockage insn, which describes that
27588 R2 is unconditionally saved after the label. */
27589 /* ??? An alternate representation might be a special insn pattern
27590 containing both the branch and the store. That might let the
27591 code that minimizes the number of DW_CFA_advance opcodes better
27592 freedom in placing the annotations. */
27593 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
27595 remove_note (save_insn, note);
27597 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
27598 copy_rtx (PATTERN (save_insn)), NULL_RTX);
27599 RTX_FRAME_RELATED_P (save_insn) = 0;
27601 join_insn = emit_insn (gen_blockage ());
27602 REG_NOTES (join_insn) = note;
27603 RTX_FRAME_RELATED_P (join_insn) = 1;
27605 if (using_static_chain_p)
27607 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
27614 /* Save CR if we use any that must be preserved. */
27615 if (!WORLD_SAVE_P (info) && info->cr_save_p)
27617 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27618 GEN_INT (info->cr_save_offset + frame_off));
27619 rtx mem = gen_frame_mem (SImode, addr);
27621 /* If we didn't copy cr before, do so now using r0. */
27622 if (cr_save_rtx == NULL_RTX)
27625 cr_save_rtx = gen_rtx_REG (SImode, 0);
27626 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27629 /* Saving CR requires a two-instruction sequence: one instruction
27630 to move the CR to a general-purpose register, and a second
27631 instruction that stores the GPR to memory.
27633 We do not emit any DWARF CFI records for the first of these,
27634 because we cannot properly represent the fact that CR is saved in
27635 a register. One reason is that we cannot express that multiple
27636 CR fields are saved; another reason is that on 64-bit, the size
27637 of the CR register in DWARF (4 bytes) differs from the size of
27638 a general-purpose register.
27640 This means if any intervening instruction were to clobber one of
27641 the call-saved CR fields, we'd have incorrect CFI. To prevent
27642 this from happening, we mark the store to memory as a use of
27643 those CR fields, which prevents any such instruction from being
27644 scheduled in between the two instructions. */
27649 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
27650 for (i = 0; i < 8; i++)
27651 if (save_reg_p (CR0_REGNO + i))
27652 crsave_v[n_crsave++]
27653 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27655 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
27656 gen_rtvec_v (n_crsave, crsave_v)));
27657 END_USE (REGNO (cr_save_rtx));
27659 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27660 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27661 so we need to construct a frame expression manually. */
27662 RTX_FRAME_RELATED_P (insn) = 1;
27664 /* Update address to be stack-pointer relative, like
27665 rs6000_frame_related would do. */
27666 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
27667 GEN_INT (info->cr_save_offset + sp_off));
27668 mem = gen_frame_mem (SImode, addr);
27670 if (DEFAULT_ABI == ABI_ELFv2)
27672 /* In the ELFv2 ABI we generate separate CFI records for each
27673 CR field that was actually saved. They all point to the
27674 same 32-bit stack slot. */
27678 for (i = 0; i < 8; i++)
27679 if (save_reg_p (CR0_REGNO + i))
27682 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
27684 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
27688 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27689 gen_rtx_PARALLEL (VOIDmode,
27690 gen_rtvec_v (n_crframe, crframe)));
27694 /* In other ABIs, by convention, we use a single CR regnum to
27695 represent the fact that all call-saved CR fields are saved.
27696 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27697 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
27698 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
27702 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27703 *separate* slots if the routine calls __builtin_eh_return, so
27704 that they can be independently restored by the unwinder. */
27705 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
27707 int i, cr_off = info->ehcr_offset;
27710 /* ??? We might get better performance by using multiple mfocrf
27712 crsave = gen_rtx_REG (SImode, 0);
27713 emit_insn (gen_prologue_movesi_from_cr (crsave));
27715 for (i = 0; i < 8; i++)
27716 if (!call_used_regs[CR0_REGNO + i])
27718 rtvec p = rtvec_alloc (2);
27720 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
27722 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27724 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27726 RTX_FRAME_RELATED_P (insn) = 1;
27727 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27728 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
27729 sp_reg_rtx, cr_off + sp_off));
27731 cr_off += reg_size;
27735 /* If we are emitting stack probes, but allocate no stack, then
27736 just note that in the dump file. */
27737 if (flag_stack_clash_protection
27740 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
27742 /* Update stack and set back pointer unless this is V.4,
27743 for which it was done previously. */
27744 if (!WORLD_SAVE_P (info) && info->push_p
27745 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
27747 rtx ptr_reg = NULL;
27750 /* If saving altivec regs we need to be able to address all save
27751 locations using a 16-bit offset. */
27752 if ((strategy & SAVE_INLINE_VRS) == 0
27753 || (info->altivec_size != 0
27754 && (info->altivec_save_offset + info->altivec_size - 16
27755 + info->total_size - frame_off) > 32767)
27756 || (info->vrsave_size != 0
27757 && (info->vrsave_save_offset
27758 + info->total_size - frame_off) > 32767))
27760 int sel = SAVRES_SAVE | SAVRES_VR;
27761 unsigned ptr_regno = ptr_regno_for_savres (sel);
27763 if (using_static_chain_p
27764 && ptr_regno == STATIC_CHAIN_REGNUM)
27766 if (REGNO (frame_reg_rtx) != ptr_regno)
27767 START_USE (ptr_regno);
27768 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27769 frame_reg_rtx = ptr_reg;
27770 ptr_off = info->altivec_save_offset + info->altivec_size;
27771 frame_off = -ptr_off;
27773 else if (REGNO (frame_reg_rtx) == 1)
27774 frame_off = info->total_size;
27775 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27777 if (REGNO (frame_reg_rtx) == 12)
27779 sp_off = info->total_size;
27780 if (frame_reg_rtx != sp_reg_rtx)
27781 rs6000_emit_stack_tie (frame_reg_rtx, false);
27784 /* Set frame pointer, if needed. */
27785 if (frame_pointer_needed)
27787 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
27789 RTX_FRAME_RELATED_P (insn) = 1;
27792 /* Save AltiVec registers if needed. Save here because the red zone does
27793 not always include AltiVec registers. */
27794 if (!WORLD_SAVE_P (info)
27795 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
27797 int end_save = info->altivec_save_offset + info->altivec_size;
27799 /* Oddly, the vector save/restore functions point r0 at the end
27800 of the save area, then use r11 or r12 to load offsets for
27801 [reg+reg] addressing. */
27802 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27803 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
27804 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27806 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27808 if (scratch_regno == 12)
27810 if (end_save + frame_off != 0)
27812 rtx offset = GEN_INT (end_save + frame_off);
27814 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27817 emit_move_insn (ptr_reg, frame_reg_rtx);
27819 ptr_off = -end_save;
27820 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27821 info->altivec_save_offset + ptr_off,
27822 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27823 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27824 NULL_RTX, NULL_RTX);
27825 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27827 /* The oddity mentioned above clobbered our frame reg. */
27828 emit_move_insn (frame_reg_rtx, ptr_reg);
27829 frame_off = ptr_off;
27832 else if (!WORLD_SAVE_P (info)
27833 && info->altivec_size != 0)
27837 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27838 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27840 rtx areg, savereg, mem;
27841 HOST_WIDE_INT offset;
27843 offset = (info->altivec_save_offset + frame_off
27844 + 16 * (i - info->first_altivec_reg_save));
27846 savereg = gen_rtx_REG (V4SImode, i);
27848 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27850 mem = gen_frame_mem (V4SImode,
27851 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27852 GEN_INT (offset)));
27853 insn = emit_insn (gen_rtx_SET (mem, savereg));
27859 areg = gen_rtx_REG (Pmode, 0);
27860 emit_move_insn (areg, GEN_INT (offset));
27862 /* AltiVec addressing mode is [reg+reg]. */
27863 mem = gen_frame_mem (V4SImode,
27864 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27866 /* Rather than emitting a generic move, force use of the stvx
27867 instruction, which we always want on ISA 2.07 (power8) systems.
27868 In particular we don't want xxpermdi/stxvd2x for little
27870 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27873 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27874 areg, GEN_INT (offset));
27878 /* VRSAVE is a bit vector representing which AltiVec registers
27879 are used. The OS uses this to determine which vector
27880 registers to save on a context switch. We need to save
27881 VRSAVE on the stack frame, add whatever AltiVec registers we
27882 used in this function, and do the corresponding magic in the
27885 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27887 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27888 be using r12 as frame_reg_rtx and r11 as the static chain
27889 pointer for nested functions. */
27890 int save_regno = 12;
27891 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27892 && !using_static_chain_p)
27894 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27897 if (using_static_chain_p)
27900 NOT_INUSE (save_regno);
27902 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27905 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27906 if (!TARGET_SINGLE_PIC_BASE
27907 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27908 && !constant_pool_empty_p ())
27909 || (DEFAULT_ABI == ABI_V4
27910 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27911 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27913 /* If emit_load_toc_table will use the link register, we need to save
27914 it. We use R12 for this purpose because emit_load_toc_table
27915 can use register 0. This allows us to use a plain 'blr' to return
27916 from the procedure more often. */
27917 int save_LR_around_toc_setup = (TARGET_ELF
27918 && DEFAULT_ABI == ABI_V4
27920 && ! info->lr_save_p
27921 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27922 if (save_LR_around_toc_setup)
27924 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27925 rtx tmp = gen_rtx_REG (Pmode, 12);
27928 insn = emit_move_insn (tmp, lr);
27929 RTX_FRAME_RELATED_P (insn) = 1;
27931 rs6000_emit_load_toc_table (TRUE);
27933 insn = emit_move_insn (lr, tmp);
27934 add_reg_note (insn, REG_CFA_RESTORE, lr);
27935 RTX_FRAME_RELATED_P (insn) = 1;
27938 rs6000_emit_load_toc_table (TRUE);
27942 if (!TARGET_SINGLE_PIC_BASE
27943 && DEFAULT_ABI == ABI_DARWIN
27944 && flag_pic && crtl->uses_pic_offset_table)
27946 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27947 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27949 /* Save and restore LR locally around this call (in R0). */
27950 if (!info->lr_save_p)
27951 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27953 emit_insn (gen_load_macho_picbase (src));
27955 emit_move_insn (gen_rtx_REG (Pmode,
27956 RS6000_PIC_OFFSET_TABLE_REGNUM),
27959 if (!info->lr_save_p)
27960 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27964 /* If we need to, save the TOC register after doing the stack setup.
27965 Do not emit eh frame info for this save. The unwinder wants info,
27966 conceptually attached to instructions in this function, about
27967 register values in the caller of this function. This R2 may have
27968 already been changed from the value in the caller.
27969 We don't attempt to write accurate DWARF EH frame info for R2
27970 because code emitted by gcc for a (non-pointer) function call
27971 doesn't save and restore R2. Instead, R2 is managed out-of-line
27972 by a linker generated plt call stub when the function resides in
27973 a shared library. This behavior is costly to describe in DWARF,
27974 both in terms of the size of DWARF info and the time taken in the
27975 unwinder to interpret it. R2 changes, apart from the
27976 calls_eh_return case earlier in this function, are handled by
27977 linux-unwind.h frob_update_context. */
27978 if (rs6000_save_toc_in_prologue_p ()
27979 && !cfun->machine->toc_is_wrapped_separately)
27981 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
27982 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
27985 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27986 if (using_split_stack && split_stack_arg_pointer_used_p ())
27987 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
27990 /* Output .extern statements for the save/restore routines we use. */
27993 rs6000_output_savres_externs (FILE *file)
27995 rs6000_stack_t *info = rs6000_stack_info ();
27997 if (TARGET_DEBUG_STACK)
27998 debug_stack_info (info);
28000 /* Write .extern for any function we will call to save and restore
28002 if (info->first_fp_reg_save < 64
28007 int regno = info->first_fp_reg_save - 32;
28009 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
28011 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
28012 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
28013 name = rs6000_savres_routine_name (regno, sel);
28014 fprintf (file, "\t.extern %s\n", name);
28016 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
28018 bool lr = (info->savres_strategy
28019 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28020 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28021 name = rs6000_savres_routine_name (regno, sel);
28022 fprintf (file, "\t.extern %s\n", name);
28027 /* Write function prologue. */
28030 rs6000_output_function_prologue (FILE *file)
28032 if (!cfun->is_thunk)
28033 rs6000_output_savres_externs (file);
28035 /* ELFv2 ABI r2 setup code and local entry point. This must follow
28036 immediately after the global entry point label. */
28037 if (rs6000_global_entry_point_needed_p ())
28039 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
28041 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
28043 if (TARGET_CMODEL != CMODEL_LARGE)
28045 /* In the small and medium code models, we assume the TOC is less
28046 2 GB away from the text section, so it can be computed via the
28047 following two-instruction sequence. */
28050 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
28051 fprintf (file, "0:\taddis 2,12,.TOC.-");
28052 assemble_name (file, buf);
28053 fprintf (file, "@ha\n");
28054 fprintf (file, "\taddi 2,2,.TOC.-");
28055 assemble_name (file, buf);
28056 fprintf (file, "@l\n");
28060 /* In the large code model, we allow arbitrary offsets between the
28061 TOC and the text section, so we have to load the offset from
28062 memory. The data field is emitted directly before the global
28063 entry point in rs6000_elf_declare_function_name. */
28066 #ifdef HAVE_AS_ENTRY_MARKERS
28067 /* If supported by the linker, emit a marker relocation. If the
28068 total code size of the final executable or shared library
28069 happens to fit into 2 GB after all, the linker will replace
28070 this code sequence with the sequence for the small or medium
28072 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
28074 fprintf (file, "\tld 2,");
28075 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
28076 assemble_name (file, buf);
28077 fprintf (file, "-");
28078 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
28079 assemble_name (file, buf);
28080 fprintf (file, "(12)\n");
28081 fprintf (file, "\tadd 2,2,12\n");
28084 fputs ("\t.localentry\t", file);
28085 assemble_name (file, name);
28086 fputs (",.-", file);
28087 assemble_name (file, name);
28088 fputs ("\n", file);
28091 /* Output -mprofile-kernel code. This needs to be done here instead of
28092 in output_function_profile since it must go after the ELFv2 ABI
28093 local entry point. */
28094 if (TARGET_PROFILE_KERNEL && crtl->profile)
28096 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
28097 gcc_assert (!TARGET_32BIT);
28099 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
28101 /* In the ELFv2 ABI we have no compiler stack word. It must be
28102 the resposibility of _mcount to preserve the static chain
28103 register if required. */
28104 if (DEFAULT_ABI != ABI_ELFv2
28105 && cfun->static_chain_decl != NULL)
28107 asm_fprintf (file, "\tstd %s,24(%s)\n",
28108 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
28109 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
28110 asm_fprintf (file, "\tld %s,24(%s)\n",
28111 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
28114 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
28117 rs6000_pic_labelno++;
28120 /* -mprofile-kernel code calls mcount before the function prolog,
28121 so a profiled leaf function should stay a leaf function. */
28123 rs6000_keep_leaf_when_profiled ()
28125 return TARGET_PROFILE_KERNEL;
28128 /* Non-zero if vmx regs are restored before the frame pop, zero if
28129 we restore after the pop when possible. */
28130 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
28132 /* Restoring cr is a two step process: loading a reg from the frame
28133 save, then moving the reg to cr. For ABI_V4 we must let the
28134 unwinder know that the stack location is no longer valid at or
28135 before the stack deallocation, but we can't emit a cfa_restore for
28136 cr at the stack deallocation like we do for other registers.
28137 The trouble is that it is possible for the move to cr to be
28138 scheduled after the stack deallocation. So say exactly where cr
28139 is located on each of the two insns. */
28142 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
28144 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
28145 rtx reg = gen_rtx_REG (SImode, regno);
28146 rtx_insn *insn = emit_move_insn (reg, mem);
28148 if (!exit_func && DEFAULT_ABI == ABI_V4)
28150 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
28151 rtx set = gen_rtx_SET (reg, cr);
28153 add_reg_note (insn, REG_CFA_REGISTER, set);
28154 RTX_FRAME_RELATED_P (insn) = 1;
28159 /* Reload CR from REG. */
28162 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
28167 if (using_mfcr_multiple)
28169 for (i = 0; i < 8; i++)
28170 if (save_reg_p (CR0_REGNO + i))
28172 gcc_assert (count);
28175 if (using_mfcr_multiple && count > 1)
28181 p = rtvec_alloc (count);
28184 for (i = 0; i < 8; i++)
28185 if (save_reg_p (CR0_REGNO + i))
28187 rtvec r = rtvec_alloc (2);
28188 RTVEC_ELT (r, 0) = reg;
28189 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
28190 RTVEC_ELT (p, ndx) =
28191 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
28192 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
28195 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28196 gcc_assert (ndx == count);
28198 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
28199 CR field separately. */
28200 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
28202 for (i = 0; i < 8; i++)
28203 if (save_reg_p (CR0_REGNO + i))
28204 add_reg_note (insn, REG_CFA_RESTORE,
28205 gen_rtx_REG (SImode, CR0_REGNO + i));
28207 RTX_FRAME_RELATED_P (insn) = 1;
28211 for (i = 0; i < 8; i++)
28212 if (save_reg_p (CR0_REGNO + i))
28214 rtx insn = emit_insn (gen_movsi_to_cr_one
28215 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28217 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
28218 CR field separately, attached to the insn that in fact
28219 restores this particular CR field. */
28220 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
28222 add_reg_note (insn, REG_CFA_RESTORE,
28223 gen_rtx_REG (SImode, CR0_REGNO + i));
28225 RTX_FRAME_RELATED_P (insn) = 1;
28229 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
28230 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
28231 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
28233 rtx_insn *insn = get_last_insn ();
28234 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
28236 add_reg_note (insn, REG_CFA_RESTORE, cr);
28237 RTX_FRAME_RELATED_P (insn) = 1;
28241 /* Like cr, the move to lr instruction can be scheduled after the
28242 stack deallocation, but unlike cr, its stack frame save is still
28243 valid. So we only need to emit the cfa_restore on the correct
28247 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
28249 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
28250 rtx reg = gen_rtx_REG (Pmode, regno);
28252 emit_move_insn (reg, mem);
28256 restore_saved_lr (int regno, bool exit_func)
28258 rtx reg = gen_rtx_REG (Pmode, regno);
28259 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
28260 rtx_insn *insn = emit_move_insn (lr, reg);
28262 if (!exit_func && flag_shrink_wrap)
28264 add_reg_note (insn, REG_CFA_RESTORE, lr);
28265 RTX_FRAME_RELATED_P (insn) = 1;
28270 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
28272 if (DEFAULT_ABI == ABI_ELFv2)
28275 for (i = 0; i < 8; i++)
28276 if (save_reg_p (CR0_REGNO + i))
28278 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
28279 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
28283 else if (info->cr_save_p)
28284 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28285 gen_rtx_REG (SImode, CR2_REGNO),
28288 if (info->lr_save_p)
28289 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28290 gen_rtx_REG (Pmode, LR_REGNO),
28292 return cfa_restores;
28295 /* Return true if OFFSET from stack pointer can be clobbered by signals.
28296 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
28297 below stack pointer not cloberred by signals. */
28300 offset_below_red_zone_p (HOST_WIDE_INT offset)
28302 return offset < (DEFAULT_ABI == ABI_V4
28304 : TARGET_32BIT ? -220 : -288);
28307 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
28310 emit_cfa_restores (rtx cfa_restores)
28312 rtx_insn *insn = get_last_insn ();
28313 rtx *loc = ®_NOTES (insn);
28316 loc = &XEXP (*loc, 1);
28317 *loc = cfa_restores;
28318 RTX_FRAME_RELATED_P (insn) = 1;
28321 /* Emit function epilogue as insns. */
28324 rs6000_emit_epilogue (int sibcall)
28326 rs6000_stack_t *info;
28327 int restoring_GPRs_inline;
28328 int restoring_FPRs_inline;
28329 int using_load_multiple;
28330 int using_mtcr_multiple;
28331 int use_backchain_to_restore_sp;
28334 HOST_WIDE_INT frame_off = 0;
28335 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
28336 rtx frame_reg_rtx = sp_reg_rtx;
28337 rtx cfa_restores = NULL_RTX;
28339 rtx cr_save_reg = NULL_RTX;
28340 machine_mode reg_mode = Pmode;
28341 int reg_size = TARGET_32BIT ? 4 : 8;
28342 machine_mode fp_reg_mode = (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
28344 int fp_reg_size = 8;
28347 unsigned ptr_regno;
28349 info = rs6000_stack_info ();
28351 strategy = info->savres_strategy;
28352 using_load_multiple = strategy & REST_MULTIPLE;
28353 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
28354 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
28355 using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
28356 || rs6000_tune == PROCESSOR_PPC603
28357 || rs6000_tune == PROCESSOR_PPC750
28359 /* Restore via the backchain when we have a large frame, since this
28360 is more efficient than an addis, addi pair. The second condition
28361 here will not trigger at the moment; We don't actually need a
28362 frame pointer for alloca, but the generic parts of the compiler
28363 give us one anyway. */
28364 use_backchain_to_restore_sp = (info->total_size + (info->lr_save_p
28365 ? info->lr_save_offset
28367 || (cfun->calls_alloca
28368 && !frame_pointer_needed));
28369 restore_lr = (info->lr_save_p
28370 && (restoring_FPRs_inline
28371 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
28372 && (restoring_GPRs_inline
28373 || info->first_fp_reg_save < 64)
28374 && !cfun->machine->lr_is_wrapped_separately);
28377 if (WORLD_SAVE_P (info))
28381 const char *alloc_rname;
28384 /* eh_rest_world_r10 will return to the location saved in the LR
28385 stack slot (which is not likely to be our caller.)
28386 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
28387 rest_world is similar, except any R10 parameter is ignored.
28388 The exception-handling stuff that was here in 2.95 is no
28389 longer necessary. */
28392 + 32 - info->first_gp_reg_save
28393 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
28394 + 63 + 1 - info->first_fp_reg_save);
28396 strcpy (rname, ((crtl->calls_eh_return) ?
28397 "*eh_rest_world_r10" : "*rest_world"));
28398 alloc_rname = ggc_strdup (rname);
28401 RTVEC_ELT (p, j++) = ret_rtx;
28403 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
28404 /* The instruction pattern requires a clobber here;
28405 it is shared with the restVEC helper. */
28407 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
28410 /* CR register traditionally saved as CR2. */
28411 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
28413 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
28414 if (flag_shrink_wrap)
28416 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
28417 gen_rtx_REG (Pmode, LR_REGNO),
28419 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28423 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28425 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
28427 = gen_frame_load (reg,
28428 frame_reg_rtx, info->gp_save_offset + reg_size * i);
28429 if (flag_shrink_wrap
28430 && save_reg_p (info->first_gp_reg_save + i))
28431 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28433 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
28435 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
28437 = gen_frame_load (reg,
28438 frame_reg_rtx, info->altivec_save_offset + 16 * i);
28439 if (flag_shrink_wrap
28440 && save_reg_p (info->first_altivec_reg_save + i))
28441 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28443 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
28445 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
28446 ? DFmode : SFmode),
28447 info->first_fp_reg_save + i);
28449 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
28450 if (flag_shrink_wrap
28451 && save_reg_p (info->first_fp_reg_save + i))
28452 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28455 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
28457 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
28459 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
28461 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
28463 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
28464 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28466 if (flag_shrink_wrap)
28468 REG_NOTES (insn) = cfa_restores;
28469 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28470 RTX_FRAME_RELATED_P (insn) = 1;
28475 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
28477 frame_off = info->total_size;
28479 /* Restore AltiVec registers if we must do so before adjusting the
28481 if (info->altivec_size != 0
28482 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28483 || (DEFAULT_ABI != ABI_V4
28484 && offset_below_red_zone_p (info->altivec_save_offset))))
28487 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28489 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
28490 if (use_backchain_to_restore_sp)
28492 int frame_regno = 11;
28494 if ((strategy & REST_INLINE_VRS) == 0)
28496 /* Of r11 and r12, select the one not clobbered by an
28497 out-of-line restore function for the frame register. */
28498 frame_regno = 11 + 12 - scratch_regno;
28500 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
28501 emit_move_insn (frame_reg_rtx,
28502 gen_rtx_MEM (Pmode, sp_reg_rtx));
28505 else if (frame_pointer_needed)
28506 frame_reg_rtx = hard_frame_pointer_rtx;
28508 if ((strategy & REST_INLINE_VRS) == 0)
28510 int end_save = info->altivec_save_offset + info->altivec_size;
28512 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28513 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28515 if (end_save + frame_off != 0)
28517 rtx offset = GEN_INT (end_save + frame_off);
28519 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28522 emit_move_insn (ptr_reg, frame_reg_rtx);
28524 ptr_off = -end_save;
28525 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28526 info->altivec_save_offset + ptr_off,
28527 0, V4SImode, SAVRES_VR);
28531 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28532 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28534 rtx addr, areg, mem, insn;
28535 rtx reg = gen_rtx_REG (V4SImode, i);
28536 HOST_WIDE_INT offset
28537 = (info->altivec_save_offset + frame_off
28538 + 16 * (i - info->first_altivec_reg_save));
28540 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28542 mem = gen_frame_mem (V4SImode,
28543 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28544 GEN_INT (offset)));
28545 insn = gen_rtx_SET (reg, mem);
28549 areg = gen_rtx_REG (Pmode, 0);
28550 emit_move_insn (areg, GEN_INT (offset));
28552 /* AltiVec addressing mode is [reg+reg]. */
28553 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28554 mem = gen_frame_mem (V4SImode, addr);
28556 /* Rather than emitting a generic move, force use of the
28557 lvx instruction, which we always want. In particular we
28558 don't want lxvd2x/xxpermdi for little endian. */
28559 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28562 (void) emit_insn (insn);
28566 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28567 if (((strategy & REST_INLINE_VRS) == 0
28568 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28569 && (flag_shrink_wrap
28570 || (offset_below_red_zone_p
28571 (info->altivec_save_offset
28572 + 16 * (i - info->first_altivec_reg_save))))
28575 rtx reg = gen_rtx_REG (V4SImode, i);
28576 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28580 /* Restore VRSAVE if we must do so before adjusting the stack. */
28581 if (info->vrsave_size != 0
28582 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28583 || (DEFAULT_ABI != ABI_V4
28584 && offset_below_red_zone_p (info->vrsave_save_offset))))
28588 if (frame_reg_rtx == sp_reg_rtx)
28590 if (use_backchain_to_restore_sp)
28592 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28593 emit_move_insn (frame_reg_rtx,
28594 gen_rtx_MEM (Pmode, sp_reg_rtx));
28597 else if (frame_pointer_needed)
28598 frame_reg_rtx = hard_frame_pointer_rtx;
28601 reg = gen_rtx_REG (SImode, 12);
28602 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28603 info->vrsave_save_offset + frame_off));
28605 emit_insn (generate_set_vrsave (reg, info, 1));
28609 /* If we have a large stack frame, restore the old stack pointer
28610 using the backchain. */
28611 if (use_backchain_to_restore_sp)
28613 if (frame_reg_rtx == sp_reg_rtx)
28615 /* Under V.4, don't reset the stack pointer until after we're done
28616 loading the saved registers. */
28617 if (DEFAULT_ABI == ABI_V4)
28618 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28620 insn = emit_move_insn (frame_reg_rtx,
28621 gen_rtx_MEM (Pmode, sp_reg_rtx));
28624 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28625 && DEFAULT_ABI == ABI_V4)
28626 /* frame_reg_rtx has been set up by the altivec restore. */
28630 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
28631 frame_reg_rtx = sp_reg_rtx;
28634 /* If we have a frame pointer, we can restore the old stack pointer
28636 else if (frame_pointer_needed)
28638 frame_reg_rtx = sp_reg_rtx;
28639 if (DEFAULT_ABI == ABI_V4)
28640 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28641 /* Prevent reordering memory accesses against stack pointer restore. */
28642 else if (cfun->calls_alloca
28643 || offset_below_red_zone_p (-info->total_size))
28644 rs6000_emit_stack_tie (frame_reg_rtx, true);
28646 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
28647 GEN_INT (info->total_size)));
28650 else if (info->push_p
28651 && DEFAULT_ABI != ABI_V4
28652 && !crtl->calls_eh_return)
28654 /* Prevent reordering memory accesses against stack pointer restore. */
28655 if (cfun->calls_alloca
28656 || offset_below_red_zone_p (-info->total_size))
28657 rs6000_emit_stack_tie (frame_reg_rtx, false);
28658 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
28659 GEN_INT (info->total_size)));
28662 if (insn && frame_reg_rtx == sp_reg_rtx)
28666 REG_NOTES (insn) = cfa_restores;
28667 cfa_restores = NULL_RTX;
28669 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28670 RTX_FRAME_RELATED_P (insn) = 1;
28673 /* Restore AltiVec registers if we have not done so already. */
28674 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28675 && info->altivec_size != 0
28676 && (DEFAULT_ABI == ABI_V4
28677 || !offset_below_red_zone_p (info->altivec_save_offset)))
28681 if ((strategy & REST_INLINE_VRS) == 0)
28683 int end_save = info->altivec_save_offset + info->altivec_size;
28685 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28686 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28687 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28689 if (end_save + frame_off != 0)
28691 rtx offset = GEN_INT (end_save + frame_off);
28693 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28696 emit_move_insn (ptr_reg, frame_reg_rtx);
28698 ptr_off = -end_save;
28699 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28700 info->altivec_save_offset + ptr_off,
28701 0, V4SImode, SAVRES_VR);
28702 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
28704 /* Frame reg was clobbered by out-of-line save. Restore it
28705 from ptr_reg, and if we are calling out-of-line gpr or
28706 fpr restore set up the correct pointer and offset. */
28707 unsigned newptr_regno = 1;
28708 if (!restoring_GPRs_inline)
28710 bool lr = info->gp_save_offset + info->gp_size == 0;
28711 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28712 newptr_regno = ptr_regno_for_savres (sel);
28713 end_save = info->gp_save_offset + info->gp_size;
28715 else if (!restoring_FPRs_inline)
28717 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
28718 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28719 newptr_regno = ptr_regno_for_savres (sel);
28720 end_save = info->fp_save_offset + info->fp_size;
28723 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
28724 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
28726 if (end_save + ptr_off != 0)
28728 rtx offset = GEN_INT (end_save + ptr_off);
28730 frame_off = -end_save;
28732 emit_insn (gen_addsi3_carry (frame_reg_rtx,
28735 emit_insn (gen_adddi3_carry (frame_reg_rtx,
28740 frame_off = ptr_off;
28741 emit_move_insn (frame_reg_rtx, ptr_reg);
28747 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28748 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28750 rtx addr, areg, mem, insn;
28751 rtx reg = gen_rtx_REG (V4SImode, i);
28752 HOST_WIDE_INT offset
28753 = (info->altivec_save_offset + frame_off
28754 + 16 * (i - info->first_altivec_reg_save));
28756 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28758 mem = gen_frame_mem (V4SImode,
28759 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28760 GEN_INT (offset)));
28761 insn = gen_rtx_SET (reg, mem);
28765 areg = gen_rtx_REG (Pmode, 0);
28766 emit_move_insn (areg, GEN_INT (offset));
28768 /* AltiVec addressing mode is [reg+reg]. */
28769 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28770 mem = gen_frame_mem (V4SImode, addr);
28772 /* Rather than emitting a generic move, force use of the
28773 lvx instruction, which we always want. In particular we
28774 don't want lxvd2x/xxpermdi for little endian. */
28775 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28778 (void) emit_insn (insn);
28782 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28783 if (((strategy & REST_INLINE_VRS) == 0
28784 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28785 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28788 rtx reg = gen_rtx_REG (V4SImode, i);
28789 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28793 /* Restore VRSAVE if we have not done so already. */
28794 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28795 && info->vrsave_size != 0
28796 && (DEFAULT_ABI == ABI_V4
28797 || !offset_below_red_zone_p (info->vrsave_save_offset)))
28801 reg = gen_rtx_REG (SImode, 12);
28802 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28803 info->vrsave_save_offset + frame_off));
28805 emit_insn (generate_set_vrsave (reg, info, 1));
28808 /* If we exit by an out-of-line restore function on ABI_V4 then that
28809 function will deallocate the stack, so we don't need to worry
28810 about the unwinder restoring cr from an invalid stack frame
28812 exit_func = (!restoring_FPRs_inline
28813 || (!restoring_GPRs_inline
28814 && info->first_fp_reg_save == 64));
28816 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28817 *separate* slots if the routine calls __builtin_eh_return, so
28818 that they can be independently restored by the unwinder. */
28819 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28821 int i, cr_off = info->ehcr_offset;
28823 for (i = 0; i < 8; i++)
28824 if (!call_used_regs[CR0_REGNO + i])
28826 rtx reg = gen_rtx_REG (SImode, 0);
28827 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28828 cr_off + frame_off));
28830 insn = emit_insn (gen_movsi_to_cr_one
28831 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28833 if (!exit_func && flag_shrink_wrap)
28835 add_reg_note (insn, REG_CFA_RESTORE,
28836 gen_rtx_REG (SImode, CR0_REGNO + i));
28838 RTX_FRAME_RELATED_P (insn) = 1;
28841 cr_off += reg_size;
28845 /* Get the old lr if we saved it. If we are restoring registers
28846 out-of-line, then the out-of-line routines can do this for us. */
28847 if (restore_lr && restoring_GPRs_inline)
28848 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28850 /* Get the old cr if we saved it. */
28851 if (info->cr_save_p)
28853 unsigned cr_save_regno = 12;
28855 if (!restoring_GPRs_inline)
28857 /* Ensure we don't use the register used by the out-of-line
28858 gpr register restore below. */
28859 bool lr = info->gp_save_offset + info->gp_size == 0;
28860 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28861 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28863 if (gpr_ptr_regno == 12)
28864 cr_save_regno = 11;
28865 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28867 else if (REGNO (frame_reg_rtx) == 12)
28868 cr_save_regno = 11;
28870 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28871 info->cr_save_offset + frame_off,
28875 /* Set LR here to try to overlap restores below. */
28876 if (restore_lr && restoring_GPRs_inline)
28877 restore_saved_lr (0, exit_func);
28879 /* Load exception handler data registers, if needed. */
28880 if (crtl->calls_eh_return)
28882 unsigned int i, regno;
28886 rtx reg = gen_rtx_REG (reg_mode, 2);
28887 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28888 frame_off + RS6000_TOC_SAVE_SLOT));
28895 regno = EH_RETURN_DATA_REGNO (i);
28896 if (regno == INVALID_REGNUM)
28899 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28900 info->ehrd_offset + frame_off
28901 + reg_size * (int) i);
28903 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28907 /* Restore GPRs. This is done as a PARALLEL if we are using
28908 the load-multiple instructions. */
28909 if (!restoring_GPRs_inline)
28911 /* We are jumping to an out-of-line function. */
28913 int end_save = info->gp_save_offset + info->gp_size;
28914 bool can_use_exit = end_save == 0;
28915 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28918 /* Emit stack reset code if we need it. */
28919 ptr_regno = ptr_regno_for_savres (sel);
28920 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28922 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28923 else if (end_save + frame_off != 0)
28924 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28925 GEN_INT (end_save + frame_off)));
28926 else if (REGNO (frame_reg_rtx) != ptr_regno)
28927 emit_move_insn (ptr_reg, frame_reg_rtx);
28928 if (REGNO (frame_reg_rtx) == ptr_regno)
28929 frame_off = -end_save;
28931 if (can_use_exit && info->cr_save_p)
28932 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28934 ptr_off = -end_save;
28935 rs6000_emit_savres_rtx (info, ptr_reg,
28936 info->gp_save_offset + ptr_off,
28937 info->lr_save_offset + ptr_off,
28940 else if (using_load_multiple)
28943 p = rtvec_alloc (32 - info->first_gp_reg_save);
28944 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28946 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28948 info->gp_save_offset + frame_off + reg_size * i);
28949 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28953 int offset = info->gp_save_offset + frame_off;
28954 for (i = info->first_gp_reg_save; i < 32; i++)
28957 && !cfun->machine->gpr_is_wrapped_separately[i])
28959 rtx reg = gen_rtx_REG (reg_mode, i);
28960 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28963 offset += reg_size;
28967 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28969 /* If the frame pointer was used then we can't delay emitting
28970 a REG_CFA_DEF_CFA note. This must happen on the insn that
28971 restores the frame pointer, r31. We may have already emitted
28972 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28973 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28974 be harmless if emitted. */
28975 if (frame_pointer_needed)
28977 insn = get_last_insn ();
28978 add_reg_note (insn, REG_CFA_DEF_CFA,
28979 plus_constant (Pmode, frame_reg_rtx, frame_off));
28980 RTX_FRAME_RELATED_P (insn) = 1;
28983 /* Set up cfa_restores. We always need these when
28984 shrink-wrapping. If not shrink-wrapping then we only need
28985 the cfa_restore when the stack location is no longer valid.
28986 The cfa_restores must be emitted on or before the insn that
28987 invalidates the stack, and of course must not be emitted
28988 before the insn that actually does the restore. The latter
28989 is why it is a bad idea to emit the cfa_restores as a group
28990 on the last instruction here that actually does a restore:
28991 That insn may be reordered with respect to others doing
28993 if (flag_shrink_wrap
28994 && !restoring_GPRs_inline
28995 && info->first_fp_reg_save == 64)
28996 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28998 for (i = info->first_gp_reg_save; i < 32; i++)
29000 && !cfun->machine->gpr_is_wrapped_separately[i])
29002 rtx reg = gen_rtx_REG (reg_mode, i);
29003 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
29007 if (!restoring_GPRs_inline
29008 && info->first_fp_reg_save == 64)
29010 /* We are jumping to an out-of-line function. */
29012 emit_cfa_restores (cfa_restores);
29016 if (restore_lr && !restoring_GPRs_inline)
29018 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
29019 restore_saved_lr (0, exit_func);
29022 /* Restore fpr's if we need to do it without calling a function. */
29023 if (restoring_FPRs_inline)
29025 int offset = info->fp_save_offset + frame_off;
29026 for (i = info->first_fp_reg_save; i < 64; i++)
29029 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
29031 rtx reg = gen_rtx_REG (fp_reg_mode, i);
29032 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
29033 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
29034 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
29038 offset += fp_reg_size;
29042 /* If we saved cr, restore it here. Just those that were used. */
29043 if (info->cr_save_p)
29044 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
29046 /* If this is V.4, unwind the stack pointer after all of the loads
29047 have been done, or set up r11 if we are restoring fp out of line. */
29049 if (!restoring_FPRs_inline)
29051 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
29052 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
29053 ptr_regno = ptr_regno_for_savres (sel);
29056 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
29057 if (REGNO (frame_reg_rtx) == ptr_regno)
29060 if (insn && restoring_FPRs_inline)
29064 REG_NOTES (insn) = cfa_restores;
29065 cfa_restores = NULL_RTX;
29067 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
29068 RTX_FRAME_RELATED_P (insn) = 1;
29071 if (crtl->calls_eh_return)
29073 rtx sa = EH_RETURN_STACKADJ_RTX;
29074 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
29077 if (!sibcall && restoring_FPRs_inline)
29081 /* We can't hang the cfa_restores off a simple return,
29082 since the shrink-wrap code sometimes uses an existing
29083 return. This means there might be a path from
29084 pre-prologue code to this return, and dwarf2cfi code
29085 wants the eh_frame unwinder state to be the same on
29086 all paths to any point. So we need to emit the
29087 cfa_restores before the return. For -m64 we really
29088 don't need epilogue cfa_restores at all, except for
29089 this irritating dwarf2cfi with shrink-wrap
29090 requirement; The stack red-zone means eh_frame info
29091 from the prologue telling the unwinder to restore
29092 from the stack is perfectly good right to the end of
29094 emit_insn (gen_blockage ());
29095 emit_cfa_restores (cfa_restores);
29096 cfa_restores = NULL_RTX;
29099 emit_jump_insn (targetm.gen_simple_return ());
29102 if (!sibcall && !restoring_FPRs_inline)
29104 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
29105 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
29107 RTVEC_ELT (p, elt++) = ret_rtx;
29109 RTVEC_ELT (p, elt++)
29110 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
29112 /* We have to restore more than two FP registers, so branch to the
29113 restore function. It will return to our caller. */
29118 if (flag_shrink_wrap)
29119 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
29121 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
29122 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
29123 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
29124 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
29126 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
29128 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
29130 RTVEC_ELT (p, elt++)
29131 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
29132 if (flag_shrink_wrap
29133 && save_reg_p (info->first_fp_reg_save + i))
29134 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
29137 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
29143 /* Ensure the cfa_restores are hung off an insn that won't
29144 be reordered above other restores. */
29145 emit_insn (gen_blockage ());
29147 emit_cfa_restores (cfa_restores);
29151 /* Write function epilogue. */
29154 rs6000_output_function_epilogue (FILE *file)
29157 macho_branch_islands ();
29160 rtx_insn *insn = get_last_insn ();
29161 rtx_insn *deleted_debug_label = NULL;
29163 /* Mach-O doesn't support labels at the end of objects, so if
29164 it looks like we might want one, take special action.
29166 First, collect any sequence of deleted debug labels. */
29169 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
29171 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
29172 notes only, instead set their CODE_LABEL_NUMBER to -1,
29173 otherwise there would be code generation differences
29174 in between -g and -g0. */
29175 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
29176 deleted_debug_label = insn;
29177 insn = PREV_INSN (insn);
29180 /* Second, if we have:
29183 then this needs to be detected, so skip past the barrier. */
29185 if (insn && BARRIER_P (insn))
29186 insn = PREV_INSN (insn);
29188 /* Up to now we've only seen notes or barriers. */
29193 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
29194 /* Trailing label: <barrier>. */
29195 fputs ("\tnop\n", file);
29198 /* Lastly, see if we have a completely empty function body. */
29199 while (insn && ! INSN_P (insn))
29200 insn = PREV_INSN (insn);
29201 /* If we don't find any insns, we've got an empty function body;
29202 I.e. completely empty - without a return or branch. This is
29203 taken as the case where a function body has been removed
29204 because it contains an inline __builtin_unreachable(). GCC
29205 states that reaching __builtin_unreachable() means UB so we're
29206 not obliged to do anything special; however, we want
29207 non-zero-sized function bodies. To meet this, and help the
29208 user out, let's trap the case. */
29210 fputs ("\ttrap\n", file);
29213 else if (deleted_debug_label)
29214 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
29215 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
29216 CODE_LABEL_NUMBER (insn) = -1;
29220 /* Output a traceback table here. See /usr/include/sys/debug.h for info
29223 We don't output a traceback table if -finhibit-size-directive was
29224 used. The documentation for -finhibit-size-directive reads
29225 ``don't output a @code{.size} assembler directive, or anything
29226 else that would cause trouble if the function is split in the
29227 middle, and the two halves are placed at locations far apart in
29228 memory.'' The traceback table has this property, since it
29229 includes the offset from the start of the function to the
29230 traceback table itself.
29232 System V.4 Powerpc's (and the embedded ABI derived from it) use a
29233 different traceback table. */
29234 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29235 && ! flag_inhibit_size_directive
29236 && rs6000_traceback != traceback_none && !cfun->is_thunk)
29238 const char *fname = NULL;
29239 const char *language_string = lang_hooks.name;
29240 int fixed_parms = 0, float_parms = 0, parm_info = 0;
29242 int optional_tbtab;
29243 rs6000_stack_t *info = rs6000_stack_info ();
29245 if (rs6000_traceback == traceback_full)
29246 optional_tbtab = 1;
29247 else if (rs6000_traceback == traceback_part)
29248 optional_tbtab = 0;
29250 optional_tbtab = !optimize_size && !TARGET_ELF;
29252 if (optional_tbtab)
29254 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
29255 while (*fname == '.') /* V.4 encodes . in the name */
29258 /* Need label immediately before tbtab, so we can compute
29259 its offset from the function start. */
29260 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
29261 ASM_OUTPUT_LABEL (file, fname);
29264 /* The .tbtab pseudo-op can only be used for the first eight
29265 expressions, since it can't handle the possibly variable
29266 length fields that follow. However, if you omit the optional
29267 fields, the assembler outputs zeros for all optional fields
29268 anyways, giving each variable length field is minimum length
29269 (as defined in sys/debug.h). Thus we can not use the .tbtab
29270 pseudo-op at all. */
29272 /* An all-zero word flags the start of the tbtab, for debuggers
29273 that have to find it by searching forward from the entry
29274 point or from the current pc. */
29275 fputs ("\t.long 0\n", file);
29277 /* Tbtab format type. Use format type 0. */
29278 fputs ("\t.byte 0,", file);
29280 /* Language type. Unfortunately, there does not seem to be any
29281 official way to discover the language being compiled, so we
29282 use language_string.
29283 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
29284 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
29285 a number, so for now use 9. LTO, Go and JIT aren't assigned numbers
29286 either, so for now use 0. */
29288 || ! strcmp (language_string, "GNU GIMPLE")
29289 || ! strcmp (language_string, "GNU Go")
29290 || ! strcmp (language_string, "libgccjit"))
29292 else if (! strcmp (language_string, "GNU F77")
29293 || lang_GNU_Fortran ())
29295 else if (! strcmp (language_string, "GNU Pascal"))
29297 else if (! strcmp (language_string, "GNU Ada"))
29299 else if (lang_GNU_CXX ()
29300 || ! strcmp (language_string, "GNU Objective-C++"))
29302 else if (! strcmp (language_string, "GNU Java"))
29304 else if (! strcmp (language_string, "GNU Objective-C"))
29307 gcc_unreachable ();
29308 fprintf (file, "%d,", i);
29310 /* 8 single bit fields: global linkage (not set for C extern linkage,
29311 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
29312 from start of procedure stored in tbtab, internal function, function
29313 has controlled storage, function has no toc, function uses fp,
29314 function logs/aborts fp operations. */
29315 /* Assume that fp operations are used if any fp reg must be saved. */
29316 fprintf (file, "%d,",
29317 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
29319 /* 6 bitfields: function is interrupt handler, name present in
29320 proc table, function calls alloca, on condition directives
29321 (controls stack walks, 3 bits), saves condition reg, saves
29323 /* The `function calls alloca' bit seems to be set whenever reg 31 is
29324 set up as a frame pointer, even when there is no alloca call. */
29325 fprintf (file, "%d,",
29326 ((optional_tbtab << 6)
29327 | ((optional_tbtab & frame_pointer_needed) << 5)
29328 | (info->cr_save_p << 1)
29329 | (info->lr_save_p)));
29331 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
29333 fprintf (file, "%d,",
29334 (info->push_p << 7) | (64 - info->first_fp_reg_save));
29336 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
29337 fprintf (file, "%d,", (32 - first_reg_to_save ()));
29339 if (optional_tbtab)
29341 /* Compute the parameter info from the function decl argument
29344 int next_parm_info_bit = 31;
29346 for (decl = DECL_ARGUMENTS (current_function_decl);
29347 decl; decl = DECL_CHAIN (decl))
29349 rtx parameter = DECL_INCOMING_RTL (decl);
29350 machine_mode mode = GET_MODE (parameter);
29352 if (GET_CODE (parameter) == REG)
29354 if (SCALAR_FLOAT_MODE_P (mode))
29377 gcc_unreachable ();
29380 /* If only one bit will fit, don't or in this entry. */
29381 if (next_parm_info_bit > 0)
29382 parm_info |= (bits << (next_parm_info_bit - 1));
29383 next_parm_info_bit -= 2;
29387 fixed_parms += ((GET_MODE_SIZE (mode)
29388 + (UNITS_PER_WORD - 1))
29390 next_parm_info_bit -= 1;
29396 /* Number of fixed point parameters. */
29397 /* This is actually the number of words of fixed point parameters; thus
29398 an 8 byte struct counts as 2; and thus the maximum value is 8. */
29399 fprintf (file, "%d,", fixed_parms);
29401 /* 2 bitfields: number of floating point parameters (7 bits), parameters
29403 /* This is actually the number of fp registers that hold parameters;
29404 and thus the maximum value is 13. */
29405 /* Set parameters on stack bit if parameters are not in their original
29406 registers, regardless of whether they are on the stack? Xlc
29407 seems to set the bit when not optimizing. */
29408 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
29410 if (optional_tbtab)
29412 /* Optional fields follow. Some are variable length. */
29414 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
29415 float, 11 double float. */
29416 /* There is an entry for each parameter in a register, in the order
29417 that they occur in the parameter list. Any intervening arguments
29418 on the stack are ignored. If the list overflows a long (max
29419 possible length 34 bits) then completely leave off all elements
29421 /* Only emit this long if there was at least one parameter. */
29422 if (fixed_parms || float_parms)
29423 fprintf (file, "\t.long %d\n", parm_info);
29425 /* Offset from start of code to tb table. */
29426 fputs ("\t.long ", file);
29427 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
29428 RS6000_OUTPUT_BASENAME (file, fname);
29430 rs6000_output_function_entry (file, fname);
29433 /* Interrupt handler mask. */
29434 /* Omit this long, since we never set the interrupt handler bit
29437 /* Number of CTL (controlled storage) anchors. */
29438 /* Omit this long, since the has_ctl bit is never set above. */
29440 /* Displacement into stack of each CTL anchor. */
29441 /* Omit this list of longs, because there are no CTL anchors. */
29443 /* Length of function name. */
29446 fprintf (file, "\t.short %d\n", (int) strlen (fname));
29448 /* Function name. */
29449 assemble_string (fname, strlen (fname));
29451 /* Register for alloca automatic storage; this is always reg 31.
29452 Only emit this if the alloca bit was set above. */
29453 if (frame_pointer_needed)
29454 fputs ("\t.byte 31\n", file);
29456 fputs ("\t.align 2\n", file);
29460 /* Arrange to define .LCTOC1 label, if not already done. */
29464 if (!toc_initialized)
29466 switch_to_section (toc_section);
29467 switch_to_section (current_function_section ());
29472 /* -fsplit-stack support. */
29474 /* A SYMBOL_REF for __morestack. */
29475 static GTY(()) rtx morestack_ref;
29478 gen_add3_const (rtx rt, rtx ra, long c)
29481 return gen_adddi3 (rt, ra, GEN_INT (c));
29483 return gen_addsi3 (rt, ra, GEN_INT (c));
29486 /* Emit -fsplit-stack prologue, which goes before the regular function
29487 prologue (at local entry point in the case of ELFv2). */
29490 rs6000_expand_split_stack_prologue (void)
29492 rs6000_stack_t *info = rs6000_stack_info ();
29493 unsigned HOST_WIDE_INT allocate;
29494 long alloc_hi, alloc_lo;
29495 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
29498 gcc_assert (flag_split_stack && reload_completed);
29503 if (global_regs[29])
29505 error ("%qs uses register r29", "-fsplit-stack");
29506 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
29507 "conflicts with %qD", global_regs_decl[29]);
29510 allocate = info->total_size;
29511 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
29513 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
29516 if (morestack_ref == NULL_RTX)
29518 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
29519 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
29520 | SYMBOL_FLAG_FUNCTION);
29523 r0 = gen_rtx_REG (Pmode, 0);
29524 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29525 r12 = gen_rtx_REG (Pmode, 12);
29526 emit_insn (gen_load_split_stack_limit (r0));
29527 /* Always emit two insns here to calculate the requested stack,
29528 so that the linker can edit them when adjusting size for calling
29529 non-split-stack code. */
29530 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
29531 alloc_lo = -allocate - alloc_hi;
29534 emit_insn (gen_add3_const (r12, r1, alloc_hi));
29536 emit_insn (gen_add3_const (r12, r12, alloc_lo));
29538 emit_insn (gen_nop ());
29542 emit_insn (gen_add3_const (r12, r1, alloc_lo));
29543 emit_insn (gen_nop ());
29546 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
29547 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
29548 ok_label = gen_label_rtx ();
29549 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29550 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
29551 gen_rtx_LABEL_REF (VOIDmode, ok_label),
29553 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29554 JUMP_LABEL (insn) = ok_label;
29555 /* Mark the jump as very likely to be taken. */
29556 add_reg_br_prob_note (insn, profile_probability::very_likely ());
29558 lr = gen_rtx_REG (Pmode, LR_REGNO);
29559 insn = emit_move_insn (r0, lr);
29560 RTX_FRAME_RELATED_P (insn) = 1;
29561 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
29562 RTX_FRAME_RELATED_P (insn) = 1;
29564 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
29565 const0_rtx, const0_rtx));
29566 call_fusage = NULL_RTX;
29567 use_reg (&call_fusage, r12);
29568 /* Say the call uses r0, even though it doesn't, to stop regrename
29569 from twiddling with the insns saving lr, trashing args for cfun.
29570 The insns restoring lr are similarly protected by making
29571 split_stack_return use r0. */
29572 use_reg (&call_fusage, r0);
29573 add_function_usage_to (insn, call_fusage);
29574 /* Indicate that this function can't jump to non-local gotos. */
29575 make_reg_eh_region_note_nothrow_nononlocal (insn);
29576 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
29577 insn = emit_move_insn (lr, r0);
29578 add_reg_note (insn, REG_CFA_RESTORE, lr);
29579 RTX_FRAME_RELATED_P (insn) = 1;
29580 emit_insn (gen_split_stack_return ());
29582 emit_label (ok_label);
29583 LABEL_NUSES (ok_label) = 1;
29586 /* Return the internal arg pointer used for function incoming
29587 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29588 to copy it to a pseudo in order for it to be preserved over calls
29589 and suchlike. We'd really like to use a pseudo here for the
29590 internal arg pointer but data-flow analysis is not prepared to
29591 accept pseudos as live at the beginning of a function. */
29594 rs6000_internal_arg_pointer (void)
29596 if (flag_split_stack
29597 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
29601 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
29605 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
29606 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
29608 /* Put the pseudo initialization right after the note at the
29609 beginning of the function. */
29610 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
29611 gen_rtx_REG (Pmode, 12));
29612 push_topmost_sequence ();
29613 emit_insn_after (pat, get_insns ());
29614 pop_topmost_sequence ();
29616 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
29617 FIRST_PARM_OFFSET (current_function_decl));
29618 return copy_to_reg (ret);
29620 return virtual_incoming_args_rtx;
29623 /* We may have to tell the dataflow pass that the split stack prologue
29624 is initializing a register. */
29627 rs6000_live_on_entry (bitmap regs)
29629 if (flag_split_stack)
29630 bitmap_set_bit (regs, 12);
29633 /* Emit -fsplit-stack dynamic stack allocation space check. */
29636 rs6000_split_stack_space_check (rtx size, rtx label)
29638 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29639 rtx limit = gen_reg_rtx (Pmode);
29640 rtx requested = gen_reg_rtx (Pmode);
29641 rtx cmp = gen_reg_rtx (CCUNSmode);
29644 emit_insn (gen_load_split_stack_limit (limit));
29645 if (CONST_INT_P (size))
29646 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
29649 size = force_reg (Pmode, size);
29650 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
29652 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
29653 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29654 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
29655 gen_rtx_LABEL_REF (VOIDmode, label),
29657 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29658 JUMP_LABEL (jump) = label;
29661 /* A C compound statement that outputs the assembler code for a thunk
29662 function, used to implement C++ virtual function calls with
29663 multiple inheritance. The thunk acts as a wrapper around a virtual
29664 function, adjusting the implicit object parameter before handing
29665 control off to the real function.
29667 First, emit code to add the integer DELTA to the location that
29668 contains the incoming first argument. Assume that this argument
29669 contains a pointer, and is the one used to pass the `this' pointer
29670 in C++. This is the incoming argument *before* the function
29671 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29672 values of all other incoming arguments.
29674 After the addition, emit code to jump to FUNCTION, which is a
29675 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29676 not touch the return address. Hence returning from FUNCTION will
29677 return to whoever called the current `thunk'.
29679 The effect must be as if FUNCTION had been called directly with the
29680 adjusted first argument. This macro is responsible for emitting
29681 all of the code for a thunk function; output_function_prologue()
29682 and output_function_epilogue() are not invoked.
29684 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29685 been extracted from it.) It might possibly be useful on some
29686 targets, but probably not.
29688 If you do not define this macro, the target-independent code in the
29689 C++ frontend will generate a less efficient heavyweight thunk that
29690 calls FUNCTION instead of jumping to it. The generic approach does
29691 not support varargs. */
29694 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
29695 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
29698 rtx this_rtx, funexp;
29701 reload_completed = 1;
29702 epilogue_completed = 1;
29704 /* Mark the end of the (empty) prologue. */
29705 emit_note (NOTE_INSN_PROLOGUE_END);
29707 /* Find the "this" pointer. If the function returns a structure,
29708 the structure return pointer is in r3. */
29709 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
29710 this_rtx = gen_rtx_REG (Pmode, 4);
29712 this_rtx = gen_rtx_REG (Pmode, 3);
29714 /* Apply the constant offset, if required. */
29716 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
29718 /* Apply the offset from the vtable, if required. */
29721 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
29722 rtx tmp = gen_rtx_REG (Pmode, 12);
29724 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
29725 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
29727 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
29728 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
29732 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
29734 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
29736 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
29739 /* Generate a tail call to the target function. */
29740 if (!TREE_USED (function))
29742 assemble_external (function);
29743 TREE_USED (function) = 1;
29745 funexp = XEXP (DECL_RTL (function), 0);
29746 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
29749 if (MACHOPIC_INDIRECT)
29750 funexp = machopic_indirect_call_target (funexp);
29753 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29754 generate sibcall RTL explicitly. */
29755 insn = emit_call_insn (
29756 gen_rtx_PARALLEL (VOIDmode,
29758 gen_rtx_CALL (VOIDmode,
29759 funexp, const0_rtx),
29760 gen_rtx_USE (VOIDmode, const0_rtx),
29761 simple_return_rtx)));
29762 SIBLING_CALL_P (insn) = 1;
29765 /* Run just enough of rest_of_compilation to get the insns emitted.
29766 There's not really enough bulk here to make other passes such as
29767 instruction scheduling worth while. Note that use_thunk calls
29768 assemble_start_function and assemble_end_function. */
29769 insn = get_insns ();
29770 shorten_branches (insn);
29771 final_start_function (insn, file, 1);
29772 final (insn, file, 1);
29773 final_end_function ();
29775 reload_completed = 0;
29776 epilogue_completed = 0;
29779 /* A quick summary of the various types of 'constant-pool tables'
29782 Target Flags Name One table per
29783 AIX (none) AIX TOC object file
29784 AIX -mfull-toc AIX TOC object file
29785 AIX -mminimal-toc AIX minimal TOC translation unit
29786 SVR4/EABI (none) SVR4 SDATA object file
29787 SVR4/EABI -fpic SVR4 pic object file
29788 SVR4/EABI -fPIC SVR4 PIC translation unit
29789 SVR4/EABI -mrelocatable EABI TOC function
29790 SVR4/EABI -maix AIX TOC object file
29791 SVR4/EABI -maix -mminimal-toc
29792 AIX minimal TOC translation unit
29794 Name Reg. Set by entries contains:
29795 made by addrs? fp? sum?
29797 AIX TOC 2 crt0 as Y option option
29798 AIX minimal TOC 30 prolog gcc Y Y option
29799 SVR4 SDATA 13 crt0 gcc N Y N
29800 SVR4 pic 30 prolog ld Y not yet N
29801 SVR4 PIC 30 prolog gcc Y option option
29802 EABI TOC 30 prolog gcc Y option option
29806 /* Hash functions for the hash table. */
29809 rs6000_hash_constant (rtx k)
29811 enum rtx_code code = GET_CODE (k);
29812 machine_mode mode = GET_MODE (k);
29813 unsigned result = (code << 3) ^ mode;
29814 const char *format;
29817 format = GET_RTX_FORMAT (code);
29818 flen = strlen (format);
29824 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29826 case CONST_WIDE_INT:
29829 flen = CONST_WIDE_INT_NUNITS (k);
29830 for (i = 0; i < flen; i++)
29831 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29836 if (mode != VOIDmode)
29837 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29849 for (; fidx < flen; fidx++)
29850 switch (format[fidx])
29855 const char *str = XSTR (k, fidx);
29856 len = strlen (str);
29857 result = result * 613 + len;
29858 for (i = 0; i < len; i++)
29859 result = result * 613 + (unsigned) str[i];
29864 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29868 result = result * 613 + (unsigned) XINT (k, fidx);
29871 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29872 result = result * 613 + (unsigned) XWINT (k, fidx);
29876 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29877 result = result * 613 + (unsigned) (XWINT (k, fidx)
29884 gcc_unreachable ();
29891 toc_hasher::hash (toc_hash_struct *thc)
29893 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29896 /* Compare H1 and H2 for equivalence. */
29899 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29904 if (h1->key_mode != h2->key_mode)
29907 return rtx_equal_p (r1, r2);
29910 /* These are the names given by the C++ front-end to vtables, and
29911 vtable-like objects. Ideally, this logic should not be here;
29912 instead, there should be some programmatic way of inquiring as
29913 to whether or not an object is a vtable. */
29915 #define VTABLE_NAME_P(NAME) \
29916 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29917 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29918 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29919 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29920 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29922 #ifdef NO_DOLLAR_IN_LABEL
29923 /* Return a GGC-allocated character string translating dollar signs in
29924 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29927 rs6000_xcoff_strip_dollar (const char *name)
29933 q = (const char *) strchr (name, '$');
29935 if (q == 0 || q == name)
29938 len = strlen (name);
29939 strip = XALLOCAVEC (char, len + 1);
29940 strcpy (strip, name);
29941 p = strip + (q - name);
29945 p = strchr (p + 1, '$');
29948 return ggc_alloc_string (strip, len);
29953 rs6000_output_symbol_ref (FILE *file, rtx x)
29955 const char *name = XSTR (x, 0);
29957 /* Currently C++ toc references to vtables can be emitted before it
29958 is decided whether the vtable is public or private. If this is
29959 the case, then the linker will eventually complain that there is
29960 a reference to an unknown section. Thus, for vtables only,
29961 we emit the TOC reference to reference the identifier and not the
29963 if (VTABLE_NAME_P (name))
29965 RS6000_OUTPUT_BASENAME (file, name);
29968 assemble_name (file, name);
29971 /* Output a TOC entry. We derive the entry name from what is being
29975 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
29978 const char *name = buf;
29980 HOST_WIDE_INT offset = 0;
29982 gcc_assert (!TARGET_NO_TOC);
29984 /* When the linker won't eliminate them, don't output duplicate
29985 TOC entries (this happens on AIX if there is any kind of TOC,
29986 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29988 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
29990 struct toc_hash_struct *h;
29992 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29993 time because GGC is not initialized at that point. */
29994 if (toc_hash_table == NULL)
29995 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
29997 h = ggc_alloc<toc_hash_struct> ();
29999 h->key_mode = mode;
30000 h->labelno = labelno;
30002 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
30003 if (*found == NULL)
30005 else /* This is indeed a duplicate.
30006 Set this label equal to that label. */
30008 fputs ("\t.set ", file);
30009 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
30010 fprintf (file, "%d,", labelno);
30011 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
30012 fprintf (file, "%d\n", ((*found)->labelno));
30015 if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF
30016 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
30017 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
30019 fputs ("\t.set ", file);
30020 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
30021 fprintf (file, "%d,", labelno);
30022 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
30023 fprintf (file, "%d\n", ((*found)->labelno));
30030 /* If we're going to put a double constant in the TOC, make sure it's
30031 aligned properly when strict alignment is on. */
30032 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
30033 && STRICT_ALIGNMENT
30034 && GET_MODE_BITSIZE (mode) >= 64
30035 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
30036 ASM_OUTPUT_ALIGN (file, 3);
30039 (*targetm.asm_out.internal_label) (file, "LC", labelno);
30041 /* Handle FP constants specially. Note that if we have a minimal
30042 TOC, things we put here aren't actually in the TOC, so we can allow
30044 if (GET_CODE (x) == CONST_DOUBLE &&
30045 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
30046 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
30050 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30051 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
30053 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
30057 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30058 fputs (DOUBLE_INT_ASM_OP, file);
30060 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
30061 k[0] & 0xffffffff, k[1] & 0xffffffff,
30062 k[2] & 0xffffffff, k[3] & 0xffffffff);
30063 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
30064 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
30065 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
30066 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
30067 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
30072 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30073 fputs ("\t.long ", file);
30075 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
30076 k[0] & 0xffffffff, k[1] & 0xffffffff,
30077 k[2] & 0xffffffff, k[3] & 0xffffffff);
30078 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
30079 k[0] & 0xffffffff, k[1] & 0xffffffff,
30080 k[2] & 0xffffffff, k[3] & 0xffffffff);
30084 else if (GET_CODE (x) == CONST_DOUBLE &&
30085 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
30089 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30090 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
30092 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
30096 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30097 fputs (DOUBLE_INT_ASM_OP, file);
30099 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
30100 k[0] & 0xffffffff, k[1] & 0xffffffff);
30101 fprintf (file, "0x%lx%08lx\n",
30102 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
30103 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
30108 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30109 fputs ("\t.long ", file);
30111 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
30112 k[0] & 0xffffffff, k[1] & 0xffffffff);
30113 fprintf (file, "0x%lx,0x%lx\n",
30114 k[0] & 0xffffffff, k[1] & 0xffffffff);
30118 else if (GET_CODE (x) == CONST_DOUBLE &&
30119 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
30123 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
30124 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
30126 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
30130 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30131 fputs (DOUBLE_INT_ASM_OP, file);
30133 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
30134 if (WORDS_BIG_ENDIAN)
30135 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
30137 fprintf (file, "0x%lx\n", l & 0xffffffff);
30142 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30143 fputs ("\t.long ", file);
30145 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
30146 fprintf (file, "0x%lx\n", l & 0xffffffff);
30150 else if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT)
30152 unsigned HOST_WIDE_INT low;
30153 HOST_WIDE_INT high;
30155 low = INTVAL (x) & 0xffffffff;
30156 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
30158 /* TOC entries are always Pmode-sized, so when big-endian
30159 smaller integer constants in the TOC need to be padded.
30160 (This is still a win over putting the constants in
30161 a separate constant pool, because then we'd have
30162 to have both a TOC entry _and_ the actual constant.)
30164 For a 32-bit target, CONST_INT values are loaded and shifted
30165 entirely within `low' and can be stored in one TOC entry. */
30167 /* It would be easy to make this work, but it doesn't now. */
30168 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
30170 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
30173 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
30174 high = (HOST_WIDE_INT) low >> 32;
30180 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30181 fputs (DOUBLE_INT_ASM_OP, file);
30183 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
30184 (long) high & 0xffffffff, (long) low & 0xffffffff);
30185 fprintf (file, "0x%lx%08lx\n",
30186 (long) high & 0xffffffff, (long) low & 0xffffffff);
30191 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
30193 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30194 fputs ("\t.long ", file);
30196 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
30197 (long) high & 0xffffffff, (long) low & 0xffffffff);
30198 fprintf (file, "0x%lx,0x%lx\n",
30199 (long) high & 0xffffffff, (long) low & 0xffffffff);
30203 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30204 fputs ("\t.long ", file);
30206 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
30207 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
30213 if (GET_CODE (x) == CONST)
30215 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
30216 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
30218 base = XEXP (XEXP (x, 0), 0);
30219 offset = INTVAL (XEXP (XEXP (x, 0), 1));
30222 switch (GET_CODE (base))
30225 name = XSTR (base, 0);
30229 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
30230 CODE_LABEL_NUMBER (XEXP (base, 0)));
30234 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
30238 gcc_unreachable ();
30241 if (TARGET_ELF || TARGET_MINIMAL_TOC)
30242 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
30245 fputs ("\t.tc ", file);
30246 RS6000_OUTPUT_BASENAME (file, name);
30249 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
30251 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
30253 /* Mark large TOC symbols on AIX with [TE] so they are mapped
30254 after other TOC symbols, reducing overflow of small TOC access
30255 to [TC] symbols. */
30256 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
30257 ? "[TE]," : "[TC],", file);
30260 /* Currently C++ toc references to vtables can be emitted before it
30261 is decided whether the vtable is public or private. If this is
30262 the case, then the linker will eventually complain that there is
30263 a TOC reference to an unknown section. Thus, for vtables only,
30264 we emit the TOC reference to reference the symbol and not the
30266 if (VTABLE_NAME_P (name))
30268 RS6000_OUTPUT_BASENAME (file, name);
30270 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
30271 else if (offset > 0)
30272 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
30275 output_addr_const (file, x);
30278 if (TARGET_XCOFF && GET_CODE (base) == SYMBOL_REF)
30280 switch (SYMBOL_REF_TLS_MODEL (base))
30284 case TLS_MODEL_LOCAL_EXEC:
30285 fputs ("@le", file);
30287 case TLS_MODEL_INITIAL_EXEC:
30288 fputs ("@ie", file);
30290 /* Use global-dynamic for local-dynamic. */
30291 case TLS_MODEL_GLOBAL_DYNAMIC:
30292 case TLS_MODEL_LOCAL_DYNAMIC:
30294 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
30295 fputs ("\t.tc .", file);
30296 RS6000_OUTPUT_BASENAME (file, name);
30297 fputs ("[TC],", file);
30298 output_addr_const (file, x);
30299 fputs ("@m", file);
30302 gcc_unreachable ();
30310 /* Output an assembler pseudo-op to write an ASCII string of N characters
30311 starting at P to FILE.
30313 On the RS/6000, we have to do this using the .byte operation and
30314 write out special characters outside the quoted string.
30315 Also, the assembler is broken; very long strings are truncated,
30316 so we must artificially break them up early. */
30319 output_ascii (FILE *file, const char *p, int n)
30322 int i, count_string;
30323 const char *for_string = "\t.byte \"";
30324 const char *for_decimal = "\t.byte ";
30325 const char *to_close = NULL;
30328 for (i = 0; i < n; i++)
30331 if (c >= ' ' && c < 0177)
30334 fputs (for_string, file);
30337 /* Write two quotes to get one. */
30345 for_decimal = "\"\n\t.byte ";
30349 if (count_string >= 512)
30351 fputs (to_close, file);
30353 for_string = "\t.byte \"";
30354 for_decimal = "\t.byte ";
30362 fputs (for_decimal, file);
30363 fprintf (file, "%d", c);
30365 for_string = "\n\t.byte \"";
30366 for_decimal = ", ";
30372 /* Now close the string if we have written one. Then end the line. */
30374 fputs (to_close, file);
30377 /* Generate a unique section name for FILENAME for a section type
30378 represented by SECTION_DESC. Output goes into BUF.
30380 SECTION_DESC can be any string, as long as it is different for each
30381 possible section type.
30383 We name the section in the same manner as xlc. The name begins with an
30384 underscore followed by the filename (after stripping any leading directory
30385 names) with the last period replaced by the string SECTION_DESC. If
30386 FILENAME does not contain a period, SECTION_DESC is appended to the end of
30390 rs6000_gen_section_name (char **buf, const char *filename,
30391 const char *section_desc)
30393 const char *q, *after_last_slash, *last_period = 0;
30397 after_last_slash = filename;
30398 for (q = filename; *q; q++)
30401 after_last_slash = q + 1;
30402 else if (*q == '.')
30406 len = strlen (after_last_slash) + strlen (section_desc) + 2;
30407 *buf = (char *) xmalloc (len);
30412 for (q = after_last_slash; *q; q++)
30414 if (q == last_period)
30416 strcpy (p, section_desc);
30417 p += strlen (section_desc);
30421 else if (ISALNUM (*q))
30425 if (last_period == 0)
30426 strcpy (p, section_desc);
30431 /* Emit profile function. */
30434 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
30436 /* Non-standard profiling for kernels, which just saves LR then calls
30437 _mcount without worrying about arg saves. The idea is to change
30438 the function prologue as little as possible as it isn't easy to
30439 account for arg save/restore code added just for _mcount. */
30440 if (TARGET_PROFILE_KERNEL)
30443 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
30445 #ifndef NO_PROFILE_COUNTERS
30446 # define NO_PROFILE_COUNTERS 0
30448 if (NO_PROFILE_COUNTERS)
30449 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
30450 LCT_NORMAL, VOIDmode);
30454 const char *label_name;
30457 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30458 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
30459 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
30461 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
30462 LCT_NORMAL, VOIDmode, fun, Pmode);
30465 else if (DEFAULT_ABI == ABI_DARWIN)
30467 const char *mcount_name = RS6000_MCOUNT;
30468 int caller_addr_regno = LR_REGNO;
30470 /* Be conservative and always set this, at least for now. */
30471 crtl->uses_pic_offset_table = 1;
30474 /* For PIC code, set up a stub and collect the caller's address
30475 from r0, which is where the prologue puts it. */
30476 if (MACHOPIC_INDIRECT
30477 && crtl->uses_pic_offset_table)
30478 caller_addr_regno = 0;
30480 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
30481 LCT_NORMAL, VOIDmode,
30482 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
30486 /* Write function profiler code. */
30489 output_function_profiler (FILE *file, int labelno)
30493 switch (DEFAULT_ABI)
30496 gcc_unreachable ();
30501 warning (0, "no profiling of 64-bit code for this ABI");
30504 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30505 fprintf (file, "\tmflr %s\n", reg_names[0]);
30506 if (NO_PROFILE_COUNTERS)
30508 asm_fprintf (file, "\tstw %s,4(%s)\n",
30509 reg_names[0], reg_names[1]);
30511 else if (TARGET_SECURE_PLT && flag_pic)
30513 if (TARGET_LINK_STACK)
30516 get_ppc476_thunk_name (name);
30517 asm_fprintf (file, "\tbl %s\n", name);
30520 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
30521 asm_fprintf (file, "\tstw %s,4(%s)\n",
30522 reg_names[0], reg_names[1]);
30523 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30524 asm_fprintf (file, "\taddis %s,%s,",
30525 reg_names[12], reg_names[12]);
30526 assemble_name (file, buf);
30527 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
30528 assemble_name (file, buf);
30529 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
30531 else if (flag_pic == 1)
30533 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
30534 asm_fprintf (file, "\tstw %s,4(%s)\n",
30535 reg_names[0], reg_names[1]);
30536 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30537 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
30538 assemble_name (file, buf);
30539 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
30541 else if (flag_pic > 1)
30543 asm_fprintf (file, "\tstw %s,4(%s)\n",
30544 reg_names[0], reg_names[1]);
30545 /* Now, we need to get the address of the label. */
30546 if (TARGET_LINK_STACK)
30549 get_ppc476_thunk_name (name);
30550 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
30551 assemble_name (file, buf);
30552 fputs ("-.\n1:", file);
30553 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30554 asm_fprintf (file, "\taddi %s,%s,4\n",
30555 reg_names[11], reg_names[11]);
30559 fputs ("\tbcl 20,31,1f\n\t.long ", file);
30560 assemble_name (file, buf);
30561 fputs ("-.\n1:", file);
30562 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30564 asm_fprintf (file, "\tlwz %s,0(%s)\n",
30565 reg_names[0], reg_names[11]);
30566 asm_fprintf (file, "\tadd %s,%s,%s\n",
30567 reg_names[0], reg_names[0], reg_names[11]);
30571 asm_fprintf (file, "\tlis %s,", reg_names[12]);
30572 assemble_name (file, buf);
30573 fputs ("@ha\n", file);
30574 asm_fprintf (file, "\tstw %s,4(%s)\n",
30575 reg_names[0], reg_names[1]);
30576 asm_fprintf (file, "\tla %s,", reg_names[0]);
30577 assemble_name (file, buf);
30578 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
30581 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30582 fprintf (file, "\tbl %s%s\n",
30583 RS6000_MCOUNT, flag_pic ? "@plt" : "");
30589 /* Don't do anything, done in output_profile_hook (). */
30596 /* The following variable value is the last issued insn. */
30598 static rtx_insn *last_scheduled_insn;
30600 /* The following variable helps to balance issuing of load and
30601 store instructions */
30603 static int load_store_pendulum;
30605 /* The following variable helps pair divide insns during scheduling. */
30606 static int divide_cnt;
30607 /* The following variable helps pair and alternate vector and vector load
30608 insns during scheduling. */
30609 static int vec_pairing;
30612 /* Power4 load update and store update instructions are cracked into a
30613 load or store and an integer insn which are executed in the same cycle.
30614 Branches have their own dispatch slot which does not count against the
30615 GCC issue rate, but it changes the program flow so there are no other
30616 instructions to issue in this cycle. */
30619 rs6000_variable_issue_1 (rtx_insn *insn, int more)
30621 last_scheduled_insn = insn;
30622 if (GET_CODE (PATTERN (insn)) == USE
30623 || GET_CODE (PATTERN (insn)) == CLOBBER)
30625 cached_can_issue_more = more;
30626 return cached_can_issue_more;
30629 if (insn_terminates_group_p (insn, current_group))
30631 cached_can_issue_more = 0;
30632 return cached_can_issue_more;
30635 /* If no reservation, but reach here */
30636 if (recog_memoized (insn) < 0)
30639 if (rs6000_sched_groups)
30641 if (is_microcoded_insn (insn))
30642 cached_can_issue_more = 0;
30643 else if (is_cracked_insn (insn))
30644 cached_can_issue_more = more > 2 ? more - 2 : 0;
30646 cached_can_issue_more = more - 1;
30648 return cached_can_issue_more;
30651 if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
30654 cached_can_issue_more = more - 1;
30655 return cached_can_issue_more;
30659 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
30661 int r = rs6000_variable_issue_1 (insn, more);
30663 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
30667 /* Adjust the cost of a scheduling dependency. Return the new cost of
30668 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30671 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
30674 enum attr_type attr_type;
30676 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
30683 /* Data dependency; DEP_INSN writes a register that INSN reads
30684 some cycles later. */
30686 /* Separate a load from a narrower, dependent store. */
30687 if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9)
30688 && GET_CODE (PATTERN (insn)) == SET
30689 && GET_CODE (PATTERN (dep_insn)) == SET
30690 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
30691 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
30692 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
30693 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
30696 attr_type = get_attr_type (insn);
30701 /* Tell the first scheduling pass about the latency between
30702 a mtctr and bctr (and mtlr and br/blr). The first
30703 scheduling pass will not know about this latency since
30704 the mtctr instruction, which has the latency associated
30705 to it, will be generated by reload. */
30708 /* Leave some extra cycles between a compare and its
30709 dependent branch, to inhibit expensive mispredicts. */
30710 if ((rs6000_tune == PROCESSOR_PPC603
30711 || rs6000_tune == PROCESSOR_PPC604
30712 || rs6000_tune == PROCESSOR_PPC604e
30713 || rs6000_tune == PROCESSOR_PPC620
30714 || rs6000_tune == PROCESSOR_PPC630
30715 || rs6000_tune == PROCESSOR_PPC750
30716 || rs6000_tune == PROCESSOR_PPC7400
30717 || rs6000_tune == PROCESSOR_PPC7450
30718 || rs6000_tune == PROCESSOR_PPCE5500
30719 || rs6000_tune == PROCESSOR_PPCE6500
30720 || rs6000_tune == PROCESSOR_POWER4
30721 || rs6000_tune == PROCESSOR_POWER5
30722 || rs6000_tune == PROCESSOR_POWER7
30723 || rs6000_tune == PROCESSOR_POWER8
30724 || rs6000_tune == PROCESSOR_POWER9
30725 || rs6000_tune == PROCESSOR_CELL)
30726 && recog_memoized (dep_insn)
30727 && (INSN_CODE (dep_insn) >= 0))
30729 switch (get_attr_type (dep_insn))
30732 case TYPE_FPCOMPARE:
30733 case TYPE_CR_LOGICAL:
30737 if (get_attr_dot (dep_insn) == DOT_YES)
30742 if (get_attr_dot (dep_insn) == DOT_YES
30743 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
30754 if ((rs6000_tune == PROCESSOR_POWER6)
30755 && recog_memoized (dep_insn)
30756 && (INSN_CODE (dep_insn) >= 0))
30759 if (GET_CODE (PATTERN (insn)) != SET)
30760 /* If this happens, we have to extend this to schedule
30761 optimally. Return default for now. */
30764 /* Adjust the cost for the case where the value written
30765 by a fixed point operation is used as the address
30766 gen value on a store. */
30767 switch (get_attr_type (dep_insn))
30772 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30773 return get_attr_sign_extend (dep_insn)
30774 == SIGN_EXTEND_YES ? 6 : 4;
30779 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30780 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30790 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30798 if (get_attr_update (dep_insn) == UPDATE_YES
30799 && ! rs6000_store_data_bypass_p (dep_insn, insn))
30805 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30811 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30812 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30822 if ((rs6000_tune == PROCESSOR_POWER6)
30823 && recog_memoized (dep_insn)
30824 && (INSN_CODE (dep_insn) >= 0))
30827 /* Adjust the cost for the case where the value written
30828 by a fixed point instruction is used within the address
30829 gen portion of a subsequent load(u)(x) */
30830 switch (get_attr_type (dep_insn))
30835 if (set_to_load_agen (dep_insn, insn))
30836 return get_attr_sign_extend (dep_insn)
30837 == SIGN_EXTEND_YES ? 6 : 4;
30842 if (set_to_load_agen (dep_insn, insn))
30843 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30853 if (set_to_load_agen (dep_insn, insn))
30861 if (get_attr_update (dep_insn) == UPDATE_YES
30862 && set_to_load_agen (dep_insn, insn))
30868 if (set_to_load_agen (dep_insn, insn))
30874 if (set_to_load_agen (dep_insn, insn))
30875 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30885 if ((rs6000_tune == PROCESSOR_POWER6)
30886 && get_attr_update (insn) == UPDATE_NO
30887 && recog_memoized (dep_insn)
30888 && (INSN_CODE (dep_insn) >= 0)
30889 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30896 /* Fall out to return default cost. */
30900 case REG_DEP_OUTPUT:
30901 /* Output dependency; DEP_INSN writes a register that INSN writes some
30903 if ((rs6000_tune == PROCESSOR_POWER6)
30904 && recog_memoized (dep_insn)
30905 && (INSN_CODE (dep_insn) >= 0))
30907 attr_type = get_attr_type (insn);
30912 case TYPE_FPSIMPLE:
30913 if (get_attr_type (dep_insn) == TYPE_FP
30914 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30918 if (get_attr_update (insn) == UPDATE_NO
30919 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30926 /* Fall through, no cost for output dependency. */
30930 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30935 gcc_unreachable ();
30941 /* Debug version of rs6000_adjust_cost. */
30944 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30945 int cost, unsigned int dw)
30947 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30955 default: dep = "unknown depencency"; break;
30956 case REG_DEP_TRUE: dep = "data dependency"; break;
30957 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30958 case REG_DEP_ANTI: dep = "anti depencency"; break;
30962 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30963 "%s, insn:\n", ret, cost, dep);
30971 /* The function returns a true if INSN is microcoded.
30972 Return false otherwise. */
30975 is_microcoded_insn (rtx_insn *insn)
30977 if (!insn || !NONDEBUG_INSN_P (insn)
30978 || GET_CODE (PATTERN (insn)) == USE
30979 || GET_CODE (PATTERN (insn)) == CLOBBER)
30982 if (rs6000_tune == PROCESSOR_CELL)
30983 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
30985 if (rs6000_sched_groups
30986 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30988 enum attr_type type = get_attr_type (insn);
30989 if ((type == TYPE_LOAD
30990 && get_attr_update (insn) == UPDATE_YES
30991 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
30992 || ((type == TYPE_LOAD || type == TYPE_STORE)
30993 && get_attr_update (insn) == UPDATE_YES
30994 && get_attr_indexed (insn) == INDEXED_YES)
30995 || type == TYPE_MFCR)
31002 /* The function returns true if INSN is cracked into 2 instructions
31003 by the processor (and therefore occupies 2 issue slots). */
31006 is_cracked_insn (rtx_insn *insn)
31008 if (!insn || !NONDEBUG_INSN_P (insn)
31009 || GET_CODE (PATTERN (insn)) == USE
31010 || GET_CODE (PATTERN (insn)) == CLOBBER)
31013 if (rs6000_sched_groups
31014 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
31016 enum attr_type type = get_attr_type (insn);
31017 if ((type == TYPE_LOAD
31018 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31019 && get_attr_update (insn) == UPDATE_NO)
31020 || (type == TYPE_LOAD
31021 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
31022 && get_attr_update (insn) == UPDATE_YES
31023 && get_attr_indexed (insn) == INDEXED_NO)
31024 || (type == TYPE_STORE
31025 && get_attr_update (insn) == UPDATE_YES
31026 && get_attr_indexed (insn) == INDEXED_NO)
31027 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
31028 && get_attr_update (insn) == UPDATE_YES)
31029 || (type == TYPE_CR_LOGICAL
31030 && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
31031 || (type == TYPE_EXTS
31032 && get_attr_dot (insn) == DOT_YES)
31033 || (type == TYPE_SHIFT
31034 && get_attr_dot (insn) == DOT_YES
31035 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
31036 || (type == TYPE_MUL
31037 && get_attr_dot (insn) == DOT_YES)
31038 || type == TYPE_DIV
31039 || (type == TYPE_INSERT
31040 && get_attr_size (insn) == SIZE_32))
31047 /* The function returns true if INSN can be issued only from
31048 the branch slot. */
31051 is_branch_slot_insn (rtx_insn *insn)
31053 if (!insn || !NONDEBUG_INSN_P (insn)
31054 || GET_CODE (PATTERN (insn)) == USE
31055 || GET_CODE (PATTERN (insn)) == CLOBBER)
31058 if (rs6000_sched_groups)
31060 enum attr_type type = get_attr_type (insn);
31061 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
31069 /* The function returns true if out_inst sets a value that is
31070 used in the address generation computation of in_insn */
31072 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
31074 rtx out_set, in_set;
31076 /* For performance reasons, only handle the simple case where
31077 both loads are a single_set. */
31078 out_set = single_set (out_insn);
31081 in_set = single_set (in_insn);
31083 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
31089 /* Try to determine base/offset/size parts of the given MEM.
31090 Return true if successful, false if all the values couldn't
31093 This function only looks for REG or REG+CONST address forms.
31094 REG+REG address form will return false. */
31097 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
31098 HOST_WIDE_INT *size)
31101 if MEM_SIZE_KNOWN_P (mem)
31102 *size = MEM_SIZE (mem);
31106 addr_rtx = (XEXP (mem, 0));
31107 if (GET_CODE (addr_rtx) == PRE_MODIFY)
31108 addr_rtx = XEXP (addr_rtx, 1);
31111 while (GET_CODE (addr_rtx) == PLUS
31112 && CONST_INT_P (XEXP (addr_rtx, 1)))
31114 *offset += INTVAL (XEXP (addr_rtx, 1));
31115 addr_rtx = XEXP (addr_rtx, 0);
31117 if (!REG_P (addr_rtx))
31124 /* The function returns true if the target storage location of
31125 mem1 is adjacent to the target storage location of mem2 */
31126 /* Return 1 if memory locations are adjacent. */
31129 adjacent_mem_locations (rtx mem1, rtx mem2)
31132 HOST_WIDE_INT off1, size1, off2, size2;
31134 if (get_memref_parts (mem1, ®1, &off1, &size1)
31135 && get_memref_parts (mem2, ®2, &off2, &size2))
31136 return ((REGNO (reg1) == REGNO (reg2))
31137 && ((off1 + size1 == off2)
31138 || (off2 + size2 == off1)));
31143 /* This function returns true if it can be determined that the two MEM
31144 locations overlap by at least 1 byte based on base reg/offset/size. */
31147 mem_locations_overlap (rtx mem1, rtx mem2)
31150 HOST_WIDE_INT off1, size1, off2, size2;
31152 if (get_memref_parts (mem1, ®1, &off1, &size1)
31153 && get_memref_parts (mem2, ®2, &off2, &size2))
31154 return ((REGNO (reg1) == REGNO (reg2))
31155 && (((off1 <= off2) && (off1 + size1 > off2))
31156 || ((off2 <= off1) && (off2 + size2 > off1))));
31161 /* A C statement (sans semicolon) to update the integer scheduling
31162 priority INSN_PRIORITY (INSN). Increase the priority to execute the
31163 INSN earlier, reduce the priority to execute INSN later. Do not
31164 define this macro if you do not need to adjust the scheduling
31165 priorities of insns. */
31168 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
31170 rtx load_mem, str_mem;
31171 /* On machines (like the 750) which have asymmetric integer units,
31172 where one integer unit can do multiply and divides and the other
31173 can't, reduce the priority of multiply/divide so it is scheduled
31174 before other integer operations. */
31177 if (! INSN_P (insn))
31180 if (GET_CODE (PATTERN (insn)) == USE)
31183 switch (rs6000_tune) {
31184 case PROCESSOR_PPC750:
31185 switch (get_attr_type (insn))
31192 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
31193 priority, priority);
31194 if (priority >= 0 && priority < 0x01000000)
31201 if (insn_must_be_first_in_group (insn)
31202 && reload_completed
31203 && current_sched_info->sched_max_insns_priority
31204 && rs6000_sched_restricted_insns_priority)
31207 /* Prioritize insns that can be dispatched only in the first
31209 if (rs6000_sched_restricted_insns_priority == 1)
31210 /* Attach highest priority to insn. This means that in
31211 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
31212 precede 'priority' (critical path) considerations. */
31213 return current_sched_info->sched_max_insns_priority;
31214 else if (rs6000_sched_restricted_insns_priority == 2)
31215 /* Increase priority of insn by a minimal amount. This means that in
31216 haifa-sched.c:ready_sort(), only 'priority' (critical path)
31217 considerations precede dispatch-slot restriction considerations. */
31218 return (priority + 1);
31221 if (rs6000_tune == PROCESSOR_POWER6
31222 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
31223 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
31224 /* Attach highest priority to insn if the scheduler has just issued two
31225 stores and this instruction is a load, or two loads and this instruction
31226 is a store. Power6 wants loads and stores scheduled alternately
31228 return current_sched_info->sched_max_insns_priority;
31233 /* Return true if the instruction is nonpipelined on the Cell. */
31235 is_nonpipeline_insn (rtx_insn *insn)
31237 enum attr_type type;
31238 if (!insn || !NONDEBUG_INSN_P (insn)
31239 || GET_CODE (PATTERN (insn)) == USE
31240 || GET_CODE (PATTERN (insn)) == CLOBBER)
31243 type = get_attr_type (insn);
31244 if (type == TYPE_MUL
31245 || type == TYPE_DIV
31246 || type == TYPE_SDIV
31247 || type == TYPE_DDIV
31248 || type == TYPE_SSQRT
31249 || type == TYPE_DSQRT
31250 || type == TYPE_MFCR
31251 || type == TYPE_MFCRF
31252 || type == TYPE_MFJMPR)
31260 /* Return how many instructions the machine can issue per cycle. */
31263 rs6000_issue_rate (void)
31265 /* Unless scheduling for register pressure, use issue rate of 1 for
31266 first scheduling pass to decrease degradation. */
31267 if (!reload_completed && !flag_sched_pressure)
31270 switch (rs6000_tune) {
31271 case PROCESSOR_RS64A:
31272 case PROCESSOR_PPC601: /* ? */
31273 case PROCESSOR_PPC7450:
31275 case PROCESSOR_PPC440:
31276 case PROCESSOR_PPC603:
31277 case PROCESSOR_PPC750:
31278 case PROCESSOR_PPC7400:
31279 case PROCESSOR_PPC8540:
31280 case PROCESSOR_PPC8548:
31281 case PROCESSOR_CELL:
31282 case PROCESSOR_PPCE300C2:
31283 case PROCESSOR_PPCE300C3:
31284 case PROCESSOR_PPCE500MC:
31285 case PROCESSOR_PPCE500MC64:
31286 case PROCESSOR_PPCE5500:
31287 case PROCESSOR_PPCE6500:
31288 case PROCESSOR_TITAN:
31290 case PROCESSOR_PPC476:
31291 case PROCESSOR_PPC604:
31292 case PROCESSOR_PPC604e:
31293 case PROCESSOR_PPC620:
31294 case PROCESSOR_PPC630:
31296 case PROCESSOR_POWER4:
31297 case PROCESSOR_POWER5:
31298 case PROCESSOR_POWER6:
31299 case PROCESSOR_POWER7:
31301 case PROCESSOR_POWER8:
31303 case PROCESSOR_POWER9:
31310 /* Return how many instructions to look ahead for better insn
31314 rs6000_use_sched_lookahead (void)
31316 switch (rs6000_tune)
31318 case PROCESSOR_PPC8540:
31319 case PROCESSOR_PPC8548:
31322 case PROCESSOR_CELL:
31323 return (reload_completed ? 8 : 0);
31330 /* We are choosing insn from the ready queue. Return zero if INSN can be
31333 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
31335 if (ready_index == 0)
31338 if (rs6000_tune != PROCESSOR_CELL)
31341 gcc_assert (insn != NULL_RTX && INSN_P (insn));
31343 if (!reload_completed
31344 || is_nonpipeline_insn (insn)
31345 || is_microcoded_insn (insn))
31351 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
31352 and return true. */
31355 find_mem_ref (rtx pat, rtx *mem_ref)
31360 /* stack_tie does not produce any real memory traffic. */
31361 if (tie_operand (pat, VOIDmode))
31364 if (GET_CODE (pat) == MEM)
31370 /* Recursively process the pattern. */
31371 fmt = GET_RTX_FORMAT (GET_CODE (pat));
31373 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
31377 if (find_mem_ref (XEXP (pat, i), mem_ref))
31380 else if (fmt[i] == 'E')
31381 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
31383 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
31391 /* Determine if PAT is a PATTERN of a load insn. */
31394 is_load_insn1 (rtx pat, rtx *load_mem)
31396 if (!pat || pat == NULL_RTX)
31399 if (GET_CODE (pat) == SET)
31400 return find_mem_ref (SET_SRC (pat), load_mem);
31402 if (GET_CODE (pat) == PARALLEL)
31406 for (i = 0; i < XVECLEN (pat, 0); i++)
31407 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
31414 /* Determine if INSN loads from memory. */
31417 is_load_insn (rtx insn, rtx *load_mem)
31419 if (!insn || !INSN_P (insn))
31425 return is_load_insn1 (PATTERN (insn), load_mem);
31428 /* Determine if PAT is a PATTERN of a store insn. */
31431 is_store_insn1 (rtx pat, rtx *str_mem)
31433 if (!pat || pat == NULL_RTX)
31436 if (GET_CODE (pat) == SET)
31437 return find_mem_ref (SET_DEST (pat), str_mem);
31439 if (GET_CODE (pat) == PARALLEL)
31443 for (i = 0; i < XVECLEN (pat, 0); i++)
31444 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
31451 /* Determine if INSN stores to memory. */
31454 is_store_insn (rtx insn, rtx *str_mem)
31456 if (!insn || !INSN_P (insn))
31459 return is_store_insn1 (PATTERN (insn), str_mem);
31462 /* Return whether TYPE is a Power9 pairable vector instruction type. */
31465 is_power9_pairable_vec_type (enum attr_type type)
31469 case TYPE_VECSIMPLE:
31470 case TYPE_VECCOMPLEX:
31474 case TYPE_VECFLOAT:
31476 case TYPE_VECDOUBLE:
31484 /* Returns whether the dependence between INSN and NEXT is considered
31485 costly by the given target. */
31488 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
31492 rtx load_mem, str_mem;
31494 /* If the flag is not enabled - no dependence is considered costly;
31495 allow all dependent insns in the same group.
31496 This is the most aggressive option. */
31497 if (rs6000_sched_costly_dep == no_dep_costly)
31500 /* If the flag is set to 1 - a dependence is always considered costly;
31501 do not allow dependent instructions in the same group.
31502 This is the most conservative option. */
31503 if (rs6000_sched_costly_dep == all_deps_costly)
31506 insn = DEP_PRO (dep);
31507 next = DEP_CON (dep);
31509 if (rs6000_sched_costly_dep == store_to_load_dep_costly
31510 && is_load_insn (next, &load_mem)
31511 && is_store_insn (insn, &str_mem))
31512 /* Prevent load after store in the same group. */
31515 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
31516 && is_load_insn (next, &load_mem)
31517 && is_store_insn (insn, &str_mem)
31518 && DEP_TYPE (dep) == REG_DEP_TRUE
31519 && mem_locations_overlap(str_mem, load_mem))
31520 /* Prevent load after store in the same group if it is a true
31524 /* The flag is set to X; dependences with latency >= X are considered costly,
31525 and will not be scheduled in the same group. */
31526 if (rs6000_sched_costly_dep <= max_dep_latency
31527 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
31533 /* Return the next insn after INSN that is found before TAIL is reached,
31534 skipping any "non-active" insns - insns that will not actually occupy
31535 an issue slot. Return NULL_RTX if such an insn is not found. */
31538 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
31540 if (insn == NULL_RTX || insn == tail)
31545 insn = NEXT_INSN (insn);
31546 if (insn == NULL_RTX || insn == tail)
31550 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
31551 || (NONJUMP_INSN_P (insn)
31552 && GET_CODE (PATTERN (insn)) != USE
31553 && GET_CODE (PATTERN (insn)) != CLOBBER
31554 && INSN_CODE (insn) != CODE_FOR_stack_tie))
31560 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31563 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
31568 enum attr_type type, type2;
31570 type = get_attr_type (last_scheduled_insn);
31572 /* Try to issue fixed point divides back-to-back in pairs so they will be
31573 routed to separate execution units and execute in parallel. */
31574 if (type == TYPE_DIV && divide_cnt == 0)
31576 /* First divide has been scheduled. */
31579 /* Scan the ready list looking for another divide, if found move it
31580 to the end of the list so it is chosen next. */
31584 if (recog_memoized (ready[pos]) >= 0
31585 && get_attr_type (ready[pos]) == TYPE_DIV)
31588 for (i = pos; i < lastpos; i++)
31589 ready[i] = ready[i + 1];
31590 ready[lastpos] = tmp;
31598 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31601 /* The best dispatch throughput for vector and vector load insns can be
31602 achieved by interleaving a vector and vector load such that they'll
31603 dispatch to the same superslice. If this pairing cannot be achieved
31604 then it is best to pair vector insns together and vector load insns
31607 To aid in this pairing, vec_pairing maintains the current state with
31608 the following values:
31610 0 : Initial state, no vecload/vector pairing has been started.
31612 1 : A vecload or vector insn has been issued and a candidate for
31613 pairing has been found and moved to the end of the ready
31615 if (type == TYPE_VECLOAD)
31617 /* Issued a vecload. */
31618 if (vec_pairing == 0)
31620 int vecload_pos = -1;
31621 /* We issued a single vecload, look for a vector insn to pair it
31622 with. If one isn't found, try to pair another vecload. */
31626 if (recog_memoized (ready[pos]) >= 0)
31628 type2 = get_attr_type (ready[pos]);
31629 if (is_power9_pairable_vec_type (type2))
31631 /* Found a vector insn to pair with, move it to the
31632 end of the ready list so it is scheduled next. */
31634 for (i = pos; i < lastpos; i++)
31635 ready[i] = ready[i + 1];
31636 ready[lastpos] = tmp;
31638 return cached_can_issue_more;
31640 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
31641 /* Remember position of first vecload seen. */
31646 if (vecload_pos >= 0)
31648 /* Didn't find a vector to pair with but did find a vecload,
31649 move it to the end of the ready list. */
31650 tmp = ready[vecload_pos];
31651 for (i = vecload_pos; i < lastpos; i++)
31652 ready[i] = ready[i + 1];
31653 ready[lastpos] = tmp;
31655 return cached_can_issue_more;
31659 else if (is_power9_pairable_vec_type (type))
31661 /* Issued a vector operation. */
31662 if (vec_pairing == 0)
31665 /* We issued a single vector insn, look for a vecload to pair it
31666 with. If one isn't found, try to pair another vector. */
31670 if (recog_memoized (ready[pos]) >= 0)
31672 type2 = get_attr_type (ready[pos]);
31673 if (type2 == TYPE_VECLOAD)
31675 /* Found a vecload insn to pair with, move it to the
31676 end of the ready list so it is scheduled next. */
31678 for (i = pos; i < lastpos; i++)
31679 ready[i] = ready[i + 1];
31680 ready[lastpos] = tmp;
31682 return cached_can_issue_more;
31684 else if (is_power9_pairable_vec_type (type2)
31686 /* Remember position of first vector insn seen. */
31693 /* Didn't find a vecload to pair with but did find a vector
31694 insn, move it to the end of the ready list. */
31695 tmp = ready[vec_pos];
31696 for (i = vec_pos; i < lastpos; i++)
31697 ready[i] = ready[i + 1];
31698 ready[lastpos] = tmp;
31700 return cached_can_issue_more;
31705 /* We've either finished a vec/vecload pair, couldn't find an insn to
31706 continue the current pair, or the last insn had nothing to do with
31707 with pairing. In any case, reset the state. */
31711 return cached_can_issue_more;
31714 /* We are about to begin issuing insns for this clock cycle. */
31717 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
31718 rtx_insn **ready ATTRIBUTE_UNUSED,
31719 int *pn_ready ATTRIBUTE_UNUSED,
31720 int clock_var ATTRIBUTE_UNUSED)
31722 int n_ready = *pn_ready;
31725 fprintf (dump, "// rs6000_sched_reorder :\n");
31727 /* Reorder the ready list, if the second to last ready insn
31728 is a nonepipeline insn. */
31729 if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
31731 if (is_nonpipeline_insn (ready[n_ready - 1])
31732 && (recog_memoized (ready[n_ready - 2]) > 0))
31733 /* Simply swap first two insns. */
31734 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
31737 if (rs6000_tune == PROCESSOR_POWER6)
31738 load_store_pendulum = 0;
31740 return rs6000_issue_rate ();
31743 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31746 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
31747 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
31750 fprintf (dump, "// rs6000_sched_reorder2 :\n");
31752 /* For Power6, we need to handle some special cases to try and keep the
31753 store queue from overflowing and triggering expensive flushes.
31755 This code monitors how load and store instructions are being issued
31756 and skews the ready list one way or the other to increase the likelihood
31757 that a desired instruction is issued at the proper time.
31759 A couple of things are done. First, we maintain a "load_store_pendulum"
31760 to track the current state of load/store issue.
31762 - If the pendulum is at zero, then no loads or stores have been
31763 issued in the current cycle so we do nothing.
31765 - If the pendulum is 1, then a single load has been issued in this
31766 cycle and we attempt to locate another load in the ready list to
31769 - If the pendulum is -2, then two stores have already been
31770 issued in this cycle, so we increase the priority of the first load
31771 in the ready list to increase it's likelihood of being chosen first
31774 - If the pendulum is -1, then a single store has been issued in this
31775 cycle and we attempt to locate another store in the ready list to
31776 issue with it, preferring a store to an adjacent memory location to
31777 facilitate store pairing in the store queue.
31779 - If the pendulum is 2, then two loads have already been
31780 issued in this cycle, so we increase the priority of the first store
31781 in the ready list to increase it's likelihood of being chosen first
31784 - If the pendulum < -2 or > 2, then do nothing.
31786 Note: This code covers the most common scenarios. There exist non
31787 load/store instructions which make use of the LSU and which
31788 would need to be accounted for to strictly model the behavior
31789 of the machine. Those instructions are currently unaccounted
31790 for to help minimize compile time overhead of this code.
31792 if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
31797 rtx load_mem, str_mem;
31799 if (is_store_insn (last_scheduled_insn, &str_mem))
31800 /* Issuing a store, swing the load_store_pendulum to the left */
31801 load_store_pendulum--;
31802 else if (is_load_insn (last_scheduled_insn, &load_mem))
31803 /* Issuing a load, swing the load_store_pendulum to the right */
31804 load_store_pendulum++;
31806 return cached_can_issue_more;
31808 /* If the pendulum is balanced, or there is only one instruction on
31809 the ready list, then all is well, so return. */
31810 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
31811 return cached_can_issue_more;
31813 if (load_store_pendulum == 1)
31815 /* A load has been issued in this cycle. Scan the ready list
31816 for another load to issue with it */
31821 if (is_load_insn (ready[pos], &load_mem))
31823 /* Found a load. Move it to the head of the ready list,
31824 and adjust it's priority so that it is more likely to
31827 for (i=pos; i<*pn_ready-1; i++)
31828 ready[i] = ready[i + 1];
31829 ready[*pn_ready-1] = tmp;
31831 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31832 INSN_PRIORITY (tmp)++;
31838 else if (load_store_pendulum == -2)
31840 /* Two stores have been issued in this cycle. Increase the
31841 priority of the first load in the ready list to favor it for
31842 issuing in the next cycle. */
31847 if (is_load_insn (ready[pos], &load_mem)
31849 && INSN_PRIORITY_KNOWN (ready[pos]))
31851 INSN_PRIORITY (ready[pos])++;
31853 /* Adjust the pendulum to account for the fact that a load
31854 was found and increased in priority. This is to prevent
31855 increasing the priority of multiple loads */
31856 load_store_pendulum--;
31863 else if (load_store_pendulum == -1)
31865 /* A store has been issued in this cycle. Scan the ready list for
31866 another store to issue with it, preferring a store to an adjacent
31868 int first_store_pos = -1;
31874 if (is_store_insn (ready[pos], &str_mem))
31877 /* Maintain the index of the first store found on the
31879 if (first_store_pos == -1)
31880 first_store_pos = pos;
31882 if (is_store_insn (last_scheduled_insn, &str_mem2)
31883 && adjacent_mem_locations (str_mem, str_mem2))
31885 /* Found an adjacent store. Move it to the head of the
31886 ready list, and adjust it's priority so that it is
31887 more likely to stay there */
31889 for (i=pos; i<*pn_ready-1; i++)
31890 ready[i] = ready[i + 1];
31891 ready[*pn_ready-1] = tmp;
31893 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31894 INSN_PRIORITY (tmp)++;
31896 first_store_pos = -1;
31904 if (first_store_pos >= 0)
31906 /* An adjacent store wasn't found, but a non-adjacent store was,
31907 so move the non-adjacent store to the front of the ready
31908 list, and adjust its priority so that it is more likely to
31910 tmp = ready[first_store_pos];
31911 for (i=first_store_pos; i<*pn_ready-1; i++)
31912 ready[i] = ready[i + 1];
31913 ready[*pn_ready-1] = tmp;
31914 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31915 INSN_PRIORITY (tmp)++;
31918 else if (load_store_pendulum == 2)
31920 /* Two loads have been issued in this cycle. Increase the priority
31921 of the first store in the ready list to favor it for issuing in
31927 if (is_store_insn (ready[pos], &str_mem)
31929 && INSN_PRIORITY_KNOWN (ready[pos]))
31931 INSN_PRIORITY (ready[pos])++;
31933 /* Adjust the pendulum to account for the fact that a store
31934 was found and increased in priority. This is to prevent
31935 increasing the priority of multiple stores */
31936 load_store_pendulum++;
31945 /* Do Power9 dependent reordering if necessary. */
31946 if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
31947 && recog_memoized (last_scheduled_insn) >= 0)
31948 return power9_sched_reorder2 (ready, *pn_ready - 1);
31950 return cached_can_issue_more;
31953 /* Return whether the presence of INSN causes a dispatch group termination
31954 of group WHICH_GROUP.
31956 If WHICH_GROUP == current_group, this function will return true if INSN
31957 causes the termination of the current group (i.e, the dispatch group to
31958 which INSN belongs). This means that INSN will be the last insn in the
31959 group it belongs to.
31961 If WHICH_GROUP == previous_group, this function will return true if INSN
31962 causes the termination of the previous group (i.e, the dispatch group that
31963 precedes the group to which INSN belongs). This means that INSN will be
31964 the first insn in the group it belongs to). */
31967 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31974 first = insn_must_be_first_in_group (insn);
31975 last = insn_must_be_last_in_group (insn);
31980 if (which_group == current_group)
31982 else if (which_group == previous_group)
31990 insn_must_be_first_in_group (rtx_insn *insn)
31992 enum attr_type type;
31996 || DEBUG_INSN_P (insn)
31997 || GET_CODE (PATTERN (insn)) == USE
31998 || GET_CODE (PATTERN (insn)) == CLOBBER)
32001 switch (rs6000_tune)
32003 case PROCESSOR_POWER5:
32004 if (is_cracked_insn (insn))
32007 case PROCESSOR_POWER4:
32008 if (is_microcoded_insn (insn))
32011 if (!rs6000_sched_groups)
32014 type = get_attr_type (insn);
32021 case TYPE_CR_LOGICAL:
32034 case PROCESSOR_POWER6:
32035 type = get_attr_type (insn);
32044 case TYPE_FPCOMPARE:
32055 if (get_attr_dot (insn) == DOT_NO
32056 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
32061 if (get_attr_size (insn) == SIZE_32)
32069 if (get_attr_update (insn) == UPDATE_YES)
32077 case PROCESSOR_POWER7:
32078 type = get_attr_type (insn);
32082 case TYPE_CR_LOGICAL:
32096 if (get_attr_dot (insn) == DOT_YES)
32101 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32102 || get_attr_update (insn) == UPDATE_YES)
32109 if (get_attr_update (insn) == UPDATE_YES)
32117 case PROCESSOR_POWER8:
32118 type = get_attr_type (insn);
32122 case TYPE_CR_LOGICAL:
32130 case TYPE_VECSTORE:
32137 if (get_attr_dot (insn) == DOT_YES)
32142 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32143 || get_attr_update (insn) == UPDATE_YES)
32148 if (get_attr_update (insn) == UPDATE_YES
32149 && get_attr_indexed (insn) == INDEXED_YES)
32165 insn_must_be_last_in_group (rtx_insn *insn)
32167 enum attr_type type;
32171 || DEBUG_INSN_P (insn)
32172 || GET_CODE (PATTERN (insn)) == USE
32173 || GET_CODE (PATTERN (insn)) == CLOBBER)
32176 switch (rs6000_tune) {
32177 case PROCESSOR_POWER4:
32178 case PROCESSOR_POWER5:
32179 if (is_microcoded_insn (insn))
32182 if (is_branch_slot_insn (insn))
32186 case PROCESSOR_POWER6:
32187 type = get_attr_type (insn);
32195 case TYPE_FPCOMPARE:
32206 if (get_attr_dot (insn) == DOT_NO
32207 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
32212 if (get_attr_size (insn) == SIZE_32)
32220 case PROCESSOR_POWER7:
32221 type = get_attr_type (insn);
32231 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32232 && get_attr_update (insn) == UPDATE_YES)
32237 if (get_attr_update (insn) == UPDATE_YES
32238 && get_attr_indexed (insn) == INDEXED_YES)
32246 case PROCESSOR_POWER8:
32247 type = get_attr_type (insn);
32259 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
32260 && get_attr_update (insn) == UPDATE_YES)
32265 if (get_attr_update (insn) == UPDATE_YES
32266 && get_attr_indexed (insn) == INDEXED_YES)
32281 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
32282 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
32285 is_costly_group (rtx *group_insns, rtx next_insn)
32288 int issue_rate = rs6000_issue_rate ();
32290 for (i = 0; i < issue_rate; i++)
32292 sd_iterator_def sd_it;
32294 rtx insn = group_insns[i];
32299 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
32301 rtx next = DEP_CON (dep);
32303 if (next == next_insn
32304 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
32312 /* Utility of the function redefine_groups.
32313 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
32314 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
32315 to keep it "far" (in a separate group) from GROUP_INSNS, following
32316 one of the following schemes, depending on the value of the flag
32317 -minsert_sched_nops = X:
32318 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
32319 in order to force NEXT_INSN into a separate group.
32320 (2) X < sched_finish_regroup_exact: insert exactly X nops.
32321 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
32322 insertion (has a group just ended, how many vacant issue slots remain in the
32323 last group, and how many dispatch groups were encountered so far). */
32326 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
32327 rtx_insn *next_insn, bool *group_end, int can_issue_more,
32332 int issue_rate = rs6000_issue_rate ();
32333 bool end = *group_end;
32336 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
32337 return can_issue_more;
32339 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
32340 return can_issue_more;
32342 force = is_costly_group (group_insns, next_insn);
32344 return can_issue_more;
32346 if (sched_verbose > 6)
32347 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
32348 *group_count ,can_issue_more);
32350 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
32353 can_issue_more = 0;
32355 /* Since only a branch can be issued in the last issue_slot, it is
32356 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
32357 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
32358 in this case the last nop will start a new group and the branch
32359 will be forced to the new group. */
32360 if (can_issue_more && !is_branch_slot_insn (next_insn))
32363 /* Do we have a special group ending nop? */
32364 if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
32365 || rs6000_tune == PROCESSOR_POWER8)
32367 nop = gen_group_ending_nop ();
32368 emit_insn_before (nop, next_insn);
32369 can_issue_more = 0;
32372 while (can_issue_more > 0)
32375 emit_insn_before (nop, next_insn);
32383 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
32385 int n_nops = rs6000_sched_insert_nops;
32387 /* Nops can't be issued from the branch slot, so the effective
32388 issue_rate for nops is 'issue_rate - 1'. */
32389 if (can_issue_more == 0)
32390 can_issue_more = issue_rate;
32392 if (can_issue_more == 0)
32394 can_issue_more = issue_rate - 1;
32397 for (i = 0; i < issue_rate; i++)
32399 group_insns[i] = 0;
32406 emit_insn_before (nop, next_insn);
32407 if (can_issue_more == issue_rate - 1) /* new group begins */
32410 if (can_issue_more == 0)
32412 can_issue_more = issue_rate - 1;
32415 for (i = 0; i < issue_rate; i++)
32417 group_insns[i] = 0;
32423 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
32426 /* Is next_insn going to start a new group? */
32429 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32430 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32431 || (can_issue_more < issue_rate &&
32432 insn_terminates_group_p (next_insn, previous_group)));
32433 if (*group_end && end)
32436 if (sched_verbose > 6)
32437 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
32438 *group_count, can_issue_more);
32439 return can_issue_more;
32442 return can_issue_more;
32445 /* This function tries to synch the dispatch groups that the compiler "sees"
32446 with the dispatch groups that the processor dispatcher is expected to
32447 form in practice. It tries to achieve this synchronization by forcing the
32448 estimated processor grouping on the compiler (as opposed to the function
32449 'pad_goups' which tries to force the scheduler's grouping on the processor).
32451 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
32452 examines the (estimated) dispatch groups that will be formed by the processor
32453 dispatcher. It marks these group boundaries to reflect the estimated
32454 processor grouping, overriding the grouping that the scheduler had marked.
32455 Depending on the value of the flag '-minsert-sched-nops' this function can
32456 force certain insns into separate groups or force a certain distance between
32457 them by inserting nops, for example, if there exists a "costly dependence"
32460 The function estimates the group boundaries that the processor will form as
32461 follows: It keeps track of how many vacant issue slots are available after
32462 each insn. A subsequent insn will start a new group if one of the following
32464 - no more vacant issue slots remain in the current dispatch group.
32465 - only the last issue slot, which is the branch slot, is vacant, but the next
32466 insn is not a branch.
32467 - only the last 2 or less issue slots, including the branch slot, are vacant,
32468 which means that a cracked insn (which occupies two issue slots) can't be
32469 issued in this group.
32470 - less than 'issue_rate' slots are vacant, and the next insn always needs to
32471 start a new group. */
32474 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32477 rtx_insn *insn, *next_insn;
32479 int can_issue_more;
32482 int group_count = 0;
32486 issue_rate = rs6000_issue_rate ();
32487 group_insns = XALLOCAVEC (rtx, issue_rate);
32488 for (i = 0; i < issue_rate; i++)
32490 group_insns[i] = 0;
32492 can_issue_more = issue_rate;
32494 insn = get_next_active_insn (prev_head_insn, tail);
32497 while (insn != NULL_RTX)
32499 slot = (issue_rate - can_issue_more);
32500 group_insns[slot] = insn;
32502 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32503 if (insn_terminates_group_p (insn, current_group))
32504 can_issue_more = 0;
32506 next_insn = get_next_active_insn (insn, tail);
32507 if (next_insn == NULL_RTX)
32508 return group_count + 1;
32510 /* Is next_insn going to start a new group? */
32512 = (can_issue_more == 0
32513 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32514 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32515 || (can_issue_more < issue_rate &&
32516 insn_terminates_group_p (next_insn, previous_group)));
32518 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
32519 next_insn, &group_end, can_issue_more,
32525 can_issue_more = 0;
32526 for (i = 0; i < issue_rate; i++)
32528 group_insns[i] = 0;
32532 if (GET_MODE (next_insn) == TImode && can_issue_more)
32533 PUT_MODE (next_insn, VOIDmode);
32534 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
32535 PUT_MODE (next_insn, TImode);
32538 if (can_issue_more == 0)
32539 can_issue_more = issue_rate;
32542 return group_count;
32545 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32546 dispatch group boundaries that the scheduler had marked. Pad with nops
32547 any dispatch groups which have vacant issue slots, in order to force the
32548 scheduler's grouping on the processor dispatcher. The function
32549 returns the number of dispatch groups found. */
32552 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32555 rtx_insn *insn, *next_insn;
32558 int can_issue_more;
32560 int group_count = 0;
32562 /* Initialize issue_rate. */
32563 issue_rate = rs6000_issue_rate ();
32564 can_issue_more = issue_rate;
32566 insn = get_next_active_insn (prev_head_insn, tail);
32567 next_insn = get_next_active_insn (insn, tail);
32569 while (insn != NULL_RTX)
32572 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32574 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
32576 if (next_insn == NULL_RTX)
32581 /* If the scheduler had marked group termination at this location
32582 (between insn and next_insn), and neither insn nor next_insn will
32583 force group termination, pad the group with nops to force group
32586 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
32587 && !insn_terminates_group_p (insn, current_group)
32588 && !insn_terminates_group_p (next_insn, previous_group))
32590 if (!is_branch_slot_insn (next_insn))
32593 while (can_issue_more)
32596 emit_insn_before (nop, next_insn);
32601 can_issue_more = issue_rate;
32606 next_insn = get_next_active_insn (insn, tail);
32609 return group_count;
32612 /* We're beginning a new block. Initialize data structures as necessary. */
32615 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
32616 int sched_verbose ATTRIBUTE_UNUSED,
32617 int max_ready ATTRIBUTE_UNUSED)
32619 last_scheduled_insn = NULL;
32620 load_store_pendulum = 0;
32625 /* The following function is called at the end of scheduling BB.
32626 After reload, it inserts nops at insn group bundling. */
32629 rs6000_sched_finish (FILE *dump, int sched_verbose)
32634 fprintf (dump, "=== Finishing schedule.\n");
32636 if (reload_completed && rs6000_sched_groups)
32638 /* Do not run sched_finish hook when selective scheduling enabled. */
32639 if (sel_sched_p ())
32642 if (rs6000_sched_insert_nops == sched_finish_none)
32645 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
32646 n_groups = pad_groups (dump, sched_verbose,
32647 current_sched_info->prev_head,
32648 current_sched_info->next_tail);
32650 n_groups = redefine_groups (dump, sched_verbose,
32651 current_sched_info->prev_head,
32652 current_sched_info->next_tail);
32654 if (sched_verbose >= 6)
32656 fprintf (dump, "ngroups = %d\n", n_groups);
32657 print_rtl (dump, current_sched_info->prev_head);
32658 fprintf (dump, "Done finish_sched\n");
32663 struct rs6000_sched_context
32665 short cached_can_issue_more;
32666 rtx_insn *last_scheduled_insn;
32667 int load_store_pendulum;
32672 typedef struct rs6000_sched_context rs6000_sched_context_def;
32673 typedef rs6000_sched_context_def *rs6000_sched_context_t;
32675 /* Allocate store for new scheduling context. */
32677 rs6000_alloc_sched_context (void)
32679 return xmalloc (sizeof (rs6000_sched_context_def));
32682 /* If CLEAN_P is true then initializes _SC with clean data,
32683 and from the global context otherwise. */
32685 rs6000_init_sched_context (void *_sc, bool clean_p)
32687 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32691 sc->cached_can_issue_more = 0;
32692 sc->last_scheduled_insn = NULL;
32693 sc->load_store_pendulum = 0;
32694 sc->divide_cnt = 0;
32695 sc->vec_pairing = 0;
32699 sc->cached_can_issue_more = cached_can_issue_more;
32700 sc->last_scheduled_insn = last_scheduled_insn;
32701 sc->load_store_pendulum = load_store_pendulum;
32702 sc->divide_cnt = divide_cnt;
32703 sc->vec_pairing = vec_pairing;
32707 /* Sets the global scheduling context to the one pointed to by _SC. */
32709 rs6000_set_sched_context (void *_sc)
32711 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32713 gcc_assert (sc != NULL);
32715 cached_can_issue_more = sc->cached_can_issue_more;
32716 last_scheduled_insn = sc->last_scheduled_insn;
32717 load_store_pendulum = sc->load_store_pendulum;
32718 divide_cnt = sc->divide_cnt;
32719 vec_pairing = sc->vec_pairing;
32724 rs6000_free_sched_context (void *_sc)
32726 gcc_assert (_sc != NULL);
32732 rs6000_sched_can_speculate_insn (rtx_insn *insn)
32734 switch (get_attr_type (insn))
32749 /* Length in units of the trampoline for entering a nested function. */
32752 rs6000_trampoline_size (void)
32756 switch (DEFAULT_ABI)
32759 gcc_unreachable ();
32762 ret = (TARGET_32BIT) ? 12 : 24;
32766 gcc_assert (!TARGET_32BIT);
32772 ret = (TARGET_32BIT) ? 40 : 48;
32779 /* Emit RTL insns to initialize the variable parts of a trampoline.
32780 FNADDR is an RTX for the address of the function's pure code.
32781 CXT is an RTX for the static chain value for the function. */
32784 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
32786 int regsize = (TARGET_32BIT) ? 4 : 8;
32787 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
32788 rtx ctx_reg = force_reg (Pmode, cxt);
32789 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
32791 switch (DEFAULT_ABI)
32794 gcc_unreachable ();
32796 /* Under AIX, just build the 3 word function descriptor */
32799 rtx fnmem, fn_reg, toc_reg;
32801 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
32802 error ("you cannot take the address of a nested function if you use "
32803 "the %qs option", "-mno-pointers-to-nested-functions");
32805 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
32806 fn_reg = gen_reg_rtx (Pmode);
32807 toc_reg = gen_reg_rtx (Pmode);
32809 /* Macro to shorten the code expansions below. */
32810 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32812 m_tramp = replace_equiv_address (m_tramp, addr);
32814 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
32815 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
32816 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
32817 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32818 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32824 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32828 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32829 LCT_NORMAL, VOIDmode,
32831 GEN_INT (rs6000_trampoline_size ()), SImode,
32839 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32840 identifier as an argument, so the front end shouldn't look it up. */
32843 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32845 return is_attribute_p ("altivec", attr_id);
32848 /* Handle the "altivec" attribute. The attribute may have
32849 arguments as follows:
32851 __attribute__((altivec(vector__)))
32852 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32853 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32855 and may appear more than once (e.g., 'vector bool char') in a
32856 given declaration. */
32859 rs6000_handle_altivec_attribute (tree *node,
32860 tree name ATTRIBUTE_UNUSED,
32862 int flags ATTRIBUTE_UNUSED,
32863 bool *no_add_attrs)
32865 tree type = *node, result = NULL_TREE;
32869 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32870 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32871 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32874 while (POINTER_TYPE_P (type)
32875 || TREE_CODE (type) == FUNCTION_TYPE
32876 || TREE_CODE (type) == METHOD_TYPE
32877 || TREE_CODE (type) == ARRAY_TYPE)
32878 type = TREE_TYPE (type);
32880 mode = TYPE_MODE (type);
32882 /* Check for invalid AltiVec type qualifiers. */
32883 if (type == long_double_type_node)
32884 error ("use of %<long double%> in AltiVec types is invalid");
32885 else if (type == boolean_type_node)
32886 error ("use of boolean types in AltiVec types is invalid");
32887 else if (TREE_CODE (type) == COMPLEX_TYPE)
32888 error ("use of %<complex%> in AltiVec types is invalid");
32889 else if (DECIMAL_FLOAT_MODE_P (mode))
32890 error ("use of decimal floating point types in AltiVec types is invalid");
32891 else if (!TARGET_VSX)
32893 if (type == long_unsigned_type_node || type == long_integer_type_node)
32896 error ("use of %<long%> in AltiVec types is invalid for "
32897 "64-bit code without %qs", "-mvsx");
32898 else if (rs6000_warn_altivec_long)
32899 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32902 else if (type == long_long_unsigned_type_node
32903 || type == long_long_integer_type_node)
32904 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32906 else if (type == double_type_node)
32907 error ("use of %<double%> in AltiVec types is invalid without %qs",
32911 switch (altivec_type)
32914 unsigned_p = TYPE_UNSIGNED (type);
32918 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32921 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32924 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32927 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32930 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32932 case E_SFmode: result = V4SF_type_node; break;
32933 case E_DFmode: result = V2DF_type_node; break;
32934 /* If the user says 'vector int bool', we may be handed the 'bool'
32935 attribute _before_ the 'vector' attribute, and so select the
32936 proper type in the 'b' case below. */
32937 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32938 case E_V2DImode: case E_V2DFmode:
32946 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32947 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32948 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32949 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32956 case E_V8HImode: result = pixel_V8HI_type_node;
32962 /* Propagate qualifiers attached to the element type
32963 onto the vector type. */
32964 if (result && result != type && TYPE_QUALS (type))
32965 result = build_qualified_type (result, TYPE_QUALS (type));
32967 *no_add_attrs = true; /* No need to hang on to the attribute. */
32970 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32975 /* AltiVec defines four built-in scalar types that serve as vector
32976 elements; we must teach the compiler how to mangle them. */
32978 static const char *
32979 rs6000_mangle_type (const_tree type)
32981 type = TYPE_MAIN_VARIANT (type);
32983 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
32984 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
32987 if (type == bool_char_type_node) return "U6__boolc";
32988 if (type == bool_short_type_node) return "U6__bools";
32989 if (type == pixel_type_node) return "u7__pixel";
32990 if (type == bool_int_type_node) return "U6__booli";
32991 if (type == bool_long_type_node) return "U6__booll";
32993 /* Use a unique name for __float128 rather than trying to use "e" or "g". Use
32994 "g" for IBM extended double, no matter whether it is long double (using
32995 -mabi=ibmlongdouble) or the distinct __ibm128 type. */
32996 if (TARGET_FLOAT128_TYPE)
32998 if (type == ieee128_float_type_node)
32999 return "U10__float128";
33001 if (TARGET_LONG_DOUBLE_128)
33003 if (type == long_double_type_node)
33004 return (TARGET_IEEEQUAD) ? "U10__float128" : "g";
33006 if (type == ibm128_float_type_node)
33011 /* Mangle IBM extended float long double as `g' (__float128) on
33012 powerpc*-linux where long-double-64 previously was the default. */
33013 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
33015 && TARGET_LONG_DOUBLE_128
33016 && !TARGET_IEEEQUAD)
33019 /* For all other types, use normal C++ mangling. */
33023 /* Handle a "longcall" or "shortcall" attribute; arguments as in
33024 struct attribute_spec.handler. */
33027 rs6000_handle_longcall_attribute (tree *node, tree name,
33028 tree args ATTRIBUTE_UNUSED,
33029 int flags ATTRIBUTE_UNUSED,
33030 bool *no_add_attrs)
33032 if (TREE_CODE (*node) != FUNCTION_TYPE
33033 && TREE_CODE (*node) != FIELD_DECL
33034 && TREE_CODE (*node) != TYPE_DECL)
33036 warning (OPT_Wattributes, "%qE attribute only applies to functions",
33038 *no_add_attrs = true;
33044 /* Set longcall attributes on all functions declared when
33045 rs6000_default_long_calls is true. */
33047 rs6000_set_default_type_attributes (tree type)
33049 if (rs6000_default_long_calls
33050 && (TREE_CODE (type) == FUNCTION_TYPE
33051 || TREE_CODE (type) == METHOD_TYPE))
33052 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
33054 TYPE_ATTRIBUTES (type));
33057 darwin_set_default_type_attributes (type);
33061 /* Return a reference suitable for calling a function with the
33062 longcall attribute. */
33065 rs6000_longcall_ref (rtx call_ref)
33067 const char *call_name;
33070 if (GET_CODE (call_ref) != SYMBOL_REF)
33073 /* System V adds '.' to the internal name, so skip them. */
33074 call_name = XSTR (call_ref, 0);
33075 if (*call_name == '.')
33077 while (*call_name == '.')
33080 node = get_identifier (call_name);
33081 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
33084 return force_reg (Pmode, call_ref);
33087 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
33088 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
33091 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
33092 struct attribute_spec.handler. */
33094 rs6000_handle_struct_attribute (tree *node, tree name,
33095 tree args ATTRIBUTE_UNUSED,
33096 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
33099 if (DECL_P (*node))
33101 if (TREE_CODE (*node) == TYPE_DECL)
33102 type = &TREE_TYPE (*node);
33107 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
33108 || TREE_CODE (*type) == UNION_TYPE)))
33110 warning (OPT_Wattributes, "%qE attribute ignored", name);
33111 *no_add_attrs = true;
33114 else if ((is_attribute_p ("ms_struct", name)
33115 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
33116 || ((is_attribute_p ("gcc_struct", name)
33117 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
33119 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
33121 *no_add_attrs = true;
33128 rs6000_ms_bitfield_layout_p (const_tree record_type)
33130 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
33131 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
33132 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
33135 #ifdef USING_ELFOS_H
33137 /* A get_unnamed_section callback, used for switching to toc_section. */
33140 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33142 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33143 && TARGET_MINIMAL_TOC)
33145 if (!toc_initialized)
33147 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
33148 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33149 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
33150 fprintf (asm_out_file, "\t.tc ");
33151 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
33152 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33153 fprintf (asm_out_file, "\n");
33155 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33156 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33157 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33158 fprintf (asm_out_file, " = .+32768\n");
33159 toc_initialized = 1;
33162 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33164 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33166 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
33167 if (!toc_initialized)
33169 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33170 toc_initialized = 1;
33175 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33176 if (!toc_initialized)
33178 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
33179 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
33180 fprintf (asm_out_file, " = .+32768\n");
33181 toc_initialized = 1;
33186 /* Implement TARGET_ASM_INIT_SECTIONS. */
33189 rs6000_elf_asm_init_sections (void)
33192 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
33195 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
33196 SDATA2_SECTION_ASM_OP);
33199 /* Implement TARGET_SELECT_RTX_SECTION. */
33202 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
33203 unsigned HOST_WIDE_INT align)
33205 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33206 return toc_section;
33208 return default_elf_select_rtx_section (mode, x, align);
33211 /* For a SYMBOL_REF, set generic flags and then perform some
33212 target-specific processing.
33214 When the AIX ABI is requested on a non-AIX system, replace the
33215 function name with the real name (with a leading .) rather than the
33216 function descriptor name. This saves a lot of overriding code to
33217 read the prefixes. */
33219 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
33221 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
33223 default_encode_section_info (decl, rtl, first);
33226 && TREE_CODE (decl) == FUNCTION_DECL
33228 && DEFAULT_ABI == ABI_AIX)
33230 rtx sym_ref = XEXP (rtl, 0);
33231 size_t len = strlen (XSTR (sym_ref, 0));
33232 char *str = XALLOCAVEC (char, len + 2);
33234 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
33235 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
33240 compare_section_name (const char *section, const char *templ)
33244 len = strlen (templ);
33245 return (strncmp (section, templ, len) == 0
33246 && (section[len] == 0 || section[len] == '.'));
33250 rs6000_elf_in_small_data_p (const_tree decl)
33252 if (rs6000_sdata == SDATA_NONE)
33255 /* We want to merge strings, so we never consider them small data. */
33256 if (TREE_CODE (decl) == STRING_CST)
33259 /* Functions are never in the small data area. */
33260 if (TREE_CODE (decl) == FUNCTION_DECL)
33263 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
33265 const char *section = DECL_SECTION_NAME (decl);
33266 if (compare_section_name (section, ".sdata")
33267 || compare_section_name (section, ".sdata2")
33268 || compare_section_name (section, ".gnu.linkonce.s")
33269 || compare_section_name (section, ".sbss")
33270 || compare_section_name (section, ".sbss2")
33271 || compare_section_name (section, ".gnu.linkonce.sb")
33272 || strcmp (section, ".PPC.EMB.sdata0") == 0
33273 || strcmp (section, ".PPC.EMB.sbss0") == 0)
33278 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
33281 && size <= g_switch_value
33282 /* If it's not public, and we're not going to reference it there,
33283 there's no need to put it in the small data section. */
33284 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
33291 #endif /* USING_ELFOS_H */
33293 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
33296 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
33298 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
33301 /* Do not place thread-local symbols refs in the object blocks. */
33304 rs6000_use_blocks_for_decl_p (const_tree decl)
33306 return !DECL_THREAD_LOCAL_P (decl);
33309 /* Return a REG that occurs in ADDR with coefficient 1.
33310 ADDR can be effectively incremented by incrementing REG.
33312 r0 is special and we must not select it as an address
33313 register by this routine since our caller will try to
33314 increment the returned register via an "la" instruction. */
33317 find_addr_reg (rtx addr)
33319 while (GET_CODE (addr) == PLUS)
33321 if (GET_CODE (XEXP (addr, 0)) == REG
33322 && REGNO (XEXP (addr, 0)) != 0)
33323 addr = XEXP (addr, 0);
33324 else if (GET_CODE (XEXP (addr, 1)) == REG
33325 && REGNO (XEXP (addr, 1)) != 0)
33326 addr = XEXP (addr, 1);
33327 else if (CONSTANT_P (XEXP (addr, 0)))
33328 addr = XEXP (addr, 1);
33329 else if (CONSTANT_P (XEXP (addr, 1)))
33330 addr = XEXP (addr, 0);
33332 gcc_unreachable ();
33334 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
33339 rs6000_fatal_bad_address (rtx op)
33341 fatal_insn ("bad address", op);
33346 typedef struct branch_island_d {
33347 tree function_name;
33353 static vec<branch_island, va_gc> *branch_islands;
33355 /* Remember to generate a branch island for far calls to the given
33359 add_compiler_branch_island (tree label_name, tree function_name,
33362 branch_island bi = {function_name, label_name, line_number};
33363 vec_safe_push (branch_islands, bi);
33366 /* Generate far-jump branch islands for everything recorded in
33367 branch_islands. Invoked immediately after the last instruction of
33368 the epilogue has been emitted; the branch islands must be appended
33369 to, and contiguous with, the function body. Mach-O stubs are
33370 generated in machopic_output_stub(). */
33373 macho_branch_islands (void)
33377 while (!vec_safe_is_empty (branch_islands))
33379 branch_island *bi = &branch_islands->last ();
33380 const char *label = IDENTIFIER_POINTER (bi->label_name);
33381 const char *name = IDENTIFIER_POINTER (bi->function_name);
33382 char name_buf[512];
33383 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
33384 if (name[0] == '*' || name[0] == '&')
33385 strcpy (name_buf, name+1);
33389 strcpy (name_buf+1, name);
33391 strcpy (tmp_buf, "\n");
33392 strcat (tmp_buf, label);
33393 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33394 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33395 dbxout_stabd (N_SLINE, bi->line_number);
33396 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33399 if (TARGET_LINK_STACK)
33402 get_ppc476_thunk_name (name);
33403 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
33404 strcat (tmp_buf, name);
33405 strcat (tmp_buf, "\n");
33406 strcat (tmp_buf, label);
33407 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
33411 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
33412 strcat (tmp_buf, label);
33413 strcat (tmp_buf, "_pic\n");
33414 strcat (tmp_buf, label);
33415 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
33418 strcat (tmp_buf, "\taddis r11,r11,ha16(");
33419 strcat (tmp_buf, name_buf);
33420 strcat (tmp_buf, " - ");
33421 strcat (tmp_buf, label);
33422 strcat (tmp_buf, "_pic)\n");
33424 strcat (tmp_buf, "\tmtlr r0\n");
33426 strcat (tmp_buf, "\taddi r12,r11,lo16(");
33427 strcat (tmp_buf, name_buf);
33428 strcat (tmp_buf, " - ");
33429 strcat (tmp_buf, label);
33430 strcat (tmp_buf, "_pic)\n");
33432 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
33436 strcat (tmp_buf, ":\nlis r12,hi16(");
33437 strcat (tmp_buf, name_buf);
33438 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
33439 strcat (tmp_buf, name_buf);
33440 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
33442 output_asm_insn (tmp_buf, 0);
33443 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
33444 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33445 dbxout_stabd (N_SLINE, bi->line_number);
33446 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
33447 branch_islands->pop ();
33451 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
33452 already there or not. */
33455 no_previous_def (tree function_name)
33460 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33461 if (function_name == bi->function_name)
33466 /* GET_PREV_LABEL gets the label name from the previous definition of
33470 get_prev_label (tree function_name)
33475 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
33476 if (function_name == bi->function_name)
33477 return bi->label_name;
33481 /* INSN is either a function call or a millicode call. It may have an
33482 unconditional jump in its delay slot.
33484 CALL_DEST is the routine we are calling. */
33487 output_call (rtx_insn *insn, rtx *operands, int dest_operand_number,
33488 int cookie_operand_number)
33490 static char buf[256];
33491 if (darwin_emit_branch_islands
33492 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
33493 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
33496 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
33498 if (no_previous_def (funname))
33500 rtx label_rtx = gen_label_rtx ();
33501 char *label_buf, temp_buf[256];
33502 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
33503 CODE_LABEL_NUMBER (label_rtx));
33504 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
33505 labelname = get_identifier (label_buf);
33506 add_compiler_branch_island (labelname, funname, insn_line (insn));
33509 labelname = get_prev_label (funname);
33511 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
33512 instruction will reach 'foo', otherwise link as 'bl L42'".
33513 "L42" should be a 'branch island', that will do a far jump to
33514 'foo'. Branch islands are generated in
33515 macho_branch_islands(). */
33516 sprintf (buf, "jbsr %%z%d,%.246s",
33517 dest_operand_number, IDENTIFIER_POINTER (labelname));
33520 sprintf (buf, "bl %%z%d", dest_operand_number);
33524 /* Generate PIC and indirect symbol stubs. */
33527 machopic_output_stub (FILE *file, const char *symb, const char *stub)
33529 unsigned int length;
33530 char *symbol_name, *lazy_ptr_name;
33531 char *local_label_0;
33532 static int label = 0;
33534 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
33535 symb = (*targetm.strip_name_encoding) (symb);
33538 length = strlen (symb);
33539 symbol_name = XALLOCAVEC (char, length + 32);
33540 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
33542 lazy_ptr_name = XALLOCAVEC (char, length + 32);
33543 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
33546 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
33548 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
33552 fprintf (file, "\t.align 5\n");
33554 fprintf (file, "%s:\n", stub);
33555 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33558 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
33559 sprintf (local_label_0, "\"L%011d$spb\"", label);
33561 fprintf (file, "\tmflr r0\n");
33562 if (TARGET_LINK_STACK)
33565 get_ppc476_thunk_name (name);
33566 fprintf (file, "\tbl %s\n", name);
33567 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33571 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
33572 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33574 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
33575 lazy_ptr_name, local_label_0);
33576 fprintf (file, "\tmtlr r0\n");
33577 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
33578 (TARGET_64BIT ? "ldu" : "lwzu"),
33579 lazy_ptr_name, local_label_0);
33580 fprintf (file, "\tmtctr r12\n");
33581 fprintf (file, "\tbctr\n");
33585 fprintf (file, "\t.align 4\n");
33587 fprintf (file, "%s:\n", stub);
33588 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33590 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
33591 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
33592 (TARGET_64BIT ? "ldu" : "lwzu"),
33594 fprintf (file, "\tmtctr r12\n");
33595 fprintf (file, "\tbctr\n");
33598 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
33599 fprintf (file, "%s:\n", lazy_ptr_name);
33600 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33601 fprintf (file, "%sdyld_stub_binding_helper\n",
33602 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
33605 /* Legitimize PIC addresses. If the address is already
33606 position-independent, we return ORIG. Newly generated
33607 position-independent addresses go into a reg. This is REG if non
33608 zero, otherwise we allocate register(s) as necessary. */
33610 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33613 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
33618 if (reg == NULL && !reload_completed)
33619 reg = gen_reg_rtx (Pmode);
33621 if (GET_CODE (orig) == CONST)
33625 if (GET_CODE (XEXP (orig, 0)) == PLUS
33626 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
33629 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
33631 /* Use a different reg for the intermediate value, as
33632 it will be marked UNCHANGING. */
33633 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
33634 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
33637 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
33640 if (GET_CODE (offset) == CONST_INT)
33642 if (SMALL_INT (offset))
33643 return plus_constant (Pmode, base, INTVAL (offset));
33644 else if (!reload_completed)
33645 offset = force_reg (Pmode, offset);
33648 rtx mem = force_const_mem (Pmode, orig);
33649 return machopic_legitimize_pic_address (mem, Pmode, reg);
33652 return gen_rtx_PLUS (Pmode, base, offset);
33655 /* Fall back on generic machopic code. */
33656 return machopic_legitimize_pic_address (orig, mode, reg);
33659 /* Output a .machine directive for the Darwin assembler, and call
33660 the generic start_file routine. */
33663 rs6000_darwin_file_start (void)
33665 static const struct
33669 HOST_WIDE_INT if_set;
33671 { "ppc64", "ppc64", MASK_64BIT },
33672 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
33673 { "power4", "ppc970", 0 },
33674 { "G5", "ppc970", 0 },
33675 { "7450", "ppc7450", 0 },
33676 { "7400", "ppc7400", MASK_ALTIVEC },
33677 { "G4", "ppc7400", 0 },
33678 { "750", "ppc750", 0 },
33679 { "740", "ppc750", 0 },
33680 { "G3", "ppc750", 0 },
33681 { "604e", "ppc604e", 0 },
33682 { "604", "ppc604", 0 },
33683 { "603e", "ppc603", 0 },
33684 { "603", "ppc603", 0 },
33685 { "601", "ppc601", 0 },
33686 { NULL, "ppc", 0 } };
33687 const char *cpu_id = "";
33690 rs6000_file_start ();
33691 darwin_file_start ();
33693 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33695 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
33696 cpu_id = rs6000_default_cpu;
33698 if (global_options_set.x_rs6000_cpu_index)
33699 cpu_id = processor_target_table[rs6000_cpu_index].name;
33701 /* Look through the mapping array. Pick the first name that either
33702 matches the argument, has a bit set in IF_SET that is also set
33703 in the target flags, or has a NULL name. */
33706 while (mapping[i].arg != NULL
33707 && strcmp (mapping[i].arg, cpu_id) != 0
33708 && (mapping[i].if_set & rs6000_isa_flags) == 0)
33711 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
33714 #endif /* TARGET_MACHO */
33718 rs6000_elf_reloc_rw_mask (void)
33722 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33728 /* Record an element in the table of global constructors. SYMBOL is
33729 a SYMBOL_REF of the function to be called; PRIORITY is a number
33730 between 0 and MAX_INIT_PRIORITY.
33732 This differs from default_named_section_asm_out_constructor in
33733 that we have special handling for -mrelocatable. */
33735 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
33737 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
33739 const char *section = ".ctors";
33742 if (priority != DEFAULT_INIT_PRIORITY)
33744 sprintf (buf, ".ctors.%.5u",
33745 /* Invert the numbering so the linker puts us in the proper
33746 order; constructors are run from right to left, and the
33747 linker sorts in increasing order. */
33748 MAX_INIT_PRIORITY - priority);
33752 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33753 assemble_align (POINTER_SIZE);
33755 if (DEFAULT_ABI == ABI_V4
33756 && (TARGET_RELOCATABLE || flag_pic > 1))
33758 fputs ("\t.long (", asm_out_file);
33759 output_addr_const (asm_out_file, symbol);
33760 fputs (")@fixup\n", asm_out_file);
33763 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33766 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
33768 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
33770 const char *section = ".dtors";
33773 if (priority != DEFAULT_INIT_PRIORITY)
33775 sprintf (buf, ".dtors.%.5u",
33776 /* Invert the numbering so the linker puts us in the proper
33777 order; constructors are run from right to left, and the
33778 linker sorts in increasing order. */
33779 MAX_INIT_PRIORITY - priority);
33783 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33784 assemble_align (POINTER_SIZE);
33786 if (DEFAULT_ABI == ABI_V4
33787 && (TARGET_RELOCATABLE || flag_pic > 1))
33789 fputs ("\t.long (", asm_out_file);
33790 output_addr_const (asm_out_file, symbol);
33791 fputs (")@fixup\n", asm_out_file);
33794 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33798 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
33800 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
33802 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
33803 ASM_OUTPUT_LABEL (file, name);
33804 fputs (DOUBLE_INT_ASM_OP, file);
33805 rs6000_output_function_entry (file, name);
33806 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
33809 fputs ("\t.size\t", file);
33810 assemble_name (file, name);
33811 fputs (",24\n\t.type\t.", file);
33812 assemble_name (file, name);
33813 fputs (",@function\n", file);
33814 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
33816 fputs ("\t.globl\t.", file);
33817 assemble_name (file, name);
33822 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33823 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33824 rs6000_output_function_entry (file, name);
33825 fputs (":\n", file);
33830 if (DEFAULT_ABI == ABI_V4
33831 && (TARGET_RELOCATABLE || flag_pic > 1)
33832 && !TARGET_SECURE_PLT
33833 && (!constant_pool_empty_p () || crtl->profile)
33834 && (uses_toc = uses_TOC ()))
33839 switch_to_other_text_partition ();
33840 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33842 fprintf (file, "\t.long ");
33843 assemble_name (file, toc_label_name);
33846 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33847 assemble_name (file, buf);
33850 switch_to_other_text_partition ();
33853 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33854 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33856 if (TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ())
33860 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33862 fprintf (file, "\t.quad .TOC.-");
33863 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33864 assemble_name (file, buf);
33868 if (DEFAULT_ABI == ABI_AIX)
33870 const char *desc_name, *orig_name;
33872 orig_name = (*targetm.strip_name_encoding) (name);
33873 desc_name = orig_name;
33874 while (*desc_name == '.')
33877 if (TREE_PUBLIC (decl))
33878 fprintf (file, "\t.globl %s\n", desc_name);
33880 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33881 fprintf (file, "%s:\n", desc_name);
33882 fprintf (file, "\t.long %s\n", orig_name);
33883 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33884 fputs ("\t.long 0\n", file);
33885 fprintf (file, "\t.previous\n");
33887 ASM_OUTPUT_LABEL (file, name);
33890 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33892 rs6000_elf_file_end (void)
33894 #ifdef HAVE_AS_GNU_ATTRIBUTE
33895 /* ??? The value emitted depends on options active at file end.
33896 Assume anyone using #pragma or attributes that might change
33897 options knows what they are doing. */
33898 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33899 && rs6000_passes_float)
33905 else if (TARGET_SF_FPR)
33909 if (rs6000_passes_long_double)
33911 if (!TARGET_LONG_DOUBLE_128)
33913 else if (TARGET_IEEEQUAD)
33918 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33920 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33922 if (rs6000_passes_vector)
33923 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33924 (TARGET_ALTIVEC_ABI ? 2 : 1));
33925 if (rs6000_returns_struct)
33926 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33927 aix_struct_return ? 2 : 1);
33930 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33931 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33932 file_end_indicate_exec_stack ();
33935 if (flag_split_stack)
33936 file_end_indicate_split_stack ();
33940 /* We have expanded a CPU builtin, so we need to emit a reference to
33941 the special symbol that LIBC uses to declare it supports the
33942 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33943 switch_to_section (data_section);
33944 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33945 fprintf (asm_out_file, "\t%s %s\n",
33946 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33953 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33954 #define HAVE_XCOFF_DWARF_EXTRAS 0
33957 static enum unwind_info_type
33958 rs6000_xcoff_debug_unwind_info (void)
33964 rs6000_xcoff_asm_output_anchor (rtx symbol)
33968 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33969 SYMBOL_REF_BLOCK_OFFSET (symbol));
33970 fprintf (asm_out_file, "%s", SET_ASM_OP);
33971 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33972 fprintf (asm_out_file, ",");
33973 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33974 fprintf (asm_out_file, "\n");
33978 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
33980 fputs (GLOBAL_ASM_OP, stream);
33981 RS6000_OUTPUT_BASENAME (stream, name);
33982 putc ('\n', stream);
33985 /* A get_unnamed_decl callback, used for read-only sections. PTR
33986 points to the section string variable. */
33989 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
33991 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
33992 *(const char *const *) directive,
33993 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33996 /* Likewise for read-write sections. */
33999 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
34001 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
34002 *(const char *const *) directive,
34003 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
34007 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
34009 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
34010 *(const char *const *) directive,
34011 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
34014 /* A get_unnamed_section callback, used for switching to toc_section. */
34017 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
34019 if (TARGET_MINIMAL_TOC)
34021 /* toc_section is always selected at least once from
34022 rs6000_xcoff_file_start, so this is guaranteed to
34023 always be defined once and only once in each file. */
34024 if (!toc_initialized)
34026 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
34027 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
34028 toc_initialized = 1;
34030 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
34031 (TARGET_32BIT ? "" : ",3"));
34034 fputs ("\t.toc\n", asm_out_file);
34037 /* Implement TARGET_ASM_INIT_SECTIONS. */
34040 rs6000_xcoff_asm_init_sections (void)
34042 read_only_data_section
34043 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
34044 &xcoff_read_only_section_name);
34046 private_data_section
34047 = get_unnamed_section (SECTION_WRITE,
34048 rs6000_xcoff_output_readwrite_section_asm_op,
34049 &xcoff_private_data_section_name);
34052 = get_unnamed_section (SECTION_TLS,
34053 rs6000_xcoff_output_tls_section_asm_op,
34054 &xcoff_tls_data_section_name);
34056 tls_private_data_section
34057 = get_unnamed_section (SECTION_TLS,
34058 rs6000_xcoff_output_tls_section_asm_op,
34059 &xcoff_private_data_section_name);
34061 read_only_private_data_section
34062 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
34063 &xcoff_private_data_section_name);
34066 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
34068 readonly_data_section = read_only_data_section;
34072 rs6000_xcoff_reloc_rw_mask (void)
34078 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
34079 tree decl ATTRIBUTE_UNUSED)
34082 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
34084 if (flags & SECTION_EXCLUDE)
34086 else if (flags & SECTION_DEBUG)
34088 fprintf (asm_out_file, "\t.dwsect %s\n", name);
34091 else if (flags & SECTION_CODE)
34093 else if (flags & SECTION_TLS)
34095 else if (flags & SECTION_WRITE)
34100 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
34101 (flags & SECTION_CODE) ? "." : "",
34102 name, suffix[smclass], flags & SECTION_ENTSIZE);
34105 #define IN_NAMED_SECTION(DECL) \
34106 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
34107 && DECL_SECTION_NAME (DECL) != NULL)
34110 rs6000_xcoff_select_section (tree decl, int reloc,
34111 unsigned HOST_WIDE_INT align)
34113 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
34115 if (align > BIGGEST_ALIGNMENT)
34117 resolve_unique_section (decl, reloc, true);
34118 if (IN_NAMED_SECTION (decl))
34119 return get_named_section (decl, NULL, reloc);
34122 if (decl_readonly_section (decl, reloc))
34124 if (TREE_PUBLIC (decl))
34125 return read_only_data_section;
34127 return read_only_private_data_section;
34132 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34134 if (TREE_PUBLIC (decl))
34135 return tls_data_section;
34136 else if (bss_initializer_p (decl))
34138 /* Convert to COMMON to emit in BSS. */
34139 DECL_COMMON (decl) = 1;
34140 return tls_comm_section;
34143 return tls_private_data_section;
34147 if (TREE_PUBLIC (decl))
34148 return data_section;
34150 return private_data_section;
34155 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
34159 /* Use select_section for private data and uninitialized data with
34160 alignment <= BIGGEST_ALIGNMENT. */
34161 if (!TREE_PUBLIC (decl)
34162 || DECL_COMMON (decl)
34163 || (DECL_INITIAL (decl) == NULL_TREE
34164 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
34165 || DECL_INITIAL (decl) == error_mark_node
34166 || (flag_zero_initialized_in_bss
34167 && initializer_zerop (DECL_INITIAL (decl))))
34170 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
34171 name = (*targetm.strip_name_encoding) (name);
34172 set_decl_section_name (decl, name);
34175 /* Select section for constant in constant pool.
34177 On RS/6000, all constants are in the private read-only data area.
34178 However, if this is being placed in the TOC it must be output as a
34182 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
34183 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
34185 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
34186 return toc_section;
34188 return read_only_private_data_section;
34191 /* Remove any trailing [DS] or the like from the symbol name. */
34193 static const char *
34194 rs6000_xcoff_strip_name_encoding (const char *name)
34199 len = strlen (name);
34200 if (name[len - 1] == ']')
34201 return ggc_alloc_string (name, len - 4);
34206 /* Section attributes. AIX is always PIC. */
34208 static unsigned int
34209 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
34211 unsigned int align;
34212 unsigned int flags = default_section_type_flags (decl, name, reloc);
34214 /* Align to at least UNIT size. */
34215 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
34216 align = MIN_UNITS_PER_WORD;
34218 /* Increase alignment of large objects if not already stricter. */
34219 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
34220 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
34221 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
34223 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
34226 /* Output at beginning of assembler file.
34228 Initialize the section names for the RS/6000 at this point.
34230 Specify filename, including full path, to assembler.
34232 We want to go into the TOC section so at least one .toc will be emitted.
34233 Also, in order to output proper .bs/.es pairs, we need at least one static
34234 [RW] section emitted.
34236 Finally, declare mcount when profiling to make the assembler happy. */
34239 rs6000_xcoff_file_start (void)
34241 rs6000_gen_section_name (&xcoff_bss_section_name,
34242 main_input_filename, ".bss_");
34243 rs6000_gen_section_name (&xcoff_private_data_section_name,
34244 main_input_filename, ".rw_");
34245 rs6000_gen_section_name (&xcoff_read_only_section_name,
34246 main_input_filename, ".ro_");
34247 rs6000_gen_section_name (&xcoff_tls_data_section_name,
34248 main_input_filename, ".tls_");
34249 rs6000_gen_section_name (&xcoff_tbss_section_name,
34250 main_input_filename, ".tbss_[UL]");
34252 fputs ("\t.file\t", asm_out_file);
34253 output_quoted_string (asm_out_file, main_input_filename);
34254 fputc ('\n', asm_out_file);
34255 if (write_symbols != NO_DEBUG)
34256 switch_to_section (private_data_section);
34257 switch_to_section (toc_section);
34258 switch_to_section (text_section);
34260 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
34261 rs6000_file_start ();
34264 /* Output at end of assembler file.
34265 On the RS/6000, referencing data should automatically pull in text. */
34268 rs6000_xcoff_file_end (void)
34270 switch_to_section (text_section);
34271 fputs ("_section_.text:\n", asm_out_file);
34272 switch_to_section (data_section);
34273 fputs (TARGET_32BIT
34274 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
34278 struct declare_alias_data
34281 bool function_descriptor;
34284 /* Declare alias N. A helper function for for_node_and_aliases. */
34287 rs6000_declare_alias (struct symtab_node *n, void *d)
34289 struct declare_alias_data *data = (struct declare_alias_data *)d;
34290 /* Main symbol is output specially, because varasm machinery does part of
34291 the job for us - we do not need to declare .globl/lglobs and such. */
34292 if (!n->alias || n->weakref)
34295 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
34298 /* Prevent assemble_alias from trying to use .set pseudo operation
34299 that does not behave as expected by the middle-end. */
34300 TREE_ASM_WRITTEN (n->decl) = true;
34302 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
34303 char *buffer = (char *) alloca (strlen (name) + 2);
34305 int dollar_inside = 0;
34307 strcpy (buffer, name);
34308 p = strchr (buffer, '$');
34312 p = strchr (p + 1, '$');
34314 if (TREE_PUBLIC (n->decl))
34316 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
34318 if (dollar_inside) {
34319 if (data->function_descriptor)
34320 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
34321 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
34323 if (data->function_descriptor)
34325 fputs ("\t.globl .", data->file);
34326 RS6000_OUTPUT_BASENAME (data->file, buffer);
34327 putc ('\n', data->file);
34329 fputs ("\t.globl ", data->file);
34330 RS6000_OUTPUT_BASENAME (data->file, buffer);
34331 putc ('\n', data->file);
34333 #ifdef ASM_WEAKEN_DECL
34334 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
34335 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
34342 if (data->function_descriptor)
34343 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
34344 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
34346 if (data->function_descriptor)
34348 fputs ("\t.lglobl .", data->file);
34349 RS6000_OUTPUT_BASENAME (data->file, buffer);
34350 putc ('\n', data->file);
34352 fputs ("\t.lglobl ", data->file);
34353 RS6000_OUTPUT_BASENAME (data->file, buffer);
34354 putc ('\n', data->file);
34356 if (data->function_descriptor)
34357 fputs (".", data->file);
34358 RS6000_OUTPUT_BASENAME (data->file, buffer);
34359 fputs (":\n", data->file);
34364 #ifdef HAVE_GAS_HIDDEN
34365 /* Helper function to calculate visibility of a DECL
34366 and return the value as a const string. */
34368 static const char *
34369 rs6000_xcoff_visibility (tree decl)
34371 static const char * const visibility_types[] = {
34372 "", ",protected", ",hidden", ",internal"
34375 enum symbol_visibility vis = DECL_VISIBILITY (decl);
34377 if (TREE_CODE (decl) == FUNCTION_DECL
34378 && cgraph_node::get (decl)
34379 && cgraph_node::get (decl)->instrumentation_clone
34380 && cgraph_node::get (decl)->instrumented_version)
34381 vis = DECL_VISIBILITY (cgraph_node::get (decl)->instrumented_version->decl);
34383 return visibility_types[vis];
34388 /* This macro produces the initial definition of a function name.
34389 On the RS/6000, we need to place an extra '.' in the function name and
34390 output the function descriptor.
34391 Dollar signs are converted to underscores.
34393 The csect for the function will have already been created when
34394 text_section was selected. We do have to go back to that csect, however.
34396 The third and fourth parameters to the .function pseudo-op (16 and 044)
34397 are placeholders which no longer have any use.
34399 Because AIX assembler's .set command has unexpected semantics, we output
34400 all aliases as alternative labels in front of the definition. */
34403 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
34405 char *buffer = (char *) alloca (strlen (name) + 1);
34407 int dollar_inside = 0;
34408 struct declare_alias_data data = {file, false};
34410 strcpy (buffer, name);
34411 p = strchr (buffer, '$');
34415 p = strchr (p + 1, '$');
34417 if (TREE_PUBLIC (decl))
34419 if (!RS6000_WEAK || !DECL_WEAK (decl))
34421 if (dollar_inside) {
34422 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
34423 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
34425 fputs ("\t.globl .", file);
34426 RS6000_OUTPUT_BASENAME (file, buffer);
34427 #ifdef HAVE_GAS_HIDDEN
34428 fputs (rs6000_xcoff_visibility (decl), file);
34435 if (dollar_inside) {
34436 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
34437 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
34439 fputs ("\t.lglobl .", file);
34440 RS6000_OUTPUT_BASENAME (file, buffer);
34443 fputs ("\t.csect ", file);
34444 RS6000_OUTPUT_BASENAME (file, buffer);
34445 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
34446 RS6000_OUTPUT_BASENAME (file, buffer);
34447 fputs (":\n", file);
34448 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34450 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
34451 RS6000_OUTPUT_BASENAME (file, buffer);
34452 fputs (", TOC[tc0], 0\n", file);
34454 switch_to_section (function_section (decl));
34456 RS6000_OUTPUT_BASENAME (file, buffer);
34457 fputs (":\n", file);
34458 data.function_descriptor = true;
34459 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34461 if (!DECL_IGNORED_P (decl))
34463 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
34464 xcoffout_declare_function (file, decl, buffer);
34465 else if (write_symbols == DWARF2_DEBUG)
34467 name = (*targetm.strip_name_encoding) (name);
34468 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
34475 /* Output assembly language to globalize a symbol from a DECL,
34476 possibly with visibility. */
34479 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
34481 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
34482 fputs (GLOBAL_ASM_OP, stream);
34483 RS6000_OUTPUT_BASENAME (stream, name);
34484 #ifdef HAVE_GAS_HIDDEN
34485 fputs (rs6000_xcoff_visibility (decl), stream);
34487 putc ('\n', stream);
34490 /* Output assembly language to define a symbol as COMMON from a DECL,
34491 possibly with visibility. */
34494 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
34495 tree decl ATTRIBUTE_UNUSED,
34497 unsigned HOST_WIDE_INT size,
34498 unsigned HOST_WIDE_INT align)
34500 unsigned HOST_WIDE_INT align2 = 2;
34503 align2 = floor_log2 (align / BITS_PER_UNIT);
34507 fputs (COMMON_ASM_OP, stream);
34508 RS6000_OUTPUT_BASENAME (stream, name);
34511 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
34514 #ifdef HAVE_GAS_HIDDEN
34516 fputs (rs6000_xcoff_visibility (decl), stream);
34518 putc ('\n', stream);
34521 /* This macro produces the initial definition of a object (variable) name.
34522 Because AIX assembler's .set command has unexpected semantics, we output
34523 all aliases as alternative labels in front of the definition. */
34526 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
34528 struct declare_alias_data data = {file, false};
34529 RS6000_OUTPUT_BASENAME (file, name);
34530 fputs (":\n", file);
34531 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
34535 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
34538 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
34540 fputs (integer_asm_op (size, FALSE), file);
34541 assemble_name (file, label);
34542 fputs ("-$", file);
34545 /* Output a symbol offset relative to the dbase for the current object.
34546 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
34549 __gcc_unwind_dbase is embedded in all executables/libraries through
34550 libgcc/config/rs6000/crtdbase.S. */
34553 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
34555 fputs (integer_asm_op (size, FALSE), file);
34556 assemble_name (file, label);
34557 fputs("-__gcc_unwind_dbase", file);
34562 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
34566 const char *symname;
34568 default_encode_section_info (decl, rtl, first);
34570 /* Careful not to prod global register variables. */
34573 symbol = XEXP (rtl, 0);
34574 if (GET_CODE (symbol) != SYMBOL_REF)
34577 flags = SYMBOL_REF_FLAGS (symbol);
34579 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34580 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
34582 SYMBOL_REF_FLAGS (symbol) = flags;
34584 /* Append mapping class to extern decls. */
34585 symname = XSTR (symbol, 0);
34586 if (decl /* sync condition with assemble_external () */
34587 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
34588 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
34589 || TREE_CODE (decl) == FUNCTION_DECL)
34590 && symname[strlen (symname) - 1] != ']')
34592 char *newname = (char *) alloca (strlen (symname) + 5);
34593 strcpy (newname, symname);
34594 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
34595 ? "[DS]" : "[UA]"));
34596 XSTR (symbol, 0) = ggc_strdup (newname);
34599 #endif /* HAVE_AS_TLS */
34600 #endif /* TARGET_XCOFF */
34603 rs6000_asm_weaken_decl (FILE *stream, tree decl,
34604 const char *name, const char *val)
34606 fputs ("\t.weak\t", stream);
34607 RS6000_OUTPUT_BASENAME (stream, name);
34608 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34609 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34612 fputs ("[DS]", stream);
34613 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34615 fputs (rs6000_xcoff_visibility (decl), stream);
34617 fputs ("\n\t.weak\t.", stream);
34618 RS6000_OUTPUT_BASENAME (stream, name);
34620 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34622 fputs (rs6000_xcoff_visibility (decl), stream);
34624 fputc ('\n', stream);
34627 #ifdef ASM_OUTPUT_DEF
34628 ASM_OUTPUT_DEF (stream, name, val);
34630 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34631 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34633 fputs ("\t.set\t.", stream);
34634 RS6000_OUTPUT_BASENAME (stream, name);
34635 fputs (",.", stream);
34636 RS6000_OUTPUT_BASENAME (stream, val);
34637 fputc ('\n', stream);
34643 /* Return true if INSN should not be copied. */
34646 rs6000_cannot_copy_insn_p (rtx_insn *insn)
34648 return recog_memoized (insn) >= 0
34649 && get_attr_cannot_copy (insn);
34652 /* Compute a (partial) cost for rtx X. Return true if the complete
34653 cost has been computed, and false if subexpressions should be
34654 scanned. In either case, *TOTAL contains the cost result. */
34657 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
34658 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
34660 int code = GET_CODE (x);
34664 /* On the RS/6000, if it is valid in the insn, it is free. */
34666 if (((outer_code == SET
34667 || outer_code == PLUS
34668 || outer_code == MINUS)
34669 && (satisfies_constraint_I (x)
34670 || satisfies_constraint_L (x)))
34671 || (outer_code == AND
34672 && (satisfies_constraint_K (x)
34674 ? satisfies_constraint_L (x)
34675 : satisfies_constraint_J (x))))
34676 || ((outer_code == IOR || outer_code == XOR)
34677 && (satisfies_constraint_K (x)
34679 ? satisfies_constraint_L (x)
34680 : satisfies_constraint_J (x))))
34681 || outer_code == ASHIFT
34682 || outer_code == ASHIFTRT
34683 || outer_code == LSHIFTRT
34684 || outer_code == ROTATE
34685 || outer_code == ROTATERT
34686 || outer_code == ZERO_EXTRACT
34687 || (outer_code == MULT
34688 && satisfies_constraint_I (x))
34689 || ((outer_code == DIV || outer_code == UDIV
34690 || outer_code == MOD || outer_code == UMOD)
34691 && exact_log2 (INTVAL (x)) >= 0)
34692 || (outer_code == COMPARE
34693 && (satisfies_constraint_I (x)
34694 || satisfies_constraint_K (x)))
34695 || ((outer_code == EQ || outer_code == NE)
34696 && (satisfies_constraint_I (x)
34697 || satisfies_constraint_K (x)
34699 ? satisfies_constraint_L (x)
34700 : satisfies_constraint_J (x))))
34701 || (outer_code == GTU
34702 && satisfies_constraint_I (x))
34703 || (outer_code == LTU
34704 && satisfies_constraint_P (x)))
34709 else if ((outer_code == PLUS
34710 && reg_or_add_cint_operand (x, VOIDmode))
34711 || (outer_code == MINUS
34712 && reg_or_sub_cint_operand (x, VOIDmode))
34713 || ((outer_code == SET
34714 || outer_code == IOR
34715 || outer_code == XOR)
34717 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
34719 *total = COSTS_N_INSNS (1);
34725 case CONST_WIDE_INT:
34729 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34733 /* When optimizing for size, MEM should be slightly more expensive
34734 than generating address, e.g., (plus (reg) (const)).
34735 L1 cache latency is about two instructions. */
34736 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34737 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
34738 *total += COSTS_N_INSNS (100);
34747 if (FLOAT_MODE_P (mode))
34748 *total = rs6000_cost->fp;
34750 *total = COSTS_N_INSNS (1);
34754 if (GET_CODE (XEXP (x, 1)) == CONST_INT
34755 && satisfies_constraint_I (XEXP (x, 1)))
34757 if (INTVAL (XEXP (x, 1)) >= -256
34758 && INTVAL (XEXP (x, 1)) <= 255)
34759 *total = rs6000_cost->mulsi_const9;
34761 *total = rs6000_cost->mulsi_const;
34763 else if (mode == SFmode)
34764 *total = rs6000_cost->fp;
34765 else if (FLOAT_MODE_P (mode))
34766 *total = rs6000_cost->dmul;
34767 else if (mode == DImode)
34768 *total = rs6000_cost->muldi;
34770 *total = rs6000_cost->mulsi;
34774 if (mode == SFmode)
34775 *total = rs6000_cost->fp;
34777 *total = rs6000_cost->dmul;
34782 if (FLOAT_MODE_P (mode))
34784 *total = mode == DFmode ? rs6000_cost->ddiv
34785 : rs6000_cost->sdiv;
34792 if (GET_CODE (XEXP (x, 1)) == CONST_INT
34793 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
34795 if (code == DIV || code == MOD)
34797 *total = COSTS_N_INSNS (2);
34800 *total = COSTS_N_INSNS (1);
34804 if (GET_MODE (XEXP (x, 1)) == DImode)
34805 *total = rs6000_cost->divdi;
34807 *total = rs6000_cost->divsi;
34809 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34810 if (!TARGET_MODULO && (code == MOD || code == UMOD))
34811 *total += COSTS_N_INSNS (2);
34815 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
34819 *total = COSTS_N_INSNS (4);
34823 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
34827 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
34831 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
34834 *total = COSTS_N_INSNS (1);
34838 if (CONST_INT_P (XEXP (x, 1)))
34840 rtx left = XEXP (x, 0);
34841 rtx_code left_code = GET_CODE (left);
34843 /* rotate-and-mask: 1 insn. */
34844 if ((left_code == ROTATE
34845 || left_code == ASHIFT
34846 || left_code == LSHIFTRT)
34847 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34849 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34850 if (!CONST_INT_P (XEXP (left, 1)))
34851 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34852 *total += COSTS_N_INSNS (1);
34856 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34857 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34858 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34859 || (val & 0xffff) == val
34860 || (val & 0xffff0000) == val
34861 || ((val & 0xffff) == 0 && mode == SImode))
34863 *total = rtx_cost (left, mode, AND, 0, speed);
34864 *total += COSTS_N_INSNS (1);
34869 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34871 *total = rtx_cost (left, mode, AND, 0, speed);
34872 *total += COSTS_N_INSNS (2);
34877 *total = COSTS_N_INSNS (1);
34882 *total = COSTS_N_INSNS (1);
34888 *total = COSTS_N_INSNS (1);
34892 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34893 the sign extend and shift separately within the insn. */
34894 if (TARGET_EXTSWSLI && mode == DImode
34895 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34896 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34907 /* Handle mul_highpart. */
34908 if (outer_code == TRUNCATE
34909 && GET_CODE (XEXP (x, 0)) == MULT)
34911 if (mode == DImode)
34912 *total = rs6000_cost->muldi;
34914 *total = rs6000_cost->mulsi;
34917 else if (outer_code == AND)
34920 *total = COSTS_N_INSNS (1);
34925 if (GET_CODE (XEXP (x, 0)) == MEM)
34928 *total = COSTS_N_INSNS (1);
34934 if (!FLOAT_MODE_P (mode))
34936 *total = COSTS_N_INSNS (1);
34942 case UNSIGNED_FLOAT:
34945 case FLOAT_TRUNCATE:
34946 *total = rs6000_cost->fp;
34950 if (mode == DFmode)
34951 *total = rs6000_cost->sfdf_convert;
34953 *total = rs6000_cost->fp;
34957 switch (XINT (x, 1))
34960 *total = rs6000_cost->fp;
34972 *total = COSTS_N_INSNS (1);
34975 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
34977 *total = rs6000_cost->fp;
34986 /* Carry bit requires mode == Pmode.
34987 NEG or PLUS already counted so only add one. */
34989 && (outer_code == NEG || outer_code == PLUS))
34991 *total = COSTS_N_INSNS (1);
34999 if (outer_code == SET)
35001 if (XEXP (x, 1) == const0_rtx)
35003 *total = COSTS_N_INSNS (2);
35008 *total = COSTS_N_INSNS (3);
35013 if (outer_code == COMPARE)
35027 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
35030 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
35031 int opno, int *total, bool speed)
35033 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
35036 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
35037 "opno = %d, total = %d, speed = %s, x:\n",
35038 ret ? "complete" : "scan inner",
35039 GET_MODE_NAME (mode),
35040 GET_RTX_NAME (outer_code),
35043 speed ? "true" : "false");
35051 rs6000_insn_cost (rtx_insn *insn, bool speed)
35053 if (recog_memoized (insn) < 0)
35057 return get_attr_length (insn);
35059 int cost = get_attr_cost (insn);
35063 int n = get_attr_length (insn) / 4;
35064 enum attr_type type = get_attr_type (insn);
35071 cost = COSTS_N_INSNS (n + 1);
35075 switch (get_attr_size (insn))
35078 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
35081 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
35084 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
35087 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
35090 gcc_unreachable ();
35094 switch (get_attr_size (insn))
35097 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
35100 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
35103 gcc_unreachable ();
35108 cost = n * rs6000_cost->fp;
35111 cost = n * rs6000_cost->dmul;
35114 cost = n * rs6000_cost->sdiv;
35117 cost = n * rs6000_cost->ddiv;
35124 cost = COSTS_N_INSNS (n + 2);
35128 cost = COSTS_N_INSNS (n);
35134 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
35137 rs6000_debug_address_cost (rtx x, machine_mode mode,
35138 addr_space_t as, bool speed)
35140 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
35142 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
35143 ret, speed ? "true" : "false");
35150 /* A C expression returning the cost of moving data from a register of class
35151 CLASS1 to one of CLASS2. */
35154 rs6000_register_move_cost (machine_mode mode,
35155 reg_class_t from, reg_class_t to)
35159 if (TARGET_DEBUG_COST)
35162 /* Moves from/to GENERAL_REGS. */
35163 if (reg_classes_intersect_p (to, GENERAL_REGS)
35164 || reg_classes_intersect_p (from, GENERAL_REGS))
35166 reg_class_t rclass = from;
35168 if (! reg_classes_intersect_p (to, GENERAL_REGS))
35171 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
35172 ret = (rs6000_memory_move_cost (mode, rclass, false)
35173 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
35175 /* It's more expensive to move CR_REGS than CR0_REGS because of the
35177 else if (rclass == CR_REGS)
35180 /* For those processors that have slow LR/CTR moves, make them more
35181 expensive than memory in order to bias spills to memory .*/
35182 else if ((rs6000_tune == PROCESSOR_POWER6
35183 || rs6000_tune == PROCESSOR_POWER7
35184 || rs6000_tune == PROCESSOR_POWER8
35185 || rs6000_tune == PROCESSOR_POWER9)
35186 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
35187 ret = 6 * hard_regno_nregs (0, mode);
35190 /* A move will cost one instruction per GPR moved. */
35191 ret = 2 * hard_regno_nregs (0, mode);
35194 /* If we have VSX, we can easily move between FPR or Altivec registers. */
35195 else if (VECTOR_MEM_VSX_P (mode)
35196 && reg_classes_intersect_p (to, VSX_REGS)
35197 && reg_classes_intersect_p (from, VSX_REGS))
35198 ret = 2 * hard_regno_nregs (FIRST_FPR_REGNO, mode);
35200 /* Moving between two similar registers is just one instruction. */
35201 else if (reg_classes_intersect_p (to, from))
35202 ret = (FLOAT128_2REG_P (mode)) ? 4 : 2;
35204 /* Everything else has to go through GENERAL_REGS. */
35206 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
35207 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
35209 if (TARGET_DEBUG_COST)
35211 if (dbg_cost_ctrl == 1)
35213 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
35214 ret, GET_MODE_NAME (mode), reg_class_names[from],
35215 reg_class_names[to]);
35222 /* A C expressions returning the cost of moving data of MODE from a register to
35226 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
35227 bool in ATTRIBUTE_UNUSED)
35231 if (TARGET_DEBUG_COST)
35234 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
35235 ret = 4 * hard_regno_nregs (0, mode);
35236 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
35237 || reg_classes_intersect_p (rclass, VSX_REGS)))
35238 ret = 4 * hard_regno_nregs (32, mode);
35239 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
35240 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
35242 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
35244 if (TARGET_DEBUG_COST)
35246 if (dbg_cost_ctrl == 1)
35248 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
35249 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
35256 /* Returns a code for a target-specific builtin that implements
35257 reciprocal of the function, or NULL_TREE if not available. */
35260 rs6000_builtin_reciprocal (tree fndecl)
35262 switch (DECL_FUNCTION_CODE (fndecl))
35264 case VSX_BUILTIN_XVSQRTDP:
35265 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
35268 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
35270 case VSX_BUILTIN_XVSQRTSP:
35271 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
35274 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
35281 /* Load up a constant. If the mode is a vector mode, splat the value across
35282 all of the vector elements. */
35285 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
35289 if (mode == SFmode || mode == DFmode)
35291 rtx d = const_double_from_real_value (dconst, mode);
35292 reg = force_reg (mode, d);
35294 else if (mode == V4SFmode)
35296 rtx d = const_double_from_real_value (dconst, SFmode);
35297 rtvec v = gen_rtvec (4, d, d, d, d);
35298 reg = gen_reg_rtx (mode);
35299 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
35301 else if (mode == V2DFmode)
35303 rtx d = const_double_from_real_value (dconst, DFmode);
35304 rtvec v = gen_rtvec (2, d, d);
35305 reg = gen_reg_rtx (mode);
35306 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
35309 gcc_unreachable ();
35314 /* Generate an FMA instruction. */
35317 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
35319 machine_mode mode = GET_MODE (target);
35322 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
35323 gcc_assert (dst != NULL);
35326 emit_move_insn (target, dst);
35329 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
35332 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
35334 machine_mode mode = GET_MODE (dst);
35337 /* This is a tad more complicated, since the fnma_optab is for
35338 a different expression: fma(-m1, m2, a), which is the same
35339 thing except in the case of signed zeros.
35341 Fortunately we know that if FMA is supported that FNMSUB is
35342 also supported in the ISA. Just expand it directly. */
35344 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
35346 r = gen_rtx_NEG (mode, a);
35347 r = gen_rtx_FMA (mode, m1, m2, r);
35348 r = gen_rtx_NEG (mode, r);
35349 emit_insn (gen_rtx_SET (dst, r));
35352 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
35353 add a reg_note saying that this was a division. Support both scalar and
35354 vector divide. Assumes no trapping math and finite arguments. */
35357 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
35359 machine_mode mode = GET_MODE (dst);
35360 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
35363 /* Low precision estimates guarantee 5 bits of accuracy. High
35364 precision estimates guarantee 14 bits of accuracy. SFmode
35365 requires 23 bits of accuracy. DFmode requires 52 bits of
35366 accuracy. Each pass at least doubles the accuracy, leading
35367 to the following. */
35368 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35369 if (mode == DFmode || mode == V2DFmode)
35372 enum insn_code code = optab_handler (smul_optab, mode);
35373 insn_gen_fn gen_mul = GEN_FCN (code);
35375 gcc_assert (code != CODE_FOR_nothing);
35377 one = rs6000_load_constant_and_splat (mode, dconst1);
35379 /* x0 = 1./d estimate */
35380 x0 = gen_reg_rtx (mode);
35381 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
35384 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
35387 /* e0 = 1. - d * x0 */
35388 e0 = gen_reg_rtx (mode);
35389 rs6000_emit_nmsub (e0, d, x0, one);
35391 /* x1 = x0 + e0 * x0 */
35392 x1 = gen_reg_rtx (mode);
35393 rs6000_emit_madd (x1, e0, x0, x0);
35395 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
35396 ++i, xprev = xnext, eprev = enext) {
35398 /* enext = eprev * eprev */
35399 enext = gen_reg_rtx (mode);
35400 emit_insn (gen_mul (enext, eprev, eprev));
35402 /* xnext = xprev + enext * xprev */
35403 xnext = gen_reg_rtx (mode);
35404 rs6000_emit_madd (xnext, enext, xprev, xprev);
35410 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
35412 /* u = n * xprev */
35413 u = gen_reg_rtx (mode);
35414 emit_insn (gen_mul (u, n, xprev));
35416 /* v = n - (d * u) */
35417 v = gen_reg_rtx (mode);
35418 rs6000_emit_nmsub (v, d, u, n);
35420 /* dst = (v * xprev) + u */
35421 rs6000_emit_madd (dst, v, xprev, u);
35424 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
35427 /* Goldschmidt's Algorithm for single/double-precision floating point
35428 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
35431 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
35433 machine_mode mode = GET_MODE (src);
35434 rtx e = gen_reg_rtx (mode);
35435 rtx g = gen_reg_rtx (mode);
35436 rtx h = gen_reg_rtx (mode);
35438 /* Low precision estimates guarantee 5 bits of accuracy. High
35439 precision estimates guarantee 14 bits of accuracy. SFmode
35440 requires 23 bits of accuracy. DFmode requires 52 bits of
35441 accuracy. Each pass at least doubles the accuracy, leading
35442 to the following. */
35443 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
35444 if (mode == DFmode || mode == V2DFmode)
35449 enum insn_code code = optab_handler (smul_optab, mode);
35450 insn_gen_fn gen_mul = GEN_FCN (code);
35452 gcc_assert (code != CODE_FOR_nothing);
35454 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
35456 /* e = rsqrt estimate */
35457 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
35460 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
35463 rtx zero = force_reg (mode, CONST0_RTX (mode));
35465 if (mode == SFmode)
35467 rtx target = emit_conditional_move (e, GT, src, zero, mode,
35470 emit_move_insn (e, target);
35474 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
35475 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
35479 /* g = sqrt estimate. */
35480 emit_insn (gen_mul (g, e, src));
35481 /* h = 1/(2*sqrt) estimate. */
35482 emit_insn (gen_mul (h, e, mhalf));
35488 rtx t = gen_reg_rtx (mode);
35489 rs6000_emit_nmsub (t, g, h, mhalf);
35490 /* Apply correction directly to 1/rsqrt estimate. */
35491 rs6000_emit_madd (dst, e, t, e);
35495 for (i = 0; i < passes; i++)
35497 rtx t1 = gen_reg_rtx (mode);
35498 rtx g1 = gen_reg_rtx (mode);
35499 rtx h1 = gen_reg_rtx (mode);
35501 rs6000_emit_nmsub (t1, g, h, mhalf);
35502 rs6000_emit_madd (g1, g, t1, g);
35503 rs6000_emit_madd (h1, h, t1, h);
35508 /* Multiply by 2 for 1/rsqrt. */
35509 emit_insn (gen_add3_insn (dst, h, h));
35514 rtx t = gen_reg_rtx (mode);
35515 rs6000_emit_nmsub (t, g, h, mhalf);
35516 rs6000_emit_madd (dst, g, t, g);
35522 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
35523 (Power7) targets. DST is the target, and SRC is the argument operand. */
35526 rs6000_emit_popcount (rtx dst, rtx src)
35528 machine_mode mode = GET_MODE (dst);
35531 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
35532 if (TARGET_POPCNTD)
35534 if (mode == SImode)
35535 emit_insn (gen_popcntdsi2 (dst, src));
35537 emit_insn (gen_popcntddi2 (dst, src));
35541 tmp1 = gen_reg_rtx (mode);
35543 if (mode == SImode)
35545 emit_insn (gen_popcntbsi2 (tmp1, src));
35546 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
35548 tmp2 = force_reg (SImode, tmp2);
35549 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
35553 emit_insn (gen_popcntbdi2 (tmp1, src));
35554 tmp2 = expand_mult (DImode, tmp1,
35555 GEN_INT ((HOST_WIDE_INT)
35556 0x01010101 << 32 | 0x01010101),
35558 tmp2 = force_reg (DImode, tmp2);
35559 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
35564 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35565 target, and SRC is the argument operand. */
35568 rs6000_emit_parity (rtx dst, rtx src)
35570 machine_mode mode = GET_MODE (dst);
35573 tmp = gen_reg_rtx (mode);
35575 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35578 if (mode == SImode)
35580 emit_insn (gen_popcntbsi2 (tmp, src));
35581 emit_insn (gen_paritysi2_cmpb (dst, tmp));
35585 emit_insn (gen_popcntbdi2 (tmp, src));
35586 emit_insn (gen_paritydi2_cmpb (dst, tmp));
35591 if (mode == SImode)
35593 /* Is mult+shift >= shift+xor+shift+xor? */
35594 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
35596 rtx tmp1, tmp2, tmp3, tmp4;
35598 tmp1 = gen_reg_rtx (SImode);
35599 emit_insn (gen_popcntbsi2 (tmp1, src));
35601 tmp2 = gen_reg_rtx (SImode);
35602 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
35603 tmp3 = gen_reg_rtx (SImode);
35604 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
35606 tmp4 = gen_reg_rtx (SImode);
35607 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
35608 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
35611 rs6000_emit_popcount (tmp, src);
35612 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
35616 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35617 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
35619 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
35621 tmp1 = gen_reg_rtx (DImode);
35622 emit_insn (gen_popcntbdi2 (tmp1, src));
35624 tmp2 = gen_reg_rtx (DImode);
35625 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
35626 tmp3 = gen_reg_rtx (DImode);
35627 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
35629 tmp4 = gen_reg_rtx (DImode);
35630 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
35631 tmp5 = gen_reg_rtx (DImode);
35632 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
35634 tmp6 = gen_reg_rtx (DImode);
35635 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
35636 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
35639 rs6000_emit_popcount (tmp, src);
35640 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
35644 /* Expand an Altivec constant permutation for little endian mode.
35645 OP0 and OP1 are the input vectors and TARGET is the output vector.
35646 SEL specifies the constant permutation vector.
35648 There are two issues: First, the two input operands must be
35649 swapped so that together they form a double-wide array in LE
35650 order. Second, the vperm instruction has surprising behavior
35651 in LE mode: it interprets the elements of the source vectors
35652 in BE mode ("left to right") and interprets the elements of
35653 the destination vector in LE mode ("right to left"). To
35654 correct for this, we must subtract each element of the permute
35655 control vector from 31.
35657 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35658 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35659 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35660 serve as the permute control vector. Then, in BE mode,
35664 places the desired result in vr9. However, in LE mode the
35665 vector contents will be
35667 vr10 = 00000003 00000002 00000001 00000000
35668 vr11 = 00000007 00000006 00000005 00000004
35670 The result of the vperm using the same permute control vector is
35672 vr9 = 05000000 07000000 01000000 03000000
35674 That is, the leftmost 4 bytes of vr10 are interpreted as the
35675 source for the rightmost 4 bytes of vr9, and so on.
35677 If we change the permute control vector to
35679 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35687 vr9 = 00000006 00000004 00000002 00000000. */
35690 altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
35691 const vec_perm_indices &sel)
35695 rtx constv, unspec;
35697 /* Unpack and adjust the constant selector. */
35698 for (i = 0; i < 16; ++i)
35700 unsigned int elt = 31 - (sel[i] & 31);
35701 perm[i] = GEN_INT (elt);
35704 /* Expand to a permute, swapping the inputs and using the
35705 adjusted selector. */
35707 op0 = force_reg (V16QImode, op0);
35709 op1 = force_reg (V16QImode, op1);
35711 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
35712 constv = force_reg (V16QImode, constv);
35713 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
35715 if (!REG_P (target))
35717 rtx tmp = gen_reg_rtx (V16QImode);
35718 emit_move_insn (tmp, unspec);
35722 emit_move_insn (target, unspec);
35725 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35726 permute control vector. But here it's not a constant, so we must
35727 generate a vector NAND or NOR to do the adjustment. */
35730 altivec_expand_vec_perm_le (rtx operands[4])
35732 rtx notx, iorx, unspec;
35733 rtx target = operands[0];
35734 rtx op0 = operands[1];
35735 rtx op1 = operands[2];
35736 rtx sel = operands[3];
35738 rtx norreg = gen_reg_rtx (V16QImode);
35739 machine_mode mode = GET_MODE (target);
35741 /* Get everything in regs so the pattern matches. */
35743 op0 = force_reg (mode, op0);
35745 op1 = force_reg (mode, op1);
35747 sel = force_reg (V16QImode, sel);
35748 if (!REG_P (target))
35749 tmp = gen_reg_rtx (mode);
35751 if (TARGET_P9_VECTOR)
35753 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
35758 /* Invert the selector with a VNAND if available, else a VNOR.
35759 The VNAND is preferred for future fusion opportunities. */
35760 notx = gen_rtx_NOT (V16QImode, sel);
35761 iorx = (TARGET_P8_VECTOR
35762 ? gen_rtx_IOR (V16QImode, notx, notx)
35763 : gen_rtx_AND (V16QImode, notx, notx));
35764 emit_insn (gen_rtx_SET (norreg, iorx));
35766 /* Permute with operands reversed and adjusted selector. */
35767 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
35771 /* Copy into target, possibly by way of a register. */
35772 if (!REG_P (target))
35774 emit_move_insn (tmp, unspec);
35778 emit_move_insn (target, unspec);
35781 /* Expand an Altivec constant permutation. Return true if we match
35782 an efficient implementation; false to fall back to VPERM.
35784 OP0 and OP1 are the input vectors and TARGET is the output vector.
35785 SEL specifies the constant permutation vector. */
35788 altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
35789 const vec_perm_indices &sel)
35791 struct altivec_perm_insn {
35792 HOST_WIDE_INT mask;
35793 enum insn_code impl;
35794 unsigned char perm[16];
35796 static const struct altivec_perm_insn patterns[] = {
35797 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
35798 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35799 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
35800 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35801 { OPTION_MASK_ALTIVEC,
35802 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
35803 : CODE_FOR_altivec_vmrglb_direct),
35804 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35805 { OPTION_MASK_ALTIVEC,
35806 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
35807 : CODE_FOR_altivec_vmrglh_direct),
35808 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35809 { OPTION_MASK_ALTIVEC,
35810 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
35811 : CODE_FOR_altivec_vmrglw_direct),
35812 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35813 { OPTION_MASK_ALTIVEC,
35814 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
35815 : CODE_FOR_altivec_vmrghb_direct),
35816 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35817 { OPTION_MASK_ALTIVEC,
35818 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
35819 : CODE_FOR_altivec_vmrghh_direct),
35820 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35821 { OPTION_MASK_ALTIVEC,
35822 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
35823 : CODE_FOR_altivec_vmrghw_direct),
35824 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35825 { OPTION_MASK_P8_VECTOR,
35826 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
35827 : CODE_FOR_p8_vmrgow_v4sf_direct),
35828 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35829 { OPTION_MASK_P8_VECTOR,
35830 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
35831 : CODE_FOR_p8_vmrgew_v4sf_direct),
35832 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35835 unsigned int i, j, elt, which;
35836 unsigned char perm[16];
35840 /* Unpack the constant selector. */
35841 for (i = which = 0; i < 16; ++i)
35844 which |= (elt < 16 ? 1 : 2);
35848 /* Simplify the constant selector based on operands. */
35852 gcc_unreachable ();
35856 if (!rtx_equal_p (op0, op1))
35861 for (i = 0; i < 16; ++i)
35873 /* Look for splat patterns. */
35878 for (i = 0; i < 16; ++i)
35879 if (perm[i] != elt)
35883 if (!BYTES_BIG_ENDIAN)
35885 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35891 for (i = 0; i < 16; i += 2)
35892 if (perm[i] != elt || perm[i + 1] != elt + 1)
35896 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35897 x = gen_reg_rtx (V8HImode);
35898 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35900 emit_move_insn (target, gen_lowpart (V16QImode, x));
35907 for (i = 0; i < 16; i += 4)
35909 || perm[i + 1] != elt + 1
35910 || perm[i + 2] != elt + 2
35911 || perm[i + 3] != elt + 3)
35915 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35916 x = gen_reg_rtx (V4SImode);
35917 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35919 emit_move_insn (target, gen_lowpart (V16QImode, x));
35925 /* Look for merge and pack patterns. */
35926 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35930 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35933 elt = patterns[j].perm[0];
35934 if (perm[0] == elt)
35936 else if (perm[0] == elt + 16)
35940 for (i = 1; i < 16; ++i)
35942 elt = patterns[j].perm[i];
35944 elt = (elt >= 16 ? elt - 16 : elt + 16);
35945 else if (one_vec && elt >= 16)
35947 if (perm[i] != elt)
35952 enum insn_code icode = patterns[j].impl;
35953 machine_mode omode = insn_data[icode].operand[0].mode;
35954 machine_mode imode = insn_data[icode].operand[1].mode;
35956 /* For little-endian, don't use vpkuwum and vpkuhum if the
35957 underlying vector type is not V4SI and V8HI, respectively.
35958 For example, using vpkuwum with a V8HI picks up the even
35959 halfwords (BE numbering) when the even halfwords (LE
35960 numbering) are what we need. */
35961 if (!BYTES_BIG_ENDIAN
35962 && icode == CODE_FOR_altivec_vpkuwum_direct
35963 && ((GET_CODE (op0) == REG
35964 && GET_MODE (op0) != V4SImode)
35965 || (GET_CODE (op0) == SUBREG
35966 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
35968 if (!BYTES_BIG_ENDIAN
35969 && icode == CODE_FOR_altivec_vpkuhum_direct
35970 && ((GET_CODE (op0) == REG
35971 && GET_MODE (op0) != V8HImode)
35972 || (GET_CODE (op0) == SUBREG
35973 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
35976 /* For little-endian, the two input operands must be swapped
35977 (or swapped back) to ensure proper right-to-left numbering
35979 if (swapped ^ !BYTES_BIG_ENDIAN)
35980 std::swap (op0, op1);
35981 if (imode != V16QImode)
35983 op0 = gen_lowpart (imode, op0);
35984 op1 = gen_lowpart (imode, op1);
35986 if (omode == V16QImode)
35989 x = gen_reg_rtx (omode);
35990 emit_insn (GEN_FCN (icode) (x, op0, op1));
35991 if (omode != V16QImode)
35992 emit_move_insn (target, gen_lowpart (V16QImode, x));
35997 if (!BYTES_BIG_ENDIAN)
35999 altivec_expand_vec_perm_const_le (target, op0, op1, sel);
36006 /* Expand a Paired Single or VSX Permute Doubleword constant permutation.
36007 Return true if we match an efficient implementation. */
36010 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
36011 unsigned char perm0, unsigned char perm1)
36015 /* If both selectors come from the same operand, fold to single op. */
36016 if ((perm0 & 2) == (perm1 & 2))
36023 /* If both operands are equal, fold to simpler permutation. */
36024 if (rtx_equal_p (op0, op1))
36027 perm1 = (perm1 & 1) + 2;
36029 /* If the first selector comes from the second operand, swap. */
36030 else if (perm0 & 2)
36036 std::swap (op0, op1);
36038 /* If the second selector does not come from the second operand, fail. */
36039 else if ((perm1 & 2) == 0)
36043 if (target != NULL)
36045 machine_mode vmode, dmode;
36048 vmode = GET_MODE (target);
36049 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
36050 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
36051 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
36052 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
36053 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
36054 emit_insn (gen_rtx_SET (target, x));
36059 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
36062 rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
36063 rtx op1, const vec_perm_indices &sel)
36065 bool testing_p = !target;
36067 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
36068 if (TARGET_ALTIVEC && testing_p)
36071 /* Check for ps_merge* or xxpermdi insns. */
36072 if ((vmode == V2SFmode && TARGET_PAIRED_FLOAT)
36073 || ((vmode == V2DFmode || vmode == V2DImode)
36074 && VECTOR_MEM_VSX_P (vmode)))
36078 op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
36079 op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
36081 if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
36085 if (TARGET_ALTIVEC)
36087 /* Force the target-independent code to lower to V16QImode. */
36088 if (vmode != V16QImode)
36090 if (altivec_expand_vec_perm_const (target, op0, op1, sel))
36097 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
36098 OP0 and OP1 are the input vectors and TARGET is the output vector.
36099 PERM specifies the constant permutation vector. */
36102 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
36103 machine_mode vmode, const vec_perm_builder &perm)
36105 rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
36107 emit_move_insn (target, x);
36110 /* Expand an extract even operation. */
36113 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
36115 machine_mode vmode = GET_MODE (target);
36116 unsigned i, nelt = GET_MODE_NUNITS (vmode);
36117 vec_perm_builder perm (nelt, nelt, 1);
36119 for (i = 0; i < nelt; i++)
36120 perm.quick_push (i * 2);
36122 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
36125 /* Expand a vector interleave operation. */
36128 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
36130 machine_mode vmode = GET_MODE (target);
36131 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
36132 vec_perm_builder perm (nelt, nelt, 1);
36134 high = (highp ? 0 : nelt / 2);
36135 for (i = 0; i < nelt / 2; i++)
36137 perm.quick_push (i + high);
36138 perm.quick_push (i + nelt + high);
36141 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
36144 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
36146 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
36148 HOST_WIDE_INT hwi_scale (scale);
36149 REAL_VALUE_TYPE r_pow;
36150 rtvec v = rtvec_alloc (2);
36152 rtx scale_vec = gen_reg_rtx (V2DFmode);
36153 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
36154 elt = const_double_from_real_value (r_pow, DFmode);
36155 RTVEC_ELT (v, 0) = elt;
36156 RTVEC_ELT (v, 1) = elt;
36157 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
36158 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
36161 /* Return an RTX representing where to find the function value of a
36162 function returning MODE. */
36164 rs6000_complex_function_value (machine_mode mode)
36166 unsigned int regno;
36168 machine_mode inner = GET_MODE_INNER (mode);
36169 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
36171 if (TARGET_FLOAT128_TYPE
36173 || (mode == TCmode && TARGET_IEEEQUAD)))
36174 regno = ALTIVEC_ARG_RETURN;
36176 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36177 regno = FP_ARG_RETURN;
36181 regno = GP_ARG_RETURN;
36183 /* 32-bit is OK since it'll go in r3/r4. */
36184 if (TARGET_32BIT && inner_bytes >= 4)
36185 return gen_rtx_REG (mode, regno);
36188 if (inner_bytes >= 8)
36189 return gen_rtx_REG (mode, regno);
36191 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
36193 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
36194 GEN_INT (inner_bytes));
36195 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
36198 /* Return an rtx describing a return value of MODE as a PARALLEL
36199 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
36200 stride REG_STRIDE. */
36203 rs6000_parallel_return (machine_mode mode,
36204 int n_elts, machine_mode elt_mode,
36205 unsigned int regno, unsigned int reg_stride)
36207 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
36210 for (i = 0; i < n_elts; i++)
36212 rtx r = gen_rtx_REG (elt_mode, regno);
36213 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
36214 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
36215 regno += reg_stride;
36221 /* Target hook for TARGET_FUNCTION_VALUE.
36223 An integer value is in r3 and a floating-point value is in fp1,
36224 unless -msoft-float. */
36227 rs6000_function_value (const_tree valtype,
36228 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
36229 bool outgoing ATTRIBUTE_UNUSED)
36232 unsigned int regno;
36233 machine_mode elt_mode;
36236 /* Special handling for structs in darwin64. */
36238 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
36240 CUMULATIVE_ARGS valcum;
36244 valcum.fregno = FP_ARG_MIN_REG;
36245 valcum.vregno = ALTIVEC_ARG_MIN_REG;
36246 /* Do a trial code generation as if this were going to be passed as
36247 an argument; if any part goes in memory, we return NULL. */
36248 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
36251 /* Otherwise fall through to standard ABI rules. */
36254 mode = TYPE_MODE (valtype);
36256 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
36257 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
36259 int first_reg, n_regs;
36261 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
36263 /* _Decimal128 must use even/odd register pairs. */
36264 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36265 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
36269 first_reg = ALTIVEC_ARG_RETURN;
36273 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
36276 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
36277 if (TARGET_32BIT && TARGET_POWERPC64)
36286 int count = GET_MODE_SIZE (mode) / 4;
36287 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
36290 if ((INTEGRAL_TYPE_P (valtype)
36291 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
36292 || POINTER_TYPE_P (valtype))
36293 mode = TARGET_32BIT ? SImode : DImode;
36295 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36296 /* _Decimal128 must use an even/odd register pair. */
36297 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36298 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
36299 && !FLOAT128_VECTOR_P (mode)
36300 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
36301 regno = FP_ARG_RETURN;
36302 else if (TREE_CODE (valtype) == COMPLEX_TYPE
36303 && targetm.calls.split_complex_arg)
36304 return rs6000_complex_function_value (mode);
36305 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36306 return register is used in both cases, and we won't see V2DImode/V2DFmode
36307 for pure altivec, combine the two cases. */
36308 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
36309 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
36310 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
36311 regno = ALTIVEC_ARG_RETURN;
36313 regno = GP_ARG_RETURN;
36315 return gen_rtx_REG (mode, regno);
36318 /* Define how to find the value returned by a library function
36319 assuming the value has mode MODE. */
36321 rs6000_libcall_value (machine_mode mode)
36323 unsigned int regno;
36325 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
36326 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
36327 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
36329 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
36330 /* _Decimal128 must use an even/odd register pair. */
36331 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
36332 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode)
36333 && TARGET_HARD_FLOAT
36334 && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
36335 regno = FP_ARG_RETURN;
36336 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
36337 return register is used in both cases, and we won't see V2DImode/V2DFmode
36338 for pure altivec, combine the two cases. */
36339 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
36340 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
36341 regno = ALTIVEC_ARG_RETURN;
36342 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
36343 return rs6000_complex_function_value (mode);
36345 regno = GP_ARG_RETURN;
36347 return gen_rtx_REG (mode, regno);
36350 /* Compute register pressure classes. We implement the target hook to avoid
36351 IRA picking something like NON_SPECIAL_REGS as a pressure class, which can
36352 lead to incorrect estimates of number of available registers and therefor
36353 increased register pressure/spill. */
36355 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
36360 pressure_classes[n++] = GENERAL_REGS;
36362 pressure_classes[n++] = VSX_REGS;
36365 if (TARGET_ALTIVEC)
36366 pressure_classes[n++] = ALTIVEC_REGS;
36367 if (TARGET_HARD_FLOAT)
36368 pressure_classes[n++] = FLOAT_REGS;
36370 pressure_classes[n++] = CR_REGS;
36371 pressure_classes[n++] = SPECIAL_REGS;
36376 /* Given FROM and TO register numbers, say whether this elimination is allowed.
36377 Frame pointer elimination is automatically handled.
36379 For the RS/6000, if frame pointer elimination is being done, we would like
36380 to convert ap into fp, not sp.
36382 We need r30 if -mminimal-toc was specified, and there are constant pool
36386 rs6000_can_eliminate (const int from, const int to)
36388 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
36389 ? ! frame_pointer_needed
36390 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
36391 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
36392 || constant_pool_empty_p ()
36396 /* Define the offset between two registers, FROM to be eliminated and its
36397 replacement TO, at the start of a routine. */
36399 rs6000_initial_elimination_offset (int from, int to)
36401 rs6000_stack_t *info = rs6000_stack_info ();
36402 HOST_WIDE_INT offset;
36404 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36405 offset = info->push_p ? 0 : -info->total_size;
36406 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36408 offset = info->push_p ? 0 : -info->total_size;
36409 if (FRAME_GROWS_DOWNWARD)
36410 offset += info->fixed_size + info->vars_size + info->parm_size;
36412 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
36413 offset = FRAME_GROWS_DOWNWARD
36414 ? info->fixed_size + info->vars_size + info->parm_size
36416 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
36417 offset = info->total_size;
36418 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
36419 offset = info->push_p ? info->total_size : 0;
36420 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
36423 gcc_unreachable ();
36428 /* Fill in sizes of registers used by unwinder. */
36431 rs6000_init_dwarf_reg_sizes_extra (tree address)
36433 if (TARGET_MACHO && ! TARGET_ALTIVEC)
36436 machine_mode mode = TYPE_MODE (char_type_node);
36437 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
36438 rtx mem = gen_rtx_MEM (BLKmode, addr);
36439 rtx value = gen_int_mode (16, mode);
36441 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
36442 The unwinder still needs to know the size of Altivec registers. */
36444 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
36446 int column = DWARF_REG_TO_UNWIND_COLUMN
36447 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
36448 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
36450 emit_move_insn (adjust_address (mem, mode, offset), value);
36455 /* Map internal gcc register numbers to debug format register numbers.
36456 FORMAT specifies the type of debug register number to use:
36457 0 -- debug information, except for frame-related sections
36458 1 -- DWARF .debug_frame section
36459 2 -- DWARF .eh_frame section */
36462 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
36464 /* Except for the above, we use the internal number for non-DWARF
36465 debug information, and also for .eh_frame. */
36466 if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2)
36469 /* On some platforms, we use the standard DWARF register
36470 numbering for .debug_info and .debug_frame. */
36471 #ifdef RS6000_USE_DWARF_NUMBERING
36474 if (regno == LR_REGNO)
36476 if (regno == CTR_REGNO)
36478 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
36479 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
36480 The actual code emitted saves the whole of CR, so we map CR2_REGNO
36481 to the DWARF reg for CR. */
36482 if (format == 1 && regno == CR2_REGNO)
36484 if (CR_REGNO_P (regno))
36485 return regno - CR0_REGNO + 86;
36486 if (regno == CA_REGNO)
36487 return 101; /* XER */
36488 if (ALTIVEC_REGNO_P (regno))
36489 return regno - FIRST_ALTIVEC_REGNO + 1124;
36490 if (regno == VRSAVE_REGNO)
36492 if (regno == VSCR_REGNO)
36498 /* target hook eh_return_filter_mode */
36499 static scalar_int_mode
36500 rs6000_eh_return_filter_mode (void)
36502 return TARGET_32BIT ? SImode : word_mode;
36505 /* Target hook for scalar_mode_supported_p. */
36507 rs6000_scalar_mode_supported_p (scalar_mode mode)
36509 /* -m32 does not support TImode. This is the default, from
36510 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
36511 same ABI as for -m32. But default_scalar_mode_supported_p allows
36512 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
36513 for -mpowerpc64. */
36514 if (TARGET_32BIT && mode == TImode)
36517 if (DECIMAL_FLOAT_MODE_P (mode))
36518 return default_decimal_float_supported_p ();
36519 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
36522 return default_scalar_mode_supported_p (mode);
36525 /* Target hook for vector_mode_supported_p. */
36527 rs6000_vector_mode_supported_p (machine_mode mode)
36530 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
36533 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36534 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36536 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
36543 /* Target hook for floatn_mode. */
36544 static opt_scalar_float_mode
36545 rs6000_floatn_mode (int n, bool extended)
36555 if (TARGET_FLOAT128_TYPE)
36556 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36558 return opt_scalar_float_mode ();
36561 return opt_scalar_float_mode ();
36564 /* Those are the only valid _FloatNx types. */
36565 gcc_unreachable ();
36579 if (TARGET_FLOAT128_TYPE)
36580 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36582 return opt_scalar_float_mode ();
36585 return opt_scalar_float_mode ();
36591 /* Target hook for c_mode_for_suffix. */
36592 static machine_mode
36593 rs6000_c_mode_for_suffix (char suffix)
36595 if (TARGET_FLOAT128_TYPE)
36597 if (suffix == 'q' || suffix == 'Q')
36598 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36600 /* At the moment, we are not defining a suffix for IBM extended double.
36601 If/when the default for -mabi=ieeelongdouble is changed, and we want
36602 to support __ibm128 constants in legacy library code, we may need to
36603 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36604 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36605 __float80 constants. */
36611 /* Target hook for invalid_arg_for_unprototyped_fn. */
36612 static const char *
36613 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
36615 return (!rs6000_darwin64_abi
36617 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
36618 && (funcdecl == NULL_TREE
36619 || (TREE_CODE (funcdecl) == FUNCTION_DECL
36620 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
36621 ? N_("AltiVec argument passed to unprototyped function")
36625 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36626 setup by using __stack_chk_fail_local hidden function instead of
36627 calling __stack_chk_fail directly. Otherwise it is better to call
36628 __stack_chk_fail directly. */
36630 static tree ATTRIBUTE_UNUSED
36631 rs6000_stack_protect_fail (void)
36633 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
36634 ? default_hidden_stack_protect_fail ()
36635 : default_external_stack_protect_fail ();
36638 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36641 static unsigned HOST_WIDE_INT
36642 rs6000_asan_shadow_offset (void)
36644 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
36648 /* Mask options that we want to support inside of attribute((target)) and
36649 #pragma GCC target operations. Note, we do not include things like
36650 64/32-bit, endianness, hard/soft floating point, etc. that would have
36651 different calling sequences. */
36653 struct rs6000_opt_mask {
36654 const char *name; /* option name */
36655 HOST_WIDE_INT mask; /* mask to set */
36656 bool invert; /* invert sense of mask */
36657 bool valid_target; /* option is a target option */
36660 static struct rs6000_opt_mask const rs6000_opt_masks[] =
36662 { "altivec", OPTION_MASK_ALTIVEC, false, true },
36663 { "cmpb", OPTION_MASK_CMPB, false, true },
36664 { "crypto", OPTION_MASK_CRYPTO, false, true },
36665 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
36666 { "dlmzb", OPTION_MASK_DLMZB, false, true },
36667 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
36669 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
36670 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
36671 { "fprnd", OPTION_MASK_FPRND, false, true },
36672 { "hard-dfp", OPTION_MASK_DFP, false, true },
36673 { "htm", OPTION_MASK_HTM, false, true },
36674 { "isel", OPTION_MASK_ISEL, false, true },
36675 { "mfcrf", OPTION_MASK_MFCRF, false, true },
36676 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
36677 { "modulo", OPTION_MASK_MODULO, false, true },
36678 { "mulhw", OPTION_MASK_MULHW, false, true },
36679 { "multiple", OPTION_MASK_MULTIPLE, false, true },
36680 { "popcntb", OPTION_MASK_POPCNTB, false, true },
36681 { "popcntd", OPTION_MASK_POPCNTD, false, true },
36682 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
36683 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
36684 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
36685 { "power9-fusion", OPTION_MASK_P9_FUSION, false, true },
36686 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
36687 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
36688 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
36689 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
36690 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
36691 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
36692 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
36693 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
36694 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
36695 { "string", 0, false, true },
36696 { "toc-fusion", OPTION_MASK_TOC_FUSION, false, true },
36697 { "update", OPTION_MASK_NO_UPDATE, true , true },
36698 { "vsx", OPTION_MASK_VSX, false, true },
36699 #ifdef OPTION_MASK_64BIT
36701 { "aix64", OPTION_MASK_64BIT, false, false },
36702 { "aix32", OPTION_MASK_64BIT, true, false },
36704 { "64", OPTION_MASK_64BIT, false, false },
36705 { "32", OPTION_MASK_64BIT, true, false },
36708 #ifdef OPTION_MASK_EABI
36709 { "eabi", OPTION_MASK_EABI, false, false },
36711 #ifdef OPTION_MASK_LITTLE_ENDIAN
36712 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
36713 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
36715 #ifdef OPTION_MASK_RELOCATABLE
36716 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
36718 #ifdef OPTION_MASK_STRICT_ALIGN
36719 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
36721 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
36722 { "string", 0, false, false },
36725 /* Builtin mask mapping for printing the flags. */
36726 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
36728 { "altivec", RS6000_BTM_ALTIVEC, false, false },
36729 { "vsx", RS6000_BTM_VSX, false, false },
36730 { "paired", RS6000_BTM_PAIRED, false, false },
36731 { "fre", RS6000_BTM_FRE, false, false },
36732 { "fres", RS6000_BTM_FRES, false, false },
36733 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
36734 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
36735 { "popcntd", RS6000_BTM_POPCNTD, false, false },
36736 { "cell", RS6000_BTM_CELL, false, false },
36737 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
36738 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
36739 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
36740 { "crypto", RS6000_BTM_CRYPTO, false, false },
36741 { "htm", RS6000_BTM_HTM, false, false },
36742 { "hard-dfp", RS6000_BTM_DFP, false, false },
36743 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
36744 { "long-double-128", RS6000_BTM_LDBL128, false, false },
36745 { "float128", RS6000_BTM_FLOAT128, false, false },
36746 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
36749 /* Option variables that we want to support inside attribute((target)) and
36750 #pragma GCC target operations. */
36752 struct rs6000_opt_var {
36753 const char *name; /* option name */
36754 size_t global_offset; /* offset of the option in global_options. */
36755 size_t target_offset; /* offset of the option in target options. */
36758 static struct rs6000_opt_var const rs6000_opt_vars[] =
36761 offsetof (struct gcc_options, x_TARGET_FRIZ),
36762 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
36763 { "avoid-indexed-addresses",
36764 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
36765 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
36767 offsetof (struct gcc_options, x_rs6000_paired_float),
36768 offsetof (struct cl_target_option, x_rs6000_paired_float), },
36770 offsetof (struct gcc_options, x_rs6000_default_long_calls),
36771 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
36772 { "optimize-swaps",
36773 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
36774 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
36775 { "allow-movmisalign",
36776 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
36777 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
36779 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
36780 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
36782 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
36783 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
36784 { "align-branch-targets",
36785 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
36786 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
36788 offsetof (struct gcc_options, x_tls_markers),
36789 offsetof (struct cl_target_option, x_tls_markers), },
36791 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36792 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36794 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36795 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36796 { "speculate-indirect-jumps",
36797 offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
36798 offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
36801 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36802 parsing. Return true if there were no errors. */
36805 rs6000_inner_target_options (tree args, bool attr_p)
36809 if (args == NULL_TREE)
36812 else if (TREE_CODE (args) == STRING_CST)
36814 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36817 while ((q = strtok (p, ",")) != NULL)
36819 bool error_p = false;
36820 bool not_valid_p = false;
36821 const char *cpu_opt = NULL;
36824 if (strncmp (q, "cpu=", 4) == 0)
36826 int cpu_index = rs6000_cpu_name_lookup (q+4);
36827 if (cpu_index >= 0)
36828 rs6000_cpu_index = cpu_index;
36835 else if (strncmp (q, "tune=", 5) == 0)
36837 int tune_index = rs6000_cpu_name_lookup (q+5);
36838 if (tune_index >= 0)
36839 rs6000_tune_index = tune_index;
36849 bool invert = false;
36853 if (strncmp (r, "no-", 3) == 0)
36859 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36860 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36862 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36864 if (!rs6000_opt_masks[i].valid_target)
36865 not_valid_p = true;
36869 rs6000_isa_flags_explicit |= mask;
36871 /* VSX needs altivec, so -mvsx automagically sets
36872 altivec and disables -mavoid-indexed-addresses. */
36875 if (mask == OPTION_MASK_VSX)
36877 mask |= OPTION_MASK_ALTIVEC;
36878 TARGET_AVOID_XFORM = 0;
36882 if (rs6000_opt_masks[i].invert)
36886 rs6000_isa_flags &= ~mask;
36888 rs6000_isa_flags |= mask;
36893 if (error_p && !not_valid_p)
36895 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36896 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36898 size_t j = rs6000_opt_vars[i].global_offset;
36899 *((int *) ((char *)&global_options + j)) = !invert;
36901 not_valid_p = false;
36909 const char *eprefix, *esuffix;
36914 eprefix = "__attribute__((__target__(";
36919 eprefix = "#pragma GCC target ";
36924 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36926 else if (not_valid_p)
36927 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36929 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36934 else if (TREE_CODE (args) == TREE_LIST)
36938 tree value = TREE_VALUE (args);
36941 bool ret2 = rs6000_inner_target_options (value, attr_p);
36945 args = TREE_CHAIN (args);
36947 while (args != NULL_TREE);
36952 error ("attribute %<target%> argument not a string");
36959 /* Print out the target options as a list for -mdebug=target. */
36962 rs6000_debug_target_options (tree args, const char *prefix)
36964 if (args == NULL_TREE)
36965 fprintf (stderr, "%s<NULL>", prefix);
36967 else if (TREE_CODE (args) == STRING_CST)
36969 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36972 while ((q = strtok (p, ",")) != NULL)
36975 fprintf (stderr, "%s\"%s\"", prefix, q);
36980 else if (TREE_CODE (args) == TREE_LIST)
36984 tree value = TREE_VALUE (args);
36987 rs6000_debug_target_options (value, prefix);
36990 args = TREE_CHAIN (args);
36992 while (args != NULL_TREE);
36996 gcc_unreachable ();
37002 /* Hook to validate attribute((target("..."))). */
37005 rs6000_valid_attribute_p (tree fndecl,
37006 tree ARG_UNUSED (name),
37010 struct cl_target_option cur_target;
37013 tree new_target, new_optimize;
37014 tree func_optimize;
37016 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
37018 if (TARGET_DEBUG_TARGET)
37020 tree tname = DECL_NAME (fndecl);
37021 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
37023 fprintf (stderr, "function: %.*s\n",
37024 (int) IDENTIFIER_LENGTH (tname),
37025 IDENTIFIER_POINTER (tname));
37027 fprintf (stderr, "function: unknown\n");
37029 fprintf (stderr, "args:");
37030 rs6000_debug_target_options (args, " ");
37031 fprintf (stderr, "\n");
37034 fprintf (stderr, "flags: 0x%x\n", flags);
37036 fprintf (stderr, "--------------------\n");
37039 /* attribute((target("default"))) does nothing, beyond
37040 affecting multi-versioning. */
37041 if (TREE_VALUE (args)
37042 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
37043 && TREE_CHAIN (args) == NULL_TREE
37044 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
37047 old_optimize = build_optimization_node (&global_options);
37048 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
37050 /* If the function changed the optimization levels as well as setting target
37051 options, start with the optimizations specified. */
37052 if (func_optimize && func_optimize != old_optimize)
37053 cl_optimization_restore (&global_options,
37054 TREE_OPTIMIZATION (func_optimize));
37056 /* The target attributes may also change some optimization flags, so update
37057 the optimization options if necessary. */
37058 cl_target_option_save (&cur_target, &global_options);
37059 rs6000_cpu_index = rs6000_tune_index = -1;
37060 ret = rs6000_inner_target_options (args, true);
37062 /* Set up any additional state. */
37065 ret = rs6000_option_override_internal (false);
37066 new_target = build_target_option_node (&global_options);
37071 new_optimize = build_optimization_node (&global_options);
37078 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
37080 if (old_optimize != new_optimize)
37081 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
37084 cl_target_option_restore (&global_options, &cur_target);
37086 if (old_optimize != new_optimize)
37087 cl_optimization_restore (&global_options,
37088 TREE_OPTIMIZATION (old_optimize));
37094 /* Hook to validate the current #pragma GCC target and set the state, and
37095 update the macros based on what was changed. If ARGS is NULL, then
37096 POP_TARGET is used to reset the options. */
37099 rs6000_pragma_target_parse (tree args, tree pop_target)
37101 tree prev_tree = build_target_option_node (&global_options);
37103 struct cl_target_option *prev_opt, *cur_opt;
37104 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
37105 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
37107 if (TARGET_DEBUG_TARGET)
37109 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
37110 fprintf (stderr, "args:");
37111 rs6000_debug_target_options (args, " ");
37112 fprintf (stderr, "\n");
37116 fprintf (stderr, "pop_target:\n");
37117 debug_tree (pop_target);
37120 fprintf (stderr, "pop_target: <NULL>\n");
37122 fprintf (stderr, "--------------------\n");
37127 cur_tree = ((pop_target)
37129 : target_option_default_node);
37130 cl_target_option_restore (&global_options,
37131 TREE_TARGET_OPTION (cur_tree));
37135 rs6000_cpu_index = rs6000_tune_index = -1;
37136 if (!rs6000_inner_target_options (args, false)
37137 || !rs6000_option_override_internal (false)
37138 || (cur_tree = build_target_option_node (&global_options))
37141 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
37142 fprintf (stderr, "invalid pragma\n");
37148 target_option_current_node = cur_tree;
37149 rs6000_activate_target_options (target_option_current_node);
37151 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
37152 change the macros that are defined. */
37153 if (rs6000_target_modify_macros_ptr)
37155 prev_opt = TREE_TARGET_OPTION (prev_tree);
37156 prev_bumask = prev_opt->x_rs6000_builtin_mask;
37157 prev_flags = prev_opt->x_rs6000_isa_flags;
37159 cur_opt = TREE_TARGET_OPTION (cur_tree);
37160 cur_flags = cur_opt->x_rs6000_isa_flags;
37161 cur_bumask = cur_opt->x_rs6000_builtin_mask;
37163 diff_bumask = (prev_bumask ^ cur_bumask);
37164 diff_flags = (prev_flags ^ cur_flags);
37166 if ((diff_flags != 0) || (diff_bumask != 0))
37168 /* Delete old macros. */
37169 rs6000_target_modify_macros_ptr (false,
37170 prev_flags & diff_flags,
37171 prev_bumask & diff_bumask);
37173 /* Define new macros. */
37174 rs6000_target_modify_macros_ptr (true,
37175 cur_flags & diff_flags,
37176 cur_bumask & diff_bumask);
37184 /* Remember the last target of rs6000_set_current_function. */
37185 static GTY(()) tree rs6000_previous_fndecl;
37187 /* Restore target's globals from NEW_TREE and invalidate the
37188 rs6000_previous_fndecl cache. */
37191 rs6000_activate_target_options (tree new_tree)
37193 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
37194 if (TREE_TARGET_GLOBALS (new_tree))
37195 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
37196 else if (new_tree == target_option_default_node)
37197 restore_target_globals (&default_target_globals);
37199 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
37200 rs6000_previous_fndecl = NULL_TREE;
37203 /* Establish appropriate back-end context for processing the function
37204 FNDECL. The argument might be NULL to indicate processing at top
37205 level, outside of any function scope. */
37207 rs6000_set_current_function (tree fndecl)
37209 if (TARGET_DEBUG_TARGET)
37211 fprintf (stderr, "\n==================== rs6000_set_current_function");
37214 fprintf (stderr, ", fndecl %s (%p)",
37215 (DECL_NAME (fndecl)
37216 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
37217 : "<unknown>"), (void *)fndecl);
37219 if (rs6000_previous_fndecl)
37220 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
37222 fprintf (stderr, "\n");
37225 /* Only change the context if the function changes. This hook is called
37226 several times in the course of compiling a function, and we don't want to
37227 slow things down too much or call target_reinit when it isn't safe. */
37228 if (fndecl == rs6000_previous_fndecl)
37232 if (rs6000_previous_fndecl == NULL_TREE)
37233 old_tree = target_option_current_node;
37234 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
37235 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
37237 old_tree = target_option_default_node;
37240 if (fndecl == NULL_TREE)
37242 if (old_tree != target_option_current_node)
37243 new_tree = target_option_current_node;
37245 new_tree = NULL_TREE;
37249 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37250 if (new_tree == NULL_TREE)
37251 new_tree = target_option_default_node;
37254 if (TARGET_DEBUG_TARGET)
37258 fprintf (stderr, "\nnew fndecl target specific options:\n");
37259 debug_tree (new_tree);
37264 fprintf (stderr, "\nold fndecl target specific options:\n");
37265 debug_tree (old_tree);
37268 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
37269 fprintf (stderr, "--------------------\n");
37272 if (new_tree && old_tree != new_tree)
37273 rs6000_activate_target_options (new_tree);
37276 rs6000_previous_fndecl = fndecl;
37280 /* Save the current options */
37283 rs6000_function_specific_save (struct cl_target_option *ptr,
37284 struct gcc_options *opts)
37286 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
37287 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
37290 /* Restore the current options */
37293 rs6000_function_specific_restore (struct gcc_options *opts,
37294 struct cl_target_option *ptr)
37297 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
37298 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
37299 (void) rs6000_option_override_internal (false);
37302 /* Print the current options */
37305 rs6000_function_specific_print (FILE *file, int indent,
37306 struct cl_target_option *ptr)
37308 rs6000_print_isa_options (file, indent, "Isa options set",
37309 ptr->x_rs6000_isa_flags);
37311 rs6000_print_isa_options (file, indent, "Isa options explicit",
37312 ptr->x_rs6000_isa_flags_explicit);
37315 /* Helper function to print the current isa or misc options on a line. */
37318 rs6000_print_options_internal (FILE *file,
37320 const char *string,
37321 HOST_WIDE_INT flags,
37322 const char *prefix,
37323 const struct rs6000_opt_mask *opts,
37324 size_t num_elements)
37327 size_t start_column = 0;
37329 size_t max_column = 120;
37330 size_t prefix_len = strlen (prefix);
37331 size_t comma_len = 0;
37332 const char *comma = "";
37335 start_column += fprintf (file, "%*s", indent, "");
37339 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
37343 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
37345 /* Print the various mask options. */
37346 cur_column = start_column;
37347 for (i = 0; i < num_elements; i++)
37349 bool invert = opts[i].invert;
37350 const char *name = opts[i].name;
37351 const char *no_str = "";
37352 HOST_WIDE_INT mask = opts[i].mask;
37353 size_t len = comma_len + prefix_len + strlen (name);
37357 if ((flags & mask) == 0)
37360 len += sizeof ("no-") - 1;
37368 if ((flags & mask) != 0)
37371 len += sizeof ("no-") - 1;
37378 if (cur_column > max_column)
37380 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
37381 cur_column = start_column + len;
37385 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
37387 comma_len = sizeof (", ") - 1;
37390 fputs ("\n", file);
37393 /* Helper function to print the current isa options on a line. */
37396 rs6000_print_isa_options (FILE *file, int indent, const char *string,
37397 HOST_WIDE_INT flags)
37399 rs6000_print_options_internal (file, indent, string, flags, "-m",
37400 &rs6000_opt_masks[0],
37401 ARRAY_SIZE (rs6000_opt_masks));
37405 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
37406 HOST_WIDE_INT flags)
37408 rs6000_print_options_internal (file, indent, string, flags, "",
37409 &rs6000_builtin_mask_names[0],
37410 ARRAY_SIZE (rs6000_builtin_mask_names));
37413 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
37414 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
37415 -mupper-regs-df, etc.).
37417 If the user used -mno-power8-vector, we need to turn off all of the implicit
37418 ISA 2.07 and 3.0 options that relate to the vector unit.
37420 If the user used -mno-power9-vector, we need to turn off all of the implicit
37421 ISA 3.0 options that relate to the vector unit.
37423 This function does not handle explicit options such as the user specifying
37424 -mdirect-move. These are handled in rs6000_option_override_internal, and
37425 the appropriate error is given if needed.
37427 We return a mask of all of the implicit options that should not be enabled
37430 static HOST_WIDE_INT
37431 rs6000_disable_incompatible_switches (void)
37433 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
37436 static const struct {
37437 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
37438 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
37439 const char *const name; /* name of the switch. */
37441 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
37442 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
37443 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
37446 for (i = 0; i < ARRAY_SIZE (flags); i++)
37448 HOST_WIDE_INT no_flag = flags[i].no_flag;
37450 if ((rs6000_isa_flags & no_flag) == 0
37451 && (rs6000_isa_flags_explicit & no_flag) != 0)
37453 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
37454 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
37460 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
37461 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
37463 set_flags &= ~rs6000_opt_masks[j].mask;
37464 error ("%<-mno-%s%> turns off %<-m%s%>",
37466 rs6000_opt_masks[j].name);
37469 gcc_assert (!set_flags);
37472 rs6000_isa_flags &= ~dep_flags;
37473 ignore_masks |= no_flag | dep_flags;
37477 return ignore_masks;
37481 /* Helper function for printing the function name when debugging. */
37483 static const char *
37484 get_decl_name (tree fn)
37491 name = DECL_NAME (fn);
37493 return "<no-name>";
37495 return IDENTIFIER_POINTER (name);
37498 /* Return the clone id of the target we are compiling code for in a target
37499 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
37500 the priority list for the target clones (ordered from lowest to
37504 rs6000_clone_priority (tree fndecl)
37506 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37507 HOST_WIDE_INT isa_masks;
37508 int ret = CLONE_DEFAULT;
37509 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
37510 const char *attrs_str = NULL;
37512 attrs = TREE_VALUE (TREE_VALUE (attrs));
37513 attrs_str = TREE_STRING_POINTER (attrs);
37515 /* Return priority zero for default function. Return the ISA needed for the
37516 function if it is not the default. */
37517 if (strcmp (attrs_str, "default") != 0)
37519 if (fn_opts == NULL_TREE)
37520 fn_opts = target_option_default_node;
37522 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
37523 isa_masks = rs6000_isa_flags;
37525 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
37527 for (ret = CLONE_MAX - 1; ret != 0; ret--)
37528 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
37532 if (TARGET_DEBUG_TARGET)
37533 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
37534 get_decl_name (fndecl), ret);
37539 /* This compares the priority of target features in function DECL1 and DECL2.
37540 It returns positive value if DECL1 is higher priority, negative value if
37541 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37542 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37545 rs6000_compare_version_priority (tree decl1, tree decl2)
37547 int priority1 = rs6000_clone_priority (decl1);
37548 int priority2 = rs6000_clone_priority (decl2);
37549 int ret = priority1 - priority2;
37551 if (TARGET_DEBUG_TARGET)
37552 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
37553 get_decl_name (decl1), get_decl_name (decl2), ret);
37558 /* Make a dispatcher declaration for the multi-versioned function DECL.
37559 Calls to DECL function will be replaced with calls to the dispatcher
37560 by the front-end. Returns the decl of the dispatcher function. */
37563 rs6000_get_function_versions_dispatcher (void *decl)
37565 tree fn = (tree) decl;
37566 struct cgraph_node *node = NULL;
37567 struct cgraph_node *default_node = NULL;
37568 struct cgraph_function_version_info *node_v = NULL;
37569 struct cgraph_function_version_info *first_v = NULL;
37571 tree dispatch_decl = NULL;
37573 struct cgraph_function_version_info *default_version_info = NULL;
37574 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
37576 if (TARGET_DEBUG_TARGET)
37577 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
37578 get_decl_name (fn));
37580 node = cgraph_node::get (fn);
37581 gcc_assert (node != NULL);
37583 node_v = node->function_version ();
37584 gcc_assert (node_v != NULL);
37586 if (node_v->dispatcher_resolver != NULL)
37587 return node_v->dispatcher_resolver;
37589 /* Find the default version and make it the first node. */
37591 /* Go to the beginning of the chain. */
37592 while (first_v->prev != NULL)
37593 first_v = first_v->prev;
37595 default_version_info = first_v;
37596 while (default_version_info != NULL)
37598 const tree decl2 = default_version_info->this_node->decl;
37599 if (is_function_default_version (decl2))
37601 default_version_info = default_version_info->next;
37604 /* If there is no default node, just return NULL. */
37605 if (default_version_info == NULL)
37608 /* Make default info the first node. */
37609 if (first_v != default_version_info)
37611 default_version_info->prev->next = default_version_info->next;
37612 if (default_version_info->next)
37613 default_version_info->next->prev = default_version_info->prev;
37614 first_v->prev = default_version_info;
37615 default_version_info->next = first_v;
37616 default_version_info->prev = NULL;
37619 default_node = default_version_info->this_node;
37621 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37622 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37623 "target_clones attribute needs GLIBC (2.23 and newer) that "
37624 "exports hardware capability bits");
37627 if (targetm.has_ifunc_p ())
37629 struct cgraph_function_version_info *it_v = NULL;
37630 struct cgraph_node *dispatcher_node = NULL;
37631 struct cgraph_function_version_info *dispatcher_version_info = NULL;
37633 /* Right now, the dispatching is done via ifunc. */
37634 dispatch_decl = make_dispatcher_decl (default_node->decl);
37636 dispatcher_node = cgraph_node::get_create (dispatch_decl);
37637 gcc_assert (dispatcher_node != NULL);
37638 dispatcher_node->dispatcher_function = 1;
37639 dispatcher_version_info
37640 = dispatcher_node->insert_new_function_version ();
37641 dispatcher_version_info->next = default_version_info;
37642 dispatcher_node->definition = 1;
37644 /* Set the dispatcher for all the versions. */
37645 it_v = default_version_info;
37646 while (it_v != NULL)
37648 it_v->dispatcher_resolver = dispatch_decl;
37654 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37655 "multiversioning needs ifunc which is not supported "
37660 return dispatch_decl;
37663 /* Make the resolver function decl to dispatch the versions of a multi-
37664 versioned function, DEFAULT_DECL. Create an empty basic block in the
37665 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37669 make_resolver_func (const tree default_decl,
37670 const tree dispatch_decl,
37671 basic_block *empty_bb)
37673 /* Make the resolver function static. The resolver function returns
37675 tree decl_name = clone_function_name (default_decl, "resolver");
37676 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
37677 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
37678 tree decl = build_fn_decl (resolver_name, type);
37679 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
37681 DECL_NAME (decl) = decl_name;
37682 TREE_USED (decl) = 1;
37683 DECL_ARTIFICIAL (decl) = 1;
37684 DECL_IGNORED_P (decl) = 0;
37685 TREE_PUBLIC (decl) = 0;
37686 DECL_UNINLINABLE (decl) = 1;
37688 /* Resolver is not external, body is generated. */
37689 DECL_EXTERNAL (decl) = 0;
37690 DECL_EXTERNAL (dispatch_decl) = 0;
37692 DECL_CONTEXT (decl) = NULL_TREE;
37693 DECL_INITIAL (decl) = make_node (BLOCK);
37694 DECL_STATIC_CONSTRUCTOR (decl) = 0;
37696 /* Build result decl and add to function_decl. */
37697 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
37698 DECL_ARTIFICIAL (t) = 1;
37699 DECL_IGNORED_P (t) = 1;
37700 DECL_RESULT (decl) = t;
37702 gimplify_function_tree (decl);
37703 push_cfun (DECL_STRUCT_FUNCTION (decl));
37704 *empty_bb = init_lowered_empty_function (decl, false,
37705 profile_count::uninitialized ());
37707 cgraph_node::add_new_function (decl, true);
37708 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
37712 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37713 DECL_ATTRIBUTES (dispatch_decl)
37714 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
37716 cgraph_node::create_same_body_alias (dispatch_decl, decl);
37721 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37722 return a pointer to VERSION_DECL if we are running on a machine that
37723 supports the index CLONE_ISA hardware architecture bits. This function will
37724 be called during version dispatch to decide which function version to
37725 execute. It returns the basic block at the end, to which more conditions
37729 add_condition_to_bb (tree function_decl, tree version_decl,
37730 int clone_isa, basic_block new_bb)
37732 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
37734 gcc_assert (new_bb != NULL);
37735 gimple_seq gseq = bb_seq (new_bb);
37738 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
37739 build_fold_addr_expr (version_decl));
37740 tree result_var = create_tmp_var (ptr_type_node);
37741 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
37742 gimple *return_stmt = gimple_build_return (result_var);
37744 if (clone_isa == CLONE_DEFAULT)
37746 gimple_seq_add_stmt (&gseq, convert_stmt);
37747 gimple_seq_add_stmt (&gseq, return_stmt);
37748 set_bb_seq (new_bb, gseq);
37749 gimple_set_bb (convert_stmt, new_bb);
37750 gimple_set_bb (return_stmt, new_bb);
37755 tree bool_zero = build_int_cst (bool_int_type_node, 0);
37756 tree cond_var = create_tmp_var (bool_int_type_node);
37757 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
37758 const char *arg_str = rs6000_clone_map[clone_isa].name;
37759 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
37760 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
37761 gimple_call_set_lhs (call_cond_stmt, cond_var);
37763 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
37764 gimple_set_bb (call_cond_stmt, new_bb);
37765 gimple_seq_add_stmt (&gseq, call_cond_stmt);
37767 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
37768 NULL_TREE, NULL_TREE);
37769 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
37770 gimple_set_bb (if_else_stmt, new_bb);
37771 gimple_seq_add_stmt (&gseq, if_else_stmt);
37773 gimple_seq_add_stmt (&gseq, convert_stmt);
37774 gimple_seq_add_stmt (&gseq, return_stmt);
37775 set_bb_seq (new_bb, gseq);
37777 basic_block bb1 = new_bb;
37778 edge e12 = split_block (bb1, if_else_stmt);
37779 basic_block bb2 = e12->dest;
37780 e12->flags &= ~EDGE_FALLTHRU;
37781 e12->flags |= EDGE_TRUE_VALUE;
37783 edge e23 = split_block (bb2, return_stmt);
37784 gimple_set_bb (convert_stmt, bb2);
37785 gimple_set_bb (return_stmt, bb2);
37787 basic_block bb3 = e23->dest;
37788 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
37791 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
37797 /* This function generates the dispatch function for multi-versioned functions.
37798 DISPATCH_DECL is the function which will contain the dispatch logic.
37799 FNDECLS are the function choices for dispatch, and is a tree chain.
37800 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37801 code is generated. */
37804 dispatch_function_versions (tree dispatch_decl,
37806 basic_block *empty_bb)
37810 vec<tree> *fndecls;
37811 tree clones[CLONE_MAX];
37813 if (TARGET_DEBUG_TARGET)
37814 fputs ("dispatch_function_versions, top\n", stderr);
37816 gcc_assert (dispatch_decl != NULL
37817 && fndecls_p != NULL
37818 && empty_bb != NULL);
37820 /* fndecls_p is actually a vector. */
37821 fndecls = static_cast<vec<tree> *> (fndecls_p);
37823 /* At least one more version other than the default. */
37824 gcc_assert (fndecls->length () >= 2);
37826 /* The first version in the vector is the default decl. */
37827 memset ((void *) clones, '\0', sizeof (clones));
37828 clones[CLONE_DEFAULT] = (*fndecls)[0];
37830 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37831 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37832 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37833 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37834 to insert the code here to do the call. */
37836 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
37838 int priority = rs6000_clone_priority (ele);
37839 if (!clones[priority])
37840 clones[priority] = ele;
37843 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
37846 if (TARGET_DEBUG_TARGET)
37847 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
37848 ix, get_decl_name (clones[ix]));
37850 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37857 /* Generate the dispatching code body to dispatch multi-versioned function
37858 DECL. The target hook is called to process the "target" attributes and
37859 provide the code to dispatch the right function at run-time. NODE points
37860 to the dispatcher decl whose body will be created. */
37863 rs6000_generate_version_dispatcher_body (void *node_p)
37866 basic_block empty_bb;
37867 struct cgraph_node *node = (cgraph_node *) node_p;
37868 struct cgraph_function_version_info *ninfo = node->function_version ();
37870 if (ninfo->dispatcher_resolver)
37871 return ninfo->dispatcher_resolver;
37873 /* node is going to be an alias, so remove the finalized bit. */
37874 node->definition = false;
37876 /* The first version in the chain corresponds to the default version. */
37877 ninfo->dispatcher_resolver = resolver
37878 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37880 if (TARGET_DEBUG_TARGET)
37881 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37882 get_decl_name (resolver));
37884 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37885 auto_vec<tree, 2> fn_ver_vec;
37887 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37889 vinfo = vinfo->next)
37891 struct cgraph_node *version = vinfo->this_node;
37892 /* Check for virtual functions here again, as by this time it should
37893 have been determined if this function needs a vtable index or
37894 not. This happens for methods in derived classes that override
37895 virtual methods in base classes but are not explicitly marked as
37897 if (DECL_VINDEX (version->decl))
37898 sorry ("Virtual function multiversioning not supported");
37900 fn_ver_vec.safe_push (version->decl);
37903 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37904 cgraph_edge::rebuild_edges ();
37910 /* Hook to determine if one function can safely inline another. */
37913 rs6000_can_inline_p (tree caller, tree callee)
37916 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37917 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37919 /* If callee has no option attributes, then it is ok to inline. */
37923 /* If caller has no option attributes, but callee does then it is not ok to
37925 else if (!caller_tree)
37930 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37931 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37933 /* Callee's options should a subset of the caller's, i.e. a vsx function
37934 can inline an altivec function but a non-vsx function can't inline a
37936 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37937 == callee_opts->x_rs6000_isa_flags)
37941 if (TARGET_DEBUG_TARGET)
37942 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37943 get_decl_name (caller), get_decl_name (callee),
37944 (ret ? "can" : "cannot"));
37949 /* Allocate a stack temp and fixup the address so it meets the particular
37950 memory requirements (either offetable or REG+REG addressing). */
37953 rs6000_allocate_stack_temp (machine_mode mode,
37954 bool offsettable_p,
37957 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37958 rtx addr = XEXP (stack, 0);
37959 int strict_p = reload_completed;
37961 if (!legitimate_indirect_address_p (addr, strict_p))
37964 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
37965 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37967 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
37968 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37974 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
37975 to such a form to deal with memory reference instructions like STFIWX that
37976 only take reg+reg addressing. */
37979 rs6000_address_for_fpconvert (rtx x)
37983 gcc_assert (MEM_P (x));
37984 addr = XEXP (x, 0);
37985 if (can_create_pseudo_p ()
37986 && ! legitimate_indirect_address_p (addr, reload_completed)
37987 && ! legitimate_indexed_address_p (addr, reload_completed))
37989 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
37991 rtx reg = XEXP (addr, 0);
37992 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
37993 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
37994 gcc_assert (REG_P (reg));
37995 emit_insn (gen_add3_insn (reg, reg, size_rtx));
37998 else if (GET_CODE (addr) == PRE_MODIFY)
38000 rtx reg = XEXP (addr, 0);
38001 rtx expr = XEXP (addr, 1);
38002 gcc_assert (REG_P (reg));
38003 gcc_assert (GET_CODE (expr) == PLUS);
38004 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
38008 x = replace_equiv_address (x, copy_addr_to_reg (addr));
38014 /* Given a memory reference, if it is not in the form for altivec memory
38015 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
38016 convert to the altivec format. */
38019 rs6000_address_for_altivec (rtx x)
38021 gcc_assert (MEM_P (x));
38022 if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
38024 rtx addr = XEXP (x, 0);
38026 if (!legitimate_indexed_address_p (addr, reload_completed)
38027 && !legitimate_indirect_address_p (addr, reload_completed))
38028 addr = copy_to_mode_reg (Pmode, addr);
38030 addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
38031 x = change_address (x, GET_MODE (x), addr);
38037 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
38039 On the RS/6000, all integer constants are acceptable, most won't be valid
38040 for particular insns, though. Only easy FP constants are acceptable. */
38043 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
38045 if (TARGET_ELF && tls_referenced_p (x))
38048 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
38049 || GET_MODE (x) == VOIDmode
38050 || (TARGET_POWERPC64 && mode == DImode)
38051 || easy_fp_constant (x, mode)
38052 || easy_vector_constant (x, mode));
38056 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
38059 chain_already_loaded (rtx_insn *last)
38061 for (; last != NULL; last = PREV_INSN (last))
38063 if (NONJUMP_INSN_P (last))
38065 rtx patt = PATTERN (last);
38067 if (GET_CODE (patt) == SET)
38069 rtx lhs = XEXP (patt, 0);
38071 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
38079 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
38082 rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
38084 const bool direct_call_p
38085 = GET_CODE (func_desc) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (func_desc);
38086 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
38087 rtx toc_load = NULL_RTX;
38088 rtx toc_restore = NULL_RTX;
38090 rtx abi_reg = NULL_RTX;
38095 /* Handle longcall attributes. */
38096 if (INTVAL (cookie) & CALL_LONG)
38097 func_desc = rs6000_longcall_ref (func_desc);
38099 /* Handle indirect calls. */
38100 if (GET_CODE (func_desc) != SYMBOL_REF
38101 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc)))
38103 /* Save the TOC into its reserved slot before the call,
38104 and prepare to restore it after the call. */
38105 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
38106 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
38107 rtx stack_toc_mem = gen_frame_mem (Pmode,
38108 gen_rtx_PLUS (Pmode, stack_ptr,
38109 stack_toc_offset));
38110 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
38111 gen_rtvec (1, stack_toc_offset),
38113 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
38115 /* Can we optimize saving the TOC in the prologue or
38116 do we need to do it at every call? */
38117 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
38118 cfun->machine->save_toc_in_prologue = true;
38121 MEM_VOLATILE_P (stack_toc_mem) = 1;
38122 emit_move_insn (stack_toc_mem, toc_reg);
38125 if (DEFAULT_ABI == ABI_ELFv2)
38127 /* A function pointer in the ELFv2 ABI is just a plain address, but
38128 the ABI requires it to be loaded into r12 before the call. */
38129 func_addr = gen_rtx_REG (Pmode, 12);
38130 emit_move_insn (func_addr, func_desc);
38131 abi_reg = func_addr;
38135 /* A function pointer under AIX is a pointer to a data area whose
38136 first word contains the actual address of the function, whose
38137 second word contains a pointer to its TOC, and whose third word
38138 contains a value to place in the static chain register (r11).
38139 Note that if we load the static chain, our "trampoline" need
38140 not have any executable code. */
38142 /* Load up address of the actual function. */
38143 func_desc = force_reg (Pmode, func_desc);
38144 func_addr = gen_reg_rtx (Pmode);
38145 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
38147 /* Prepare to load the TOC of the called function. Note that the
38148 TOC load must happen immediately before the actual call so
38149 that unwinding the TOC registers works correctly. See the
38150 comment in frob_update_context. */
38151 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
38152 rtx func_toc_mem = gen_rtx_MEM (Pmode,
38153 gen_rtx_PLUS (Pmode, func_desc,
38155 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
38157 /* If we have a static chain, load it up. But, if the call was
38158 originally direct, the 3rd word has not been written since no
38159 trampoline has been built, so we ought not to load it, lest we
38160 override a static chain value. */
38162 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
38163 && !chain_already_loaded (get_current_sequence ()->next->last))
38165 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
38166 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
38167 rtx func_sc_mem = gen_rtx_MEM (Pmode,
38168 gen_rtx_PLUS (Pmode, func_desc,
38170 emit_move_insn (sc_reg, func_sc_mem);
38177 /* Direct calls use the TOC: for local calls, the callee will
38178 assume the TOC register is set; for non-local calls, the
38179 PLT stub needs the TOC register. */
38181 func_addr = func_desc;
38184 /* Create the call. */
38185 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag);
38186 if (value != NULL_RTX)
38187 call[0] = gen_rtx_SET (value, call[0]);
38191 call[n_call++] = toc_load;
38193 call[n_call++] = toc_restore;
38195 call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
38197 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
38198 insn = emit_call_insn (insn);
38200 /* Mention all registers defined by the ABI to hold information
38201 as uses in CALL_INSN_FUNCTION_USAGE. */
38203 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
38206 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
38209 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
38214 gcc_assert (INTVAL (cookie) == 0);
38216 /* Create the call. */
38217 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag);
38218 if (value != NULL_RTX)
38219 call[0] = gen_rtx_SET (value, call[0]);
38221 call[1] = simple_return_rtx;
38223 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
38224 insn = emit_call_insn (insn);
38226 /* Note use of the TOC register. */
38227 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
38230 /* Return whether we need to always update the saved TOC pointer when we update
38231 the stack pointer. */
38234 rs6000_save_toc_in_prologue_p (void)
38236 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
38239 #ifdef HAVE_GAS_HIDDEN
38240 # define USE_HIDDEN_LINKONCE 1
38242 # define USE_HIDDEN_LINKONCE 0
38245 /* Fills in the label name that should be used for a 476 link stack thunk. */
38248 get_ppc476_thunk_name (char name[32])
38250 gcc_assert (TARGET_LINK_STACK);
38252 if (USE_HIDDEN_LINKONCE)
38253 sprintf (name, "__ppc476.get_thunk");
38255 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
38258 /* This function emits the simple thunk routine that is used to preserve
38259 the link stack on the 476 cpu. */
38261 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
38263 rs6000_code_end (void)
38268 if (!TARGET_LINK_STACK)
38271 get_ppc476_thunk_name (name);
38273 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
38274 build_function_type_list (void_type_node, NULL_TREE));
38275 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
38276 NULL_TREE, void_type_node);
38277 TREE_PUBLIC (decl) = 1;
38278 TREE_STATIC (decl) = 1;
38281 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
38283 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
38284 targetm.asm_out.unique_section (decl, 0);
38285 switch_to_section (get_named_section (decl, NULL, 0));
38286 DECL_WEAK (decl) = 1;
38287 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
38288 targetm.asm_out.globalize_label (asm_out_file, name);
38289 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
38290 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
38295 switch_to_section (text_section);
38296 ASM_OUTPUT_LABEL (asm_out_file, name);
38299 DECL_INITIAL (decl) = make_node (BLOCK);
38300 current_function_decl = decl;
38301 allocate_struct_function (decl, false);
38302 init_function_start (decl);
38303 first_function_block_is_cold = false;
38304 /* Make sure unwind info is emitted for the thunk if needed. */
38305 final_start_function (emit_barrier (), asm_out_file, 1);
38307 fputs ("\tblr\n", asm_out_file);
38309 final_end_function ();
38310 init_insn_lengths ();
38311 free_after_compilation (cfun);
38313 current_function_decl = NULL;
38316 /* Add r30 to hard reg set if the prologue sets it up and it is not
38317 pic_offset_table_rtx. */
38320 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
38322 if (!TARGET_SINGLE_PIC_BASE
38324 && TARGET_MINIMAL_TOC
38325 && !constant_pool_empty_p ())
38326 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
38327 if (cfun->machine->split_stack_argp_used)
38328 add_to_hard_reg_set (&set->set, Pmode, 12);
38330 /* Make sure the hard reg set doesn't include r2, which was possibly added
38331 via PIC_OFFSET_TABLE_REGNUM. */
38333 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
38337 /* Helper function for rs6000_split_logical to emit a logical instruction after
38338 spliting the operation to single GPR registers.
38340 DEST is the destination register.
38341 OP1 and OP2 are the input source registers.
38342 CODE is the base operation (AND, IOR, XOR, NOT).
38343 MODE is the machine mode.
38344 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38345 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38346 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38349 rs6000_split_logical_inner (rtx dest,
38352 enum rtx_code code,
38354 bool complement_final_p,
38355 bool complement_op1_p,
38356 bool complement_op2_p)
38360 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38361 if (op2 && GET_CODE (op2) == CONST_INT
38362 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
38363 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38365 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
38366 HOST_WIDE_INT value = INTVAL (op2) & mask;
38368 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38373 emit_insn (gen_rtx_SET (dest, const0_rtx));
38377 else if (value == mask)
38379 if (!rtx_equal_p (dest, op1))
38380 emit_insn (gen_rtx_SET (dest, op1));
38385 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38386 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38387 else if (code == IOR || code == XOR)
38391 if (!rtx_equal_p (dest, op1))
38392 emit_insn (gen_rtx_SET (dest, op1));
38398 if (code == AND && mode == SImode
38399 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38401 emit_insn (gen_andsi3 (dest, op1, op2));
38405 if (complement_op1_p)
38406 op1 = gen_rtx_NOT (mode, op1);
38408 if (complement_op2_p)
38409 op2 = gen_rtx_NOT (mode, op2);
38411 /* For canonical RTL, if only one arm is inverted it is the first. */
38412 if (!complement_op1_p && complement_op2_p)
38413 std::swap (op1, op2);
38415 bool_rtx = ((code == NOT)
38416 ? gen_rtx_NOT (mode, op1)
38417 : gen_rtx_fmt_ee (code, mode, op1, op2));
38419 if (complement_final_p)
38420 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
38422 emit_insn (gen_rtx_SET (dest, bool_rtx));
38425 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38426 operations are split immediately during RTL generation to allow for more
38427 optimizations of the AND/IOR/XOR.
38429 OPERANDS is an array containing the destination and two input operands.
38430 CODE is the base operation (AND, IOR, XOR, NOT).
38431 MODE is the machine mode.
38432 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38433 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38434 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38435 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38436 formation of the AND instructions. */
38439 rs6000_split_logical_di (rtx operands[3],
38440 enum rtx_code code,
38441 bool complement_final_p,
38442 bool complement_op1_p,
38443 bool complement_op2_p)
38445 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
38446 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
38447 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
38448 enum hi_lo { hi = 0, lo = 1 };
38449 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
38452 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
38453 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
38454 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
38455 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
38458 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
38461 if (GET_CODE (operands[2]) != CONST_INT)
38463 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
38464 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
38468 HOST_WIDE_INT value = INTVAL (operands[2]);
38469 HOST_WIDE_INT value_hi_lo[2];
38471 gcc_assert (!complement_final_p);
38472 gcc_assert (!complement_op1_p);
38473 gcc_assert (!complement_op2_p);
38475 value_hi_lo[hi] = value >> 32;
38476 value_hi_lo[lo] = value & lower_32bits;
38478 for (i = 0; i < 2; i++)
38480 HOST_WIDE_INT sub_value = value_hi_lo[i];
38482 if (sub_value & sign_bit)
38483 sub_value |= upper_32bits;
38485 op2_hi_lo[i] = GEN_INT (sub_value);
38487 /* If this is an AND instruction, check to see if we need to load
38488 the value in a register. */
38489 if (code == AND && sub_value != -1 && sub_value != 0
38490 && !and_operand (op2_hi_lo[i], SImode))
38491 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
38496 for (i = 0; i < 2; i++)
38498 /* Split large IOR/XOR operations. */
38499 if ((code == IOR || code == XOR)
38500 && GET_CODE (op2_hi_lo[i]) == CONST_INT
38501 && !complement_final_p
38502 && !complement_op1_p
38503 && !complement_op2_p
38504 && !logical_const_operand (op2_hi_lo[i], SImode))
38506 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
38507 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
38508 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
38509 rtx tmp = gen_reg_rtx (SImode);
38511 /* Make sure the constant is sign extended. */
38512 if ((hi_16bits & sign_bit) != 0)
38513 hi_16bits |= upper_32bits;
38515 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
38516 code, SImode, false, false, false);
38518 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
38519 code, SImode, false, false, false);
38522 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
38523 code, SImode, complement_final_p,
38524 complement_op1_p, complement_op2_p);
38530 /* Split the insns that make up boolean operations operating on multiple GPR
38531 registers. The boolean MD patterns ensure that the inputs either are
38532 exactly the same as the output registers, or there is no overlap.
38534 OPERANDS is an array containing the destination and two input operands.
38535 CODE is the base operation (AND, IOR, XOR, NOT).
38536 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38537 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38538 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38541 rs6000_split_logical (rtx operands[3],
38542 enum rtx_code code,
38543 bool complement_final_p,
38544 bool complement_op1_p,
38545 bool complement_op2_p)
38547 machine_mode mode = GET_MODE (operands[0]);
38548 machine_mode sub_mode;
38550 int sub_size, regno0, regno1, nregs, i;
38552 /* If this is DImode, use the specialized version that can run before
38553 register allocation. */
38554 if (mode == DImode && !TARGET_POWERPC64)
38556 rs6000_split_logical_di (operands, code, complement_final_p,
38557 complement_op1_p, complement_op2_p);
38563 op2 = (code == NOT) ? NULL_RTX : operands[2];
38564 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
38565 sub_size = GET_MODE_SIZE (sub_mode);
38566 regno0 = REGNO (op0);
38567 regno1 = REGNO (op1);
38569 gcc_assert (reload_completed);
38570 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38571 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38573 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
38574 gcc_assert (nregs > 1);
38576 if (op2 && REG_P (op2))
38577 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
38579 for (i = 0; i < nregs; i++)
38581 int offset = i * sub_size;
38582 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
38583 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
38584 rtx sub_op2 = ((code == NOT)
38586 : simplify_subreg (sub_mode, op2, mode, offset));
38588 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
38589 complement_final_p, complement_op1_p,
38597 /* Return true if the peephole2 can combine a load involving a combination of
38598 an addis instruction and a load with an offset that can be fused together on
38602 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
38603 rtx addis_value, /* addis value. */
38604 rtx target, /* target register that is loaded. */
38605 rtx mem) /* bottom part of the memory addr. */
38610 /* Validate arguments. */
38611 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38614 if (!base_reg_operand (target, GET_MODE (target)))
38617 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38620 /* Allow sign/zero extension. */
38621 if (GET_CODE (mem) == ZERO_EXTEND
38622 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
38623 mem = XEXP (mem, 0);
38628 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
38631 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38632 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
38635 /* Validate that the register used to load the high value is either the
38636 register being loaded, or we can safely replace its use.
38638 This function is only called from the peephole2 pass and we assume that
38639 there are 2 instructions in the peephole (addis and load), so we want to
38640 check if the target register was not used in the memory address and the
38641 register to hold the addis result is dead after the peephole. */
38642 if (REGNO (addis_reg) != REGNO (target))
38644 if (reg_mentioned_p (target, mem))
38647 if (!peep2_reg_dead_p (2, addis_reg))
38650 /* If the target register being loaded is the stack pointer, we must
38651 avoid loading any other value into it, even temporarily. */
38652 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
38656 base_reg = XEXP (addr, 0);
38657 return REGNO (addis_reg) == REGNO (base_reg);
38660 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38661 sequence. We adjust the addis register to use the target register. If the
38662 load sign extends, we adjust the code to do the zero extending load, and an
38663 explicit sign extension later since the fusion only covers zero extending
38667 operands[0] register set with addis (to be replaced with target)
38668 operands[1] value set via addis
38669 operands[2] target register being loaded
38670 operands[3] D-form memory reference using operands[0]. */
38673 expand_fusion_gpr_load (rtx *operands)
38675 rtx addis_value = operands[1];
38676 rtx target = operands[2];
38677 rtx orig_mem = operands[3];
38678 rtx new_addr, new_mem, orig_addr, offset;
38679 enum rtx_code plus_or_lo_sum;
38680 machine_mode target_mode = GET_MODE (target);
38681 machine_mode extend_mode = target_mode;
38682 machine_mode ptr_mode = Pmode;
38683 enum rtx_code extend = UNKNOWN;
38685 if (GET_CODE (orig_mem) == ZERO_EXTEND
38686 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
38688 extend = GET_CODE (orig_mem);
38689 orig_mem = XEXP (orig_mem, 0);
38690 target_mode = GET_MODE (orig_mem);
38693 gcc_assert (MEM_P (orig_mem));
38695 orig_addr = XEXP (orig_mem, 0);
38696 plus_or_lo_sum = GET_CODE (orig_addr);
38697 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38699 offset = XEXP (orig_addr, 1);
38700 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38701 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38703 if (extend != UNKNOWN)
38704 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
38706 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
38707 UNSPEC_FUSION_GPR);
38708 emit_insn (gen_rtx_SET (target, new_mem));
38710 if (extend == SIGN_EXTEND)
38712 int sub_off = ((BYTES_BIG_ENDIAN)
38713 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
38716 = simplify_subreg (target_mode, target, extend_mode, sub_off);
38718 emit_insn (gen_rtx_SET (target,
38719 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
38725 /* Emit the addis instruction that will be part of a fused instruction
38729 emit_fusion_addis (rtx target, rtx addis_value)
38732 const char *addis_str = NULL;
38734 /* Emit the addis instruction. */
38735 fuse_ops[0] = target;
38736 if (satisfies_constraint_L (addis_value))
38738 fuse_ops[1] = addis_value;
38739 addis_str = "lis %0,%v1";
38742 else if (GET_CODE (addis_value) == PLUS)
38744 rtx op0 = XEXP (addis_value, 0);
38745 rtx op1 = XEXP (addis_value, 1);
38747 if (REG_P (op0) && CONST_INT_P (op1)
38748 && satisfies_constraint_L (op1))
38752 addis_str = "addis %0,%1,%v2";
38756 else if (GET_CODE (addis_value) == HIGH)
38758 rtx value = XEXP (addis_value, 0);
38759 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
38761 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
38762 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
38764 addis_str = "addis %0,%2,%1@toc@ha";
38766 else if (TARGET_XCOFF)
38767 addis_str = "addis %0,%1@u(%2)";
38770 gcc_unreachable ();
38773 else if (GET_CODE (value) == PLUS)
38775 rtx op0 = XEXP (value, 0);
38776 rtx op1 = XEXP (value, 1);
38778 if (GET_CODE (op0) == UNSPEC
38779 && XINT (op0, 1) == UNSPEC_TOCREL
38780 && CONST_INT_P (op1))
38782 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
38783 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
38786 addis_str = "addis %0,%2,%1+%3@toc@ha";
38788 else if (TARGET_XCOFF)
38789 addis_str = "addis %0,%1+%3@u(%2)";
38792 gcc_unreachable ();
38796 else if (satisfies_constraint_L (value))
38798 fuse_ops[1] = value;
38799 addis_str = "lis %0,%v1";
38802 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
38804 fuse_ops[1] = value;
38805 addis_str = "lis %0,%1@ha";
38810 fatal_insn ("Could not generate addis value for fusion", addis_value);
38812 output_asm_insn (addis_str, fuse_ops);
38815 /* Emit a D-form load or store instruction that is the second instruction
38816 of a fusion sequence. */
38819 emit_fusion_load_store (rtx load_store_reg, rtx addis_reg, rtx offset,
38820 const char *insn_str)
38823 char insn_template[80];
38825 fuse_ops[0] = load_store_reg;
38826 fuse_ops[1] = addis_reg;
38828 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
38830 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
38831 fuse_ops[2] = offset;
38832 output_asm_insn (insn_template, fuse_ops);
38835 else if (GET_CODE (offset) == UNSPEC
38836 && XINT (offset, 1) == UNSPEC_TOCREL)
38839 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
38841 else if (TARGET_XCOFF)
38842 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38845 gcc_unreachable ();
38847 fuse_ops[2] = XVECEXP (offset, 0, 0);
38848 output_asm_insn (insn_template, fuse_ops);
38851 else if (GET_CODE (offset) == PLUS
38852 && GET_CODE (XEXP (offset, 0)) == UNSPEC
38853 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
38854 && CONST_INT_P (XEXP (offset, 1)))
38856 rtx tocrel_unspec = XEXP (offset, 0);
38858 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
38860 else if (TARGET_XCOFF)
38861 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
38864 gcc_unreachable ();
38866 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
38867 fuse_ops[3] = XEXP (offset, 1);
38868 output_asm_insn (insn_template, fuse_ops);
38871 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
38873 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38875 fuse_ops[2] = offset;
38876 output_asm_insn (insn_template, fuse_ops);
38880 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38885 /* Wrap a TOC address that can be fused to indicate that special fusion
38886 processing is needed. */
38889 fusion_wrap_memory_address (rtx old_mem)
38891 rtx old_addr = XEXP (old_mem, 0);
38892 rtvec v = gen_rtvec (1, old_addr);
38893 rtx new_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_FUSION_ADDIS);
38894 return replace_equiv_address_nv (old_mem, new_addr, false);
38897 /* Given an address, convert it into the addis and load offset parts. Addresses
38898 created during the peephole2 process look like:
38899 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38900 (unspec [(...)] UNSPEC_TOCREL))
38902 Addresses created via toc fusion look like:
38903 (unspec [(unspec [(...)] UNSPEC_TOCREL)] UNSPEC_FUSION_ADDIS)) */
38906 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38910 if (GET_CODE (addr) == UNSPEC && XINT (addr, 1) == UNSPEC_FUSION_ADDIS)
38912 lo = XVECEXP (addr, 0, 0);
38913 hi = gen_rtx_HIGH (Pmode, lo);
38915 else if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38917 hi = XEXP (addr, 0);
38918 lo = XEXP (addr, 1);
38921 gcc_unreachable ();
38927 /* Return a string to fuse an addis instruction with a gpr load to the same
38928 register that we loaded up the addis instruction. The address that is used
38929 is the logical address that was formed during peephole2:
38930 (lo_sum (high) (low-part))
38932 Or the address is the TOC address that is wrapped before register allocation:
38933 (unspec [(addr) (toc-reg)] UNSPEC_FUSION_ADDIS)
38935 The code is complicated, so we call output_asm_insn directly, and just
38939 emit_fusion_gpr_load (rtx target, rtx mem)
38944 const char *load_str = NULL;
38947 if (GET_CODE (mem) == ZERO_EXTEND)
38948 mem = XEXP (mem, 0);
38950 gcc_assert (REG_P (target) && MEM_P (mem));
38952 addr = XEXP (mem, 0);
38953 fusion_split_address (addr, &addis_value, &load_offset);
38955 /* Now emit the load instruction to the same register. */
38956 mode = GET_MODE (mem);
38974 gcc_assert (TARGET_POWERPC64);
38979 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
38982 /* Emit the addis instruction. */
38983 emit_fusion_addis (target, addis_value);
38985 /* Emit the D-form load instruction. */
38986 emit_fusion_load_store (target, target, load_offset, load_str);
38992 /* Return true if the peephole2 can combine a load/store involving a
38993 combination of an addis instruction and the memory operation. This was
38994 added to the ISA 3.0 (power9) hardware. */
38997 fusion_p9_p (rtx addis_reg, /* register set via addis. */
38998 rtx addis_value, /* addis value. */
38999 rtx dest, /* destination (memory or register). */
39000 rtx src) /* source (register or memory). */
39002 rtx addr, mem, offset;
39003 machine_mode mode = GET_MODE (src);
39005 /* Validate arguments. */
39006 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
39009 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
39012 /* Ignore extend operations that are part of the load. */
39013 if (GET_CODE (src) == FLOAT_EXTEND || GET_CODE (src) == ZERO_EXTEND)
39014 src = XEXP (src, 0);
39016 /* Test for memory<-register or register<-memory. */
39017 if (fpr_reg_operand (src, mode) || int_reg_operand (src, mode))
39025 else if (MEM_P (src))
39027 if (!fpr_reg_operand (dest, mode) && !int_reg_operand (dest, mode))
39036 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
39037 if (GET_CODE (addr) == PLUS)
39039 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
39042 return satisfies_constraint_I (XEXP (addr, 1));
39045 else if (GET_CODE (addr) == LO_SUM)
39047 if (!rtx_equal_p (addis_reg, XEXP (addr, 0)))
39050 offset = XEXP (addr, 1);
39051 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
39052 return small_toc_ref (offset, GET_MODE (offset));
39054 else if (TARGET_ELF && !TARGET_POWERPC64)
39055 return CONSTANT_P (offset);
39061 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
39065 operands[0] register set with addis
39066 operands[1] value set via addis
39067 operands[2] target register being loaded
39068 operands[3] D-form memory reference using operands[0].
39070 This is similar to the fusion introduced with power8, except it scales to
39071 both loads/stores and does not require the result register to be the same as
39072 the base register. At the moment, we only do this if register set with addis
39076 expand_fusion_p9_load (rtx *operands)
39078 rtx tmp_reg = operands[0];
39079 rtx addis_value = operands[1];
39080 rtx target = operands[2];
39081 rtx orig_mem = operands[3];
39082 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn;
39083 enum rtx_code plus_or_lo_sum;
39084 machine_mode target_mode = GET_MODE (target);
39085 machine_mode extend_mode = target_mode;
39086 machine_mode ptr_mode = Pmode;
39087 enum rtx_code extend = UNKNOWN;
39089 if (GET_CODE (orig_mem) == FLOAT_EXTEND || GET_CODE (orig_mem) == ZERO_EXTEND)
39091 extend = GET_CODE (orig_mem);
39092 orig_mem = XEXP (orig_mem, 0);
39093 target_mode = GET_MODE (orig_mem);
39096 gcc_assert (MEM_P (orig_mem));
39098 orig_addr = XEXP (orig_mem, 0);
39099 plus_or_lo_sum = GET_CODE (orig_addr);
39100 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
39102 offset = XEXP (orig_addr, 1);
39103 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
39104 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
39106 if (extend != UNKNOWN)
39107 new_mem = gen_rtx_fmt_e (extend, extend_mode, new_mem);
39109 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
39112 set = gen_rtx_SET (target, new_mem);
39113 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
39114 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
39120 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
39124 operands[0] register set with addis
39125 operands[1] value set via addis
39126 operands[2] target D-form memory being stored to
39127 operands[3] register being stored
39129 This is similar to the fusion introduced with power8, except it scales to
39130 both loads/stores and does not require the result register to be the same as
39131 the base register. At the moment, we only do this if register set with addis
39135 expand_fusion_p9_store (rtx *operands)
39137 rtx tmp_reg = operands[0];
39138 rtx addis_value = operands[1];
39139 rtx orig_mem = operands[2];
39140 rtx src = operands[3];
39141 rtx new_addr, new_mem, orig_addr, offset, set, clobber, insn, new_src;
39142 enum rtx_code plus_or_lo_sum;
39143 machine_mode target_mode = GET_MODE (orig_mem);
39144 machine_mode ptr_mode = Pmode;
39146 gcc_assert (MEM_P (orig_mem));
39148 orig_addr = XEXP (orig_mem, 0);
39149 plus_or_lo_sum = GET_CODE (orig_addr);
39150 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
39152 offset = XEXP (orig_addr, 1);
39153 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
39154 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
39156 new_src = gen_rtx_UNSPEC (target_mode, gen_rtvec (1, src),
39159 set = gen_rtx_SET (new_mem, new_src);
39160 clobber = gen_rtx_CLOBBER (VOIDmode, tmp_reg);
39161 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber));
39167 /* Return a string to fuse an addis instruction with a load using extended
39168 fusion. The address that is used is the logical address that was formed
39169 during peephole2: (lo_sum (high) (low-part))
39171 The code is complicated, so we call output_asm_insn directly, and just
39175 emit_fusion_p9_load (rtx reg, rtx mem, rtx tmp_reg)
39177 machine_mode mode = GET_MODE (reg);
39181 const char *load_string;
39184 if (GET_CODE (mem) == FLOAT_EXTEND || GET_CODE (mem) == ZERO_EXTEND)
39186 mem = XEXP (mem, 0);
39187 mode = GET_MODE (mem);
39190 if (GET_CODE (reg) == SUBREG)
39192 gcc_assert (SUBREG_BYTE (reg) == 0);
39193 reg = SUBREG_REG (reg);
39197 fatal_insn ("emit_fusion_p9_load, bad reg #1", reg);
39200 if (FP_REGNO_P (r))
39202 if (mode == SFmode)
39203 load_string = "lfs";
39204 else if (mode == DFmode || mode == DImode)
39205 load_string = "lfd";
39207 gcc_unreachable ();
39209 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
39211 if (mode == SFmode)
39212 load_string = "lxssp";
39213 else if (mode == DFmode || mode == DImode)
39214 load_string = "lxsd";
39216 gcc_unreachable ();
39218 else if (INT_REGNO_P (r))
39223 load_string = "lbz";
39226 load_string = "lhz";
39230 load_string = "lwz";
39234 if (!TARGET_POWERPC64)
39235 gcc_unreachable ();
39236 load_string = "ld";
39239 gcc_unreachable ();
39243 fatal_insn ("emit_fusion_p9_load, bad reg #2", reg);
39246 fatal_insn ("emit_fusion_p9_load not MEM", mem);
39248 addr = XEXP (mem, 0);
39249 fusion_split_address (addr, &hi, &lo);
39251 /* Emit the addis instruction. */
39252 emit_fusion_addis (tmp_reg, hi);
39254 /* Emit the D-form load instruction. */
39255 emit_fusion_load_store (reg, tmp_reg, lo, load_string);
39260 /* Return a string to fuse an addis instruction with a store using extended
39261 fusion. The address that is used is the logical address that was formed
39262 during peephole2: (lo_sum (high) (low-part))
39264 The code is complicated, so we call output_asm_insn directly, and just
39268 emit_fusion_p9_store (rtx mem, rtx reg, rtx tmp_reg)
39270 machine_mode mode = GET_MODE (reg);
39274 const char *store_string;
39277 if (GET_CODE (reg) == SUBREG)
39279 gcc_assert (SUBREG_BYTE (reg) == 0);
39280 reg = SUBREG_REG (reg);
39284 fatal_insn ("emit_fusion_p9_store, bad reg #1", reg);
39287 if (FP_REGNO_P (r))
39289 if (mode == SFmode)
39290 store_string = "stfs";
39291 else if (mode == DFmode)
39292 store_string = "stfd";
39294 gcc_unreachable ();
39296 else if (ALTIVEC_REGNO_P (r) && TARGET_P9_VECTOR)
39298 if (mode == SFmode)
39299 store_string = "stxssp";
39300 else if (mode == DFmode || mode == DImode)
39301 store_string = "stxsd";
39303 gcc_unreachable ();
39305 else if (INT_REGNO_P (r))
39310 store_string = "stb";
39313 store_string = "sth";
39317 store_string = "stw";
39321 if (!TARGET_POWERPC64)
39322 gcc_unreachable ();
39323 store_string = "std";
39326 gcc_unreachable ();
39330 fatal_insn ("emit_fusion_p9_store, bad reg #2", reg);
39333 fatal_insn ("emit_fusion_p9_store not MEM", mem);
39335 addr = XEXP (mem, 0);
39336 fusion_split_address (addr, &hi, &lo);
39338 /* Emit the addis instruction. */
39339 emit_fusion_addis (tmp_reg, hi);
39341 /* Emit the D-form load instruction. */
39342 emit_fusion_load_store (reg, tmp_reg, lo, store_string);
39347 #ifdef RS6000_GLIBC_ATOMIC_FENV
39348 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
39349 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
39352 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
39355 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
39357 if (!TARGET_HARD_FLOAT)
39359 #ifdef RS6000_GLIBC_ATOMIC_FENV
39360 if (atomic_hold_decl == NULL_TREE)
39363 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39364 get_identifier ("__atomic_feholdexcept"),
39365 build_function_type_list (void_type_node,
39366 double_ptr_type_node,
39368 TREE_PUBLIC (atomic_hold_decl) = 1;
39369 DECL_EXTERNAL (atomic_hold_decl) = 1;
39372 if (atomic_clear_decl == NULL_TREE)
39375 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39376 get_identifier ("__atomic_feclearexcept"),
39377 build_function_type_list (void_type_node,
39379 TREE_PUBLIC (atomic_clear_decl) = 1;
39380 DECL_EXTERNAL (atomic_clear_decl) = 1;
39383 tree const_double = build_qualified_type (double_type_node,
39385 tree const_double_ptr = build_pointer_type (const_double);
39386 if (atomic_update_decl == NULL_TREE)
39389 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
39390 get_identifier ("__atomic_feupdateenv"),
39391 build_function_type_list (void_type_node,
39394 TREE_PUBLIC (atomic_update_decl) = 1;
39395 DECL_EXTERNAL (atomic_update_decl) = 1;
39398 tree fenv_var = create_tmp_var_raw (double_type_node);
39399 TREE_ADDRESSABLE (fenv_var) = 1;
39400 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
39402 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
39403 *clear = build_call_expr (atomic_clear_decl, 0);
39404 *update = build_call_expr (atomic_update_decl, 1,
39405 fold_convert (const_double_ptr, fenv_addr));
39410 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
39411 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
39412 tree call_mffs = build_call_expr (mffs, 0);
39414 /* Generates the equivalent of feholdexcept (&fenv_var)
39416 *fenv_var = __builtin_mffs ();
39418 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
39419 __builtin_mtfsf (0xff, fenv_hold); */
39421 /* Mask to clear everything except for the rounding modes and non-IEEE
39422 arithmetic flag. */
39423 const unsigned HOST_WIDE_INT hold_exception_mask =
39424 HOST_WIDE_INT_C (0xffffffff00000007);
39426 tree fenv_var = create_tmp_var_raw (double_type_node);
39428 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
39430 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
39431 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39432 build_int_cst (uint64_type_node,
39433 hold_exception_mask));
39435 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39438 tree hold_mtfsf = build_call_expr (mtfsf, 2,
39439 build_int_cst (unsigned_type_node, 0xff),
39442 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
39444 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
39446 double fenv_clear = __builtin_mffs ();
39447 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
39448 __builtin_mtfsf (0xff, fenv_clear); */
39450 /* Mask to clear everything except for the rounding modes and non-IEEE
39451 arithmetic flag. */
39452 const unsigned HOST_WIDE_INT clear_exception_mask =
39453 HOST_WIDE_INT_C (0xffffffff00000000);
39455 tree fenv_clear = create_tmp_var_raw (double_type_node);
39457 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
39459 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
39460 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
39462 build_int_cst (uint64_type_node,
39463 clear_exception_mask));
39465 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39466 fenv_clear_llu_and);
39468 tree clear_mtfsf = build_call_expr (mtfsf, 2,
39469 build_int_cst (unsigned_type_node, 0xff),
39472 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
39474 /* Generates the equivalent of feupdateenv (&fenv_var)
39476 double old_fenv = __builtin_mffs ();
39477 double fenv_update;
39478 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
39479 (*(uint64_t*)fenv_var 0x1ff80fff);
39480 __builtin_mtfsf (0xff, fenv_update); */
39482 const unsigned HOST_WIDE_INT update_exception_mask =
39483 HOST_WIDE_INT_C (0xffffffff1fffff00);
39484 const unsigned HOST_WIDE_INT new_exception_mask =
39485 HOST_WIDE_INT_C (0x1ff80fff);
39487 tree old_fenv = create_tmp_var_raw (double_type_node);
39488 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
39490 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
39491 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
39492 build_int_cst (uint64_type_node,
39493 update_exception_mask));
39495 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
39496 build_int_cst (uint64_type_node,
39497 new_exception_mask));
39499 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
39500 old_llu_and, new_llu_and);
39502 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
39505 tree update_mtfsf = build_call_expr (mtfsf, 2,
39506 build_int_cst (unsigned_type_node, 0xff),
39507 fenv_update_mtfsf);
39509 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
39513 rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
39515 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39517 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39518 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39520 /* The destination of the vmrgew instruction layout is:
39521 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39522 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39523 vmrgew instruction will be correct. */
39524 if (VECTOR_ELT_ORDER_BIG)
39526 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
39528 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
39533 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
39534 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
39537 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39538 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39540 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
39541 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
39543 if (VECTOR_ELT_ORDER_BIG)
39544 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39546 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39550 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
39552 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39554 rtx_tmp0 = gen_reg_rtx (V2DImode);
39555 rtx_tmp1 = gen_reg_rtx (V2DImode);
39557 /* The destination of the vmrgew instruction layout is:
39558 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39559 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39560 vmrgew instruction will be correct. */
39561 if (VECTOR_ELT_ORDER_BIG)
39563 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
39564 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
39568 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
39569 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
39572 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39573 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39575 if (signed_convert)
39577 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
39578 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
39582 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
39583 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
39586 if (VECTOR_ELT_ORDER_BIG)
39587 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39589 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39593 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
39596 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39598 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39599 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39601 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
39602 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
39604 rtx_tmp2 = gen_reg_rtx (V4SImode);
39605 rtx_tmp3 = gen_reg_rtx (V4SImode);
39607 if (signed_convert)
39609 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
39610 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
39614 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
39615 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
39618 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
39621 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39624 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
39625 optimization_type opt_type)
39630 return (opt_type == OPTIMIZE_FOR_SPEED
39631 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
39638 /* Implement TARGET_CONSTANT_ALIGNMENT. */
39640 static HOST_WIDE_INT
39641 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
39643 if (TREE_CODE (exp) == STRING_CST
39644 && (STRICT_ALIGNMENT || !optimize_size))
39645 return MAX (align, BITS_PER_WORD);
39649 /* Implement TARGET_STARTING_FRAME_OFFSET. */
39651 static HOST_WIDE_INT
39652 rs6000_starting_frame_offset (void)
39654 if (FRAME_GROWS_DOWNWARD)
39656 return RS6000_STARTING_FRAME_OFFSET;
39659 struct gcc_target targetm = TARGET_INITIALIZER;
39661 #include "gt-rs6000.h"