1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2019 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
35 #include "stringpool.h"
42 #include "diagnostic-core.h"
43 #include "insn-attr.h"
46 #include "fold-const.h"
48 #include "stor-layout.h"
50 #include "print-tree.h"
56 #include "common/common-target.h"
57 #include "langhooks.h"
59 #include "sched-int.h"
61 #include "gimple-fold.h"
62 #include "gimple-iterator.h"
63 #include "gimple-ssa.h"
64 #include "gimple-walk.h"
67 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
69 #include "target-globals.h"
71 #include "tree-vector-builder.h"
73 #include "tree-pass.h"
76 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
79 #include "gstab.h" /* for N_SLINE */
81 #include "case-cfn-macros.h"
83 #include "tree-ssa-propagate.h"
85 #include "tree-ssanames.h"
87 /* This file should be included last. */
88 #include "target-def.h"
90 #ifndef TARGET_NO_PROTOTYPE
91 #define TARGET_NO_PROTOTYPE 0
94 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
95 systems will also set long double to be IEEE 128-bit. AIX and Darwin
96 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
97 those systems will not pick up this default. This needs to be after all
98 of the include files, so that POWERPC_LINUX and POWERPC_FREEBSD are
100 #ifndef TARGET_IEEEQUAD_DEFAULT
101 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
102 #define TARGET_IEEEQUAD_DEFAULT 1
104 #define TARGET_IEEEQUAD_DEFAULT 0
108 static pad_direction rs6000_function_arg_padding (machine_mode, const_tree);
110 /* Structure used to define the rs6000 stack */
111 typedef struct rs6000_stack {
112 int reload_completed; /* stack info won't change from here on */
113 int first_gp_reg_save; /* first callee saved GP register used */
114 int first_fp_reg_save; /* first callee saved FP register used */
115 int first_altivec_reg_save; /* first callee saved AltiVec register used */
116 int lr_save_p; /* true if the link reg needs to be saved */
117 int cr_save_p; /* true if the CR reg needs to be saved */
118 unsigned int vrsave_mask; /* mask of vec registers to save */
119 int push_p; /* true if we need to allocate stack space */
120 int calls_p; /* true if the function makes any calls */
121 int world_save_p; /* true if we're saving *everything*:
122 r13-r31, cr, f14-f31, vrsave, v20-v31 */
123 enum rs6000_abi abi; /* which ABI to use */
124 int gp_save_offset; /* offset to save GP regs from initial SP */
125 int fp_save_offset; /* offset to save FP regs from initial SP */
126 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
127 int lr_save_offset; /* offset to save LR from initial SP */
128 int cr_save_offset; /* offset to save CR from initial SP */
129 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
130 int varargs_save_offset; /* offset to save the varargs registers */
131 int ehrd_offset; /* offset to EH return data */
132 int ehcr_offset; /* offset to EH CR field data */
133 int reg_size; /* register size (4 or 8) */
134 HOST_WIDE_INT vars_size; /* variable save area size */
135 int parm_size; /* outgoing parameter size */
136 int save_size; /* save area size */
137 int fixed_size; /* fixed size of stack frame */
138 int gp_size; /* size of saved GP registers */
139 int fp_size; /* size of saved FP registers */
140 int altivec_size; /* size of saved AltiVec registers */
141 int cr_size; /* size to hold CR if not in fixed area */
142 int vrsave_size; /* size to hold VRSAVE */
143 int altivec_padding_size; /* size of altivec alignment padding */
144 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
148 /* A C structure for machine-specific, per-function data.
149 This is added to the cfun structure. */
150 typedef struct GTY(()) machine_function
152 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
153 int ra_needs_full_frame;
154 /* Flags if __builtin_return_address (0) was used. */
156 /* Cache lr_save_p after expansion of builtin_eh_return. */
158 /* Whether we need to save the TOC to the reserved stack location in the
159 function prologue. */
160 bool save_toc_in_prologue;
161 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
162 varargs save area. */
163 HOST_WIDE_INT varargs_save_offset;
164 /* Alternative internal arg pointer for -fsplit-stack. */
165 rtx split_stack_arg_pointer;
166 bool split_stack_argp_used;
167 /* Flag if r2 setup is needed with ELFv2 ABI. */
168 bool r2_setup_needed;
169 /* The number of components we use for separate shrink-wrapping. */
171 /* The components already handled by separate shrink-wrapping, which should
172 not be considered by the prologue and epilogue. */
173 bool gpr_is_wrapped_separately[32];
174 bool fpr_is_wrapped_separately[32];
175 bool lr_is_wrapped_separately;
176 bool toc_is_wrapped_separately;
179 /* Support targetm.vectorize.builtin_mask_for_load. */
180 static GTY(()) tree altivec_builtin_mask_for_load;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Label number of label created for -mrelocatable, to call to so we can
186 get the address of the GOT section */
187 static int rs6000_pic_labelno;
190 /* Counter for labels which are to be placed in .fixup. */
191 int fixuplabelno = 0;
194 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
197 /* Specify the machine mode that pointers have. After generation of rtl, the
198 compiler makes no further distinction between pointers and any other objects
199 of this machine mode. */
200 scalar_int_mode rs6000_pmode;
203 /* Note whether IEEE 128-bit floating point was passed or returned, either as
204 the __float128/_Float128 explicit type, or when long double is IEEE 128-bit
205 floating point. We changed the default C++ mangling for these types and we
206 may want to generate a weak alias of the old mangling (U10__float128) to the
207 new mangling (u9__ieee128). */
208 static bool rs6000_passes_ieee128;
211 /* Generate the manged name (i.e. U10__float128) used in GCC 8.1, and not the
212 name used in current releases (i.e. u9__ieee128). */
213 static bool ieee128_mangling_gcc_8_1;
215 /* Width in bits of a pointer. */
216 unsigned rs6000_pointer_size;
218 #ifdef HAVE_AS_GNU_ATTRIBUTE
219 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
220 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
222 /* Flag whether floating point values have been passed/returned.
223 Note that this doesn't say whether fprs are used, since the
224 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
225 should be set for soft-float values passed in gprs and ieee128
226 values passed in vsx registers. */
227 static bool rs6000_passes_float;
228 static bool rs6000_passes_long_double;
229 /* Flag whether vector values have been passed/returned. */
230 static bool rs6000_passes_vector;
231 /* Flag whether small (<= 8 byte) structures have been returned. */
232 static bool rs6000_returns_struct;
235 /* Value is TRUE if register/mode pair is acceptable. */
236 static bool rs6000_hard_regno_mode_ok_p
237 [NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
239 /* Maximum number of registers needed for a given register class and mode. */
240 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
242 /* How many registers are needed for a given register and mode. */
243 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
245 /* Map register number to register class. */
246 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
248 static int dbg_cost_ctrl;
250 /* Built in types. */
251 tree rs6000_builtin_types[RS6000_BTI_MAX];
252 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
254 /* Flag to say the TOC is initialized */
255 int toc_initialized, need_toc_init;
256 char toc_label_name[10];
258 /* Cached value of rs6000_variable_issue. This is cached in
259 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
260 static short cached_can_issue_more;
262 static GTY(()) section *read_only_data_section;
263 static GTY(()) section *private_data_section;
264 static GTY(()) section *tls_data_section;
265 static GTY(()) section *tls_private_data_section;
266 static GTY(()) section *read_only_private_data_section;
267 static GTY(()) section *sdata2_section;
268 static GTY(()) section *toc_section;
270 struct builtin_description
272 const HOST_WIDE_INT mask;
273 const enum insn_code icode;
274 const char *const name;
275 const enum rs6000_builtins code;
278 /* Describe the vector unit used for modes. */
279 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
280 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
282 /* Register classes for various constraints that are based on the target
284 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
286 /* Describe the alignment of a vector. */
287 int rs6000_vector_align[NUM_MACHINE_MODES];
289 /* Map selected modes to types for builtins. */
290 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
292 /* What modes to automatically generate reciprocal divide estimate (fre) and
293 reciprocal sqrt (frsqrte) for. */
294 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
296 /* Masks to determine which reciprocal esitmate instructions to generate
298 enum rs6000_recip_mask {
299 RECIP_SF_DIV = 0x001, /* Use divide estimate */
300 RECIP_DF_DIV = 0x002,
301 RECIP_V4SF_DIV = 0x004,
302 RECIP_V2DF_DIV = 0x008,
304 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
305 RECIP_DF_RSQRT = 0x020,
306 RECIP_V4SF_RSQRT = 0x040,
307 RECIP_V2DF_RSQRT = 0x080,
309 /* Various combination of flags for -mrecip=xxx. */
311 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
312 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
313 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
315 RECIP_HIGH_PRECISION = RECIP_ALL,
317 /* On low precision machines like the power5, don't enable double precision
318 reciprocal square root estimate, since it isn't accurate enough. */
319 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
322 /* -mrecip options. */
325 const char *string; /* option name */
326 unsigned int mask; /* mask bits to set */
327 } recip_options[] = {
328 { "all", RECIP_ALL },
329 { "none", RECIP_NONE },
330 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
332 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
333 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
334 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
335 | RECIP_V2DF_RSQRT) },
336 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
337 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
340 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
346 { "power9", PPC_PLATFORM_POWER9 },
347 { "power8", PPC_PLATFORM_POWER8 },
348 { "power7", PPC_PLATFORM_POWER7 },
349 { "power6x", PPC_PLATFORM_POWER6X },
350 { "power6", PPC_PLATFORM_POWER6 },
351 { "power5+", PPC_PLATFORM_POWER5_PLUS },
352 { "power5", PPC_PLATFORM_POWER5 },
353 { "ppc970", PPC_PLATFORM_PPC970 },
354 { "power4", PPC_PLATFORM_POWER4 },
355 { "ppca2", PPC_PLATFORM_PPCA2 },
356 { "ppc476", PPC_PLATFORM_PPC476 },
357 { "ppc464", PPC_PLATFORM_PPC464 },
358 { "ppc440", PPC_PLATFORM_PPC440 },
359 { "ppc405", PPC_PLATFORM_PPC405 },
360 { "ppc-cell-be", PPC_PLATFORM_CELL_BE }
363 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
369 } cpu_supports_info[] = {
370 /* AT_HWCAP masks. */
371 { "4xxmac", PPC_FEATURE_HAS_4xxMAC, 0 },
372 { "altivec", PPC_FEATURE_HAS_ALTIVEC, 0 },
373 { "arch_2_05", PPC_FEATURE_ARCH_2_05, 0 },
374 { "arch_2_06", PPC_FEATURE_ARCH_2_06, 0 },
375 { "archpmu", PPC_FEATURE_PERFMON_COMPAT, 0 },
376 { "booke", PPC_FEATURE_BOOKE, 0 },
377 { "cellbe", PPC_FEATURE_CELL_BE, 0 },
378 { "dfp", PPC_FEATURE_HAS_DFP, 0 },
379 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE, 0 },
380 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE, 0 },
381 { "fpu", PPC_FEATURE_HAS_FPU, 0 },
382 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP, 0 },
383 { "mmu", PPC_FEATURE_HAS_MMU, 0 },
384 { "notb", PPC_FEATURE_NO_TB, 0 },
385 { "pa6t", PPC_FEATURE_PA6T, 0 },
386 { "power4", PPC_FEATURE_POWER4, 0 },
387 { "power5", PPC_FEATURE_POWER5, 0 },
388 { "power5+", PPC_FEATURE_POWER5_PLUS, 0 },
389 { "power6x", PPC_FEATURE_POWER6_EXT, 0 },
390 { "ppc32", PPC_FEATURE_32, 0 },
391 { "ppc601", PPC_FEATURE_601_INSTR, 0 },
392 { "ppc64", PPC_FEATURE_64, 0 },
393 { "ppcle", PPC_FEATURE_PPC_LE, 0 },
394 { "smt", PPC_FEATURE_SMT, 0 },
395 { "spe", PPC_FEATURE_HAS_SPE, 0 },
396 { "true_le", PPC_FEATURE_TRUE_LE, 0 },
397 { "ucache", PPC_FEATURE_UNIFIED_CACHE, 0 },
398 { "vsx", PPC_FEATURE_HAS_VSX, 0 },
400 /* AT_HWCAP2 masks. */
401 { "arch_2_07", PPC_FEATURE2_ARCH_2_07, 1 },
402 { "dscr", PPC_FEATURE2_HAS_DSCR, 1 },
403 { "ebb", PPC_FEATURE2_HAS_EBB, 1 },
404 { "htm", PPC_FEATURE2_HAS_HTM, 1 },
405 { "htm-nosc", PPC_FEATURE2_HTM_NOSC, 1 },
406 { "htm-no-suspend", PPC_FEATURE2_HTM_NO_SUSPEND, 1 },
407 { "isel", PPC_FEATURE2_HAS_ISEL, 1 },
408 { "tar", PPC_FEATURE2_HAS_TAR, 1 },
409 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO, 1 },
410 { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 },
411 { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 },
412 { "darn", PPC_FEATURE2_DARN, 1 },
413 { "scv", PPC_FEATURE2_SCV, 1 }
416 /* On PowerPC, we have a limited number of target clones that we care about
417 which means we can use an array to hold the options, rather than having more
418 elaborate data structures to identify each possible variation. Order the
419 clones from the default to the highest ISA. */
421 CLONE_DEFAULT = 0, /* default clone. */
422 CLONE_ISA_2_05, /* ISA 2.05 (power6). */
423 CLONE_ISA_2_06, /* ISA 2.06 (power7). */
424 CLONE_ISA_2_07, /* ISA 2.07 (power8). */
425 CLONE_ISA_3_00, /* ISA 3.00 (power9). */
429 /* Map compiler ISA bits into HWCAP names. */
431 HOST_WIDE_INT isa_mask; /* rs6000_isa mask */
432 const char *name; /* name to use in __builtin_cpu_supports. */
435 static const struct clone_map rs6000_clone_map[CLONE_MAX] = {
436 { 0, "" }, /* Default options. */
437 { OPTION_MASK_CMPB, "arch_2_05" }, /* ISA 2.05 (power6). */
438 { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */
439 { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */
440 { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */
444 /* Newer LIBCs explicitly export this symbol to declare that they provide
445 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
446 reference to this symbol whenever we expand a CPU builtin, so that
447 we never link against an old LIBC. */
448 const char *tcb_verification_symbol = "__parse_hwcap_and_convert_at_platform";
450 /* True if we have expanded a CPU builtin. */
453 /* Pointer to function (in rs6000-c.c) that can define or undefine target
454 macros that have changed. Languages that don't support the preprocessor
455 don't link in rs6000-c.c, so we can't call it directly. */
456 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
458 /* Simplfy register classes into simpler classifications. We assume
459 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
460 check for standard register classes (gpr/floating/altivec/vsx) and
461 floating/vector classes (float/altivec/vsx). */
463 enum rs6000_reg_type {
474 /* Map register class to register type. */
475 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
477 /* First/last register type for the 'normal' register types (i.e. general
478 purpose, floating point, altivec, and VSX registers). */
479 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
481 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
484 /* Register classes we care about in secondary reload or go if legitimate
485 address. We only need to worry about GPR, FPR, and Altivec registers here,
486 along an ANY field that is the OR of the 3 register classes. */
488 enum rs6000_reload_reg_type {
489 RELOAD_REG_GPR, /* General purpose registers. */
490 RELOAD_REG_FPR, /* Traditional floating point regs. */
491 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
492 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
496 /* For setting up register classes, loop through the 3 register classes mapping
497 into real registers, and skip the ANY class, which is just an OR of the
499 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
500 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
502 /* Map reload register type to a register in the register class. */
503 struct reload_reg_map_type {
504 const char *name; /* Register class name. */
505 int reg; /* Register in the register class. */
508 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
509 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
510 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
511 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
512 { "Any", -1 }, /* RELOAD_REG_ANY. */
515 /* Mask bits for each register class, indexed per mode. Historically the
516 compiler has been more restrictive which types can do PRE_MODIFY instead of
517 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
518 typedef unsigned char addr_mask_type;
520 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
521 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
522 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
523 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
524 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
525 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
526 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
527 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
529 /* Register type masks based on the type, of valid addressing modes. */
530 struct rs6000_reg_addr {
531 enum insn_code reload_load; /* INSN to reload for loading. */
532 enum insn_code reload_store; /* INSN to reload for storing. */
533 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
534 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
535 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
536 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
537 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
540 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
542 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
544 mode_supports_pre_incdec_p (machine_mode mode)
546 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
550 /* Helper function to say whether a mode supports PRE_MODIFY. */
552 mode_supports_pre_modify_p (machine_mode mode)
554 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
558 /* Return true if we have D-form addressing in altivec registers. */
560 mode_supports_vmx_dform (machine_mode mode)
562 return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
565 /* Return true if we have D-form addressing in VSX registers. This addressing
566 is more limited than normal d-form addressing in that the offset must be
567 aligned on a 16-byte boundary. */
569 mode_supports_dq_form (machine_mode mode)
571 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
575 /* Given that there exists at least one variable that is set (produced)
576 by OUT_INSN and read (consumed) by IN_INSN, return true iff
577 IN_INSN represents one or more memory store operations and none of
578 the variables set by OUT_INSN is used by IN_INSN as the address of a
579 store operation. If either IN_INSN or OUT_INSN does not represent
580 a "single" RTL SET expression (as loosely defined by the
581 implementation of the single_set function) or a PARALLEL with only
582 SETs, CLOBBERs, and USEs inside, this function returns false.
584 This rs6000-specific version of store_data_bypass_p checks for
585 certain conditions that result in assertion failures (and internal
586 compiler errors) in the generic store_data_bypass_p function and
587 returns false rather than calling store_data_bypass_p if one of the
588 problematic conditions is detected. */
591 rs6000_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
598 in_set = single_set (in_insn);
601 if (MEM_P (SET_DEST (in_set)))
603 out_set = single_set (out_insn);
606 out_pat = PATTERN (out_insn);
607 if (GET_CODE (out_pat) == PARALLEL)
609 for (i = 0; i < XVECLEN (out_pat, 0); i++)
611 out_exp = XVECEXP (out_pat, 0, i);
612 if ((GET_CODE (out_exp) == CLOBBER)
613 || (GET_CODE (out_exp) == USE))
615 else if (GET_CODE (out_exp) != SET)
624 in_pat = PATTERN (in_insn);
625 if (GET_CODE (in_pat) != PARALLEL)
628 for (i = 0; i < XVECLEN (in_pat, 0); i++)
630 in_exp = XVECEXP (in_pat, 0, i);
631 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE))
633 else if (GET_CODE (in_exp) != SET)
636 if (MEM_P (SET_DEST (in_exp)))
638 out_set = single_set (out_insn);
641 out_pat = PATTERN (out_insn);
642 if (GET_CODE (out_pat) != PARALLEL)
644 for (j = 0; j < XVECLEN (out_pat, 0); j++)
646 out_exp = XVECEXP (out_pat, 0, j);
647 if ((GET_CODE (out_exp) == CLOBBER)
648 || (GET_CODE (out_exp) == USE))
650 else if (GET_CODE (out_exp) != SET)
657 return store_data_bypass_p (out_insn, in_insn);
661 /* Processor costs (relative to an add) */
663 const struct processor_costs *rs6000_cost;
665 /* Instruction size costs on 32bit processors. */
667 struct processor_costs size32_cost = {
668 COSTS_N_INSNS (1), /* mulsi */
669 COSTS_N_INSNS (1), /* mulsi_const */
670 COSTS_N_INSNS (1), /* mulsi_const9 */
671 COSTS_N_INSNS (1), /* muldi */
672 COSTS_N_INSNS (1), /* divsi */
673 COSTS_N_INSNS (1), /* divdi */
674 COSTS_N_INSNS (1), /* fp */
675 COSTS_N_INSNS (1), /* dmul */
676 COSTS_N_INSNS (1), /* sdiv */
677 COSTS_N_INSNS (1), /* ddiv */
678 32, /* cache line size */
682 0, /* SF->DF convert */
685 /* Instruction size costs on 64bit processors. */
687 struct processor_costs size64_cost = {
688 COSTS_N_INSNS (1), /* mulsi */
689 COSTS_N_INSNS (1), /* mulsi_const */
690 COSTS_N_INSNS (1), /* mulsi_const9 */
691 COSTS_N_INSNS (1), /* muldi */
692 COSTS_N_INSNS (1), /* divsi */
693 COSTS_N_INSNS (1), /* divdi */
694 COSTS_N_INSNS (1), /* fp */
695 COSTS_N_INSNS (1), /* dmul */
696 COSTS_N_INSNS (1), /* sdiv */
697 COSTS_N_INSNS (1), /* ddiv */
698 128, /* cache line size */
702 0, /* SF->DF convert */
705 /* Instruction costs on RS64A processors. */
707 struct processor_costs rs64a_cost = {
708 COSTS_N_INSNS (20), /* mulsi */
709 COSTS_N_INSNS (12), /* mulsi_const */
710 COSTS_N_INSNS (8), /* mulsi_const9 */
711 COSTS_N_INSNS (34), /* muldi */
712 COSTS_N_INSNS (65), /* divsi */
713 COSTS_N_INSNS (67), /* divdi */
714 COSTS_N_INSNS (4), /* fp */
715 COSTS_N_INSNS (4), /* dmul */
716 COSTS_N_INSNS (31), /* sdiv */
717 COSTS_N_INSNS (31), /* ddiv */
718 128, /* cache line size */
722 0, /* SF->DF convert */
725 /* Instruction costs on MPCCORE processors. */
727 struct processor_costs mpccore_cost = {
728 COSTS_N_INSNS (2), /* mulsi */
729 COSTS_N_INSNS (2), /* mulsi_const */
730 COSTS_N_INSNS (2), /* mulsi_const9 */
731 COSTS_N_INSNS (2), /* muldi */
732 COSTS_N_INSNS (6), /* divsi */
733 COSTS_N_INSNS (6), /* divdi */
734 COSTS_N_INSNS (4), /* fp */
735 COSTS_N_INSNS (5), /* dmul */
736 COSTS_N_INSNS (10), /* sdiv */
737 COSTS_N_INSNS (17), /* ddiv */
738 32, /* cache line size */
742 0, /* SF->DF convert */
745 /* Instruction costs on PPC403 processors. */
747 struct processor_costs ppc403_cost = {
748 COSTS_N_INSNS (4), /* mulsi */
749 COSTS_N_INSNS (4), /* mulsi_const */
750 COSTS_N_INSNS (4), /* mulsi_const9 */
751 COSTS_N_INSNS (4), /* muldi */
752 COSTS_N_INSNS (33), /* divsi */
753 COSTS_N_INSNS (33), /* divdi */
754 COSTS_N_INSNS (11), /* fp */
755 COSTS_N_INSNS (11), /* dmul */
756 COSTS_N_INSNS (11), /* sdiv */
757 COSTS_N_INSNS (11), /* ddiv */
758 32, /* cache line size */
762 0, /* SF->DF convert */
765 /* Instruction costs on PPC405 processors. */
767 struct processor_costs ppc405_cost = {
768 COSTS_N_INSNS (5), /* mulsi */
769 COSTS_N_INSNS (4), /* mulsi_const */
770 COSTS_N_INSNS (3), /* mulsi_const9 */
771 COSTS_N_INSNS (5), /* muldi */
772 COSTS_N_INSNS (35), /* divsi */
773 COSTS_N_INSNS (35), /* divdi */
774 COSTS_N_INSNS (11), /* fp */
775 COSTS_N_INSNS (11), /* dmul */
776 COSTS_N_INSNS (11), /* sdiv */
777 COSTS_N_INSNS (11), /* ddiv */
778 32, /* cache line size */
782 0, /* SF->DF convert */
785 /* Instruction costs on PPC440 processors. */
787 struct processor_costs ppc440_cost = {
788 COSTS_N_INSNS (3), /* mulsi */
789 COSTS_N_INSNS (2), /* mulsi_const */
790 COSTS_N_INSNS (2), /* mulsi_const9 */
791 COSTS_N_INSNS (3), /* muldi */
792 COSTS_N_INSNS (34), /* divsi */
793 COSTS_N_INSNS (34), /* divdi */
794 COSTS_N_INSNS (5), /* fp */
795 COSTS_N_INSNS (5), /* dmul */
796 COSTS_N_INSNS (19), /* sdiv */
797 COSTS_N_INSNS (33), /* ddiv */
798 32, /* cache line size */
802 0, /* SF->DF convert */
805 /* Instruction costs on PPC476 processors. */
807 struct processor_costs ppc476_cost = {
808 COSTS_N_INSNS (4), /* mulsi */
809 COSTS_N_INSNS (4), /* mulsi_const */
810 COSTS_N_INSNS (4), /* mulsi_const9 */
811 COSTS_N_INSNS (4), /* muldi */
812 COSTS_N_INSNS (11), /* divsi */
813 COSTS_N_INSNS (11), /* divdi */
814 COSTS_N_INSNS (6), /* fp */
815 COSTS_N_INSNS (6), /* dmul */
816 COSTS_N_INSNS (19), /* sdiv */
817 COSTS_N_INSNS (33), /* ddiv */
818 32, /* l1 cache line size */
822 0, /* SF->DF convert */
825 /* Instruction costs on PPC601 processors. */
827 struct processor_costs ppc601_cost = {
828 COSTS_N_INSNS (5), /* mulsi */
829 COSTS_N_INSNS (5), /* mulsi_const */
830 COSTS_N_INSNS (5), /* mulsi_const9 */
831 COSTS_N_INSNS (5), /* muldi */
832 COSTS_N_INSNS (36), /* divsi */
833 COSTS_N_INSNS (36), /* divdi */
834 COSTS_N_INSNS (4), /* fp */
835 COSTS_N_INSNS (5), /* dmul */
836 COSTS_N_INSNS (17), /* sdiv */
837 COSTS_N_INSNS (31), /* ddiv */
838 32, /* cache line size */
842 0, /* SF->DF convert */
845 /* Instruction costs on PPC603 processors. */
847 struct processor_costs ppc603_cost = {
848 COSTS_N_INSNS (5), /* mulsi */
849 COSTS_N_INSNS (3), /* mulsi_const */
850 COSTS_N_INSNS (2), /* mulsi_const9 */
851 COSTS_N_INSNS (5), /* muldi */
852 COSTS_N_INSNS (37), /* divsi */
853 COSTS_N_INSNS (37), /* divdi */
854 COSTS_N_INSNS (3), /* fp */
855 COSTS_N_INSNS (4), /* dmul */
856 COSTS_N_INSNS (18), /* sdiv */
857 COSTS_N_INSNS (33), /* ddiv */
858 32, /* cache line size */
862 0, /* SF->DF convert */
865 /* Instruction costs on PPC604 processors. */
867 struct processor_costs ppc604_cost = {
868 COSTS_N_INSNS (4), /* mulsi */
869 COSTS_N_INSNS (4), /* mulsi_const */
870 COSTS_N_INSNS (4), /* mulsi_const9 */
871 COSTS_N_INSNS (4), /* muldi */
872 COSTS_N_INSNS (20), /* divsi */
873 COSTS_N_INSNS (20), /* divdi */
874 COSTS_N_INSNS (3), /* fp */
875 COSTS_N_INSNS (3), /* dmul */
876 COSTS_N_INSNS (18), /* sdiv */
877 COSTS_N_INSNS (32), /* ddiv */
878 32, /* cache line size */
882 0, /* SF->DF convert */
885 /* Instruction costs on PPC604e processors. */
887 struct processor_costs ppc604e_cost = {
888 COSTS_N_INSNS (2), /* mulsi */
889 COSTS_N_INSNS (2), /* mulsi_const */
890 COSTS_N_INSNS (2), /* mulsi_const9 */
891 COSTS_N_INSNS (2), /* muldi */
892 COSTS_N_INSNS (20), /* divsi */
893 COSTS_N_INSNS (20), /* divdi */
894 COSTS_N_INSNS (3), /* fp */
895 COSTS_N_INSNS (3), /* dmul */
896 COSTS_N_INSNS (18), /* sdiv */
897 COSTS_N_INSNS (32), /* ddiv */
898 32, /* cache line size */
902 0, /* SF->DF convert */
905 /* Instruction costs on PPC620 processors. */
907 struct processor_costs ppc620_cost = {
908 COSTS_N_INSNS (5), /* mulsi */
909 COSTS_N_INSNS (4), /* mulsi_const */
910 COSTS_N_INSNS (3), /* mulsi_const9 */
911 COSTS_N_INSNS (7), /* muldi */
912 COSTS_N_INSNS (21), /* divsi */
913 COSTS_N_INSNS (37), /* divdi */
914 COSTS_N_INSNS (3), /* fp */
915 COSTS_N_INSNS (3), /* dmul */
916 COSTS_N_INSNS (18), /* sdiv */
917 COSTS_N_INSNS (32), /* ddiv */
918 128, /* cache line size */
922 0, /* SF->DF convert */
925 /* Instruction costs on PPC630 processors. */
927 struct processor_costs ppc630_cost = {
928 COSTS_N_INSNS (5), /* mulsi */
929 COSTS_N_INSNS (4), /* mulsi_const */
930 COSTS_N_INSNS (3), /* mulsi_const9 */
931 COSTS_N_INSNS (7), /* muldi */
932 COSTS_N_INSNS (21), /* divsi */
933 COSTS_N_INSNS (37), /* divdi */
934 COSTS_N_INSNS (3), /* fp */
935 COSTS_N_INSNS (3), /* dmul */
936 COSTS_N_INSNS (17), /* sdiv */
937 COSTS_N_INSNS (21), /* ddiv */
938 128, /* cache line size */
942 0, /* SF->DF convert */
945 /* Instruction costs on Cell processor. */
946 /* COSTS_N_INSNS (1) ~ one add. */
948 struct processor_costs ppccell_cost = {
949 COSTS_N_INSNS (9/2)+2, /* mulsi */
950 COSTS_N_INSNS (6/2), /* mulsi_const */
951 COSTS_N_INSNS (6/2), /* mulsi_const9 */
952 COSTS_N_INSNS (15/2)+2, /* muldi */
953 COSTS_N_INSNS (38/2), /* divsi */
954 COSTS_N_INSNS (70/2), /* divdi */
955 COSTS_N_INSNS (10/2), /* fp */
956 COSTS_N_INSNS (10/2), /* dmul */
957 COSTS_N_INSNS (74/2), /* sdiv */
958 COSTS_N_INSNS (74/2), /* ddiv */
959 128, /* cache line size */
963 0, /* SF->DF convert */
966 /* Instruction costs on PPC750 and PPC7400 processors. */
968 struct processor_costs ppc750_cost = {
969 COSTS_N_INSNS (5), /* mulsi */
970 COSTS_N_INSNS (3), /* mulsi_const */
971 COSTS_N_INSNS (2), /* mulsi_const9 */
972 COSTS_N_INSNS (5), /* muldi */
973 COSTS_N_INSNS (17), /* divsi */
974 COSTS_N_INSNS (17), /* divdi */
975 COSTS_N_INSNS (3), /* fp */
976 COSTS_N_INSNS (3), /* dmul */
977 COSTS_N_INSNS (17), /* sdiv */
978 COSTS_N_INSNS (31), /* ddiv */
979 32, /* cache line size */
983 0, /* SF->DF convert */
986 /* Instruction costs on PPC7450 processors. */
988 struct processor_costs ppc7450_cost = {
989 COSTS_N_INSNS (4), /* mulsi */
990 COSTS_N_INSNS (3), /* mulsi_const */
991 COSTS_N_INSNS (3), /* mulsi_const9 */
992 COSTS_N_INSNS (4), /* muldi */
993 COSTS_N_INSNS (23), /* divsi */
994 COSTS_N_INSNS (23), /* divdi */
995 COSTS_N_INSNS (5), /* fp */
996 COSTS_N_INSNS (5), /* dmul */
997 COSTS_N_INSNS (21), /* sdiv */
998 COSTS_N_INSNS (35), /* ddiv */
999 32, /* cache line size */
1001 1024, /* l2 cache */
1003 0, /* SF->DF convert */
1006 /* Instruction costs on PPC8540 processors. */
1008 struct processor_costs ppc8540_cost = {
1009 COSTS_N_INSNS (4), /* mulsi */
1010 COSTS_N_INSNS (4), /* mulsi_const */
1011 COSTS_N_INSNS (4), /* mulsi_const9 */
1012 COSTS_N_INSNS (4), /* muldi */
1013 COSTS_N_INSNS (19), /* divsi */
1014 COSTS_N_INSNS (19), /* divdi */
1015 COSTS_N_INSNS (4), /* fp */
1016 COSTS_N_INSNS (4), /* dmul */
1017 COSTS_N_INSNS (29), /* sdiv */
1018 COSTS_N_INSNS (29), /* ddiv */
1019 32, /* cache line size */
1022 1, /* prefetch streams /*/
1023 0, /* SF->DF convert */
1026 /* Instruction costs on E300C2 and E300C3 cores. */
1028 struct processor_costs ppce300c2c3_cost = {
1029 COSTS_N_INSNS (4), /* mulsi */
1030 COSTS_N_INSNS (4), /* mulsi_const */
1031 COSTS_N_INSNS (4), /* mulsi_const9 */
1032 COSTS_N_INSNS (4), /* muldi */
1033 COSTS_N_INSNS (19), /* divsi */
1034 COSTS_N_INSNS (19), /* divdi */
1035 COSTS_N_INSNS (3), /* fp */
1036 COSTS_N_INSNS (4), /* dmul */
1037 COSTS_N_INSNS (18), /* sdiv */
1038 COSTS_N_INSNS (33), /* ddiv */
1042 1, /* prefetch streams /*/
1043 0, /* SF->DF convert */
1046 /* Instruction costs on PPCE500MC processors. */
1048 struct processor_costs ppce500mc_cost = {
1049 COSTS_N_INSNS (4), /* mulsi */
1050 COSTS_N_INSNS (4), /* mulsi_const */
1051 COSTS_N_INSNS (4), /* mulsi_const9 */
1052 COSTS_N_INSNS (4), /* muldi */
1053 COSTS_N_INSNS (14), /* divsi */
1054 COSTS_N_INSNS (14), /* divdi */
1055 COSTS_N_INSNS (8), /* fp */
1056 COSTS_N_INSNS (10), /* dmul */
1057 COSTS_N_INSNS (36), /* sdiv */
1058 COSTS_N_INSNS (66), /* ddiv */
1059 64, /* cache line size */
1062 1, /* prefetch streams /*/
1063 0, /* SF->DF convert */
1066 /* Instruction costs on PPCE500MC64 processors. */
1068 struct processor_costs ppce500mc64_cost = {
1069 COSTS_N_INSNS (4), /* mulsi */
1070 COSTS_N_INSNS (4), /* mulsi_const */
1071 COSTS_N_INSNS (4), /* mulsi_const9 */
1072 COSTS_N_INSNS (4), /* muldi */
1073 COSTS_N_INSNS (14), /* divsi */
1074 COSTS_N_INSNS (14), /* divdi */
1075 COSTS_N_INSNS (4), /* fp */
1076 COSTS_N_INSNS (10), /* dmul */
1077 COSTS_N_INSNS (36), /* sdiv */
1078 COSTS_N_INSNS (66), /* ddiv */
1079 64, /* cache line size */
1082 1, /* prefetch streams /*/
1083 0, /* SF->DF convert */
1086 /* Instruction costs on PPCE5500 processors. */
1088 struct processor_costs ppce5500_cost = {
1089 COSTS_N_INSNS (5), /* mulsi */
1090 COSTS_N_INSNS (5), /* mulsi_const */
1091 COSTS_N_INSNS (4), /* mulsi_const9 */
1092 COSTS_N_INSNS (5), /* muldi */
1093 COSTS_N_INSNS (14), /* divsi */
1094 COSTS_N_INSNS (14), /* divdi */
1095 COSTS_N_INSNS (7), /* fp */
1096 COSTS_N_INSNS (10), /* dmul */
1097 COSTS_N_INSNS (36), /* sdiv */
1098 COSTS_N_INSNS (66), /* ddiv */
1099 64, /* cache line size */
1102 1, /* prefetch streams /*/
1103 0, /* SF->DF convert */
1106 /* Instruction costs on PPCE6500 processors. */
1108 struct processor_costs ppce6500_cost = {
1109 COSTS_N_INSNS (5), /* mulsi */
1110 COSTS_N_INSNS (5), /* mulsi_const */
1111 COSTS_N_INSNS (4), /* mulsi_const9 */
1112 COSTS_N_INSNS (5), /* muldi */
1113 COSTS_N_INSNS (14), /* divsi */
1114 COSTS_N_INSNS (14), /* divdi */
1115 COSTS_N_INSNS (7), /* fp */
1116 COSTS_N_INSNS (10), /* dmul */
1117 COSTS_N_INSNS (36), /* sdiv */
1118 COSTS_N_INSNS (66), /* ddiv */
1119 64, /* cache line size */
1122 1, /* prefetch streams /*/
1123 0, /* SF->DF convert */
1126 /* Instruction costs on AppliedMicro Titan processors. */
1128 struct processor_costs titan_cost = {
1129 COSTS_N_INSNS (5), /* mulsi */
1130 COSTS_N_INSNS (5), /* mulsi_const */
1131 COSTS_N_INSNS (5), /* mulsi_const9 */
1132 COSTS_N_INSNS (5), /* muldi */
1133 COSTS_N_INSNS (18), /* divsi */
1134 COSTS_N_INSNS (18), /* divdi */
1135 COSTS_N_INSNS (10), /* fp */
1136 COSTS_N_INSNS (10), /* dmul */
1137 COSTS_N_INSNS (46), /* sdiv */
1138 COSTS_N_INSNS (72), /* ddiv */
1139 32, /* cache line size */
1142 1, /* prefetch streams /*/
1143 0, /* SF->DF convert */
1146 /* Instruction costs on POWER4 and POWER5 processors. */
1148 struct processor_costs power4_cost = {
1149 COSTS_N_INSNS (3), /* mulsi */
1150 COSTS_N_INSNS (2), /* mulsi_const */
1151 COSTS_N_INSNS (2), /* mulsi_const9 */
1152 COSTS_N_INSNS (4), /* muldi */
1153 COSTS_N_INSNS (18), /* divsi */
1154 COSTS_N_INSNS (34), /* divdi */
1155 COSTS_N_INSNS (3), /* fp */
1156 COSTS_N_INSNS (3), /* dmul */
1157 COSTS_N_INSNS (17), /* sdiv */
1158 COSTS_N_INSNS (17), /* ddiv */
1159 128, /* cache line size */
1161 1024, /* l2 cache */
1162 8, /* prefetch streams /*/
1163 0, /* SF->DF convert */
1166 /* Instruction costs on POWER6 processors. */
1168 struct processor_costs power6_cost = {
1169 COSTS_N_INSNS (8), /* mulsi */
1170 COSTS_N_INSNS (8), /* mulsi_const */
1171 COSTS_N_INSNS (8), /* mulsi_const9 */
1172 COSTS_N_INSNS (8), /* muldi */
1173 COSTS_N_INSNS (22), /* divsi */
1174 COSTS_N_INSNS (28), /* divdi */
1175 COSTS_N_INSNS (3), /* fp */
1176 COSTS_N_INSNS (3), /* dmul */
1177 COSTS_N_INSNS (13), /* sdiv */
1178 COSTS_N_INSNS (16), /* ddiv */
1179 128, /* cache line size */
1181 2048, /* l2 cache */
1182 16, /* prefetch streams */
1183 0, /* SF->DF convert */
1186 /* Instruction costs on POWER7 processors. */
1188 struct processor_costs power7_cost = {
1189 COSTS_N_INSNS (2), /* mulsi */
1190 COSTS_N_INSNS (2), /* mulsi_const */
1191 COSTS_N_INSNS (2), /* mulsi_const9 */
1192 COSTS_N_INSNS (2), /* muldi */
1193 COSTS_N_INSNS (18), /* divsi */
1194 COSTS_N_INSNS (34), /* divdi */
1195 COSTS_N_INSNS (3), /* fp */
1196 COSTS_N_INSNS (3), /* dmul */
1197 COSTS_N_INSNS (13), /* sdiv */
1198 COSTS_N_INSNS (16), /* ddiv */
1199 128, /* cache line size */
1202 12, /* prefetch streams */
1203 COSTS_N_INSNS (3), /* SF->DF convert */
1206 /* Instruction costs on POWER8 processors. */
1208 struct processor_costs power8_cost = {
1209 COSTS_N_INSNS (3), /* mulsi */
1210 COSTS_N_INSNS (3), /* mulsi_const */
1211 COSTS_N_INSNS (3), /* mulsi_const9 */
1212 COSTS_N_INSNS (3), /* muldi */
1213 COSTS_N_INSNS (19), /* divsi */
1214 COSTS_N_INSNS (35), /* divdi */
1215 COSTS_N_INSNS (3), /* fp */
1216 COSTS_N_INSNS (3), /* dmul */
1217 COSTS_N_INSNS (14), /* sdiv */
1218 COSTS_N_INSNS (17), /* ddiv */
1219 128, /* cache line size */
1222 12, /* prefetch streams */
1223 COSTS_N_INSNS (3), /* SF->DF convert */
1226 /* Instruction costs on POWER9 processors. */
1228 struct processor_costs power9_cost = {
1229 COSTS_N_INSNS (3), /* mulsi */
1230 COSTS_N_INSNS (3), /* mulsi_const */
1231 COSTS_N_INSNS (3), /* mulsi_const9 */
1232 COSTS_N_INSNS (3), /* muldi */
1233 COSTS_N_INSNS (8), /* divsi */
1234 COSTS_N_INSNS (12), /* divdi */
1235 COSTS_N_INSNS (3), /* fp */
1236 COSTS_N_INSNS (3), /* dmul */
1237 COSTS_N_INSNS (13), /* sdiv */
1238 COSTS_N_INSNS (18), /* ddiv */
1239 128, /* cache line size */
1242 8, /* prefetch streams */
1243 COSTS_N_INSNS (3), /* SF->DF convert */
1246 /* Instruction costs on POWER A2 processors. */
1248 struct processor_costs ppca2_cost = {
1249 COSTS_N_INSNS (16), /* mulsi */
1250 COSTS_N_INSNS (16), /* mulsi_const */
1251 COSTS_N_INSNS (16), /* mulsi_const9 */
1252 COSTS_N_INSNS (16), /* muldi */
1253 COSTS_N_INSNS (22), /* divsi */
1254 COSTS_N_INSNS (28), /* divdi */
1255 COSTS_N_INSNS (3), /* fp */
1256 COSTS_N_INSNS (3), /* dmul */
1257 COSTS_N_INSNS (59), /* sdiv */
1258 COSTS_N_INSNS (72), /* ddiv */
1261 2048, /* l2 cache */
1262 16, /* prefetch streams */
1263 0, /* SF->DF convert */
1267 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1268 #undef RS6000_BUILTIN_0
1269 #undef RS6000_BUILTIN_1
1270 #undef RS6000_BUILTIN_2
1271 #undef RS6000_BUILTIN_3
1272 #undef RS6000_BUILTIN_A
1273 #undef RS6000_BUILTIN_D
1274 #undef RS6000_BUILTIN_H
1275 #undef RS6000_BUILTIN_P
1276 #undef RS6000_BUILTIN_X
1278 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1279 { NAME, ICODE, MASK, ATTR },
1281 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1282 { NAME, ICODE, MASK, ATTR },
1284 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1285 { NAME, ICODE, MASK, ATTR },
1287 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1288 { NAME, ICODE, MASK, ATTR },
1290 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1291 { NAME, ICODE, MASK, ATTR },
1293 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1294 { NAME, ICODE, MASK, ATTR },
1296 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1297 { NAME, ICODE, MASK, ATTR },
1299 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1300 { NAME, ICODE, MASK, ATTR },
1302 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1303 { NAME, ICODE, MASK, ATTR },
1305 struct rs6000_builtin_info_type {
1307 const enum insn_code icode;
1308 const HOST_WIDE_INT mask;
1309 const unsigned attr;
1312 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1314 #include "rs6000-builtin.def"
1317 #undef RS6000_BUILTIN_0
1318 #undef RS6000_BUILTIN_1
1319 #undef RS6000_BUILTIN_2
1320 #undef RS6000_BUILTIN_3
1321 #undef RS6000_BUILTIN_A
1322 #undef RS6000_BUILTIN_D
1323 #undef RS6000_BUILTIN_H
1324 #undef RS6000_BUILTIN_P
1325 #undef RS6000_BUILTIN_X
1327 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1328 static tree (*rs6000_veclib_handler) (combined_fn, tree, tree);
1331 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1332 static struct machine_function * rs6000_init_machine_status (void);
1333 static int rs6000_ra_ever_killed (void);
1334 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1335 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1336 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1337 static tree rs6000_builtin_vectorized_libmass (combined_fn, tree, tree);
1338 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1339 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1340 static bool rs6000_debug_rtx_costs (rtx, machine_mode, int, int, int *, bool);
1341 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1343 static int rs6000_debug_adjust_cost (rtx_insn *, int, rtx_insn *, int,
1345 static bool is_microcoded_insn (rtx_insn *);
1346 static bool is_nonpipeline_insn (rtx_insn *);
1347 static bool is_cracked_insn (rtx_insn *);
1348 static bool is_load_insn (rtx, rtx *);
1349 static bool is_store_insn (rtx, rtx *);
1350 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1351 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1352 static bool insn_must_be_first_in_group (rtx_insn *);
1353 static bool insn_must_be_last_in_group (rtx_insn *);
1354 static void altivec_init_builtins (void);
1355 static tree builtin_function_type (machine_mode, machine_mode,
1356 machine_mode, machine_mode,
1357 enum rs6000_builtins, const char *name);
1358 static void rs6000_common_init_builtins (void);
1359 static void htm_init_builtins (void);
1360 static rs6000_stack_t *rs6000_stack_info (void);
1361 static void is_altivec_return_reg (rtx, void *);
1362 int easy_vector_constant (rtx, machine_mode);
1363 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1364 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1365 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1368 static void macho_branch_islands (void);
1369 static tree get_prev_label (tree);
1371 static bool rs6000_mode_dependent_address (const_rtx);
1372 static bool rs6000_debug_mode_dependent_address (const_rtx);
1373 static bool rs6000_offsettable_memref_p (rtx, machine_mode, bool);
1374 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1376 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1379 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1380 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1382 static bool rs6000_debug_secondary_memory_needed (machine_mode,
1385 static bool rs6000_debug_can_change_mode_class (machine_mode,
1388 static bool rs6000_save_toc_in_prologue_p (void);
1389 static rtx rs6000_internal_arg_pointer (void);
1391 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1392 = rs6000_mode_dependent_address;
1394 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1396 = rs6000_secondary_reload_class;
1398 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1399 = rs6000_preferred_reload_class;
1401 const int INSN_NOT_AVAILABLE = -1;
1403 static void rs6000_print_isa_options (FILE *, int, const char *,
1405 static void rs6000_print_builtin_options (FILE *, int, const char *,
1407 static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
1409 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1410 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1411 enum rs6000_reg_type,
1413 secondary_reload_info *,
1415 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1416 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused));
1417 static tree rs6000_fold_builtin (tree, int, tree *, bool);
1419 /* Hash table stuff for keeping track of TOC entries. */
1421 struct GTY((for_user)) toc_hash_struct
1423 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1424 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1426 machine_mode key_mode;
1430 struct toc_hasher : ggc_ptr_hash<toc_hash_struct>
1432 static hashval_t hash (toc_hash_struct *);
1433 static bool equal (toc_hash_struct *, toc_hash_struct *);
1436 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1438 /* Hash table to keep track of the argument types for builtin functions. */
1440 struct GTY((for_user)) builtin_hash_struct
1443 machine_mode mode[4]; /* return value + 3 arguments. */
1444 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1447 struct builtin_hasher : ggc_ptr_hash<builtin_hash_struct>
1449 static hashval_t hash (builtin_hash_struct *);
1450 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1453 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1456 /* Default register names. */
1457 char rs6000_reg_names[][8] =
1460 "0", "1", "2", "3", "4", "5", "6", "7",
1461 "8", "9", "10", "11", "12", "13", "14", "15",
1462 "16", "17", "18", "19", "20", "21", "22", "23",
1463 "24", "25", "26", "27", "28", "29", "30", "31",
1465 "0", "1", "2", "3", "4", "5", "6", "7",
1466 "8", "9", "10", "11", "12", "13", "14", "15",
1467 "16", "17", "18", "19", "20", "21", "22", "23",
1468 "24", "25", "26", "27", "28", "29", "30", "31",
1470 "0", "1", "2", "3", "4", "5", "6", "7",
1471 "8", "9", "10", "11", "12", "13", "14", "15",
1472 "16", "17", "18", "19", "20", "21", "22", "23",
1473 "24", "25", "26", "27", "28", "29", "30", "31",
1475 "lr", "ctr", "ca", "ap",
1477 "0", "1", "2", "3", "4", "5", "6", "7",
1478 /* vrsave vscr sfp */
1479 "vrsave", "vscr", "sfp",
1482 #ifdef TARGET_REGNAMES
1483 static const char alt_reg_names[][8] =
1486 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1487 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1488 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1489 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1491 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1492 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1493 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1494 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1496 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1497 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1498 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1499 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1501 "lr", "ctr", "ca", "ap",
1503 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1504 /* vrsave vscr sfp */
1505 "vrsave", "vscr", "sfp",
1509 /* Table of valid machine attributes. */
1511 static const struct attribute_spec rs6000_attribute_table[] =
1513 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
1514 affects_type_identity, handler, exclude } */
1515 { "altivec", 1, 1, false, true, false, false,
1516 rs6000_handle_altivec_attribute, NULL },
1517 { "longcall", 0, 0, false, true, true, false,
1518 rs6000_handle_longcall_attribute, NULL },
1519 { "shortcall", 0, 0, false, true, true, false,
1520 rs6000_handle_longcall_attribute, NULL },
1521 { "ms_struct", 0, 0, false, false, false, false,
1522 rs6000_handle_struct_attribute, NULL },
1523 { "gcc_struct", 0, 0, false, false, false, false,
1524 rs6000_handle_struct_attribute, NULL },
1525 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1526 SUBTARGET_ATTRIBUTE_TABLE,
1528 { NULL, 0, 0, false, false, false, false, NULL, NULL }
1531 #ifndef TARGET_PROFILE_KERNEL
1532 #define TARGET_PROFILE_KERNEL 0
1535 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1536 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1538 /* Initialize the GCC target structure. */
1539 #undef TARGET_ATTRIBUTE_TABLE
1540 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1541 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1542 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1543 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1544 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1546 #undef TARGET_ASM_ALIGNED_DI_OP
1547 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1549 /* Default unaligned ops are only provided for ELF. Find the ops needed
1550 for non-ELF systems. */
1551 #ifndef OBJECT_FORMAT_ELF
1553 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1555 #undef TARGET_ASM_UNALIGNED_HI_OP
1556 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1557 #undef TARGET_ASM_UNALIGNED_SI_OP
1558 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1559 #undef TARGET_ASM_UNALIGNED_DI_OP
1560 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1563 #undef TARGET_ASM_UNALIGNED_HI_OP
1564 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1565 #undef TARGET_ASM_UNALIGNED_SI_OP
1566 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1567 #undef TARGET_ASM_UNALIGNED_DI_OP
1568 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1569 #undef TARGET_ASM_ALIGNED_DI_OP
1570 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1574 /* This hook deals with fixups for relocatable code and DI-mode objects
1576 #undef TARGET_ASM_INTEGER
1577 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1579 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1580 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1581 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1584 #undef TARGET_SET_UP_BY_PROLOGUE
1585 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1587 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1588 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1589 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1590 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1591 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1592 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1593 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1594 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1595 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1596 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1597 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1598 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1600 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1601 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1603 #undef TARGET_INTERNAL_ARG_POINTER
1604 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1606 #undef TARGET_HAVE_TLS
1607 #define TARGET_HAVE_TLS HAVE_AS_TLS
1609 #undef TARGET_CANNOT_FORCE_CONST_MEM
1610 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1612 #undef TARGET_DELEGITIMIZE_ADDRESS
1613 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1615 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1616 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1618 #undef TARGET_LEGITIMATE_COMBINED_INSN
1619 #define TARGET_LEGITIMATE_COMBINED_INSN rs6000_legitimate_combined_insn
1621 #undef TARGET_ASM_FUNCTION_PROLOGUE
1622 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1623 #undef TARGET_ASM_FUNCTION_EPILOGUE
1624 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1626 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1627 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1629 #undef TARGET_LEGITIMIZE_ADDRESS
1630 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1632 #undef TARGET_SCHED_VARIABLE_ISSUE
1633 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1635 #undef TARGET_SCHED_ISSUE_RATE
1636 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1637 #undef TARGET_SCHED_ADJUST_COST
1638 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1639 #undef TARGET_SCHED_ADJUST_PRIORITY
1640 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1641 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1642 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1643 #undef TARGET_SCHED_INIT
1644 #define TARGET_SCHED_INIT rs6000_sched_init
1645 #undef TARGET_SCHED_FINISH
1646 #define TARGET_SCHED_FINISH rs6000_sched_finish
1647 #undef TARGET_SCHED_REORDER
1648 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1649 #undef TARGET_SCHED_REORDER2
1650 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1652 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1653 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1655 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1656 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1658 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1659 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1660 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1661 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1662 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1663 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1664 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1665 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1667 #undef TARGET_SCHED_CAN_SPECULATE_INSN
1668 #define TARGET_SCHED_CAN_SPECULATE_INSN rs6000_sched_can_speculate_insn
1670 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1671 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1672 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1673 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1674 rs6000_builtin_support_vector_misalignment
1675 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1676 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1677 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1678 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1679 rs6000_builtin_vectorization_cost
1680 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1681 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1682 rs6000_preferred_simd_mode
1683 #undef TARGET_VECTORIZE_INIT_COST
1684 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1685 #undef TARGET_VECTORIZE_ADD_STMT_COST
1686 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1687 #undef TARGET_VECTORIZE_FINISH_COST
1688 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1689 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1690 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1692 #undef TARGET_INIT_BUILTINS
1693 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1694 #undef TARGET_BUILTIN_DECL
1695 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1697 #undef TARGET_FOLD_BUILTIN
1698 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1699 #undef TARGET_GIMPLE_FOLD_BUILTIN
1700 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1702 #undef TARGET_EXPAND_BUILTIN
1703 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1705 #undef TARGET_MANGLE_TYPE
1706 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1708 #undef TARGET_INIT_LIBFUNCS
1709 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1712 #undef TARGET_BINDS_LOCAL_P
1713 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1716 #undef TARGET_MS_BITFIELD_LAYOUT_P
1717 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1719 #undef TARGET_ASM_OUTPUT_MI_THUNK
1720 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1722 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1723 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1725 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1726 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1728 #undef TARGET_REGISTER_MOVE_COST
1729 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1730 #undef TARGET_MEMORY_MOVE_COST
1731 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1732 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
1733 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
1734 rs6000_ira_change_pseudo_allocno_class
1735 #undef TARGET_CANNOT_COPY_INSN_P
1736 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1737 #undef TARGET_RTX_COSTS
1738 #define TARGET_RTX_COSTS rs6000_rtx_costs
1739 #undef TARGET_ADDRESS_COST
1740 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1741 #undef TARGET_INSN_COST
1742 #define TARGET_INSN_COST rs6000_insn_cost
1744 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1745 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1747 #undef TARGET_PROMOTE_FUNCTION_MODE
1748 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1750 #undef TARGET_RETURN_IN_MEMORY
1751 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1753 #undef TARGET_RETURN_IN_MSB
1754 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1756 #undef TARGET_SETUP_INCOMING_VARARGS
1757 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1759 /* Always strict argument naming on rs6000. */
1760 #undef TARGET_STRICT_ARGUMENT_NAMING
1761 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1762 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1763 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1764 #undef TARGET_SPLIT_COMPLEX_ARG
1765 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1766 #undef TARGET_MUST_PASS_IN_STACK
1767 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1768 #undef TARGET_PASS_BY_REFERENCE
1769 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1770 #undef TARGET_ARG_PARTIAL_BYTES
1771 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1772 #undef TARGET_FUNCTION_ARG_ADVANCE
1773 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1774 #undef TARGET_FUNCTION_ARG
1775 #define TARGET_FUNCTION_ARG rs6000_function_arg
1776 #undef TARGET_FUNCTION_ARG_PADDING
1777 #define TARGET_FUNCTION_ARG_PADDING rs6000_function_arg_padding
1778 #undef TARGET_FUNCTION_ARG_BOUNDARY
1779 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1781 #undef TARGET_BUILD_BUILTIN_VA_LIST
1782 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1784 #undef TARGET_EXPAND_BUILTIN_VA_START
1785 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1787 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1788 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1790 #undef TARGET_EH_RETURN_FILTER_MODE
1791 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1793 #undef TARGET_TRANSLATE_MODE_ATTRIBUTE
1794 #define TARGET_TRANSLATE_MODE_ATTRIBUTE rs6000_translate_mode_attribute
1796 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1797 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1799 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1800 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1802 #undef TARGET_FLOATN_MODE
1803 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1805 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1806 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1808 #undef TARGET_MD_ASM_ADJUST
1809 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1811 #undef TARGET_OPTION_OVERRIDE
1812 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1814 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1815 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1816 rs6000_builtin_vectorized_function
1818 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1819 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1820 rs6000_builtin_md_vectorized_function
1822 #undef TARGET_STACK_PROTECT_GUARD
1823 #define TARGET_STACK_PROTECT_GUARD rs6000_init_stack_protect_guard
1826 #undef TARGET_STACK_PROTECT_FAIL
1827 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1831 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1832 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1835 /* Use a 32-bit anchor range. This leads to sequences like:
1837 addis tmp,anchor,high
1840 where tmp itself acts as an anchor, and can be shared between
1841 accesses to the same 64k page. */
1842 #undef TARGET_MIN_ANCHOR_OFFSET
1843 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1844 #undef TARGET_MAX_ANCHOR_OFFSET
1845 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1846 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1847 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1848 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1849 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1851 #undef TARGET_BUILTIN_RECIPROCAL
1852 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1854 #undef TARGET_SECONDARY_RELOAD
1855 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1856 #undef TARGET_SECONDARY_MEMORY_NEEDED
1857 #define TARGET_SECONDARY_MEMORY_NEEDED rs6000_secondary_memory_needed
1858 #undef TARGET_SECONDARY_MEMORY_NEEDED_MODE
1859 #define TARGET_SECONDARY_MEMORY_NEEDED_MODE rs6000_secondary_memory_needed_mode
1861 #undef TARGET_LEGITIMATE_ADDRESS_P
1862 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1864 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1865 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1867 #undef TARGET_COMPUTE_PRESSURE_CLASSES
1868 #define TARGET_COMPUTE_PRESSURE_CLASSES rs6000_compute_pressure_classes
1870 #undef TARGET_CAN_ELIMINATE
1871 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1873 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1874 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1876 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1877 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1879 #undef TARGET_TRAMPOLINE_INIT
1880 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1882 #undef TARGET_FUNCTION_VALUE
1883 #define TARGET_FUNCTION_VALUE rs6000_function_value
1885 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1886 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1888 #undef TARGET_OPTION_SAVE
1889 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1891 #undef TARGET_OPTION_RESTORE
1892 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1894 #undef TARGET_OPTION_PRINT
1895 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1897 #undef TARGET_CAN_INLINE_P
1898 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1900 #undef TARGET_SET_CURRENT_FUNCTION
1901 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1903 #undef TARGET_LEGITIMATE_CONSTANT_P
1904 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1906 #undef TARGET_VECTORIZE_VEC_PERM_CONST
1907 #define TARGET_VECTORIZE_VEC_PERM_CONST rs6000_vectorize_vec_perm_const
1909 #undef TARGET_CAN_USE_DOLOOP_P
1910 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1912 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1913 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1915 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1916 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1917 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1918 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1919 #undef TARGET_UNWIND_WORD_MODE
1920 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1922 #undef TARGET_OFFLOAD_OPTIONS
1923 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1925 #undef TARGET_C_MODE_FOR_SUFFIX
1926 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1928 #undef TARGET_INVALID_BINARY_OP
1929 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1931 #undef TARGET_OPTAB_SUPPORTED_P
1932 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1934 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1935 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1937 #undef TARGET_COMPARE_VERSION_PRIORITY
1938 #define TARGET_COMPARE_VERSION_PRIORITY rs6000_compare_version_priority
1940 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
1941 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
1942 rs6000_generate_version_dispatcher_body
1944 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
1945 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
1946 rs6000_get_function_versions_dispatcher
1948 #undef TARGET_OPTION_FUNCTION_VERSIONS
1949 #define TARGET_OPTION_FUNCTION_VERSIONS common_function_versions
1951 #undef TARGET_HARD_REGNO_NREGS
1952 #define TARGET_HARD_REGNO_NREGS rs6000_hard_regno_nregs_hook
1953 #undef TARGET_HARD_REGNO_MODE_OK
1954 #define TARGET_HARD_REGNO_MODE_OK rs6000_hard_regno_mode_ok
1956 #undef TARGET_MODES_TIEABLE_P
1957 #define TARGET_MODES_TIEABLE_P rs6000_modes_tieable_p
1959 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
1960 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
1961 rs6000_hard_regno_call_part_clobbered
1963 #undef TARGET_SLOW_UNALIGNED_ACCESS
1964 #define TARGET_SLOW_UNALIGNED_ACCESS rs6000_slow_unaligned_access
1966 #undef TARGET_CAN_CHANGE_MODE_CLASS
1967 #define TARGET_CAN_CHANGE_MODE_CLASS rs6000_can_change_mode_class
1969 #undef TARGET_CONSTANT_ALIGNMENT
1970 #define TARGET_CONSTANT_ALIGNMENT rs6000_constant_alignment
1972 #undef TARGET_STARTING_FRAME_OFFSET
1973 #define TARGET_STARTING_FRAME_OFFSET rs6000_starting_frame_offset
1975 #if TARGET_ELF && RS6000_WEAK
1976 #undef TARGET_ASM_GLOBALIZE_DECL_NAME
1977 #define TARGET_ASM_GLOBALIZE_DECL_NAME rs6000_globalize_decl_name
1980 #undef TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P
1981 #define TARGET_SETJMP_PRESERVES_NONVOLATILE_REGS_P hook_bool_void_true
1983 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
1984 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME rs6000_mangle_decl_assembler_name
1987 /* Processor table. */
1990 const char *const name; /* Canonical processor name. */
1991 const enum processor_type processor; /* Processor type enum value. */
1992 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1995 static struct rs6000_ptt const processor_target_table[] =
1997 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1998 #include "rs6000-cpus.def"
2002 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
2006 rs6000_cpu_name_lookup (const char *name)
2012 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
2013 if (! strcmp (name, processor_target_table[i].name))
2021 /* Return number of consecutive hard regs needed starting at reg REGNO
2022 to hold something of mode MODE.
2023 This is ordinarily the length in words of a value of mode MODE
2024 but can be less for certain modes in special long registers.
2026 POWER and PowerPC GPRs hold 32 bits worth;
2027 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
2030 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
2032 unsigned HOST_WIDE_INT reg_size;
2034 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
2035 128-bit floating point that can go in vector registers, which has VSX
2036 memory addressing. */
2037 if (FP_REGNO_P (regno))
2038 reg_size = (VECTOR_MEM_VSX_P (mode) || FLOAT128_VECTOR_P (mode)
2039 ? UNITS_PER_VSX_WORD
2040 : UNITS_PER_FP_WORD);
2042 else if (ALTIVEC_REGNO_P (regno))
2043 reg_size = UNITS_PER_ALTIVEC_WORD;
2046 reg_size = UNITS_PER_WORD;
2048 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
2051 /* Value is 1 if hard register REGNO can hold a value of machine-mode
2054 rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
2056 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
2058 if (COMPLEX_MODE_P (mode))
2059 mode = GET_MODE_INNER (mode);
2061 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
2062 register combinations, and use PTImode where we need to deal with quad
2063 word memory operations. Don't allow quad words in the argument or frame
2064 pointer registers, just registers 0..31. */
2065 if (mode == PTImode)
2066 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2067 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
2068 && ((regno & 1) == 0));
2070 /* VSX registers that overlap the FPR registers are larger than for non-VSX
2071 implementations. Don't allow an item to be split between a FP register
2072 and an Altivec register. Allow TImode in all VSX registers if the user
2074 if (TARGET_VSX && VSX_REGNO_P (regno)
2075 && (VECTOR_MEM_VSX_P (mode)
2076 || FLOAT128_VECTOR_P (mode)
2077 || reg_addr[mode].scalar_in_vmx_p
2079 || (TARGET_VADDUQM && mode == V1TImode)))
2081 if (FP_REGNO_P (regno))
2082 return FP_REGNO_P (last_regno);
2084 if (ALTIVEC_REGNO_P (regno))
2086 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
2089 return ALTIVEC_REGNO_P (last_regno);
2093 /* The GPRs can hold any mode, but values bigger than one register
2094 cannot go past R31. */
2095 if (INT_REGNO_P (regno))
2096 return INT_REGNO_P (last_regno);
2098 /* The float registers (except for VSX vector modes) can only hold floating
2099 modes and DImode. */
2100 if (FP_REGNO_P (regno))
2102 if (FLOAT128_VECTOR_P (mode))
2105 if (SCALAR_FLOAT_MODE_P (mode)
2106 && (mode != TDmode || (regno % 2) == 0)
2107 && FP_REGNO_P (last_regno))
2110 if (GET_MODE_CLASS (mode) == MODE_INT)
2112 if(GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
2115 if (TARGET_P8_VECTOR && (mode == SImode))
2118 if (TARGET_P9_VECTOR && (mode == QImode || mode == HImode))
2125 /* The CR register can only hold CC modes. */
2126 if (CR_REGNO_P (regno))
2127 return GET_MODE_CLASS (mode) == MODE_CC;
2129 if (CA_REGNO_P (regno))
2130 return mode == Pmode || mode == SImode;
2132 /* AltiVec only in AldyVec registers. */
2133 if (ALTIVEC_REGNO_P (regno))
2134 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
2135 || mode == V1TImode);
2137 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2138 and it must be able to fit within the register set. */
2140 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
2143 /* Implement TARGET_HARD_REGNO_NREGS. */
2146 rs6000_hard_regno_nregs_hook (unsigned int regno, machine_mode mode)
2148 return rs6000_hard_regno_nregs[mode][regno];
2151 /* Implement TARGET_HARD_REGNO_MODE_OK. */
2154 rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
2156 return rs6000_hard_regno_mode_ok_p[mode][regno];
2159 /* Implement TARGET_MODES_TIEABLE_P.
2161 PTImode cannot tie with other modes because PTImode is restricted to even
2162 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
2165 Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE
2166 128-bit floating point on VSX systems ties with other vectors. */
2169 rs6000_modes_tieable_p (machine_mode mode1, machine_mode mode2)
2171 if (mode1 == PTImode)
2172 return mode2 == PTImode;
2173 if (mode2 == PTImode)
2176 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode1))
2177 return ALTIVEC_OR_VSX_VECTOR_MODE (mode2);
2178 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode2))
2181 if (SCALAR_FLOAT_MODE_P (mode1))
2182 return SCALAR_FLOAT_MODE_P (mode2);
2183 if (SCALAR_FLOAT_MODE_P (mode2))
2186 if (GET_MODE_CLASS (mode1) == MODE_CC)
2187 return GET_MODE_CLASS (mode2) == MODE_CC;
2188 if (GET_MODE_CLASS (mode2) == MODE_CC)
2194 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. */
2197 rs6000_hard_regno_call_part_clobbered (rtx_insn *insn ATTRIBUTE_UNUSED,
2198 unsigned int regno, machine_mode mode)
2202 && GET_MODE_SIZE (mode) > 4
2203 && INT_REGNO_P (regno))
2207 && FP_REGNO_P (regno)
2208 && GET_MODE_SIZE (mode) > 8
2209 && !FLOAT128_2REG_P (mode))
2215 /* Print interesting facts about registers. */
2217 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
2221 for (r = first_regno; r <= last_regno; ++r)
2223 const char *comma = "";
2226 if (first_regno == last_regno)
2227 fprintf (stderr, "%s:\t", reg_name);
2229 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
2232 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2233 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
2237 fprintf (stderr, ",\n\t");
2242 if (rs6000_hard_regno_nregs[m][r] > 1)
2243 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
2244 rs6000_hard_regno_nregs[m][r]);
2246 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
2251 if (call_used_regs[r])
2255 fprintf (stderr, ",\n\t");
2260 len += fprintf (stderr, "%s%s", comma, "call-used");
2268 fprintf (stderr, ",\n\t");
2273 len += fprintf (stderr, "%s%s", comma, "fixed");
2279 fprintf (stderr, ",\n\t");
2283 len += fprintf (stderr, "%sreg-class = %s", comma,
2284 reg_class_names[(int)rs6000_regno_regclass[r]]);
2289 fprintf (stderr, ",\n\t");
2293 fprintf (stderr, "%sregno = %d\n", comma, r);
2298 rs6000_debug_vector_unit (enum rs6000_vector v)
2304 case VECTOR_NONE: ret = "none"; break;
2305 case VECTOR_ALTIVEC: ret = "altivec"; break;
2306 case VECTOR_VSX: ret = "vsx"; break;
2307 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
2308 default: ret = "unknown"; break;
2314 /* Inner function printing just the address mask for a particular reload
2316 DEBUG_FUNCTION char *
2317 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
2322 if ((mask & RELOAD_REG_VALID) != 0)
2324 else if (keep_spaces)
2327 if ((mask & RELOAD_REG_MULTIPLE) != 0)
2329 else if (keep_spaces)
2332 if ((mask & RELOAD_REG_INDEXED) != 0)
2334 else if (keep_spaces)
2337 if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
2339 else if ((mask & RELOAD_REG_OFFSET) != 0)
2341 else if (keep_spaces)
2344 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
2346 else if (keep_spaces)
2349 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
2351 else if (keep_spaces)
2354 if ((mask & RELOAD_REG_AND_M16) != 0)
2356 else if (keep_spaces)
2364 /* Print the address masks in a human readble fashion. */
2366 rs6000_debug_print_mode (ssize_t m)
2371 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
2372 for (rc = 0; rc < N_RELOAD_REG; rc++)
2373 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
2374 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
2376 if ((reg_addr[m].reload_store != CODE_FOR_nothing)
2377 || (reg_addr[m].reload_load != CODE_FOR_nothing))
2379 fprintf (stderr, "%*s Reload=%c%c", spaces, "",
2380 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2381 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*');
2385 spaces += sizeof (" Reload=sl") - 1;
2387 if (reg_addr[m].scalar_in_vmx_p)
2389 fprintf (stderr, "%*s Upper=y", spaces, "");
2393 spaces += sizeof (" Upper=y") - 1;
2395 if (rs6000_vector_unit[m] != VECTOR_NONE
2396 || rs6000_vector_mem[m] != VECTOR_NONE)
2398 fprintf (stderr, "%*s vector: arith=%-10s mem=%s",
2400 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2401 rs6000_debug_vector_unit (rs6000_vector_mem[m]));
2404 fputs ("\n", stderr);
2407 #define DEBUG_FMT_ID "%-32s= "
2408 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2409 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2410 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2412 /* Print various interesting information with -mdebug=reg. */
2414 rs6000_debug_reg_global (void)
2416 static const char *const tf[2] = { "false", "true" };
2417 const char *nl = (const char *)0;
2420 char costly_num[20];
2422 char flags_buffer[40];
2423 const char *costly_str;
2424 const char *nop_str;
2425 const char *trace_str;
2426 const char *abi_str;
2427 const char *cmodel_str;
2428 struct cl_target_option cl_opts;
2430 /* Modes we want tieable information on. */
2431 static const machine_mode print_tieable_modes[] = {
2465 /* Virtual regs we are interested in. */
2466 const static struct {
2467 int regno; /* register number. */
2468 const char *name; /* register name. */
2469 } virtual_regs[] = {
2470 { STACK_POINTER_REGNUM, "stack pointer:" },
2471 { TOC_REGNUM, "toc: " },
2472 { STATIC_CHAIN_REGNUM, "static chain: " },
2473 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2474 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2475 { ARG_POINTER_REGNUM, "arg pointer: " },
2476 { FRAME_POINTER_REGNUM, "frame pointer:" },
2477 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2478 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2479 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2480 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2481 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2482 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2483 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2484 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2485 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2488 fputs ("\nHard register information:\n", stderr);
2489 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2490 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2491 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2494 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2495 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2496 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2497 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2498 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2499 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2501 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2502 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2503 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2507 "d reg_class = %s\n"
2508 "f reg_class = %s\n"
2509 "v reg_class = %s\n"
2510 "wa reg_class = %s\n"
2511 "wd reg_class = %s\n"
2512 "we reg_class = %s\n"
2513 "wf reg_class = %s\n"
2514 "wg reg_class = %s\n"
2515 "wi reg_class = %s\n"
2516 "wk reg_class = %s\n"
2517 "wl reg_class = %s\n"
2518 "wm reg_class = %s\n"
2519 "wp reg_class = %s\n"
2520 "wq reg_class = %s\n"
2521 "wr reg_class = %s\n"
2522 "ws reg_class = %s\n"
2523 "wt reg_class = %s\n"
2524 "wv reg_class = %s\n"
2525 "ww reg_class = %s\n"
2526 "wx reg_class = %s\n"
2527 "wz reg_class = %s\n"
2528 "wA reg_class = %s\n"
2530 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2531 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2532 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2533 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2534 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2535 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
2536 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2537 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2538 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2539 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
2540 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
2541 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
2542 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
2543 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
2544 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2545 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2546 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2547 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2548 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2549 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2550 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
2551 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
2554 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2555 rs6000_debug_print_mode (m);
2557 fputs ("\n", stderr);
2559 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2561 machine_mode mode1 = print_tieable_modes[m1];
2562 bool first_time = true;
2564 nl = (const char *)0;
2565 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2567 machine_mode mode2 = print_tieable_modes[m2];
2568 if (mode1 != mode2 && rs6000_modes_tieable_p (mode1, mode2))
2572 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2577 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2582 fputs ("\n", stderr);
2588 if (rs6000_recip_control)
2590 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2592 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2593 if (rs6000_recip_bits[m])
2596 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2598 (RS6000_RECIP_AUTO_RE_P (m)
2600 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2601 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2603 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2606 fputs ("\n", stderr);
2609 if (rs6000_cpu_index >= 0)
2611 const char *name = processor_target_table[rs6000_cpu_index].name;
2613 = processor_target_table[rs6000_cpu_index].target_enable;
2615 sprintf (flags_buffer, "-mcpu=%s flags", name);
2616 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2619 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2621 if (rs6000_tune_index >= 0)
2623 const char *name = processor_target_table[rs6000_tune_index].name;
2625 = processor_target_table[rs6000_tune_index].target_enable;
2627 sprintf (flags_buffer, "-mtune=%s flags", name);
2628 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2631 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2633 cl_target_option_save (&cl_opts, &global_options);
2634 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2637 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2638 rs6000_isa_flags_explicit);
2640 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2641 rs6000_builtin_mask);
2643 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2645 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2646 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2648 switch (rs6000_sched_costly_dep)
2650 case max_dep_latency:
2651 costly_str = "max_dep_latency";
2655 costly_str = "no_dep_costly";
2658 case all_deps_costly:
2659 costly_str = "all_deps_costly";
2662 case true_store_to_load_dep_costly:
2663 costly_str = "true_store_to_load_dep_costly";
2666 case store_to_load_dep_costly:
2667 costly_str = "store_to_load_dep_costly";
2671 costly_str = costly_num;
2672 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2676 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2678 switch (rs6000_sched_insert_nops)
2680 case sched_finish_regroup_exact:
2681 nop_str = "sched_finish_regroup_exact";
2684 case sched_finish_pad_groups:
2685 nop_str = "sched_finish_pad_groups";
2688 case sched_finish_none:
2689 nop_str = "sched_finish_none";
2694 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2698 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2700 switch (rs6000_sdata)
2707 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2711 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2715 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2720 switch (rs6000_traceback)
2722 case traceback_default: trace_str = "default"; break;
2723 case traceback_none: trace_str = "none"; break;
2724 case traceback_part: trace_str = "part"; break;
2725 case traceback_full: trace_str = "full"; break;
2726 default: trace_str = "unknown"; break;
2729 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2731 switch (rs6000_current_cmodel)
2733 case CMODEL_SMALL: cmodel_str = "small"; break;
2734 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2735 case CMODEL_LARGE: cmodel_str = "large"; break;
2736 default: cmodel_str = "unknown"; break;
2739 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2741 switch (rs6000_current_abi)
2743 case ABI_NONE: abi_str = "none"; break;
2744 case ABI_AIX: abi_str = "aix"; break;
2745 case ABI_ELFv2: abi_str = "ELFv2"; break;
2746 case ABI_V4: abi_str = "V4"; break;
2747 case ABI_DARWIN: abi_str = "darwin"; break;
2748 default: abi_str = "unknown"; break;
2751 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2753 if (rs6000_altivec_abi)
2754 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2756 if (rs6000_darwin64_abi)
2757 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2759 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2760 (TARGET_SOFT_FLOAT ? "true" : "false"));
2762 if (TARGET_LINK_STACK)
2763 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2765 if (TARGET_P8_FUSION)
2769 strcpy (options, "power8");
2770 if (TARGET_P8_FUSION_SIGN)
2771 strcat (options, ", sign");
2773 fprintf (stderr, DEBUG_FMT_S, "fusion", options);
2776 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2777 TARGET_SECURE_PLT ? "secure" : "bss");
2778 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2779 aix_struct_return ? "aix" : "sysv");
2780 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2781 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2782 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2783 tf[!!rs6000_align_branch_targets]);
2784 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2785 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2786 rs6000_long_double_type_size);
2787 if (rs6000_long_double_type_size > 64)
2789 fprintf (stderr, DEBUG_FMT_S, "long double type",
2790 TARGET_IEEEQUAD ? "IEEE" : "IBM");
2791 fprintf (stderr, DEBUG_FMT_S, "default long double type",
2792 TARGET_IEEEQUAD_DEFAULT ? "IEEE" : "IBM");
2794 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2795 (int)rs6000_sched_restricted_insns_priority);
2796 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2798 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2799 (int)RS6000_BUILTIN_COUNT);
2801 fprintf (stderr, DEBUG_FMT_D, "Enable float128 on VSX",
2802 (int)TARGET_FLOAT128_ENABLE_TYPE);
2805 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2806 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2808 if (TARGET_DIRECT_MOVE_128)
2809 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
2810 (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
2814 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2815 legitimate address support to figure out the appropriate addressing to
2819 rs6000_setup_reg_addr_masks (void)
2821 ssize_t rc, reg, m, nregs;
2822 addr_mask_type any_addr_mask, addr_mask;
2824 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2826 machine_mode m2 = (machine_mode) m;
2827 bool complex_p = false;
2828 bool small_int_p = (m2 == QImode || m2 == HImode || m2 == SImode);
2831 if (COMPLEX_MODE_P (m2))
2834 m2 = GET_MODE_INNER (m2);
2837 msize = GET_MODE_SIZE (m2);
2839 /* SDmode is special in that we want to access it only via REG+REG
2840 addressing on power7 and above, since we want to use the LFIWZX and
2841 STFIWZX instructions to load it. */
2842 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2845 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2848 reg = reload_reg_map[rc].reg;
2850 /* Can mode values go in the GPR/FPR/Altivec registers? */
2851 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2853 bool small_int_vsx_p = (small_int_p
2854 && (rc == RELOAD_REG_FPR
2855 || rc == RELOAD_REG_VMX));
2857 nregs = rs6000_hard_regno_nregs[m][reg];
2858 addr_mask |= RELOAD_REG_VALID;
2860 /* Indicate if the mode takes more than 1 physical register. If
2861 it takes a single register, indicate it can do REG+REG
2862 addressing. Small integers in VSX registers can only do
2863 REG+REG addressing. */
2864 if (small_int_vsx_p)
2865 addr_mask |= RELOAD_REG_INDEXED;
2866 else if (nregs > 1 || m == BLKmode || complex_p)
2867 addr_mask |= RELOAD_REG_MULTIPLE;
2869 addr_mask |= RELOAD_REG_INDEXED;
2871 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2872 addressing. If we allow scalars into Altivec registers,
2873 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY.
2875 For VSX systems, we don't allow update addressing for
2876 DFmode/SFmode if those registers can go in both the
2877 traditional floating point registers and Altivec registers.
2878 The load/store instructions for the Altivec registers do not
2879 have update forms. If we allowed update addressing, it seems
2880 to break IV-OPT code using floating point if the index type is
2881 int instead of long (PR target/81550 and target/84042). */
2884 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2886 && !VECTOR_MODE_P (m2)
2887 && !FLOAT128_VECTOR_P (m2)
2889 && (m != E_DFmode || !TARGET_VSX)
2890 && (m != E_SFmode || !TARGET_P8_VECTOR)
2891 && !small_int_vsx_p)
2893 addr_mask |= RELOAD_REG_PRE_INCDEC;
2895 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2896 we don't allow PRE_MODIFY for some multi-register
2901 addr_mask |= RELOAD_REG_PRE_MODIFY;
2905 if (TARGET_POWERPC64)
2906 addr_mask |= RELOAD_REG_PRE_MODIFY;
2911 if (TARGET_HARD_FLOAT)
2912 addr_mask |= RELOAD_REG_PRE_MODIFY;
2918 /* GPR and FPR registers can do REG+OFFSET addressing, except
2919 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
2920 for 64-bit scalars and 32-bit SFmode to altivec registers. */
2921 if ((addr_mask != 0) && !indexed_only_p
2923 && (rc == RELOAD_REG_GPR
2924 || ((msize == 8 || m2 == SFmode)
2925 && (rc == RELOAD_REG_FPR
2926 || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
2927 addr_mask |= RELOAD_REG_OFFSET;
2929 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
2930 instructions are enabled. The offset for 128-bit VSX registers is
2931 only 12-bits. While GPRs can handle the full offset range, VSX
2932 registers can only handle the restricted range. */
2933 else if ((addr_mask != 0) && !indexed_only_p
2934 && msize == 16 && TARGET_P9_VECTOR
2935 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
2936 || (m2 == TImode && TARGET_VSX)))
2938 addr_mask |= RELOAD_REG_OFFSET;
2939 if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
2940 addr_mask |= RELOAD_REG_QUAD_OFFSET;
2943 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2944 addressing on 128-bit types. */
2945 if (rc == RELOAD_REG_VMX && msize == 16
2946 && (addr_mask & RELOAD_REG_VALID) != 0)
2947 addr_mask |= RELOAD_REG_AND_M16;
2949 reg_addr[m].addr_mask[rc] = addr_mask;
2950 any_addr_mask |= addr_mask;
2953 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
2958 /* Initialize the various global tables that are based on register size. */
2960 rs6000_init_hard_regno_mode_ok (bool global_init_p)
2966 /* Precalculate REGNO_REG_CLASS. */
2967 rs6000_regno_regclass[0] = GENERAL_REGS;
2968 for (r = 1; r < 32; ++r)
2969 rs6000_regno_regclass[r] = BASE_REGS;
2971 for (r = 32; r < 64; ++r)
2972 rs6000_regno_regclass[r] = FLOAT_REGS;
2974 for (r = 64; HARD_REGISTER_NUM_P (r); ++r)
2975 rs6000_regno_regclass[r] = NO_REGS;
2977 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
2978 rs6000_regno_regclass[r] = ALTIVEC_REGS;
2980 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
2981 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
2982 rs6000_regno_regclass[r] = CR_REGS;
2984 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
2985 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
2986 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
2987 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
2988 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
2989 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
2990 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
2992 /* Precalculate register class to simpler reload register class. We don't
2993 need all of the register classes that are combinations of different
2994 classes, just the simple ones that have constraint letters. */
2995 for (c = 0; c < N_REG_CLASSES; c++)
2996 reg_class_to_reg_type[c] = NO_REG_TYPE;
2998 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
2999 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
3000 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
3001 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
3002 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
3003 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
3004 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
3005 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
3006 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
3007 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
3011 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
3012 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
3016 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
3017 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
3020 /* Precalculate the valid memory formats as well as the vector information,
3021 this must be set up before the rs6000_hard_regno_nregs_internal calls
3023 gcc_assert ((int)VECTOR_NONE == 0);
3024 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
3025 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_mem));
3027 gcc_assert ((int)CODE_FOR_nothing == 0);
3028 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
3030 gcc_assert ((int)NO_REGS == 0);
3031 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
3033 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
3034 believes it can use native alignment or still uses 128-bit alignment. */
3035 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
3046 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3047 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3048 if (TARGET_FLOAT128_TYPE)
3050 rs6000_vector_mem[KFmode] = VECTOR_VSX;
3051 rs6000_vector_align[KFmode] = 128;
3053 if (FLOAT128_IEEE_P (TFmode))
3055 rs6000_vector_mem[TFmode] = VECTOR_VSX;
3056 rs6000_vector_align[TFmode] = 128;
3060 /* V2DF mode, VSX only. */
3063 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
3064 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
3065 rs6000_vector_align[V2DFmode] = align64;
3068 /* V4SF mode, either VSX or Altivec. */
3071 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
3072 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
3073 rs6000_vector_align[V4SFmode] = align32;
3075 else if (TARGET_ALTIVEC)
3077 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
3078 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
3079 rs6000_vector_align[V4SFmode] = align32;
3082 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3086 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
3087 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
3088 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
3089 rs6000_vector_align[V4SImode] = align32;
3090 rs6000_vector_align[V8HImode] = align32;
3091 rs6000_vector_align[V16QImode] = align32;
3095 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
3096 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
3097 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
3101 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
3102 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
3103 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
3107 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3108 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3111 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
3112 rs6000_vector_unit[V2DImode]
3113 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3114 rs6000_vector_align[V2DImode] = align64;
3116 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
3117 rs6000_vector_unit[V1TImode]
3118 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
3119 rs6000_vector_align[V1TImode] = 128;
3122 /* DFmode, see if we want to use the VSX unit. Memory is handled
3123 differently, so don't set rs6000_vector_mem. */
3126 rs6000_vector_unit[DFmode] = VECTOR_VSX;
3127 rs6000_vector_align[DFmode] = 64;
3130 /* SFmode, see if we want to use the VSX unit. */
3131 if (TARGET_P8_VECTOR)
3133 rs6000_vector_unit[SFmode] = VECTOR_VSX;
3134 rs6000_vector_align[SFmode] = 32;
3137 /* Allow TImode in VSX register and set the VSX memory macros. */
3140 rs6000_vector_mem[TImode] = VECTOR_VSX;
3141 rs6000_vector_align[TImode] = align64;
3144 /* Register class constraints for the constraints that depend on compile
3145 switches. When the VSX code was added, different constraints were added
3146 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3147 of the VSX registers are used. The register classes for scalar floating
3148 point types is set, based on whether we allow that type into the upper
3149 (Altivec) registers. GCC has register classes to target the Altivec
3150 registers for load/store operations, to select using a VSX memory
3151 operation instead of the traditional floating point operation. The
3154 d - Register class to use with traditional DFmode instructions.
3155 f - Register class to use with traditional SFmode instructions.
3156 v - Altivec register.
3157 wa - Any VSX register.
3158 wc - Reserved to represent individual CR bits (used in LLVM).
3159 wd - Preferred register class for V2DFmode.
3160 wf - Preferred register class for V4SFmode.
3161 wg - Float register for power6x move insns.
3162 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3163 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3164 wl - Float register if we can do 32-bit signed int loads.
3165 wm - VSX register for ISA 2.07 direct move operations.
3166 wn - always NO_REGS.
3167 wr - GPR if 64-bit mode is permitted.
3168 ws - Register class to do ISA 2.06 DF operations.
3169 wt - VSX register for TImode in VSX registers.
3170 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3171 ww - Register class to do SF conversions in with VSX operations.
3172 wx - Float register if we can do 32-bit int stores.
3173 wz - Float register if we can do 32-bit unsigned int loads. */
3175 if (TARGET_HARD_FLOAT)
3177 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
3178 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
3183 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
3184 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
3185 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
3186 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; /* DFmode */
3187 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; /* DFmode */
3188 rs6000_constraints[RS6000_CONSTRAINT_wi] = VSX_REGS; /* DImode */
3189 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
3192 /* Add conditional constraints based on various options, to allow us to
3193 collapse multiple insn patterns. */
3195 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
3197 if (TARGET_MFPGPR) /* DFmode */
3198 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
3201 rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
3203 if (TARGET_DIRECT_MOVE)
3205 rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
3206 = rs6000_constraints[RS6000_CONSTRAINT_ws];
3207 rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
3210 if (TARGET_POWERPC64)
3212 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
3213 rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
3216 if (TARGET_P8_VECTOR) /* SFmode */
3217 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
3218 else if (TARGET_VSX)
3219 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
3222 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
3225 rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */
3227 if (TARGET_FLOAT128_TYPE)
3229 rs6000_constraints[RS6000_CONSTRAINT_wq] = VSX_REGS; /* KFmode */
3230 if (FLOAT128_IEEE_P (TFmode))
3231 rs6000_constraints[RS6000_CONSTRAINT_wp] = VSX_REGS; /* TFmode */
3234 /* Support for new direct moves (ISA 3.0 + 64bit). */
3235 if (TARGET_DIRECT_MOVE_128)
3236 rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
3238 /* Set up the reload helper and direct move functions. */
3239 if (TARGET_VSX || TARGET_ALTIVEC)
3243 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
3244 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
3245 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
3246 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
3247 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
3248 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
3249 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
3250 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
3251 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
3252 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
3253 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
3254 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
3255 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
3256 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
3257 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
3258 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
3259 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
3260 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
3261 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
3262 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
3264 if (FLOAT128_VECTOR_P (KFmode))
3266 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_di_store;
3267 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_di_load;
3270 if (FLOAT128_VECTOR_P (TFmode))
3272 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_di_store;
3273 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_di_load;
3276 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3278 if (TARGET_NO_SDMODE_STACK)
3280 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
3281 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
3286 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
3287 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
3290 if (TARGET_DIRECT_MOVE && !TARGET_DIRECT_MOVE_128)
3292 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
3293 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
3294 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
3295 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
3296 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
3297 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
3298 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
3299 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
3300 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
3302 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
3303 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
3304 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
3305 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
3306 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
3307 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
3308 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
3309 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
3310 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
3312 if (FLOAT128_VECTOR_P (KFmode))
3314 reg_addr[KFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxkf;
3315 reg_addr[KFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprkf;
3318 if (FLOAT128_VECTOR_P (TFmode))
3320 reg_addr[TFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxtf;
3321 reg_addr[TFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprtf;
3327 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
3328 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
3329 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
3330 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
3331 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
3332 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
3333 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
3334 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
3335 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
3336 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
3337 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
3338 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
3339 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
3340 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
3341 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
3342 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
3343 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
3344 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
3345 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
3346 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
3348 if (FLOAT128_VECTOR_P (KFmode))
3350 reg_addr[KFmode].reload_store = CODE_FOR_reload_kf_si_store;
3351 reg_addr[KFmode].reload_load = CODE_FOR_reload_kf_si_load;
3354 if (FLOAT128_IEEE_P (TFmode))
3356 reg_addr[TFmode].reload_store = CODE_FOR_reload_tf_si_store;
3357 reg_addr[TFmode].reload_load = CODE_FOR_reload_tf_si_load;
3360 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3362 if (TARGET_NO_SDMODE_STACK)
3364 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
3365 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
3370 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
3371 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
3374 if (TARGET_DIRECT_MOVE)
3376 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
3377 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
3378 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
3382 reg_addr[DFmode].scalar_in_vmx_p = true;
3383 reg_addr[DImode].scalar_in_vmx_p = true;
3385 if (TARGET_P8_VECTOR)
3387 reg_addr[SFmode].scalar_in_vmx_p = true;
3388 reg_addr[SImode].scalar_in_vmx_p = true;
3390 if (TARGET_P9_VECTOR)
3392 reg_addr[HImode].scalar_in_vmx_p = true;
3393 reg_addr[QImode].scalar_in_vmx_p = true;
3398 /* Precalculate HARD_REGNO_NREGS. */
3399 for (r = 0; HARD_REGISTER_NUM_P (r); ++r)
3400 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3401 rs6000_hard_regno_nregs[m][r]
3402 = rs6000_hard_regno_nregs_internal (r, (machine_mode) m);
3404 /* Precalculate TARGET_HARD_REGNO_MODE_OK. */
3405 for (r = 0; HARD_REGISTER_NUM_P (r); ++r)
3406 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3407 rs6000_hard_regno_mode_ok_p[m][r]
3408 = rs6000_hard_regno_mode_ok_uncached (r, (machine_mode) m);
3410 /* Precalculate CLASS_MAX_NREGS sizes. */
3411 for (c = 0; c < LIM_REG_CLASSES; ++c)
3415 if (TARGET_VSX && VSX_REG_CLASS_P (c))
3416 reg_size = UNITS_PER_VSX_WORD;
3418 else if (c == ALTIVEC_REGS)
3419 reg_size = UNITS_PER_ALTIVEC_WORD;
3421 else if (c == FLOAT_REGS)
3422 reg_size = UNITS_PER_FP_WORD;
3425 reg_size = UNITS_PER_WORD;
3427 for (m = 0; m < NUM_MACHINE_MODES; ++m)
3429 machine_mode m2 = (machine_mode)m;
3430 int reg_size2 = reg_size;
3432 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3434 if (TARGET_VSX && VSX_REG_CLASS_P (c) && FLOAT128_2REG_P (m))
3435 reg_size2 = UNITS_PER_FP_WORD;
3437 rs6000_class_max_nregs[m][c]
3438 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
3442 /* Calculate which modes to automatically generate code to use a the
3443 reciprocal divide and square root instructions. In the future, possibly
3444 automatically generate the instructions even if the user did not specify
3445 -mrecip. The older machines double precision reciprocal sqrt estimate is
3446 not accurate enough. */
3447 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
3449 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3451 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3452 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3453 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
3454 if (VECTOR_UNIT_VSX_P (V2DFmode))
3455 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
3457 if (TARGET_FRSQRTES)
3458 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3460 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3461 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
3462 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3463 if (VECTOR_UNIT_VSX_P (V2DFmode))
3464 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
3466 if (rs6000_recip_control)
3468 if (!flag_finite_math_only)
3469 warning (0, "%qs requires %qs or %qs", "-mrecip", "-ffinite-math",
3471 if (flag_trapping_math)
3472 warning (0, "%qs requires %qs or %qs", "-mrecip",
3473 "-fno-trapping-math", "-ffast-math");
3474 if (!flag_reciprocal_math)
3475 warning (0, "%qs requires %qs or %qs", "-mrecip", "-freciprocal-math",
3477 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
3479 if (RS6000_RECIP_HAVE_RE_P (SFmode)
3480 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
3481 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3483 if (RS6000_RECIP_HAVE_RE_P (DFmode)
3484 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
3485 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3487 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3488 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3489 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3491 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3492 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3493 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3495 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3496 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3497 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3499 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3500 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3501 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3503 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3504 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3505 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3507 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3508 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3509 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3513 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3514 legitimate address support to figure out the appropriate addressing to
3516 rs6000_setup_reg_addr_masks ();
3518 if (global_init_p || TARGET_DEBUG_TARGET)
3520 if (TARGET_DEBUG_REG)
3521 rs6000_debug_reg_global ();
3523 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3525 "SImode variable mult cost = %d\n"
3526 "SImode constant mult cost = %d\n"
3527 "SImode short constant mult cost = %d\n"
3528 "DImode multipliciation cost = %d\n"
3529 "SImode division cost = %d\n"
3530 "DImode division cost = %d\n"
3531 "Simple fp operation cost = %d\n"
3532 "DFmode multiplication cost = %d\n"
3533 "SFmode division cost = %d\n"
3534 "DFmode division cost = %d\n"
3535 "cache line size = %d\n"
3536 "l1 cache size = %d\n"
3537 "l2 cache size = %d\n"
3538 "simultaneous prefetches = %d\n"
3541 rs6000_cost->mulsi_const,
3542 rs6000_cost->mulsi_const9,
3550 rs6000_cost->cache_line_size,
3551 rs6000_cost->l1_cache_size,
3552 rs6000_cost->l2_cache_size,
3553 rs6000_cost->simultaneous_prefetches);
3558 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3561 darwin_rs6000_override_options (void)
3563 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3565 rs6000_altivec_abi = 1;
3566 TARGET_ALTIVEC_VRSAVE = 1;
3567 rs6000_current_abi = ABI_DARWIN;
3569 if (DEFAULT_ABI == ABI_DARWIN
3571 darwin_one_byte_bool = 1;
3573 if (TARGET_64BIT && ! TARGET_POWERPC64)
3575 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3576 warning (0, "%qs requires PowerPC64 architecture, enabling", "-m64");
3580 rs6000_default_long_calls = 1;
3581 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3584 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3586 if (!flag_mkernel && !flag_apple_kext
3588 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3589 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3591 /* Unless the user (not the configurer) has explicitly overridden
3592 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3593 G4 unless targeting the kernel. */
3596 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3597 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3598 && ! global_options_set.x_rs6000_cpu_index)
3600 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3605 /* If not otherwise specified by a target, make 'long double' equivalent to
3608 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3609 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3612 /* Return the builtin mask of the various options used that could affect which
3613 builtins were used. In the past we used target_flags, but we've run out of
3614 bits, and some options are no longer in target_flags. */
3617 rs6000_builtin_mask_calculate (void)
3619 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3620 | ((TARGET_CMPB) ? RS6000_BTM_CMPB : 0)
3621 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3622 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3623 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3624 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3625 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3626 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3627 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3628 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3629 | ((TARGET_P9_VECTOR) ? RS6000_BTM_P9_VECTOR : 0)
3630 | ((TARGET_P9_MISC) ? RS6000_BTM_P9_MISC : 0)
3631 | ((TARGET_MODULO) ? RS6000_BTM_MODULO : 0)
3632 | ((TARGET_64BIT) ? RS6000_BTM_64BIT : 0)
3633 | ((TARGET_POWERPC64) ? RS6000_BTM_POWERPC64 : 0)
3634 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3635 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3636 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3637 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3638 | ((TARGET_LONG_DOUBLE_128
3639 && TARGET_HARD_FLOAT
3640 && !TARGET_IEEEQUAD) ? RS6000_BTM_LDBL128 : 0)
3641 | ((TARGET_FLOAT128_TYPE) ? RS6000_BTM_FLOAT128 : 0)
3642 | ((TARGET_FLOAT128_HW) ? RS6000_BTM_FLOAT128_HW : 0));
3645 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3646 to clobber the XER[CA] bit because clobbering that bit without telling
3647 the compiler worked just fine with versions of GCC before GCC 5, and
3648 breaking a lot of older code in ways that are hard to track down is
3649 not such a great idea. */
3652 rs6000_md_asm_adjust (vec<rtx> &/*outputs*/, vec<rtx> &/*inputs*/,
3653 vec<const char *> &/*constraints*/,
3654 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs)
3656 clobbers.safe_push (gen_rtx_REG (SImode, CA_REGNO));
3657 SET_HARD_REG_BIT (clobbered_regs, CA_REGNO);
3661 /* Override command line options.
3663 Combine build-specific configuration information with options
3664 specified on the command line to set various state variables which
3665 influence code generation, optimization, and expansion of built-in
3666 functions. Assure that command-line configuration preferences are
3667 compatible with each other and with the build configuration; issue
3668 warnings while adjusting configuration or error messages while
3669 rejecting configuration.
3671 Upon entry to this function:
3673 This function is called once at the beginning of
3674 compilation, and then again at the start and end of compiling
3675 each section of code that has a different configuration, as
3676 indicated, for example, by adding the
3678 __attribute__((__target__("cpu=power9")))
3680 qualifier to a function definition or, for example, by bracketing
3683 #pragma GCC target("altivec")
3687 #pragma GCC reset_options
3689 directives. Parameter global_init_p is true for the initial
3690 invocation, which initializes global variables, and false for all
3691 subsequent invocations.
3694 Various global state information is assumed to be valid. This
3695 includes OPTION_TARGET_CPU_DEFAULT, representing the name of the
3696 default CPU specified at build configure time, TARGET_DEFAULT,
3697 representing the default set of option flags for the default
3698 target, and global_options_set.x_rs6000_isa_flags, representing
3699 which options were requested on the command line.
3701 Upon return from this function:
3703 rs6000_isa_flags_explicit has a non-zero bit for each flag that
3704 was set by name on the command line. Additionally, if certain
3705 attributes are automatically enabled or disabled by this function
3706 in order to assure compatibility between options and
3707 configuration, the flags associated with those attributes are
3708 also set. By setting these "explicit bits", we avoid the risk
3709 that other code might accidentally overwrite these particular
3710 attributes with "default values".
3712 The various bits of rs6000_isa_flags are set to indicate the
3713 target options that have been selected for the most current
3714 compilation efforts. This has the effect of also turning on the
3715 associated TARGET_XXX values since these are macros which are
3716 generally defined to test the corresponding bit of the
3717 rs6000_isa_flags variable.
3719 The variable rs6000_builtin_mask is set to represent the target
3720 options for the most current compilation efforts, consistent with
3721 the current contents of rs6000_isa_flags. This variable controls
3722 expansion of built-in functions.
3724 Various other global variables and fields of global structures
3725 (over 50 in all) are initialized to reflect the desired options
3726 for the most current compilation efforts. */
3729 rs6000_option_override_internal (bool global_init_p)
3733 HOST_WIDE_INT set_masks;
3734 HOST_WIDE_INT ignore_masks;
3737 struct cl_target_option *main_target_opt
3738 = ((global_init_p || target_option_default_node == NULL)
3739 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
3741 /* Print defaults. */
3742 if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
3743 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
3745 /* Remember the explicit arguments. */
3747 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
3749 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3750 library functions, so warn about it. The flag may be useful for
3751 performance studies from time to time though, so don't disable it
3753 if (global_options_set.x_rs6000_alignment_flags
3754 && rs6000_alignment_flags == MASK_ALIGN_POWER
3755 && DEFAULT_ABI == ABI_DARWIN
3757 warning (0, "%qs is not supported for 64-bit Darwin;"
3758 " it is incompatible with the installed C and C++ libraries",
3761 /* Numerous experiment shows that IRA based loop pressure
3762 calculation works better for RTL loop invariant motion on targets
3763 with enough (>= 32) registers. It is an expensive optimization.
3764 So it is on only for peak performance. */
3765 if (optimize >= 3 && global_init_p
3766 && !global_options_set.x_flag_ira_loop_pressure)
3767 flag_ira_loop_pressure = 1;
3769 /* -fsanitize=address needs to turn on -fasynchronous-unwind-tables in order
3770 for tracebacks to be complete but not if any -fasynchronous-unwind-tables
3771 options were already specified. */
3772 if (flag_sanitize & SANITIZE_USER_ADDRESS
3773 && !global_options_set.x_flag_asynchronous_unwind_tables)
3774 flag_asynchronous_unwind_tables = 1;
3776 /* Set the pointer size. */
3779 rs6000_pmode = DImode;
3780 rs6000_pointer_size = 64;
3784 rs6000_pmode = SImode;
3785 rs6000_pointer_size = 32;
3788 /* Some OSs don't support saving the high part of 64-bit registers on context
3789 switch. Other OSs don't support saving Altivec registers. On those OSs,
3790 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3791 if the user wants either, the user must explicitly specify them and we
3792 won't interfere with the user's specification. */
3794 set_masks = POWERPC_MASKS;
3795 #ifdef OS_MISSING_POWERPC64
3796 if (OS_MISSING_POWERPC64)
3797 set_masks &= ~OPTION_MASK_POWERPC64;
3799 #ifdef OS_MISSING_ALTIVEC
3800 if (OS_MISSING_ALTIVEC)
3801 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX
3802 | OTHER_VSX_VECTOR_MASKS);
3805 /* Don't override by the processor default if given explicitly. */
3806 set_masks &= ~rs6000_isa_flags_explicit;
3808 if (global_init_p && rs6000_dejagnu_cpu_index >= 0)
3809 rs6000_cpu_index = rs6000_dejagnu_cpu_index;
3811 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3812 the cpu in a target attribute or pragma, but did not specify a tuning
3813 option, use the cpu for the tuning option rather than the option specified
3814 with -mtune on the command line. Process a '--with-cpu' configuration
3815 request as an implicit --cpu. */
3816 if (rs6000_cpu_index >= 0)
3817 cpu_index = rs6000_cpu_index;
3818 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
3819 cpu_index = main_target_opt->x_rs6000_cpu_index;
3820 else if (OPTION_TARGET_CPU_DEFAULT)
3821 cpu_index = rs6000_cpu_name_lookup (OPTION_TARGET_CPU_DEFAULT);
3823 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3824 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3825 with those from the cpu, except for options that were explicitly set. If
3826 we don't have a cpu, do not override the target bits set in
3830 rs6000_cpu_index = cpu_index;
3831 rs6000_isa_flags &= ~set_masks;
3832 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
3837 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3838 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3839 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3840 to using rs6000_isa_flags, we need to do the initialization here.
3842 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3843 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3844 HOST_WIDE_INT flags;
3846 flags = TARGET_DEFAULT;
3849 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3850 const char *default_cpu = (!TARGET_POWERPC64
3855 int default_cpu_index = rs6000_cpu_name_lookup (default_cpu);
3856 flags = processor_target_table[default_cpu_index].target_enable;
3858 rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
3861 if (rs6000_tune_index >= 0)
3862 tune_index = rs6000_tune_index;
3863 else if (cpu_index >= 0)
3864 rs6000_tune_index = tune_index = cpu_index;
3868 enum processor_type tune_proc
3869 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
3872 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
3873 if (processor_target_table[i].processor == tune_proc)
3881 rs6000_cpu = processor_target_table[cpu_index].processor;
3883 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
3885 gcc_assert (tune_index >= 0);
3886 rs6000_tune = processor_target_table[tune_index].processor;
3888 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
3889 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
3890 || rs6000_cpu == PROCESSOR_PPCE5500)
3893 error ("AltiVec not supported in this target");
3896 /* If we are optimizing big endian systems for space, use the load/store
3897 multiple instructions. */
3898 if (BYTES_BIG_ENDIAN && optimize_size)
3899 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE;
3901 /* Don't allow -mmultiple on little endian systems unless the cpu is a 750,
3902 because the hardware doesn't support the instructions used in little
3903 endian mode, and causes an alignment trap. The 750 does not cause an
3904 alignment trap (except when the target is unaligned). */
3906 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750 && TARGET_MULTIPLE)
3908 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
3909 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
3910 warning (0, "%qs is not supported on little endian systems",
3914 /* If little-endian, default to -mstrict-align on older processors.
3915 Testing for htm matches power8 and later. */
3916 if (!BYTES_BIG_ENDIAN
3917 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
3918 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
3920 if (!rs6000_fold_gimple)
3922 "gimple folding of rs6000 builtins has been disabled.\n");
3924 /* Add some warnings for VSX. */
3927 const char *msg = NULL;
3928 if (!TARGET_HARD_FLOAT)
3930 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3931 msg = N_("%<-mvsx%> requires hardware floating point");
3934 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3935 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3938 else if (TARGET_AVOID_XFORM > 0)
3939 msg = N_("%<-mvsx%> needs indexed addressing");
3940 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
3941 & OPTION_MASK_ALTIVEC))
3943 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3944 msg = N_("%<-mvsx%> and %<-mno-altivec%> are incompatible");
3946 msg = N_("%<-mno-altivec%> disables vsx");
3952 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3953 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3957 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3958 the -mcpu setting to enable options that conflict. */
3959 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
3960 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
3961 | OPTION_MASK_ALTIVEC
3962 | OPTION_MASK_VSX)) != 0)
3963 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
3964 | OPTION_MASK_DIRECT_MOVE)
3965 & ~rs6000_isa_flags_explicit);
3967 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
3968 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
3970 /* Handle explicit -mno-{altivec,vsx,power8-vector,power9-vector} and turn
3971 off all of the options that depend on those flags. */
3972 ignore_masks = rs6000_disable_incompatible_switches ();
3974 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3975 unless the user explicitly used the -mno-<option> to disable the code. */
3976 if (TARGET_P9_VECTOR || TARGET_MODULO || TARGET_P9_MISC)
3977 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
3978 else if (TARGET_P9_MINMAX)
3982 if (cpu_index == PROCESSOR_POWER9)
3984 /* legacy behavior: allow -mcpu=power9 with certain
3985 capabilities explicitly disabled. */
3986 rs6000_isa_flags |= (ISA_3_0_MASKS_SERVER & ~ignore_masks);
3989 error ("power9 target option is incompatible with %<%s=<xxx>%> "
3990 "for <xxx> less than power9", "-mcpu");
3992 else if ((ISA_3_0_MASKS_SERVER & rs6000_isa_flags_explicit)
3993 != (ISA_3_0_MASKS_SERVER & rs6000_isa_flags
3994 & rs6000_isa_flags_explicit))
3995 /* Enforce that none of the ISA_3_0_MASKS_SERVER flags
3996 were explicitly cleared. */
3997 error ("%qs incompatible with explicitly disabled options",
4000 rs6000_isa_flags |= ISA_3_0_MASKS_SERVER;
4002 else if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
4003 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~ignore_masks);
4004 else if (TARGET_VSX)
4005 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~ignore_masks);
4006 else if (TARGET_POPCNTD)
4007 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~ignore_masks);
4008 else if (TARGET_DFP)
4009 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~ignore_masks);
4010 else if (TARGET_CMPB)
4011 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~ignore_masks);
4012 else if (TARGET_FPRND)
4013 rs6000_isa_flags |= (ISA_2_4_MASKS & ~ignore_masks);
4014 else if (TARGET_POPCNTB)
4015 rs6000_isa_flags |= (ISA_2_2_MASKS & ~ignore_masks);
4016 else if (TARGET_ALTIVEC)
4017 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~ignore_masks);
4019 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
4021 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
4022 error ("%qs requires %qs", "-mcrypto", "-maltivec");
4023 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
4026 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
4028 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
4029 error ("%qs requires %qs", "-mdirect-move", "-mvsx");
4030 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
4033 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
4035 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4036 error ("%qs requires %qs", "-mpower8-vector", "-maltivec");
4037 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4040 if (TARGET_P8_VECTOR && !TARGET_VSX)
4042 if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4043 && (rs6000_isa_flags_explicit & OPTION_MASK_VSX))
4044 error ("%qs requires %qs", "-mpower8-vector", "-mvsx");
4045 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR) == 0)
4047 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
4048 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
4049 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4053 /* OPTION_MASK_P8_VECTOR is explicit, and OPTION_MASK_VSX is
4055 rs6000_isa_flags |= OPTION_MASK_VSX;
4056 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
4060 if (TARGET_DFP && !TARGET_HARD_FLOAT)
4062 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
4063 error ("%qs requires %qs", "-mhard-dfp", "-mhard-float");
4064 rs6000_isa_flags &= ~OPTION_MASK_DFP;
4067 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4068 silently turn off quad memory mode. */
4069 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
4071 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4072 warning (0, N_("%<-mquad-memory%> requires 64-bit mode"));
4074 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
4075 warning (0, N_("%<-mquad-memory-atomic%> requires 64-bit mode"));
4077 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
4078 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
4081 /* Non-atomic quad memory load/store are disabled for little endian, since
4082 the words are reversed, but atomic operations can still be done by
4083 swapping the words. */
4084 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
4086 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
4087 warning (0, N_("%<-mquad-memory%> is not available in little endian "
4090 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
4093 /* Assume if the user asked for normal quad memory instructions, they want
4094 the atomic versions as well, unless they explicity told us not to use quad
4095 word atomic instructions. */
4096 if (TARGET_QUAD_MEMORY
4097 && !TARGET_QUAD_MEMORY_ATOMIC
4098 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
4099 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
4101 /* If we can shrink-wrap the TOC register save separately, then use
4102 -msave-toc-indirect unless explicitly disabled. */
4103 if ((rs6000_isa_flags_explicit & OPTION_MASK_SAVE_TOC_INDIRECT) == 0
4104 && flag_shrink_wrap_separate
4105 && optimize_function_for_speed_p (cfun))
4106 rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
4108 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4109 generating power8 instructions. Power9 does not optimize power8 fusion
4111 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
4113 if (processor_target_table[tune_index].processor == PROCESSOR_POWER8)
4114 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4116 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4119 /* Setting additional fusion flags turns on base fusion. */
4120 if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN)
4122 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
4124 if (TARGET_P8_FUSION_SIGN)
4125 error ("%qs requires %qs", "-mpower8-fusion-sign",
4128 rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
4131 rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
4134 /* Power8 does not fuse sign extended loads with the addis. If we are
4135 optimizing at high levels for speed, convert a sign extended load into a
4136 zero extending load, and an explicit sign extension. */
4137 if (TARGET_P8_FUSION
4138 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
4139 && optimize_function_for_speed_p (cfun)
4141 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
4143 /* ISA 3.0 vector instructions include ISA 2.07. */
4144 if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
4146 /* We prefer to not mention undocumented options in
4147 error messages. However, if users have managed to select
4148 power9-vector without selecting power8-vector, they
4149 already know about undocumented flags. */
4150 if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) &&
4151 (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR))
4152 error ("%qs requires %qs", "-mpower9-vector", "-mpower8-vector");
4153 else if ((rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR) == 0)
4155 rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
4156 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
4157 rs6000_isa_flags_explicit |= OPTION_MASK_P9_VECTOR;
4161 /* OPTION_MASK_P9_VECTOR is explicit and
4162 OPTION_MASK_P8_VECTOR is not explicit. */
4163 rs6000_isa_flags |= OPTION_MASK_P8_VECTOR;
4164 rs6000_isa_flags_explicit |= OPTION_MASK_P8_VECTOR;
4168 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4169 support. If we only have ISA 2.06 support, and the user did not specify
4170 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4171 but we don't enable the full vectorization support */
4172 if (TARGET_ALLOW_MOVMISALIGN == -1 && TARGET_P8_VECTOR && TARGET_DIRECT_MOVE)
4173 TARGET_ALLOW_MOVMISALIGN = 1;
4175 else if (TARGET_ALLOW_MOVMISALIGN && !TARGET_VSX)
4177 if (TARGET_ALLOW_MOVMISALIGN > 0
4178 && global_options_set.x_TARGET_ALLOW_MOVMISALIGN)
4179 error ("%qs requires %qs", "-mallow-movmisalign", "-mvsx");
4181 TARGET_ALLOW_MOVMISALIGN = 0;
4184 /* Determine when unaligned vector accesses are permitted, and when
4185 they are preferred over masked Altivec loads. Note that if
4186 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4187 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4189 if (TARGET_EFFICIENT_UNALIGNED_VSX)
4193 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4194 error ("%qs requires %qs", "-mefficient-unaligned-vsx", "-mvsx");
4196 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4199 else if (!TARGET_ALLOW_MOVMISALIGN)
4201 if (rs6000_isa_flags_explicit & OPTION_MASK_EFFICIENT_UNALIGNED_VSX)
4202 error ("%qs requires %qs", "-munefficient-unaligned-vsx",
4203 "-mallow-movmisalign");
4205 rs6000_isa_flags &= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX;
4209 /* Use long double size to select the appropriate long double. We use
4210 TYPE_PRECISION to differentiate the 3 different long double types. We map
4211 128 into the precision used for TFmode. */
4212 int default_long_double_size = (RS6000_DEFAULT_LONG_DOUBLE_SIZE == 64
4214 : FLOAT_PRECISION_TFmode);
4216 /* Set long double size before the IEEE 128-bit tests. */
4217 if (!global_options_set.x_rs6000_long_double_type_size)
4219 if (main_target_opt != NULL
4220 && (main_target_opt->x_rs6000_long_double_type_size
4221 != default_long_double_size))
4222 error ("target attribute or pragma changes %<long double%> size");
4224 rs6000_long_double_type_size = default_long_double_size;
4226 else if (rs6000_long_double_type_size == 128)
4227 rs6000_long_double_type_size = FLOAT_PRECISION_TFmode;
4228 else if (global_options_set.x_rs6000_ieeequad)
4230 if (global_options.x_rs6000_ieeequad)
4231 error ("%qs requires %qs", "-mabi=ieeelongdouble", "-mlong-double-128");
4233 error ("%qs requires %qs", "-mabi=ibmlongdouble", "-mlong-double-128");
4236 /* Set -mabi=ieeelongdouble on some old targets. In the future, power server
4237 systems will also set long double to be IEEE 128-bit. AIX and Darwin
4238 explicitly redefine TARGET_IEEEQUAD and TARGET_IEEEQUAD_DEFAULT to 0, so
4239 those systems will not pick up this default. Warn if the user changes the
4240 default unless -Wno-psabi. */
4241 if (!global_options_set.x_rs6000_ieeequad)
4242 rs6000_ieeequad = TARGET_IEEEQUAD_DEFAULT;
4246 if (global_options.x_rs6000_ieeequad
4247 && (!TARGET_POPCNTD || !TARGET_VSX))
4248 error ("%qs requires full ISA 2.06 support", "-mabi=ieeelongdouble");
4250 if (rs6000_ieeequad != TARGET_IEEEQUAD_DEFAULT && TARGET_LONG_DOUBLE_128)
4252 static bool warned_change_long_double;
4253 if (!warned_change_long_double)
4255 warned_change_long_double = true;
4256 if (TARGET_IEEEQUAD)
4257 warning (OPT_Wpsabi, "Using IEEE extended precision "
4260 warning (OPT_Wpsabi, "Using IBM extended precision "
4266 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4267 sytems. In GCC 7, we would enable the the IEEE 128-bit floating point
4268 infrastructure (-mfloat128-type) but not enable the actual __float128 type
4269 unless the user used the explicit -mfloat128. In GCC 8, we enable both
4270 the keyword as well as the type. */
4271 TARGET_FLOAT128_TYPE = TARGET_FLOAT128_ENABLE_TYPE && TARGET_VSX;
4273 /* IEEE 128-bit floating point requires VSX support. */
4274 if (TARGET_FLOAT128_KEYWORD)
4278 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) != 0)
4279 error ("%qs requires VSX support", "%<-mfloat128%>");
4281 TARGET_FLOAT128_TYPE = 0;
4282 rs6000_isa_flags &= ~(OPTION_MASK_FLOAT128_KEYWORD
4283 | OPTION_MASK_FLOAT128_HW);
4285 else if (!TARGET_FLOAT128_TYPE)
4287 TARGET_FLOAT128_TYPE = 1;
4288 warning (0, "The %<-mfloat128%> option may not be fully supported");
4292 /* Enable the __float128 keyword under Linux by default. */
4293 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_KEYWORD
4294 && (rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_KEYWORD) == 0)
4295 rs6000_isa_flags |= OPTION_MASK_FLOAT128_KEYWORD;
4297 /* If we have are supporting the float128 type and full ISA 3.0 support,
4298 enable -mfloat128-hardware by default. However, don't enable the
4299 __float128 keyword if it was explicitly turned off. 64-bit mode is needed
4300 because sometimes the compiler wants to put things in an integer
4301 container, and if we don't have __int128 support, it is impossible. */
4302 if (TARGET_FLOAT128_TYPE && !TARGET_FLOAT128_HW && TARGET_64BIT
4303 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) == ISA_3_0_MASKS_IEEE
4304 && !(rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW))
4305 rs6000_isa_flags |= OPTION_MASK_FLOAT128_HW;
4307 if (TARGET_FLOAT128_HW
4308 && (rs6000_isa_flags & ISA_3_0_MASKS_IEEE) != ISA_3_0_MASKS_IEEE)
4310 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4311 error ("%qs requires full ISA 3.0 support", "%<-mfloat128-hardware%>");
4313 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4316 if (TARGET_FLOAT128_HW && !TARGET_64BIT)
4318 if ((rs6000_isa_flags_explicit & OPTION_MASK_FLOAT128_HW) != 0)
4319 error ("%qs requires %qs", "%<-mfloat128-hardware%>", "-m64");
4321 rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
4324 /* Print the options after updating the defaults. */
4325 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4326 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
4328 /* E500mc does "better" if we inline more aggressively. Respect the
4329 user's opinion, though. */
4330 if (rs6000_block_move_inline_limit == 0
4331 && (rs6000_tune == PROCESSOR_PPCE500MC
4332 || rs6000_tune == PROCESSOR_PPCE500MC64
4333 || rs6000_tune == PROCESSOR_PPCE5500
4334 || rs6000_tune == PROCESSOR_PPCE6500))
4335 rs6000_block_move_inline_limit = 128;
4337 /* store_one_arg depends on expand_block_move to handle at least the
4338 size of reg_parm_stack_space. */
4339 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
4340 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
4344 /* If the appropriate debug option is enabled, replace the target hooks
4345 with debug versions that call the real version and then prints
4346 debugging information. */
4347 if (TARGET_DEBUG_COST)
4349 targetm.rtx_costs = rs6000_debug_rtx_costs;
4350 targetm.address_cost = rs6000_debug_address_cost;
4351 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
4354 if (TARGET_DEBUG_ADDR)
4356 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
4357 targetm.legitimize_address = rs6000_debug_legitimize_address;
4358 rs6000_secondary_reload_class_ptr
4359 = rs6000_debug_secondary_reload_class;
4360 targetm.secondary_memory_needed
4361 = rs6000_debug_secondary_memory_needed;
4362 targetm.can_change_mode_class
4363 = rs6000_debug_can_change_mode_class;
4364 rs6000_preferred_reload_class_ptr
4365 = rs6000_debug_preferred_reload_class;
4366 rs6000_mode_dependent_address_ptr
4367 = rs6000_debug_mode_dependent_address;
4370 if (rs6000_veclibabi_name)
4372 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
4373 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
4376 error ("unknown vectorization library ABI type (%qs) for "
4377 "%qs switch", rs6000_veclibabi_name, "-mveclibabi=");
4383 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4384 target attribute or pragma which automatically enables both options,
4385 unless the altivec ABI was set. This is set by default for 64-bit, but
4387 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4389 TARGET_FLOAT128_TYPE = 0;
4390 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC
4391 | OPTION_MASK_FLOAT128_KEYWORD)
4392 & ~rs6000_isa_flags_explicit);
4395 /* Enable Altivec ABI for AIX -maltivec. */
4396 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
4398 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
4399 error ("target attribute or pragma changes AltiVec ABI");
4401 rs6000_altivec_abi = 1;
4404 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4405 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4406 be explicitly overridden in either case. */
4409 if (!global_options_set.x_rs6000_altivec_abi
4410 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
4412 if (main_target_opt != NULL &&
4413 !main_target_opt->x_rs6000_altivec_abi)
4414 error ("target attribute or pragma changes AltiVec ABI");
4416 rs6000_altivec_abi = 1;
4420 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4421 So far, the only darwin64 targets are also MACH-O. */
4423 && DEFAULT_ABI == ABI_DARWIN
4426 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
4427 error ("target attribute or pragma changes darwin64 ABI");
4430 rs6000_darwin64_abi = 1;
4431 /* Default to natural alignment, for better performance. */
4432 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
4436 /* Place FP constants in the constant pool instead of TOC
4437 if section anchors enabled. */
4438 if (flag_section_anchors
4439 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
4440 TARGET_NO_FP_IN_TOC = 1;
4442 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4443 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
4445 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4446 SUBTARGET_OVERRIDE_OPTIONS;
4448 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4449 SUBSUBTARGET_OVERRIDE_OPTIONS;
4451 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4452 SUB3TARGET_OVERRIDE_OPTIONS;
4455 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
4456 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
4458 rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
4459 && rs6000_tune != PROCESSOR_POWER5
4460 && rs6000_tune != PROCESSOR_POWER6
4461 && rs6000_tune != PROCESSOR_POWER7
4462 && rs6000_tune != PROCESSOR_POWER8
4463 && rs6000_tune != PROCESSOR_POWER9
4464 && rs6000_tune != PROCESSOR_PPCA2
4465 && rs6000_tune != PROCESSOR_CELL
4466 && rs6000_tune != PROCESSOR_PPC476);
4467 rs6000_sched_groups = (rs6000_tune == PROCESSOR_POWER4
4468 || rs6000_tune == PROCESSOR_POWER5
4469 || rs6000_tune == PROCESSOR_POWER7
4470 || rs6000_tune == PROCESSOR_POWER8);
4471 rs6000_align_branch_targets = (rs6000_tune == PROCESSOR_POWER4
4472 || rs6000_tune == PROCESSOR_POWER5
4473 || rs6000_tune == PROCESSOR_POWER6
4474 || rs6000_tune == PROCESSOR_POWER7
4475 || rs6000_tune == PROCESSOR_POWER8
4476 || rs6000_tune == PROCESSOR_POWER9
4477 || rs6000_tune == PROCESSOR_PPCE500MC
4478 || rs6000_tune == PROCESSOR_PPCE500MC64
4479 || rs6000_tune == PROCESSOR_PPCE5500
4480 || rs6000_tune == PROCESSOR_PPCE6500);
4482 /* Allow debug switches to override the above settings. These are set to -1
4483 in rs6000.opt to indicate the user hasn't directly set the switch. */
4484 if (TARGET_ALWAYS_HINT >= 0)
4485 rs6000_always_hint = TARGET_ALWAYS_HINT;
4487 if (TARGET_SCHED_GROUPS >= 0)
4488 rs6000_sched_groups = TARGET_SCHED_GROUPS;
4490 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
4491 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
4493 rs6000_sched_restricted_insns_priority
4494 = (rs6000_sched_groups ? 1 : 0);
4496 /* Handle -msched-costly-dep option. */
4497 rs6000_sched_costly_dep
4498 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
4500 if (rs6000_sched_costly_dep_str)
4502 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
4503 rs6000_sched_costly_dep = no_dep_costly;
4504 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
4505 rs6000_sched_costly_dep = all_deps_costly;
4506 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
4507 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
4508 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
4509 rs6000_sched_costly_dep = store_to_load_dep_costly;
4511 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
4512 atoi (rs6000_sched_costly_dep_str));
4515 /* Handle -minsert-sched-nops option. */
4516 rs6000_sched_insert_nops
4517 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
4519 if (rs6000_sched_insert_nops_str)
4521 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
4522 rs6000_sched_insert_nops = sched_finish_none;
4523 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
4524 rs6000_sched_insert_nops = sched_finish_pad_groups;
4525 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
4526 rs6000_sched_insert_nops = sched_finish_regroup_exact;
4528 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
4529 atoi (rs6000_sched_insert_nops_str));
4532 /* Handle stack protector */
4533 if (!global_options_set.x_rs6000_stack_protector_guard)
4534 #ifdef TARGET_THREAD_SSP_OFFSET
4535 rs6000_stack_protector_guard = SSP_TLS;
4537 rs6000_stack_protector_guard = SSP_GLOBAL;
4540 #ifdef TARGET_THREAD_SSP_OFFSET
4541 rs6000_stack_protector_guard_offset = TARGET_THREAD_SSP_OFFSET;
4542 rs6000_stack_protector_guard_reg = TARGET_64BIT ? 13 : 2;
4545 if (global_options_set.x_rs6000_stack_protector_guard_offset_str)
4548 const char *str = rs6000_stack_protector_guard_offset_str;
4551 long offset = strtol (str, &endp, 0);
4552 if (!*str || *endp || errno)
4553 error ("%qs is not a valid number in %qs", str,
4554 "-mstack-protector-guard-offset=");
4556 if (!IN_RANGE (offset, -0x8000, 0x7fff)
4557 || (TARGET_64BIT && (offset & 3)))
4558 error ("%qs is not a valid offset in %qs", str,
4559 "-mstack-protector-guard-offset=");
4561 rs6000_stack_protector_guard_offset = offset;
4564 if (global_options_set.x_rs6000_stack_protector_guard_reg_str)
4566 const char *str = rs6000_stack_protector_guard_reg_str;
4567 int reg = decode_reg_name (str);
4569 if (!IN_RANGE (reg, 1, 31))
4570 error ("%qs is not a valid base register in %qs", str,
4571 "-mstack-protector-guard-reg=");
4573 rs6000_stack_protector_guard_reg = reg;
4576 if (rs6000_stack_protector_guard == SSP_TLS
4577 && !IN_RANGE (rs6000_stack_protector_guard_reg, 1, 31))
4578 error ("%qs needs a valid base register", "-mstack-protector-guard=tls");
4582 #ifdef TARGET_REGNAMES
4583 /* If the user desires alternate register names, copy in the
4584 alternate names now. */
4585 if (TARGET_REGNAMES)
4586 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
4589 /* Set aix_struct_return last, after the ABI is determined.
4590 If -maix-struct-return or -msvr4-struct-return was explicitly
4591 used, don't override with the ABI default. */
4592 if (!global_options_set.x_aix_struct_return)
4593 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
4596 /* IBM XL compiler defaults to unsigned bitfields. */
4597 if (TARGET_XL_COMPAT)
4598 flag_signed_bitfields = 0;
4601 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
4602 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
4604 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
4606 /* We can only guarantee the availability of DI pseudo-ops when
4607 assembling for 64-bit targets. */
4610 targetm.asm_out.aligned_op.di = NULL;
4611 targetm.asm_out.unaligned_op.di = NULL;
4615 /* Set branch target alignment, if not optimizing for size. */
4618 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4619 aligned 8byte to avoid misprediction by the branch predictor. */
4620 if (rs6000_tune == PROCESSOR_TITAN
4621 || rs6000_tune == PROCESSOR_CELL)
4623 if (flag_align_functions && !str_align_functions)
4624 str_align_functions = "8";
4625 if (flag_align_jumps && !str_align_jumps)
4626 str_align_jumps = "8";
4627 if (flag_align_loops && !str_align_loops)
4628 str_align_loops = "8";
4630 if (rs6000_align_branch_targets)
4632 if (flag_align_functions && !str_align_functions)
4633 str_align_functions = "16";
4634 if (flag_align_jumps && !str_align_jumps)
4635 str_align_jumps = "16";
4636 if (flag_align_loops && !str_align_loops)
4638 can_override_loop_align = 1;
4639 str_align_loops = "16";
4643 if (flag_align_jumps && !str_align_jumps)
4644 str_align_jumps = "16";
4645 if (flag_align_loops && !str_align_loops)
4646 str_align_loops = "16";
4649 /* Arrange to save and restore machine status around nested functions. */
4650 init_machine_status = rs6000_init_machine_status;
4652 /* We should always be splitting complex arguments, but we can't break
4653 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4654 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
4655 targetm.calls.split_complex_arg = NULL;
4657 /* The AIX and ELFv1 ABIs define standard function descriptors. */
4658 if (DEFAULT_ABI == ABI_AIX)
4659 targetm.calls.custom_function_descriptors = 0;
4662 /* Initialize rs6000_cost with the appropriate target costs. */
4664 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
4666 switch (rs6000_tune)
4668 case PROCESSOR_RS64A:
4669 rs6000_cost = &rs64a_cost;
4672 case PROCESSOR_MPCCORE:
4673 rs6000_cost = &mpccore_cost;
4676 case PROCESSOR_PPC403:
4677 rs6000_cost = &ppc403_cost;
4680 case PROCESSOR_PPC405:
4681 rs6000_cost = &ppc405_cost;
4684 case PROCESSOR_PPC440:
4685 rs6000_cost = &ppc440_cost;
4688 case PROCESSOR_PPC476:
4689 rs6000_cost = &ppc476_cost;
4692 case PROCESSOR_PPC601:
4693 rs6000_cost = &ppc601_cost;
4696 case PROCESSOR_PPC603:
4697 rs6000_cost = &ppc603_cost;
4700 case PROCESSOR_PPC604:
4701 rs6000_cost = &ppc604_cost;
4704 case PROCESSOR_PPC604e:
4705 rs6000_cost = &ppc604e_cost;
4708 case PROCESSOR_PPC620:
4709 rs6000_cost = &ppc620_cost;
4712 case PROCESSOR_PPC630:
4713 rs6000_cost = &ppc630_cost;
4716 case PROCESSOR_CELL:
4717 rs6000_cost = &ppccell_cost;
4720 case PROCESSOR_PPC750:
4721 case PROCESSOR_PPC7400:
4722 rs6000_cost = &ppc750_cost;
4725 case PROCESSOR_PPC7450:
4726 rs6000_cost = &ppc7450_cost;
4729 case PROCESSOR_PPC8540:
4730 case PROCESSOR_PPC8548:
4731 rs6000_cost = &ppc8540_cost;
4734 case PROCESSOR_PPCE300C2:
4735 case PROCESSOR_PPCE300C3:
4736 rs6000_cost = &ppce300c2c3_cost;
4739 case PROCESSOR_PPCE500MC:
4740 rs6000_cost = &ppce500mc_cost;
4743 case PROCESSOR_PPCE500MC64:
4744 rs6000_cost = &ppce500mc64_cost;
4747 case PROCESSOR_PPCE5500:
4748 rs6000_cost = &ppce5500_cost;
4751 case PROCESSOR_PPCE6500:
4752 rs6000_cost = &ppce6500_cost;
4755 case PROCESSOR_TITAN:
4756 rs6000_cost = &titan_cost;
4759 case PROCESSOR_POWER4:
4760 case PROCESSOR_POWER5:
4761 rs6000_cost = &power4_cost;
4764 case PROCESSOR_POWER6:
4765 rs6000_cost = &power6_cost;
4768 case PROCESSOR_POWER7:
4769 rs6000_cost = &power7_cost;
4772 case PROCESSOR_POWER8:
4773 rs6000_cost = &power8_cost;
4776 case PROCESSOR_POWER9:
4777 rs6000_cost = &power9_cost;
4780 case PROCESSOR_PPCA2:
4781 rs6000_cost = &ppca2_cost;
4790 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
4791 rs6000_cost->simultaneous_prefetches,
4792 global_options.x_param_values,
4793 global_options_set.x_param_values);
4794 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
4795 global_options.x_param_values,
4796 global_options_set.x_param_values);
4797 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
4798 rs6000_cost->cache_line_size,
4799 global_options.x_param_values,
4800 global_options_set.x_param_values);
4801 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
4802 global_options.x_param_values,
4803 global_options_set.x_param_values);
4805 /* Increase loop peeling limits based on performance analysis. */
4806 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
4807 global_options.x_param_values,
4808 global_options_set.x_param_values);
4809 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
4810 global_options.x_param_values,
4811 global_options_set.x_param_values);
4813 /* Use the 'model' -fsched-pressure algorithm by default. */
4814 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM,
4815 SCHED_PRESSURE_MODEL,
4816 global_options.x_param_values,
4817 global_options_set.x_param_values);
4819 /* If using typedef char *va_list, signal that
4820 __builtin_va_start (&ap, 0) can be optimized to
4821 ap = __builtin_next_arg (0). */
4822 if (DEFAULT_ABI != ABI_V4)
4823 targetm.expand_builtin_va_start = NULL;
4826 /* If not explicitly specified via option, decide whether to generate indexed
4827 load/store instructions. A value of -1 indicates that the
4828 initial value of this variable has not been overwritten. During
4829 compilation, TARGET_AVOID_XFORM is either 0 or 1. */
4830 if (TARGET_AVOID_XFORM == -1)
4831 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4832 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4833 need indexed accesses and the type used is the scalar type of the element
4834 being loaded or stored. */
4835 TARGET_AVOID_XFORM = (rs6000_tune == PROCESSOR_POWER6 && TARGET_CMPB
4836 && !TARGET_ALTIVEC);
4838 /* Set the -mrecip options. */
4839 if (rs6000_recip_name)
4841 char *p = ASTRDUP (rs6000_recip_name);
4843 unsigned int mask, i;
4846 while ((q = strtok (p, ",")) != NULL)
4857 if (!strcmp (q, "default"))
4858 mask = ((TARGET_RECIP_PRECISION)
4859 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
4862 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
4863 if (!strcmp (q, recip_options[i].string))
4865 mask = recip_options[i].mask;
4869 if (i == ARRAY_SIZE (recip_options))
4871 error ("unknown option for %<%s=%s%>", "-mrecip", q);
4879 rs6000_recip_control &= ~mask;
4881 rs6000_recip_control |= mask;
4885 /* Set the builtin mask of the various options used that could affect which
4886 builtins were used. In the past we used target_flags, but we've run out
4887 of bits, and some options are no longer in target_flags. */
4888 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
4889 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
4890 rs6000_print_builtin_options (stderr, 0, "builtin mask",
4891 rs6000_builtin_mask);
4893 /* Initialize all of the registers. */
4894 rs6000_init_hard_regno_mode_ok (global_init_p);
4896 /* Save the initial options in case the user does function specific options */
4898 target_option_default_node = target_option_current_node
4899 = build_target_option_node (&global_options);
4901 /* If not explicitly specified via option, decide whether to generate the
4902 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4903 if (TARGET_LINK_STACK == -1)
4904 SET_TARGET_LINK_STACK (rs6000_tune == PROCESSOR_PPC476 && flag_pic);
4906 /* Deprecate use of -mno-speculate-indirect-jumps. */
4907 if (!rs6000_speculate_indirect_jumps)
4908 warning (0, "%qs is deprecated and not recommended in any circumstances",
4909 "-mno-speculate-indirect-jumps");
4914 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4915 define the target cpu type. */
4918 rs6000_option_override (void)
4920 (void) rs6000_option_override_internal (true);
4924 /* Implement targetm.vectorize.builtin_mask_for_load. */
4926 rs6000_builtin_mask_for_load (void)
4928 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
4929 if ((TARGET_ALTIVEC && !TARGET_VSX)
4930 || (TARGET_VSX && !TARGET_EFFICIENT_UNALIGNED_VSX))
4931 return altivec_builtin_mask_for_load;
4936 /* Implement LOOP_ALIGN. */
4938 rs6000_loop_align (rtx label)
4943 /* Don't override loop alignment if -falign-loops was specified. */
4944 if (!can_override_loop_align)
4947 bb = BLOCK_FOR_INSN (label);
4948 ninsns = num_loop_insns(bb->loop_father);
4950 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4951 if (ninsns > 4 && ninsns <= 8
4952 && (rs6000_tune == PROCESSOR_POWER4
4953 || rs6000_tune == PROCESSOR_POWER5
4954 || rs6000_tune == PROCESSOR_POWER6
4955 || rs6000_tune == PROCESSOR_POWER7
4956 || rs6000_tune == PROCESSOR_POWER8))
4957 return align_flags (5);
4962 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4963 after applying N number of iterations. This routine does not determine
4964 how may iterations are required to reach desired alignment. */
4967 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
4974 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
4977 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
4987 /* Assuming that all other types are naturally aligned. CHECKME! */
4992 /* Return true if the vector misalignment factor is supported by the
4995 rs6000_builtin_support_vector_misalignment (machine_mode mode,
5002 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5005 /* Return if movmisalign pattern is not supported for this mode. */
5006 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
5009 if (misalignment == -1)
5011 /* Misalignment factor is unknown at compile time but we know
5012 it's word aligned. */
5013 if (rs6000_vector_alignment_reachable (type, is_packed))
5015 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
5017 if (element_size == 64 || element_size == 32)
5024 /* VSX supports word-aligned vector. */
5025 if (misalignment % 4 == 0)
5031 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5033 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
5034 tree vectype, int misalign)
5039 switch (type_of_cost)
5049 case cond_branch_not_taken:
5058 case vec_promote_demote:
5064 case cond_branch_taken:
5067 case unaligned_load:
5068 case vector_gather_load:
5069 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5072 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5074 elements = TYPE_VECTOR_SUBPARTS (vectype);
5076 /* Double word aligned. */
5084 /* Double word aligned. */
5088 /* Unknown misalignment. */
5101 /* Misaligned loads are not supported. */
5106 case unaligned_store:
5107 case vector_scatter_store:
5108 if (TARGET_EFFICIENT_UNALIGNED_VSX)
5111 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
5113 elements = TYPE_VECTOR_SUBPARTS (vectype);
5115 /* Double word aligned. */
5123 /* Double word aligned. */
5127 /* Unknown misalignment. */
5140 /* Misaligned stores are not supported. */
5146 /* This is a rough approximation assuming non-constant elements
5147 constructed into a vector via element insertion. FIXME:
5148 vec_construct is not granular enough for uniformly good
5149 decisions. If the initialization is a splat, this is
5150 cheaper than we estimate. Improve this someday. */
5151 elem_type = TREE_TYPE (vectype);
5152 /* 32-bit vectors loaded into registers are stored as double
5153 precision, so we need 2 permutes, 2 converts, and 1 merge
5154 to construct a vector of short floats from them. */
5155 if (SCALAR_FLOAT_TYPE_P (elem_type)
5156 && TYPE_PRECISION (elem_type) == 32)
5158 /* On POWER9, integer vector types are built up in GPRs and then
5159 use a direct move (2 cycles). For POWER8 this is even worse,
5160 as we need two direct moves and a merge, and the direct moves
5162 else if (INTEGRAL_TYPE_P (elem_type))
5164 if (TARGET_P9_VECTOR)
5165 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 2;
5167 return TYPE_VECTOR_SUBPARTS (vectype) - 1 + 5;
5170 /* V2DFmode doesn't need a direct move. */
5178 /* Implement targetm.vectorize.preferred_simd_mode. */
5181 rs6000_preferred_simd_mode (scalar_mode mode)
5190 if (TARGET_ALTIVEC || TARGET_VSX)
5210 typedef struct _rs6000_cost_data
5212 struct loop *loop_info;
5216 /* Test for likely overcommitment of vector hardware resources. If a
5217 loop iteration is relatively large, and too large a percentage of
5218 instructions in the loop are vectorized, the cost model may not
5219 adequately reflect delays from unavailable vector resources.
5220 Penalize the loop body cost for this case. */
5223 rs6000_density_test (rs6000_cost_data *data)
5225 const int DENSITY_PCT_THRESHOLD = 85;
5226 const int DENSITY_SIZE_THRESHOLD = 70;
5227 const int DENSITY_PENALTY = 10;
5228 struct loop *loop = data->loop_info;
5229 basic_block *bbs = get_loop_body (loop);
5230 int nbbs = loop->num_nodes;
5231 loop_vec_info loop_vinfo = loop_vec_info_for_loop (data->loop_info);
5232 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
5235 for (i = 0; i < nbbs; i++)
5237 basic_block bb = bbs[i];
5238 gimple_stmt_iterator gsi;
5240 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
5242 gimple *stmt = gsi_stmt (gsi);
5243 stmt_vec_info stmt_info = loop_vinfo->lookup_stmt (stmt);
5245 if (!STMT_VINFO_RELEVANT_P (stmt_info)
5246 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
5252 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
5254 if (density_pct > DENSITY_PCT_THRESHOLD
5255 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
5257 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
5258 if (dump_enabled_p ())
5259 dump_printf_loc (MSG_NOTE, vect_location,
5260 "density %d%%, cost %d exceeds threshold, penalizing "
5261 "loop body cost by %d%%", density_pct,
5262 vec_cost + not_vec_cost, DENSITY_PENALTY);
5266 /* Implement targetm.vectorize.init_cost. */
5268 /* For each vectorized loop, this var holds TRUE iff a non-memory vector
5269 instruction is needed by the vectorization. */
5270 static bool rs6000_vect_nonmem;
5273 rs6000_init_cost (struct loop *loop_info)
5275 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
5276 data->loop_info = loop_info;
5277 data->cost[vect_prologue] = 0;
5278 data->cost[vect_body] = 0;
5279 data->cost[vect_epilogue] = 0;
5280 rs6000_vect_nonmem = false;
5284 /* Implement targetm.vectorize.add_stmt_cost. */
5287 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
5288 struct _stmt_vec_info *stmt_info, int misalign,
5289 enum vect_cost_model_location where)
5291 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5292 unsigned retval = 0;
5294 if (flag_vect_cost_model)
5296 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
5297 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
5299 /* Statements in an inner loop relative to the loop being
5300 vectorized are weighted more heavily. The value here is
5301 arbitrary and could potentially be improved with analysis. */
5302 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
5303 count *= 50; /* FIXME. */
5305 retval = (unsigned) (count * stmt_cost);
5306 cost_data->cost[where] += retval;
5308 /* Check whether we're doing something other than just a copy loop.
5309 Not all such loops may be profitably vectorized; see
5310 rs6000_finish_cost. */
5311 if ((kind == vec_to_scalar || kind == vec_perm
5312 || kind == vec_promote_demote || kind == vec_construct
5313 || kind == scalar_to_vec)
5314 || (where == vect_body && kind == vector_stmt))
5315 rs6000_vect_nonmem = true;
5321 /* Implement targetm.vectorize.finish_cost. */
5324 rs6000_finish_cost (void *data, unsigned *prologue_cost,
5325 unsigned *body_cost, unsigned *epilogue_cost)
5327 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
5329 if (cost_data->loop_info)
5330 rs6000_density_test (cost_data);
5332 /* Don't vectorize minimum-vectorization-factor, simple copy loops
5333 that require versioning for any reason. The vectorization is at
5334 best a wash inside the loop, and the versioning checks make
5335 profitability highly unlikely and potentially quite harmful. */
5336 if (cost_data->loop_info)
5338 loop_vec_info vec_info = loop_vec_info_for_loop (cost_data->loop_info);
5339 if (!rs6000_vect_nonmem
5340 && LOOP_VINFO_VECT_FACTOR (vec_info) == 2
5341 && LOOP_REQUIRES_VERSIONING (vec_info))
5342 cost_data->cost[vect_body] += 10000;
5345 *prologue_cost = cost_data->cost[vect_prologue];
5346 *body_cost = cost_data->cost[vect_body];
5347 *epilogue_cost = cost_data->cost[vect_epilogue];
5350 /* Implement targetm.vectorize.destroy_cost_data. */
5353 rs6000_destroy_cost_data (void *data)
5358 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5359 library with vectorized intrinsics. */
5362 rs6000_builtin_vectorized_libmass (combined_fn fn, tree type_out,
5366 const char *suffix = NULL;
5367 tree fntype, new_fndecl, bdecl = NULL_TREE;
5370 machine_mode el_mode, in_mode;
5373 /* Libmass is suitable for unsafe math only as it does not correctly support
5374 parts of IEEE with the required precision such as denormals. Only support
5375 it if we have VSX to use the simd d2 or f4 functions.
5376 XXX: Add variable length support. */
5377 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
5380 el_mode = TYPE_MODE (TREE_TYPE (type_out));
5381 n = TYPE_VECTOR_SUBPARTS (type_out);
5382 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5383 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5384 if (el_mode != in_mode
5420 if (el_mode == DFmode && n == 2)
5422 bdecl = mathfn_built_in (double_type_node, fn);
5423 suffix = "d2"; /* pow -> powd2 */
5425 else if (el_mode == SFmode && n == 4)
5427 bdecl = mathfn_built_in (float_type_node, fn);
5428 suffix = "4"; /* powf -> powf4 */
5440 gcc_assert (suffix != NULL);
5441 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
5445 strcpy (name, bname + sizeof ("__builtin_") - 1);
5446 strcat (name, suffix);
5449 fntype = build_function_type_list (type_out, type_in, NULL);
5450 else if (n_args == 2)
5451 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
5455 /* Build a function declaration for the vectorized function. */
5456 new_fndecl = build_decl (BUILTINS_LOCATION,
5457 FUNCTION_DECL, get_identifier (name), fntype);
5458 TREE_PUBLIC (new_fndecl) = 1;
5459 DECL_EXTERNAL (new_fndecl) = 1;
5460 DECL_IS_NOVOPS (new_fndecl) = 1;
5461 TREE_READONLY (new_fndecl) = 1;
5466 /* Returns a function decl for a vectorized version of the builtin function
5467 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5468 if it is not available. */
5471 rs6000_builtin_vectorized_function (unsigned int fn, tree type_out,
5474 machine_mode in_mode, out_mode;
5477 if (TARGET_DEBUG_BUILTIN)
5478 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5479 combined_fn_name (combined_fn (fn)),
5480 GET_MODE_NAME (TYPE_MODE (type_out)),
5481 GET_MODE_NAME (TYPE_MODE (type_in)));
5483 if (TREE_CODE (type_out) != VECTOR_TYPE
5484 || TREE_CODE (type_in) != VECTOR_TYPE)
5487 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5488 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5489 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5490 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5495 if (VECTOR_UNIT_VSX_P (V2DFmode)
5496 && out_mode == DFmode && out_n == 2
5497 && in_mode == DFmode && in_n == 2)
5498 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
5499 if (VECTOR_UNIT_VSX_P (V4SFmode)
5500 && out_mode == SFmode && out_n == 4
5501 && in_mode == SFmode && in_n == 4)
5502 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
5503 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5504 && out_mode == SFmode && out_n == 4
5505 && in_mode == SFmode && in_n == 4)
5506 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
5509 if (VECTOR_UNIT_VSX_P (V2DFmode)
5510 && out_mode == DFmode && out_n == 2
5511 && in_mode == DFmode && in_n == 2)
5512 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
5513 if (VECTOR_UNIT_VSX_P (V4SFmode)
5514 && out_mode == SFmode && out_n == 4
5515 && in_mode == SFmode && in_n == 4)
5516 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
5517 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5518 && out_mode == SFmode && out_n == 4
5519 && in_mode == SFmode && in_n == 4)
5520 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
5523 if (VECTOR_UNIT_VSX_P (V2DFmode)
5524 && out_mode == DFmode && out_n == 2
5525 && in_mode == DFmode && in_n == 2)
5526 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
5527 if (VECTOR_UNIT_VSX_P (V4SFmode)
5528 && out_mode == SFmode && out_n == 4
5529 && in_mode == SFmode && in_n == 4)
5530 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
5531 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5532 && out_mode == SFmode && out_n == 4
5533 && in_mode == SFmode && in_n == 4)
5534 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
5537 if (VECTOR_UNIT_VSX_P (V2DFmode)
5538 && out_mode == DFmode && out_n == 2
5539 && in_mode == DFmode && in_n == 2)
5540 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
5541 if (VECTOR_UNIT_VSX_P (V4SFmode)
5542 && out_mode == SFmode && out_n == 4
5543 && in_mode == SFmode && in_n == 4)
5544 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
5545 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5546 && out_mode == SFmode && out_n == 4
5547 && in_mode == SFmode && in_n == 4)
5548 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
5551 if (VECTOR_UNIT_VSX_P (V2DFmode)
5552 && out_mode == DFmode && out_n == 2
5553 && in_mode == DFmode && in_n == 2)
5554 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
5555 if (VECTOR_UNIT_VSX_P (V4SFmode)
5556 && out_mode == SFmode && out_n == 4
5557 && in_mode == SFmode && in_n == 4)
5558 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
5559 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
5560 && out_mode == SFmode && out_n == 4
5561 && in_mode == SFmode && in_n == 4)
5562 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
5565 if (VECTOR_UNIT_VSX_P (V2DFmode)
5566 && flag_unsafe_math_optimizations
5567 && out_mode == DFmode && out_n == 2
5568 && in_mode == DFmode && in_n == 2)
5569 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
5570 if (VECTOR_UNIT_VSX_P (V4SFmode)
5571 && flag_unsafe_math_optimizations
5572 && out_mode == SFmode && out_n == 4
5573 && in_mode == SFmode && in_n == 4)
5574 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
5577 if (VECTOR_UNIT_VSX_P (V2DFmode)
5578 && !flag_trapping_math
5579 && out_mode == DFmode && out_n == 2
5580 && in_mode == DFmode && in_n == 2)
5581 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
5582 if (VECTOR_UNIT_VSX_P (V4SFmode)
5583 && !flag_trapping_math
5584 && out_mode == SFmode && out_n == 4
5585 && in_mode == SFmode && in_n == 4)
5586 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
5592 /* Generate calls to libmass if appropriate. */
5593 if (rs6000_veclib_handler)
5594 return rs6000_veclib_handler (combined_fn (fn), type_out, type_in);
5599 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5602 rs6000_builtin_md_vectorized_function (tree fndecl, tree type_out,
5605 machine_mode in_mode, out_mode;
5608 if (TARGET_DEBUG_BUILTIN)
5609 fprintf (stderr, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5610 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
5611 GET_MODE_NAME (TYPE_MODE (type_out)),
5612 GET_MODE_NAME (TYPE_MODE (type_in)));
5614 if (TREE_CODE (type_out) != VECTOR_TYPE
5615 || TREE_CODE (type_in) != VECTOR_TYPE)
5618 out_mode = TYPE_MODE (TREE_TYPE (type_out));
5619 out_n = TYPE_VECTOR_SUBPARTS (type_out);
5620 in_mode = TYPE_MODE (TREE_TYPE (type_in));
5621 in_n = TYPE_VECTOR_SUBPARTS (type_in);
5623 enum rs6000_builtins fn
5624 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
5627 case RS6000_BUILTIN_RSQRTF:
5628 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5629 && out_mode == SFmode && out_n == 4
5630 && in_mode == SFmode && in_n == 4)
5631 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
5633 case RS6000_BUILTIN_RSQRT:
5634 if (VECTOR_UNIT_VSX_P (V2DFmode)
5635 && out_mode == DFmode && out_n == 2
5636 && in_mode == DFmode && in_n == 2)
5637 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
5639 case RS6000_BUILTIN_RECIPF:
5640 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
5641 && out_mode == SFmode && out_n == 4
5642 && in_mode == SFmode && in_n == 4)
5643 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
5645 case RS6000_BUILTIN_RECIP:
5646 if (VECTOR_UNIT_VSX_P (V2DFmode)
5647 && out_mode == DFmode && out_n == 2
5648 && in_mode == DFmode && in_n == 2)
5649 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
5657 /* Default CPU string for rs6000*_file_start functions. */
5658 static const char *rs6000_default_cpu;
5660 /* Do anything needed at the start of the asm file. */
5663 rs6000_file_start (void)
5666 const char *start = buffer;
5667 FILE *file = asm_out_file;
5669 rs6000_default_cpu = TARGET_CPU_DEFAULT;
5671 default_file_start ();
5673 if (flag_verbose_asm)
5675 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
5677 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
5679 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
5683 if (global_options_set.x_rs6000_cpu_index)
5685 fprintf (file, "%s -mcpu=%s", start,
5686 processor_target_table[rs6000_cpu_index].name);
5690 if (global_options_set.x_rs6000_tune_index)
5692 fprintf (file, "%s -mtune=%s", start,
5693 processor_target_table[rs6000_tune_index].name);
5697 if (PPC405_ERRATUM77)
5699 fprintf (file, "%s PPC405CR_ERRATUM77", start);
5703 #ifdef USING_ELFOS_H
5704 switch (rs6000_sdata)
5706 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
5707 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
5708 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
5709 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
5712 if (rs6000_sdata && g_switch_value)
5714 fprintf (file, "%s -G %d", start,
5724 #ifdef USING_ELFOS_H
5725 if (!(rs6000_default_cpu && rs6000_default_cpu[0])
5726 && !global_options_set.x_rs6000_cpu_index)
5728 fputs ("\t.machine ", asm_out_file);
5729 if ((rs6000_isa_flags & OPTION_MASK_MODULO) != 0)
5730 fputs ("power9\n", asm_out_file);
5731 else if ((rs6000_isa_flags & OPTION_MASK_DIRECT_MOVE) != 0)
5732 fputs ("power8\n", asm_out_file);
5733 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTD) != 0)
5734 fputs ("power7\n", asm_out_file);
5735 else if ((rs6000_isa_flags & OPTION_MASK_CMPB) != 0)
5736 fputs ("power6\n", asm_out_file);
5737 else if ((rs6000_isa_flags & OPTION_MASK_POPCNTB) != 0)
5738 fputs ("power5\n", asm_out_file);
5739 else if ((rs6000_isa_flags & OPTION_MASK_MFCRF) != 0)
5740 fputs ("power4\n", asm_out_file);
5741 else if ((rs6000_isa_flags & OPTION_MASK_POWERPC64) != 0)
5742 fputs ("ppc64\n", asm_out_file);
5744 fputs ("ppc\n", asm_out_file);
5748 if (DEFAULT_ABI == ABI_ELFv2)
5749 fprintf (file, "\t.abiversion 2\n");
5753 /* Return nonzero if this function is known to have a null epilogue. */
5756 direct_return (void)
5758 if (reload_completed)
5760 rs6000_stack_t *info = rs6000_stack_info ();
5762 if (info->first_gp_reg_save == 32
5763 && info->first_fp_reg_save == 64
5764 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
5765 && ! info->lr_save_p
5766 && ! info->cr_save_p
5767 && info->vrsave_size == 0
5775 /* Helper for num_insns_constant. Calculate number of instructions to
5776 load VALUE to a single gpr using combinations of addi, addis, ori,
5777 oris and sldi instructions. */
5780 num_insns_constant_gpr (HOST_WIDE_INT value)
5782 /* signed constant loadable with addi */
5783 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
5786 /* constant loadable with addis */
5787 else if ((value & 0xffff) == 0
5788 && (value >> 31 == -1 || value >> 31 == 0))
5791 else if (TARGET_POWERPC64)
5793 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
5794 HOST_WIDE_INT high = value >> 31;
5796 if (high == 0 || high == -1)
5802 return num_insns_constant_gpr (high) + 1;
5804 return num_insns_constant_gpr (low) + 1;
5806 return (num_insns_constant_gpr (high)
5807 + num_insns_constant_gpr (low) + 1);
5814 /* Helper for num_insns_constant. Allow constants formed by the
5815 num_insns_constant_gpr sequences, plus li -1, rldicl/rldicr/rlwinm,
5816 and handle modes that require multiple gprs. */
5819 num_insns_constant_multi (HOST_WIDE_INT value, machine_mode mode)
5821 int nregs = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5825 HOST_WIDE_INT low = sext_hwi (value, BITS_PER_WORD);
5826 int insns = num_insns_constant_gpr (low);
5828 /* We won't get more than 2 from num_insns_constant_gpr
5829 except when TARGET_POWERPC64 and mode is DImode or
5830 wider, so the register mode must be DImode. */
5831 && rs6000_is_valid_and_mask (GEN_INT (low), DImode))
5834 value >>= BITS_PER_WORD;
5839 /* Return the number of instructions it takes to form a constant in as
5840 many gprs are needed for MODE. */
5843 num_insns_constant (rtx op, machine_mode mode)
5847 switch (GET_CODE (op))
5853 case CONST_WIDE_INT:
5856 for (int i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
5857 insns += num_insns_constant_multi (CONST_WIDE_INT_ELT (op, i),
5864 const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
5866 if (mode == SFmode || mode == SDmode)
5871 REAL_VALUE_TO_TARGET_DECIMAL32 (*rv, l);
5873 REAL_VALUE_TO_TARGET_SINGLE (*rv, l);
5874 /* See the first define_split in rs6000.md handling a
5875 const_double_operand. */
5879 else if (mode == DFmode || mode == DDmode)
5884 REAL_VALUE_TO_TARGET_DECIMAL64 (*rv, l);
5886 REAL_VALUE_TO_TARGET_DOUBLE (*rv, l);
5888 /* See the second (32-bit) and third (64-bit) define_split
5889 in rs6000.md handling a const_double_operand. */
5890 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 0 : 1] << 32;
5891 val |= l[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffffUL;
5894 else if (mode == TFmode || mode == TDmode
5895 || mode == KFmode || mode == IFmode)
5901 REAL_VALUE_TO_TARGET_DECIMAL128 (*rv, l);
5903 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*rv, l);
5905 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 0 : 3] << 32;
5906 val |= l[WORDS_BIG_ENDIAN ? 1 : 2] & 0xffffffffUL;
5907 insns = num_insns_constant_multi (val, DImode);
5908 val = (unsigned HOST_WIDE_INT) l[WORDS_BIG_ENDIAN ? 2 : 1] << 32;
5909 val |= l[WORDS_BIG_ENDIAN ? 3 : 0] & 0xffffffffUL;
5910 insns += num_insns_constant_multi (val, DImode);
5922 return num_insns_constant_multi (val, mode);
5925 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5926 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5927 corresponding element of the vector, but for V4SFmode, the
5928 corresponding "float" is interpreted as an SImode integer. */
5931 const_vector_elt_as_int (rtx op, unsigned int elt)
5935 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5936 gcc_assert (GET_MODE (op) != V2DImode
5937 && GET_MODE (op) != V2DFmode);
5939 tmp = CONST_VECTOR_ELT (op, elt);
5940 if (GET_MODE (op) == V4SFmode)
5941 tmp = gen_lowpart (SImode, tmp);
5942 return INTVAL (tmp);
5945 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5946 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5947 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5948 all items are set to the same value and contain COPIES replicas of the
5949 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5950 operand and the others are set to the value of the operand's msb. */
5953 vspltis_constant (rtx op, unsigned step, unsigned copies)
5955 machine_mode mode = GET_MODE (op);
5956 machine_mode inner = GET_MODE_INNER (mode);
5964 HOST_WIDE_INT splat_val;
5965 HOST_WIDE_INT msb_val;
5967 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
5970 nunits = GET_MODE_NUNITS (mode);
5971 bitsize = GET_MODE_BITSIZE (inner);
5972 mask = GET_MODE_MASK (inner);
5974 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
5976 msb_val = val >= 0 ? 0 : -1;
5978 /* Construct the value to be splatted, if possible. If not, return 0. */
5979 for (i = 2; i <= copies; i *= 2)
5981 HOST_WIDE_INT small_val;
5983 small_val = splat_val >> bitsize;
5985 if (splat_val != ((HOST_WIDE_INT)
5986 ((unsigned HOST_WIDE_INT) small_val << bitsize)
5987 | (small_val & mask)))
5989 splat_val = small_val;
5992 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5993 if (EASY_VECTOR_15 (splat_val))
5996 /* Also check if we can splat, and then add the result to itself. Do so if
5997 the value is positive, of if the splat instruction is using OP's mode;
5998 for splat_val < 0, the splat and the add should use the same mode. */
5999 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
6000 && (splat_val >= 0 || (step == 1 && copies == 1)))
6003 /* Also check if are loading up the most significant bit which can be done by
6004 loading up -1 and shifting the value left by -1. */
6005 else if (EASY_VECTOR_MSB (splat_val, inner))
6011 /* Check if VAL is present in every STEP-th element, and the
6012 other elements are filled with its most significant bit. */
6013 for (i = 1; i < nunits; ++i)
6015 HOST_WIDE_INT desired_val;
6016 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
6017 if ((i & (step - 1)) == 0)
6020 desired_val = msb_val;
6022 if (desired_val != const_vector_elt_as_int (op, elt))
6029 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6030 instruction, filling in the bottom elements with 0 or -1.
6032 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6033 for the number of zeroes to shift in, or negative for the number of 0xff
6036 OP is a CONST_VECTOR. */
6039 vspltis_shifted (rtx op)
6041 machine_mode mode = GET_MODE (op);
6042 machine_mode inner = GET_MODE_INNER (mode);
6050 if (mode != V16QImode && mode != V8HImode && mode != V4SImode)
6053 /* We need to create pseudo registers to do the shift, so don't recognize
6054 shift vector constants after reload. */
6055 if (!can_create_pseudo_p ())
6058 nunits = GET_MODE_NUNITS (mode);
6059 mask = GET_MODE_MASK (inner);
6061 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? 0 : nunits - 1);
6063 /* Check if the value can really be the operand of a vspltis[bhw]. */
6064 if (EASY_VECTOR_15 (val))
6067 /* Also check if we are loading up the most significant bit which can be done
6068 by loading up -1 and shifting the value left by -1. */
6069 else if (EASY_VECTOR_MSB (val, inner))
6075 /* Check if VAL is present in every STEP-th element until we find elements
6076 that are 0 or all 1 bits. */
6077 for (i = 1; i < nunits; ++i)
6079 unsigned elt = BYTES_BIG_ENDIAN ? i : nunits - 1 - i;
6080 HOST_WIDE_INT elt_val = const_vector_elt_as_int (op, elt);
6082 /* If the value isn't the splat value, check for the remaining elements
6088 for (j = i+1; j < nunits; ++j)
6090 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6091 if (const_vector_elt_as_int (op, elt2) != 0)
6095 return (nunits - i) * GET_MODE_SIZE (inner);
6098 else if ((elt_val & mask) == mask)
6100 for (j = i+1; j < nunits; ++j)
6102 unsigned elt2 = BYTES_BIG_ENDIAN ? j : nunits - 1 - j;
6103 if ((const_vector_elt_as_int (op, elt2) & mask) != mask)
6107 return -((nunits - i) * GET_MODE_SIZE (inner));
6115 /* If all elements are equal, we don't need to do VLSDOI. */
6120 /* Return true if OP is of the given MODE and can be synthesized
6121 with a vspltisb, vspltish or vspltisw. */
6124 easy_altivec_constant (rtx op, machine_mode mode)
6126 unsigned step, copies;
6128 if (mode == VOIDmode)
6129 mode = GET_MODE (op);
6130 else if (mode != GET_MODE (op))
6133 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6135 if (mode == V2DFmode)
6136 return zero_constant (op, mode);
6138 else if (mode == V2DImode)
6140 if (!CONST_INT_P (CONST_VECTOR_ELT (op, 0))
6141 || !CONST_INT_P (CONST_VECTOR_ELT (op, 1)))
6144 if (zero_constant (op, mode))
6147 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
6148 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
6154 /* V1TImode is a special container for TImode. Ignore for now. */
6155 else if (mode == V1TImode)
6158 /* Start with a vspltisw. */
6159 step = GET_MODE_NUNITS (mode) / 4;
6162 if (vspltis_constant (op, step, copies))
6165 /* Then try with a vspltish. */
6171 if (vspltis_constant (op, step, copies))
6174 /* And finally a vspltisb. */
6180 if (vspltis_constant (op, step, copies))
6183 if (vspltis_shifted (op) != 0)
6189 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6190 result is OP. Abort if it is not possible. */
6193 gen_easy_altivec_constant (rtx op)
6195 machine_mode mode = GET_MODE (op);
6196 int nunits = GET_MODE_NUNITS (mode);
6197 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
6198 unsigned step = nunits / 4;
6199 unsigned copies = 1;
6201 /* Start with a vspltisw. */
6202 if (vspltis_constant (op, step, copies))
6203 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
6205 /* Then try with a vspltish. */
6211 if (vspltis_constant (op, step, copies))
6212 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
6214 /* And finally a vspltisb. */
6220 if (vspltis_constant (op, step, copies))
6221 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
6226 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6227 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6229 Return the number of instructions needed (1 or 2) into the address pointed
6232 Return the constant that is being split via CONSTANT_PTR. */
6235 xxspltib_constant_p (rtx op,
6240 size_t nunits = GET_MODE_NUNITS (mode);
6242 HOST_WIDE_INT value;
6245 /* Set the returned values to out of bound values. */
6246 *num_insns_ptr = -1;
6247 *constant_ptr = 256;
6249 if (!TARGET_P9_VECTOR)
6252 if (mode == VOIDmode)
6253 mode = GET_MODE (op);
6255 else if (mode != GET_MODE (op) && GET_MODE (op) != VOIDmode)
6258 /* Handle (vec_duplicate <constant>). */
6259 if (GET_CODE (op) == VEC_DUPLICATE)
6261 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6262 && mode != V2DImode)
6265 element = XEXP (op, 0);
6266 if (!CONST_INT_P (element))
6269 value = INTVAL (element);
6270 if (!IN_RANGE (value, -128, 127))
6274 /* Handle (const_vector [...]). */
6275 else if (GET_CODE (op) == CONST_VECTOR)
6277 if (mode != V16QImode && mode != V8HImode && mode != V4SImode
6278 && mode != V2DImode)
6281 element = CONST_VECTOR_ELT (op, 0);
6282 if (!CONST_INT_P (element))
6285 value = INTVAL (element);
6286 if (!IN_RANGE (value, -128, 127))
6289 for (i = 1; i < nunits; i++)
6291 element = CONST_VECTOR_ELT (op, i);
6292 if (!CONST_INT_P (element))
6295 if (value != INTVAL (element))
6300 /* Handle integer constants being loaded into the upper part of the VSX
6301 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6302 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6303 else if (CONST_INT_P (op))
6305 if (!SCALAR_INT_MODE_P (mode))
6308 value = INTVAL (op);
6309 if (!IN_RANGE (value, -128, 127))
6312 if (!IN_RANGE (value, -1, 0))
6314 if (!(reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID))
6317 if (EASY_VECTOR_15 (value))
6325 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6326 sign extend. Special case 0/-1 to allow getting any VSX register instead
6327 of an Altivec register. */
6328 if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
6329 && EASY_VECTOR_15 (value))
6332 /* Return # of instructions and the constant byte for XXSPLTIB. */
6333 if (mode == V16QImode)
6336 else if (IN_RANGE (value, -1, 0))
6342 *constant_ptr = (int) value;
6347 output_vec_const_move (rtx *operands)
6355 mode = GET_MODE (dest);
6359 bool dest_vmx_p = ALTIVEC_REGNO_P (REGNO (dest));
6360 int xxspltib_value = 256;
6363 if (zero_constant (vec, mode))
6365 if (TARGET_P9_VECTOR)
6366 return "xxspltib %x0,0";
6368 else if (dest_vmx_p)
6369 return "vspltisw %0,0";
6372 return "xxlxor %x0,%x0,%x0";
6375 if (all_ones_constant (vec, mode))
6377 if (TARGET_P9_VECTOR)
6378 return "xxspltib %x0,255";
6380 else if (dest_vmx_p)
6381 return "vspltisw %0,-1";
6383 else if (TARGET_P8_VECTOR)
6384 return "xxlorc %x0,%x0,%x0";
6390 if (TARGET_P9_VECTOR
6391 && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
6395 operands[2] = GEN_INT (xxspltib_value & 0xff);
6396 return "xxspltib %x0,%2";
6407 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest)));
6408 if (zero_constant (vec, mode))
6409 return "vspltisw %0,0";
6411 if (all_ones_constant (vec, mode))
6412 return "vspltisw %0,-1";
6414 /* Do we need to construct a value using VSLDOI? */
6415 shift = vspltis_shifted (vec);
6419 splat_vec = gen_easy_altivec_constant (vec);
6420 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
6421 operands[1] = XEXP (splat_vec, 0);
6422 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
6425 switch (GET_MODE (splat_vec))
6428 return "vspltisw %0,%1";
6431 return "vspltish %0,%1";
6434 return "vspltisb %0,%1";
6444 /* Initialize vector TARGET to VALS. */
6447 rs6000_expand_vector_init (rtx target, rtx vals)
6449 machine_mode mode = GET_MODE (target);
6450 machine_mode inner_mode = GET_MODE_INNER (mode);
6451 int n_elts = GET_MODE_NUNITS (mode);
6452 int n_var = 0, one_var = -1;
6453 bool all_same = true, all_const_zero = true;
6457 for (i = 0; i < n_elts; ++i)
6459 x = XVECEXP (vals, 0, i);
6460 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
6461 ++n_var, one_var = i;
6462 else if (x != CONST0_RTX (inner_mode))
6463 all_const_zero = false;
6465 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
6471 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
6472 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
6473 if ((int_vector_p || TARGET_VSX) && all_const_zero)
6475 /* Zero register. */
6476 emit_move_insn (target, CONST0_RTX (mode));
6479 else if (int_vector_p && easy_vector_constant (const_vec, mode))
6481 /* Splat immediate. */
6482 emit_insn (gen_rtx_SET (target, const_vec));
6487 /* Load from constant pool. */
6488 emit_move_insn (target, const_vec);
6493 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6494 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
6498 size_t num_elements = all_same ? 1 : 2;
6499 for (i = 0; i < num_elements; i++)
6501 op[i] = XVECEXP (vals, 0, i);
6502 /* Just in case there is a SUBREG with a smaller mode, do a
6504 if (GET_MODE (op[i]) != inner_mode)
6506 rtx tmp = gen_reg_rtx (inner_mode);
6507 convert_move (tmp, op[i], 0);
6510 /* Allow load with splat double word. */
6511 else if (MEM_P (op[i]))
6514 op[i] = force_reg (inner_mode, op[i]);
6516 else if (!REG_P (op[i]))
6517 op[i] = force_reg (inner_mode, op[i]);
6522 if (mode == V2DFmode)
6523 emit_insn (gen_vsx_splat_v2df (target, op[0]));
6525 emit_insn (gen_vsx_splat_v2di (target, op[0]));
6529 if (mode == V2DFmode)
6530 emit_insn (gen_vsx_concat_v2df (target, op[0], op[1]));
6532 emit_insn (gen_vsx_concat_v2di (target, op[0], op[1]));
6537 /* Special case initializing vector int if we are on 64-bit systems with
6538 direct move or we have the ISA 3.0 instructions. */
6539 if (mode == V4SImode && VECTOR_MEM_VSX_P (V4SImode)
6540 && TARGET_DIRECT_MOVE_64BIT)
6544 rtx element0 = XVECEXP (vals, 0, 0);
6545 if (MEM_P (element0))
6546 element0 = rs6000_force_indexed_or_indirect_mem (element0);
6548 element0 = force_reg (SImode, element0);
6550 if (TARGET_P9_VECTOR)
6551 emit_insn (gen_vsx_splat_v4si (target, element0));
6554 rtx tmp = gen_reg_rtx (DImode);
6555 emit_insn (gen_zero_extendsidi2 (tmp, element0));
6556 emit_insn (gen_vsx_splat_v4si_di (target, tmp));
6565 for (i = 0; i < 4; i++)
6566 elements[i] = force_reg (SImode, XVECEXP (vals, 0, i));
6568 emit_insn (gen_vsx_init_v4si (target, elements[0], elements[1],
6569 elements[2], elements[3]));
6574 /* With single precision floating point on VSX, know that internally single
6575 precision is actually represented as a double, and either make 2 V2DF
6576 vectors, and convert these vectors to single precision, or do one
6577 conversion, and splat the result to the other elements. */
6578 if (mode == V4SFmode && VECTOR_MEM_VSX_P (V4SFmode))
6582 rtx element0 = XVECEXP (vals, 0, 0);
6584 if (TARGET_P9_VECTOR)
6586 if (MEM_P (element0))
6587 element0 = rs6000_force_indexed_or_indirect_mem (element0);
6589 emit_insn (gen_vsx_splat_v4sf (target, element0));
6594 rtx freg = gen_reg_rtx (V4SFmode);
6595 rtx sreg = force_reg (SFmode, element0);
6596 rtx cvt = (TARGET_XSCVDPSPN
6597 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
6598 : gen_vsx_xscvdpsp_scalar (freg, sreg));
6601 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg,
6607 rtx dbl_even = gen_reg_rtx (V2DFmode);
6608 rtx dbl_odd = gen_reg_rtx (V2DFmode);
6609 rtx flt_even = gen_reg_rtx (V4SFmode);
6610 rtx flt_odd = gen_reg_rtx (V4SFmode);
6611 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
6612 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
6613 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
6614 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
6616 /* Use VMRGEW if we can instead of doing a permute. */
6617 if (TARGET_P8_VECTOR)
6619 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op2));
6620 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op1, op3));
6621 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6622 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6623 if (BYTES_BIG_ENDIAN)
6624 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_even, flt_odd));
6626 emit_insn (gen_p8_vmrgew_v4sf_direct (target, flt_odd, flt_even));
6630 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
6631 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
6632 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
6633 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
6634 rs6000_expand_extract_even (target, flt_even, flt_odd);
6640 /* Special case initializing vector short/char that are splats if we are on
6641 64-bit systems with direct move. */
6642 if (all_same && TARGET_DIRECT_MOVE_64BIT
6643 && (mode == V16QImode || mode == V8HImode))
6645 rtx op0 = XVECEXP (vals, 0, 0);
6646 rtx di_tmp = gen_reg_rtx (DImode);
6649 op0 = force_reg (GET_MODE_INNER (mode), op0);
6651 if (mode == V16QImode)
6653 emit_insn (gen_zero_extendqidi2 (di_tmp, op0));
6654 emit_insn (gen_vsx_vspltb_di (target, di_tmp));
6658 if (mode == V8HImode)
6660 emit_insn (gen_zero_extendhidi2 (di_tmp, op0));
6661 emit_insn (gen_vsx_vsplth_di (target, di_tmp));
6666 /* Store value to stack temp. Load vector element. Splat. However, splat
6667 of 64-bit items is not supported on Altivec. */
6668 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
6670 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6671 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
6672 XVECEXP (vals, 0, 0));
6673 x = gen_rtx_UNSPEC (VOIDmode,
6674 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6675 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6677 gen_rtx_SET (target, mem),
6679 x = gen_rtx_VEC_SELECT (inner_mode, target,
6680 gen_rtx_PARALLEL (VOIDmode,
6681 gen_rtvec (1, const0_rtx)));
6682 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_DUPLICATE (mode, x)));
6686 /* One field is non-constant. Load constant then overwrite
6690 rtx copy = copy_rtx (vals);
6692 /* Load constant part of vector, substitute neighboring value for
6694 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
6695 rs6000_expand_vector_init (target, copy);
6697 /* Insert variable. */
6698 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
6702 /* Construct the vector in memory one field at a time
6703 and load the whole vector. */
6704 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
6705 for (i = 0; i < n_elts; i++)
6706 emit_move_insn (adjust_address_nv (mem, inner_mode,
6707 i * GET_MODE_SIZE (inner_mode)),
6708 XVECEXP (vals, 0, i));
6709 emit_move_insn (target, mem);
6712 /* Set field ELT of TARGET to VAL. */
6715 rs6000_expand_vector_set (rtx target, rtx val, int elt)
6717 machine_mode mode = GET_MODE (target);
6718 machine_mode inner_mode = GET_MODE_INNER (mode);
6719 rtx reg = gen_reg_rtx (mode);
6721 int width = GET_MODE_SIZE (inner_mode);
6724 val = force_reg (GET_MODE (val), val);
6726 if (VECTOR_MEM_VSX_P (mode))
6728 rtx insn = NULL_RTX;
6729 rtx elt_rtx = GEN_INT (elt);
6731 if (mode == V2DFmode)
6732 insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
6734 else if (mode == V2DImode)
6735 insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
6737 else if (TARGET_P9_VECTOR && TARGET_POWERPC64)
6739 if (mode == V4SImode)
6740 insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
6741 else if (mode == V8HImode)
6742 insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
6743 else if (mode == V16QImode)
6744 insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
6745 else if (mode == V4SFmode)
6746 insn = gen_vsx_set_v4sf_p9 (target, target, val, elt_rtx);
6756 /* Simplify setting single element vectors like V1TImode. */
6757 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
6759 emit_move_insn (target, gen_lowpart (mode, val));
6763 /* Load single variable value. */
6764 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
6765 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
6766 x = gen_rtx_UNSPEC (VOIDmode,
6767 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
6768 emit_insn (gen_rtx_PARALLEL (VOIDmode,
6770 gen_rtx_SET (reg, mem),
6773 /* Linear sequence. */
6774 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
6775 for (i = 0; i < 16; ++i)
6776 XVECEXP (mask, 0, i) = GEN_INT (i);
6778 /* Set permute mask to insert element into target. */
6779 for (i = 0; i < width; ++i)
6780 XVECEXP (mask, 0, elt*width + i)
6781 = GEN_INT (i + 0x10);
6782 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
6784 if (BYTES_BIG_ENDIAN)
6785 x = gen_rtx_UNSPEC (mode,
6786 gen_rtvec (3, target, reg,
6787 force_reg (V16QImode, x)),
6791 if (TARGET_P9_VECTOR)
6792 x = gen_rtx_UNSPEC (mode,
6793 gen_rtvec (3, reg, target,
6794 force_reg (V16QImode, x)),
6798 /* Invert selector. We prefer to generate VNAND on P8 so
6799 that future fusion opportunities can kick in, but must
6800 generate VNOR elsewhere. */
6801 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
6802 rtx iorx = (TARGET_P8_VECTOR
6803 ? gen_rtx_IOR (V16QImode, notx, notx)
6804 : gen_rtx_AND (V16QImode, notx, notx));
6805 rtx tmp = gen_reg_rtx (V16QImode);
6806 emit_insn (gen_rtx_SET (tmp, iorx));
6808 /* Permute with operands reversed and adjusted selector. */
6809 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
6814 emit_insn (gen_rtx_SET (target, x));
6817 /* Extract field ELT from VEC into TARGET. */
6820 rs6000_expand_vector_extract (rtx target, rtx vec, rtx elt)
6822 machine_mode mode = GET_MODE (vec);
6823 machine_mode inner_mode = GET_MODE_INNER (mode);
6826 if (VECTOR_MEM_VSX_P (mode) && CONST_INT_P (elt))
6833 emit_move_insn (target, gen_lowpart (TImode, vec));
6836 emit_insn (gen_vsx_extract_v2df (target, vec, elt));
6839 emit_insn (gen_vsx_extract_v2di (target, vec, elt));
6842 emit_insn (gen_vsx_extract_v4sf (target, vec, elt));
6845 if (TARGET_DIRECT_MOVE_64BIT)
6847 emit_insn (gen_vsx_extract_v16qi (target, vec, elt));
6853 if (TARGET_DIRECT_MOVE_64BIT)
6855 emit_insn (gen_vsx_extract_v8hi (target, vec, elt));
6861 if (TARGET_DIRECT_MOVE_64BIT)
6863 emit_insn (gen_vsx_extract_v4si (target, vec, elt));
6869 else if (VECTOR_MEM_VSX_P (mode) && !CONST_INT_P (elt)
6870 && TARGET_DIRECT_MOVE_64BIT)
6872 if (GET_MODE (elt) != DImode)
6874 rtx tmp = gen_reg_rtx (DImode);
6875 convert_move (tmp, elt, 0);
6878 else if (!REG_P (elt))
6879 elt = force_reg (DImode, elt);
6884 emit_move_insn (target, gen_lowpart (TImode, vec));
6888 emit_insn (gen_vsx_extract_v2df_var (target, vec, elt));
6892 emit_insn (gen_vsx_extract_v2di_var (target, vec, elt));
6896 emit_insn (gen_vsx_extract_v4sf_var (target, vec, elt));
6900 emit_insn (gen_vsx_extract_v4si_var (target, vec, elt));
6904 emit_insn (gen_vsx_extract_v8hi_var (target, vec, elt));
6908 emit_insn (gen_vsx_extract_v16qi_var (target, vec, elt));
6916 /* Allocate mode-sized buffer. */
6917 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
6919 emit_move_insn (mem, vec);
6920 if (CONST_INT_P (elt))
6922 int modulo_elt = INTVAL (elt) % GET_MODE_NUNITS (mode);
6924 /* Add offset to field within buffer matching vector element. */
6925 mem = adjust_address_nv (mem, inner_mode,
6926 modulo_elt * GET_MODE_SIZE (inner_mode));
6927 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
6931 unsigned int ele_size = GET_MODE_SIZE (inner_mode);
6932 rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (mode) - 1);
6933 rtx new_addr = gen_reg_rtx (Pmode);
6935 elt = gen_rtx_AND (Pmode, elt, num_ele_m1);
6937 elt = gen_rtx_MULT (Pmode, elt, GEN_INT (ele_size));
6938 new_addr = gen_rtx_PLUS (Pmode, XEXP (mem, 0), elt);
6939 new_addr = change_address (mem, inner_mode, new_addr);
6940 emit_move_insn (target, new_addr);
6944 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
6945 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
6946 temporary (BASE_TMP) to fixup the address. Return the new memory address
6947 that is valid for reads or writes to a given register (SCALAR_REG). */
6950 rs6000_adjust_vec_address (rtx scalar_reg,
6954 machine_mode scalar_mode)
6956 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
6957 rtx addr = XEXP (mem, 0);
6962 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
6963 gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
6965 /* Calculate what we need to add to the address to get the element
6967 if (CONST_INT_P (element))
6968 element_offset = GEN_INT (INTVAL (element) * scalar_size);
6971 int byte_shift = exact_log2 (scalar_size);
6972 gcc_assert (byte_shift >= 0);
6974 if (byte_shift == 0)
6975 element_offset = element;
6979 if (TARGET_POWERPC64)
6980 emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
6982 emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
6984 element_offset = base_tmp;
6988 /* Create the new address pointing to the element within the vector. If we
6989 are adding 0, we don't have to change the address. */
6990 if (element_offset == const0_rtx)
6993 /* A simple indirect address can be converted into a reg + offset
6995 else if (REG_P (addr) || SUBREG_P (addr))
6996 new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
6998 /* Optimize D-FORM addresses with constant offset with a constant element, to
6999 include the element offset in the address directly. */
7000 else if (GET_CODE (addr) == PLUS)
7002 rtx op0 = XEXP (addr, 0);
7003 rtx op1 = XEXP (addr, 1);
7006 gcc_assert (REG_P (op0) || SUBREG_P (op0));
7007 if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
7009 HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
7010 rtx offset_rtx = GEN_INT (offset);
7012 if (IN_RANGE (offset, -32768, 32767)
7013 && (scalar_size < 8 || (offset & 0x3) == 0))
7014 new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
7017 emit_move_insn (base_tmp, offset_rtx);
7018 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7023 bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
7024 bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
7026 /* Note, ADDI requires the register being added to be a base
7027 register. If the register was R0, load it up into the temporary
7030 && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
7032 insn = gen_add3_insn (base_tmp, op1, element_offset);
7033 gcc_assert (insn != NULL_RTX);
7038 && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
7040 insn = gen_add3_insn (base_tmp, element_offset, op1);
7041 gcc_assert (insn != NULL_RTX);
7047 emit_move_insn (base_tmp, op1);
7048 emit_insn (gen_add2_insn (base_tmp, element_offset));
7051 new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
7057 emit_move_insn (base_tmp, addr);
7058 new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
7061 /* If we have a PLUS, we need to see whether the particular register class
7062 allows for D-FORM or X-FORM addressing. */
7063 if (GET_CODE (new_addr) == PLUS)
7065 rtx op1 = XEXP (new_addr, 1);
7066 addr_mask_type addr_mask;
7067 unsigned int scalar_regno = reg_or_subregno (scalar_reg);
7069 gcc_assert (HARD_REGISTER_NUM_P (scalar_regno));
7070 if (INT_REGNO_P (scalar_regno))
7071 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_GPR];
7073 else if (FP_REGNO_P (scalar_regno))
7074 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_FPR];
7076 else if (ALTIVEC_REGNO_P (scalar_regno))
7077 addr_mask = reg_addr[scalar_mode].addr_mask[RELOAD_REG_VMX];
7082 if (REG_P (op1) || SUBREG_P (op1))
7083 valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
7085 valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
7088 else if (REG_P (new_addr) || SUBREG_P (new_addr))
7089 valid_addr_p = true;
7092 valid_addr_p = false;
7096 emit_move_insn (base_tmp, new_addr);
7097 new_addr = base_tmp;
7100 return change_address (mem, scalar_mode, new_addr);
7103 /* Split a variable vec_extract operation into the component instructions. */
7106 rs6000_split_vec_extract_var (rtx dest, rtx src, rtx element, rtx tmp_gpr,
7109 machine_mode mode = GET_MODE (src);
7110 machine_mode scalar_mode = GET_MODE_INNER (GET_MODE (src));
7111 unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
7112 int byte_shift = exact_log2 (scalar_size);
7114 gcc_assert (byte_shift >= 0);
7116 /* If we are given a memory address, optimize to load just the element. We
7117 don't have to adjust the vector element number on little endian
7121 int num_elements = GET_MODE_NUNITS (mode);
7122 rtx num_ele_m1 = GEN_INT (num_elements - 1);
7124 emit_insn (gen_anddi3 (element, element, num_ele_m1));
7125 gcc_assert (REG_P (tmp_gpr));
7126 emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
7127 tmp_gpr, scalar_mode));
7131 else if (REG_P (src) || SUBREG_P (src))
7133 int num_elements = GET_MODE_NUNITS (mode);
7134 int bits_in_element = mode_to_bits (GET_MODE_INNER (mode));
7135 int bit_shift = 7 - exact_log2 (num_elements);
7137 unsigned int dest_regno = reg_or_subregno (dest);
7138 unsigned int src_regno = reg_or_subregno (src);
7139 unsigned int element_regno = reg_or_subregno (element);
7141 gcc_assert (REG_P (tmp_gpr));
7143 /* See if we want to generate VEXTU{B,H,W}{L,R}X if the destination is in
7144 a general purpose register. */
7145 if (TARGET_P9_VECTOR
7146 && (mode == V16QImode || mode == V8HImode || mode == V4SImode)
7147 && INT_REGNO_P (dest_regno)
7148 && ALTIVEC_REGNO_P (src_regno)
7149 && INT_REGNO_P (element_regno))
7151 rtx dest_si = gen_rtx_REG (SImode, dest_regno);
7152 rtx element_si = gen_rtx_REG (SImode, element_regno);
7154 if (mode == V16QImode)
7155 emit_insn (BYTES_BIG_ENDIAN
7156 ? gen_vextublx (dest_si, element_si, src)
7157 : gen_vextubrx (dest_si, element_si, src));
7159 else if (mode == V8HImode)
7161 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7162 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const1_rtx));
7163 emit_insn (BYTES_BIG_ENDIAN
7164 ? gen_vextuhlx (dest_si, tmp_gpr_si, src)
7165 : gen_vextuhrx (dest_si, tmp_gpr_si, src));
7171 rtx tmp_gpr_si = gen_rtx_REG (SImode, REGNO (tmp_gpr));
7172 emit_insn (gen_ashlsi3 (tmp_gpr_si, element_si, const2_rtx));
7173 emit_insn (BYTES_BIG_ENDIAN
7174 ? gen_vextuwlx (dest_si, tmp_gpr_si, src)
7175 : gen_vextuwrx (dest_si, tmp_gpr_si, src));
7182 gcc_assert (REG_P (tmp_altivec));
7184 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7185 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7186 will shift the element into the upper position (adding 3 to convert a
7187 byte shift into a bit shift). */
7188 if (scalar_size == 8)
7190 if (!BYTES_BIG_ENDIAN)
7192 emit_insn (gen_xordi3 (tmp_gpr, element, const1_rtx));
7198 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7200 emit_insn (gen_rtx_SET (tmp_gpr,
7201 gen_rtx_AND (DImode,
7202 gen_rtx_ASHIFT (DImode,
7209 if (!BYTES_BIG_ENDIAN)
7211 rtx num_ele_m1 = GEN_INT (num_elements - 1);
7213 emit_insn (gen_anddi3 (tmp_gpr, element, num_ele_m1));
7214 emit_insn (gen_subdi3 (tmp_gpr, num_ele_m1, tmp_gpr));
7220 emit_insn (gen_ashldi3 (tmp_gpr, element2, GEN_INT (bit_shift)));
7223 /* Get the value into the lower byte of the Altivec register where VSLO
7225 if (TARGET_P9_VECTOR)
7226 emit_insn (gen_vsx_splat_v2di (tmp_altivec, tmp_gpr));
7227 else if (can_create_pseudo_p ())
7228 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_gpr, tmp_gpr));
7231 rtx tmp_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7232 emit_move_insn (tmp_di, tmp_gpr);
7233 emit_insn (gen_vsx_concat_v2di (tmp_altivec, tmp_di, tmp_di));
7236 /* Do the VSLO to get the value into the final location. */
7240 emit_insn (gen_vsx_vslo_v2df (dest, src, tmp_altivec));
7244 emit_insn (gen_vsx_vslo_v2di (dest, src, tmp_altivec));
7249 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7250 rtx tmp_altivec_v4sf = gen_rtx_REG (V4SFmode, REGNO (tmp_altivec));
7251 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7252 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7255 emit_insn (gen_vsx_xscvspdp_scalar2 (dest, tmp_altivec_v4sf));
7263 rtx tmp_altivec_di = gen_rtx_REG (DImode, REGNO (tmp_altivec));
7264 rtx src_v2di = gen_rtx_REG (V2DImode, REGNO (src));
7265 rtx tmp_gpr_di = gen_rtx_REG (DImode, REGNO (dest));
7266 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di, src_v2di,
7268 emit_move_insn (tmp_gpr_di, tmp_altivec_di);
7269 emit_insn (gen_lshrdi3 (tmp_gpr_di, tmp_gpr_di,
7270 GEN_INT (64 - bits_in_element)));
7284 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7285 selects whether the alignment is abi mandated, optional, or
7286 both abi and optional alignment. */
7289 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
7291 if (how != align_opt)
7293 if (TREE_CODE (type) == VECTOR_TYPE && align < 128)
7297 if (how != align_abi)
7299 if (TREE_CODE (type) == ARRAY_TYPE
7300 && TYPE_MODE (TREE_TYPE (type)) == QImode)
7302 if (align < BITS_PER_WORD)
7303 align = BITS_PER_WORD;
7310 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. Altivec vector memory
7311 instructions simply ignore the low bits; VSX memory instructions
7312 are aligned to 4 or 8 bytes. */
7315 rs6000_slow_unaligned_access (machine_mode mode, unsigned int align)
7317 return (STRICT_ALIGNMENT
7318 || (!TARGET_EFFICIENT_UNALIGNED_VSX
7319 && ((SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && align < 32)
7320 || ((VECTOR_MODE_P (mode) || FLOAT128_VECTOR_P (mode))
7321 && (int) align < VECTOR_ALIGN (mode)))));
7324 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7327 rs6000_special_adjust_field_align_p (tree type, unsigned int computed)
7329 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
7331 if (computed != 128)
7334 if (!warned && warn_psabi)
7337 inform (input_location,
7338 "the layout of aggregates containing vectors with"
7339 " %d-byte alignment has changed in GCC 5",
7340 computed / BITS_PER_UNIT);
7343 /* In current GCC there is no special case. */
7350 /* AIX increases natural record alignment to doubleword if the first
7351 field is an FP double while the FP fields remain word aligned. */
7354 rs6000_special_round_type_align (tree type, unsigned int computed,
7355 unsigned int specified)
7357 unsigned int align = MAX (computed, specified);
7358 tree field = TYPE_FIELDS (type);
7360 /* Skip all non field decls */
7361 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7362 field = DECL_CHAIN (field);
7364 if (field != NULL && field != type)
7366 type = TREE_TYPE (field);
7367 while (TREE_CODE (type) == ARRAY_TYPE)
7368 type = TREE_TYPE (type);
7370 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
7371 align = MAX (align, 64);
7377 /* Darwin increases record alignment to the natural alignment of
7381 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
7382 unsigned int specified)
7384 unsigned int align = MAX (computed, specified);
7386 if (TYPE_PACKED (type))
7389 /* Find the first field, looking down into aggregates. */
7391 tree field = TYPE_FIELDS (type);
7392 /* Skip all non field decls */
7393 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
7394 field = DECL_CHAIN (field);
7397 /* A packed field does not contribute any extra alignment. */
7398 if (DECL_PACKED (field))
7400 type = TREE_TYPE (field);
7401 while (TREE_CODE (type) == ARRAY_TYPE)
7402 type = TREE_TYPE (type);
7403 } while (AGGREGATE_TYPE_P (type));
7405 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
7406 align = MAX (align, TYPE_ALIGN (type));
7411 /* Return 1 for an operand in small memory on V.4/eabi. */
7414 small_data_operand (rtx op ATTRIBUTE_UNUSED,
7415 machine_mode mode ATTRIBUTE_UNUSED)
7420 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
7423 if (DEFAULT_ABI != ABI_V4)
7426 if (SYMBOL_REF_P (op))
7429 else if (GET_CODE (op) != CONST
7430 || GET_CODE (XEXP (op, 0)) != PLUS
7431 || !SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
7432 || !CONST_INT_P (XEXP (XEXP (op, 0), 1)))
7437 rtx sum = XEXP (op, 0);
7438 HOST_WIDE_INT summand;
7440 /* We have to be careful here, because it is the referenced address
7441 that must be 32k from _SDA_BASE_, not just the symbol. */
7442 summand = INTVAL (XEXP (sum, 1));
7443 if (summand < 0 || summand > g_switch_value)
7446 sym_ref = XEXP (sum, 0);
7449 return SYMBOL_REF_SMALL_P (sym_ref);
7455 /* Return true if either operand is a general purpose register. */
7458 gpr_or_gpr_p (rtx op0, rtx op1)
7460 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
7461 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
7464 /* Return true if this is a move direct operation between GPR registers and
7465 floating point/VSX registers. */
7468 direct_move_p (rtx op0, rtx op1)
7472 if (!REG_P (op0) || !REG_P (op1))
7475 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
7478 regno0 = REGNO (op0);
7479 regno1 = REGNO (op1);
7480 if (!HARD_REGISTER_NUM_P (regno0) || !HARD_REGISTER_NUM_P (regno1))
7483 if (INT_REGNO_P (regno0))
7484 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
7486 else if (INT_REGNO_P (regno1))
7488 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
7491 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
7498 /* Return true if the OFFSET is valid for the quad address instructions that
7499 use d-form (register + offset) addressing. */
7502 quad_address_offset_p (HOST_WIDE_INT offset)
7504 return (IN_RANGE (offset, -32768, 32767) && ((offset) & 0xf) == 0);
7507 /* Return true if the ADDR is an acceptable address for a quad memory
7508 operation of mode MODE (either LQ/STQ for general purpose registers, or
7509 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
7510 is intended for LQ/STQ. If it is false, the address is intended for the ISA
7511 3.0 LXV/STXV instruction. */
7514 quad_address_p (rtx addr, machine_mode mode, bool strict)
7518 if (GET_MODE_SIZE (mode) != 16)
7521 if (legitimate_indirect_address_p (addr, strict))
7524 if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode))
7527 if (GET_CODE (addr) != PLUS)
7530 op0 = XEXP (addr, 0);
7531 if (!REG_P (op0) || !INT_REG_OK_FOR_BASE_P (op0, strict))
7534 op1 = XEXP (addr, 1);
7535 if (!CONST_INT_P (op1))
7538 return quad_address_offset_p (INTVAL (op1));
7541 /* Return true if this is a load or store quad operation. This function does
7542 not handle the atomic quad memory instructions. */
7545 quad_load_store_p (rtx op0, rtx op1)
7549 if (!TARGET_QUAD_MEMORY)
7552 else if (REG_P (op0) && MEM_P (op1))
7553 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
7554 && quad_memory_operand (op1, GET_MODE (op1))
7555 && !reg_overlap_mentioned_p (op0, op1));
7557 else if (MEM_P (op0) && REG_P (op1))
7558 ret = (quad_memory_operand (op0, GET_MODE (op0))
7559 && quad_int_reg_operand (op1, GET_MODE (op1)));
7564 if (TARGET_DEBUG_ADDR)
7566 fprintf (stderr, "\n========== quad_load_store, return %s\n",
7567 ret ? "true" : "false");
7568 debug_rtx (gen_rtx_SET (op0, op1));
7574 /* Given an address, return a constant offset term if one exists. */
7577 address_offset (rtx op)
7579 if (GET_CODE (op) == PRE_INC
7580 || GET_CODE (op) == PRE_DEC)
7582 else if (GET_CODE (op) == PRE_MODIFY
7583 || GET_CODE (op) == LO_SUM)
7586 if (GET_CODE (op) == CONST)
7589 if (GET_CODE (op) == PLUS)
7592 if (CONST_INT_P (op))
7598 /* Return true if the MEM operand is a memory operand suitable for use
7599 with a (full width, possibly multiple) gpr load/store. On
7600 powerpc64 this means the offset must be divisible by 4.
7601 Implements 'Y' constraint.
7603 Accept direct, indexed, offset, lo_sum and tocref. Since this is
7604 a constraint function we know the operand has satisfied a suitable
7607 Offsetting a lo_sum should not be allowed, except where we know by
7608 alignment that a 32k boundary is not crossed. Note that by
7609 "offsetting" here we mean a further offset to access parts of the
7610 MEM. It's fine to have a lo_sum where the inner address is offset
7611 from a sym, since the same sym+offset will appear in the high part
7612 of the address calculation. */
7615 mem_operand_gpr (rtx op, machine_mode mode)
7617 unsigned HOST_WIDE_INT offset;
7619 rtx addr = XEXP (op, 0);
7621 /* PR85755: Allow PRE_INC and PRE_DEC addresses. */
7623 && (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
7624 && mode_supports_pre_incdec_p (mode)
7625 && legitimate_indirect_address_p (XEXP (addr, 0), false))
7628 /* Don't allow non-offsettable addresses. See PRs 83969 and 84279. */
7629 if (!rs6000_offsettable_memref_p (op, mode, false))
7632 op = address_offset (addr);
7636 offset = INTVAL (op);
7637 if (TARGET_POWERPC64 && (offset & 3) != 0)
7640 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
7644 if (GET_CODE (addr) == LO_SUM)
7645 /* For lo_sum addresses, we must allow any offset except one that
7646 causes a wrap, so test only the low 16 bits. */
7647 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7649 return offset + 0x8000 < 0x10000u - extra;
7652 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
7653 enforce an offset divisible by 4 even for 32-bit. */
7656 mem_operand_ds_form (rtx op, machine_mode mode)
7658 unsigned HOST_WIDE_INT offset;
7660 rtx addr = XEXP (op, 0);
7662 if (!offsettable_address_p (false, mode, addr))
7665 op = address_offset (addr);
7669 offset = INTVAL (op);
7670 if ((offset & 3) != 0)
7673 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
7677 if (GET_CODE (addr) == LO_SUM)
7678 /* For lo_sum addresses, we must allow any offset except one that
7679 causes a wrap, so test only the low 16 bits. */
7680 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
7682 return offset + 0x8000 < 0x10000u - extra;
7685 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
7688 reg_offset_addressing_ok_p (machine_mode mode)
7702 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
7703 ISA 3.0 vector d-form addressing mode was added. While TImode is not
7704 a vector mode, if we want to use the VSX registers to move it around,
7705 we need to restrict ourselves to reg+reg addressing. Similarly for
7706 IEEE 128-bit floating point that is passed in a single vector
7708 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
7709 return mode_supports_dq_form (mode);
7713 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
7714 addressing for the LFIWZX and STFIWX instructions. */
7715 if (TARGET_NO_SDMODE_STACK)
7727 virtual_stack_registers_memory_p (rtx op)
7732 regnum = REGNO (op);
7734 else if (GET_CODE (op) == PLUS
7735 && REG_P (XEXP (op, 0))
7736 && CONST_INT_P (XEXP (op, 1)))
7737 regnum = REGNO (XEXP (op, 0));
7742 return (regnum >= FIRST_VIRTUAL_REGISTER
7743 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
7746 /* Return true if a MODE sized memory accesses to OP plus OFFSET
7747 is known to not straddle a 32k boundary. This function is used
7748 to determine whether -mcmodel=medium code can use TOC pointer
7749 relative addressing for OP. This means the alignment of the TOC
7750 pointer must also be taken into account, and unfortunately that is
7753 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
7754 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
7758 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
7762 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
7764 if (!SYMBOL_REF_P (op))
7767 /* ISA 3.0 vector d-form addressing is restricted, don't allow
7769 if (mode_supports_dq_form (mode))
7772 dsize = GET_MODE_SIZE (mode);
7773 decl = SYMBOL_REF_DECL (op);
7779 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
7780 replacing memory addresses with an anchor plus offset. We
7781 could find the decl by rummaging around in the block->objects
7782 VEC for the given offset but that seems like too much work. */
7783 dalign = BITS_PER_UNIT;
7784 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
7785 && SYMBOL_REF_ANCHOR_P (op)
7786 && SYMBOL_REF_BLOCK (op) != NULL)
7788 struct object_block *block = SYMBOL_REF_BLOCK (op);
7790 dalign = block->alignment;
7791 offset += SYMBOL_REF_BLOCK_OFFSET (op);
7793 else if (CONSTANT_POOL_ADDRESS_P (op))
7795 /* It would be nice to have get_pool_align().. */
7796 machine_mode cmode = get_pool_mode (op);
7798 dalign = GET_MODE_ALIGNMENT (cmode);
7801 else if (DECL_P (decl))
7803 dalign = DECL_ALIGN (decl);
7807 /* Allow BLKmode when the entire object is known to not
7808 cross a 32k boundary. */
7809 if (!DECL_SIZE_UNIT (decl))
7812 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
7815 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
7819 dalign /= BITS_PER_UNIT;
7820 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
7821 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
7822 return dalign >= dsize;
7828 /* Find how many bits of the alignment we know for this access. */
7829 dalign /= BITS_PER_UNIT;
7830 if (dalign > POWERPC64_TOC_POINTER_ALIGNMENT)
7831 dalign = POWERPC64_TOC_POINTER_ALIGNMENT;
7833 lsb = offset & -offset;
7837 return dalign >= dsize;
7841 constant_pool_expr_p (rtx op)
7845 split_const (op, &base, &offset);
7846 return (SYMBOL_REF_P (base)
7847 && CONSTANT_POOL_ADDRESS_P (base)
7848 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
7851 /* These are only used to pass through from print_operand/print_operand_address
7852 to rs6000_output_addr_const_extra over the intervening function
7853 output_addr_const which is not target code. */
7854 static const_rtx tocrel_base_oac, tocrel_offset_oac;
7856 /* Return true if OP is a toc pointer relative address (the output
7857 of create_TOC_reference). If STRICT, do not match non-split
7858 -mcmodel=large/medium toc pointer relative addresses. If the pointers
7859 are non-NULL, place base and offset pieces in TOCREL_BASE_RET and
7860 TOCREL_OFFSET_RET respectively. */
7863 toc_relative_expr_p (const_rtx op, bool strict, const_rtx *tocrel_base_ret,
7864 const_rtx *tocrel_offset_ret)
7869 if (TARGET_CMODEL != CMODEL_SMALL)
7871 /* When strict ensure we have everything tidy. */
7873 && !(GET_CODE (op) == LO_SUM
7874 && REG_P (XEXP (op, 0))
7875 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict)))
7878 /* When not strict, allow non-split TOC addresses and also allow
7879 (lo_sum (high ..)) TOC addresses created during reload. */
7880 if (GET_CODE (op) == LO_SUM)
7884 const_rtx tocrel_base = op;
7885 const_rtx tocrel_offset = const0_rtx;
7887 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
7889 tocrel_base = XEXP (op, 0);
7890 tocrel_offset = XEXP (op, 1);
7893 if (tocrel_base_ret)
7894 *tocrel_base_ret = tocrel_base;
7895 if (tocrel_offset_ret)
7896 *tocrel_offset_ret = tocrel_offset;
7898 return (GET_CODE (tocrel_base) == UNSPEC
7899 && XINT (tocrel_base, 1) == UNSPEC_TOCREL
7900 && REG_P (XVECEXP (tocrel_base, 0, 1))
7901 && REGNO (XVECEXP (tocrel_base, 0, 1)) == TOC_REGISTER);
7904 /* Return true if X is a constant pool address, and also for cmodel=medium
7905 if X is a toc-relative address known to be offsettable within MODE. */
7908 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
7911 const_rtx tocrel_base, tocrel_offset;
7912 return (toc_relative_expr_p (x, strict, &tocrel_base, &tocrel_offset)
7913 && (TARGET_CMODEL != CMODEL_MEDIUM
7914 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
7916 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
7917 INTVAL (tocrel_offset), mode)));
7921 legitimate_small_data_p (machine_mode mode, rtx x)
7923 return (DEFAULT_ABI == ABI_V4
7924 && !flag_pic && !TARGET_TOC
7925 && (SYMBOL_REF_P (x) || GET_CODE (x) == CONST)
7926 && small_data_operand (x, mode));
7930 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
7931 bool strict, bool worst_case)
7933 unsigned HOST_WIDE_INT offset;
7936 if (GET_CODE (x) != PLUS)
7938 if (!REG_P (XEXP (x, 0)))
7940 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
7942 if (mode_supports_dq_form (mode))
7943 return quad_address_p (x, mode, strict);
7944 if (!reg_offset_addressing_ok_p (mode))
7945 return virtual_stack_registers_memory_p (x);
7946 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
7948 if (!CONST_INT_P (XEXP (x, 1)))
7951 offset = INTVAL (XEXP (x, 1));
7958 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
7960 if (VECTOR_MEM_VSX_P (mode))
7965 if (!TARGET_POWERPC64)
7967 else if (offset & 3)
7980 if (!TARGET_POWERPC64)
7982 else if (offset & 3)
7991 return offset < 0x10000 - extra;
7995 legitimate_indexed_address_p (rtx x, int strict)
7999 if (GET_CODE (x) != PLUS)
8005 return (REG_P (op0) && REG_P (op1)
8006 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
8007 && INT_REG_OK_FOR_INDEX_P (op1, strict))
8008 || (INT_REG_OK_FOR_BASE_P (op1, strict)
8009 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
8013 avoiding_indexed_address_p (machine_mode mode)
8015 /* Avoid indexed addressing for modes that have non-indexed
8016 load/store instruction forms. */
8017 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
8021 legitimate_indirect_address_p (rtx x, int strict)
8023 return REG_P (x) && INT_REG_OK_FOR_BASE_P (x, strict);
8027 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
8029 if (!TARGET_MACHO || !flag_pic
8030 || mode != SImode || !MEM_P (x))
8034 if (GET_CODE (x) != LO_SUM)
8036 if (!REG_P (XEXP (x, 0)))
8038 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
8042 return CONSTANT_P (x);
8046 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
8048 if (GET_CODE (x) != LO_SUM)
8050 if (!REG_P (XEXP (x, 0)))
8052 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
8054 /* quad word addresses are restricted, and we can't use LO_SUM. */
8055 if (mode_supports_dq_form (mode))
8059 if (TARGET_ELF || TARGET_MACHO)
8063 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8065 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8066 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8067 recognizes some LO_SUM addresses as valid although this
8068 function says opposite. In most cases, LRA through different
8069 transformations can generate correct code for address reloads.
8070 It cannot manage only some LO_SUM cases. So we need to add
8071 code here saying that some addresses are still valid. */
8072 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
8073 && small_toc_ref (x, VOIDmode));
8074 if (TARGET_TOC && ! large_toc_ok)
8076 if (GET_MODE_NUNITS (mode) != 1)
8078 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8079 && !(/* ??? Assume floating point reg based on mode? */
8080 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8083 return CONSTANT_P (x) || large_toc_ok;
8090 /* Try machine-dependent ways of modifying an illegitimate address
8091 to be legitimate. If we find one, return the new, valid address.
8092 This is used from only one place: `memory_address' in explow.c.
8094 OLDX is the address as it was before break_out_memory_refs was
8095 called. In some cases it is useful to look at this to decide what
8098 It is always safe for this function to do nothing. It exists to
8099 recognize opportunities to optimize the output.
8101 On RS/6000, first check for the sum of a register with a constant
8102 integer that is out of range. If so, generate code to add the
8103 constant with the low-order 16 bits masked to the register and force
8104 this result into another register (this can be done with `cau').
8105 Then generate an address of REG+(CONST&0xffff), allowing for the
8106 possibility of bit 16 being a one.
8108 Then check for the sum of a register and something not constant, try to
8109 load the other things into a register and return the sum. */
8112 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
8117 if (!reg_offset_addressing_ok_p (mode)
8118 || mode_supports_dq_form (mode))
8120 if (virtual_stack_registers_memory_p (x))
8123 /* In theory we should not be seeing addresses of the form reg+0,
8124 but just in case it is generated, optimize it away. */
8125 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
8126 return force_reg (Pmode, XEXP (x, 0));
8128 /* For TImode with load/store quad, restrict addresses to just a single
8129 pointer, so it works with both GPRs and VSX registers. */
8130 /* Make sure both operands are registers. */
8131 else if (GET_CODE (x) == PLUS
8132 && (mode != TImode || !TARGET_VSX))
8133 return gen_rtx_PLUS (Pmode,
8134 force_reg (Pmode, XEXP (x, 0)),
8135 force_reg (Pmode, XEXP (x, 1)));
8137 return force_reg (Pmode, x);
8139 if (SYMBOL_REF_P (x))
8141 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
8143 return rs6000_legitimize_tls_address (x, model);
8155 /* As in legitimate_offset_address_p we do not assume
8156 worst-case. The mode here is just a hint as to the registers
8157 used. A TImode is usually in gprs, but may actually be in
8158 fprs. Leave worst-case scenario for reload to handle via
8159 insn constraints. PTImode is only GPRs. */
8166 if (GET_CODE (x) == PLUS
8167 && REG_P (XEXP (x, 0))
8168 && CONST_INT_P (XEXP (x, 1))
8169 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
8170 >= 0x10000 - extra))
8172 HOST_WIDE_INT high_int, low_int;
8174 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8175 if (low_int >= 0x8000 - extra)
8177 high_int = INTVAL (XEXP (x, 1)) - low_int;
8178 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
8179 GEN_INT (high_int)), 0);
8180 return plus_constant (Pmode, sum, low_int);
8182 else if (GET_CODE (x) == PLUS
8183 && REG_P (XEXP (x, 0))
8184 && !CONST_INT_P (XEXP (x, 1))
8185 && GET_MODE_NUNITS (mode) == 1
8186 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8187 || (/* ??? Assume floating point reg based on mode? */
8188 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode)))
8189 && !avoiding_indexed_address_p (mode))
8191 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
8192 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
8194 else if ((TARGET_ELF
8196 || !MACHO_DYNAMIC_NO_PIC_P
8203 && !CONST_WIDE_INT_P (x)
8204 && !CONST_DOUBLE_P (x)
8206 && GET_MODE_NUNITS (mode) == 1
8207 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
8208 || (/* ??? Assume floating point reg based on mode? */
8209 TARGET_HARD_FLOAT && (mode == DFmode || mode == DDmode))))
8211 rtx reg = gen_reg_rtx (Pmode);
8213 emit_insn (gen_elf_high (reg, x));
8215 emit_insn (gen_macho_high (reg, x));
8216 return gen_rtx_LO_SUM (Pmode, reg, x);
8220 && constant_pool_expr_p (x)
8221 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
8222 return create_TOC_reference (x, NULL_RTX);
8227 /* Debug version of rs6000_legitimize_address. */
8229 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
8235 ret = rs6000_legitimize_address (x, oldx, mode);
8236 insns = get_insns ();
8242 "\nrs6000_legitimize_address: mode %s, old code %s, "
8243 "new code %s, modified\n",
8244 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
8245 GET_RTX_NAME (GET_CODE (ret)));
8247 fprintf (stderr, "Original address:\n");
8250 fprintf (stderr, "oldx:\n");
8253 fprintf (stderr, "New address:\n");
8258 fprintf (stderr, "Insns added:\n");
8259 debug_rtx_list (insns, 20);
8265 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8266 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
8277 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8278 We need to emit DTP-relative relocations. */
8280 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
8282 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
8287 fputs ("\t.long\t", file);
8290 fputs (DOUBLE_INT_ASM_OP, file);
8295 output_addr_const (file, x);
8297 fputs ("@dtprel+0x8000", file);
8298 else if (TARGET_XCOFF && SYMBOL_REF_P (x))
8300 switch (SYMBOL_REF_TLS_MODEL (x))
8304 case TLS_MODEL_LOCAL_EXEC:
8305 fputs ("@le", file);
8307 case TLS_MODEL_INITIAL_EXEC:
8308 fputs ("@ie", file);
8310 case TLS_MODEL_GLOBAL_DYNAMIC:
8311 case TLS_MODEL_LOCAL_DYNAMIC:
8320 /* Return true if X is a symbol that refers to real (rather than emulated)
8324 rs6000_real_tls_symbol_ref_p (rtx x)
8326 return (SYMBOL_REF_P (x)
8327 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
8330 /* In the name of slightly smaller debug output, and to cater to
8331 general assembler lossage, recognize various UNSPEC sequences
8332 and turn them back into a direct symbol reference. */
8335 rs6000_delegitimize_address (rtx orig_x)
8339 if (GET_CODE (orig_x) == UNSPEC && XINT (orig_x, 1) == UNSPEC_FUSION_GPR)
8340 orig_x = XVECEXP (orig_x, 0, 0);
8342 orig_x = delegitimize_mem_from_attrs (orig_x);
8349 if (TARGET_CMODEL != CMODEL_SMALL && GET_CODE (y) == LO_SUM)
8353 if (GET_CODE (y) == PLUS
8354 && GET_MODE (y) == Pmode
8355 && CONST_INT_P (XEXP (y, 1)))
8357 offset = XEXP (y, 1);
8361 if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_TOCREL)
8363 y = XVECEXP (y, 0, 0);
8366 /* Do not associate thread-local symbols with the original
8367 constant pool symbol. */
8370 && CONSTANT_POOL_ADDRESS_P (y)
8371 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
8375 if (offset != NULL_RTX)
8376 y = gen_rtx_PLUS (Pmode, y, offset);
8377 if (!MEM_P (orig_x))
8380 return replace_equiv_address_nv (orig_x, y);
8384 && GET_CODE (orig_x) == LO_SUM
8385 && GET_CODE (XEXP (orig_x, 1)) == CONST)
8387 y = XEXP (XEXP (orig_x, 1), 0);
8388 if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
8389 return XVECEXP (y, 0, 0);
8395 /* Return true if X shouldn't be emitted into the debug info.
8396 The linker doesn't like .toc section references from
8397 .debug_* sections, so reject .toc section symbols. */
8400 rs6000_const_not_ok_for_debug_p (rtx x)
8402 if (GET_CODE (x) == UNSPEC)
8404 if (SYMBOL_REF_P (x)
8405 && CONSTANT_POOL_ADDRESS_P (x))
8407 rtx c = get_pool_constant (x);
8408 machine_mode cmode = get_pool_mode (x);
8409 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
8416 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
8419 rs6000_legitimate_combined_insn (rtx_insn *insn)
8421 int icode = INSN_CODE (insn);
8423 /* Reject creating doloop insns. Combine should not be allowed
8424 to create these for a number of reasons:
8425 1) In a nested loop, if combine creates one of these in an
8426 outer loop and the register allocator happens to allocate ctr
8427 to the outer loop insn, then the inner loop can't use ctr.
8428 Inner loops ought to be more highly optimized.
8429 2) Combine often wants to create one of these from what was
8430 originally a three insn sequence, first combining the three
8431 insns to two, then to ctrsi/ctrdi. When ctrsi/ctrdi is not
8432 allocated ctr, the splitter takes use back to the three insn
8433 sequence. It's better to stop combine at the two insn
8435 3) Faced with not being able to allocate ctr for ctrsi/crtdi
8436 insns, the register allocator sometimes uses floating point
8437 or vector registers for the pseudo. Since ctrsi/ctrdi is a
8438 jump insn and output reloads are not implemented for jumps,
8439 the ctrsi/ctrdi splitters need to handle all possible cases.
8440 That's a pain, and it gets to be seriously difficult when a
8441 splitter that runs after reload needs memory to transfer from
8442 a gpr to fpr. See PR70098 and PR71763 which are not fixed
8443 for the difficult case. It's better to not create problems
8444 in the first place. */
8445 if (icode != CODE_FOR_nothing
8446 && (icode == CODE_FOR_bdz_si
8447 || icode == CODE_FOR_bdz_di
8448 || icode == CODE_FOR_bdnz_si
8449 || icode == CODE_FOR_bdnz_di
8450 || icode == CODE_FOR_bdztf_si
8451 || icode == CODE_FOR_bdztf_di
8452 || icode == CODE_FOR_bdnztf_si
8453 || icode == CODE_FOR_bdnztf_di))
8459 /* Construct the SYMBOL_REF for the tls_get_addr function. */
8461 static GTY(()) rtx rs6000_tls_symbol;
8463 rs6000_tls_get_addr (void)
8465 if (!rs6000_tls_symbol)
8466 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
8468 return rs6000_tls_symbol;
8471 /* Construct the SYMBOL_REF for TLS GOT references. */
8473 static GTY(()) rtx rs6000_got_symbol;
8475 rs6000_got_sym (void)
8477 if (!rs6000_got_symbol)
8479 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8480 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
8481 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
8484 return rs6000_got_symbol;
8487 /* AIX Thread-Local Address support. */
8490 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
8492 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
8496 name = XSTR (addr, 0);
8497 /* Append TLS CSECT qualifier, unless the symbol already is qualified
8498 or the symbol will be in TLS private data section. */
8499 if (name[strlen (name) - 1] != ']'
8500 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
8501 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
8503 tlsname = XALLOCAVEC (char, strlen (name) + 4);
8504 strcpy (tlsname, name);
8506 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
8507 tlsaddr = copy_rtx (addr);
8508 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
8513 /* Place addr into TOC constant pool. */
8514 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
8516 /* Output the TOC entry and create the MEM referencing the value. */
8517 if (constant_pool_expr_p (XEXP (sym, 0))
8518 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
8520 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
8521 mem = gen_const_mem (Pmode, tocref);
8522 set_mem_alias_set (mem, get_TOC_alias_set ());
8527 /* Use global-dynamic for local-dynamic. */
8528 if (model == TLS_MODEL_GLOBAL_DYNAMIC
8529 || model == TLS_MODEL_LOCAL_DYNAMIC)
8531 /* Create new TOC reference for @m symbol. */
8532 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
8533 tlsname = XALLOCAVEC (char, strlen (name) + 1);
8534 strcpy (tlsname, "*LCM");
8535 strcat (tlsname, name + 3);
8536 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
8537 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
8538 tocref = create_TOC_reference (modaddr, NULL_RTX);
8539 rtx modmem = gen_const_mem (Pmode, tocref);
8540 set_mem_alias_set (modmem, get_TOC_alias_set ());
8542 rtx modreg = gen_reg_rtx (Pmode);
8543 emit_insn (gen_rtx_SET (modreg, modmem));
8545 tmpreg = gen_reg_rtx (Pmode);
8546 emit_insn (gen_rtx_SET (tmpreg, mem));
8548 dest = gen_reg_rtx (Pmode);
8550 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
8552 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
8555 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
8556 else if (TARGET_32BIT)
8558 tlsreg = gen_reg_rtx (SImode);
8559 emit_insn (gen_tls_get_tpointer (tlsreg));
8562 tlsreg = gen_rtx_REG (DImode, 13);
8564 /* Load the TOC value into temporary register. */
8565 tmpreg = gen_reg_rtx (Pmode);
8566 emit_insn (gen_rtx_SET (tmpreg, mem));
8567 set_unique_reg_note (get_last_insn (), REG_EQUAL,
8568 gen_rtx_MINUS (Pmode, addr, tlsreg));
8570 /* Add TOC symbol value to TLS pointer. */
8571 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
8576 /* Output arg setup instructions for a !TARGET_TLS_MARKERS
8577 __tls_get_addr call. */
8580 rs6000_output_tlsargs (rtx *operands)
8582 /* Set up operands for output_asm_insn, without modifying OPERANDS. */
8585 /* The set dest of the call, ie. r3, which is also the first arg reg. */
8586 op[0] = operands[0];
8587 /* The TLS symbol from global_tlsarg stashed as CALL operand 2. */
8588 op[1] = XVECEXP (operands[2], 0, 0);
8589 if (XINT (operands[2], 1) == UNSPEC_TLSGD)
8591 /* The GOT register. */
8592 op[2] = XVECEXP (operands[2], 0, 1);
8593 if (TARGET_CMODEL != CMODEL_SMALL)
8594 output_asm_insn ("addis %0,%2,%1@got@tlsgd@ha\n\t"
8595 "addi %0,%0,%1@got@tlsgd@l", op);
8597 output_asm_insn ("addi %0,%2,%1@got@tlsgd", op);
8599 else if (XINT (operands[2], 1) == UNSPEC_TLSLD)
8601 if (TARGET_CMODEL != CMODEL_SMALL)
8602 output_asm_insn ("addis %0,%1,%&@got@tlsld@ha\n\t"
8603 "addi %0,%0,%&@got@tlsld@l", op);
8605 output_asm_insn ("addi %0,%1,%&@got@tlsld", op);
8611 /* Passes the tls arg value for global dynamic and local dynamic
8612 emit_library_call_value in rs6000_legitimize_tls_address to
8613 rs6000_call_aix and rs6000_call_sysv. This is used to emit the
8614 marker relocs put on __tls_get_addr calls. */
8615 static rtx global_tlsarg;
8617 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
8618 this (thread-local) address. */
8621 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
8626 return rs6000_legitimize_tls_address_aix (addr, model);
8628 dest = gen_reg_rtx (Pmode);
8629 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
8635 tlsreg = gen_rtx_REG (Pmode, 13);
8636 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
8640 tlsreg = gen_rtx_REG (Pmode, 2);
8641 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
8645 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
8649 tmp = gen_reg_rtx (Pmode);
8652 tlsreg = gen_rtx_REG (Pmode, 13);
8653 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
8657 tlsreg = gen_rtx_REG (Pmode, 2);
8658 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
8662 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
8664 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
8669 rtx got, tga, tmp1, tmp2;
8671 /* We currently use relocations like @got@tlsgd for tls, which
8672 means the linker will handle allocation of tls entries, placing
8673 them in the .got section. So use a pointer to the .got section,
8674 not one to secondary TOC sections used by 64-bit -mminimal-toc,
8675 or to secondary GOT sections used by 32-bit -fPIC. */
8677 got = gen_rtx_REG (Pmode, 2);
8681 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
8684 rtx gsym = rs6000_got_sym ();
8685 got = gen_reg_rtx (Pmode);
8687 rs6000_emit_move (got, gsym, Pmode);
8692 tmp1 = gen_reg_rtx (Pmode);
8693 tmp2 = gen_reg_rtx (Pmode);
8694 mem = gen_const_mem (Pmode, tmp1);
8695 lab = gen_label_rtx ();
8696 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
8697 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
8698 if (TARGET_LINK_STACK)
8699 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
8700 emit_move_insn (tmp2, mem);
8701 rtx_insn *last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
8702 set_unique_reg_note (last, REG_EQUAL, gsym);
8707 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
8709 rtx arg = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addr, got),
8711 tga = rs6000_tls_get_addr ();
8712 global_tlsarg = arg;
8713 if (TARGET_TLS_MARKERS)
8715 rtx argreg = gen_rtx_REG (Pmode, 3);
8716 emit_insn (gen_rtx_SET (argreg, arg));
8717 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
8721 emit_library_call_value (tga, dest, LCT_CONST, Pmode);
8722 global_tlsarg = NULL_RTX;
8724 /* Make a note so that the result of this call can be CSEd. */
8725 rtvec vec = gen_rtvec (1, copy_rtx (arg));
8726 rtx uns = gen_rtx_UNSPEC (Pmode, vec, UNSPEC_TLS_GET_ADDR);
8727 set_unique_reg_note (get_last_insn (), REG_EQUAL, uns);
8729 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
8731 rtx arg = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got), UNSPEC_TLSLD);
8732 tga = rs6000_tls_get_addr ();
8733 tmp1 = gen_reg_rtx (Pmode);
8734 global_tlsarg = arg;
8735 if (TARGET_TLS_MARKERS)
8737 rtx argreg = gen_rtx_REG (Pmode, 3);
8738 emit_insn (gen_rtx_SET (argreg, arg));
8739 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
8743 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode);
8744 global_tlsarg = NULL_RTX;
8746 /* Make a note so that the result of this call can be CSEd. */
8747 rtvec vec = gen_rtvec (1, copy_rtx (arg));
8748 rtx uns = gen_rtx_UNSPEC (Pmode, vec, UNSPEC_TLS_GET_ADDR);
8749 set_unique_reg_note (get_last_insn (), REG_EQUAL, uns);
8751 if (rs6000_tls_size == 16)
8754 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
8756 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
8758 else if (rs6000_tls_size == 32)
8760 tmp2 = gen_reg_rtx (Pmode);
8762 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
8764 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
8767 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
8769 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
8773 tmp2 = gen_reg_rtx (Pmode);
8775 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
8777 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
8779 insn = gen_rtx_SET (dest, gen_rtx_PLUS (Pmode, tmp2, tmp1));
8785 /* IE, or 64-bit offset LE. */
8786 tmp2 = gen_reg_rtx (Pmode);
8788 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
8790 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
8793 insn = gen_tls_tls_64 (dest, tmp2, addr);
8795 insn = gen_tls_tls_32 (dest, tmp2, addr);
8803 /* Only create the global variable for the stack protect guard if we are using
8804 the global flavor of that guard. */
8806 rs6000_init_stack_protect_guard (void)
8808 if (rs6000_stack_protector_guard == SSP_GLOBAL)
8809 return default_stack_protect_guard ();
8814 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
8817 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
8819 if (GET_CODE (x) == HIGH
8820 && GET_CODE (XEXP (x, 0)) == UNSPEC)
8823 /* A TLS symbol in the TOC cannot contain a sum. */
8824 if (GET_CODE (x) == CONST
8825 && GET_CODE (XEXP (x, 0)) == PLUS
8826 && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
8827 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
8830 /* Do not place an ELF TLS symbol in the constant pool. */
8831 return TARGET_ELF && tls_referenced_p (x);
8834 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
8835 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
8836 can be addressed relative to the toc pointer. */
8839 use_toc_relative_ref (rtx sym, machine_mode mode)
8841 return ((constant_pool_expr_p (sym)
8842 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
8843 get_pool_mode (sym)))
8844 || (TARGET_CMODEL == CMODEL_MEDIUM
8845 && SYMBOL_REF_LOCAL_P (sym)
8846 && GET_MODE_SIZE (mode) <= POWERPC64_TOC_POINTER_ALIGNMENT));
8849 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
8850 that is a valid memory address for an instruction.
8851 The MODE argument is the machine mode for the MEM expression
8852 that wants to use this address.
8854 On the RS/6000, there are four valid address: a SYMBOL_REF that
8855 refers to a constant pool entry of an address (or the sum of it
8856 plus a constant), a short (16-bit signed) constant plus a register,
8857 the sum of two registers, or a register indirect, possibly with an
8858 auto-increment. For DFmode, DDmode and DImode with a constant plus
8859 register, we must ensure that both words are addressable or PowerPC64
8860 with offset word aligned.
8862 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
8863 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
8864 because adjacent memory cells are accessed by adding word-sized offsets
8865 during assembly output. */
8867 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
8869 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
8870 bool quad_offset_p = mode_supports_dq_form (mode);
8872 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
8873 if (VECTOR_MEM_ALTIVEC_P (mode)
8874 && GET_CODE (x) == AND
8875 && CONST_INT_P (XEXP (x, 1))
8876 && INTVAL (XEXP (x, 1)) == -16)
8879 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
8881 if (legitimate_indirect_address_p (x, reg_ok_strict))
8884 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
8885 && mode_supports_pre_incdec_p (mode)
8886 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
8888 /* Handle restricted vector d-form offsets in ISA 3.0. */
8891 if (quad_address_p (x, mode, reg_ok_strict))
8894 else if (virtual_stack_registers_memory_p (x))
8897 else if (reg_offset_p)
8899 if (legitimate_small_data_p (mode, x))
8901 if (legitimate_constant_pool_address_p (x, mode,
8902 reg_ok_strict || lra_in_progress))
8906 /* For TImode, if we have TImode in VSX registers, only allow register
8907 indirect addresses. This will allow the values to go in either GPRs
8908 or VSX registers without reloading. The vector types would tend to
8909 go into VSX registers, so we allow REG+REG, while TImode seems
8910 somewhat split, in that some uses are GPR based, and some VSX based. */
8911 /* FIXME: We could loosen this by changing the following to
8912 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX)
8913 but currently we cannot allow REG+REG addressing for TImode. See
8914 PR72827 for complete details on how this ends up hoodwinking DSE. */
8915 if (mode == TImode && TARGET_VSX)
8917 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
8920 && GET_CODE (x) == PLUS
8921 && REG_P (XEXP (x, 0))
8922 && (XEXP (x, 0) == virtual_stack_vars_rtx
8923 || XEXP (x, 0) == arg_pointer_rtx)
8924 && CONST_INT_P (XEXP (x, 1)))
8926 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
8928 if (!FLOAT128_2REG_P (mode)
8929 && (TARGET_HARD_FLOAT
8931 || (mode != DFmode && mode != DDmode))
8932 && (TARGET_POWERPC64 || mode != DImode)
8933 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
8935 && !avoiding_indexed_address_p (mode)
8936 && legitimate_indexed_address_p (x, reg_ok_strict))
8938 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
8939 && mode_supports_pre_modify_p (mode)
8940 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
8941 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
8942 reg_ok_strict, false)
8943 || (!avoiding_indexed_address_p (mode)
8944 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
8945 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
8947 if (reg_offset_p && !quad_offset_p
8948 && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
8953 /* Debug version of rs6000_legitimate_address_p. */
8955 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
8958 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
8960 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
8961 "strict = %d, reload = %s, code = %s\n",
8962 ret ? "true" : "false",
8963 GET_MODE_NAME (mode),
8965 (reload_completed ? "after" : "before"),
8966 GET_RTX_NAME (GET_CODE (x)));
8972 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
8975 rs6000_mode_dependent_address_p (const_rtx addr,
8976 addr_space_t as ATTRIBUTE_UNUSED)
8978 return rs6000_mode_dependent_address_ptr (addr);
8981 /* Go to LABEL if ADDR (a legitimate address expression)
8982 has an effect that depends on the machine mode it is used for.
8984 On the RS/6000 this is true of all integral offsets (since AltiVec
8985 and VSX modes don't allow them) or is a pre-increment or decrement.
8987 ??? Except that due to conceptual problems in offsettable_address_p
8988 we can't really report the problems of integral offsets. So leave
8989 this assuming that the adjustable offset must be valid for the
8990 sub-words of a TFmode operand, which is what we had before. */
8993 rs6000_mode_dependent_address (const_rtx addr)
8995 switch (GET_CODE (addr))
8998 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
8999 is considered a legitimate address before reload, so there
9000 are no offset restrictions in that case. Note that this
9001 condition is safe in strict mode because any address involving
9002 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9003 been rejected as illegitimate. */
9004 if (XEXP (addr, 0) != virtual_stack_vars_rtx
9005 && XEXP (addr, 0) != arg_pointer_rtx
9006 && CONST_INT_P (XEXP (addr, 1)))
9008 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
9009 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
9014 /* Anything in the constant pool is sufficiently aligned that
9015 all bytes have the same high part address. */
9016 return !legitimate_constant_pool_address_p (addr, QImode, false);
9018 /* Auto-increment cases are now treated generically in recog.c. */
9020 return TARGET_UPDATE;
9022 /* AND is only allowed in Altivec loads. */
9033 /* Debug version of rs6000_mode_dependent_address. */
9035 rs6000_debug_mode_dependent_address (const_rtx addr)
9037 bool ret = rs6000_mode_dependent_address (addr);
9039 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
9040 ret ? "true" : "false");
9046 /* Implement FIND_BASE_TERM. */
9049 rs6000_find_base_term (rtx op)
9054 if (GET_CODE (base) == CONST)
9055 base = XEXP (base, 0);
9056 if (GET_CODE (base) == PLUS)
9057 base = XEXP (base, 0);
9058 if (GET_CODE (base) == UNSPEC)
9059 switch (XINT (base, 1))
9062 case UNSPEC_MACHOPIC_OFFSET:
9063 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9064 for aliasing purposes. */
9065 return XVECEXP (base, 0, 0);
9071 /* More elaborate version of recog's offsettable_memref_p predicate
9072 that works around the ??? note of rs6000_mode_dependent_address.
9073 In particular it accepts
9075 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9077 in 32-bit mode, that the recog predicate rejects. */
9080 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
9087 /* First mimic offsettable_memref_p. */
9088 if (offsettable_address_p (strict, GET_MODE (op), XEXP (op, 0)))
9091 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9092 the latter predicate knows nothing about the mode of the memory
9093 reference and, therefore, assumes that it is the largest supported
9094 mode (TFmode). As a consequence, legitimate offsettable memory
9095 references are rejected. rs6000_legitimate_offset_address_p contains
9096 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9097 at least with a little bit of help here given that we know the
9098 actual registers used. */
9099 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
9100 || GET_MODE_SIZE (reg_mode) == 4);
9101 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
9102 strict, worst_case);
9105 /* Determine the reassociation width to be used in reassociate_bb.
9106 This takes into account how many parallel operations we
9107 can actually do of a given type, and also the latency.
9111 vect add/sub/mul 2/cycle
9112 fp add/sub/mul 2/cycle
9117 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED,
9120 switch (rs6000_tune)
9122 case PROCESSOR_POWER8:
9123 case PROCESSOR_POWER9:
9124 if (DECIMAL_FLOAT_MODE_P (mode))
9126 if (VECTOR_MODE_P (mode))
9128 if (INTEGRAL_MODE_P (mode))
9130 if (FLOAT_MODE_P (mode))
9139 /* Change register usage conditional on target flags. */
9141 rs6000_conditional_register_usage (void)
9145 if (TARGET_DEBUG_TARGET)
9146 fprintf (stderr, "rs6000_conditional_register_usage called\n");
9148 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
9150 fixed_regs[13] = call_used_regs[13]
9151 = call_really_used_regs[13] = 1;
9153 /* Conditionally disable FPRs. */
9154 if (TARGET_SOFT_FLOAT)
9155 for (i = 32; i < 64; i++)
9156 fixed_regs[i] = call_used_regs[i]
9157 = call_really_used_regs[i] = 1;
9159 /* The TOC register is not killed across calls in a way that is
9160 visible to the compiler. */
9161 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9162 call_really_used_regs[2] = 0;
9164 if (DEFAULT_ABI == ABI_V4 && flag_pic == 2)
9165 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9167 if (DEFAULT_ABI == ABI_V4 && flag_pic == 1)
9168 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9169 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9170 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9172 if (DEFAULT_ABI == ABI_DARWIN && flag_pic)
9173 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9174 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9175 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9177 if (TARGET_TOC && TARGET_MINIMAL_TOC)
9178 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
9179 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9181 if (!TARGET_ALTIVEC && !TARGET_VSX)
9183 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
9184 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9185 call_really_used_regs[VRSAVE_REGNO] = 1;
9188 if (TARGET_ALTIVEC || TARGET_VSX)
9189 global_regs[VSCR_REGNO] = 1;
9191 if (TARGET_ALTIVEC_ABI)
9193 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
9194 call_used_regs[i] = call_really_used_regs[i] = 1;
9196 /* AIX reserves VR20:31 in non-extended ABI mode. */
9198 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
9199 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
9204 /* Output insns to set DEST equal to the constant SOURCE as a series of
9205 lis, ori and shl instructions and return TRUE. */
9208 rs6000_emit_set_const (rtx dest, rtx source)
9210 machine_mode mode = GET_MODE (dest);
9215 gcc_checking_assert (CONST_INT_P (source));
9216 c = INTVAL (source);
9221 emit_insn (gen_rtx_SET (dest, source));
9225 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
9227 emit_insn (gen_rtx_SET (copy_rtx (temp),
9228 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
9229 emit_insn (gen_rtx_SET (dest,
9230 gen_rtx_IOR (SImode, copy_rtx (temp),
9231 GEN_INT (c & 0xffff))));
9235 if (!TARGET_POWERPC64)
9239 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
9241 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
9243 emit_move_insn (hi, GEN_INT (c >> 32));
9244 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
9245 emit_move_insn (lo, GEN_INT (c));
9248 rs6000_emit_set_long_const (dest, c);
9255 insn = get_last_insn ();
9256 set = single_set (insn);
9257 if (! CONSTANT_P (SET_SRC (set)))
9258 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
9263 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9264 Output insns to set DEST equal to the constant C as a series of
9265 lis, ori and shl instructions. */
9268 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
9271 HOST_WIDE_INT ud1, ud2, ud3, ud4;
9281 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
9282 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
9283 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
9285 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
9286 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
9288 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9290 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9291 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9293 emit_move_insn (dest,
9294 gen_rtx_IOR (DImode, copy_rtx (temp),
9297 else if (ud3 == 0 && ud4 == 0)
9299 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9301 gcc_assert (ud2 & 0x8000);
9302 emit_move_insn (copy_rtx (temp),
9303 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
9305 emit_move_insn (copy_rtx (temp),
9306 gen_rtx_IOR (DImode, copy_rtx (temp),
9308 emit_move_insn (dest,
9309 gen_rtx_ZERO_EXTEND (DImode,
9310 gen_lowpart (SImode,
9313 else if ((ud4 == 0xffff && (ud3 & 0x8000))
9314 || (ud4 == 0 && ! (ud3 & 0x8000)))
9316 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9318 emit_move_insn (copy_rtx (temp),
9319 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
9321 emit_move_insn (copy_rtx (temp),
9322 gen_rtx_IOR (DImode, copy_rtx (temp),
9324 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9325 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9328 emit_move_insn (dest,
9329 gen_rtx_IOR (DImode, copy_rtx (temp),
9334 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
9336 emit_move_insn (copy_rtx (temp),
9337 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
9339 emit_move_insn (copy_rtx (temp),
9340 gen_rtx_IOR (DImode, copy_rtx (temp),
9343 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
9344 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
9347 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
9348 gen_rtx_IOR (DImode, copy_rtx (temp),
9349 GEN_INT (ud2 << 16)));
9351 emit_move_insn (dest,
9352 gen_rtx_IOR (DImode, copy_rtx (temp),
9357 /* Helper for the following. Get rid of [r+r] memory refs
9358 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
9361 rs6000_eliminate_indexed_memrefs (rtx operands[2])
9363 if (MEM_P (operands[0])
9364 && !REG_P (XEXP (operands[0], 0))
9365 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
9366 GET_MODE (operands[0]), false))
9368 = replace_equiv_address (operands[0],
9369 copy_addr_to_reg (XEXP (operands[0], 0)));
9371 if (MEM_P (operands[1])
9372 && !REG_P (XEXP (operands[1], 0))
9373 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
9374 GET_MODE (operands[1]), false))
9376 = replace_equiv_address (operands[1],
9377 copy_addr_to_reg (XEXP (operands[1], 0)));
9380 /* Generate a vector of constants to permute MODE for a little-endian
9381 storage operation by swapping the two halves of a vector. */
9383 rs6000_const_vec (machine_mode mode)
9411 v = rtvec_alloc (subparts);
9413 for (i = 0; i < subparts / 2; ++i)
9414 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
9415 for (i = subparts / 2; i < subparts; ++i)
9416 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
9421 /* Emit an lxvd2x, stxvd2x, or xxpermdi instruction for a VSX load or
9424 rs6000_emit_le_vsx_permute (rtx dest, rtx source, machine_mode mode)
9426 /* Scalar permutations are easier to express in integer modes rather than
9427 floating-point modes, so cast them here. We use V1TImode instead
9428 of TImode to ensure that the values don't go through GPRs. */
9429 if (FLOAT128_VECTOR_P (mode))
9431 dest = gen_lowpart (V1TImode, dest);
9432 source = gen_lowpart (V1TImode, source);
9436 /* Use ROTATE instead of VEC_SELECT if the mode contains only a single
9438 if (mode == TImode || mode == V1TImode)
9439 emit_insn (gen_rtx_SET (dest, gen_rtx_ROTATE (mode, source,
9443 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
9444 emit_insn (gen_rtx_SET (dest, gen_rtx_VEC_SELECT (mode, source, par)));
9448 /* Emit a little-endian load from vector memory location SOURCE to VSX
9449 register DEST in mode MODE. The load is done with two permuting
9450 insn's that represent an lxvd2x and xxpermdi. */
9452 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
9454 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
9456 if (mode == TImode || mode == V1TImode)
9459 dest = gen_lowpart (V2DImode, dest);
9460 source = adjust_address (source, V2DImode, 0);
9463 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
9464 rs6000_emit_le_vsx_permute (tmp, source, mode);
9465 rs6000_emit_le_vsx_permute (dest, tmp, mode);
9468 /* Emit a little-endian store to vector memory location DEST from VSX
9469 register SOURCE in mode MODE. The store is done with two permuting
9470 insn's that represent an xxpermdi and an stxvd2x. */
9472 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
9474 /* This should never be called during or after LRA, because it does
9475 not re-permute the source register. It is intended only for use
9477 gcc_assert (!lra_in_progress && !reload_completed);
9479 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
9481 if (mode == TImode || mode == V1TImode)
9484 dest = adjust_address (dest, V2DImode, 0);
9485 source = gen_lowpart (V2DImode, source);
9488 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
9489 rs6000_emit_le_vsx_permute (tmp, source, mode);
9490 rs6000_emit_le_vsx_permute (dest, tmp, mode);
9493 /* Emit a sequence representing a little-endian VSX load or store,
9494 moving data from SOURCE to DEST in mode MODE. This is done
9495 separately from rs6000_emit_move to ensure it is called only
9496 during expand. LE VSX loads and stores introduced later are
9497 handled with a split. The expand-time RTL generation allows
9498 us to optimize away redundant pairs of register-permutes. */
9500 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
9502 gcc_assert (!BYTES_BIG_ENDIAN
9503 && VECTOR_MEM_VSX_P (mode)
9504 && !TARGET_P9_VECTOR
9505 && !gpr_or_gpr_p (dest, source)
9506 && (MEM_P (source) ^ MEM_P (dest)));
9510 gcc_assert (REG_P (dest) || SUBREG_P (dest));
9511 rs6000_emit_le_vsx_load (dest, source, mode);
9515 if (!REG_P (source))
9516 source = force_reg (mode, source);
9517 rs6000_emit_le_vsx_store (dest, source, mode);
9521 /* Return whether a SFmode or SImode move can be done without converting one
9522 mode to another. This arrises when we have:
9524 (SUBREG:SF (REG:SI ...))
9525 (SUBREG:SI (REG:SF ...))
9527 and one of the values is in a floating point/vector register, where SFmode
9528 scalars are stored in DFmode format. */
9531 valid_sf_si_move (rtx dest, rtx src, machine_mode mode)
9533 if (TARGET_ALLOW_SF_SUBREG)
9536 if (mode != SFmode && GET_MODE_CLASS (mode) != MODE_INT)
9539 if (!SUBREG_P (src) || !sf_subreg_operand (src, mode))
9542 /*. Allow (set (SUBREG:SI (REG:SF)) (SUBREG:SI (REG:SF))). */
9543 if (SUBREG_P (dest))
9545 rtx dest_subreg = SUBREG_REG (dest);
9546 rtx src_subreg = SUBREG_REG (src);
9547 return GET_MODE (dest_subreg) == GET_MODE (src_subreg);
9554 /* Helper function to change moves with:
9556 (SUBREG:SF (REG:SI)) and
9557 (SUBREG:SI (REG:SF))
9559 into separate UNSPEC insns. In the PowerPC architecture, scalar SFmode
9560 values are stored as DFmode values in the VSX registers. We need to convert
9561 the bits before we can use a direct move or operate on the bits in the
9562 vector register as an integer type.
9564 Skip things like (set (SUBREG:SI (...) (SUBREG:SI (...)). */
9567 rs6000_emit_move_si_sf_subreg (rtx dest, rtx source, machine_mode mode)
9569 if (TARGET_DIRECT_MOVE_64BIT && !reload_completed
9570 && (!SUBREG_P (dest) || !sf_subreg_operand (dest, mode))
9571 && SUBREG_P (source) && sf_subreg_operand (source, mode))
9573 rtx inner_source = SUBREG_REG (source);
9574 machine_mode inner_mode = GET_MODE (inner_source);
9576 if (mode == SImode && inner_mode == SFmode)
9578 emit_insn (gen_movsi_from_sf (dest, inner_source));
9582 if (mode == SFmode && inner_mode == SImode)
9584 emit_insn (gen_movsf_from_si (dest, inner_source));
9592 /* Emit a move from SOURCE to DEST in mode MODE. */
9594 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
9598 operands[1] = source;
9600 if (TARGET_DEBUG_ADDR)
9603 "\nrs6000_emit_move: mode = %s, lra_in_progress = %d, "
9604 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
9605 GET_MODE_NAME (mode),
9608 can_create_pseudo_p ());
9610 fprintf (stderr, "source:\n");
9614 /* Check that we get CONST_WIDE_INT only when we should. */
9615 if (CONST_WIDE_INT_P (operands[1])
9616 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9619 #ifdef HAVE_AS_GNU_ATTRIBUTE
9620 /* If we use a long double type, set the flags in .gnu_attribute that say
9621 what the long double type is. This is to allow the linker's warning
9622 message for the wrong long double to be useful, even if the function does
9623 not do a call (for example, doing a 128-bit add on power9 if the long
9624 double type is IEEE 128-bit. Do not set this if __ibm128 or __floa128 are
9625 used if they aren't the default long dobule type. */
9626 if (rs6000_gnu_attr && (HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT))
9628 if (TARGET_LONG_DOUBLE_128 && (mode == TFmode || mode == TCmode))
9629 rs6000_passes_float = rs6000_passes_long_double = true;
9631 else if (!TARGET_LONG_DOUBLE_128 && (mode == DFmode || mode == DCmode))
9632 rs6000_passes_float = rs6000_passes_long_double = true;
9636 /* See if we need to special case SImode/SFmode SUBREG moves. */
9637 if ((mode == SImode || mode == SFmode) && SUBREG_P (source)
9638 && rs6000_emit_move_si_sf_subreg (dest, source, mode))
9641 /* Check if GCC is setting up a block move that will end up using FP
9642 registers as temporaries. We must make sure this is acceptable. */
9643 if (MEM_P (operands[0])
9644 && MEM_P (operands[1])
9646 && (rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[0]))
9647 || rs6000_slow_unaligned_access (DImode, MEM_ALIGN (operands[1])))
9648 && ! (rs6000_slow_unaligned_access (SImode,
9649 (MEM_ALIGN (operands[0]) > 32
9650 ? 32 : MEM_ALIGN (operands[0])))
9651 || rs6000_slow_unaligned_access (SImode,
9652 (MEM_ALIGN (operands[1]) > 32
9653 ? 32 : MEM_ALIGN (operands[1]))))
9654 && ! MEM_VOLATILE_P (operands [0])
9655 && ! MEM_VOLATILE_P (operands [1]))
9657 emit_move_insn (adjust_address (operands[0], SImode, 0),
9658 adjust_address (operands[1], SImode, 0));
9659 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
9660 adjust_address (copy_rtx (operands[1]), SImode, 4));
9664 if (can_create_pseudo_p () && MEM_P (operands[0])
9665 && !gpc_reg_operand (operands[1], mode))
9666 operands[1] = force_reg (mode, operands[1]);
9668 /* Recognize the case where operand[1] is a reference to thread-local
9669 data and load its address to a register. */
9670 if (tls_referenced_p (operands[1]))
9672 enum tls_model model;
9673 rtx tmp = operands[1];
9676 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
9678 addend = XEXP (XEXP (tmp, 0), 1);
9679 tmp = XEXP (XEXP (tmp, 0), 0);
9682 gcc_assert (SYMBOL_REF_P (tmp));
9683 model = SYMBOL_REF_TLS_MODEL (tmp);
9684 gcc_assert (model != 0);
9686 tmp = rs6000_legitimize_tls_address (tmp, model);
9689 tmp = gen_rtx_PLUS (mode, tmp, addend);
9690 tmp = force_operand (tmp, operands[0]);
9695 /* 128-bit constant floating-point values on Darwin should really be loaded
9696 as two parts. However, this premature splitting is a problem when DFmode
9697 values can go into Altivec registers. */
9698 if (TARGET_MACHO && CONST_DOUBLE_P (operands[1]) && FLOAT128_IBM_P (mode)
9699 && !reg_addr[DFmode].scalar_in_vmx_p)
9701 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
9702 simplify_gen_subreg (DFmode, operands[1], mode, 0),
9704 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
9705 GET_MODE_SIZE (DFmode)),
9706 simplify_gen_subreg (DFmode, operands[1], mode,
9707 GET_MODE_SIZE (DFmode)),
9712 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
9713 p1:SD) if p1 is not of floating point class and p0 is spilled as
9714 we can have no analogous movsd_store for this. */
9715 if (lra_in_progress && mode == DDmode
9716 && REG_P (operands[0]) && !HARD_REGISTER_P (operands[0])
9717 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
9718 && SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))
9719 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
9722 int regno = REGNO (SUBREG_REG (operands[1]));
9724 if (!HARD_REGISTER_NUM_P (regno))
9726 cl = reg_preferred_class (regno);
9727 regno = reg_renumber[regno];
9729 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
9731 if (regno >= 0 && ! FP_REGNO_P (regno))
9734 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
9735 operands[1] = SUBREG_REG (operands[1]);
9740 && REG_P (operands[0]) && !HARD_REGISTER_P (operands[0])
9741 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
9742 && (REG_P (operands[1])
9743 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))))
9745 int regno = reg_or_subregno (operands[1]);
9748 if (!HARD_REGISTER_NUM_P (regno))
9750 cl = reg_preferred_class (regno);
9751 gcc_assert (cl != NO_REGS);
9752 regno = reg_renumber[regno];
9754 regno = ira_class_hard_regs[cl][0];
9756 if (FP_REGNO_P (regno))
9758 if (GET_MODE (operands[0]) != DDmode)
9759 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
9760 emit_insn (gen_movsd_store (operands[0], operands[1]));
9762 else if (INT_REGNO_P (regno))
9763 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
9768 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
9769 p:DD)) if p0 is not of floating point class and p1 is spilled as
9770 we can have no analogous movsd_load for this. */
9771 if (lra_in_progress && mode == DDmode
9772 && SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))
9773 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
9774 && REG_P (operands[1]) && !HARD_REGISTER_P (operands[1])
9775 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
9778 int regno = REGNO (SUBREG_REG (operands[0]));
9780 if (!HARD_REGISTER_NUM_P (regno))
9782 cl = reg_preferred_class (regno);
9783 regno = reg_renumber[regno];
9785 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
9787 if (regno >= 0 && ! FP_REGNO_P (regno))
9790 operands[0] = SUBREG_REG (operands[0]);
9791 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
9796 && (REG_P (operands[0])
9797 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))))
9798 && REG_P (operands[1]) && !HARD_REGISTER_P (operands[1])
9799 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
9801 int regno = reg_or_subregno (operands[0]);
9804 if (!HARD_REGISTER_NUM_P (regno))
9806 cl = reg_preferred_class (regno);
9807 gcc_assert (cl != NO_REGS);
9808 regno = reg_renumber[regno];
9810 regno = ira_class_hard_regs[cl][0];
9812 if (FP_REGNO_P (regno))
9814 if (GET_MODE (operands[1]) != DDmode)
9815 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
9816 emit_insn (gen_movsd_load (operands[0], operands[1]));
9818 else if (INT_REGNO_P (regno))
9819 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
9825 /* FIXME: In the long term, this switch statement should go away
9826 and be replaced by a sequence of tests based on things like
9832 if (CONSTANT_P (operands[1])
9833 && !CONST_INT_P (operands[1]))
9834 operands[1] = force_const_mem (mode, operands[1]);
9841 if (FLOAT128_2REG_P (mode))
9842 rs6000_eliminate_indexed_memrefs (operands);
9849 if (CONSTANT_P (operands[1])
9850 && ! easy_fp_constant (operands[1], mode))
9851 operands[1] = force_const_mem (mode, operands[1]);
9861 if (CONSTANT_P (operands[1])
9862 && !easy_vector_constant (operands[1], mode))
9863 operands[1] = force_const_mem (mode, operands[1]);
9868 /* Use default pattern for address of ELF small data */
9871 && DEFAULT_ABI == ABI_V4
9872 && (SYMBOL_REF_P (operands[1])
9873 || GET_CODE (operands[1]) == CONST)
9874 && small_data_operand (operands[1], mode))
9876 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9880 if (DEFAULT_ABI == ABI_V4
9881 && mode == Pmode && mode == SImode
9882 && flag_pic == 1 && got_operand (operands[1], mode))
9884 emit_insn (gen_movsi_got (operands[0], operands[1]));
9888 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
9892 && CONSTANT_P (operands[1])
9893 && GET_CODE (operands[1]) != HIGH
9894 && !CONST_INT_P (operands[1]))
9896 rtx target = (!can_create_pseudo_p ()
9898 : gen_reg_rtx (mode));
9900 /* If this is a function address on -mcall-aixdesc,
9901 convert it to the address of the descriptor. */
9902 if (DEFAULT_ABI == ABI_AIX
9903 && SYMBOL_REF_P (operands[1])
9904 && XSTR (operands[1], 0)[0] == '.')
9906 const char *name = XSTR (operands[1], 0);
9908 while (*name == '.')
9910 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
9911 CONSTANT_POOL_ADDRESS_P (new_ref)
9912 = CONSTANT_POOL_ADDRESS_P (operands[1]);
9913 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
9914 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
9915 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
9916 operands[1] = new_ref;
9919 if (DEFAULT_ABI == ABI_DARWIN)
9922 if (MACHO_DYNAMIC_NO_PIC_P)
9924 /* Take care of any required data indirection. */
9925 operands[1] = rs6000_machopic_legitimize_pic_address (
9926 operands[1], mode, operands[0]);
9927 if (operands[0] != operands[1])
9928 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9932 emit_insn (gen_macho_high (target, operands[1]));
9933 emit_insn (gen_macho_low (operands[0], target, operands[1]));
9937 emit_insn (gen_elf_high (target, operands[1]));
9938 emit_insn (gen_elf_low (operands[0], target, operands[1]));
9942 /* If this is a SYMBOL_REF that refers to a constant pool entry,
9943 and we have put it in the TOC, we just need to make a TOC-relative
9946 && SYMBOL_REF_P (operands[1])
9947 && use_toc_relative_ref (operands[1], mode))
9948 operands[1] = create_TOC_reference (operands[1], operands[0]);
9949 else if (mode == Pmode
9950 && CONSTANT_P (operands[1])
9951 && GET_CODE (operands[1]) != HIGH
9952 && ((REG_P (operands[0])
9953 && FP_REGNO_P (REGNO (operands[0])))
9954 || !CONST_INT_P (operands[1])
9955 || (num_insns_constant (operands[1], mode)
9956 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
9957 && !toc_relative_expr_p (operands[1], false, NULL, NULL)
9958 && (TARGET_CMODEL == CMODEL_SMALL
9959 || can_create_pseudo_p ()
9960 || (REG_P (operands[0])
9961 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
9965 /* Darwin uses a special PIC legitimizer. */
9966 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
9969 rs6000_machopic_legitimize_pic_address (operands[1], mode,
9971 if (operands[0] != operands[1])
9972 emit_insn (gen_rtx_SET (operands[0], operands[1]));
9977 /* If we are to limit the number of things we put in the TOC and
9978 this is a symbol plus a constant we can add in one insn,
9979 just put the symbol in the TOC and add the constant. */
9980 if (GET_CODE (operands[1]) == CONST
9981 && TARGET_NO_SUM_IN_TOC
9982 && GET_CODE (XEXP (operands[1], 0)) == PLUS
9983 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
9984 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
9985 || SYMBOL_REF_P (XEXP (XEXP (operands[1], 0), 0)))
9986 && ! side_effects_p (operands[0]))
9989 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
9990 rtx other = XEXP (XEXP (operands[1], 0), 1);
9992 sym = force_reg (mode, sym);
9993 emit_insn (gen_add3_insn (operands[0], sym, other));
9997 operands[1] = force_const_mem (mode, operands[1]);
10000 && SYMBOL_REF_P (XEXP (operands[1], 0))
10001 && use_toc_relative_ref (XEXP (operands[1], 0), mode))
10003 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
10005 operands[1] = gen_const_mem (mode, tocref);
10006 set_mem_alias_set (operands[1], get_TOC_alias_set ());
10012 if (!VECTOR_MEM_VSX_P (TImode))
10013 rs6000_eliminate_indexed_memrefs (operands);
10017 rs6000_eliminate_indexed_memrefs (operands);
10021 fatal_insn ("bad move", gen_rtx_SET (dest, source));
10024 /* Above, we may have called force_const_mem which may have returned
10025 an invalid address. If we can, fix this up; otherwise, reload will
10026 have to deal with it. */
10027 if (MEM_P (operands[1]))
10028 operands[1] = validize_mem (operands[1]);
10030 emit_insn (gen_rtx_SET (operands[0], operands[1]));
10033 /* Nonzero if we can use a floating-point register to pass this arg. */
10034 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10035 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10036 && (CUM)->fregno <= FP_ARG_MAX_REG \
10037 && TARGET_HARD_FLOAT)
10039 /* Nonzero if we can use an AltiVec register to pass this arg. */
10040 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10041 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10042 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10043 && TARGET_ALTIVEC_ABI \
10046 /* Walk down the type tree of TYPE counting consecutive base elements.
10047 If *MODEP is VOIDmode, then set it to the first valid floating point
10048 or vector type. If a non-floating point or vector type is found, or
10049 if a floating point or vector type that doesn't match a non-VOIDmode
10050 *MODEP is found, then return -1, otherwise return the count in the
10054 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
10057 HOST_WIDE_INT size;
10059 switch (TREE_CODE (type))
10062 mode = TYPE_MODE (type);
10063 if (!SCALAR_FLOAT_MODE_P (mode))
10066 if (*modep == VOIDmode)
10069 if (*modep == mode)
10075 mode = TYPE_MODE (TREE_TYPE (type));
10076 if (!SCALAR_FLOAT_MODE_P (mode))
10079 if (*modep == VOIDmode)
10082 if (*modep == mode)
10088 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
10091 /* Use V4SImode as representative of all 128-bit vector types. */
10092 size = int_size_in_bytes (type);
10102 if (*modep == VOIDmode)
10105 /* Vector modes are considered to be opaque: two vectors are
10106 equivalent for the purposes of being homogeneous aggregates
10107 if they are the same size. */
10108 if (*modep == mode)
10116 tree index = TYPE_DOMAIN (type);
10118 /* Can't handle incomplete types nor sizes that are not
10120 if (!COMPLETE_TYPE_P (type)
10121 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10124 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
10127 || !TYPE_MAX_VALUE (index)
10128 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
10129 || !TYPE_MIN_VALUE (index)
10130 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
10134 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
10135 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
10137 /* There must be no padding. */
10138 if (wi::to_wide (TYPE_SIZE (type))
10139 != count * GET_MODE_BITSIZE (*modep))
10151 /* Can't handle incomplete types nor sizes that are not
10153 if (!COMPLETE_TYPE_P (type)
10154 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10157 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10159 if (TREE_CODE (field) != FIELD_DECL)
10162 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10165 count += sub_count;
10168 /* There must be no padding. */
10169 if (wi::to_wide (TYPE_SIZE (type))
10170 != count * GET_MODE_BITSIZE (*modep))
10177 case QUAL_UNION_TYPE:
10179 /* These aren't very interesting except in a degenerate case. */
10184 /* Can't handle incomplete types nor sizes that are not
10186 if (!COMPLETE_TYPE_P (type)
10187 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
10190 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
10192 if (TREE_CODE (field) != FIELD_DECL)
10195 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
10198 count = count > sub_count ? count : sub_count;
10201 /* There must be no padding. */
10202 if (wi::to_wide (TYPE_SIZE (type))
10203 != count * GET_MODE_BITSIZE (*modep))
10216 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
10217 float or vector aggregate that shall be passed in FP/vector registers
10218 according to the ELFv2 ABI, return the homogeneous element mode in
10219 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
10221 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
10224 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
10225 machine_mode *elt_mode,
10228 /* Note that we do not accept complex types at the top level as
10229 homogeneous aggregates; these types are handled via the
10230 targetm.calls.split_complex_arg mechanism. Complex types
10231 can be elements of homogeneous aggregates, however. */
10232 if (TARGET_HARD_FLOAT && DEFAULT_ABI == ABI_ELFv2 && type
10233 && AGGREGATE_TYPE_P (type))
10235 machine_mode field_mode = VOIDmode;
10236 int field_count = rs6000_aggregate_candidate (type, &field_mode);
10238 if (field_count > 0)
10240 int reg_size = ALTIVEC_OR_VSX_VECTOR_MODE (field_mode) ? 16 : 8;
10241 int field_size = ROUND_UP (GET_MODE_SIZE (field_mode), reg_size);
10243 /* The ELFv2 ABI allows homogeneous aggregates to occupy
10244 up to AGGR_ARG_NUM_REG registers. */
10245 if (field_count * field_size <= AGGR_ARG_NUM_REG * reg_size)
10248 *elt_mode = field_mode;
10250 *n_elts = field_count;
10263 /* Return a nonzero value to say to return the function value in
10264 memory, just as large structures are always returned. TYPE will be
10265 the data type of the value, and FNTYPE will be the type of the
10266 function doing the returning, or @code{NULL} for libcalls.
10268 The AIX ABI for the RS/6000 specifies that all structures are
10269 returned in memory. The Darwin ABI does the same.
10271 For the Darwin 64 Bit ABI, a function result can be returned in
10272 registers or in memory, depending on the size of the return data
10273 type. If it is returned in registers, the value occupies the same
10274 registers as it would if it were the first and only function
10275 argument. Otherwise, the function places its result in memory at
10276 the location pointed to by GPR3.
10278 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
10279 but a draft put them in memory, and GCC used to implement the draft
10280 instead of the final standard. Therefore, aix_struct_return
10281 controls this instead of DEFAULT_ABI; V.4 targets needing backward
10282 compatibility can change DRAFT_V4_STRUCT_RET to override the
10283 default, and -m switches get the final word. See
10284 rs6000_option_override_internal for more details.
10286 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
10287 long double support is enabled. These values are returned in memory.
10289 int_size_in_bytes returns -1 for variable size objects, which go in
10290 memory always. The cast to unsigned makes -1 > 8. */
10293 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
10295 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
10297 && rs6000_darwin64_abi
10298 && TREE_CODE (type) == RECORD_TYPE
10299 && int_size_in_bytes (type) > 0)
10301 CUMULATIVE_ARGS valcum;
10305 valcum.fregno = FP_ARG_MIN_REG;
10306 valcum.vregno = ALTIVEC_ARG_MIN_REG;
10307 /* Do a trial code generation as if this were going to be passed
10308 as an argument; if any part goes in memory, we return NULL. */
10309 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
10312 /* Otherwise fall through to more conventional ABI rules. */
10315 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
10316 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
10320 /* The ELFv2 ABI returns aggregates up to 16B in registers */
10321 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
10322 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
10325 if (AGGREGATE_TYPE_P (type)
10326 && (aix_struct_return
10327 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
10330 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10331 modes only exist for GCC vector types if -maltivec. */
10332 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
10333 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
10336 /* Return synthetic vectors in memory. */
10337 if (TREE_CODE (type) == VECTOR_TYPE
10338 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
10340 static bool warned_for_return_big_vectors = false;
10341 if (!warned_for_return_big_vectors)
10343 warning (OPT_Wpsabi, "GCC vector returned by reference: "
10344 "non-standard ABI extension with no compatibility "
10346 warned_for_return_big_vectors = true;
10351 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
10352 && FLOAT128_IEEE_P (TYPE_MODE (type)))
10358 /* Specify whether values returned in registers should be at the most
10359 significant end of a register. We want aggregates returned by
10360 value to match the way aggregates are passed to functions. */
10363 rs6000_return_in_msb (const_tree valtype)
10365 return (DEFAULT_ABI == ABI_ELFv2
10366 && BYTES_BIG_ENDIAN
10367 && AGGREGATE_TYPE_P (valtype)
10368 && (rs6000_function_arg_padding (TYPE_MODE (valtype), valtype)
10372 #ifdef HAVE_AS_GNU_ATTRIBUTE
10373 /* Return TRUE if a call to function FNDECL may be one that
10374 potentially affects the function calling ABI of the object file. */
10377 call_ABI_of_interest (tree fndecl)
10379 if (rs6000_gnu_attr && symtab->state == EXPANSION)
10381 struct cgraph_node *c_node;
10383 /* Libcalls are always interesting. */
10384 if (fndecl == NULL_TREE)
10387 /* Any call to an external function is interesting. */
10388 if (DECL_EXTERNAL (fndecl))
10391 /* Interesting functions that we are emitting in this object file. */
10392 c_node = cgraph_node::get (fndecl);
10393 c_node = c_node->ultimate_alias_target ();
10394 return !c_node->only_called_directly_p ();
10400 /* Initialize a variable CUM of type CUMULATIVE_ARGS
10401 for a call to a function whose data type is FNTYPE.
10402 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
10404 For incoming args we set the number of arguments in the prototype large
10405 so we never return a PARALLEL. */
10408 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
10409 rtx libname ATTRIBUTE_UNUSED, int incoming,
10410 int libcall, int n_named_args,
10412 machine_mode return_mode ATTRIBUTE_UNUSED)
10414 static CUMULATIVE_ARGS zero_cumulative;
10416 *cum = zero_cumulative;
10418 cum->fregno = FP_ARG_MIN_REG;
10419 cum->vregno = ALTIVEC_ARG_MIN_REG;
10420 cum->prototype = (fntype && prototype_p (fntype));
10421 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
10422 ? CALL_LIBCALL : CALL_NORMAL);
10423 cum->sysv_gregno = GP_ARG_MIN_REG;
10424 cum->stdarg = stdarg_p (fntype);
10425 cum->libcall = libcall;
10427 cum->nargs_prototype = 0;
10428 if (incoming || cum->prototype)
10429 cum->nargs_prototype = n_named_args;
10431 /* Check for a longcall attribute. */
10432 if ((!fntype && rs6000_default_long_calls)
10434 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
10435 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
10436 cum->call_cookie |= CALL_LONG;
10437 else if (DEFAULT_ABI != ABI_DARWIN)
10439 bool is_local = (fndecl
10440 && !DECL_EXTERNAL (fndecl)
10441 && !DECL_WEAK (fndecl)
10442 && (*targetm.binds_local_p) (fndecl));
10448 && lookup_attribute ("noplt", TYPE_ATTRIBUTES (fntype)))
10449 cum->call_cookie |= CALL_LONG;
10454 && lookup_attribute ("plt", TYPE_ATTRIBUTES (fntype))))
10455 cum->call_cookie |= CALL_LONG;
10459 if (TARGET_DEBUG_ARG)
10461 fprintf (stderr, "\ninit_cumulative_args:");
10464 tree ret_type = TREE_TYPE (fntype);
10465 fprintf (stderr, " ret code = %s,",
10466 get_tree_code_name (TREE_CODE (ret_type)));
10469 if (cum->call_cookie & CALL_LONG)
10470 fprintf (stderr, " longcall,");
10472 fprintf (stderr, " proto = %d, nargs = %d\n",
10473 cum->prototype, cum->nargs_prototype);
10476 #ifdef HAVE_AS_GNU_ATTRIBUTE
10477 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4))
10479 cum->escapes = call_ABI_of_interest (fndecl);
10486 return_type = TREE_TYPE (fntype);
10487 return_mode = TYPE_MODE (return_type);
10490 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
10492 if (return_type != NULL)
10494 if (TREE_CODE (return_type) == RECORD_TYPE
10495 && TYPE_TRANSPARENT_AGGR (return_type))
10497 return_type = TREE_TYPE (first_field (return_type));
10498 return_mode = TYPE_MODE (return_type);
10500 if (AGGREGATE_TYPE_P (return_type)
10501 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
10503 rs6000_returns_struct = true;
10505 if (SCALAR_FLOAT_MODE_P (return_mode))
10507 rs6000_passes_float = true;
10508 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
10509 && (FLOAT128_IBM_P (return_mode)
10510 || FLOAT128_IEEE_P (return_mode)
10511 || (return_type != NULL
10512 && (TYPE_MAIN_VARIANT (return_type)
10513 == long_double_type_node))))
10514 rs6000_passes_long_double = true;
10516 /* Note if we passed or return a IEEE 128-bit type. We changed
10517 the mangling for these types, and we may need to make an alias
10518 with the old mangling. */
10519 if (FLOAT128_IEEE_P (return_mode))
10520 rs6000_passes_ieee128 = true;
10522 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode))
10523 rs6000_passes_vector = true;
10530 && TARGET_ALTIVEC_ABI
10531 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
10533 error ("cannot return value in vector register because"
10534 " altivec instructions are disabled, use %qs"
10535 " to enable them", "-maltivec");
10539 /* The mode the ABI uses for a word. This is not the same as word_mode
10540 for -m32 -mpowerpc64. This is used to implement various target hooks. */
10542 static scalar_int_mode
10543 rs6000_abi_word_mode (void)
10545 return TARGET_32BIT ? SImode : DImode;
10548 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
10550 rs6000_offload_options (void)
10553 return xstrdup ("-foffload-abi=lp64");
10555 return xstrdup ("-foffload-abi=ilp32");
10558 /* On rs6000, function arguments are promoted, as are function return
10561 static machine_mode
10562 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
10564 int *punsignedp ATTRIBUTE_UNUSED,
10567 PROMOTE_MODE (mode, *punsignedp, type);
10572 /* Return true if TYPE must be passed on the stack and not in registers. */
10575 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
10577 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
10578 return must_pass_in_stack_var_size (mode, type);
10580 return must_pass_in_stack_var_size_or_pad (mode, type);
10584 is_complex_IBM_long_double (machine_mode mode)
10586 return mode == ICmode || (mode == TCmode && FLOAT128_IBM_P (TCmode));
10589 /* Whether ABI_V4 passes MODE args to a function in floating point
10593 abi_v4_pass_in_fpr (machine_mode mode, bool named)
10595 if (!TARGET_HARD_FLOAT)
10597 if (mode == DFmode)
10599 if (mode == SFmode && named)
10601 /* ABI_V4 passes complex IBM long double in 8 gprs.
10602 Stupid, but we can't change the ABI now. */
10603 if (is_complex_IBM_long_double (mode))
10605 if (FLOAT128_2REG_P (mode))
10607 if (DECIMAL_FLOAT_MODE_P (mode))
10612 /* Implement TARGET_FUNCTION_ARG_PADDING.
10614 For the AIX ABI structs are always stored left shifted in their
10617 static pad_direction
10618 rs6000_function_arg_padding (machine_mode mode, const_tree type)
10620 #ifndef AGGREGATE_PADDING_FIXED
10621 #define AGGREGATE_PADDING_FIXED 0
10623 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
10624 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
10627 if (!AGGREGATE_PADDING_FIXED)
10629 /* GCC used to pass structures of the same size as integer types as
10630 if they were in fact integers, ignoring TARGET_FUNCTION_ARG_PADDING.
10631 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
10632 passed padded downward, except that -mstrict-align further
10633 muddied the water in that multi-component structures of 2 and 4
10634 bytes in size were passed padded upward.
10636 The following arranges for best compatibility with previous
10637 versions of gcc, but removes the -mstrict-align dependency. */
10638 if (BYTES_BIG_ENDIAN)
10640 HOST_WIDE_INT size = 0;
10642 if (mode == BLKmode)
10644 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
10645 size = int_size_in_bytes (type);
10648 size = GET_MODE_SIZE (mode);
10650 if (size == 1 || size == 2 || size == 4)
10651 return PAD_DOWNWARD;
10656 if (AGGREGATES_PAD_UPWARD_ALWAYS)
10658 if (type != 0 && AGGREGATE_TYPE_P (type))
10662 /* Fall back to the default. */
10663 return default_function_arg_padding (mode, type);
10666 /* If defined, a C expression that gives the alignment boundary, in bits,
10667 of an argument with the specified mode and type. If it is not defined,
10668 PARM_BOUNDARY is used for all arguments.
10670 V.4 wants long longs and doubles to be double word aligned. Just
10671 testing the mode size is a boneheaded way to do this as it means
10672 that other types such as complex int are also double word aligned.
10673 However, we're stuck with this because changing the ABI might break
10674 existing library interfaces.
10676 Quadword align Altivec/VSX vectors.
10677 Quadword align large synthetic vector types. */
10679 static unsigned int
10680 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
10682 machine_mode elt_mode;
10685 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10687 if (DEFAULT_ABI == ABI_V4
10688 && (GET_MODE_SIZE (mode) == 8
10689 || (TARGET_HARD_FLOAT
10690 && !is_complex_IBM_long_double (mode)
10691 && FLOAT128_2REG_P (mode))))
10693 else if (FLOAT128_VECTOR_P (mode))
10695 else if (type && TREE_CODE (type) == VECTOR_TYPE
10696 && int_size_in_bytes (type) >= 8
10697 && int_size_in_bytes (type) < 16)
10699 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
10700 || (type && TREE_CODE (type) == VECTOR_TYPE
10701 && int_size_in_bytes (type) >= 16))
10704 /* Aggregate types that need > 8 byte alignment are quadword-aligned
10705 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
10706 -mcompat-align-parm is used. */
10707 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
10708 || DEFAULT_ABI == ABI_ELFv2)
10709 && type && TYPE_ALIGN (type) > 64)
10711 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
10712 or homogeneous float/vector aggregates here. We already handled
10713 vector aggregates above, but still need to check for float here. */
10714 bool aggregate_p = (AGGREGATE_TYPE_P (type)
10715 && !SCALAR_FLOAT_MODE_P (elt_mode));
10717 /* We used to check for BLKmode instead of the above aggregate type
10718 check. Warn when this results in any difference to the ABI. */
10719 if (aggregate_p != (mode == BLKmode))
10721 static bool warned;
10722 if (!warned && warn_psabi)
10725 inform (input_location,
10726 "the ABI of passing aggregates with %d-byte alignment"
10727 " has changed in GCC 5",
10728 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
10736 /* Similar for the Darwin64 ABI. Note that for historical reasons we
10737 implement the "aggregate type" check as a BLKmode check here; this
10738 means certain aggregate types are in fact not aligned. */
10739 if (TARGET_MACHO && rs6000_darwin64_abi
10741 && type && TYPE_ALIGN (type) > 64)
10744 return PARM_BOUNDARY;
10747 /* The offset in words to the start of the parameter save area. */
10749 static unsigned int
10750 rs6000_parm_offset (void)
10752 return (DEFAULT_ABI == ABI_V4 ? 2
10753 : DEFAULT_ABI == ABI_ELFv2 ? 4
10757 /* For a function parm of MODE and TYPE, return the starting word in
10758 the parameter area. NWORDS of the parameter area are already used. */
10760 static unsigned int
10761 rs6000_parm_start (machine_mode mode, const_tree type,
10762 unsigned int nwords)
10764 unsigned int align;
10766 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
10767 return nwords + (-(rs6000_parm_offset () + nwords) & align);
10770 /* Compute the size (in words) of a function argument. */
10772 static unsigned long
10773 rs6000_arg_size (machine_mode mode, const_tree type)
10775 unsigned long size;
10777 if (mode != BLKmode)
10778 size = GET_MODE_SIZE (mode);
10780 size = int_size_in_bytes (type);
10783 return (size + 3) >> 2;
10785 return (size + 7) >> 3;
10788 /* Use this to flush pending int fields. */
10791 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
10792 HOST_WIDE_INT bitpos, int final)
10794 unsigned int startbit, endbit;
10795 int intregs, intoffset;
10797 /* Handle the situations where a float is taking up the first half
10798 of the GPR, and the other half is empty (typically due to
10799 alignment restrictions). We can detect this by a 8-byte-aligned
10800 int field, or by seeing that this is the final flush for this
10801 argument. Count the word and continue on. */
10802 if (cum->floats_in_gpr == 1
10803 && (cum->intoffset % 64 == 0
10804 || (cum->intoffset == -1 && final)))
10807 cum->floats_in_gpr = 0;
10810 if (cum->intoffset == -1)
10813 intoffset = cum->intoffset;
10814 cum->intoffset = -1;
10815 cum->floats_in_gpr = 0;
10817 if (intoffset % BITS_PER_WORD != 0)
10819 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
10820 if (!int_mode_for_size (bits, 0).exists ())
10822 /* We couldn't find an appropriate mode, which happens,
10823 e.g., in packed structs when there are 3 bytes to load.
10824 Back intoffset back to the beginning of the word in this
10826 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
10830 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
10831 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
10832 intregs = (endbit - startbit) / BITS_PER_WORD;
10833 cum->words += intregs;
10834 /* words should be unsigned. */
10835 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
10837 int pad = (endbit/BITS_PER_WORD) - cum->words;
10842 /* The darwin64 ABI calls for us to recurse down through structs,
10843 looking for elements passed in registers. Unfortunately, we have
10844 to track int register count here also because of misalignments
10845 in powerpc alignment mode. */
10848 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
10850 HOST_WIDE_INT startbitpos)
10854 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
10855 if (TREE_CODE (f) == FIELD_DECL)
10857 HOST_WIDE_INT bitpos = startbitpos;
10858 tree ftype = TREE_TYPE (f);
10860 if (ftype == error_mark_node)
10862 mode = TYPE_MODE (ftype);
10864 if (DECL_SIZE (f) != 0
10865 && tree_fits_uhwi_p (bit_position (f)))
10866 bitpos += int_bit_position (f);
10868 /* ??? FIXME: else assume zero offset. */
10870 if (TREE_CODE (ftype) == RECORD_TYPE)
10871 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
10872 else if (USE_FP_FOR_ARG_P (cum, mode))
10874 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
10875 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
10876 cum->fregno += n_fpregs;
10877 /* Single-precision floats present a special problem for
10878 us, because they are smaller than an 8-byte GPR, and so
10879 the structure-packing rules combined with the standard
10880 varargs behavior mean that we want to pack float/float
10881 and float/int combinations into a single register's
10882 space. This is complicated by the arg advance flushing,
10883 which works on arbitrarily large groups of int-type
10885 if (mode == SFmode)
10887 if (cum->floats_in_gpr == 1)
10889 /* Two floats in a word; count the word and reset
10890 the float count. */
10892 cum->floats_in_gpr = 0;
10894 else if (bitpos % 64 == 0)
10896 /* A float at the beginning of an 8-byte word;
10897 count it and put off adjusting cum->words until
10898 we see if a arg advance flush is going to do it
10900 cum->floats_in_gpr++;
10904 /* The float is at the end of a word, preceded
10905 by integer fields, so the arg advance flush
10906 just above has already set cum->words and
10907 everything is taken care of. */
10911 cum->words += n_fpregs;
10913 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
10915 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
10919 else if (cum->intoffset == -1)
10920 cum->intoffset = bitpos;
10924 /* Check for an item that needs to be considered specially under the darwin 64
10925 bit ABI. These are record types where the mode is BLK or the structure is
10926 8 bytes in size. */
10928 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
10930 return rs6000_darwin64_abi
10931 && ((mode == BLKmode
10932 && TREE_CODE (type) == RECORD_TYPE
10933 && int_size_in_bytes (type) > 0)
10934 || (type && TREE_CODE (type) == RECORD_TYPE
10935 && int_size_in_bytes (type) == 8)) ? 1 : 0;
10938 /* Update the data in CUM to advance over an argument
10939 of mode MODE and data type TYPE.
10940 (TYPE is null for libcalls where that information may not be available.)
10942 Note that for args passed by reference, function_arg will be called
10943 with MODE and TYPE set to that of the pointer to the arg, not the arg
10947 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
10948 const_tree type, bool named, int depth)
10950 machine_mode elt_mode;
10953 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10955 /* Only tick off an argument if we're not recursing. */
10957 cum->nargs_prototype--;
10959 #ifdef HAVE_AS_GNU_ATTRIBUTE
10960 if (TARGET_ELF && (TARGET_64BIT || DEFAULT_ABI == ABI_V4)
10963 if (SCALAR_FLOAT_MODE_P (mode))
10965 rs6000_passes_float = true;
10966 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE || TARGET_64BIT)
10967 && (FLOAT128_IBM_P (mode)
10968 || FLOAT128_IEEE_P (mode)
10970 && TYPE_MAIN_VARIANT (type) == long_double_type_node)))
10971 rs6000_passes_long_double = true;
10973 /* Note if we passed or return a IEEE 128-bit type. We changed the
10974 mangling for these types, and we may need to make an alias with
10975 the old mangling. */
10976 if (FLOAT128_IEEE_P (mode))
10977 rs6000_passes_ieee128 = true;
10979 if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
10980 rs6000_passes_vector = true;
10984 if (TARGET_ALTIVEC_ABI
10985 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
10986 || (type && TREE_CODE (type) == VECTOR_TYPE
10987 && int_size_in_bytes (type) == 16)))
10989 bool stack = false;
10991 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
10993 cum->vregno += n_elts;
10995 if (!TARGET_ALTIVEC)
10996 error ("cannot pass argument in vector register because"
10997 " altivec instructions are disabled, use %qs"
10998 " to enable them", "-maltivec");
11000 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11001 even if it is going to be passed in a vector register.
11002 Darwin does the same for variable-argument functions. */
11003 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11005 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
11015 /* Vector parameters must be 16-byte aligned. In 32-bit
11016 mode this means we need to take into account the offset
11017 to the parameter save area. In 64-bit mode, they just
11018 have to start on an even word, since the parameter save
11019 area is 16-byte aligned. */
11021 align = -(rs6000_parm_offset () + cum->words) & 3;
11023 align = cum->words & 1;
11024 cum->words += align + rs6000_arg_size (mode, type);
11026 if (TARGET_DEBUG_ARG)
11028 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
11029 cum->words, align);
11030 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
11031 cum->nargs_prototype, cum->prototype,
11032 GET_MODE_NAME (mode));
11036 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11038 int size = int_size_in_bytes (type);
11039 /* Variable sized types have size == -1 and are
11040 treated as if consisting entirely of ints.
11041 Pad to 16 byte boundary if needed. */
11042 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11043 && (cum->words % 2) != 0)
11045 /* For varargs, we can just go up by the size of the struct. */
11047 cum->words += (size + 7) / 8;
11050 /* It is tempting to say int register count just goes up by
11051 sizeof(type)/8, but this is wrong in a case such as
11052 { int; double; int; } [powerpc alignment]. We have to
11053 grovel through the fields for these too. */
11054 cum->intoffset = 0;
11055 cum->floats_in_gpr = 0;
11056 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
11057 rs6000_darwin64_record_arg_advance_flush (cum,
11058 size * BITS_PER_UNIT, 1);
11060 if (TARGET_DEBUG_ARG)
11062 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
11063 cum->words, TYPE_ALIGN (type), size);
11065 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11066 cum->nargs_prototype, cum->prototype,
11067 GET_MODE_NAME (mode));
11070 else if (DEFAULT_ABI == ABI_V4)
11072 if (abi_v4_pass_in_fpr (mode, named))
11074 /* _Decimal128 must use an even/odd register pair. This assumes
11075 that the register number is odd when fregno is odd. */
11076 if (mode == TDmode && (cum->fregno % 2) == 1)
11079 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11080 <= FP_ARG_V4_MAX_REG)
11081 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
11084 cum->fregno = FP_ARG_V4_MAX_REG + 1;
11085 if (mode == DFmode || FLOAT128_IBM_P (mode)
11086 || mode == DDmode || mode == TDmode)
11087 cum->words += cum->words & 1;
11088 cum->words += rs6000_arg_size (mode, type);
11093 int n_words = rs6000_arg_size (mode, type);
11094 int gregno = cum->sysv_gregno;
11096 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11097 As does any other 2 word item such as complex int due to a
11098 historical mistake. */
11100 gregno += (1 - gregno) & 1;
11102 /* Multi-reg args are not split between registers and stack. */
11103 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11105 /* Long long is aligned on the stack. So are other 2 word
11106 items such as complex int due to a historical mistake. */
11108 cum->words += cum->words & 1;
11109 cum->words += n_words;
11112 /* Note: continuing to accumulate gregno past when we've started
11113 spilling to the stack indicates the fact that we've started
11114 spilling to the stack to expand_builtin_saveregs. */
11115 cum->sysv_gregno = gregno + n_words;
11118 if (TARGET_DEBUG_ARG)
11120 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11121 cum->words, cum->fregno);
11122 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
11123 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
11124 fprintf (stderr, "mode = %4s, named = %d\n",
11125 GET_MODE_NAME (mode), named);
11130 int n_words = rs6000_arg_size (mode, type);
11131 int start_words = cum->words;
11132 int align_words = rs6000_parm_start (mode, type, start_words);
11134 cum->words = align_words + n_words;
11136 if (SCALAR_FLOAT_MODE_P (elt_mode) && TARGET_HARD_FLOAT)
11138 /* _Decimal128 must be passed in an even/odd float register pair.
11139 This assumes that the register number is odd when fregno is
11141 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11143 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
11146 if (TARGET_DEBUG_ARG)
11148 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
11149 cum->words, cum->fregno);
11150 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
11151 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
11152 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
11153 named, align_words - start_words, depth);
11159 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
11160 const_tree type, bool named)
11162 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
11166 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11167 structure between cum->intoffset and bitpos to integer registers. */
11170 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
11171 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
11174 unsigned int regno;
11175 unsigned int startbit, endbit;
11176 int this_regno, intregs, intoffset;
11179 if (cum->intoffset == -1)
11182 intoffset = cum->intoffset;
11183 cum->intoffset = -1;
11185 /* If this is the trailing part of a word, try to only load that
11186 much into the register. Otherwise load the whole register. Note
11187 that in the latter case we may pick up unwanted bits. It's not a
11188 problem at the moment but may wish to revisit. */
11190 if (intoffset % BITS_PER_WORD != 0)
11192 unsigned int bits = BITS_PER_WORD - intoffset % BITS_PER_WORD;
11193 if (!int_mode_for_size (bits, 0).exists (&mode))
11195 /* We couldn't find an appropriate mode, which happens,
11196 e.g., in packed structs when there are 3 bytes to load.
11197 Back intoffset back to the beginning of the word in this
11199 intoffset = ROUND_DOWN (intoffset, BITS_PER_WORD);
11206 startbit = ROUND_DOWN (intoffset, BITS_PER_WORD);
11207 endbit = ROUND_UP (bitpos, BITS_PER_WORD);
11208 intregs = (endbit - startbit) / BITS_PER_WORD;
11209 this_regno = cum->words + intoffset / BITS_PER_WORD;
11211 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
11212 cum->use_stack = 1;
11214 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
11218 intoffset /= BITS_PER_UNIT;
11221 regno = GP_ARG_MIN_REG + this_regno;
11222 reg = gen_rtx_REG (mode, regno);
11224 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
11227 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
11231 while (intregs > 0);
11234 /* Recursive workhorse for the following. */
11237 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
11238 HOST_WIDE_INT startbitpos, rtx rvec[],
11243 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
11244 if (TREE_CODE (f) == FIELD_DECL)
11246 HOST_WIDE_INT bitpos = startbitpos;
11247 tree ftype = TREE_TYPE (f);
11249 if (ftype == error_mark_node)
11251 mode = TYPE_MODE (ftype);
11253 if (DECL_SIZE (f) != 0
11254 && tree_fits_uhwi_p (bit_position (f)))
11255 bitpos += int_bit_position (f);
11257 /* ??? FIXME: else assume zero offset. */
11259 if (TREE_CODE (ftype) == RECORD_TYPE)
11260 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
11261 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
11263 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
11267 case E_SCmode: mode = SFmode; break;
11268 case E_DCmode: mode = DFmode; break;
11269 case E_TCmode: mode = TFmode; break;
11273 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11274 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
11276 gcc_assert (cum->fregno == FP_ARG_MAX_REG
11277 && (mode == TFmode || mode == TDmode));
11278 /* Long double or _Decimal128 split over regs and memory. */
11279 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
11283 = gen_rtx_EXPR_LIST (VOIDmode,
11284 gen_rtx_REG (mode, cum->fregno++),
11285 GEN_INT (bitpos / BITS_PER_UNIT));
11286 if (FLOAT128_2REG_P (mode))
11289 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
11291 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
11293 = gen_rtx_EXPR_LIST (VOIDmode,
11294 gen_rtx_REG (mode, cum->vregno++),
11295 GEN_INT (bitpos / BITS_PER_UNIT));
11297 else if (cum->intoffset == -1)
11298 cum->intoffset = bitpos;
11302 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
11303 the register(s) to be used for each field and subfield of a struct
11304 being passed by value, along with the offset of where the
11305 register's value may be found in the block. FP fields go in FP
11306 register, vector fields go in vector registers, and everything
11307 else goes in int registers, packed as in memory.
11309 This code is also used for function return values. RETVAL indicates
11310 whether this is the case.
11312 Much of this is taken from the SPARC V9 port, which has a similar
11313 calling convention. */
11316 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
11317 bool named, bool retval)
11319 rtx rvec[FIRST_PSEUDO_REGISTER];
11320 int k = 1, kbase = 1;
11321 HOST_WIDE_INT typesize = int_size_in_bytes (type);
11322 /* This is a copy; modifications are not visible to our caller. */
11323 CUMULATIVE_ARGS copy_cum = *orig_cum;
11324 CUMULATIVE_ARGS *cum = ©_cum;
11326 /* Pad to 16 byte boundary if needed. */
11327 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
11328 && (cum->words % 2) != 0)
11331 cum->intoffset = 0;
11332 cum->use_stack = 0;
11333 cum->named = named;
11335 /* Put entries into rvec[] for individual FP and vector fields, and
11336 for the chunks of memory that go in int regs. Note we start at
11337 element 1; 0 is reserved for an indication of using memory, and
11338 may or may not be filled in below. */
11339 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
11340 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
11342 /* If any part of the struct went on the stack put all of it there.
11343 This hack is because the generic code for
11344 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
11345 parts of the struct are not at the beginning. */
11346 if (cum->use_stack)
11349 return NULL_RTX; /* doesn't go in registers at all */
11351 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11353 if (k > 1 || cum->use_stack)
11354 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
11359 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
11362 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
11367 rtx rvec[GP_ARG_NUM_REG + 1];
11369 if (align_words >= GP_ARG_NUM_REG)
11372 n_units = rs6000_arg_size (mode, type);
11374 /* Optimize the simple case where the arg fits in one gpr, except in
11375 the case of BLKmode due to assign_parms assuming that registers are
11376 BITS_PER_WORD wide. */
11378 || (n_units == 1 && mode != BLKmode))
11379 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11382 if (align_words + n_units > GP_ARG_NUM_REG)
11383 /* Not all of the arg fits in gprs. Say that it goes in memory too,
11384 using a magic NULL_RTX component.
11385 This is not strictly correct. Only some of the arg belongs in
11386 memory, not all of it. However, the normal scheme using
11387 function_arg_partial_nregs can result in unusual subregs, eg.
11388 (subreg:SI (reg:DF) 4), which are not handled well. The code to
11389 store the whole arg to memory is often more efficient than code
11390 to store pieces, and we know that space is available in the right
11391 place for the whole arg. */
11392 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11397 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
11398 rtx off = GEN_INT (i++ * 4);
11399 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11401 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
11403 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
11406 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
11407 but must also be copied into the parameter save area starting at
11408 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
11409 to the GPRs and/or memory. Return the number of elements used. */
11412 rs6000_psave_function_arg (machine_mode mode, const_tree type,
11413 int align_words, rtx *rvec)
11417 if (align_words < GP_ARG_NUM_REG)
11419 int n_words = rs6000_arg_size (mode, type);
11421 if (align_words + n_words > GP_ARG_NUM_REG
11423 || (TARGET_32BIT && TARGET_POWERPC64))
11425 /* If this is partially on the stack, then we only
11426 include the portion actually in registers here. */
11427 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
11430 if (align_words + n_words > GP_ARG_NUM_REG)
11432 /* Not all of the arg fits in gprs. Say that it goes in memory
11433 too, using a magic NULL_RTX component. Also see comment in
11434 rs6000_mixed_function_arg for why the normal
11435 function_arg_partial_nregs scheme doesn't work in this case. */
11436 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11441 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
11442 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
11443 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11445 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
11449 /* The whole arg fits in gprs. */
11450 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11451 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
11456 /* It's entirely in memory. */
11457 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
11463 /* RVEC is a vector of K components of an argument of mode MODE.
11464 Construct the final function_arg return value from it. */
11467 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
11469 gcc_assert (k >= 1);
11471 /* Avoid returning a PARALLEL in the trivial cases. */
11474 if (XEXP (rvec[0], 0) == NULL_RTX)
11477 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
11478 return XEXP (rvec[0], 0);
11481 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
11484 /* Determine where to put an argument to a function.
11485 Value is zero to push the argument on the stack,
11486 or a hard register in which to store the argument.
11488 MODE is the argument's machine mode.
11489 TYPE is the data type of the argument (as a tree).
11490 This is null for libcalls where that information may
11492 CUM is a variable of type CUMULATIVE_ARGS which gives info about
11493 the preceding args and about the function being called. It is
11494 not modified in this routine.
11495 NAMED is nonzero if this argument is a named parameter
11496 (otherwise it is an extra parameter matching an ellipsis).
11498 On RS/6000 the first eight words of non-FP are normally in registers
11499 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
11500 Under V.4, the first 8 FP args are in registers.
11502 If this is floating-point and no prototype is specified, we use
11503 both an FP and integer register (or possibly FP reg and stack). Library
11504 functions (when CALL_LIBCALL is set) always have the proper types for args,
11505 so we can pass the FP value just in one register. emit_library_function
11506 doesn't support PARALLEL anyway.
11508 Note that for args passed by reference, function_arg will be called
11509 with MODE and TYPE set to that of the pointer to the arg, not the arg
11513 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
11514 const_tree type, bool named)
11516 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
11517 enum rs6000_abi abi = DEFAULT_ABI;
11518 machine_mode elt_mode;
11521 /* Return a marker to indicate whether CR1 needs to set or clear the
11522 bit that V.4 uses to say fp args were passed in registers.
11523 Assume that we don't need the marker for software floating point,
11524 or compiler generated library calls. */
11525 if (mode == VOIDmode)
11528 && (cum->call_cookie & CALL_LIBCALL) == 0
11530 || (cum->nargs_prototype < 0
11531 && (cum->prototype || TARGET_NO_PROTOTYPE)))
11532 && TARGET_HARD_FLOAT)
11533 return GEN_INT (cum->call_cookie
11534 | ((cum->fregno == FP_ARG_MIN_REG)
11535 ? CALL_V4_SET_FP_ARGS
11536 : CALL_V4_CLEAR_FP_ARGS));
11538 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
11541 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11543 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11545 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
11546 if (rslt != NULL_RTX)
11548 /* Else fall through to usual handling. */
11551 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11553 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
11557 /* Do we also need to pass this argument in the parameter save area?
11558 Library support functions for IEEE 128-bit are assumed to not need the
11559 value passed both in GPRs and in vector registers. */
11560 if (TARGET_64BIT && !cum->prototype
11561 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
11563 int align_words = ROUND_UP (cum->words, 2);
11564 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
11567 /* Describe where this argument goes in the vector registers. */
11568 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
11570 r = gen_rtx_REG (elt_mode, cum->vregno + i);
11571 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
11572 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11575 return rs6000_finish_function_arg (mode, rvec, k);
11577 else if (TARGET_ALTIVEC_ABI
11578 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
11579 || (type && TREE_CODE (type) == VECTOR_TYPE
11580 && int_size_in_bytes (type) == 16)))
11582 if (named || abi == ABI_V4)
11586 /* Vector parameters to varargs functions under AIX or Darwin
11587 get passed in memory and possibly also in GPRs. */
11588 int align, align_words, n_words;
11589 machine_mode part_mode;
11591 /* Vector parameters must be 16-byte aligned. In 32-bit
11592 mode this means we need to take into account the offset
11593 to the parameter save area. In 64-bit mode, they just
11594 have to start on an even word, since the parameter save
11595 area is 16-byte aligned. */
11597 align = -(rs6000_parm_offset () + cum->words) & 3;
11599 align = cum->words & 1;
11600 align_words = cum->words + align;
11602 /* Out of registers? Memory, then. */
11603 if (align_words >= GP_ARG_NUM_REG)
11606 if (TARGET_32BIT && TARGET_POWERPC64)
11607 return rs6000_mixed_function_arg (mode, type, align_words);
11609 /* The vector value goes in GPRs. Only the part of the
11610 value in GPRs is reported here. */
11612 n_words = rs6000_arg_size (mode, type);
11613 if (align_words + n_words > GP_ARG_NUM_REG)
11614 /* Fortunately, there are only two possibilities, the value
11615 is either wholly in GPRs or half in GPRs and half not. */
11616 part_mode = DImode;
11618 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
11622 else if (abi == ABI_V4)
11624 if (abi_v4_pass_in_fpr (mode, named))
11626 /* _Decimal128 must use an even/odd register pair. This assumes
11627 that the register number is odd when fregno is odd. */
11628 if (mode == TDmode && (cum->fregno % 2) == 1)
11631 if (cum->fregno + (FLOAT128_2REG_P (mode) ? 1 : 0)
11632 <= FP_ARG_V4_MAX_REG)
11633 return gen_rtx_REG (mode, cum->fregno);
11639 int n_words = rs6000_arg_size (mode, type);
11640 int gregno = cum->sysv_gregno;
11642 /* Long long is put in (r3,r4), (r5,r6), (r7,r8) or (r9,r10).
11643 As does any other 2 word item such as complex int due to a
11644 historical mistake. */
11646 gregno += (1 - gregno) & 1;
11648 /* Multi-reg args are not split between registers and stack. */
11649 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
11652 if (TARGET_32BIT && TARGET_POWERPC64)
11653 return rs6000_mixed_function_arg (mode, type,
11654 gregno - GP_ARG_MIN_REG);
11655 return gen_rtx_REG (mode, gregno);
11660 int align_words = rs6000_parm_start (mode, type, cum->words);
11662 /* _Decimal128 must be passed in an even/odd float register pair.
11663 This assumes that the register number is odd when fregno is odd. */
11664 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
11667 if (USE_FP_FOR_ARG_P (cum, elt_mode)
11668 && !(TARGET_AIX && !TARGET_ELF
11669 && type != NULL && AGGREGATE_TYPE_P (type)))
11671 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
11674 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
11677 /* Do we also need to pass this argument in the parameter
11679 if (type && (cum->nargs_prototype <= 0
11680 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11681 && TARGET_XL_COMPAT
11682 && align_words >= GP_ARG_NUM_REG)))
11683 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
11685 /* Describe where this argument goes in the fprs. */
11686 for (i = 0; i < n_elts
11687 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
11689 /* Check if the argument is split over registers and memory.
11690 This can only ever happen for long double or _Decimal128;
11691 complex types are handled via split_complex_arg. */
11692 machine_mode fmode = elt_mode;
11693 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
11695 gcc_assert (FLOAT128_2REG_P (fmode));
11696 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
11699 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
11700 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
11701 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11704 /* If there were not enough FPRs to hold the argument, the rest
11705 usually goes into memory. However, if the current position
11706 is still within the register parameter area, a portion may
11707 actually have to go into GPRs.
11709 Note that it may happen that the portion of the argument
11710 passed in the first "half" of the first GPR was already
11711 passed in the last FPR as well.
11713 For unnamed arguments, we already set up GPRs to cover the
11714 whole argument in rs6000_psave_function_arg, so there is
11715 nothing further to do at this point. */
11716 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
11717 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
11718 && cum->nargs_prototype > 0)
11720 static bool warned;
11722 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
11723 int n_words = rs6000_arg_size (mode, type);
11725 align_words += fpr_words;
11726 n_words -= fpr_words;
11730 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
11731 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
11732 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
11734 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
11736 if (!warned && warn_psabi)
11739 inform (input_location,
11740 "the ABI of passing homogeneous %<float%> aggregates"
11741 " has changed in GCC 5");
11745 return rs6000_finish_function_arg (mode, rvec, k);
11747 else if (align_words < GP_ARG_NUM_REG)
11749 if (TARGET_32BIT && TARGET_POWERPC64)
11750 return rs6000_mixed_function_arg (mode, type, align_words);
11752 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
11759 /* For an arg passed partly in registers and partly in memory, this is
11760 the number of bytes passed in registers. For args passed entirely in
11761 registers or entirely in memory, zero. When an arg is described by a
11762 PARALLEL, perhaps using more than one register type, this function
11763 returns the number of bytes used by the first element of the PARALLEL. */
11766 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
11767 tree type, bool named)
11769 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
11770 bool passed_in_gprs = true;
11773 machine_mode elt_mode;
11776 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
11778 if (DEFAULT_ABI == ABI_V4)
11781 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
11783 /* If we are passing this arg in the fixed parameter save area (gprs or
11784 memory) as well as VRs, we do not use the partial bytes mechanism;
11785 instead, rs6000_function_arg will return a PARALLEL including a memory
11786 element as necessary. Library support functions for IEEE 128-bit are
11787 assumed to not need the value passed both in GPRs and in vector
11789 if (TARGET_64BIT && !cum->prototype
11790 && (!cum->libcall || !FLOAT128_VECTOR_P (elt_mode)))
11793 /* Otherwise, we pass in VRs only. Check for partial copies. */
11794 passed_in_gprs = false;
11795 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
11796 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
11799 /* In this complicated case we just disable the partial_nregs code. */
11800 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
11803 align_words = rs6000_parm_start (mode, type, cum->words);
11805 if (USE_FP_FOR_ARG_P (cum, elt_mode)
11806 && !(TARGET_AIX && !TARGET_ELF
11807 && type != NULL && AGGREGATE_TYPE_P (type)))
11809 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
11811 /* If we are passing this arg in the fixed parameter save area
11812 (gprs or memory) as well as FPRs, we do not use the partial
11813 bytes mechanism; instead, rs6000_function_arg will return a
11814 PARALLEL including a memory element as necessary. */
11816 && (cum->nargs_prototype <= 0
11817 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
11818 && TARGET_XL_COMPAT
11819 && align_words >= GP_ARG_NUM_REG)))
11822 /* Otherwise, we pass in FPRs only. Check for partial copies. */
11823 passed_in_gprs = false;
11824 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
11826 /* Compute number of bytes / words passed in FPRs. If there
11827 is still space available in the register parameter area
11828 *after* that amount, a part of the argument will be passed
11829 in GPRs. In that case, the total amount passed in any
11830 registers is equal to the amount that would have been passed
11831 in GPRs if everything were passed there, so we fall back to
11832 the GPR code below to compute the appropriate value. */
11833 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
11834 * MIN (8, GET_MODE_SIZE (elt_mode)));
11835 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
11837 if (align_words + fpr_words < GP_ARG_NUM_REG)
11838 passed_in_gprs = true;
11845 && align_words < GP_ARG_NUM_REG
11846 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
11847 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
11849 if (ret != 0 && TARGET_DEBUG_ARG)
11850 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
11855 /* A C expression that indicates when an argument must be passed by
11856 reference. If nonzero for an argument, a copy of that argument is
11857 made in memory and a pointer to the argument is passed instead of
11858 the argument itself. The pointer is passed in whatever way is
11859 appropriate for passing a pointer to that type.
11861 Under V.4, aggregates and long double are passed by reference.
11863 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
11864 reference unless the AltiVec vector extension ABI is in force.
11866 As an extension to all ABIs, variable sized types are passed by
11870 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
11871 machine_mode mode, const_tree type,
11872 bool named ATTRIBUTE_UNUSED)
11877 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD
11878 && FLOAT128_IEEE_P (TYPE_MODE (type)))
11880 if (TARGET_DEBUG_ARG)
11881 fprintf (stderr, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
11885 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
11887 if (TARGET_DEBUG_ARG)
11888 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
11892 if (int_size_in_bytes (type) < 0)
11894 if (TARGET_DEBUG_ARG)
11895 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
11899 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11900 modes only exist for GCC vector types if -maltivec. */
11901 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
11903 if (TARGET_DEBUG_ARG)
11904 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
11908 /* Pass synthetic vectors in memory. */
11909 if (TREE_CODE (type) == VECTOR_TYPE
11910 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
11912 static bool warned_for_pass_big_vectors = false;
11913 if (TARGET_DEBUG_ARG)
11914 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
11915 if (!warned_for_pass_big_vectors)
11917 warning (OPT_Wpsabi, "GCC vector passed by reference: "
11918 "non-standard ABI extension with no compatibility "
11920 warned_for_pass_big_vectors = true;
11928 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
11929 already processes. Return true if the parameter must be passed
11930 (fully or partially) on the stack. */
11933 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
11939 /* Catch errors. */
11940 if (type == NULL || type == error_mark_node)
11943 /* Handle types with no storage requirement. */
11944 if (TYPE_MODE (type) == VOIDmode)
11947 /* Handle complex types. */
11948 if (TREE_CODE (type) == COMPLEX_TYPE)
11949 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
11950 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
11952 /* Handle transparent aggregates. */
11953 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
11954 && TYPE_TRANSPARENT_AGGR (type))
11955 type = TREE_TYPE (first_field (type));
11957 /* See if this arg was passed by invisible reference. */
11958 if (pass_by_reference (get_cumulative_args (args_so_far),
11959 TYPE_MODE (type), type, true))
11960 type = build_pointer_type (type);
11962 /* Find mode as it is passed by the ABI. */
11963 unsignedp = TYPE_UNSIGNED (type);
11964 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
11966 /* If we must pass in stack, we need a stack. */
11967 if (rs6000_must_pass_in_stack (mode, type))
11970 /* If there is no incoming register, we need a stack. */
11971 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
11972 if (entry_parm == NULL)
11975 /* Likewise if we need to pass both in registers and on the stack. */
11976 if (GET_CODE (entry_parm) == PARALLEL
11977 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
11980 /* Also true if we're partially in registers and partially not. */
11981 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
11984 /* Update info on where next arg arrives in registers. */
11985 rs6000_function_arg_advance (args_so_far, mode, type, true);
11989 /* Return true if FUN has no prototype, has a variable argument
11990 list, or passes any parameter in memory. */
11993 rs6000_function_parms_need_stack (tree fun, bool incoming)
11995 tree fntype, result;
11996 CUMULATIVE_ARGS args_so_far_v;
11997 cumulative_args_t args_so_far;
12000 /* Must be a libcall, all of which only use reg parms. */
12005 fntype = TREE_TYPE (fun);
12007 /* Varargs functions need the parameter save area. */
12008 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
12011 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
12012 args_so_far = pack_cumulative_args (&args_so_far_v);
12014 /* When incoming, we will have been passed the function decl.
12015 It is necessary to use the decl to handle K&R style functions,
12016 where TYPE_ARG_TYPES may not be available. */
12019 gcc_assert (DECL_P (fun));
12020 result = DECL_RESULT (fun);
12023 result = TREE_TYPE (fntype);
12025 if (result && aggregate_value_p (result, fntype))
12027 if (!TYPE_P (result))
12028 result = TREE_TYPE (result);
12029 result = build_pointer_type (result);
12030 rs6000_parm_needs_stack (args_so_far, result);
12037 for (parm = DECL_ARGUMENTS (fun);
12038 parm && parm != void_list_node;
12039 parm = TREE_CHAIN (parm))
12040 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
12045 function_args_iterator args_iter;
12048 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
12049 if (rs6000_parm_needs_stack (args_so_far, arg_type))
12056 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12057 usually a constant depending on the ABI. However, in the ELFv2 ABI
12058 the register parameter area is optional when calling a function that
12059 has a prototype is scope, has no variable argument list, and passes
12060 all parameters in registers. */
12063 rs6000_reg_parm_stack_space (tree fun, bool incoming)
12065 int reg_parm_stack_space;
12067 switch (DEFAULT_ABI)
12070 reg_parm_stack_space = 0;
12075 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12079 /* ??? Recomputing this every time is a bit expensive. Is there
12080 a place to cache this information? */
12081 if (rs6000_function_parms_need_stack (fun, incoming))
12082 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
12084 reg_parm_stack_space = 0;
12088 return reg_parm_stack_space;
12092 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
12095 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
12100 for (i = 0; i < nregs; i++)
12102 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
12103 if (reload_completed)
12105 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
12108 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
12109 i * GET_MODE_SIZE (reg_mode));
12112 tem = replace_equiv_address (tem, XEXP (tem, 0));
12116 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
12120 /* Perform any needed actions needed for a function that is receiving a
12121 variable number of arguments.
12125 MODE and TYPE are the mode and type of the current parameter.
12127 PRETEND_SIZE is a variable that should be set to the amount of stack
12128 that must be pushed by the prolog to pretend that our caller pushed
12131 Normally, this macro will push all remaining incoming registers on the
12132 stack and set PRETEND_SIZE to the length of the registers pushed. */
12135 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
12136 tree type, int *pretend_size ATTRIBUTE_UNUSED,
12139 CUMULATIVE_ARGS next_cum;
12140 int reg_size = TARGET_32BIT ? 4 : 8;
12141 rtx save_area = NULL_RTX, mem;
12142 int first_reg_offset;
12143 alias_set_type set;
12145 /* Skip the last named argument. */
12146 next_cum = *get_cumulative_args (cum);
12147 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
12149 if (DEFAULT_ABI == ABI_V4)
12151 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
12155 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
12156 HOST_WIDE_INT offset = 0;
12158 /* Try to optimize the size of the varargs save area.
12159 The ABI requires that ap.reg_save_area is doubleword
12160 aligned, but we don't need to allocate space for all
12161 the bytes, only those to which we actually will save
12163 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
12164 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
12165 if (TARGET_HARD_FLOAT
12166 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12167 && cfun->va_list_fpr_size)
12170 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
12171 * UNITS_PER_FP_WORD;
12172 if (cfun->va_list_fpr_size
12173 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12174 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
12176 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
12177 * UNITS_PER_FP_WORD;
12181 offset = -((first_reg_offset * reg_size) & ~7);
12182 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
12184 gpr_reg_num = cfun->va_list_gpr_size;
12185 if (reg_size == 4 && (first_reg_offset & 1))
12188 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
12191 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
12192 * UNITS_PER_FP_WORD
12193 - (int) (GP_ARG_NUM_REG * reg_size);
12195 if (gpr_size + fpr_size)
12198 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
12199 gcc_assert (MEM_P (reg_save_area));
12200 reg_save_area = XEXP (reg_save_area, 0);
12201 if (GET_CODE (reg_save_area) == PLUS)
12203 gcc_assert (XEXP (reg_save_area, 0)
12204 == virtual_stack_vars_rtx);
12205 gcc_assert (CONST_INT_P (XEXP (reg_save_area, 1)));
12206 offset += INTVAL (XEXP (reg_save_area, 1));
12209 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
12212 cfun->machine->varargs_save_offset = offset;
12213 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
12218 first_reg_offset = next_cum.words;
12219 save_area = crtl->args.internal_arg_pointer;
12221 if (targetm.calls.must_pass_in_stack (mode, type))
12222 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
12225 set = get_varargs_alias_set ();
12226 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
12227 && cfun->va_list_gpr_size)
12229 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
12231 if (va_list_gpr_counter_field)
12232 /* V4 va_list_gpr_size counts number of registers needed. */
12233 n_gpr = cfun->va_list_gpr_size;
12235 /* char * va_list instead counts number of bytes needed. */
12236 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
12241 mem = gen_rtx_MEM (BLKmode,
12242 plus_constant (Pmode, save_area,
12243 first_reg_offset * reg_size));
12244 MEM_NOTRAP_P (mem) = 1;
12245 set_mem_alias_set (mem, set);
12246 set_mem_align (mem, BITS_PER_WORD);
12248 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
12252 /* Save FP registers if needed. */
12253 if (DEFAULT_ABI == ABI_V4
12254 && TARGET_HARD_FLOAT
12256 && next_cum.fregno <= FP_ARG_V4_MAX_REG
12257 && cfun->va_list_fpr_size)
12259 int fregno = next_cum.fregno, nregs;
12260 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
12261 rtx lab = gen_label_rtx ();
12262 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
12263 * UNITS_PER_FP_WORD);
12266 (gen_rtx_SET (pc_rtx,
12267 gen_rtx_IF_THEN_ELSE (VOIDmode,
12268 gen_rtx_NE (VOIDmode, cr1,
12270 gen_rtx_LABEL_REF (VOIDmode, lab),
12274 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
12275 fregno++, off += UNITS_PER_FP_WORD, nregs++)
12277 mem = gen_rtx_MEM (TARGET_HARD_FLOAT ? DFmode : SFmode,
12278 plus_constant (Pmode, save_area, off));
12279 MEM_NOTRAP_P (mem) = 1;
12280 set_mem_alias_set (mem, set);
12281 set_mem_align (mem, GET_MODE_ALIGNMENT (
12282 TARGET_HARD_FLOAT ? DFmode : SFmode));
12283 emit_move_insn (mem, gen_rtx_REG (
12284 TARGET_HARD_FLOAT ? DFmode : SFmode, fregno));
12291 /* Create the va_list data type. */
12294 rs6000_build_builtin_va_list (void)
12296 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
12298 /* For AIX, prefer 'char *' because that's what the system
12299 header files like. */
12300 if (DEFAULT_ABI != ABI_V4)
12301 return build_pointer_type (char_type_node);
12303 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
12304 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
12305 get_identifier ("__va_list_tag"), record);
12307 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
12308 unsigned_char_type_node);
12309 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
12310 unsigned_char_type_node);
12311 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
12312 every user file. */
12313 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12314 get_identifier ("reserved"), short_unsigned_type_node);
12315 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12316 get_identifier ("overflow_arg_area"),
12318 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
12319 get_identifier ("reg_save_area"),
12322 va_list_gpr_counter_field = f_gpr;
12323 va_list_fpr_counter_field = f_fpr;
12325 DECL_FIELD_CONTEXT (f_gpr) = record;
12326 DECL_FIELD_CONTEXT (f_fpr) = record;
12327 DECL_FIELD_CONTEXT (f_res) = record;
12328 DECL_FIELD_CONTEXT (f_ovf) = record;
12329 DECL_FIELD_CONTEXT (f_sav) = record;
12331 TYPE_STUB_DECL (record) = type_decl;
12332 TYPE_NAME (record) = type_decl;
12333 TYPE_FIELDS (record) = f_gpr;
12334 DECL_CHAIN (f_gpr) = f_fpr;
12335 DECL_CHAIN (f_fpr) = f_res;
12336 DECL_CHAIN (f_res) = f_ovf;
12337 DECL_CHAIN (f_ovf) = f_sav;
12339 layout_type (record);
12341 /* The correct type is an array type of one element. */
12342 return build_array_type (record, build_index_type (size_zero_node));
12345 /* Implement va_start. */
12348 rs6000_va_start (tree valist, rtx nextarg)
12350 HOST_WIDE_INT words, n_gpr, n_fpr;
12351 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12352 tree gpr, fpr, ovf, sav, t;
12354 /* Only SVR4 needs something special. */
12355 if (DEFAULT_ABI != ABI_V4)
12357 std_expand_builtin_va_start (valist, nextarg);
12361 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12362 f_fpr = DECL_CHAIN (f_gpr);
12363 f_res = DECL_CHAIN (f_fpr);
12364 f_ovf = DECL_CHAIN (f_res);
12365 f_sav = DECL_CHAIN (f_ovf);
12367 valist = build_simple_mem_ref (valist);
12368 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12369 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12371 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12373 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12376 /* Count number of gp and fp argument registers used. */
12377 words = crtl->args.info.words;
12378 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
12380 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
12383 if (TARGET_DEBUG_ARG)
12384 fprintf (stderr, "va_start: words = " HOST_WIDE_INT_PRINT_DEC", n_gpr = "
12385 HOST_WIDE_INT_PRINT_DEC", n_fpr = " HOST_WIDE_INT_PRINT_DEC"\n",
12386 words, n_gpr, n_fpr);
12388 if (cfun->va_list_gpr_size)
12390 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
12391 build_int_cst (NULL_TREE, n_gpr));
12392 TREE_SIDE_EFFECTS (t) = 1;
12393 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12396 if (cfun->va_list_fpr_size)
12398 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
12399 build_int_cst (NULL_TREE, n_fpr));
12400 TREE_SIDE_EFFECTS (t) = 1;
12401 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12403 #ifdef HAVE_AS_GNU_ATTRIBUTE
12404 if (call_ABI_of_interest (cfun->decl))
12405 rs6000_passes_float = true;
12409 /* Find the overflow area. */
12410 t = make_tree (TREE_TYPE (ovf), crtl->args.internal_arg_pointer);
12412 t = fold_build_pointer_plus_hwi (t, words * MIN_UNITS_PER_WORD);
12413 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
12414 TREE_SIDE_EFFECTS (t) = 1;
12415 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12417 /* If there were no va_arg invocations, don't set up the register
12419 if (!cfun->va_list_gpr_size
12420 && !cfun->va_list_fpr_size
12421 && n_gpr < GP_ARG_NUM_REG
12422 && n_fpr < FP_ARG_V4_MAX_REG)
12425 /* Find the register save area. */
12426 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
12427 if (cfun->machine->varargs_save_offset)
12428 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
12429 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
12430 TREE_SIDE_EFFECTS (t) = 1;
12431 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
12434 /* Implement va_arg. */
12437 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
12438 gimple_seq *post_p)
12440 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
12441 tree gpr, fpr, ovf, sav, reg, t, u;
12442 int size, rsize, n_reg, sav_ofs, sav_scale;
12443 tree lab_false, lab_over, addr;
12445 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
12449 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
12451 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
12452 return build_va_arg_indirect_ref (t);
12455 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
12456 earlier version of gcc, with the property that it always applied alignment
12457 adjustments to the va-args (even for zero-sized types). The cheapest way
12458 to deal with this is to replicate the effect of the part of
12459 std_gimplify_va_arg_expr that carries out the align adjust, for the case
12461 We don't need to check for pass-by-reference because of the test above.
12462 We can return a simplifed answer, since we know there's no offset to add. */
12465 && rs6000_darwin64_abi)
12466 || DEFAULT_ABI == ABI_ELFv2
12467 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
12468 && integer_zerop (TYPE_SIZE (type)))
12470 unsigned HOST_WIDE_INT align, boundary;
12471 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
12472 align = PARM_BOUNDARY / BITS_PER_UNIT;
12473 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
12474 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
12475 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
12476 boundary /= BITS_PER_UNIT;
12477 if (boundary > align)
12480 /* This updates arg ptr by the amount that would be necessary
12481 to align the zero-sized (but not zero-alignment) item. */
12482 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
12483 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
12484 gimplify_and_add (t, pre_p);
12486 t = fold_convert (sizetype, valist_tmp);
12487 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
12488 fold_convert (TREE_TYPE (valist),
12489 fold_build2 (BIT_AND_EXPR, sizetype, t,
12490 size_int (-boundary))));
12491 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
12492 gimplify_and_add (t, pre_p);
12494 /* Since it is zero-sized there's no increment for the item itself. */
12495 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
12496 return build_va_arg_indirect_ref (valist_tmp);
12499 if (DEFAULT_ABI != ABI_V4)
12501 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
12503 tree elem_type = TREE_TYPE (type);
12504 machine_mode elem_mode = TYPE_MODE (elem_type);
12505 int elem_size = GET_MODE_SIZE (elem_mode);
12507 if (elem_size < UNITS_PER_WORD)
12509 tree real_part, imag_part;
12510 gimple_seq post = NULL;
12512 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
12514 /* Copy the value into a temporary, lest the formal temporary
12515 be reused out from under us. */
12516 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
12517 gimple_seq_add_seq (pre_p, post);
12519 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
12522 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
12526 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
12529 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
12530 f_fpr = DECL_CHAIN (f_gpr);
12531 f_res = DECL_CHAIN (f_fpr);
12532 f_ovf = DECL_CHAIN (f_res);
12533 f_sav = DECL_CHAIN (f_ovf);
12535 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
12536 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
12538 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
12540 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
12543 size = int_size_in_bytes (type);
12544 rsize = (size + 3) / 4;
12545 int pad = 4 * rsize - size;
12548 machine_mode mode = TYPE_MODE (type);
12549 if (abi_v4_pass_in_fpr (mode, false))
12551 /* FP args go in FP registers, if present. */
12553 n_reg = (size + 7) / 8;
12554 sav_ofs = (TARGET_HARD_FLOAT ? 8 : 4) * 4;
12555 sav_scale = (TARGET_HARD_FLOAT ? 8 : 4);
12556 if (mode != SFmode && mode != SDmode)
12561 /* Otherwise into GP registers. */
12570 /* Pull the value out of the saved registers.... */
12573 addr = create_tmp_var (ptr_type_node, "addr");
12575 /* AltiVec vectors never go in registers when -mabi=altivec. */
12576 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12580 lab_false = create_artificial_label (input_location);
12581 lab_over = create_artificial_label (input_location);
12583 /* Long long is aligned in the registers. As are any other 2 gpr
12584 item such as complex int due to a historical mistake. */
12586 if (n_reg == 2 && reg == gpr)
12589 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12590 build_int_cst (TREE_TYPE (reg), n_reg - 1));
12591 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
12592 unshare_expr (reg), u);
12594 /* _Decimal128 is passed in even/odd fpr pairs; the stored
12595 reg number is 0 for f1, so we want to make it odd. */
12596 else if (reg == fpr && mode == TDmode)
12598 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12599 build_int_cst (TREE_TYPE (reg), 1));
12600 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
12603 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
12604 t = build2 (GE_EXPR, boolean_type_node, u, t);
12605 u = build1 (GOTO_EXPR, void_type_node, lab_false);
12606 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
12607 gimplify_and_add (t, pre_p);
12611 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
12613 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
12614 build_int_cst (TREE_TYPE (reg), n_reg));
12615 u = fold_convert (sizetype, u);
12616 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
12617 t = fold_build_pointer_plus (t, u);
12619 /* _Decimal32 varargs are located in the second word of the 64-bit
12620 FP register for 32-bit binaries. */
12621 if (TARGET_32BIT && TARGET_HARD_FLOAT && mode == SDmode)
12622 t = fold_build_pointer_plus_hwi (t, size);
12624 /* Args are passed right-aligned. */
12625 if (BYTES_BIG_ENDIAN)
12626 t = fold_build_pointer_plus_hwi (t, pad);
12628 gimplify_assign (addr, t, pre_p);
12630 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
12632 stmt = gimple_build_label (lab_false);
12633 gimple_seq_add_stmt (pre_p, stmt);
12635 if ((n_reg == 2 && !regalign) || n_reg > 2)
12637 /* Ensure that we don't find any more args in regs.
12638 Alignment has taken care of for special cases. */
12639 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
12643 /* ... otherwise out of the overflow area. */
12645 /* Care for on-stack alignment if needed. */
12649 t = fold_build_pointer_plus_hwi (t, align - 1);
12650 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
12651 build_int_cst (TREE_TYPE (t), -align));
12654 /* Args are passed right-aligned. */
12655 if (BYTES_BIG_ENDIAN)
12656 t = fold_build_pointer_plus_hwi (t, pad);
12658 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
12660 gimplify_assign (unshare_expr (addr), t, pre_p);
12662 t = fold_build_pointer_plus_hwi (t, size);
12663 gimplify_assign (unshare_expr (ovf), t, pre_p);
12667 stmt = gimple_build_label (lab_over);
12668 gimple_seq_add_stmt (pre_p, stmt);
12671 if (STRICT_ALIGNMENT
12672 && (TYPE_ALIGN (type)
12673 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
12675 /* The value (of type complex double, for example) may not be
12676 aligned in memory in the saved registers, so copy via a
12677 temporary. (This is the same code as used for SPARC.) */
12678 tree tmp = create_tmp_var (type, "va_arg_tmp");
12679 tree dest_addr = build_fold_addr_expr (tmp);
12681 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
12682 3, dest_addr, addr, size_int (rsize * 4));
12683 TREE_ADDRESSABLE (tmp) = 1;
12685 gimplify_and_add (copy, pre_p);
12689 addr = fold_convert (ptrtype, addr);
12690 return build_va_arg_indirect_ref (addr);
12696 def_builtin (const char *name, tree type, enum rs6000_builtins code)
12699 unsigned classify = rs6000_builtin_info[(int)code].attr;
12700 const char *attr_string = "";
12702 gcc_assert (name != NULL);
12703 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
12705 if (rs6000_builtin_decls[(int)code])
12706 fatal_error (input_location,
12707 "internal error: builtin function %qs already processed",
12710 rs6000_builtin_decls[(int)code] = t =
12711 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
12713 /* Set any special attributes. */
12714 if ((classify & RS6000_BTC_CONST) != 0)
12716 /* const function, function only depends on the inputs. */
12717 TREE_READONLY (t) = 1;
12718 TREE_NOTHROW (t) = 1;
12719 attr_string = ", const";
12721 else if ((classify & RS6000_BTC_PURE) != 0)
12723 /* pure function, function can read global memory, but does not set any
12725 DECL_PURE_P (t) = 1;
12726 TREE_NOTHROW (t) = 1;
12727 attr_string = ", pure";
12729 else if ((classify & RS6000_BTC_FP) != 0)
12731 /* Function is a math function. If rounding mode is on, then treat the
12732 function as not reading global memory, but it can have arbitrary side
12733 effects. If it is off, then assume the function is a const function.
12734 This mimics the ATTR_MATHFN_FPROUNDING attribute in
12735 builtin-attribute.def that is used for the math functions. */
12736 TREE_NOTHROW (t) = 1;
12737 if (flag_rounding_math)
12739 DECL_PURE_P (t) = 1;
12740 DECL_IS_NOVOPS (t) = 1;
12741 attr_string = ", fp, pure";
12745 TREE_READONLY (t) = 1;
12746 attr_string = ", fp, const";
12749 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
12750 gcc_unreachable ();
12752 if (TARGET_DEBUG_BUILTIN)
12753 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
12754 (int)code, name, attr_string);
12757 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
12759 #undef RS6000_BUILTIN_0
12760 #undef RS6000_BUILTIN_1
12761 #undef RS6000_BUILTIN_2
12762 #undef RS6000_BUILTIN_3
12763 #undef RS6000_BUILTIN_A
12764 #undef RS6000_BUILTIN_D
12765 #undef RS6000_BUILTIN_H
12766 #undef RS6000_BUILTIN_P
12767 #undef RS6000_BUILTIN_X
12769 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12770 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12771 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12772 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
12773 { MASK, ICODE, NAME, ENUM },
12775 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12776 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12777 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12778 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12779 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12781 static const struct builtin_description bdesc_3arg[] =
12783 #include "rs6000-builtin.def"
12786 /* DST operations: void foo (void *, const int, const char). */
12788 #undef RS6000_BUILTIN_0
12789 #undef RS6000_BUILTIN_1
12790 #undef RS6000_BUILTIN_2
12791 #undef RS6000_BUILTIN_3
12792 #undef RS6000_BUILTIN_A
12793 #undef RS6000_BUILTIN_D
12794 #undef RS6000_BUILTIN_H
12795 #undef RS6000_BUILTIN_P
12796 #undef RS6000_BUILTIN_X
12798 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12799 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12800 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12801 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12802 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12803 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
12804 { MASK, ICODE, NAME, ENUM },
12806 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12807 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12808 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12810 static const struct builtin_description bdesc_dst[] =
12812 #include "rs6000-builtin.def"
12815 /* Simple binary operations: VECc = foo (VECa, VECb). */
12817 #undef RS6000_BUILTIN_0
12818 #undef RS6000_BUILTIN_1
12819 #undef RS6000_BUILTIN_2
12820 #undef RS6000_BUILTIN_3
12821 #undef RS6000_BUILTIN_A
12822 #undef RS6000_BUILTIN_D
12823 #undef RS6000_BUILTIN_H
12824 #undef RS6000_BUILTIN_P
12825 #undef RS6000_BUILTIN_X
12827 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12828 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12829 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
12830 { MASK, ICODE, NAME, ENUM },
12832 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12833 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12834 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12835 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12836 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12837 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12839 static const struct builtin_description bdesc_2arg[] =
12841 #include "rs6000-builtin.def"
12844 #undef RS6000_BUILTIN_0
12845 #undef RS6000_BUILTIN_1
12846 #undef RS6000_BUILTIN_2
12847 #undef RS6000_BUILTIN_3
12848 #undef RS6000_BUILTIN_A
12849 #undef RS6000_BUILTIN_D
12850 #undef RS6000_BUILTIN_H
12851 #undef RS6000_BUILTIN_P
12852 #undef RS6000_BUILTIN_X
12854 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12855 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12856 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12857 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12858 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12859 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12860 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12861 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
12862 { MASK, ICODE, NAME, ENUM },
12864 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12866 /* AltiVec predicates. */
12868 static const struct builtin_description bdesc_altivec_preds[] =
12870 #include "rs6000-builtin.def"
12873 /* ABS* operations. */
12875 #undef RS6000_BUILTIN_0
12876 #undef RS6000_BUILTIN_1
12877 #undef RS6000_BUILTIN_2
12878 #undef RS6000_BUILTIN_3
12879 #undef RS6000_BUILTIN_A
12880 #undef RS6000_BUILTIN_D
12881 #undef RS6000_BUILTIN_H
12882 #undef RS6000_BUILTIN_P
12883 #undef RS6000_BUILTIN_X
12885 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12886 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12887 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12888 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12889 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
12890 { MASK, ICODE, NAME, ENUM },
12892 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12893 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12894 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12895 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12897 static const struct builtin_description bdesc_abs[] =
12899 #include "rs6000-builtin.def"
12902 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
12905 #undef RS6000_BUILTIN_0
12906 #undef RS6000_BUILTIN_1
12907 #undef RS6000_BUILTIN_2
12908 #undef RS6000_BUILTIN_3
12909 #undef RS6000_BUILTIN_A
12910 #undef RS6000_BUILTIN_D
12911 #undef RS6000_BUILTIN_H
12912 #undef RS6000_BUILTIN_P
12913 #undef RS6000_BUILTIN_X
12915 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12916 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
12917 { MASK, ICODE, NAME, ENUM },
12919 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12920 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12921 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12922 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12923 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12924 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12925 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12927 static const struct builtin_description bdesc_1arg[] =
12929 #include "rs6000-builtin.def"
12932 /* Simple no-argument operations: result = __builtin_darn_32 () */
12934 #undef RS6000_BUILTIN_0
12935 #undef RS6000_BUILTIN_1
12936 #undef RS6000_BUILTIN_2
12937 #undef RS6000_BUILTIN_3
12938 #undef RS6000_BUILTIN_A
12939 #undef RS6000_BUILTIN_D
12940 #undef RS6000_BUILTIN_H
12941 #undef RS6000_BUILTIN_P
12942 #undef RS6000_BUILTIN_X
12944 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
12945 { MASK, ICODE, NAME, ENUM },
12947 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12948 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12949 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12950 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12951 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12952 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
12953 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12954 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12956 static const struct builtin_description bdesc_0arg[] =
12958 #include "rs6000-builtin.def"
12961 /* HTM builtins. */
12962 #undef RS6000_BUILTIN_0
12963 #undef RS6000_BUILTIN_1
12964 #undef RS6000_BUILTIN_2
12965 #undef RS6000_BUILTIN_3
12966 #undef RS6000_BUILTIN_A
12967 #undef RS6000_BUILTIN_D
12968 #undef RS6000_BUILTIN_H
12969 #undef RS6000_BUILTIN_P
12970 #undef RS6000_BUILTIN_X
12972 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
12973 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
12974 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
12975 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
12976 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
12977 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
12978 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
12979 { MASK, ICODE, NAME, ENUM },
12981 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
12982 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
12984 static const struct builtin_description bdesc_htm[] =
12986 #include "rs6000-builtin.def"
12989 #undef RS6000_BUILTIN_0
12990 #undef RS6000_BUILTIN_1
12991 #undef RS6000_BUILTIN_2
12992 #undef RS6000_BUILTIN_3
12993 #undef RS6000_BUILTIN_A
12994 #undef RS6000_BUILTIN_D
12995 #undef RS6000_BUILTIN_H
12996 #undef RS6000_BUILTIN_P
12998 /* Return true if a builtin function is overloaded. */
13000 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
13002 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
13006 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode)
13008 return rs6000_builtin_info[(int)fncode].name;
13011 /* Expand an expression EXP that calls a builtin without arguments. */
13013 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
13016 machine_mode tmode = insn_data[icode].operand[0].mode;
13018 if (icode == CODE_FOR_nothing)
13019 /* Builtin not supported on this processor. */
13022 if (icode == CODE_FOR_rs6000_mffsl
13023 && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13025 error ("%<__builtin_mffsl%> not supported with %<-msoft-float%>");
13030 || GET_MODE (target) != tmode
13031 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13032 target = gen_reg_rtx (tmode);
13034 pat = GEN_FCN (icode) (target);
13044 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
13047 tree arg0 = CALL_EXPR_ARG (exp, 0);
13048 tree arg1 = CALL_EXPR_ARG (exp, 1);
13049 rtx op0 = expand_normal (arg0);
13050 rtx op1 = expand_normal (arg1);
13051 machine_mode mode0 = insn_data[icode].operand[0].mode;
13052 machine_mode mode1 = insn_data[icode].operand[1].mode;
13054 if (icode == CODE_FOR_nothing)
13055 /* Builtin not supported on this processor. */
13058 /* If we got invalid arguments bail out before generating bad rtl. */
13059 if (arg0 == error_mark_node || arg1 == error_mark_node)
13062 if (!CONST_INT_P (op0)
13063 || INTVAL (op0) > 255
13064 || INTVAL (op0) < 0)
13066 error ("argument 1 must be an 8-bit field value");
13070 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13071 op0 = copy_to_mode_reg (mode0, op0);
13073 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13074 op1 = copy_to_mode_reg (mode1, op1);
13076 pat = GEN_FCN (icode) (op0, op1);
13085 rs6000_expand_mtfsb_builtin (enum insn_code icode, tree exp)
13088 tree arg0 = CALL_EXPR_ARG (exp, 0);
13089 rtx op0 = expand_normal (arg0);
13091 if (icode == CODE_FOR_nothing)
13092 /* Builtin not supported on this processor. */
13095 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13097 error ("%<__builtin_mtfsb0%> and %<__builtin_mtfsb1%> not supported with "
13098 "%<-msoft-float%>");
13102 /* If we got invalid arguments bail out before generating bad rtl. */
13103 if (arg0 == error_mark_node)
13106 /* Only allow bit numbers 0 to 31. */
13107 if (!u5bit_cint_operand (op0, VOIDmode))
13109 error ("Argument must be a constant between 0 and 31.");
13113 pat = GEN_FCN (icode) (op0);
13122 rs6000_expand_set_fpscr_rn_builtin (enum insn_code icode, tree exp)
13125 tree arg0 = CALL_EXPR_ARG (exp, 0);
13126 rtx op0 = expand_normal (arg0);
13127 machine_mode mode0 = insn_data[icode].operand[0].mode;
13129 if (icode == CODE_FOR_nothing)
13130 /* Builtin not supported on this processor. */
13133 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13135 error ("%<__builtin_set_fpscr_rn%> not supported with %<-msoft-float%>");
13139 /* If we got invalid arguments bail out before generating bad rtl. */
13140 if (arg0 == error_mark_node)
13143 /* If the argument is a constant, check the range. Argument can only be a
13144 2-bit value. Unfortunately, can't check the range of the value at
13145 compile time if the argument is a variable. The least significant two
13146 bits of the argument, regardless of type, are used to set the rounding
13147 mode. All other bits are ignored. */
13148 if (CONST_INT_P (op0) && !const_0_to_3_operand(op0, VOIDmode))
13150 error ("Argument must be a value between 0 and 3.");
13154 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13155 op0 = copy_to_mode_reg (mode0, op0);
13157 pat = GEN_FCN (icode) (op0);
13165 rs6000_expand_set_fpscr_drn_builtin (enum insn_code icode, tree exp)
13168 tree arg0 = CALL_EXPR_ARG (exp, 0);
13169 rtx op0 = expand_normal (arg0);
13170 machine_mode mode0 = insn_data[icode].operand[0].mode;
13173 /* Builtin not supported in 32-bit mode. */
13174 fatal_error (input_location,
13175 "%<__builtin_set_fpscr_drn%> is not supported "
13178 if (rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
13180 error ("%<__builtin_set_fpscr_drn%> not supported with %<-msoft-float%>");
13184 if (icode == CODE_FOR_nothing)
13185 /* Builtin not supported on this processor. */
13188 /* If we got invalid arguments bail out before generating bad rtl. */
13189 if (arg0 == error_mark_node)
13192 /* If the argument is a constant, check the range. Agrument can only be a
13193 3-bit value. Unfortunately, can't check the range of the value at
13194 compile time if the argument is a variable. The least significant two
13195 bits of the argument, regardless of type, are used to set the rounding
13196 mode. All other bits are ignored. */
13197 if (CONST_INT_P (op0) && !const_0_to_7_operand(op0, VOIDmode))
13199 error ("Argument must be a value between 0 and 7.");
13203 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13204 op0 = copy_to_mode_reg (mode0, op0);
13206 pat = GEN_FCN (icode) (op0);
13215 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
13218 tree arg0 = CALL_EXPR_ARG (exp, 0);
13219 rtx op0 = expand_normal (arg0);
13220 machine_mode tmode = insn_data[icode].operand[0].mode;
13221 machine_mode mode0 = insn_data[icode].operand[1].mode;
13223 if (icode == CODE_FOR_nothing)
13224 /* Builtin not supported on this processor. */
13227 /* If we got invalid arguments bail out before generating bad rtl. */
13228 if (arg0 == error_mark_node)
13231 if (icode == CODE_FOR_altivec_vspltisb
13232 || icode == CODE_FOR_altivec_vspltish
13233 || icode == CODE_FOR_altivec_vspltisw)
13235 /* Only allow 5-bit *signed* literals. */
13236 if (!CONST_INT_P (op0)
13237 || INTVAL (op0) > 15
13238 || INTVAL (op0) < -16)
13240 error ("argument 1 must be a 5-bit signed literal");
13241 return CONST0_RTX (tmode);
13246 || GET_MODE (target) != tmode
13247 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13248 target = gen_reg_rtx (tmode);
13250 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13251 op0 = copy_to_mode_reg (mode0, op0);
13253 pat = GEN_FCN (icode) (target, op0);
13262 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
13264 rtx pat, scratch1, scratch2;
13265 tree arg0 = CALL_EXPR_ARG (exp, 0);
13266 rtx op0 = expand_normal (arg0);
13267 machine_mode tmode = insn_data[icode].operand[0].mode;
13268 machine_mode mode0 = insn_data[icode].operand[1].mode;
13270 /* If we have invalid arguments, bail out before generating bad rtl. */
13271 if (arg0 == error_mark_node)
13275 || GET_MODE (target) != tmode
13276 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13277 target = gen_reg_rtx (tmode);
13279 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13280 op0 = copy_to_mode_reg (mode0, op0);
13282 scratch1 = gen_reg_rtx (mode0);
13283 scratch2 = gen_reg_rtx (mode0);
13285 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
13294 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
13297 tree arg0 = CALL_EXPR_ARG (exp, 0);
13298 tree arg1 = CALL_EXPR_ARG (exp, 1);
13299 rtx op0 = expand_normal (arg0);
13300 rtx op1 = expand_normal (arg1);
13301 machine_mode tmode = insn_data[icode].operand[0].mode;
13302 machine_mode mode0 = insn_data[icode].operand[1].mode;
13303 machine_mode mode1 = insn_data[icode].operand[2].mode;
13305 if (icode == CODE_FOR_nothing)
13306 /* Builtin not supported on this processor. */
13309 /* If we got invalid arguments bail out before generating bad rtl. */
13310 if (arg0 == error_mark_node || arg1 == error_mark_node)
13313 if (icode == CODE_FOR_unpackv1ti
13314 || icode == CODE_FOR_unpackkf
13315 || icode == CODE_FOR_unpacktf
13316 || icode == CODE_FOR_unpackif
13317 || icode == CODE_FOR_unpacktd)
13319 /* Only allow 1-bit unsigned literals. */
13321 if (TREE_CODE (arg1) != INTEGER_CST
13322 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))
13324 error ("argument 2 must be a 1-bit unsigned literal");
13325 return CONST0_RTX (tmode);
13328 else if (icode == CODE_FOR_altivec_vspltw)
13330 /* Only allow 2-bit unsigned literals. */
13332 if (TREE_CODE (arg1) != INTEGER_CST
13333 || TREE_INT_CST_LOW (arg1) & ~3)
13335 error ("argument 2 must be a 2-bit unsigned literal");
13336 return CONST0_RTX (tmode);
13339 else if (icode == CODE_FOR_altivec_vsplth)
13341 /* Only allow 3-bit unsigned literals. */
13343 if (TREE_CODE (arg1) != INTEGER_CST
13344 || TREE_INT_CST_LOW (arg1) & ~7)
13346 error ("argument 2 must be a 3-bit unsigned literal");
13347 return CONST0_RTX (tmode);
13350 else if (icode == CODE_FOR_altivec_vspltb)
13352 /* Only allow 4-bit unsigned literals. */
13354 if (TREE_CODE (arg1) != INTEGER_CST
13355 || TREE_INT_CST_LOW (arg1) & ~15)
13357 error ("argument 2 must be a 4-bit unsigned literal");
13358 return CONST0_RTX (tmode);
13361 else if (icode == CODE_FOR_altivec_vcfux
13362 || icode == CODE_FOR_altivec_vcfsx
13363 || icode == CODE_FOR_altivec_vctsxs
13364 || icode == CODE_FOR_altivec_vctuxs)
13366 /* Only allow 5-bit unsigned literals. */
13368 if (TREE_CODE (arg1) != INTEGER_CST
13369 || TREE_INT_CST_LOW (arg1) & ~0x1f)
13371 error ("argument 2 must be a 5-bit unsigned literal");
13372 return CONST0_RTX (tmode);
13375 else if (icode == CODE_FOR_dfptstsfi_eq_dd
13376 || icode == CODE_FOR_dfptstsfi_lt_dd
13377 || icode == CODE_FOR_dfptstsfi_gt_dd
13378 || icode == CODE_FOR_dfptstsfi_unordered_dd
13379 || icode == CODE_FOR_dfptstsfi_eq_td
13380 || icode == CODE_FOR_dfptstsfi_lt_td
13381 || icode == CODE_FOR_dfptstsfi_gt_td
13382 || icode == CODE_FOR_dfptstsfi_unordered_td)
13384 /* Only allow 6-bit unsigned literals. */
13386 if (TREE_CODE (arg0) != INTEGER_CST
13387 || !IN_RANGE (TREE_INT_CST_LOW (arg0), 0, 63))
13389 error ("argument 1 must be a 6-bit unsigned literal");
13390 return CONST0_RTX (tmode);
13393 else if (icode == CODE_FOR_xststdcqp_kf
13394 || icode == CODE_FOR_xststdcqp_tf
13395 || icode == CODE_FOR_xststdcdp
13396 || icode == CODE_FOR_xststdcsp
13397 || icode == CODE_FOR_xvtstdcdp
13398 || icode == CODE_FOR_xvtstdcsp)
13400 /* Only allow 7-bit unsigned literals. */
13402 if (TREE_CODE (arg1) != INTEGER_CST
13403 || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 127))
13405 error ("argument 2 must be a 7-bit unsigned literal");
13406 return CONST0_RTX (tmode);
13411 || GET_MODE (target) != tmode
13412 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13413 target = gen_reg_rtx (tmode);
13415 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13416 op0 = copy_to_mode_reg (mode0, op0);
13417 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13418 op1 = copy_to_mode_reg (mode1, op1);
13420 pat = GEN_FCN (icode) (target, op0, op1);
13429 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
13432 tree cr6_form = CALL_EXPR_ARG (exp, 0);
13433 tree arg0 = CALL_EXPR_ARG (exp, 1);
13434 tree arg1 = CALL_EXPR_ARG (exp, 2);
13435 rtx op0 = expand_normal (arg0);
13436 rtx op1 = expand_normal (arg1);
13437 machine_mode tmode = SImode;
13438 machine_mode mode0 = insn_data[icode].operand[1].mode;
13439 machine_mode mode1 = insn_data[icode].operand[2].mode;
13442 if (TREE_CODE (cr6_form) != INTEGER_CST)
13444 error ("argument 1 of %qs must be a constant",
13445 "__builtin_altivec_predicate");
13449 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
13451 gcc_assert (mode0 == mode1);
13453 /* If we have invalid arguments, bail out before generating bad rtl. */
13454 if (arg0 == error_mark_node || arg1 == error_mark_node)
13458 || GET_MODE (target) != tmode
13459 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13460 target = gen_reg_rtx (tmode);
13462 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13463 op0 = copy_to_mode_reg (mode0, op0);
13464 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13465 op1 = copy_to_mode_reg (mode1, op1);
13467 /* Note that for many of the relevant operations (e.g. cmpne or
13468 cmpeq) with float or double operands, it makes more sense for the
13469 mode of the allocated scratch register to select a vector of
13470 integer. But the choice to copy the mode of operand 0 was made
13471 long ago and there are no plans to change it. */
13472 scratch = gen_reg_rtx (mode0);
13474 pat = GEN_FCN (icode) (scratch, op0, op1);
13479 /* The vec_any* and vec_all* predicates use the same opcodes for two
13480 different operations, but the bits in CR6 will be different
13481 depending on what information we want. So we have to play tricks
13482 with CR6 to get the right bits out.
13484 If you think this is disgusting, look at the specs for the
13485 AltiVec predicates. */
13487 switch (cr6_form_int)
13490 emit_insn (gen_cr6_test_for_zero (target));
13493 emit_insn (gen_cr6_test_for_zero_reverse (target));
13496 emit_insn (gen_cr6_test_for_lt (target));
13499 emit_insn (gen_cr6_test_for_lt_reverse (target));
13502 error ("argument 1 of %qs is out of range",
13503 "__builtin_altivec_predicate");
13511 swap_endian_selector_for_mode (machine_mode mode)
13513 unsigned int swap1[16] = {15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0};
13514 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
13515 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
13516 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
13518 unsigned int *swaparray, i;
13538 gcc_unreachable ();
13541 for (i = 0; i < 16; ++i)
13542 perm[i] = GEN_INT (swaparray[i]);
13544 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode,
13545 gen_rtvec_v (16, perm)));
13549 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
13552 tree arg0 = CALL_EXPR_ARG (exp, 0);
13553 tree arg1 = CALL_EXPR_ARG (exp, 1);
13554 machine_mode tmode = insn_data[icode].operand[0].mode;
13555 machine_mode mode0 = Pmode;
13556 machine_mode mode1 = Pmode;
13557 rtx op0 = expand_normal (arg0);
13558 rtx op1 = expand_normal (arg1);
13560 if (icode == CODE_FOR_nothing)
13561 /* Builtin not supported on this processor. */
13564 /* If we got invalid arguments bail out before generating bad rtl. */
13565 if (arg0 == error_mark_node || arg1 == error_mark_node)
13569 || GET_MODE (target) != tmode
13570 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13571 target = gen_reg_rtx (tmode);
13573 op1 = copy_to_mode_reg (mode1, op1);
13575 /* For LVX, express the RTL accurately by ANDing the address with -16.
13576 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
13577 so the raw address is fine. */
13578 if (icode == CODE_FOR_altivec_lvx_v1ti
13579 || icode == CODE_FOR_altivec_lvx_v2df
13580 || icode == CODE_FOR_altivec_lvx_v2di
13581 || icode == CODE_FOR_altivec_lvx_v4sf
13582 || icode == CODE_FOR_altivec_lvx_v4si
13583 || icode == CODE_FOR_altivec_lvx_v8hi
13584 || icode == CODE_FOR_altivec_lvx_v16qi)
13587 if (op0 == const0_rtx)
13591 op0 = copy_to_mode_reg (mode0, op0);
13592 rawaddr = gen_rtx_PLUS (Pmode, op1, op0);
13594 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
13595 addr = gen_rtx_MEM (blk ? BLKmode : tmode, addr);
13597 emit_insn (gen_rtx_SET (target, addr));
13601 if (op0 == const0_rtx)
13602 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
13605 op0 = copy_to_mode_reg (mode0, op0);
13606 addr = gen_rtx_MEM (blk ? BLKmode : tmode,
13607 gen_rtx_PLUS (Pmode, op1, op0));
13610 pat = GEN_FCN (icode) (target, addr);
13620 altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
13623 tree arg0 = CALL_EXPR_ARG (exp, 0);
13624 tree arg1 = CALL_EXPR_ARG (exp, 1);
13625 tree arg2 = CALL_EXPR_ARG (exp, 2);
13626 rtx op0 = expand_normal (arg0);
13627 rtx op1 = expand_normal (arg1);
13628 rtx op2 = expand_normal (arg2);
13629 machine_mode mode0 = insn_data[icode].operand[0].mode;
13630 machine_mode mode1 = insn_data[icode].operand[1].mode;
13631 machine_mode mode2 = insn_data[icode].operand[2].mode;
13633 if (icode == CODE_FOR_nothing)
13634 /* Builtin not supported on this processor. */
13637 /* If we got invalid arguments bail out before generating bad rtl. */
13638 if (arg0 == error_mark_node
13639 || arg1 == error_mark_node
13640 || arg2 == error_mark_node)
13643 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13644 op0 = copy_to_mode_reg (mode0, op0);
13645 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13646 op1 = copy_to_mode_reg (mode1, op1);
13647 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
13648 op2 = copy_to_mode_reg (mode2, op2);
13650 pat = GEN_FCN (icode) (op0, op1, op2);
13658 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
13660 tree arg0 = CALL_EXPR_ARG (exp, 0);
13661 tree arg1 = CALL_EXPR_ARG (exp, 1);
13662 tree arg2 = CALL_EXPR_ARG (exp, 2);
13663 rtx op0 = expand_normal (arg0);
13664 rtx op1 = expand_normal (arg1);
13665 rtx op2 = expand_normal (arg2);
13666 rtx pat, addr, rawaddr;
13667 machine_mode tmode = insn_data[icode].operand[0].mode;
13668 machine_mode smode = insn_data[icode].operand[1].mode;
13669 machine_mode mode1 = Pmode;
13670 machine_mode mode2 = Pmode;
13672 /* Invalid arguments. Bail before doing anything stoopid! */
13673 if (arg0 == error_mark_node
13674 || arg1 == error_mark_node
13675 || arg2 == error_mark_node)
13678 op2 = copy_to_mode_reg (mode2, op2);
13680 /* For STVX, express the RTL accurately by ANDing the address with -16.
13681 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
13682 so the raw address is fine. */
13683 if (icode == CODE_FOR_altivec_stvx_v2df
13684 || icode == CODE_FOR_altivec_stvx_v2di
13685 || icode == CODE_FOR_altivec_stvx_v4sf
13686 || icode == CODE_FOR_altivec_stvx_v4si
13687 || icode == CODE_FOR_altivec_stvx_v8hi
13688 || icode == CODE_FOR_altivec_stvx_v16qi)
13690 if (op1 == const0_rtx)
13694 op1 = copy_to_mode_reg (mode1, op1);
13695 rawaddr = gen_rtx_PLUS (Pmode, op2, op1);
13698 addr = gen_rtx_AND (Pmode, rawaddr, gen_rtx_CONST_INT (Pmode, -16));
13699 addr = gen_rtx_MEM (tmode, addr);
13701 op0 = copy_to_mode_reg (tmode, op0);
13703 emit_insn (gen_rtx_SET (addr, op0));
13707 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
13708 op0 = copy_to_mode_reg (smode, op0);
13710 if (op1 == const0_rtx)
13711 addr = gen_rtx_MEM (tmode, op2);
13714 op1 = copy_to_mode_reg (mode1, op1);
13715 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op2, op1));
13718 pat = GEN_FCN (icode) (addr, op0);
13726 /* Return the appropriate SPR number associated with the given builtin. */
13727 static inline HOST_WIDE_INT
13728 htm_spr_num (enum rs6000_builtins code)
13730 if (code == HTM_BUILTIN_GET_TFHAR
13731 || code == HTM_BUILTIN_SET_TFHAR)
13733 else if (code == HTM_BUILTIN_GET_TFIAR
13734 || code == HTM_BUILTIN_SET_TFIAR)
13736 else if (code == HTM_BUILTIN_GET_TEXASR
13737 || code == HTM_BUILTIN_SET_TEXASR)
13739 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
13740 || code == HTM_BUILTIN_SET_TEXASRU);
13741 return TEXASRU_SPR;
13744 /* Return the correct ICODE value depending on whether we are
13745 setting or reading the HTM SPRs. */
13746 static inline enum insn_code
13747 rs6000_htm_spr_icode (bool nonvoid)
13750 return (TARGET_POWERPC64) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
13752 return (TARGET_POWERPC64) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
13755 /* Expand the HTM builtin in EXP and store the result in TARGET.
13756 Store true in *EXPANDEDP if we found a builtin to expand. */
13758 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
13760 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13761 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
13762 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
13763 const struct builtin_description *d;
13768 if (!TARGET_POWERPC64
13769 && (fcode == HTM_BUILTIN_TABORTDC
13770 || fcode == HTM_BUILTIN_TABORTDCI))
13772 size_t uns_fcode = (size_t)fcode;
13773 const char *name = rs6000_builtin_info[uns_fcode].name;
13774 error ("builtin %qs is only valid in 64-bit mode", name);
13778 /* Expand the HTM builtins. */
13780 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
13781 if (d->code == fcode)
13783 rtx op[MAX_HTM_OPERANDS], pat;
13786 call_expr_arg_iterator iter;
13787 unsigned attr = rs6000_builtin_info[fcode].attr;
13788 enum insn_code icode = d->icode;
13789 const struct insn_operand_data *insn_op;
13790 bool uses_spr = (attr & RS6000_BTC_SPR);
13794 icode = rs6000_htm_spr_icode (nonvoid);
13795 insn_op = &insn_data[icode].operand[0];
13799 machine_mode tmode = (uses_spr) ? insn_op->mode : E_SImode;
13801 || GET_MODE (target) != tmode
13802 || (uses_spr && !(*insn_op->predicate) (target, tmode)))
13803 target = gen_reg_rtx (tmode);
13805 op[nopnds++] = target;
13808 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
13810 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
13813 insn_op = &insn_data[icode].operand[nopnds];
13815 op[nopnds] = expand_normal (arg);
13817 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
13819 if (!strcmp (insn_op->constraint, "n"))
13821 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
13822 if (!CONST_INT_P (op[nopnds]))
13823 error ("argument %d must be an unsigned literal", arg_num);
13825 error ("argument %d is an unsigned literal that is "
13826 "out of range", arg_num);
13829 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
13835 /* Handle the builtins for extended mnemonics. These accept
13836 no arguments, but map to builtins that take arguments. */
13839 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
13840 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
13841 op[nopnds++] = GEN_INT (1);
13843 attr |= RS6000_BTC_UNARY;
13845 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
13846 op[nopnds++] = GEN_INT (0);
13848 attr |= RS6000_BTC_UNARY;
13854 /* If this builtin accesses SPRs, then pass in the appropriate
13855 SPR number and SPR regno as the last two operands. */
13858 machine_mode mode = (TARGET_POWERPC64) ? DImode : SImode;
13859 op[nopnds++] = gen_rtx_CONST_INT (mode, htm_spr_num (fcode));
13861 /* If this builtin accesses a CR, then pass in a scratch
13862 CR as the last operand. */
13863 else if (attr & RS6000_BTC_CR)
13864 { cr = gen_reg_rtx (CCmode);
13870 int expected_nopnds = 0;
13871 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
13872 expected_nopnds = 1;
13873 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
13874 expected_nopnds = 2;
13875 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
13876 expected_nopnds = 3;
13877 if (!(attr & RS6000_BTC_VOID))
13878 expected_nopnds += 1;
13880 expected_nopnds += 1;
13882 gcc_assert (nopnds == expected_nopnds
13883 && nopnds <= MAX_HTM_OPERANDS);
13889 pat = GEN_FCN (icode) (op[0]);
13892 pat = GEN_FCN (icode) (op[0], op[1]);
13895 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
13898 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
13901 gcc_unreachable ();
13907 if (attr & RS6000_BTC_CR)
13909 if (fcode == HTM_BUILTIN_TBEGIN)
13911 /* Emit code to set TARGET to true or false depending on
13912 whether the tbegin. instruction successfully or failed
13913 to start a transaction. We do this by placing the 1's
13914 complement of CR's EQ bit into TARGET. */
13915 rtx scratch = gen_reg_rtx (SImode);
13916 emit_insn (gen_rtx_SET (scratch,
13917 gen_rtx_EQ (SImode, cr,
13919 emit_insn (gen_rtx_SET (target,
13920 gen_rtx_XOR (SImode, scratch,
13925 /* Emit code to copy the 4-bit condition register field
13926 CR into the least significant end of register TARGET. */
13927 rtx scratch1 = gen_reg_rtx (SImode);
13928 rtx scratch2 = gen_reg_rtx (SImode);
13929 rtx subreg = simplify_gen_subreg (CCmode, scratch1, SImode, 0);
13930 emit_insn (gen_movcc (subreg, cr));
13931 emit_insn (gen_lshrsi3 (scratch2, scratch1, GEN_INT (28)));
13932 emit_insn (gen_andsi3 (target, scratch2, GEN_INT (0xf)));
13941 *expandedp = false;
13945 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
13948 cpu_expand_builtin (enum rs6000_builtins fcode, tree exp ATTRIBUTE_UNUSED,
13951 /* __builtin_cpu_init () is a nop, so expand to nothing. */
13952 if (fcode == RS6000_BUILTIN_CPU_INIT)
13955 if (target == 0 || GET_MODE (target) != SImode)
13956 target = gen_reg_rtx (SImode);
13958 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
13959 tree arg = TREE_OPERAND (CALL_EXPR_ARG (exp, 0), 0);
13960 /* Target clones creates an ARRAY_REF instead of STRING_CST, convert it back
13961 to a STRING_CST. */
13962 if (TREE_CODE (arg) == ARRAY_REF
13963 && TREE_CODE (TREE_OPERAND (arg, 0)) == STRING_CST
13964 && TREE_CODE (TREE_OPERAND (arg, 1)) == INTEGER_CST
13965 && compare_tree_int (TREE_OPERAND (arg, 1), 0) == 0)
13966 arg = TREE_OPERAND (arg, 0);
13968 if (TREE_CODE (arg) != STRING_CST)
13970 error ("builtin %qs only accepts a string argument",
13971 rs6000_builtin_info[(size_t) fcode].name);
13975 if (fcode == RS6000_BUILTIN_CPU_IS)
13977 const char *cpu = TREE_STRING_POINTER (arg);
13978 rtx cpuid = NULL_RTX;
13979 for (size_t i = 0; i < ARRAY_SIZE (cpu_is_info); i++)
13980 if (strcmp (cpu, cpu_is_info[i].cpu) == 0)
13982 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
13983 cpuid = GEN_INT (cpu_is_info[i].cpuid + _DL_FIRST_PLATFORM);
13986 if (cpuid == NULL_RTX)
13988 /* Invalid CPU argument. */
13989 error ("cpu %qs is an invalid argument to builtin %qs",
13990 cpu, rs6000_builtin_info[(size_t) fcode].name);
13994 rtx platform = gen_reg_rtx (SImode);
13995 rtx tcbmem = gen_const_mem (SImode,
13996 gen_rtx_PLUS (Pmode,
13997 gen_rtx_REG (Pmode, TLS_REGNUM),
13998 GEN_INT (TCB_PLATFORM_OFFSET)));
13999 emit_move_insn (platform, tcbmem);
14000 emit_insn (gen_eqsi3 (target, platform, cpuid));
14002 else if (fcode == RS6000_BUILTIN_CPU_SUPPORTS)
14004 const char *hwcap = TREE_STRING_POINTER (arg);
14005 rtx mask = NULL_RTX;
14007 for (size_t i = 0; i < ARRAY_SIZE (cpu_supports_info); i++)
14008 if (strcmp (hwcap, cpu_supports_info[i].hwcap) == 0)
14010 mask = GEN_INT (cpu_supports_info[i].mask);
14011 hwcap_offset = TCB_HWCAP_OFFSET (cpu_supports_info[i].id);
14014 if (mask == NULL_RTX)
14016 /* Invalid HWCAP argument. */
14017 error ("%s %qs is an invalid argument to builtin %qs",
14018 "hwcap", hwcap, rs6000_builtin_info[(size_t) fcode].name);
14022 rtx tcb_hwcap = gen_reg_rtx (SImode);
14023 rtx tcbmem = gen_const_mem (SImode,
14024 gen_rtx_PLUS (Pmode,
14025 gen_rtx_REG (Pmode, TLS_REGNUM),
14026 GEN_INT (hwcap_offset)));
14027 emit_move_insn (tcb_hwcap, tcbmem);
14028 rtx scratch1 = gen_reg_rtx (SImode);
14029 emit_insn (gen_rtx_SET (scratch1, gen_rtx_AND (SImode, tcb_hwcap, mask)));
14030 rtx scratch2 = gen_reg_rtx (SImode);
14031 emit_insn (gen_eqsi3 (scratch2, scratch1, const0_rtx));
14032 emit_insn (gen_rtx_SET (target, gen_rtx_XOR (SImode, scratch2, const1_rtx)));
14035 gcc_unreachable ();
14037 /* Record that we have expanded a CPU builtin, so that we can later
14038 emit a reference to the special symbol exported by LIBC to ensure we
14039 do not link against an old LIBC that doesn't support this feature. */
14040 cpu_builtin_p = true;
14043 warning (0, "builtin %qs needs GLIBC (2.23 and newer) that exports hardware "
14044 "capability bits", rs6000_builtin_info[(size_t) fcode].name);
14046 /* For old LIBCs, always return FALSE. */
14047 emit_move_insn (target, GEN_INT (0));
14048 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
14054 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
14057 tree arg0 = CALL_EXPR_ARG (exp, 0);
14058 tree arg1 = CALL_EXPR_ARG (exp, 1);
14059 tree arg2 = CALL_EXPR_ARG (exp, 2);
14060 rtx op0 = expand_normal (arg0);
14061 rtx op1 = expand_normal (arg1);
14062 rtx op2 = expand_normal (arg2);
14063 machine_mode tmode = insn_data[icode].operand[0].mode;
14064 machine_mode mode0 = insn_data[icode].operand[1].mode;
14065 machine_mode mode1 = insn_data[icode].operand[2].mode;
14066 machine_mode mode2 = insn_data[icode].operand[3].mode;
14068 if (icode == CODE_FOR_nothing)
14069 /* Builtin not supported on this processor. */
14072 /* If we got invalid arguments bail out before generating bad rtl. */
14073 if (arg0 == error_mark_node
14074 || arg1 == error_mark_node
14075 || arg2 == error_mark_node)
14078 /* Check and prepare argument depending on the instruction code.
14080 Note that a switch statement instead of the sequence of tests
14081 would be incorrect as many of the CODE_FOR values could be
14082 CODE_FOR_nothing and that would yield multiple alternatives
14083 with identical values. We'd never reach here at runtime in
14085 if (icode == CODE_FOR_altivec_vsldoi_v4sf
14086 || icode == CODE_FOR_altivec_vsldoi_v2df
14087 || icode == CODE_FOR_altivec_vsldoi_v4si
14088 || icode == CODE_FOR_altivec_vsldoi_v8hi
14089 || icode == CODE_FOR_altivec_vsldoi_v16qi)
14091 /* Only allow 4-bit unsigned literals. */
14093 if (TREE_CODE (arg2) != INTEGER_CST
14094 || TREE_INT_CST_LOW (arg2) & ~0xf)
14096 error ("argument 3 must be a 4-bit unsigned literal");
14097 return CONST0_RTX (tmode);
14100 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
14101 || icode == CODE_FOR_vsx_xxpermdi_v2di
14102 || icode == CODE_FOR_vsx_xxpermdi_v2df_be
14103 || icode == CODE_FOR_vsx_xxpermdi_v2di_be
14104 || icode == CODE_FOR_vsx_xxpermdi_v1ti
14105 || icode == CODE_FOR_vsx_xxpermdi_v4sf
14106 || icode == CODE_FOR_vsx_xxpermdi_v4si
14107 || icode == CODE_FOR_vsx_xxpermdi_v8hi
14108 || icode == CODE_FOR_vsx_xxpermdi_v16qi
14109 || icode == CODE_FOR_vsx_xxsldwi_v16qi
14110 || icode == CODE_FOR_vsx_xxsldwi_v8hi
14111 || icode == CODE_FOR_vsx_xxsldwi_v4si
14112 || icode == CODE_FOR_vsx_xxsldwi_v4sf
14113 || icode == CODE_FOR_vsx_xxsldwi_v2di
14114 || icode == CODE_FOR_vsx_xxsldwi_v2df)
14116 /* Only allow 2-bit unsigned literals. */
14118 if (TREE_CODE (arg2) != INTEGER_CST
14119 || TREE_INT_CST_LOW (arg2) & ~0x3)
14121 error ("argument 3 must be a 2-bit unsigned literal");
14122 return CONST0_RTX (tmode);
14125 else if (icode == CODE_FOR_vsx_set_v2df
14126 || icode == CODE_FOR_vsx_set_v2di
14127 || icode == CODE_FOR_bcdadd
14128 || icode == CODE_FOR_bcdadd_lt
14129 || icode == CODE_FOR_bcdadd_eq
14130 || icode == CODE_FOR_bcdadd_gt
14131 || icode == CODE_FOR_bcdsub
14132 || icode == CODE_FOR_bcdsub_lt
14133 || icode == CODE_FOR_bcdsub_eq
14134 || icode == CODE_FOR_bcdsub_gt)
14136 /* Only allow 1-bit unsigned literals. */
14138 if (TREE_CODE (arg2) != INTEGER_CST
14139 || TREE_INT_CST_LOW (arg2) & ~0x1)
14141 error ("argument 3 must be a 1-bit unsigned literal");
14142 return CONST0_RTX (tmode);
14145 else if (icode == CODE_FOR_dfp_ddedpd_dd
14146 || icode == CODE_FOR_dfp_ddedpd_td)
14148 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
14150 if (TREE_CODE (arg0) != INTEGER_CST
14151 || TREE_INT_CST_LOW (arg2) & ~0x3)
14153 error ("argument 1 must be 0 or 2");
14154 return CONST0_RTX (tmode);
14157 else if (icode == CODE_FOR_dfp_denbcd_dd
14158 || icode == CODE_FOR_dfp_denbcd_td)
14160 /* Only allow 1-bit unsigned literals. */
14162 if (TREE_CODE (arg0) != INTEGER_CST
14163 || TREE_INT_CST_LOW (arg0) & ~0x1)
14165 error ("argument 1 must be a 1-bit unsigned literal");
14166 return CONST0_RTX (tmode);
14169 else if (icode == CODE_FOR_dfp_dscli_dd
14170 || icode == CODE_FOR_dfp_dscli_td
14171 || icode == CODE_FOR_dfp_dscri_dd
14172 || icode == CODE_FOR_dfp_dscri_td)
14174 /* Only allow 6-bit unsigned literals. */
14176 if (TREE_CODE (arg1) != INTEGER_CST
14177 || TREE_INT_CST_LOW (arg1) & ~0x3f)
14179 error ("argument 2 must be a 6-bit unsigned literal");
14180 return CONST0_RTX (tmode);
14183 else if (icode == CODE_FOR_crypto_vshasigmaw
14184 || icode == CODE_FOR_crypto_vshasigmad)
14186 /* Check whether the 2nd and 3rd arguments are integer constants and in
14187 range and prepare arguments. */
14189 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (wi::to_wide (arg1), 2))
14191 error ("argument 2 must be 0 or 1");
14192 return CONST0_RTX (tmode);
14196 if (TREE_CODE (arg2) != INTEGER_CST
14197 || wi::geu_p (wi::to_wide (arg2), 16))
14199 error ("argument 3 must be in the range [0, 15]");
14200 return CONST0_RTX (tmode);
14205 || GET_MODE (target) != tmode
14206 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14207 target = gen_reg_rtx (tmode);
14209 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
14210 op0 = copy_to_mode_reg (mode0, op0);
14211 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
14212 op1 = copy_to_mode_reg (mode1, op1);
14213 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
14214 op2 = copy_to_mode_reg (mode2, op2);
14216 pat = GEN_FCN (icode) (target, op0, op1, op2);
14225 /* Expand the dst builtins. */
14227 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
14230 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14231 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14232 tree arg0, arg1, arg2;
14233 machine_mode mode0, mode1;
14234 rtx pat, op0, op1, op2;
14235 const struct builtin_description *d;
14238 *expandedp = false;
14240 /* Handle DST variants. */
14242 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
14243 if (d->code == fcode)
14245 arg0 = CALL_EXPR_ARG (exp, 0);
14246 arg1 = CALL_EXPR_ARG (exp, 1);
14247 arg2 = CALL_EXPR_ARG (exp, 2);
14248 op0 = expand_normal (arg0);
14249 op1 = expand_normal (arg1);
14250 op2 = expand_normal (arg2);
14251 mode0 = insn_data[d->icode].operand[0].mode;
14252 mode1 = insn_data[d->icode].operand[1].mode;
14254 /* Invalid arguments, bail out before generating bad rtl. */
14255 if (arg0 == error_mark_node
14256 || arg1 == error_mark_node
14257 || arg2 == error_mark_node)
14262 if (TREE_CODE (arg2) != INTEGER_CST
14263 || TREE_INT_CST_LOW (arg2) & ~0x3)
14265 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
14269 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
14270 op0 = copy_to_mode_reg (Pmode, op0);
14271 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
14272 op1 = copy_to_mode_reg (mode1, op1);
14274 pat = GEN_FCN (d->icode) (op0, op1, op2);
14284 /* Expand vec_init builtin. */
14286 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
14288 machine_mode tmode = TYPE_MODE (type);
14289 machine_mode inner_mode = GET_MODE_INNER (tmode);
14290 int i, n_elt = GET_MODE_NUNITS (tmode);
14292 gcc_assert (VECTOR_MODE_P (tmode));
14293 gcc_assert (n_elt == call_expr_nargs (exp));
14295 if (!target || !register_operand (target, tmode))
14296 target = gen_reg_rtx (tmode);
14298 /* If we have a vector compromised of a single element, such as V1TImode, do
14299 the initialization directly. */
14300 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
14302 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
14303 emit_move_insn (target, gen_lowpart (tmode, x));
14307 rtvec v = rtvec_alloc (n_elt);
14309 for (i = 0; i < n_elt; ++i)
14311 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
14312 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
14315 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
14321 /* Return the integer constant in ARG. Constrain it to be in the range
14322 of the subparts of VEC_TYPE; issue an error if not. */
14325 get_element_number (tree vec_type, tree arg)
14327 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
14329 if (!tree_fits_uhwi_p (arg)
14330 || (elt = tree_to_uhwi (arg), elt > max))
14332 error ("selector must be an integer constant in the range [0, %wi]", max);
14339 /* Expand vec_set builtin. */
14341 altivec_expand_vec_set_builtin (tree exp)
14343 machine_mode tmode, mode1;
14344 tree arg0, arg1, arg2;
14348 arg0 = CALL_EXPR_ARG (exp, 0);
14349 arg1 = CALL_EXPR_ARG (exp, 1);
14350 arg2 = CALL_EXPR_ARG (exp, 2);
14352 tmode = TYPE_MODE (TREE_TYPE (arg0));
14353 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14354 gcc_assert (VECTOR_MODE_P (tmode));
14356 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
14357 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
14358 elt = get_element_number (TREE_TYPE (arg0), arg2);
14360 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
14361 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
14363 op0 = force_reg (tmode, op0);
14364 op1 = force_reg (mode1, op1);
14366 rs6000_expand_vector_set (op0, op1, elt);
14371 /* Expand vec_ext builtin. */
14373 altivec_expand_vec_ext_builtin (tree exp, rtx target)
14375 machine_mode tmode, mode0;
14380 arg0 = CALL_EXPR_ARG (exp, 0);
14381 arg1 = CALL_EXPR_ARG (exp, 1);
14383 op0 = expand_normal (arg0);
14384 op1 = expand_normal (arg1);
14386 if (TREE_CODE (arg1) == INTEGER_CST)
14388 unsigned HOST_WIDE_INT elt;
14389 unsigned HOST_WIDE_INT size = TYPE_VECTOR_SUBPARTS (TREE_TYPE (arg0));
14390 unsigned int truncated_selector;
14391 /* Even if !tree_fits_uhwi_p (arg1)), TREE_INT_CST_LOW (arg0)
14392 returns low-order bits of INTEGER_CST for modulo indexing. */
14393 elt = TREE_INT_CST_LOW (arg1);
14394 truncated_selector = elt % size;
14395 op1 = GEN_INT (truncated_selector);
14398 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
14399 mode0 = TYPE_MODE (TREE_TYPE (arg0));
14400 gcc_assert (VECTOR_MODE_P (mode0));
14402 op0 = force_reg (mode0, op0);
14404 if (optimize || !target || !register_operand (target, tmode))
14405 target = gen_reg_rtx (tmode);
14407 rs6000_expand_vector_extract (target, op0, op1);
14412 /* Expand the builtin in EXP and store the result in TARGET. Store
14413 true in *EXPANDEDP if we found a builtin to expand. */
14415 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
14417 const struct builtin_description *d;
14419 enum insn_code icode;
14420 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14421 tree arg0, arg1, arg2;
14423 machine_mode tmode, mode0;
14424 enum rs6000_builtins fcode
14425 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
14427 if (rs6000_overloaded_builtin_p (fcode))
14430 error ("unresolved overload for Altivec builtin %qF", fndecl);
14432 /* Given it is invalid, just generate a normal call. */
14433 return expand_call (exp, target, false);
14436 target = altivec_expand_dst_builtin (exp, target, expandedp);
14444 case ALTIVEC_BUILTIN_STVX_V2DF:
14445 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
14446 case ALTIVEC_BUILTIN_STVX_V2DI:
14447 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
14448 case ALTIVEC_BUILTIN_STVX_V4SF:
14449 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
14450 case ALTIVEC_BUILTIN_STVX:
14451 case ALTIVEC_BUILTIN_STVX_V4SI:
14452 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
14453 case ALTIVEC_BUILTIN_STVX_V8HI:
14454 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
14455 case ALTIVEC_BUILTIN_STVX_V16QI:
14456 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
14457 case ALTIVEC_BUILTIN_STVEBX:
14458 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
14459 case ALTIVEC_BUILTIN_STVEHX:
14460 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
14461 case ALTIVEC_BUILTIN_STVEWX:
14462 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
14463 case ALTIVEC_BUILTIN_STVXL_V2DF:
14464 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
14465 case ALTIVEC_BUILTIN_STVXL_V2DI:
14466 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
14467 case ALTIVEC_BUILTIN_STVXL_V4SF:
14468 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
14469 case ALTIVEC_BUILTIN_STVXL:
14470 case ALTIVEC_BUILTIN_STVXL_V4SI:
14471 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
14472 case ALTIVEC_BUILTIN_STVXL_V8HI:
14473 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
14474 case ALTIVEC_BUILTIN_STVXL_V16QI:
14475 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
14477 case ALTIVEC_BUILTIN_STVLX:
14478 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
14479 case ALTIVEC_BUILTIN_STVLXL:
14480 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
14481 case ALTIVEC_BUILTIN_STVRX:
14482 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
14483 case ALTIVEC_BUILTIN_STVRXL:
14484 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
14486 case P9V_BUILTIN_STXVL:
14487 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl, exp);
14489 case P9V_BUILTIN_XST_LEN_R:
14490 return altivec_expand_stxvl_builtin (CODE_FOR_xst_len_r, exp);
14492 case VSX_BUILTIN_STXVD2X_V1TI:
14493 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
14494 case VSX_BUILTIN_STXVD2X_V2DF:
14495 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
14496 case VSX_BUILTIN_STXVD2X_V2DI:
14497 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
14498 case VSX_BUILTIN_STXVW4X_V4SF:
14499 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
14500 case VSX_BUILTIN_STXVW4X_V4SI:
14501 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
14502 case VSX_BUILTIN_STXVW4X_V8HI:
14503 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
14504 case VSX_BUILTIN_STXVW4X_V16QI:
14505 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
14507 /* For the following on big endian, it's ok to use any appropriate
14508 unaligned-supporting store, so use a generic expander. For
14509 little-endian, the exact element-reversing instruction must
14511 case VSX_BUILTIN_ST_ELEMREV_V1TI:
14513 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v1ti
14514 : CODE_FOR_vsx_st_elemrev_v1ti);
14515 return altivec_expand_stv_builtin (code, exp);
14517 case VSX_BUILTIN_ST_ELEMREV_V2DF:
14519 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2df
14520 : CODE_FOR_vsx_st_elemrev_v2df);
14521 return altivec_expand_stv_builtin (code, exp);
14523 case VSX_BUILTIN_ST_ELEMREV_V2DI:
14525 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v2di
14526 : CODE_FOR_vsx_st_elemrev_v2di);
14527 return altivec_expand_stv_builtin (code, exp);
14529 case VSX_BUILTIN_ST_ELEMREV_V4SF:
14531 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4sf
14532 : CODE_FOR_vsx_st_elemrev_v4sf);
14533 return altivec_expand_stv_builtin (code, exp);
14535 case VSX_BUILTIN_ST_ELEMREV_V4SI:
14537 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v4si
14538 : CODE_FOR_vsx_st_elemrev_v4si);
14539 return altivec_expand_stv_builtin (code, exp);
14541 case VSX_BUILTIN_ST_ELEMREV_V8HI:
14543 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v8hi
14544 : CODE_FOR_vsx_st_elemrev_v8hi);
14545 return altivec_expand_stv_builtin (code, exp);
14547 case VSX_BUILTIN_ST_ELEMREV_V16QI:
14549 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_store_v16qi
14550 : CODE_FOR_vsx_st_elemrev_v16qi);
14551 return altivec_expand_stv_builtin (code, exp);
14554 case ALTIVEC_BUILTIN_MFVSCR:
14555 icode = CODE_FOR_altivec_mfvscr;
14556 tmode = insn_data[icode].operand[0].mode;
14559 || GET_MODE (target) != tmode
14560 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14561 target = gen_reg_rtx (tmode);
14563 pat = GEN_FCN (icode) (target);
14569 case ALTIVEC_BUILTIN_MTVSCR:
14570 icode = CODE_FOR_altivec_mtvscr;
14571 arg0 = CALL_EXPR_ARG (exp, 0);
14572 op0 = expand_normal (arg0);
14573 mode0 = insn_data[icode].operand[0].mode;
14575 /* If we got invalid arguments bail out before generating bad rtl. */
14576 if (arg0 == error_mark_node)
14579 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
14580 op0 = copy_to_mode_reg (mode0, op0);
14582 pat = GEN_FCN (icode) (op0);
14587 case ALTIVEC_BUILTIN_DSSALL:
14588 emit_insn (gen_altivec_dssall ());
14591 case ALTIVEC_BUILTIN_DSS:
14592 icode = CODE_FOR_altivec_dss;
14593 arg0 = CALL_EXPR_ARG (exp, 0);
14595 op0 = expand_normal (arg0);
14596 mode0 = insn_data[icode].operand[0].mode;
14598 /* If we got invalid arguments bail out before generating bad rtl. */
14599 if (arg0 == error_mark_node)
14602 if (TREE_CODE (arg0) != INTEGER_CST
14603 || TREE_INT_CST_LOW (arg0) & ~0x3)
14605 error ("argument to %qs must be a 2-bit unsigned literal", "dss");
14609 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
14610 op0 = copy_to_mode_reg (mode0, op0);
14612 emit_insn (gen_altivec_dss (op0));
14615 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
14616 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
14617 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
14618 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
14619 case VSX_BUILTIN_VEC_INIT_V2DF:
14620 case VSX_BUILTIN_VEC_INIT_V2DI:
14621 case VSX_BUILTIN_VEC_INIT_V1TI:
14622 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
14624 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
14625 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
14626 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
14627 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
14628 case VSX_BUILTIN_VEC_SET_V2DF:
14629 case VSX_BUILTIN_VEC_SET_V2DI:
14630 case VSX_BUILTIN_VEC_SET_V1TI:
14631 return altivec_expand_vec_set_builtin (exp);
14633 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
14634 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
14635 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
14636 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
14637 case VSX_BUILTIN_VEC_EXT_V2DF:
14638 case VSX_BUILTIN_VEC_EXT_V2DI:
14639 case VSX_BUILTIN_VEC_EXT_V1TI:
14640 return altivec_expand_vec_ext_builtin (exp, target);
14642 case P9V_BUILTIN_VEC_EXTRACT4B:
14643 arg1 = CALL_EXPR_ARG (exp, 1);
14646 /* Generate a normal call if it is invalid. */
14647 if (arg1 == error_mark_node)
14648 return expand_call (exp, target, false);
14650 if (TREE_CODE (arg1) != INTEGER_CST || TREE_INT_CST_LOW (arg1) > 12)
14652 error ("second argument to %qs must be [0, 12]", "vec_vextract4b");
14653 return expand_call (exp, target, false);
14657 case P9V_BUILTIN_VEC_INSERT4B:
14658 arg2 = CALL_EXPR_ARG (exp, 2);
14661 /* Generate a normal call if it is invalid. */
14662 if (arg2 == error_mark_node)
14663 return expand_call (exp, target, false);
14665 if (TREE_CODE (arg2) != INTEGER_CST || TREE_INT_CST_LOW (arg2) > 12)
14667 error ("third argument to %qs must be [0, 12]", "vec_vinsert4b");
14668 return expand_call (exp, target, false);
14674 /* Fall through. */
14677 /* Expand abs* operations. */
14679 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
14680 if (d->code == fcode)
14681 return altivec_expand_abs_builtin (d->icode, exp, target);
14683 /* Expand the AltiVec predicates. */
14684 d = bdesc_altivec_preds;
14685 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
14686 if (d->code == fcode)
14687 return altivec_expand_predicate_builtin (d->icode, exp, target);
14689 /* LV* are funky. We initialized them differently. */
14692 case ALTIVEC_BUILTIN_LVSL:
14693 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
14694 exp, target, false);
14695 case ALTIVEC_BUILTIN_LVSR:
14696 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
14697 exp, target, false);
14698 case ALTIVEC_BUILTIN_LVEBX:
14699 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
14700 exp, target, false);
14701 case ALTIVEC_BUILTIN_LVEHX:
14702 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
14703 exp, target, false);
14704 case ALTIVEC_BUILTIN_LVEWX:
14705 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
14706 exp, target, false);
14707 case ALTIVEC_BUILTIN_LVXL_V2DF:
14708 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
14709 exp, target, false);
14710 case ALTIVEC_BUILTIN_LVXL_V2DI:
14711 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
14712 exp, target, false);
14713 case ALTIVEC_BUILTIN_LVXL_V4SF:
14714 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
14715 exp, target, false);
14716 case ALTIVEC_BUILTIN_LVXL:
14717 case ALTIVEC_BUILTIN_LVXL_V4SI:
14718 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
14719 exp, target, false);
14720 case ALTIVEC_BUILTIN_LVXL_V8HI:
14721 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
14722 exp, target, false);
14723 case ALTIVEC_BUILTIN_LVXL_V16QI:
14724 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
14725 exp, target, false);
14726 case ALTIVEC_BUILTIN_LVX_V1TI:
14727 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v1ti,
14728 exp, target, false);
14729 case ALTIVEC_BUILTIN_LVX_V2DF:
14730 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
14731 exp, target, false);
14732 case ALTIVEC_BUILTIN_LVX_V2DI:
14733 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
14734 exp, target, false);
14735 case ALTIVEC_BUILTIN_LVX_V4SF:
14736 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
14737 exp, target, false);
14738 case ALTIVEC_BUILTIN_LVX:
14739 case ALTIVEC_BUILTIN_LVX_V4SI:
14740 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
14741 exp, target, false);
14742 case ALTIVEC_BUILTIN_LVX_V8HI:
14743 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
14744 exp, target, false);
14745 case ALTIVEC_BUILTIN_LVX_V16QI:
14746 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
14747 exp, target, false);
14748 case ALTIVEC_BUILTIN_LVLX:
14749 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
14750 exp, target, true);
14751 case ALTIVEC_BUILTIN_LVLXL:
14752 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
14753 exp, target, true);
14754 case ALTIVEC_BUILTIN_LVRX:
14755 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
14756 exp, target, true);
14757 case ALTIVEC_BUILTIN_LVRXL:
14758 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
14759 exp, target, true);
14760 case VSX_BUILTIN_LXVD2X_V1TI:
14761 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
14762 exp, target, false);
14763 case VSX_BUILTIN_LXVD2X_V2DF:
14764 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
14765 exp, target, false);
14766 case VSX_BUILTIN_LXVD2X_V2DI:
14767 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
14768 exp, target, false);
14769 case VSX_BUILTIN_LXVW4X_V4SF:
14770 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
14771 exp, target, false);
14772 case VSX_BUILTIN_LXVW4X_V4SI:
14773 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
14774 exp, target, false);
14775 case VSX_BUILTIN_LXVW4X_V8HI:
14776 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
14777 exp, target, false);
14778 case VSX_BUILTIN_LXVW4X_V16QI:
14779 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
14780 exp, target, false);
14781 /* For the following on big endian, it's ok to use any appropriate
14782 unaligned-supporting load, so use a generic expander. For
14783 little-endian, the exact element-reversing instruction must
14785 case VSX_BUILTIN_LD_ELEMREV_V2DF:
14787 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2df
14788 : CODE_FOR_vsx_ld_elemrev_v2df);
14789 return altivec_expand_lv_builtin (code, exp, target, false);
14791 case VSX_BUILTIN_LD_ELEMREV_V1TI:
14793 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v1ti
14794 : CODE_FOR_vsx_ld_elemrev_v1ti);
14795 return altivec_expand_lv_builtin (code, exp, target, false);
14797 case VSX_BUILTIN_LD_ELEMREV_V2DI:
14799 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v2di
14800 : CODE_FOR_vsx_ld_elemrev_v2di);
14801 return altivec_expand_lv_builtin (code, exp, target, false);
14803 case VSX_BUILTIN_LD_ELEMREV_V4SF:
14805 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4sf
14806 : CODE_FOR_vsx_ld_elemrev_v4sf);
14807 return altivec_expand_lv_builtin (code, exp, target, false);
14809 case VSX_BUILTIN_LD_ELEMREV_V4SI:
14811 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v4si
14812 : CODE_FOR_vsx_ld_elemrev_v4si);
14813 return altivec_expand_lv_builtin (code, exp, target, false);
14815 case VSX_BUILTIN_LD_ELEMREV_V8HI:
14817 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v8hi
14818 : CODE_FOR_vsx_ld_elemrev_v8hi);
14819 return altivec_expand_lv_builtin (code, exp, target, false);
14821 case VSX_BUILTIN_LD_ELEMREV_V16QI:
14823 enum insn_code code = (BYTES_BIG_ENDIAN ? CODE_FOR_vsx_load_v16qi
14824 : CODE_FOR_vsx_ld_elemrev_v16qi);
14825 return altivec_expand_lv_builtin (code, exp, target, false);
14830 /* Fall through. */
14833 *expandedp = false;
14837 /* Check whether a builtin function is supported in this target
14840 rs6000_builtin_is_supported_p (enum rs6000_builtins fncode)
14842 HOST_WIDE_INT fnmask = rs6000_builtin_info[fncode].mask;
14843 if ((fnmask & rs6000_builtin_mask) != fnmask)
14849 /* Raise an error message for a builtin function that is called without the
14850 appropriate target options being set. */
14853 rs6000_invalid_builtin (enum rs6000_builtins fncode)
14855 size_t uns_fncode = (size_t) fncode;
14856 const char *name = rs6000_builtin_info[uns_fncode].name;
14857 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
14859 gcc_assert (name != NULL);
14860 if ((fnmask & RS6000_BTM_CELL) != 0)
14861 error ("builtin function %qs is only valid for the cell processor", name);
14862 else if ((fnmask & RS6000_BTM_VSX) != 0)
14863 error ("builtin function %qs requires the %qs option", name, "-mvsx");
14864 else if ((fnmask & RS6000_BTM_HTM) != 0)
14865 error ("builtin function %qs requires the %qs option", name, "-mhtm");
14866 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
14867 error ("builtin function %qs requires the %qs option", name, "-maltivec");
14868 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
14869 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
14870 error ("builtin function %qs requires the %qs and %qs options",
14871 name, "-mhard-dfp", "-mpower8-vector");
14872 else if ((fnmask & RS6000_BTM_DFP) != 0)
14873 error ("builtin function %qs requires the %qs option", name, "-mhard-dfp");
14874 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
14875 error ("builtin function %qs requires the %qs option", name,
14876 "-mpower8-vector");
14877 else if ((fnmask & (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
14878 == (RS6000_BTM_P9_VECTOR | RS6000_BTM_64BIT))
14879 error ("builtin function %qs requires the %qs and %qs options",
14880 name, "-mcpu=power9", "-m64");
14881 else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
14882 error ("builtin function %qs requires the %qs option", name,
14884 else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
14885 == (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
14886 error ("builtin function %qs requires the %qs and %qs options",
14887 name, "-mcpu=power9", "-m64");
14888 else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
14889 error ("builtin function %qs requires the %qs option", name,
14891 else if ((fnmask & RS6000_BTM_LDBL128) == RS6000_BTM_LDBL128)
14893 if (!TARGET_HARD_FLOAT)
14894 error ("builtin function %qs requires the %qs option", name,
14897 error ("builtin function %qs requires the %qs option", name,
14898 TARGET_IEEEQUAD ? "-mabi=ibmlongdouble" : "-mlong-double-128");
14900 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
14901 error ("builtin function %qs requires the %qs option", name,
14903 else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
14904 error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
14906 else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
14907 error ("builtin function %qs requires the %qs option", name,
14909 else if ((fnmask & (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
14910 == (RS6000_BTM_POPCNTD | RS6000_BTM_POWERPC64))
14911 error ("builtin function %qs requires the %qs (or newer), and "
14912 "%qs or %qs options",
14913 name, "-mcpu=power7", "-m64", "-mpowerpc64");
14915 error ("builtin function %qs is not supported with the current options",
14919 /* Target hook for early folding of built-ins, shamelessly stolen
14923 rs6000_fold_builtin (tree fndecl ATTRIBUTE_UNUSED,
14924 int n_args ATTRIBUTE_UNUSED,
14925 tree *args ATTRIBUTE_UNUSED,
14926 bool ignore ATTRIBUTE_UNUSED)
14928 #ifdef SUBTARGET_FOLD_BUILTIN
14929 return SUBTARGET_FOLD_BUILTIN (fndecl, n_args, args, ignore);
14935 /* Helper function to sort out which built-ins may be valid without having
14938 rs6000_builtin_valid_without_lhs (enum rs6000_builtins fn_code)
14942 case ALTIVEC_BUILTIN_STVX_V16QI:
14943 case ALTIVEC_BUILTIN_STVX_V8HI:
14944 case ALTIVEC_BUILTIN_STVX_V4SI:
14945 case ALTIVEC_BUILTIN_STVX_V4SF:
14946 case ALTIVEC_BUILTIN_STVX_V2DI:
14947 case ALTIVEC_BUILTIN_STVX_V2DF:
14948 case VSX_BUILTIN_STXVW4X_V16QI:
14949 case VSX_BUILTIN_STXVW4X_V8HI:
14950 case VSX_BUILTIN_STXVW4X_V4SF:
14951 case VSX_BUILTIN_STXVW4X_V4SI:
14952 case VSX_BUILTIN_STXVD2X_V2DF:
14953 case VSX_BUILTIN_STXVD2X_V2DI:
14960 /* Helper function to handle the gimple folding of a vector compare
14961 operation. This sets up true/false vectors, and uses the
14962 VEC_COND_EXPR operation.
14963 CODE indicates which comparison is to be made. (EQ, GT, ...).
14964 TYPE indicates the type of the result. */
14966 fold_build_vec_cmp (tree_code code, tree type,
14967 tree arg0, tree arg1)
14969 tree cmp_type = build_same_sized_truth_vector_type (type);
14970 tree zero_vec = build_zero_cst (type);
14971 tree minus_one_vec = build_minus_one_cst (type);
14972 tree cmp = fold_build2 (code, cmp_type, arg0, arg1);
14973 return fold_build3 (VEC_COND_EXPR, type, cmp, minus_one_vec, zero_vec);
14976 /* Helper function to handle the in-between steps for the
14977 vector compare built-ins. */
14979 fold_compare_helper (gimple_stmt_iterator *gsi, tree_code code, gimple *stmt)
14981 tree arg0 = gimple_call_arg (stmt, 0);
14982 tree arg1 = gimple_call_arg (stmt, 1);
14983 tree lhs = gimple_call_lhs (stmt);
14984 tree cmp = fold_build_vec_cmp (code, TREE_TYPE (lhs), arg0, arg1);
14985 gimple *g = gimple_build_assign (lhs, cmp);
14986 gimple_set_location (g, gimple_location (stmt));
14987 gsi_replace (gsi, g, true);
14990 /* Helper function to map V2DF and V4SF types to their
14991 integral equivalents (V2DI and V4SI). */
14992 tree map_to_integral_tree_type (tree input_tree_type)
14994 if (INTEGRAL_TYPE_P (TREE_TYPE (input_tree_type)))
14995 return input_tree_type;
14998 if (types_compatible_p (TREE_TYPE (input_tree_type),
14999 TREE_TYPE (V2DF_type_node)))
15000 return V2DI_type_node;
15001 else if (types_compatible_p (TREE_TYPE (input_tree_type),
15002 TREE_TYPE (V4SF_type_node)))
15003 return V4SI_type_node;
15005 gcc_unreachable ();
15009 /* Helper function to handle the vector merge[hl] built-ins. The
15010 implementation difference between h and l versions for this code are in
15011 the values used when building of the permute vector for high word versus
15012 low word merge. The variance is keyed off the use_high parameter. */
15014 fold_mergehl_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_high)
15016 tree arg0 = gimple_call_arg (stmt, 0);
15017 tree arg1 = gimple_call_arg (stmt, 1);
15018 tree lhs = gimple_call_lhs (stmt);
15019 tree lhs_type = TREE_TYPE (lhs);
15020 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15021 int midpoint = n_elts / 2;
15027 /* The permute_type will match the lhs for integral types. For double and
15028 float types, the permute type needs to map to the V2 or V4 type that
15031 permute_type = map_to_integral_tree_type (lhs_type);
15032 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
15034 for (int i = 0; i < midpoint; i++)
15036 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15038 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15039 offset + n_elts + i));
15042 tree permute = elts.build ();
15044 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15045 gimple_set_location (g, gimple_location (stmt));
15046 gsi_replace (gsi, g, true);
15049 /* Helper function to handle the vector merge[eo] built-ins. */
15051 fold_mergeeo_helper (gimple_stmt_iterator *gsi, gimple *stmt, int use_odd)
15053 tree arg0 = gimple_call_arg (stmt, 0);
15054 tree arg1 = gimple_call_arg (stmt, 1);
15055 tree lhs = gimple_call_lhs (stmt);
15056 tree lhs_type = TREE_TYPE (lhs);
15057 int n_elts = TYPE_VECTOR_SUBPARTS (lhs_type);
15059 /* The permute_type will match the lhs for integral types. For double and
15060 float types, the permute type needs to map to the V2 or V4 type that
15063 permute_type = map_to_integral_tree_type (lhs_type);
15065 tree_vector_builder elts (permute_type, VECTOR_CST_NELTS (arg0), 1);
15067 /* Build the permute vector. */
15068 for (int i = 0; i < n_elts / 2; i++)
15070 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15072 elts.safe_push (build_int_cst (TREE_TYPE (permute_type),
15073 2*i + use_odd + n_elts));
15076 tree permute = elts.build ();
15078 gimple *g = gimple_build_assign (lhs, VEC_PERM_EXPR, arg0, arg1, permute);
15079 gimple_set_location (g, gimple_location (stmt));
15080 gsi_replace (gsi, g, true);
15083 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
15084 a constant, use rs6000_fold_builtin.) */
15087 rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
15089 gimple *stmt = gsi_stmt (*gsi);
15090 tree fndecl = gimple_call_fndecl (stmt);
15091 gcc_checking_assert (fndecl && DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD);
15092 enum rs6000_builtins fn_code
15093 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
15094 tree arg0, arg1, lhs, temp;
15095 enum tree_code bcode;
15098 size_t uns_fncode = (size_t) fn_code;
15099 enum insn_code icode = rs6000_builtin_info[uns_fncode].icode;
15100 const char *fn_name1 = rs6000_builtin_info[uns_fncode].name;
15101 const char *fn_name2 = (icode != CODE_FOR_nothing)
15102 ? get_insn_name ((int) icode)
15105 if (TARGET_DEBUG_BUILTIN)
15106 fprintf (stderr, "rs6000_gimple_fold_builtin %d %s %s\n",
15107 fn_code, fn_name1, fn_name2);
15109 if (!rs6000_fold_gimple)
15112 /* Prevent gimple folding for code that does not have a LHS, unless it is
15113 allowed per the rs6000_builtin_valid_without_lhs helper function. */
15114 if (!gimple_call_lhs (stmt) && !rs6000_builtin_valid_without_lhs (fn_code))
15117 /* Don't fold invalid builtins, let rs6000_expand_builtin diagnose it. */
15118 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fncode].mask;
15119 bool func_valid_p = (rs6000_builtin_mask & mask) == mask;
15125 /* Flavors of vec_add. We deliberately don't expand
15126 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
15127 TImode, resulting in much poorer code generation. */
15128 case ALTIVEC_BUILTIN_VADDUBM:
15129 case ALTIVEC_BUILTIN_VADDUHM:
15130 case ALTIVEC_BUILTIN_VADDUWM:
15131 case P8V_BUILTIN_VADDUDM:
15132 case ALTIVEC_BUILTIN_VADDFP:
15133 case VSX_BUILTIN_XVADDDP:
15136 arg0 = gimple_call_arg (stmt, 0);
15137 arg1 = gimple_call_arg (stmt, 1);
15138 lhs = gimple_call_lhs (stmt);
15139 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (lhs)))
15140 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (lhs))))
15142 /* Ensure the binary operation is performed in a type
15143 that wraps if it is integral type. */
15144 gimple_seq stmts = NULL;
15145 tree type = unsigned_type_for (TREE_TYPE (lhs));
15146 tree uarg0 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15148 tree uarg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15150 tree res = gimple_build (&stmts, gimple_location (stmt), bcode,
15151 type, uarg0, uarg1);
15152 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15153 g = gimple_build_assign (lhs, VIEW_CONVERT_EXPR,
15154 build1 (VIEW_CONVERT_EXPR,
15155 TREE_TYPE (lhs), res));
15156 gsi_replace (gsi, g, true);
15159 g = gimple_build_assign (lhs, bcode, arg0, arg1);
15160 gimple_set_location (g, gimple_location (stmt));
15161 gsi_replace (gsi, g, true);
15163 /* Flavors of vec_sub. We deliberately don't expand
15164 P8V_BUILTIN_VSUBUQM. */
15165 case ALTIVEC_BUILTIN_VSUBUBM:
15166 case ALTIVEC_BUILTIN_VSUBUHM:
15167 case ALTIVEC_BUILTIN_VSUBUWM:
15168 case P8V_BUILTIN_VSUBUDM:
15169 case ALTIVEC_BUILTIN_VSUBFP:
15170 case VSX_BUILTIN_XVSUBDP:
15171 bcode = MINUS_EXPR;
15173 case VSX_BUILTIN_XVMULSP:
15174 case VSX_BUILTIN_XVMULDP:
15175 arg0 = gimple_call_arg (stmt, 0);
15176 arg1 = gimple_call_arg (stmt, 1);
15177 lhs = gimple_call_lhs (stmt);
15178 g = gimple_build_assign (lhs, MULT_EXPR, arg0, arg1);
15179 gimple_set_location (g, gimple_location (stmt));
15180 gsi_replace (gsi, g, true);
15182 /* Even element flavors of vec_mul (signed). */
15183 case ALTIVEC_BUILTIN_VMULESB:
15184 case ALTIVEC_BUILTIN_VMULESH:
15185 case P8V_BUILTIN_VMULESW:
15186 /* Even element flavors of vec_mul (unsigned). */
15187 case ALTIVEC_BUILTIN_VMULEUB:
15188 case ALTIVEC_BUILTIN_VMULEUH:
15189 case P8V_BUILTIN_VMULEUW:
15190 arg0 = gimple_call_arg (stmt, 0);
15191 arg1 = gimple_call_arg (stmt, 1);
15192 lhs = gimple_call_lhs (stmt);
15193 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_EVEN_EXPR, arg0, arg1);
15194 gimple_set_location (g, gimple_location (stmt));
15195 gsi_replace (gsi, g, true);
15197 /* Odd element flavors of vec_mul (signed). */
15198 case ALTIVEC_BUILTIN_VMULOSB:
15199 case ALTIVEC_BUILTIN_VMULOSH:
15200 case P8V_BUILTIN_VMULOSW:
15201 /* Odd element flavors of vec_mul (unsigned). */
15202 case ALTIVEC_BUILTIN_VMULOUB:
15203 case ALTIVEC_BUILTIN_VMULOUH:
15204 case P8V_BUILTIN_VMULOUW:
15205 arg0 = gimple_call_arg (stmt, 0);
15206 arg1 = gimple_call_arg (stmt, 1);
15207 lhs = gimple_call_lhs (stmt);
15208 g = gimple_build_assign (lhs, VEC_WIDEN_MULT_ODD_EXPR, arg0, arg1);
15209 gimple_set_location (g, gimple_location (stmt));
15210 gsi_replace (gsi, g, true);
15212 /* Flavors of vec_div (Integer). */
15213 case VSX_BUILTIN_DIV_V2DI:
15214 case VSX_BUILTIN_UDIV_V2DI:
15215 arg0 = gimple_call_arg (stmt, 0);
15216 arg1 = gimple_call_arg (stmt, 1);
15217 lhs = gimple_call_lhs (stmt);
15218 g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
15219 gimple_set_location (g, gimple_location (stmt));
15220 gsi_replace (gsi, g, true);
15222 /* Flavors of vec_div (Float). */
15223 case VSX_BUILTIN_XVDIVSP:
15224 case VSX_BUILTIN_XVDIVDP:
15225 arg0 = gimple_call_arg (stmt, 0);
15226 arg1 = gimple_call_arg (stmt, 1);
15227 lhs = gimple_call_lhs (stmt);
15228 g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
15229 gimple_set_location (g, gimple_location (stmt));
15230 gsi_replace (gsi, g, true);
15232 /* Flavors of vec_and. */
15233 case ALTIVEC_BUILTIN_VAND:
15234 arg0 = gimple_call_arg (stmt, 0);
15235 arg1 = gimple_call_arg (stmt, 1);
15236 lhs = gimple_call_lhs (stmt);
15237 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, arg1);
15238 gimple_set_location (g, gimple_location (stmt));
15239 gsi_replace (gsi, g, true);
15241 /* Flavors of vec_andc. */
15242 case ALTIVEC_BUILTIN_VANDC:
15243 arg0 = gimple_call_arg (stmt, 0);
15244 arg1 = gimple_call_arg (stmt, 1);
15245 lhs = gimple_call_lhs (stmt);
15246 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15247 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15248 gimple_set_location (g, gimple_location (stmt));
15249 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15250 g = gimple_build_assign (lhs, BIT_AND_EXPR, arg0, temp);
15251 gimple_set_location (g, gimple_location (stmt));
15252 gsi_replace (gsi, g, true);
15254 /* Flavors of vec_nand. */
15255 case P8V_BUILTIN_VEC_NAND:
15256 case P8V_BUILTIN_NAND_V16QI:
15257 case P8V_BUILTIN_NAND_V8HI:
15258 case P8V_BUILTIN_NAND_V4SI:
15259 case P8V_BUILTIN_NAND_V4SF:
15260 case P8V_BUILTIN_NAND_V2DF:
15261 case P8V_BUILTIN_NAND_V2DI:
15262 arg0 = gimple_call_arg (stmt, 0);
15263 arg1 = gimple_call_arg (stmt, 1);
15264 lhs = gimple_call_lhs (stmt);
15265 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15266 g = gimple_build_assign (temp, BIT_AND_EXPR, arg0, arg1);
15267 gimple_set_location (g, gimple_location (stmt));
15268 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15269 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15270 gimple_set_location (g, gimple_location (stmt));
15271 gsi_replace (gsi, g, true);
15273 /* Flavors of vec_or. */
15274 case ALTIVEC_BUILTIN_VOR:
15275 arg0 = gimple_call_arg (stmt, 0);
15276 arg1 = gimple_call_arg (stmt, 1);
15277 lhs = gimple_call_lhs (stmt);
15278 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, arg1);
15279 gimple_set_location (g, gimple_location (stmt));
15280 gsi_replace (gsi, g, true);
15282 /* flavors of vec_orc. */
15283 case P8V_BUILTIN_ORC_V16QI:
15284 case P8V_BUILTIN_ORC_V8HI:
15285 case P8V_BUILTIN_ORC_V4SI:
15286 case P8V_BUILTIN_ORC_V4SF:
15287 case P8V_BUILTIN_ORC_V2DF:
15288 case P8V_BUILTIN_ORC_V2DI:
15289 arg0 = gimple_call_arg (stmt, 0);
15290 arg1 = gimple_call_arg (stmt, 1);
15291 lhs = gimple_call_lhs (stmt);
15292 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15293 g = gimple_build_assign (temp, BIT_NOT_EXPR, arg1);
15294 gimple_set_location (g, gimple_location (stmt));
15295 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15296 g = gimple_build_assign (lhs, BIT_IOR_EXPR, arg0, temp);
15297 gimple_set_location (g, gimple_location (stmt));
15298 gsi_replace (gsi, g, true);
15300 /* Flavors of vec_xor. */
15301 case ALTIVEC_BUILTIN_VXOR:
15302 arg0 = gimple_call_arg (stmt, 0);
15303 arg1 = gimple_call_arg (stmt, 1);
15304 lhs = gimple_call_lhs (stmt);
15305 g = gimple_build_assign (lhs, BIT_XOR_EXPR, arg0, arg1);
15306 gimple_set_location (g, gimple_location (stmt));
15307 gsi_replace (gsi, g, true);
15309 /* Flavors of vec_nor. */
15310 case ALTIVEC_BUILTIN_VNOR:
15311 arg0 = gimple_call_arg (stmt, 0);
15312 arg1 = gimple_call_arg (stmt, 1);
15313 lhs = gimple_call_lhs (stmt);
15314 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15315 g = gimple_build_assign (temp, BIT_IOR_EXPR, arg0, arg1);
15316 gimple_set_location (g, gimple_location (stmt));
15317 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15318 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15319 gimple_set_location (g, gimple_location (stmt));
15320 gsi_replace (gsi, g, true);
15322 /* flavors of vec_abs. */
15323 case ALTIVEC_BUILTIN_ABS_V16QI:
15324 case ALTIVEC_BUILTIN_ABS_V8HI:
15325 case ALTIVEC_BUILTIN_ABS_V4SI:
15326 case ALTIVEC_BUILTIN_ABS_V4SF:
15327 case P8V_BUILTIN_ABS_V2DI:
15328 case VSX_BUILTIN_XVABSDP:
15329 arg0 = gimple_call_arg (stmt, 0);
15330 if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
15331 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
15333 lhs = gimple_call_lhs (stmt);
15334 g = gimple_build_assign (lhs, ABS_EXPR, arg0);
15335 gimple_set_location (g, gimple_location (stmt));
15336 gsi_replace (gsi, g, true);
15338 /* flavors of vec_min. */
15339 case VSX_BUILTIN_XVMINDP:
15340 case P8V_BUILTIN_VMINSD:
15341 case P8V_BUILTIN_VMINUD:
15342 case ALTIVEC_BUILTIN_VMINSB:
15343 case ALTIVEC_BUILTIN_VMINSH:
15344 case ALTIVEC_BUILTIN_VMINSW:
15345 case ALTIVEC_BUILTIN_VMINUB:
15346 case ALTIVEC_BUILTIN_VMINUH:
15347 case ALTIVEC_BUILTIN_VMINUW:
15348 case ALTIVEC_BUILTIN_VMINFP:
15349 arg0 = gimple_call_arg (stmt, 0);
15350 arg1 = gimple_call_arg (stmt, 1);
15351 lhs = gimple_call_lhs (stmt);
15352 g = gimple_build_assign (lhs, MIN_EXPR, arg0, arg1);
15353 gimple_set_location (g, gimple_location (stmt));
15354 gsi_replace (gsi, g, true);
15356 /* flavors of vec_max. */
15357 case VSX_BUILTIN_XVMAXDP:
15358 case P8V_BUILTIN_VMAXSD:
15359 case P8V_BUILTIN_VMAXUD:
15360 case ALTIVEC_BUILTIN_VMAXSB:
15361 case ALTIVEC_BUILTIN_VMAXSH:
15362 case ALTIVEC_BUILTIN_VMAXSW:
15363 case ALTIVEC_BUILTIN_VMAXUB:
15364 case ALTIVEC_BUILTIN_VMAXUH:
15365 case ALTIVEC_BUILTIN_VMAXUW:
15366 case ALTIVEC_BUILTIN_VMAXFP:
15367 arg0 = gimple_call_arg (stmt, 0);
15368 arg1 = gimple_call_arg (stmt, 1);
15369 lhs = gimple_call_lhs (stmt);
15370 g = gimple_build_assign (lhs, MAX_EXPR, arg0, arg1);
15371 gimple_set_location (g, gimple_location (stmt));
15372 gsi_replace (gsi, g, true);
15374 /* Flavors of vec_eqv. */
15375 case P8V_BUILTIN_EQV_V16QI:
15376 case P8V_BUILTIN_EQV_V8HI:
15377 case P8V_BUILTIN_EQV_V4SI:
15378 case P8V_BUILTIN_EQV_V4SF:
15379 case P8V_BUILTIN_EQV_V2DF:
15380 case P8V_BUILTIN_EQV_V2DI:
15381 arg0 = gimple_call_arg (stmt, 0);
15382 arg1 = gimple_call_arg (stmt, 1);
15383 lhs = gimple_call_lhs (stmt);
15384 temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1));
15385 g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1);
15386 gimple_set_location (g, gimple_location (stmt));
15387 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15388 g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp);
15389 gimple_set_location (g, gimple_location (stmt));
15390 gsi_replace (gsi, g, true);
15392 /* Flavors of vec_rotate_left. */
15393 case ALTIVEC_BUILTIN_VRLB:
15394 case ALTIVEC_BUILTIN_VRLH:
15395 case ALTIVEC_BUILTIN_VRLW:
15396 case P8V_BUILTIN_VRLD:
15397 arg0 = gimple_call_arg (stmt, 0);
15398 arg1 = gimple_call_arg (stmt, 1);
15399 lhs = gimple_call_lhs (stmt);
15400 g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
15401 gimple_set_location (g, gimple_location (stmt));
15402 gsi_replace (gsi, g, true);
15404 /* Flavors of vector shift right algebraic.
15405 vec_sra{b,h,w} -> vsra{b,h,w}. */
15406 case ALTIVEC_BUILTIN_VSRAB:
15407 case ALTIVEC_BUILTIN_VSRAH:
15408 case ALTIVEC_BUILTIN_VSRAW:
15409 case P8V_BUILTIN_VSRAD:
15411 arg0 = gimple_call_arg (stmt, 0);
15412 arg1 = gimple_call_arg (stmt, 1);
15413 lhs = gimple_call_lhs (stmt);
15414 tree arg1_type = TREE_TYPE (arg1);
15415 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15416 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15417 location_t loc = gimple_location (stmt);
15418 /* Force arg1 into the range valid matching the arg0 type. */
15419 /* Build a vector consisting of the max valid bit-size values. */
15420 int n_elts = VECTOR_CST_NELTS (arg1);
15421 tree element_size = build_int_cst (unsigned_element_type,
15423 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
15424 for (int i = 0; i < n_elts; i++)
15425 elts.safe_push (element_size);
15426 tree modulo_tree = elts.build ();
15427 /* Modulo the provided shift value against that vector. */
15428 gimple_seq stmts = NULL;
15429 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15430 unsigned_arg1_type, arg1);
15431 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15432 unsigned_arg1_type, unsigned_arg1,
15434 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15435 /* And finally, do the shift. */
15436 g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, new_arg1);
15437 gimple_set_location (g, loc);
15438 gsi_replace (gsi, g, true);
15441 /* Flavors of vector shift left.
15442 builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
15443 case ALTIVEC_BUILTIN_VSLB:
15444 case ALTIVEC_BUILTIN_VSLH:
15445 case ALTIVEC_BUILTIN_VSLW:
15446 case P8V_BUILTIN_VSLD:
15449 gimple_seq stmts = NULL;
15450 arg0 = gimple_call_arg (stmt, 0);
15451 tree arg0_type = TREE_TYPE (arg0);
15452 if (INTEGRAL_TYPE_P (TREE_TYPE (arg0_type))
15453 && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0_type)))
15455 arg1 = gimple_call_arg (stmt, 1);
15456 tree arg1_type = TREE_TYPE (arg1);
15457 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15458 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15459 loc = gimple_location (stmt);
15460 lhs = gimple_call_lhs (stmt);
15461 /* Force arg1 into the range valid matching the arg0 type. */
15462 /* Build a vector consisting of the max valid bit-size values. */
15463 int n_elts = VECTOR_CST_NELTS (arg1);
15464 int tree_size_in_bits = TREE_INT_CST_LOW (size_in_bytes (arg1_type))
15466 tree element_size = build_int_cst (unsigned_element_type,
15467 tree_size_in_bits / n_elts);
15468 tree_vector_builder elts (unsigned_type_for (arg1_type), n_elts, 1);
15469 for (int i = 0; i < n_elts; i++)
15470 elts.safe_push (element_size);
15471 tree modulo_tree = elts.build ();
15472 /* Modulo the provided shift value against that vector. */
15473 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15474 unsigned_arg1_type, arg1);
15475 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15476 unsigned_arg1_type, unsigned_arg1,
15478 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15479 /* And finally, do the shift. */
15480 g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, new_arg1);
15481 gimple_set_location (g, gimple_location (stmt));
15482 gsi_replace (gsi, g, true);
15485 /* Flavors of vector shift right. */
15486 case ALTIVEC_BUILTIN_VSRB:
15487 case ALTIVEC_BUILTIN_VSRH:
15488 case ALTIVEC_BUILTIN_VSRW:
15489 case P8V_BUILTIN_VSRD:
15491 arg0 = gimple_call_arg (stmt, 0);
15492 arg1 = gimple_call_arg (stmt, 1);
15493 lhs = gimple_call_lhs (stmt);
15494 tree arg1_type = TREE_TYPE (arg1);
15495 tree unsigned_arg1_type = unsigned_type_for (TREE_TYPE (arg1));
15496 tree unsigned_element_type = unsigned_type_for (TREE_TYPE (arg1_type));
15497 location_t loc = gimple_location (stmt);
15498 gimple_seq stmts = NULL;
15499 /* Convert arg0 to unsigned. */
15501 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15502 unsigned_type_for (TREE_TYPE (arg0)), arg0);
15503 /* Force arg1 into the range valid matching the arg0 type. */
15504 /* Build a vector consisting of the max valid bit-size values. */
15505 int n_elts = VECTOR_CST_NELTS (arg1);
15506 tree element_size = build_int_cst (unsigned_element_type,
15508 tree_vector_builder elts (unsigned_arg1_type, n_elts, 1);
15509 for (int i = 0; i < n_elts; i++)
15510 elts.safe_push (element_size);
15511 tree modulo_tree = elts.build ();
15512 /* Modulo the provided shift value against that vector. */
15513 tree unsigned_arg1 = gimple_build (&stmts, VIEW_CONVERT_EXPR,
15514 unsigned_arg1_type, arg1);
15515 tree new_arg1 = gimple_build (&stmts, loc, TRUNC_MOD_EXPR,
15516 unsigned_arg1_type, unsigned_arg1,
15518 /* Do the shift. */
15520 = gimple_build (&stmts, RSHIFT_EXPR,
15521 TREE_TYPE (arg0_unsigned), arg0_unsigned, new_arg1);
15522 /* Convert result back to the lhs type. */
15523 res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
15524 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15525 update_call_from_tree (gsi, res);
15528 /* Vector loads. */
15529 case ALTIVEC_BUILTIN_LVX_V16QI:
15530 case ALTIVEC_BUILTIN_LVX_V8HI:
15531 case ALTIVEC_BUILTIN_LVX_V4SI:
15532 case ALTIVEC_BUILTIN_LVX_V4SF:
15533 case ALTIVEC_BUILTIN_LVX_V2DI:
15534 case ALTIVEC_BUILTIN_LVX_V2DF:
15535 case ALTIVEC_BUILTIN_LVX_V1TI:
15537 arg0 = gimple_call_arg (stmt, 0); // offset
15538 arg1 = gimple_call_arg (stmt, 1); // address
15539 lhs = gimple_call_lhs (stmt);
15540 location_t loc = gimple_location (stmt);
15541 /* Since arg1 may be cast to a different type, just use ptr_type_node
15542 here instead of trying to enforce TBAA on pointer types. */
15543 tree arg1_type = ptr_type_node;
15544 tree lhs_type = TREE_TYPE (lhs);
15545 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15546 the tree using the value from arg0. The resulting type will match
15547 the type of arg1. */
15548 gimple_seq stmts = NULL;
15549 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15550 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15551 arg1_type, arg1, temp_offset);
15552 /* Mask off any lower bits from the address. */
15553 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15554 arg1_type, temp_addr,
15555 build_int_cst (arg1_type, -16));
15556 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15557 if (!is_gimple_mem_ref_addr (aligned_addr))
15559 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
15560 gimple *g = gimple_build_assign (t, aligned_addr);
15561 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15564 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15565 take an offset, but since we've already incorporated the offset
15566 above, here we just pass in a zero. */
15568 = gimple_build_assign (lhs, build2 (MEM_REF, lhs_type, aligned_addr,
15569 build_int_cst (arg1_type, 0)));
15570 gimple_set_location (g, loc);
15571 gsi_replace (gsi, g, true);
15574 /* Vector stores. */
15575 case ALTIVEC_BUILTIN_STVX_V16QI:
15576 case ALTIVEC_BUILTIN_STVX_V8HI:
15577 case ALTIVEC_BUILTIN_STVX_V4SI:
15578 case ALTIVEC_BUILTIN_STVX_V4SF:
15579 case ALTIVEC_BUILTIN_STVX_V2DI:
15580 case ALTIVEC_BUILTIN_STVX_V2DF:
15582 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15583 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15584 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15585 location_t loc = gimple_location (stmt);
15586 tree arg0_type = TREE_TYPE (arg0);
15587 /* Use ptr_type_node (no TBAA) for the arg2_type.
15588 FIXME: (Richard) "A proper fix would be to transition this type as
15589 seen from the frontend to GIMPLE, for example in a similar way we
15590 do for MEM_REFs by piggy-backing that on an extra argument, a
15591 constant zero pointer of the alias pointer type to use (which would
15592 also serve as a type indicator of the store itself). I'd use a
15593 target specific internal function for this (not sure if we can have
15594 those target specific, but I guess if it's folded away then that's
15595 fine) and get away with the overload set." */
15596 tree arg2_type = ptr_type_node;
15597 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15598 the tree using the value from arg0. The resulting type will match
15599 the type of arg2. */
15600 gimple_seq stmts = NULL;
15601 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15602 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15603 arg2_type, arg2, temp_offset);
15604 /* Mask off any lower bits from the address. */
15605 tree aligned_addr = gimple_build (&stmts, loc, BIT_AND_EXPR,
15606 arg2_type, temp_addr,
15607 build_int_cst (arg2_type, -16));
15608 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15609 if (!is_gimple_mem_ref_addr (aligned_addr))
15611 tree t = make_ssa_name (TREE_TYPE (aligned_addr));
15612 gimple *g = gimple_build_assign (t, aligned_addr);
15613 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15616 /* The desired gimple result should be similar to:
15617 MEM[(__vector floatD.1407 *)_1] = vf1D.2697; */
15619 = gimple_build_assign (build2 (MEM_REF, arg0_type, aligned_addr,
15620 build_int_cst (arg2_type, 0)), arg0);
15621 gimple_set_location (g, loc);
15622 gsi_replace (gsi, g, true);
15626 /* unaligned Vector loads. */
15627 case VSX_BUILTIN_LXVW4X_V16QI:
15628 case VSX_BUILTIN_LXVW4X_V8HI:
15629 case VSX_BUILTIN_LXVW4X_V4SF:
15630 case VSX_BUILTIN_LXVW4X_V4SI:
15631 case VSX_BUILTIN_LXVD2X_V2DF:
15632 case VSX_BUILTIN_LXVD2X_V2DI:
15634 arg0 = gimple_call_arg (stmt, 0); // offset
15635 arg1 = gimple_call_arg (stmt, 1); // address
15636 lhs = gimple_call_lhs (stmt);
15637 location_t loc = gimple_location (stmt);
15638 /* Since arg1 may be cast to a different type, just use ptr_type_node
15639 here instead of trying to enforce TBAA on pointer types. */
15640 tree arg1_type = ptr_type_node;
15641 tree lhs_type = TREE_TYPE (lhs);
15642 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15643 required alignment (power) is 4 bytes regardless of data type. */
15644 tree align_ltype = build_aligned_type (lhs_type, 4);
15645 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15646 the tree using the value from arg0. The resulting type will match
15647 the type of arg1. */
15648 gimple_seq stmts = NULL;
15649 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg0);
15650 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15651 arg1_type, arg1, temp_offset);
15652 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15653 if (!is_gimple_mem_ref_addr (temp_addr))
15655 tree t = make_ssa_name (TREE_TYPE (temp_addr));
15656 gimple *g = gimple_build_assign (t, temp_addr);
15657 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15660 /* Use the build2 helper to set up the mem_ref. The MEM_REF could also
15661 take an offset, but since we've already incorporated the offset
15662 above, here we just pass in a zero. */
15664 g = gimple_build_assign (lhs, build2 (MEM_REF, align_ltype, temp_addr,
15665 build_int_cst (arg1_type, 0)));
15666 gimple_set_location (g, loc);
15667 gsi_replace (gsi, g, true);
15671 /* unaligned Vector stores. */
15672 case VSX_BUILTIN_STXVW4X_V16QI:
15673 case VSX_BUILTIN_STXVW4X_V8HI:
15674 case VSX_BUILTIN_STXVW4X_V4SF:
15675 case VSX_BUILTIN_STXVW4X_V4SI:
15676 case VSX_BUILTIN_STXVD2X_V2DF:
15677 case VSX_BUILTIN_STXVD2X_V2DI:
15679 arg0 = gimple_call_arg (stmt, 0); /* Value to be stored. */
15680 arg1 = gimple_call_arg (stmt, 1); /* Offset. */
15681 tree arg2 = gimple_call_arg (stmt, 2); /* Store-to address. */
15682 location_t loc = gimple_location (stmt);
15683 tree arg0_type = TREE_TYPE (arg0);
15684 /* Use ptr_type_node (no TBAA) for the arg2_type. */
15685 tree arg2_type = ptr_type_node;
15686 /* In GIMPLE the type of the MEM_REF specifies the alignment. The
15687 required alignment (power) is 4 bytes regardless of data type. */
15688 tree align_stype = build_aligned_type (arg0_type, 4);
15689 /* POINTER_PLUS_EXPR wants the offset to be of type 'sizetype'. Create
15690 the tree using the value from arg1. */
15691 gimple_seq stmts = NULL;
15692 tree temp_offset = gimple_convert (&stmts, loc, sizetype, arg1);
15693 tree temp_addr = gimple_build (&stmts, loc, POINTER_PLUS_EXPR,
15694 arg2_type, arg2, temp_offset);
15695 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15696 if (!is_gimple_mem_ref_addr (temp_addr))
15698 tree t = make_ssa_name (TREE_TYPE (temp_addr));
15699 gimple *g = gimple_build_assign (t, temp_addr);
15700 gsi_insert_before (gsi, g, GSI_SAME_STMT);
15704 g = gimple_build_assign (build2 (MEM_REF, align_stype, temp_addr,
15705 build_int_cst (arg2_type, 0)), arg0);
15706 gimple_set_location (g, loc);
15707 gsi_replace (gsi, g, true);
15711 /* Vector Fused multiply-add (fma). */
15712 case ALTIVEC_BUILTIN_VMADDFP:
15713 case VSX_BUILTIN_XVMADDDP:
15714 case ALTIVEC_BUILTIN_VMLADDUHM:
15716 arg0 = gimple_call_arg (stmt, 0);
15717 arg1 = gimple_call_arg (stmt, 1);
15718 tree arg2 = gimple_call_arg (stmt, 2);
15719 lhs = gimple_call_lhs (stmt);
15720 gcall *g = gimple_build_call_internal (IFN_FMA, 3, arg0, arg1, arg2);
15721 gimple_call_set_lhs (g, lhs);
15722 gimple_call_set_nothrow (g, true);
15723 gimple_set_location (g, gimple_location (stmt));
15724 gsi_replace (gsi, g, true);
15728 /* Vector compares; EQ, NE, GE, GT, LE. */
15729 case ALTIVEC_BUILTIN_VCMPEQUB:
15730 case ALTIVEC_BUILTIN_VCMPEQUH:
15731 case ALTIVEC_BUILTIN_VCMPEQUW:
15732 case P8V_BUILTIN_VCMPEQUD:
15733 fold_compare_helper (gsi, EQ_EXPR, stmt);
15736 case P9V_BUILTIN_CMPNEB:
15737 case P9V_BUILTIN_CMPNEH:
15738 case P9V_BUILTIN_CMPNEW:
15739 fold_compare_helper (gsi, NE_EXPR, stmt);
15742 case VSX_BUILTIN_CMPGE_16QI:
15743 case VSX_BUILTIN_CMPGE_U16QI:
15744 case VSX_BUILTIN_CMPGE_8HI:
15745 case VSX_BUILTIN_CMPGE_U8HI:
15746 case VSX_BUILTIN_CMPGE_4SI:
15747 case VSX_BUILTIN_CMPGE_U4SI:
15748 case VSX_BUILTIN_CMPGE_2DI:
15749 case VSX_BUILTIN_CMPGE_U2DI:
15750 fold_compare_helper (gsi, GE_EXPR, stmt);
15753 case ALTIVEC_BUILTIN_VCMPGTSB:
15754 case ALTIVEC_BUILTIN_VCMPGTUB:
15755 case ALTIVEC_BUILTIN_VCMPGTSH:
15756 case ALTIVEC_BUILTIN_VCMPGTUH:
15757 case ALTIVEC_BUILTIN_VCMPGTSW:
15758 case ALTIVEC_BUILTIN_VCMPGTUW:
15759 case P8V_BUILTIN_VCMPGTUD:
15760 case P8V_BUILTIN_VCMPGTSD:
15761 fold_compare_helper (gsi, GT_EXPR, stmt);
15764 case VSX_BUILTIN_CMPLE_16QI:
15765 case VSX_BUILTIN_CMPLE_U16QI:
15766 case VSX_BUILTIN_CMPLE_8HI:
15767 case VSX_BUILTIN_CMPLE_U8HI:
15768 case VSX_BUILTIN_CMPLE_4SI:
15769 case VSX_BUILTIN_CMPLE_U4SI:
15770 case VSX_BUILTIN_CMPLE_2DI:
15771 case VSX_BUILTIN_CMPLE_U2DI:
15772 fold_compare_helper (gsi, LE_EXPR, stmt);
15775 /* flavors of vec_splat_[us]{8,16,32}. */
15776 case ALTIVEC_BUILTIN_VSPLTISB:
15777 case ALTIVEC_BUILTIN_VSPLTISH:
15778 case ALTIVEC_BUILTIN_VSPLTISW:
15780 arg0 = gimple_call_arg (stmt, 0);
15781 lhs = gimple_call_lhs (stmt);
15783 /* Only fold the vec_splat_*() if the lower bits of arg 0 is a
15784 5-bit signed constant in range -16 to +15. */
15785 if (TREE_CODE (arg0) != INTEGER_CST
15786 || !IN_RANGE (TREE_INT_CST_LOW (arg0), -16, 15))
15788 gimple_seq stmts = NULL;
15789 location_t loc = gimple_location (stmt);
15790 tree splat_value = gimple_convert (&stmts, loc,
15791 TREE_TYPE (TREE_TYPE (lhs)), arg0);
15792 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15793 tree splat_tree = build_vector_from_val (TREE_TYPE (lhs), splat_value);
15794 g = gimple_build_assign (lhs, splat_tree);
15795 gimple_set_location (g, gimple_location (stmt));
15796 gsi_replace (gsi, g, true);
15800 /* Flavors of vec_splat. */
15801 /* a = vec_splat (b, 0x3) becomes a = { b[3],b[3],b[3],...}; */
15802 case ALTIVEC_BUILTIN_VSPLTB:
15803 case ALTIVEC_BUILTIN_VSPLTH:
15804 case ALTIVEC_BUILTIN_VSPLTW:
15805 case VSX_BUILTIN_XXSPLTD_V2DI:
15806 case VSX_BUILTIN_XXSPLTD_V2DF:
15808 arg0 = gimple_call_arg (stmt, 0); /* input vector. */
15809 arg1 = gimple_call_arg (stmt, 1); /* index into arg0. */
15810 /* Only fold the vec_splat_*() if arg1 is both a constant value and
15811 is a valid index into the arg0 vector. */
15812 unsigned int n_elts = VECTOR_CST_NELTS (arg0);
15813 if (TREE_CODE (arg1) != INTEGER_CST
15814 || TREE_INT_CST_LOW (arg1) > (n_elts -1))
15816 lhs = gimple_call_lhs (stmt);
15817 tree lhs_type = TREE_TYPE (lhs);
15818 tree arg0_type = TREE_TYPE (arg0);
15820 if (TREE_CODE (arg0) == VECTOR_CST)
15821 splat = VECTOR_CST_ELT (arg0, TREE_INT_CST_LOW (arg1));
15824 /* Determine (in bits) the length and start location of the
15825 splat value for a call to the tree_vec_extract helper. */
15826 int splat_elem_size = TREE_INT_CST_LOW (size_in_bytes (arg0_type))
15827 * BITS_PER_UNIT / n_elts;
15828 int splat_start_bit = TREE_INT_CST_LOW (arg1) * splat_elem_size;
15829 tree len = build_int_cst (bitsizetype, splat_elem_size);
15830 tree start = build_int_cst (bitsizetype, splat_start_bit);
15831 splat = tree_vec_extract (gsi, TREE_TYPE (lhs_type), arg0,
15834 /* And finally, build the new vector. */
15835 tree splat_tree = build_vector_from_val (lhs_type, splat);
15836 g = gimple_build_assign (lhs, splat_tree);
15837 gimple_set_location (g, gimple_location (stmt));
15838 gsi_replace (gsi, g, true);
15842 /* vec_mergel (integrals). */
15843 case ALTIVEC_BUILTIN_VMRGLH:
15844 case ALTIVEC_BUILTIN_VMRGLW:
15845 case VSX_BUILTIN_XXMRGLW_4SI:
15846 case ALTIVEC_BUILTIN_VMRGLB:
15847 case VSX_BUILTIN_VEC_MERGEL_V2DI:
15848 case VSX_BUILTIN_XXMRGLW_4SF:
15849 case VSX_BUILTIN_VEC_MERGEL_V2DF:
15850 fold_mergehl_helper (gsi, stmt, 1);
15852 /* vec_mergeh (integrals). */
15853 case ALTIVEC_BUILTIN_VMRGHH:
15854 case ALTIVEC_BUILTIN_VMRGHW:
15855 case VSX_BUILTIN_XXMRGHW_4SI:
15856 case ALTIVEC_BUILTIN_VMRGHB:
15857 case VSX_BUILTIN_VEC_MERGEH_V2DI:
15858 case VSX_BUILTIN_XXMRGHW_4SF:
15859 case VSX_BUILTIN_VEC_MERGEH_V2DF:
15860 fold_mergehl_helper (gsi, stmt, 0);
15863 /* Flavors of vec_mergee. */
15864 case P8V_BUILTIN_VMRGEW_V4SI:
15865 case P8V_BUILTIN_VMRGEW_V2DI:
15866 case P8V_BUILTIN_VMRGEW_V4SF:
15867 case P8V_BUILTIN_VMRGEW_V2DF:
15868 fold_mergeeo_helper (gsi, stmt, 0);
15870 /* Flavors of vec_mergeo. */
15871 case P8V_BUILTIN_VMRGOW_V4SI:
15872 case P8V_BUILTIN_VMRGOW_V2DI:
15873 case P8V_BUILTIN_VMRGOW_V4SF:
15874 case P8V_BUILTIN_VMRGOW_V2DF:
15875 fold_mergeeo_helper (gsi, stmt, 1);
15878 /* d = vec_pack (a, b) */
15879 case P8V_BUILTIN_VPKUDUM:
15880 case ALTIVEC_BUILTIN_VPKUHUM:
15881 case ALTIVEC_BUILTIN_VPKUWUM:
15883 arg0 = gimple_call_arg (stmt, 0);
15884 arg1 = gimple_call_arg (stmt, 1);
15885 lhs = gimple_call_lhs (stmt);
15886 gimple *g = gimple_build_assign (lhs, VEC_PACK_TRUNC_EXPR, arg0, arg1);
15887 gimple_set_location (g, gimple_location (stmt));
15888 gsi_replace (gsi, g, true);
15892 /* d = vec_unpackh (a) */
15893 /* Note that the UNPACK_{HI,LO}_EXPR used in the gimple_build_assign call
15894 in this code is sensitive to endian-ness, and needs to be inverted to
15895 handle both LE and BE targets. */
15896 case ALTIVEC_BUILTIN_VUPKHSB:
15897 case ALTIVEC_BUILTIN_VUPKHSH:
15898 case P8V_BUILTIN_VUPKHSW:
15900 arg0 = gimple_call_arg (stmt, 0);
15901 lhs = gimple_call_lhs (stmt);
15902 if (BYTES_BIG_ENDIAN)
15903 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
15905 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
15906 gimple_set_location (g, gimple_location (stmt));
15907 gsi_replace (gsi, g, true);
15910 /* d = vec_unpackl (a) */
15911 case ALTIVEC_BUILTIN_VUPKLSB:
15912 case ALTIVEC_BUILTIN_VUPKLSH:
15913 case P8V_BUILTIN_VUPKLSW:
15915 arg0 = gimple_call_arg (stmt, 0);
15916 lhs = gimple_call_lhs (stmt);
15917 if (BYTES_BIG_ENDIAN)
15918 g = gimple_build_assign (lhs, VEC_UNPACK_LO_EXPR, arg0);
15920 g = gimple_build_assign (lhs, VEC_UNPACK_HI_EXPR, arg0);
15921 gimple_set_location (g, gimple_location (stmt));
15922 gsi_replace (gsi, g, true);
15925 /* There is no gimple type corresponding with pixel, so just return. */
15926 case ALTIVEC_BUILTIN_VUPKHPX:
15927 case ALTIVEC_BUILTIN_VUPKLPX:
15931 case ALTIVEC_BUILTIN_VPERM_16QI:
15932 case ALTIVEC_BUILTIN_VPERM_8HI:
15933 case ALTIVEC_BUILTIN_VPERM_4SI:
15934 case ALTIVEC_BUILTIN_VPERM_2DI:
15935 case ALTIVEC_BUILTIN_VPERM_4SF:
15936 case ALTIVEC_BUILTIN_VPERM_2DF:
15938 arg0 = gimple_call_arg (stmt, 0);
15939 arg1 = gimple_call_arg (stmt, 1);
15940 tree permute = gimple_call_arg (stmt, 2);
15941 lhs = gimple_call_lhs (stmt);
15942 location_t loc = gimple_location (stmt);
15943 gimple_seq stmts = NULL;
15944 // convert arg0 and arg1 to match the type of the permute
15945 // for the VEC_PERM_EXPR operation.
15946 tree permute_type = (TREE_TYPE (permute));
15947 tree arg0_ptype = gimple_convert (&stmts, loc, permute_type, arg0);
15948 tree arg1_ptype = gimple_convert (&stmts, loc, permute_type, arg1);
15949 tree lhs_ptype = gimple_build (&stmts, loc, VEC_PERM_EXPR,
15950 permute_type, arg0_ptype, arg1_ptype,
15952 // Convert the result back to the desired lhs type upon completion.
15953 tree temp = gimple_convert (&stmts, loc, TREE_TYPE (lhs), lhs_ptype);
15954 gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
15955 g = gimple_build_assign (lhs, temp);
15956 gimple_set_location (g, loc);
15957 gsi_replace (gsi, g, true);
15962 if (TARGET_DEBUG_BUILTIN)
15963 fprintf (stderr, "gimple builtin intrinsic not matched:%d %s %s\n",
15964 fn_code, fn_name1, fn_name2);
15971 /* Expand an expression EXP that calls a built-in function,
15972 with result going to TARGET if that's convenient
15973 (and in mode MODE if that's convenient).
15974 SUBTARGET may be used as the target for computing one of EXP's operands.
15975 IGNORE is nonzero if the value is to be ignored. */
15978 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
15979 machine_mode mode ATTRIBUTE_UNUSED,
15980 int ignore ATTRIBUTE_UNUSED)
15982 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
15983 enum rs6000_builtins fcode
15984 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
15985 size_t uns_fcode = (size_t)fcode;
15986 const struct builtin_description *d;
15990 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
15991 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
15992 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
15994 /* We have two different modes (KFmode, TFmode) that are the IEEE 128-bit
15995 floating point type, depending on whether long double is the IBM extended
15996 double (KFmode) or long double is IEEE 128-bit (TFmode). It is simpler if
15997 we only define one variant of the built-in function, and switch the code
15998 when defining it, rather than defining two built-ins and using the
15999 overload table in rs6000-c.c to switch between the two. If we don't have
16000 the proper assembler, don't do this switch because CODE_FOR_*kf* and
16001 CODE_FOR_*tf* will be CODE_FOR_nothing. */
16002 if (FLOAT128_IEEE_P (TFmode))
16008 case CODE_FOR_sqrtkf2_odd: icode = CODE_FOR_sqrttf2_odd; break;
16009 case CODE_FOR_trunckfdf2_odd: icode = CODE_FOR_trunctfdf2_odd; break;
16010 case CODE_FOR_addkf3_odd: icode = CODE_FOR_addtf3_odd; break;
16011 case CODE_FOR_subkf3_odd: icode = CODE_FOR_subtf3_odd; break;
16012 case CODE_FOR_mulkf3_odd: icode = CODE_FOR_multf3_odd; break;
16013 case CODE_FOR_divkf3_odd: icode = CODE_FOR_divtf3_odd; break;
16014 case CODE_FOR_fmakf4_odd: icode = CODE_FOR_fmatf4_odd; break;
16015 case CODE_FOR_xsxexpqp_kf: icode = CODE_FOR_xsxexpqp_tf; break;
16016 case CODE_FOR_xsxsigqp_kf: icode = CODE_FOR_xsxsigqp_tf; break;
16017 case CODE_FOR_xststdcnegqp_kf: icode = CODE_FOR_xststdcnegqp_tf; break;
16018 case CODE_FOR_xsiexpqp_kf: icode = CODE_FOR_xsiexpqp_tf; break;
16019 case CODE_FOR_xsiexpqpf_kf: icode = CODE_FOR_xsiexpqpf_tf; break;
16020 case CODE_FOR_xststdcqp_kf: icode = CODE_FOR_xststdcqp_tf; break;
16023 if (TARGET_DEBUG_BUILTIN)
16025 const char *name1 = rs6000_builtin_info[uns_fcode].name;
16026 const char *name2 = (icode != CODE_FOR_nothing)
16027 ? get_insn_name ((int) icode)
16031 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
16033 default: name3 = "unknown"; break;
16034 case RS6000_BTC_SPECIAL: name3 = "special"; break;
16035 case RS6000_BTC_UNARY: name3 = "unary"; break;
16036 case RS6000_BTC_BINARY: name3 = "binary"; break;
16037 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
16038 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
16039 case RS6000_BTC_ABS: name3 = "abs"; break;
16040 case RS6000_BTC_DST: name3 = "dst"; break;
16045 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16046 (name1) ? name1 : "---", fcode,
16047 (name2) ? name2 : "---", (int) icode,
16049 func_valid_p ? "" : ", not valid");
16054 rs6000_invalid_builtin (fcode);
16056 /* Given it is invalid, just generate a normal call. */
16057 return expand_call (exp, target, ignore);
16062 case RS6000_BUILTIN_RECIP:
16063 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
16065 case RS6000_BUILTIN_RECIPF:
16066 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
16068 case RS6000_BUILTIN_RSQRTF:
16069 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
16071 case RS6000_BUILTIN_RSQRT:
16072 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
16074 case POWER7_BUILTIN_BPERMD:
16075 return rs6000_expand_binop_builtin (((TARGET_64BIT)
16076 ? CODE_FOR_bpermd_di
16077 : CODE_FOR_bpermd_si), exp, target);
16079 case RS6000_BUILTIN_GET_TB:
16080 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
16083 case RS6000_BUILTIN_MFTB:
16084 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
16085 ? CODE_FOR_rs6000_mftb_di
16086 : CODE_FOR_rs6000_mftb_si),
16089 case RS6000_BUILTIN_MFFS:
16090 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
16092 case RS6000_BUILTIN_MTFSB0:
16093 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb0, exp);
16095 case RS6000_BUILTIN_MTFSB1:
16096 return rs6000_expand_mtfsb_builtin (CODE_FOR_rs6000_mtfsb1, exp);
16098 case RS6000_BUILTIN_SET_FPSCR_RN:
16099 return rs6000_expand_set_fpscr_rn_builtin (CODE_FOR_rs6000_set_fpscr_rn,
16102 case RS6000_BUILTIN_SET_FPSCR_DRN:
16104 rs6000_expand_set_fpscr_drn_builtin (CODE_FOR_rs6000_set_fpscr_drn,
16107 case RS6000_BUILTIN_MFFSL:
16108 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffsl, target);
16110 case RS6000_BUILTIN_MTFSF:
16111 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
16113 case RS6000_BUILTIN_CPU_INIT:
16114 case RS6000_BUILTIN_CPU_IS:
16115 case RS6000_BUILTIN_CPU_SUPPORTS:
16116 return cpu_expand_builtin (fcode, exp, target);
16118 case MISC_BUILTIN_SPEC_BARRIER:
16120 emit_insn (gen_speculation_barrier ());
16124 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
16125 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
16127 int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
16128 : (int) CODE_FOR_altivec_lvsl_direct);
16129 machine_mode tmode = insn_data[icode2].operand[0].mode;
16130 machine_mode mode = insn_data[icode2].operand[1].mode;
16134 gcc_assert (TARGET_ALTIVEC);
16136 arg = CALL_EXPR_ARG (exp, 0);
16137 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
16138 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
16139 addr = memory_address (mode, op);
16140 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
16144 /* For the load case need to negate the address. */
16145 op = gen_reg_rtx (GET_MODE (addr));
16146 emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr)));
16148 op = gen_rtx_MEM (mode, op);
16151 || GET_MODE (target) != tmode
16152 || ! (*insn_data[icode2].operand[0].predicate) (target, tmode))
16153 target = gen_reg_rtx (tmode);
16155 pat = GEN_FCN (icode2) (target, op);
16163 case ALTIVEC_BUILTIN_VCFUX:
16164 case ALTIVEC_BUILTIN_VCFSX:
16165 case ALTIVEC_BUILTIN_VCTUXS:
16166 case ALTIVEC_BUILTIN_VCTSXS:
16167 /* FIXME: There's got to be a nicer way to handle this case than
16168 constructing a new CALL_EXPR. */
16169 if (call_expr_nargs (exp) == 1)
16171 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
16172 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
16176 /* For the pack and unpack int128 routines, fix up the builtin so it
16177 uses the correct IBM128 type. */
16178 case MISC_BUILTIN_PACK_IF:
16179 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16181 icode = CODE_FOR_packtf;
16182 fcode = MISC_BUILTIN_PACK_TF;
16183 uns_fcode = (size_t)fcode;
16187 case MISC_BUILTIN_UNPACK_IF:
16188 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
16190 icode = CODE_FOR_unpacktf;
16191 fcode = MISC_BUILTIN_UNPACK_TF;
16192 uns_fcode = (size_t)fcode;
16200 if (TARGET_ALTIVEC)
16202 ret = altivec_expand_builtin (exp, target, &success);
16209 ret = htm_expand_builtin (exp, target, &success);
16215 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
16216 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16217 gcc_assert (attr == RS6000_BTC_UNARY
16218 || attr == RS6000_BTC_BINARY
16219 || attr == RS6000_BTC_TERNARY
16220 || attr == RS6000_BTC_SPECIAL);
16222 /* Handle simple unary operations. */
16224 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
16225 if (d->code == fcode)
16226 return rs6000_expand_unop_builtin (icode, exp, target);
16228 /* Handle simple binary operations. */
16230 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
16231 if (d->code == fcode)
16232 return rs6000_expand_binop_builtin (icode, exp, target);
16234 /* Handle simple ternary operations. */
16236 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
16237 if (d->code == fcode)
16238 return rs6000_expand_ternop_builtin (icode, exp, target);
16240 /* Handle simple no-argument operations. */
16242 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
16243 if (d->code == fcode)
16244 return rs6000_expand_zeroop_builtin (icode, target);
16246 gcc_unreachable ();
16249 /* Create a builtin vector type with a name. Taking care not to give
16250 the canonical type a name. */
16253 rs6000_vector_type (const char *name, tree elt_type, unsigned num_elts)
16255 tree result = build_vector_type (elt_type, num_elts);
16257 /* Copy so we don't give the canonical type a name. */
16258 result = build_variant_type_copy (result);
16260 add_builtin_type (name, result);
16266 rs6000_init_builtins (void)
16272 if (TARGET_DEBUG_BUILTIN)
16273 fprintf (stderr, "rs6000_init_builtins%s%s\n",
16274 (TARGET_ALTIVEC) ? ", altivec" : "",
16275 (TARGET_VSX) ? ", vsx" : "");
16277 V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64 ? "__vector long"
16278 : "__vector long long",
16279 intDI_type_node, 2);
16280 V2DF_type_node = rs6000_vector_type ("__vector double", double_type_node, 2);
16281 V4SI_type_node = rs6000_vector_type ("__vector signed int",
16282 intSI_type_node, 4);
16283 V4SF_type_node = rs6000_vector_type ("__vector float", float_type_node, 4);
16284 V8HI_type_node = rs6000_vector_type ("__vector signed short",
16285 intHI_type_node, 8);
16286 V16QI_type_node = rs6000_vector_type ("__vector signed char",
16287 intQI_type_node, 16);
16289 unsigned_V16QI_type_node = rs6000_vector_type ("__vector unsigned char",
16290 unsigned_intQI_type_node, 16);
16291 unsigned_V8HI_type_node = rs6000_vector_type ("__vector unsigned short",
16292 unsigned_intHI_type_node, 8);
16293 unsigned_V4SI_type_node = rs6000_vector_type ("__vector unsigned int",
16294 unsigned_intSI_type_node, 4);
16295 unsigned_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16296 ? "__vector unsigned long"
16297 : "__vector unsigned long long",
16298 unsigned_intDI_type_node, 2);
16300 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
16302 const_str_type_node
16303 = build_pointer_type (build_qualified_type (char_type_node,
16306 /* We use V1TI mode as a special container to hold __int128_t items that
16307 must live in VSX registers. */
16308 if (intTI_type_node)
16310 V1TI_type_node = rs6000_vector_type ("__vector __int128",
16311 intTI_type_node, 1);
16312 unsigned_V1TI_type_node
16313 = rs6000_vector_type ("__vector unsigned __int128",
16314 unsigned_intTI_type_node, 1);
16317 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16318 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16319 'vector unsigned short'. */
16321 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
16322 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16323 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
16324 bool_long_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
16325 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
16327 long_integer_type_internal_node = long_integer_type_node;
16328 long_unsigned_type_internal_node = long_unsigned_type_node;
16329 long_long_integer_type_internal_node = long_long_integer_type_node;
16330 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
16331 intQI_type_internal_node = intQI_type_node;
16332 uintQI_type_internal_node = unsigned_intQI_type_node;
16333 intHI_type_internal_node = intHI_type_node;
16334 uintHI_type_internal_node = unsigned_intHI_type_node;
16335 intSI_type_internal_node = intSI_type_node;
16336 uintSI_type_internal_node = unsigned_intSI_type_node;
16337 intDI_type_internal_node = intDI_type_node;
16338 uintDI_type_internal_node = unsigned_intDI_type_node;
16339 intTI_type_internal_node = intTI_type_node;
16340 uintTI_type_internal_node = unsigned_intTI_type_node;
16341 float_type_internal_node = float_type_node;
16342 double_type_internal_node = double_type_node;
16343 long_double_type_internal_node = long_double_type_node;
16344 dfloat64_type_internal_node = dfloat64_type_node;
16345 dfloat128_type_internal_node = dfloat128_type_node;
16346 void_type_internal_node = void_type_node;
16348 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16349 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16350 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16351 format that uses a pair of doubles, depending on the switches and
16354 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16355 floating point, we need make sure the type is non-zero or else self-test
16356 fails during bootstrap.
16358 Always create __ibm128 as a separate type, even if the current long double
16359 format is IBM extended double.
16361 For IEEE 128-bit floating point, always create the type __ieee128. If the
16362 user used -mfloat128, rs6000-c.c will create a define from __float128 to
16364 if (TARGET_FLOAT128_TYPE)
16366 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
16367 ibm128_float_type_node = long_double_type_node;
16370 ibm128_float_type_node = make_node (REAL_TYPE);
16371 TYPE_PRECISION (ibm128_float_type_node) = 128;
16372 SET_TYPE_MODE (ibm128_float_type_node, IFmode);
16373 layout_type (ibm128_float_type_node);
16376 lang_hooks.types.register_builtin_type (ibm128_float_type_node,
16379 if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)
16380 ieee128_float_type_node = long_double_type_node;
16382 ieee128_float_type_node = float128_type_node;
16384 lang_hooks.types.register_builtin_type (ieee128_float_type_node,
16389 ieee128_float_type_node = ibm128_float_type_node = long_double_type_node;
16391 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16393 builtin_mode_to_type[QImode][0] = integer_type_node;
16394 builtin_mode_to_type[HImode][0] = integer_type_node;
16395 builtin_mode_to_type[SImode][0] = intSI_type_node;
16396 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
16397 builtin_mode_to_type[DImode][0] = intDI_type_node;
16398 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
16399 builtin_mode_to_type[TImode][0] = intTI_type_node;
16400 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
16401 builtin_mode_to_type[SFmode][0] = float_type_node;
16402 builtin_mode_to_type[DFmode][0] = double_type_node;
16403 builtin_mode_to_type[IFmode][0] = ibm128_float_type_node;
16404 builtin_mode_to_type[KFmode][0] = ieee128_float_type_node;
16405 builtin_mode_to_type[TFmode][0] = long_double_type_node;
16406 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
16407 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
16408 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
16409 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
16410 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
16411 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
16412 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
16413 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
16414 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
16415 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
16416 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
16417 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
16418 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
16419 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
16421 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
16422 TYPE_NAME (bool_char_type_node) = tdecl;
16424 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
16425 TYPE_NAME (bool_short_type_node) = tdecl;
16427 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
16428 TYPE_NAME (bool_int_type_node) = tdecl;
16430 tdecl = add_builtin_type ("__pixel", pixel_type_node);
16431 TYPE_NAME (pixel_type_node) = tdecl;
16433 bool_V16QI_type_node = rs6000_vector_type ("__vector __bool char",
16434 bool_char_type_node, 16);
16435 bool_V8HI_type_node = rs6000_vector_type ("__vector __bool short",
16436 bool_short_type_node, 8);
16437 bool_V4SI_type_node = rs6000_vector_type ("__vector __bool int",
16438 bool_int_type_node, 4);
16439 bool_V2DI_type_node = rs6000_vector_type (TARGET_POWERPC64
16440 ? "__vector __bool long"
16441 : "__vector __bool long long",
16442 bool_long_long_type_node, 2);
16443 pixel_V8HI_type_node = rs6000_vector_type ("__vector __pixel",
16444 pixel_type_node, 8);
16446 /* Create Altivec and VSX builtins on machines with at least the
16447 general purpose extensions (970 and newer) to allow the use of
16448 the target attribute. */
16449 if (TARGET_EXTRA_BUILTINS)
16450 altivec_init_builtins ();
16452 htm_init_builtins ();
16454 if (TARGET_EXTRA_BUILTINS)
16455 rs6000_common_init_builtins ();
16457 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
16458 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
16459 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
16461 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
16462 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
16463 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
16465 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
16466 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
16467 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
16469 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
16470 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
16471 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
16473 mode = (TARGET_64BIT) ? DImode : SImode;
16474 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
16475 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
16476 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
16478 ftype = build_function_type_list (unsigned_intDI_type_node,
16480 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
16483 ftype = build_function_type_list (unsigned_intDI_type_node,
16486 ftype = build_function_type_list (unsigned_intSI_type_node,
16488 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
16490 ftype = build_function_type_list (double_type_node, NULL_TREE);
16491 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
16493 ftype = build_function_type_list (double_type_node, NULL_TREE);
16494 def_builtin ("__builtin_mffsl", ftype, RS6000_BUILTIN_MFFSL);
16496 ftype = build_function_type_list (void_type_node,
16499 def_builtin ("__builtin_mtfsb0", ftype, RS6000_BUILTIN_MTFSB0);
16501 ftype = build_function_type_list (void_type_node,
16504 def_builtin ("__builtin_mtfsb1", ftype, RS6000_BUILTIN_MTFSB1);
16506 ftype = build_function_type_list (void_type_node,
16509 def_builtin ("__builtin_set_fpscr_rn", ftype, RS6000_BUILTIN_SET_FPSCR_RN);
16511 ftype = build_function_type_list (void_type_node,
16514 def_builtin ("__builtin_set_fpscr_drn", ftype, RS6000_BUILTIN_SET_FPSCR_DRN);
16516 ftype = build_function_type_list (void_type_node,
16517 intSI_type_node, double_type_node,
16519 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
16521 ftype = build_function_type_list (void_type_node, NULL_TREE);
16522 def_builtin ("__builtin_cpu_init", ftype, RS6000_BUILTIN_CPU_INIT);
16523 def_builtin ("__builtin_ppc_speculation_barrier", ftype,
16524 MISC_BUILTIN_SPEC_BARRIER);
16526 ftype = build_function_type_list (bool_int_type_node, const_ptr_type_node,
16528 def_builtin ("__builtin_cpu_is", ftype, RS6000_BUILTIN_CPU_IS);
16529 def_builtin ("__builtin_cpu_supports", ftype, RS6000_BUILTIN_CPU_SUPPORTS);
16531 /* AIX libm provides clog as __clog. */
16532 if (TARGET_XCOFF &&
16533 (tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
16534 set_user_assembler_name (tdecl, "__clog");
16536 #ifdef SUBTARGET_INIT_BUILTINS
16537 SUBTARGET_INIT_BUILTINS;
16541 /* Returns the rs6000 builtin decl for CODE. */
16544 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
16546 HOST_WIDE_INT fnmask;
16548 if (code >= RS6000_BUILTIN_COUNT)
16549 return error_mark_node;
16551 fnmask = rs6000_builtin_info[code].mask;
16552 if ((fnmask & rs6000_builtin_mask) != fnmask)
16554 rs6000_invalid_builtin ((enum rs6000_builtins)code);
16555 return error_mark_node;
16558 return rs6000_builtin_decls[code];
16562 altivec_init_builtins (void)
16564 const struct builtin_description *d;
16568 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
16570 tree pvoid_type_node = build_pointer_type (void_type_node);
16572 tree pcvoid_type_node
16573 = build_pointer_type (build_qualified_type (void_type_node,
16576 tree int_ftype_opaque
16577 = build_function_type_list (integer_type_node,
16578 opaque_V4SI_type_node, NULL_TREE);
16579 tree opaque_ftype_opaque
16580 = build_function_type_list (integer_type_node, NULL_TREE);
16581 tree opaque_ftype_opaque_int
16582 = build_function_type_list (opaque_V4SI_type_node,
16583 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
16584 tree opaque_ftype_opaque_opaque_int
16585 = build_function_type_list (opaque_V4SI_type_node,
16586 opaque_V4SI_type_node, opaque_V4SI_type_node,
16587 integer_type_node, NULL_TREE);
16588 tree opaque_ftype_opaque_opaque_opaque
16589 = build_function_type_list (opaque_V4SI_type_node,
16590 opaque_V4SI_type_node, opaque_V4SI_type_node,
16591 opaque_V4SI_type_node, NULL_TREE);
16592 tree opaque_ftype_opaque_opaque
16593 = build_function_type_list (opaque_V4SI_type_node,
16594 opaque_V4SI_type_node, opaque_V4SI_type_node,
16596 tree int_ftype_int_opaque_opaque
16597 = build_function_type_list (integer_type_node,
16598 integer_type_node, opaque_V4SI_type_node,
16599 opaque_V4SI_type_node, NULL_TREE);
16600 tree int_ftype_int_v4si_v4si
16601 = build_function_type_list (integer_type_node,
16602 integer_type_node, V4SI_type_node,
16603 V4SI_type_node, NULL_TREE);
16604 tree int_ftype_int_v2di_v2di
16605 = build_function_type_list (integer_type_node,
16606 integer_type_node, V2DI_type_node,
16607 V2DI_type_node, NULL_TREE);
16608 tree void_ftype_v4si
16609 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
16610 tree v8hi_ftype_void
16611 = build_function_type_list (V8HI_type_node, NULL_TREE);
16612 tree void_ftype_void
16613 = build_function_type_list (void_type_node, NULL_TREE);
16614 tree void_ftype_int
16615 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
16617 tree opaque_ftype_long_pcvoid
16618 = build_function_type_list (opaque_V4SI_type_node,
16619 long_integer_type_node, pcvoid_type_node,
16621 tree v16qi_ftype_long_pcvoid
16622 = build_function_type_list (V16QI_type_node,
16623 long_integer_type_node, pcvoid_type_node,
16625 tree v8hi_ftype_long_pcvoid
16626 = build_function_type_list (V8HI_type_node,
16627 long_integer_type_node, pcvoid_type_node,
16629 tree v4si_ftype_long_pcvoid
16630 = build_function_type_list (V4SI_type_node,
16631 long_integer_type_node, pcvoid_type_node,
16633 tree v4sf_ftype_long_pcvoid
16634 = build_function_type_list (V4SF_type_node,
16635 long_integer_type_node, pcvoid_type_node,
16637 tree v2df_ftype_long_pcvoid
16638 = build_function_type_list (V2DF_type_node,
16639 long_integer_type_node, pcvoid_type_node,
16641 tree v2di_ftype_long_pcvoid
16642 = build_function_type_list (V2DI_type_node,
16643 long_integer_type_node, pcvoid_type_node,
16645 tree v1ti_ftype_long_pcvoid
16646 = build_function_type_list (V1TI_type_node,
16647 long_integer_type_node, pcvoid_type_node,
16650 tree void_ftype_opaque_long_pvoid
16651 = build_function_type_list (void_type_node,
16652 opaque_V4SI_type_node, long_integer_type_node,
16653 pvoid_type_node, NULL_TREE);
16654 tree void_ftype_v4si_long_pvoid
16655 = build_function_type_list (void_type_node,
16656 V4SI_type_node, long_integer_type_node,
16657 pvoid_type_node, NULL_TREE);
16658 tree void_ftype_v16qi_long_pvoid
16659 = build_function_type_list (void_type_node,
16660 V16QI_type_node, long_integer_type_node,
16661 pvoid_type_node, NULL_TREE);
16663 tree void_ftype_v16qi_pvoid_long
16664 = build_function_type_list (void_type_node,
16665 V16QI_type_node, pvoid_type_node,
16666 long_integer_type_node, NULL_TREE);
16668 tree void_ftype_v8hi_long_pvoid
16669 = build_function_type_list (void_type_node,
16670 V8HI_type_node, long_integer_type_node,
16671 pvoid_type_node, NULL_TREE);
16672 tree void_ftype_v4sf_long_pvoid
16673 = build_function_type_list (void_type_node,
16674 V4SF_type_node, long_integer_type_node,
16675 pvoid_type_node, NULL_TREE);
16676 tree void_ftype_v2df_long_pvoid
16677 = build_function_type_list (void_type_node,
16678 V2DF_type_node, long_integer_type_node,
16679 pvoid_type_node, NULL_TREE);
16680 tree void_ftype_v1ti_long_pvoid
16681 = build_function_type_list (void_type_node,
16682 V1TI_type_node, long_integer_type_node,
16683 pvoid_type_node, NULL_TREE);
16684 tree void_ftype_v2di_long_pvoid
16685 = build_function_type_list (void_type_node,
16686 V2DI_type_node, long_integer_type_node,
16687 pvoid_type_node, NULL_TREE);
16688 tree int_ftype_int_v8hi_v8hi
16689 = build_function_type_list (integer_type_node,
16690 integer_type_node, V8HI_type_node,
16691 V8HI_type_node, NULL_TREE);
16692 tree int_ftype_int_v16qi_v16qi
16693 = build_function_type_list (integer_type_node,
16694 integer_type_node, V16QI_type_node,
16695 V16QI_type_node, NULL_TREE);
16696 tree int_ftype_int_v4sf_v4sf
16697 = build_function_type_list (integer_type_node,
16698 integer_type_node, V4SF_type_node,
16699 V4SF_type_node, NULL_TREE);
16700 tree int_ftype_int_v2df_v2df
16701 = build_function_type_list (integer_type_node,
16702 integer_type_node, V2DF_type_node,
16703 V2DF_type_node, NULL_TREE);
16704 tree v2di_ftype_v2di
16705 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
16706 tree v4si_ftype_v4si
16707 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
16708 tree v8hi_ftype_v8hi
16709 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
16710 tree v16qi_ftype_v16qi
16711 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
16712 tree v4sf_ftype_v4sf
16713 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
16714 tree v2df_ftype_v2df
16715 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
16716 tree void_ftype_pcvoid_int_int
16717 = build_function_type_list (void_type_node,
16718 pcvoid_type_node, integer_type_node,
16719 integer_type_node, NULL_TREE);
16721 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
16722 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
16723 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
16724 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
16725 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
16726 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
16727 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
16728 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
16729 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
16730 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
16731 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
16732 ALTIVEC_BUILTIN_LVXL_V2DF);
16733 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
16734 ALTIVEC_BUILTIN_LVXL_V2DI);
16735 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
16736 ALTIVEC_BUILTIN_LVXL_V4SF);
16737 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
16738 ALTIVEC_BUILTIN_LVXL_V4SI);
16739 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
16740 ALTIVEC_BUILTIN_LVXL_V8HI);
16741 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
16742 ALTIVEC_BUILTIN_LVXL_V16QI);
16743 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
16744 def_builtin ("__builtin_altivec_lvx_v1ti", v1ti_ftype_long_pcvoid,
16745 ALTIVEC_BUILTIN_LVX_V1TI);
16746 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
16747 ALTIVEC_BUILTIN_LVX_V2DF);
16748 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
16749 ALTIVEC_BUILTIN_LVX_V2DI);
16750 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
16751 ALTIVEC_BUILTIN_LVX_V4SF);
16752 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
16753 ALTIVEC_BUILTIN_LVX_V4SI);
16754 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
16755 ALTIVEC_BUILTIN_LVX_V8HI);
16756 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
16757 ALTIVEC_BUILTIN_LVX_V16QI);
16758 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
16759 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
16760 ALTIVEC_BUILTIN_STVX_V2DF);
16761 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
16762 ALTIVEC_BUILTIN_STVX_V2DI);
16763 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
16764 ALTIVEC_BUILTIN_STVX_V4SF);
16765 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
16766 ALTIVEC_BUILTIN_STVX_V4SI);
16767 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
16768 ALTIVEC_BUILTIN_STVX_V8HI);
16769 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
16770 ALTIVEC_BUILTIN_STVX_V16QI);
16771 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
16772 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
16773 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
16774 ALTIVEC_BUILTIN_STVXL_V2DF);
16775 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
16776 ALTIVEC_BUILTIN_STVXL_V2DI);
16777 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
16778 ALTIVEC_BUILTIN_STVXL_V4SF);
16779 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
16780 ALTIVEC_BUILTIN_STVXL_V4SI);
16781 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
16782 ALTIVEC_BUILTIN_STVXL_V8HI);
16783 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
16784 ALTIVEC_BUILTIN_STVXL_V16QI);
16785 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
16786 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
16787 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
16788 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
16789 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
16790 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
16791 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
16792 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
16793 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
16794 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
16795 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
16796 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
16797 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
16798 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
16799 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
16800 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
16802 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
16803 VSX_BUILTIN_LXVD2X_V2DF);
16804 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
16805 VSX_BUILTIN_LXVD2X_V2DI);
16806 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
16807 VSX_BUILTIN_LXVW4X_V4SF);
16808 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
16809 VSX_BUILTIN_LXVW4X_V4SI);
16810 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
16811 VSX_BUILTIN_LXVW4X_V8HI);
16812 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
16813 VSX_BUILTIN_LXVW4X_V16QI);
16814 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
16815 VSX_BUILTIN_STXVD2X_V2DF);
16816 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
16817 VSX_BUILTIN_STXVD2X_V2DI);
16818 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
16819 VSX_BUILTIN_STXVW4X_V4SF);
16820 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
16821 VSX_BUILTIN_STXVW4X_V4SI);
16822 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
16823 VSX_BUILTIN_STXVW4X_V8HI);
16824 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
16825 VSX_BUILTIN_STXVW4X_V16QI);
16827 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid,
16828 VSX_BUILTIN_LD_ELEMREV_V2DF);
16829 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid,
16830 VSX_BUILTIN_LD_ELEMREV_V2DI);
16831 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid,
16832 VSX_BUILTIN_LD_ELEMREV_V4SF);
16833 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid,
16834 VSX_BUILTIN_LD_ELEMREV_V4SI);
16835 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid,
16836 VSX_BUILTIN_LD_ELEMREV_V8HI);
16837 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid,
16838 VSX_BUILTIN_LD_ELEMREV_V16QI);
16839 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid,
16840 VSX_BUILTIN_ST_ELEMREV_V2DF);
16841 def_builtin ("__builtin_vsx_st_elemrev_v1ti", void_ftype_v1ti_long_pvoid,
16842 VSX_BUILTIN_ST_ELEMREV_V1TI);
16843 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid,
16844 VSX_BUILTIN_ST_ELEMREV_V2DI);
16845 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid,
16846 VSX_BUILTIN_ST_ELEMREV_V4SF);
16847 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid,
16848 VSX_BUILTIN_ST_ELEMREV_V4SI);
16849 def_builtin ("__builtin_vsx_st_elemrev_v8hi", void_ftype_v8hi_long_pvoid,
16850 VSX_BUILTIN_ST_ELEMREV_V8HI);
16851 def_builtin ("__builtin_vsx_st_elemrev_v16qi", void_ftype_v16qi_long_pvoid,
16852 VSX_BUILTIN_ST_ELEMREV_V16QI);
16854 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
16855 VSX_BUILTIN_VEC_LD);
16856 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
16857 VSX_BUILTIN_VEC_ST);
16858 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid,
16859 VSX_BUILTIN_VEC_XL);
16860 def_builtin ("__builtin_vec_xl_be", opaque_ftype_long_pcvoid,
16861 VSX_BUILTIN_VEC_XL_BE);
16862 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid,
16863 VSX_BUILTIN_VEC_XST);
16864 def_builtin ("__builtin_vec_xst_be", void_ftype_opaque_long_pvoid,
16865 VSX_BUILTIN_VEC_XST_BE);
16867 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
16868 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
16869 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
16871 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
16872 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
16873 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
16874 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
16875 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
16876 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
16877 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
16878 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
16879 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
16880 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
16881 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
16882 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
16884 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque,
16885 ALTIVEC_BUILTIN_VEC_ADDE);
16886 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque,
16887 ALTIVEC_BUILTIN_VEC_ADDEC);
16888 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque,
16889 ALTIVEC_BUILTIN_VEC_CMPNE);
16890 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque,
16891 ALTIVEC_BUILTIN_VEC_MUL);
16892 def_builtin ("__builtin_vec_sube", opaque_ftype_opaque_opaque_opaque,
16893 ALTIVEC_BUILTIN_VEC_SUBE);
16894 def_builtin ("__builtin_vec_subec", opaque_ftype_opaque_opaque_opaque,
16895 ALTIVEC_BUILTIN_VEC_SUBEC);
16897 /* Cell builtins. */
16898 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
16899 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
16900 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
16901 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
16903 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
16904 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
16905 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
16906 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
16908 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
16909 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
16910 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
16911 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
16913 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
16914 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
16915 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
16916 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
16918 if (TARGET_P9_VECTOR)
16920 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
16921 P9V_BUILTIN_STXVL);
16922 def_builtin ("__builtin_xst_len_r", void_ftype_v16qi_pvoid_long,
16923 P9V_BUILTIN_XST_LEN_R);
16926 /* Add the DST variants. */
16928 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
16930 HOST_WIDE_INT mask = d->mask;
16932 /* It is expected that these dst built-in functions may have
16933 d->icode equal to CODE_FOR_nothing. */
16934 if ((mask & builtin_mask) != mask)
16936 if (TARGET_DEBUG_BUILTIN)
16937 fprintf (stderr, "altivec_init_builtins, skip dst %s\n",
16941 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
16944 /* Initialize the predicates. */
16945 d = bdesc_altivec_preds;
16946 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
16948 machine_mode mode1;
16950 HOST_WIDE_INT mask = d->mask;
16952 if ((mask & builtin_mask) != mask)
16954 if (TARGET_DEBUG_BUILTIN)
16955 fprintf (stderr, "altivec_init_builtins, skip predicate %s\n",
16960 if (rs6000_overloaded_builtin_p (d->code))
16964 /* Cannot define builtin if the instruction is disabled. */
16965 gcc_assert (d->icode != CODE_FOR_nothing);
16966 mode1 = insn_data[d->icode].operand[1].mode;
16972 type = int_ftype_int_opaque_opaque;
16975 type = int_ftype_int_v2di_v2di;
16978 type = int_ftype_int_v4si_v4si;
16981 type = int_ftype_int_v8hi_v8hi;
16984 type = int_ftype_int_v16qi_v16qi;
16987 type = int_ftype_int_v4sf_v4sf;
16990 type = int_ftype_int_v2df_v2df;
16993 gcc_unreachable ();
16996 def_builtin (d->name, type, d->code);
16999 /* Initialize the abs* operators. */
17001 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
17003 machine_mode mode0;
17005 HOST_WIDE_INT mask = d->mask;
17007 if ((mask & builtin_mask) != mask)
17009 if (TARGET_DEBUG_BUILTIN)
17010 fprintf (stderr, "altivec_init_builtins, skip abs %s\n",
17015 /* Cannot define builtin if the instruction is disabled. */
17016 gcc_assert (d->icode != CODE_FOR_nothing);
17017 mode0 = insn_data[d->icode].operand[0].mode;
17022 type = v2di_ftype_v2di;
17025 type = v4si_ftype_v4si;
17028 type = v8hi_ftype_v8hi;
17031 type = v16qi_ftype_v16qi;
17034 type = v4sf_ftype_v4sf;
17037 type = v2df_ftype_v2df;
17040 gcc_unreachable ();
17043 def_builtin (d->name, type, d->code);
17046 /* Initialize target builtin that implements
17047 targetm.vectorize.builtin_mask_for_load. */
17049 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
17050 v16qi_ftype_long_pcvoid,
17051 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
17052 BUILT_IN_MD, NULL, NULL_TREE);
17053 TREE_READONLY (decl) = 1;
17054 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17055 altivec_builtin_mask_for_load = decl;
17057 /* Access to the vec_init patterns. */
17058 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
17059 integer_type_node, integer_type_node,
17060 integer_type_node, NULL_TREE);
17061 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
17063 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
17064 short_integer_type_node,
17065 short_integer_type_node,
17066 short_integer_type_node,
17067 short_integer_type_node,
17068 short_integer_type_node,
17069 short_integer_type_node,
17070 short_integer_type_node, NULL_TREE);
17071 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
17073 ftype = build_function_type_list (V16QI_type_node, char_type_node,
17074 char_type_node, char_type_node,
17075 char_type_node, char_type_node,
17076 char_type_node, char_type_node,
17077 char_type_node, char_type_node,
17078 char_type_node, char_type_node,
17079 char_type_node, char_type_node,
17080 char_type_node, char_type_node,
17081 char_type_node, NULL_TREE);
17082 def_builtin ("__builtin_vec_init_v16qi", ftype,
17083 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
17085 ftype = build_function_type_list (V4SF_type_node, float_type_node,
17086 float_type_node, float_type_node,
17087 float_type_node, NULL_TREE);
17088 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
17090 /* VSX builtins. */
17091 ftype = build_function_type_list (V2DF_type_node, double_type_node,
17092 double_type_node, NULL_TREE);
17093 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
17095 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
17096 intDI_type_node, NULL_TREE);
17097 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
17099 /* Access to the vec_set patterns. */
17100 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
17102 integer_type_node, NULL_TREE);
17103 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
17105 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
17107 integer_type_node, NULL_TREE);
17108 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
17110 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
17112 integer_type_node, NULL_TREE);
17113 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
17115 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
17117 integer_type_node, NULL_TREE);
17118 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
17120 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
17122 integer_type_node, NULL_TREE);
17123 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
17125 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
17127 integer_type_node, NULL_TREE);
17128 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
17130 /* Access to the vec_extract patterns. */
17131 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
17132 integer_type_node, NULL_TREE);
17133 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
17135 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
17136 integer_type_node, NULL_TREE);
17137 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
17139 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
17140 integer_type_node, NULL_TREE);
17141 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
17143 ftype = build_function_type_list (float_type_node, V4SF_type_node,
17144 integer_type_node, NULL_TREE);
17145 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
17147 ftype = build_function_type_list (double_type_node, V2DF_type_node,
17148 integer_type_node, NULL_TREE);
17149 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
17151 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
17152 integer_type_node, NULL_TREE);
17153 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
17156 if (V1TI_type_node)
17158 tree v1ti_ftype_long_pcvoid
17159 = build_function_type_list (V1TI_type_node,
17160 long_integer_type_node, pcvoid_type_node,
17162 tree void_ftype_v1ti_long_pvoid
17163 = build_function_type_list (void_type_node,
17164 V1TI_type_node, long_integer_type_node,
17165 pvoid_type_node, NULL_TREE);
17166 def_builtin ("__builtin_vsx_ld_elemrev_v1ti", v1ti_ftype_long_pcvoid,
17167 VSX_BUILTIN_LD_ELEMREV_V1TI);
17168 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
17169 VSX_BUILTIN_LXVD2X_V1TI);
17170 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
17171 VSX_BUILTIN_STXVD2X_V1TI);
17172 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
17173 NULL_TREE, NULL_TREE);
17174 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
17175 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
17177 integer_type_node, NULL_TREE);
17178 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
17179 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
17180 integer_type_node, NULL_TREE);
17181 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
17187 htm_init_builtins (void)
17189 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17190 const struct builtin_description *d;
17194 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
17196 tree op[MAX_HTM_OPERANDS], type;
17197 HOST_WIDE_INT mask = d->mask;
17198 unsigned attr = rs6000_builtin_info[d->code].attr;
17199 bool void_func = (attr & RS6000_BTC_VOID);
17200 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
17202 tree gpr_type_node;
17206 /* It is expected that these htm built-in functions may have
17207 d->icode equal to CODE_FOR_nothing. */
17209 if (TARGET_32BIT && TARGET_POWERPC64)
17210 gpr_type_node = long_long_unsigned_type_node;
17212 gpr_type_node = long_unsigned_type_node;
17214 if (attr & RS6000_BTC_SPR)
17216 rettype = gpr_type_node;
17217 argtype = gpr_type_node;
17219 else if (d->code == HTM_BUILTIN_TABORTDC
17220 || d->code == HTM_BUILTIN_TABORTDCI)
17222 rettype = unsigned_type_node;
17223 argtype = gpr_type_node;
17227 rettype = unsigned_type_node;
17228 argtype = unsigned_type_node;
17231 if ((mask & builtin_mask) != mask)
17233 if (TARGET_DEBUG_BUILTIN)
17234 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
17240 if (TARGET_DEBUG_BUILTIN)
17241 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
17242 (long unsigned) i);
17246 op[nopnds++] = (void_func) ? void_type_node : rettype;
17248 if (attr_args == RS6000_BTC_UNARY)
17249 op[nopnds++] = argtype;
17250 else if (attr_args == RS6000_BTC_BINARY)
17252 op[nopnds++] = argtype;
17253 op[nopnds++] = argtype;
17255 else if (attr_args == RS6000_BTC_TERNARY)
17257 op[nopnds++] = argtype;
17258 op[nopnds++] = argtype;
17259 op[nopnds++] = argtype;
17265 type = build_function_type_list (op[0], NULL_TREE);
17268 type = build_function_type_list (op[0], op[1], NULL_TREE);
17271 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
17274 type = build_function_type_list (op[0], op[1], op[2], op[3],
17278 gcc_unreachable ();
17281 def_builtin (d->name, type, d->code);
17285 /* Hash function for builtin functions with up to 3 arguments and a return
17288 builtin_hasher::hash (builtin_hash_struct *bh)
17293 for (i = 0; i < 4; i++)
17295 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
17296 ret = (ret * 2) + bh->uns_p[i];
17302 /* Compare builtin hash entries H1 and H2 for equivalence. */
17304 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
17306 return ((p1->mode[0] == p2->mode[0])
17307 && (p1->mode[1] == p2->mode[1])
17308 && (p1->mode[2] == p2->mode[2])
17309 && (p1->mode[3] == p2->mode[3])
17310 && (p1->uns_p[0] == p2->uns_p[0])
17311 && (p1->uns_p[1] == p2->uns_p[1])
17312 && (p1->uns_p[2] == p2->uns_p[2])
17313 && (p1->uns_p[3] == p2->uns_p[3]));
17316 /* Map types for builtin functions with an explicit return type and up to 3
17317 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
17318 of the argument. */
17320 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
17321 machine_mode mode_arg1, machine_mode mode_arg2,
17322 enum rs6000_builtins builtin, const char *name)
17324 struct builtin_hash_struct h;
17325 struct builtin_hash_struct *h2;
17328 tree ret_type = NULL_TREE;
17329 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
17331 /* Create builtin_hash_table. */
17332 if (builtin_hash_table == NULL)
17333 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
17335 h.type = NULL_TREE;
17336 h.mode[0] = mode_ret;
17337 h.mode[1] = mode_arg0;
17338 h.mode[2] = mode_arg1;
17339 h.mode[3] = mode_arg2;
17345 /* If the builtin is a type that produces unsigned results or takes unsigned
17346 arguments, and it is returned as a decl for the vectorizer (such as
17347 widening multiplies, permute), make sure the arguments and return value
17348 are type correct. */
17351 /* unsigned 1 argument functions. */
17352 case CRYPTO_BUILTIN_VSBOX:
17353 case CRYPTO_BUILTIN_VSBOX_BE:
17354 case P8V_BUILTIN_VGBBD:
17355 case MISC_BUILTIN_CDTBCD:
17356 case MISC_BUILTIN_CBCDTD:
17361 /* unsigned 2 argument functions. */
17362 case ALTIVEC_BUILTIN_VMULEUB:
17363 case ALTIVEC_BUILTIN_VMULEUH:
17364 case P8V_BUILTIN_VMULEUW:
17365 case ALTIVEC_BUILTIN_VMULOUB:
17366 case ALTIVEC_BUILTIN_VMULOUH:
17367 case P8V_BUILTIN_VMULOUW:
17368 case CRYPTO_BUILTIN_VCIPHER:
17369 case CRYPTO_BUILTIN_VCIPHER_BE:
17370 case CRYPTO_BUILTIN_VCIPHERLAST:
17371 case CRYPTO_BUILTIN_VCIPHERLAST_BE:
17372 case CRYPTO_BUILTIN_VNCIPHER:
17373 case CRYPTO_BUILTIN_VNCIPHER_BE:
17374 case CRYPTO_BUILTIN_VNCIPHERLAST:
17375 case CRYPTO_BUILTIN_VNCIPHERLAST_BE:
17376 case CRYPTO_BUILTIN_VPMSUMB:
17377 case CRYPTO_BUILTIN_VPMSUMH:
17378 case CRYPTO_BUILTIN_VPMSUMW:
17379 case CRYPTO_BUILTIN_VPMSUMD:
17380 case CRYPTO_BUILTIN_VPMSUM:
17381 case MISC_BUILTIN_ADDG6S:
17382 case MISC_BUILTIN_DIVWEU:
17383 case MISC_BUILTIN_DIVDEU:
17384 case VSX_BUILTIN_UDIV_V2DI:
17385 case ALTIVEC_BUILTIN_VMAXUB:
17386 case ALTIVEC_BUILTIN_VMINUB:
17387 case ALTIVEC_BUILTIN_VMAXUH:
17388 case ALTIVEC_BUILTIN_VMINUH:
17389 case ALTIVEC_BUILTIN_VMAXUW:
17390 case ALTIVEC_BUILTIN_VMINUW:
17391 case P8V_BUILTIN_VMAXUD:
17392 case P8V_BUILTIN_VMINUD:
17398 /* unsigned 3 argument functions. */
17399 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
17400 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
17401 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
17402 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
17403 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
17404 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
17405 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
17406 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
17407 case VSX_BUILTIN_VPERM_16QI_UNS:
17408 case VSX_BUILTIN_VPERM_8HI_UNS:
17409 case VSX_BUILTIN_VPERM_4SI_UNS:
17410 case VSX_BUILTIN_VPERM_2DI_UNS:
17411 case VSX_BUILTIN_XXSEL_16QI_UNS:
17412 case VSX_BUILTIN_XXSEL_8HI_UNS:
17413 case VSX_BUILTIN_XXSEL_4SI_UNS:
17414 case VSX_BUILTIN_XXSEL_2DI_UNS:
17415 case CRYPTO_BUILTIN_VPERMXOR:
17416 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
17417 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
17418 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
17419 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
17420 case CRYPTO_BUILTIN_VSHASIGMAW:
17421 case CRYPTO_BUILTIN_VSHASIGMAD:
17422 case CRYPTO_BUILTIN_VSHASIGMA:
17429 /* signed permute functions with unsigned char mask. */
17430 case ALTIVEC_BUILTIN_VPERM_16QI:
17431 case ALTIVEC_BUILTIN_VPERM_8HI:
17432 case ALTIVEC_BUILTIN_VPERM_4SI:
17433 case ALTIVEC_BUILTIN_VPERM_4SF:
17434 case ALTIVEC_BUILTIN_VPERM_2DI:
17435 case ALTIVEC_BUILTIN_VPERM_2DF:
17436 case VSX_BUILTIN_VPERM_16QI:
17437 case VSX_BUILTIN_VPERM_8HI:
17438 case VSX_BUILTIN_VPERM_4SI:
17439 case VSX_BUILTIN_VPERM_4SF:
17440 case VSX_BUILTIN_VPERM_2DI:
17441 case VSX_BUILTIN_VPERM_2DF:
17445 /* unsigned args, signed return. */
17446 case VSX_BUILTIN_XVCVUXDSP:
17447 case VSX_BUILTIN_XVCVUXDDP_UNS:
17448 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
17452 /* signed args, unsigned return. */
17453 case VSX_BUILTIN_XVCVDPUXDS_UNS:
17454 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
17455 case MISC_BUILTIN_UNPACK_TD:
17456 case MISC_BUILTIN_UNPACK_V1TI:
17460 /* unsigned arguments, bool return (compares). */
17461 case ALTIVEC_BUILTIN_VCMPEQUB:
17462 case ALTIVEC_BUILTIN_VCMPEQUH:
17463 case ALTIVEC_BUILTIN_VCMPEQUW:
17464 case P8V_BUILTIN_VCMPEQUD:
17465 case VSX_BUILTIN_CMPGE_U16QI:
17466 case VSX_BUILTIN_CMPGE_U8HI:
17467 case VSX_BUILTIN_CMPGE_U4SI:
17468 case VSX_BUILTIN_CMPGE_U2DI:
17469 case ALTIVEC_BUILTIN_VCMPGTUB:
17470 case ALTIVEC_BUILTIN_VCMPGTUH:
17471 case ALTIVEC_BUILTIN_VCMPGTUW:
17472 case P8V_BUILTIN_VCMPGTUD:
17477 /* unsigned arguments for 128-bit pack instructions. */
17478 case MISC_BUILTIN_PACK_TD:
17479 case MISC_BUILTIN_PACK_V1TI:
17484 /* unsigned second arguments (vector shift right). */
17485 case ALTIVEC_BUILTIN_VSRB:
17486 case ALTIVEC_BUILTIN_VSRH:
17487 case ALTIVEC_BUILTIN_VSRW:
17488 case P8V_BUILTIN_VSRD:
17496 /* Figure out how many args are present. */
17497 while (num_args > 0 && h.mode[num_args] == VOIDmode)
17500 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
17501 if (!ret_type && h.uns_p[0])
17502 ret_type = builtin_mode_to_type[h.mode[0]][0];
17505 fatal_error (input_location,
17506 "internal error: builtin function %qs had an unexpected "
17507 "return type %qs", name, GET_MODE_NAME (h.mode[0]));
17509 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
17510 arg_type[i] = NULL_TREE;
17512 for (i = 0; i < num_args; i++)
17514 int m = (int) h.mode[i+1];
17515 int uns_p = h.uns_p[i+1];
17517 arg_type[i] = builtin_mode_to_type[m][uns_p];
17518 if (!arg_type[i] && uns_p)
17519 arg_type[i] = builtin_mode_to_type[m][0];
17522 fatal_error (input_location,
17523 "internal error: builtin function %qs, argument %d "
17524 "had unexpected argument type %qs", name, i,
17525 GET_MODE_NAME (m));
17528 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
17529 if (*found == NULL)
17531 h2 = ggc_alloc<builtin_hash_struct> ();
17535 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
17536 arg_type[2], NULL_TREE);
17539 return (*found)->type;
17543 rs6000_common_init_builtins (void)
17545 const struct builtin_description *d;
17548 tree opaque_ftype_opaque = NULL_TREE;
17549 tree opaque_ftype_opaque_opaque = NULL_TREE;
17550 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
17551 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
17553 /* Create Altivec and VSX builtins on machines with at least the
17554 general purpose extensions (970 and newer) to allow the use of
17555 the target attribute. */
17557 if (TARGET_EXTRA_BUILTINS)
17558 builtin_mask |= RS6000_BTM_COMMON;
17560 /* Add the ternary operators. */
17562 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
17565 HOST_WIDE_INT mask = d->mask;
17567 if ((mask & builtin_mask) != mask)
17569 if (TARGET_DEBUG_BUILTIN)
17570 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
17574 if (rs6000_overloaded_builtin_p (d->code))
17576 if (! (type = opaque_ftype_opaque_opaque_opaque))
17577 type = opaque_ftype_opaque_opaque_opaque
17578 = build_function_type_list (opaque_V4SI_type_node,
17579 opaque_V4SI_type_node,
17580 opaque_V4SI_type_node,
17581 opaque_V4SI_type_node,
17586 enum insn_code icode = d->icode;
17589 if (TARGET_DEBUG_BUILTIN)
17590 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
17596 if (icode == CODE_FOR_nothing)
17598 if (TARGET_DEBUG_BUILTIN)
17599 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
17605 type = builtin_function_type (insn_data[icode].operand[0].mode,
17606 insn_data[icode].operand[1].mode,
17607 insn_data[icode].operand[2].mode,
17608 insn_data[icode].operand[3].mode,
17612 def_builtin (d->name, type, d->code);
17615 /* Add the binary operators. */
17617 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
17619 machine_mode mode0, mode1, mode2;
17621 HOST_WIDE_INT mask = d->mask;
17623 if ((mask & builtin_mask) != mask)
17625 if (TARGET_DEBUG_BUILTIN)
17626 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
17630 if (rs6000_overloaded_builtin_p (d->code))
17632 if (! (type = opaque_ftype_opaque_opaque))
17633 type = opaque_ftype_opaque_opaque
17634 = build_function_type_list (opaque_V4SI_type_node,
17635 opaque_V4SI_type_node,
17636 opaque_V4SI_type_node,
17641 enum insn_code icode = d->icode;
17644 if (TARGET_DEBUG_BUILTIN)
17645 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
17651 if (icode == CODE_FOR_nothing)
17653 if (TARGET_DEBUG_BUILTIN)
17654 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
17660 mode0 = insn_data[icode].operand[0].mode;
17661 mode1 = insn_data[icode].operand[1].mode;
17662 mode2 = insn_data[icode].operand[2].mode;
17664 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
17668 def_builtin (d->name, type, d->code);
17671 /* Add the simple unary operators. */
17673 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
17675 machine_mode mode0, mode1;
17677 HOST_WIDE_INT mask = d->mask;
17679 if ((mask & builtin_mask) != mask)
17681 if (TARGET_DEBUG_BUILTIN)
17682 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
17686 if (rs6000_overloaded_builtin_p (d->code))
17688 if (! (type = opaque_ftype_opaque))
17689 type = opaque_ftype_opaque
17690 = build_function_type_list (opaque_V4SI_type_node,
17691 opaque_V4SI_type_node,
17696 enum insn_code icode = d->icode;
17699 if (TARGET_DEBUG_BUILTIN)
17700 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
17706 if (icode == CODE_FOR_nothing)
17708 if (TARGET_DEBUG_BUILTIN)
17709 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
17715 mode0 = insn_data[icode].operand[0].mode;
17716 mode1 = insn_data[icode].operand[1].mode;
17718 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
17722 def_builtin (d->name, type, d->code);
17725 /* Add the simple no-argument operators. */
17727 for (i = 0; i < ARRAY_SIZE (bdesc_0arg); i++, d++)
17729 machine_mode mode0;
17731 HOST_WIDE_INT mask = d->mask;
17733 if ((mask & builtin_mask) != mask)
17735 if (TARGET_DEBUG_BUILTIN)
17736 fprintf (stderr, "rs6000_builtin, skip no-argument %s\n", d->name);
17739 if (rs6000_overloaded_builtin_p (d->code))
17741 if (!opaque_ftype_opaque)
17742 opaque_ftype_opaque
17743 = build_function_type_list (opaque_V4SI_type_node, NULL_TREE);
17744 type = opaque_ftype_opaque;
17748 enum insn_code icode = d->icode;
17751 if (TARGET_DEBUG_BUILTIN)
17752 fprintf (stderr, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
17753 (long unsigned) i);
17756 if (icode == CODE_FOR_nothing)
17758 if (TARGET_DEBUG_BUILTIN)
17760 "rs6000_builtin, skip no-argument %s (no code)\n",
17764 mode0 = insn_data[icode].operand[0].mode;
17765 type = builtin_function_type (mode0, VOIDmode, VOIDmode, VOIDmode,
17768 def_builtin (d->name, type, d->code);
17772 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
17774 init_float128_ibm (machine_mode mode)
17776 if (!TARGET_XL_COMPAT)
17778 set_optab_libfunc (add_optab, mode, "__gcc_qadd");
17779 set_optab_libfunc (sub_optab, mode, "__gcc_qsub");
17780 set_optab_libfunc (smul_optab, mode, "__gcc_qmul");
17781 set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv");
17783 if (!TARGET_HARD_FLOAT)
17785 set_optab_libfunc (neg_optab, mode, "__gcc_qneg");
17786 set_optab_libfunc (eq_optab, mode, "__gcc_qeq");
17787 set_optab_libfunc (ne_optab, mode, "__gcc_qne");
17788 set_optab_libfunc (gt_optab, mode, "__gcc_qgt");
17789 set_optab_libfunc (ge_optab, mode, "__gcc_qge");
17790 set_optab_libfunc (lt_optab, mode, "__gcc_qlt");
17791 set_optab_libfunc (le_optab, mode, "__gcc_qle");
17792 set_optab_libfunc (unord_optab, mode, "__gcc_qunord");
17794 set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq");
17795 set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq");
17796 set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos");
17797 set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod");
17798 set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi");
17799 set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou");
17800 set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq");
17801 set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq");
17806 set_optab_libfunc (add_optab, mode, "_xlqadd");
17807 set_optab_libfunc (sub_optab, mode, "_xlqsub");
17808 set_optab_libfunc (smul_optab, mode, "_xlqmul");
17809 set_optab_libfunc (sdiv_optab, mode, "_xlqdiv");
17812 /* Add various conversions for IFmode to use the traditional TFmode
17814 if (mode == IFmode)
17816 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdtf");
17817 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddtf");
17818 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdtf");
17819 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunctfsd");
17820 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunctfdd");
17821 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendtftd");
17823 if (TARGET_POWERPC64)
17825 set_conv_libfunc (sfix_optab, TImode, mode, "__fixtfti");
17826 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunstfti");
17827 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattitf");
17828 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntitf");
17833 /* Create a decl for either complex long double multiply or complex long double
17834 divide when long double is IEEE 128-bit floating point. We can't use
17835 __multc3 and __divtc3 because the original long double using IBM extended
17836 double used those names. The complex multiply/divide functions are encoded
17837 as builtin functions with a complex result and 4 scalar inputs. */
17840 create_complex_muldiv (const char *name, built_in_function fncode, tree fntype)
17842 tree fndecl = add_builtin_function (name, fntype, fncode, BUILT_IN_NORMAL,
17845 set_builtin_decl (fncode, fndecl, true);
17847 if (TARGET_DEBUG_BUILTIN)
17848 fprintf (stderr, "create complex %s, fncode: %d\n", name, (int) fncode);
17853 /* Set up IEEE 128-bit floating point routines. Use different names if the
17854 arguments can be passed in a vector register. The historical PowerPC
17855 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
17856 continue to use that if we aren't using vector registers to pass IEEE
17857 128-bit floating point. */
17860 init_float128_ieee (machine_mode mode)
17862 if (FLOAT128_VECTOR_P (mode))
17864 static bool complex_muldiv_init_p = false;
17866 /* Set up to call __mulkc3 and __divkc3 under -mabi=ieeelongdouble. If
17867 we have clone or target attributes, this will be called a second
17868 time. We want to create the built-in function only once. */
17869 if (mode == TFmode && TARGET_IEEEQUAD && !complex_muldiv_init_p)
17871 complex_muldiv_init_p = true;
17872 built_in_function fncode_mul =
17873 (built_in_function) (BUILT_IN_COMPLEX_MUL_MIN + TCmode
17874 - MIN_MODE_COMPLEX_FLOAT);
17875 built_in_function fncode_div =
17876 (built_in_function) (BUILT_IN_COMPLEX_DIV_MIN + TCmode
17877 - MIN_MODE_COMPLEX_FLOAT);
17879 tree fntype = build_function_type_list (complex_long_double_type_node,
17880 long_double_type_node,
17881 long_double_type_node,
17882 long_double_type_node,
17883 long_double_type_node,
17886 create_complex_muldiv ("__mulkc3", fncode_mul, fntype);
17887 create_complex_muldiv ("__divkc3", fncode_div, fntype);
17890 set_optab_libfunc (add_optab, mode, "__addkf3");
17891 set_optab_libfunc (sub_optab, mode, "__subkf3");
17892 set_optab_libfunc (neg_optab, mode, "__negkf2");
17893 set_optab_libfunc (smul_optab, mode, "__mulkf3");
17894 set_optab_libfunc (sdiv_optab, mode, "__divkf3");
17895 set_optab_libfunc (sqrt_optab, mode, "__sqrtkf2");
17896 set_optab_libfunc (abs_optab, mode, "__abskf2");
17897 set_optab_libfunc (powi_optab, mode, "__powikf2");
17899 set_optab_libfunc (eq_optab, mode, "__eqkf2");
17900 set_optab_libfunc (ne_optab, mode, "__nekf2");
17901 set_optab_libfunc (gt_optab, mode, "__gtkf2");
17902 set_optab_libfunc (ge_optab, mode, "__gekf2");
17903 set_optab_libfunc (lt_optab, mode, "__ltkf2");
17904 set_optab_libfunc (le_optab, mode, "__lekf2");
17905 set_optab_libfunc (unord_optab, mode, "__unordkf2");
17907 set_conv_libfunc (sext_optab, mode, SFmode, "__extendsfkf2");
17908 set_conv_libfunc (sext_optab, mode, DFmode, "__extenddfkf2");
17909 set_conv_libfunc (trunc_optab, SFmode, mode, "__trunckfsf2");
17910 set_conv_libfunc (trunc_optab, DFmode, mode, "__trunckfdf2");
17912 set_conv_libfunc (sext_optab, mode, IFmode, "__trunctfkf2");
17913 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17914 set_conv_libfunc (sext_optab, mode, TFmode, "__trunctfkf2");
17916 set_conv_libfunc (trunc_optab, IFmode, mode, "__extendkftf2");
17917 if (mode != TFmode && FLOAT128_IBM_P (TFmode))
17918 set_conv_libfunc (trunc_optab, TFmode, mode, "__extendkftf2");
17920 set_conv_libfunc (sext_optab, mode, SDmode, "__dpd_extendsdkf");
17921 set_conv_libfunc (sext_optab, mode, DDmode, "__dpd_extendddkf");
17922 set_conv_libfunc (trunc_optab, mode, TDmode, "__dpd_trunctdkf");
17923 set_conv_libfunc (trunc_optab, SDmode, mode, "__dpd_trunckfsd");
17924 set_conv_libfunc (trunc_optab, DDmode, mode, "__dpd_trunckfdd");
17925 set_conv_libfunc (sext_optab, TDmode, mode, "__dpd_extendkftd");
17927 set_conv_libfunc (sfix_optab, SImode, mode, "__fixkfsi");
17928 set_conv_libfunc (ufix_optab, SImode, mode, "__fixunskfsi");
17929 set_conv_libfunc (sfix_optab, DImode, mode, "__fixkfdi");
17930 set_conv_libfunc (ufix_optab, DImode, mode, "__fixunskfdi");
17932 set_conv_libfunc (sfloat_optab, mode, SImode, "__floatsikf");
17933 set_conv_libfunc (ufloat_optab, mode, SImode, "__floatunsikf");
17934 set_conv_libfunc (sfloat_optab, mode, DImode, "__floatdikf");
17935 set_conv_libfunc (ufloat_optab, mode, DImode, "__floatundikf");
17937 if (TARGET_POWERPC64)
17939 set_conv_libfunc (sfix_optab, TImode, mode, "__fixkfti");
17940 set_conv_libfunc (ufix_optab, TImode, mode, "__fixunskfti");
17941 set_conv_libfunc (sfloat_optab, mode, TImode, "__floattikf");
17942 set_conv_libfunc (ufloat_optab, mode, TImode, "__floatuntikf");
17948 set_optab_libfunc (add_optab, mode, "_q_add");
17949 set_optab_libfunc (sub_optab, mode, "_q_sub");
17950 set_optab_libfunc (neg_optab, mode, "_q_neg");
17951 set_optab_libfunc (smul_optab, mode, "_q_mul");
17952 set_optab_libfunc (sdiv_optab, mode, "_q_div");
17953 if (TARGET_PPC_GPOPT)
17954 set_optab_libfunc (sqrt_optab, mode, "_q_sqrt");
17956 set_optab_libfunc (eq_optab, mode, "_q_feq");
17957 set_optab_libfunc (ne_optab, mode, "_q_fne");
17958 set_optab_libfunc (gt_optab, mode, "_q_fgt");
17959 set_optab_libfunc (ge_optab, mode, "_q_fge");
17960 set_optab_libfunc (lt_optab, mode, "_q_flt");
17961 set_optab_libfunc (le_optab, mode, "_q_fle");
17963 set_conv_libfunc (sext_optab, mode, SFmode, "_q_stoq");
17964 set_conv_libfunc (sext_optab, mode, DFmode, "_q_dtoq");
17965 set_conv_libfunc (trunc_optab, SFmode, mode, "_q_qtos");
17966 set_conv_libfunc (trunc_optab, DFmode, mode, "_q_qtod");
17967 set_conv_libfunc (sfix_optab, SImode, mode, "_q_qtoi");
17968 set_conv_libfunc (ufix_optab, SImode, mode, "_q_qtou");
17969 set_conv_libfunc (sfloat_optab, mode, SImode, "_q_itoq");
17970 set_conv_libfunc (ufloat_optab, mode, SImode, "_q_utoq");
17975 rs6000_init_libfuncs (void)
17977 /* __float128 support. */
17978 if (TARGET_FLOAT128_TYPE)
17980 init_float128_ibm (IFmode);
17981 init_float128_ieee (KFmode);
17984 /* AIX/Darwin/64-bit Linux quad floating point routines. */
17985 if (TARGET_LONG_DOUBLE_128)
17987 if (!TARGET_IEEEQUAD)
17988 init_float128_ibm (TFmode);
17990 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
17992 init_float128_ieee (TFmode);
17996 /* Emit a potentially record-form instruction, setting DST from SRC.
17997 If DOT is 0, that is all; otherwise, set CCREG to the result of the
17998 signed comparison of DST with zero. If DOT is 1, the generated RTL
17999 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18000 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18001 a separate COMPARE. */
18004 rs6000_emit_dot_insn (rtx dst, rtx src, int dot, rtx ccreg)
18008 emit_move_insn (dst, src);
18012 if (cc_reg_not_cr0_operand (ccreg, CCmode))
18014 emit_move_insn (dst, src);
18015 emit_move_insn (ccreg, gen_rtx_COMPARE (CCmode, dst, const0_rtx));
18019 rtx ccset = gen_rtx_SET (ccreg, gen_rtx_COMPARE (CCmode, src, const0_rtx));
18022 rtx clobber = gen_rtx_CLOBBER (VOIDmode, dst);
18023 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, clobber)));
18027 rtx set = gen_rtx_SET (dst, src);
18028 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, ccset, set)));
18033 /* A validation routine: say whether CODE, a condition code, and MODE
18034 match. The other alternatives either don't make sense or should
18035 never be generated. */
18038 validate_condition_mode (enum rtx_code code, machine_mode mode)
18040 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
18041 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
18042 && GET_MODE_CLASS (mode) == MODE_CC);
18044 /* These don't make sense. */
18045 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
18046 || mode != CCUNSmode);
18048 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
18049 || mode == CCUNSmode);
18051 gcc_assert (mode == CCFPmode
18052 || (code != ORDERED && code != UNORDERED
18053 && code != UNEQ && code != LTGT
18054 && code != UNGT && code != UNLT
18055 && code != UNGE && code != UNLE));
18057 /* These should never be generated except for
18058 flag_finite_math_only. */
18059 gcc_assert (mode != CCFPmode
18060 || flag_finite_math_only
18061 || (code != LE && code != GE
18062 && code != UNEQ && code != LTGT
18063 && code != UNGT && code != UNLT));
18065 /* These are invalid; the information is not there. */
18066 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
18070 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
18071 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
18072 not zero, store there the bit offset (counted from the right) where
18073 the single stretch of 1 bits begins; and similarly for B, the bit
18074 offset where it ends. */
18077 rs6000_is_valid_mask (rtx mask, int *b, int *e, machine_mode mode)
18079 unsigned HOST_WIDE_INT val = INTVAL (mask);
18080 unsigned HOST_WIDE_INT bit;
18082 int n = GET_MODE_PRECISION (mode);
18084 if (mode != DImode && mode != SImode)
18087 if (INTVAL (mask) >= 0)
18090 ne = exact_log2 (bit);
18091 nb = exact_log2 (val + bit);
18093 else if (val + 1 == 0)
18102 nb = exact_log2 (bit);
18103 ne = exact_log2 (val + bit);
18108 ne = exact_log2 (bit);
18109 if (val + bit == 0)
18117 if (nb < 0 || ne < 0 || nb >= n || ne >= n)
18128 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
18129 or rldicr instruction, to implement an AND with it in mode MODE. */
18132 rs6000_is_valid_and_mask (rtx mask, machine_mode mode)
18136 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18139 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
18141 if (mode == DImode)
18142 return (ne == 0 || nb == 63 || (nb < 32 && ne <= nb));
18144 /* For SImode, rlwinm can do everything. */
18145 if (mode == SImode)
18146 return (nb < 32 && ne < 32);
18151 /* Return the instruction template for an AND with mask in mode MODE, with
18152 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18155 rs6000_insn_for_and_mask (machine_mode mode, rtx *operands, bool dot)
18159 if (!rs6000_is_valid_mask (operands[2], &nb, &ne, mode))
18160 gcc_unreachable ();
18162 if (mode == DImode && ne == 0)
18164 operands[3] = GEN_INT (63 - nb);
18166 return "rldicl. %0,%1,0,%3";
18167 return "rldicl %0,%1,0,%3";
18170 if (mode == DImode && nb == 63)
18172 operands[3] = GEN_INT (63 - ne);
18174 return "rldicr. %0,%1,0,%3";
18175 return "rldicr %0,%1,0,%3";
18178 if (nb < 32 && ne < 32)
18180 operands[3] = GEN_INT (31 - nb);
18181 operands[4] = GEN_INT (31 - ne);
18183 return "rlwinm. %0,%1,0,%3,%4";
18184 return "rlwinm %0,%1,0,%3,%4";
18187 gcc_unreachable ();
18190 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
18191 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
18192 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
18195 rs6000_is_valid_shift_mask (rtx mask, rtx shift, machine_mode mode)
18199 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18202 int n = GET_MODE_PRECISION (mode);
18205 if (CONST_INT_P (XEXP (shift, 1)))
18207 sh = INTVAL (XEXP (shift, 1));
18208 if (sh < 0 || sh >= n)
18212 rtx_code code = GET_CODE (shift);
18214 /* Convert any shift by 0 to a rotate, to simplify below code. */
18218 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18219 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18221 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18227 /* DImode rotates need rld*. */
18228 if (mode == DImode && code == ROTATE)
18229 return (nb == 63 || ne == 0 || ne == sh);
18231 /* SImode rotates need rlw*. */
18232 if (mode == SImode && code == ROTATE)
18233 return (nb < 32 && ne < 32 && sh < 32);
18235 /* Wrap-around masks are only okay for rotates. */
18239 /* Variable shifts are only okay for rotates. */
18243 /* Don't allow ASHIFT if the mask is wrong for that. */
18244 if (code == ASHIFT && ne < sh)
18247 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
18248 if the mask is wrong for that. */
18249 if (nb < 32 && ne < 32 && sh < 32
18250 && !(code == LSHIFTRT && nb >= 32 - sh))
18253 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
18254 if the mask is wrong for that. */
18255 if (code == LSHIFTRT)
18257 if (nb == 63 || ne == 0 || ne == sh)
18258 return !(code == LSHIFTRT && nb >= sh);
18263 /* Return the instruction template for a shift with mask in mode MODE, with
18264 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18267 rs6000_insn_for_shift_mask (machine_mode mode, rtx *operands, bool dot)
18271 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18272 gcc_unreachable ();
18274 if (mode == DImode && ne == 0)
18276 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18277 operands[2] = GEN_INT (64 - INTVAL (operands[2]));
18278 operands[3] = GEN_INT (63 - nb);
18280 return "rld%I2cl. %0,%1,%2,%3";
18281 return "rld%I2cl %0,%1,%2,%3";
18284 if (mode == DImode && nb == 63)
18286 operands[3] = GEN_INT (63 - ne);
18288 return "rld%I2cr. %0,%1,%2,%3";
18289 return "rld%I2cr %0,%1,%2,%3";
18293 && GET_CODE (operands[4]) != LSHIFTRT
18294 && CONST_INT_P (operands[2])
18295 && ne == INTVAL (operands[2]))
18297 operands[3] = GEN_INT (63 - nb);
18299 return "rld%I2c. %0,%1,%2,%3";
18300 return "rld%I2c %0,%1,%2,%3";
18303 if (nb < 32 && ne < 32)
18305 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18306 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18307 operands[3] = GEN_INT (31 - nb);
18308 operands[4] = GEN_INT (31 - ne);
18309 /* This insn can also be a 64-bit rotate with mask that really makes
18310 it just a shift right (with mask); the %h below are to adjust for
18311 that situation (shift count is >= 32 in that case). */
18313 return "rlw%I2nm. %0,%1,%h2,%3,%4";
18314 return "rlw%I2nm %0,%1,%h2,%3,%4";
18317 gcc_unreachable ();
18320 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
18321 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
18322 ASHIFT, or LSHIFTRT) in mode MODE. */
18325 rs6000_is_valid_insert_mask (rtx mask, rtx shift, machine_mode mode)
18329 if (!rs6000_is_valid_mask (mask, &nb, &ne, mode))
18332 int n = GET_MODE_PRECISION (mode);
18334 int sh = INTVAL (XEXP (shift, 1));
18335 if (sh < 0 || sh >= n)
18338 rtx_code code = GET_CODE (shift);
18340 /* Convert any shift by 0 to a rotate, to simplify below code. */
18344 /* Convert rotate to simple shift if we can, to make analysis simpler. */
18345 if (code == ROTATE && sh >= 0 && nb >= ne && ne >= sh)
18347 if (code == ROTATE && sh >= 0 && nb >= ne && nb < sh)
18353 /* DImode rotates need rldimi. */
18354 if (mode == DImode && code == ROTATE)
18357 /* SImode rotates need rlwimi. */
18358 if (mode == SImode && code == ROTATE)
18359 return (nb < 32 && ne < 32 && sh < 32);
18361 /* Wrap-around masks are only okay for rotates. */
18365 /* Don't allow ASHIFT if the mask is wrong for that. */
18366 if (code == ASHIFT && ne < sh)
18369 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
18370 if the mask is wrong for that. */
18371 if (nb < 32 && ne < 32 && sh < 32
18372 && !(code == LSHIFTRT && nb >= 32 - sh))
18375 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
18376 if the mask is wrong for that. */
18377 if (code == LSHIFTRT)
18380 return !(code == LSHIFTRT && nb >= sh);
18385 /* Return the instruction template for an insert with mask in mode MODE, with
18386 operands OPERANDS. If DOT is true, make it a record-form instruction. */
18389 rs6000_insn_for_insert_mask (machine_mode mode, rtx *operands, bool dot)
18393 if (!rs6000_is_valid_mask (operands[3], &nb, &ne, mode))
18394 gcc_unreachable ();
18396 /* Prefer rldimi because rlwimi is cracked. */
18397 if (TARGET_POWERPC64
18398 && (!dot || mode == DImode)
18399 && GET_CODE (operands[4]) != LSHIFTRT
18400 && ne == INTVAL (operands[2]))
18402 operands[3] = GEN_INT (63 - nb);
18404 return "rldimi. %0,%1,%2,%3";
18405 return "rldimi %0,%1,%2,%3";
18408 if (nb < 32 && ne < 32)
18410 if (GET_CODE (operands[4]) == LSHIFTRT && INTVAL (operands[2]))
18411 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
18412 operands[3] = GEN_INT (31 - nb);
18413 operands[4] = GEN_INT (31 - ne);
18415 return "rlwimi. %0,%1,%2,%3,%4";
18416 return "rlwimi %0,%1,%2,%3,%4";
18419 gcc_unreachable ();
18422 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
18423 using two machine instructions. */
18426 rs6000_is_valid_2insn_and (rtx c, machine_mode mode)
18428 /* There are two kinds of AND we can handle with two insns:
18429 1) those we can do with two rl* insn;
18432 We do not handle that last case yet. */
18434 /* If there is just one stretch of ones, we can do it. */
18435 if (rs6000_is_valid_mask (c, NULL, NULL, mode))
18438 /* Otherwise, fill in the lowest "hole"; if we can do the result with
18439 one insn, we can do the whole thing with two. */
18440 unsigned HOST_WIDE_INT val = INTVAL (c);
18441 unsigned HOST_WIDE_INT bit1 = val & -val;
18442 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18443 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18444 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18445 return rs6000_is_valid_and_mask (GEN_INT (val + bit3 - bit2), mode);
18448 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
18449 If EXPAND is true, split rotate-and-mask instructions we generate to
18450 their constituent parts as well (this is used during expand); if DOT
18451 is 1, make the last insn a record-form instruction clobbering the
18452 destination GPR and setting the CC reg (from operands[3]); if 2, set
18453 that GPR as well as the CC reg. */
18456 rs6000_emit_2insn_and (machine_mode mode, rtx *operands, bool expand, int dot)
18458 gcc_assert (!(expand && dot));
18460 unsigned HOST_WIDE_INT val = INTVAL (operands[2]);
18462 /* If it is one stretch of ones, it is DImode; shift left, mask, then
18463 shift right. This generates better code than doing the masks without
18464 shifts, or shifting first right and then left. */
18466 if (rs6000_is_valid_mask (operands[2], &nb, &ne, mode) && nb >= ne)
18468 gcc_assert (mode == DImode);
18470 int shift = 63 - nb;
18473 rtx tmp1 = gen_reg_rtx (DImode);
18474 rtx tmp2 = gen_reg_rtx (DImode);
18475 emit_insn (gen_ashldi3 (tmp1, operands[1], GEN_INT (shift)));
18476 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (val << shift)));
18477 emit_insn (gen_lshrdi3 (operands[0], tmp2, GEN_INT (shift)));
18481 rtx tmp = gen_rtx_ASHIFT (mode, operands[1], GEN_INT (shift));
18482 tmp = gen_rtx_AND (mode, tmp, GEN_INT (val << shift));
18483 emit_move_insn (operands[0], tmp);
18484 tmp = gen_rtx_LSHIFTRT (mode, operands[0], GEN_INT (shift));
18485 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18490 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
18491 that does the rest. */
18492 unsigned HOST_WIDE_INT bit1 = val & -val;
18493 unsigned HOST_WIDE_INT bit2 = (val + bit1) & ~val;
18494 unsigned HOST_WIDE_INT val1 = (val + bit1) & val;
18495 unsigned HOST_WIDE_INT bit3 = val1 & -val1;
18497 unsigned HOST_WIDE_INT mask1 = -bit3 + bit2 - 1;
18498 unsigned HOST_WIDE_INT mask2 = val + bit3 - bit2;
18500 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2), mode));
18502 /* Two "no-rotate"-and-mask instructions, for SImode. */
18503 if (rs6000_is_valid_and_mask (GEN_INT (mask1), mode))
18505 gcc_assert (mode == SImode);
18507 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18508 rtx tmp = gen_rtx_AND (mode, operands[1], GEN_INT (mask1));
18509 emit_move_insn (reg, tmp);
18510 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18511 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18515 gcc_assert (mode == DImode);
18517 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
18518 insns; we have to do the first in SImode, because it wraps. */
18519 if (mask2 <= 0xffffffff
18520 && rs6000_is_valid_and_mask (GEN_INT (mask1), SImode))
18522 rtx reg = expand ? gen_reg_rtx (mode) : operands[0];
18523 rtx tmp = gen_rtx_AND (SImode, gen_lowpart (SImode, operands[1]),
18525 rtx reg_low = gen_lowpart (SImode, reg);
18526 emit_move_insn (reg_low, tmp);
18527 tmp = gen_rtx_AND (mode, reg, GEN_INT (mask2));
18528 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18532 /* Two rld* insns: rotate, clear the hole in the middle (which now is
18533 at the top end), rotate back and clear the other hole. */
18534 int right = exact_log2 (bit3);
18535 int left = 64 - right;
18537 /* Rotate the mask too. */
18538 mask1 = (mask1 >> right) | ((bit2 - 1) << left);
18542 rtx tmp1 = gen_reg_rtx (DImode);
18543 rtx tmp2 = gen_reg_rtx (DImode);
18544 rtx tmp3 = gen_reg_rtx (DImode);
18545 emit_insn (gen_rotldi3 (tmp1, operands[1], GEN_INT (left)));
18546 emit_insn (gen_anddi3 (tmp2, tmp1, GEN_INT (mask1)));
18547 emit_insn (gen_rotldi3 (tmp3, tmp2, GEN_INT (right)));
18548 emit_insn (gen_anddi3 (operands[0], tmp3, GEN_INT (mask2)));
18552 rtx tmp = gen_rtx_ROTATE (mode, operands[1], GEN_INT (left));
18553 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask1));
18554 emit_move_insn (operands[0], tmp);
18555 tmp = gen_rtx_ROTATE (mode, operands[0], GEN_INT (right));
18556 tmp = gen_rtx_AND (mode, tmp, GEN_INT (mask2));
18557 rs6000_emit_dot_insn (operands[0], tmp, dot, dot ? operands[3] : 0);
18561 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
18562 for lfq and stfq insns iff the registers are hard registers. */
18565 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
18567 /* We might have been passed a SUBREG. */
18568 if (!REG_P (reg1) || !REG_P (reg2))
18571 /* We might have been passed non floating point registers. */
18572 if (!FP_REGNO_P (REGNO (reg1))
18573 || !FP_REGNO_P (REGNO (reg2)))
18576 return (REGNO (reg1) == REGNO (reg2) - 1);
18579 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
18580 addr1 and addr2 must be in consecutive memory locations
18581 (addr2 == addr1 + 8). */
18584 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
18587 unsigned int reg1, reg2;
18588 int offset1, offset2;
18590 /* The mems cannot be volatile. */
18591 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
18594 addr1 = XEXP (mem1, 0);
18595 addr2 = XEXP (mem2, 0);
18597 /* Extract an offset (if used) from the first addr. */
18598 if (GET_CODE (addr1) == PLUS)
18600 /* If not a REG, return zero. */
18601 if (!REG_P (XEXP (addr1, 0)))
18605 reg1 = REGNO (XEXP (addr1, 0));
18606 /* The offset must be constant! */
18607 if (!CONST_INT_P (XEXP (addr1, 1)))
18609 offset1 = INTVAL (XEXP (addr1, 1));
18612 else if (!REG_P (addr1))
18616 reg1 = REGNO (addr1);
18617 /* This was a simple (mem (reg)) expression. Offset is 0. */
18621 /* And now for the second addr. */
18622 if (GET_CODE (addr2) == PLUS)
18624 /* If not a REG, return zero. */
18625 if (!REG_P (XEXP (addr2, 0)))
18629 reg2 = REGNO (XEXP (addr2, 0));
18630 /* The offset must be constant. */
18631 if (!CONST_INT_P (XEXP (addr2, 1)))
18633 offset2 = INTVAL (XEXP (addr2, 1));
18636 else if (!REG_P (addr2))
18640 reg2 = REGNO (addr2);
18641 /* This was a simple (mem (reg)) expression. Offset is 0. */
18645 /* Both of these must have the same base register. */
18649 /* The offset for the second addr must be 8 more than the first addr. */
18650 if (offset2 != offset1 + 8)
18653 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
18658 /* Implement TARGET_SECONDARY_RELOAD_NEEDED_MODE. For SDmode values we
18659 need to use DDmode, in all other cases we can use the same mode. */
18660 static machine_mode
18661 rs6000_secondary_memory_needed_mode (machine_mode mode)
18663 if (lra_in_progress && mode == SDmode)
18668 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
18669 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
18670 only work on the traditional altivec registers, note if an altivec register
18673 static enum rs6000_reg_type
18674 register_to_reg_type (rtx reg, bool *is_altivec)
18676 HOST_WIDE_INT regno;
18677 enum reg_class rclass;
18679 if (SUBREG_P (reg))
18680 reg = SUBREG_REG (reg);
18683 return NO_REG_TYPE;
18685 regno = REGNO (reg);
18686 if (!HARD_REGISTER_NUM_P (regno))
18688 if (!lra_in_progress && !reload_completed)
18689 return PSEUDO_REG_TYPE;
18691 regno = true_regnum (reg);
18692 if (regno < 0 || !HARD_REGISTER_NUM_P (regno))
18693 return PSEUDO_REG_TYPE;
18696 gcc_assert (regno >= 0);
18698 if (is_altivec && ALTIVEC_REGNO_P (regno))
18699 *is_altivec = true;
18701 rclass = rs6000_regno_regclass[regno];
18702 return reg_class_to_reg_type[(int)rclass];
18705 /* Helper function to return the cost of adding a TOC entry address. */
18708 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
18712 if (TARGET_CMODEL != CMODEL_SMALL)
18713 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
18716 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
18721 /* Helper function for rs6000_secondary_reload to determine whether the memory
18722 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
18723 needs reloading. Return negative if the memory is not handled by the memory
18724 helper functions and to try a different reload method, 0 if no additional
18725 instructions are need, and positive to give the extra cost for the
18729 rs6000_secondary_reload_memory (rtx addr,
18730 enum reg_class rclass,
18733 int extra_cost = 0;
18734 rtx reg, and_arg, plus_arg0, plus_arg1;
18735 addr_mask_type addr_mask;
18736 const char *type = NULL;
18737 const char *fail_msg = NULL;
18739 if (GPR_REG_CLASS_P (rclass))
18740 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
18742 else if (rclass == FLOAT_REGS)
18743 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
18745 else if (rclass == ALTIVEC_REGS)
18746 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
18748 /* For the combined VSX_REGS, turn off Altivec AND -16. */
18749 else if (rclass == VSX_REGS)
18750 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
18751 & ~RELOAD_REG_AND_M16);
18753 /* If the register allocator hasn't made up its mind yet on the register
18754 class to use, settle on defaults to use. */
18755 else if (rclass == NO_REGS)
18757 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_ANY]
18758 & ~RELOAD_REG_AND_M16);
18760 if ((addr_mask & RELOAD_REG_MULTIPLE) != 0)
18761 addr_mask &= ~(RELOAD_REG_INDEXED
18762 | RELOAD_REG_PRE_INCDEC
18763 | RELOAD_REG_PRE_MODIFY);
18769 /* If the register isn't valid in this register class, just return now. */
18770 if ((addr_mask & RELOAD_REG_VALID) == 0)
18772 if (TARGET_DEBUG_ADDR)
18775 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
18776 "not valid in class\n",
18777 GET_MODE_NAME (mode), reg_class_names[rclass]);
18784 switch (GET_CODE (addr))
18786 /* Does the register class supports auto update forms for this mode? We
18787 don't need a scratch register, since the powerpc only supports
18788 PRE_INC, PRE_DEC, and PRE_MODIFY. */
18791 reg = XEXP (addr, 0);
18792 if (!base_reg_operand (addr, GET_MODE (reg)))
18794 fail_msg = "no base register #1";
18798 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
18806 reg = XEXP (addr, 0);
18807 plus_arg1 = XEXP (addr, 1);
18808 if (!base_reg_operand (reg, GET_MODE (reg))
18809 || GET_CODE (plus_arg1) != PLUS
18810 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
18812 fail_msg = "bad PRE_MODIFY";
18816 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
18823 /* Do we need to simulate AND -16 to clear the bottom address bits used
18824 in VMX load/stores? Only allow the AND for vector sizes. */
18826 and_arg = XEXP (addr, 0);
18827 if (GET_MODE_SIZE (mode) != 16
18828 || !CONST_INT_P (XEXP (addr, 1))
18829 || INTVAL (XEXP (addr, 1)) != -16)
18831 fail_msg = "bad Altivec AND #1";
18835 if (rclass != ALTIVEC_REGS)
18837 if (legitimate_indirect_address_p (and_arg, false))
18840 else if (legitimate_indexed_address_p (and_arg, false))
18845 fail_msg = "bad Altivec AND #2";
18853 /* If this is an indirect address, make sure it is a base register. */
18856 if (!legitimate_indirect_address_p (addr, false))
18863 /* If this is an indexed address, make sure the register class can handle
18864 indexed addresses for this mode. */
18866 plus_arg0 = XEXP (addr, 0);
18867 plus_arg1 = XEXP (addr, 1);
18869 /* (plus (plus (reg) (constant)) (constant)) is generated during
18870 push_reload processing, so handle it now. */
18871 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
18873 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18880 /* (plus (plus (reg) (constant)) (reg)) is also generated during
18881 push_reload processing, so handle it now. */
18882 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
18884 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
18887 type = "indexed #2";
18891 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
18893 fail_msg = "no base register #2";
18897 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
18899 if ((addr_mask & RELOAD_REG_INDEXED) == 0
18900 || !legitimate_indexed_address_p (addr, false))
18907 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0
18908 && CONST_INT_P (plus_arg1))
18910 if (!quad_address_offset_p (INTVAL (plus_arg1)))
18913 type = "vector d-form offset";
18917 /* Make sure the register class can handle offset addresses. */
18918 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
18920 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18923 type = "offset #2";
18929 fail_msg = "bad PLUS";
18936 /* Quad offsets are restricted and can't handle normal addresses. */
18937 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18940 type = "vector d-form lo_sum";
18943 else if (!legitimate_lo_sum_address_p (mode, addr, false))
18945 fail_msg = "bad LO_SUM";
18949 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18956 /* Static addresses need to create a TOC entry. */
18960 if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18963 type = "vector d-form lo_sum #2";
18969 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
18973 /* TOC references look like offsetable memory. */
18975 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
18977 fail_msg = "bad UNSPEC";
18981 else if ((addr_mask & RELOAD_REG_QUAD_OFFSET) != 0)
18984 type = "vector d-form lo_sum #3";
18987 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
18990 type = "toc reference";
18996 fail_msg = "bad address";
19001 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
19003 if (extra_cost < 0)
19005 "rs6000_secondary_reload_memory error: mode = %s, "
19006 "class = %s, addr_mask = '%s', %s\n",
19007 GET_MODE_NAME (mode),
19008 reg_class_names[rclass],
19009 rs6000_debug_addr_mask (addr_mask, false),
19010 (fail_msg != NULL) ? fail_msg : "<bad address>");
19014 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
19015 "addr_mask = '%s', extra cost = %d, %s\n",
19016 GET_MODE_NAME (mode),
19017 reg_class_names[rclass],
19018 rs6000_debug_addr_mask (addr_mask, false),
19020 (type) ? type : "<none>");
19028 /* Helper function for rs6000_secondary_reload to return true if a move to a
19029 different register classe is really a simple move. */
19032 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
19033 enum rs6000_reg_type from_type,
19036 int size = GET_MODE_SIZE (mode);
19038 /* Add support for various direct moves available. In this function, we only
19039 look at cases where we don't need any extra registers, and one or more
19040 simple move insns are issued. Originally small integers are not allowed
19041 in FPR/VSX registers. Single precision binary floating is not a simple
19042 move because we need to convert to the single precision memory layout.
19043 The 4-byte SDmode can be moved. TDmode values are disallowed since they
19044 need special direct move handling, which we do not support yet. */
19045 if (TARGET_DIRECT_MOVE
19046 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19047 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
19049 if (TARGET_POWERPC64)
19051 /* ISA 2.07: MTVSRD or MVFVSRD. */
19055 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
19056 if (size == 16 && TARGET_P9_VECTOR && mode != TDmode)
19060 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19061 if (TARGET_P8_VECTOR)
19063 if (mode == SImode)
19066 if (TARGET_P9_VECTOR && (mode == HImode || mode == QImode))
19070 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
19071 if (mode == SDmode)
19075 /* Power6+: MFTGPR or MFFGPR. */
19076 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
19077 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
19078 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19081 /* Move to/from SPR. */
19082 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
19083 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
19084 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
19090 /* Direct move helper function for rs6000_secondary_reload, handle all of the
19091 special direct moves that involve allocating an extra register, return the
19092 insn code of the helper function if there is such a function or
19093 CODE_FOR_nothing if not. */
19096 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
19097 enum rs6000_reg_type from_type,
19099 secondary_reload_info *sri,
19103 enum insn_code icode = CODE_FOR_nothing;
19105 int size = GET_MODE_SIZE (mode);
19107 if (TARGET_POWERPC64 && size == 16)
19109 /* Handle moving 128-bit values from GPRs to VSX point registers on
19110 ISA 2.07 (power8, power9) when running in 64-bit mode using
19111 XXPERMDI to glue the two 64-bit values back together. */
19112 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19114 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
19115 icode = reg_addr[mode].reload_vsx_gpr;
19118 /* Handle moving 128-bit values from VSX point registers to GPRs on
19119 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
19120 bottom 64-bit value. */
19121 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19123 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
19124 icode = reg_addr[mode].reload_gpr_vsx;
19128 else if (TARGET_POWERPC64 && mode == SFmode)
19130 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
19132 cost = 3; /* xscvdpspn, mfvsrd, and. */
19133 icode = reg_addr[mode].reload_gpr_vsx;
19136 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
19138 cost = 2; /* mtvsrz, xscvspdpn. */
19139 icode = reg_addr[mode].reload_vsx_gpr;
19143 else if (!TARGET_POWERPC64 && size == 8)
19145 /* Handle moving 64-bit values from GPRs to floating point registers on
19146 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
19147 32-bit values back together. Altivec register classes must be handled
19148 specially since a different instruction is used, and the secondary
19149 reload support requires a single instruction class in the scratch
19150 register constraint. However, right now TFmode is not allowed in
19151 Altivec registers, so the pattern will never match. */
19152 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
19154 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
19155 icode = reg_addr[mode].reload_fpr_gpr;
19159 if (icode != CODE_FOR_nothing)
19164 sri->icode = icode;
19165 sri->extra_cost = cost;
19172 /* Return whether a move between two register classes can be done either
19173 directly (simple move) or via a pattern that uses a single extra temporary
19174 (using ISA 2.07's direct move in this case. */
19177 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
19178 enum rs6000_reg_type from_type,
19180 secondary_reload_info *sri,
19183 /* Fall back to load/store reloads if either type is not a register. */
19184 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
19187 /* If we haven't allocated registers yet, assume the move can be done for the
19188 standard register types. */
19189 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
19190 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
19191 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
19194 /* Moves to the same set of registers is a simple move for non-specialized
19196 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
19199 /* Check whether a simple move can be done directly. */
19200 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
19204 sri->icode = CODE_FOR_nothing;
19205 sri->extra_cost = 0;
19210 /* Now check if we can do it in a few steps. */
19211 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
19215 /* Inform reload about cases where moving X with a mode MODE to a register in
19216 RCLASS requires an extra scratch or immediate register. Return the class
19217 needed for the immediate register.
19219 For VSX and Altivec, we may need a register to convert sp+offset into
19222 For misaligned 64-bit gpr loads and stores we need a register to
19223 convert an offset address to indirect. */
19226 rs6000_secondary_reload (bool in_p,
19228 reg_class_t rclass_i,
19230 secondary_reload_info *sri)
19232 enum reg_class rclass = (enum reg_class) rclass_i;
19233 reg_class_t ret = ALL_REGS;
19234 enum insn_code icode;
19235 bool default_p = false;
19236 bool done_p = false;
19238 /* Allow subreg of memory before/during reload. */
19239 bool memory_p = (MEM_P (x)
19240 || (!reload_completed && SUBREG_P (x)
19241 && MEM_P (SUBREG_REG (x))));
19243 sri->icode = CODE_FOR_nothing;
19244 sri->t_icode = CODE_FOR_nothing;
19245 sri->extra_cost = 0;
19247 ? reg_addr[mode].reload_load
19248 : reg_addr[mode].reload_store);
19250 if (REG_P (x) || register_operand (x, mode))
19252 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
19253 bool altivec_p = (rclass == ALTIVEC_REGS);
19254 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
19257 std::swap (to_type, from_type);
19259 /* Can we do a direct move of some sort? */
19260 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
19263 icode = (enum insn_code)sri->icode;
19270 /* Make sure 0.0 is not reloaded or forced into memory. */
19271 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
19278 /* If this is a scalar floating point value and we want to load it into the
19279 traditional Altivec registers, do it via a move via a traditional floating
19280 point register, unless we have D-form addressing. Also make sure that
19281 non-zero constants use a FPR. */
19282 if (!done_p && reg_addr[mode].scalar_in_vmx_p
19283 && !mode_supports_vmx_dform (mode)
19284 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19285 && (memory_p || CONST_DOUBLE_P (x)))
19292 /* Handle reload of load/stores if we have reload helper functions. */
19293 if (!done_p && icode != CODE_FOR_nothing && memory_p)
19295 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
19298 if (extra_cost >= 0)
19302 if (extra_cost > 0)
19304 sri->extra_cost = extra_cost;
19305 sri->icode = icode;
19310 /* Handle unaligned loads and stores of integer registers. */
19311 if (!done_p && TARGET_POWERPC64
19312 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19314 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
19316 rtx addr = XEXP (x, 0);
19317 rtx off = address_offset (addr);
19319 if (off != NULL_RTX)
19321 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19322 unsigned HOST_WIDE_INT offset = INTVAL (off);
19324 /* We need a secondary reload when our legitimate_address_p
19325 says the address is good (as otherwise the entire address
19326 will be reloaded), and the offset is not a multiple of
19327 four or we have an address wrap. Address wrap will only
19328 occur for LO_SUMs since legitimate_offset_address_p
19329 rejects addresses for 16-byte mems that will wrap. */
19330 if (GET_CODE (addr) == LO_SUM
19331 ? (1 /* legitimate_address_p allows any offset for lo_sum */
19332 && ((offset & 3) != 0
19333 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
19334 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
19335 && (offset & 3) != 0))
19337 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
19339 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_load
19340 : CODE_FOR_reload_di_load);
19342 sri->icode = ((TARGET_32BIT) ? CODE_FOR_reload_si_store
19343 : CODE_FOR_reload_di_store);
19344 sri->extra_cost = 2;
19355 if (!done_p && !TARGET_POWERPC64
19356 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
19358 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
19360 rtx addr = XEXP (x, 0);
19361 rtx off = address_offset (addr);
19363 if (off != NULL_RTX)
19365 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
19366 unsigned HOST_WIDE_INT offset = INTVAL (off);
19368 /* We need a secondary reload when our legitimate_address_p
19369 says the address is good (as otherwise the entire address
19370 will be reloaded), and we have a wrap.
19372 legitimate_lo_sum_address_p allows LO_SUM addresses to
19373 have any offset so test for wrap in the low 16 bits.
19375 legitimate_offset_address_p checks for the range
19376 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
19377 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
19378 [0x7ff4,0x7fff] respectively, so test for the
19379 intersection of these ranges, [0x7ffc,0x7fff] and
19380 [0x7ff4,0x7ff7] respectively.
19382 Note that the address we see here may have been
19383 manipulated by legitimize_reload_address. */
19384 if (GET_CODE (addr) == LO_SUM
19385 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
19386 : offset - (0x8000 - extra) < UNITS_PER_WORD)
19389 sri->icode = CODE_FOR_reload_si_load;
19391 sri->icode = CODE_FOR_reload_si_store;
19392 sri->extra_cost = 2;
19407 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
19409 gcc_assert (ret != ALL_REGS);
19411 if (TARGET_DEBUG_ADDR)
19414 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
19416 reg_class_names[ret],
19417 in_p ? "true" : "false",
19418 reg_class_names[rclass],
19419 GET_MODE_NAME (mode));
19421 if (reload_completed)
19422 fputs (", after reload", stderr);
19425 fputs (", done_p not set", stderr);
19428 fputs (", default secondary reload", stderr);
19430 if (sri->icode != CODE_FOR_nothing)
19431 fprintf (stderr, ", reload func = %s, extra cost = %d",
19432 insn_data[sri->icode].name, sri->extra_cost);
19434 else if (sri->extra_cost > 0)
19435 fprintf (stderr, ", extra cost = %d", sri->extra_cost);
19437 fputs ("\n", stderr);
19444 /* Better tracing for rs6000_secondary_reload_inner. */
19447 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
19452 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
19454 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
19455 store_p ? "store" : "load");
19458 set = gen_rtx_SET (mem, reg);
19460 set = gen_rtx_SET (reg, mem);
19462 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
19463 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
19466 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
19467 ATTRIBUTE_NORETURN;
19470 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
19473 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
19474 gcc_unreachable ();
19477 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
19478 reload helper functions. These were identified in
19479 rs6000_secondary_reload_memory, and if reload decided to use the secondary
19480 reload, it calls the insns:
19481 reload_<RELOAD:mode>_<P:mptrsize>_store
19482 reload_<RELOAD:mode>_<P:mptrsize>_load
19484 which in turn calls this function, to do whatever is necessary to create
19485 valid addresses. */
19488 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
19490 int regno = true_regnum (reg);
19491 machine_mode mode = GET_MODE (reg);
19492 addr_mask_type addr_mask;
19495 rtx op_reg, op0, op1;
19500 if (regno < 0 || !HARD_REGISTER_NUM_P (regno) || !MEM_P (mem)
19501 || !base_reg_operand (scratch, GET_MODE (scratch)))
19502 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19504 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
19505 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
19507 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
19508 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
19510 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
19511 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
19514 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19516 /* Make sure the mode is valid in this register class. */
19517 if ((addr_mask & RELOAD_REG_VALID) == 0)
19518 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19520 if (TARGET_DEBUG_ADDR)
19521 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
19523 new_addr = addr = XEXP (mem, 0);
19524 switch (GET_CODE (addr))
19526 /* Does the register class support auto update forms for this mode? If
19527 not, do the update now. We don't need a scratch register, since the
19528 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
19531 op_reg = XEXP (addr, 0);
19532 if (!base_reg_operand (op_reg, Pmode))
19533 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19535 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
19537 int delta = GET_MODE_SIZE (mode);
19538 if (GET_CODE (addr) == PRE_DEC)
19540 emit_insn (gen_add2_insn (op_reg, GEN_INT (delta)));
19546 op0 = XEXP (addr, 0);
19547 op1 = XEXP (addr, 1);
19548 if (!base_reg_operand (op0, Pmode)
19549 || GET_CODE (op1) != PLUS
19550 || !rtx_equal_p (op0, XEXP (op1, 0)))
19551 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19553 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
19555 emit_insn (gen_rtx_SET (op0, op1));
19560 /* Do we need to simulate AND -16 to clear the bottom address bits used
19561 in VMX load/stores? */
19563 op0 = XEXP (addr, 0);
19564 op1 = XEXP (addr, 1);
19565 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
19567 if (REG_P (op0) || SUBREG_P (op0))
19570 else if (GET_CODE (op1) == PLUS)
19572 emit_insn (gen_rtx_SET (scratch, op1));
19577 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19579 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
19580 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
19581 rv = gen_rtvec (2, gen_rtx_SET (scratch, and_op), cc_clobber);
19582 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
19583 new_addr = scratch;
19587 /* If this is an indirect address, make sure it is a base register. */
19590 if (!base_reg_operand (addr, GET_MODE (addr)))
19592 emit_insn (gen_rtx_SET (scratch, addr));
19593 new_addr = scratch;
19597 /* If this is an indexed address, make sure the register class can handle
19598 indexed addresses for this mode. */
19600 op0 = XEXP (addr, 0);
19601 op1 = XEXP (addr, 1);
19602 if (!base_reg_operand (op0, Pmode))
19603 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19605 else if (int_reg_operand (op1, Pmode))
19607 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19609 emit_insn (gen_rtx_SET (scratch, addr));
19610 new_addr = scratch;
19614 else if (mode_supports_dq_form (mode) && CONST_INT_P (op1))
19616 if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
19617 || !quad_address_p (addr, mode, false))
19619 emit_insn (gen_rtx_SET (scratch, addr));
19620 new_addr = scratch;
19624 /* Make sure the register class can handle offset addresses. */
19625 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
19627 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19629 emit_insn (gen_rtx_SET (scratch, addr));
19630 new_addr = scratch;
19635 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19640 op0 = XEXP (addr, 0);
19641 op1 = XEXP (addr, 1);
19642 if (!base_reg_operand (op0, Pmode))
19643 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19645 else if (int_reg_operand (op1, Pmode))
19647 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
19649 emit_insn (gen_rtx_SET (scratch, addr));
19650 new_addr = scratch;
19654 /* Quad offsets are restricted and can't handle normal addresses. */
19655 else if (mode_supports_dq_form (mode))
19657 emit_insn (gen_rtx_SET (scratch, addr));
19658 new_addr = scratch;
19661 /* Make sure the register class can handle offset addresses. */
19662 else if (legitimate_lo_sum_address_p (mode, addr, false))
19664 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
19666 emit_insn (gen_rtx_SET (scratch, addr));
19667 new_addr = scratch;
19672 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19679 rs6000_emit_move (scratch, addr, Pmode);
19680 new_addr = scratch;
19684 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
19687 /* Adjust the address if it changed. */
19688 if (addr != new_addr)
19690 mem = replace_equiv_address_nv (mem, new_addr);
19691 if (TARGET_DEBUG_ADDR)
19692 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
19695 /* Now create the move. */
19697 emit_insn (gen_rtx_SET (mem, reg));
19699 emit_insn (gen_rtx_SET (reg, mem));
19704 /* Convert reloads involving 64-bit gprs and misaligned offset
19705 addressing, or multiple 32-bit gprs and offsets that are too large,
19706 to use indirect addressing. */
19709 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
19711 int regno = true_regnum (reg);
19712 enum reg_class rclass;
19714 rtx scratch_or_premodify = scratch;
19716 if (TARGET_DEBUG_ADDR)
19718 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
19719 store_p ? "store" : "load");
19720 fprintf (stderr, "reg:\n");
19722 fprintf (stderr, "mem:\n");
19724 fprintf (stderr, "scratch:\n");
19725 debug_rtx (scratch);
19728 gcc_assert (regno >= 0 && HARD_REGISTER_NUM_P (regno));
19729 gcc_assert (MEM_P (mem));
19730 rclass = REGNO_REG_CLASS (regno);
19731 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
19732 addr = XEXP (mem, 0);
19734 if (GET_CODE (addr) == PRE_MODIFY)
19736 gcc_assert (REG_P (XEXP (addr, 0))
19737 && GET_CODE (XEXP (addr, 1)) == PLUS
19738 && XEXP (XEXP (addr, 1), 0) == XEXP (addr, 0));
19739 scratch_or_premodify = XEXP (addr, 0);
19740 addr = XEXP (addr, 1);
19742 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
19744 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
19746 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
19748 /* Now create the move. */
19750 emit_insn (gen_rtx_SET (mem, reg));
19752 emit_insn (gen_rtx_SET (reg, mem));
19757 /* Given an rtx X being reloaded into a reg required to be
19758 in class CLASS, return the class of reg to actually use.
19759 In general this is just CLASS; but on some machines
19760 in some cases it is preferable to use a more restrictive class.
19762 On the RS/6000, we have to return NO_REGS when we want to reload a
19763 floating-point CONST_DOUBLE to force it to be copied to memory.
19765 We also don't want to reload integer values into floating-point
19766 registers if we can at all help it. In fact, this can
19767 cause reload to die, if it tries to generate a reload of CTR
19768 into a FP register and discovers it doesn't have the memory location
19771 ??? Would it be a good idea to have reload do the converse, that is
19772 try to reload floating modes into FP registers if possible?
19775 static enum reg_class
19776 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
19778 machine_mode mode = GET_MODE (x);
19779 bool is_constant = CONSTANT_P (x);
19781 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
19782 reload class for it. */
19783 if ((rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19784 && (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_VALID) == 0)
19787 if ((rclass == FLOAT_REGS || rclass == VSX_REGS)
19788 && (reg_addr[mode].addr_mask[RELOAD_REG_FPR] & RELOAD_REG_VALID) == 0)
19791 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
19792 the reloading of address expressions using PLUS into floating point
19794 if (TARGET_VSX && VSX_REG_CLASS_P (rclass) && GET_CODE (x) != PLUS)
19798 /* Zero is always allowed in all VSX registers. */
19799 if (x == CONST0_RTX (mode))
19802 /* If this is a vector constant that can be formed with a few Altivec
19803 instructions, we want altivec registers. */
19804 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
19805 return ALTIVEC_REGS;
19807 /* If this is an integer constant that can easily be loaded into
19808 vector registers, allow it. */
19809 if (CONST_INT_P (x))
19811 HOST_WIDE_INT value = INTVAL (x);
19813 /* ISA 2.07 can generate -1 in all registers with XXLORC. ISA
19814 2.06 can generate it in the Altivec registers with
19818 if (TARGET_P8_VECTOR)
19820 else if (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
19821 return ALTIVEC_REGS;
19826 /* ISA 3.0 can load -128..127 using the XXSPLTIB instruction and
19827 a sign extend in the Altivec registers. */
19828 if (IN_RANGE (value, -128, 127) && TARGET_P9_VECTOR
19829 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS))
19830 return ALTIVEC_REGS;
19833 /* Force constant to memory. */
19837 /* D-form addressing can easily reload the value. */
19838 if (mode_supports_vmx_dform (mode)
19839 || mode_supports_dq_form (mode))
19842 /* If this is a scalar floating point value and we don't have D-form
19843 addressing, prefer the traditional floating point registers so that we
19844 can use D-form (register+offset) addressing. */
19845 if (rclass == VSX_REGS
19846 && (mode == SFmode || GET_MODE_SIZE (mode) == 8))
19849 /* Prefer the Altivec registers if Altivec is handling the vector
19850 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
19852 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
19853 || mode == V1TImode)
19854 return ALTIVEC_REGS;
19859 if (is_constant || GET_CODE (x) == PLUS)
19861 if (reg_class_subset_p (GENERAL_REGS, rclass))
19862 return GENERAL_REGS;
19863 if (reg_class_subset_p (BASE_REGS, rclass))
19868 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == GEN_OR_FLOAT_REGS)
19869 return GENERAL_REGS;
19874 /* Debug version of rs6000_preferred_reload_class. */
19875 static enum reg_class
19876 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
19878 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
19881 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
19883 reg_class_names[ret], reg_class_names[rclass],
19884 GET_MODE_NAME (GET_MODE (x)));
19890 /* If we are copying between FP or AltiVec registers and anything else, we need
19891 a memory location. The exception is when we are targeting ppc64 and the
19892 move to/from fpr to gpr instructions are available. Also, under VSX, you
19893 can copy vector registers from the FP register set to the Altivec register
19894 set and vice versa. */
19897 rs6000_secondary_memory_needed (machine_mode mode,
19898 reg_class_t from_class,
19899 reg_class_t to_class)
19901 enum rs6000_reg_type from_type, to_type;
19902 bool altivec_p = ((from_class == ALTIVEC_REGS)
19903 || (to_class == ALTIVEC_REGS));
19905 /* If a simple/direct move is available, we don't need secondary memory */
19906 from_type = reg_class_to_reg_type[(int)from_class];
19907 to_type = reg_class_to_reg_type[(int)to_class];
19909 if (rs6000_secondary_reload_move (to_type, from_type, mode,
19910 (secondary_reload_info *)0, altivec_p))
19913 /* If we have a floating point or vector register class, we need to use
19914 memory to transfer the data. */
19915 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
19921 /* Debug version of rs6000_secondary_memory_needed. */
19923 rs6000_debug_secondary_memory_needed (machine_mode mode,
19924 reg_class_t from_class,
19925 reg_class_t to_class)
19927 bool ret = rs6000_secondary_memory_needed (mode, from_class, to_class);
19930 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
19931 "to_class = %s, mode = %s\n",
19932 ret ? "true" : "false",
19933 reg_class_names[from_class],
19934 reg_class_names[to_class],
19935 GET_MODE_NAME (mode));
19940 /* Return the register class of a scratch register needed to copy IN into
19941 or out of a register in RCLASS in MODE. If it can be done directly,
19942 NO_REGS is returned. */
19944 static enum reg_class
19945 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
19950 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
19952 && MACHOPIC_INDIRECT
19956 /* We cannot copy a symbolic operand directly into anything
19957 other than BASE_REGS for TARGET_ELF. So indicate that a
19958 register from BASE_REGS is needed as an intermediate
19961 On Darwin, pic addresses require a load from memory, which
19962 needs a base register. */
19963 if (rclass != BASE_REGS
19964 && (SYMBOL_REF_P (in)
19965 || GET_CODE (in) == HIGH
19966 || GET_CODE (in) == LABEL_REF
19967 || GET_CODE (in) == CONST))
19973 regno = REGNO (in);
19974 if (!HARD_REGISTER_NUM_P (regno))
19976 regno = true_regnum (in);
19977 if (!HARD_REGISTER_NUM_P (regno))
19981 else if (SUBREG_P (in))
19983 regno = true_regnum (in);
19984 if (!HARD_REGISTER_NUM_P (regno))
19990 /* If we have VSX register moves, prefer moving scalar values between
19991 Altivec registers and GPR by going via an FPR (and then via memory)
19992 instead of reloading the secondary memory address for Altivec moves. */
19994 && GET_MODE_SIZE (mode) < 16
19995 && !mode_supports_vmx_dform (mode)
19996 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
19997 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
19998 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
19999 && (regno >= 0 && INT_REGNO_P (regno)))))
20002 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
20004 if (rclass == GENERAL_REGS || rclass == BASE_REGS
20005 || (regno >= 0 && INT_REGNO_P (regno)))
20008 /* Constants, memory, and VSX registers can go into VSX registers (both the
20009 traditional floating point and the altivec registers). */
20010 if (rclass == VSX_REGS
20011 && (regno == -1 || VSX_REGNO_P (regno)))
20014 /* Constants, memory, and FP registers can go into FP registers. */
20015 if ((regno == -1 || FP_REGNO_P (regno))
20016 && (rclass == FLOAT_REGS || rclass == GEN_OR_FLOAT_REGS))
20017 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
20019 /* Memory, and AltiVec registers can go into AltiVec registers. */
20020 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
20021 && rclass == ALTIVEC_REGS)
20024 /* We can copy among the CR registers. */
20025 if ((rclass == CR_REGS || rclass == CR0_REGS)
20026 && regno >= 0 && CR_REGNO_P (regno))
20029 /* Otherwise, we need GENERAL_REGS. */
20030 return GENERAL_REGS;
20033 /* Debug version of rs6000_secondary_reload_class. */
20034 static enum reg_class
20035 rs6000_debug_secondary_reload_class (enum reg_class rclass,
20036 machine_mode mode, rtx in)
20038 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
20040 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
20041 "mode = %s, input rtx:\n",
20042 reg_class_names[ret], reg_class_names[rclass],
20043 GET_MODE_NAME (mode));
20049 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
20052 rs6000_can_change_mode_class (machine_mode from,
20054 reg_class_t rclass)
20056 unsigned from_size = GET_MODE_SIZE (from);
20057 unsigned to_size = GET_MODE_SIZE (to);
20059 if (from_size != to_size)
20061 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
20063 if (reg_classes_intersect_p (xclass, rclass))
20065 unsigned to_nregs = hard_regno_nregs (FIRST_FPR_REGNO, to);
20066 unsigned from_nregs = hard_regno_nregs (FIRST_FPR_REGNO, from);
20067 bool to_float128_vector_p = FLOAT128_VECTOR_P (to);
20068 bool from_float128_vector_p = FLOAT128_VECTOR_P (from);
20070 /* Don't allow 64-bit types to overlap with 128-bit types that take a
20071 single register under VSX because the scalar part of the register
20072 is in the upper 64-bits, and not the lower 64-bits. Types like
20073 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
20074 IEEE floating point can't overlap, and neither can small
20077 if (to_float128_vector_p && from_float128_vector_p)
20080 else if (to_float128_vector_p || from_float128_vector_p)
20083 /* TDmode in floating-mode registers must always go into a register
20084 pair with the most significant word in the even-numbered register
20085 to match ISA requirements. In little-endian mode, this does not
20086 match subreg numbering, so we cannot allow subregs. */
20087 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
20090 if (from_size < 8 || to_size < 8)
20093 if (from_size == 8 && (8 * to_nregs) != to_size)
20096 if (to_size == 8 && (8 * from_nregs) != from_size)
20105 /* Since the VSX register set includes traditional floating point registers
20106 and altivec registers, just check for the size being different instead of
20107 trying to check whether the modes are vector modes. Otherwise it won't
20108 allow say DF and DI to change classes. For types like TFmode and TDmode
20109 that take 2 64-bit registers, rather than a single 128-bit register, don't
20110 allow subregs of those types to other 128 bit types. */
20111 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
20113 unsigned num_regs = (from_size + 15) / 16;
20114 if (hard_regno_nregs (FIRST_FPR_REGNO, to) > num_regs
20115 || hard_regno_nregs (FIRST_FPR_REGNO, from) > num_regs)
20118 return (from_size == 8 || from_size == 16);
20121 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
20122 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
20128 /* Debug version of rs6000_can_change_mode_class. */
20130 rs6000_debug_can_change_mode_class (machine_mode from,
20132 reg_class_t rclass)
20134 bool ret = rs6000_can_change_mode_class (from, to, rclass);
20137 "rs6000_can_change_mode_class, return %s, from = %s, "
20138 "to = %s, rclass = %s\n",
20139 ret ? "true" : "false",
20140 GET_MODE_NAME (from), GET_MODE_NAME (to),
20141 reg_class_names[rclass]);
20146 /* Return a string to do a move operation of 128 bits of data. */
20149 rs6000_output_move_128bit (rtx operands[])
20151 rtx dest = operands[0];
20152 rtx src = operands[1];
20153 machine_mode mode = GET_MODE (dest);
20156 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
20157 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
20161 dest_regno = REGNO (dest);
20162 dest_gpr_p = INT_REGNO_P (dest_regno);
20163 dest_fp_p = FP_REGNO_P (dest_regno);
20164 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
20165 dest_vsx_p = dest_fp_p | dest_vmx_p;
20170 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
20175 src_regno = REGNO (src);
20176 src_gpr_p = INT_REGNO_P (src_regno);
20177 src_fp_p = FP_REGNO_P (src_regno);
20178 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
20179 src_vsx_p = src_fp_p | src_vmx_p;
20184 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
20187 /* Register moves. */
20188 if (dest_regno >= 0 && src_regno >= 0)
20195 if (TARGET_DIRECT_MOVE_128 && src_vsx_p)
20196 return (WORDS_BIG_ENDIAN
20197 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
20198 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
20200 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
20204 else if (TARGET_VSX && dest_vsx_p)
20207 return "xxlor %x0,%x1,%x1";
20209 else if (TARGET_DIRECT_MOVE_128 && src_gpr_p)
20210 return (WORDS_BIG_ENDIAN
20211 ? "mtvsrdd %x0,%1,%L1"
20212 : "mtvsrdd %x0,%L1,%1");
20214 else if (TARGET_DIRECT_MOVE && src_gpr_p)
20218 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
20219 return "vor %0,%1,%1";
20221 else if (dest_fp_p && src_fp_p)
20226 else if (dest_regno >= 0 && MEM_P (src))
20230 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20236 else if (TARGET_ALTIVEC && dest_vmx_p
20237 && altivec_indexed_or_indirect_operand (src, mode))
20238 return "lvx %0,%y1";
20240 else if (TARGET_VSX && dest_vsx_p)
20242 if (mode_supports_dq_form (mode)
20243 && quad_address_p (XEXP (src, 0), mode, true))
20244 return "lxv %x0,%1";
20246 else if (TARGET_P9_VECTOR)
20247 return "lxvx %x0,%y1";
20249 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20250 return "lxvw4x %x0,%y1";
20253 return "lxvd2x %x0,%y1";
20256 else if (TARGET_ALTIVEC && dest_vmx_p)
20257 return "lvx %0,%y1";
20259 else if (dest_fp_p)
20264 else if (src_regno >= 0 && MEM_P (dest))
20268 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
20269 return "stq %1,%0";
20274 else if (TARGET_ALTIVEC && src_vmx_p
20275 && altivec_indexed_or_indirect_operand (dest, mode))
20276 return "stvx %1,%y0";
20278 else if (TARGET_VSX && src_vsx_p)
20280 if (mode_supports_dq_form (mode)
20281 && quad_address_p (XEXP (dest, 0), mode, true))
20282 return "stxv %x1,%0";
20284 else if (TARGET_P9_VECTOR)
20285 return "stxvx %x1,%y0";
20287 else if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
20288 return "stxvw4x %x1,%y0";
20291 return "stxvd2x %x1,%y0";
20294 else if (TARGET_ALTIVEC && src_vmx_p)
20295 return "stvx %1,%y0";
20302 else if (dest_regno >= 0
20303 && (CONST_INT_P (src)
20304 || CONST_WIDE_INT_P (src)
20305 || CONST_DOUBLE_P (src)
20306 || GET_CODE (src) == CONST_VECTOR))
20311 else if ((dest_vmx_p && TARGET_ALTIVEC)
20312 || (dest_vsx_p && TARGET_VSX))
20313 return output_vec_const_move (operands);
20316 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest, src));
20319 /* Validate a 128-bit move. */
20321 rs6000_move_128bit_ok_p (rtx operands[])
20323 machine_mode mode = GET_MODE (operands[0]);
20324 return (gpc_reg_operand (operands[0], mode)
20325 || gpc_reg_operand (operands[1], mode));
20328 /* Return true if a 128-bit move needs to be split. */
20330 rs6000_split_128bit_ok_p (rtx operands[])
20332 if (!reload_completed)
20335 if (!gpr_or_gpr_p (operands[0], operands[1]))
20338 if (quad_load_store_p (operands[0], operands[1]))
20345 /* Given a comparison operation, return the bit number in CCR to test. We
20346 know this is a valid comparison.
20348 SCC_P is 1 if this is for an scc. That means that %D will have been
20349 used instead of %C, so the bits will be in different places.
20351 Return -1 if OP isn't a valid comparison for some reason. */
20354 ccr_bit (rtx op, int scc_p)
20356 enum rtx_code code = GET_CODE (op);
20357 machine_mode cc_mode;
20362 if (!COMPARISON_P (op))
20365 reg = XEXP (op, 0);
20367 if (!REG_P (reg) || !CR_REGNO_P (REGNO (reg)))
20370 cc_mode = GET_MODE (reg);
20371 cc_regnum = REGNO (reg);
20372 base_bit = 4 * (cc_regnum - CR0_REGNO);
20374 validate_condition_mode (code, cc_mode);
20376 /* When generating a sCOND operation, only positive conditions are
20395 return scc_p ? base_bit + 3 : base_bit + 2;
20397 return base_bit + 2;
20398 case GT: case GTU: case UNLE:
20399 return base_bit + 1;
20400 case LT: case LTU: case UNGE:
20402 case ORDERED: case UNORDERED:
20403 return base_bit + 3;
20406 /* If scc, we will have done a cror to put the bit in the
20407 unordered position. So test that bit. For integer, this is ! LT
20408 unless this is an scc insn. */
20409 return scc_p ? base_bit + 3 : base_bit;
20412 return scc_p ? base_bit + 3 : base_bit + 1;
20419 /* Return the GOT register. */
20422 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
20424 /* The second flow pass currently (June 1999) can't update
20425 regs_ever_live without disturbing other parts of the compiler, so
20426 update it here to make the prolog/epilogue code happy. */
20427 if (!can_create_pseudo_p ()
20428 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
20429 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
20431 crtl->uses_pic_offset_table = 1;
20433 return pic_offset_table_rtx;
20436 static rs6000_stack_t stack_info;
20438 /* Function to init struct machine_function.
20439 This will be called, via a pointer variable,
20440 from push_function_context. */
20442 static struct machine_function *
20443 rs6000_init_machine_status (void)
20445 stack_info.reload_completed = 0;
20446 return ggc_cleared_alloc<machine_function> ();
20449 #define INT_P(X) (CONST_INT_P (X) && GET_MODE (X) == VOIDmode)
20451 /* Write out a function code label. */
20454 rs6000_output_function_entry (FILE *file, const char *fname)
20456 if (fname[0] != '.')
20458 switch (DEFAULT_ABI)
20461 gcc_unreachable ();
20467 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
20477 RS6000_OUTPUT_BASENAME (file, fname);
20480 /* Print an operand. Recognize special options, documented below. */
20483 /* Access to .sdata2 through r2 (see -msdata=eabi in invoke.texi) is
20484 only introduced by the linker, when applying the sda21
20486 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
20487 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
20489 #define SMALL_DATA_RELOC "sda21"
20490 #define SMALL_DATA_REG 0
20494 print_operand (FILE *file, rtx x, int code)
20497 unsigned HOST_WIDE_INT uval;
20501 /* %a is output_address. */
20503 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
20507 /* Like 'J' but get to the GT bit only. */
20508 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20510 output_operand_lossage ("invalid %%D value");
20514 /* Bit 1 is GT bit. */
20515 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
20517 /* Add one for shift count in rlinm for scc. */
20518 fprintf (file, "%d", i + 1);
20522 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
20525 output_operand_lossage ("invalid %%e value");
20530 if ((uval & 0xffff) == 0 && uval != 0)
20535 /* X is a CR register. Print the number of the EQ bit of the CR */
20536 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20537 output_operand_lossage ("invalid %%E value");
20539 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
20543 /* X is a CR register. Print the shift count needed to move it
20544 to the high-order four bits. */
20545 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20546 output_operand_lossage ("invalid %%f value");
20548 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
20552 /* Similar, but print the count for the rotate in the opposite
20554 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20555 output_operand_lossage ("invalid %%F value");
20557 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
20561 /* X is a constant integer. If it is negative, print "m",
20562 otherwise print "z". This is to make an aze or ame insn. */
20563 if (!CONST_INT_P (x))
20564 output_operand_lossage ("invalid %%G value");
20565 else if (INTVAL (x) >= 0)
20572 /* If constant, output low-order five bits. Otherwise, write
20575 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
20577 print_operand (file, x, 0);
20581 /* If constant, output low-order six bits. Otherwise, write
20584 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
20586 print_operand (file, x, 0);
20590 /* Print `i' if this is a constant, else nothing. */
20596 /* Write the bit number in CCR for jump. */
20597 i = ccr_bit (x, 0);
20599 output_operand_lossage ("invalid %%j code");
20601 fprintf (file, "%d", i);
20605 /* Similar, but add one for shift count in rlinm for scc and pass
20606 scc flag to `ccr_bit'. */
20607 i = ccr_bit (x, 1);
20609 output_operand_lossage ("invalid %%J code");
20611 /* If we want bit 31, write a shift count of zero, not 32. */
20612 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20616 /* X must be a constant. Write the 1's complement of the
20619 output_operand_lossage ("invalid %%k value");
20621 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
20625 /* X must be a symbolic constant on ELF. Write an
20626 expression suitable for an 'addi' that adds in the low 16
20627 bits of the MEM. */
20628 if (GET_CODE (x) == CONST)
20630 if (GET_CODE (XEXP (x, 0)) != PLUS
20631 || (!SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
20632 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
20633 || !CONST_INT_P (XEXP (XEXP (x, 0), 1)))
20634 output_operand_lossage ("invalid %%K value");
20636 print_operand_address (file, x);
20637 fputs ("@l", file);
20640 /* %l is output_asm_label. */
20643 /* Write second word of DImode or DFmode reference. Works on register
20644 or non-indexed memory only. */
20646 fputs (reg_names[REGNO (x) + 1], file);
20647 else if (MEM_P (x))
20649 machine_mode mode = GET_MODE (x);
20650 /* Handle possible auto-increment. Since it is pre-increment and
20651 we have already done it, we can just use an offset of word. */
20652 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20653 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20654 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20656 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20657 output_address (mode, plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
20660 output_address (mode, XEXP (adjust_address_nv (x, SImode,
20664 if (small_data_operand (x, GET_MODE (x)))
20665 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20666 reg_names[SMALL_DATA_REG]);
20670 case 'N': /* Unused */
20671 /* Write the number of elements in the vector times 4. */
20672 if (GET_CODE (x) != PARALLEL)
20673 output_operand_lossage ("invalid %%N value");
20675 fprintf (file, "%d", XVECLEN (x, 0) * 4);
20678 case 'O': /* Unused */
20679 /* Similar, but subtract 1 first. */
20680 if (GET_CODE (x) != PARALLEL)
20681 output_operand_lossage ("invalid %%O value");
20683 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
20687 /* X is a CONST_INT that is a power of two. Output the logarithm. */
20690 || (i = exact_log2 (INTVAL (x))) < 0)
20691 output_operand_lossage ("invalid %%p value");
20693 fprintf (file, "%d", i);
20697 /* The operand must be an indirect memory reference. The result
20698 is the register name. */
20699 if (!MEM_P (x) || !REG_P (XEXP (x, 0))
20700 || REGNO (XEXP (x, 0)) >= 32)
20701 output_operand_lossage ("invalid %%P value");
20703 fputs (reg_names[REGNO (XEXP (x, 0))], file);
20707 /* This outputs the logical code corresponding to a boolean
20708 expression. The expression may have one or both operands
20709 negated (if one, only the first one). For condition register
20710 logical operations, it will also treat the negated
20711 CR codes as NOTs, but not handle NOTs of them. */
20713 const char *const *t = 0;
20715 enum rtx_code code = GET_CODE (x);
20716 static const char * const tbl[3][3] = {
20717 { "and", "andc", "nor" },
20718 { "or", "orc", "nand" },
20719 { "xor", "eqv", "xor" } };
20723 else if (code == IOR)
20725 else if (code == XOR)
20728 output_operand_lossage ("invalid %%q value");
20730 if (GET_CODE (XEXP (x, 0)) != NOT)
20734 if (GET_CODE (XEXP (x, 1)) == NOT)
20745 if (! TARGET_MFCRF)
20751 /* X is a CR register. Print the mask for `mtcrf'. */
20752 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20753 output_operand_lossage ("invalid %%R value");
20755 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
20759 /* Low 5 bits of 32 - value */
20761 output_operand_lossage ("invalid %%s value");
20763 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
20767 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
20768 if (!REG_P (x) || !CR_REGNO_P (REGNO (x)))
20770 output_operand_lossage ("invalid %%t value");
20774 /* Bit 3 is OV bit. */
20775 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
20777 /* If we want bit 31, write a shift count of zero, not 32. */
20778 fprintf (file, "%d", i == 31 ? 0 : i + 1);
20782 /* Print the symbolic name of a branch target register. */
20783 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
20784 x = XVECEXP (x, 0, 0);
20785 if (!REG_P (x) || (REGNO (x) != LR_REGNO
20786 && REGNO (x) != CTR_REGNO))
20787 output_operand_lossage ("invalid %%T value");
20788 else if (REGNO (x) == LR_REGNO)
20789 fputs ("lr", file);
20791 fputs ("ctr", file);
20795 /* High-order or low-order 16 bits of constant, whichever is non-zero,
20796 for use in unsigned operand. */
20799 output_operand_lossage ("invalid %%u value");
20804 if ((uval & 0xffff) == 0)
20807 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
20811 /* High-order 16 bits of constant for use in signed operand. */
20813 output_operand_lossage ("invalid %%v value");
20815 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
20816 (INTVAL (x) >> 16) & 0xffff);
20820 /* Print `u' if this has an auto-increment or auto-decrement. */
20822 && (GET_CODE (XEXP (x, 0)) == PRE_INC
20823 || GET_CODE (XEXP (x, 0)) == PRE_DEC
20824 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
20829 /* Print the trap code for this operand. */
20830 switch (GET_CODE (x))
20833 fputs ("eq", file); /* 4 */
20836 fputs ("ne", file); /* 24 */
20839 fputs ("lt", file); /* 16 */
20842 fputs ("le", file); /* 20 */
20845 fputs ("gt", file); /* 8 */
20848 fputs ("ge", file); /* 12 */
20851 fputs ("llt", file); /* 2 */
20854 fputs ("lle", file); /* 6 */
20857 fputs ("lgt", file); /* 1 */
20860 fputs ("lge", file); /* 5 */
20863 output_operand_lossage ("invalid %%V value");
20868 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
20871 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
20872 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
20874 print_operand (file, x, 0);
20878 /* X is a FPR or Altivec register used in a VSX context. */
20879 if (!REG_P (x) || !VSX_REGNO_P (REGNO (x)))
20880 output_operand_lossage ("invalid %%x value");
20883 int reg = REGNO (x);
20884 int vsx_reg = (FP_REGNO_P (reg)
20886 : reg - FIRST_ALTIVEC_REGNO + 32);
20888 #ifdef TARGET_REGNAMES
20889 if (TARGET_REGNAMES)
20890 fprintf (file, "%%vs%d", vsx_reg);
20893 fprintf (file, "%d", vsx_reg);
20899 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
20900 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
20901 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
20906 /* Like 'L', for third word of TImode/PTImode */
20908 fputs (reg_names[REGNO (x) + 2], file);
20909 else if (MEM_P (x))
20911 machine_mode mode = GET_MODE (x);
20912 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20913 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20914 output_address (mode, plus_constant (Pmode,
20915 XEXP (XEXP (x, 0), 0), 8));
20916 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20917 output_address (mode, plus_constant (Pmode,
20918 XEXP (XEXP (x, 0), 0), 8));
20920 output_address (mode, XEXP (adjust_address_nv (x, SImode, 8), 0));
20921 if (small_data_operand (x, GET_MODE (x)))
20922 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20923 reg_names[SMALL_DATA_REG]);
20928 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
20929 x = XVECEXP (x, 0, 1);
20930 /* X is a SYMBOL_REF. Write out the name preceded by a
20931 period and without any trailing data in brackets. Used for function
20932 names. If we are configured for System V (or the embedded ABI) on
20933 the PowerPC, do not emit the period, since those systems do not use
20934 TOCs and the like. */
20935 if (!SYMBOL_REF_P (x))
20937 output_operand_lossage ("invalid %%z value");
20941 /* For macho, check to see if we need a stub. */
20944 const char *name = XSTR (x, 0);
20946 if (darwin_emit_branch_islands
20947 && MACHOPIC_INDIRECT
20948 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
20949 name = machopic_indirection_name (x, /*stub_p=*/true);
20951 assemble_name (file, name);
20953 else if (!DOT_SYMBOLS)
20954 assemble_name (file, XSTR (x, 0));
20956 rs6000_output_function_entry (file, XSTR (x, 0));
20960 /* Like 'L', for last word of TImode/PTImode. */
20962 fputs (reg_names[REGNO (x) + 3], file);
20963 else if (MEM_P (x))
20965 machine_mode mode = GET_MODE (x);
20966 if (GET_CODE (XEXP (x, 0)) == PRE_INC
20967 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
20968 output_address (mode, plus_constant (Pmode,
20969 XEXP (XEXP (x, 0), 0), 12));
20970 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
20971 output_address (mode, plus_constant (Pmode,
20972 XEXP (XEXP (x, 0), 0), 12));
20974 output_address (mode, XEXP (adjust_address_nv (x, SImode, 12), 0));
20975 if (small_data_operand (x, GET_MODE (x)))
20976 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
20977 reg_names[SMALL_DATA_REG]);
20981 /* Print AltiVec memory operand. */
20986 gcc_assert (MEM_P (x));
20990 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (GET_MODE (x))
20991 && GET_CODE (tmp) == AND
20992 && CONST_INT_P (XEXP (tmp, 1))
20993 && INTVAL (XEXP (tmp, 1)) == -16)
20994 tmp = XEXP (tmp, 0);
20995 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
20996 && GET_CODE (tmp) == PRE_MODIFY)
20997 tmp = XEXP (tmp, 1);
20999 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
21002 if (GET_CODE (tmp) != PLUS
21003 || !REG_P (XEXP (tmp, 0))
21004 || !REG_P (XEXP (tmp, 1)))
21006 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
21010 if (REGNO (XEXP (tmp, 0)) == 0)
21011 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
21012 reg_names[ REGNO (XEXP (tmp, 0)) ]);
21014 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
21015 reg_names[ REGNO (XEXP (tmp, 1)) ]);
21022 fprintf (file, "%s", reg_names[REGNO (x)]);
21023 else if (MEM_P (x))
21025 /* We need to handle PRE_INC and PRE_DEC here, since we need to
21026 know the width from the mode. */
21027 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
21028 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
21029 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21030 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
21031 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
21032 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
21033 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
21034 output_address (GET_MODE (x), XEXP (XEXP (x, 0), 1));
21036 output_address (GET_MODE (x), XEXP (x, 0));
21038 else if (toc_relative_expr_p (x, false,
21039 &tocrel_base_oac, &tocrel_offset_oac))
21040 /* This hack along with a corresponding hack in
21041 rs6000_output_addr_const_extra arranges to output addends
21042 where the assembler expects to find them. eg.
21043 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
21044 without this hack would be output as "x@toc+4". We
21046 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21047 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
21048 output_addr_const (file, XVECEXP (x, 0, 0));
21049 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
21050 output_addr_const (file, XVECEXP (x, 0, 1));
21052 output_addr_const (file, x);
21056 if (const char *name = get_some_local_dynamic_name ())
21057 assemble_name (file, name);
21059 output_operand_lossage ("'%%&' used without any "
21060 "local dynamic TLS references");
21064 output_operand_lossage ("invalid %%xn code");
21068 /* Print the address of an operand. */
21071 print_operand_address (FILE *file, rtx x)
21074 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
21075 else if (SYMBOL_REF_P (x) || GET_CODE (x) == CONST
21076 || GET_CODE (x) == LABEL_REF)
21078 output_addr_const (file, x);
21079 if (small_data_operand (x, GET_MODE (x)))
21080 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
21081 reg_names[SMALL_DATA_REG]);
21083 gcc_assert (!TARGET_TOC);
21085 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21086 && REG_P (XEXP (x, 1)))
21088 if (REGNO (XEXP (x, 0)) == 0)
21089 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
21090 reg_names[ REGNO (XEXP (x, 0)) ]);
21092 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
21093 reg_names[ REGNO (XEXP (x, 1)) ]);
21095 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
21096 && CONST_INT_P (XEXP (x, 1)))
21097 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
21098 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
21100 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21101 && CONSTANT_P (XEXP (x, 1)))
21103 fprintf (file, "lo16(");
21104 output_addr_const (file, XEXP (x, 1));
21105 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21109 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
21110 && CONSTANT_P (XEXP (x, 1)))
21112 output_addr_const (file, XEXP (x, 1));
21113 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
21116 else if (toc_relative_expr_p (x, false, &tocrel_base_oac, &tocrel_offset_oac))
21118 /* This hack along with a corresponding hack in
21119 rs6000_output_addr_const_extra arranges to output addends
21120 where the assembler expects to find them. eg.
21122 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
21123 without this hack would be output as "x@toc+8@l(9)". We
21124 want "x+8@toc@l(9)". */
21125 output_addr_const (file, CONST_CAST_RTX (tocrel_base_oac));
21126 if (GET_CODE (x) == LO_SUM)
21127 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
21129 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base_oac, 0, 1))]);
21132 output_addr_const (file, x);
21135 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
21138 rs6000_output_addr_const_extra (FILE *file, rtx x)
21140 if (GET_CODE (x) == UNSPEC)
21141 switch (XINT (x, 1))
21143 case UNSPEC_TOCREL:
21144 gcc_checking_assert (SYMBOL_REF_P (XVECEXP (x, 0, 0))
21145 && REG_P (XVECEXP (x, 0, 1))
21146 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
21147 output_addr_const (file, XVECEXP (x, 0, 0));
21148 if (x == tocrel_base_oac && tocrel_offset_oac != const0_rtx)
21150 if (INTVAL (tocrel_offset_oac) >= 0)
21151 fprintf (file, "+");
21152 output_addr_const (file, CONST_CAST_RTX (tocrel_offset_oac));
21154 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
21157 assemble_name (file, toc_label_name);
21160 else if (TARGET_ELF)
21161 fputs ("@toc", file);
21165 case UNSPEC_MACHOPIC_OFFSET:
21166 output_addr_const (file, XVECEXP (x, 0, 0));
21168 machopic_output_function_base_name (file);
21175 /* Target hook for assembling integer objects. The PowerPC version has
21176 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
21177 is defined. It also needs to handle DI-mode objects on 64-bit
21181 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
21183 #ifdef RELOCATABLE_NEEDS_FIXUP
21184 /* Special handling for SI values. */
21185 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
21187 static int recurse = 0;
21189 /* For -mrelocatable, we mark all addresses that need to be fixed up in
21190 the .fixup section. Since the TOC section is already relocated, we
21191 don't need to mark it here. We used to skip the text section, but it
21192 should never be valid for relocated addresses to be placed in the text
21194 if (DEFAULT_ABI == ABI_V4
21195 && (TARGET_RELOCATABLE || flag_pic > 1)
21196 && in_section != toc_section
21198 && !CONST_SCALAR_INT_P (x)
21204 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
21206 ASM_OUTPUT_LABEL (asm_out_file, buf);
21207 fprintf (asm_out_file, "\t.long\t(");
21208 output_addr_const (asm_out_file, x);
21209 fprintf (asm_out_file, ")@fixup\n");
21210 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
21211 ASM_OUTPUT_ALIGN (asm_out_file, 2);
21212 fprintf (asm_out_file, "\t.long\t");
21213 assemble_name (asm_out_file, buf);
21214 fprintf (asm_out_file, "\n\t.previous\n");
21218 /* Remove initial .'s to turn a -mcall-aixdesc function
21219 address into the address of the descriptor, not the function
21221 else if (SYMBOL_REF_P (x)
21222 && XSTR (x, 0)[0] == '.'
21223 && DEFAULT_ABI == ABI_AIX)
21225 const char *name = XSTR (x, 0);
21226 while (*name == '.')
21229 fprintf (asm_out_file, "\t.long\t%s\n", name);
21233 #endif /* RELOCATABLE_NEEDS_FIXUP */
21234 return default_assemble_integer (x, size, aligned_p);
21237 /* Return a template string for assembly to emit when making an
21238 external call. FUNOP is the call mem argument operand number. */
21240 static const char *
21241 rs6000_call_template_1 (rtx *operands, unsigned int funop, bool sibcall)
21243 /* -Wformat-overflow workaround, without which gcc thinks that %u
21244 might produce 10 digits. */
21245 gcc_assert (funop <= MAX_RECOG_OPERANDS);
21249 if (TARGET_TLS_MARKERS && GET_CODE (operands[funop + 1]) == UNSPEC)
21251 if (XINT (operands[funop + 1], 1) == UNSPEC_TLSGD)
21252 sprintf (arg, "(%%%u@tlsgd)", funop + 1);
21253 else if (XINT (operands[funop + 1], 1) == UNSPEC_TLSLD)
21254 sprintf (arg, "(%%&@tlsld)");
21256 gcc_unreachable ();
21259 /* The magic 32768 offset here corresponds to the offset of
21260 r30 in .got2, as given by LCTOC1. See sysv4.h:toc_section. */
21262 sprintf (z, "%%z%u%s", funop,
21263 (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic == 2
21266 static char str[32]; /* 2 spare */
21267 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
21268 sprintf (str, "b%s %s%s%s", sibcall ? "" : "l", z, arg,
21269 sibcall ? "" : "\n\tnop");
21270 else if (DEFAULT_ABI == ABI_V4)
21271 sprintf (str, "b%s %s%s%s", sibcall ? "" : "l", z, arg,
21272 flag_pic ? "@plt" : "");
21274 /* If/when we remove the mlongcall opt, we can share the AIX/ELGv2 case. */
21275 else if (DEFAULT_ABI == ABI_DARWIN)
21277 /* The cookie is in operand func+2. */
21278 gcc_checking_assert (GET_CODE (operands[funop + 2]) == CONST_INT);
21279 int cookie = INTVAL (operands[funop + 2]);
21280 if (cookie & CALL_LONG)
21282 tree funname = get_identifier (XSTR (operands[funop], 0));
21283 tree labelname = get_prev_label (funname);
21284 gcc_checking_assert (labelname && !sibcall);
21286 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
21287 instruction will reach 'foo', otherwise link as 'bl L42'".
21288 "L42" should be a 'branch island', that will do a far jump to
21289 'foo'. Branch islands are generated in
21290 macho_branch_islands(). */
21291 sprintf (str, "jbsr %%z%u,%.10s", funop,
21292 IDENTIFIER_POINTER (labelname));
21295 /* Same as AIX or ELFv2, except to keep backwards compat, no nop
21297 sprintf (str, "b%s %s%s", sibcall ? "" : "l", z, arg);
21301 gcc_unreachable ();
21306 rs6000_call_template (rtx *operands, unsigned int funop)
21308 return rs6000_call_template_1 (operands, funop, false);
21312 rs6000_sibcall_template (rtx *operands, unsigned int funop)
21314 return rs6000_call_template_1 (operands, funop, true);
21317 /* As above, for indirect calls. */
21319 static const char *
21320 rs6000_indirect_call_template_1 (rtx *operands, unsigned int funop,
21323 /* -Wformat-overflow workaround, without which gcc thinks that %u
21324 might produce 10 digits. Note that -Wformat-overflow will not
21325 currently warn here for str[], so do not rely on a warning to
21326 ensure str[] is correctly sized. */
21327 gcc_assert (funop <= MAX_RECOG_OPERANDS);
21329 /* Currently, funop is either 0 or 1. The maximum string is always
21330 a !speculate 64-bit __tls_get_addr call.
21334 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21335 . 29 .reloc .,R_PPC64_PLTSEQ,%z1\n\t
21337 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21338 . 30 .reloc .,R_PPC64_PLTCALL,%z1\n\t
21345 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21346 . 29 .reloc .,R_PPC64_PLTSEQ,%z1\n\t
21348 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21349 . 30 .reloc .,R_PPC64_PLTCALL,%z1\n\t
21356 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21357 . 35 .reloc .,R_PPC64_PLTSEQ,%z1+32768\n\t
21359 . 27 .reloc .,R_PPC64_TLSGD,%2\n\t
21360 . 36 .reloc .,R_PPC64_PLTCALL,%z1+32768\n\t
21364 static char str[160]; /* 8 spare */
21366 const char *ptrload = TARGET_64BIT ? "d" : "wz";
21368 if (DEFAULT_ABI == ABI_AIX)
21371 ptrload, funop + 2);
21373 /* We don't need the extra code to stop indirect call speculation if
21375 bool speculate = (TARGET_MACHO
21376 || rs6000_speculate_indirect_jumps
21377 || (REG_P (operands[funop])
21378 && REGNO (operands[funop]) == LR_REGNO));
21380 if (TARGET_PLTSEQ && GET_CODE (operands[funop]) == UNSPEC)
21382 const char *rel64 = TARGET_64BIT ? "64" : "";
21385 if (TARGET_TLS_MARKERS && GET_CODE (operands[funop + 1]) == UNSPEC)
21387 if (XINT (operands[funop + 1], 1) == UNSPEC_TLSGD)
21388 sprintf (tls, ".reloc .,R_PPC%s_TLSGD,%%%u\n\t",
21390 else if (XINT (operands[funop + 1], 1) == UNSPEC_TLSLD)
21391 sprintf (tls, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21394 gcc_unreachable ();
21397 const char *addend = (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
21398 && flag_pic == 2 ? "+32768" : "");
21402 "%s.reloc .,R_PPC%s_PLTSEQ,%%z%u%s\n\t",
21403 tls, rel64, funop, addend);
21404 s += sprintf (s, "crset 2\n\t");
21407 "%s.reloc .,R_PPC%s_PLTCALL,%%z%u%s\n\t",
21408 tls, rel64, funop, addend);
21410 else if (!speculate)
21411 s += sprintf (s, "crset 2\n\t");
21413 if (DEFAULT_ABI == ABI_AIX)
21419 funop, ptrload, funop + 3);
21424 funop, ptrload, funop + 3);
21426 else if (DEFAULT_ABI == ABI_ELFv2)
21432 funop, ptrload, funop + 2);
21437 funop, ptrload, funop + 2);
21444 funop, sibcall ? "" : "l");
21448 funop, sibcall ? "" : "l", sibcall ? "\n\tb $" : "");
21454 rs6000_indirect_call_template (rtx *operands, unsigned int funop)
21456 return rs6000_indirect_call_template_1 (operands, funop, false);
21460 rs6000_indirect_sibcall_template (rtx *operands, unsigned int funop)
21462 return rs6000_indirect_call_template_1 (operands, funop, true);
21466 /* Output indirect call insns.
21467 WHICH is 0 for tocsave, 1 for plt16_ha, 2 for plt16_lo, 3 for mtctr. */
21469 rs6000_pltseq_template (rtx *operands, int which)
21471 const char *rel64 = TARGET_64BIT ? "64" : "";
21474 if (TARGET_TLS_MARKERS && GET_CODE (operands[3]) == UNSPEC)
21476 if (XINT (operands[3], 1) == UNSPEC_TLSGD)
21477 sprintf (tls, ".reloc .,R_PPC%s_TLSGD,%%3\n\t",
21479 else if (XINT (operands[3], 1) == UNSPEC_TLSLD)
21480 sprintf (tls, ".reloc .,R_PPC%s_TLSLD,%%&\n\t",
21483 gcc_unreachable ();
21486 gcc_assert (DEFAULT_ABI == ABI_ELFv2 || DEFAULT_ABI == ABI_V4);
21487 static char str[96]; /* 15 spare */
21488 const char *off = WORDS_BIG_ENDIAN ? "+2" : "";
21489 const char *addend = (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
21490 && flag_pic == 2 ? "+32768" : "");
21495 "%s.reloc .,R_PPC%s_PLTSEQ,%%z2\n\t"
21497 tls, rel64, TARGET_64BIT ? "d 2,24(1)" : "w 2,12(1)");
21500 if (DEFAULT_ABI == ABI_V4 && !flag_pic)
21502 "%s.reloc .%s,R_PPC%s_PLT16_HA,%%z2\n\t"
21507 "%s.reloc .%s,R_PPC%s_PLT16_HA,%%z2%s\n\t"
21509 tls, off, rel64, addend);
21513 "%s.reloc .%s,R_PPC%s_PLT16_LO%s,%%z2%s\n\t"
21515 tls, off, rel64, TARGET_64BIT ? "_DS" : "", addend,
21516 TARGET_64BIT ? "d" : "wz");
21520 "%s.reloc .,R_PPC%s_PLTSEQ,%%z2%s\n\t"
21522 tls, rel64, addend);
21525 gcc_unreachable ();
21531 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
21532 /* Emit an assembler directive to set symbol visibility for DECL to
21533 VISIBILITY_TYPE. */
21536 rs6000_assemble_visibility (tree decl, int vis)
21541 /* Functions need to have their entry point symbol visibility set as
21542 well as their descriptor symbol visibility. */
21543 if (DEFAULT_ABI == ABI_AIX
21545 && TREE_CODE (decl) == FUNCTION_DECL)
21547 static const char * const visibility_types[] = {
21548 NULL, "protected", "hidden", "internal"
21551 const char *name, *type;
21553 name = ((* targetm.strip_name_encoding)
21554 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
21555 type = visibility_types[vis];
21557 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
21558 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
21561 default_assemble_visibility (decl, vis);
21566 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
21568 /* Reversal of FP compares takes care -- an ordered compare
21569 becomes an unordered compare and vice versa. */
21570 if (mode == CCFPmode
21571 && (!flag_finite_math_only
21572 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
21573 || code == UNEQ || code == LTGT))
21574 return reverse_condition_maybe_unordered (code);
21576 return reverse_condition (code);
21579 /* Generate a compare for CODE. Return a brand-new rtx that
21580 represents the result of the compare. */
21583 rs6000_generate_compare (rtx cmp, machine_mode mode)
21585 machine_mode comp_mode;
21586 rtx compare_result;
21587 enum rtx_code code = GET_CODE (cmp);
21588 rtx op0 = XEXP (cmp, 0);
21589 rtx op1 = XEXP (cmp, 1);
21591 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21592 comp_mode = CCmode;
21593 else if (FLOAT_MODE_P (mode))
21594 comp_mode = CCFPmode;
21595 else if (code == GTU || code == LTU
21596 || code == GEU || code == LEU)
21597 comp_mode = CCUNSmode;
21598 else if ((code == EQ || code == NE)
21599 && unsigned_reg_p (op0)
21600 && (unsigned_reg_p (op1)
21601 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
21602 /* These are unsigned values, perhaps there will be a later
21603 ordering compare that can be shared with this one. */
21604 comp_mode = CCUNSmode;
21606 comp_mode = CCmode;
21608 /* If we have an unsigned compare, make sure we don't have a signed value as
21610 if (comp_mode == CCUNSmode && CONST_INT_P (op1)
21611 && INTVAL (op1) < 0)
21613 op0 = copy_rtx_if_shared (op0);
21614 op1 = force_reg (GET_MODE (op0), op1);
21615 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
21618 /* First, the compare. */
21619 compare_result = gen_reg_rtx (comp_mode);
21621 /* IEEE 128-bit support in VSX registers when we do not have hardware
21623 if (!TARGET_FLOAT128_HW && FLOAT128_VECTOR_P (mode))
21625 rtx libfunc = NULL_RTX;
21626 bool check_nan = false;
21633 libfunc = optab_libfunc (eq_optab, mode);
21638 libfunc = optab_libfunc (ge_optab, mode);
21643 libfunc = optab_libfunc (le_optab, mode);
21648 libfunc = optab_libfunc (unord_optab, mode);
21649 code = (code == UNORDERED) ? NE : EQ;
21655 libfunc = optab_libfunc (ge_optab, mode);
21656 code = (code == UNGE) ? GE : GT;
21662 libfunc = optab_libfunc (le_optab, mode);
21663 code = (code == UNLE) ? LE : LT;
21669 libfunc = optab_libfunc (eq_optab, mode);
21670 code = (code = UNEQ) ? EQ : NE;
21674 gcc_unreachable ();
21677 gcc_assert (libfunc);
21680 dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21681 SImode, op0, mode, op1, mode);
21683 /* The library signals an exception for signalling NaNs, so we need to
21684 handle isgreater, etc. by first checking isordered. */
21687 rtx ne_rtx, normal_dest, unord_dest;
21688 rtx unord_func = optab_libfunc (unord_optab, mode);
21689 rtx join_label = gen_label_rtx ();
21690 rtx join_ref = gen_rtx_LABEL_REF (VOIDmode, join_label);
21691 rtx unord_cmp = gen_reg_rtx (comp_mode);
21694 /* Test for either value being a NaN. */
21695 gcc_assert (unord_func);
21696 unord_dest = emit_library_call_value (unord_func, NULL_RTX, LCT_CONST,
21697 SImode, op0, mode, op1, mode);
21699 /* Set value (0) if either value is a NaN, and jump to the join
21701 dest = gen_reg_rtx (SImode);
21702 emit_move_insn (dest, const1_rtx);
21703 emit_insn (gen_rtx_SET (unord_cmp,
21704 gen_rtx_COMPARE (comp_mode, unord_dest,
21707 ne_rtx = gen_rtx_NE (comp_mode, unord_cmp, const0_rtx);
21708 emit_jump_insn (gen_rtx_SET (pc_rtx,
21709 gen_rtx_IF_THEN_ELSE (VOIDmode, ne_rtx,
21713 /* Do the normal comparison, knowing that the values are not
21715 normal_dest = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST,
21716 SImode, op0, mode, op1, mode);
21718 emit_insn (gen_cstoresi4 (dest,
21719 gen_rtx_fmt_ee (code, SImode, normal_dest,
21721 normal_dest, const0_rtx));
21723 /* Join NaN and non-Nan paths. Compare dest against 0. */
21724 emit_label (join_label);
21728 emit_insn (gen_rtx_SET (compare_result,
21729 gen_rtx_COMPARE (comp_mode, dest, const0_rtx)));
21734 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
21735 CLOBBERs to match cmptf_internal2 pattern. */
21736 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
21737 && FLOAT128_IBM_P (GET_MODE (op0))
21738 && TARGET_HARD_FLOAT)
21739 emit_insn (gen_rtx_PARALLEL (VOIDmode,
21741 gen_rtx_SET (compare_result,
21742 gen_rtx_COMPARE (comp_mode, op0, op1)),
21743 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21744 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21745 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21746 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21747 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21748 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21749 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21750 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
21751 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
21752 else if (GET_CODE (op1) == UNSPEC
21753 && XINT (op1, 1) == UNSPEC_SP_TEST)
21755 rtx op1b = XVECEXP (op1, 0, 0);
21756 comp_mode = CCEQmode;
21757 compare_result = gen_reg_rtx (CCEQmode);
21759 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
21761 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
21764 emit_insn (gen_rtx_SET (compare_result,
21765 gen_rtx_COMPARE (comp_mode, op0, op1)));
21768 /* Some kinds of FP comparisons need an OR operation;
21769 under flag_finite_math_only we don't bother. */
21770 if (FLOAT_MODE_P (mode)
21771 && (!FLOAT128_IEEE_P (mode) || TARGET_FLOAT128_HW)
21772 && !flag_finite_math_only
21773 && (code == LE || code == GE
21774 || code == UNEQ || code == LTGT
21775 || code == UNGT || code == UNLT))
21777 enum rtx_code or1, or2;
21778 rtx or1_rtx, or2_rtx, compare2_rtx;
21779 rtx or_result = gen_reg_rtx (CCEQmode);
21783 case LE: or1 = LT; or2 = EQ; break;
21784 case GE: or1 = GT; or2 = EQ; break;
21785 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
21786 case LTGT: or1 = LT; or2 = GT; break;
21787 case UNGT: or1 = UNORDERED; or2 = GT; break;
21788 case UNLT: or1 = UNORDERED; or2 = LT; break;
21789 default: gcc_unreachable ();
21791 validate_condition_mode (or1, comp_mode);
21792 validate_condition_mode (or2, comp_mode);
21793 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
21794 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
21795 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
21796 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
21798 emit_insn (gen_rtx_SET (or_result, compare2_rtx));
21800 compare_result = or_result;
21804 validate_condition_mode (code, GET_MODE (compare_result));
21806 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
21810 /* Return the diagnostic message string if the binary operation OP is
21811 not permitted on TYPE1 and TYPE2, NULL otherwise. */
21814 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED,
21818 machine_mode mode1 = TYPE_MODE (type1);
21819 machine_mode mode2 = TYPE_MODE (type2);
21821 /* For complex modes, use the inner type. */
21822 if (COMPLEX_MODE_P (mode1))
21823 mode1 = GET_MODE_INNER (mode1);
21825 if (COMPLEX_MODE_P (mode2))
21826 mode2 = GET_MODE_INNER (mode2);
21828 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
21829 double to intermix unless -mfloat128-convert. */
21830 if (mode1 == mode2)
21833 if (!TARGET_FLOAT128_CVT)
21835 if ((mode1 == KFmode && mode2 == IFmode)
21836 || (mode1 == IFmode && mode2 == KFmode))
21837 return N_("__float128 and __ibm128 cannot be used in the same "
21840 if (TARGET_IEEEQUAD
21841 && ((mode1 == IFmode && mode2 == TFmode)
21842 || (mode1 == TFmode && mode2 == IFmode)))
21843 return N_("__ibm128 and long double cannot be used in the same "
21846 if (!TARGET_IEEEQUAD
21847 && ((mode1 == KFmode && mode2 == TFmode)
21848 || (mode1 == TFmode && mode2 == KFmode)))
21849 return N_("__float128 and long double cannot be used in the same "
21857 /* Expand floating point conversion to/from __float128 and __ibm128. */
21860 rs6000_expand_float128_convert (rtx dest, rtx src, bool unsigned_p)
21862 machine_mode dest_mode = GET_MODE (dest);
21863 machine_mode src_mode = GET_MODE (src);
21864 convert_optab cvt = unknown_optab;
21865 bool do_move = false;
21866 rtx libfunc = NULL_RTX;
21868 typedef rtx (*rtx_2func_t) (rtx, rtx);
21869 rtx_2func_t hw_convert = (rtx_2func_t)0;
21873 rtx_2func_t from_df;
21874 rtx_2func_t from_sf;
21875 rtx_2func_t from_si_sign;
21876 rtx_2func_t from_si_uns;
21877 rtx_2func_t from_di_sign;
21878 rtx_2func_t from_di_uns;
21881 rtx_2func_t to_si_sign;
21882 rtx_2func_t to_si_uns;
21883 rtx_2func_t to_di_sign;
21884 rtx_2func_t to_di_uns;
21885 } hw_conversions[2] = {
21886 /* convertions to/from KFmode */
21888 gen_extenddfkf2_hw, /* KFmode <- DFmode. */
21889 gen_extendsfkf2_hw, /* KFmode <- SFmode. */
21890 gen_float_kfsi2_hw, /* KFmode <- SImode (signed). */
21891 gen_floatuns_kfsi2_hw, /* KFmode <- SImode (unsigned). */
21892 gen_float_kfdi2_hw, /* KFmode <- DImode (signed). */
21893 gen_floatuns_kfdi2_hw, /* KFmode <- DImode (unsigned). */
21894 gen_trunckfdf2_hw, /* DFmode <- KFmode. */
21895 gen_trunckfsf2_hw, /* SFmode <- KFmode. */
21896 gen_fix_kfsi2_hw, /* SImode <- KFmode (signed). */
21897 gen_fixuns_kfsi2_hw, /* SImode <- KFmode (unsigned). */
21898 gen_fix_kfdi2_hw, /* DImode <- KFmode (signed). */
21899 gen_fixuns_kfdi2_hw, /* DImode <- KFmode (unsigned). */
21902 /* convertions to/from TFmode */
21904 gen_extenddftf2_hw, /* TFmode <- DFmode. */
21905 gen_extendsftf2_hw, /* TFmode <- SFmode. */
21906 gen_float_tfsi2_hw, /* TFmode <- SImode (signed). */
21907 gen_floatuns_tfsi2_hw, /* TFmode <- SImode (unsigned). */
21908 gen_float_tfdi2_hw, /* TFmode <- DImode (signed). */
21909 gen_floatuns_tfdi2_hw, /* TFmode <- DImode (unsigned). */
21910 gen_trunctfdf2_hw, /* DFmode <- TFmode. */
21911 gen_trunctfsf2_hw, /* SFmode <- TFmode. */
21912 gen_fix_tfsi2_hw, /* SImode <- TFmode (signed). */
21913 gen_fixuns_tfsi2_hw, /* SImode <- TFmode (unsigned). */
21914 gen_fix_tfdi2_hw, /* DImode <- TFmode (signed). */
21915 gen_fixuns_tfdi2_hw, /* DImode <- TFmode (unsigned). */
21919 if (dest_mode == src_mode)
21920 gcc_unreachable ();
21922 /* Eliminate memory operations. */
21924 src = force_reg (src_mode, src);
21928 rtx tmp = gen_reg_rtx (dest_mode);
21929 rs6000_expand_float128_convert (tmp, src, unsigned_p);
21930 rs6000_emit_move (dest, tmp, dest_mode);
21934 /* Convert to IEEE 128-bit floating point. */
21935 if (FLOAT128_IEEE_P (dest_mode))
21937 if (dest_mode == KFmode)
21939 else if (dest_mode == TFmode)
21942 gcc_unreachable ();
21948 hw_convert = hw_conversions[kf_or_tf].from_df;
21953 hw_convert = hw_conversions[kf_or_tf].from_sf;
21959 if (FLOAT128_IBM_P (src_mode))
21968 cvt = ufloat_optab;
21969 hw_convert = hw_conversions[kf_or_tf].from_si_uns;
21973 cvt = sfloat_optab;
21974 hw_convert = hw_conversions[kf_or_tf].from_si_sign;
21981 cvt = ufloat_optab;
21982 hw_convert = hw_conversions[kf_or_tf].from_di_uns;
21986 cvt = sfloat_optab;
21987 hw_convert = hw_conversions[kf_or_tf].from_di_sign;
21992 gcc_unreachable ();
21996 /* Convert from IEEE 128-bit floating point. */
21997 else if (FLOAT128_IEEE_P (src_mode))
21999 if (src_mode == KFmode)
22001 else if (src_mode == TFmode)
22004 gcc_unreachable ();
22010 hw_convert = hw_conversions[kf_or_tf].to_df;
22015 hw_convert = hw_conversions[kf_or_tf].to_sf;
22021 if (FLOAT128_IBM_P (dest_mode))
22031 hw_convert = hw_conversions[kf_or_tf].to_si_uns;
22036 hw_convert = hw_conversions[kf_or_tf].to_si_sign;
22044 hw_convert = hw_conversions[kf_or_tf].to_di_uns;
22049 hw_convert = hw_conversions[kf_or_tf].to_di_sign;
22054 gcc_unreachable ();
22058 /* Both IBM format. */
22059 else if (FLOAT128_IBM_P (dest_mode) && FLOAT128_IBM_P (src_mode))
22063 gcc_unreachable ();
22065 /* Handle conversion between TFmode/KFmode/IFmode. */
22067 emit_insn (gen_rtx_SET (dest, gen_rtx_FLOAT_EXTEND (dest_mode, src)));
22069 /* Handle conversion if we have hardware support. */
22070 else if (TARGET_FLOAT128_HW && hw_convert)
22071 emit_insn ((hw_convert) (dest, src));
22073 /* Call an external function to do the conversion. */
22074 else if (cvt != unknown_optab)
22076 libfunc = convert_optab_libfunc (cvt, dest_mode, src_mode);
22077 gcc_assert (libfunc != NULL_RTX);
22079 dest2 = emit_library_call_value (libfunc, dest, LCT_CONST, dest_mode,
22082 gcc_assert (dest2 != NULL_RTX);
22083 if (!rtx_equal_p (dest, dest2))
22084 emit_move_insn (dest, dest2);
22088 gcc_unreachable ();
22094 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
22095 can be used as that dest register. Return the dest register. */
22098 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
22100 if (op2 == const0_rtx)
22103 if (GET_CODE (scratch) == SCRATCH)
22104 scratch = gen_reg_rtx (mode);
22106 if (logical_operand (op2, mode))
22107 emit_insn (gen_rtx_SET (scratch, gen_rtx_XOR (mode, op1, op2)));
22109 emit_insn (gen_rtx_SET (scratch,
22110 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
22116 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
22119 machine_mode op_mode;
22120 enum rtx_code cond_code;
22121 rtx result = operands[0];
22123 condition_rtx = rs6000_generate_compare (operands[1], mode);
22124 cond_code = GET_CODE (condition_rtx);
22126 if (cond_code == NE
22127 || cond_code == GE || cond_code == LE
22128 || cond_code == GEU || cond_code == LEU
22129 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
22131 rtx not_result = gen_reg_rtx (CCEQmode);
22132 rtx not_op, rev_cond_rtx;
22133 machine_mode cc_mode;
22135 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
22137 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
22138 SImode, XEXP (condition_rtx, 0), const0_rtx);
22139 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
22140 emit_insn (gen_rtx_SET (not_result, not_op));
22141 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
22144 op_mode = GET_MODE (XEXP (operands[1], 0));
22145 if (op_mode == VOIDmode)
22146 op_mode = GET_MODE (XEXP (operands[1], 1));
22148 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
22150 PUT_MODE (condition_rtx, DImode);
22151 convert_move (result, condition_rtx, 0);
22155 PUT_MODE (condition_rtx, SImode);
22156 emit_insn (gen_rtx_SET (result, condition_rtx));
22160 /* Emit a branch of kind CODE to location LOC. */
22163 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
22165 rtx condition_rtx, loc_ref;
22167 condition_rtx = rs6000_generate_compare (operands[0], mode);
22168 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
22169 emit_jump_insn (gen_rtx_SET (pc_rtx,
22170 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
22171 loc_ref, pc_rtx)));
22174 /* Return the string to output a conditional branch to LABEL, which is
22175 the operand template of the label, or NULL if the branch is really a
22176 conditional return.
22178 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
22179 condition code register and its mode specifies what kind of
22180 comparison we made.
22182 REVERSED is nonzero if we should reverse the sense of the comparison.
22184 INSN is the insn. */
22187 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
22189 static char string[64];
22190 enum rtx_code code = GET_CODE (op);
22191 rtx cc_reg = XEXP (op, 0);
22192 machine_mode mode = GET_MODE (cc_reg);
22193 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
22194 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
22195 int really_reversed = reversed ^ need_longbranch;
22201 validate_condition_mode (code, mode);
22203 /* Work out which way this really branches. We could use
22204 reverse_condition_maybe_unordered here always but this
22205 makes the resulting assembler clearer. */
22206 if (really_reversed)
22208 /* Reversal of FP compares takes care -- an ordered compare
22209 becomes an unordered compare and vice versa. */
22210 if (mode == CCFPmode)
22211 code = reverse_condition_maybe_unordered (code);
22213 code = reverse_condition (code);
22218 /* Not all of these are actually distinct opcodes, but
22219 we distinguish them for clarity of the resulting assembler. */
22220 case NE: case LTGT:
22221 ccode = "ne"; break;
22222 case EQ: case UNEQ:
22223 ccode = "eq"; break;
22225 ccode = "ge"; break;
22226 case GT: case GTU: case UNGT:
22227 ccode = "gt"; break;
22229 ccode = "le"; break;
22230 case LT: case LTU: case UNLT:
22231 ccode = "lt"; break;
22232 case UNORDERED: ccode = "un"; break;
22233 case ORDERED: ccode = "nu"; break;
22234 case UNGE: ccode = "nl"; break;
22235 case UNLE: ccode = "ng"; break;
22237 gcc_unreachable ();
22240 /* Maybe we have a guess as to how likely the branch is. */
22242 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
22243 if (note != NULL_RTX)
22245 /* PROB is the difference from 50%. */
22246 int prob = profile_probability::from_reg_br_prob_note (XINT (note, 0))
22247 .to_reg_br_prob_base () - REG_BR_PROB_BASE / 2;
22249 /* Only hint for highly probable/improbable branches on newer cpus when
22250 we have real profile data, as static prediction overrides processor
22251 dynamic prediction. For older cpus we may as well always hint, but
22252 assume not taken for branches that are very close to 50% as a
22253 mispredicted taken branch is more expensive than a
22254 mispredicted not-taken branch. */
22255 if (rs6000_always_hint
22256 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
22257 && (profile_status_for_fn (cfun) != PROFILE_GUESSED)
22258 && br_prob_note_reliable_p (note)))
22260 if (abs (prob) > REG_BR_PROB_BASE / 20
22261 && ((prob > 0) ^ need_longbranch))
22269 s += sprintf (s, "b%slr%s ", ccode, pred);
22271 s += sprintf (s, "b%s%s ", ccode, pred);
22273 /* We need to escape any '%' characters in the reg_names string.
22274 Assume they'd only be the first character.... */
22275 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
22277 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
22281 /* If the branch distance was too far, we may have to use an
22282 unconditional branch to go the distance. */
22283 if (need_longbranch)
22284 s += sprintf (s, ",$+8\n\tb %s", label);
22286 s += sprintf (s, ",%s", label);
22292 /* Return insn for VSX or Altivec comparisons. */
22295 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
22298 machine_mode mode = GET_MODE (op0);
22306 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
22317 mask = gen_reg_rtx (mode);
22318 emit_insn (gen_rtx_SET (mask, gen_rtx_fmt_ee (code, mode, op0, op1)));
22325 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
22326 DMODE is expected destination mode. This is a recursive function. */
22329 rs6000_emit_vector_compare (enum rtx_code rcode,
22331 machine_mode dmode)
22334 bool swap_operands = false;
22335 bool try_again = false;
22337 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
22338 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
22340 /* See if the comparison works as is. */
22341 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22349 swap_operands = true;
22354 swap_operands = true;
22362 /* Invert condition and try again.
22363 e.g., A != B becomes ~(A==B). */
22365 enum rtx_code rev_code;
22366 enum insn_code nor_code;
22369 rev_code = reverse_condition_maybe_unordered (rcode);
22370 if (rev_code == UNKNOWN)
22373 nor_code = optab_handler (one_cmpl_optab, dmode);
22374 if (nor_code == CODE_FOR_nothing)
22377 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
22381 mask = gen_reg_rtx (dmode);
22382 emit_insn (GEN_FCN (nor_code) (mask, mask2));
22390 /* Try GT/GTU/LT/LTU OR EQ */
22393 enum insn_code ior_code;
22394 enum rtx_code new_code;
22415 gcc_unreachable ();
22418 ior_code = optab_handler (ior_optab, dmode);
22419 if (ior_code == CODE_FOR_nothing)
22422 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
22426 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
22430 mask = gen_reg_rtx (dmode);
22431 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
22442 std::swap (op0, op1);
22444 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
22449 /* You only get two chances. */
22453 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
22454 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
22455 operands for the relation operation COND. */
22458 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
22459 rtx cond, rtx cc_op0, rtx cc_op1)
22461 machine_mode dest_mode = GET_MODE (dest);
22462 machine_mode mask_mode = GET_MODE (cc_op0);
22463 enum rtx_code rcode = GET_CODE (cond);
22464 machine_mode cc_mode = CCmode;
22467 bool invert_move = false;
22469 if (VECTOR_UNIT_NONE_P (dest_mode))
22472 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
22473 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
22477 /* Swap operands if we can, and fall back to doing the operation as
22478 specified, and doing a NOR to invert the test. */
22484 /* Invert condition and try again.
22485 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
22486 invert_move = true;
22487 rcode = reverse_condition_maybe_unordered (rcode);
22488 if (rcode == UNKNOWN)
22494 if (GET_MODE_CLASS (mask_mode) == MODE_VECTOR_INT)
22496 /* Invert condition to avoid compound test. */
22497 invert_move = true;
22498 rcode = reverse_condition (rcode);
22506 /* Mark unsigned tests with CCUNSmode. */
22507 cc_mode = CCUNSmode;
22509 /* Invert condition to avoid compound test if necessary. */
22510 if (rcode == GEU || rcode == LEU)
22512 invert_move = true;
22513 rcode = reverse_condition (rcode);
22521 /* Get the vector mask for the given relational operations. */
22522 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
22528 std::swap (op_true, op_false);
22530 /* Optimize vec1 == vec2, to know the mask generates -1/0. */
22531 if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
22532 && (GET_CODE (op_true) == CONST_VECTOR
22533 || GET_CODE (op_false) == CONST_VECTOR))
22535 rtx constant_0 = CONST0_RTX (dest_mode);
22536 rtx constant_m1 = CONSTM1_RTX (dest_mode);
22538 if (op_true == constant_m1 && op_false == constant_0)
22540 emit_move_insn (dest, mask);
22544 else if (op_true == constant_0 && op_false == constant_m1)
22546 emit_insn (gen_rtx_SET (dest, gen_rtx_NOT (dest_mode, mask)));
22550 /* If we can't use the vector comparison directly, perhaps we can use
22551 the mask for the true or false fields, instead of loading up a
22553 if (op_true == constant_m1)
22556 if (op_false == constant_0)
22560 if (!REG_P (op_true) && !SUBREG_P (op_true))
22561 op_true = force_reg (dest_mode, op_true);
22563 if (!REG_P (op_false) && !SUBREG_P (op_false))
22564 op_false = force_reg (dest_mode, op_false);
22566 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
22567 CONST0_RTX (dest_mode));
22568 emit_insn (gen_rtx_SET (dest,
22569 gen_rtx_IF_THEN_ELSE (dest_mode,
22576 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
22577 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
22578 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
22579 hardware has no such operation. */
22582 rs6000_emit_p9_fp_minmax (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22584 enum rtx_code code = GET_CODE (op);
22585 rtx op0 = XEXP (op, 0);
22586 rtx op1 = XEXP (op, 1);
22587 machine_mode compare_mode = GET_MODE (op0);
22588 machine_mode result_mode = GET_MODE (dest);
22589 bool max_p = false;
22591 if (result_mode != compare_mode)
22594 if (code == GE || code == GT)
22596 else if (code == LE || code == LT)
22601 if (rtx_equal_p (op0, true_cond) && rtx_equal_p (op1, false_cond))
22604 else if (rtx_equal_p (op1, true_cond) && rtx_equal_p (op0, false_cond))
22610 rs6000_emit_minmax (dest, max_p ? SMAX : SMIN, op0, op1);
22614 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
22615 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
22616 operands of the last comparison is nonzero/true, FALSE_COND if it is
22617 zero/false. Return 0 if the hardware has no such operation. */
22620 rs6000_emit_p9_fp_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22622 enum rtx_code code = GET_CODE (op);
22623 rtx op0 = XEXP (op, 0);
22624 rtx op1 = XEXP (op, 1);
22625 machine_mode result_mode = GET_MODE (dest);
22630 if (!can_create_pseudo_p ())
22643 code = swap_condition (code);
22644 std::swap (op0, op1);
22651 /* Generate: [(parallel [(set (dest)
22652 (if_then_else (op (cmp1) (cmp2))
22655 (clobber (scratch))])]. */
22657 compare_rtx = gen_rtx_fmt_ee (code, CCFPmode, op0, op1);
22658 cmove_rtx = gen_rtx_SET (dest,
22659 gen_rtx_IF_THEN_ELSE (result_mode,
22664 clobber_rtx = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (V2DImode));
22665 emit_insn (gen_rtx_PARALLEL (VOIDmode,
22666 gen_rtvec (2, cmove_rtx, clobber_rtx)));
22671 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
22672 operands of the last comparison is nonzero/true, FALSE_COND if it
22673 is zero/false. Return 0 if the hardware has no such operation. */
22676 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22678 enum rtx_code code = GET_CODE (op);
22679 rtx op0 = XEXP (op, 0);
22680 rtx op1 = XEXP (op, 1);
22681 machine_mode compare_mode = GET_MODE (op0);
22682 machine_mode result_mode = GET_MODE (dest);
22684 bool is_against_zero;
22686 /* These modes should always match. */
22687 if (GET_MODE (op1) != compare_mode
22688 /* In the isel case however, we can use a compare immediate, so
22689 op1 may be a small constant. */
22690 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
22692 if (GET_MODE (true_cond) != result_mode)
22694 if (GET_MODE (false_cond) != result_mode)
22697 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
22698 if (TARGET_P9_MINMAX
22699 && (compare_mode == SFmode || compare_mode == DFmode)
22700 && (result_mode == SFmode || result_mode == DFmode))
22702 if (rs6000_emit_p9_fp_minmax (dest, op, true_cond, false_cond))
22705 if (rs6000_emit_p9_fp_cmove (dest, op, true_cond, false_cond))
22709 /* Don't allow using floating point comparisons for integer results for
22711 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
22714 /* First, work out if the hardware can do this at all, or
22715 if it's too slow.... */
22716 if (!FLOAT_MODE_P (compare_mode))
22719 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
22723 is_against_zero = op1 == CONST0_RTX (compare_mode);
22725 /* A floating-point subtract might overflow, underflow, or produce
22726 an inexact result, thus changing the floating-point flags, so it
22727 can't be generated if we care about that. It's safe if one side
22728 of the construct is zero, since then no subtract will be
22730 if (SCALAR_FLOAT_MODE_P (compare_mode)
22731 && flag_trapping_math && ! is_against_zero)
22734 /* Eliminate half of the comparisons by switching operands, this
22735 makes the remaining code simpler. */
22736 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
22737 || code == LTGT || code == LT || code == UNLE)
22739 code = reverse_condition_maybe_unordered (code);
22741 true_cond = false_cond;
22745 /* UNEQ and LTGT take four instructions for a comparison with zero,
22746 it'll probably be faster to use a branch here too. */
22747 if (code == UNEQ && HONOR_NANS (compare_mode))
22750 /* We're going to try to implement comparisons by performing
22751 a subtract, then comparing against zero. Unfortunately,
22752 Inf - Inf is NaN which is not zero, and so if we don't
22753 know that the operand is finite and the comparison
22754 would treat EQ different to UNORDERED, we can't do it. */
22755 if (HONOR_INFINITIES (compare_mode)
22756 && code != GT && code != UNGE
22757 && (!CONST_DOUBLE_P (op1)
22758 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1)))
22759 /* Constructs of the form (a OP b ? a : b) are safe. */
22760 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
22761 || (! rtx_equal_p (op0, true_cond)
22762 && ! rtx_equal_p (op1, true_cond))))
22765 /* At this point we know we can use fsel. */
22767 /* Reduce the comparison to a comparison against zero. */
22768 if (! is_against_zero)
22770 temp = gen_reg_rtx (compare_mode);
22771 emit_insn (gen_rtx_SET (temp, gen_rtx_MINUS (compare_mode, op0, op1)));
22773 op1 = CONST0_RTX (compare_mode);
22776 /* If we don't care about NaNs we can reduce some of the comparisons
22777 down to faster ones. */
22778 if (! HONOR_NANS (compare_mode))
22784 true_cond = false_cond;
22797 /* Now, reduce everything down to a GE. */
22804 temp = gen_reg_rtx (compare_mode);
22805 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22810 temp = gen_reg_rtx (compare_mode);
22811 emit_insn (gen_rtx_SET (temp, gen_rtx_ABS (compare_mode, op0)));
22816 temp = gen_reg_rtx (compare_mode);
22817 emit_insn (gen_rtx_SET (temp,
22818 gen_rtx_NEG (compare_mode,
22819 gen_rtx_ABS (compare_mode, op0))));
22824 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
22825 temp = gen_reg_rtx (result_mode);
22826 emit_insn (gen_rtx_SET (temp,
22827 gen_rtx_IF_THEN_ELSE (result_mode,
22828 gen_rtx_GE (VOIDmode,
22830 true_cond, false_cond)));
22831 false_cond = true_cond;
22834 temp = gen_reg_rtx (compare_mode);
22835 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22840 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
22841 temp = gen_reg_rtx (result_mode);
22842 emit_insn (gen_rtx_SET (temp,
22843 gen_rtx_IF_THEN_ELSE (result_mode,
22844 gen_rtx_GE (VOIDmode,
22846 true_cond, false_cond)));
22847 true_cond = false_cond;
22850 temp = gen_reg_rtx (compare_mode);
22851 emit_insn (gen_rtx_SET (temp, gen_rtx_NEG (compare_mode, op0)));
22856 gcc_unreachable ();
22859 emit_insn (gen_rtx_SET (dest,
22860 gen_rtx_IF_THEN_ELSE (result_mode,
22861 gen_rtx_GE (VOIDmode,
22863 true_cond, false_cond)));
22867 /* Same as above, but for ints (isel). */
22870 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
22872 rtx condition_rtx, cr;
22873 machine_mode mode = GET_MODE (dest);
22874 enum rtx_code cond_code;
22875 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
22878 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
22881 /* We still have to do the compare, because isel doesn't do a
22882 compare, it just looks at the CRx bits set by a previous compare
22884 condition_rtx = rs6000_generate_compare (op, mode);
22885 cond_code = GET_CODE (condition_rtx);
22886 cr = XEXP (condition_rtx, 0);
22887 signedp = GET_MODE (cr) == CCmode;
22889 isel_func = (mode == SImode
22890 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
22891 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
22895 case LT: case GT: case LTU: case GTU: case EQ:
22896 /* isel handles these directly. */
22900 /* We need to swap the sense of the comparison. */
22902 std::swap (false_cond, true_cond);
22903 PUT_CODE (condition_rtx, reverse_condition (cond_code));
22908 false_cond = force_reg (mode, false_cond);
22909 if (true_cond != const0_rtx)
22910 true_cond = force_reg (mode, true_cond);
22912 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
22918 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
22920 machine_mode mode = GET_MODE (op0);
22924 /* VSX/altivec have direct min/max insns. */
22925 if ((code == SMAX || code == SMIN)
22926 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
22927 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
22929 emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1)));
22933 if (code == SMAX || code == SMIN)
22938 if (code == SMAX || code == UMAX)
22939 target = emit_conditional_move (dest, c, op0, op1, mode,
22940 op0, op1, mode, 0);
22942 target = emit_conditional_move (dest, c, op0, op1, mode,
22943 op1, op0, mode, 0);
22944 gcc_assert (target);
22945 if (target != dest)
22946 emit_move_insn (dest, target);
22949 /* A subroutine of the atomic operation splitters. Jump to LABEL if
22950 COND is true. Mark the jump as unlikely to be taken. */
22953 emit_unlikely_jump (rtx cond, rtx label)
22955 rtx x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
22956 rtx_insn *insn = emit_jump_insn (gen_rtx_SET (pc_rtx, x));
22957 add_reg_br_prob_note (insn, profile_probability::very_unlikely ());
22960 /* A subroutine of the atomic operation splitters. Emit a load-locked
22961 instruction in MODE. For QI/HImode, possibly use a pattern than includes
22962 the zero_extend operation. */
22965 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
22967 rtx (*fn) (rtx, rtx) = NULL;
22972 fn = gen_load_lockedqi;
22975 fn = gen_load_lockedhi;
22978 if (GET_MODE (mem) == QImode)
22979 fn = gen_load_lockedqi_si;
22980 else if (GET_MODE (mem) == HImode)
22981 fn = gen_load_lockedhi_si;
22983 fn = gen_load_lockedsi;
22986 fn = gen_load_lockeddi;
22989 fn = gen_load_lockedti;
22992 gcc_unreachable ();
22994 emit_insn (fn (reg, mem));
22997 /* A subroutine of the atomic operation splitters. Emit a store-conditional
22998 instruction in MODE. */
23001 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
23003 rtx (*fn) (rtx, rtx, rtx) = NULL;
23008 fn = gen_store_conditionalqi;
23011 fn = gen_store_conditionalhi;
23014 fn = gen_store_conditionalsi;
23017 fn = gen_store_conditionaldi;
23020 fn = gen_store_conditionalti;
23023 gcc_unreachable ();
23026 /* Emit sync before stwcx. to address PPC405 Erratum. */
23027 if (PPC405_ERRATUM77)
23028 emit_insn (gen_hwsync ());
23030 emit_insn (fn (res, mem, val));
23033 /* Expand barriers before and after a load_locked/store_cond sequence. */
23036 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
23038 rtx addr = XEXP (mem, 0);
23040 if (!legitimate_indirect_address_p (addr, reload_completed)
23041 && !legitimate_indexed_address_p (addr, reload_completed))
23043 addr = force_reg (Pmode, addr);
23044 mem = replace_equiv_address_nv (mem, addr);
23049 case MEMMODEL_RELAXED:
23050 case MEMMODEL_CONSUME:
23051 case MEMMODEL_ACQUIRE:
23053 case MEMMODEL_RELEASE:
23054 case MEMMODEL_ACQ_REL:
23055 emit_insn (gen_lwsync ());
23057 case MEMMODEL_SEQ_CST:
23058 emit_insn (gen_hwsync ());
23061 gcc_unreachable ();
23067 rs6000_post_atomic_barrier (enum memmodel model)
23071 case MEMMODEL_RELAXED:
23072 case MEMMODEL_CONSUME:
23073 case MEMMODEL_RELEASE:
23075 case MEMMODEL_ACQUIRE:
23076 case MEMMODEL_ACQ_REL:
23077 case MEMMODEL_SEQ_CST:
23078 emit_insn (gen_isync ());
23081 gcc_unreachable ();
23085 /* A subroutine of the various atomic expanders. For sub-word operations,
23086 we must adjust things to operate on SImode. Given the original MEM,
23087 return a new aligned memory. Also build and return the quantities by
23088 which to shift and mask. */
23091 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
23093 rtx addr, align, shift, mask, mem;
23094 HOST_WIDE_INT shift_mask;
23095 machine_mode mode = GET_MODE (orig_mem);
23097 /* For smaller modes, we have to implement this via SImode. */
23098 shift_mask = (mode == QImode ? 0x18 : 0x10);
23100 addr = XEXP (orig_mem, 0);
23101 addr = force_reg (GET_MODE (addr), addr);
23103 /* Aligned memory containing subword. Generate a new memory. We
23104 do not want any of the existing MEM_ATTR data, as we're now
23105 accessing memory outside the original object. */
23106 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
23107 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23108 mem = gen_rtx_MEM (SImode, align);
23109 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
23110 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
23111 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
23113 /* Shift amount for subword relative to aligned word. */
23114 shift = gen_reg_rtx (SImode);
23115 addr = gen_lowpart (SImode, addr);
23116 rtx tmp = gen_reg_rtx (SImode);
23117 emit_insn (gen_ashlsi3 (tmp, addr, GEN_INT (3)));
23118 emit_insn (gen_andsi3 (shift, tmp, GEN_INT (shift_mask)));
23119 if (BYTES_BIG_ENDIAN)
23120 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
23121 shift, 1, OPTAB_LIB_WIDEN);
23124 /* Mask for insertion. */
23125 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
23126 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
23132 /* A subroutine of the various atomic expanders. For sub-word operands,
23133 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
23136 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
23140 x = gen_reg_rtx (SImode);
23141 emit_insn (gen_rtx_SET (x, gen_rtx_AND (SImode,
23142 gen_rtx_NOT (SImode, mask),
23145 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
23150 /* A subroutine of the various atomic expanders. For sub-word operands,
23151 extract WIDE to NARROW via SHIFT. */
23154 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
23156 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
23157 wide, 1, OPTAB_LIB_WIDEN);
23158 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
23161 /* Expand an atomic compare and swap operation. */
23164 rs6000_expand_atomic_compare_and_swap (rtx operands[])
23166 rtx boolval, retval, mem, oldval, newval, cond;
23167 rtx label1, label2, x, mask, shift;
23168 machine_mode mode, orig_mode;
23169 enum memmodel mod_s, mod_f;
23172 boolval = operands[0];
23173 retval = operands[1];
23175 oldval = operands[3];
23176 newval = operands[4];
23177 is_weak = (INTVAL (operands[5]) != 0);
23178 mod_s = memmodel_base (INTVAL (operands[6]));
23179 mod_f = memmodel_base (INTVAL (operands[7]));
23180 orig_mode = mode = GET_MODE (mem);
23182 mask = shift = NULL_RTX;
23183 if (mode == QImode || mode == HImode)
23185 /* Before power8, we didn't have access to lbarx/lharx, so generate a
23186 lwarx and shift/mask operations. With power8, we need to do the
23187 comparison in SImode, but the store is still done in QI/HImode. */
23188 oldval = convert_modes (SImode, mode, oldval, 1);
23190 if (!TARGET_SYNC_HI_QI)
23192 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23194 /* Shift and mask OLDVAL into position with the word. */
23195 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
23196 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23198 /* Shift and mask NEWVAL into position within the word. */
23199 newval = convert_modes (SImode, mode, newval, 1);
23200 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
23201 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23204 /* Prepare to adjust the return value. */
23205 retval = gen_reg_rtx (SImode);
23208 else if (reg_overlap_mentioned_p (retval, oldval))
23209 oldval = copy_to_reg (oldval);
23211 if (mode != TImode && !reg_or_short_operand (oldval, mode))
23212 oldval = copy_to_mode_reg (mode, oldval);
23214 if (reg_overlap_mentioned_p (retval, newval))
23215 newval = copy_to_reg (newval);
23217 mem = rs6000_pre_atomic_barrier (mem, mod_s);
23222 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23223 emit_label (XEXP (label1, 0));
23225 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23227 emit_load_locked (mode, retval, mem);
23231 x = expand_simple_binop (SImode, AND, retval, mask,
23232 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23234 cond = gen_reg_rtx (CCmode);
23235 /* If we have TImode, synthesize a comparison. */
23236 if (mode != TImode)
23237 x = gen_rtx_COMPARE (CCmode, x, oldval);
23240 rtx xor1_result = gen_reg_rtx (DImode);
23241 rtx xor2_result = gen_reg_rtx (DImode);
23242 rtx or_result = gen_reg_rtx (DImode);
23243 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
23244 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
23245 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
23246 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
23248 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
23249 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
23250 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
23251 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
23254 emit_insn (gen_rtx_SET (cond, x));
23256 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23257 emit_unlikely_jump (x, label2);
23261 x = rs6000_mask_atomic_subword (retval, newval, mask);
23263 emit_store_conditional (orig_mode, cond, mem, x);
23267 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23268 emit_unlikely_jump (x, label1);
23271 if (!is_mm_relaxed (mod_f))
23272 emit_label (XEXP (label2, 0));
23274 rs6000_post_atomic_barrier (mod_s);
23276 if (is_mm_relaxed (mod_f))
23277 emit_label (XEXP (label2, 0));
23280 rs6000_finish_atomic_subword (operands[1], retval, shift);
23281 else if (mode != GET_MODE (operands[1]))
23282 convert_move (operands[1], retval, 1);
23284 /* In all cases, CR0 contains EQ on success, and NE on failure. */
23285 x = gen_rtx_EQ (SImode, cond, const0_rtx);
23286 emit_insn (gen_rtx_SET (boolval, x));
23289 /* Expand an atomic exchange operation. */
23292 rs6000_expand_atomic_exchange (rtx operands[])
23294 rtx retval, mem, val, cond;
23296 enum memmodel model;
23297 rtx label, x, mask, shift;
23299 retval = operands[0];
23302 model = memmodel_base (INTVAL (operands[3]));
23303 mode = GET_MODE (mem);
23305 mask = shift = NULL_RTX;
23306 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
23308 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23310 /* Shift and mask VAL into position with the word. */
23311 val = convert_modes (SImode, mode, val, 1);
23312 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23313 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23315 /* Prepare to adjust the return value. */
23316 retval = gen_reg_rtx (SImode);
23320 mem = rs6000_pre_atomic_barrier (mem, model);
23322 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
23323 emit_label (XEXP (label, 0));
23325 emit_load_locked (mode, retval, mem);
23329 x = rs6000_mask_atomic_subword (retval, val, mask);
23331 cond = gen_reg_rtx (CCmode);
23332 emit_store_conditional (mode, cond, mem, x);
23334 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23335 emit_unlikely_jump (x, label);
23337 rs6000_post_atomic_barrier (model);
23340 rs6000_finish_atomic_subword (operands[0], retval, shift);
23343 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
23344 to perform. MEM is the memory on which to operate. VAL is the second
23345 operand of the binary operator. BEFORE and AFTER are optional locations to
23346 return the value of MEM either before of after the operation. MODEL_RTX
23347 is a CONST_INT containing the memory model to use. */
23350 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
23351 rtx orig_before, rtx orig_after, rtx model_rtx)
23353 enum memmodel model = memmodel_base (INTVAL (model_rtx));
23354 machine_mode mode = GET_MODE (mem);
23355 machine_mode store_mode = mode;
23356 rtx label, x, cond, mask, shift;
23357 rtx before = orig_before, after = orig_after;
23359 mask = shift = NULL_RTX;
23360 /* On power8, we want to use SImode for the operation. On previous systems,
23361 use the operation in a subword and shift/mask to get the proper byte or
23363 if (mode == QImode || mode == HImode)
23365 if (TARGET_SYNC_HI_QI)
23367 val = convert_modes (SImode, mode, val, 1);
23369 /* Prepare to adjust the return value. */
23370 before = gen_reg_rtx (SImode);
23372 after = gen_reg_rtx (SImode);
23377 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
23379 /* Shift and mask VAL into position with the word. */
23380 val = convert_modes (SImode, mode, val, 1);
23381 val = expand_simple_binop (SImode, ASHIFT, val, shift,
23382 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23388 /* We've already zero-extended VAL. That is sufficient to
23389 make certain that it does not affect other bits. */
23394 /* If we make certain that all of the other bits in VAL are
23395 set, that will be sufficient to not affect other bits. */
23396 x = gen_rtx_NOT (SImode, mask);
23397 x = gen_rtx_IOR (SImode, x, val);
23398 emit_insn (gen_rtx_SET (val, x));
23405 /* These will all affect bits outside the field and need
23406 adjustment via MASK within the loop. */
23410 gcc_unreachable ();
23413 /* Prepare to adjust the return value. */
23414 before = gen_reg_rtx (SImode);
23416 after = gen_reg_rtx (SImode);
23417 store_mode = mode = SImode;
23421 mem = rs6000_pre_atomic_barrier (mem, model);
23423 label = gen_label_rtx ();
23424 emit_label (label);
23425 label = gen_rtx_LABEL_REF (VOIDmode, label);
23427 if (before == NULL_RTX)
23428 before = gen_reg_rtx (mode);
23430 emit_load_locked (mode, before, mem);
23434 x = expand_simple_binop (mode, AND, before, val,
23435 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23436 after = expand_simple_unop (mode, NOT, x, after, 1);
23440 after = expand_simple_binop (mode, code, before, val,
23441 after, 1, OPTAB_LIB_WIDEN);
23447 x = expand_simple_binop (SImode, AND, after, mask,
23448 NULL_RTX, 1, OPTAB_LIB_WIDEN);
23449 x = rs6000_mask_atomic_subword (before, x, mask);
23451 else if (store_mode != mode)
23452 x = convert_modes (store_mode, mode, x, 1);
23454 cond = gen_reg_rtx (CCmode);
23455 emit_store_conditional (store_mode, cond, mem, x);
23457 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
23458 emit_unlikely_jump (x, label);
23460 rs6000_post_atomic_barrier (model);
23464 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
23465 then do the calcuations in a SImode register. */
23467 rs6000_finish_atomic_subword (orig_before, before, shift);
23469 rs6000_finish_atomic_subword (orig_after, after, shift);
23471 else if (store_mode != mode)
23473 /* QImode/HImode on machines with lbarx/lharx where we do the native
23474 operation and then do the calcuations in a SImode register. */
23476 convert_move (orig_before, before, 1);
23478 convert_move (orig_after, after, 1);
23480 else if (orig_after && after != orig_after)
23481 emit_move_insn (orig_after, after);
23484 /* Emit instructions to move SRC to DST. Called by splitters for
23485 multi-register moves. It will emit at most one instruction for
23486 each register that is accessed; that is, it won't emit li/lis pairs
23487 (or equivalent for 64-bit code). One of SRC or DST must be a hard
23491 rs6000_split_multireg_move (rtx dst, rtx src)
23493 /* The register number of the first register being moved. */
23495 /* The mode that is to be moved. */
23497 /* The mode that the move is being done in, and its size. */
23498 machine_mode reg_mode;
23500 /* The number of registers that will be moved. */
23503 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
23504 mode = GET_MODE (dst);
23505 nregs = hard_regno_nregs (reg, mode);
23506 if (FP_REGNO_P (reg))
23507 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
23508 (TARGET_HARD_FLOAT ? DFmode : SFmode);
23509 else if (ALTIVEC_REGNO_P (reg))
23510 reg_mode = V16QImode;
23512 reg_mode = word_mode;
23513 reg_mode_size = GET_MODE_SIZE (reg_mode);
23515 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
23517 /* TDmode residing in FP registers is special, since the ISA requires that
23518 the lower-numbered word of a register pair is always the most significant
23519 word, even in little-endian mode. This does not match the usual subreg
23520 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
23521 the appropriate constituent registers "by hand" in little-endian mode.
23523 Note we do not need to check for destructive overlap here since TDmode
23524 can only reside in even/odd register pairs. */
23525 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
23530 for (i = 0; i < nregs; i++)
23532 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
23533 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
23535 p_src = simplify_gen_subreg (reg_mode, src, mode,
23536 i * reg_mode_size);
23538 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
23539 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
23541 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
23542 i * reg_mode_size);
23544 emit_insn (gen_rtx_SET (p_dst, p_src));
23550 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
23552 /* Move register range backwards, if we might have destructive
23555 for (i = nregs - 1; i >= 0; i--)
23556 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23557 i * reg_mode_size),
23558 simplify_gen_subreg (reg_mode, src, mode,
23559 i * reg_mode_size)));
23565 bool used_update = false;
23566 rtx restore_basereg = NULL_RTX;
23568 if (MEM_P (src) && INT_REGNO_P (reg))
23572 if (GET_CODE (XEXP (src, 0)) == PRE_INC
23573 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
23576 breg = XEXP (XEXP (src, 0), 0);
23577 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
23578 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
23579 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
23580 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23581 src = replace_equiv_address (src, breg);
23583 else if (! rs6000_offsettable_memref_p (src, reg_mode, true))
23585 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
23587 rtx basereg = XEXP (XEXP (src, 0), 0);
23590 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
23591 emit_insn (gen_rtx_SET (ndst,
23592 gen_rtx_MEM (reg_mode,
23594 used_update = true;
23597 emit_insn (gen_rtx_SET (basereg,
23598 XEXP (XEXP (src, 0), 1)));
23599 src = replace_equiv_address (src, basereg);
23603 rtx basereg = gen_rtx_REG (Pmode, reg);
23604 emit_insn (gen_rtx_SET (basereg, XEXP (src, 0)));
23605 src = replace_equiv_address (src, basereg);
23609 breg = XEXP (src, 0);
23610 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
23611 breg = XEXP (breg, 0);
23613 /* If the base register we are using to address memory is
23614 also a destination reg, then change that register last. */
23616 && REGNO (breg) >= REGNO (dst)
23617 && REGNO (breg) < REGNO (dst) + nregs)
23618 j = REGNO (breg) - REGNO (dst);
23620 else if (MEM_P (dst) && INT_REGNO_P (reg))
23624 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
23625 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
23628 breg = XEXP (XEXP (dst, 0), 0);
23629 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
23630 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
23631 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
23633 /* We have to update the breg before doing the store.
23634 Use store with update, if available. */
23638 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23639 emit_insn (TARGET_32BIT
23640 ? (TARGET_POWERPC64
23641 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
23642 : gen_movsi_si_update (breg, breg, delta_rtx, nsrc))
23643 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
23644 used_update = true;
23647 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
23648 dst = replace_equiv_address (dst, breg);
23650 else if (!rs6000_offsettable_memref_p (dst, reg_mode, true)
23651 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
23653 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
23655 rtx basereg = XEXP (XEXP (dst, 0), 0);
23658 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
23659 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode,
23662 used_update = true;
23665 emit_insn (gen_rtx_SET (basereg,
23666 XEXP (XEXP (dst, 0), 1)));
23667 dst = replace_equiv_address (dst, basereg);
23671 rtx basereg = XEXP (XEXP (dst, 0), 0);
23672 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
23673 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
23675 && REG_P (offsetreg)
23676 && REGNO (basereg) != REGNO (offsetreg));
23677 if (REGNO (basereg) == 0)
23679 rtx tmp = offsetreg;
23680 offsetreg = basereg;
23683 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
23684 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
23685 dst = replace_equiv_address (dst, basereg);
23688 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
23689 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode, true));
23692 for (i = 0; i < nregs; i++)
23694 /* Calculate index to next subword. */
23699 /* If compiler already emitted move of first word by
23700 store with update, no need to do anything. */
23701 if (j == 0 && used_update)
23704 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode, dst, mode,
23705 j * reg_mode_size),
23706 simplify_gen_subreg (reg_mode, src, mode,
23707 j * reg_mode_size)));
23709 if (restore_basereg != NULL_RTX)
23710 emit_insn (restore_basereg);
23715 /* This page contains routines that are used to determine what the
23716 function prologue and epilogue code will do and write them out. */
23718 /* Determine whether the REG is really used. */
23721 save_reg_p (int reg)
23723 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM && !TARGET_SINGLE_PIC_BASE)
23725 /* When calling eh_return, we must return true for all the cases
23726 where conditional_register_usage marks the PIC offset reg
23727 call used or fixed. */
23728 if (crtl->calls_eh_return
23729 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
23730 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
23731 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
23734 /* We need to mark the PIC offset register live for the same
23735 conditions as it is set up in rs6000_emit_prologue, or
23736 otherwise it won't be saved before we clobber it. */
23737 if (TARGET_TOC && TARGET_MINIMAL_TOC
23738 && !constant_pool_empty_p ())
23741 if (DEFAULT_ABI == ABI_V4
23742 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
23743 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
23746 if (DEFAULT_ABI == ABI_DARWIN
23747 && flag_pic && crtl->uses_pic_offset_table)
23751 return !call_used_regs[reg] && df_regs_ever_live_p (reg);
23754 /* Return the first fixed-point register that is required to be
23755 saved. 32 if none. */
23758 first_reg_to_save (void)
23762 /* Find lowest numbered live register. */
23763 for (first_reg = 13; first_reg <= 31; first_reg++)
23764 if (save_reg_p (first_reg))
23770 /* Similar, for FP regs. */
23773 first_fp_reg_to_save (void)
23777 /* Find lowest numbered live register. */
23778 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
23779 if (save_reg_p (first_reg))
23785 /* Similar, for AltiVec regs. */
23788 first_altivec_reg_to_save (void)
23792 /* Stack frame remains as is unless we are in AltiVec ABI. */
23793 if (! TARGET_ALTIVEC_ABI)
23794 return LAST_ALTIVEC_REGNO + 1;
23796 /* On Darwin, the unwind routines are compiled without
23797 TARGET_ALTIVEC, and use save_world to save/restore the
23798 altivec registers when necessary. */
23799 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23800 && ! TARGET_ALTIVEC)
23801 return FIRST_ALTIVEC_REGNO + 20;
23803 /* Find lowest numbered live register. */
23804 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
23805 if (save_reg_p (i))
23811 /* Return a 32-bit mask of the AltiVec registers we need to set in
23812 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
23813 the 32-bit word is 0. */
23815 static unsigned int
23816 compute_vrsave_mask (void)
23818 unsigned int i, mask = 0;
23820 /* On Darwin, the unwind routines are compiled without
23821 TARGET_ALTIVEC, and use save_world to save/restore the
23822 call-saved altivec registers when necessary. */
23823 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
23824 && ! TARGET_ALTIVEC)
23827 /* First, find out if we use _any_ altivec registers. */
23828 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
23829 if (df_regs_ever_live_p (i))
23830 mask |= ALTIVEC_REG_BIT (i);
23835 /* Next, remove the argument registers from the set. These must
23836 be in the VRSAVE mask set by the caller, so we don't need to add
23837 them in again. More importantly, the mask we compute here is
23838 used to generate CLOBBERs in the set_vrsave insn, and we do not
23839 wish the argument registers to die. */
23840 for (i = ALTIVEC_ARG_MIN_REG; i < (unsigned) crtl->args.info.vregno; i++)
23841 mask &= ~ALTIVEC_REG_BIT (i);
23843 /* Similarly, remove the return value from the set. */
23846 diddle_return_value (is_altivec_return_reg, &yes);
23848 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
23854 /* For a very restricted set of circumstances, we can cut down the
23855 size of prologues/epilogues by calling our own save/restore-the-world
23859 compute_save_world_info (rs6000_stack_t *info)
23861 info->world_save_p = 1;
23863 = (WORLD_SAVE_P (info)
23864 && DEFAULT_ABI == ABI_DARWIN
23865 && !cfun->has_nonlocal_label
23866 && info->first_fp_reg_save == FIRST_SAVED_FP_REGNO
23867 && info->first_gp_reg_save == FIRST_SAVED_GP_REGNO
23868 && info->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
23869 && info->cr_save_p);
23871 /* This will not work in conjunction with sibcalls. Make sure there
23872 are none. (This check is expensive, but seldom executed.) */
23873 if (WORLD_SAVE_P (info))
23876 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
23877 if (CALL_P (insn) && SIBLING_CALL_P (insn))
23879 info->world_save_p = 0;
23884 if (WORLD_SAVE_P (info))
23886 /* Even if we're not touching VRsave, make sure there's room on the
23887 stack for it, if it looks like we're calling SAVE_WORLD, which
23888 will attempt to save it. */
23889 info->vrsave_size = 4;
23891 /* If we are going to save the world, we need to save the link register too. */
23892 info->lr_save_p = 1;
23894 /* "Save" the VRsave register too if we're saving the world. */
23895 if (info->vrsave_mask == 0)
23896 info->vrsave_mask = compute_vrsave_mask ();
23898 /* Because the Darwin register save/restore routines only handle
23899 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
23901 gcc_assert (info->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
23902 && (info->first_altivec_reg_save
23903 >= FIRST_SAVED_ALTIVEC_REGNO));
23911 is_altivec_return_reg (rtx reg, void *xyes)
23913 bool *yes = (bool *) xyes;
23914 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
23919 /* Return whether REG is a global user reg or has been specifed by
23920 -ffixed-REG. We should not restore these, and so cannot use
23921 lmw or out-of-line restore functions if there are any. We also
23922 can't save them (well, emit frame notes for them), because frame
23923 unwinding during exception handling will restore saved registers. */
23926 fixed_reg_p (int reg)
23928 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
23929 backend sets it, overriding anything the user might have given. */
23930 if (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
23931 && ((DEFAULT_ABI == ABI_V4 && flag_pic)
23932 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
23933 || (TARGET_TOC && TARGET_MINIMAL_TOC)))
23936 return fixed_regs[reg];
23939 /* Determine the strategy for savings/restoring registers. */
23942 SAVE_MULTIPLE = 0x1,
23943 SAVE_INLINE_GPRS = 0x2,
23944 SAVE_INLINE_FPRS = 0x4,
23945 SAVE_NOINLINE_GPRS_SAVES_LR = 0x8,
23946 SAVE_NOINLINE_FPRS_SAVES_LR = 0x10,
23947 SAVE_INLINE_VRS = 0x20,
23948 REST_MULTIPLE = 0x100,
23949 REST_INLINE_GPRS = 0x200,
23950 REST_INLINE_FPRS = 0x400,
23951 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x800,
23952 REST_INLINE_VRS = 0x1000
23956 rs6000_savres_strategy (rs6000_stack_t *info,
23957 bool using_static_chain_p)
23961 /* Select between in-line and out-of-line save and restore of regs.
23962 First, all the obvious cases where we don't use out-of-line. */
23963 if (crtl->calls_eh_return
23964 || cfun->machine->ra_need_lr)
23965 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
23966 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
23967 | SAVE_INLINE_VRS | REST_INLINE_VRS);
23969 if (info->first_gp_reg_save == 32)
23970 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23972 if (info->first_fp_reg_save == 64)
23973 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23975 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1)
23976 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23978 /* Define cutoff for using out-of-line functions to save registers. */
23979 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
23981 if (!optimize_size)
23983 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
23984 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23985 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
23989 /* Prefer out-of-line restore if it will exit. */
23990 if (info->first_fp_reg_save > 61)
23991 strategy |= SAVE_INLINE_FPRS;
23992 if (info->first_gp_reg_save > 29)
23994 if (info->first_fp_reg_save == 64)
23995 strategy |= SAVE_INLINE_GPRS;
23997 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
23999 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
24000 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24003 else if (DEFAULT_ABI == ABI_DARWIN)
24005 if (info->first_fp_reg_save > 60)
24006 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24007 if (info->first_gp_reg_save > 29)
24008 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24009 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24013 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24014 if ((flag_shrink_wrap_separate && optimize_function_for_speed_p (cfun))
24015 || info->first_fp_reg_save > 61)
24016 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
24017 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24018 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
24021 /* Don't bother to try to save things out-of-line if r11 is occupied
24022 by the static chain. It would require too much fiddling and the
24023 static chain is rarely used anyway. FPRs are saved w.r.t the stack
24024 pointer on Darwin, and AIX uses r1 or r12. */
24025 if (using_static_chain_p
24026 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
24027 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
24029 | SAVE_INLINE_VRS);
24031 /* Don't ever restore fixed regs. That means we can't use the
24032 out-of-line register restore functions if a fixed reg is in the
24033 range of regs restored. */
24034 if (!(strategy & REST_INLINE_FPRS))
24035 for (int i = info->first_fp_reg_save; i < 64; i++)
24038 strategy |= REST_INLINE_FPRS;
24042 /* We can only use the out-of-line routines to restore fprs if we've
24043 saved all the registers from first_fp_reg_save in the prologue.
24044 Otherwise, we risk loading garbage. Of course, if we have saved
24045 out-of-line then we know we haven't skipped any fprs. */
24046 if ((strategy & SAVE_INLINE_FPRS)
24047 && !(strategy & REST_INLINE_FPRS))
24048 for (int i = info->first_fp_reg_save; i < 64; i++)
24049 if (!save_reg_p (i))
24051 strategy |= REST_INLINE_FPRS;
24055 /* Similarly, for altivec regs. */
24056 if (!(strategy & REST_INLINE_VRS))
24057 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24060 strategy |= REST_INLINE_VRS;
24064 if ((strategy & SAVE_INLINE_VRS)
24065 && !(strategy & REST_INLINE_VRS))
24066 for (int i = info->first_altivec_reg_save; i < LAST_ALTIVEC_REGNO + 1; i++)
24067 if (!save_reg_p (i))
24069 strategy |= REST_INLINE_VRS;
24073 /* info->lr_save_p isn't yet set if the only reason lr needs to be
24074 saved is an out-of-line save or restore. Set up the value for
24075 the next test (excluding out-of-line gprs). */
24076 bool lr_save_p = (info->lr_save_p
24077 || !(strategy & SAVE_INLINE_FPRS)
24078 || !(strategy & SAVE_INLINE_VRS)
24079 || !(strategy & REST_INLINE_FPRS)
24080 || !(strategy & REST_INLINE_VRS));
24082 if (TARGET_MULTIPLE
24083 && !TARGET_POWERPC64
24084 && info->first_gp_reg_save < 31
24085 && !(flag_shrink_wrap
24086 && flag_shrink_wrap_separate
24087 && optimize_function_for_speed_p (cfun)))
24090 for (int i = info->first_gp_reg_save; i < 32; i++)
24091 if (save_reg_p (i))
24095 /* Don't use store multiple if only one reg needs to be
24096 saved. This can occur for example when the ABI_V4 pic reg
24097 (r30) needs to be saved to make calls, but r31 is not
24099 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24102 /* Prefer store multiple for saves over out-of-line
24103 routines, since the store-multiple instruction will
24104 always be smaller. */
24105 strategy |= SAVE_INLINE_GPRS | SAVE_MULTIPLE;
24107 /* The situation is more complicated with load multiple.
24108 We'd prefer to use the out-of-line routines for restores,
24109 since the "exit" out-of-line routines can handle the
24110 restore of LR and the frame teardown. However if doesn't
24111 make sense to use the out-of-line routine if that is the
24112 only reason we'd need to save LR, and we can't use the
24113 "exit" out-of-line gpr restore if we have saved some
24114 fprs; In those cases it is advantageous to use load
24115 multiple when available. */
24116 if (info->first_fp_reg_save != 64 || !lr_save_p)
24117 strategy |= REST_INLINE_GPRS | REST_MULTIPLE;
24121 /* Using the "exit" out-of-line routine does not improve code size
24122 if using it would require lr to be saved and if only saving one
24124 else if (!lr_save_p && info->first_gp_reg_save > 29)
24125 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
24127 /* Don't ever restore fixed regs. */
24128 if ((strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24129 for (int i = info->first_gp_reg_save; i < 32; i++)
24130 if (fixed_reg_p (i))
24132 strategy |= REST_INLINE_GPRS;
24133 strategy &= ~REST_MULTIPLE;
24137 /* We can only use load multiple or the out-of-line routines to
24138 restore gprs if we've saved all the registers from
24139 first_gp_reg_save. Otherwise, we risk loading garbage.
24140 Of course, if we have saved out-of-line or used stmw then we know
24141 we haven't skipped any gprs. */
24142 if ((strategy & (SAVE_INLINE_GPRS | SAVE_MULTIPLE)) == SAVE_INLINE_GPRS
24143 && (strategy & (REST_INLINE_GPRS | REST_MULTIPLE)) != REST_INLINE_GPRS)
24144 for (int i = info->first_gp_reg_save; i < 32; i++)
24145 if (!save_reg_p (i))
24147 strategy |= REST_INLINE_GPRS;
24148 strategy &= ~REST_MULTIPLE;
24152 if (TARGET_ELF && TARGET_64BIT)
24154 if (!(strategy & SAVE_INLINE_FPRS))
24155 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24156 else if (!(strategy & SAVE_INLINE_GPRS)
24157 && info->first_fp_reg_save == 64)
24158 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
24160 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
24161 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
24163 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
24164 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
24169 /* Calculate the stack information for the current function. This is
24170 complicated by having two separate calling sequences, the AIX calling
24171 sequence and the V.4 calling sequence.
24173 AIX (and Darwin/Mac OS X) stack frames look like:
24175 SP----> +---------------------------------------+
24176 | back chain to caller | 0 0
24177 +---------------------------------------+
24178 | saved CR | 4 8 (8-11)
24179 +---------------------------------------+
24181 +---------------------------------------+
24182 | reserved for compilers | 12 24
24183 +---------------------------------------+
24184 | reserved for binders | 16 32
24185 +---------------------------------------+
24186 | saved TOC pointer | 20 40
24187 +---------------------------------------+
24188 | Parameter save area (+padding*) (P) | 24 48
24189 +---------------------------------------+
24190 | Alloca space (A) | 24+P etc.
24191 +---------------------------------------+
24192 | Local variable space (L) | 24+P+A
24193 +---------------------------------------+
24194 | Float/int conversion temporary (X) | 24+P+A+L
24195 +---------------------------------------+
24196 | Save area for AltiVec registers (W) | 24+P+A+L+X
24197 +---------------------------------------+
24198 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
24199 +---------------------------------------+
24200 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
24201 +---------------------------------------+
24202 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
24203 +---------------------------------------+
24204 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
24205 +---------------------------------------+
24206 old SP->| back chain to caller's caller |
24207 +---------------------------------------+
24209 * If the alloca area is present, the parameter save area is
24210 padded so that the former starts 16-byte aligned.
24212 The required alignment for AIX configurations is two words (i.e., 8
24215 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
24217 SP----> +---------------------------------------+
24218 | Back chain to caller | 0
24219 +---------------------------------------+
24220 | Save area for CR | 8
24221 +---------------------------------------+
24223 +---------------------------------------+
24224 | Saved TOC pointer | 24
24225 +---------------------------------------+
24226 | Parameter save area (+padding*) (P) | 32
24227 +---------------------------------------+
24228 | Alloca space (A) | 32+P
24229 +---------------------------------------+
24230 | Local variable space (L) | 32+P+A
24231 +---------------------------------------+
24232 | Save area for AltiVec registers (W) | 32+P+A+L
24233 +---------------------------------------+
24234 | AltiVec alignment padding (Y) | 32+P+A+L+W
24235 +---------------------------------------+
24236 | Save area for GP registers (G) | 32+P+A+L+W+Y
24237 +---------------------------------------+
24238 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
24239 +---------------------------------------+
24240 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
24241 +---------------------------------------+
24243 * If the alloca area is present, the parameter save area is
24244 padded so that the former starts 16-byte aligned.
24246 V.4 stack frames look like:
24248 SP----> +---------------------------------------+
24249 | back chain to caller | 0
24250 +---------------------------------------+
24251 | caller's saved LR | 4
24252 +---------------------------------------+
24253 | Parameter save area (+padding*) (P) | 8
24254 +---------------------------------------+
24255 | Alloca space (A) | 8+P
24256 +---------------------------------------+
24257 | Varargs save area (V) | 8+P+A
24258 +---------------------------------------+
24259 | Local variable space (L) | 8+P+A+V
24260 +---------------------------------------+
24261 | Float/int conversion temporary (X) | 8+P+A+V+L
24262 +---------------------------------------+
24263 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
24264 +---------------------------------------+
24265 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
24266 +---------------------------------------+
24267 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
24268 +---------------------------------------+
24269 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
24270 +---------------------------------------+
24271 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
24272 +---------------------------------------+
24273 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
24274 +---------------------------------------+
24275 old SP->| back chain to caller's caller |
24276 +---------------------------------------+
24278 * If the alloca area is present and the required alignment is
24279 16 bytes, the parameter save area is padded so that the
24280 alloca area starts 16-byte aligned.
24282 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
24283 given. (But note below and in sysv4.h that we require only 8 and
24284 may round up the size of our stack frame anyways. The historical
24285 reason is early versions of powerpc-linux which didn't properly
24286 align the stack at program startup. A happy side-effect is that
24287 -mno-eabi libraries can be used with -meabi programs.)
24289 The EABI configuration defaults to the V.4 layout. However,
24290 the stack alignment requirements may differ. If -mno-eabi is not
24291 given, the required stack alignment is 8 bytes; if -mno-eabi is
24292 given, the required alignment is 16 bytes. (But see V.4 comment
24295 #ifndef ABI_STACK_BOUNDARY
24296 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
24299 static rs6000_stack_t *
24300 rs6000_stack_info (void)
24302 /* We should never be called for thunks, we are not set up for that. */
24303 gcc_assert (!cfun->is_thunk);
24305 rs6000_stack_t *info = &stack_info;
24306 int reg_size = TARGET_32BIT ? 4 : 8;
24311 HOST_WIDE_INT non_fixed_size;
24312 bool using_static_chain_p;
24314 if (reload_completed && info->reload_completed)
24317 memset (info, 0, sizeof (*info));
24318 info->reload_completed = reload_completed;
24320 /* Select which calling sequence. */
24321 info->abi = DEFAULT_ABI;
24323 /* Calculate which registers need to be saved & save area size. */
24324 info->first_gp_reg_save = first_reg_to_save ();
24325 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
24326 even if it currently looks like we won't. Reload may need it to
24327 get at a constant; if so, it will have already created a constant
24328 pool entry for it. */
24329 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
24330 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
24331 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
24332 && crtl->uses_const_pool
24333 && info->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
24334 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
24336 first_gp = info->first_gp_reg_save;
24338 info->gp_size = reg_size * (32 - first_gp);
24340 info->first_fp_reg_save = first_fp_reg_to_save ();
24341 info->fp_size = 8 * (64 - info->first_fp_reg_save);
24343 info->first_altivec_reg_save = first_altivec_reg_to_save ();
24344 info->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
24345 - info->first_altivec_reg_save);
24347 /* Does this function call anything? */
24348 info->calls_p = (!crtl->is_leaf || cfun->machine->ra_needs_full_frame);
24350 /* Determine if we need to save the condition code registers. */
24351 if (save_reg_p (CR2_REGNO)
24352 || save_reg_p (CR3_REGNO)
24353 || save_reg_p (CR4_REGNO))
24355 info->cr_save_p = 1;
24356 if (DEFAULT_ABI == ABI_V4)
24357 info->cr_size = reg_size;
24360 /* If the current function calls __builtin_eh_return, then we need
24361 to allocate stack space for registers that will hold data for
24362 the exception handler. */
24363 if (crtl->calls_eh_return)
24366 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
24369 ehrd_size = i * UNITS_PER_WORD;
24374 /* In the ELFv2 ABI, we also need to allocate space for separate
24375 CR field save areas if the function calls __builtin_eh_return. */
24376 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24378 /* This hard-codes that we have three call-saved CR fields. */
24379 ehcr_size = 3 * reg_size;
24380 /* We do *not* use the regular CR save mechanism. */
24381 info->cr_save_p = 0;
24386 /* Determine various sizes. */
24387 info->reg_size = reg_size;
24388 info->fixed_size = RS6000_SAVE_AREA;
24389 info->vars_size = RS6000_ALIGN (get_frame_size (), 8);
24390 if (cfun->calls_alloca)
24392 RS6000_ALIGN (crtl->outgoing_args_size + info->fixed_size,
24393 STACK_BOUNDARY / BITS_PER_UNIT) - info->fixed_size;
24395 info->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
24396 TARGET_ALTIVEC ? 16 : 8);
24397 if (FRAME_GROWS_DOWNWARD)
24399 += RS6000_ALIGN (info->fixed_size + info->vars_size + info->parm_size,
24400 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
24401 - (info->fixed_size + info->vars_size + info->parm_size);
24403 if (TARGET_ALTIVEC_ABI)
24404 info->vrsave_mask = compute_vrsave_mask ();
24406 if (TARGET_ALTIVEC_VRSAVE && info->vrsave_mask)
24407 info->vrsave_size = 4;
24409 compute_save_world_info (info);
24411 /* Calculate the offsets. */
24412 switch (DEFAULT_ABI)
24416 gcc_unreachable ();
24421 info->fp_save_offset = -info->fp_size;
24422 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24424 if (TARGET_ALTIVEC_ABI)
24426 info->vrsave_save_offset = info->gp_save_offset - info->vrsave_size;
24428 /* Align stack so vector save area is on a quadword boundary.
24429 The padding goes above the vectors. */
24430 if (info->altivec_size != 0)
24431 info->altivec_padding_size = info->vrsave_save_offset & 0xF;
24433 info->altivec_save_offset = info->vrsave_save_offset
24434 - info->altivec_padding_size
24435 - info->altivec_size;
24436 gcc_assert (info->altivec_size == 0
24437 || info->altivec_save_offset % 16 == 0);
24439 /* Adjust for AltiVec case. */
24440 info->ehrd_offset = info->altivec_save_offset - ehrd_size;
24443 info->ehrd_offset = info->gp_save_offset - ehrd_size;
24445 info->ehcr_offset = info->ehrd_offset - ehcr_size;
24446 info->cr_save_offset = reg_size; /* first word when 64-bit. */
24447 info->lr_save_offset = 2*reg_size;
24451 info->fp_save_offset = -info->fp_size;
24452 info->gp_save_offset = info->fp_save_offset - info->gp_size;
24453 info->cr_save_offset = info->gp_save_offset - info->cr_size;
24455 if (TARGET_ALTIVEC_ABI)
24457 info->vrsave_save_offset = info->cr_save_offset - info->vrsave_size;
24459 /* Align stack so vector save area is on a quadword boundary. */
24460 if (info->altivec_size != 0)
24461 info->altivec_padding_size = 16 - (-info->vrsave_save_offset % 16);
24463 info->altivec_save_offset = info->vrsave_save_offset
24464 - info->altivec_padding_size
24465 - info->altivec_size;
24467 /* Adjust for AltiVec case. */
24468 info->ehrd_offset = info->altivec_save_offset;
24471 info->ehrd_offset = info->cr_save_offset;
24473 info->ehrd_offset -= ehrd_size;
24474 info->lr_save_offset = reg_size;
24477 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
24478 info->save_size = RS6000_ALIGN (info->fp_size
24480 + info->altivec_size
24481 + info->altivec_padding_size
24485 + info->vrsave_size,
24488 non_fixed_size = info->vars_size + info->parm_size + info->save_size;
24490 info->total_size = RS6000_ALIGN (non_fixed_size + info->fixed_size,
24491 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
24493 /* Determine if we need to save the link register. */
24495 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24497 && !TARGET_PROFILE_KERNEL)
24498 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
24499 #ifdef TARGET_RELOCATABLE
24500 || (DEFAULT_ABI == ABI_V4
24501 && (TARGET_RELOCATABLE || flag_pic > 1)
24502 && !constant_pool_empty_p ())
24504 || rs6000_ra_ever_killed ())
24505 info->lr_save_p = 1;
24507 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
24508 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
24509 && call_used_regs[STATIC_CHAIN_REGNUM]);
24510 info->savres_strategy = rs6000_savres_strategy (info, using_static_chain_p);
24512 if (!(info->savres_strategy & SAVE_INLINE_GPRS)
24513 || !(info->savres_strategy & SAVE_INLINE_FPRS)
24514 || !(info->savres_strategy & SAVE_INLINE_VRS)
24515 || !(info->savres_strategy & REST_INLINE_GPRS)
24516 || !(info->savres_strategy & REST_INLINE_FPRS)
24517 || !(info->savres_strategy & REST_INLINE_VRS))
24518 info->lr_save_p = 1;
24520 if (info->lr_save_p)
24521 df_set_regs_ever_live (LR_REGNO, true);
24523 /* Determine if we need to allocate any stack frame:
24525 For AIX we need to push the stack if a frame pointer is needed
24526 (because the stack might be dynamically adjusted), if we are
24527 debugging, if we make calls, or if the sum of fp_save, gp_save,
24528 and local variables are more than the space needed to save all
24529 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
24530 + 18*8 = 288 (GPR13 reserved).
24532 For V.4 we don't have the stack cushion that AIX uses, but assume
24533 that the debugger can handle stackless frames. */
24538 else if (DEFAULT_ABI == ABI_V4)
24539 info->push_p = non_fixed_size != 0;
24541 else if (frame_pointer_needed)
24544 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
24548 info->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
24554 debug_stack_info (rs6000_stack_t *info)
24556 const char *abi_string;
24559 info = rs6000_stack_info ();
24561 fprintf (stderr, "\nStack information for function %s:\n",
24562 ((current_function_decl && DECL_NAME (current_function_decl))
24563 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
24568 default: abi_string = "Unknown"; break;
24569 case ABI_NONE: abi_string = "NONE"; break;
24570 case ABI_AIX: abi_string = "AIX"; break;
24571 case ABI_ELFv2: abi_string = "ELFv2"; break;
24572 case ABI_DARWIN: abi_string = "Darwin"; break;
24573 case ABI_V4: abi_string = "V.4"; break;
24576 fprintf (stderr, "\tABI = %5s\n", abi_string);
24578 if (TARGET_ALTIVEC_ABI)
24579 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
24581 if (info->first_gp_reg_save != 32)
24582 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
24584 if (info->first_fp_reg_save != 64)
24585 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
24587 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
24588 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
24589 info->first_altivec_reg_save);
24591 if (info->lr_save_p)
24592 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
24594 if (info->cr_save_p)
24595 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
24597 if (info->vrsave_mask)
24598 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
24601 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
24604 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
24607 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
24610 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
24612 if (info->altivec_size)
24613 fprintf (stderr, "\taltivec_save_offset = %5d\n",
24614 info->altivec_save_offset);
24616 if (info->vrsave_size)
24617 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
24618 info->vrsave_save_offset);
24620 if (info->lr_save_p)
24621 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
24623 if (info->cr_save_p)
24624 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
24626 if (info->varargs_save_offset)
24627 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
24629 if (info->total_size)
24630 fprintf (stderr, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24633 if (info->vars_size)
24634 fprintf (stderr, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC"\n",
24637 if (info->parm_size)
24638 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
24640 if (info->fixed_size)
24641 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
24644 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
24647 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
24649 if (info->altivec_size)
24650 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
24652 if (info->vrsave_size)
24653 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
24655 if (info->altivec_padding_size)
24656 fprintf (stderr, "\taltivec_padding_size= %5d\n",
24657 info->altivec_padding_size);
24660 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
24662 if (info->save_size)
24663 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
24665 if (info->reg_size != 4)
24666 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
24668 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
24670 if (info->abi == ABI_DARWIN)
24671 fprintf (stderr, "\tWORLD_SAVE_P = %5d\n", WORLD_SAVE_P(info));
24673 fprintf (stderr, "\n");
24677 rs6000_return_addr (int count, rtx frame)
24679 /* We can't use get_hard_reg_initial_val for LR when count == 0 if LR
24680 is trashed by the prologue, as it is for PIC on ABI_V4 and Darwin. */
24682 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
24684 cfun->machine->ra_needs_full_frame = 1;
24687 /* FRAME is set to frame_pointer_rtx by the generic code, but that
24688 is good for loading 0(r1) only when !FRAME_GROWS_DOWNWARD. */
24689 frame = stack_pointer_rtx;
24690 rtx prev_frame_addr = memory_address (Pmode, frame);
24691 rtx prev_frame = copy_to_reg (gen_rtx_MEM (Pmode, prev_frame_addr));
24692 rtx lr_save_off = plus_constant (Pmode,
24693 prev_frame, RETURN_ADDRESS_OFFSET);
24694 rtx lr_save_addr = memory_address (Pmode, lr_save_off);
24695 return gen_rtx_MEM (Pmode, lr_save_addr);
24698 cfun->machine->ra_need_lr = 1;
24699 return get_hard_reg_initial_val (Pmode, LR_REGNO);
24702 /* Say whether a function is a candidate for sibcall handling or not. */
24705 rs6000_function_ok_for_sibcall (tree decl, tree exp)
24709 /* The sibcall epilogue may clobber the static chain register.
24710 ??? We could work harder and avoid that, but it's probably
24711 not worth the hassle in practice. */
24712 if (CALL_EXPR_STATIC_CHAIN (exp))
24716 fntype = TREE_TYPE (decl);
24718 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
24720 /* We can't do it if the called function has more vector parameters
24721 than the current function; there's nowhere to put the VRsave code. */
24722 if (TARGET_ALTIVEC_ABI
24723 && TARGET_ALTIVEC_VRSAVE
24724 && !(decl && decl == current_function_decl))
24726 function_args_iterator args_iter;
24730 /* Functions with vector parameters are required to have a
24731 prototype, so the argument type info must be available
24733 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
24734 if (TREE_CODE (type) == VECTOR_TYPE
24735 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24738 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
24739 if (TREE_CODE (type) == VECTOR_TYPE
24740 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
24747 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
24748 functions, because the callee may have a different TOC pointer to
24749 the caller and there's no way to ensure we restore the TOC when
24750 we return. With the secure-plt SYSV ABI we can't make non-local
24751 calls when -fpic/PIC because the plt call stubs use r30. */
24752 if (DEFAULT_ABI == ABI_DARWIN
24753 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24755 && !DECL_EXTERNAL (decl)
24756 && !DECL_WEAK (decl)
24757 && (*targetm.binds_local_p) (decl))
24758 || (DEFAULT_ABI == ABI_V4
24759 && (!TARGET_SECURE_PLT
24762 && (*targetm.binds_local_p) (decl)))))
24764 tree attr_list = TYPE_ATTRIBUTES (fntype);
24766 if (!lookup_attribute ("longcall", attr_list)
24767 || lookup_attribute ("shortcall", attr_list))
24775 rs6000_ra_ever_killed (void)
24781 if (cfun->is_thunk)
24784 if (cfun->machine->lr_save_state)
24785 return cfun->machine->lr_save_state - 1;
24787 /* regs_ever_live has LR marked as used if any sibcalls are present,
24788 but this should not force saving and restoring in the
24789 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
24790 clobbers LR, so that is inappropriate. */
24792 /* Also, the prologue can generate a store into LR that
24793 doesn't really count, like this:
24796 bcl to set PIC register
24800 When we're called from the epilogue, we need to avoid counting
24801 this as a store. */
24803 push_topmost_sequence ();
24804 top = get_insns ();
24805 pop_topmost_sequence ();
24806 reg = gen_rtx_REG (Pmode, LR_REGNO);
24808 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
24814 if (!SIBLING_CALL_P (insn))
24817 else if (find_regno_note (insn, REG_INC, LR_REGNO))
24819 else if (set_of (reg, insn) != NULL_RTX
24820 && !prologue_epilogue_contains (insn))
24827 /* Emit instructions needed to load the TOC register.
24828 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
24829 a constant pool; or for SVR4 -fpic. */
24832 rs6000_emit_load_toc_table (int fromprolog)
24835 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
24837 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
24840 rtx lab, tmp1, tmp2, got;
24842 lab = gen_label_rtx ();
24843 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
24844 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24847 got = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24851 got = rs6000_got_sym ();
24852 tmp1 = tmp2 = dest;
24855 tmp1 = gen_reg_rtx (Pmode);
24856 tmp2 = gen_reg_rtx (Pmode);
24858 emit_insn (gen_load_toc_v4_PIC_1 (lab));
24859 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
24860 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
24861 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
24863 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
24865 emit_insn (gen_load_toc_v4_pic_si ());
24866 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24868 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
24871 rtx temp0 = (fromprolog
24872 ? gen_rtx_REG (Pmode, 0)
24873 : gen_reg_rtx (Pmode));
24879 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
24880 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24882 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
24883 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
24885 emit_insn (gen_load_toc_v4_PIC_1 (symF));
24886 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24887 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
24893 tocsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24895 lab = gen_label_rtx ();
24896 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
24897 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
24898 if (TARGET_LINK_STACK)
24899 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
24900 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
24902 emit_insn (gen_addsi3 (dest, temp0, dest));
24904 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
24906 /* This is for AIX code running in non-PIC ELF32. */
24907 rtx realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (toc_label_name));
24910 emit_insn (gen_elf_high (dest, realsym));
24911 emit_insn (gen_elf_low (dest, dest, realsym));
24915 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24918 emit_insn (gen_load_toc_aix_si (dest));
24920 emit_insn (gen_load_toc_aix_di (dest));
24924 /* Emit instructions to restore the link register after determining where
24925 its value has been stored. */
24928 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
24930 rs6000_stack_t *info = rs6000_stack_info ();
24933 operands[0] = source;
24934 operands[1] = scratch;
24936 if (info->lr_save_p)
24938 rtx frame_rtx = stack_pointer_rtx;
24939 HOST_WIDE_INT sp_offset = 0;
24942 if (frame_pointer_needed
24943 || cfun->calls_alloca
24944 || info->total_size > 32767)
24946 tmp = gen_frame_mem (Pmode, frame_rtx);
24947 emit_move_insn (operands[1], tmp);
24948 frame_rtx = operands[1];
24950 else if (info->push_p)
24951 sp_offset = info->total_size;
24953 tmp = plus_constant (Pmode, frame_rtx,
24954 info->lr_save_offset + sp_offset);
24955 tmp = gen_frame_mem (Pmode, tmp);
24956 emit_move_insn (tmp, operands[0]);
24959 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
24961 /* Freeze lr_save_p. We've just emitted rtl that depends on the
24962 state of lr_save_p so any change from here on would be a bug. In
24963 particular, stop rs6000_ra_ever_killed from considering the SET
24964 of lr we may have added just above. */
24965 cfun->machine->lr_save_state = info->lr_save_p + 1;
24968 static GTY(()) alias_set_type set = -1;
24971 get_TOC_alias_set (void)
24974 set = new_alias_set ();
24978 /* This returns nonzero if the current function uses the TOC. This is
24979 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
24980 is generated by the ABI_V4 load_toc_* patterns.
24981 Return 2 instead of 1 if the load_toc_* pattern is in the function
24982 partition that doesn't start the function. */
24990 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
24994 rtx pat = PATTERN (insn);
24997 if (GET_CODE (pat) == PARALLEL)
24998 for (i = 0; i < XVECLEN (pat, 0); i++)
25000 rtx sub = XVECEXP (pat, 0, i);
25001 if (GET_CODE (sub) == USE)
25003 sub = XEXP (sub, 0);
25004 if (GET_CODE (sub) == UNSPEC
25005 && XINT (sub, 1) == UNSPEC_TOC)
25010 else if (crtl->has_bb_partition
25012 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
25020 create_TOC_reference (rtx symbol, rtx largetoc_reg)
25022 rtx tocrel, tocreg, hi;
25024 if (TARGET_DEBUG_ADDR)
25026 if (SYMBOL_REF_P (symbol))
25027 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
25031 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
25032 GET_RTX_NAME (GET_CODE (symbol)));
25033 debug_rtx (symbol);
25037 if (!can_create_pseudo_p ())
25038 df_set_regs_ever_live (TOC_REGISTER, true);
25040 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
25041 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
25042 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
25045 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
25046 if (largetoc_reg != NULL)
25048 emit_move_insn (largetoc_reg, hi);
25051 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
25054 /* Issue assembly directives that create a reference to the given DWARF
25055 FRAME_TABLE_LABEL from the current function section. */
25057 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
25059 fprintf (asm_out_file, "\t.ref %s\n",
25060 (* targetm.strip_name_encoding) (frame_table_label));
25063 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
25064 and the change to the stack pointer. */
25067 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
25074 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25075 if (hard_frame_needed)
25076 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
25077 if (!(REGNO (fp) == STACK_POINTER_REGNUM
25078 || (hard_frame_needed
25079 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
25082 p = rtvec_alloc (i);
25085 rtx mem = gen_frame_mem (BLKmode, regs[i]);
25086 RTVEC_ELT (p, i) = gen_rtx_SET (mem, const0_rtx);
25089 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
25092 /* Allocate SIZE_INT bytes on the stack using a store with update style insn
25093 and set the appropriate attributes for the generated insn. Return the
25094 first insn which adjusts the stack pointer or the last insn before
25095 the stack adjustment loop.
25097 SIZE_INT is used to create the CFI note for the allocation.
25099 SIZE_RTX is an rtx containing the size of the adjustment. Note that
25100 since stacks grow to lower addresses its runtime value is -SIZE_INT.
25102 ORIG_SP contains the backchain value that must be stored at *sp. */
25105 rs6000_emit_allocate_stack_1 (HOST_WIDE_INT size_int, rtx orig_sp)
25109 rtx size_rtx = GEN_INT (-size_int);
25110 if (size_int > 32767)
25112 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25113 /* Need a note here so that try_split doesn't get confused. */
25114 if (get_last_insn () == NULL_RTX)
25115 emit_note (NOTE_INSN_DELETED);
25116 insn = emit_move_insn (tmp_reg, size_rtx);
25117 try_split (PATTERN (insn), insn, 0);
25118 size_rtx = tmp_reg;
25122 insn = emit_insn (gen_movsi_update_stack (stack_pointer_rtx,
25127 insn = emit_insn (gen_movdi_update_stack (stack_pointer_rtx,
25131 rtx par = PATTERN (insn);
25132 gcc_assert (GET_CODE (par) == PARALLEL);
25133 rtx set = XVECEXP (par, 0, 0);
25134 gcc_assert (GET_CODE (set) == SET);
25135 rtx mem = SET_DEST (set);
25136 gcc_assert (MEM_P (mem));
25137 MEM_NOTRAP_P (mem) = 1;
25138 set_mem_alias_set (mem, get_frame_alias_set ());
25140 RTX_FRAME_RELATED_P (insn) = 1;
25141 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25142 gen_rtx_SET (stack_pointer_rtx,
25143 gen_rtx_PLUS (Pmode,
25145 GEN_INT (-size_int))));
25147 /* Emit a blockage to ensure the allocation/probing insns are
25148 not optimized, combined, removed, etc. Add REG_STACK_CHECK
25149 note for similar reasons. */
25150 if (flag_stack_clash_protection)
25152 add_reg_note (insn, REG_STACK_CHECK, const0_rtx);
25153 emit_insn (gen_blockage ());
25159 static HOST_WIDE_INT
25160 get_stack_clash_protection_probe_interval (void)
25162 return (HOST_WIDE_INT_1U
25163 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_PROBE_INTERVAL));
25166 static HOST_WIDE_INT
25167 get_stack_clash_protection_guard_size (void)
25169 return (HOST_WIDE_INT_1U
25170 << PARAM_VALUE (PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE));
25173 /* Allocate ORIG_SIZE bytes on the stack and probe the newly
25174 allocated space every STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes.
25176 COPY_REG, if non-null, should contain a copy of the original
25177 stack pointer at exit from this function.
25179 This is subtly different than the Ada probing in that it tries hard to
25180 prevent attacks that jump the stack guard. Thus it is never allowed to
25181 allocate more than STACK_CLASH_PROTECTION_PROBE_INTERVAL bytes of stack
25182 space without a suitable probe. */
25184 rs6000_emit_probe_stack_range_stack_clash (HOST_WIDE_INT orig_size,
25187 rtx orig_sp = copy_reg;
25189 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25191 /* Round the size down to a multiple of PROBE_INTERVAL. */
25192 HOST_WIDE_INT rounded_size = ROUND_DOWN (orig_size, probe_interval);
25194 /* If explicitly requested,
25195 or the rounded size is not the same as the original size
25196 or the the rounded size is greater than a page,
25197 then we will need a copy of the original stack pointer. */
25198 if (rounded_size != orig_size
25199 || rounded_size > probe_interval
25202 /* If the caller did not request a copy of the incoming stack
25203 pointer, then we use r0 to hold the copy. */
25205 orig_sp = gen_rtx_REG (Pmode, 0);
25206 emit_move_insn (orig_sp, stack_pointer_rtx);
25209 /* There's three cases here.
25211 One is a single probe which is the most common and most efficiently
25212 implemented as it does not have to have a copy of the original
25213 stack pointer if there are no residuals.
25215 Second is unrolled allocation/probes which we use if there's just
25216 a few of them. It needs to save the original stack pointer into a
25217 temporary for use as a source register in the allocation/probe.
25219 Last is a loop. This is the most uncommon case and least efficient. */
25220 rtx_insn *retval = NULL;
25221 if (rounded_size == probe_interval)
25223 retval = rs6000_emit_allocate_stack_1 (probe_interval, stack_pointer_rtx);
25225 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25227 else if (rounded_size <= 8 * probe_interval)
25229 /* The ABI requires using the store with update insns to allocate
25230 space and store the backchain into the stack
25232 So we save the current stack pointer into a temporary, then
25233 emit the store-with-update insns to store the saved stack pointer
25234 into the right location in each new page. */
25235 for (int i = 0; i < rounded_size; i += probe_interval)
25238 = rs6000_emit_allocate_stack_1 (probe_interval, orig_sp);
25240 /* Save the first stack adjustment in RETVAL. */
25245 dump_stack_clash_frame_info (PROBE_INLINE, rounded_size != orig_size);
25249 /* Compute the ending address. */
25251 = copy_reg ? gen_rtx_REG (Pmode, 0) : gen_rtx_REG (Pmode, 12);
25252 rtx rs = GEN_INT (-rounded_size);
25254 if (add_operand (rs, Pmode))
25255 insn = emit_insn (gen_add3_insn (end_addr, stack_pointer_rtx, rs));
25258 emit_move_insn (end_addr, GEN_INT (-rounded_size));
25259 insn = emit_insn (gen_add3_insn (end_addr, end_addr,
25260 stack_pointer_rtx));
25261 /* Describe the effect of INSN to the CFI engine. */
25262 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
25263 gen_rtx_SET (end_addr,
25264 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
25267 RTX_FRAME_RELATED_P (insn) = 1;
25269 /* Emit the loop. */
25271 retval = emit_insn (gen_probe_stack_rangedi (stack_pointer_rtx,
25272 stack_pointer_rtx, orig_sp,
25275 retval = emit_insn (gen_probe_stack_rangesi (stack_pointer_rtx,
25276 stack_pointer_rtx, orig_sp,
25278 RTX_FRAME_RELATED_P (retval) = 1;
25279 /* Describe the effect of INSN to the CFI engine. */
25280 add_reg_note (retval, REG_FRAME_RELATED_EXPR,
25281 gen_rtx_SET (stack_pointer_rtx, end_addr));
25283 /* Emit a blockage to ensure the allocation/probing insns are
25284 not optimized, combined, removed, etc. Other cases handle this
25285 within their call to rs6000_emit_allocate_stack_1. */
25286 emit_insn (gen_blockage ());
25288 dump_stack_clash_frame_info (PROBE_LOOP, rounded_size != orig_size);
25291 if (orig_size != rounded_size)
25293 /* Allocate (and implicitly probe) any residual space. */
25294 HOST_WIDE_INT residual = orig_size - rounded_size;
25296 rtx_insn *insn = rs6000_emit_allocate_stack_1 (residual, orig_sp);
25298 /* If the residual was the only allocation, then we can return the
25299 allocating insn. */
25307 /* Emit the correct code for allocating stack space, as insns.
25308 If COPY_REG, make sure a copy of the old frame is left there.
25309 The generated code may use hard register 0 as a temporary. */
25312 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
25315 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
25316 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
25317 rtx todec = gen_int_mode (-size, Pmode);
25319 if (INTVAL (todec) != -size)
25321 warning (0, "stack frame too large");
25322 emit_insn (gen_trap ());
25326 if (crtl->limit_stack)
25328 if (REG_P (stack_limit_rtx)
25329 && REGNO (stack_limit_rtx) > 1
25330 && REGNO (stack_limit_rtx) <= 31)
25333 = gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size));
25336 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg, const0_rtx));
25338 else if (SYMBOL_REF_P (stack_limit_rtx)
25340 && DEFAULT_ABI == ABI_V4
25343 rtx toload = gen_rtx_CONST (VOIDmode,
25344 gen_rtx_PLUS (Pmode,
25348 emit_insn (gen_elf_high (tmp_reg, toload));
25349 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
25350 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
25354 warning (0, "stack limit expression is not supported");
25357 if (flag_stack_clash_protection)
25359 if (size < get_stack_clash_protection_guard_size ())
25360 dump_stack_clash_frame_info (NO_PROBE_SMALL_FRAME, true);
25363 rtx_insn *insn = rs6000_emit_probe_stack_range_stack_clash (size,
25366 /* If we asked for a copy with an offset, then we still need add in
25368 if (copy_reg && copy_off)
25369 emit_insn (gen_add3_insn (copy_reg, copy_reg, GEN_INT (copy_off)));
25377 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
25379 emit_move_insn (copy_reg, stack_reg);
25382 /* Since we didn't use gen_frame_mem to generate the MEM, grab
25383 it now and set the alias set/attributes. The above gen_*_update
25384 calls will generate a PARALLEL with the MEM set being the first
25386 insn = rs6000_emit_allocate_stack_1 (size, stack_reg);
25390 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
25392 #if PROBE_INTERVAL > 32768
25393 #error Cannot use indexed addressing mode for stack probing
25396 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
25397 inclusive. These are offsets from the current stack pointer. */
25400 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
25402 /* See if we have a constant small number of probes to generate. If so,
25403 that's the easy case. */
25404 if (first + size <= 32768)
25408 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
25409 it exceeds SIZE. If only one probe is needed, this will not
25410 generate any code. Then probe at FIRST + SIZE. */
25411 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
25412 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25415 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
25419 /* Otherwise, do the same as above, but in a loop. Note that we must be
25420 extra careful with variables wrapping around because we might be at
25421 the very top (or the very bottom) of the address space and we have
25422 to be able to handle this case properly; in particular, we use an
25423 equality test for the loop condition. */
25426 HOST_WIDE_INT rounded_size;
25427 rtx r12 = gen_rtx_REG (Pmode, 12);
25428 rtx r0 = gen_rtx_REG (Pmode, 0);
25430 /* Sanity check for the addressing mode we're going to use. */
25431 gcc_assert (first <= 32768);
25433 /* Step 1: round SIZE to the previous multiple of the interval. */
25435 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL);
25438 /* Step 2: compute initial and final value of the loop counter. */
25440 /* TEST_ADDR = SP + FIRST. */
25441 emit_insn (gen_rtx_SET (r12, plus_constant (Pmode, stack_pointer_rtx,
25444 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
25445 if (rounded_size > 32768)
25447 emit_move_insn (r0, GEN_INT (-rounded_size));
25448 emit_insn (gen_rtx_SET (r0, gen_rtx_PLUS (Pmode, r12, r0)));
25451 emit_insn (gen_rtx_SET (r0, plus_constant (Pmode, r12,
25455 /* Step 3: the loop
25459 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
25462 while (TEST_ADDR != LAST_ADDR)
25464 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
25465 until it is equal to ROUNDED_SIZE. */
25468 emit_insn (gen_probe_stack_rangedi (r12, r12, stack_pointer_rtx, r0));
25470 emit_insn (gen_probe_stack_rangesi (r12, r12, stack_pointer_rtx, r0));
25473 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
25474 that SIZE is equal to ROUNDED_SIZE. */
25476 if (size != rounded_size)
25477 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
25481 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
25482 addresses, not offsets. */
25484 static const char *
25485 output_probe_stack_range_1 (rtx reg1, rtx reg2)
25487 static int labelno = 0;
25491 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25494 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25496 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
25498 xops[1] = GEN_INT (-PROBE_INTERVAL);
25499 output_asm_insn ("addi %0,%0,%1", xops);
25501 /* Probe at TEST_ADDR. */
25502 xops[1] = gen_rtx_REG (Pmode, 0);
25503 output_asm_insn ("stw %1,0(%0)", xops);
25505 /* Test if TEST_ADDR == LAST_ADDR. */
25508 output_asm_insn ("cmpd 0,%0,%1", xops);
25510 output_asm_insn ("cmpw 0,%0,%1", xops);
25513 fputs ("\tbne 0,", asm_out_file);
25514 assemble_name_raw (asm_out_file, loop_lab);
25515 fputc ('\n', asm_out_file);
25520 /* This function is called when rs6000_frame_related is processing
25521 SETs within a PARALLEL, and returns whether the REGNO save ought to
25522 be marked RTX_FRAME_RELATED_P. The PARALLELs involved are those
25523 for out-of-line register save functions, store multiple, and the
25524 Darwin world_save. They may contain registers that don't really
25528 interesting_frame_related_regno (unsigned int regno)
25530 /* Saves apparently of r0 are actually saving LR. It doesn't make
25531 sense to substitute the regno here to test save_reg_p (LR_REGNO).
25532 We *know* LR needs saving, and dwarf2cfi.c is able to deduce that
25533 (set (mem) (r0)) is saving LR from a prior (set (r0) (lr)) marked
25534 as frame related. */
25537 /* If we see CR2 then we are here on a Darwin world save. Saves of
25538 CR2 signify the whole CR is being saved. This is a long-standing
25539 ABI wart fixed by ELFv2. As for r0/lr there is no need to check
25540 that CR needs to be saved. */
25541 if (regno == CR2_REGNO)
25543 /* Omit frame info for any user-defined global regs. If frame info
25544 is supplied for them, frame unwinding will restore a user reg.
25545 Also omit frame info for any reg we don't need to save, as that
25546 bloats frame info and can cause problems with shrink wrapping.
25547 Since global regs won't be seen as needing to be saved, both of
25548 these conditions are covered by save_reg_p. */
25549 return save_reg_p (regno);
25552 /* Probe a range of stack addresses from REG1 to REG3 inclusive. These are
25553 addresses, not offsets.
25555 REG2 contains the backchain that must be stored into *sp at each allocation.
25557 This is subtly different than the Ada probing above in that it tries hard
25558 to prevent attacks that jump the stack guard. Thus, it is never allowed
25559 to allocate more than PROBE_INTERVAL bytes of stack space without a
25562 static const char *
25563 output_probe_stack_range_stack_clash (rtx reg1, rtx reg2, rtx reg3)
25565 static int labelno = 0;
25569 HOST_WIDE_INT probe_interval = get_stack_clash_protection_probe_interval ();
25571 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++);
25573 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
25575 /* This allocates and probes. */
25578 xops[2] = GEN_INT (-probe_interval);
25580 output_asm_insn ("stdu %1,%2(%0)", xops);
25582 output_asm_insn ("stwu %1,%2(%0)", xops);
25584 /* Jump to LOOP_LAB if TEST_ADDR != LAST_ADDR. */
25588 output_asm_insn ("cmpd 0,%0,%1", xops);
25590 output_asm_insn ("cmpw 0,%0,%1", xops);
25592 fputs ("\tbne 0,", asm_out_file);
25593 assemble_name_raw (asm_out_file, loop_lab);
25594 fputc ('\n', asm_out_file);
25599 /* Wrapper around the output_probe_stack_range routines. */
25601 output_probe_stack_range (rtx reg1, rtx reg2, rtx reg3)
25603 if (flag_stack_clash_protection)
25604 return output_probe_stack_range_stack_clash (reg1, reg2, reg3);
25606 return output_probe_stack_range_1 (reg1, reg3);
25609 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
25610 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
25611 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
25612 deduce these equivalences by itself so it wasn't necessary to hold
25613 its hand so much. Don't be tempted to always supply d2_f_d_e with
25614 the actual cfa register, ie. r31 when we are using a hard frame
25615 pointer. That fails when saving regs off r1, and sched moves the
25616 r31 setup past the reg saves. */
25619 rs6000_frame_related (rtx_insn *insn, rtx reg, HOST_WIDE_INT val,
25620 rtx reg2, rtx repl2)
25624 if (REGNO (reg) == STACK_POINTER_REGNUM)
25626 gcc_checking_assert (val == 0);
25630 repl = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
25633 rtx pat = PATTERN (insn);
25634 if (!repl && !reg2)
25636 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
25637 if (GET_CODE (pat) == PARALLEL)
25638 for (int i = 0; i < XVECLEN (pat, 0); i++)
25639 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25641 rtx set = XVECEXP (pat, 0, i);
25643 if (!REG_P (SET_SRC (set))
25644 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25645 RTX_FRAME_RELATED_P (set) = 1;
25647 RTX_FRAME_RELATED_P (insn) = 1;
25651 /* We expect that 'pat' is either a SET or a PARALLEL containing
25652 SETs (and possibly other stuff). In a PARALLEL, all the SETs
25653 are important so they all have to be marked RTX_FRAME_RELATED_P.
25654 Call simplify_replace_rtx on the SETs rather than the whole insn
25655 so as to leave the other stuff alone (for example USE of r12). */
25657 set_used_flags (pat);
25658 if (GET_CODE (pat) == SET)
25661 pat = simplify_replace_rtx (pat, reg, repl);
25663 pat = simplify_replace_rtx (pat, reg2, repl2);
25665 else if (GET_CODE (pat) == PARALLEL)
25667 pat = shallow_copy_rtx (pat);
25668 XVEC (pat, 0) = shallow_copy_rtvec (XVEC (pat, 0));
25670 for (int i = 0; i < XVECLEN (pat, 0); i++)
25671 if (GET_CODE (XVECEXP (pat, 0, i)) == SET)
25673 rtx set = XVECEXP (pat, 0, i);
25676 set = simplify_replace_rtx (set, reg, repl);
25678 set = simplify_replace_rtx (set, reg2, repl2);
25679 XVECEXP (pat, 0, i) = set;
25681 if (!REG_P (SET_SRC (set))
25682 || interesting_frame_related_regno (REGNO (SET_SRC (set))))
25683 RTX_FRAME_RELATED_P (set) = 1;
25687 gcc_unreachable ();
25689 RTX_FRAME_RELATED_P (insn) = 1;
25690 add_reg_note (insn, REG_FRAME_RELATED_EXPR, copy_rtx_if_shared (pat));
25695 /* Returns an insn that has a vrsave set operation with the
25696 appropriate CLOBBERs. */
25699 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
25702 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
25703 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
25706 = gen_rtx_SET (vrsave,
25707 gen_rtx_UNSPEC_VOLATILE (SImode,
25708 gen_rtvec (2, reg, vrsave),
25709 UNSPECV_SET_VRSAVE));
25713 /* We need to clobber the registers in the mask so the scheduler
25714 does not move sets to VRSAVE before sets of AltiVec registers.
25716 However, if the function receives nonlocal gotos, reload will set
25717 all call saved registers live. We will end up with:
25719 (set (reg 999) (mem))
25720 (parallel [ (set (reg vrsave) (unspec blah))
25721 (clobber (reg 999))])
25723 The clobber will cause the store into reg 999 to be dead, and
25724 flow will attempt to delete an epilogue insn. In this case, we
25725 need an unspec use/set of the register. */
25727 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
25728 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
25730 if (!epiloguep || call_used_regs [i])
25731 clobs[nclobs++] = gen_hard_reg_clobber (V4SImode, i);
25734 rtx reg = gen_rtx_REG (V4SImode, i);
25737 = gen_rtx_SET (reg,
25738 gen_rtx_UNSPEC (V4SImode,
25739 gen_rtvec (1, reg), 27));
25743 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
25745 for (i = 0; i < nclobs; ++i)
25746 XVECEXP (insn, 0, i) = clobs[i];
25752 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
25756 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
25757 mem = gen_frame_mem (GET_MODE (reg), addr);
25758 return gen_rtx_SET (store ? mem : reg, store ? reg : mem);
25762 gen_frame_load (rtx reg, rtx frame_reg, int offset)
25764 return gen_frame_set (reg, frame_reg, offset, false);
25768 gen_frame_store (rtx reg, rtx frame_reg, int offset)
25770 return gen_frame_set (reg, frame_reg, offset, true);
25773 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
25774 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
25777 emit_frame_save (rtx frame_reg, machine_mode mode,
25778 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
25782 /* Some cases that need register indexed addressing. */
25783 gcc_checking_assert (!(TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
25784 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode)));
25786 reg = gen_rtx_REG (mode, regno);
25787 rtx_insn *insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
25788 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
25789 NULL_RTX, NULL_RTX);
25792 /* Emit an offset memory reference suitable for a frame store, while
25793 converting to a valid addressing mode. */
25796 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
25798 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, GEN_INT (offset)));
25801 #ifndef TARGET_FIX_AND_CONTINUE
25802 #define TARGET_FIX_AND_CONTINUE 0
25805 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
25806 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
25807 #define LAST_SAVRES_REGISTER 31
25808 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
25819 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
25821 /* Temporary holding space for an out-of-line register save/restore
25823 static char savres_routine_name[30];
25825 /* Return the name for an out-of-line register save/restore routine.
25826 We are saving/restoring GPRs if GPR is true. */
25829 rs6000_savres_routine_name (int regno, int sel)
25831 const char *prefix = "";
25832 const char *suffix = "";
25834 /* Different targets are supposed to define
25835 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
25836 routine name could be defined with:
25838 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
25840 This is a nice idea in practice, but in reality, things are
25841 complicated in several ways:
25843 - ELF targets have save/restore routines for GPRs.
25845 - PPC64 ELF targets have routines for save/restore of GPRs that
25846 differ in what they do with the link register, so having a set
25847 prefix doesn't work. (We only use one of the save routines at
25848 the moment, though.)
25850 - PPC32 elf targets have "exit" versions of the restore routines
25851 that restore the link register and can save some extra space.
25852 These require an extra suffix. (There are also "tail" versions
25853 of the restore routines and "GOT" versions of the save routines,
25854 but we don't generate those at present. Same problems apply,
25857 We deal with all this by synthesizing our own prefix/suffix and
25858 using that for the simple sprintf call shown above. */
25859 if (DEFAULT_ABI == ABI_V4)
25864 if ((sel & SAVRES_REG) == SAVRES_GPR)
25865 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
25866 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25867 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
25868 else if ((sel & SAVRES_REG) == SAVRES_VR)
25869 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25873 if ((sel & SAVRES_LR))
25876 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25878 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
25879 /* No out-of-line save/restore routines for GPRs on AIX. */
25880 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
25884 if ((sel & SAVRES_REG) == SAVRES_GPR)
25885 prefix = ((sel & SAVRES_SAVE)
25886 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
25887 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
25888 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25890 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
25891 if ((sel & SAVRES_LR))
25892 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
25896 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
25897 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
25900 else if ((sel & SAVRES_REG) == SAVRES_VR)
25901 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
25906 if (DEFAULT_ABI == ABI_DARWIN)
25908 /* The Darwin approach is (slightly) different, in order to be
25909 compatible with code generated by the system toolchain. There is a
25910 single symbol for the start of save sequence, and the code here
25911 embeds an offset into that code on the basis of the first register
25913 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
25914 if ((sel & SAVRES_REG) == SAVRES_GPR)
25915 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
25916 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
25917 (regno - 13) * 4, prefix, regno);
25918 else if ((sel & SAVRES_REG) == SAVRES_FPR)
25919 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
25920 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
25921 else if ((sel & SAVRES_REG) == SAVRES_VR)
25922 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
25923 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
25928 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
25930 return savres_routine_name;
25933 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
25934 We are saving/restoring GPRs if GPR is true. */
25937 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
25939 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
25940 ? info->first_gp_reg_save
25941 : (sel & SAVRES_REG) == SAVRES_FPR
25942 ? info->first_fp_reg_save - 32
25943 : (sel & SAVRES_REG) == SAVRES_VR
25944 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
25949 /* Don't generate bogus routine names. */
25950 gcc_assert (FIRST_SAVRES_REGISTER <= regno
25951 && regno <= LAST_SAVRES_REGISTER
25952 && select >= 0 && select <= 12);
25954 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
25960 name = rs6000_savres_routine_name (regno, sel);
25962 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
25963 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
25964 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
25970 /* Emit a sequence of insns, including a stack tie if needed, for
25971 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
25972 reset the stack pointer, but move the base of the frame into
25973 reg UPDT_REGNO for use by out-of-line register restore routines. */
25976 rs6000_emit_stack_reset (rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
25977 unsigned updt_regno)
25979 /* If there is nothing to do, don't do anything. */
25980 if (frame_off == 0 && REGNO (frame_reg_rtx) == updt_regno)
25983 rtx updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
25985 /* This blockage is needed so that sched doesn't decide to move
25986 the sp change before the register restores. */
25987 if (DEFAULT_ABI == ABI_V4)
25988 return emit_insn (gen_stack_restore_tie (updt_reg_rtx, frame_reg_rtx,
25989 GEN_INT (frame_off)));
25991 /* If we are restoring registers out-of-line, we will be using the
25992 "exit" variants of the restore routines, which will reset the
25993 stack for us. But we do need to point updt_reg into the
25994 right place for those routines. */
25995 if (frame_off != 0)
25996 return emit_insn (gen_add3_insn (updt_reg_rtx,
25997 frame_reg_rtx, GEN_INT (frame_off)));
25999 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
26004 /* Return the register number used as a pointer by out-of-line
26005 save/restore functions. */
26007 static inline unsigned
26008 ptr_regno_for_savres (int sel)
26010 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26011 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
26012 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
26015 /* Construct a parallel rtx describing the effect of a call to an
26016 out-of-line register save/restore routine, and emit the insn
26017 or jump_insn as appropriate. */
26020 rs6000_emit_savres_rtx (rs6000_stack_t *info,
26021 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
26022 machine_mode reg_mode, int sel)
26025 int offset, start_reg, end_reg, n_regs, use_reg;
26026 int reg_size = GET_MODE_SIZE (reg_mode);
26033 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26034 ? info->first_gp_reg_save
26035 : (sel & SAVRES_REG) == SAVRES_FPR
26036 ? info->first_fp_reg_save
26037 : (sel & SAVRES_REG) == SAVRES_VR
26038 ? info->first_altivec_reg_save
26040 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
26042 : (sel & SAVRES_REG) == SAVRES_FPR
26044 : (sel & SAVRES_REG) == SAVRES_VR
26045 ? LAST_ALTIVEC_REGNO + 1
26047 n_regs = end_reg - start_reg;
26048 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
26049 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
26052 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26053 RTVEC_ELT (p, offset++) = ret_rtx;
26055 RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, LR_REGNO);
26057 sym = rs6000_savres_routine_sym (info, sel);
26058 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
26060 use_reg = ptr_regno_for_savres (sel);
26061 if ((sel & SAVRES_REG) == SAVRES_VR)
26063 /* Vector regs are saved/restored using [reg+reg] addressing. */
26064 RTVEC_ELT (p, offset++) = gen_hard_reg_clobber (Pmode, use_reg);
26065 RTVEC_ELT (p, offset++)
26066 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
26069 RTVEC_ELT (p, offset++)
26070 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
26072 for (i = 0; i < end_reg - start_reg; i++)
26073 RTVEC_ELT (p, i + offset)
26074 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
26075 frame_reg_rtx, save_area_offset + reg_size * i,
26076 (sel & SAVRES_SAVE) != 0);
26078 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26079 RTVEC_ELT (p, i + offset)
26080 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
26082 par = gen_rtx_PARALLEL (VOIDmode, p);
26084 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
26086 insn = emit_jump_insn (par);
26087 JUMP_LABEL (insn) = ret_rtx;
26090 insn = emit_insn (par);
26094 /* Emit prologue code to store CR fields that need to be saved into REG. This
26095 function should only be called when moving the non-volatile CRs to REG, it
26096 is not a general purpose routine to move the entire set of CRs to REG.
26097 Specifically, gen_prologue_movesi_from_cr() does not contain uses of the
26101 rs6000_emit_prologue_move_from_cr (rtx reg)
26103 /* Only the ELFv2 ABI allows storing only selected fields. */
26104 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
26106 int i, cr_reg[8], count = 0;
26108 /* Collect CR fields that must be saved. */
26109 for (i = 0; i < 8; i++)
26110 if (save_reg_p (CR0_REGNO + i))
26111 cr_reg[count++] = i;
26113 /* If it's just a single one, use mfcrf. */
26116 rtvec p = rtvec_alloc (1);
26117 rtvec r = rtvec_alloc (2);
26118 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
26119 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
26121 = gen_rtx_SET (reg,
26122 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
26124 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26128 /* ??? It might be better to handle count == 2 / 3 cases here
26129 as well, using logical operations to combine the values. */
26132 emit_insn (gen_prologue_movesi_from_cr (reg));
26135 /* Return whether the split-stack arg pointer (r12) is used. */
26138 split_stack_arg_pointer_used_p (void)
26140 /* If the pseudo holding the arg pointer is no longer a pseudo,
26141 then the arg pointer is used. */
26142 if (cfun->machine->split_stack_arg_pointer != NULL_RTX
26143 && (!REG_P (cfun->machine->split_stack_arg_pointer)
26144 || HARD_REGISTER_P (cfun->machine->split_stack_arg_pointer)))
26147 /* Unfortunately we also need to do some code scanning, since
26148 r12 may have been substituted for the pseudo. */
26150 basic_block bb = ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb;
26151 FOR_BB_INSNS (bb, insn)
26152 if (NONDEBUG_INSN_P (insn))
26154 /* A call destroys r12. */
26159 FOR_EACH_INSN_USE (use, insn)
26161 rtx x = DF_REF_REG (use);
26162 if (REG_P (x) && REGNO (x) == 12)
26166 FOR_EACH_INSN_DEF (def, insn)
26168 rtx x = DF_REF_REG (def);
26169 if (REG_P (x) && REGNO (x) == 12)
26173 return bitmap_bit_p (DF_LR_OUT (bb), 12);
26176 /* Return whether we need to emit an ELFv2 global entry point prologue. */
26179 rs6000_global_entry_point_needed_p (void)
26181 /* Only needed for the ELFv2 ABI. */
26182 if (DEFAULT_ABI != ABI_ELFv2)
26185 /* With -msingle-pic-base, we assume the whole program shares the same
26186 TOC, so no global entry point prologues are needed anywhere. */
26187 if (TARGET_SINGLE_PIC_BASE)
26190 /* Ensure we have a global entry point for thunks. ??? We could
26191 avoid that if the target routine doesn't need a global entry point,
26192 but we do not know whether this is the case at this point. */
26193 if (cfun->is_thunk)
26196 /* For regular functions, rs6000_emit_prologue sets this flag if the
26197 routine ever uses the TOC pointer. */
26198 return cfun->machine->r2_setup_needed;
26201 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
26203 rs6000_get_separate_components (void)
26205 rs6000_stack_t *info = rs6000_stack_info ();
26207 if (WORLD_SAVE_P (info))
26210 gcc_assert (!(info->savres_strategy & SAVE_MULTIPLE)
26211 && !(info->savres_strategy & REST_MULTIPLE));
26213 /* Component 0 is the save/restore of LR (done via GPR0).
26214 Component 2 is the save of the TOC (GPR2).
26215 Components 13..31 are the save/restore of GPR13..GPR31.
26216 Components 46..63 are the save/restore of FPR14..FPR31. */
26218 cfun->machine->n_components = 64;
26220 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26221 bitmap_clear (components);
26223 int reg_size = TARGET_32BIT ? 4 : 8;
26224 int fp_reg_size = 8;
26226 /* The GPRs we need saved to the frame. */
26227 if ((info->savres_strategy & SAVE_INLINE_GPRS)
26228 && (info->savres_strategy & REST_INLINE_GPRS))
26230 int offset = info->gp_save_offset;
26232 offset += info->total_size;
26234 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26236 if (IN_RANGE (offset, -0x8000, 0x7fff)
26237 && save_reg_p (regno))
26238 bitmap_set_bit (components, regno);
26240 offset += reg_size;
26244 /* Don't mess with the hard frame pointer. */
26245 if (frame_pointer_needed)
26246 bitmap_clear_bit (components, HARD_FRAME_POINTER_REGNUM);
26248 /* Don't mess with the fixed TOC register. */
26249 if ((TARGET_TOC && TARGET_MINIMAL_TOC)
26250 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
26251 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
26252 bitmap_clear_bit (components, RS6000_PIC_OFFSET_TABLE_REGNUM);
26254 /* The FPRs we need saved to the frame. */
26255 if ((info->savres_strategy & SAVE_INLINE_FPRS)
26256 && (info->savres_strategy & REST_INLINE_FPRS))
26258 int offset = info->fp_save_offset;
26260 offset += info->total_size;
26262 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26264 if (IN_RANGE (offset, -0x8000, 0x7fff) && save_reg_p (regno))
26265 bitmap_set_bit (components, regno);
26267 offset += fp_reg_size;
26271 /* Optimize LR save and restore if we can. This is component 0. Any
26272 out-of-line register save/restore routines need LR. */
26273 if (info->lr_save_p
26274 && !(flag_pic && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
26275 && (info->savres_strategy & SAVE_INLINE_GPRS)
26276 && (info->savres_strategy & REST_INLINE_GPRS)
26277 && (info->savres_strategy & SAVE_INLINE_FPRS)
26278 && (info->savres_strategy & REST_INLINE_FPRS)
26279 && (info->savres_strategy & SAVE_INLINE_VRS)
26280 && (info->savres_strategy & REST_INLINE_VRS))
26282 int offset = info->lr_save_offset;
26284 offset += info->total_size;
26285 if (IN_RANGE (offset, -0x8000, 0x7fff))
26286 bitmap_set_bit (components, 0);
26289 /* Optimize saving the TOC. This is component 2. */
26290 if (cfun->machine->save_toc_in_prologue)
26291 bitmap_set_bit (components, 2);
26296 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
26298 rs6000_components_for_bb (basic_block bb)
26300 rs6000_stack_t *info = rs6000_stack_info ();
26302 bitmap in = DF_LIVE_IN (bb);
26303 bitmap gen = &DF_LIVE_BB_INFO (bb)->gen;
26304 bitmap kill = &DF_LIVE_BB_INFO (bb)->kill;
26306 sbitmap components = sbitmap_alloc (cfun->machine->n_components);
26307 bitmap_clear (components);
26309 /* A register is used in a bb if it is in the IN, GEN, or KILL sets. */
26312 for (unsigned regno = info->first_gp_reg_save; regno < 32; regno++)
26313 if (bitmap_bit_p (in, regno)
26314 || bitmap_bit_p (gen, regno)
26315 || bitmap_bit_p (kill, regno))
26316 bitmap_set_bit (components, regno);
26319 for (unsigned regno = info->first_fp_reg_save; regno < 64; regno++)
26320 if (bitmap_bit_p (in, regno)
26321 || bitmap_bit_p (gen, regno)
26322 || bitmap_bit_p (kill, regno))
26323 bitmap_set_bit (components, regno);
26325 /* The link register. */
26326 if (bitmap_bit_p (in, LR_REGNO)
26327 || bitmap_bit_p (gen, LR_REGNO)
26328 || bitmap_bit_p (kill, LR_REGNO))
26329 bitmap_set_bit (components, 0);
26331 /* The TOC save. */
26332 if (bitmap_bit_p (in, TOC_REGNUM)
26333 || bitmap_bit_p (gen, TOC_REGNUM)
26334 || bitmap_bit_p (kill, TOC_REGNUM))
26335 bitmap_set_bit (components, 2);
26340 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
26342 rs6000_disqualify_components (sbitmap components, edge e,
26343 sbitmap edge_components, bool /*is_prologue*/)
26345 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
26346 live where we want to place that code. */
26347 if (bitmap_bit_p (edge_components, 0)
26348 && bitmap_bit_p (DF_LIVE_IN (e->dest), 0))
26351 fprintf (dump_file, "Disqualifying LR because GPR0 is live "
26352 "on entry to bb %d\n", e->dest->index);
26353 bitmap_clear_bit (components, 0);
26357 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
26359 rs6000_emit_prologue_components (sbitmap components)
26361 rs6000_stack_t *info = rs6000_stack_info ();
26362 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26363 ? HARD_FRAME_POINTER_REGNUM
26364 : STACK_POINTER_REGNUM);
26366 machine_mode reg_mode = Pmode;
26367 int reg_size = TARGET_32BIT ? 4 : 8;
26368 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26369 int fp_reg_size = 8;
26371 /* Prologue for LR. */
26372 if (bitmap_bit_p (components, 0))
26374 rtx lr = gen_rtx_REG (reg_mode, LR_REGNO);
26375 rtx reg = gen_rtx_REG (reg_mode, 0);
26376 rtx_insn *insn = emit_move_insn (reg, lr);
26377 RTX_FRAME_RELATED_P (insn) = 1;
26378 add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (reg, lr));
26380 int offset = info->lr_save_offset;
26382 offset += info->total_size;
26384 insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26385 RTX_FRAME_RELATED_P (insn) = 1;
26386 rtx mem = copy_rtx (SET_DEST (single_set (insn)));
26387 add_reg_note (insn, REG_CFA_OFFSET, gen_rtx_SET (mem, lr));
26390 /* Prologue for TOC. */
26391 if (bitmap_bit_p (components, 2))
26393 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
26394 rtx sp_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26395 emit_insn (gen_frame_store (reg, sp_reg, RS6000_TOC_SAVE_SLOT));
26398 /* Prologue for the GPRs. */
26399 int offset = info->gp_save_offset;
26401 offset += info->total_size;
26403 for (int i = info->first_gp_reg_save; i < 32; i++)
26405 if (bitmap_bit_p (components, i))
26407 rtx reg = gen_rtx_REG (reg_mode, i);
26408 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26409 RTX_FRAME_RELATED_P (insn) = 1;
26410 rtx set = copy_rtx (single_set (insn));
26411 add_reg_note (insn, REG_CFA_OFFSET, set);
26414 offset += reg_size;
26417 /* Prologue for the FPRs. */
26418 offset = info->fp_save_offset;
26420 offset += info->total_size;
26422 for (int i = info->first_fp_reg_save; i < 64; i++)
26424 if (bitmap_bit_p (components, i))
26426 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26427 rtx_insn *insn = emit_insn (gen_frame_store (reg, ptr_reg, offset));
26428 RTX_FRAME_RELATED_P (insn) = 1;
26429 rtx set = copy_rtx (single_set (insn));
26430 add_reg_note (insn, REG_CFA_OFFSET, set);
26433 offset += fp_reg_size;
26437 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
26439 rs6000_emit_epilogue_components (sbitmap components)
26441 rs6000_stack_t *info = rs6000_stack_info ();
26442 rtx ptr_reg = gen_rtx_REG (Pmode, frame_pointer_needed
26443 ? HARD_FRAME_POINTER_REGNUM
26444 : STACK_POINTER_REGNUM);
26446 machine_mode reg_mode = Pmode;
26447 int reg_size = TARGET_32BIT ? 4 : 8;
26449 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26450 int fp_reg_size = 8;
26452 /* Epilogue for the FPRs. */
26453 int offset = info->fp_save_offset;
26455 offset += info->total_size;
26457 for (int i = info->first_fp_reg_save; i < 64; i++)
26459 if (bitmap_bit_p (components, i))
26461 rtx reg = gen_rtx_REG (fp_reg_mode, i);
26462 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26463 RTX_FRAME_RELATED_P (insn) = 1;
26464 add_reg_note (insn, REG_CFA_RESTORE, reg);
26467 offset += fp_reg_size;
26470 /* Epilogue for the GPRs. */
26471 offset = info->gp_save_offset;
26473 offset += info->total_size;
26475 for (int i = info->first_gp_reg_save; i < 32; i++)
26477 if (bitmap_bit_p (components, i))
26479 rtx reg = gen_rtx_REG (reg_mode, i);
26480 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26481 RTX_FRAME_RELATED_P (insn) = 1;
26482 add_reg_note (insn, REG_CFA_RESTORE, reg);
26485 offset += reg_size;
26488 /* Epilogue for LR. */
26489 if (bitmap_bit_p (components, 0))
26491 int offset = info->lr_save_offset;
26493 offset += info->total_size;
26495 rtx reg = gen_rtx_REG (reg_mode, 0);
26496 rtx_insn *insn = emit_insn (gen_frame_load (reg, ptr_reg, offset));
26498 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
26499 insn = emit_move_insn (lr, reg);
26500 RTX_FRAME_RELATED_P (insn) = 1;
26501 add_reg_note (insn, REG_CFA_RESTORE, lr);
26505 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
26507 rs6000_set_handled_components (sbitmap components)
26509 rs6000_stack_t *info = rs6000_stack_info ();
26511 for (int i = info->first_gp_reg_save; i < 32; i++)
26512 if (bitmap_bit_p (components, i))
26513 cfun->machine->gpr_is_wrapped_separately[i] = true;
26515 for (int i = info->first_fp_reg_save; i < 64; i++)
26516 if (bitmap_bit_p (components, i))
26517 cfun->machine->fpr_is_wrapped_separately[i - 32] = true;
26519 if (bitmap_bit_p (components, 0))
26520 cfun->machine->lr_is_wrapped_separately = true;
26522 if (bitmap_bit_p (components, 2))
26523 cfun->machine->toc_is_wrapped_separately = true;
26526 /* VRSAVE is a bit vector representing which AltiVec registers
26527 are used. The OS uses this to determine which vector
26528 registers to save on a context switch. We need to save
26529 VRSAVE on the stack frame, add whatever AltiVec registers we
26530 used in this function, and do the corresponding magic in the
26533 emit_vrsave_prologue (rs6000_stack_t *info, int save_regno,
26534 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26536 /* Get VRSAVE into a GPR. */
26537 rtx reg = gen_rtx_REG (SImode, save_regno);
26538 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
26540 emit_insn (gen_get_vrsave_internal (reg));
26542 emit_insn (gen_rtx_SET (reg, vrsave));
26545 int offset = info->vrsave_save_offset + frame_off;
26546 emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
26548 /* Include the registers in the mask. */
26549 emit_insn (gen_iorsi3 (reg, reg, GEN_INT (info->vrsave_mask)));
26551 emit_insn (generate_set_vrsave (reg, info, 0));
26554 /* Set up the arg pointer (r12) for -fsplit-stack code. If __morestack was
26555 called, it left the arg pointer to the old stack in r29. Otherwise, the
26556 arg pointer is the top of the current frame. */
26558 emit_split_stack_prologue (rs6000_stack_t *info, rtx_insn *sp_adjust,
26559 HOST_WIDE_INT frame_off, rtx frame_reg_rtx)
26561 cfun->machine->split_stack_argp_used = true;
26565 rtx r12 = gen_rtx_REG (Pmode, 12);
26566 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26567 rtx set_r12 = gen_rtx_SET (r12, sp_reg_rtx);
26568 emit_insn_before (set_r12, sp_adjust);
26570 else if (frame_off != 0 || REGNO (frame_reg_rtx) != 12)
26572 rtx r12 = gen_rtx_REG (Pmode, 12);
26573 if (frame_off == 0)
26574 emit_move_insn (r12, frame_reg_rtx);
26576 emit_insn (gen_add3_insn (r12, frame_reg_rtx, GEN_INT (frame_off)));
26581 rtx r12 = gen_rtx_REG (Pmode, 12);
26582 rtx r29 = gen_rtx_REG (Pmode, 29);
26583 rtx cr7 = gen_rtx_REG (CCUNSmode, CR7_REGNO);
26584 rtx not_more = gen_label_rtx ();
26587 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
26588 gen_rtx_GEU (VOIDmode, cr7, const0_rtx),
26589 gen_rtx_LABEL_REF (VOIDmode, not_more),
26591 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
26592 JUMP_LABEL (jump) = not_more;
26593 LABEL_NUSES (not_more) += 1;
26594 emit_move_insn (r12, r29);
26595 emit_label (not_more);
26599 /* Emit function prologue as insns. */
26602 rs6000_emit_prologue (void)
26604 rs6000_stack_t *info = rs6000_stack_info ();
26605 machine_mode reg_mode = Pmode;
26606 int reg_size = TARGET_32BIT ? 4 : 8;
26607 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
26608 int fp_reg_size = 8;
26609 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
26610 rtx frame_reg_rtx = sp_reg_rtx;
26611 unsigned int cr_save_regno;
26612 rtx cr_save_rtx = NULL_RTX;
26615 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
26616 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
26617 && call_used_regs[STATIC_CHAIN_REGNUM]);
26618 int using_split_stack = (flag_split_stack
26619 && (lookup_attribute ("no_split_stack",
26620 DECL_ATTRIBUTES (cfun->decl))
26623 /* Offset to top of frame for frame_reg and sp respectively. */
26624 HOST_WIDE_INT frame_off = 0;
26625 HOST_WIDE_INT sp_off = 0;
26626 /* sp_adjust is the stack adjusting instruction, tracked so that the
26627 insn setting up the split-stack arg pointer can be emitted just
26628 prior to it, when r12 is not used here for other purposes. */
26629 rtx_insn *sp_adjust = 0;
26632 /* Track and check usage of r0, r11, r12. */
26633 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
26634 #define START_USE(R) do \
26636 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26637 reg_inuse |= 1 << (R); \
26639 #define END_USE(R) do \
26641 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
26642 reg_inuse &= ~(1 << (R)); \
26644 #define NOT_INUSE(R) do \
26646 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
26649 #define START_USE(R) do {} while (0)
26650 #define END_USE(R) do {} while (0)
26651 #define NOT_INUSE(R) do {} while (0)
26654 if (DEFAULT_ABI == ABI_ELFv2
26655 && !TARGET_SINGLE_PIC_BASE)
26657 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
26659 /* With -mminimal-toc we may generate an extra use of r2 below. */
26660 if (TARGET_TOC && TARGET_MINIMAL_TOC
26661 && !constant_pool_empty_p ())
26662 cfun->machine->r2_setup_needed = true;
26666 if (flag_stack_usage_info)
26667 current_function_static_stack_size = info->total_size;
26669 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
26671 HOST_WIDE_INT size = info->total_size;
26673 if (crtl->is_leaf && !cfun->calls_alloca)
26675 if (size > PROBE_INTERVAL && size > get_stack_check_protect ())
26676 rs6000_emit_probe_stack_range (get_stack_check_protect (),
26677 size - get_stack_check_protect ());
26680 rs6000_emit_probe_stack_range (get_stack_check_protect (), size);
26683 if (TARGET_FIX_AND_CONTINUE)
26685 /* gdb on darwin arranges to forward a function from the old
26686 address by modifying the first 5 instructions of the function
26687 to branch to the overriding function. This is necessary to
26688 permit function pointers that point to the old function to
26689 actually forward to the new function. */
26690 emit_insn (gen_nop ());
26691 emit_insn (gen_nop ());
26692 emit_insn (gen_nop ());
26693 emit_insn (gen_nop ());
26694 emit_insn (gen_nop ());
26697 /* Handle world saves specially here. */
26698 if (WORLD_SAVE_P (info))
26705 /* save_world expects lr in r0. */
26706 reg0 = gen_rtx_REG (Pmode, 0);
26707 if (info->lr_save_p)
26709 insn = emit_move_insn (reg0,
26710 gen_rtx_REG (Pmode, LR_REGNO));
26711 RTX_FRAME_RELATED_P (insn) = 1;
26714 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
26715 assumptions about the offsets of various bits of the stack
26717 gcc_assert (info->gp_save_offset == -220
26718 && info->fp_save_offset == -144
26719 && info->lr_save_offset == 8
26720 && info->cr_save_offset == 4
26723 && (!crtl->calls_eh_return
26724 || info->ehrd_offset == -432)
26725 && info->vrsave_save_offset == -224
26726 && info->altivec_save_offset == -416);
26728 treg = gen_rtx_REG (SImode, 11);
26729 emit_move_insn (treg, GEN_INT (-info->total_size));
26731 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
26732 in R11. It also clobbers R12, so beware! */
26734 /* Preserve CR2 for save_world prologues */
26736 sz += 32 - info->first_gp_reg_save;
26737 sz += 64 - info->first_fp_reg_save;
26738 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
26739 p = rtvec_alloc (sz);
26741 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, LR_REGNO);
26742 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
26743 gen_rtx_SYMBOL_REF (Pmode,
26745 /* We do floats first so that the instruction pattern matches
26747 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
26749 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
26750 info->first_fp_reg_save + i),
26752 info->fp_save_offset + frame_off + 8 * i);
26753 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
26755 = gen_frame_store (gen_rtx_REG (V4SImode,
26756 info->first_altivec_reg_save + i),
26758 info->altivec_save_offset + frame_off + 16 * i);
26759 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26761 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26763 info->gp_save_offset + frame_off + reg_size * i);
26765 /* CR register traditionally saved as CR2. */
26767 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
26768 frame_reg_rtx, info->cr_save_offset + frame_off);
26769 /* Explain about use of R0. */
26770 if (info->lr_save_p)
26772 = gen_frame_store (reg0,
26773 frame_reg_rtx, info->lr_save_offset + frame_off);
26774 /* Explain what happens to the stack pointer. */
26776 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
26777 RTVEC_ELT (p, j++) = gen_rtx_SET (sp_reg_rtx, newval);
26780 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26781 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26782 treg, GEN_INT (-info->total_size));
26783 sp_off = frame_off = info->total_size;
26786 strategy = info->savres_strategy;
26788 /* For V.4, update stack before we do any saving and set back pointer. */
26789 if (! WORLD_SAVE_P (info)
26791 && (DEFAULT_ABI == ABI_V4
26792 || crtl->calls_eh_return))
26794 bool need_r11 = (!(strategy & SAVE_INLINE_FPRS)
26795 || !(strategy & SAVE_INLINE_GPRS)
26796 || !(strategy & SAVE_INLINE_VRS));
26797 int ptr_regno = -1;
26798 rtx ptr_reg = NULL_RTX;
26801 if (info->total_size < 32767)
26802 frame_off = info->total_size;
26805 else if (info->cr_save_p
26807 || info->first_fp_reg_save < 64
26808 || info->first_gp_reg_save < 32
26809 || info->altivec_size != 0
26810 || info->vrsave_size != 0
26811 || crtl->calls_eh_return)
26815 /* The prologue won't be saving any regs so there is no need
26816 to set up a frame register to access any frame save area.
26817 We also won't be using frame_off anywhere below, but set
26818 the correct value anyway to protect against future
26819 changes to this function. */
26820 frame_off = info->total_size;
26822 if (ptr_regno != -1)
26824 /* Set up the frame offset to that needed by the first
26825 out-of-line save function. */
26826 START_USE (ptr_regno);
26827 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26828 frame_reg_rtx = ptr_reg;
26829 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
26830 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
26831 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
26832 ptr_off = info->gp_save_offset + info->gp_size;
26833 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
26834 ptr_off = info->altivec_save_offset + info->altivec_size;
26835 frame_off = -ptr_off;
26837 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
26839 if (REGNO (frame_reg_rtx) == 12)
26841 sp_off = info->total_size;
26842 if (frame_reg_rtx != sp_reg_rtx)
26843 rs6000_emit_stack_tie (frame_reg_rtx, false);
26846 /* If we use the link register, get it into r0. */
26847 if (!WORLD_SAVE_P (info) && info->lr_save_p
26848 && !cfun->machine->lr_is_wrapped_separately)
26850 rtx addr, reg, mem;
26852 reg = gen_rtx_REG (Pmode, 0);
26854 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
26855 RTX_FRAME_RELATED_P (insn) = 1;
26857 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
26858 | SAVE_NOINLINE_FPRS_SAVES_LR)))
26860 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
26861 GEN_INT (info->lr_save_offset + frame_off));
26862 mem = gen_rtx_MEM (Pmode, addr);
26863 /* This should not be of rs6000_sr_alias_set, because of
26864 __builtin_return_address. */
26866 insn = emit_move_insn (mem, reg);
26867 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26868 NULL_RTX, NULL_RTX);
26873 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
26874 r12 will be needed by out-of-line gpr save. */
26875 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26876 && !(strategy & (SAVE_INLINE_GPRS
26877 | SAVE_NOINLINE_GPRS_SAVES_LR))
26879 if (!WORLD_SAVE_P (info)
26881 && REGNO (frame_reg_rtx) != cr_save_regno
26882 && !(using_static_chain_p && cr_save_regno == 11)
26883 && !(using_split_stack && cr_save_regno == 12 && sp_adjust))
26885 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
26886 START_USE (cr_save_regno);
26887 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
26890 /* Do any required saving of fpr's. If only one or two to save, do
26891 it ourselves. Otherwise, call function. */
26892 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
26894 int offset = info->fp_save_offset + frame_off;
26895 for (int i = info->first_fp_reg_save; i < 64; i++)
26898 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
26899 emit_frame_save (frame_reg_rtx, fp_reg_mode, i, offset,
26900 sp_off - frame_off);
26902 offset += fp_reg_size;
26905 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
26907 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
26908 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
26909 unsigned ptr_regno = ptr_regno_for_savres (sel);
26910 rtx ptr_reg = frame_reg_rtx;
26912 if (REGNO (frame_reg_rtx) == ptr_regno)
26913 gcc_checking_assert (frame_off == 0);
26916 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26917 NOT_INUSE (ptr_regno);
26918 emit_insn (gen_add3_insn (ptr_reg,
26919 frame_reg_rtx, GEN_INT (frame_off)));
26921 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26922 info->fp_save_offset,
26923 info->lr_save_offset,
26925 rs6000_frame_related (insn, ptr_reg, sp_off,
26926 NULL_RTX, NULL_RTX);
26931 /* Save GPRs. This is done as a PARALLEL if we are using
26932 the store-multiple instructions. */
26933 if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
26935 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
26936 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
26937 unsigned ptr_regno = ptr_regno_for_savres (sel);
26938 rtx ptr_reg = frame_reg_rtx;
26939 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
26940 int end_save = info->gp_save_offset + info->gp_size;
26943 if (ptr_regno == 12)
26946 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
26948 /* Need to adjust r11 (r12) if we saved any FPRs. */
26949 if (end_save + frame_off != 0)
26951 rtx offset = GEN_INT (end_save + frame_off);
26954 frame_off = -end_save;
26956 NOT_INUSE (ptr_regno);
26957 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
26959 else if (!ptr_set_up)
26961 NOT_INUSE (ptr_regno);
26962 emit_move_insn (ptr_reg, frame_reg_rtx);
26964 ptr_off = -end_save;
26965 insn = rs6000_emit_savres_rtx (info, ptr_reg,
26966 info->gp_save_offset + ptr_off,
26967 info->lr_save_offset + ptr_off,
26969 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
26970 NULL_RTX, NULL_RTX);
26974 else if (!WORLD_SAVE_P (info) && (strategy & SAVE_MULTIPLE))
26978 p = rtvec_alloc (32 - info->first_gp_reg_save);
26979 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
26981 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
26983 info->gp_save_offset + frame_off + reg_size * i);
26984 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
26985 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
26986 NULL_RTX, NULL_RTX);
26988 else if (!WORLD_SAVE_P (info))
26990 int offset = info->gp_save_offset + frame_off;
26991 for (int i = info->first_gp_reg_save; i < 32; i++)
26994 && !cfun->machine->gpr_is_wrapped_separately[i])
26995 emit_frame_save (frame_reg_rtx, reg_mode, i, offset,
26996 sp_off - frame_off);
26998 offset += reg_size;
27002 if (crtl->calls_eh_return)
27009 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27010 if (regno == INVALID_REGNUM)
27014 p = rtvec_alloc (i);
27018 unsigned int regno = EH_RETURN_DATA_REGNO (i);
27019 if (regno == INVALID_REGNUM)
27023 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
27025 info->ehrd_offset + sp_off + reg_size * (int) i);
27026 RTVEC_ELT (p, i) = set;
27027 RTX_FRAME_RELATED_P (set) = 1;
27030 insn = emit_insn (gen_blockage ());
27031 RTX_FRAME_RELATED_P (insn) = 1;
27032 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
27035 /* In AIX ABI we need to make sure r2 is really saved. */
27036 if (TARGET_AIX && crtl->calls_eh_return)
27038 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
27039 rtx join_insn, note;
27040 rtx_insn *save_insn;
27041 long toc_restore_insn;
27043 tmp_reg = gen_rtx_REG (Pmode, 11);
27044 tmp_reg_si = gen_rtx_REG (SImode, 11);
27045 if (using_static_chain_p)
27048 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
27052 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
27053 /* Peek at instruction to which this function returns. If it's
27054 restoring r2, then we know we've already saved r2. We can't
27055 unconditionally save r2 because the value we have will already
27056 be updated if we arrived at this function via a plt call or
27057 toc adjusting stub. */
27058 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
27059 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
27060 + RS6000_TOC_SAVE_SLOT);
27061 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
27062 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
27063 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
27064 validate_condition_mode (EQ, CCUNSmode);
27065 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
27066 emit_insn (gen_rtx_SET (compare_result,
27067 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
27068 toc_save_done = gen_label_rtx ();
27069 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
27070 gen_rtx_EQ (VOIDmode, compare_result,
27072 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
27074 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
27075 JUMP_LABEL (jump) = toc_save_done;
27076 LABEL_NUSES (toc_save_done) += 1;
27078 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
27079 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
27080 sp_off - frame_off);
27082 emit_label (toc_save_done);
27084 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
27085 have a CFG that has different saves along different paths.
27086 Move the note to a dummy blockage insn, which describes that
27087 R2 is unconditionally saved after the label. */
27088 /* ??? An alternate representation might be a special insn pattern
27089 containing both the branch and the store. That might let the
27090 code that minimizes the number of DW_CFA_advance opcodes better
27091 freedom in placing the annotations. */
27092 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
27094 remove_note (save_insn, note);
27096 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
27097 copy_rtx (PATTERN (save_insn)), NULL_RTX);
27098 RTX_FRAME_RELATED_P (save_insn) = 0;
27100 join_insn = emit_insn (gen_blockage ());
27101 REG_NOTES (join_insn) = note;
27102 RTX_FRAME_RELATED_P (join_insn) = 1;
27104 if (using_static_chain_p)
27106 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
27113 /* Save CR if we use any that must be preserved. */
27114 if (!WORLD_SAVE_P (info) && info->cr_save_p)
27116 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
27117 GEN_INT (info->cr_save_offset + frame_off));
27118 rtx mem = gen_frame_mem (SImode, addr);
27120 /* If we didn't copy cr before, do so now using r0. */
27121 if (cr_save_rtx == NULL_RTX)
27124 cr_save_rtx = gen_rtx_REG (SImode, 0);
27125 rs6000_emit_prologue_move_from_cr (cr_save_rtx);
27128 /* Saving CR requires a two-instruction sequence: one instruction
27129 to move the CR to a general-purpose register, and a second
27130 instruction that stores the GPR to memory.
27132 We do not emit any DWARF CFI records for the first of these,
27133 because we cannot properly represent the fact that CR is saved in
27134 a register. One reason is that we cannot express that multiple
27135 CR fields are saved; another reason is that on 64-bit, the size
27136 of the CR register in DWARF (4 bytes) differs from the size of
27137 a general-purpose register.
27139 This means if any intervening instruction were to clobber one of
27140 the call-saved CR fields, we'd have incorrect CFI. To prevent
27141 this from happening, we mark the store to memory as a use of
27142 those CR fields, which prevents any such instruction from being
27143 scheduled in between the two instructions. */
27148 crsave_v[n_crsave++] = gen_rtx_SET (mem, cr_save_rtx);
27149 for (i = 0; i < 8; i++)
27150 if (save_reg_p (CR0_REGNO + i))
27151 crsave_v[n_crsave++]
27152 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27154 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
27155 gen_rtvec_v (n_crsave, crsave_v)));
27156 END_USE (REGNO (cr_save_rtx));
27158 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
27159 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
27160 so we need to construct a frame expression manually. */
27161 RTX_FRAME_RELATED_P (insn) = 1;
27163 /* Update address to be stack-pointer relative, like
27164 rs6000_frame_related would do. */
27165 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
27166 GEN_INT (info->cr_save_offset + sp_off));
27167 mem = gen_frame_mem (SImode, addr);
27169 if (DEFAULT_ABI == ABI_ELFv2)
27171 /* In the ELFv2 ABI we generate separate CFI records for each
27172 CR field that was actually saved. They all point to the
27173 same 32-bit stack slot. */
27177 for (i = 0; i < 8; i++)
27178 if (save_reg_p (CR0_REGNO + i))
27181 = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR0_REGNO + i));
27183 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
27187 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27188 gen_rtx_PARALLEL (VOIDmode,
27189 gen_rtvec_v (n_crframe, crframe)));
27193 /* In other ABIs, by convention, we use a single CR regnum to
27194 represent the fact that all call-saved CR fields are saved.
27195 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
27196 rtx set = gen_rtx_SET (mem, gen_rtx_REG (SImode, CR2_REGNO));
27197 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
27201 /* In the ELFv2 ABI we need to save all call-saved CR fields into
27202 *separate* slots if the routine calls __builtin_eh_return, so
27203 that they can be independently restored by the unwinder. */
27204 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
27206 int i, cr_off = info->ehcr_offset;
27209 /* ??? We might get better performance by using multiple mfocrf
27211 crsave = gen_rtx_REG (SImode, 0);
27212 emit_insn (gen_prologue_movesi_from_cr (crsave));
27214 for (i = 0; i < 8; i++)
27215 if (!call_used_regs[CR0_REGNO + i])
27217 rtvec p = rtvec_alloc (2);
27219 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
27221 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
27223 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27225 RTX_FRAME_RELATED_P (insn) = 1;
27226 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
27227 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
27228 sp_reg_rtx, cr_off + sp_off));
27230 cr_off += reg_size;
27234 /* If we are emitting stack probes, but allocate no stack, then
27235 just note that in the dump file. */
27236 if (flag_stack_clash_protection
27239 dump_stack_clash_frame_info (NO_PROBE_NO_FRAME, false);
27241 /* Update stack and set back pointer unless this is V.4,
27242 for which it was done previously. */
27243 if (!WORLD_SAVE_P (info) && info->push_p
27244 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
27246 rtx ptr_reg = NULL;
27249 /* If saving altivec regs we need to be able to address all save
27250 locations using a 16-bit offset. */
27251 if ((strategy & SAVE_INLINE_VRS) == 0
27252 || (info->altivec_size != 0
27253 && (info->altivec_save_offset + info->altivec_size - 16
27254 + info->total_size - frame_off) > 32767)
27255 || (info->vrsave_size != 0
27256 && (info->vrsave_save_offset
27257 + info->total_size - frame_off) > 32767))
27259 int sel = SAVRES_SAVE | SAVRES_VR;
27260 unsigned ptr_regno = ptr_regno_for_savres (sel);
27262 if (using_static_chain_p
27263 && ptr_regno == STATIC_CHAIN_REGNUM)
27265 if (REGNO (frame_reg_rtx) != ptr_regno)
27266 START_USE (ptr_regno);
27267 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
27268 frame_reg_rtx = ptr_reg;
27269 ptr_off = info->altivec_save_offset + info->altivec_size;
27270 frame_off = -ptr_off;
27272 else if (REGNO (frame_reg_rtx) == 1)
27273 frame_off = info->total_size;
27274 sp_adjust = rs6000_emit_allocate_stack (info->total_size,
27276 if (REGNO (frame_reg_rtx) == 12)
27278 sp_off = info->total_size;
27279 if (frame_reg_rtx != sp_reg_rtx)
27280 rs6000_emit_stack_tie (frame_reg_rtx, false);
27283 /* Set frame pointer, if needed. */
27284 if (frame_pointer_needed)
27286 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
27288 RTX_FRAME_RELATED_P (insn) = 1;
27291 /* Save AltiVec registers if needed. Save here because the red zone does
27292 not always include AltiVec registers. */
27293 if (!WORLD_SAVE_P (info)
27294 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
27296 int end_save = info->altivec_save_offset + info->altivec_size;
27298 /* Oddly, the vector save/restore functions point r0 at the end
27299 of the save area, then use r11 or r12 to load offsets for
27300 [reg+reg] addressing. */
27301 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
27302 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
27303 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
27305 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27307 if (scratch_regno == 12)
27309 if (end_save + frame_off != 0)
27311 rtx offset = GEN_INT (end_save + frame_off);
27313 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
27316 emit_move_insn (ptr_reg, frame_reg_rtx);
27318 ptr_off = -end_save;
27319 insn = rs6000_emit_savres_rtx (info, scratch_reg,
27320 info->altivec_save_offset + ptr_off,
27321 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
27322 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
27323 NULL_RTX, NULL_RTX);
27324 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
27326 /* The oddity mentioned above clobbered our frame reg. */
27327 emit_move_insn (frame_reg_rtx, ptr_reg);
27328 frame_off = ptr_off;
27331 else if (!WORLD_SAVE_P (info)
27332 && info->altivec_size != 0)
27336 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
27337 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
27339 rtx areg, savereg, mem;
27340 HOST_WIDE_INT offset;
27342 offset = (info->altivec_save_offset + frame_off
27343 + 16 * (i - info->first_altivec_reg_save));
27345 savereg = gen_rtx_REG (V4SImode, i);
27347 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
27349 mem = gen_frame_mem (V4SImode,
27350 gen_rtx_PLUS (Pmode, frame_reg_rtx,
27351 GEN_INT (offset)));
27352 insn = emit_insn (gen_rtx_SET (mem, savereg));
27358 areg = gen_rtx_REG (Pmode, 0);
27359 emit_move_insn (areg, GEN_INT (offset));
27361 /* AltiVec addressing mode is [reg+reg]. */
27362 mem = gen_frame_mem (V4SImode,
27363 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
27365 /* Rather than emitting a generic move, force use of the stvx
27366 instruction, which we always want on ISA 2.07 (power8) systems.
27367 In particular we don't want xxpermdi/stxvd2x for little
27369 insn = emit_insn (gen_altivec_stvx_v4si_internal (mem, savereg));
27372 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
27373 areg, GEN_INT (offset));
27377 /* VRSAVE is a bit vector representing which AltiVec registers
27378 are used. The OS uses this to determine which vector
27379 registers to save on a context switch. We need to save
27380 VRSAVE on the stack frame, add whatever AltiVec registers we
27381 used in this function, and do the corresponding magic in the
27384 if (!WORLD_SAVE_P (info) && info->vrsave_size != 0)
27386 /* Get VRSAVE into a GPR. Note that ABI_V4 and ABI_DARWIN might
27387 be using r12 as frame_reg_rtx and r11 as the static chain
27388 pointer for nested functions. */
27389 int save_regno = 12;
27390 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
27391 && !using_static_chain_p)
27393 else if (using_split_stack || REGNO (frame_reg_rtx) == 12)
27396 if (using_static_chain_p)
27399 NOT_INUSE (save_regno);
27401 emit_vrsave_prologue (info, save_regno, frame_off, frame_reg_rtx);
27404 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
27405 if (!TARGET_SINGLE_PIC_BASE
27406 && ((TARGET_TOC && TARGET_MINIMAL_TOC
27407 && !constant_pool_empty_p ())
27408 || (DEFAULT_ABI == ABI_V4
27409 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
27410 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
27412 /* If emit_load_toc_table will use the link register, we need to save
27413 it. We use R12 for this purpose because emit_load_toc_table
27414 can use register 0. This allows us to use a plain 'blr' to return
27415 from the procedure more often. */
27416 int save_LR_around_toc_setup = (TARGET_ELF
27417 && DEFAULT_ABI == ABI_V4
27419 && ! info->lr_save_p
27420 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
27421 if (save_LR_around_toc_setup)
27423 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27424 rtx tmp = gen_rtx_REG (Pmode, 12);
27427 insn = emit_move_insn (tmp, lr);
27428 RTX_FRAME_RELATED_P (insn) = 1;
27430 rs6000_emit_load_toc_table (TRUE);
27432 insn = emit_move_insn (lr, tmp);
27433 add_reg_note (insn, REG_CFA_RESTORE, lr);
27434 RTX_FRAME_RELATED_P (insn) = 1;
27437 rs6000_emit_load_toc_table (TRUE);
27441 if (!TARGET_SINGLE_PIC_BASE
27442 && DEFAULT_ABI == ABI_DARWIN
27443 && flag_pic && crtl->uses_pic_offset_table)
27445 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27446 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
27448 /* Save and restore LR locally around this call (in R0). */
27449 if (!info->lr_save_p)
27450 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
27452 emit_insn (gen_load_macho_picbase (src));
27454 emit_move_insn (gen_rtx_REG (Pmode,
27455 RS6000_PIC_OFFSET_TABLE_REGNUM),
27458 if (!info->lr_save_p)
27459 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
27463 /* If we need to, save the TOC register after doing the stack setup.
27464 Do not emit eh frame info for this save. The unwinder wants info,
27465 conceptually attached to instructions in this function, about
27466 register values in the caller of this function. This R2 may have
27467 already been changed from the value in the caller.
27468 We don't attempt to write accurate DWARF EH frame info for R2
27469 because code emitted by gcc for a (non-pointer) function call
27470 doesn't save and restore R2. Instead, R2 is managed out-of-line
27471 by a linker generated plt call stub when the function resides in
27472 a shared library. This behavior is costly to describe in DWARF,
27473 both in terms of the size of DWARF info and the time taken in the
27474 unwinder to interpret it. R2 changes, apart from the
27475 calls_eh_return case earlier in this function, are handled by
27476 linux-unwind.h frob_update_context. */
27477 if (rs6000_save_toc_in_prologue_p ()
27478 && !cfun->machine->toc_is_wrapped_separately)
27480 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
27481 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
27484 /* Set up the arg pointer (r12) for -fsplit-stack code. */
27485 if (using_split_stack && split_stack_arg_pointer_used_p ())
27486 emit_split_stack_prologue (info, sp_adjust, frame_off, frame_reg_rtx);
27489 /* Output .extern statements for the save/restore routines we use. */
27492 rs6000_output_savres_externs (FILE *file)
27494 rs6000_stack_t *info = rs6000_stack_info ();
27496 if (TARGET_DEBUG_STACK)
27497 debug_stack_info (info);
27499 /* Write .extern for any function we will call to save and restore
27501 if (info->first_fp_reg_save < 64
27506 int regno = info->first_fp_reg_save - 32;
27508 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
27510 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
27511 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
27512 name = rs6000_savres_routine_name (regno, sel);
27513 fprintf (file, "\t.extern %s\n", name);
27515 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
27517 bool lr = (info->savres_strategy
27518 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
27519 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
27520 name = rs6000_savres_routine_name (regno, sel);
27521 fprintf (file, "\t.extern %s\n", name);
27526 /* Write function prologue. */
27529 rs6000_output_function_prologue (FILE *file)
27531 if (!cfun->is_thunk)
27532 rs6000_output_savres_externs (file);
27534 /* ELFv2 ABI r2 setup code and local entry point. This must follow
27535 immediately after the global entry point label. */
27536 if (rs6000_global_entry_point_needed_p ())
27538 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
27540 (*targetm.asm_out.internal_label) (file, "LCF", rs6000_pic_labelno);
27542 if (TARGET_CMODEL != CMODEL_LARGE)
27544 /* In the small and medium code models, we assume the TOC is less
27545 2 GB away from the text section, so it can be computed via the
27546 following two-instruction sequence. */
27549 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27550 fprintf (file, "0:\taddis 2,12,.TOC.-");
27551 assemble_name (file, buf);
27552 fprintf (file, "@ha\n");
27553 fprintf (file, "\taddi 2,2,.TOC.-");
27554 assemble_name (file, buf);
27555 fprintf (file, "@l\n");
27559 /* In the large code model, we allow arbitrary offsets between the
27560 TOC and the text section, so we have to load the offset from
27561 memory. The data field is emitted directly before the global
27562 entry point in rs6000_elf_declare_function_name. */
27565 #ifdef HAVE_AS_ENTRY_MARKERS
27566 /* If supported by the linker, emit a marker relocation. If the
27567 total code size of the final executable or shared library
27568 happens to fit into 2 GB after all, the linker will replace
27569 this code sequence with the sequence for the small or medium
27571 fprintf (file, "\t.reloc .,R_PPC64_ENTRY\n");
27573 fprintf (file, "\tld 2,");
27574 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
27575 assemble_name (file, buf);
27576 fprintf (file, "-");
27577 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
27578 assemble_name (file, buf);
27579 fprintf (file, "(12)\n");
27580 fprintf (file, "\tadd 2,2,12\n");
27583 fputs ("\t.localentry\t", file);
27584 assemble_name (file, name);
27585 fputs (",.-", file);
27586 assemble_name (file, name);
27587 fputs ("\n", file);
27590 /* Output -mprofile-kernel code. This needs to be done here instead of
27591 in output_function_profile since it must go after the ELFv2 ABI
27592 local entry point. */
27593 if (TARGET_PROFILE_KERNEL && crtl->profile)
27595 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
27596 gcc_assert (!TARGET_32BIT);
27598 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
27600 /* In the ELFv2 ABI we have no compiler stack word. It must be
27601 the resposibility of _mcount to preserve the static chain
27602 register if required. */
27603 if (DEFAULT_ABI != ABI_ELFv2
27604 && cfun->static_chain_decl != NULL)
27606 asm_fprintf (file, "\tstd %s,24(%s)\n",
27607 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27608 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27609 asm_fprintf (file, "\tld %s,24(%s)\n",
27610 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
27613 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
27616 rs6000_pic_labelno++;
27619 /* -mprofile-kernel code calls mcount before the function prolog,
27620 so a profiled leaf function should stay a leaf function. */
27622 rs6000_keep_leaf_when_profiled ()
27624 return TARGET_PROFILE_KERNEL;
27627 /* Non-zero if vmx regs are restored before the frame pop, zero if
27628 we restore after the pop when possible. */
27629 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
27631 /* Restoring cr is a two step process: loading a reg from the frame
27632 save, then moving the reg to cr. For ABI_V4 we must let the
27633 unwinder know that the stack location is no longer valid at or
27634 before the stack deallocation, but we can't emit a cfa_restore for
27635 cr at the stack deallocation like we do for other registers.
27636 The trouble is that it is possible for the move to cr to be
27637 scheduled after the stack deallocation. So say exactly where cr
27638 is located on each of the two insns. */
27641 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
27643 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
27644 rtx reg = gen_rtx_REG (SImode, regno);
27645 rtx_insn *insn = emit_move_insn (reg, mem);
27647 if (!exit_func && DEFAULT_ABI == ABI_V4)
27649 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27650 rtx set = gen_rtx_SET (reg, cr);
27652 add_reg_note (insn, REG_CFA_REGISTER, set);
27653 RTX_FRAME_RELATED_P (insn) = 1;
27658 /* Reload CR from REG. */
27661 restore_saved_cr (rtx reg, bool using_mfcr_multiple, bool exit_func)
27666 if (using_mfcr_multiple)
27668 for (i = 0; i < 8; i++)
27669 if (save_reg_p (CR0_REGNO + i))
27671 gcc_assert (count);
27674 if (using_mfcr_multiple && count > 1)
27680 p = rtvec_alloc (count);
27683 for (i = 0; i < 8; i++)
27684 if (save_reg_p (CR0_REGNO + i))
27686 rtvec r = rtvec_alloc (2);
27687 RTVEC_ELT (r, 0) = reg;
27688 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
27689 RTVEC_ELT (p, ndx) =
27690 gen_rtx_SET (gen_rtx_REG (CCmode, CR0_REGNO + i),
27691 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
27694 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
27695 gcc_assert (ndx == count);
27697 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27698 CR field separately. */
27699 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27701 for (i = 0; i < 8; i++)
27702 if (save_reg_p (CR0_REGNO + i))
27703 add_reg_note (insn, REG_CFA_RESTORE,
27704 gen_rtx_REG (SImode, CR0_REGNO + i));
27706 RTX_FRAME_RELATED_P (insn) = 1;
27710 for (i = 0; i < 8; i++)
27711 if (save_reg_p (CR0_REGNO + i))
27713 rtx insn = emit_insn (gen_movsi_to_cr_one
27714 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
27716 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
27717 CR field separately, attached to the insn that in fact
27718 restores this particular CR field. */
27719 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
27721 add_reg_note (insn, REG_CFA_RESTORE,
27722 gen_rtx_REG (SImode, CR0_REGNO + i));
27724 RTX_FRAME_RELATED_P (insn) = 1;
27728 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
27729 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
27730 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
27732 rtx_insn *insn = get_last_insn ();
27733 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
27735 add_reg_note (insn, REG_CFA_RESTORE, cr);
27736 RTX_FRAME_RELATED_P (insn) = 1;
27740 /* Like cr, the move to lr instruction can be scheduled after the
27741 stack deallocation, but unlike cr, its stack frame save is still
27742 valid. So we only need to emit the cfa_restore on the correct
27746 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
27748 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
27749 rtx reg = gen_rtx_REG (Pmode, regno);
27751 emit_move_insn (reg, mem);
27755 restore_saved_lr (int regno, bool exit_func)
27757 rtx reg = gen_rtx_REG (Pmode, regno);
27758 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
27759 rtx_insn *insn = emit_move_insn (lr, reg);
27761 if (!exit_func && flag_shrink_wrap)
27763 add_reg_note (insn, REG_CFA_RESTORE, lr);
27764 RTX_FRAME_RELATED_P (insn) = 1;
27769 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
27771 if (DEFAULT_ABI == ABI_ELFv2)
27774 for (i = 0; i < 8; i++)
27775 if (save_reg_p (CR0_REGNO + i))
27777 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
27778 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
27782 else if (info->cr_save_p)
27783 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27784 gen_rtx_REG (SImode, CR2_REGNO),
27787 if (info->lr_save_p)
27788 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27789 gen_rtx_REG (Pmode, LR_REGNO),
27791 return cfa_restores;
27794 /* Return true if OFFSET from stack pointer can be clobbered by signals.
27795 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
27796 below stack pointer not cloberred by signals. */
27799 offset_below_red_zone_p (HOST_WIDE_INT offset)
27801 return offset < (DEFAULT_ABI == ABI_V4
27803 : TARGET_32BIT ? -220 : -288);
27806 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
27809 emit_cfa_restores (rtx cfa_restores)
27811 rtx_insn *insn = get_last_insn ();
27812 rtx *loc = ®_NOTES (insn);
27815 loc = &XEXP (*loc, 1);
27816 *loc = cfa_restores;
27817 RTX_FRAME_RELATED_P (insn) = 1;
27820 /* Emit function epilogue as insns. */
27823 rs6000_emit_epilogue (enum epilogue_type epilogue_type)
27825 HOST_WIDE_INT frame_off = 0;
27826 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
27827 rtx frame_reg_rtx = sp_reg_rtx;
27828 rtx cfa_restores = NULL_RTX;
27830 rtx cr_save_reg = NULL_RTX;
27831 machine_mode reg_mode = Pmode;
27832 int reg_size = TARGET_32BIT ? 4 : 8;
27833 machine_mode fp_reg_mode = TARGET_HARD_FLOAT ? DFmode : SFmode;
27834 int fp_reg_size = 8;
27836 unsigned ptr_regno;
27838 rs6000_stack_t *info = rs6000_stack_info ();
27840 if (epilogue_type == EPILOGUE_TYPE_NORMAL && crtl->calls_eh_return)
27841 epilogue_type = EPILOGUE_TYPE_EH_RETURN;
27843 int strategy = info->savres_strategy;
27844 bool using_load_multiple = !!(strategy & REST_MULTIPLE);
27845 bool restoring_GPRs_inline = !!(strategy & REST_INLINE_GPRS);
27846 bool restoring_FPRs_inline = !!(strategy & REST_INLINE_FPRS);
27847 if (epilogue_type == EPILOGUE_TYPE_SIBCALL)
27849 restoring_GPRs_inline = true;
27850 restoring_FPRs_inline = true;
27853 bool using_mtcr_multiple = (rs6000_tune == PROCESSOR_PPC601
27854 || rs6000_tune == PROCESSOR_PPC603
27855 || rs6000_tune == PROCESSOR_PPC750
27858 /* Restore via the backchain when we have a large frame, since this
27859 is more efficient than an addis, addi pair. The second condition
27860 here will not trigger at the moment; We don't actually need a
27861 frame pointer for alloca, but the generic parts of the compiler
27862 give us one anyway. */
27863 bool use_backchain_to_restore_sp
27864 = (info->total_size + (info->lr_save_p ? info->lr_save_offset : 0) > 32767
27865 || (cfun->calls_alloca && !frame_pointer_needed));
27867 bool restore_lr = (info->lr_save_p
27868 && (restoring_FPRs_inline
27869 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
27870 && (restoring_GPRs_inline
27871 || info->first_fp_reg_save < 64)
27872 && !cfun->machine->lr_is_wrapped_separately);
27875 if (WORLD_SAVE_P (info))
27877 gcc_assert (epilogue_type != EPILOGUE_TYPE_SIBCALL);
27879 /* eh_rest_world_r10 will return to the location saved in the LR
27880 stack slot (which is not likely to be our caller.)
27881 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
27882 rest_world is similar, except any R10 parameter is ignored.
27883 The exception-handling stuff that was here in 2.95 is no
27884 longer necessary. */
27888 + 32 - info->first_gp_reg_save
27889 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
27890 + 63 + 1 - info->first_fp_reg_save);
27893 switch (epilogue_type)
27895 case EPILOGUE_TYPE_NORMAL:
27896 rname = ggc_strdup ("*rest_world");
27899 case EPILOGUE_TYPE_EH_RETURN:
27900 rname = ggc_strdup ("*eh_rest_world_r10");
27904 gcc_unreachable ();
27908 RTVEC_ELT (p, j++) = ret_rtx;
27910 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, rname));
27911 /* The instruction pattern requires a clobber here;
27912 it is shared with the restVEC helper. */
27913 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (Pmode, 11);
27916 /* CR register traditionally saved as CR2. */
27917 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
27919 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
27920 if (flag_shrink_wrap)
27922 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
27923 gen_rtx_REG (Pmode, LR_REGNO),
27925 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27930 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
27932 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
27934 = gen_frame_load (reg,
27935 frame_reg_rtx, info->gp_save_offset + reg_size * i);
27936 if (flag_shrink_wrap
27937 && save_reg_p (info->first_gp_reg_save + i))
27938 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27940 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
27942 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
27944 = gen_frame_load (reg,
27945 frame_reg_rtx, info->altivec_save_offset + 16 * i);
27946 if (flag_shrink_wrap
27947 && save_reg_p (info->first_altivec_reg_save + i))
27948 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27950 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
27952 rtx reg = gen_rtx_REG (TARGET_HARD_FLOAT ? DFmode : SFmode,
27953 info->first_fp_reg_save + i);
27955 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
27956 if (flag_shrink_wrap
27957 && save_reg_p (info->first_fp_reg_save + i))
27958 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
27960 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (Pmode, 0);
27961 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 12);
27962 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 7);
27963 RTVEC_ELT (p, j++) = gen_hard_reg_clobber (SImode, 8);
27965 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
27966 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
27968 if (flag_shrink_wrap)
27970 REG_NOTES (insn) = cfa_restores;
27971 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
27972 RTX_FRAME_RELATED_P (insn) = 1;
27977 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
27979 frame_off = info->total_size;
27981 /* Restore AltiVec registers if we must do so before adjusting the
27983 if (info->altivec_size != 0
27984 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
27985 || (DEFAULT_ABI != ABI_V4
27986 && offset_below_red_zone_p (info->altivec_save_offset))))
27989 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
27991 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
27992 if (use_backchain_to_restore_sp)
27994 int frame_regno = 11;
27996 if ((strategy & REST_INLINE_VRS) == 0)
27998 /* Of r11 and r12, select the one not clobbered by an
27999 out-of-line restore function for the frame register. */
28000 frame_regno = 11 + 12 - scratch_regno;
28002 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
28003 emit_move_insn (frame_reg_rtx,
28004 gen_rtx_MEM (Pmode, sp_reg_rtx));
28007 else if (frame_pointer_needed)
28008 frame_reg_rtx = hard_frame_pointer_rtx;
28010 if ((strategy & REST_INLINE_VRS) == 0)
28012 int end_save = info->altivec_save_offset + info->altivec_size;
28014 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28015 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28017 if (end_save + frame_off != 0)
28019 rtx offset = GEN_INT (end_save + frame_off);
28021 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28024 emit_move_insn (ptr_reg, frame_reg_rtx);
28026 ptr_off = -end_save;
28027 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28028 info->altivec_save_offset + ptr_off,
28029 0, V4SImode, SAVRES_VR);
28033 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28034 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28036 rtx addr, areg, mem, insn;
28037 rtx reg = gen_rtx_REG (V4SImode, i);
28038 HOST_WIDE_INT offset
28039 = (info->altivec_save_offset + frame_off
28040 + 16 * (i - info->first_altivec_reg_save));
28042 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28044 mem = gen_frame_mem (V4SImode,
28045 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28046 GEN_INT (offset)));
28047 insn = gen_rtx_SET (reg, mem);
28051 areg = gen_rtx_REG (Pmode, 0);
28052 emit_move_insn (areg, GEN_INT (offset));
28054 /* AltiVec addressing mode is [reg+reg]. */
28055 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28056 mem = gen_frame_mem (V4SImode, addr);
28058 /* Rather than emitting a generic move, force use of the
28059 lvx instruction, which we always want. In particular we
28060 don't want lxvd2x/xxpermdi for little endian. */
28061 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28064 (void) emit_insn (insn);
28068 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28069 if (((strategy & REST_INLINE_VRS) == 0
28070 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28071 && (flag_shrink_wrap
28072 || (offset_below_red_zone_p
28073 (info->altivec_save_offset
28074 + 16 * (i - info->first_altivec_reg_save))))
28077 rtx reg = gen_rtx_REG (V4SImode, i);
28078 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28082 /* Restore VRSAVE if we must do so before adjusting the stack. */
28083 if (info->vrsave_size != 0
28084 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28085 || (DEFAULT_ABI != ABI_V4
28086 && offset_below_red_zone_p (info->vrsave_save_offset))))
28090 if (frame_reg_rtx == sp_reg_rtx)
28092 if (use_backchain_to_restore_sp)
28094 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28095 emit_move_insn (frame_reg_rtx,
28096 gen_rtx_MEM (Pmode, sp_reg_rtx));
28099 else if (frame_pointer_needed)
28100 frame_reg_rtx = hard_frame_pointer_rtx;
28103 reg = gen_rtx_REG (SImode, 12);
28104 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28105 info->vrsave_save_offset + frame_off));
28107 emit_insn (generate_set_vrsave (reg, info, 1));
28111 /* If we have a large stack frame, restore the old stack pointer
28112 using the backchain. */
28113 if (use_backchain_to_restore_sp)
28115 if (frame_reg_rtx == sp_reg_rtx)
28117 /* Under V.4, don't reset the stack pointer until after we're done
28118 loading the saved registers. */
28119 if (DEFAULT_ABI == ABI_V4)
28120 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28122 insn = emit_move_insn (frame_reg_rtx,
28123 gen_rtx_MEM (Pmode, sp_reg_rtx));
28126 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28127 && DEFAULT_ABI == ABI_V4)
28128 /* frame_reg_rtx has been set up by the altivec restore. */
28132 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
28133 frame_reg_rtx = sp_reg_rtx;
28136 /* If we have a frame pointer, we can restore the old stack pointer
28138 else if (frame_pointer_needed)
28140 frame_reg_rtx = sp_reg_rtx;
28141 if (DEFAULT_ABI == ABI_V4)
28142 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
28143 /* Prevent reordering memory accesses against stack pointer restore. */
28144 else if (cfun->calls_alloca
28145 || offset_below_red_zone_p (-info->total_size))
28146 rs6000_emit_stack_tie (frame_reg_rtx, true);
28148 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
28149 GEN_INT (info->total_size)));
28152 else if (info->push_p
28153 && DEFAULT_ABI != ABI_V4
28154 && epilogue_type != EPILOGUE_TYPE_EH_RETURN)
28156 /* Prevent reordering memory accesses against stack pointer restore. */
28157 if (cfun->calls_alloca
28158 || offset_below_red_zone_p (-info->total_size))
28159 rs6000_emit_stack_tie (frame_reg_rtx, false);
28160 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
28161 GEN_INT (info->total_size)));
28164 if (insn && frame_reg_rtx == sp_reg_rtx)
28168 REG_NOTES (insn) = cfa_restores;
28169 cfa_restores = NULL_RTX;
28171 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28172 RTX_FRAME_RELATED_P (insn) = 1;
28175 /* Restore AltiVec registers if we have not done so already. */
28176 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28177 && info->altivec_size != 0
28178 && (DEFAULT_ABI == ABI_V4
28179 || !offset_below_red_zone_p (info->altivec_save_offset)))
28183 if ((strategy & REST_INLINE_VRS) == 0)
28185 int end_save = info->altivec_save_offset + info->altivec_size;
28187 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
28188 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
28189 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
28191 if (end_save + frame_off != 0)
28193 rtx offset = GEN_INT (end_save + frame_off);
28195 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
28198 emit_move_insn (ptr_reg, frame_reg_rtx);
28200 ptr_off = -end_save;
28201 insn = rs6000_emit_savres_rtx (info, scratch_reg,
28202 info->altivec_save_offset + ptr_off,
28203 0, V4SImode, SAVRES_VR);
28204 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
28206 /* Frame reg was clobbered by out-of-line save. Restore it
28207 from ptr_reg, and if we are calling out-of-line gpr or
28208 fpr restore set up the correct pointer and offset. */
28209 unsigned newptr_regno = 1;
28210 if (!restoring_GPRs_inline)
28212 bool lr = info->gp_save_offset + info->gp_size == 0;
28213 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28214 newptr_regno = ptr_regno_for_savres (sel);
28215 end_save = info->gp_save_offset + info->gp_size;
28217 else if (!restoring_FPRs_inline)
28219 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
28220 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28221 newptr_regno = ptr_regno_for_savres (sel);
28222 end_save = info->fp_save_offset + info->fp_size;
28225 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
28226 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
28228 if (end_save + ptr_off != 0)
28230 rtx offset = GEN_INT (end_save + ptr_off);
28232 frame_off = -end_save;
28234 emit_insn (gen_addsi3_carry (frame_reg_rtx,
28237 emit_insn (gen_adddi3_carry (frame_reg_rtx,
28242 frame_off = ptr_off;
28243 emit_move_insn (frame_reg_rtx, ptr_reg);
28249 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28250 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
28252 rtx addr, areg, mem, insn;
28253 rtx reg = gen_rtx_REG (V4SImode, i);
28254 HOST_WIDE_INT offset
28255 = (info->altivec_save_offset + frame_off
28256 + 16 * (i - info->first_altivec_reg_save));
28258 if (TARGET_P9_VECTOR && quad_address_offset_p (offset))
28260 mem = gen_frame_mem (V4SImode,
28261 gen_rtx_PLUS (Pmode, frame_reg_rtx,
28262 GEN_INT (offset)));
28263 insn = gen_rtx_SET (reg, mem);
28267 areg = gen_rtx_REG (Pmode, 0);
28268 emit_move_insn (areg, GEN_INT (offset));
28270 /* AltiVec addressing mode is [reg+reg]. */
28271 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
28272 mem = gen_frame_mem (V4SImode, addr);
28274 /* Rather than emitting a generic move, force use of the
28275 lvx instruction, which we always want. In particular we
28276 don't want lxvd2x/xxpermdi for little endian. */
28277 insn = gen_altivec_lvx_v4si_internal (reg, mem);
28280 (void) emit_insn (insn);
28284 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
28285 if (((strategy & REST_INLINE_VRS) == 0
28286 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
28287 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28290 rtx reg = gen_rtx_REG (V4SImode, i);
28291 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28295 /* Restore VRSAVE if we have not done so already. */
28296 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
28297 && info->vrsave_size != 0
28298 && (DEFAULT_ABI == ABI_V4
28299 || !offset_below_red_zone_p (info->vrsave_save_offset)))
28303 reg = gen_rtx_REG (SImode, 12);
28304 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28305 info->vrsave_save_offset + frame_off));
28307 emit_insn (generate_set_vrsave (reg, info, 1));
28310 /* If we exit by an out-of-line restore function on ABI_V4 then that
28311 function will deallocate the stack, so we don't need to worry
28312 about the unwinder restoring cr from an invalid stack frame
28314 bool exit_func = (!restoring_FPRs_inline
28315 || (!restoring_GPRs_inline
28316 && info->first_fp_reg_save == 64));
28318 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
28319 *separate* slots if the routine calls __builtin_eh_return, so
28320 that they can be independently restored by the unwinder. */
28321 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
28323 int i, cr_off = info->ehcr_offset;
28325 for (i = 0; i < 8; i++)
28326 if (!call_used_regs[CR0_REGNO + i])
28328 rtx reg = gen_rtx_REG (SImode, 0);
28329 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28330 cr_off + frame_off));
28332 insn = emit_insn (gen_movsi_to_cr_one
28333 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
28335 if (!exit_func && flag_shrink_wrap)
28337 add_reg_note (insn, REG_CFA_RESTORE,
28338 gen_rtx_REG (SImode, CR0_REGNO + i));
28340 RTX_FRAME_RELATED_P (insn) = 1;
28343 cr_off += reg_size;
28347 /* Get the old lr if we saved it. If we are restoring registers
28348 out-of-line, then the out-of-line routines can do this for us. */
28349 if (restore_lr && restoring_GPRs_inline)
28350 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28352 /* Get the old cr if we saved it. */
28353 if (info->cr_save_p)
28355 unsigned cr_save_regno = 12;
28357 if (!restoring_GPRs_inline)
28359 /* Ensure we don't use the register used by the out-of-line
28360 gpr register restore below. */
28361 bool lr = info->gp_save_offset + info->gp_size == 0;
28362 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
28363 int gpr_ptr_regno = ptr_regno_for_savres (sel);
28365 if (gpr_ptr_regno == 12)
28366 cr_save_regno = 11;
28367 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
28369 else if (REGNO (frame_reg_rtx) == 12)
28370 cr_save_regno = 11;
28372 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
28373 info->cr_save_offset + frame_off,
28377 /* Set LR here to try to overlap restores below. */
28378 if (restore_lr && restoring_GPRs_inline)
28379 restore_saved_lr (0, exit_func);
28381 /* Load exception handler data registers, if needed. */
28382 if (epilogue_type == EPILOGUE_TYPE_EH_RETURN)
28384 unsigned int i, regno;
28388 rtx reg = gen_rtx_REG (reg_mode, 2);
28389 emit_insn (gen_frame_load (reg, frame_reg_rtx,
28390 frame_off + RS6000_TOC_SAVE_SLOT));
28397 regno = EH_RETURN_DATA_REGNO (i);
28398 if (regno == INVALID_REGNUM)
28401 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
28402 info->ehrd_offset + frame_off
28403 + reg_size * (int) i);
28405 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
28409 /* Restore GPRs. This is done as a PARALLEL if we are using
28410 the load-multiple instructions. */
28411 if (!restoring_GPRs_inline)
28413 /* We are jumping to an out-of-line function. */
28415 int end_save = info->gp_save_offset + info->gp_size;
28416 bool can_use_exit = end_save == 0;
28417 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
28420 /* Emit stack reset code if we need it. */
28421 ptr_regno = ptr_regno_for_savres (sel);
28422 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
28424 rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28425 else if (end_save + frame_off != 0)
28426 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
28427 GEN_INT (end_save + frame_off)));
28428 else if (REGNO (frame_reg_rtx) != ptr_regno)
28429 emit_move_insn (ptr_reg, frame_reg_rtx);
28430 if (REGNO (frame_reg_rtx) == ptr_regno)
28431 frame_off = -end_save;
28433 if (can_use_exit && info->cr_save_p)
28434 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
28436 ptr_off = -end_save;
28437 rs6000_emit_savres_rtx (info, ptr_reg,
28438 info->gp_save_offset + ptr_off,
28439 info->lr_save_offset + ptr_off,
28442 else if (using_load_multiple)
28445 p = rtvec_alloc (32 - info->first_gp_reg_save);
28446 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
28448 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
28450 info->gp_save_offset + frame_off + reg_size * i);
28451 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
28455 int offset = info->gp_save_offset + frame_off;
28456 for (i = info->first_gp_reg_save; i < 32; i++)
28459 && !cfun->machine->gpr_is_wrapped_separately[i])
28461 rtx reg = gen_rtx_REG (reg_mode, i);
28462 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28465 offset += reg_size;
28469 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28471 /* If the frame pointer was used then we can't delay emitting
28472 a REG_CFA_DEF_CFA note. This must happen on the insn that
28473 restores the frame pointer, r31. We may have already emitted
28474 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
28475 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
28476 be harmless if emitted. */
28477 if (frame_pointer_needed)
28479 insn = get_last_insn ();
28480 add_reg_note (insn, REG_CFA_DEF_CFA,
28481 plus_constant (Pmode, frame_reg_rtx, frame_off));
28482 RTX_FRAME_RELATED_P (insn) = 1;
28485 /* Set up cfa_restores. We always need these when
28486 shrink-wrapping. If not shrink-wrapping then we only need
28487 the cfa_restore when the stack location is no longer valid.
28488 The cfa_restores must be emitted on or before the insn that
28489 invalidates the stack, and of course must not be emitted
28490 before the insn that actually does the restore. The latter
28491 is why it is a bad idea to emit the cfa_restores as a group
28492 on the last instruction here that actually does a restore:
28493 That insn may be reordered with respect to others doing
28495 if (flag_shrink_wrap
28496 && !restoring_GPRs_inline
28497 && info->first_fp_reg_save == 64)
28498 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28500 for (i = info->first_gp_reg_save; i < 32; i++)
28502 && !cfun->machine->gpr_is_wrapped_separately[i])
28504 rtx reg = gen_rtx_REG (reg_mode, i);
28505 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28509 if (!restoring_GPRs_inline
28510 && info->first_fp_reg_save == 64)
28512 /* We are jumping to an out-of-line function. */
28514 emit_cfa_restores (cfa_restores);
28518 if (restore_lr && !restoring_GPRs_inline)
28520 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
28521 restore_saved_lr (0, exit_func);
28524 /* Restore fpr's if we need to do it without calling a function. */
28525 if (restoring_FPRs_inline)
28527 int offset = info->fp_save_offset + frame_off;
28528 for (i = info->first_fp_reg_save; i < 64; i++)
28531 && !cfun->machine->fpr_is_wrapped_separately[i - 32])
28533 rtx reg = gen_rtx_REG (fp_reg_mode, i);
28534 emit_insn (gen_frame_load (reg, frame_reg_rtx, offset));
28535 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
28536 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
28540 offset += fp_reg_size;
28544 /* If we saved cr, restore it here. Just those that were used. */
28545 if (info->cr_save_p)
28546 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
28548 /* If this is V.4, unwind the stack pointer after all of the loads
28549 have been done, or set up r11 if we are restoring fp out of line. */
28551 if (!restoring_FPRs_inline)
28553 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28554 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
28555 ptr_regno = ptr_regno_for_savres (sel);
28558 insn = rs6000_emit_stack_reset (frame_reg_rtx, frame_off, ptr_regno);
28559 if (REGNO (frame_reg_rtx) == ptr_regno)
28562 if (insn && restoring_FPRs_inline)
28566 REG_NOTES (insn) = cfa_restores;
28567 cfa_restores = NULL_RTX;
28569 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
28570 RTX_FRAME_RELATED_P (insn) = 1;
28573 if (epilogue_type == EPILOGUE_TYPE_EH_RETURN)
28575 rtx sa = EH_RETURN_STACKADJ_RTX;
28576 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
28579 if (epilogue_type != EPILOGUE_TYPE_SIBCALL && restoring_FPRs_inline)
28583 /* We can't hang the cfa_restores off a simple return,
28584 since the shrink-wrap code sometimes uses an existing
28585 return. This means there might be a path from
28586 pre-prologue code to this return, and dwarf2cfi code
28587 wants the eh_frame unwinder state to be the same on
28588 all paths to any point. So we need to emit the
28589 cfa_restores before the return. For -m64 we really
28590 don't need epilogue cfa_restores at all, except for
28591 this irritating dwarf2cfi with shrink-wrap
28592 requirement; The stack red-zone means eh_frame info
28593 from the prologue telling the unwinder to restore
28594 from the stack is perfectly good right to the end of
28596 emit_insn (gen_blockage ());
28597 emit_cfa_restores (cfa_restores);
28598 cfa_restores = NULL_RTX;
28601 emit_jump_insn (targetm.gen_simple_return ());
28604 if (epilogue_type != EPILOGUE_TYPE_SIBCALL && !restoring_FPRs_inline)
28606 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
28607 rtvec p = rtvec_alloc (3 + !!lr + 64 - info->first_fp_reg_save);
28609 RTVEC_ELT (p, elt++) = ret_rtx;
28611 RTVEC_ELT (p, elt++) = gen_hard_reg_clobber (Pmode, LR_REGNO);
28613 /* We have to restore more than two FP registers, so branch to the
28614 restore function. It will return to our caller. */
28619 if (flag_shrink_wrap)
28620 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
28622 sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0));
28623 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, sym);
28624 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
28625 RTVEC_ELT (p, elt++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
28627 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
28629 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
28631 RTVEC_ELT (p, elt++)
28632 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
28633 if (flag_shrink_wrap
28634 && save_reg_p (info->first_fp_reg_save + i))
28635 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
28638 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
28643 if (epilogue_type == EPILOGUE_TYPE_SIBCALL)
28644 /* Ensure the cfa_restores are hung off an insn that won't
28645 be reordered above other restores. */
28646 emit_insn (gen_blockage ());
28648 emit_cfa_restores (cfa_restores);
28652 /* Write function epilogue. */
28655 rs6000_output_function_epilogue (FILE *file)
28658 macho_branch_islands ();
28661 rtx_insn *insn = get_last_insn ();
28662 rtx_insn *deleted_debug_label = NULL;
28664 /* Mach-O doesn't support labels at the end of objects, so if
28665 it looks like we might want one, take special action.
28667 First, collect any sequence of deleted debug labels. */
28670 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
28672 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
28673 notes only, instead set their CODE_LABEL_NUMBER to -1,
28674 otherwise there would be code generation differences
28675 in between -g and -g0. */
28676 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28677 deleted_debug_label = insn;
28678 insn = PREV_INSN (insn);
28681 /* Second, if we have:
28684 then this needs to be detected, so skip past the barrier. */
28686 if (insn && BARRIER_P (insn))
28687 insn = PREV_INSN (insn);
28689 /* Up to now we've only seen notes or barriers. */
28694 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL))
28695 /* Trailing label: <barrier>. */
28696 fputs ("\tnop\n", file);
28699 /* Lastly, see if we have a completely empty function body. */
28700 while (insn && ! INSN_P (insn))
28701 insn = PREV_INSN (insn);
28702 /* If we don't find any insns, we've got an empty function body;
28703 I.e. completely empty - without a return or branch. This is
28704 taken as the case where a function body has been removed
28705 because it contains an inline __builtin_unreachable(). GCC
28706 states that reaching __builtin_unreachable() means UB so we're
28707 not obliged to do anything special; however, we want
28708 non-zero-sized function bodies. To meet this, and help the
28709 user out, let's trap the case. */
28711 fputs ("\ttrap\n", file);
28714 else if (deleted_debug_label)
28715 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
28716 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
28717 CODE_LABEL_NUMBER (insn) = -1;
28721 /* Output a traceback table here. See /usr/include/sys/debug.h for info
28724 We don't output a traceback table if -finhibit-size-directive was
28725 used. The documentation for -finhibit-size-directive reads
28726 ``don't output a @code{.size} assembler directive, or anything
28727 else that would cause trouble if the function is split in the
28728 middle, and the two halves are placed at locations far apart in
28729 memory.'' The traceback table has this property, since it
28730 includes the offset from the start of the function to the
28731 traceback table itself.
28733 System V.4 Powerpc's (and the embedded ABI derived from it) use a
28734 different traceback table. */
28735 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
28736 && ! flag_inhibit_size_directive
28737 && rs6000_traceback != traceback_none && !cfun->is_thunk)
28739 const char *fname = NULL;
28740 const char *language_string = lang_hooks.name;
28741 int fixed_parms = 0, float_parms = 0, parm_info = 0;
28743 int optional_tbtab;
28744 rs6000_stack_t *info = rs6000_stack_info ();
28746 if (rs6000_traceback == traceback_full)
28747 optional_tbtab = 1;
28748 else if (rs6000_traceback == traceback_part)
28749 optional_tbtab = 0;
28751 optional_tbtab = !optimize_size && !TARGET_ELF;
28753 if (optional_tbtab)
28755 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
28756 while (*fname == '.') /* V.4 encodes . in the name */
28759 /* Need label immediately before tbtab, so we can compute
28760 its offset from the function start. */
28761 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28762 ASM_OUTPUT_LABEL (file, fname);
28765 /* The .tbtab pseudo-op can only be used for the first eight
28766 expressions, since it can't handle the possibly variable
28767 length fields that follow. However, if you omit the optional
28768 fields, the assembler outputs zeros for all optional fields
28769 anyways, giving each variable length field is minimum length
28770 (as defined in sys/debug.h). Thus we cannot use the .tbtab
28771 pseudo-op at all. */
28773 /* An all-zero word flags the start of the tbtab, for debuggers
28774 that have to find it by searching forward from the entry
28775 point or from the current pc. */
28776 fputs ("\t.long 0\n", file);
28778 /* Tbtab format type. Use format type 0. */
28779 fputs ("\t.byte 0,", file);
28781 /* Language type. Unfortunately, there does not seem to be any
28782 official way to discover the language being compiled, so we
28783 use language_string.
28784 C is 0. Fortran is 1. Ada is 3. C++ is 9.
28785 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
28786 a number, so for now use 9. LTO, Go, D, and JIT aren't assigned
28787 numbers either, so for now use 0. */
28789 || ! strcmp (language_string, "GNU GIMPLE")
28790 || ! strcmp (language_string, "GNU Go")
28791 || ! strcmp (language_string, "GNU D")
28792 || ! strcmp (language_string, "libgccjit"))
28794 else if (! strcmp (language_string, "GNU F77")
28795 || lang_GNU_Fortran ())
28797 else if (! strcmp (language_string, "GNU Ada"))
28799 else if (lang_GNU_CXX ()
28800 || ! strcmp (language_string, "GNU Objective-C++"))
28802 else if (! strcmp (language_string, "GNU Java"))
28804 else if (! strcmp (language_string, "GNU Objective-C"))
28807 gcc_unreachable ();
28808 fprintf (file, "%d,", i);
28810 /* 8 single bit fields: global linkage (not set for C extern linkage,
28811 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
28812 from start of procedure stored in tbtab, internal function, function
28813 has controlled storage, function has no toc, function uses fp,
28814 function logs/aborts fp operations. */
28815 /* Assume that fp operations are used if any fp reg must be saved. */
28816 fprintf (file, "%d,",
28817 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
28819 /* 6 bitfields: function is interrupt handler, name present in
28820 proc table, function calls alloca, on condition directives
28821 (controls stack walks, 3 bits), saves condition reg, saves
28823 /* The `function calls alloca' bit seems to be set whenever reg 31 is
28824 set up as a frame pointer, even when there is no alloca call. */
28825 fprintf (file, "%d,",
28826 ((optional_tbtab << 6)
28827 | ((optional_tbtab & frame_pointer_needed) << 5)
28828 | (info->cr_save_p << 1)
28829 | (info->lr_save_p)));
28831 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
28833 fprintf (file, "%d,",
28834 (info->push_p << 7) | (64 - info->first_fp_reg_save));
28836 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
28837 fprintf (file, "%d,", (32 - first_reg_to_save ()));
28839 if (optional_tbtab)
28841 /* Compute the parameter info from the function decl argument
28844 int next_parm_info_bit = 31;
28846 for (decl = DECL_ARGUMENTS (current_function_decl);
28847 decl; decl = DECL_CHAIN (decl))
28849 rtx parameter = DECL_INCOMING_RTL (decl);
28850 machine_mode mode = GET_MODE (parameter);
28852 if (REG_P (parameter))
28854 if (SCALAR_FLOAT_MODE_P (mode))
28877 gcc_unreachable ();
28880 /* If only one bit will fit, don't or in this entry. */
28881 if (next_parm_info_bit > 0)
28882 parm_info |= (bits << (next_parm_info_bit - 1));
28883 next_parm_info_bit -= 2;
28887 fixed_parms += ((GET_MODE_SIZE (mode)
28888 + (UNITS_PER_WORD - 1))
28890 next_parm_info_bit -= 1;
28896 /* Number of fixed point parameters. */
28897 /* This is actually the number of words of fixed point parameters; thus
28898 an 8 byte struct counts as 2; and thus the maximum value is 8. */
28899 fprintf (file, "%d,", fixed_parms);
28901 /* 2 bitfields: number of floating point parameters (7 bits), parameters
28903 /* This is actually the number of fp registers that hold parameters;
28904 and thus the maximum value is 13. */
28905 /* Set parameters on stack bit if parameters are not in their original
28906 registers, regardless of whether they are on the stack? Xlc
28907 seems to set the bit when not optimizing. */
28908 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
28910 if (optional_tbtab)
28912 /* Optional fields follow. Some are variable length. */
28914 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single
28915 float, 11 double float. */
28916 /* There is an entry for each parameter in a register, in the order
28917 that they occur in the parameter list. Any intervening arguments
28918 on the stack are ignored. If the list overflows a long (max
28919 possible length 34 bits) then completely leave off all elements
28921 /* Only emit this long if there was at least one parameter. */
28922 if (fixed_parms || float_parms)
28923 fprintf (file, "\t.long %d\n", parm_info);
28925 /* Offset from start of code to tb table. */
28926 fputs ("\t.long ", file);
28927 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
28928 RS6000_OUTPUT_BASENAME (file, fname);
28930 rs6000_output_function_entry (file, fname);
28933 /* Interrupt handler mask. */
28934 /* Omit this long, since we never set the interrupt handler bit
28937 /* Number of CTL (controlled storage) anchors. */
28938 /* Omit this long, since the has_ctl bit is never set above. */
28940 /* Displacement into stack of each CTL anchor. */
28941 /* Omit this list of longs, because there are no CTL anchors. */
28943 /* Length of function name. */
28946 fprintf (file, "\t.short %d\n", (int) strlen (fname));
28948 /* Function name. */
28949 assemble_string (fname, strlen (fname));
28951 /* Register for alloca automatic storage; this is always reg 31.
28952 Only emit this if the alloca bit was set above. */
28953 if (frame_pointer_needed)
28954 fputs ("\t.byte 31\n", file);
28956 fputs ("\t.align 2\n", file);
28960 /* Arrange to define .LCTOC1 label, if not already done. */
28964 if (!toc_initialized)
28966 switch_to_section (toc_section);
28967 switch_to_section (current_function_section ());
28972 /* -fsplit-stack support. */
28974 /* A SYMBOL_REF for __morestack. */
28975 static GTY(()) rtx morestack_ref;
28978 gen_add3_const (rtx rt, rtx ra, long c)
28981 return gen_adddi3 (rt, ra, GEN_INT (c));
28983 return gen_addsi3 (rt, ra, GEN_INT (c));
28986 /* Emit -fsplit-stack prologue, which goes before the regular function
28987 prologue (at local entry point in the case of ELFv2). */
28990 rs6000_expand_split_stack_prologue (void)
28992 rs6000_stack_t *info = rs6000_stack_info ();
28993 unsigned HOST_WIDE_INT allocate;
28994 long alloc_hi, alloc_lo;
28995 rtx r0, r1, r12, lr, ok_label, compare, jump, call_fusage;
28998 gcc_assert (flag_split_stack && reload_completed);
29003 if (global_regs[29])
29005 error ("%qs uses register r29", "%<-fsplit-stack%>");
29006 inform (DECL_SOURCE_LOCATION (global_regs_decl[29]),
29007 "conflicts with %qD", global_regs_decl[29]);
29010 allocate = info->total_size;
29011 if (allocate > (unsigned HOST_WIDE_INT) 1 << 31)
29013 sorry ("Stack frame larger than 2G is not supported for "
29014 "%<-fsplit-stack%>");
29017 if (morestack_ref == NULL_RTX)
29019 morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack");
29020 SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL
29021 | SYMBOL_FLAG_FUNCTION);
29024 r0 = gen_rtx_REG (Pmode, 0);
29025 r1 = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29026 r12 = gen_rtx_REG (Pmode, 12);
29027 emit_insn (gen_load_split_stack_limit (r0));
29028 /* Always emit two insns here to calculate the requested stack,
29029 so that the linker can edit them when adjusting size for calling
29030 non-split-stack code. */
29031 alloc_hi = (-allocate + 0x8000) & ~0xffffL;
29032 alloc_lo = -allocate - alloc_hi;
29035 emit_insn (gen_add3_const (r12, r1, alloc_hi));
29037 emit_insn (gen_add3_const (r12, r12, alloc_lo));
29039 emit_insn (gen_nop ());
29043 emit_insn (gen_add3_const (r12, r1, alloc_lo));
29044 emit_insn (gen_nop ());
29047 compare = gen_rtx_REG (CCUNSmode, CR7_REGNO);
29048 emit_insn (gen_rtx_SET (compare, gen_rtx_COMPARE (CCUNSmode, r12, r0)));
29049 ok_label = gen_label_rtx ();
29050 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29051 gen_rtx_GEU (VOIDmode, compare, const0_rtx),
29052 gen_rtx_LABEL_REF (VOIDmode, ok_label),
29054 insn = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29055 JUMP_LABEL (insn) = ok_label;
29056 /* Mark the jump as very likely to be taken. */
29057 add_reg_br_prob_note (insn, profile_probability::very_likely ());
29059 lr = gen_rtx_REG (Pmode, LR_REGNO);
29060 insn = emit_move_insn (r0, lr);
29061 RTX_FRAME_RELATED_P (insn) = 1;
29062 insn = emit_insn (gen_frame_store (r0, r1, info->lr_save_offset));
29063 RTX_FRAME_RELATED_P (insn) = 1;
29065 insn = emit_call_insn (gen_call (gen_rtx_MEM (SImode, morestack_ref),
29066 const0_rtx, const0_rtx));
29067 call_fusage = NULL_RTX;
29068 use_reg (&call_fusage, r12);
29069 /* Say the call uses r0, even though it doesn't, to stop regrename
29070 from twiddling with the insns saving lr, trashing args for cfun.
29071 The insns restoring lr are similarly protected by making
29072 split_stack_return use r0. */
29073 use_reg (&call_fusage, r0);
29074 add_function_usage_to (insn, call_fusage);
29075 /* Indicate that this function can't jump to non-local gotos. */
29076 make_reg_eh_region_note_nothrow_nononlocal (insn);
29077 emit_insn (gen_frame_load (r0, r1, info->lr_save_offset));
29078 insn = emit_move_insn (lr, r0);
29079 add_reg_note (insn, REG_CFA_RESTORE, lr);
29080 RTX_FRAME_RELATED_P (insn) = 1;
29081 emit_insn (gen_split_stack_return ());
29083 emit_label (ok_label);
29084 LABEL_NUSES (ok_label) = 1;
29087 /* Return the internal arg pointer used for function incoming
29088 arguments. When -fsplit-stack, the arg pointer is r12 so we need
29089 to copy it to a pseudo in order for it to be preserved over calls
29090 and suchlike. We'd really like to use a pseudo here for the
29091 internal arg pointer but data-flow analysis is not prepared to
29092 accept pseudos as live at the beginning of a function. */
29095 rs6000_internal_arg_pointer (void)
29097 if (flag_split_stack
29098 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl))
29102 if (cfun->machine->split_stack_arg_pointer == NULL_RTX)
29106 cfun->machine->split_stack_arg_pointer = gen_reg_rtx (Pmode);
29107 REG_POINTER (cfun->machine->split_stack_arg_pointer) = 1;
29109 /* Put the pseudo initialization right after the note at the
29110 beginning of the function. */
29111 pat = gen_rtx_SET (cfun->machine->split_stack_arg_pointer,
29112 gen_rtx_REG (Pmode, 12));
29113 push_topmost_sequence ();
29114 emit_insn_after (pat, get_insns ());
29115 pop_topmost_sequence ();
29117 rtx ret = plus_constant (Pmode, cfun->machine->split_stack_arg_pointer,
29118 FIRST_PARM_OFFSET (current_function_decl));
29119 return copy_to_reg (ret);
29121 return virtual_incoming_args_rtx;
29124 /* We may have to tell the dataflow pass that the split stack prologue
29125 is initializing a register. */
29128 rs6000_live_on_entry (bitmap regs)
29130 if (flag_split_stack)
29131 bitmap_set_bit (regs, 12);
29134 /* Emit -fsplit-stack dynamic stack allocation space check. */
29137 rs6000_split_stack_space_check (rtx size, rtx label)
29139 rtx sp = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29140 rtx limit = gen_reg_rtx (Pmode);
29141 rtx requested = gen_reg_rtx (Pmode);
29142 rtx cmp = gen_reg_rtx (CCUNSmode);
29145 emit_insn (gen_load_split_stack_limit (limit));
29146 if (CONST_INT_P (size))
29147 emit_insn (gen_add3_insn (requested, sp, GEN_INT (-INTVAL (size))));
29150 size = force_reg (Pmode, size);
29151 emit_move_insn (requested, gen_rtx_MINUS (Pmode, sp, size));
29153 emit_insn (gen_rtx_SET (cmp, gen_rtx_COMPARE (CCUNSmode, requested, limit)));
29154 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
29155 gen_rtx_GEU (VOIDmode, cmp, const0_rtx),
29156 gen_rtx_LABEL_REF (VOIDmode, label),
29158 jump = emit_jump_insn (gen_rtx_SET (pc_rtx, jump));
29159 JUMP_LABEL (jump) = label;
29162 /* A C compound statement that outputs the assembler code for a thunk
29163 function, used to implement C++ virtual function calls with
29164 multiple inheritance. The thunk acts as a wrapper around a virtual
29165 function, adjusting the implicit object parameter before handing
29166 control off to the real function.
29168 First, emit code to add the integer DELTA to the location that
29169 contains the incoming first argument. Assume that this argument
29170 contains a pointer, and is the one used to pass the `this' pointer
29171 in C++. This is the incoming argument *before* the function
29172 prologue, e.g. `%o0' on a sparc. The addition must preserve the
29173 values of all other incoming arguments.
29175 After the addition, emit code to jump to FUNCTION, which is a
29176 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
29177 not touch the return address. Hence returning from FUNCTION will
29178 return to whoever called the current `thunk'.
29180 The effect must be as if FUNCTION had been called directly with the
29181 adjusted first argument. This macro is responsible for emitting
29182 all of the code for a thunk function; output_function_prologue()
29183 and output_function_epilogue() are not invoked.
29185 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
29186 been extracted from it.) It might possibly be useful on some
29187 targets, but probably not.
29189 If you do not define this macro, the target-independent code in the
29190 C++ frontend will generate a less efficient heavyweight thunk that
29191 calls FUNCTION instead of jumping to it. The generic approach does
29192 not support varargs. */
29195 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
29196 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
29199 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl));
29200 rtx this_rtx, funexp;
29203 reload_completed = 1;
29204 epilogue_completed = 1;
29206 /* Mark the end of the (empty) prologue. */
29207 emit_note (NOTE_INSN_PROLOGUE_END);
29209 /* Find the "this" pointer. If the function returns a structure,
29210 the structure return pointer is in r3. */
29211 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
29212 this_rtx = gen_rtx_REG (Pmode, 4);
29214 this_rtx = gen_rtx_REG (Pmode, 3);
29216 /* Apply the constant offset, if required. */
29218 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
29220 /* Apply the offset from the vtable, if required. */
29223 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
29224 rtx tmp = gen_rtx_REG (Pmode, 12);
29226 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
29227 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
29229 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
29230 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
29234 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
29236 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
29238 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
29241 /* Generate a tail call to the target function. */
29242 if (!TREE_USED (function))
29244 assemble_external (function);
29245 TREE_USED (function) = 1;
29247 funexp = XEXP (DECL_RTL (function), 0);
29248 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
29251 if (MACHOPIC_INDIRECT)
29252 funexp = machopic_indirect_call_target (funexp);
29255 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
29256 generate sibcall RTL explicitly. */
29257 insn = emit_call_insn (
29258 gen_rtx_PARALLEL (VOIDmode,
29260 gen_rtx_CALL (VOIDmode,
29261 funexp, const0_rtx),
29262 gen_rtx_USE (VOIDmode, const0_rtx),
29263 simple_return_rtx)));
29264 SIBLING_CALL_P (insn) = 1;
29267 /* Run just enough of rest_of_compilation to get the insns emitted.
29268 There's not really enough bulk here to make other passes such as
29269 instruction scheduling worth while. Note that use_thunk calls
29270 assemble_start_function and assemble_end_function. */
29271 insn = get_insns ();
29272 shorten_branches (insn);
29273 assemble_start_function (thunk_fndecl, fnname);
29274 final_start_function (insn, file, 1);
29275 final (insn, file, 1);
29276 final_end_function ();
29277 assemble_end_function (thunk_fndecl, fnname);
29279 reload_completed = 0;
29280 epilogue_completed = 0;
29283 /* A quick summary of the various types of 'constant-pool tables'
29286 Target Flags Name One table per
29287 AIX (none) AIX TOC object file
29288 AIX -mfull-toc AIX TOC object file
29289 AIX -mminimal-toc AIX minimal TOC translation unit
29290 SVR4/EABI (none) SVR4 SDATA object file
29291 SVR4/EABI -fpic SVR4 pic object file
29292 SVR4/EABI -fPIC SVR4 PIC translation unit
29293 SVR4/EABI -mrelocatable EABI TOC function
29294 SVR4/EABI -maix AIX TOC object file
29295 SVR4/EABI -maix -mminimal-toc
29296 AIX minimal TOC translation unit
29298 Name Reg. Set by entries contains:
29299 made by addrs? fp? sum?
29301 AIX TOC 2 crt0 as Y option option
29302 AIX minimal TOC 30 prolog gcc Y Y option
29303 SVR4 SDATA 13 crt0 gcc N Y N
29304 SVR4 pic 30 prolog ld Y not yet N
29305 SVR4 PIC 30 prolog gcc Y option option
29306 EABI TOC 30 prolog gcc Y option option
29310 /* Hash functions for the hash table. */
29313 rs6000_hash_constant (rtx k)
29315 enum rtx_code code = GET_CODE (k);
29316 machine_mode mode = GET_MODE (k);
29317 unsigned result = (code << 3) ^ mode;
29318 const char *format;
29321 format = GET_RTX_FORMAT (code);
29322 flen = strlen (format);
29328 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
29330 case CONST_WIDE_INT:
29333 flen = CONST_WIDE_INT_NUNITS (k);
29334 for (i = 0; i < flen; i++)
29335 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
29340 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
29350 for (; fidx < flen; fidx++)
29351 switch (format[fidx])
29356 const char *str = XSTR (k, fidx);
29357 len = strlen (str);
29358 result = result * 613 + len;
29359 for (i = 0; i < len; i++)
29360 result = result * 613 + (unsigned) str[i];
29365 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
29369 result = result * 613 + (unsigned) XINT (k, fidx);
29372 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
29373 result = result * 613 + (unsigned) XWINT (k, fidx);
29377 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
29378 result = result * 613 + (unsigned) (XWINT (k, fidx)
29385 gcc_unreachable ();
29392 toc_hasher::hash (toc_hash_struct *thc)
29394 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
29397 /* Compare H1 and H2 for equivalence. */
29400 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
29405 if (h1->key_mode != h2->key_mode)
29408 return rtx_equal_p (r1, r2);
29411 /* These are the names given by the C++ front-end to vtables, and
29412 vtable-like objects. Ideally, this logic should not be here;
29413 instead, there should be some programmatic way of inquiring as
29414 to whether or not an object is a vtable. */
29416 #define VTABLE_NAME_P(NAME) \
29417 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
29418 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
29419 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
29420 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
29421 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
29423 #ifdef NO_DOLLAR_IN_LABEL
29424 /* Return a GGC-allocated character string translating dollar signs in
29425 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
29428 rs6000_xcoff_strip_dollar (const char *name)
29434 q = (const char *) strchr (name, '$');
29436 if (q == 0 || q == name)
29439 len = strlen (name);
29440 strip = XALLOCAVEC (char, len + 1);
29441 strcpy (strip, name);
29442 p = strip + (q - name);
29446 p = strchr (p + 1, '$');
29449 return ggc_alloc_string (strip, len);
29454 rs6000_output_symbol_ref (FILE *file, rtx x)
29456 const char *name = XSTR (x, 0);
29458 /* Currently C++ toc references to vtables can be emitted before it
29459 is decided whether the vtable is public or private. If this is
29460 the case, then the linker will eventually complain that there is
29461 a reference to an unknown section. Thus, for vtables only,
29462 we emit the TOC reference to reference the identifier and not the
29464 if (VTABLE_NAME_P (name))
29466 RS6000_OUTPUT_BASENAME (file, name);
29469 assemble_name (file, name);
29472 /* Output a TOC entry. We derive the entry name from what is being
29476 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
29479 const char *name = buf;
29481 HOST_WIDE_INT offset = 0;
29483 gcc_assert (!TARGET_NO_TOC);
29485 /* When the linker won't eliminate them, don't output duplicate
29486 TOC entries (this happens on AIX if there is any kind of TOC,
29487 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
29489 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
29491 struct toc_hash_struct *h;
29493 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
29494 time because GGC is not initialized at that point. */
29495 if (toc_hash_table == NULL)
29496 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
29498 h = ggc_alloc<toc_hash_struct> ();
29500 h->key_mode = mode;
29501 h->labelno = labelno;
29503 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
29504 if (*found == NULL)
29506 else /* This is indeed a duplicate.
29507 Set this label equal to that label. */
29509 fputs ("\t.set ", file);
29510 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29511 fprintf (file, "%d,", labelno);
29512 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
29513 fprintf (file, "%d\n", ((*found)->labelno));
29516 if (TARGET_XCOFF && SYMBOL_REF_P (x)
29517 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
29518 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
29520 fputs ("\t.set ", file);
29521 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29522 fprintf (file, "%d,", labelno);
29523 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
29524 fprintf (file, "%d\n", ((*found)->labelno));
29531 /* If we're going to put a double constant in the TOC, make sure it's
29532 aligned properly when strict alignment is on. */
29533 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
29534 && STRICT_ALIGNMENT
29535 && GET_MODE_BITSIZE (mode) >= 64
29536 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
29537 ASM_OUTPUT_ALIGN (file, 3);
29540 (*targetm.asm_out.internal_label) (file, "LC", labelno);
29542 /* Handle FP constants specially. Note that if we have a minimal
29543 TOC, things we put here aren't actually in the TOC, so we can allow
29545 if (CONST_DOUBLE_P (x)
29546 && (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode
29547 || GET_MODE (x) == IFmode || GET_MODE (x) == KFmode))
29551 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29552 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x), k);
29554 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29558 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29559 fputs (DOUBLE_INT_ASM_OP, file);
29561 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29562 k[0] & 0xffffffff, k[1] & 0xffffffff,
29563 k[2] & 0xffffffff, k[3] & 0xffffffff);
29564 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
29565 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29566 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
29567 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
29568 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
29573 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29574 fputs ("\t.long ", file);
29576 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
29577 k[0] & 0xffffffff, k[1] & 0xffffffff,
29578 k[2] & 0xffffffff, k[3] & 0xffffffff);
29579 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
29580 k[0] & 0xffffffff, k[1] & 0xffffffff,
29581 k[2] & 0xffffffff, k[3] & 0xffffffff);
29585 else if (CONST_DOUBLE_P (x)
29586 && (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
29590 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29591 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x), k);
29593 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), k);
29597 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29598 fputs (DOUBLE_INT_ASM_OP, file);
29600 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29601 k[0] & 0xffffffff, k[1] & 0xffffffff);
29602 fprintf (file, "0x%lx%08lx\n",
29603 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
29604 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
29609 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29610 fputs ("\t.long ", file);
29612 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
29613 k[0] & 0xffffffff, k[1] & 0xffffffff);
29614 fprintf (file, "0x%lx,0x%lx\n",
29615 k[0] & 0xffffffff, k[1] & 0xffffffff);
29619 else if (CONST_DOUBLE_P (x)
29620 && (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
29624 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
29625 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x), l);
29627 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l);
29631 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29632 fputs (DOUBLE_INT_ASM_OP, file);
29634 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29635 if (WORDS_BIG_ENDIAN)
29636 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
29638 fprintf (file, "0x%lx\n", l & 0xffffffff);
29643 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29644 fputs ("\t.long ", file);
29646 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
29647 fprintf (file, "0x%lx\n", l & 0xffffffff);
29651 else if (GET_MODE (x) == VOIDmode && CONST_INT_P (x))
29653 unsigned HOST_WIDE_INT low;
29654 HOST_WIDE_INT high;
29656 low = INTVAL (x) & 0xffffffff;
29657 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
29659 /* TOC entries are always Pmode-sized, so when big-endian
29660 smaller integer constants in the TOC need to be padded.
29661 (This is still a win over putting the constants in
29662 a separate constant pool, because then we'd have
29663 to have both a TOC entry _and_ the actual constant.)
29665 For a 32-bit target, CONST_INT values are loaded and shifted
29666 entirely within `low' and can be stored in one TOC entry. */
29668 /* It would be easy to make this work, but it doesn't now. */
29669 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
29671 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
29674 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
29675 high = (HOST_WIDE_INT) low >> 32;
29681 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29682 fputs (DOUBLE_INT_ASM_OP, file);
29684 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29685 (long) high & 0xffffffff, (long) low & 0xffffffff);
29686 fprintf (file, "0x%lx%08lx\n",
29687 (long) high & 0xffffffff, (long) low & 0xffffffff);
29692 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
29694 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29695 fputs ("\t.long ", file);
29697 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
29698 (long) high & 0xffffffff, (long) low & 0xffffffff);
29699 fprintf (file, "0x%lx,0x%lx\n",
29700 (long) high & 0xffffffff, (long) low & 0xffffffff);
29704 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29705 fputs ("\t.long ", file);
29707 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
29708 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
29714 if (GET_CODE (x) == CONST)
29716 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
29717 && CONST_INT_P (XEXP (XEXP (x, 0), 1)));
29719 base = XEXP (XEXP (x, 0), 0);
29720 offset = INTVAL (XEXP (XEXP (x, 0), 1));
29723 switch (GET_CODE (base))
29726 name = XSTR (base, 0);
29730 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
29731 CODE_LABEL_NUMBER (XEXP (base, 0)));
29735 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
29739 gcc_unreachable ();
29742 if (TARGET_ELF || TARGET_MINIMAL_TOC)
29743 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
29746 fputs ("\t.tc ", file);
29747 RS6000_OUTPUT_BASENAME (file, name);
29750 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
29752 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
29754 /* Mark large TOC symbols on AIX with [TE] so they are mapped
29755 after other TOC symbols, reducing overflow of small TOC access
29756 to [TC] symbols. */
29757 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
29758 ? "[TE]," : "[TC],", file);
29761 /* Currently C++ toc references to vtables can be emitted before it
29762 is decided whether the vtable is public or private. If this is
29763 the case, then the linker will eventually complain that there is
29764 a TOC reference to an unknown section. Thus, for vtables only,
29765 we emit the TOC reference to reference the symbol and not the
29767 if (VTABLE_NAME_P (name))
29769 RS6000_OUTPUT_BASENAME (file, name);
29771 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
29772 else if (offset > 0)
29773 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
29776 output_addr_const (file, x);
29779 if (TARGET_XCOFF && SYMBOL_REF_P (base))
29781 switch (SYMBOL_REF_TLS_MODEL (base))
29785 case TLS_MODEL_LOCAL_EXEC:
29786 fputs ("@le", file);
29788 case TLS_MODEL_INITIAL_EXEC:
29789 fputs ("@ie", file);
29791 /* Use global-dynamic for local-dynamic. */
29792 case TLS_MODEL_GLOBAL_DYNAMIC:
29793 case TLS_MODEL_LOCAL_DYNAMIC:
29795 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
29796 fputs ("\t.tc .", file);
29797 RS6000_OUTPUT_BASENAME (file, name);
29798 fputs ("[TC],", file);
29799 output_addr_const (file, x);
29800 fputs ("@m", file);
29803 gcc_unreachable ();
29811 /* Output an assembler pseudo-op to write an ASCII string of N characters
29812 starting at P to FILE.
29814 On the RS/6000, we have to do this using the .byte operation and
29815 write out special characters outside the quoted string.
29816 Also, the assembler is broken; very long strings are truncated,
29817 so we must artificially break them up early. */
29820 output_ascii (FILE *file, const char *p, int n)
29823 int i, count_string;
29824 const char *for_string = "\t.byte \"";
29825 const char *for_decimal = "\t.byte ";
29826 const char *to_close = NULL;
29829 for (i = 0; i < n; i++)
29832 if (c >= ' ' && c < 0177)
29835 fputs (for_string, file);
29838 /* Write two quotes to get one. */
29846 for_decimal = "\"\n\t.byte ";
29850 if (count_string >= 512)
29852 fputs (to_close, file);
29854 for_string = "\t.byte \"";
29855 for_decimal = "\t.byte ";
29863 fputs (for_decimal, file);
29864 fprintf (file, "%d", c);
29866 for_string = "\n\t.byte \"";
29867 for_decimal = ", ";
29873 /* Now close the string if we have written one. Then end the line. */
29875 fputs (to_close, file);
29878 /* Generate a unique section name for FILENAME for a section type
29879 represented by SECTION_DESC. Output goes into BUF.
29881 SECTION_DESC can be any string, as long as it is different for each
29882 possible section type.
29884 We name the section in the same manner as xlc. The name begins with an
29885 underscore followed by the filename (after stripping any leading directory
29886 names) with the last period replaced by the string SECTION_DESC. If
29887 FILENAME does not contain a period, SECTION_DESC is appended to the end of
29891 rs6000_gen_section_name (char **buf, const char *filename,
29892 const char *section_desc)
29894 const char *q, *after_last_slash, *last_period = 0;
29898 after_last_slash = filename;
29899 for (q = filename; *q; q++)
29902 after_last_slash = q + 1;
29903 else if (*q == '.')
29907 len = strlen (after_last_slash) + strlen (section_desc) + 2;
29908 *buf = (char *) xmalloc (len);
29913 for (q = after_last_slash; *q; q++)
29915 if (q == last_period)
29917 strcpy (p, section_desc);
29918 p += strlen (section_desc);
29922 else if (ISALNUM (*q))
29926 if (last_period == 0)
29927 strcpy (p, section_desc);
29932 /* Emit profile function. */
29935 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
29937 /* Non-standard profiling for kernels, which just saves LR then calls
29938 _mcount without worrying about arg saves. The idea is to change
29939 the function prologue as little as possible as it isn't easy to
29940 account for arg save/restore code added just for _mcount. */
29941 if (TARGET_PROFILE_KERNEL)
29944 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29946 #ifndef NO_PROFILE_COUNTERS
29947 # define NO_PROFILE_COUNTERS 0
29949 if (NO_PROFILE_COUNTERS)
29950 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29951 LCT_NORMAL, VOIDmode);
29955 const char *label_name;
29958 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
29959 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
29960 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
29962 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
29963 LCT_NORMAL, VOIDmode, fun, Pmode);
29966 else if (DEFAULT_ABI == ABI_DARWIN)
29968 const char *mcount_name = RS6000_MCOUNT;
29969 int caller_addr_regno = LR_REGNO;
29971 /* Be conservative and always set this, at least for now. */
29972 crtl->uses_pic_offset_table = 1;
29975 /* For PIC code, set up a stub and collect the caller's address
29976 from r0, which is where the prologue puts it. */
29977 if (MACHOPIC_INDIRECT
29978 && crtl->uses_pic_offset_table)
29979 caller_addr_regno = 0;
29981 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
29982 LCT_NORMAL, VOIDmode,
29983 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
29987 /* Write function profiler code. */
29990 output_function_profiler (FILE *file, int labelno)
29994 switch (DEFAULT_ABI)
29997 gcc_unreachable ();
30002 warning (0, "no profiling of 64-bit code for this ABI");
30005 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
30006 fprintf (file, "\tmflr %s\n", reg_names[0]);
30007 if (NO_PROFILE_COUNTERS)
30009 asm_fprintf (file, "\tstw %s,4(%s)\n",
30010 reg_names[0], reg_names[1]);
30012 else if (TARGET_SECURE_PLT && flag_pic)
30014 if (TARGET_LINK_STACK)
30017 get_ppc476_thunk_name (name);
30018 asm_fprintf (file, "\tbl %s\n", name);
30021 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
30022 asm_fprintf (file, "\tstw %s,4(%s)\n",
30023 reg_names[0], reg_names[1]);
30024 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30025 asm_fprintf (file, "\taddis %s,%s,",
30026 reg_names[12], reg_names[12]);
30027 assemble_name (file, buf);
30028 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
30029 assemble_name (file, buf);
30030 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
30032 else if (flag_pic == 1)
30034 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
30035 asm_fprintf (file, "\tstw %s,4(%s)\n",
30036 reg_names[0], reg_names[1]);
30037 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
30038 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
30039 assemble_name (file, buf);
30040 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
30042 else if (flag_pic > 1)
30044 asm_fprintf (file, "\tstw %s,4(%s)\n",
30045 reg_names[0], reg_names[1]);
30046 /* Now, we need to get the address of the label. */
30047 if (TARGET_LINK_STACK)
30050 get_ppc476_thunk_name (name);
30051 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
30052 assemble_name (file, buf);
30053 fputs ("-.\n1:", file);
30054 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30055 asm_fprintf (file, "\taddi %s,%s,4\n",
30056 reg_names[11], reg_names[11]);
30060 fputs ("\tbcl 20,31,1f\n\t.long ", file);
30061 assemble_name (file, buf);
30062 fputs ("-.\n1:", file);
30063 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
30065 asm_fprintf (file, "\tlwz %s,0(%s)\n",
30066 reg_names[0], reg_names[11]);
30067 asm_fprintf (file, "\tadd %s,%s,%s\n",
30068 reg_names[0], reg_names[0], reg_names[11]);
30072 asm_fprintf (file, "\tlis %s,", reg_names[12]);
30073 assemble_name (file, buf);
30074 fputs ("@ha\n", file);
30075 asm_fprintf (file, "\tstw %s,4(%s)\n",
30076 reg_names[0], reg_names[1]);
30077 asm_fprintf (file, "\tla %s,", reg_names[0]);
30078 assemble_name (file, buf);
30079 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
30082 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
30083 fprintf (file, "\tbl %s%s\n",
30084 RS6000_MCOUNT, flag_pic ? "@plt" : "");
30090 /* Don't do anything, done in output_profile_hook (). */
30097 /* The following variable value is the last issued insn. */
30099 static rtx_insn *last_scheduled_insn;
30101 /* The following variable helps to balance issuing of load and
30102 store instructions */
30104 static int load_store_pendulum;
30106 /* The following variable helps pair divide insns during scheduling. */
30107 static int divide_cnt;
30108 /* The following variable helps pair and alternate vector and vector load
30109 insns during scheduling. */
30110 static int vec_pairing;
30113 /* Power4 load update and store update instructions are cracked into a
30114 load or store and an integer insn which are executed in the same cycle.
30115 Branches have their own dispatch slot which does not count against the
30116 GCC issue rate, but it changes the program flow so there are no other
30117 instructions to issue in this cycle. */
30120 rs6000_variable_issue_1 (rtx_insn *insn, int more)
30122 last_scheduled_insn = insn;
30123 if (GET_CODE (PATTERN (insn)) == USE
30124 || GET_CODE (PATTERN (insn)) == CLOBBER)
30126 cached_can_issue_more = more;
30127 return cached_can_issue_more;
30130 if (insn_terminates_group_p (insn, current_group))
30132 cached_can_issue_more = 0;
30133 return cached_can_issue_more;
30136 /* If no reservation, but reach here */
30137 if (recog_memoized (insn) < 0)
30140 if (rs6000_sched_groups)
30142 if (is_microcoded_insn (insn))
30143 cached_can_issue_more = 0;
30144 else if (is_cracked_insn (insn))
30145 cached_can_issue_more = more > 2 ? more - 2 : 0;
30147 cached_can_issue_more = more - 1;
30149 return cached_can_issue_more;
30152 if (rs6000_tune == PROCESSOR_CELL && is_nonpipeline_insn (insn))
30155 cached_can_issue_more = more - 1;
30156 return cached_can_issue_more;
30160 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
30162 int r = rs6000_variable_issue_1 (insn, more);
30164 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
30168 /* Adjust the cost of a scheduling dependency. Return the new cost of
30169 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
30172 rs6000_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
30175 enum attr_type attr_type;
30177 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
30184 /* Data dependency; DEP_INSN writes a register that INSN reads
30185 some cycles later. */
30187 /* Separate a load from a narrower, dependent store. */
30188 if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9)
30189 && GET_CODE (PATTERN (insn)) == SET
30190 && GET_CODE (PATTERN (dep_insn)) == SET
30191 && MEM_P (XEXP (PATTERN (insn), 1))
30192 && MEM_P (XEXP (PATTERN (dep_insn), 0))
30193 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
30194 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
30197 attr_type = get_attr_type (insn);
30202 /* Tell the first scheduling pass about the latency between
30203 a mtctr and bctr (and mtlr and br/blr). The first
30204 scheduling pass will not know about this latency since
30205 the mtctr instruction, which has the latency associated
30206 to it, will be generated by reload. */
30209 /* Leave some extra cycles between a compare and its
30210 dependent branch, to inhibit expensive mispredicts. */
30211 if ((rs6000_tune == PROCESSOR_PPC603
30212 || rs6000_tune == PROCESSOR_PPC604
30213 || rs6000_tune == PROCESSOR_PPC604e
30214 || rs6000_tune == PROCESSOR_PPC620
30215 || rs6000_tune == PROCESSOR_PPC630
30216 || rs6000_tune == PROCESSOR_PPC750
30217 || rs6000_tune == PROCESSOR_PPC7400
30218 || rs6000_tune == PROCESSOR_PPC7450
30219 || rs6000_tune == PROCESSOR_PPCE5500
30220 || rs6000_tune == PROCESSOR_PPCE6500
30221 || rs6000_tune == PROCESSOR_POWER4
30222 || rs6000_tune == PROCESSOR_POWER5
30223 || rs6000_tune == PROCESSOR_POWER7
30224 || rs6000_tune == PROCESSOR_POWER8
30225 || rs6000_tune == PROCESSOR_POWER9
30226 || rs6000_tune == PROCESSOR_CELL)
30227 && recog_memoized (dep_insn)
30228 && (INSN_CODE (dep_insn) >= 0))
30230 switch (get_attr_type (dep_insn))
30233 case TYPE_FPCOMPARE:
30234 case TYPE_CR_LOGICAL:
30238 if (get_attr_dot (dep_insn) == DOT_YES)
30243 if (get_attr_dot (dep_insn) == DOT_YES
30244 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
30255 if ((rs6000_tune == PROCESSOR_POWER6)
30256 && recog_memoized (dep_insn)
30257 && (INSN_CODE (dep_insn) >= 0))
30260 if (GET_CODE (PATTERN (insn)) != SET)
30261 /* If this happens, we have to extend this to schedule
30262 optimally. Return default for now. */
30265 /* Adjust the cost for the case where the value written
30266 by a fixed point operation is used as the address
30267 gen value on a store. */
30268 switch (get_attr_type (dep_insn))
30273 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30274 return get_attr_sign_extend (dep_insn)
30275 == SIGN_EXTEND_YES ? 6 : 4;
30280 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30281 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30291 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30299 if (get_attr_update (dep_insn) == UPDATE_YES
30300 && ! rs6000_store_data_bypass_p (dep_insn, insn))
30306 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30312 if (! rs6000_store_data_bypass_p (dep_insn, insn))
30313 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30323 if ((rs6000_tune == PROCESSOR_POWER6)
30324 && recog_memoized (dep_insn)
30325 && (INSN_CODE (dep_insn) >= 0))
30328 /* Adjust the cost for the case where the value written
30329 by a fixed point instruction is used within the address
30330 gen portion of a subsequent load(u)(x) */
30331 switch (get_attr_type (dep_insn))
30336 if (set_to_load_agen (dep_insn, insn))
30337 return get_attr_sign_extend (dep_insn)
30338 == SIGN_EXTEND_YES ? 6 : 4;
30343 if (set_to_load_agen (dep_insn, insn))
30344 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
30354 if (set_to_load_agen (dep_insn, insn))
30362 if (get_attr_update (dep_insn) == UPDATE_YES
30363 && set_to_load_agen (dep_insn, insn))
30369 if (set_to_load_agen (dep_insn, insn))
30375 if (set_to_load_agen (dep_insn, insn))
30376 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
30386 if ((rs6000_tune == PROCESSOR_POWER6)
30387 && get_attr_update (insn) == UPDATE_NO
30388 && recog_memoized (dep_insn)
30389 && (INSN_CODE (dep_insn) >= 0)
30390 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
30397 /* Fall out to return default cost. */
30401 case REG_DEP_OUTPUT:
30402 /* Output dependency; DEP_INSN writes a register that INSN writes some
30404 if ((rs6000_tune == PROCESSOR_POWER6)
30405 && recog_memoized (dep_insn)
30406 && (INSN_CODE (dep_insn) >= 0))
30408 attr_type = get_attr_type (insn);
30413 case TYPE_FPSIMPLE:
30414 if (get_attr_type (dep_insn) == TYPE_FP
30415 || get_attr_type (dep_insn) == TYPE_FPSIMPLE)
30419 if (get_attr_update (insn) == UPDATE_NO
30420 && get_attr_type (dep_insn) == TYPE_MFFGPR)
30427 /* Fall through, no cost for output dependency. */
30431 /* Anti dependency; DEP_INSN reads a register that INSN writes some
30436 gcc_unreachable ();
30442 /* Debug version of rs6000_adjust_cost. */
30445 rs6000_debug_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
30446 int cost, unsigned int dw)
30448 int ret = rs6000_adjust_cost (insn, dep_type, dep_insn, cost, dw);
30456 default: dep = "unknown depencency"; break;
30457 case REG_DEP_TRUE: dep = "data dependency"; break;
30458 case REG_DEP_OUTPUT: dep = "output dependency"; break;
30459 case REG_DEP_ANTI: dep = "anti depencency"; break;
30463 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
30464 "%s, insn:\n", ret, cost, dep);
30472 /* The function returns a true if INSN is microcoded.
30473 Return false otherwise. */
30476 is_microcoded_insn (rtx_insn *insn)
30478 if (!insn || !NONDEBUG_INSN_P (insn)
30479 || GET_CODE (PATTERN (insn)) == USE
30480 || GET_CODE (PATTERN (insn)) == CLOBBER)
30483 if (rs6000_tune == PROCESSOR_CELL)
30484 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
30486 if (rs6000_sched_groups
30487 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30489 enum attr_type type = get_attr_type (insn);
30490 if ((type == TYPE_LOAD
30491 && get_attr_update (insn) == UPDATE_YES
30492 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
30493 || ((type == TYPE_LOAD || type == TYPE_STORE)
30494 && get_attr_update (insn) == UPDATE_YES
30495 && get_attr_indexed (insn) == INDEXED_YES)
30496 || type == TYPE_MFCR)
30503 /* The function returns true if INSN is cracked into 2 instructions
30504 by the processor (and therefore occupies 2 issue slots). */
30507 is_cracked_insn (rtx_insn *insn)
30509 if (!insn || !NONDEBUG_INSN_P (insn)
30510 || GET_CODE (PATTERN (insn)) == USE
30511 || GET_CODE (PATTERN (insn)) == CLOBBER)
30514 if (rs6000_sched_groups
30515 && (rs6000_tune == PROCESSOR_POWER4 || rs6000_tune == PROCESSOR_POWER5))
30517 enum attr_type type = get_attr_type (insn);
30518 if ((type == TYPE_LOAD
30519 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
30520 && get_attr_update (insn) == UPDATE_NO)
30521 || (type == TYPE_LOAD
30522 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
30523 && get_attr_update (insn) == UPDATE_YES
30524 && get_attr_indexed (insn) == INDEXED_NO)
30525 || (type == TYPE_STORE
30526 && get_attr_update (insn) == UPDATE_YES
30527 && get_attr_indexed (insn) == INDEXED_NO)
30528 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
30529 && get_attr_update (insn) == UPDATE_YES)
30530 || (type == TYPE_CR_LOGICAL
30531 && get_attr_cr_logical_3op (insn) == CR_LOGICAL_3OP_YES)
30532 || (type == TYPE_EXTS
30533 && get_attr_dot (insn) == DOT_YES)
30534 || (type == TYPE_SHIFT
30535 && get_attr_dot (insn) == DOT_YES
30536 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
30537 || (type == TYPE_MUL
30538 && get_attr_dot (insn) == DOT_YES)
30539 || type == TYPE_DIV
30540 || (type == TYPE_INSERT
30541 && get_attr_size (insn) == SIZE_32))
30548 /* The function returns true if INSN can be issued only from
30549 the branch slot. */
30552 is_branch_slot_insn (rtx_insn *insn)
30554 if (!insn || !NONDEBUG_INSN_P (insn)
30555 || GET_CODE (PATTERN (insn)) == USE
30556 || GET_CODE (PATTERN (insn)) == CLOBBER)
30559 if (rs6000_sched_groups)
30561 enum attr_type type = get_attr_type (insn);
30562 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
30570 /* The function returns true if out_inst sets a value that is
30571 used in the address generation computation of in_insn */
30573 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
30575 rtx out_set, in_set;
30577 /* For performance reasons, only handle the simple case where
30578 both loads are a single_set. */
30579 out_set = single_set (out_insn);
30582 in_set = single_set (in_insn);
30584 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
30590 /* Try to determine base/offset/size parts of the given MEM.
30591 Return true if successful, false if all the values couldn't
30594 This function only looks for REG or REG+CONST address forms.
30595 REG+REG address form will return false. */
30598 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
30599 HOST_WIDE_INT *size)
30602 if MEM_SIZE_KNOWN_P (mem)
30603 *size = MEM_SIZE (mem);
30607 addr_rtx = (XEXP (mem, 0));
30608 if (GET_CODE (addr_rtx) == PRE_MODIFY)
30609 addr_rtx = XEXP (addr_rtx, 1);
30612 while (GET_CODE (addr_rtx) == PLUS
30613 && CONST_INT_P (XEXP (addr_rtx, 1)))
30615 *offset += INTVAL (XEXP (addr_rtx, 1));
30616 addr_rtx = XEXP (addr_rtx, 0);
30618 if (!REG_P (addr_rtx))
30625 /* The function returns true if the target storage location of
30626 mem1 is adjacent to the target storage location of mem2 */
30627 /* Return 1 if memory locations are adjacent. */
30630 adjacent_mem_locations (rtx mem1, rtx mem2)
30633 HOST_WIDE_INT off1, size1, off2, size2;
30635 if (get_memref_parts (mem1, ®1, &off1, &size1)
30636 && get_memref_parts (mem2, ®2, &off2, &size2))
30637 return ((REGNO (reg1) == REGNO (reg2))
30638 && ((off1 + size1 == off2)
30639 || (off2 + size2 == off1)));
30644 /* This function returns true if it can be determined that the two MEM
30645 locations overlap by at least 1 byte based on base reg/offset/size. */
30648 mem_locations_overlap (rtx mem1, rtx mem2)
30651 HOST_WIDE_INT off1, size1, off2, size2;
30653 if (get_memref_parts (mem1, ®1, &off1, &size1)
30654 && get_memref_parts (mem2, ®2, &off2, &size2))
30655 return ((REGNO (reg1) == REGNO (reg2))
30656 && (((off1 <= off2) && (off1 + size1 > off2))
30657 || ((off2 <= off1) && (off2 + size2 > off1))));
30662 /* A C statement (sans semicolon) to update the integer scheduling
30663 priority INSN_PRIORITY (INSN). Increase the priority to execute the
30664 INSN earlier, reduce the priority to execute INSN later. Do not
30665 define this macro if you do not need to adjust the scheduling
30666 priorities of insns. */
30669 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
30671 rtx load_mem, str_mem;
30672 /* On machines (like the 750) which have asymmetric integer units,
30673 where one integer unit can do multiply and divides and the other
30674 can't, reduce the priority of multiply/divide so it is scheduled
30675 before other integer operations. */
30678 if (! INSN_P (insn))
30681 if (GET_CODE (PATTERN (insn)) == USE)
30684 switch (rs6000_tune) {
30685 case PROCESSOR_PPC750:
30686 switch (get_attr_type (insn))
30693 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
30694 priority, priority);
30695 if (priority >= 0 && priority < 0x01000000)
30702 if (insn_must_be_first_in_group (insn)
30703 && reload_completed
30704 && current_sched_info->sched_max_insns_priority
30705 && rs6000_sched_restricted_insns_priority)
30708 /* Prioritize insns that can be dispatched only in the first
30710 if (rs6000_sched_restricted_insns_priority == 1)
30711 /* Attach highest priority to insn. This means that in
30712 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
30713 precede 'priority' (critical path) considerations. */
30714 return current_sched_info->sched_max_insns_priority;
30715 else if (rs6000_sched_restricted_insns_priority == 2)
30716 /* Increase priority of insn by a minimal amount. This means that in
30717 haifa-sched.c:ready_sort(), only 'priority' (critical path)
30718 considerations precede dispatch-slot restriction considerations. */
30719 return (priority + 1);
30722 if (rs6000_tune == PROCESSOR_POWER6
30723 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
30724 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
30725 /* Attach highest priority to insn if the scheduler has just issued two
30726 stores and this instruction is a load, or two loads and this instruction
30727 is a store. Power6 wants loads and stores scheduled alternately
30729 return current_sched_info->sched_max_insns_priority;
30734 /* Return true if the instruction is nonpipelined on the Cell. */
30736 is_nonpipeline_insn (rtx_insn *insn)
30738 enum attr_type type;
30739 if (!insn || !NONDEBUG_INSN_P (insn)
30740 || GET_CODE (PATTERN (insn)) == USE
30741 || GET_CODE (PATTERN (insn)) == CLOBBER)
30744 type = get_attr_type (insn);
30745 if (type == TYPE_MUL
30746 || type == TYPE_DIV
30747 || type == TYPE_SDIV
30748 || type == TYPE_DDIV
30749 || type == TYPE_SSQRT
30750 || type == TYPE_DSQRT
30751 || type == TYPE_MFCR
30752 || type == TYPE_MFCRF
30753 || type == TYPE_MFJMPR)
30761 /* Return how many instructions the machine can issue per cycle. */
30764 rs6000_issue_rate (void)
30766 /* Unless scheduling for register pressure, use issue rate of 1 for
30767 first scheduling pass to decrease degradation. */
30768 if (!reload_completed && !flag_sched_pressure)
30771 switch (rs6000_tune) {
30772 case PROCESSOR_RS64A:
30773 case PROCESSOR_PPC601: /* ? */
30774 case PROCESSOR_PPC7450:
30776 case PROCESSOR_PPC440:
30777 case PROCESSOR_PPC603:
30778 case PROCESSOR_PPC750:
30779 case PROCESSOR_PPC7400:
30780 case PROCESSOR_PPC8540:
30781 case PROCESSOR_PPC8548:
30782 case PROCESSOR_CELL:
30783 case PROCESSOR_PPCE300C2:
30784 case PROCESSOR_PPCE300C3:
30785 case PROCESSOR_PPCE500MC:
30786 case PROCESSOR_PPCE500MC64:
30787 case PROCESSOR_PPCE5500:
30788 case PROCESSOR_PPCE6500:
30789 case PROCESSOR_TITAN:
30791 case PROCESSOR_PPC476:
30792 case PROCESSOR_PPC604:
30793 case PROCESSOR_PPC604e:
30794 case PROCESSOR_PPC620:
30795 case PROCESSOR_PPC630:
30797 case PROCESSOR_POWER4:
30798 case PROCESSOR_POWER5:
30799 case PROCESSOR_POWER6:
30800 case PROCESSOR_POWER7:
30802 case PROCESSOR_POWER8:
30804 case PROCESSOR_POWER9:
30811 /* Return how many instructions to look ahead for better insn
30815 rs6000_use_sched_lookahead (void)
30817 switch (rs6000_tune)
30819 case PROCESSOR_PPC8540:
30820 case PROCESSOR_PPC8548:
30823 case PROCESSOR_CELL:
30824 return (reload_completed ? 8 : 0);
30831 /* We are choosing insn from the ready queue. Return zero if INSN can be
30834 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
30836 if (ready_index == 0)
30839 if (rs6000_tune != PROCESSOR_CELL)
30842 gcc_assert (insn != NULL_RTX && INSN_P (insn));
30844 if (!reload_completed
30845 || is_nonpipeline_insn (insn)
30846 || is_microcoded_insn (insn))
30852 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
30853 and return true. */
30856 find_mem_ref (rtx pat, rtx *mem_ref)
30861 /* stack_tie does not produce any real memory traffic. */
30862 if (tie_operand (pat, VOIDmode))
30871 /* Recursively process the pattern. */
30872 fmt = GET_RTX_FORMAT (GET_CODE (pat));
30874 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
30878 if (find_mem_ref (XEXP (pat, i), mem_ref))
30881 else if (fmt[i] == 'E')
30882 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
30884 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
30892 /* Determine if PAT is a PATTERN of a load insn. */
30895 is_load_insn1 (rtx pat, rtx *load_mem)
30897 if (!pat || pat == NULL_RTX)
30900 if (GET_CODE (pat) == SET)
30901 return find_mem_ref (SET_SRC (pat), load_mem);
30903 if (GET_CODE (pat) == PARALLEL)
30907 for (i = 0; i < XVECLEN (pat, 0); i++)
30908 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
30915 /* Determine if INSN loads from memory. */
30918 is_load_insn (rtx insn, rtx *load_mem)
30920 if (!insn || !INSN_P (insn))
30926 return is_load_insn1 (PATTERN (insn), load_mem);
30929 /* Determine if PAT is a PATTERN of a store insn. */
30932 is_store_insn1 (rtx pat, rtx *str_mem)
30934 if (!pat || pat == NULL_RTX)
30937 if (GET_CODE (pat) == SET)
30938 return find_mem_ref (SET_DEST (pat), str_mem);
30940 if (GET_CODE (pat) == PARALLEL)
30944 for (i = 0; i < XVECLEN (pat, 0); i++)
30945 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
30952 /* Determine if INSN stores to memory. */
30955 is_store_insn (rtx insn, rtx *str_mem)
30957 if (!insn || !INSN_P (insn))
30960 return is_store_insn1 (PATTERN (insn), str_mem);
30963 /* Return whether TYPE is a Power9 pairable vector instruction type. */
30966 is_power9_pairable_vec_type (enum attr_type type)
30970 case TYPE_VECSIMPLE:
30971 case TYPE_VECCOMPLEX:
30975 case TYPE_VECFLOAT:
30977 case TYPE_VECDOUBLE:
30985 /* Returns whether the dependence between INSN and NEXT is considered
30986 costly by the given target. */
30989 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
30993 rtx load_mem, str_mem;
30995 /* If the flag is not enabled - no dependence is considered costly;
30996 allow all dependent insns in the same group.
30997 This is the most aggressive option. */
30998 if (rs6000_sched_costly_dep == no_dep_costly)
31001 /* If the flag is set to 1 - a dependence is always considered costly;
31002 do not allow dependent instructions in the same group.
31003 This is the most conservative option. */
31004 if (rs6000_sched_costly_dep == all_deps_costly)
31007 insn = DEP_PRO (dep);
31008 next = DEP_CON (dep);
31010 if (rs6000_sched_costly_dep == store_to_load_dep_costly
31011 && is_load_insn (next, &load_mem)
31012 && is_store_insn (insn, &str_mem))
31013 /* Prevent load after store in the same group. */
31016 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
31017 && is_load_insn (next, &load_mem)
31018 && is_store_insn (insn, &str_mem)
31019 && DEP_TYPE (dep) == REG_DEP_TRUE
31020 && mem_locations_overlap(str_mem, load_mem))
31021 /* Prevent load after store in the same group if it is a true
31025 /* The flag is set to X; dependences with latency >= X are considered costly,
31026 and will not be scheduled in the same group. */
31027 if (rs6000_sched_costly_dep <= max_dep_latency
31028 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
31034 /* Return the next insn after INSN that is found before TAIL is reached,
31035 skipping any "non-active" insns - insns that will not actually occupy
31036 an issue slot. Return NULL_RTX if such an insn is not found. */
31039 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
31041 if (insn == NULL_RTX || insn == tail)
31046 insn = NEXT_INSN (insn);
31047 if (insn == NULL_RTX || insn == tail)
31051 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
31052 || (NONJUMP_INSN_P (insn)
31053 && GET_CODE (PATTERN (insn)) != USE
31054 && GET_CODE (PATTERN (insn)) != CLOBBER
31055 && INSN_CODE (insn) != CODE_FOR_stack_tie))
31061 /* Do Power9 specific sched_reorder2 reordering of ready list. */
31064 power9_sched_reorder2 (rtx_insn **ready, int lastpos)
31069 enum attr_type type, type2;
31071 type = get_attr_type (last_scheduled_insn);
31073 /* Try to issue fixed point divides back-to-back in pairs so they will be
31074 routed to separate execution units and execute in parallel. */
31075 if (type == TYPE_DIV && divide_cnt == 0)
31077 /* First divide has been scheduled. */
31080 /* Scan the ready list looking for another divide, if found move it
31081 to the end of the list so it is chosen next. */
31085 if (recog_memoized (ready[pos]) >= 0
31086 && get_attr_type (ready[pos]) == TYPE_DIV)
31089 for (i = pos; i < lastpos; i++)
31090 ready[i] = ready[i + 1];
31091 ready[lastpos] = tmp;
31099 /* Last insn was the 2nd divide or not a divide, reset the counter. */
31102 /* The best dispatch throughput for vector and vector load insns can be
31103 achieved by interleaving a vector and vector load such that they'll
31104 dispatch to the same superslice. If this pairing cannot be achieved
31105 then it is best to pair vector insns together and vector load insns
31108 To aid in this pairing, vec_pairing maintains the current state with
31109 the following values:
31111 0 : Initial state, no vecload/vector pairing has been started.
31113 1 : A vecload or vector insn has been issued and a candidate for
31114 pairing has been found and moved to the end of the ready
31116 if (type == TYPE_VECLOAD)
31118 /* Issued a vecload. */
31119 if (vec_pairing == 0)
31121 int vecload_pos = -1;
31122 /* We issued a single vecload, look for a vector insn to pair it
31123 with. If one isn't found, try to pair another vecload. */
31127 if (recog_memoized (ready[pos]) >= 0)
31129 type2 = get_attr_type (ready[pos]);
31130 if (is_power9_pairable_vec_type (type2))
31132 /* Found a vector insn to pair with, move it to the
31133 end of the ready list so it is scheduled next. */
31135 for (i = pos; i < lastpos; i++)
31136 ready[i] = ready[i + 1];
31137 ready[lastpos] = tmp;
31139 return cached_can_issue_more;
31141 else if (type2 == TYPE_VECLOAD && vecload_pos == -1)
31142 /* Remember position of first vecload seen. */
31147 if (vecload_pos >= 0)
31149 /* Didn't find a vector to pair with but did find a vecload,
31150 move it to the end of the ready list. */
31151 tmp = ready[vecload_pos];
31152 for (i = vecload_pos; i < lastpos; i++)
31153 ready[i] = ready[i + 1];
31154 ready[lastpos] = tmp;
31156 return cached_can_issue_more;
31160 else if (is_power9_pairable_vec_type (type))
31162 /* Issued a vector operation. */
31163 if (vec_pairing == 0)
31166 /* We issued a single vector insn, look for a vecload to pair it
31167 with. If one isn't found, try to pair another vector. */
31171 if (recog_memoized (ready[pos]) >= 0)
31173 type2 = get_attr_type (ready[pos]);
31174 if (type2 == TYPE_VECLOAD)
31176 /* Found a vecload insn to pair with, move it to the
31177 end of the ready list so it is scheduled next. */
31179 for (i = pos; i < lastpos; i++)
31180 ready[i] = ready[i + 1];
31181 ready[lastpos] = tmp;
31183 return cached_can_issue_more;
31185 else if (is_power9_pairable_vec_type (type2)
31187 /* Remember position of first vector insn seen. */
31194 /* Didn't find a vecload to pair with but did find a vector
31195 insn, move it to the end of the ready list. */
31196 tmp = ready[vec_pos];
31197 for (i = vec_pos; i < lastpos; i++)
31198 ready[i] = ready[i + 1];
31199 ready[lastpos] = tmp;
31201 return cached_can_issue_more;
31206 /* We've either finished a vec/vecload pair, couldn't find an insn to
31207 continue the current pair, or the last insn had nothing to do with
31208 with pairing. In any case, reset the state. */
31212 return cached_can_issue_more;
31215 /* We are about to begin issuing insns for this clock cycle. */
31218 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
31219 rtx_insn **ready ATTRIBUTE_UNUSED,
31220 int *pn_ready ATTRIBUTE_UNUSED,
31221 int clock_var ATTRIBUTE_UNUSED)
31223 int n_ready = *pn_ready;
31226 fprintf (dump, "// rs6000_sched_reorder :\n");
31228 /* Reorder the ready list, if the second to last ready insn
31229 is a nonepipeline insn. */
31230 if (rs6000_tune == PROCESSOR_CELL && n_ready > 1)
31232 if (is_nonpipeline_insn (ready[n_ready - 1])
31233 && (recog_memoized (ready[n_ready - 2]) > 0))
31234 /* Simply swap first two insns. */
31235 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
31238 if (rs6000_tune == PROCESSOR_POWER6)
31239 load_store_pendulum = 0;
31241 return rs6000_issue_rate ();
31244 /* Like rs6000_sched_reorder, but called after issuing each insn. */
31247 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
31248 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
31251 fprintf (dump, "// rs6000_sched_reorder2 :\n");
31253 /* For Power6, we need to handle some special cases to try and keep the
31254 store queue from overflowing and triggering expensive flushes.
31256 This code monitors how load and store instructions are being issued
31257 and skews the ready list one way or the other to increase the likelihood
31258 that a desired instruction is issued at the proper time.
31260 A couple of things are done. First, we maintain a "load_store_pendulum"
31261 to track the current state of load/store issue.
31263 - If the pendulum is at zero, then no loads or stores have been
31264 issued in the current cycle so we do nothing.
31266 - If the pendulum is 1, then a single load has been issued in this
31267 cycle and we attempt to locate another load in the ready list to
31270 - If the pendulum is -2, then two stores have already been
31271 issued in this cycle, so we increase the priority of the first load
31272 in the ready list to increase it's likelihood of being chosen first
31275 - If the pendulum is -1, then a single store has been issued in this
31276 cycle and we attempt to locate another store in the ready list to
31277 issue with it, preferring a store to an adjacent memory location to
31278 facilitate store pairing in the store queue.
31280 - If the pendulum is 2, then two loads have already been
31281 issued in this cycle, so we increase the priority of the first store
31282 in the ready list to increase it's likelihood of being chosen first
31285 - If the pendulum < -2 or > 2, then do nothing.
31287 Note: This code covers the most common scenarios. There exist non
31288 load/store instructions which make use of the LSU and which
31289 would need to be accounted for to strictly model the behavior
31290 of the machine. Those instructions are currently unaccounted
31291 for to help minimize compile time overhead of this code.
31293 if (rs6000_tune == PROCESSOR_POWER6 && last_scheduled_insn)
31298 rtx load_mem, str_mem;
31300 if (is_store_insn (last_scheduled_insn, &str_mem))
31301 /* Issuing a store, swing the load_store_pendulum to the left */
31302 load_store_pendulum--;
31303 else if (is_load_insn (last_scheduled_insn, &load_mem))
31304 /* Issuing a load, swing the load_store_pendulum to the right */
31305 load_store_pendulum++;
31307 return cached_can_issue_more;
31309 /* If the pendulum is balanced, or there is only one instruction on
31310 the ready list, then all is well, so return. */
31311 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
31312 return cached_can_issue_more;
31314 if (load_store_pendulum == 1)
31316 /* A load has been issued in this cycle. Scan the ready list
31317 for another load to issue with it */
31322 if (is_load_insn (ready[pos], &load_mem))
31324 /* Found a load. Move it to the head of the ready list,
31325 and adjust it's priority so that it is more likely to
31328 for (i=pos; i<*pn_ready-1; i++)
31329 ready[i] = ready[i + 1];
31330 ready[*pn_ready-1] = tmp;
31332 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31333 INSN_PRIORITY (tmp)++;
31339 else if (load_store_pendulum == -2)
31341 /* Two stores have been issued in this cycle. Increase the
31342 priority of the first load in the ready list to favor it for
31343 issuing in the next cycle. */
31348 if (is_load_insn (ready[pos], &load_mem)
31350 && INSN_PRIORITY_KNOWN (ready[pos]))
31352 INSN_PRIORITY (ready[pos])++;
31354 /* Adjust the pendulum to account for the fact that a load
31355 was found and increased in priority. This is to prevent
31356 increasing the priority of multiple loads */
31357 load_store_pendulum--;
31364 else if (load_store_pendulum == -1)
31366 /* A store has been issued in this cycle. Scan the ready list for
31367 another store to issue with it, preferring a store to an adjacent
31369 int first_store_pos = -1;
31375 if (is_store_insn (ready[pos], &str_mem))
31378 /* Maintain the index of the first store found on the
31380 if (first_store_pos == -1)
31381 first_store_pos = pos;
31383 if (is_store_insn (last_scheduled_insn, &str_mem2)
31384 && adjacent_mem_locations (str_mem, str_mem2))
31386 /* Found an adjacent store. Move it to the head of the
31387 ready list, and adjust it's priority so that it is
31388 more likely to stay there */
31390 for (i=pos; i<*pn_ready-1; i++)
31391 ready[i] = ready[i + 1];
31392 ready[*pn_ready-1] = tmp;
31394 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31395 INSN_PRIORITY (tmp)++;
31397 first_store_pos = -1;
31405 if (first_store_pos >= 0)
31407 /* An adjacent store wasn't found, but a non-adjacent store was,
31408 so move the non-adjacent store to the front of the ready
31409 list, and adjust its priority so that it is more likely to
31411 tmp = ready[first_store_pos];
31412 for (i=first_store_pos; i<*pn_ready-1; i++)
31413 ready[i] = ready[i + 1];
31414 ready[*pn_ready-1] = tmp;
31415 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
31416 INSN_PRIORITY (tmp)++;
31419 else if (load_store_pendulum == 2)
31421 /* Two loads have been issued in this cycle. Increase the priority
31422 of the first store in the ready list to favor it for issuing in
31428 if (is_store_insn (ready[pos], &str_mem)
31430 && INSN_PRIORITY_KNOWN (ready[pos]))
31432 INSN_PRIORITY (ready[pos])++;
31434 /* Adjust the pendulum to account for the fact that a store
31435 was found and increased in priority. This is to prevent
31436 increasing the priority of multiple stores */
31437 load_store_pendulum++;
31446 /* Do Power9 dependent reordering if necessary. */
31447 if (rs6000_tune == PROCESSOR_POWER9 && last_scheduled_insn
31448 && recog_memoized (last_scheduled_insn) >= 0)
31449 return power9_sched_reorder2 (ready, *pn_ready - 1);
31451 return cached_can_issue_more;
31454 /* Return whether the presence of INSN causes a dispatch group termination
31455 of group WHICH_GROUP.
31457 If WHICH_GROUP == current_group, this function will return true if INSN
31458 causes the termination of the current group (i.e, the dispatch group to
31459 which INSN belongs). This means that INSN will be the last insn in the
31460 group it belongs to.
31462 If WHICH_GROUP == previous_group, this function will return true if INSN
31463 causes the termination of the previous group (i.e, the dispatch group that
31464 precedes the group to which INSN belongs). This means that INSN will be
31465 the first insn in the group it belongs to). */
31468 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
31475 first = insn_must_be_first_in_group (insn);
31476 last = insn_must_be_last_in_group (insn);
31481 if (which_group == current_group)
31483 else if (which_group == previous_group)
31491 insn_must_be_first_in_group (rtx_insn *insn)
31493 enum attr_type type;
31497 || DEBUG_INSN_P (insn)
31498 || GET_CODE (PATTERN (insn)) == USE
31499 || GET_CODE (PATTERN (insn)) == CLOBBER)
31502 switch (rs6000_tune)
31504 case PROCESSOR_POWER5:
31505 if (is_cracked_insn (insn))
31508 case PROCESSOR_POWER4:
31509 if (is_microcoded_insn (insn))
31512 if (!rs6000_sched_groups)
31515 type = get_attr_type (insn);
31522 case TYPE_CR_LOGICAL:
31535 case PROCESSOR_POWER6:
31536 type = get_attr_type (insn);
31545 case TYPE_FPCOMPARE:
31556 if (get_attr_dot (insn) == DOT_NO
31557 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31562 if (get_attr_size (insn) == SIZE_32)
31570 if (get_attr_update (insn) == UPDATE_YES)
31578 case PROCESSOR_POWER7:
31579 type = get_attr_type (insn);
31583 case TYPE_CR_LOGICAL:
31597 if (get_attr_dot (insn) == DOT_YES)
31602 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31603 || get_attr_update (insn) == UPDATE_YES)
31610 if (get_attr_update (insn) == UPDATE_YES)
31618 case PROCESSOR_POWER8:
31619 type = get_attr_type (insn);
31623 case TYPE_CR_LOGICAL:
31631 case TYPE_VECSTORE:
31638 if (get_attr_dot (insn) == DOT_YES)
31643 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31644 || get_attr_update (insn) == UPDATE_YES)
31649 if (get_attr_update (insn) == UPDATE_YES
31650 && get_attr_indexed (insn) == INDEXED_YES)
31666 insn_must_be_last_in_group (rtx_insn *insn)
31668 enum attr_type type;
31672 || DEBUG_INSN_P (insn)
31673 || GET_CODE (PATTERN (insn)) == USE
31674 || GET_CODE (PATTERN (insn)) == CLOBBER)
31677 switch (rs6000_tune) {
31678 case PROCESSOR_POWER4:
31679 case PROCESSOR_POWER5:
31680 if (is_microcoded_insn (insn))
31683 if (is_branch_slot_insn (insn))
31687 case PROCESSOR_POWER6:
31688 type = get_attr_type (insn);
31696 case TYPE_FPCOMPARE:
31707 if (get_attr_dot (insn) == DOT_NO
31708 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
31713 if (get_attr_size (insn) == SIZE_32)
31721 case PROCESSOR_POWER7:
31722 type = get_attr_type (insn);
31732 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31733 && get_attr_update (insn) == UPDATE_YES)
31738 if (get_attr_update (insn) == UPDATE_YES
31739 && get_attr_indexed (insn) == INDEXED_YES)
31747 case PROCESSOR_POWER8:
31748 type = get_attr_type (insn);
31760 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
31761 && get_attr_update (insn) == UPDATE_YES)
31766 if (get_attr_update (insn) == UPDATE_YES
31767 && get_attr_indexed (insn) == INDEXED_YES)
31782 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
31783 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
31786 is_costly_group (rtx *group_insns, rtx next_insn)
31789 int issue_rate = rs6000_issue_rate ();
31791 for (i = 0; i < issue_rate; i++)
31793 sd_iterator_def sd_it;
31795 rtx insn = group_insns[i];
31800 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
31802 rtx next = DEP_CON (dep);
31804 if (next == next_insn
31805 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
31813 /* Utility of the function redefine_groups.
31814 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
31815 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
31816 to keep it "far" (in a separate group) from GROUP_INSNS, following
31817 one of the following schemes, depending on the value of the flag
31818 -minsert_sched_nops = X:
31819 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
31820 in order to force NEXT_INSN into a separate group.
31821 (2) X < sched_finish_regroup_exact: insert exactly X nops.
31822 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
31823 insertion (has a group just ended, how many vacant issue slots remain in the
31824 last group, and how many dispatch groups were encountered so far). */
31827 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
31828 rtx_insn *next_insn, bool *group_end, int can_issue_more,
31833 int issue_rate = rs6000_issue_rate ();
31834 bool end = *group_end;
31837 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
31838 return can_issue_more;
31840 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
31841 return can_issue_more;
31843 force = is_costly_group (group_insns, next_insn);
31845 return can_issue_more;
31847 if (sched_verbose > 6)
31848 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
31849 *group_count ,can_issue_more);
31851 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
31854 can_issue_more = 0;
31856 /* Since only a branch can be issued in the last issue_slot, it is
31857 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
31858 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
31859 in this case the last nop will start a new group and the branch
31860 will be forced to the new group. */
31861 if (can_issue_more && !is_branch_slot_insn (next_insn))
31864 /* Do we have a special group ending nop? */
31865 if (rs6000_tune == PROCESSOR_POWER6 || rs6000_tune == PROCESSOR_POWER7
31866 || rs6000_tune == PROCESSOR_POWER8)
31868 nop = gen_group_ending_nop ();
31869 emit_insn_before (nop, next_insn);
31870 can_issue_more = 0;
31873 while (can_issue_more > 0)
31876 emit_insn_before (nop, next_insn);
31884 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
31886 int n_nops = rs6000_sched_insert_nops;
31888 /* Nops can't be issued from the branch slot, so the effective
31889 issue_rate for nops is 'issue_rate - 1'. */
31890 if (can_issue_more == 0)
31891 can_issue_more = issue_rate;
31893 if (can_issue_more == 0)
31895 can_issue_more = issue_rate - 1;
31898 for (i = 0; i < issue_rate; i++)
31900 group_insns[i] = 0;
31907 emit_insn_before (nop, next_insn);
31908 if (can_issue_more == issue_rate - 1) /* new group begins */
31911 if (can_issue_more == 0)
31913 can_issue_more = issue_rate - 1;
31916 for (i = 0; i < issue_rate; i++)
31918 group_insns[i] = 0;
31924 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
31927 /* Is next_insn going to start a new group? */
31930 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
31931 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
31932 || (can_issue_more < issue_rate &&
31933 insn_terminates_group_p (next_insn, previous_group)));
31934 if (*group_end && end)
31937 if (sched_verbose > 6)
31938 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
31939 *group_count, can_issue_more);
31940 return can_issue_more;
31943 return can_issue_more;
31946 /* This function tries to synch the dispatch groups that the compiler "sees"
31947 with the dispatch groups that the processor dispatcher is expected to
31948 form in practice. It tries to achieve this synchronization by forcing the
31949 estimated processor grouping on the compiler (as opposed to the function
31950 'pad_goups' which tries to force the scheduler's grouping on the processor).
31952 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
31953 examines the (estimated) dispatch groups that will be formed by the processor
31954 dispatcher. It marks these group boundaries to reflect the estimated
31955 processor grouping, overriding the grouping that the scheduler had marked.
31956 Depending on the value of the flag '-minsert-sched-nops' this function can
31957 force certain insns into separate groups or force a certain distance between
31958 them by inserting nops, for example, if there exists a "costly dependence"
31961 The function estimates the group boundaries that the processor will form as
31962 follows: It keeps track of how many vacant issue slots are available after
31963 each insn. A subsequent insn will start a new group if one of the following
31965 - no more vacant issue slots remain in the current dispatch group.
31966 - only the last issue slot, which is the branch slot, is vacant, but the next
31967 insn is not a branch.
31968 - only the last 2 or less issue slots, including the branch slot, are vacant,
31969 which means that a cracked insn (which occupies two issue slots) can't be
31970 issued in this group.
31971 - less than 'issue_rate' slots are vacant, and the next insn always needs to
31972 start a new group. */
31975 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
31978 rtx_insn *insn, *next_insn;
31980 int can_issue_more;
31983 int group_count = 0;
31987 issue_rate = rs6000_issue_rate ();
31988 group_insns = XALLOCAVEC (rtx, issue_rate);
31989 for (i = 0; i < issue_rate; i++)
31991 group_insns[i] = 0;
31993 can_issue_more = issue_rate;
31995 insn = get_next_active_insn (prev_head_insn, tail);
31998 while (insn != NULL_RTX)
32000 slot = (issue_rate - can_issue_more);
32001 group_insns[slot] = insn;
32003 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32004 if (insn_terminates_group_p (insn, current_group))
32005 can_issue_more = 0;
32007 next_insn = get_next_active_insn (insn, tail);
32008 if (next_insn == NULL_RTX)
32009 return group_count + 1;
32011 /* Is next_insn going to start a new group? */
32013 = (can_issue_more == 0
32014 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
32015 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
32016 || (can_issue_more < issue_rate &&
32017 insn_terminates_group_p (next_insn, previous_group)));
32019 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
32020 next_insn, &group_end, can_issue_more,
32026 can_issue_more = 0;
32027 for (i = 0; i < issue_rate; i++)
32029 group_insns[i] = 0;
32033 if (GET_MODE (next_insn) == TImode && can_issue_more)
32034 PUT_MODE (next_insn, VOIDmode);
32035 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
32036 PUT_MODE (next_insn, TImode);
32039 if (can_issue_more == 0)
32040 can_issue_more = issue_rate;
32043 return group_count;
32046 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
32047 dispatch group boundaries that the scheduler had marked. Pad with nops
32048 any dispatch groups which have vacant issue slots, in order to force the
32049 scheduler's grouping on the processor dispatcher. The function
32050 returns the number of dispatch groups found. */
32053 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
32056 rtx_insn *insn, *next_insn;
32059 int can_issue_more;
32061 int group_count = 0;
32063 /* Initialize issue_rate. */
32064 issue_rate = rs6000_issue_rate ();
32065 can_issue_more = issue_rate;
32067 insn = get_next_active_insn (prev_head_insn, tail);
32068 next_insn = get_next_active_insn (insn, tail);
32070 while (insn != NULL_RTX)
32073 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
32075 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
32077 if (next_insn == NULL_RTX)
32082 /* If the scheduler had marked group termination at this location
32083 (between insn and next_insn), and neither insn nor next_insn will
32084 force group termination, pad the group with nops to force group
32087 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
32088 && !insn_terminates_group_p (insn, current_group)
32089 && !insn_terminates_group_p (next_insn, previous_group))
32091 if (!is_branch_slot_insn (next_insn))
32094 while (can_issue_more)
32097 emit_insn_before (nop, next_insn);
32102 can_issue_more = issue_rate;
32107 next_insn = get_next_active_insn (insn, tail);
32110 return group_count;
32113 /* We're beginning a new block. Initialize data structures as necessary. */
32116 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
32117 int sched_verbose ATTRIBUTE_UNUSED,
32118 int max_ready ATTRIBUTE_UNUSED)
32120 last_scheduled_insn = NULL;
32121 load_store_pendulum = 0;
32126 /* The following function is called at the end of scheduling BB.
32127 After reload, it inserts nops at insn group bundling. */
32130 rs6000_sched_finish (FILE *dump, int sched_verbose)
32135 fprintf (dump, "=== Finishing schedule.\n");
32137 if (reload_completed && rs6000_sched_groups)
32139 /* Do not run sched_finish hook when selective scheduling enabled. */
32140 if (sel_sched_p ())
32143 if (rs6000_sched_insert_nops == sched_finish_none)
32146 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
32147 n_groups = pad_groups (dump, sched_verbose,
32148 current_sched_info->prev_head,
32149 current_sched_info->next_tail);
32151 n_groups = redefine_groups (dump, sched_verbose,
32152 current_sched_info->prev_head,
32153 current_sched_info->next_tail);
32155 if (sched_verbose >= 6)
32157 fprintf (dump, "ngroups = %d\n", n_groups);
32158 print_rtl (dump, current_sched_info->prev_head);
32159 fprintf (dump, "Done finish_sched\n");
32164 struct rs6000_sched_context
32166 short cached_can_issue_more;
32167 rtx_insn *last_scheduled_insn;
32168 int load_store_pendulum;
32173 typedef struct rs6000_sched_context rs6000_sched_context_def;
32174 typedef rs6000_sched_context_def *rs6000_sched_context_t;
32176 /* Allocate store for new scheduling context. */
32178 rs6000_alloc_sched_context (void)
32180 return xmalloc (sizeof (rs6000_sched_context_def));
32183 /* If CLEAN_P is true then initializes _SC with clean data,
32184 and from the global context otherwise. */
32186 rs6000_init_sched_context (void *_sc, bool clean_p)
32188 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32192 sc->cached_can_issue_more = 0;
32193 sc->last_scheduled_insn = NULL;
32194 sc->load_store_pendulum = 0;
32195 sc->divide_cnt = 0;
32196 sc->vec_pairing = 0;
32200 sc->cached_can_issue_more = cached_can_issue_more;
32201 sc->last_scheduled_insn = last_scheduled_insn;
32202 sc->load_store_pendulum = load_store_pendulum;
32203 sc->divide_cnt = divide_cnt;
32204 sc->vec_pairing = vec_pairing;
32208 /* Sets the global scheduling context to the one pointed to by _SC. */
32210 rs6000_set_sched_context (void *_sc)
32212 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
32214 gcc_assert (sc != NULL);
32216 cached_can_issue_more = sc->cached_can_issue_more;
32217 last_scheduled_insn = sc->last_scheduled_insn;
32218 load_store_pendulum = sc->load_store_pendulum;
32219 divide_cnt = sc->divide_cnt;
32220 vec_pairing = sc->vec_pairing;
32225 rs6000_free_sched_context (void *_sc)
32227 gcc_assert (_sc != NULL);
32233 rs6000_sched_can_speculate_insn (rtx_insn *insn)
32235 switch (get_attr_type (insn))
32250 /* Length in units of the trampoline for entering a nested function. */
32253 rs6000_trampoline_size (void)
32257 switch (DEFAULT_ABI)
32260 gcc_unreachable ();
32263 ret = (TARGET_32BIT) ? 12 : 24;
32267 gcc_assert (!TARGET_32BIT);
32273 ret = (TARGET_32BIT) ? 40 : 48;
32280 /* Emit RTL insns to initialize the variable parts of a trampoline.
32281 FNADDR is an RTX for the address of the function's pure code.
32282 CXT is an RTX for the static chain value for the function. */
32285 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
32287 int regsize = (TARGET_32BIT) ? 4 : 8;
32288 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
32289 rtx ctx_reg = force_reg (Pmode, cxt);
32290 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
32292 switch (DEFAULT_ABI)
32295 gcc_unreachable ();
32297 /* Under AIX, just build the 3 word function descriptor */
32300 rtx fnmem, fn_reg, toc_reg;
32302 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
32303 error ("you cannot take the address of a nested function if you use "
32304 "the %qs option", "-mno-pointers-to-nested-functions");
32306 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
32307 fn_reg = gen_reg_rtx (Pmode);
32308 toc_reg = gen_reg_rtx (Pmode);
32310 /* Macro to shorten the code expansions below. */
32311 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
32313 m_tramp = replace_equiv_address (m_tramp, addr);
32315 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
32316 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
32317 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
32318 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
32319 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
32325 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
32329 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
32330 LCT_NORMAL, VOIDmode,
32332 GEN_INT (rs6000_trampoline_size ()), SImode,
32340 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
32341 identifier as an argument, so the front end shouldn't look it up. */
32344 rs6000_attribute_takes_identifier_p (const_tree attr_id)
32346 return is_attribute_p ("altivec", attr_id);
32349 /* Handle the "altivec" attribute. The attribute may have
32350 arguments as follows:
32352 __attribute__((altivec(vector__)))
32353 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
32354 __attribute__((altivec(bool__))) (always followed by 'unsigned')
32356 and may appear more than once (e.g., 'vector bool char') in a
32357 given declaration. */
32360 rs6000_handle_altivec_attribute (tree *node,
32361 tree name ATTRIBUTE_UNUSED,
32363 int flags ATTRIBUTE_UNUSED,
32364 bool *no_add_attrs)
32366 tree type = *node, result = NULL_TREE;
32370 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
32371 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
32372 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
32375 while (POINTER_TYPE_P (type)
32376 || TREE_CODE (type) == FUNCTION_TYPE
32377 || TREE_CODE (type) == METHOD_TYPE
32378 || TREE_CODE (type) == ARRAY_TYPE)
32379 type = TREE_TYPE (type);
32381 mode = TYPE_MODE (type);
32383 /* Check for invalid AltiVec type qualifiers. */
32384 if (type == long_double_type_node)
32385 error ("use of %<long double%> in AltiVec types is invalid");
32386 else if (type == boolean_type_node)
32387 error ("use of boolean types in AltiVec types is invalid");
32388 else if (TREE_CODE (type) == COMPLEX_TYPE)
32389 error ("use of %<complex%> in AltiVec types is invalid");
32390 else if (DECIMAL_FLOAT_MODE_P (mode))
32391 error ("use of decimal floating point types in AltiVec types is invalid");
32392 else if (!TARGET_VSX)
32394 if (type == long_unsigned_type_node || type == long_integer_type_node)
32397 error ("use of %<long%> in AltiVec types is invalid for "
32398 "64-bit code without %qs", "-mvsx");
32399 else if (rs6000_warn_altivec_long)
32400 warning (0, "use of %<long%> in AltiVec types is deprecated; "
32403 else if (type == long_long_unsigned_type_node
32404 || type == long_long_integer_type_node)
32405 error ("use of %<long long%> in AltiVec types is invalid without %qs",
32407 else if (type == double_type_node)
32408 error ("use of %<double%> in AltiVec types is invalid without %qs",
32412 switch (altivec_type)
32415 unsigned_p = TYPE_UNSIGNED (type);
32419 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
32422 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
32425 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
32428 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
32431 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
32433 case E_SFmode: result = V4SF_type_node; break;
32434 case E_DFmode: result = V2DF_type_node; break;
32435 /* If the user says 'vector int bool', we may be handed the 'bool'
32436 attribute _before_ the 'vector' attribute, and so select the
32437 proper type in the 'b' case below. */
32438 case E_V4SImode: case E_V8HImode: case E_V16QImode: case E_V4SFmode:
32439 case E_V2DImode: case E_V2DFmode:
32447 case E_DImode: case E_V2DImode: result = bool_V2DI_type_node; break;
32448 case E_SImode: case E_V4SImode: result = bool_V4SI_type_node; break;
32449 case E_HImode: case E_V8HImode: result = bool_V8HI_type_node; break;
32450 case E_QImode: case E_V16QImode: result = bool_V16QI_type_node;
32457 case E_V8HImode: result = pixel_V8HI_type_node;
32463 /* Propagate qualifiers attached to the element type
32464 onto the vector type. */
32465 if (result && result != type && TYPE_QUALS (type))
32466 result = build_qualified_type (result, TYPE_QUALS (type));
32468 *no_add_attrs = true; /* No need to hang on to the attribute. */
32471 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
32476 /* AltiVec defines five built-in scalar types that serve as vector
32477 elements; we must teach the compiler how to mangle them. The 128-bit
32478 floating point mangling is target-specific as well. */
32480 static const char *
32481 rs6000_mangle_type (const_tree type)
32483 type = TYPE_MAIN_VARIANT (type);
32485 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
32486 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
32489 if (type == bool_char_type_node) return "U6__boolc";
32490 if (type == bool_short_type_node) return "U6__bools";
32491 if (type == pixel_type_node) return "u7__pixel";
32492 if (type == bool_int_type_node) return "U6__booli";
32493 if (type == bool_long_long_type_node) return "U6__boolx";
32495 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IBM_P (TYPE_MODE (type)))
32497 if (SCALAR_FLOAT_TYPE_P (type) && FLOAT128_IEEE_P (TYPE_MODE (type)))
32498 return ieee128_mangling_gcc_8_1 ? "U10__float128" : "u9__ieee128";
32500 /* For all other types, use the default mangling. */
32504 /* Handle a "longcall" or "shortcall" attribute; arguments as in
32505 struct attribute_spec.handler. */
32508 rs6000_handle_longcall_attribute (tree *node, tree name,
32509 tree args ATTRIBUTE_UNUSED,
32510 int flags ATTRIBUTE_UNUSED,
32511 bool *no_add_attrs)
32513 if (TREE_CODE (*node) != FUNCTION_TYPE
32514 && TREE_CODE (*node) != FIELD_DECL
32515 && TREE_CODE (*node) != TYPE_DECL)
32517 warning (OPT_Wattributes, "%qE attribute only applies to functions",
32519 *no_add_attrs = true;
32525 /* Set longcall attributes on all functions declared when
32526 rs6000_default_long_calls is true. */
32528 rs6000_set_default_type_attributes (tree type)
32530 if (rs6000_default_long_calls
32531 && (TREE_CODE (type) == FUNCTION_TYPE
32532 || TREE_CODE (type) == METHOD_TYPE))
32533 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
32535 TYPE_ATTRIBUTES (type));
32538 darwin_set_default_type_attributes (type);
32542 /* Return a reference suitable for calling a function with the
32543 longcall attribute. */
32546 rs6000_longcall_ref (rtx call_ref, rtx arg)
32548 /* System V adds '.' to the internal name, so skip them. */
32549 const char *call_name = XSTR (call_ref, 0);
32550 if (*call_name == '.')
32552 while (*call_name == '.')
32555 tree node = get_identifier (call_name);
32556 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
32561 rtx base = const0_rtx;
32563 if (DEFAULT_ABI == ABI_ELFv2)
32565 base = gen_rtx_REG (Pmode, TOC_REGISTER);
32571 base = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
32574 /* Reg must match that used by linker PLT stubs. For ELFv2, r12
32575 may be used by a function global entry point. For SysV4, r11
32576 is used by __glink_PLTresolve lazy resolver entry. */
32577 rtx reg = gen_rtx_REG (Pmode, regno);
32578 rtx hi = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, base, call_ref, arg),
32580 rtx lo = gen_rtx_UNSPEC (Pmode, gen_rtvec (3, reg, call_ref, arg),
32582 emit_insn (gen_rtx_SET (reg, hi));
32583 emit_insn (gen_rtx_SET (reg, lo));
32587 return force_reg (Pmode, call_ref);
32590 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
32591 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
32594 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
32595 struct attribute_spec.handler. */
32597 rs6000_handle_struct_attribute (tree *node, tree name,
32598 tree args ATTRIBUTE_UNUSED,
32599 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
32602 if (DECL_P (*node))
32604 if (TREE_CODE (*node) == TYPE_DECL)
32605 type = &TREE_TYPE (*node);
32610 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
32611 || TREE_CODE (*type) == UNION_TYPE)))
32613 warning (OPT_Wattributes, "%qE attribute ignored", name);
32614 *no_add_attrs = true;
32617 else if ((is_attribute_p ("ms_struct", name)
32618 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
32619 || ((is_attribute_p ("gcc_struct", name)
32620 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
32622 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
32624 *no_add_attrs = true;
32631 rs6000_ms_bitfield_layout_p (const_tree record_type)
32633 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
32634 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
32635 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
32638 #ifdef USING_ELFOS_H
32640 /* A get_unnamed_section callback, used for switching to toc_section. */
32643 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
32645 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32646 && TARGET_MINIMAL_TOC)
32648 if (!toc_initialized)
32650 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32651 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32652 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
32653 fprintf (asm_out_file, "\t.tc ");
32654 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
32655 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32656 fprintf (asm_out_file, "\n");
32658 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32659 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32660 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32661 fprintf (asm_out_file, " = .+32768\n");
32662 toc_initialized = 1;
32665 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32667 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
32669 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
32670 if (!toc_initialized)
32672 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32673 toc_initialized = 1;
32678 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
32679 if (!toc_initialized)
32681 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
32682 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
32683 fprintf (asm_out_file, " = .+32768\n");
32684 toc_initialized = 1;
32689 /* Implement TARGET_ASM_INIT_SECTIONS. */
32692 rs6000_elf_asm_init_sections (void)
32695 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
32698 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
32699 SDATA2_SECTION_ASM_OP);
32702 /* Implement TARGET_SELECT_RTX_SECTION. */
32705 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
32706 unsigned HOST_WIDE_INT align)
32708 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
32709 return toc_section;
32711 return default_elf_select_rtx_section (mode, x, align);
32714 /* For a SYMBOL_REF, set generic flags and then perform some
32715 target-specific processing.
32717 When the AIX ABI is requested on a non-AIX system, replace the
32718 function name with the real name (with a leading .) rather than the
32719 function descriptor name. This saves a lot of overriding code to
32720 read the prefixes. */
32722 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
32724 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
32726 default_encode_section_info (decl, rtl, first);
32729 && TREE_CODE (decl) == FUNCTION_DECL
32731 && DEFAULT_ABI == ABI_AIX)
32733 rtx sym_ref = XEXP (rtl, 0);
32734 size_t len = strlen (XSTR (sym_ref, 0));
32735 char *str = XALLOCAVEC (char, len + 2);
32737 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
32738 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
32743 compare_section_name (const char *section, const char *templ)
32747 len = strlen (templ);
32748 return (strncmp (section, templ, len) == 0
32749 && (section[len] == 0 || section[len] == '.'));
32753 rs6000_elf_in_small_data_p (const_tree decl)
32755 if (rs6000_sdata == SDATA_NONE)
32758 /* We want to merge strings, so we never consider them small data. */
32759 if (TREE_CODE (decl) == STRING_CST)
32762 /* Functions are never in the small data area. */
32763 if (TREE_CODE (decl) == FUNCTION_DECL)
32766 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
32768 const char *section = DECL_SECTION_NAME (decl);
32769 if (compare_section_name (section, ".sdata")
32770 || compare_section_name (section, ".sdata2")
32771 || compare_section_name (section, ".gnu.linkonce.s")
32772 || compare_section_name (section, ".sbss")
32773 || compare_section_name (section, ".sbss2")
32774 || compare_section_name (section, ".gnu.linkonce.sb")
32775 || strcmp (section, ".PPC.EMB.sdata0") == 0
32776 || strcmp (section, ".PPC.EMB.sbss0") == 0)
32781 /* If we are told not to put readonly data in sdata, then don't. */
32782 if (TREE_READONLY (decl) && rs6000_sdata != SDATA_EABI
32783 && !rs6000_readonly_in_sdata)
32786 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
32789 && size <= g_switch_value
32790 /* If it's not public, and we're not going to reference it there,
32791 there's no need to put it in the small data section. */
32792 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
32799 #endif /* USING_ELFOS_H */
32801 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
32804 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
32806 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
32809 /* Do not place thread-local symbols refs in the object blocks. */
32812 rs6000_use_blocks_for_decl_p (const_tree decl)
32814 return !DECL_THREAD_LOCAL_P (decl);
32817 /* Return a REG that occurs in ADDR with coefficient 1.
32818 ADDR can be effectively incremented by incrementing REG.
32820 r0 is special and we must not select it as an address
32821 register by this routine since our caller will try to
32822 increment the returned register via an "la" instruction. */
32825 find_addr_reg (rtx addr)
32827 while (GET_CODE (addr) == PLUS)
32829 if (REG_P (XEXP (addr, 0))
32830 && REGNO (XEXP (addr, 0)) != 0)
32831 addr = XEXP (addr, 0);
32832 else if (REG_P (XEXP (addr, 1))
32833 && REGNO (XEXP (addr, 1)) != 0)
32834 addr = XEXP (addr, 1);
32835 else if (CONSTANT_P (XEXP (addr, 0)))
32836 addr = XEXP (addr, 1);
32837 else if (CONSTANT_P (XEXP (addr, 1)))
32838 addr = XEXP (addr, 0);
32840 gcc_unreachable ();
32842 gcc_assert (REG_P (addr) && REGNO (addr) != 0);
32847 rs6000_fatal_bad_address (rtx op)
32849 fatal_insn ("bad address", op);
32854 typedef struct branch_island_d {
32855 tree function_name;
32861 static vec<branch_island, va_gc> *branch_islands;
32863 /* Remember to generate a branch island for far calls to the given
32867 add_compiler_branch_island (tree label_name, tree function_name,
32870 branch_island bi = {function_name, label_name, line_number};
32871 vec_safe_push (branch_islands, bi);
32874 /* Generate far-jump branch islands for everything recorded in
32875 branch_islands. Invoked immediately after the last instruction of
32876 the epilogue has been emitted; the branch islands must be appended
32877 to, and contiguous with, the function body. Mach-O stubs are
32878 generated in machopic_output_stub(). */
32881 macho_branch_islands (void)
32885 while (!vec_safe_is_empty (branch_islands))
32887 branch_island *bi = &branch_islands->last ();
32888 const char *label = IDENTIFIER_POINTER (bi->label_name);
32889 const char *name = IDENTIFIER_POINTER (bi->function_name);
32890 char name_buf[512];
32891 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
32892 if (name[0] == '*' || name[0] == '&')
32893 strcpy (name_buf, name+1);
32897 strcpy (name_buf+1, name);
32899 strcpy (tmp_buf, "\n");
32900 strcat (tmp_buf, label);
32901 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32902 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32903 dbxout_stabd (N_SLINE, bi->line_number);
32904 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32907 if (TARGET_LINK_STACK)
32910 get_ppc476_thunk_name (name);
32911 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
32912 strcat (tmp_buf, name);
32913 strcat (tmp_buf, "\n");
32914 strcat (tmp_buf, label);
32915 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32919 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
32920 strcat (tmp_buf, label);
32921 strcat (tmp_buf, "_pic\n");
32922 strcat (tmp_buf, label);
32923 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
32926 strcat (tmp_buf, "\taddis r11,r11,ha16(");
32927 strcat (tmp_buf, name_buf);
32928 strcat (tmp_buf, " - ");
32929 strcat (tmp_buf, label);
32930 strcat (tmp_buf, "_pic)\n");
32932 strcat (tmp_buf, "\tmtlr r0\n");
32934 strcat (tmp_buf, "\taddi r12,r11,lo16(");
32935 strcat (tmp_buf, name_buf);
32936 strcat (tmp_buf, " - ");
32937 strcat (tmp_buf, label);
32938 strcat (tmp_buf, "_pic)\n");
32940 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
32944 strcat (tmp_buf, ":\n\tlis r12,hi16(");
32945 strcat (tmp_buf, name_buf);
32946 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
32947 strcat (tmp_buf, name_buf);
32948 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
32950 output_asm_insn (tmp_buf, 0);
32951 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
32952 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
32953 dbxout_stabd (N_SLINE, bi->line_number);
32954 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
32955 branch_islands->pop ();
32959 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
32960 already there or not. */
32963 no_previous_def (tree function_name)
32968 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
32969 if (function_name == bi->function_name)
32974 /* GET_PREV_LABEL gets the label name from the previous definition of
32978 get_prev_label (tree function_name)
32983 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
32984 if (function_name == bi->function_name)
32985 return bi->label_name;
32989 /* Generate PIC and indirect symbol stubs. */
32992 machopic_output_stub (FILE *file, const char *symb, const char *stub)
32994 unsigned int length;
32995 char *symbol_name, *lazy_ptr_name;
32996 char *local_label_0;
32997 static unsigned label = 0;
32999 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
33000 symb = (*targetm.strip_name_encoding) (symb);
33003 length = strlen (symb);
33004 symbol_name = XALLOCAVEC (char, length + 32);
33005 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
33007 lazy_ptr_name = XALLOCAVEC (char, length + 32);
33008 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
33011 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
33013 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
33017 fprintf (file, "\t.align 5\n");
33019 fprintf (file, "%s:\n", stub);
33020 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33023 local_label_0 = XALLOCAVEC (char, 16);
33024 sprintf (local_label_0, "L%u$spb", label);
33026 fprintf (file, "\tmflr r0\n");
33027 if (TARGET_LINK_STACK)
33030 get_ppc476_thunk_name (name);
33031 fprintf (file, "\tbl %s\n", name);
33032 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33036 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
33037 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
33039 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
33040 lazy_ptr_name, local_label_0);
33041 fprintf (file, "\tmtlr r0\n");
33042 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
33043 (TARGET_64BIT ? "ldu" : "lwzu"),
33044 lazy_ptr_name, local_label_0);
33045 fprintf (file, "\tmtctr r12\n");
33046 fprintf (file, "\tbctr\n");
33050 fprintf (file, "\t.align 4\n");
33052 fprintf (file, "%s:\n", stub);
33053 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33055 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
33056 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
33057 (TARGET_64BIT ? "ldu" : "lwzu"),
33059 fprintf (file, "\tmtctr r12\n");
33060 fprintf (file, "\tbctr\n");
33063 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
33064 fprintf (file, "%s:\n", lazy_ptr_name);
33065 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
33066 fprintf (file, "%sdyld_stub_binding_helper\n",
33067 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
33070 /* Legitimize PIC addresses. If the address is already
33071 position-independent, we return ORIG. Newly generated
33072 position-independent addresses go into a reg. This is REG if non
33073 zero, otherwise we allocate register(s) as necessary. */
33075 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
33078 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
33083 if (reg == NULL && !reload_completed)
33084 reg = gen_reg_rtx (Pmode);
33086 if (GET_CODE (orig) == CONST)
33090 if (GET_CODE (XEXP (orig, 0)) == PLUS
33091 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
33094 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
33096 /* Use a different reg for the intermediate value, as
33097 it will be marked UNCHANGING. */
33098 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
33099 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
33102 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
33105 if (CONST_INT_P (offset))
33107 if (SMALL_INT (offset))
33108 return plus_constant (Pmode, base, INTVAL (offset));
33109 else if (!reload_completed)
33110 offset = force_reg (Pmode, offset);
33113 rtx mem = force_const_mem (Pmode, orig);
33114 return machopic_legitimize_pic_address (mem, Pmode, reg);
33117 return gen_rtx_PLUS (Pmode, base, offset);
33120 /* Fall back on generic machopic code. */
33121 return machopic_legitimize_pic_address (orig, mode, reg);
33124 /* Output a .machine directive for the Darwin assembler, and call
33125 the generic start_file routine. */
33128 rs6000_darwin_file_start (void)
33130 static const struct
33134 HOST_WIDE_INT if_set;
33136 { "ppc64", "ppc64", MASK_64BIT },
33137 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
33138 { "power4", "ppc970", 0 },
33139 { "G5", "ppc970", 0 },
33140 { "7450", "ppc7450", 0 },
33141 { "7400", "ppc7400", MASK_ALTIVEC },
33142 { "G4", "ppc7400", 0 },
33143 { "750", "ppc750", 0 },
33144 { "740", "ppc750", 0 },
33145 { "G3", "ppc750", 0 },
33146 { "604e", "ppc604e", 0 },
33147 { "604", "ppc604", 0 },
33148 { "603e", "ppc603", 0 },
33149 { "603", "ppc603", 0 },
33150 { "601", "ppc601", 0 },
33151 { NULL, "ppc", 0 } };
33152 const char *cpu_id = "";
33155 rs6000_file_start ();
33156 darwin_file_start ();
33158 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
33160 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
33161 cpu_id = rs6000_default_cpu;
33163 if (global_options_set.x_rs6000_cpu_index)
33164 cpu_id = processor_target_table[rs6000_cpu_index].name;
33166 /* Look through the mapping array. Pick the first name that either
33167 matches the argument, has a bit set in IF_SET that is also set
33168 in the target flags, or has a NULL name. */
33171 while (mapping[i].arg != NULL
33172 && strcmp (mapping[i].arg, cpu_id) != 0
33173 && (mapping[i].if_set & rs6000_isa_flags) == 0)
33176 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
33179 #endif /* TARGET_MACHO */
33183 rs6000_elf_reloc_rw_mask (void)
33187 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
33193 /* Record an element in the table of global constructors. SYMBOL is
33194 a SYMBOL_REF of the function to be called; PRIORITY is a number
33195 between 0 and MAX_INIT_PRIORITY.
33197 This differs from default_named_section_asm_out_constructor in
33198 that we have special handling for -mrelocatable. */
33200 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
33202 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
33204 const char *section = ".ctors";
33207 if (priority != DEFAULT_INIT_PRIORITY)
33209 sprintf (buf, ".ctors.%.5u",
33210 /* Invert the numbering so the linker puts us in the proper
33211 order; constructors are run from right to left, and the
33212 linker sorts in increasing order. */
33213 MAX_INIT_PRIORITY - priority);
33217 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33218 assemble_align (POINTER_SIZE);
33220 if (DEFAULT_ABI == ABI_V4
33221 && (TARGET_RELOCATABLE || flag_pic > 1))
33223 fputs ("\t.long (", asm_out_file);
33224 output_addr_const (asm_out_file, symbol);
33225 fputs (")@fixup\n", asm_out_file);
33228 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33231 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
33233 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
33235 const char *section = ".dtors";
33238 if (priority != DEFAULT_INIT_PRIORITY)
33240 sprintf (buf, ".dtors.%.5u",
33241 /* Invert the numbering so the linker puts us in the proper
33242 order; constructors are run from right to left, and the
33243 linker sorts in increasing order. */
33244 MAX_INIT_PRIORITY - priority);
33248 switch_to_section (get_section (section, SECTION_WRITE, NULL));
33249 assemble_align (POINTER_SIZE);
33251 if (DEFAULT_ABI == ABI_V4
33252 && (TARGET_RELOCATABLE || flag_pic > 1))
33254 fputs ("\t.long (", asm_out_file);
33255 output_addr_const (asm_out_file, symbol);
33256 fputs (")@fixup\n", asm_out_file);
33259 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
33263 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
33265 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
33267 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
33268 ASM_OUTPUT_LABEL (file, name);
33269 fputs (DOUBLE_INT_ASM_OP, file);
33270 rs6000_output_function_entry (file, name);
33271 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
33274 fputs ("\t.size\t", file);
33275 assemble_name (file, name);
33276 fputs (",24\n\t.type\t.", file);
33277 assemble_name (file, name);
33278 fputs (",@function\n", file);
33279 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
33281 fputs ("\t.globl\t.", file);
33282 assemble_name (file, name);
33287 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33288 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33289 rs6000_output_function_entry (file, name);
33290 fputs (":\n", file);
33295 if (DEFAULT_ABI == ABI_V4
33296 && (TARGET_RELOCATABLE || flag_pic > 1)
33297 && !TARGET_SECURE_PLT
33298 && (!constant_pool_empty_p () || crtl->profile)
33299 && (uses_toc = uses_TOC ()))
33304 switch_to_other_text_partition ();
33305 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33307 fprintf (file, "\t.long ");
33308 assemble_name (file, toc_label_name);
33311 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33312 assemble_name (file, buf);
33315 switch_to_other_text_partition ();
33318 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
33319 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
33321 if (TARGET_CMODEL == CMODEL_LARGE && rs6000_global_entry_point_needed_p ())
33325 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
33327 fprintf (file, "\t.quad .TOC.-");
33328 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
33329 assemble_name (file, buf);
33333 if (DEFAULT_ABI == ABI_AIX)
33335 const char *desc_name, *orig_name;
33337 orig_name = (*targetm.strip_name_encoding) (name);
33338 desc_name = orig_name;
33339 while (*desc_name == '.')
33342 if (TREE_PUBLIC (decl))
33343 fprintf (file, "\t.globl %s\n", desc_name);
33345 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
33346 fprintf (file, "%s:\n", desc_name);
33347 fprintf (file, "\t.long %s\n", orig_name);
33348 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
33349 fputs ("\t.long 0\n", file);
33350 fprintf (file, "\t.previous\n");
33352 ASM_OUTPUT_LABEL (file, name);
33355 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
33357 rs6000_elf_file_end (void)
33359 #ifdef HAVE_AS_GNU_ATTRIBUTE
33360 /* ??? The value emitted depends on options active at file end.
33361 Assume anyone using #pragma or attributes that might change
33362 options knows what they are doing. */
33363 if ((TARGET_64BIT || DEFAULT_ABI == ABI_V4)
33364 && rs6000_passes_float)
33368 if (TARGET_HARD_FLOAT)
33372 if (rs6000_passes_long_double)
33374 if (!TARGET_LONG_DOUBLE_128)
33376 else if (TARGET_IEEEQUAD)
33381 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", fp);
33383 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
33385 if (rs6000_passes_vector)
33386 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
33387 (TARGET_ALTIVEC_ABI ? 2 : 1));
33388 if (rs6000_returns_struct)
33389 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
33390 aix_struct_return ? 2 : 1);
33393 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
33394 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
33395 file_end_indicate_exec_stack ();
33398 if (flag_split_stack)
33399 file_end_indicate_split_stack ();
33403 /* We have expanded a CPU builtin, so we need to emit a reference to
33404 the special symbol that LIBC uses to declare it supports the
33405 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
33406 switch_to_section (data_section);
33407 fprintf (asm_out_file, "\t.align %u\n", TARGET_32BIT ? 2 : 3);
33408 fprintf (asm_out_file, "\t%s %s\n",
33409 TARGET_32BIT ? ".long" : ".quad", tcb_verification_symbol);
33416 #ifndef HAVE_XCOFF_DWARF_EXTRAS
33417 #define HAVE_XCOFF_DWARF_EXTRAS 0
33420 static enum unwind_info_type
33421 rs6000_xcoff_debug_unwind_info (void)
33427 rs6000_xcoff_asm_output_anchor (rtx symbol)
33431 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
33432 SYMBOL_REF_BLOCK_OFFSET (symbol));
33433 fprintf (asm_out_file, "%s", SET_ASM_OP);
33434 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
33435 fprintf (asm_out_file, ",");
33436 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
33437 fprintf (asm_out_file, "\n");
33441 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
33443 fputs (GLOBAL_ASM_OP, stream);
33444 RS6000_OUTPUT_BASENAME (stream, name);
33445 putc ('\n', stream);
33448 /* A get_unnamed_decl callback, used for read-only sections. PTR
33449 points to the section string variable. */
33452 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
33454 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
33455 *(const char *const *) directive,
33456 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33459 /* Likewise for read-write sections. */
33462 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
33464 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
33465 *(const char *const *) directive,
33466 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33470 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
33472 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
33473 *(const char *const *) directive,
33474 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
33477 /* A get_unnamed_section callback, used for switching to toc_section. */
33480 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
33482 if (TARGET_MINIMAL_TOC)
33484 /* toc_section is always selected at least once from
33485 rs6000_xcoff_file_start, so this is guaranteed to
33486 always be defined once and only once in each file. */
33487 if (!toc_initialized)
33489 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
33490 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
33491 toc_initialized = 1;
33493 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
33494 (TARGET_32BIT ? "" : ",3"));
33497 fputs ("\t.toc\n", asm_out_file);
33500 /* Implement TARGET_ASM_INIT_SECTIONS. */
33503 rs6000_xcoff_asm_init_sections (void)
33505 read_only_data_section
33506 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33507 &xcoff_read_only_section_name);
33509 private_data_section
33510 = get_unnamed_section (SECTION_WRITE,
33511 rs6000_xcoff_output_readwrite_section_asm_op,
33512 &xcoff_private_data_section_name);
33514 read_only_private_data_section
33515 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
33516 &xcoff_private_rodata_section_name);
33519 = get_unnamed_section (SECTION_TLS,
33520 rs6000_xcoff_output_tls_section_asm_op,
33521 &xcoff_tls_data_section_name);
33523 tls_private_data_section
33524 = get_unnamed_section (SECTION_TLS,
33525 rs6000_xcoff_output_tls_section_asm_op,
33526 &xcoff_private_data_section_name);
33529 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
33531 readonly_data_section = read_only_data_section;
33535 rs6000_xcoff_reloc_rw_mask (void)
33541 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
33542 tree decl ATTRIBUTE_UNUSED)
33545 static const char * const suffix[5] = { "PR", "RO", "RW", "TL", "XO" };
33547 if (flags & SECTION_EXCLUDE)
33549 else if (flags & SECTION_DEBUG)
33551 fprintf (asm_out_file, "\t.dwsect %s\n", name);
33554 else if (flags & SECTION_CODE)
33556 else if (flags & SECTION_TLS)
33558 else if (flags & SECTION_WRITE)
33563 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
33564 (flags & SECTION_CODE) ? "." : "",
33565 name, suffix[smclass], flags & SECTION_ENTSIZE);
33568 #define IN_NAMED_SECTION(DECL) \
33569 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
33570 && DECL_SECTION_NAME (DECL) != NULL)
33573 rs6000_xcoff_select_section (tree decl, int reloc,
33574 unsigned HOST_WIDE_INT align)
33576 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
33578 if (align > BIGGEST_ALIGNMENT)
33580 resolve_unique_section (decl, reloc, true);
33581 if (IN_NAMED_SECTION (decl))
33582 return get_named_section (decl, NULL, reloc);
33585 if (decl_readonly_section (decl, reloc))
33587 if (TREE_PUBLIC (decl))
33588 return read_only_data_section;
33590 return read_only_private_data_section;
33595 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
33597 if (TREE_PUBLIC (decl))
33598 return tls_data_section;
33599 else if (bss_initializer_p (decl))
33601 /* Convert to COMMON to emit in BSS. */
33602 DECL_COMMON (decl) = 1;
33603 return tls_comm_section;
33606 return tls_private_data_section;
33610 if (TREE_PUBLIC (decl))
33611 return data_section;
33613 return private_data_section;
33618 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
33622 /* Use select_section for private data and uninitialized data with
33623 alignment <= BIGGEST_ALIGNMENT. */
33624 if (!TREE_PUBLIC (decl)
33625 || DECL_COMMON (decl)
33626 || (DECL_INITIAL (decl) == NULL_TREE
33627 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
33628 || DECL_INITIAL (decl) == error_mark_node
33629 || (flag_zero_initialized_in_bss
33630 && initializer_zerop (DECL_INITIAL (decl))))
33633 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
33634 name = (*targetm.strip_name_encoding) (name);
33635 set_decl_section_name (decl, name);
33638 /* Select section for constant in constant pool.
33640 On RS/6000, all constants are in the private read-only data area.
33641 However, if this is being placed in the TOC it must be output as a
33645 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
33646 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
33648 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
33649 return toc_section;
33651 return read_only_private_data_section;
33654 /* Remove any trailing [DS] or the like from the symbol name. */
33656 static const char *
33657 rs6000_xcoff_strip_name_encoding (const char *name)
33662 len = strlen (name);
33663 if (name[len - 1] == ']')
33664 return ggc_alloc_string (name, len - 4);
33669 /* Section attributes. AIX is always PIC. */
33671 static unsigned int
33672 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
33674 unsigned int align;
33675 unsigned int flags = default_section_type_flags (decl, name, reloc);
33677 /* Align to at least UNIT size. */
33678 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
33679 align = MIN_UNITS_PER_WORD;
33681 /* Increase alignment of large objects if not already stricter. */
33682 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
33683 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
33684 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
33686 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
33689 /* Output at beginning of assembler file.
33691 Initialize the section names for the RS/6000 at this point.
33693 Specify filename, including full path, to assembler.
33695 We want to go into the TOC section so at least one .toc will be emitted.
33696 Also, in order to output proper .bs/.es pairs, we need at least one static
33697 [RW] section emitted.
33699 Finally, declare mcount when profiling to make the assembler happy. */
33702 rs6000_xcoff_file_start (void)
33704 rs6000_gen_section_name (&xcoff_bss_section_name,
33705 main_input_filename, ".bss_");
33706 rs6000_gen_section_name (&xcoff_private_data_section_name,
33707 main_input_filename, ".rw_");
33708 rs6000_gen_section_name (&xcoff_private_rodata_section_name,
33709 main_input_filename, ".rop_");
33710 rs6000_gen_section_name (&xcoff_read_only_section_name,
33711 main_input_filename, ".ro_");
33712 rs6000_gen_section_name (&xcoff_tls_data_section_name,
33713 main_input_filename, ".tls_");
33714 rs6000_gen_section_name (&xcoff_tbss_section_name,
33715 main_input_filename, ".tbss_[UL]");
33717 fputs ("\t.file\t", asm_out_file);
33718 output_quoted_string (asm_out_file, main_input_filename);
33719 fputc ('\n', asm_out_file);
33720 if (write_symbols != NO_DEBUG)
33721 switch_to_section (private_data_section);
33722 switch_to_section (toc_section);
33723 switch_to_section (text_section);
33725 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
33726 rs6000_file_start ();
33729 /* Output at end of assembler file.
33730 On the RS/6000, referencing data should automatically pull in text. */
33733 rs6000_xcoff_file_end (void)
33735 switch_to_section (text_section);
33736 fputs ("_section_.text:\n", asm_out_file);
33737 switch_to_section (data_section);
33738 fputs (TARGET_32BIT
33739 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
33743 struct declare_alias_data
33746 bool function_descriptor;
33749 /* Declare alias N. A helper function for for_node_and_aliases. */
33752 rs6000_declare_alias (struct symtab_node *n, void *d)
33754 struct declare_alias_data *data = (struct declare_alias_data *)d;
33755 /* Main symbol is output specially, because varasm machinery does part of
33756 the job for us - we do not need to declare .globl/lglobs and such. */
33757 if (!n->alias || n->weakref)
33760 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
33763 /* Prevent assemble_alias from trying to use .set pseudo operation
33764 that does not behave as expected by the middle-end. */
33765 TREE_ASM_WRITTEN (n->decl) = true;
33767 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
33768 char *buffer = (char *) alloca (strlen (name) + 2);
33770 int dollar_inside = 0;
33772 strcpy (buffer, name);
33773 p = strchr (buffer, '$');
33777 p = strchr (p + 1, '$');
33779 if (TREE_PUBLIC (n->decl))
33781 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
33783 if (dollar_inside) {
33784 if (data->function_descriptor)
33785 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33786 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33788 if (data->function_descriptor)
33790 fputs ("\t.globl .", data->file);
33791 RS6000_OUTPUT_BASENAME (data->file, buffer);
33792 putc ('\n', data->file);
33794 fputs ("\t.globl ", data->file);
33795 RS6000_OUTPUT_BASENAME (data->file, buffer);
33796 putc ('\n', data->file);
33798 #ifdef ASM_WEAKEN_DECL
33799 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
33800 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
33807 if (data->function_descriptor)
33808 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
33809 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
33811 if (data->function_descriptor)
33813 fputs ("\t.lglobl .", data->file);
33814 RS6000_OUTPUT_BASENAME (data->file, buffer);
33815 putc ('\n', data->file);
33817 fputs ("\t.lglobl ", data->file);
33818 RS6000_OUTPUT_BASENAME (data->file, buffer);
33819 putc ('\n', data->file);
33821 if (data->function_descriptor)
33822 fputs (".", data->file);
33823 RS6000_OUTPUT_BASENAME (data->file, buffer);
33824 fputs (":\n", data->file);
33829 #ifdef HAVE_GAS_HIDDEN
33830 /* Helper function to calculate visibility of a DECL
33831 and return the value as a const string. */
33833 static const char *
33834 rs6000_xcoff_visibility (tree decl)
33836 static const char * const visibility_types[] = {
33837 "", ",protected", ",hidden", ",internal"
33840 enum symbol_visibility vis = DECL_VISIBILITY (decl);
33841 return visibility_types[vis];
33846 /* This macro produces the initial definition of a function name.
33847 On the RS/6000, we need to place an extra '.' in the function name and
33848 output the function descriptor.
33849 Dollar signs are converted to underscores.
33851 The csect for the function will have already been created when
33852 text_section was selected. We do have to go back to that csect, however.
33854 The third and fourth parameters to the .function pseudo-op (16 and 044)
33855 are placeholders which no longer have any use.
33857 Because AIX assembler's .set command has unexpected semantics, we output
33858 all aliases as alternative labels in front of the definition. */
33861 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
33863 char *buffer = (char *) alloca (strlen (name) + 1);
33865 int dollar_inside = 0;
33866 struct declare_alias_data data = {file, false};
33868 strcpy (buffer, name);
33869 p = strchr (buffer, '$');
33873 p = strchr (p + 1, '$');
33875 if (TREE_PUBLIC (decl))
33877 if (!RS6000_WEAK || !DECL_WEAK (decl))
33879 if (dollar_inside) {
33880 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33881 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33883 fputs ("\t.globl .", file);
33884 RS6000_OUTPUT_BASENAME (file, buffer);
33885 #ifdef HAVE_GAS_HIDDEN
33886 fputs (rs6000_xcoff_visibility (decl), file);
33893 if (dollar_inside) {
33894 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
33895 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
33897 fputs ("\t.lglobl .", file);
33898 RS6000_OUTPUT_BASENAME (file, buffer);
33901 fputs ("\t.csect ", file);
33902 RS6000_OUTPUT_BASENAME (file, buffer);
33903 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
33904 RS6000_OUTPUT_BASENAME (file, buffer);
33905 fputs (":\n", file);
33906 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33908 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
33909 RS6000_OUTPUT_BASENAME (file, buffer);
33910 fputs (", TOC[tc0], 0\n", file);
33912 switch_to_section (function_section (decl));
33914 RS6000_OUTPUT_BASENAME (file, buffer);
33915 fputs (":\n", file);
33916 data.function_descriptor = true;
33917 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33919 if (!DECL_IGNORED_P (decl))
33921 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
33922 xcoffout_declare_function (file, decl, buffer);
33923 else if (write_symbols == DWARF2_DEBUG)
33925 name = (*targetm.strip_name_encoding) (name);
33926 fprintf (file, "\t.function .%s,.%s,2,0\n", name, name);
33933 /* Output assembly language to globalize a symbol from a DECL,
33934 possibly with visibility. */
33937 rs6000_xcoff_asm_globalize_decl_name (FILE *stream, tree decl)
33939 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
33940 fputs (GLOBAL_ASM_OP, stream);
33941 RS6000_OUTPUT_BASENAME (stream, name);
33942 #ifdef HAVE_GAS_HIDDEN
33943 fputs (rs6000_xcoff_visibility (decl), stream);
33945 putc ('\n', stream);
33948 /* Output assembly language to define a symbol as COMMON from a DECL,
33949 possibly with visibility. */
33952 rs6000_xcoff_asm_output_aligned_decl_common (FILE *stream,
33953 tree decl ATTRIBUTE_UNUSED,
33955 unsigned HOST_WIDE_INT size,
33956 unsigned HOST_WIDE_INT align)
33958 unsigned HOST_WIDE_INT align2 = 2;
33961 align2 = floor_log2 (align / BITS_PER_UNIT);
33965 fputs (COMMON_ASM_OP, stream);
33966 RS6000_OUTPUT_BASENAME (stream, name);
33969 "," HOST_WIDE_INT_PRINT_UNSIGNED "," HOST_WIDE_INT_PRINT_UNSIGNED,
33972 #ifdef HAVE_GAS_HIDDEN
33974 fputs (rs6000_xcoff_visibility (decl), stream);
33976 putc ('\n', stream);
33979 /* This macro produces the initial definition of a object (variable) name.
33980 Because AIX assembler's .set command has unexpected semantics, we output
33981 all aliases as alternative labels in front of the definition. */
33984 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
33986 struct declare_alias_data data = {file, false};
33987 RS6000_OUTPUT_BASENAME (file, name);
33988 fputs (":\n", file);
33989 symtab_node::get_create (decl)->call_for_symbol_and_aliases (rs6000_declare_alias,
33993 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
33996 rs6000_asm_output_dwarf_pcrel (FILE *file, int size, const char *label)
33998 fputs (integer_asm_op (size, FALSE), file);
33999 assemble_name (file, label);
34000 fputs ("-$", file);
34003 /* Output a symbol offset relative to the dbase for the current object.
34004 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
34007 __gcc_unwind_dbase is embedded in all executables/libraries through
34008 libgcc/config/rs6000/crtdbase.S. */
34011 rs6000_asm_output_dwarf_datarel (FILE *file, int size, const char *label)
34013 fputs (integer_asm_op (size, FALSE), file);
34014 assemble_name (file, label);
34015 fputs("-__gcc_unwind_dbase", file);
34020 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
34024 const char *symname;
34026 default_encode_section_info (decl, rtl, first);
34028 /* Careful not to prod global register variables. */
34031 symbol = XEXP (rtl, 0);
34032 if (!SYMBOL_REF_P (symbol))
34035 flags = SYMBOL_REF_FLAGS (symbol);
34037 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
34038 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
34040 SYMBOL_REF_FLAGS (symbol) = flags;
34042 /* Append mapping class to extern decls. */
34043 symname = XSTR (symbol, 0);
34044 if (decl /* sync condition with assemble_external () */
34045 && DECL_P (decl) && DECL_EXTERNAL (decl) && TREE_PUBLIC (decl)
34046 && ((TREE_CODE (decl) == VAR_DECL && !DECL_THREAD_LOCAL_P (decl))
34047 || TREE_CODE (decl) == FUNCTION_DECL)
34048 && symname[strlen (symname) - 1] != ']')
34050 char *newname = (char *) alloca (strlen (symname) + 5);
34051 strcpy (newname, symname);
34052 strcat (newname, (TREE_CODE (decl) == FUNCTION_DECL
34053 ? "[DS]" : "[UA]"));
34054 XSTR (symbol, 0) = ggc_strdup (newname);
34057 #endif /* HAVE_AS_TLS */
34058 #endif /* TARGET_XCOFF */
34061 rs6000_asm_weaken_decl (FILE *stream, tree decl,
34062 const char *name, const char *val)
34064 fputs ("\t.weak\t", stream);
34065 RS6000_OUTPUT_BASENAME (stream, name);
34066 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34067 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34070 fputs ("[DS]", stream);
34071 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34073 fputs (rs6000_xcoff_visibility (decl), stream);
34075 fputs ("\n\t.weak\t.", stream);
34076 RS6000_OUTPUT_BASENAME (stream, name);
34078 #if TARGET_XCOFF && HAVE_GAS_HIDDEN
34080 fputs (rs6000_xcoff_visibility (decl), stream);
34082 fputc ('\n', stream);
34085 #ifdef ASM_OUTPUT_DEF
34086 ASM_OUTPUT_DEF (stream, name, val);
34088 if (decl && TREE_CODE (decl) == FUNCTION_DECL
34089 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS)
34091 fputs ("\t.set\t.", stream);
34092 RS6000_OUTPUT_BASENAME (stream, name);
34093 fputs (",.", stream);
34094 RS6000_OUTPUT_BASENAME (stream, val);
34095 fputc ('\n', stream);
34101 /* Return true if INSN should not be copied. */
34104 rs6000_cannot_copy_insn_p (rtx_insn *insn)
34106 return recog_memoized (insn) >= 0
34107 && get_attr_cannot_copy (insn);
34110 /* Compute a (partial) cost for rtx X. Return true if the complete
34111 cost has been computed, and false if subexpressions should be
34112 scanned. In either case, *TOTAL contains the cost result. */
34115 rs6000_rtx_costs (rtx x, machine_mode mode, int outer_code,
34116 int opno ATTRIBUTE_UNUSED, int *total, bool speed)
34118 int code = GET_CODE (x);
34122 /* On the RS/6000, if it is valid in the insn, it is free. */
34124 if (((outer_code == SET
34125 || outer_code == PLUS
34126 || outer_code == MINUS)
34127 && (satisfies_constraint_I (x)
34128 || satisfies_constraint_L (x)))
34129 || (outer_code == AND
34130 && (satisfies_constraint_K (x)
34132 ? satisfies_constraint_L (x)
34133 : satisfies_constraint_J (x))))
34134 || ((outer_code == IOR || outer_code == XOR)
34135 && (satisfies_constraint_K (x)
34137 ? satisfies_constraint_L (x)
34138 : satisfies_constraint_J (x))))
34139 || outer_code == ASHIFT
34140 || outer_code == ASHIFTRT
34141 || outer_code == LSHIFTRT
34142 || outer_code == ROTATE
34143 || outer_code == ROTATERT
34144 || outer_code == ZERO_EXTRACT
34145 || (outer_code == MULT
34146 && satisfies_constraint_I (x))
34147 || ((outer_code == DIV || outer_code == UDIV
34148 || outer_code == MOD || outer_code == UMOD)
34149 && exact_log2 (INTVAL (x)) >= 0)
34150 || (outer_code == COMPARE
34151 && (satisfies_constraint_I (x)
34152 || satisfies_constraint_K (x)))
34153 || ((outer_code == EQ || outer_code == NE)
34154 && (satisfies_constraint_I (x)
34155 || satisfies_constraint_K (x)
34157 ? satisfies_constraint_L (x)
34158 : satisfies_constraint_J (x))))
34159 || (outer_code == GTU
34160 && satisfies_constraint_I (x))
34161 || (outer_code == LTU
34162 && satisfies_constraint_P (x)))
34167 else if ((outer_code == PLUS
34168 && reg_or_add_cint_operand (x, VOIDmode))
34169 || (outer_code == MINUS
34170 && reg_or_sub_cint_operand (x, VOIDmode))
34171 || ((outer_code == SET
34172 || outer_code == IOR
34173 || outer_code == XOR)
34175 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
34177 *total = COSTS_N_INSNS (1);
34183 case CONST_WIDE_INT:
34187 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34191 /* When optimizing for size, MEM should be slightly more expensive
34192 than generating address, e.g., (plus (reg) (const)).
34193 L1 cache latency is about two instructions. */
34194 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
34195 if (rs6000_slow_unaligned_access (mode, MEM_ALIGN (x)))
34196 *total += COSTS_N_INSNS (100);
34205 if (FLOAT_MODE_P (mode))
34206 *total = rs6000_cost->fp;
34208 *total = COSTS_N_INSNS (1);
34212 if (CONST_INT_P (XEXP (x, 1))
34213 && satisfies_constraint_I (XEXP (x, 1)))
34215 if (INTVAL (XEXP (x, 1)) >= -256
34216 && INTVAL (XEXP (x, 1)) <= 255)
34217 *total = rs6000_cost->mulsi_const9;
34219 *total = rs6000_cost->mulsi_const;
34221 else if (mode == SFmode)
34222 *total = rs6000_cost->fp;
34223 else if (FLOAT_MODE_P (mode))
34224 *total = rs6000_cost->dmul;
34225 else if (mode == DImode)
34226 *total = rs6000_cost->muldi;
34228 *total = rs6000_cost->mulsi;
34232 if (mode == SFmode)
34233 *total = rs6000_cost->fp;
34235 *total = rs6000_cost->dmul;
34240 if (FLOAT_MODE_P (mode))
34242 *total = mode == DFmode ? rs6000_cost->ddiv
34243 : rs6000_cost->sdiv;
34250 if (CONST_INT_P (XEXP (x, 1))
34251 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
34253 if (code == DIV || code == MOD)
34255 *total = COSTS_N_INSNS (2);
34258 *total = COSTS_N_INSNS (1);
34262 if (GET_MODE (XEXP (x, 1)) == DImode)
34263 *total = rs6000_cost->divdi;
34265 *total = rs6000_cost->divsi;
34267 /* Add in shift and subtract for MOD unless we have a mod instruction. */
34268 if (!TARGET_MODULO && (code == MOD || code == UMOD))
34269 *total += COSTS_N_INSNS (2);
34273 *total = COSTS_N_INSNS (TARGET_CTZ ? 1 : 4);
34277 *total = COSTS_N_INSNS (4);
34281 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
34285 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
34289 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
34292 *total = COSTS_N_INSNS (1);
34296 if (CONST_INT_P (XEXP (x, 1)))
34298 rtx left = XEXP (x, 0);
34299 rtx_code left_code = GET_CODE (left);
34301 /* rotate-and-mask: 1 insn. */
34302 if ((left_code == ROTATE
34303 || left_code == ASHIFT
34304 || left_code == LSHIFTRT)
34305 && rs6000_is_valid_shift_mask (XEXP (x, 1), left, mode))
34307 *total = rtx_cost (XEXP (left, 0), mode, left_code, 0, speed);
34308 if (!CONST_INT_P (XEXP (left, 1)))
34309 *total += rtx_cost (XEXP (left, 1), SImode, left_code, 1, speed);
34310 *total += COSTS_N_INSNS (1);
34314 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
34315 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
34316 if (rs6000_is_valid_and_mask (XEXP (x, 1), mode)
34317 || (val & 0xffff) == val
34318 || (val & 0xffff0000) == val
34319 || ((val & 0xffff) == 0 && mode == SImode))
34321 *total = rtx_cost (left, mode, AND, 0, speed);
34322 *total += COSTS_N_INSNS (1);
34327 if (rs6000_is_valid_2insn_and (XEXP (x, 1), mode))
34329 *total = rtx_cost (left, mode, AND, 0, speed);
34330 *total += COSTS_N_INSNS (2);
34335 *total = COSTS_N_INSNS (1);
34340 *total = COSTS_N_INSNS (1);
34346 *total = COSTS_N_INSNS (1);
34350 /* The EXTSWSLI instruction is a combined instruction. Don't count both
34351 the sign extend and shift separately within the insn. */
34352 if (TARGET_EXTSWSLI && mode == DImode
34353 && GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
34354 && GET_MODE (XEXP (XEXP (x, 0), 0)) == SImode)
34365 /* Handle mul_highpart. */
34366 if (outer_code == TRUNCATE
34367 && GET_CODE (XEXP (x, 0)) == MULT)
34369 if (mode == DImode)
34370 *total = rs6000_cost->muldi;
34372 *total = rs6000_cost->mulsi;
34375 else if (outer_code == AND)
34378 *total = COSTS_N_INSNS (1);
34383 if (MEM_P (XEXP (x, 0)))
34386 *total = COSTS_N_INSNS (1);
34392 if (!FLOAT_MODE_P (mode))
34394 *total = COSTS_N_INSNS (1);
34400 case UNSIGNED_FLOAT:
34403 case FLOAT_TRUNCATE:
34404 *total = rs6000_cost->fp;
34408 if (mode == DFmode)
34409 *total = rs6000_cost->sfdf_convert;
34411 *total = rs6000_cost->fp;
34415 switch (XINT (x, 1))
34418 *total = rs6000_cost->fp;
34430 *total = COSTS_N_INSNS (1);
34433 else if (FLOAT_MODE_P (mode) && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT)
34435 *total = rs6000_cost->fp;
34444 /* Carry bit requires mode == Pmode.
34445 NEG or PLUS already counted so only add one. */
34447 && (outer_code == NEG || outer_code == PLUS))
34449 *total = COSTS_N_INSNS (1);
34457 if (outer_code == SET)
34459 if (XEXP (x, 1) == const0_rtx)
34461 *total = COSTS_N_INSNS (2);
34466 *total = COSTS_N_INSNS (3);
34471 if (outer_code == COMPARE)
34485 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
34488 rs6000_debug_rtx_costs (rtx x, machine_mode mode, int outer_code,
34489 int opno, int *total, bool speed)
34491 bool ret = rs6000_rtx_costs (x, mode, outer_code, opno, total, speed);
34494 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
34495 "opno = %d, total = %d, speed = %s, x:\n",
34496 ret ? "complete" : "scan inner",
34497 GET_MODE_NAME (mode),
34498 GET_RTX_NAME (outer_code),
34501 speed ? "true" : "false");
34509 rs6000_insn_cost (rtx_insn *insn, bool speed)
34511 if (recog_memoized (insn) < 0)
34515 return get_attr_length (insn);
34517 int cost = get_attr_cost (insn);
34521 int n = get_attr_length (insn) / 4;
34522 enum attr_type type = get_attr_type (insn);
34529 cost = COSTS_N_INSNS (n + 1);
34533 switch (get_attr_size (insn))
34536 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const9;
34539 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi_const;
34542 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->mulsi;
34545 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->muldi;
34548 gcc_unreachable ();
34552 switch (get_attr_size (insn))
34555 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divsi;
34558 cost = COSTS_N_INSNS (n - 1) + rs6000_cost->divdi;
34561 gcc_unreachable ();
34566 cost = n * rs6000_cost->fp;
34569 cost = n * rs6000_cost->dmul;
34572 cost = n * rs6000_cost->sdiv;
34575 cost = n * rs6000_cost->ddiv;
34582 cost = COSTS_N_INSNS (n + 2);
34586 cost = COSTS_N_INSNS (n);
34592 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
34595 rs6000_debug_address_cost (rtx x, machine_mode mode,
34596 addr_space_t as, bool speed)
34598 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
34600 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
34601 ret, speed ? "true" : "false");
34608 /* A C expression returning the cost of moving data from a register of class
34609 CLASS1 to one of CLASS2. */
34612 rs6000_register_move_cost (machine_mode mode,
34613 reg_class_t from, reg_class_t to)
34616 reg_class_t rclass;
34618 if (TARGET_DEBUG_COST)
34621 /* If we have VSX, we can easily move between FPR or Altivec registers,
34622 otherwise we can only easily move within classes.
34623 Do this first so we give best-case answers for union classes
34624 containing both gprs and vsx regs. */
34625 HARD_REG_SET to_vsx, from_vsx;
34626 COPY_HARD_REG_SET (to_vsx, reg_class_contents[to]);
34627 AND_HARD_REG_SET (to_vsx, reg_class_contents[VSX_REGS]);
34628 COPY_HARD_REG_SET (from_vsx, reg_class_contents[from]);
34629 AND_HARD_REG_SET (from_vsx, reg_class_contents[VSX_REGS]);
34630 if (!hard_reg_set_empty_p (to_vsx)
34631 && !hard_reg_set_empty_p (from_vsx)
34633 || hard_reg_set_intersect_p (to_vsx, from_vsx)))
34635 int reg = FIRST_FPR_REGNO;
34637 || (TEST_HARD_REG_BIT (to_vsx, FIRST_ALTIVEC_REGNO)
34638 && TEST_HARD_REG_BIT (from_vsx, FIRST_ALTIVEC_REGNO)))
34639 reg = FIRST_ALTIVEC_REGNO;
34640 ret = 2 * hard_regno_nregs (reg, mode);
34643 /* Moves from/to GENERAL_REGS. */
34644 else if ((rclass = from, reg_classes_intersect_p (to, GENERAL_REGS))
34645 || (rclass = to, reg_classes_intersect_p (from, GENERAL_REGS)))
34647 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
34649 if (TARGET_DIRECT_MOVE)
34651 /* Keep the cost for direct moves above that for within
34652 a register class even if the actual processor cost is
34653 comparable. We do this because a direct move insn
34654 can't be a nop, whereas with ideal register
34655 allocation a move within the same class might turn
34656 out to be a nop. */
34657 if (rs6000_tune == PROCESSOR_POWER9)
34658 ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34660 ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34661 /* SFmode requires a conversion when moving between gprs
34663 if (mode == SFmode)
34667 ret = (rs6000_memory_move_cost (mode, rclass, false)
34668 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
34671 /* It's more expensive to move CR_REGS than CR0_REGS because of the
34673 else if (rclass == CR_REGS)
34676 /* For those processors that have slow LR/CTR moves, make them more
34677 expensive than memory in order to bias spills to memory .*/
34678 else if ((rs6000_tune == PROCESSOR_POWER6
34679 || rs6000_tune == PROCESSOR_POWER7
34680 || rs6000_tune == PROCESSOR_POWER8
34681 || rs6000_tune == PROCESSOR_POWER9)
34682 && reg_class_subset_p (rclass, SPECIAL_REGS))
34683 ret = 6 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34686 /* A move will cost one instruction per GPR moved. */
34687 ret = 2 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
34690 /* Everything else has to go through GENERAL_REGS. */
34692 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
34693 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
34695 if (TARGET_DEBUG_COST)
34697 if (dbg_cost_ctrl == 1)
34699 "rs6000_register_move_cost: ret=%d, mode=%s, from=%s, to=%s\n",
34700 ret, GET_MODE_NAME (mode), reg_class_names[from],
34701 reg_class_names[to]);
34708 /* A C expressions returning the cost of moving data of MODE from a register to
34712 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
34713 bool in ATTRIBUTE_UNUSED)
34717 if (TARGET_DEBUG_COST)
34720 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
34721 ret = 4 * hard_regno_nregs (0, mode);
34722 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
34723 || reg_classes_intersect_p (rclass, VSX_REGS)))
34724 ret = 4 * hard_regno_nregs (32, mode);
34725 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
34726 ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode);
34728 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
34730 if (TARGET_DEBUG_COST)
34732 if (dbg_cost_ctrl == 1)
34734 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
34735 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
34742 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
34744 The register allocator chooses GEN_OR_VSX_REGS for the allocno
34745 class if GENERAL_REGS and VSX_REGS cost is lower than the memory
34746 cost. This happens a lot when TARGET_DIRECT_MOVE makes the register
34747 move cost between GENERAL_REGS and VSX_REGS low.
34749 It might seem reasonable to use a union class. After all, if usage
34750 of vsr is low and gpr high, it might make sense to spill gpr to vsr
34751 rather than memory. However, in cases where register pressure of
34752 both is high, like the cactus_adm spec test, allowing
34753 GEN_OR_VSX_REGS as the allocno class results in bad decisions in
34754 the first scheduling pass. This is partly due to an allocno of
34755 GEN_OR_VSX_REGS wrongly contributing to the GENERAL_REGS pressure
34756 class, which gives too high a pressure for GENERAL_REGS and too low
34757 for VSX_REGS. So, force a choice of the subclass here.
34759 The best class is also the union if GENERAL_REGS and VSX_REGS have
34760 the same cost. In that case we do use GEN_OR_VSX_REGS as the
34761 allocno class, since trying to narrow down the class by regno mode
34762 is prone to error. For example, SImode is allowed in VSX regs and
34763 in some cases (eg. gcc.target/powerpc/p9-xxbr-3.c do_bswap32_vect)
34764 it would be wrong to choose an allocno of GENERAL_REGS based on
34768 rs6000_ira_change_pseudo_allocno_class (int regno ATTRIBUTE_UNUSED,
34769 reg_class_t allocno_class,
34770 reg_class_t best_class)
34772 switch (allocno_class)
34774 case GEN_OR_VSX_REGS:
34775 /* best_class must be a subset of allocno_class. */
34776 gcc_checking_assert (best_class == GEN_OR_VSX_REGS
34777 || best_class == GEN_OR_FLOAT_REGS
34778 || best_class == VSX_REGS
34779 || best_class == ALTIVEC_REGS
34780 || best_class == FLOAT_REGS
34781 || best_class == GENERAL_REGS
34782 || best_class == BASE_REGS);
34783 /* Use best_class but choose wider classes when copying from the
34784 wider class to best_class is cheap. This mimics IRA choice
34785 of allocno class. */
34786 if (best_class == BASE_REGS)
34787 return GENERAL_REGS;
34789 && (best_class == FLOAT_REGS || best_class == ALTIVEC_REGS))
34797 return allocno_class;
34800 /* Returns a code for a target-specific builtin that implements
34801 reciprocal of the function, or NULL_TREE if not available. */
34804 rs6000_builtin_reciprocal (tree fndecl)
34806 switch (DECL_FUNCTION_CODE (fndecl))
34808 case VSX_BUILTIN_XVSQRTDP:
34809 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
34812 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
34814 case VSX_BUILTIN_XVSQRTSP:
34815 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
34818 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
34825 /* Load up a constant. If the mode is a vector mode, splat the value across
34826 all of the vector elements. */
34829 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
34833 if (mode == SFmode || mode == DFmode)
34835 rtx d = const_double_from_real_value (dconst, mode);
34836 reg = force_reg (mode, d);
34838 else if (mode == V4SFmode)
34840 rtx d = const_double_from_real_value (dconst, SFmode);
34841 rtvec v = gen_rtvec (4, d, d, d, d);
34842 reg = gen_reg_rtx (mode);
34843 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34845 else if (mode == V2DFmode)
34847 rtx d = const_double_from_real_value (dconst, DFmode);
34848 rtvec v = gen_rtvec (2, d, d);
34849 reg = gen_reg_rtx (mode);
34850 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
34853 gcc_unreachable ();
34858 /* Generate an FMA instruction. */
34861 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
34863 machine_mode mode = GET_MODE (target);
34866 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
34867 gcc_assert (dst != NULL);
34870 emit_move_insn (target, dst);
34873 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
34876 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
34878 machine_mode mode = GET_MODE (dst);
34881 /* This is a tad more complicated, since the fnma_optab is for
34882 a different expression: fma(-m1, m2, a), which is the same
34883 thing except in the case of signed zeros.
34885 Fortunately we know that if FMA is supported that FNMSUB is
34886 also supported in the ISA. Just expand it directly. */
34888 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
34890 r = gen_rtx_NEG (mode, a);
34891 r = gen_rtx_FMA (mode, m1, m2, r);
34892 r = gen_rtx_NEG (mode, r);
34893 emit_insn (gen_rtx_SET (dst, r));
34896 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
34897 add a reg_note saying that this was a division. Support both scalar and
34898 vector divide. Assumes no trapping math and finite arguments. */
34901 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
34903 machine_mode mode = GET_MODE (dst);
34904 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
34907 /* Low precision estimates guarantee 5 bits of accuracy. High
34908 precision estimates guarantee 14 bits of accuracy. SFmode
34909 requires 23 bits of accuracy. DFmode requires 52 bits of
34910 accuracy. Each pass at least doubles the accuracy, leading
34911 to the following. */
34912 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34913 if (mode == DFmode || mode == V2DFmode)
34916 enum insn_code code = optab_handler (smul_optab, mode);
34917 insn_gen_fn gen_mul = GEN_FCN (code);
34919 gcc_assert (code != CODE_FOR_nothing);
34921 one = rs6000_load_constant_and_splat (mode, dconst1);
34923 /* x0 = 1./d estimate */
34924 x0 = gen_reg_rtx (mode);
34925 emit_insn (gen_rtx_SET (x0, gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
34928 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
34931 /* e0 = 1. - d * x0 */
34932 e0 = gen_reg_rtx (mode);
34933 rs6000_emit_nmsub (e0, d, x0, one);
34935 /* x1 = x0 + e0 * x0 */
34936 x1 = gen_reg_rtx (mode);
34937 rs6000_emit_madd (x1, e0, x0, x0);
34939 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
34940 ++i, xprev = xnext, eprev = enext) {
34942 /* enext = eprev * eprev */
34943 enext = gen_reg_rtx (mode);
34944 emit_insn (gen_mul (enext, eprev, eprev));
34946 /* xnext = xprev + enext * xprev */
34947 xnext = gen_reg_rtx (mode);
34948 rs6000_emit_madd (xnext, enext, xprev, xprev);
34954 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
34956 /* u = n * xprev */
34957 u = gen_reg_rtx (mode);
34958 emit_insn (gen_mul (u, n, xprev));
34960 /* v = n - (d * u) */
34961 v = gen_reg_rtx (mode);
34962 rs6000_emit_nmsub (v, d, u, n);
34964 /* dst = (v * xprev) + u */
34965 rs6000_emit_madd (dst, v, xprev, u);
34968 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
34971 /* Goldschmidt's Algorithm for single/double-precision floating point
34972 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
34975 rs6000_emit_swsqrt (rtx dst, rtx src, bool recip)
34977 machine_mode mode = GET_MODE (src);
34978 rtx e = gen_reg_rtx (mode);
34979 rtx g = gen_reg_rtx (mode);
34980 rtx h = gen_reg_rtx (mode);
34982 /* Low precision estimates guarantee 5 bits of accuracy. High
34983 precision estimates guarantee 14 bits of accuracy. SFmode
34984 requires 23 bits of accuracy. DFmode requires 52 bits of
34985 accuracy. Each pass at least doubles the accuracy, leading
34986 to the following. */
34987 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
34988 if (mode == DFmode || mode == V2DFmode)
34993 enum insn_code code = optab_handler (smul_optab, mode);
34994 insn_gen_fn gen_mul = GEN_FCN (code);
34996 gcc_assert (code != CODE_FOR_nothing);
34998 mhalf = rs6000_load_constant_and_splat (mode, dconsthalf);
35000 /* e = rsqrt estimate */
35001 emit_insn (gen_rtx_SET (e, gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
35004 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
35007 rtx zero = force_reg (mode, CONST0_RTX (mode));
35009 if (mode == SFmode)
35011 rtx target = emit_conditional_move (e, GT, src, zero, mode,
35014 emit_move_insn (e, target);
35018 rtx cond = gen_rtx_GT (VOIDmode, e, zero);
35019 rs6000_emit_vector_cond_expr (e, e, zero, cond, src, zero);
35023 /* g = sqrt estimate. */
35024 emit_insn (gen_mul (g, e, src));
35025 /* h = 1/(2*sqrt) estimate. */
35026 emit_insn (gen_mul (h, e, mhalf));
35032 rtx t = gen_reg_rtx (mode);
35033 rs6000_emit_nmsub (t, g, h, mhalf);
35034 /* Apply correction directly to 1/rsqrt estimate. */
35035 rs6000_emit_madd (dst, e, t, e);
35039 for (i = 0; i < passes; i++)
35041 rtx t1 = gen_reg_rtx (mode);
35042 rtx g1 = gen_reg_rtx (mode);
35043 rtx h1 = gen_reg_rtx (mode);
35045 rs6000_emit_nmsub (t1, g, h, mhalf);
35046 rs6000_emit_madd (g1, g, t1, g);
35047 rs6000_emit_madd (h1, h, t1, h);
35052 /* Multiply by 2 for 1/rsqrt. */
35053 emit_insn (gen_add3_insn (dst, h, h));
35058 rtx t = gen_reg_rtx (mode);
35059 rs6000_emit_nmsub (t, g, h, mhalf);
35060 rs6000_emit_madd (dst, g, t, g);
35066 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
35067 (Power7) targets. DST is the target, and SRC is the argument operand. */
35070 rs6000_emit_popcount (rtx dst, rtx src)
35072 machine_mode mode = GET_MODE (dst);
35075 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
35076 if (TARGET_POPCNTD)
35078 if (mode == SImode)
35079 emit_insn (gen_popcntdsi2 (dst, src));
35081 emit_insn (gen_popcntddi2 (dst, src));
35085 tmp1 = gen_reg_rtx (mode);
35087 if (mode == SImode)
35089 emit_insn (gen_popcntbsi2 (tmp1, src));
35090 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
35092 tmp2 = force_reg (SImode, tmp2);
35093 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
35097 emit_insn (gen_popcntbdi2 (tmp1, src));
35098 tmp2 = expand_mult (DImode, tmp1,
35099 GEN_INT ((HOST_WIDE_INT)
35100 0x01010101 << 32 | 0x01010101),
35102 tmp2 = force_reg (DImode, tmp2);
35103 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
35108 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
35109 target, and SRC is the argument operand. */
35112 rs6000_emit_parity (rtx dst, rtx src)
35114 machine_mode mode = GET_MODE (dst);
35117 tmp = gen_reg_rtx (mode);
35119 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
35122 if (mode == SImode)
35124 emit_insn (gen_popcntbsi2 (tmp, src));
35125 emit_insn (gen_paritysi2_cmpb (dst, tmp));
35129 emit_insn (gen_popcntbdi2 (tmp, src));
35130 emit_insn (gen_paritydi2_cmpb (dst, tmp));
35135 if (mode == SImode)
35137 /* Is mult+shift >= shift+xor+shift+xor? */
35138 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
35140 rtx tmp1, tmp2, tmp3, tmp4;
35142 tmp1 = gen_reg_rtx (SImode);
35143 emit_insn (gen_popcntbsi2 (tmp1, src));
35145 tmp2 = gen_reg_rtx (SImode);
35146 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
35147 tmp3 = gen_reg_rtx (SImode);
35148 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
35150 tmp4 = gen_reg_rtx (SImode);
35151 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
35152 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
35155 rs6000_emit_popcount (tmp, src);
35156 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
35160 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
35161 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
35163 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
35165 tmp1 = gen_reg_rtx (DImode);
35166 emit_insn (gen_popcntbdi2 (tmp1, src));
35168 tmp2 = gen_reg_rtx (DImode);
35169 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
35170 tmp3 = gen_reg_rtx (DImode);
35171 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
35173 tmp4 = gen_reg_rtx (DImode);
35174 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
35175 tmp5 = gen_reg_rtx (DImode);
35176 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
35178 tmp6 = gen_reg_rtx (DImode);
35179 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
35180 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
35183 rs6000_emit_popcount (tmp, src);
35184 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
35188 /* Expand an Altivec constant permutation for little endian mode.
35189 OP0 and OP1 are the input vectors and TARGET is the output vector.
35190 SEL specifies the constant permutation vector.
35192 There are two issues: First, the two input operands must be
35193 swapped so that together they form a double-wide array in LE
35194 order. Second, the vperm instruction has surprising behavior
35195 in LE mode: it interprets the elements of the source vectors
35196 in BE mode ("left to right") and interprets the elements of
35197 the destination vector in LE mode ("right to left"). To
35198 correct for this, we must subtract each element of the permute
35199 control vector from 31.
35201 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
35202 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
35203 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
35204 serve as the permute control vector. Then, in BE mode,
35208 places the desired result in vr9. However, in LE mode the
35209 vector contents will be
35211 vr10 = 00000003 00000002 00000001 00000000
35212 vr11 = 00000007 00000006 00000005 00000004
35214 The result of the vperm using the same permute control vector is
35216 vr9 = 05000000 07000000 01000000 03000000
35218 That is, the leftmost 4 bytes of vr10 are interpreted as the
35219 source for the rightmost 4 bytes of vr9, and so on.
35221 If we change the permute control vector to
35223 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
35231 vr9 = 00000006 00000004 00000002 00000000. */
35234 altivec_expand_vec_perm_const_le (rtx target, rtx op0, rtx op1,
35235 const vec_perm_indices &sel)
35239 rtx constv, unspec;
35241 /* Unpack and adjust the constant selector. */
35242 for (i = 0; i < 16; ++i)
35244 unsigned int elt = 31 - (sel[i] & 31);
35245 perm[i] = GEN_INT (elt);
35248 /* Expand to a permute, swapping the inputs and using the
35249 adjusted selector. */
35251 op0 = force_reg (V16QImode, op0);
35253 op1 = force_reg (V16QImode, op1);
35255 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
35256 constv = force_reg (V16QImode, constv);
35257 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
35259 if (!REG_P (target))
35261 rtx tmp = gen_reg_rtx (V16QImode);
35262 emit_move_insn (tmp, unspec);
35266 emit_move_insn (target, unspec);
35269 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
35270 permute control vector. But here it's not a constant, so we must
35271 generate a vector NAND or NOR to do the adjustment. */
35274 altivec_expand_vec_perm_le (rtx operands[4])
35276 rtx notx, iorx, unspec;
35277 rtx target = operands[0];
35278 rtx op0 = operands[1];
35279 rtx op1 = operands[2];
35280 rtx sel = operands[3];
35282 rtx norreg = gen_reg_rtx (V16QImode);
35283 machine_mode mode = GET_MODE (target);
35285 /* Get everything in regs so the pattern matches. */
35287 op0 = force_reg (mode, op0);
35289 op1 = force_reg (mode, op1);
35291 sel = force_reg (V16QImode, sel);
35292 if (!REG_P (target))
35293 tmp = gen_reg_rtx (mode);
35295 if (TARGET_P9_VECTOR)
35297 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, sel),
35302 /* Invert the selector with a VNAND if available, else a VNOR.
35303 The VNAND is preferred for future fusion opportunities. */
35304 notx = gen_rtx_NOT (V16QImode, sel);
35305 iorx = (TARGET_P8_VECTOR
35306 ? gen_rtx_IOR (V16QImode, notx, notx)
35307 : gen_rtx_AND (V16QImode, notx, notx));
35308 emit_insn (gen_rtx_SET (norreg, iorx));
35310 /* Permute with operands reversed and adjusted selector. */
35311 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
35315 /* Copy into target, possibly by way of a register. */
35316 if (!REG_P (target))
35318 emit_move_insn (tmp, unspec);
35322 emit_move_insn (target, unspec);
35325 /* Expand an Altivec constant permutation. Return true if we match
35326 an efficient implementation; false to fall back to VPERM.
35328 OP0 and OP1 are the input vectors and TARGET is the output vector.
35329 SEL specifies the constant permutation vector. */
35332 altivec_expand_vec_perm_const (rtx target, rtx op0, rtx op1,
35333 const vec_perm_indices &sel)
35335 struct altivec_perm_insn {
35336 HOST_WIDE_INT mask;
35337 enum insn_code impl;
35338 unsigned char perm[16];
35340 static const struct altivec_perm_insn patterns[] = {
35341 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
35342 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
35343 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
35344 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
35345 { OPTION_MASK_ALTIVEC,
35346 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
35347 : CODE_FOR_altivec_vmrglb_direct),
35348 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
35349 { OPTION_MASK_ALTIVEC,
35350 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
35351 : CODE_FOR_altivec_vmrglh_direct),
35352 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
35353 { OPTION_MASK_ALTIVEC,
35354 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
35355 : CODE_FOR_altivec_vmrglw_direct),
35356 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
35357 { OPTION_MASK_ALTIVEC,
35358 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
35359 : CODE_FOR_altivec_vmrghb_direct),
35360 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
35361 { OPTION_MASK_ALTIVEC,
35362 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
35363 : CODE_FOR_altivec_vmrghh_direct),
35364 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
35365 { OPTION_MASK_ALTIVEC,
35366 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
35367 : CODE_FOR_altivec_vmrghw_direct),
35368 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
35369 { OPTION_MASK_P8_VECTOR,
35370 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgew_v4sf_direct
35371 : CODE_FOR_p8_vmrgow_v4sf_direct),
35372 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
35373 { OPTION_MASK_P8_VECTOR,
35374 (BYTES_BIG_ENDIAN ? CODE_FOR_p8_vmrgow_v4sf_direct
35375 : CODE_FOR_p8_vmrgew_v4sf_direct),
35376 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
35379 unsigned int i, j, elt, which;
35380 unsigned char perm[16];
35384 /* Unpack the constant selector. */
35385 for (i = which = 0; i < 16; ++i)
35388 which |= (elt < 16 ? 1 : 2);
35392 /* Simplify the constant selector based on operands. */
35396 gcc_unreachable ();
35400 if (!rtx_equal_p (op0, op1))
35405 for (i = 0; i < 16; ++i)
35417 /* Look for splat patterns. */
35422 for (i = 0; i < 16; ++i)
35423 if (perm[i] != elt)
35427 if (!BYTES_BIG_ENDIAN)
35429 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
35435 for (i = 0; i < 16; i += 2)
35436 if (perm[i] != elt || perm[i + 1] != elt + 1)
35440 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
35441 x = gen_reg_rtx (V8HImode);
35442 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
35444 emit_move_insn (target, gen_lowpart (V16QImode, x));
35451 for (i = 0; i < 16; i += 4)
35453 || perm[i + 1] != elt + 1
35454 || perm[i + 2] != elt + 2
35455 || perm[i + 3] != elt + 3)
35459 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
35460 x = gen_reg_rtx (V4SImode);
35461 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
35463 emit_move_insn (target, gen_lowpart (V16QImode, x));
35469 /* Look for merge and pack patterns. */
35470 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
35474 if ((patterns[j].mask & rs6000_isa_flags) == 0)
35477 elt = patterns[j].perm[0];
35478 if (perm[0] == elt)
35480 else if (perm[0] == elt + 16)
35484 for (i = 1; i < 16; ++i)
35486 elt = patterns[j].perm[i];
35488 elt = (elt >= 16 ? elt - 16 : elt + 16);
35489 else if (one_vec && elt >= 16)
35491 if (perm[i] != elt)
35496 enum insn_code icode = patterns[j].impl;
35497 machine_mode omode = insn_data[icode].operand[0].mode;
35498 machine_mode imode = insn_data[icode].operand[1].mode;
35500 /* For little-endian, don't use vpkuwum and vpkuhum if the
35501 underlying vector type is not V4SI and V8HI, respectively.
35502 For example, using vpkuwum with a V8HI picks up the even
35503 halfwords (BE numbering) when the even halfwords (LE
35504 numbering) are what we need. */
35505 if (!BYTES_BIG_ENDIAN
35506 && icode == CODE_FOR_altivec_vpkuwum_direct
35508 && GET_MODE (op0) != V4SImode)
35510 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
35512 if (!BYTES_BIG_ENDIAN
35513 && icode == CODE_FOR_altivec_vpkuhum_direct
35515 && GET_MODE (op0) != V8HImode)
35517 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
35520 /* For little-endian, the two input operands must be swapped
35521 (or swapped back) to ensure proper right-to-left numbering
35523 if (swapped ^ !BYTES_BIG_ENDIAN)
35524 std::swap (op0, op1);
35525 if (imode != V16QImode)
35527 op0 = gen_lowpart (imode, op0);
35528 op1 = gen_lowpart (imode, op1);
35530 if (omode == V16QImode)
35533 x = gen_reg_rtx (omode);
35534 emit_insn (GEN_FCN (icode) (x, op0, op1));
35535 if (omode != V16QImode)
35536 emit_move_insn (target, gen_lowpart (V16QImode, x));
35541 if (!BYTES_BIG_ENDIAN)
35543 altivec_expand_vec_perm_const_le (target, op0, op1, sel);
35550 /* Expand a VSX Permute Doubleword constant permutation.
35551 Return true if we match an efficient implementation. */
35554 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
35555 unsigned char perm0, unsigned char perm1)
35559 /* If both selectors come from the same operand, fold to single op. */
35560 if ((perm0 & 2) == (perm1 & 2))
35567 /* If both operands are equal, fold to simpler permutation. */
35568 if (rtx_equal_p (op0, op1))
35571 perm1 = (perm1 & 1) + 2;
35573 /* If the first selector comes from the second operand, swap. */
35574 else if (perm0 & 2)
35580 std::swap (op0, op1);
35582 /* If the second selector does not come from the second operand, fail. */
35583 else if ((perm1 & 2) == 0)
35587 if (target != NULL)
35589 machine_mode vmode, dmode;
35592 vmode = GET_MODE (target);
35593 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
35594 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4).require ();
35595 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
35596 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
35597 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
35598 emit_insn (gen_rtx_SET (target, x));
35603 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
35606 rs6000_vectorize_vec_perm_const (machine_mode vmode, rtx target, rtx op0,
35607 rtx op1, const vec_perm_indices &sel)
35609 bool testing_p = !target;
35611 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
35612 if (TARGET_ALTIVEC && testing_p)
35615 /* Check for ps_merge* or xxpermdi insns. */
35616 if ((vmode == V2DFmode || vmode == V2DImode) && VECTOR_MEM_VSX_P (vmode))
35620 op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
35621 op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
35623 if (rs6000_expand_vec_perm_const_1 (target, op0, op1, sel[0], sel[1]))
35627 if (TARGET_ALTIVEC)
35629 /* Force the target-independent code to lower to V16QImode. */
35630 if (vmode != V16QImode)
35632 if (altivec_expand_vec_perm_const (target, op0, op1, sel))
35639 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave.
35640 OP0 and OP1 are the input vectors and TARGET is the output vector.
35641 PERM specifies the constant permutation vector. */
35644 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
35645 machine_mode vmode, const vec_perm_builder &perm)
35647 rtx x = expand_vec_perm_const (vmode, op0, op1, perm, BLKmode, target);
35649 emit_move_insn (target, x);
35652 /* Expand an extract even operation. */
35655 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
35657 machine_mode vmode = GET_MODE (target);
35658 unsigned i, nelt = GET_MODE_NUNITS (vmode);
35659 vec_perm_builder perm (nelt, nelt, 1);
35661 for (i = 0; i < nelt; i++)
35662 perm.quick_push (i * 2);
35664 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35667 /* Expand a vector interleave operation. */
35670 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
35672 machine_mode vmode = GET_MODE (target);
35673 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
35674 vec_perm_builder perm (nelt, nelt, 1);
35676 high = (highp ? 0 : nelt / 2);
35677 for (i = 0; i < nelt / 2; i++)
35679 perm.quick_push (i + high);
35680 perm.quick_push (i + nelt + high);
35683 rs6000_do_expand_vec_perm (target, op0, op1, vmode, perm);
35686 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
35688 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
35690 HOST_WIDE_INT hwi_scale (scale);
35691 REAL_VALUE_TYPE r_pow;
35692 rtvec v = rtvec_alloc (2);
35694 rtx scale_vec = gen_reg_rtx (V2DFmode);
35695 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
35696 elt = const_double_from_real_value (r_pow, DFmode);
35697 RTVEC_ELT (v, 0) = elt;
35698 RTVEC_ELT (v, 1) = elt;
35699 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
35700 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
35703 /* Return an RTX representing where to find the function value of a
35704 function returning MODE. */
35706 rs6000_complex_function_value (machine_mode mode)
35708 unsigned int regno;
35710 machine_mode inner = GET_MODE_INNER (mode);
35711 unsigned int inner_bytes = GET_MODE_UNIT_SIZE (mode);
35713 if (TARGET_FLOAT128_TYPE
35715 || (mode == TCmode && TARGET_IEEEQUAD)))
35716 regno = ALTIVEC_ARG_RETURN;
35718 else if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35719 regno = FP_ARG_RETURN;
35723 regno = GP_ARG_RETURN;
35725 /* 32-bit is OK since it'll go in r3/r4. */
35726 if (TARGET_32BIT && inner_bytes >= 4)
35727 return gen_rtx_REG (mode, regno);
35730 if (inner_bytes >= 8)
35731 return gen_rtx_REG (mode, regno);
35733 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
35735 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
35736 GEN_INT (inner_bytes));
35737 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
35740 /* Return an rtx describing a return value of MODE as a PARALLEL
35741 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
35742 stride REG_STRIDE. */
35745 rs6000_parallel_return (machine_mode mode,
35746 int n_elts, machine_mode elt_mode,
35747 unsigned int regno, unsigned int reg_stride)
35749 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
35752 for (i = 0; i < n_elts; i++)
35754 rtx r = gen_rtx_REG (elt_mode, regno);
35755 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
35756 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
35757 regno += reg_stride;
35763 /* Target hook for TARGET_FUNCTION_VALUE.
35765 An integer value is in r3 and a floating-point value is in fp1,
35766 unless -msoft-float. */
35769 rs6000_function_value (const_tree valtype,
35770 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
35771 bool outgoing ATTRIBUTE_UNUSED)
35774 unsigned int regno;
35775 machine_mode elt_mode;
35778 /* Special handling for structs in darwin64. */
35780 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
35782 CUMULATIVE_ARGS valcum;
35786 valcum.fregno = FP_ARG_MIN_REG;
35787 valcum.vregno = ALTIVEC_ARG_MIN_REG;
35788 /* Do a trial code generation as if this were going to be passed as
35789 an argument; if any part goes in memory, we return NULL. */
35790 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
35793 /* Otherwise fall through to standard ABI rules. */
35796 mode = TYPE_MODE (valtype);
35798 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
35799 if (rs6000_discover_homogeneous_aggregate (mode, valtype, &elt_mode, &n_elts))
35801 int first_reg, n_regs;
35803 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode))
35805 /* _Decimal128 must use even/odd register pairs. */
35806 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35807 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
35811 first_reg = ALTIVEC_ARG_RETURN;
35815 return rs6000_parallel_return (mode, n_elts, elt_mode, first_reg, n_regs);
35818 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
35819 if (TARGET_32BIT && TARGET_POWERPC64)
35828 int count = GET_MODE_SIZE (mode) / 4;
35829 return rs6000_parallel_return (mode, count, SImode, GP_ARG_RETURN, 1);
35832 if ((INTEGRAL_TYPE_P (valtype)
35833 && GET_MODE_BITSIZE (mode) < (TARGET_32BIT ? 32 : 64))
35834 || POINTER_TYPE_P (valtype))
35835 mode = TARGET_32BIT ? SImode : DImode;
35837 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35838 /* _Decimal128 must use an even/odd register pair. */
35839 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35840 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT
35841 && !FLOAT128_VECTOR_P (mode))
35842 regno = FP_ARG_RETURN;
35843 else if (TREE_CODE (valtype) == COMPLEX_TYPE
35844 && targetm.calls.split_complex_arg)
35845 return rs6000_complex_function_value (mode);
35846 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35847 return register is used in both cases, and we won't see V2DImode/V2DFmode
35848 for pure altivec, combine the two cases. */
35849 else if ((TREE_CODE (valtype) == VECTOR_TYPE || FLOAT128_VECTOR_P (mode))
35850 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
35851 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
35852 regno = ALTIVEC_ARG_RETURN;
35854 regno = GP_ARG_RETURN;
35856 return gen_rtx_REG (mode, regno);
35859 /* Define how to find the value returned by a library function
35860 assuming the value has mode MODE. */
35862 rs6000_libcall_value (machine_mode mode)
35864 unsigned int regno;
35866 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
35867 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
35868 return rs6000_parallel_return (mode, 2, SImode, GP_ARG_RETURN, 1);
35870 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT)
35871 /* _Decimal128 must use an even/odd register pair. */
35872 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
35873 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode) && TARGET_HARD_FLOAT)
35874 regno = FP_ARG_RETURN;
35875 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
35876 return register is used in both cases, and we won't see V2DImode/V2DFmode
35877 for pure altivec, combine the two cases. */
35878 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
35879 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
35880 regno = ALTIVEC_ARG_RETURN;
35881 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
35882 return rs6000_complex_function_value (mode);
35884 regno = GP_ARG_RETURN;
35886 return gen_rtx_REG (mode, regno);
35889 /* Compute register pressure classes. We implement the target hook to avoid
35890 IRA picking something like GEN_OR_FLOAT_REGS as a pressure class, which can
35891 lead to incorrect estimates of number of available registers and therefor
35892 increased register pressure/spill. */
35894 rs6000_compute_pressure_classes (enum reg_class *pressure_classes)
35899 pressure_classes[n++] = GENERAL_REGS;
35901 pressure_classes[n++] = VSX_REGS;
35904 if (TARGET_ALTIVEC)
35905 pressure_classes[n++] = ALTIVEC_REGS;
35906 if (TARGET_HARD_FLOAT)
35907 pressure_classes[n++] = FLOAT_REGS;
35909 pressure_classes[n++] = CR_REGS;
35910 pressure_classes[n++] = SPECIAL_REGS;
35915 /* Given FROM and TO register numbers, say whether this elimination is allowed.
35916 Frame pointer elimination is automatically handled.
35918 For the RS/6000, if frame pointer elimination is being done, we would like
35919 to convert ap into fp, not sp.
35921 We need r30 if -mminimal-toc was specified, and there are constant pool
35925 rs6000_can_eliminate (const int from, const int to)
35927 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
35928 ? ! frame_pointer_needed
35929 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
35930 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC
35931 || constant_pool_empty_p ()
35935 /* Define the offset between two registers, FROM to be eliminated and its
35936 replacement TO, at the start of a routine. */
35938 rs6000_initial_elimination_offset (int from, int to)
35940 rs6000_stack_t *info = rs6000_stack_info ();
35941 HOST_WIDE_INT offset;
35943 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35944 offset = info->push_p ? 0 : -info->total_size;
35945 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35947 offset = info->push_p ? 0 : -info->total_size;
35948 if (FRAME_GROWS_DOWNWARD)
35949 offset += info->fixed_size + info->vars_size + info->parm_size;
35951 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35952 offset = FRAME_GROWS_DOWNWARD
35953 ? info->fixed_size + info->vars_size + info->parm_size
35955 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
35956 offset = info->total_size;
35957 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
35958 offset = info->push_p ? info->total_size : 0;
35959 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
35962 gcc_unreachable ();
35967 /* Fill in sizes of registers used by unwinder. */
35970 rs6000_init_dwarf_reg_sizes_extra (tree address)
35972 if (TARGET_MACHO && ! TARGET_ALTIVEC)
35975 machine_mode mode = TYPE_MODE (char_type_node);
35976 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
35977 rtx mem = gen_rtx_MEM (BLKmode, addr);
35978 rtx value = gen_int_mode (16, mode);
35980 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
35981 The unwinder still needs to know the size of Altivec registers. */
35983 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
35985 int column = DWARF_REG_TO_UNWIND_COLUMN
35986 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
35987 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
35989 emit_move_insn (adjust_address (mem, mode, offset), value);
35994 /* Map internal gcc register numbers to debug format register numbers.
35995 FORMAT specifies the type of debug register number to use:
35996 0 -- debug information, except for frame-related sections
35997 1 -- DWARF .debug_frame section
35998 2 -- DWARF .eh_frame section */
36001 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
36003 /* On some platforms, we use the standard DWARF register
36004 numbering for .debug_info and .debug_frame. */
36005 if ((format == 0 && write_symbols == DWARF2_DEBUG) || format == 1)
36007 #ifdef RS6000_USE_DWARF_NUMBERING
36010 if (FP_REGNO_P (regno))
36011 return regno - FIRST_FPR_REGNO + 32;
36012 if (ALTIVEC_REGNO_P (regno))
36013 return regno - FIRST_ALTIVEC_REGNO + 1124;
36014 if (regno == LR_REGNO)
36016 if (regno == CTR_REGNO)
36018 if (regno == CA_REGNO)
36019 return 101; /* XER */
36020 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
36021 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
36022 The actual code emitted saves the whole of CR, so we map CR2_REGNO
36023 to the DWARF reg for CR. */
36024 if (format == 1 && regno == CR2_REGNO)
36026 if (CR_REGNO_P (regno))
36027 return regno - CR0_REGNO + 86;
36028 if (regno == VRSAVE_REGNO)
36030 if (regno == VSCR_REGNO)
36033 /* These do not make much sense. */
36034 if (regno == FRAME_POINTER_REGNUM)
36036 if (regno == ARG_POINTER_REGNUM)
36041 gcc_unreachable ();
36045 /* We use the GCC 7 (and before) internal number for non-DWARF debug
36046 information, and also for .eh_frame. */
36047 /* Translate the regnos to their numbers in GCC 7 (and before). */
36050 if (FP_REGNO_P (regno))
36051 return regno - FIRST_FPR_REGNO + 32;
36052 if (ALTIVEC_REGNO_P (regno))
36053 return regno - FIRST_ALTIVEC_REGNO + 77;
36054 if (regno == LR_REGNO)
36056 if (regno == CTR_REGNO)
36058 if (regno == CA_REGNO)
36059 return 76; /* XER */
36060 if (CR_REGNO_P (regno))
36061 return regno - CR0_REGNO + 68;
36062 if (regno == VRSAVE_REGNO)
36064 if (regno == VSCR_REGNO)
36067 if (regno == FRAME_POINTER_REGNUM)
36069 if (regno == ARG_POINTER_REGNUM)
36074 gcc_unreachable ();
36077 /* target hook eh_return_filter_mode */
36078 static scalar_int_mode
36079 rs6000_eh_return_filter_mode (void)
36081 return TARGET_32BIT ? SImode : word_mode;
36084 /* Target hook for translate_mode_attribute. */
36085 static machine_mode
36086 rs6000_translate_mode_attribute (machine_mode mode)
36088 if ((FLOAT128_IEEE_P (mode)
36089 && ieee128_float_type_node == long_double_type_node)
36090 || (FLOAT128_IBM_P (mode)
36091 && ibm128_float_type_node == long_double_type_node))
36092 return COMPLEX_MODE_P (mode) ? E_TCmode : E_TFmode;
36096 /* Target hook for scalar_mode_supported_p. */
36098 rs6000_scalar_mode_supported_p (scalar_mode mode)
36100 /* -m32 does not support TImode. This is the default, from
36101 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
36102 same ABI as for -m32. But default_scalar_mode_supported_p allows
36103 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
36104 for -mpowerpc64. */
36105 if (TARGET_32BIT && mode == TImode)
36108 if (DECIMAL_FLOAT_MODE_P (mode))
36109 return default_decimal_float_supported_p ();
36110 else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode))
36113 return default_scalar_mode_supported_p (mode);
36116 /* Target hook for vector_mode_supported_p. */
36118 rs6000_vector_mode_supported_p (machine_mode mode)
36120 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
36121 128-bit, the compiler might try to widen IEEE 128-bit to IBM
36123 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && !FLOAT128_IEEE_P (mode))
36130 /* Target hook for floatn_mode. */
36131 static opt_scalar_float_mode
36132 rs6000_floatn_mode (int n, bool extended)
36142 if (TARGET_FLOAT128_TYPE)
36143 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36145 return opt_scalar_float_mode ();
36148 return opt_scalar_float_mode ();
36151 /* Those are the only valid _FloatNx types. */
36152 gcc_unreachable ();
36166 if (TARGET_FLOAT128_TYPE)
36167 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36169 return opt_scalar_float_mode ();
36172 return opt_scalar_float_mode ();
36178 /* Target hook for c_mode_for_suffix. */
36179 static machine_mode
36180 rs6000_c_mode_for_suffix (char suffix)
36182 if (TARGET_FLOAT128_TYPE)
36184 if (suffix == 'q' || suffix == 'Q')
36185 return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode;
36187 /* At the moment, we are not defining a suffix for IBM extended double.
36188 If/when the default for -mabi=ieeelongdouble is changed, and we want
36189 to support __ibm128 constants in legacy library code, we may need to
36190 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
36191 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
36192 __float80 constants. */
36198 /* Target hook for invalid_arg_for_unprototyped_fn. */
36199 static const char *
36200 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
36202 return (!rs6000_darwin64_abi
36204 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
36205 && (funcdecl == NULL_TREE
36206 || (TREE_CODE (funcdecl) == FUNCTION_DECL
36207 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
36208 ? N_("AltiVec argument passed to unprototyped function")
36212 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
36213 setup by using __stack_chk_fail_local hidden function instead of
36214 calling __stack_chk_fail directly. Otherwise it is better to call
36215 __stack_chk_fail directly. */
36217 static tree ATTRIBUTE_UNUSED
36218 rs6000_stack_protect_fail (void)
36220 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
36221 ? default_hidden_stack_protect_fail ()
36222 : default_external_stack_protect_fail ();
36225 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
36228 static unsigned HOST_WIDE_INT
36229 rs6000_asan_shadow_offset (void)
36231 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
36235 /* Mask options that we want to support inside of attribute((target)) and
36236 #pragma GCC target operations. Note, we do not include things like
36237 64/32-bit, endianness, hard/soft floating point, etc. that would have
36238 different calling sequences. */
36240 struct rs6000_opt_mask {
36241 const char *name; /* option name */
36242 HOST_WIDE_INT mask; /* mask to set */
36243 bool invert; /* invert sense of mask */
36244 bool valid_target; /* option is a target option */
36247 static struct rs6000_opt_mask const rs6000_opt_masks[] =
36249 { "altivec", OPTION_MASK_ALTIVEC, false, true },
36250 { "cmpb", OPTION_MASK_CMPB, false, true },
36251 { "crypto", OPTION_MASK_CRYPTO, false, true },
36252 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
36253 { "dlmzb", OPTION_MASK_DLMZB, false, true },
36254 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX,
36256 { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true },
36257 { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
36258 { "fprnd", OPTION_MASK_FPRND, false, true },
36259 { "hard-dfp", OPTION_MASK_DFP, false, true },
36260 { "htm", OPTION_MASK_HTM, false, true },
36261 { "isel", OPTION_MASK_ISEL, false, true },
36262 { "mfcrf", OPTION_MASK_MFCRF, false, true },
36263 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
36264 { "modulo", OPTION_MASK_MODULO, false, true },
36265 { "mulhw", OPTION_MASK_MULHW, false, true },
36266 { "multiple", OPTION_MASK_MULTIPLE, false, true },
36267 { "popcntb", OPTION_MASK_POPCNTB, false, true },
36268 { "popcntd", OPTION_MASK_POPCNTD, false, true },
36269 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
36270 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
36271 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
36272 { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
36273 { "power9-misc", OPTION_MASK_P9_MISC, false, true },
36274 { "power9-vector", OPTION_MASK_P9_VECTOR, false, true },
36275 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
36276 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
36277 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
36278 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
36279 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
36280 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
36281 { "string", 0, false, true },
36282 { "update", OPTION_MASK_NO_UPDATE, true , true },
36283 { "vsx", OPTION_MASK_VSX, false, true },
36284 #ifdef OPTION_MASK_64BIT
36286 { "aix64", OPTION_MASK_64BIT, false, false },
36287 { "aix32", OPTION_MASK_64BIT, true, false },
36289 { "64", OPTION_MASK_64BIT, false, false },
36290 { "32", OPTION_MASK_64BIT, true, false },
36293 #ifdef OPTION_MASK_EABI
36294 { "eabi", OPTION_MASK_EABI, false, false },
36296 #ifdef OPTION_MASK_LITTLE_ENDIAN
36297 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
36298 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
36300 #ifdef OPTION_MASK_RELOCATABLE
36301 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
36303 #ifdef OPTION_MASK_STRICT_ALIGN
36304 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
36306 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
36307 { "string", 0, false, false },
36310 /* Builtin mask mapping for printing the flags. */
36311 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
36313 { "altivec", RS6000_BTM_ALTIVEC, false, false },
36314 { "vsx", RS6000_BTM_VSX, false, false },
36315 { "fre", RS6000_BTM_FRE, false, false },
36316 { "fres", RS6000_BTM_FRES, false, false },
36317 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
36318 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
36319 { "popcntd", RS6000_BTM_POPCNTD, false, false },
36320 { "cell", RS6000_BTM_CELL, false, false },
36321 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
36322 { "power9-vector", RS6000_BTM_P9_VECTOR, false, false },
36323 { "power9-misc", RS6000_BTM_P9_MISC, false, false },
36324 { "crypto", RS6000_BTM_CRYPTO, false, false },
36325 { "htm", RS6000_BTM_HTM, false, false },
36326 { "hard-dfp", RS6000_BTM_DFP, false, false },
36327 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
36328 { "long-double-128", RS6000_BTM_LDBL128, false, false },
36329 { "powerpc64", RS6000_BTM_POWERPC64, false, false },
36330 { "float128", RS6000_BTM_FLOAT128, false, false },
36331 { "float128-hw", RS6000_BTM_FLOAT128_HW,false, false },
36334 /* Option variables that we want to support inside attribute((target)) and
36335 #pragma GCC target operations. */
36337 struct rs6000_opt_var {
36338 const char *name; /* option name */
36339 size_t global_offset; /* offset of the option in global_options. */
36340 size_t target_offset; /* offset of the option in target options. */
36343 static struct rs6000_opt_var const rs6000_opt_vars[] =
36346 offsetof (struct gcc_options, x_TARGET_FRIZ),
36347 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
36348 { "avoid-indexed-addresses",
36349 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
36350 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
36352 offsetof (struct gcc_options, x_rs6000_default_long_calls),
36353 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
36354 { "optimize-swaps",
36355 offsetof (struct gcc_options, x_rs6000_optimize_swaps),
36356 offsetof (struct cl_target_option, x_rs6000_optimize_swaps), },
36357 { "allow-movmisalign",
36358 offsetof (struct gcc_options, x_TARGET_ALLOW_MOVMISALIGN),
36359 offsetof (struct cl_target_option, x_TARGET_ALLOW_MOVMISALIGN), },
36361 offsetof (struct gcc_options, x_TARGET_SCHED_GROUPS),
36362 offsetof (struct cl_target_option, x_TARGET_SCHED_GROUPS), },
36364 offsetof (struct gcc_options, x_TARGET_ALWAYS_HINT),
36365 offsetof (struct cl_target_option, x_TARGET_ALWAYS_HINT), },
36366 { "align-branch-targets",
36367 offsetof (struct gcc_options, x_TARGET_ALIGN_BRANCH_TARGETS),
36368 offsetof (struct cl_target_option, x_TARGET_ALIGN_BRANCH_TARGETS), },
36370 offsetof (struct gcc_options, x_tls_markers),
36371 offsetof (struct cl_target_option, x_tls_markers), },
36373 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36374 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36376 offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
36377 offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
36378 { "speculate-indirect-jumps",
36379 offsetof (struct gcc_options, x_rs6000_speculate_indirect_jumps),
36380 offsetof (struct cl_target_option, x_rs6000_speculate_indirect_jumps), },
36383 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
36384 parsing. Return true if there were no errors. */
36387 rs6000_inner_target_options (tree args, bool attr_p)
36391 if (args == NULL_TREE)
36394 else if (TREE_CODE (args) == STRING_CST)
36396 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36399 while ((q = strtok (p, ",")) != NULL)
36401 bool error_p = false;
36402 bool not_valid_p = false;
36403 const char *cpu_opt = NULL;
36406 if (strncmp (q, "cpu=", 4) == 0)
36408 int cpu_index = rs6000_cpu_name_lookup (q+4);
36409 if (cpu_index >= 0)
36410 rs6000_cpu_index = cpu_index;
36417 else if (strncmp (q, "tune=", 5) == 0)
36419 int tune_index = rs6000_cpu_name_lookup (q+5);
36420 if (tune_index >= 0)
36421 rs6000_tune_index = tune_index;
36431 bool invert = false;
36435 if (strncmp (r, "no-", 3) == 0)
36441 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
36442 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
36444 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
36446 if (!rs6000_opt_masks[i].valid_target)
36447 not_valid_p = true;
36451 rs6000_isa_flags_explicit |= mask;
36453 /* VSX needs altivec, so -mvsx automagically sets
36454 altivec and disables -mavoid-indexed-addresses. */
36457 if (mask == OPTION_MASK_VSX)
36459 mask |= OPTION_MASK_ALTIVEC;
36460 TARGET_AVOID_XFORM = 0;
36464 if (rs6000_opt_masks[i].invert)
36468 rs6000_isa_flags &= ~mask;
36470 rs6000_isa_flags |= mask;
36475 if (error_p && !not_valid_p)
36477 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
36478 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
36480 size_t j = rs6000_opt_vars[i].global_offset;
36481 *((int *) ((char *)&global_options + j)) = !invert;
36483 not_valid_p = false;
36491 const char *eprefix, *esuffix;
36496 eprefix = "__attribute__((__target__(";
36501 eprefix = "#pragma GCC target ";
36506 error ("invalid cpu %qs for %s%qs%s", cpu_opt, eprefix,
36508 else if (not_valid_p)
36509 error ("%s%qs%s is not allowed", eprefix, q, esuffix);
36511 error ("%s%qs%s is invalid", eprefix, q, esuffix);
36516 else if (TREE_CODE (args) == TREE_LIST)
36520 tree value = TREE_VALUE (args);
36523 bool ret2 = rs6000_inner_target_options (value, attr_p);
36527 args = TREE_CHAIN (args);
36529 while (args != NULL_TREE);
36534 error ("attribute %<target%> argument not a string");
36541 /* Print out the target options as a list for -mdebug=target. */
36544 rs6000_debug_target_options (tree args, const char *prefix)
36546 if (args == NULL_TREE)
36547 fprintf (stderr, "%s<NULL>", prefix);
36549 else if (TREE_CODE (args) == STRING_CST)
36551 char *p = ASTRDUP (TREE_STRING_POINTER (args));
36554 while ((q = strtok (p, ",")) != NULL)
36557 fprintf (stderr, "%s\"%s\"", prefix, q);
36562 else if (TREE_CODE (args) == TREE_LIST)
36566 tree value = TREE_VALUE (args);
36569 rs6000_debug_target_options (value, prefix);
36572 args = TREE_CHAIN (args);
36574 while (args != NULL_TREE);
36578 gcc_unreachable ();
36584 /* Hook to validate attribute((target("..."))). */
36587 rs6000_valid_attribute_p (tree fndecl,
36588 tree ARG_UNUSED (name),
36592 struct cl_target_option cur_target;
36595 tree new_target, new_optimize;
36596 tree func_optimize;
36598 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
36600 if (TARGET_DEBUG_TARGET)
36602 tree tname = DECL_NAME (fndecl);
36603 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
36605 fprintf (stderr, "function: %.*s\n",
36606 (int) IDENTIFIER_LENGTH (tname),
36607 IDENTIFIER_POINTER (tname));
36609 fprintf (stderr, "function: unknown\n");
36611 fprintf (stderr, "args:");
36612 rs6000_debug_target_options (args, " ");
36613 fprintf (stderr, "\n");
36616 fprintf (stderr, "flags: 0x%x\n", flags);
36618 fprintf (stderr, "--------------------\n");
36621 /* attribute((target("default"))) does nothing, beyond
36622 affecting multi-versioning. */
36623 if (TREE_VALUE (args)
36624 && TREE_CODE (TREE_VALUE (args)) == STRING_CST
36625 && TREE_CHAIN (args) == NULL_TREE
36626 && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0)
36629 old_optimize = build_optimization_node (&global_options);
36630 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
36632 /* If the function changed the optimization levels as well as setting target
36633 options, start with the optimizations specified. */
36634 if (func_optimize && func_optimize != old_optimize)
36635 cl_optimization_restore (&global_options,
36636 TREE_OPTIMIZATION (func_optimize));
36638 /* The target attributes may also change some optimization flags, so update
36639 the optimization options if necessary. */
36640 cl_target_option_save (&cur_target, &global_options);
36641 rs6000_cpu_index = rs6000_tune_index = -1;
36642 ret = rs6000_inner_target_options (args, true);
36644 /* Set up any additional state. */
36647 ret = rs6000_option_override_internal (false);
36648 new_target = build_target_option_node (&global_options);
36653 new_optimize = build_optimization_node (&global_options);
36660 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
36662 if (old_optimize != new_optimize)
36663 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
36666 cl_target_option_restore (&global_options, &cur_target);
36668 if (old_optimize != new_optimize)
36669 cl_optimization_restore (&global_options,
36670 TREE_OPTIMIZATION (old_optimize));
36676 /* Hook to validate the current #pragma GCC target and set the state, and
36677 update the macros based on what was changed. If ARGS is NULL, then
36678 POP_TARGET is used to reset the options. */
36681 rs6000_pragma_target_parse (tree args, tree pop_target)
36683 tree prev_tree = build_target_option_node (&global_options);
36685 struct cl_target_option *prev_opt, *cur_opt;
36686 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
36687 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
36689 if (TARGET_DEBUG_TARGET)
36691 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
36692 fprintf (stderr, "args:");
36693 rs6000_debug_target_options (args, " ");
36694 fprintf (stderr, "\n");
36698 fprintf (stderr, "pop_target:\n");
36699 debug_tree (pop_target);
36702 fprintf (stderr, "pop_target: <NULL>\n");
36704 fprintf (stderr, "--------------------\n");
36709 cur_tree = ((pop_target)
36711 : target_option_default_node);
36712 cl_target_option_restore (&global_options,
36713 TREE_TARGET_OPTION (cur_tree));
36717 rs6000_cpu_index = rs6000_tune_index = -1;
36718 if (!rs6000_inner_target_options (args, false)
36719 || !rs6000_option_override_internal (false)
36720 || (cur_tree = build_target_option_node (&global_options))
36723 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
36724 fprintf (stderr, "invalid pragma\n");
36730 target_option_current_node = cur_tree;
36731 rs6000_activate_target_options (target_option_current_node);
36733 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
36734 change the macros that are defined. */
36735 if (rs6000_target_modify_macros_ptr)
36737 prev_opt = TREE_TARGET_OPTION (prev_tree);
36738 prev_bumask = prev_opt->x_rs6000_builtin_mask;
36739 prev_flags = prev_opt->x_rs6000_isa_flags;
36741 cur_opt = TREE_TARGET_OPTION (cur_tree);
36742 cur_flags = cur_opt->x_rs6000_isa_flags;
36743 cur_bumask = cur_opt->x_rs6000_builtin_mask;
36745 diff_bumask = (prev_bumask ^ cur_bumask);
36746 diff_flags = (prev_flags ^ cur_flags);
36748 if ((diff_flags != 0) || (diff_bumask != 0))
36750 /* Delete old macros. */
36751 rs6000_target_modify_macros_ptr (false,
36752 prev_flags & diff_flags,
36753 prev_bumask & diff_bumask);
36755 /* Define new macros. */
36756 rs6000_target_modify_macros_ptr (true,
36757 cur_flags & diff_flags,
36758 cur_bumask & diff_bumask);
36766 /* Remember the last target of rs6000_set_current_function. */
36767 static GTY(()) tree rs6000_previous_fndecl;
36769 /* Restore target's globals from NEW_TREE and invalidate the
36770 rs6000_previous_fndecl cache. */
36773 rs6000_activate_target_options (tree new_tree)
36775 cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree));
36776 if (TREE_TARGET_GLOBALS (new_tree))
36777 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
36778 else if (new_tree == target_option_default_node)
36779 restore_target_globals (&default_target_globals);
36781 TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts ();
36782 rs6000_previous_fndecl = NULL_TREE;
36785 /* Establish appropriate back-end context for processing the function
36786 FNDECL. The argument might be NULL to indicate processing at top
36787 level, outside of any function scope. */
36789 rs6000_set_current_function (tree fndecl)
36791 if (TARGET_DEBUG_TARGET)
36793 fprintf (stderr, "\n==================== rs6000_set_current_function");
36796 fprintf (stderr, ", fndecl %s (%p)",
36797 (DECL_NAME (fndecl)
36798 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
36799 : "<unknown>"), (void *)fndecl);
36801 if (rs6000_previous_fndecl)
36802 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
36804 fprintf (stderr, "\n");
36807 /* Only change the context if the function changes. This hook is called
36808 several times in the course of compiling a function, and we don't want to
36809 slow things down too much or call target_reinit when it isn't safe. */
36810 if (fndecl == rs6000_previous_fndecl)
36814 if (rs6000_previous_fndecl == NULL_TREE)
36815 old_tree = target_option_current_node;
36816 else if (DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl))
36817 old_tree = DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl);
36819 old_tree = target_option_default_node;
36822 if (fndecl == NULL_TREE)
36824 if (old_tree != target_option_current_node)
36825 new_tree = target_option_current_node;
36827 new_tree = NULL_TREE;
36831 new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
36832 if (new_tree == NULL_TREE)
36833 new_tree = target_option_default_node;
36836 if (TARGET_DEBUG_TARGET)
36840 fprintf (stderr, "\nnew fndecl target specific options:\n");
36841 debug_tree (new_tree);
36846 fprintf (stderr, "\nold fndecl target specific options:\n");
36847 debug_tree (old_tree);
36850 if (old_tree != NULL_TREE || new_tree != NULL_TREE)
36851 fprintf (stderr, "--------------------\n");
36854 if (new_tree && old_tree != new_tree)
36855 rs6000_activate_target_options (new_tree);
36858 rs6000_previous_fndecl = fndecl;
36862 /* Save the current options */
36865 rs6000_function_specific_save (struct cl_target_option *ptr,
36866 struct gcc_options *opts)
36868 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
36869 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
36872 /* Restore the current options */
36875 rs6000_function_specific_restore (struct gcc_options *opts,
36876 struct cl_target_option *ptr)
36879 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
36880 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
36881 (void) rs6000_option_override_internal (false);
36884 /* Print the current options */
36887 rs6000_function_specific_print (FILE *file, int indent,
36888 struct cl_target_option *ptr)
36890 rs6000_print_isa_options (file, indent, "Isa options set",
36891 ptr->x_rs6000_isa_flags);
36893 rs6000_print_isa_options (file, indent, "Isa options explicit",
36894 ptr->x_rs6000_isa_flags_explicit);
36897 /* Helper function to print the current isa or misc options on a line. */
36900 rs6000_print_options_internal (FILE *file,
36902 const char *string,
36903 HOST_WIDE_INT flags,
36904 const char *prefix,
36905 const struct rs6000_opt_mask *opts,
36906 size_t num_elements)
36909 size_t start_column = 0;
36911 size_t max_column = 120;
36912 size_t prefix_len = strlen (prefix);
36913 size_t comma_len = 0;
36914 const char *comma = "";
36917 start_column += fprintf (file, "%*s", indent, "");
36921 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
36925 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
36927 /* Print the various mask options. */
36928 cur_column = start_column;
36929 for (i = 0; i < num_elements; i++)
36931 bool invert = opts[i].invert;
36932 const char *name = opts[i].name;
36933 const char *no_str = "";
36934 HOST_WIDE_INT mask = opts[i].mask;
36935 size_t len = comma_len + prefix_len + strlen (name);
36939 if ((flags & mask) == 0)
36942 len += sizeof ("no-") - 1;
36950 if ((flags & mask) != 0)
36953 len += sizeof ("no-") - 1;
36960 if (cur_column > max_column)
36962 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
36963 cur_column = start_column + len;
36967 fprintf (file, "%s%s%s%s", comma, prefix, no_str, name);
36969 comma_len = sizeof (", ") - 1;
36972 fputs ("\n", file);
36975 /* Helper function to print the current isa options on a line. */
36978 rs6000_print_isa_options (FILE *file, int indent, const char *string,
36979 HOST_WIDE_INT flags)
36981 rs6000_print_options_internal (file, indent, string, flags, "-m",
36982 &rs6000_opt_masks[0],
36983 ARRAY_SIZE (rs6000_opt_masks));
36987 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
36988 HOST_WIDE_INT flags)
36990 rs6000_print_options_internal (file, indent, string, flags, "",
36991 &rs6000_builtin_mask_names[0],
36992 ARRAY_SIZE (rs6000_builtin_mask_names));
36995 /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
36996 2.07, and 3.0 options that relate to the vector unit (-mdirect-move,
36997 -mupper-regs-df, etc.).
36999 If the user used -mno-power8-vector, we need to turn off all of the implicit
37000 ISA 2.07 and 3.0 options that relate to the vector unit.
37002 If the user used -mno-power9-vector, we need to turn off all of the implicit
37003 ISA 3.0 options that relate to the vector unit.
37005 This function does not handle explicit options such as the user specifying
37006 -mdirect-move. These are handled in rs6000_option_override_internal, and
37007 the appropriate error is given if needed.
37009 We return a mask of all of the implicit options that should not be enabled
37012 static HOST_WIDE_INT
37013 rs6000_disable_incompatible_switches (void)
37015 HOST_WIDE_INT ignore_masks = rs6000_isa_flags_explicit;
37018 static const struct {
37019 const HOST_WIDE_INT no_flag; /* flag explicitly turned off. */
37020 const HOST_WIDE_INT dep_flags; /* flags that depend on this option. */
37021 const char *const name; /* name of the switch. */
37023 { OPTION_MASK_P9_VECTOR, OTHER_P9_VECTOR_MASKS, "power9-vector" },
37024 { OPTION_MASK_P8_VECTOR, OTHER_P8_VECTOR_MASKS, "power8-vector" },
37025 { OPTION_MASK_VSX, OTHER_VSX_VECTOR_MASKS, "vsx" },
37028 for (i = 0; i < ARRAY_SIZE (flags); i++)
37030 HOST_WIDE_INT no_flag = flags[i].no_flag;
37032 if ((rs6000_isa_flags & no_flag) == 0
37033 && (rs6000_isa_flags_explicit & no_flag) != 0)
37035 HOST_WIDE_INT dep_flags = flags[i].dep_flags;
37036 HOST_WIDE_INT set_flags = (rs6000_isa_flags_explicit
37042 for (j = 0; j < ARRAY_SIZE (rs6000_opt_masks); j++)
37043 if ((set_flags & rs6000_opt_masks[j].mask) != 0)
37045 set_flags &= ~rs6000_opt_masks[j].mask;
37046 error ("%<-mno-%s%> turns off %<-m%s%>",
37048 rs6000_opt_masks[j].name);
37051 gcc_assert (!set_flags);
37054 rs6000_isa_flags &= ~dep_flags;
37055 ignore_masks |= no_flag | dep_flags;
37059 return ignore_masks;
37063 /* Helper function for printing the function name when debugging. */
37065 static const char *
37066 get_decl_name (tree fn)
37073 name = DECL_NAME (fn);
37075 return "<no-name>";
37077 return IDENTIFIER_POINTER (name);
37080 /* Return the clone id of the target we are compiling code for in a target
37081 clone. The clone id is ordered from 0 (default) to CLONE_MAX-1 and gives
37082 the priority list for the target clones (ordered from lowest to
37086 rs6000_clone_priority (tree fndecl)
37088 tree fn_opts = DECL_FUNCTION_SPECIFIC_TARGET (fndecl);
37089 HOST_WIDE_INT isa_masks;
37090 int ret = CLONE_DEFAULT;
37091 tree attrs = lookup_attribute ("target", DECL_ATTRIBUTES (fndecl));
37092 const char *attrs_str = NULL;
37094 attrs = TREE_VALUE (TREE_VALUE (attrs));
37095 attrs_str = TREE_STRING_POINTER (attrs);
37097 /* Return priority zero for default function. Return the ISA needed for the
37098 function if it is not the default. */
37099 if (strcmp (attrs_str, "default") != 0)
37101 if (fn_opts == NULL_TREE)
37102 fn_opts = target_option_default_node;
37104 if (!fn_opts || !TREE_TARGET_OPTION (fn_opts))
37105 isa_masks = rs6000_isa_flags;
37107 isa_masks = TREE_TARGET_OPTION (fn_opts)->x_rs6000_isa_flags;
37109 for (ret = CLONE_MAX - 1; ret != 0; ret--)
37110 if ((rs6000_clone_map[ret].isa_mask & isa_masks) != 0)
37114 if (TARGET_DEBUG_TARGET)
37115 fprintf (stderr, "rs6000_get_function_version_priority (%s) => %d\n",
37116 get_decl_name (fndecl), ret);
37121 /* This compares the priority of target features in function DECL1 and DECL2.
37122 It returns positive value if DECL1 is higher priority, negative value if
37123 DECL2 is higher priority and 0 if they are the same. Note, priorities are
37124 ordered from lowest (CLONE_DEFAULT) to highest (currently CLONE_ISA_3_0). */
37127 rs6000_compare_version_priority (tree decl1, tree decl2)
37129 int priority1 = rs6000_clone_priority (decl1);
37130 int priority2 = rs6000_clone_priority (decl2);
37131 int ret = priority1 - priority2;
37133 if (TARGET_DEBUG_TARGET)
37134 fprintf (stderr, "rs6000_compare_version_priority (%s, %s) => %d\n",
37135 get_decl_name (decl1), get_decl_name (decl2), ret);
37140 /* Make a dispatcher declaration for the multi-versioned function DECL.
37141 Calls to DECL function will be replaced with calls to the dispatcher
37142 by the front-end. Returns the decl of the dispatcher function. */
37145 rs6000_get_function_versions_dispatcher (void *decl)
37147 tree fn = (tree) decl;
37148 struct cgraph_node *node = NULL;
37149 struct cgraph_node *default_node = NULL;
37150 struct cgraph_function_version_info *node_v = NULL;
37151 struct cgraph_function_version_info *first_v = NULL;
37153 tree dispatch_decl = NULL;
37155 struct cgraph_function_version_info *default_version_info = NULL;
37156 gcc_assert (fn != NULL && DECL_FUNCTION_VERSIONED (fn));
37158 if (TARGET_DEBUG_TARGET)
37159 fprintf (stderr, "rs6000_get_function_versions_dispatcher (%s)\n",
37160 get_decl_name (fn));
37162 node = cgraph_node::get (fn);
37163 gcc_assert (node != NULL);
37165 node_v = node->function_version ();
37166 gcc_assert (node_v != NULL);
37168 if (node_v->dispatcher_resolver != NULL)
37169 return node_v->dispatcher_resolver;
37171 /* Find the default version and make it the first node. */
37173 /* Go to the beginning of the chain. */
37174 while (first_v->prev != NULL)
37175 first_v = first_v->prev;
37177 default_version_info = first_v;
37178 while (default_version_info != NULL)
37180 const tree decl2 = default_version_info->this_node->decl;
37181 if (is_function_default_version (decl2))
37183 default_version_info = default_version_info->next;
37186 /* If there is no default node, just return NULL. */
37187 if (default_version_info == NULL)
37190 /* Make default info the first node. */
37191 if (first_v != default_version_info)
37193 default_version_info->prev->next = default_version_info->next;
37194 if (default_version_info->next)
37195 default_version_info->next->prev = default_version_info->prev;
37196 first_v->prev = default_version_info;
37197 default_version_info->next = first_v;
37198 default_version_info->prev = NULL;
37201 default_node = default_version_info->this_node;
37203 #ifndef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
37204 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37205 "%<target_clones%> attribute needs GLIBC (2.23 and newer) that "
37206 "exports hardware capability bits");
37209 if (targetm.has_ifunc_p ())
37211 struct cgraph_function_version_info *it_v = NULL;
37212 struct cgraph_node *dispatcher_node = NULL;
37213 struct cgraph_function_version_info *dispatcher_version_info = NULL;
37215 /* Right now, the dispatching is done via ifunc. */
37216 dispatch_decl = make_dispatcher_decl (default_node->decl);
37218 dispatcher_node = cgraph_node::get_create (dispatch_decl);
37219 gcc_assert (dispatcher_node != NULL);
37220 dispatcher_node->dispatcher_function = 1;
37221 dispatcher_version_info
37222 = dispatcher_node->insert_new_function_version ();
37223 dispatcher_version_info->next = default_version_info;
37224 dispatcher_node->definition = 1;
37226 /* Set the dispatcher for all the versions. */
37227 it_v = default_version_info;
37228 while (it_v != NULL)
37230 it_v->dispatcher_resolver = dispatch_decl;
37236 error_at (DECL_SOURCE_LOCATION (default_node->decl),
37237 "multiversioning needs ifunc which is not supported "
37242 return dispatch_decl;
37245 /* Make the resolver function decl to dispatch the versions of a multi-
37246 versioned function, DEFAULT_DECL. Create an empty basic block in the
37247 resolver and store the pointer in EMPTY_BB. Return the decl of the resolver
37251 make_resolver_func (const tree default_decl,
37252 const tree dispatch_decl,
37253 basic_block *empty_bb)
37255 /* Make the resolver function static. The resolver function returns
37257 tree decl_name = clone_function_name (default_decl, "resolver");
37258 const char *resolver_name = IDENTIFIER_POINTER (decl_name);
37259 tree type = build_function_type_list (ptr_type_node, NULL_TREE);
37260 tree decl = build_fn_decl (resolver_name, type);
37261 SET_DECL_ASSEMBLER_NAME (decl, decl_name);
37263 DECL_NAME (decl) = decl_name;
37264 TREE_USED (decl) = 1;
37265 DECL_ARTIFICIAL (decl) = 1;
37266 DECL_IGNORED_P (decl) = 0;
37267 TREE_PUBLIC (decl) = 0;
37268 DECL_UNINLINABLE (decl) = 1;
37270 /* Resolver is not external, body is generated. */
37271 DECL_EXTERNAL (decl) = 0;
37272 DECL_EXTERNAL (dispatch_decl) = 0;
37274 DECL_CONTEXT (decl) = NULL_TREE;
37275 DECL_INITIAL (decl) = make_node (BLOCK);
37276 DECL_STATIC_CONSTRUCTOR (decl) = 0;
37278 /* Build result decl and add to function_decl. */
37279 tree t = build_decl (UNKNOWN_LOCATION, RESULT_DECL, NULL_TREE, ptr_type_node);
37280 DECL_CONTEXT (t) = decl;
37281 DECL_ARTIFICIAL (t) = 1;
37282 DECL_IGNORED_P (t) = 1;
37283 DECL_RESULT (decl) = t;
37285 gimplify_function_tree (decl);
37286 push_cfun (DECL_STRUCT_FUNCTION (decl));
37287 *empty_bb = init_lowered_empty_function (decl, false,
37288 profile_count::uninitialized ());
37290 cgraph_node::add_new_function (decl, true);
37291 symtab->call_cgraph_insertion_hooks (cgraph_node::get_create (decl));
37295 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
37296 DECL_ATTRIBUTES (dispatch_decl)
37297 = make_attribute ("ifunc", resolver_name, DECL_ATTRIBUTES (dispatch_decl));
37299 cgraph_node::create_same_body_alias (dispatch_decl, decl);
37304 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL to
37305 return a pointer to VERSION_DECL if we are running on a machine that
37306 supports the index CLONE_ISA hardware architecture bits. This function will
37307 be called during version dispatch to decide which function version to
37308 execute. It returns the basic block at the end, to which more conditions
37312 add_condition_to_bb (tree function_decl, tree version_decl,
37313 int clone_isa, basic_block new_bb)
37315 push_cfun (DECL_STRUCT_FUNCTION (function_decl));
37317 gcc_assert (new_bb != NULL);
37318 gimple_seq gseq = bb_seq (new_bb);
37321 tree convert_expr = build1 (CONVERT_EXPR, ptr_type_node,
37322 build_fold_addr_expr (version_decl));
37323 tree result_var = create_tmp_var (ptr_type_node);
37324 gimple *convert_stmt = gimple_build_assign (result_var, convert_expr);
37325 gimple *return_stmt = gimple_build_return (result_var);
37327 if (clone_isa == CLONE_DEFAULT)
37329 gimple_seq_add_stmt (&gseq, convert_stmt);
37330 gimple_seq_add_stmt (&gseq, return_stmt);
37331 set_bb_seq (new_bb, gseq);
37332 gimple_set_bb (convert_stmt, new_bb);
37333 gimple_set_bb (return_stmt, new_bb);
37338 tree bool_zero = build_int_cst (bool_int_type_node, 0);
37339 tree cond_var = create_tmp_var (bool_int_type_node);
37340 tree predicate_decl = rs6000_builtin_decls [(int) RS6000_BUILTIN_CPU_SUPPORTS];
37341 const char *arg_str = rs6000_clone_map[clone_isa].name;
37342 tree predicate_arg = build_string_literal (strlen (arg_str) + 1, arg_str);
37343 gimple *call_cond_stmt = gimple_build_call (predicate_decl, 1, predicate_arg);
37344 gimple_call_set_lhs (call_cond_stmt, cond_var);
37346 gimple_set_block (call_cond_stmt, DECL_INITIAL (function_decl));
37347 gimple_set_bb (call_cond_stmt, new_bb);
37348 gimple_seq_add_stmt (&gseq, call_cond_stmt);
37350 gimple *if_else_stmt = gimple_build_cond (NE_EXPR, cond_var, bool_zero,
37351 NULL_TREE, NULL_TREE);
37352 gimple_set_block (if_else_stmt, DECL_INITIAL (function_decl));
37353 gimple_set_bb (if_else_stmt, new_bb);
37354 gimple_seq_add_stmt (&gseq, if_else_stmt);
37356 gimple_seq_add_stmt (&gseq, convert_stmt);
37357 gimple_seq_add_stmt (&gseq, return_stmt);
37358 set_bb_seq (new_bb, gseq);
37360 basic_block bb1 = new_bb;
37361 edge e12 = split_block (bb1, if_else_stmt);
37362 basic_block bb2 = e12->dest;
37363 e12->flags &= ~EDGE_FALLTHRU;
37364 e12->flags |= EDGE_TRUE_VALUE;
37366 edge e23 = split_block (bb2, return_stmt);
37367 gimple_set_bb (convert_stmt, bb2);
37368 gimple_set_bb (return_stmt, bb2);
37370 basic_block bb3 = e23->dest;
37371 make_edge (bb1, bb3, EDGE_FALSE_VALUE);
37374 make_edge (bb2, EXIT_BLOCK_PTR_FOR_FN (cfun), 0);
37380 /* This function generates the dispatch function for multi-versioned functions.
37381 DISPATCH_DECL is the function which will contain the dispatch logic.
37382 FNDECLS are the function choices for dispatch, and is a tree chain.
37383 EMPTY_BB is the basic block pointer in DISPATCH_DECL in which the dispatch
37384 code is generated. */
37387 dispatch_function_versions (tree dispatch_decl,
37389 basic_block *empty_bb)
37393 vec<tree> *fndecls;
37394 tree clones[CLONE_MAX];
37396 if (TARGET_DEBUG_TARGET)
37397 fputs ("dispatch_function_versions, top\n", stderr);
37399 gcc_assert (dispatch_decl != NULL
37400 && fndecls_p != NULL
37401 && empty_bb != NULL);
37403 /* fndecls_p is actually a vector. */
37404 fndecls = static_cast<vec<tree> *> (fndecls_p);
37406 /* At least one more version other than the default. */
37407 gcc_assert (fndecls->length () >= 2);
37409 /* The first version in the vector is the default decl. */
37410 memset ((void *) clones, '\0', sizeof (clones));
37411 clones[CLONE_DEFAULT] = (*fndecls)[0];
37413 /* On the PowerPC, we do not need to call __builtin_cpu_init, which is a NOP
37414 on the PowerPC (on the x86_64, it is not a NOP). The builtin function
37415 __builtin_cpu_support ensures that the TOC fields are setup by requiring a
37416 recent glibc. If we ever need to call __builtin_cpu_init, we would need
37417 to insert the code here to do the call. */
37419 for (ix = 1; fndecls->iterate (ix, &ele); ++ix)
37421 int priority = rs6000_clone_priority (ele);
37422 if (!clones[priority])
37423 clones[priority] = ele;
37426 for (ix = CLONE_MAX - 1; ix >= 0; ix--)
37429 if (TARGET_DEBUG_TARGET)
37430 fprintf (stderr, "dispatch_function_versions, clone %d, %s\n",
37431 ix, get_decl_name (clones[ix]));
37433 *empty_bb = add_condition_to_bb (dispatch_decl, clones[ix], ix,
37440 /* Generate the dispatching code body to dispatch multi-versioned function
37441 DECL. The target hook is called to process the "target" attributes and
37442 provide the code to dispatch the right function at run-time. NODE points
37443 to the dispatcher decl whose body will be created. */
37446 rs6000_generate_version_dispatcher_body (void *node_p)
37449 basic_block empty_bb;
37450 struct cgraph_node *node = (cgraph_node *) node_p;
37451 struct cgraph_function_version_info *ninfo = node->function_version ();
37453 if (ninfo->dispatcher_resolver)
37454 return ninfo->dispatcher_resolver;
37456 /* node is going to be an alias, so remove the finalized bit. */
37457 node->definition = false;
37459 /* The first version in the chain corresponds to the default version. */
37460 ninfo->dispatcher_resolver = resolver
37461 = make_resolver_func (ninfo->next->this_node->decl, node->decl, &empty_bb);
37463 if (TARGET_DEBUG_TARGET)
37464 fprintf (stderr, "rs6000_get_function_versions_dispatcher, %s\n",
37465 get_decl_name (resolver));
37467 push_cfun (DECL_STRUCT_FUNCTION (resolver));
37468 auto_vec<tree, 2> fn_ver_vec;
37470 for (struct cgraph_function_version_info *vinfo = ninfo->next;
37472 vinfo = vinfo->next)
37474 struct cgraph_node *version = vinfo->this_node;
37475 /* Check for virtual functions here again, as by this time it should
37476 have been determined if this function needs a vtable index or
37477 not. This happens for methods in derived classes that override
37478 virtual methods in base classes but are not explicitly marked as
37480 if (DECL_VINDEX (version->decl))
37481 sorry ("Virtual function multiversioning not supported");
37483 fn_ver_vec.safe_push (version->decl);
37486 dispatch_function_versions (resolver, &fn_ver_vec, &empty_bb);
37487 cgraph_edge::rebuild_edges ();
37493 /* Hook to determine if one function can safely inline another. */
37496 rs6000_can_inline_p (tree caller, tree callee)
37499 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
37500 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
37502 /* If callee has no option attributes, then it is ok to inline. */
37506 /* If caller has no option attributes, but callee does then it is not ok to
37508 else if (!caller_tree)
37513 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
37514 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
37516 /* Callee's options should a subset of the caller's, i.e. a vsx function
37517 can inline an altivec function but a non-vsx function can't inline a
37519 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
37520 == callee_opts->x_rs6000_isa_flags)
37524 if (TARGET_DEBUG_TARGET)
37525 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
37526 get_decl_name (caller), get_decl_name (callee),
37527 (ret ? "can" : "cannot"));
37532 /* Allocate a stack temp and fixup the address so it meets the particular
37533 memory requirements (either offetable or REG+REG addressing). */
37536 rs6000_allocate_stack_temp (machine_mode mode,
37537 bool offsettable_p,
37540 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
37541 rtx addr = XEXP (stack, 0);
37542 int strict_p = reload_completed;
37544 if (!legitimate_indirect_address_p (addr, strict_p))
37547 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
37548 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37550 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
37551 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
37557 /* Given a memory reference, if it is not a reg or reg+reg addressing,
37558 convert to such a form to deal with memory reference instructions
37559 like STFIWX and LDBRX that only take reg+reg addressing. */
37562 rs6000_force_indexed_or_indirect_mem (rtx x)
37564 machine_mode mode = GET_MODE (x);
37566 gcc_assert (MEM_P (x));
37567 if (can_create_pseudo_p () && !indexed_or_indirect_operand (x, mode))
37569 rtx addr = XEXP (x, 0);
37570 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
37572 rtx reg = XEXP (addr, 0);
37573 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
37574 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
37575 gcc_assert (REG_P (reg));
37576 emit_insn (gen_add3_insn (reg, reg, size_rtx));
37579 else if (GET_CODE (addr) == PRE_MODIFY)
37581 rtx reg = XEXP (addr, 0);
37582 rtx expr = XEXP (addr, 1);
37583 gcc_assert (REG_P (reg));
37584 gcc_assert (GET_CODE (expr) == PLUS);
37585 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
37589 x = replace_equiv_address (x, force_reg (Pmode, addr));
37595 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
37597 On the RS/6000, all integer constants are acceptable, most won't be valid
37598 for particular insns, though. Only easy FP constants are acceptable. */
37601 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
37603 if (TARGET_ELF && tls_referenced_p (x))
37606 if (CONST_DOUBLE_P (x))
37607 return easy_fp_constant (x, mode);
37609 if (GET_CODE (x) == CONST_VECTOR)
37610 return easy_vector_constant (x, mode);
37616 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
37619 chain_already_loaded (rtx_insn *last)
37621 for (; last != NULL; last = PREV_INSN (last))
37623 if (NONJUMP_INSN_P (last))
37625 rtx patt = PATTERN (last);
37627 if (GET_CODE (patt) == SET)
37629 rtx lhs = XEXP (patt, 0);
37631 if (REG_P (lhs) && REGNO (lhs) == STATIC_CHAIN_REGNUM)
37639 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
37642 rs6000_call_aix (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37644 rtx func = func_desc;
37645 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
37646 rtx toc_load = NULL_RTX;
37647 rtx toc_restore = NULL_RTX;
37649 rtx abi_reg = NULL_RTX;
37653 bool is_pltseq_longcall;
37656 tlsarg = global_tlsarg;
37658 /* Handle longcall attributes. */
37659 is_pltseq_longcall = false;
37660 if ((INTVAL (cookie) & CALL_LONG) != 0
37661 && GET_CODE (func_desc) == SYMBOL_REF)
37663 func = rs6000_longcall_ref (func_desc, tlsarg);
37665 is_pltseq_longcall = true;
37668 /* Handle indirect calls. */
37669 if (!SYMBOL_REF_P (func)
37670 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func)))
37672 /* Save the TOC into its reserved slot before the call,
37673 and prepare to restore it after the call. */
37674 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
37675 rtx stack_toc_unspec = gen_rtx_UNSPEC (Pmode,
37676 gen_rtvec (1, stack_toc_offset),
37678 toc_restore = gen_rtx_SET (toc_reg, stack_toc_unspec);
37680 /* Can we optimize saving the TOC in the prologue or
37681 do we need to do it at every call? */
37682 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
37683 cfun->machine->save_toc_in_prologue = true;
37686 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
37687 rtx stack_toc_mem = gen_frame_mem (Pmode,
37688 gen_rtx_PLUS (Pmode, stack_ptr,
37689 stack_toc_offset));
37690 MEM_VOLATILE_P (stack_toc_mem) = 1;
37691 if (is_pltseq_longcall)
37693 /* Use USPEC_PLTSEQ here to emit every instruction in an
37694 inline PLT call sequence with a reloc, enabling the
37695 linker to edit the sequence back to a direct call
37696 when that makes sense. */
37697 rtvec v = gen_rtvec (3, toc_reg, func_desc, tlsarg);
37698 rtx mark_toc_reg = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37699 emit_insn (gen_rtx_SET (stack_toc_mem, mark_toc_reg));
37702 emit_move_insn (stack_toc_mem, toc_reg);
37705 if (DEFAULT_ABI == ABI_ELFv2)
37707 /* A function pointer in the ELFv2 ABI is just a plain address, but
37708 the ABI requires it to be loaded into r12 before the call. */
37709 func_addr = gen_rtx_REG (Pmode, 12);
37710 if (!rtx_equal_p (func_addr, func))
37711 emit_move_insn (func_addr, func);
37712 abi_reg = func_addr;
37713 /* Indirect calls via CTR are strongly preferred over indirect
37714 calls via LR, so move the address there. Needed to mark
37715 this insn for linker plt sequence editing too. */
37716 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37717 if (is_pltseq_longcall)
37719 rtvec v = gen_rtvec (3, abi_reg, func_desc, tlsarg);
37720 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37721 emit_insn (gen_rtx_SET (func_addr, mark_func));
37722 v = gen_rtvec (2, func_addr, func_desc);
37723 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37726 emit_move_insn (func_addr, abi_reg);
37730 /* A function pointer under AIX is a pointer to a data area whose
37731 first word contains the actual address of the function, whose
37732 second word contains a pointer to its TOC, and whose third word
37733 contains a value to place in the static chain register (r11).
37734 Note that if we load the static chain, our "trampoline" need
37735 not have any executable code. */
37737 /* Load up address of the actual function. */
37738 func = force_reg (Pmode, func);
37739 func_addr = gen_reg_rtx (Pmode);
37740 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func));
37742 /* Indirect calls via CTR are strongly preferred over indirect
37743 calls via LR, so move the address there. */
37744 rtx ctr_reg = gen_rtx_REG (Pmode, CTR_REGNO);
37745 emit_move_insn (ctr_reg, func_addr);
37746 func_addr = ctr_reg;
37748 /* Prepare to load the TOC of the called function. Note that the
37749 TOC load must happen immediately before the actual call so
37750 that unwinding the TOC registers works correctly. See the
37751 comment in frob_update_context. */
37752 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
37753 rtx func_toc_mem = gen_rtx_MEM (Pmode,
37754 gen_rtx_PLUS (Pmode, func,
37756 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
37758 /* If we have a static chain, load it up. But, if the call was
37759 originally direct, the 3rd word has not been written since no
37760 trampoline has been built, so we ought not to load it, lest we
37761 override a static chain value. */
37762 if (!(GET_CODE (func_desc) == SYMBOL_REF
37763 && SYMBOL_REF_FUNCTION_P (func_desc))
37764 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
37765 && !chain_already_loaded (get_current_sequence ()->next->last))
37767 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
37768 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
37769 rtx func_sc_mem = gen_rtx_MEM (Pmode,
37770 gen_rtx_PLUS (Pmode, func,
37772 emit_move_insn (sc_reg, func_sc_mem);
37779 /* Direct calls use the TOC: for local calls, the callee will
37780 assume the TOC register is set; for non-local calls, the
37781 PLT stub needs the TOC register. */
37786 /* Create the call. */
37787 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
37788 if (value != NULL_RTX)
37789 call[0] = gen_rtx_SET (value, call[0]);
37793 call[n_call++] = toc_load;
37795 call[n_call++] = toc_restore;
37797 call[n_call++] = gen_hard_reg_clobber (Pmode, LR_REGNO);
37799 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
37800 insn = emit_call_insn (insn);
37802 /* Mention all registers defined by the ABI to hold information
37803 as uses in CALL_INSN_FUNCTION_USAGE. */
37805 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37808 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
37811 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37816 gcc_assert (INTVAL (cookie) == 0);
37819 tlsarg = global_tlsarg;
37821 /* Create the call. */
37822 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), tlsarg);
37823 if (value != NULL_RTX)
37824 call[0] = gen_rtx_SET (value, call[0]);
37826 call[1] = simple_return_rtx;
37828 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
37829 insn = emit_call_insn (insn);
37831 /* Note use of the TOC register. */
37832 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
37835 /* Expand code to perform a call under the SYSV4 ABI. */
37838 rs6000_call_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37840 rtx func = func_desc;
37844 rtx abi_reg = NULL_RTX;
37848 tlsarg = global_tlsarg;
37850 /* Handle longcall attributes. */
37851 if ((INTVAL (cookie) & CALL_LONG) != 0
37852 && GET_CODE (func_desc) == SYMBOL_REF)
37854 func = rs6000_longcall_ref (func_desc, tlsarg);
37855 /* If the longcall was implemented as an inline PLT call using
37856 PLT unspecs then func will be REG:r11. If not, func will be
37857 a pseudo reg. The inline PLT call sequence supports lazy
37858 linking (and longcalls to functions in dlopen'd libraries).
37859 The other style of longcalls don't. The lazy linking entry
37860 to the dynamic symbol resolver requires r11 be the function
37861 address (as it is for linker generated PLT stubs). Ensure
37862 r11 stays valid to the bctrl by marking r11 used by the call. */
37867 /* Handle indirect calls. */
37868 if (GET_CODE (func) != SYMBOL_REF)
37870 func = force_reg (Pmode, func);
37872 /* Indirect calls via CTR are strongly preferred over indirect
37873 calls via LR, so move the address there. That can't be left
37874 to reload because we want to mark every instruction in an
37875 inline PLT call sequence with a reloc, enabling the linker to
37876 edit the sequence back to a direct call when that makes sense. */
37877 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37880 rtvec v = gen_rtvec (3, func, func_desc, tlsarg);
37881 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37882 emit_insn (gen_rtx_SET (func_addr, mark_func));
37883 v = gen_rtvec (2, func_addr, func_desc);
37884 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37887 emit_move_insn (func_addr, func);
37892 /* Create the call. */
37893 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
37894 if (value != NULL_RTX)
37895 call[0] = gen_rtx_SET (value, call[0]);
37897 call[1] = gen_rtx_USE (VOIDmode, cookie);
37899 if (TARGET_SECURE_PLT
37901 && GET_CODE (func_addr) == SYMBOL_REF
37902 && !SYMBOL_REF_LOCAL_P (func_addr))
37903 call[n++] = gen_rtx_USE (VOIDmode, pic_offset_table_rtx);
37905 call[n++] = gen_hard_reg_clobber (Pmode, LR_REGNO);
37907 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n, call));
37908 insn = emit_call_insn (insn);
37910 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37913 /* Expand code to perform a sibling call under the SysV4 ABI. */
37916 rs6000_sibcall_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
37918 rtx func = func_desc;
37922 rtx abi_reg = NULL_RTX;
37925 tlsarg = global_tlsarg;
37927 /* Handle longcall attributes. */
37928 if ((INTVAL (cookie) & CALL_LONG) != 0
37929 && GET_CODE (func_desc) == SYMBOL_REF)
37931 func = rs6000_longcall_ref (func_desc, tlsarg);
37932 /* If the longcall was implemented as an inline PLT call using
37933 PLT unspecs then func will be REG:r11. If not, func will be
37934 a pseudo reg. The inline PLT call sequence supports lazy
37935 linking (and longcalls to functions in dlopen'd libraries).
37936 The other style of longcalls don't. The lazy linking entry
37937 to the dynamic symbol resolver requires r11 be the function
37938 address (as it is for linker generated PLT stubs). Ensure
37939 r11 stays valid to the bctr by marking r11 used by the call. */
37944 /* Handle indirect calls. */
37945 if (GET_CODE (func) != SYMBOL_REF)
37947 func = force_reg (Pmode, func);
37949 /* Indirect sibcalls must go via CTR. That can't be left to
37950 reload because we want to mark every instruction in an inline
37951 PLT call sequence with a reloc, enabling the linker to edit
37952 the sequence back to a direct call when that makes sense. */
37953 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
37956 rtvec v = gen_rtvec (3, func, func_desc, tlsarg);
37957 rtx mark_func = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37958 emit_insn (gen_rtx_SET (func_addr, mark_func));
37959 v = gen_rtvec (2, func_addr, func_desc);
37960 func_addr = gen_rtx_UNSPEC (Pmode, v, UNSPEC_PLTSEQ);
37963 emit_move_insn (func_addr, func);
37968 /* Create the call. */
37969 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
37970 if (value != NULL_RTX)
37971 call[0] = gen_rtx_SET (value, call[0]);
37973 call[1] = gen_rtx_USE (VOIDmode, cookie);
37974 call[2] = simple_return_rtx;
37976 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (3, call));
37977 insn = emit_call_insn (insn);
37979 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
37984 /* Expand code to perform a call under the Darwin ABI.
37985 Modulo handling of mlongcall, this is much the same as sysv.
37986 if/when the longcall optimisation is removed, we could drop this
37987 code and use the sysv case (taking care to avoid the tls stuff).
37989 We can use this for sibcalls too, if needed. */
37992 rs6000_call_darwin_1 (rtx value, rtx func_desc, rtx tlsarg,
37993 rtx cookie, bool sibcall)
37995 rtx func = func_desc;
37999 int cookie_val = INTVAL (cookie);
38000 bool make_island = false;
38002 /* Handle longcall attributes, there are two cases for Darwin:
38003 1) Newer linkers are capable of synthesising any branch islands needed.
38004 2) We need a helper branch island synthesised by the compiler.
38005 The second case has mostly been retired and we don't use it for m64.
38006 In fact, it's is an optimisation, we could just indirect as sysv does..
38007 ... however, backwards compatibility for now.
38008 If we're going to use this, then we need to keep the CALL_LONG bit set,
38009 so that we can pick up the special insn form later. */
38010 if ((cookie_val & CALL_LONG) != 0
38011 && GET_CODE (func_desc) == SYMBOL_REF)
38013 if (darwin_emit_branch_islands && TARGET_32BIT)
38014 make_island = true; /* Do nothing yet, retain the CALL_LONG flag. */
38017 /* The linker is capable of doing this, but the user explicitly
38018 asked for -mlongcall, so we'll do the 'normal' version. */
38019 func = rs6000_longcall_ref (func_desc, NULL_RTX);
38020 cookie_val &= ~CALL_LONG; /* Handled, zap it. */
38024 /* Handle indirect calls. */
38025 if (GET_CODE (func) != SYMBOL_REF)
38027 func = force_reg (Pmode, func);
38029 /* Indirect calls via CTR are strongly preferred over indirect
38030 calls via LR, and are required for indirect sibcalls, so move
38031 the address there. */
38032 func_addr = gen_rtx_REG (Pmode, CTR_REGNO);
38033 emit_move_insn (func_addr, func);
38038 /* Create the call. */
38039 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), tlsarg);
38040 if (value != NULL_RTX)
38041 call[0] = gen_rtx_SET (value, call[0]);
38043 call[1] = gen_rtx_USE (VOIDmode, GEN_INT (cookie_val));
38046 call[2] = simple_return_rtx;
38048 call[2] = gen_hard_reg_clobber (Pmode, LR_REGNO);
38050 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (3, call));
38051 insn = emit_call_insn (insn);
38052 /* Now we have the debug info in the insn, we can set up the branch island
38053 if we're using one. */
38056 tree funname = get_identifier (XSTR (func_desc, 0));
38058 if (no_previous_def (funname))
38060 rtx label_rtx = gen_label_rtx ();
38061 char *label_buf, temp_buf[256];
38062 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
38063 CODE_LABEL_NUMBER (label_rtx));
38064 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
38065 tree labelname = get_identifier (label_buf);
38066 add_compiler_branch_island (labelname, funname,
38067 insn_line ((const rtx_insn*)insn));
38074 rs6000_call_darwin (rtx value ATTRIBUTE_UNUSED, rtx func_desc ATTRIBUTE_UNUSED,
38075 rtx tlsarg ATTRIBUTE_UNUSED, rtx cookie ATTRIBUTE_UNUSED)
38078 rs6000_call_darwin_1 (value, func_desc, tlsarg, cookie, false);
38086 rs6000_sibcall_darwin (rtx value ATTRIBUTE_UNUSED, rtx func_desc ATTRIBUTE_UNUSED,
38087 rtx tlsarg ATTRIBUTE_UNUSED, rtx cookie ATTRIBUTE_UNUSED)
38090 rs6000_call_darwin_1 (value, func_desc, tlsarg, cookie, true);
38097 /* Return whether we need to always update the saved TOC pointer when we update
38098 the stack pointer. */
38101 rs6000_save_toc_in_prologue_p (void)
38103 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
38106 #ifdef HAVE_GAS_HIDDEN
38107 # define USE_HIDDEN_LINKONCE 1
38109 # define USE_HIDDEN_LINKONCE 0
38112 /* Fills in the label name that should be used for a 476 link stack thunk. */
38115 get_ppc476_thunk_name (char name[32])
38117 gcc_assert (TARGET_LINK_STACK);
38119 if (USE_HIDDEN_LINKONCE)
38120 sprintf (name, "__ppc476.get_thunk");
38122 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
38125 /* This function emits the simple thunk routine that is used to preserve
38126 the link stack on the 476 cpu. */
38128 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
38130 rs6000_code_end (void)
38135 if (!TARGET_LINK_STACK)
38138 get_ppc476_thunk_name (name);
38140 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
38141 build_function_type_list (void_type_node, NULL_TREE));
38142 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
38143 NULL_TREE, void_type_node);
38144 TREE_PUBLIC (decl) = 1;
38145 TREE_STATIC (decl) = 1;
38148 if (USE_HIDDEN_LINKONCE && !TARGET_XCOFF)
38150 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
38151 targetm.asm_out.unique_section (decl, 0);
38152 switch_to_section (get_named_section (decl, NULL, 0));
38153 DECL_WEAK (decl) = 1;
38154 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
38155 targetm.asm_out.globalize_label (asm_out_file, name);
38156 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
38157 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
38162 switch_to_section (text_section);
38163 ASM_OUTPUT_LABEL (asm_out_file, name);
38166 DECL_INITIAL (decl) = make_node (BLOCK);
38167 current_function_decl = decl;
38168 allocate_struct_function (decl, false);
38169 init_function_start (decl);
38170 first_function_block_is_cold = false;
38171 /* Make sure unwind info is emitted for the thunk if needed. */
38172 final_start_function (emit_barrier (), asm_out_file, 1);
38174 fputs ("\tblr\n", asm_out_file);
38176 final_end_function ();
38177 init_insn_lengths ();
38178 free_after_compilation (cfun);
38180 current_function_decl = NULL;
38183 /* Add r30 to hard reg set if the prologue sets it up and it is not
38184 pic_offset_table_rtx. */
38187 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
38189 if (!TARGET_SINGLE_PIC_BASE
38191 && TARGET_MINIMAL_TOC
38192 && !constant_pool_empty_p ())
38193 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
38194 if (cfun->machine->split_stack_argp_used)
38195 add_to_hard_reg_set (&set->set, Pmode, 12);
38197 /* Make sure the hard reg set doesn't include r2, which was possibly added
38198 via PIC_OFFSET_TABLE_REGNUM. */
38200 remove_from_hard_reg_set (&set->set, Pmode, TOC_REGNUM);
38204 /* Helper function for rs6000_split_logical to emit a logical instruction after
38205 spliting the operation to single GPR registers.
38207 DEST is the destination register.
38208 OP1 and OP2 are the input source registers.
38209 CODE is the base operation (AND, IOR, XOR, NOT).
38210 MODE is the machine mode.
38211 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38212 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38213 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38216 rs6000_split_logical_inner (rtx dest,
38219 enum rtx_code code,
38221 bool complement_final_p,
38222 bool complement_op1_p,
38223 bool complement_op2_p)
38227 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38228 if (op2 && CONST_INT_P (op2)
38229 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
38230 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38232 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
38233 HOST_WIDE_INT value = INTVAL (op2) & mask;
38235 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38240 emit_insn (gen_rtx_SET (dest, const0_rtx));
38244 else if (value == mask)
38246 if (!rtx_equal_p (dest, op1))
38247 emit_insn (gen_rtx_SET (dest, op1));
38252 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38253 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38254 else if (code == IOR || code == XOR)
38258 if (!rtx_equal_p (dest, op1))
38259 emit_insn (gen_rtx_SET (dest, op1));
38265 if (code == AND && mode == SImode
38266 && !complement_final_p && !complement_op1_p && !complement_op2_p)
38268 emit_insn (gen_andsi3 (dest, op1, op2));
38272 if (complement_op1_p)
38273 op1 = gen_rtx_NOT (mode, op1);
38275 if (complement_op2_p)
38276 op2 = gen_rtx_NOT (mode, op2);
38278 /* For canonical RTL, if only one arm is inverted it is the first. */
38279 if (!complement_op1_p && complement_op2_p)
38280 std::swap (op1, op2);
38282 bool_rtx = ((code == NOT)
38283 ? gen_rtx_NOT (mode, op1)
38284 : gen_rtx_fmt_ee (code, mode, op1, op2));
38286 if (complement_final_p)
38287 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
38289 emit_insn (gen_rtx_SET (dest, bool_rtx));
38292 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38293 operations are split immediately during RTL generation to allow for more
38294 optimizations of the AND/IOR/XOR.
38296 OPERANDS is an array containing the destination and two input operands.
38297 CODE is the base operation (AND, IOR, XOR, NOT).
38298 MODE is the machine mode.
38299 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38300 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38301 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38302 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38303 formation of the AND instructions. */
38306 rs6000_split_logical_di (rtx operands[3],
38307 enum rtx_code code,
38308 bool complement_final_p,
38309 bool complement_op1_p,
38310 bool complement_op2_p)
38312 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
38313 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
38314 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
38315 enum hi_lo { hi = 0, lo = 1 };
38316 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
38319 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
38320 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
38321 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
38322 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
38325 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
38328 if (!CONST_INT_P (operands[2]))
38330 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
38331 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
38335 HOST_WIDE_INT value = INTVAL (operands[2]);
38336 HOST_WIDE_INT value_hi_lo[2];
38338 gcc_assert (!complement_final_p);
38339 gcc_assert (!complement_op1_p);
38340 gcc_assert (!complement_op2_p);
38342 value_hi_lo[hi] = value >> 32;
38343 value_hi_lo[lo] = value & lower_32bits;
38345 for (i = 0; i < 2; i++)
38347 HOST_WIDE_INT sub_value = value_hi_lo[i];
38349 if (sub_value & sign_bit)
38350 sub_value |= upper_32bits;
38352 op2_hi_lo[i] = GEN_INT (sub_value);
38354 /* If this is an AND instruction, check to see if we need to load
38355 the value in a register. */
38356 if (code == AND && sub_value != -1 && sub_value != 0
38357 && !and_operand (op2_hi_lo[i], SImode))
38358 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
38363 for (i = 0; i < 2; i++)
38365 /* Split large IOR/XOR operations. */
38366 if ((code == IOR || code == XOR)
38367 && CONST_INT_P (op2_hi_lo[i])
38368 && !complement_final_p
38369 && !complement_op1_p
38370 && !complement_op2_p
38371 && !logical_const_operand (op2_hi_lo[i], SImode))
38373 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
38374 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
38375 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
38376 rtx tmp = gen_reg_rtx (SImode);
38378 /* Make sure the constant is sign extended. */
38379 if ((hi_16bits & sign_bit) != 0)
38380 hi_16bits |= upper_32bits;
38382 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
38383 code, SImode, false, false, false);
38385 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
38386 code, SImode, false, false, false);
38389 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
38390 code, SImode, complement_final_p,
38391 complement_op1_p, complement_op2_p);
38397 /* Split the insns that make up boolean operations operating on multiple GPR
38398 registers. The boolean MD patterns ensure that the inputs either are
38399 exactly the same as the output registers, or there is no overlap.
38401 OPERANDS is an array containing the destination and two input operands.
38402 CODE is the base operation (AND, IOR, XOR, NOT).
38403 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38404 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38405 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38408 rs6000_split_logical (rtx operands[3],
38409 enum rtx_code code,
38410 bool complement_final_p,
38411 bool complement_op1_p,
38412 bool complement_op2_p)
38414 machine_mode mode = GET_MODE (operands[0]);
38415 machine_mode sub_mode;
38417 int sub_size, regno0, regno1, nregs, i;
38419 /* If this is DImode, use the specialized version that can run before
38420 register allocation. */
38421 if (mode == DImode && !TARGET_POWERPC64)
38423 rs6000_split_logical_di (operands, code, complement_final_p,
38424 complement_op1_p, complement_op2_p);
38430 op2 = (code == NOT) ? NULL_RTX : operands[2];
38431 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
38432 sub_size = GET_MODE_SIZE (sub_mode);
38433 regno0 = REGNO (op0);
38434 regno1 = REGNO (op1);
38436 gcc_assert (reload_completed);
38437 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38438 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
38440 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
38441 gcc_assert (nregs > 1);
38443 if (op2 && REG_P (op2))
38444 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
38446 for (i = 0; i < nregs; i++)
38448 int offset = i * sub_size;
38449 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
38450 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
38451 rtx sub_op2 = ((code == NOT)
38453 : simplify_subreg (sub_mode, op2, mode, offset));
38455 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
38456 complement_final_p, complement_op1_p,
38464 /* Return true if the peephole2 can combine a load involving a combination of
38465 an addis instruction and a load with an offset that can be fused together on
38469 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
38470 rtx addis_value, /* addis value. */
38471 rtx target, /* target register that is loaded. */
38472 rtx mem) /* bottom part of the memory addr. */
38477 /* Validate arguments. */
38478 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
38481 if (!base_reg_operand (target, GET_MODE (target)))
38484 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
38487 /* Allow sign/zero extension. */
38488 if (GET_CODE (mem) == ZERO_EXTEND
38489 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
38490 mem = XEXP (mem, 0);
38495 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
38498 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
38499 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
38502 /* Validate that the register used to load the high value is either the
38503 register being loaded, or we can safely replace its use.
38505 This function is only called from the peephole2 pass and we assume that
38506 there are 2 instructions in the peephole (addis and load), so we want to
38507 check if the target register was not used in the memory address and the
38508 register to hold the addis result is dead after the peephole. */
38509 if (REGNO (addis_reg) != REGNO (target))
38511 if (reg_mentioned_p (target, mem))
38514 if (!peep2_reg_dead_p (2, addis_reg))
38517 /* If the target register being loaded is the stack pointer, we must
38518 avoid loading any other value into it, even temporarily. */
38519 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
38523 base_reg = XEXP (addr, 0);
38524 return REGNO (addis_reg) == REGNO (base_reg);
38527 /* During the peephole2 pass, adjust and expand the insns for a load fusion
38528 sequence. We adjust the addis register to use the target register. If the
38529 load sign extends, we adjust the code to do the zero extending load, and an
38530 explicit sign extension later since the fusion only covers zero extending
38534 operands[0] register set with addis (to be replaced with target)
38535 operands[1] value set via addis
38536 operands[2] target register being loaded
38537 operands[3] D-form memory reference using operands[0]. */
38540 expand_fusion_gpr_load (rtx *operands)
38542 rtx addis_value = operands[1];
38543 rtx target = operands[2];
38544 rtx orig_mem = operands[3];
38545 rtx new_addr, new_mem, orig_addr, offset;
38546 enum rtx_code plus_or_lo_sum;
38547 machine_mode target_mode = GET_MODE (target);
38548 machine_mode extend_mode = target_mode;
38549 machine_mode ptr_mode = Pmode;
38550 enum rtx_code extend = UNKNOWN;
38552 if (GET_CODE (orig_mem) == ZERO_EXTEND
38553 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
38555 extend = GET_CODE (orig_mem);
38556 orig_mem = XEXP (orig_mem, 0);
38557 target_mode = GET_MODE (orig_mem);
38560 gcc_assert (MEM_P (orig_mem));
38562 orig_addr = XEXP (orig_mem, 0);
38563 plus_or_lo_sum = GET_CODE (orig_addr);
38564 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
38566 offset = XEXP (orig_addr, 1);
38567 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
38568 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
38570 if (extend != UNKNOWN)
38571 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
38573 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
38574 UNSPEC_FUSION_GPR);
38575 emit_insn (gen_rtx_SET (target, new_mem));
38577 if (extend == SIGN_EXTEND)
38579 int sub_off = ((BYTES_BIG_ENDIAN)
38580 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
38583 = simplify_subreg (target_mode, target, extend_mode, sub_off);
38585 emit_insn (gen_rtx_SET (target,
38586 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
38592 /* Emit the addis instruction that will be part of a fused instruction
38596 emit_fusion_addis (rtx target, rtx addis_value)
38599 const char *addis_str = NULL;
38601 /* Emit the addis instruction. */
38602 fuse_ops[0] = target;
38603 if (satisfies_constraint_L (addis_value))
38605 fuse_ops[1] = addis_value;
38606 addis_str = "lis %0,%v1";
38609 else if (GET_CODE (addis_value) == PLUS)
38611 rtx op0 = XEXP (addis_value, 0);
38612 rtx op1 = XEXP (addis_value, 1);
38614 if (REG_P (op0) && CONST_INT_P (op1)
38615 && satisfies_constraint_L (op1))
38619 addis_str = "addis %0,%1,%v2";
38623 else if (GET_CODE (addis_value) == HIGH)
38625 rtx value = XEXP (addis_value, 0);
38626 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
38628 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
38629 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
38631 addis_str = "addis %0,%2,%1@toc@ha";
38633 else if (TARGET_XCOFF)
38634 addis_str = "addis %0,%1@u(%2)";
38637 gcc_unreachable ();
38640 else if (GET_CODE (value) == PLUS)
38642 rtx op0 = XEXP (value, 0);
38643 rtx op1 = XEXP (value, 1);
38645 if (GET_CODE (op0) == UNSPEC
38646 && XINT (op0, 1) == UNSPEC_TOCREL
38647 && CONST_INT_P (op1))
38649 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
38650 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
38653 addis_str = "addis %0,%2,%1+%3@toc@ha";
38655 else if (TARGET_XCOFF)
38656 addis_str = "addis %0,%1+%3@u(%2)";
38659 gcc_unreachable ();
38663 else if (satisfies_constraint_L (value))
38665 fuse_ops[1] = value;
38666 addis_str = "lis %0,%v1";
38669 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
38671 fuse_ops[1] = value;
38672 addis_str = "lis %0,%1@ha";
38677 fatal_insn ("Could not generate addis value for fusion", addis_value);
38679 output_asm_insn (addis_str, fuse_ops);
38682 /* Emit a D-form load or store instruction that is the second instruction
38683 of a fusion sequence. */
38686 emit_fusion_load (rtx load_reg, rtx addis_reg, rtx offset, const char *insn_str)
38689 char insn_template[80];
38691 fuse_ops[0] = load_reg;
38692 fuse_ops[1] = addis_reg;
38694 if (CONST_INT_P (offset) && satisfies_constraint_I (offset))
38696 sprintf (insn_template, "%s %%0,%%2(%%1)", insn_str);
38697 fuse_ops[2] = offset;
38698 output_asm_insn (insn_template, fuse_ops);
38701 else if (GET_CODE (offset) == UNSPEC
38702 && XINT (offset, 1) == UNSPEC_TOCREL)
38705 sprintf (insn_template, "%s %%0,%%2@toc@l(%%1)", insn_str);
38707 else if (TARGET_XCOFF)
38708 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38711 gcc_unreachable ();
38713 fuse_ops[2] = XVECEXP (offset, 0, 0);
38714 output_asm_insn (insn_template, fuse_ops);
38717 else if (GET_CODE (offset) == PLUS
38718 && GET_CODE (XEXP (offset, 0)) == UNSPEC
38719 && XINT (XEXP (offset, 0), 1) == UNSPEC_TOCREL
38720 && CONST_INT_P (XEXP (offset, 1)))
38722 rtx tocrel_unspec = XEXP (offset, 0);
38724 sprintf (insn_template, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str);
38726 else if (TARGET_XCOFF)
38727 sprintf (insn_template, "%s %%0,%%2+%%3@l(%%1)", insn_str);
38730 gcc_unreachable ();
38732 fuse_ops[2] = XVECEXP (tocrel_unspec, 0, 0);
38733 fuse_ops[3] = XEXP (offset, 1);
38734 output_asm_insn (insn_template, fuse_ops);
38737 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (offset))
38739 sprintf (insn_template, "%s %%0,%%2@l(%%1)", insn_str);
38741 fuse_ops[2] = offset;
38742 output_asm_insn (insn_template, fuse_ops);
38746 fatal_insn ("Unable to generate load/store offset for fusion", offset);
38751 /* Given an address, convert it into the addis and load offset parts. Addresses
38752 created during the peephole2 process look like:
38753 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
38754 (unspec [(...)] UNSPEC_TOCREL)) */
38757 fusion_split_address (rtx addr, rtx *p_hi, rtx *p_lo)
38761 if (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
38763 hi = XEXP (addr, 0);
38764 lo = XEXP (addr, 1);
38767 gcc_unreachable ();
38773 /* Return a string to fuse an addis instruction with a gpr load to the same
38774 register that we loaded up the addis instruction. The address that is used
38775 is the logical address that was formed during peephole2:
38776 (lo_sum (high) (low-part))
38778 The code is complicated, so we call output_asm_insn directly, and just
38782 emit_fusion_gpr_load (rtx target, rtx mem)
38787 const char *load_str = NULL;
38790 if (GET_CODE (mem) == ZERO_EXTEND)
38791 mem = XEXP (mem, 0);
38793 gcc_assert (REG_P (target) && MEM_P (mem));
38795 addr = XEXP (mem, 0);
38796 fusion_split_address (addr, &addis_value, &load_offset);
38798 /* Now emit the load instruction to the same register. */
38799 mode = GET_MODE (mem);
38817 gcc_assert (TARGET_POWERPC64);
38822 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target, mem));
38825 /* Emit the addis instruction. */
38826 emit_fusion_addis (target, addis_value);
38828 /* Emit the D-form load instruction. */
38829 emit_fusion_load (target, target, load_offset, load_str);
38835 #ifdef RS6000_GLIBC_ATOMIC_FENV
38836 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
38837 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
38840 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
38843 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
38845 if (!TARGET_HARD_FLOAT)
38847 #ifdef RS6000_GLIBC_ATOMIC_FENV
38848 if (atomic_hold_decl == NULL_TREE)
38851 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38852 get_identifier ("__atomic_feholdexcept"),
38853 build_function_type_list (void_type_node,
38854 double_ptr_type_node,
38856 TREE_PUBLIC (atomic_hold_decl) = 1;
38857 DECL_EXTERNAL (atomic_hold_decl) = 1;
38860 if (atomic_clear_decl == NULL_TREE)
38863 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38864 get_identifier ("__atomic_feclearexcept"),
38865 build_function_type_list (void_type_node,
38867 TREE_PUBLIC (atomic_clear_decl) = 1;
38868 DECL_EXTERNAL (atomic_clear_decl) = 1;
38871 tree const_double = build_qualified_type (double_type_node,
38873 tree const_double_ptr = build_pointer_type (const_double);
38874 if (atomic_update_decl == NULL_TREE)
38877 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
38878 get_identifier ("__atomic_feupdateenv"),
38879 build_function_type_list (void_type_node,
38882 TREE_PUBLIC (atomic_update_decl) = 1;
38883 DECL_EXTERNAL (atomic_update_decl) = 1;
38886 tree fenv_var = create_tmp_var_raw (double_type_node);
38887 TREE_ADDRESSABLE (fenv_var) = 1;
38888 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
38890 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
38891 *clear = build_call_expr (atomic_clear_decl, 0);
38892 *update = build_call_expr (atomic_update_decl, 1,
38893 fold_convert (const_double_ptr, fenv_addr));
38898 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
38899 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
38900 tree call_mffs = build_call_expr (mffs, 0);
38902 /* Generates the equivalent of feholdexcept (&fenv_var)
38904 *fenv_var = __builtin_mffs ();
38906 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
38907 __builtin_mtfsf (0xff, fenv_hold); */
38909 /* Mask to clear everything except for the rounding modes and non-IEEE
38910 arithmetic flag. */
38911 const unsigned HOST_WIDE_INT hold_exception_mask =
38912 HOST_WIDE_INT_C (0xffffffff00000007);
38914 tree fenv_var = create_tmp_var_raw (double_type_node);
38916 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
38918 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
38919 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38920 build_int_cst (uint64_type_node,
38921 hold_exception_mask));
38923 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38926 tree hold_mtfsf = build_call_expr (mtfsf, 2,
38927 build_int_cst (unsigned_type_node, 0xff),
38930 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
38932 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
38934 double fenv_clear = __builtin_mffs ();
38935 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
38936 __builtin_mtfsf (0xff, fenv_clear); */
38938 /* Mask to clear everything except for the rounding modes and non-IEEE
38939 arithmetic flag. */
38940 const unsigned HOST_WIDE_INT clear_exception_mask =
38941 HOST_WIDE_INT_C (0xffffffff00000000);
38943 tree fenv_clear = create_tmp_var_raw (double_type_node);
38945 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
38947 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
38948 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
38950 build_int_cst (uint64_type_node,
38951 clear_exception_mask));
38953 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38954 fenv_clear_llu_and);
38956 tree clear_mtfsf = build_call_expr (mtfsf, 2,
38957 build_int_cst (unsigned_type_node, 0xff),
38960 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
38962 /* Generates the equivalent of feupdateenv (&fenv_var)
38964 double old_fenv = __builtin_mffs ();
38965 double fenv_update;
38966 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
38967 (*(uint64_t*)fenv_var 0x1ff80fff);
38968 __builtin_mtfsf (0xff, fenv_update); */
38970 const unsigned HOST_WIDE_INT update_exception_mask =
38971 HOST_WIDE_INT_C (0xffffffff1fffff00);
38972 const unsigned HOST_WIDE_INT new_exception_mask =
38973 HOST_WIDE_INT_C (0x1ff80fff);
38975 tree old_fenv = create_tmp_var_raw (double_type_node);
38976 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
38978 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
38979 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
38980 build_int_cst (uint64_type_node,
38981 update_exception_mask));
38983 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
38984 build_int_cst (uint64_type_node,
38985 new_exception_mask));
38987 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
38988 old_llu_and, new_llu_and);
38990 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
38993 tree update_mtfsf = build_call_expr (mtfsf, 2,
38994 build_int_cst (unsigned_type_node, 0xff),
38995 fenv_update_mtfsf);
38997 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
39001 rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
39003 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39005 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39006 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39008 /* The destination of the vmrgew instruction layout is:
39009 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39010 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39011 vmrgew instruction will be correct. */
39012 if (BYTES_BIG_ENDIAN)
39014 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp0, src1, src2,
39016 emit_insn (gen_vsx_xxpermdi_v2df_be (rtx_tmp1, src1, src2,
39021 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (3)));
39022 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (0)));
39025 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39026 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39028 emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
39029 emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
39031 if (BYTES_BIG_ENDIAN)
39032 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39034 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39038 rs6000_generate_float2_code (bool signed_convert, rtx dst, rtx src1, rtx src2)
39040 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39042 rtx_tmp0 = gen_reg_rtx (V2DImode);
39043 rtx_tmp1 = gen_reg_rtx (V2DImode);
39045 /* The destination of the vmrgew instruction layout is:
39046 rtx_tmp2[0] rtx_tmp3[0] rtx_tmp2[1] rtx_tmp3[0].
39047 Setup rtx_tmp0 and rtx_tmp1 to ensure the order of the elements after the
39048 vmrgew instruction will be correct. */
39049 if (BYTES_BIG_ENDIAN)
39051 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp0, src1, src2, GEN_INT (0)));
39052 emit_insn (gen_vsx_xxpermdi_v2di_be (rtx_tmp1, src1, src2, GEN_INT (3)));
39056 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp0, src1, src2, GEN_INT (3)));
39057 emit_insn (gen_vsx_xxpermdi_v2di (rtx_tmp1, src1, src2, GEN_INT (0)));
39060 rtx_tmp2 = gen_reg_rtx (V4SFmode);
39061 rtx_tmp3 = gen_reg_rtx (V4SFmode);
39063 if (signed_convert)
39065 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp2, rtx_tmp0));
39066 emit_insn (gen_vsx_xvcvsxdsp (rtx_tmp3, rtx_tmp1));
39070 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp2, rtx_tmp0));
39071 emit_insn (gen_vsx_xvcvuxdsp (rtx_tmp3, rtx_tmp1));
39074 if (BYTES_BIG_ENDIAN)
39075 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
39077 emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp3, rtx_tmp2));
39081 rs6000_generate_vsigned2_code (bool signed_convert, rtx dst, rtx src1,
39084 rtx rtx_tmp0, rtx_tmp1, rtx_tmp2, rtx_tmp3;
39086 rtx_tmp0 = gen_reg_rtx (V2DFmode);
39087 rtx_tmp1 = gen_reg_rtx (V2DFmode);
39089 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp0, src1, src2, GEN_INT (0)));
39090 emit_insn (gen_vsx_xxpermdi_v2df (rtx_tmp1, src1, src2, GEN_INT (3)));
39092 rtx_tmp2 = gen_reg_rtx (V4SImode);
39093 rtx_tmp3 = gen_reg_rtx (V4SImode);
39095 if (signed_convert)
39097 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp2, rtx_tmp0));
39098 emit_insn (gen_vsx_xvcvdpsxws (rtx_tmp3, rtx_tmp1));
39102 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp2, rtx_tmp0));
39103 emit_insn (gen_vsx_xvcvdpuxws (rtx_tmp3, rtx_tmp1));
39106 emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
39109 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
39112 rs6000_optab_supported_p (int op, machine_mode mode1, machine_mode,
39113 optimization_type opt_type)
39118 return (opt_type == OPTIMIZE_FOR_SPEED
39119 && RS6000_RECIP_AUTO_RSQRTE_P (mode1));
39126 /* Implement TARGET_CONSTANT_ALIGNMENT. */
39128 static HOST_WIDE_INT
39129 rs6000_constant_alignment (const_tree exp, HOST_WIDE_INT align)
39131 if (TREE_CODE (exp) == STRING_CST
39132 && (STRICT_ALIGNMENT || !optimize_size))
39133 return MAX (align, BITS_PER_WORD);
39137 /* Implement TARGET_STARTING_FRAME_OFFSET. */
39139 static HOST_WIDE_INT
39140 rs6000_starting_frame_offset (void)
39142 if (FRAME_GROWS_DOWNWARD)
39144 return RS6000_STARTING_FRAME_OFFSET;
39148 /* Create an alias for a mangled name where we have changed the mangling (in
39149 GCC 8.1, we used U10__float128, and now we use u9__ieee128). This is called
39150 via the target hook TARGET_ASM_GLOBALIZE_DECL_NAME. */
39152 #if TARGET_ELF && RS6000_WEAK
39154 rs6000_globalize_decl_name (FILE * stream, tree decl)
39156 const char *name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
39158 targetm.asm_out.globalize_label (stream, name);
39160 if (rs6000_passes_ieee128 && name[0] == '_' && name[1] == 'Z')
39162 tree save_asm_name = DECL_ASSEMBLER_NAME (decl);
39163 const char *old_name;
39165 ieee128_mangling_gcc_8_1 = true;
39166 lang_hooks.set_decl_assembler_name (decl);
39167 old_name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
39168 SET_DECL_ASSEMBLER_NAME (decl, save_asm_name);
39169 ieee128_mangling_gcc_8_1 = false;
39171 if (strcmp (name, old_name) != 0)
39173 fprintf (stream, "\t.weak %s\n", old_name);
39174 fprintf (stream, "\t.set %s,%s\n", old_name, name);
39181 /* On 64-bit Linux and Freebsd systems, possibly switch the long double library
39182 function names from <foo>l to <foo>f128 if the default long double type is
39183 IEEE 128-bit. Typically, with the C and C++ languages, the standard math.h
39184 include file switches the names on systems that support long double as IEEE
39185 128-bit, but that doesn't work if the user uses __builtin_<foo>l directly.
39186 In the future, glibc will export names like __ieee128_sinf128 and we can
39187 switch to using those instead of using sinf128, which pollutes the user's
39190 This will switch the names for Fortran math functions as well (which doesn't
39191 use math.h). However, Fortran needs other changes to the compiler and
39192 library before you can switch the real*16 type at compile time.
39194 We use the TARGET_MANGLE_DECL_ASSEMBLER_NAME hook to change this name. We
39195 only do this if the default is that long double is IBM extended double, and
39196 the user asked for IEEE 128-bit. */
39199 rs6000_mangle_decl_assembler_name (tree decl, tree id)
39201 if (!TARGET_IEEEQUAD_DEFAULT && TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
39202 && TREE_CODE (decl) == FUNCTION_DECL && DECL_IS_BUILTIN (decl) )
39204 size_t len = IDENTIFIER_LENGTH (id);
39205 const char *name = IDENTIFIER_POINTER (id);
39207 if (name[len - 1] == 'l')
39209 bool uses_ieee128_p = false;
39210 tree type = TREE_TYPE (decl);
39211 machine_mode ret_mode = TYPE_MODE (type);
39213 /* See if the function returns a IEEE 128-bit floating point type or
39215 if (ret_mode == TFmode || ret_mode == TCmode)
39216 uses_ieee128_p = true;
39219 function_args_iterator args_iter;
39222 /* See if the function passes a IEEE 128-bit floating point type
39223 or complex type. */
39224 FOREACH_FUNCTION_ARGS (type, arg, args_iter)
39226 machine_mode arg_mode = TYPE_MODE (arg);
39227 if (arg_mode == TFmode || arg_mode == TCmode)
39229 uses_ieee128_p = true;
39235 /* If we passed or returned an IEEE 128-bit floating point type,
39236 change the name. */
39237 if (uses_ieee128_p)
39239 char *name2 = (char *) alloca (len + 4);
39240 memcpy (name2, name, len - 1);
39241 strcpy (name2 + len - 1, "f128");
39242 id = get_identifier (name2);
39251 struct gcc_target targetm = TARGET_INITIALIZER;
39253 #include "gt-rs6000.h"