1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
56 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
59 #ifndef TARGET_NO_PROTOTYPE
60 #define TARGET_NO_PROTOTYPE 0
63 #define EASY_VECTOR_15(n, x, y) ((n) >= -16 && (n) <= 15 \
64 && easy_vector_same (x, y))
66 #define EASY_VECTOR_15_ADD_SELF(n, x, y) ((n) >= 0x10 && (n) <= 0x1e \
68 && easy_vector_same (x, y))
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int toc_save_p; /* true if the TOC needs to be saved */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
116 /* Target cpu type */
118 enum processor_type rs6000_cpu;
119 struct rs6000_cpu_select rs6000_select[3] =
121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
127 /* Support adjust_priority scheduler hook
128 and -mprioritize-restricted-insns= option. */
129 const char *rs6000_sched_restricted_insns_priority_str;
130 int rs6000_sched_restricted_insns_priority;
132 /* Support for -msched-costly-dep option. */
133 const char *rs6000_sched_costly_dep_str;
134 enum rs6000_dependence_cost rs6000_sched_costly_dep;
136 /* Support for -minsert-sched-nops option. */
137 const char *rs6000_sched_insert_nops_str;
138 enum rs6000_nop_insertion rs6000_sched_insert_nops;
140 /* Size of long double */
141 const char *rs6000_long_double_size_string;
142 int rs6000_long_double_type_size;
144 /* Whether -mabi=altivec has appeared */
145 int rs6000_altivec_abi;
147 /* Whether VRSAVE instructions should be generated. */
148 int rs6000_altivec_vrsave;
150 /* String from -mvrsave= option. */
151 const char *rs6000_altivec_vrsave_string;
153 /* Nonzero if we want SPE ABI extensions. */
156 /* Whether isel instructions should be generated. */
159 /* Whether SPE simd instructions should be generated. */
162 /* Nonzero if floating point operations are done in the GPRs. */
163 int rs6000_float_gprs = 0;
165 /* String from -mfloat-gprs=. */
166 const char *rs6000_float_gprs_string;
168 /* String from -misel=. */
169 const char *rs6000_isel_string;
171 /* String from -mspe=. */
172 const char *rs6000_spe_string;
174 /* Set to nonzero once AIX common-mode calls have been defined. */
175 static GTY(()) int common_mode_defined;
177 /* Save information from a "cmpxx" operation until the branch or scc is
179 rtx rs6000_compare_op0, rs6000_compare_op1;
180 int rs6000_compare_fp_p;
182 /* Label number of label created for -mrelocatable, to call to so we can
183 get the address of the GOT section */
184 int rs6000_pic_labelno;
187 /* Which abi to adhere to */
188 const char *rs6000_abi_name;
190 /* Semantics of the small data area */
191 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
193 /* Which small data model to use */
194 const char *rs6000_sdata_name = (char *)0;
196 /* Counter for labels which are to be placed in .fixup. */
197 int fixuplabelno = 0;
200 /* Bit size of immediate TLS offsets and string from which it is decoded. */
201 int rs6000_tls_size = 32;
202 const char *rs6000_tls_size_string;
204 /* ABI enumeration available for subtarget to use. */
205 enum rs6000_abi rs6000_current_abi;
207 /* ABI string from -mabi= option. */
208 const char *rs6000_abi_string;
211 const char *rs6000_debug_name;
212 int rs6000_debug_stack; /* debug stack applications */
213 int rs6000_debug_arg; /* debug argument handling */
216 static GTY(()) tree opaque_V2SI_type_node;
217 static GTY(()) tree opaque_V2SF_type_node;
218 static GTY(()) tree opaque_p_V2SI_type_node;
220 const char *rs6000_traceback_name;
222 traceback_default = 0,
228 /* Flag to say the TOC is initialized */
230 char toc_label_name[10];
232 /* Alias set for saves and restores from the rs6000 stack. */
233 static int rs6000_sr_alias_set;
235 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
236 The only place that looks at this is rs6000_set_default_type_attributes;
237 everywhere else should rely on the presence or absence of a longcall
238 attribute on the function declaration. */
239 int rs6000_default_long_calls;
240 const char *rs6000_longcall_switch;
242 /* Control alignment for fields within structures. */
243 /* String from -malign-XXXXX. */
244 const char *rs6000_alignment_string;
245 int rs6000_alignment_flags;
247 struct builtin_description
249 /* mask is not const because we're going to alter it below. This
250 nonsense will go away when we rewrite the -march infrastructure
251 to give us more target flag bits. */
253 const enum insn_code icode;
254 const char *const name;
255 const enum rs6000_builtins code;
258 static bool rs6000_function_ok_for_sibcall (tree, tree);
259 static int num_insns_constant_wide (HOST_WIDE_INT);
260 static void validate_condition_mode (enum rtx_code, enum machine_mode);
261 static rtx rs6000_generate_compare (enum rtx_code);
262 static void rs6000_maybe_dead (rtx);
263 static void rs6000_emit_stack_tie (void);
264 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
265 static rtx spe_synthesize_frame_save (rtx);
266 static bool spe_func_has_64bit_regs_p (void);
267 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
269 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
270 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
271 static unsigned rs6000_hash_constant (rtx);
272 static unsigned toc_hash_function (const void *);
273 static int toc_hash_eq (const void *, const void *);
274 static int constant_pool_expr_1 (rtx, int *, int *);
275 static bool constant_pool_expr_p (rtx);
276 static bool toc_relative_expr_p (rtx);
277 static bool legitimate_small_data_p (enum machine_mode, rtx);
278 static bool legitimate_offset_address_p (enum machine_mode, rtx, int);
279 static bool legitimate_indexed_address_p (rtx, int);
280 static bool legitimate_indirect_address_p (rtx, int);
281 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
282 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
283 static struct machine_function * rs6000_init_machine_status (void);
284 static bool rs6000_assemble_integer (rtx, unsigned int, int);
285 #ifdef HAVE_GAS_HIDDEN
286 static void rs6000_assemble_visibility (tree, int);
288 static int rs6000_ra_ever_killed (void);
289 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
290 extern const struct attribute_spec rs6000_attribute_table[];
291 static void rs6000_set_default_type_attributes (tree);
292 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
293 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
294 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
296 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
297 static bool rs6000_return_in_memory (tree, tree);
298 static void rs6000_file_start (void);
300 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
301 static void rs6000_elf_asm_out_constructor (rtx, int);
302 static void rs6000_elf_asm_out_destructor (rtx, int);
303 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
304 static void rs6000_elf_unique_section (tree, int);
305 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
306 unsigned HOST_WIDE_INT);
307 static void rs6000_elf_encode_section_info (tree, rtx, int)
309 static bool rs6000_elf_in_small_data_p (tree);
312 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
313 static void rs6000_xcoff_asm_named_section (const char *, unsigned int);
314 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
315 static void rs6000_xcoff_unique_section (tree, int);
316 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
317 unsigned HOST_WIDE_INT);
318 static const char * rs6000_xcoff_strip_name_encoding (const char *);
319 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
320 static void rs6000_xcoff_file_start (void);
321 static void rs6000_xcoff_file_end (void);
324 static bool rs6000_binds_local_p (tree);
326 static int rs6000_use_dfa_pipeline_interface (void);
327 static int rs6000_variable_issue (FILE *, int, rtx, int);
328 static bool rs6000_rtx_costs (rtx, int, int, int *);
329 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
330 static bool is_microcoded_insn (rtx);
331 static int is_dispatch_slot_restricted (rtx);
332 static bool is_cracked_insn (rtx);
333 static bool is_branch_slot_insn (rtx);
334 static int rs6000_adjust_priority (rtx, int);
335 static int rs6000_issue_rate (void);
336 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
337 static rtx get_next_active_insn (rtx, rtx);
338 static bool insn_terminates_group_p (rtx , enum group_termination);
339 static bool is_costly_group (rtx *, rtx);
340 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
341 static int redefine_groups (FILE *, int, rtx, rtx);
342 static int pad_groups (FILE *, int, rtx, rtx);
343 static void rs6000_sched_finish (FILE *, int);
344 static int rs6000_use_sched_lookahead (void);
346 static void rs6000_init_builtins (void);
347 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
348 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
349 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
350 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
351 static void altivec_init_builtins (void);
352 static void rs6000_common_init_builtins (void);
353 static void rs6000_init_libfuncs (void);
355 static void enable_mask_for_builtins (struct builtin_description *, int,
356 enum rs6000_builtins,
357 enum rs6000_builtins);
358 static void spe_init_builtins (void);
359 static rtx spe_expand_builtin (tree, rtx, bool *);
360 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
361 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
362 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
363 static rs6000_stack_t *rs6000_stack_info (void);
364 static void debug_stack_info (rs6000_stack_t *);
366 static rtx altivec_expand_builtin (tree, rtx, bool *);
367 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
368 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
369 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
370 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
371 static rtx altivec_expand_predicate_builtin (enum insn_code,
372 const char *, tree, rtx);
373 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
374 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
375 static void rs6000_parse_abi_options (void);
376 static void rs6000_parse_alignment_option (void);
377 static void rs6000_parse_tls_size_option (void);
378 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
379 static int first_altivec_reg_to_save (void);
380 static unsigned int compute_vrsave_mask (void);
381 static void is_altivec_return_reg (rtx, void *);
382 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
383 int easy_vector_constant (rtx, enum machine_mode);
384 static int easy_vector_same (rtx, enum machine_mode);
385 static bool is_ev64_opaque_type (tree);
386 static rtx rs6000_dwarf_register_span (rtx);
387 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
388 static rtx rs6000_tls_get_addr (void);
389 static rtx rs6000_got_sym (void);
390 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
391 static const char *rs6000_get_some_local_dynamic_name (void);
392 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
393 static rtx rs6000_complex_function_value (enum machine_mode);
394 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
395 enum machine_mode, tree);
396 static rtx rs6000_mixed_function_arg (CUMULATIVE_ARGS *,
397 enum machine_mode, tree, int);
398 static void rs6000_move_block_from_reg(int regno, rtx x, int nregs);
399 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
400 enum machine_mode, tree,
403 static void macho_branch_islands (void);
404 static void add_compiler_branch_island (tree, tree, int);
405 static int no_previous_def (tree function_name);
406 static tree get_prev_label (tree function_name);
409 static tree rs6000_build_builtin_va_list (void);
411 /* Hash table stuff for keeping track of TOC entries. */
413 struct toc_hash_struct GTY(())
415 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
416 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
418 enum machine_mode key_mode;
422 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
424 /* Default register names. */
425 char rs6000_reg_names[][8] =
427 "0", "1", "2", "3", "4", "5", "6", "7",
428 "8", "9", "10", "11", "12", "13", "14", "15",
429 "16", "17", "18", "19", "20", "21", "22", "23",
430 "24", "25", "26", "27", "28", "29", "30", "31",
431 "0", "1", "2", "3", "4", "5", "6", "7",
432 "8", "9", "10", "11", "12", "13", "14", "15",
433 "16", "17", "18", "19", "20", "21", "22", "23",
434 "24", "25", "26", "27", "28", "29", "30", "31",
435 "mq", "lr", "ctr","ap",
436 "0", "1", "2", "3", "4", "5", "6", "7",
438 /* AltiVec registers. */
439 "0", "1", "2", "3", "4", "5", "6", "7",
440 "8", "9", "10", "11", "12", "13", "14", "15",
441 "16", "17", "18", "19", "20", "21", "22", "23",
442 "24", "25", "26", "27", "28", "29", "30", "31",
448 #ifdef TARGET_REGNAMES
449 static const char alt_reg_names[][8] =
451 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
452 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
453 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
454 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
455 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
456 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
457 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
458 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
459 "mq", "lr", "ctr", "ap",
460 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
462 /* AltiVec registers. */
463 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
464 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
465 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
466 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
473 #ifndef MASK_STRICT_ALIGN
474 #define MASK_STRICT_ALIGN 0
476 #ifndef TARGET_PROFILE_KERNEL
477 #define TARGET_PROFILE_KERNEL 0
480 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
481 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
483 /* Return 1 for a symbol ref for a thread-local storage symbol. */
484 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
485 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
487 /* Initialize the GCC target structure. */
488 #undef TARGET_ATTRIBUTE_TABLE
489 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
490 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
491 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
493 #undef TARGET_ASM_ALIGNED_DI_OP
494 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
496 /* Default unaligned ops are only provided for ELF. Find the ops needed
497 for non-ELF systems. */
498 #ifndef OBJECT_FORMAT_ELF
500 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
502 #undef TARGET_ASM_UNALIGNED_HI_OP
503 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
504 #undef TARGET_ASM_UNALIGNED_SI_OP
505 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
506 #undef TARGET_ASM_UNALIGNED_DI_OP
507 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
510 #undef TARGET_ASM_UNALIGNED_HI_OP
511 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
512 #undef TARGET_ASM_UNALIGNED_SI_OP
513 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
517 /* This hook deals with fixups for relocatable code and DI-mode objects
519 #undef TARGET_ASM_INTEGER
520 #define TARGET_ASM_INTEGER rs6000_assemble_integer
522 #ifdef HAVE_GAS_HIDDEN
523 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
524 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
527 #undef TARGET_HAVE_TLS
528 #define TARGET_HAVE_TLS HAVE_AS_TLS
530 #undef TARGET_CANNOT_FORCE_CONST_MEM
531 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
533 #undef TARGET_ASM_FUNCTION_PROLOGUE
534 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
535 #undef TARGET_ASM_FUNCTION_EPILOGUE
536 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
538 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
539 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE rs6000_use_dfa_pipeline_interface
540 #undef TARGET_SCHED_VARIABLE_ISSUE
541 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
543 #undef TARGET_SCHED_ISSUE_RATE
544 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
545 #undef TARGET_SCHED_ADJUST_COST
546 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
547 #undef TARGET_SCHED_ADJUST_PRIORITY
548 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
549 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
550 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
551 #undef TARGET_SCHED_FINISH
552 #define TARGET_SCHED_FINISH rs6000_sched_finish
554 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
555 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
557 #undef TARGET_INIT_BUILTINS
558 #define TARGET_INIT_BUILTINS rs6000_init_builtins
560 #undef TARGET_EXPAND_BUILTIN
561 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
563 #undef TARGET_INIT_LIBFUNCS
564 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
567 #undef TARGET_BINDS_LOCAL_P
568 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
571 #undef TARGET_ASM_OUTPUT_MI_THUNK
572 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
574 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
575 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
577 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
578 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
580 #undef TARGET_RTX_COSTS
581 #define TARGET_RTX_COSTS rs6000_rtx_costs
582 #undef TARGET_ADDRESS_COST
583 #define TARGET_ADDRESS_COST hook_int_rtx_0
585 #undef TARGET_VECTOR_OPAQUE_P
586 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
588 #undef TARGET_DWARF_REGISTER_SPAN
589 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
591 /* On rs6000, function arguments are promoted, as are function return
593 #undef TARGET_PROMOTE_FUNCTION_ARGS
594 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
595 #undef TARGET_PROMOTE_FUNCTION_RETURN
596 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
598 /* Structure return values are passed as an extra parameter. */
599 #undef TARGET_STRUCT_VALUE_RTX
600 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
602 #undef TARGET_RETURN_IN_MEMORY
603 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
605 #undef TARGET_SETUP_INCOMING_VARARGS
606 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
608 /* Always strict argument naming on rs6000. */
609 #undef TARGET_STRICT_ARGUMENT_NAMING
610 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
611 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
612 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
614 #undef TARGET_BUILD_BUILTIN_VA_LIST
615 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
617 struct gcc_target targetm = TARGET_INITIALIZER;
619 /* Override command line options. Mostly we process the processor
620 type and sometimes adjust other TARGET_ options. */
623 rs6000_override_options (const char *default_cpu)
626 struct rs6000_cpu_select *ptr;
629 /* Simplifications for entries below. */
632 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
633 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
636 /* This table occasionally claims that a processor does not support
637 a particular feature even though it does, but the feature is slower
638 than the alternative. Thus, it shouldn't be relied on as a
639 complete description of the processor's support.
641 Please keep this list in order, and don't forget to update the
642 documentation in invoke.texi when adding a new processor or
646 const char *const name; /* Canonical processor name. */
647 const enum processor_type processor; /* Processor type enum value. */
648 const int target_enable; /* Target flags to enable. */
649 } const processor_target_table[]
650 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
651 {"403", PROCESSOR_PPC403,
652 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
653 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
654 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
655 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
656 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
657 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
658 {"601", PROCESSOR_PPC601,
659 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
660 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
661 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
662 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
663 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
664 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
665 {"620", PROCESSOR_PPC620, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
666 {"630", PROCESSOR_PPC630, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
667 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
668 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
669 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
670 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
671 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
672 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
673 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
674 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
675 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
676 {"970", PROCESSOR_POWER4,
677 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
678 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
679 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
680 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
681 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
682 {"G5", PROCESSOR_POWER4,
683 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
684 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
685 {"power2", PROCESSOR_POWER,
686 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
687 {"power3", PROCESSOR_PPC630, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
688 {"power4", PROCESSOR_POWER4, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
689 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
690 {"powerpc64", PROCESSOR_POWERPC64,
691 POWERPC_BASE_MASK | MASK_POWERPC64},
692 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
693 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
694 {"rios2", PROCESSOR_RIOS2,
695 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
696 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
697 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
698 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK},
701 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
703 /* Save current -mmultiple/-mno-multiple status. */
704 int multiple = TARGET_MULTIPLE;
705 /* Save current -mstring/-mno-string status. */
706 int string = TARGET_STRING;
708 /* Some OSs don't support saving the high part of 64-bit registers on
709 context switch. Other OSs don't support saving Altivec registers.
710 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
711 settings; if the user wants either, the user must explicitly specify
712 them and we won't interfere with the user's specification. */
715 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
716 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
717 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
720 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
721 #ifdef OS_MISSING_POWERPC64
722 if (OS_MISSING_POWERPC64)
723 set_masks &= ~MASK_POWERPC64;
725 #ifdef OS_MISSING_ALTIVEC
726 if (OS_MISSING_ALTIVEC)
727 set_masks &= ~MASK_ALTIVEC;
730 /* Identify the processor type. */
731 rs6000_select[0].string = default_cpu;
732 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
734 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
736 ptr = &rs6000_select[i];
737 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
739 for (j = 0; j < ptt_size; j++)
740 if (! strcmp (ptr->string, processor_target_table[j].name))
743 rs6000_cpu = processor_target_table[j].processor;
747 target_flags &= ~set_masks;
748 target_flags |= (processor_target_table[j].target_enable
755 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
762 /* If we are optimizing big endian systems for space, use the load/store
763 multiple and string instructions. */
764 if (BYTES_BIG_ENDIAN && optimize_size)
765 target_flags |= MASK_MULTIPLE | MASK_STRING;
767 /* If -mmultiple or -mno-multiple was explicitly used, don't
768 override with the processor default */
769 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
770 target_flags = (target_flags & ~MASK_MULTIPLE) | multiple;
772 /* If -mstring or -mno-string was explicitly used, don't override
773 with the processor default. */
774 if ((target_flags_explicit & MASK_STRING) != 0)
775 target_flags = (target_flags & ~MASK_STRING) | string;
777 /* Don't allow -mmultiple or -mstring on little endian systems
778 unless the cpu is a 750, because the hardware doesn't support the
779 instructions used in little endian mode, and causes an alignment
780 trap. The 750 does not cause an alignment trap (except when the
781 target is unaligned). */
783 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
787 target_flags &= ~MASK_MULTIPLE;
788 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
789 warning ("-mmultiple is not supported on little endian systems");
794 target_flags &= ~MASK_STRING;
795 if ((target_flags_explicit & MASK_STRING) != 0)
796 warning ("-mstring is not supported on little endian systems");
800 /* Set debug flags */
801 if (rs6000_debug_name)
803 if (! strcmp (rs6000_debug_name, "all"))
804 rs6000_debug_stack = rs6000_debug_arg = 1;
805 else if (! strcmp (rs6000_debug_name, "stack"))
806 rs6000_debug_stack = 1;
807 else if (! strcmp (rs6000_debug_name, "arg"))
808 rs6000_debug_arg = 1;
810 error ("unknown -mdebug-%s switch", rs6000_debug_name);
813 if (rs6000_traceback_name)
815 if (! strncmp (rs6000_traceback_name, "full", 4))
816 rs6000_traceback = traceback_full;
817 else if (! strncmp (rs6000_traceback_name, "part", 4))
818 rs6000_traceback = traceback_part;
819 else if (! strncmp (rs6000_traceback_name, "no", 2))
820 rs6000_traceback = traceback_none;
822 error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'",
823 rs6000_traceback_name);
826 /* Set size of long double */
827 rs6000_long_double_type_size = 64;
828 if (rs6000_long_double_size_string)
831 int size = strtol (rs6000_long_double_size_string, &tail, 10);
832 if (*tail != '\0' || (size != 64 && size != 128))
833 error ("Unknown switch -mlong-double-%s",
834 rs6000_long_double_size_string);
836 rs6000_long_double_type_size = size;
839 /* Handle -mabi= options. */
840 rs6000_parse_abi_options ();
842 /* Handle -malign-XXXXX option. */
843 rs6000_parse_alignment_option ();
845 /* Handle generic -mFOO=YES/NO options. */
846 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
847 &rs6000_altivec_vrsave);
848 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
850 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
851 rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string,
854 /* Handle -mtls-size option. */
855 rs6000_parse_tls_size_option ();
857 #ifdef SUBTARGET_OVERRIDE_OPTIONS
858 SUBTARGET_OVERRIDE_OPTIONS;
860 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
861 SUBSUBTARGET_OVERRIDE_OPTIONS;
866 /* The e500 does not have string instructions, and we set
867 MASK_STRING above when optimizing for size. */
868 if ((target_flags & MASK_STRING) != 0)
869 target_flags = target_flags & ~MASK_STRING;
871 /* No SPE means 64-bit long doubles, even if an E500. */
872 if (rs6000_spe_string != 0
873 && !strcmp (rs6000_spe_string, "no"))
874 rs6000_long_double_type_size = 64;
876 else if (rs6000_select[1].string != NULL)
878 /* For the powerpc-eabispe configuration, we set all these by
879 default, so let's unset them if we manually set another
880 CPU that is not the E500. */
881 if (rs6000_abi_string == 0)
883 if (rs6000_spe_string == 0)
885 if (rs6000_float_gprs_string == 0)
886 rs6000_float_gprs = 0;
887 if (rs6000_isel_string == 0)
889 if (rs6000_long_double_size_string == 0)
890 rs6000_long_double_type_size = 64;
893 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
894 using TARGET_OPTIONS to handle a toggle switch, but we're out of
895 bits in target_flags so TARGET_SWITCHES cannot be used.
896 Assumption here is that rs6000_longcall_switch points into the
897 text of the complete option, rather than being a copy, so we can
898 scan back for the presence or absence of the no- modifier. */
899 if (rs6000_longcall_switch)
901 const char *base = rs6000_longcall_switch;
902 while (base[-1] != 'm') base--;
904 if (*rs6000_longcall_switch != '\0')
905 error ("invalid option `%s'", base);
906 rs6000_default_long_calls = (base[0] != 'n');
909 /* Handle -mprioritize-restricted-insns option. */
910 rs6000_sched_restricted_insns_priority = DEFAULT_RESTRICTED_INSNS_PRIORITY;
911 if (rs6000_sched_restricted_insns_priority_str)
912 rs6000_sched_restricted_insns_priority =
913 atoi (rs6000_sched_restricted_insns_priority_str);
915 /* Handle -msched-costly-dep option. */
916 rs6000_sched_costly_dep = DEFAULT_SCHED_COSTLY_DEP;
917 if (rs6000_sched_costly_dep_str)
919 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
920 rs6000_sched_costly_dep = no_dep_costly;
921 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
922 rs6000_sched_costly_dep = all_deps_costly;
923 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
924 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
925 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
926 rs6000_sched_costly_dep = store_to_load_dep_costly;
928 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
931 /* Handle -minsert-sched-nops option. */
932 rs6000_sched_insert_nops = DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME;
933 if (rs6000_sched_insert_nops_str)
935 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
936 rs6000_sched_insert_nops = sched_finish_none;
937 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
938 rs6000_sched_insert_nops = sched_finish_pad_groups;
939 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
940 rs6000_sched_insert_nops = sched_finish_regroup_exact;
942 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
945 #ifdef TARGET_REGNAMES
946 /* If the user desires alternate register names, copy in the
947 alternate names now. */
949 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
952 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
953 If -maix-struct-return or -msvr4-struct-return was explicitly
954 used, don't override with the ABI default. */
955 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
957 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
958 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
960 target_flags |= MASK_AIX_STRUCT_RET;
963 if (TARGET_LONG_DOUBLE_128
964 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
965 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
967 /* Allocate an alias set for register saves & restores from stack. */
968 rs6000_sr_alias_set = new_alias_set ();
971 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
973 /* We can only guarantee the availability of DI pseudo-ops when
974 assembling for 64-bit targets. */
977 targetm.asm_out.aligned_op.di = NULL;
978 targetm.asm_out.unaligned_op.di = NULL;
981 /* Set maximum branch target alignment at two instructions, eight bytes. */
982 align_jumps_max_skip = 8;
983 align_loops_max_skip = 8;
985 /* Arrange to save and restore machine status around nested functions. */
986 init_machine_status = rs6000_init_machine_status;
989 /* Handle generic options of the form -mfoo=yes/no.
990 NAME is the option name.
991 VALUE is the option value.
992 FLAG is the pointer to the flag where to store a 1 or 0, depending on
993 whether the option value is 'yes' or 'no' respectively. */
995 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
999 else if (!strcmp (value, "yes"))
1001 else if (!strcmp (value, "no"))
1004 error ("unknown -m%s= option specified: '%s'", name, value);
1007 /* Handle -mabi= options. */
1009 rs6000_parse_abi_options (void)
1011 if (rs6000_abi_string == 0)
1013 else if (! strcmp (rs6000_abi_string, "altivec"))
1014 rs6000_altivec_abi = 1;
1015 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1016 rs6000_altivec_abi = 0;
1017 else if (! strcmp (rs6000_abi_string, "spe"))
1020 if (!TARGET_SPE_ABI)
1021 error ("not configured for ABI: '%s'", rs6000_abi_string);
1024 else if (! strcmp (rs6000_abi_string, "no-spe"))
1027 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1030 /* Handle -malign-XXXXXX options. */
1032 rs6000_parse_alignment_option (void)
1034 if (rs6000_alignment_string == 0)
1036 else if (! strcmp (rs6000_alignment_string, "power"))
1037 rs6000_alignment_flags = MASK_ALIGN_POWER;
1038 else if (! strcmp (rs6000_alignment_string, "natural"))
1039 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1041 error ("unknown -malign-XXXXX option specified: '%s'",
1042 rs6000_alignment_string);
1045 /* Validate and record the size specified with the -mtls-size option. */
1048 rs6000_parse_tls_size_option (void)
1050 if (rs6000_tls_size_string == 0)
1052 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1053 rs6000_tls_size = 16;
1054 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1055 rs6000_tls_size = 32;
1056 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1057 rs6000_tls_size = 64;
1059 error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string);
1063 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1067 /* Do anything needed at the start of the asm file. */
1070 rs6000_file_start (void)
1074 const char *start = buffer;
1075 struct rs6000_cpu_select *ptr;
1076 const char *default_cpu = TARGET_CPU_DEFAULT;
1077 FILE *file = asm_out_file;
1079 default_file_start ();
1081 #ifdef TARGET_BI_ARCH
1082 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1086 if (flag_verbose_asm)
1088 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1089 rs6000_select[0].string = default_cpu;
1091 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1093 ptr = &rs6000_select[i];
1094 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1096 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1101 #ifdef USING_ELFOS_H
1102 switch (rs6000_sdata)
1104 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1105 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1106 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1107 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1110 if (rs6000_sdata && g_switch_value)
1112 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1123 /* Return nonzero if this function is known to have a null epilogue. */
1126 direct_return (void)
1128 if (reload_completed)
1130 rs6000_stack_t *info = rs6000_stack_info ();
1132 if (info->first_gp_reg_save == 32
1133 && info->first_fp_reg_save == 64
1134 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1135 && ! info->lr_save_p
1136 && ! info->cr_save_p
1137 && info->vrsave_mask == 0
1145 /* Returns 1 always. */
1148 any_operand (rtx op ATTRIBUTE_UNUSED,
1149 enum machine_mode mode ATTRIBUTE_UNUSED)
1154 /* Returns 1 if op is the count register. */
1156 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1158 if (GET_CODE (op) != REG)
1161 if (REGNO (op) == COUNT_REGISTER_REGNUM)
1164 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1170 /* Returns 1 if op is an altivec register. */
1172 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1175 return (register_operand (op, mode)
1176 && (GET_CODE (op) != REG
1177 || REGNO (op) > FIRST_PSEUDO_REGISTER
1178 || ALTIVEC_REGNO_P (REGNO (op))));
1182 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1184 if (GET_CODE (op) != REG)
1187 if (XER_REGNO_P (REGNO (op)))
1193 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1194 by such constants completes more quickly. */
1197 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1199 return ( GET_CODE (op) == CONST_INT
1200 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1203 /* Return 1 if OP is a constant that can fit in a D field. */
1206 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1208 return (GET_CODE (op) == CONST_INT
1209 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1212 /* Similar for an unsigned D field. */
1215 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1217 return (GET_CODE (op) == CONST_INT
1218 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1221 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1224 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1226 return (GET_CODE (op) == CONST_INT
1227 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1230 /* Returns 1 if OP is a CONST_INT that is a positive value
1231 and an exact power of 2. */
1234 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1236 return (GET_CODE (op) == CONST_INT
1238 && exact_log2 (INTVAL (op)) >= 0);
1241 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1245 gpc_reg_operand (rtx op, enum machine_mode mode)
1247 return (register_operand (op, mode)
1248 && (GET_CODE (op) != REG
1249 || (REGNO (op) >= ARG_POINTER_REGNUM
1250 && !XER_REGNO_P (REGNO (op)))
1251 || REGNO (op) < MQ_REGNO));
1254 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1258 cc_reg_operand (rtx op, enum machine_mode mode)
1260 return (register_operand (op, mode)
1261 && (GET_CODE (op) != REG
1262 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1263 || CR_REGNO_P (REGNO (op))));
1266 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1267 CR field that isn't CR0. */
1270 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1272 return (register_operand (op, mode)
1273 && (GET_CODE (op) != REG
1274 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1275 || CR_REGNO_NOT_CR0_P (REGNO (op))));
1278 /* Returns 1 if OP is either a constant integer valid for a D-field or
1279 a non-special register. If a register, it must be in the proper
1280 mode unless MODE is VOIDmode. */
1283 reg_or_short_operand (rtx op, enum machine_mode mode)
1285 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1288 /* Similar, except check if the negation of the constant would be
1289 valid for a D-field. */
1292 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1294 if (GET_CODE (op) == CONST_INT)
1295 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
1297 return gpc_reg_operand (op, mode);
1300 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1301 a non-special register. If a register, it must be in the proper
1302 mode unless MODE is VOIDmode. */
1305 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1307 if (gpc_reg_operand (op, mode))
1309 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1316 /* Return 1 if the operand is either a register or an integer whose
1317 high-order 16 bits are zero. */
1320 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1322 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1325 /* Return 1 is the operand is either a non-special register or ANY
1326 constant integer. */
1329 reg_or_cint_operand (rtx op, enum machine_mode mode)
1331 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1334 /* Return 1 is the operand is either a non-special register or ANY
1335 32-bit signed constant integer. */
1338 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
1340 return (gpc_reg_operand (op, mode)
1341 || (GET_CODE (op) == CONST_INT
1342 #if HOST_BITS_PER_WIDE_INT != 32
1343 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
1344 < (unsigned HOST_WIDE_INT) 0x100000000ll)
1349 /* Return 1 is the operand is either a non-special register or a 32-bit
1350 signed constant integer valid for 64-bit addition. */
1353 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
1355 return (gpc_reg_operand (op, mode)
1356 || (GET_CODE (op) == CONST_INT
1357 #if HOST_BITS_PER_WIDE_INT == 32
1358 && INTVAL (op) < 0x7fff8000
1360 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
1366 /* Return 1 is the operand is either a non-special register or a 32-bit
1367 signed constant integer valid for 64-bit subtraction. */
1370 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
1372 return (gpc_reg_operand (op, mode)
1373 || (GET_CODE (op) == CONST_INT
1374 #if HOST_BITS_PER_WIDE_INT == 32
1375 && (- INTVAL (op)) < 0x7fff8000
1377 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
1383 /* Return 1 is the operand is either a non-special register or ANY
1384 32-bit unsigned constant integer. */
1387 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
1389 if (GET_CODE (op) == CONST_INT)
1391 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
1393 if (GET_MODE_BITSIZE (mode) <= 32)
1396 if (INTVAL (op) < 0)
1400 return ((INTVAL (op) & GET_MODE_MASK (mode)
1401 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
1403 else if (GET_CODE (op) == CONST_DOUBLE)
1405 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1409 return CONST_DOUBLE_HIGH (op) == 0;
1412 return gpc_reg_operand (op, mode);
1415 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
1418 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1420 return (GET_CODE (op) == SYMBOL_REF
1421 || GET_CODE (op) == CONST
1422 || GET_CODE (op) == LABEL_REF);
1425 /* Return 1 if the operand is a simple references that can be loaded via
1426 the GOT (labels involving addition aren't allowed). */
1429 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1431 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
1434 /* Return the number of instructions it takes to form a constant in an
1435 integer register. */
1438 num_insns_constant_wide (HOST_WIDE_INT value)
1440 /* signed constant loadable with {cal|addi} */
1441 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1444 /* constant loadable with {cau|addis} */
1445 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1448 #if HOST_BITS_PER_WIDE_INT == 64
1449 else if (TARGET_POWERPC64)
1451 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1452 HOST_WIDE_INT high = value >> 31;
1454 if (high == 0 || high == -1)
1460 return num_insns_constant_wide (high) + 1;
1462 return (num_insns_constant_wide (high)
1463 + num_insns_constant_wide (low) + 1);
1472 num_insns_constant (rtx op, enum machine_mode mode)
1474 if (GET_CODE (op) == CONST_INT)
1476 #if HOST_BITS_PER_WIDE_INT == 64
1477 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1478 && mask64_operand (op, mode))
1482 return num_insns_constant_wide (INTVAL (op));
1485 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1490 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1491 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1492 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1495 else if (GET_CODE (op) == CONST_DOUBLE)
1501 int endian = (WORDS_BIG_ENDIAN == 0);
1503 if (mode == VOIDmode || mode == DImode)
1505 high = CONST_DOUBLE_HIGH (op);
1506 low = CONST_DOUBLE_LOW (op);
1510 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1511 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1513 low = l[1 - endian];
1517 return (num_insns_constant_wide (low)
1518 + num_insns_constant_wide (high));
1522 if (high == 0 && low >= 0)
1523 return num_insns_constant_wide (low);
1525 else if (high == -1 && low < 0)
1526 return num_insns_constant_wide (low);
1528 else if (mask64_operand (op, mode))
1532 return num_insns_constant_wide (high) + 1;
1535 return (num_insns_constant_wide (high)
1536 + num_insns_constant_wide (low) + 1);
1544 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
1545 register with one instruction per word. We only do this if we can
1546 safely read CONST_DOUBLE_{LOW,HIGH}. */
1549 easy_fp_constant (rtx op, enum machine_mode mode)
1551 if (GET_CODE (op) != CONST_DOUBLE
1552 || GET_MODE (op) != mode
1553 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
1556 /* Consider all constants with -msoft-float to be easy. */
1557 if ((TARGET_SOFT_FLOAT || !TARGET_FPRS)
1561 /* If we are using V.4 style PIC, consider all constants to be hard. */
1562 if (flag_pic && DEFAULT_ABI == ABI_V4)
1565 #ifdef TARGET_RELOCATABLE
1566 /* Similarly if we are using -mrelocatable, consider all constants
1568 if (TARGET_RELOCATABLE)
1577 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1578 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
1580 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1581 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
1582 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
1583 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
1586 else if (mode == DFmode)
1591 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1592 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
1594 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
1595 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
1598 else if (mode == SFmode)
1603 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1604 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1606 return num_insns_constant_wide (l) == 1;
1609 else if (mode == DImode)
1610 return ((TARGET_POWERPC64
1611 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
1612 || (num_insns_constant (op, DImode) <= 2));
1614 else if (mode == SImode)
1620 /* Return nonzero if all elements of a vector have the same value. */
1623 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1627 units = CONST_VECTOR_NUNITS (op);
1629 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1630 for (i = 1; i < units; ++i)
1631 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1638 /* Return 1 if the operand is a CONST_INT and can be put into a
1639 register without using memory. */
1642 easy_vector_constant (rtx op, enum machine_mode mode)
1646 if (GET_CODE (op) != CONST_VECTOR
1651 if (zero_constant (op, mode)
1652 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
1653 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
1656 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
1659 if (TARGET_SPE && mode == V1DImode)
1662 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1663 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
1665 /* Limit SPE vectors to 15 bits signed. These we can generate with:
1667 evmergelo r0, r0, r0
1670 I don't know how efficient it would be to allow bigger constants,
1671 considering we'll have an extra 'ori' for every 'li'. I doubt 5
1672 instructions is better than a 64-bit memory load, but I don't
1673 have the e500 timing specs. */
1674 if (TARGET_SPE && mode == V2SImode
1675 && cst >= -0x7fff && cst <= 0x7fff
1676 && cst2 >= -0x7fff && cst2 <= 0x7fff)
1679 if (TARGET_ALTIVEC && EASY_VECTOR_15 (cst, op, mode))
1682 if (TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode))
1688 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
1691 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
1695 if (!easy_vector_constant (op, mode))
1698 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1700 return TARGET_ALTIVEC && EASY_VECTOR_15_ADD_SELF (cst, op, mode);
1704 output_vec_const_move (rtx *operands)
1707 enum machine_mode mode;
1713 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
1714 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
1715 mode = GET_MODE (dest);
1719 if (zero_constant (vec, mode))
1720 return "vxor %0,%0,%0";
1721 else if (EASY_VECTOR_15 (cst, vec, mode))
1723 operands[1] = GEN_INT (cst);
1727 return "vspltisw %0,%1";
1729 return "vspltish %0,%1";
1731 return "vspltisb %0,%1";
1736 else if (EASY_VECTOR_15_ADD_SELF (cst, vec, mode))
1744 /* Vector constant 0 is handled as a splitter of V2SI, and in the
1745 pattern of V1DI, V4HI, and V2SF.
1747 FIXME: We should probably return # and add post reload
1748 splitters for these, but this way is so easy ;-).
1750 operands[1] = GEN_INT (cst);
1751 operands[2] = GEN_INT (cst2);
1753 return "li %0,%1\n\tevmergelo %0,%0,%0";
1755 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
1761 /* Return 1 if the operand is the constant 0. This works for scalars
1762 as well as vectors. */
1764 zero_constant (rtx op, enum machine_mode mode)
1766 return op == CONST0_RTX (mode);
1769 /* Return 1 if the operand is 0.0. */
1771 zero_fp_constant (rtx op, enum machine_mode mode)
1773 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
1776 /* Return 1 if the operand is in volatile memory. Note that during
1777 the RTL generation phase, memory_operand does not return TRUE for
1778 volatile memory references. So this function allows us to
1779 recognize volatile references where its safe. */
1782 volatile_mem_operand (rtx op, enum machine_mode mode)
1784 if (GET_CODE (op) != MEM)
1787 if (!MEM_VOLATILE_P (op))
1790 if (mode != GET_MODE (op))
1793 if (reload_completed)
1794 return memory_operand (op, mode);
1796 if (reload_in_progress)
1797 return strict_memory_address_p (mode, XEXP (op, 0));
1799 return memory_address_p (mode, XEXP (op, 0));
1802 /* Return 1 if the operand is an offsettable memory operand. */
1805 offsettable_mem_operand (rtx op, enum machine_mode mode)
1807 return ((GET_CODE (op) == MEM)
1808 && offsettable_address_p (reload_completed || reload_in_progress,
1809 mode, XEXP (op, 0)));
1812 /* Return 1 if the operand is either an easy FP constant (see above) or
1816 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
1818 return memory_operand (op, mode) || easy_fp_constant (op, mode);
1821 /* Return 1 if the operand is either a non-special register or an item
1822 that can be used as the operand of a `mode' add insn. */
1825 add_operand (rtx op, enum machine_mode mode)
1827 if (GET_CODE (op) == CONST_INT)
1828 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1829 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1831 return gpc_reg_operand (op, mode);
1834 /* Return 1 if OP is a constant but not a valid add_operand. */
1837 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1839 return (GET_CODE (op) == CONST_INT
1840 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
1841 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
1844 /* Return 1 if the operand is a non-special register or a constant that
1845 can be used as the operand of an OR or XOR insn on the RS/6000. */
1848 logical_operand (rtx op, enum machine_mode mode)
1850 HOST_WIDE_INT opl, oph;
1852 if (gpc_reg_operand (op, mode))
1855 if (GET_CODE (op) == CONST_INT)
1857 opl = INTVAL (op) & GET_MODE_MASK (mode);
1859 #if HOST_BITS_PER_WIDE_INT <= 32
1860 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
1864 else if (GET_CODE (op) == CONST_DOUBLE)
1866 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1869 opl = CONST_DOUBLE_LOW (op);
1870 oph = CONST_DOUBLE_HIGH (op);
1877 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
1878 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
1881 /* Return 1 if C is a constant that is not a logical operand (as
1882 above), but could be split into one. */
1885 non_logical_cint_operand (rtx op, enum machine_mode mode)
1887 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
1888 && ! logical_operand (op, mode)
1889 && reg_or_logical_cint_operand (op, mode));
1892 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
1893 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
1894 Reject all ones and all zeros, since these should have been optimized
1895 away and confuse the making of MB and ME. */
1898 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1900 HOST_WIDE_INT c, lsb;
1902 if (GET_CODE (op) != CONST_INT)
1907 /* Fail in 64-bit mode if the mask wraps around because the upper
1908 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
1909 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
1912 /* We don't change the number of transitions by inverting,
1913 so make sure we start with the LS bit zero. */
1917 /* Reject all zeros or all ones. */
1921 /* Find the first transition. */
1924 /* Invert to look for a second transition. */
1927 /* Erase first transition. */
1930 /* Find the second transition (if any). */
1933 /* Match if all the bits above are 1's (or c is zero). */
1937 /* Return 1 for the PowerPC64 rlwinm corner case. */
1940 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1942 HOST_WIDE_INT c, lsb;
1944 if (GET_CODE (op) != CONST_INT)
1949 if ((c & 0x80000001) != 0x80000001)
1963 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
1964 It is if there are no more than one 1->0 or 0->1 transitions.
1965 Reject all zeros, since zero should have been optimized away and
1966 confuses the making of MB and ME. */
1969 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1971 if (GET_CODE (op) == CONST_INT)
1973 HOST_WIDE_INT c, lsb;
1977 /* Reject all zeros. */
1981 /* We don't change the number of transitions by inverting,
1982 so make sure we start with the LS bit zero. */
1986 /* Find the transition, and check that all bits above are 1's. */
1989 /* Match if all the bits above are 1's (or c is zero). */
1995 /* Like mask64_operand, but allow up to three transitions. This
1996 predicate is used by insn patterns that generate two rldicl or
1997 rldicr machine insns. */
2000 mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2002 if (GET_CODE (op) == CONST_INT)
2004 HOST_WIDE_INT c, lsb;
2008 /* Disallow all zeros. */
2012 /* We don't change the number of transitions by inverting,
2013 so make sure we start with the LS bit zero. */
2017 /* Find the first transition. */
2020 /* Invert to look for a second transition. */
2023 /* Erase first transition. */
2026 /* Find the second transition. */
2029 /* Invert to look for a third transition. */
2032 /* Erase second transition. */
2035 /* Find the third transition (if any). */
2038 /* Match if all the bits above are 1's (or c is zero). */
2044 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2045 implement ANDing by the mask IN. */
2047 build_mask64_2_operands (rtx in, rtx *out)
2049 #if HOST_BITS_PER_WIDE_INT >= 64
2050 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2053 if (GET_CODE (in) != CONST_INT)
2059 /* Assume c initially something like 0x00fff000000fffff. The idea
2060 is to rotate the word so that the middle ^^^^^^ group of zeros
2061 is at the MS end and can be cleared with an rldicl mask. We then
2062 rotate back and clear off the MS ^^ group of zeros with a
2064 c = ~c; /* c == 0xff000ffffff00000 */
2065 lsb = c & -c; /* lsb == 0x0000000000100000 */
2066 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2067 c = ~c; /* c == 0x00fff000000fffff */
2068 c &= -lsb; /* c == 0x00fff00000000000 */
2069 lsb = c & -c; /* lsb == 0x0000100000000000 */
2070 c = ~c; /* c == 0xff000fffffffffff */
2071 c &= -lsb; /* c == 0xff00000000000000 */
2073 while ((lsb >>= 1) != 0)
2074 shift++; /* shift == 44 on exit from loop */
2075 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2076 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2077 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2081 /* Assume c initially something like 0xff000f0000000000. The idea
2082 is to rotate the word so that the ^^^ middle group of zeros
2083 is at the LS end and can be cleared with an rldicr mask. We then
2084 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2086 lsb = c & -c; /* lsb == 0x0000010000000000 */
2087 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2088 c = ~c; /* c == 0x00fff0ffffffffff */
2089 c &= -lsb; /* c == 0x00fff00000000000 */
2090 lsb = c & -c; /* lsb == 0x0000100000000000 */
2091 c = ~c; /* c == 0xff000fffffffffff */
2092 c &= -lsb; /* c == 0xff00000000000000 */
2094 while ((lsb >>= 1) != 0)
2095 shift++; /* shift == 44 on exit from loop */
2096 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2097 m1 >>= shift; /* m1 == 0x0000000000000fff */
2098 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2101 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2102 masks will be all 1's. We are guaranteed more than one transition. */
2103 out[0] = GEN_INT (64 - shift);
2104 out[1] = GEN_INT (m1);
2105 out[2] = GEN_INT (shift);
2106 out[3] = GEN_INT (m2);
2114 /* Return 1 if the operand is either a non-special register or a constant
2115 that can be used as the operand of a PowerPC64 logical AND insn. */
2118 and64_operand (rtx op, enum machine_mode mode)
2120 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2121 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2123 return (logical_operand (op, mode) || mask64_operand (op, mode));
2126 /* Like the above, but also match constants that can be implemented
2127 with two rldicl or rldicr insns. */
2130 and64_2_operand (rtx op, enum machine_mode mode)
2132 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2133 return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
2135 return logical_operand (op, mode) || mask64_2_operand (op, mode);
2138 /* Return 1 if the operand is either a non-special register or a
2139 constant that can be used as the operand of an RS/6000 logical AND insn. */
2142 and_operand (rtx op, enum machine_mode mode)
2144 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2145 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2147 return (logical_operand (op, mode) || mask_operand (op, mode));
2150 /* Return 1 if the operand is a general register or memory operand. */
2153 reg_or_mem_operand (rtx op, enum machine_mode mode)
2155 return (gpc_reg_operand (op, mode)
2156 || memory_operand (op, mode)
2157 || macho_lo_sum_memory_operand (op, mode)
2158 || volatile_mem_operand (op, mode));
2161 /* Return 1 if the operand is a general register or memory operand without
2162 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2166 lwa_operand (rtx op, enum machine_mode mode)
2170 if (reload_completed && GET_CODE (inner) == SUBREG)
2171 inner = SUBREG_REG (inner);
2173 return gpc_reg_operand (inner, mode)
2174 || (memory_operand (inner, mode)
2175 && GET_CODE (XEXP (inner, 0)) != PRE_INC
2176 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2177 && (GET_CODE (XEXP (inner, 0)) != PLUS
2178 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2179 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2182 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2185 symbol_ref_operand (rtx op, enum machine_mode mode)
2187 if (mode != VOIDmode && GET_MODE (op) != mode)
2190 return (GET_CODE (op) == SYMBOL_REF
2191 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2194 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2195 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2198 call_operand (rtx op, enum machine_mode mode)
2200 if (mode != VOIDmode && GET_MODE (op) != mode)
2203 return (GET_CODE (op) == SYMBOL_REF
2204 || (GET_CODE (op) == REG
2205 && (REGNO (op) == LINK_REGISTER_REGNUM
2206 || REGNO (op) == COUNT_REGISTER_REGNUM
2207 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2210 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2214 current_file_function_operand (rtx op,
2215 enum machine_mode mode ATTRIBUTE_UNUSED)
2217 return (GET_CODE (op) == SYMBOL_REF
2218 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2219 && (SYMBOL_REF_LOCAL_P (op)
2220 || (op == XEXP (DECL_RTL (current_function_decl), 0))));
2223 /* Return 1 if this operand is a valid input for a move insn. */
2226 input_operand (rtx op, enum machine_mode mode)
2228 /* Memory is always valid. */
2229 if (memory_operand (op, mode))
2232 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
2233 if (GET_CODE (op) == CONSTANT_P_RTX)
2236 /* For floating-point, easy constants are valid. */
2237 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2239 && easy_fp_constant (op, mode))
2242 /* Allow any integer constant. */
2243 if (GET_MODE_CLASS (mode) == MODE_INT
2244 && (GET_CODE (op) == CONST_INT
2245 || GET_CODE (op) == CONST_DOUBLE))
2248 /* Allow easy vector constants. */
2249 if (GET_CODE (op) == CONST_VECTOR
2250 && easy_vector_constant (op, mode))
2253 /* For floating-point or multi-word mode, the only remaining valid type
2255 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2256 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
2257 return register_operand (op, mode);
2259 /* The only cases left are integral modes one word or smaller (we
2260 do not get called for MODE_CC values). These can be in any
2262 if (register_operand (op, mode))
2265 /* A SYMBOL_REF referring to the TOC is valid. */
2266 if (legitimate_constant_pool_address_p (op))
2269 /* A constant pool expression (relative to the TOC) is valid */
2270 if (toc_relative_expr_p (op))
2273 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
2275 if (DEFAULT_ABI == ABI_V4
2276 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
2277 && small_data_operand (op, Pmode))
2283 /* Return 1 for an operand in small memory on V.4/eabi. */
2286 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2287 enum machine_mode mode ATTRIBUTE_UNUSED)
2292 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2295 if (DEFAULT_ABI != ABI_V4)
2298 if (GET_CODE (op) == SYMBOL_REF)
2301 else if (GET_CODE (op) != CONST
2302 || GET_CODE (XEXP (op, 0)) != PLUS
2303 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2304 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2309 rtx sum = XEXP (op, 0);
2310 HOST_WIDE_INT summand;
2312 /* We have to be careful here, because it is the referenced address
2313 that must be 32k from _SDA_BASE_, not just the symbol. */
2314 summand = INTVAL (XEXP (sum, 1));
2315 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2318 sym_ref = XEXP (sum, 0);
2321 return SYMBOL_REF_SMALL_P (sym_ref);
2327 /* Return true if either operand is a general purpose register. */
2330 gpr_or_gpr_p (rtx op0, rtx op1)
2332 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2333 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2337 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2340 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2342 switch (GET_CODE(op))
2345 if (RS6000_SYMBOL_REF_TLS_P (op))
2347 else if (CONSTANT_POOL_ADDRESS_P (op))
2349 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2357 else if (! strcmp (XSTR (op, 0), toc_label_name))
2366 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2367 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2369 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2378 constant_pool_expr_p (rtx op)
2382 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2386 toc_relative_expr_p (rtx op)
2390 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2393 /* SPE offset addressing is limited to 5-bits worth of double words. */
2394 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2397 legitimate_constant_pool_address_p (rtx x)
2400 && GET_CODE (x) == PLUS
2401 && GET_CODE (XEXP (x, 0)) == REG
2402 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2403 && constant_pool_expr_p (XEXP (x, 1)));
2407 legitimate_small_data_p (enum machine_mode mode, rtx x)
2409 return (DEFAULT_ABI == ABI_V4
2410 && !flag_pic && !TARGET_TOC
2411 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2412 && small_data_operand (x, mode));
2416 legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2418 unsigned HOST_WIDE_INT offset, extra;
2420 if (GET_CODE (x) != PLUS)
2422 if (GET_CODE (XEXP (x, 0)) != REG)
2424 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2426 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2429 offset = INTVAL (XEXP (x, 1));
2437 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2438 which leaves the only valid constant offset of zero, which by
2439 canonicalization rules is also invalid. */
2446 /* SPE vector modes. */
2447 return SPE_CONST_OFFSET_OK (offset);
2453 else if (offset & 3)
2461 else if (offset & 3)
2471 return (offset + extra >= offset) && (offset + extra + 0x8000 < 0x10000);
2475 legitimate_indexed_address_p (rtx x, int strict)
2479 if (GET_CODE (x) != PLUS)
2484 if (!REG_P (op0) || !REG_P (op1))
2487 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2488 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2489 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2490 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2494 legitimate_indirect_address_p (rtx x, int strict)
2496 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2500 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2502 if (!TARGET_MACHO || !flag_pic
2503 || mode != SImode || GET_CODE(x) != MEM)
2507 if (GET_CODE (x) != LO_SUM)
2509 if (GET_CODE (XEXP (x, 0)) != REG)
2511 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2515 return CONSTANT_P (x);
2519 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2521 if (GET_CODE (x) != LO_SUM)
2523 if (GET_CODE (XEXP (x, 0)) != REG)
2525 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2531 if (DEFAULT_ABI != ABI_AIX && flag_pic)
2535 if (GET_MODE_NUNITS (mode) != 1)
2537 if (GET_MODE_BITSIZE (mode) > 32
2538 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode))
2541 return CONSTANT_P (x);
2548 /* Try machine-dependent ways of modifying an illegitimate address
2549 to be legitimate. If we find one, return the new, valid address.
2550 This is used from only one place: `memory_address' in explow.c.
2552 OLDX is the address as it was before break_out_memory_refs was
2553 called. In some cases it is useful to look at this to decide what
2556 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2558 It is always safe for this function to do nothing. It exists to
2559 recognize opportunities to optimize the output.
2561 On RS/6000, first check for the sum of a register with a constant
2562 integer that is out of range. If so, generate code to add the
2563 constant with the low-order 16 bits masked to the register and force
2564 this result into another register (this can be done with `cau').
2565 Then generate an address of REG+(CONST&0xffff), allowing for the
2566 possibility of bit 16 being a one.
2568 Then check for the sum of a register and something not constant, try to
2569 load the other things into a register and return the sum. */
2572 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2573 enum machine_mode mode)
2575 if (GET_CODE (x) == SYMBOL_REF)
2577 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2579 return rs6000_legitimize_tls_address (x, model);
2582 if (GET_CODE (x) == PLUS
2583 && GET_CODE (XEXP (x, 0)) == REG
2584 && GET_CODE (XEXP (x, 1)) == CONST_INT
2585 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2587 HOST_WIDE_INT high_int, low_int;
2589 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2590 high_int = INTVAL (XEXP (x, 1)) - low_int;
2591 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2592 GEN_INT (high_int)), 0);
2593 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2595 else if (GET_CODE (x) == PLUS
2596 && GET_CODE (XEXP (x, 0)) == REG
2597 && GET_CODE (XEXP (x, 1)) != CONST_INT
2598 && GET_MODE_NUNITS (mode) == 1
2599 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2601 || (mode != DFmode && mode != TFmode))
2602 && (TARGET_POWERPC64 || mode != DImode)
2605 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2606 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2608 else if (ALTIVEC_VECTOR_MODE (mode))
2612 /* Make sure both operands are registers. */
2613 if (GET_CODE (x) == PLUS)
2614 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2615 force_reg (Pmode, XEXP (x, 1)));
2617 reg = force_reg (Pmode, x);
2620 else if (SPE_VECTOR_MODE (mode))
2622 /* We accept [reg + reg] and [reg + OFFSET]. */
2624 if (GET_CODE (x) == PLUS)
2626 rtx op1 = XEXP (x, 0);
2627 rtx op2 = XEXP (x, 1);
2629 op1 = force_reg (Pmode, op1);
2631 if (GET_CODE (op2) != REG
2632 && (GET_CODE (op2) != CONST_INT
2633 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2634 op2 = force_reg (Pmode, op2);
2636 return gen_rtx_PLUS (Pmode, op1, op2);
2639 return force_reg (Pmode, x);
2645 && GET_CODE (x) != CONST_INT
2646 && GET_CODE (x) != CONST_DOUBLE
2648 && GET_MODE_NUNITS (mode) == 1
2649 && (GET_MODE_BITSIZE (mode) <= 32
2650 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2652 rtx reg = gen_reg_rtx (Pmode);
2653 emit_insn (gen_elf_high (reg, x));
2654 return gen_rtx_LO_SUM (Pmode, reg, x);
2656 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2659 && ! MACHO_DYNAMIC_NO_PIC_P
2661 && GET_CODE (x) != CONST_INT
2662 && GET_CODE (x) != CONST_DOUBLE
2664 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2668 rtx reg = gen_reg_rtx (Pmode);
2669 emit_insn (gen_macho_high (reg, x));
2670 return gen_rtx_LO_SUM (Pmode, reg, x);
2673 && constant_pool_expr_p (x)
2674 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2676 return create_TOC_reference (x);
2682 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2684 static GTY(()) rtx rs6000_tls_symbol;
2686 rs6000_tls_get_addr (void)
2688 if (!rs6000_tls_symbol)
2689 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2691 return rs6000_tls_symbol;
2694 /* Construct the SYMBOL_REF for TLS GOT references. */
2696 static GTY(()) rtx rs6000_got_symbol;
2698 rs6000_got_sym (void)
2700 if (!rs6000_got_symbol)
2702 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2703 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2704 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2707 return rs6000_got_symbol;
2710 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2711 this (thread-local) address. */
2714 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2718 dest = gen_reg_rtx (Pmode);
2719 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2725 tlsreg = gen_rtx_REG (Pmode, 13);
2726 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2730 tlsreg = gen_rtx_REG (Pmode, 2);
2731 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2735 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2739 tmp = gen_reg_rtx (Pmode);
2742 tlsreg = gen_rtx_REG (Pmode, 13);
2743 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2747 tlsreg = gen_rtx_REG (Pmode, 2);
2748 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2752 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2754 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2759 rtx r3, got, tga, tmp1, tmp2, eqv;
2762 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2766 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2769 rtx gsym = rs6000_got_sym ();
2770 got = gen_reg_rtx (Pmode);
2772 rs6000_emit_move (got, gsym, Pmode);
2776 static int tls_got_labelno = 0;
2777 rtx tempLR, lab, tmp3, mem;
2780 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
2781 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
2782 tempLR = gen_reg_rtx (Pmode);
2783 tmp1 = gen_reg_rtx (Pmode);
2784 tmp2 = gen_reg_rtx (Pmode);
2785 tmp3 = gen_reg_rtx (Pmode);
2786 mem = gen_rtx_MEM (Pmode, tmp1);
2787 RTX_UNCHANGING_P (mem) = 1;
2789 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
2791 emit_move_insn (tmp1, tempLR);
2792 emit_move_insn (tmp2, mem);
2793 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2794 last = emit_move_insn (got, tmp3);
2795 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2797 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2799 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2805 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2807 r3 = gen_rtx_REG (Pmode, 3);
2809 insn = gen_tls_gd_64 (r3, got, addr);
2811 insn = gen_tls_gd_32 (r3, got, addr);
2814 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2815 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2816 insn = emit_call_insn (insn);
2817 CONST_OR_PURE_CALL_P (insn) = 1;
2818 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2819 insn = get_insns ();
2821 emit_libcall_block (insn, dest, r3, addr);
2823 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2825 r3 = gen_rtx_REG (Pmode, 3);
2827 insn = gen_tls_ld_64 (r3, got);
2829 insn = gen_tls_ld_32 (r3, got);
2832 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2833 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2834 insn = emit_call_insn (insn);
2835 CONST_OR_PURE_CALL_P (insn) = 1;
2836 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2837 insn = get_insns ();
2839 tmp1 = gen_reg_rtx (Pmode);
2840 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2842 emit_libcall_block (insn, tmp1, r3, eqv);
2843 if (rs6000_tls_size == 16)
2846 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2848 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2850 else if (rs6000_tls_size == 32)
2852 tmp2 = gen_reg_rtx (Pmode);
2854 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2856 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2859 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2861 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2865 tmp2 = gen_reg_rtx (Pmode);
2867 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2869 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2871 insn = gen_rtx_SET (Pmode, dest,
2872 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2878 /* IE, or 64 bit offset LE. */
2879 tmp2 = gen_reg_rtx (Pmode);
2881 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2883 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2886 insn = gen_tls_tls_64 (dest, tmp2, addr);
2888 insn = gen_tls_tls_32 (dest, tmp2, addr);
2896 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
2897 instruction definitions. */
2900 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
2902 return RS6000_SYMBOL_REF_TLS_P (x);
2905 /* Return 1 if X contains a thread-local symbol. */
2908 rs6000_tls_referenced_p (rtx x)
2910 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2913 /* Return 1 if *X is a thread-local symbol. This is the same as
2914 rs6000_tls_symbol_ref except for the type of the unused argument. */
2917 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2919 return RS6000_SYMBOL_REF_TLS_P (*x);
2922 /* The convention appears to be to define this wherever it is used.
2923 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2924 is now used here. */
2925 #ifndef REG_MODE_OK_FOR_BASE_P
2926 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2929 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2930 replace the input X, or the original X if no replacement is called for.
2931 The output parameter *WIN is 1 if the calling macro should goto WIN,
2934 For RS/6000, we wish to handle large displacements off a base
2935 register by splitting the addend across an addiu/addis and the mem insn.
2936 This cuts number of extra insns needed from 3 to 1.
2938 On Darwin, we use this to generate code for floating point constants.
2939 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2940 The Darwin code is inside #if TARGET_MACHO because only then is
2941 machopic_function_base_name() defined. */
2943 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
2944 int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win)
2946 /* We must recognize output that we have already generated ourselves. */
2947 if (GET_CODE (x) == PLUS
2948 && GET_CODE (XEXP (x, 0)) == PLUS
2949 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2950 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2951 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2953 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2954 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2955 opnum, (enum reload_type)type);
2961 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
2962 && GET_CODE (x) == LO_SUM
2963 && GET_CODE (XEXP (x, 0)) == PLUS
2964 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
2965 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
2966 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
2967 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
2968 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
2969 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
2970 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
2972 /* Result of previous invocation of this function on Darwin
2973 floating point constant. */
2974 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2975 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
2976 opnum, (enum reload_type)type);
2981 if (GET_CODE (x) == PLUS
2982 && GET_CODE (XEXP (x, 0)) == REG
2983 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2984 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
2985 && GET_CODE (XEXP (x, 1)) == CONST_INT
2986 && !SPE_VECTOR_MODE (mode)
2987 && !ALTIVEC_VECTOR_MODE (mode))
2989 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2990 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2992 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
2994 /* Check for 32-bit overflow. */
2995 if (high + low != val)
3001 /* Reload the high part into a base reg; leave the low part
3002 in the mem directly. */
3004 x = gen_rtx_PLUS (GET_MODE (x),
3005 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3009 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3010 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3011 opnum, (enum reload_type)type);
3016 if (GET_CODE (x) == SYMBOL_REF
3017 && DEFAULT_ABI == ABI_DARWIN
3018 && !ALTIVEC_VECTOR_MODE (mode)
3021 /* Darwin load of floating point constant. */
3022 rtx offset = gen_rtx (CONST, Pmode,
3023 gen_rtx (MINUS, Pmode, x,
3024 gen_rtx (SYMBOL_REF, Pmode,
3025 machopic_function_base_name ())));
3026 x = gen_rtx (LO_SUM, GET_MODE (x),
3027 gen_rtx (PLUS, Pmode, pic_offset_table_rtx,
3028 gen_rtx (HIGH, Pmode, offset)), offset);
3029 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3030 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3031 opnum, (enum reload_type)type);
3035 if (GET_CODE (x) == SYMBOL_REF
3036 && DEFAULT_ABI == ABI_DARWIN
3037 && !ALTIVEC_VECTOR_MODE (mode)
3038 && MACHO_DYNAMIC_NO_PIC_P)
3040 /* Darwin load of floating point constant. */
3041 x = gen_rtx (LO_SUM, GET_MODE (x),
3042 gen_rtx (HIGH, Pmode, x), x);
3043 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3044 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3045 opnum, (enum reload_type)type);
3051 && constant_pool_expr_p (x)
3052 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3054 (x) = create_TOC_reference (x);
3062 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3063 that is a valid memory address for an instruction.
3064 The MODE argument is the machine mode for the MEM expression
3065 that wants to use this address.
3067 On the RS/6000, there are four valid address: a SYMBOL_REF that
3068 refers to a constant pool entry of an address (or the sum of it
3069 plus a constant), a short (16-bit signed) constant plus a register,
3070 the sum of two registers, or a register indirect, possibly with an
3071 auto-increment. For DFmode and DImode with a constant plus register,
3072 we must ensure that both words are addressable or PowerPC64 with offset
3075 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3076 32-bit DImode, TImode), indexed addressing cannot be used because
3077 adjacent memory cells are accessed by adding word-sized offsets
3078 during assembly output. */
3080 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3082 if (RS6000_SYMBOL_REF_TLS_P (x))
3084 if (legitimate_indirect_address_p (x, reg_ok_strict))
3086 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3087 && !ALTIVEC_VECTOR_MODE (mode)
3088 && !SPE_VECTOR_MODE (mode)
3090 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3092 if (legitimate_small_data_p (mode, x))
3094 if (legitimate_constant_pool_address_p (x))
3096 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3098 && GET_CODE (x) == PLUS
3099 && GET_CODE (XEXP (x, 0)) == REG
3100 && XEXP (x, 0) == virtual_stack_vars_rtx
3101 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3103 if (legitimate_offset_address_p (mode, x, reg_ok_strict))
3106 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3108 || (mode != DFmode && mode != TFmode))
3109 && (TARGET_POWERPC64 || mode != DImode)
3110 && legitimate_indexed_address_p (x, reg_ok_strict))
3112 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3117 /* Go to LABEL if ADDR (a legitimate address expression)
3118 has an effect that depends on the machine mode it is used for.
3120 On the RS/6000 this is true of all integral offsets (since AltiVec
3121 modes don't allow them) or is a pre-increment or decrement.
3123 ??? Except that due to conceptual problems in offsettable_address_p
3124 we can't really report the problems of integral offsets. So leave
3125 this assuming that the adjustable offset must be valid for the
3126 sub-words of a TFmode operand, which is what we had before. */
3129 rs6000_mode_dependent_address (rtx addr)
3131 switch (GET_CODE (addr))
3134 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3136 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3137 return val + 12 + 0x8000 >= 0x10000;
3146 return TARGET_UPDATE;
3155 /* Try to output insns to set TARGET equal to the constant C if it can
3156 be done in less than N insns. Do all computations in MODE.
3157 Returns the place where the output has been placed if it can be
3158 done and the insns have been emitted. If it would take more than N
3159 insns, zero is returned and no insns and emitted. */
3162 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3163 rtx source, int n ATTRIBUTE_UNUSED)
3165 rtx result, insn, set;
3166 HOST_WIDE_INT c0, c1;
3168 if (mode == QImode || mode == HImode)
3171 dest = gen_reg_rtx (mode);
3172 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3175 else if (mode == SImode)
3177 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3179 emit_insn (gen_rtx_SET (VOIDmode, result,
3180 GEN_INT (INTVAL (source)
3181 & (~ (HOST_WIDE_INT) 0xffff))));
3182 emit_insn (gen_rtx_SET (VOIDmode, dest,
3183 gen_rtx_IOR (SImode, result,
3184 GEN_INT (INTVAL (source) & 0xffff))));
3187 else if (mode == DImode)
3189 if (GET_CODE (source) == CONST_INT)
3191 c0 = INTVAL (source);
3194 else if (GET_CODE (source) == CONST_DOUBLE)
3196 #if HOST_BITS_PER_WIDE_INT >= 64
3197 c0 = CONST_DOUBLE_LOW (source);
3200 c0 = CONST_DOUBLE_LOW (source);
3201 c1 = CONST_DOUBLE_HIGH (source);
3207 result = rs6000_emit_set_long_const (dest, c0, c1);
3212 insn = get_last_insn ();
3213 set = single_set (insn);
3214 if (! CONSTANT_P (SET_SRC (set)))
3215 set_unique_reg_note (insn, REG_EQUAL, source);
3220 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3221 fall back to a straight forward decomposition. We do this to avoid
3222 exponential run times encountered when looking for longer sequences
3223 with rs6000_emit_set_const. */
3225 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3227 if (!TARGET_POWERPC64)
3229 rtx operand1, operand2;
3231 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3233 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3235 emit_move_insn (operand1, GEN_INT (c1));
3236 emit_move_insn (operand2, GEN_INT (c2));
3240 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3243 ud2 = (c1 & 0xffff0000) >> 16;
3244 #if HOST_BITS_PER_WIDE_INT >= 64
3248 ud4 = (c2 & 0xffff0000) >> 16;
3250 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3251 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3254 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3256 emit_move_insn (dest, GEN_INT (ud1));
3259 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3260 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3263 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3266 emit_move_insn (dest, GEN_INT (ud2 << 16));
3268 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3270 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3271 || (ud4 == 0 && ! (ud3 & 0x8000)))
3274 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3277 emit_move_insn (dest, GEN_INT (ud3 << 16));
3280 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3281 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3283 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3288 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3291 emit_move_insn (dest, GEN_INT (ud4 << 16));
3294 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3296 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3298 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3299 GEN_INT (ud2 << 16)));
3301 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3307 /* Emit a move from SOURCE to DEST in mode MODE. */
3309 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3313 operands[1] = source;
3315 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3316 if (GET_CODE (operands[1]) == CONST_DOUBLE
3317 && ! FLOAT_MODE_P (mode)
3318 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3320 /* FIXME. This should never happen. */
3321 /* Since it seems that it does, do the safe thing and convert
3323 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3325 if (GET_CODE (operands[1]) == CONST_DOUBLE
3326 && ! FLOAT_MODE_P (mode)
3327 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3328 && CONST_DOUBLE_LOW (operands[1]) >= 0)
3329 || (CONST_DOUBLE_HIGH (operands[1]) == -1
3330 && CONST_DOUBLE_LOW (operands[1]) < 0)))
3333 /* Check if GCC is setting up a block move that will end up using FP
3334 registers as temporaries. We must make sure this is acceptable. */
3335 if (GET_CODE (operands[0]) == MEM
3336 && GET_CODE (operands[1]) == MEM
3338 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3339 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3340 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3341 ? 32 : MEM_ALIGN (operands[0])))
3342 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3344 : MEM_ALIGN (operands[1]))))
3345 && ! MEM_VOLATILE_P (operands [0])
3346 && ! MEM_VOLATILE_P (operands [1]))
3348 emit_move_insn (adjust_address (operands[0], SImode, 0),
3349 adjust_address (operands[1], SImode, 0));
3350 emit_move_insn (adjust_address (operands[0], SImode, 4),
3351 adjust_address (operands[1], SImode, 4));
3355 if (!no_new_pseudos)
3357 if (GET_CODE (operands[1]) == MEM && optimize > 0
3358 && (mode == QImode || mode == HImode || mode == SImode)
3359 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode))
3361 rtx reg = gen_reg_rtx (word_mode);
3363 emit_insn (gen_rtx_SET (word_mode, reg,
3364 gen_rtx_ZERO_EXTEND (word_mode,
3366 operands[1] = gen_lowpart (mode, reg);
3368 if (GET_CODE (operands[0]) != REG)
3369 operands[1] = force_reg (mode, operands[1]);
3372 if (mode == SFmode && ! TARGET_POWERPC
3373 && TARGET_HARD_FLOAT && TARGET_FPRS
3374 && GET_CODE (operands[0]) == MEM)
3378 if (reload_in_progress || reload_completed)
3379 regnum = true_regnum (operands[1]);
3380 else if (GET_CODE (operands[1]) == REG)
3381 regnum = REGNO (operands[1]);
3385 /* If operands[1] is a register, on POWER it may have
3386 double-precision data in it, so truncate it to single
3388 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3391 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3392 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3393 operands[1] = newreg;
3397 /* Recognize the case where operand[1] is a reference to thread-local
3398 data and load its address to a register. */
3399 if (GET_CODE (operands[1]) == SYMBOL_REF)
3401 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3403 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3406 /* Handle the case where reload calls us with an invalid address. */
3407 if (reload_in_progress && mode == Pmode
3408 && (! general_operand (operands[1], mode)
3409 || ! nonimmediate_operand (operands[0], mode)))
3412 /* Handle the case of CONSTANT_P_RTX. */
3413 if (GET_CODE (operands[1]) == CONSTANT_P_RTX)
3416 /* 128-bit constant floating-point values on Darwin should really be
3417 loaded as two parts. */
3418 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3419 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3420 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3422 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3423 know how to get a DFmode SUBREG of a TFmode. */
3424 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3425 simplify_gen_subreg (DImode, operands[1], mode, 0),
3427 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3428 GET_MODE_SIZE (DImode)),
3429 simplify_gen_subreg (DImode, operands[1], mode,
3430 GET_MODE_SIZE (DImode)),
3435 /* FIXME: In the long term, this switch statement should go away
3436 and be replaced by a sequence of tests based on things like
3442 if (CONSTANT_P (operands[1])
3443 && GET_CODE (operands[1]) != CONST_INT)
3444 operands[1] = force_const_mem (mode, operands[1]);
3450 if (CONSTANT_P (operands[1])
3451 && ! easy_fp_constant (operands[1], mode))
3452 operands[1] = force_const_mem (mode, operands[1]);
3463 if (CONSTANT_P (operands[1])
3464 && !easy_vector_constant (operands[1], mode))
3465 operands[1] = force_const_mem (mode, operands[1]);
3470 /* Use default pattern for address of ELF small data */
3473 && DEFAULT_ABI == ABI_V4
3474 && (GET_CODE (operands[1]) == SYMBOL_REF
3475 || GET_CODE (operands[1]) == CONST)
3476 && small_data_operand (operands[1], mode))
3478 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3482 if (DEFAULT_ABI == ABI_V4
3483 && mode == Pmode && mode == SImode
3484 && flag_pic == 1 && got_operand (operands[1], mode))
3486 emit_insn (gen_movsi_got (operands[0], operands[1]));
3490 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3494 && CONSTANT_P (operands[1])
3495 && GET_CODE (operands[1]) != HIGH
3496 && GET_CODE (operands[1]) != CONST_INT)
3498 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3500 /* If this is a function address on -mcall-aixdesc,
3501 convert it to the address of the descriptor. */
3502 if (DEFAULT_ABI == ABI_AIX
3503 && GET_CODE (operands[1]) == SYMBOL_REF
3504 && XSTR (operands[1], 0)[0] == '.')
3506 const char *name = XSTR (operands[1], 0);
3508 while (*name == '.')
3510 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3511 CONSTANT_POOL_ADDRESS_P (new_ref)
3512 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3513 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3514 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3515 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3516 operands[1] = new_ref;
3519 if (DEFAULT_ABI == ABI_DARWIN)
3522 if (MACHO_DYNAMIC_NO_PIC_P)
3524 /* Take care of any required data indirection. */
3525 operands[1] = rs6000_machopic_legitimize_pic_address (
3526 operands[1], mode, operands[0]);
3527 if (operands[0] != operands[1])
3528 emit_insn (gen_rtx_SET (VOIDmode,
3529 operands[0], operands[1]));
3533 emit_insn (gen_macho_high (target, operands[1]));
3534 emit_insn (gen_macho_low (operands[0], target, operands[1]));
3538 emit_insn (gen_elf_high (target, operands[1]));
3539 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3543 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3544 and we have put it in the TOC, we just need to make a TOC-relative
3547 && GET_CODE (operands[1]) == SYMBOL_REF
3548 && constant_pool_expr_p (operands[1])
3549 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3550 get_pool_mode (operands[1])))
3552 operands[1] = create_TOC_reference (operands[1]);
3554 else if (mode == Pmode
3555 && CONSTANT_P (operands[1])
3556 && ((GET_CODE (operands[1]) != CONST_INT
3557 && ! easy_fp_constant (operands[1], mode))
3558 || (GET_CODE (operands[1]) == CONST_INT
3559 && num_insns_constant (operands[1], mode) > 2)
3560 || (GET_CODE (operands[0]) == REG
3561 && FP_REGNO_P (REGNO (operands[0]))))
3562 && GET_CODE (operands[1]) != HIGH
3563 && ! legitimate_constant_pool_address_p (operands[1])
3564 && ! toc_relative_expr_p (operands[1]))
3566 /* Emit a USE operation so that the constant isn't deleted if
3567 expensive optimizations are turned on because nobody
3568 references it. This should only be done for operands that
3569 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3570 This should not be done for operands that contain LABEL_REFs.
3571 For now, we just handle the obvious case. */
3572 if (GET_CODE (operands[1]) != LABEL_REF)
3573 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3576 /* Darwin uses a special PIC legitimizer. */
3577 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3580 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3582 if (operands[0] != operands[1])
3583 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3588 /* If we are to limit the number of things we put in the TOC and
3589 this is a symbol plus a constant we can add in one insn,
3590 just put the symbol in the TOC and add the constant. Don't do
3591 this if reload is in progress. */
3592 if (GET_CODE (operands[1]) == CONST
3593 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3594 && GET_CODE (XEXP (operands[1], 0)) == PLUS
3595 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
3596 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3597 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3598 && ! side_effects_p (operands[0]))
3601 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
3602 rtx other = XEXP (XEXP (operands[1], 0), 1);
3604 sym = force_reg (mode, sym);
3606 emit_insn (gen_addsi3 (operands[0], sym, other));
3608 emit_insn (gen_adddi3 (operands[0], sym, other));
3612 operands[1] = force_const_mem (mode, operands[1]);
3615 && constant_pool_expr_p (XEXP (operands[1], 0))
3616 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3617 get_pool_constant (XEXP (operands[1], 0)),
3618 get_pool_mode (XEXP (operands[1], 0))))
3621 = gen_rtx_MEM (mode,
3622 create_TOC_reference (XEXP (operands[1], 0)));
3623 set_mem_alias_set (operands[1], get_TOC_alias_set ());
3624 RTX_UNCHANGING_P (operands[1]) = 1;
3630 if (GET_CODE (operands[0]) == MEM
3631 && GET_CODE (XEXP (operands[0], 0)) != REG
3632 && ! reload_in_progress)
3634 = replace_equiv_address (operands[0],
3635 copy_addr_to_reg (XEXP (operands[0], 0)));
3637 if (GET_CODE (operands[1]) == MEM
3638 && GET_CODE (XEXP (operands[1], 0)) != REG
3639 && ! reload_in_progress)
3641 = replace_equiv_address (operands[1],
3642 copy_addr_to_reg (XEXP (operands[1], 0)));
3645 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3647 gen_rtx_SET (VOIDmode,
3648 operands[0], operands[1]),
3649 gen_rtx_CLOBBER (VOIDmode,
3650 gen_rtx_SCRATCH (SImode)))));
3659 /* Above, we may have called force_const_mem which may have returned
3660 an invalid address. If we can, fix this up; otherwise, reload will
3661 have to deal with it. */
3662 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3663 operands[1] = validize_mem (operands[1]);
3666 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3669 /* Nonzero if we can use a floating-point register to pass this arg. */
3670 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3671 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3672 && (CUM)->fregno <= FP_ARG_MAX_REG \
3673 && TARGET_HARD_FLOAT && TARGET_FPRS)
3675 /* Nonzero if we can use an AltiVec register to pass this arg. */
3676 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3677 (ALTIVEC_VECTOR_MODE (MODE) \
3678 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3679 && TARGET_ALTIVEC_ABI \
3680 && (DEFAULT_ABI == ABI_V4 || (NAMED)))
3682 /* Return a nonzero value to say to return the function value in
3683 memory, just as large structures are always returned. TYPE will be
3684 the data type of the value, and FNTYPE will be the type of the
3685 function doing the returning, or @code{NULL} for libcalls.
3687 The AIX ABI for the RS/6000 specifies that all structures are
3688 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3689 specifies that structures <= 8 bytes are returned in r3/r4, but a
3690 draft put them in memory, and GCC used to implement the draft
3691 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3692 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3693 compatibility can change DRAFT_V4_STRUCT_RET to override the
3694 default, and -m switches get the final word. See
3695 rs6000_override_options for more details.
3697 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3698 long double support is enabled. These values are returned in memory.
3700 int_size_in_bytes returns -1 for variable size objects, which go in
3701 memory always. The cast to unsigned makes -1 > 8. */
3704 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3706 if (AGGREGATE_TYPE_P (type)
3707 && (TARGET_AIX_STRUCT_RET
3708 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3710 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3715 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3716 for a call to a function whose data type is FNTYPE.
3717 For a library call, FNTYPE is 0.
3719 For incoming args we set the number of arguments in the prototype large
3720 so we never return a PARALLEL. */
3723 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3724 rtx libname ATTRIBUTE_UNUSED, int incoming, int libcall)
3726 static CUMULATIVE_ARGS zero_cumulative;
3728 *cum = zero_cumulative;
3730 cum->fregno = FP_ARG_MIN_REG;
3731 cum->vregno = ALTIVEC_ARG_MIN_REG;
3732 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3733 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3734 ? CALL_LIBCALL : CALL_NORMAL);
3735 cum->sysv_gregno = GP_ARG_MIN_REG;
3736 cum->stdarg = fntype
3737 && (TYPE_ARG_TYPES (fntype) != 0
3738 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3739 != void_type_node));
3742 cum->nargs_prototype = 1000; /* don't return a PARALLEL */
3744 else if (cum->prototype)
3745 cum->nargs_prototype = (list_length (TYPE_ARG_TYPES (fntype)) - 1
3746 + (TYPE_MODE (TREE_TYPE (fntype)) == BLKmode
3747 || rs6000_return_in_memory (TREE_TYPE (fntype),
3751 cum->nargs_prototype = 0;
3753 /* Check for a longcall attribute. */
3755 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3756 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
3757 cum->call_cookie = CALL_LONG;
3759 if (TARGET_DEBUG_ARG)
3761 fprintf (stderr, "\ninit_cumulative_args:");
3764 tree ret_type = TREE_TYPE (fntype);
3765 fprintf (stderr, " ret code = %s,",
3766 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3769 if (cum->call_cookie & CALL_LONG)
3770 fprintf (stderr, " longcall,");
3772 fprintf (stderr, " proto = %d, nargs = %d\n",
3773 cum->prototype, cum->nargs_prototype);
3777 /* If defined, a C expression which determines whether, and in which
3778 direction, to pad out an argument with extra space. The value
3779 should be of type `enum direction': either `upward' to pad above
3780 the argument, `downward' to pad below, or `none' to inhibit
3783 For the AIX ABI structs are always stored left shifted in their
3787 function_arg_padding (enum machine_mode mode, tree type)
3789 #ifndef AGGREGATE_PADDING_FIXED
3790 #define AGGREGATE_PADDING_FIXED 0
3792 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
3793 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
3796 if (!AGGREGATE_PADDING_FIXED)
3798 /* GCC used to pass structures of the same size as integer types as
3799 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
3800 ie. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
3801 passed padded downward, except that -mstrict-align further
3802 muddied the water in that multi-component structures of 2 and 4
3803 bytes in size were passed padded upward.
3805 The following arranges for best compatibility with previous
3806 versions of gcc, but removes the -mstrict-align dependency. */
3807 if (BYTES_BIG_ENDIAN)
3809 HOST_WIDE_INT size = 0;
3811 if (mode == BLKmode)
3813 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
3814 size = int_size_in_bytes (type);
3817 size = GET_MODE_SIZE (mode);
3819 if (size == 1 || size == 2 || size == 4)
3825 if (AGGREGATES_PAD_UPWARD_ALWAYS)
3827 if (type != 0 && AGGREGATE_TYPE_P (type))
3831 /* Fall back to the default. */
3832 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
3835 /* If defined, a C expression that gives the alignment boundary, in bits,
3836 of an argument with the specified mode and type. If it is not defined,
3837 PARM_BOUNDARY is used for all arguments.
3839 V.4 wants long longs to be double word aligned. */
3842 function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED)
3844 if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode))
3846 else if (SPE_VECTOR_MODE (mode))
3848 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
3851 return PARM_BOUNDARY;
3854 /* Update the data in CUM to advance over an argument
3855 of mode MODE and data type TYPE.
3856 (TYPE is null for libcalls where that information may not be available.) */
3859 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3860 tree type, int named)
3862 cum->nargs_prototype--;
3864 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
3866 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
3869 /* In variable-argument functions, vector arguments get GPRs allocated
3870 even if they are going to be passed in a vector register. */
3871 if (cum->stdarg && DEFAULT_ABI != ABI_V4)
3875 /* Vector parameters must be 16-byte aligned. This places
3876 them at 2 mod 4 in terms of words in 32-bit mode, since
3877 the parameter save area starts at offset 24 from the
3878 stack. In 64-bit mode, they just have to start on an
3879 even word, since the parameter save area is 16-byte
3880 aligned. Space for GPRs is reserved even if the argument
3881 will be passed in memory. */
3883 align = ((6 - (cum->words & 3)) & 3);
3885 align = cum->words & 1;
3886 cum->words += align + RS6000_ARG_SIZE (mode, type);
3888 if (TARGET_DEBUG_ARG)
3890 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
3892 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
3893 cum->nargs_prototype, cum->prototype,
3894 GET_MODE_NAME (mode));
3898 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
3900 && cum->sysv_gregno <= GP_ARG_MAX_REG)
3902 else if (DEFAULT_ABI == ABI_V4)
3904 if (TARGET_HARD_FLOAT && TARGET_FPRS
3905 && (mode == SFmode || mode == DFmode))
3907 if (cum->fregno <= FP_ARG_V4_MAX_REG)
3912 cum->words += cum->words & 1;
3913 cum->words += RS6000_ARG_SIZE (mode, type);
3919 int gregno = cum->sysv_gregno;
3921 /* Aggregates and IEEE quad get passed by reference. */
3922 if ((type && AGGREGATE_TYPE_P (type))
3926 n_words = RS6000_ARG_SIZE (mode, type);
3928 /* Long long and SPE vectors are put in odd registers. */
3929 if (n_words == 2 && (gregno & 1) == 0)
3932 /* Long long and SPE vectors are not split between registers
3934 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
3936 /* Long long is aligned on the stack. */
3938 cum->words += cum->words & 1;
3939 cum->words += n_words;
3942 /* Note: continuing to accumulate gregno past when we've started
3943 spilling to the stack indicates the fact that we've started
3944 spilling to the stack to expand_builtin_saveregs. */
3945 cum->sysv_gregno = gregno + n_words;
3948 if (TARGET_DEBUG_ARG)
3950 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
3951 cum->words, cum->fregno);
3952 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
3953 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
3954 fprintf (stderr, "mode = %4s, named = %d\n",
3955 GET_MODE_NAME (mode), named);
3960 int align = (TARGET_32BIT && (cum->words & 1) != 0
3961 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
3963 cum->words += align + RS6000_ARG_SIZE (mode, type);
3965 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3966 && TARGET_HARD_FLOAT && TARGET_FPRS)
3967 cum->fregno += (mode == TFmode ? 2 : 1);
3969 if (TARGET_DEBUG_ARG)
3971 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
3972 cum->words, cum->fregno);
3973 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
3974 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
3975 fprintf (stderr, "named = %d, align = %d\n", named, align);
3980 /* Determine where to put a SIMD argument on the SPE. */
3983 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
3988 int gregno = cum->sysv_gregno;
3989 int n_words = RS6000_ARG_SIZE (mode, type);
3991 /* SPE vectors are put in odd registers. */
3992 if (n_words == 2 && (gregno & 1) == 0)
3995 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
3998 enum machine_mode m = SImode;
4000 r1 = gen_rtx_REG (m, gregno);
4001 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4002 r2 = gen_rtx_REG (m, gregno + 1);
4003 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4004 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4011 if (cum->sysv_gregno <= GP_ARG_MAX_REG)
4012 return gen_rtx_REG (mode, cum->sysv_gregno);
4018 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4021 rs6000_mixed_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4022 tree type, int align_words)
4026 /* -mpowerpc64 with 32bit ABI splits up a DFmode argument
4027 in vararg list into zero, one or two GPRs */
4028 if (align_words >= GP_ARG_NUM_REG)
4029 return gen_rtx_PARALLEL (DFmode,
4031 gen_rtx_EXPR_LIST (VOIDmode,
4032 NULL_RTX, const0_rtx),
4033 gen_rtx_EXPR_LIST (VOIDmode,
4037 else if (align_words + RS6000_ARG_SIZE (mode, type)
4039 /* If this is partially on the stack, then we only
4040 include the portion actually in registers here. */
4041 return gen_rtx_PARALLEL (DFmode,
4043 gen_rtx_EXPR_LIST (VOIDmode,
4044 gen_rtx_REG (SImode,
4048 gen_rtx_EXPR_LIST (VOIDmode,
4053 /* split a DFmode arg into two GPRs */
4054 return gen_rtx_PARALLEL (DFmode,
4056 gen_rtx_EXPR_LIST (VOIDmode,
4057 gen_rtx_REG (SImode,
4061 gen_rtx_EXPR_LIST (VOIDmode,
4062 gen_rtx_REG (SImode,
4066 gen_rtx_EXPR_LIST (VOIDmode,
4067 gen_rtx_REG (mode, cum->fregno),
4070 /* -mpowerpc64 with 32bit ABI splits up a DImode argument into one
4072 else if (mode == DImode)
4074 if (align_words < GP_ARG_NUM_REG - 1)
4075 return gen_rtx_PARALLEL (DImode,
4077 gen_rtx_EXPR_LIST (VOIDmode,
4078 gen_rtx_REG (SImode,
4082 gen_rtx_EXPR_LIST (VOIDmode,
4083 gen_rtx_REG (SImode,
4087 else if (align_words == GP_ARG_NUM_REG - 1)
4088 return gen_rtx_PARALLEL (DImode,
4090 gen_rtx_EXPR_LIST (VOIDmode,
4091 NULL_RTX, const0_rtx),
4092 gen_rtx_EXPR_LIST (VOIDmode,
4093 gen_rtx_REG (SImode,
4098 else if (mode == BLKmode && align_words <= (GP_ARG_NUM_REG - 1))
4101 int size = int_size_in_bytes (type);
4102 int no_units = ((size - 1) / 4) + 1;
4103 int max_no_words = GP_ARG_NUM_REG - align_words;
4104 int rtlvec_len = no_units < max_no_words ? no_units : max_no_words;
4105 rtx *rtlvec = (rtx *) alloca (rtlvec_len * sizeof (rtx));
4107 memset ((char *) rtlvec, 0, rtlvec_len * sizeof (rtx));
4109 for (k=0; k < rtlvec_len; k++)
4110 rtlvec[k] = gen_rtx_EXPR_LIST (VOIDmode,
4111 gen_rtx_REG (SImode,
4114 k == 0 ? const0_rtx : GEN_INT (k*4));
4116 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k, rtlvec));
4122 /* Determine where to put an argument to a function.
4123 Value is zero to push the argument on the stack,
4124 or a hard register in which to store the argument.
4126 MODE is the argument's machine mode.
4127 TYPE is the data type of the argument (as a tree).
4128 This is null for libcalls where that information may
4130 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4131 the preceding args and about the function being called.
4132 NAMED is nonzero if this argument is a named parameter
4133 (otherwise it is an extra parameter matching an ellipsis).
4135 On RS/6000 the first eight words of non-FP are normally in registers
4136 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4137 Under V.4, the first 8 FP args are in registers.
4139 If this is floating-point and no prototype is specified, we use
4140 both an FP and integer register (or possibly FP reg and stack). Library
4141 functions (when CALL_LIBCALL is set) always have the proper types for args,
4142 so we can pass the FP value just in one register. emit_library_function
4143 doesn't support PARALLEL anyway. */
4146 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4147 tree type, int named)
4149 enum rs6000_abi abi = DEFAULT_ABI;
4151 /* Return a marker to indicate whether CR1 needs to set or clear the
4152 bit that V.4 uses to say fp args were passed in registers.
4153 Assume that we don't need the marker for software floating point,
4154 or compiler generated library calls. */
4155 if (mode == VOIDmode)
4158 && cum->nargs_prototype < 0
4159 && (cum->call_cookie & CALL_LIBCALL) == 0
4160 && (cum->prototype || TARGET_NO_PROTOTYPE))
4162 /* For the SPE, we need to crxor CR6 always. */
4164 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4165 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4166 return GEN_INT (cum->call_cookie
4167 | ((cum->fregno == FP_ARG_MIN_REG)
4168 ? CALL_V4_SET_FP_ARGS
4169 : CALL_V4_CLEAR_FP_ARGS));
4172 return GEN_INT (cum->call_cookie);
4175 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4176 return gen_rtx_REG (mode, cum->vregno);
4177 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4179 if (named || abi == ABI_V4)
4183 /* Vector parameters to varargs functions under AIX or Darwin
4184 get passed in memory and possibly also in GPRs. */
4185 int align, align_words;
4186 enum machine_mode part_mode = mode;
4188 /* Vector parameters must be 16-byte aligned. This places them at
4189 2 mod 4 in terms of words in 32-bit mode, since the parameter
4190 save area starts at offset 24 from the stack. In 64-bit mode,
4191 they just have to start on an even word, since the parameter
4192 save area is 16-byte aligned. */
4194 align = ((6 - (cum->words & 3)) & 3);
4196 align = cum->words & 1;
4197 align_words = cum->words + align;
4199 /* Out of registers? Memory, then. */
4200 if (align_words >= GP_ARG_NUM_REG)
4203 /* The vector value goes in GPRs. Only the part of the
4204 value in GPRs is reported here. */
4205 if (align_words + CLASS_MAX_NREGS (mode, GENERAL_REGS)
4207 /* Fortunately, there are only two possibilities, the value
4208 is either wholly in GPRs or half in GPRs and half not. */
4211 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
4214 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
4215 return rs6000_spe_function_arg (cum, mode, type);
4216 else if (abi == ABI_V4)
4218 if (TARGET_HARD_FLOAT && TARGET_FPRS
4219 && (mode == SFmode || mode == DFmode))
4221 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4222 return gen_rtx_REG (mode, cum->fregno);
4229 int gregno = cum->sysv_gregno;
4231 /* Aggregates and IEEE quad get passed by reference. */
4232 if ((type && AGGREGATE_TYPE_P (type))
4236 n_words = RS6000_ARG_SIZE (mode, type);
4238 /* Long long and SPE vectors are put in odd registers. */
4239 if (n_words == 2 && (gregno & 1) == 0)
4242 /* Long long do not split between registers and stack. */
4243 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4244 return gen_rtx_REG (mode, gregno);
4251 int align = (TARGET_32BIT && (cum->words & 1) != 0
4252 && function_arg_boundary (mode, type) == 64) ? 1 : 0;
4253 int align_words = cum->words + align;
4255 if (type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
4258 if (TARGET_32BIT && TARGET_POWERPC64
4259 && (mode == DFmode || mode == DImode || mode == BLKmode))
4260 return rs6000_mixed_function_arg (cum, mode, type, align_words);
4262 if (USE_FP_FOR_ARG_P (cum, mode, type))
4265 || ((cum->nargs_prototype > 0)
4266 /* IBM AIX extended its linkage convention definition always
4267 to require FP args after register save area hole on the
4269 && (DEFAULT_ABI != ABI_AIX
4271 || (align_words < GP_ARG_NUM_REG))))
4272 return gen_rtx_REG (mode, cum->fregno);
4274 return gen_rtx_PARALLEL (mode,
4276 gen_rtx_EXPR_LIST (VOIDmode,
4277 ((align_words >= GP_ARG_NUM_REG)
4280 + RS6000_ARG_SIZE (mode, type)
4282 /* If this is partially on the stack, then
4283 we only include the portion actually
4284 in registers here. */
4285 ? gen_rtx_REG (SImode,
4286 GP_ARG_MIN_REG + align_words)
4287 : gen_rtx_REG (mode,
4288 GP_ARG_MIN_REG + align_words))),
4290 gen_rtx_EXPR_LIST (VOIDmode,
4291 gen_rtx_REG (mode, cum->fregno),
4294 else if (align_words < GP_ARG_NUM_REG)
4295 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4301 /* For an arg passed partly in registers and partly in memory,
4302 this is the number of registers used.
4303 For args passed entirely in registers or entirely in memory, zero. */
4306 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4307 tree type, int named)
4309 if (DEFAULT_ABI == ABI_V4)
4312 if (USE_FP_FOR_ARG_P (cum, mode, type)
4313 || USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4315 if (cum->nargs_prototype >= 0)
4319 if (cum->words < GP_ARG_NUM_REG
4320 && GP_ARG_NUM_REG < (cum->words + RS6000_ARG_SIZE (mode, type)))
4322 int ret = GP_ARG_NUM_REG - cum->words;
4323 if (ret && TARGET_DEBUG_ARG)
4324 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
4332 /* A C expression that indicates when an argument must be passed by
4333 reference. If nonzero for an argument, a copy of that argument is
4334 made in memory and a pointer to the argument is passed instead of
4335 the argument itself. The pointer is passed in whatever way is
4336 appropriate for passing a pointer to that type.
4338 Under V.4, structures and unions are passed by reference.
4340 As an extension to all ABIs, variable sized types are passed by
4344 function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4345 enum machine_mode mode ATTRIBUTE_UNUSED,
4346 tree type, int named ATTRIBUTE_UNUSED)
4348 if (DEFAULT_ABI == ABI_V4
4349 && ((type && AGGREGATE_TYPE_P (type))
4352 if (TARGET_DEBUG_ARG)
4353 fprintf (stderr, "function_arg_pass_by_reference: aggregate\n");
4357 return type && int_size_in_bytes (type) < 0;
4361 rs6000_move_block_from_reg(int regno, rtx x, int nregs)
4364 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
4369 for (i = 0; i < nregs; i++)
4371 rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
4372 if (reload_completed)
4374 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
4377 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
4378 i * GET_MODE_SIZE(reg_mode));
4381 tem = replace_equiv_address (tem, XEXP (tem, 0));
4383 if (tem == NULL_RTX)
4386 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
4391 /* Perform any needed actions needed for a function that is receiving a
4392 variable number of arguments.
4396 MODE and TYPE are the mode and type of the current parameter.
4398 PRETEND_SIZE is a variable that should be set to the amount of stack
4399 that must be pushed by the prolog to pretend that our caller pushed
4402 Normally, this macro will push all remaining incoming registers on the
4403 stack and set PRETEND_SIZE to the length of the registers pushed. */
4406 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4407 tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
4409 CUMULATIVE_ARGS next_cum;
4410 int reg_size = TARGET_32BIT ? 4 : 8;
4411 rtx save_area = NULL_RTX, mem;
4412 int first_reg_offset, set;
4414 /* Skip the last named argument. */
4416 function_arg_advance (&next_cum, mode, type, 1);
4418 if (DEFAULT_ABI == ABI_V4)
4420 /* Indicate to allocate space on the stack for varargs save area. */
4421 cfun->machine->sysv_varargs_p = 1;
4423 save_area = plus_constant (virtual_stack_vars_rtx,
4424 - RS6000_VARARGS_SIZE);
4426 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
4430 first_reg_offset = next_cum.words;
4431 save_area = virtual_incoming_args_rtx;
4432 cfun->machine->sysv_varargs_p = 0;
4434 if (MUST_PASS_IN_STACK (mode, type))
4435 first_reg_offset += RS6000_ARG_SIZE (TYPE_MODE (type), type);
4438 set = get_varargs_alias_set ();
4439 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
4441 mem = gen_rtx_MEM (BLKmode,
4442 plus_constant (save_area,
4443 first_reg_offset * reg_size)),
4444 set_mem_alias_set (mem, set);
4445 set_mem_align (mem, BITS_PER_WORD);
4447 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
4448 GP_ARG_NUM_REG - first_reg_offset);
4451 /* Save FP registers if needed. */
4452 if (DEFAULT_ABI == ABI_V4
4453 && TARGET_HARD_FLOAT && TARGET_FPRS
4455 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
4457 int fregno = next_cum.fregno;
4458 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
4459 rtx lab = gen_label_rtx ();
4460 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
4462 emit_jump_insn (gen_rtx_SET (VOIDmode,
4464 gen_rtx_IF_THEN_ELSE (VOIDmode,
4465 gen_rtx_NE (VOIDmode, cr1,
4467 gen_rtx_LABEL_REF (VOIDmode, lab),
4470 while (fregno <= FP_ARG_V4_MAX_REG)
4472 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
4473 set_mem_alias_set (mem, set);
4474 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
4483 /* Create the va_list data type. */
4486 rs6000_build_builtin_va_list (void)
4488 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
4490 /* For AIX, prefer 'char *' because that's what the system
4491 header files like. */
4492 if (DEFAULT_ABI != ABI_V4)
4493 return build_pointer_type (char_type_node);
4495 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
4496 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
4498 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
4499 unsigned_char_type_node);
4500 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
4501 unsigned_char_type_node);
4502 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
4504 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
4505 short_unsigned_type_node);
4506 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
4508 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
4511 DECL_FIELD_CONTEXT (f_gpr) = record;
4512 DECL_FIELD_CONTEXT (f_fpr) = record;
4513 DECL_FIELD_CONTEXT (f_res) = record;
4514 DECL_FIELD_CONTEXT (f_ovf) = record;
4515 DECL_FIELD_CONTEXT (f_sav) = record;
4517 TREE_CHAIN (record) = type_decl;
4518 TYPE_NAME (record) = type_decl;
4519 TYPE_FIELDS (record) = f_gpr;
4520 TREE_CHAIN (f_gpr) = f_fpr;
4521 TREE_CHAIN (f_fpr) = f_res;
4522 TREE_CHAIN (f_res) = f_ovf;
4523 TREE_CHAIN (f_ovf) = f_sav;
4525 layout_type (record);
4527 /* The correct type is an array type of one element. */
4528 return build_array_type (record, build_index_type (size_zero_node));
4531 /* Implement va_start. */
4534 rs6000_va_start (tree valist, rtx nextarg)
4536 HOST_WIDE_INT words, n_gpr, n_fpr;
4537 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4538 tree gpr, fpr, ovf, sav, t;
4540 /* Only SVR4 needs something special. */
4541 if (DEFAULT_ABI != ABI_V4)
4543 std_expand_builtin_va_start (valist, nextarg);
4547 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4548 f_fpr = TREE_CHAIN (f_gpr);
4549 f_res = TREE_CHAIN (f_fpr);
4550 f_ovf = TREE_CHAIN (f_res);
4551 f_sav = TREE_CHAIN (f_ovf);
4553 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4554 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4555 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4556 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4557 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4559 /* Count number of gp and fp argument registers used. */
4560 words = current_function_args_info.words;
4561 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
4562 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
4564 if (TARGET_DEBUG_ARG)
4565 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
4566 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
4567 words, n_gpr, n_fpr);
4569 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, build_int_2 (n_gpr, 0));
4570 TREE_SIDE_EFFECTS (t) = 1;
4571 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4573 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, build_int_2 (n_fpr, 0));
4574 TREE_SIDE_EFFECTS (t) = 1;
4575 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4577 /* Find the overflow area. */
4578 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
4580 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
4581 build_int_2 (words * UNITS_PER_WORD, 0));
4582 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4583 TREE_SIDE_EFFECTS (t) = 1;
4584 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4586 /* Find the register save area. */
4587 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
4588 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
4589 build_int_2 (-RS6000_VARARGS_SIZE, -1));
4590 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
4591 TREE_SIDE_EFFECTS (t) = 1;
4592 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4595 /* Implement va_arg. */
4598 rs6000_va_arg (tree valist, tree type)
4600 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
4601 tree gpr, fpr, ovf, sav, reg, t, u;
4602 int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale;
4603 rtx lab_false, lab_over, addr_rtx, r;
4605 if (DEFAULT_ABI != ABI_V4)
4607 /* Variable sized types are passed by reference. */
4608 if (int_size_in_bytes (type) < 0)
4610 u = build_pointer_type (type);
4612 /* Args grow upward. */
4613 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
4614 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4615 TREE_SIDE_EFFECTS (t) = 1;
4617 t = build1 (NOP_EXPR, build_pointer_type (u), t);
4618 TREE_SIDE_EFFECTS (t) = 1;
4620 t = build1 (INDIRECT_REF, u, t);
4621 TREE_SIDE_EFFECTS (t) = 1;
4623 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4627 /* Altivec arguments must be aligned to a 128-bit boundary. */
4628 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4630 tree vtype = TREE_TYPE (valist);
4631 tree new_valist, modify;
4633 /* Round address up to multiple of 16. Computes
4635 new_valist = fold (build (BIT_AND_EXPR, vtype,
4636 fold (build (PLUS_EXPR, vtype, valist,
4637 build_int_2 (15, 0))),
4638 build_int_2 (~15, -1)));
4640 /* Update valist. */
4641 modify = build (MODIFY_EXPR, TREE_TYPE (valist), valist,
4643 TREE_SIDE_EFFECTS (modify) = 1;
4644 expand_expr (modify, const0_rtx, VOIDmode, EXPAND_NORMAL);
4647 return std_expand_builtin_va_arg (valist, type);
4651 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
4652 f_fpr = TREE_CHAIN (f_gpr);
4653 f_res = TREE_CHAIN (f_fpr);
4654 f_ovf = TREE_CHAIN (f_res);
4655 f_sav = TREE_CHAIN (f_ovf);
4657 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
4658 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr);
4659 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr);
4660 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf);
4661 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav);
4663 size = int_size_in_bytes (type);
4664 rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4666 if (AGGREGATE_TYPE_P (type) || TYPE_MODE (type) == TFmode)
4668 /* Aggregates and long doubles are passed by reference. */
4674 size = UNITS_PER_WORD;
4677 else if (FLOAT_TYPE_P (type) && TARGET_HARD_FLOAT && TARGET_FPRS)
4679 /* FP args go in FP registers, if present. */
4688 /* Otherwise into GP registers. */
4696 /* Pull the value out of the saved registers ... */
4698 lab_false = gen_label_rtx ();
4699 lab_over = gen_label_rtx ();
4700 addr_rtx = gen_reg_rtx (Pmode);
4702 /* AltiVec vectors never go in registers. */
4703 if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE)
4705 TREE_THIS_VOLATILE (reg) = 1;
4706 emit_cmp_and_jump_insns
4707 (expand_expr (reg, NULL_RTX, QImode, EXPAND_NORMAL),
4708 GEN_INT (8 - n_reg + 1), GE, const1_rtx, QImode, 1,
4711 /* Long long is aligned in the registers. */
4714 u = build (BIT_AND_EXPR, TREE_TYPE (reg), reg,
4715 build_int_2 (n_reg - 1, 0));
4716 u = build (PLUS_EXPR, TREE_TYPE (reg), reg, u);
4717 u = build (MODIFY_EXPR, TREE_TYPE (reg), reg, u);
4718 TREE_SIDE_EFFECTS (u) = 1;
4719 expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
4723 t = build (PLUS_EXPR, ptr_type_node, sav, build_int_2 (sav_ofs, 0));
4727 u = build (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
4728 build_int_2 (n_reg, 0));
4729 TREE_SIDE_EFFECTS (u) = 1;
4731 u = build1 (CONVERT_EXPR, integer_type_node, u);
4732 TREE_SIDE_EFFECTS (u) = 1;
4734 u = build (MULT_EXPR, integer_type_node, u, build_int_2 (sav_scale, 0));
4735 TREE_SIDE_EFFECTS (u) = 1;
4737 t = build (PLUS_EXPR, ptr_type_node, t, u);
4738 TREE_SIDE_EFFECTS (t) = 1;
4740 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4742 emit_move_insn (addr_rtx, r);
4744 emit_jump_insn (gen_jump (lab_over));
4748 emit_label (lab_false);
4750 /* ... otherwise out of the overflow area. */
4752 /* Make sure we don't find reg 7 for the next int arg.
4754 All AltiVec vectors go in the overflow area. So in the AltiVec
4755 case we need to get the vectors from the overflow area, but
4756 remember where the GPRs and FPRs are. */
4757 if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE
4758 || !TARGET_ALTIVEC))
4760 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0));
4761 TREE_SIDE_EFFECTS (t) = 1;
4762 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4765 /* Care for on-stack alignment if needed. */
4772 /* AltiVec vectors are 16 byte aligned. */
4773 if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE)
4778 t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align, 0));
4779 t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align-1, -1));
4783 r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL);
4785 emit_move_insn (addr_rtx, r);
4787 t = build (PLUS_EXPR, TREE_TYPE (t), t, build_int_2 (size, 0));
4788 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
4789 TREE_SIDE_EFFECTS (t) = 1;
4790 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
4792 emit_label (lab_over);
4796 r = gen_rtx_MEM (Pmode, addr_rtx);
4797 set_mem_alias_set (r, get_varargs_alias_set ());
4798 emit_move_insn (addr_rtx, r);
4806 #define def_builtin(MASK, NAME, TYPE, CODE) \
4808 if ((MASK) & target_flags) \
4809 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
4813 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
4815 static const struct builtin_description bdesc_3arg[] =
4817 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
4818 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
4819 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
4820 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
4821 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
4822 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
4823 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
4824 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
4825 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
4826 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
4827 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
4828 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
4829 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
4830 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
4831 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
4832 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
4833 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
4834 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
4835 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
4836 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
4837 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
4838 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
4839 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
4842 /* DST operations: void foo (void *, const int, const char). */
4844 static const struct builtin_description bdesc_dst[] =
4846 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
4847 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
4848 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
4849 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
4852 /* Simple binary operations: VECc = foo (VECa, VECb). */
4854 static struct builtin_description bdesc_2arg[] =
4856 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
4857 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
4858 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
4859 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
4860 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
4861 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
4862 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
4863 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
4864 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
4865 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
4866 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
4867 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
4868 { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
4869 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
4870 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
4871 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
4872 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
4873 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
4874 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
4875 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
4876 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
4877 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
4878 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
4879 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
4880 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
4881 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
4882 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
4883 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
4884 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
4885 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
4886 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
4887 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
4888 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
4889 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
4890 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
4891 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
4892 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
4893 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
4894 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
4895 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
4896 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
4897 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
4898 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
4899 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
4900 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
4901 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
4902 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
4903 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
4904 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
4905 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
4906 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
4907 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
4908 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
4909 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
4910 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
4911 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
4912 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
4913 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
4914 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
4915 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
4916 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
4917 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
4918 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
4919 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
4920 { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
4921 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
4922 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
4923 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
4924 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
4925 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
4926 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
4927 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
4928 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
4929 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
4930 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
4931 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
4932 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
4933 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
4934 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
4935 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
4936 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
4937 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
4938 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
4939 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
4940 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
4941 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
4942 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
4943 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
4944 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
4945 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
4946 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
4947 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
4948 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
4949 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
4950 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
4951 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
4952 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
4953 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
4954 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
4955 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
4956 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
4957 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
4958 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
4959 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
4960 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
4961 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
4962 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
4963 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
4964 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
4965 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
4966 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
4967 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
4968 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
4970 /* Place holder, leave as first spe builtin. */
4971 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
4972 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
4973 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
4974 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
4975 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
4976 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
4977 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
4978 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
4979 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
4980 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
4981 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
4982 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
4983 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
4984 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
4985 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
4986 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
4987 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
4988 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
4989 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
4990 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
4991 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
4992 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
4993 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
4994 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
4995 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
4996 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
4997 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
4998 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
4999 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5000 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5001 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5002 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5003 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5004 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5005 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5006 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5007 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5008 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5009 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5010 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5011 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5012 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5013 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5014 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5015 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5016 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5017 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5018 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5019 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5020 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5021 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5022 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5023 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5024 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5025 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5026 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5027 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5028 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5029 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5030 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5031 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5032 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5033 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5034 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5035 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5036 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5037 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5038 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5039 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5040 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5041 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5042 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5043 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5044 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
5045 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5046 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
5047 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5048 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5049 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5050 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5051 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5052 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5053 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5054 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5055 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5056 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5057 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5058 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5059 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5060 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5061 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5062 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5063 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5064 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5065 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5066 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5067 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5068 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5069 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5070 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5071 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5072 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5073 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5074 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5075 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5076 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5077 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5078 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5079 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5081 /* SPE binary operations expecting a 5-bit unsigned literal. */
5082 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5084 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5085 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5086 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5087 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5088 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5089 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5090 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5091 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5092 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5093 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5094 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5095 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5096 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5097 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5098 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5099 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5100 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5101 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5102 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5103 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5104 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5105 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5106 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5107 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5108 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5109 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5111 /* Place-holder. Leave as last binary SPE builtin. */
5112 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
5115 /* AltiVec predicates. */
5117 struct builtin_description_predicates
5119 const unsigned int mask;
5120 const enum insn_code icode;
5122 const char *const name;
5123 const enum rs6000_builtins code;
5126 static const struct builtin_description_predicates bdesc_altivec_preds[] =
5128 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5129 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5130 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5131 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5132 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5133 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5134 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5135 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5136 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5137 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5138 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5139 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5140 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
5143 /* SPE predicates. */
5144 static struct builtin_description bdesc_spe_predicates[] =
5146 /* Place-holder. Leave as first. */
5147 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5148 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5149 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5150 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5151 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5152 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5153 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5154 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5155 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5156 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5157 /* Place-holder. Leave as last. */
5158 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5161 /* SPE evsel predicates. */
5162 static struct builtin_description bdesc_spe_evsel[] =
5164 /* Place-holder. Leave as first. */
5165 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5166 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5167 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5168 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5169 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5170 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5171 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5172 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5173 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5174 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5175 /* Place-holder. Leave as last. */
5176 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5179 /* ABS* operations. */
5181 static const struct builtin_description bdesc_abs[] =
5183 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5184 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5185 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5186 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5187 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5188 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5189 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5192 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5195 static struct builtin_description bdesc_1arg[] =
5197 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5198 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5199 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5200 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5201 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5202 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5203 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5204 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
5205 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5206 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5207 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
5208 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5209 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5210 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5211 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5212 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5213 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
5215 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5216 end with SPE_BUILTIN_EVSUBFUSIAAW. */
5217 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5218 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5219 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5220 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5221 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5222 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5223 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5224 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5225 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5226 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5227 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5228 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5229 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5230 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5231 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5232 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5233 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5234 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5235 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5236 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5237 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5238 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5239 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
5240 { 0, CODE_FOR_spe_evneg, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
5241 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5242 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5243 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5244 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
5246 /* Place-holder. Leave as last unary SPE builtin. */
5247 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
5251 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
5254 tree arg0 = TREE_VALUE (arglist);
5255 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5256 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5257 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5259 if (icode == CODE_FOR_nothing)
5260 /* Builtin not supported on this processor. */
5263 /* If we got invalid arguments bail out before generating bad rtl. */
5264 if (arg0 == error_mark_node)
5267 if (icode == CODE_FOR_altivec_vspltisb
5268 || icode == CODE_FOR_altivec_vspltish
5269 || icode == CODE_FOR_altivec_vspltisw
5270 || icode == CODE_FOR_spe_evsplatfi
5271 || icode == CODE_FOR_spe_evsplati)
5273 /* Only allow 5-bit *signed* literals. */
5274 if (GET_CODE (op0) != CONST_INT
5275 || INTVAL (op0) > 0x1f
5276 || INTVAL (op0) < -0x1f)
5278 error ("argument 1 must be a 5-bit signed literal");
5284 || GET_MODE (target) != tmode
5285 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5286 target = gen_reg_rtx (tmode);
5288 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5289 op0 = copy_to_mode_reg (mode0, op0);
5291 pat = GEN_FCN (icode) (target, op0);
5300 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
5302 rtx pat, scratch1, scratch2;
5303 tree arg0 = TREE_VALUE (arglist);
5304 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5305 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5306 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5308 /* If we have invalid arguments, bail out before generating bad rtl. */
5309 if (arg0 == error_mark_node)
5313 || GET_MODE (target) != tmode
5314 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5315 target = gen_reg_rtx (tmode);
5317 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5318 op0 = copy_to_mode_reg (mode0, op0);
5320 scratch1 = gen_reg_rtx (mode0);
5321 scratch2 = gen_reg_rtx (mode0);
5323 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
5332 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
5335 tree arg0 = TREE_VALUE (arglist);
5336 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5337 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5338 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5339 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5340 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5341 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5343 if (icode == CODE_FOR_nothing)
5344 /* Builtin not supported on this processor. */
5347 /* If we got invalid arguments bail out before generating bad rtl. */
5348 if (arg0 == error_mark_node || arg1 == error_mark_node)
5351 if (icode == CODE_FOR_altivec_vcfux
5352 || icode == CODE_FOR_altivec_vcfsx
5353 || icode == CODE_FOR_altivec_vctsxs
5354 || icode == CODE_FOR_altivec_vctuxs
5355 || icode == CODE_FOR_altivec_vspltb
5356 || icode == CODE_FOR_altivec_vsplth
5357 || icode == CODE_FOR_altivec_vspltw
5358 || icode == CODE_FOR_spe_evaddiw
5359 || icode == CODE_FOR_spe_evldd
5360 || icode == CODE_FOR_spe_evldh
5361 || icode == CODE_FOR_spe_evldw
5362 || icode == CODE_FOR_spe_evlhhesplat
5363 || icode == CODE_FOR_spe_evlhhossplat
5364 || icode == CODE_FOR_spe_evlhhousplat
5365 || icode == CODE_FOR_spe_evlwhe
5366 || icode == CODE_FOR_spe_evlwhos
5367 || icode == CODE_FOR_spe_evlwhou
5368 || icode == CODE_FOR_spe_evlwhsplat
5369 || icode == CODE_FOR_spe_evlwwsplat
5370 || icode == CODE_FOR_spe_evrlwi
5371 || icode == CODE_FOR_spe_evslwi
5372 || icode == CODE_FOR_spe_evsrwis
5373 || icode == CODE_FOR_spe_evsubifw
5374 || icode == CODE_FOR_spe_evsrwiu)
5376 /* Only allow 5-bit unsigned literals. */
5377 if (TREE_CODE (arg1) != INTEGER_CST
5378 || TREE_INT_CST_LOW (arg1) & ~0x1f)
5380 error ("argument 2 must be a 5-bit unsigned literal");
5386 || GET_MODE (target) != tmode
5387 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5388 target = gen_reg_rtx (tmode);
5390 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5391 op0 = copy_to_mode_reg (mode0, op0);
5392 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5393 op1 = copy_to_mode_reg (mode1, op1);
5395 pat = GEN_FCN (icode) (target, op0, op1);
5404 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
5405 tree arglist, rtx target)
5408 tree cr6_form = TREE_VALUE (arglist);
5409 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
5410 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5411 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5412 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5413 enum machine_mode tmode = SImode;
5414 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5415 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5418 if (TREE_CODE (cr6_form) != INTEGER_CST)
5420 error ("argument 1 of __builtin_altivec_predicate must be a constant");
5424 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
5429 /* If we have invalid arguments, bail out before generating bad rtl. */
5430 if (arg0 == error_mark_node || arg1 == error_mark_node)
5434 || GET_MODE (target) != tmode
5435 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5436 target = gen_reg_rtx (tmode);
5438 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5439 op0 = copy_to_mode_reg (mode0, op0);
5440 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5441 op1 = copy_to_mode_reg (mode1, op1);
5443 scratch = gen_reg_rtx (mode0);
5445 pat = GEN_FCN (icode) (scratch, op0, op1,
5446 gen_rtx (SYMBOL_REF, Pmode, opcode));
5451 /* The vec_any* and vec_all* predicates use the same opcodes for two
5452 different operations, but the bits in CR6 will be different
5453 depending on what information we want. So we have to play tricks
5454 with CR6 to get the right bits out.
5456 If you think this is disgusting, look at the specs for the
5457 AltiVec predicates. */
5459 switch (cr6_form_int)
5462 emit_insn (gen_cr6_test_for_zero (target));
5465 emit_insn (gen_cr6_test_for_zero_reverse (target));
5468 emit_insn (gen_cr6_test_for_lt (target));
5471 emit_insn (gen_cr6_test_for_lt_reverse (target));
5474 error ("argument 1 of __builtin_altivec_predicate is out of range");
5482 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
5485 tree arg0 = TREE_VALUE (arglist);
5486 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5487 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5488 enum machine_mode mode0 = Pmode;
5489 enum machine_mode mode1 = Pmode;
5490 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5491 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5493 if (icode == CODE_FOR_nothing)
5494 /* Builtin not supported on this processor. */
5497 /* If we got invalid arguments bail out before generating bad rtl. */
5498 if (arg0 == error_mark_node || arg1 == error_mark_node)
5502 || GET_MODE (target) != tmode
5503 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5504 target = gen_reg_rtx (tmode);
5506 op1 = copy_to_mode_reg (mode1, op1);
5508 if (op0 == const0_rtx)
5510 addr = gen_rtx_MEM (tmode, op1);
5514 op0 = copy_to_mode_reg (mode0, op0);
5515 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
5518 pat = GEN_FCN (icode) (target, addr);
5528 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
5530 tree arg0 = TREE_VALUE (arglist);
5531 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5532 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5533 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5534 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5535 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5537 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5538 enum machine_mode mode1 = Pmode;
5539 enum machine_mode mode2 = Pmode;
5541 /* Invalid arguments. Bail before doing anything stoopid! */
5542 if (arg0 == error_mark_node
5543 || arg1 == error_mark_node
5544 || arg2 == error_mark_node)
5547 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
5548 op0 = copy_to_mode_reg (tmode, op0);
5550 op2 = copy_to_mode_reg (mode2, op2);
5552 if (op1 == const0_rtx)
5554 addr = gen_rtx_MEM (tmode, op2);
5558 op1 = copy_to_mode_reg (mode1, op1);
5559 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
5562 pat = GEN_FCN (icode) (addr, op0);
5569 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
5572 tree arg0 = TREE_VALUE (arglist);
5573 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5574 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5575 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5576 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5577 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5578 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5579 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5580 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5581 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
5583 if (icode == CODE_FOR_nothing)
5584 /* Builtin not supported on this processor. */
5587 /* If we got invalid arguments bail out before generating bad rtl. */
5588 if (arg0 == error_mark_node
5589 || arg1 == error_mark_node
5590 || arg2 == error_mark_node)
5593 if (icode == CODE_FOR_altivec_vsldoi_4sf
5594 || icode == CODE_FOR_altivec_vsldoi_4si
5595 || icode == CODE_FOR_altivec_vsldoi_8hi
5596 || icode == CODE_FOR_altivec_vsldoi_16qi)
5598 /* Only allow 4-bit unsigned literals. */
5599 if (TREE_CODE (arg2) != INTEGER_CST
5600 || TREE_INT_CST_LOW (arg2) & ~0xf)
5602 error ("argument 3 must be a 4-bit unsigned literal");
5608 || GET_MODE (target) != tmode
5609 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5610 target = gen_reg_rtx (tmode);
5612 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5613 op0 = copy_to_mode_reg (mode0, op0);
5614 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
5615 op1 = copy_to_mode_reg (mode1, op1);
5616 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
5617 op2 = copy_to_mode_reg (mode2, op2);
5619 pat = GEN_FCN (icode) (target, op0, op1, op2);
5627 /* Expand the lvx builtins. */
5629 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
5631 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5632 tree arglist = TREE_OPERAND (exp, 1);
5633 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5635 enum machine_mode tmode, mode0;
5637 enum insn_code icode;
5641 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
5642 icode = CODE_FOR_altivec_lvx_16qi;
5644 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
5645 icode = CODE_FOR_altivec_lvx_8hi;
5647 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
5648 icode = CODE_FOR_altivec_lvx_4si;
5650 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
5651 icode = CODE_FOR_altivec_lvx_4sf;
5660 arg0 = TREE_VALUE (arglist);
5661 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5662 tmode = insn_data[icode].operand[0].mode;
5663 mode0 = insn_data[icode].operand[1].mode;
5666 || GET_MODE (target) != tmode
5667 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5668 target = gen_reg_rtx (tmode);
5670 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5671 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5673 pat = GEN_FCN (icode) (target, op0);
5680 /* Expand the stvx builtins. */
5682 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
5685 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5686 tree arglist = TREE_OPERAND (exp, 1);
5687 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5689 enum machine_mode mode0, mode1;
5691 enum insn_code icode;
5695 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
5696 icode = CODE_FOR_altivec_stvx_16qi;
5698 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
5699 icode = CODE_FOR_altivec_stvx_8hi;
5701 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
5702 icode = CODE_FOR_altivec_stvx_4si;
5704 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
5705 icode = CODE_FOR_altivec_stvx_4sf;
5712 arg0 = TREE_VALUE (arglist);
5713 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5714 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5715 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5716 mode0 = insn_data[icode].operand[0].mode;
5717 mode1 = insn_data[icode].operand[1].mode;
5719 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
5720 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5721 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
5722 op1 = copy_to_mode_reg (mode1, op1);
5724 pat = GEN_FCN (icode) (op0, op1);
5732 /* Expand the dst builtins. */
5734 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
5737 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5738 tree arglist = TREE_OPERAND (exp, 1);
5739 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5740 tree arg0, arg1, arg2;
5741 enum machine_mode mode0, mode1, mode2;
5742 rtx pat, op0, op1, op2;
5743 struct builtin_description *d;
5748 /* Handle DST variants. */
5749 d = (struct builtin_description *) bdesc_dst;
5750 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
5751 if (d->code == fcode)
5753 arg0 = TREE_VALUE (arglist);
5754 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5755 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
5756 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5757 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5758 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
5759 mode0 = insn_data[d->icode].operand[0].mode;
5760 mode1 = insn_data[d->icode].operand[1].mode;
5761 mode2 = insn_data[d->icode].operand[2].mode;
5763 /* Invalid arguments, bail out before generating bad rtl. */
5764 if (arg0 == error_mark_node
5765 || arg1 == error_mark_node
5766 || arg2 == error_mark_node)
5769 if (TREE_CODE (arg2) != INTEGER_CST
5770 || TREE_INT_CST_LOW (arg2) & ~0x3)
5772 error ("argument to `%s' must be a 2-bit unsigned literal", d->name);
5776 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
5777 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
5778 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
5779 op1 = copy_to_mode_reg (mode1, op1);
5781 pat = GEN_FCN (d->icode) (op0, op1, op2);
5792 /* Expand the builtin in EXP and store the result in TARGET. Store
5793 true in *EXPANDEDP if we found a builtin to expand. */
5795 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
5797 struct builtin_description *d;
5798 struct builtin_description_predicates *dp;
5800 enum insn_code icode;
5801 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5802 tree arglist = TREE_OPERAND (exp, 1);
5805 enum machine_mode tmode, mode0;
5806 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5808 target = altivec_expand_ld_builtin (exp, target, expandedp);
5812 target = altivec_expand_st_builtin (exp, target, expandedp);
5816 target = altivec_expand_dst_builtin (exp, target, expandedp);
5824 case ALTIVEC_BUILTIN_STVX:
5825 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
5826 case ALTIVEC_BUILTIN_STVEBX:
5827 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
5828 case ALTIVEC_BUILTIN_STVEHX:
5829 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
5830 case ALTIVEC_BUILTIN_STVEWX:
5831 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
5832 case ALTIVEC_BUILTIN_STVXL:
5833 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
5835 case ALTIVEC_BUILTIN_MFVSCR:
5836 icode = CODE_FOR_altivec_mfvscr;
5837 tmode = insn_data[icode].operand[0].mode;
5840 || GET_MODE (target) != tmode
5841 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5842 target = gen_reg_rtx (tmode);
5844 pat = GEN_FCN (icode) (target);
5850 case ALTIVEC_BUILTIN_MTVSCR:
5851 icode = CODE_FOR_altivec_mtvscr;
5852 arg0 = TREE_VALUE (arglist);
5853 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5854 mode0 = insn_data[icode].operand[0].mode;
5856 /* If we got invalid arguments bail out before generating bad rtl. */
5857 if (arg0 == error_mark_node)
5860 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
5861 op0 = copy_to_mode_reg (mode0, op0);
5863 pat = GEN_FCN (icode) (op0);
5868 case ALTIVEC_BUILTIN_DSSALL:
5869 emit_insn (gen_altivec_dssall ());
5872 case ALTIVEC_BUILTIN_DSS:
5873 icode = CODE_FOR_altivec_dss;
5874 arg0 = TREE_VALUE (arglist);
5875 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5876 mode0 = insn_data[icode].operand[0].mode;
5878 /* If we got invalid arguments bail out before generating bad rtl. */
5879 if (arg0 == error_mark_node)
5882 if (TREE_CODE (arg0) != INTEGER_CST
5883 || TREE_INT_CST_LOW (arg0) & ~0x3)
5885 error ("argument to dss must be a 2-bit unsigned literal");
5889 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
5890 op0 = copy_to_mode_reg (mode0, op0);
5892 emit_insn (gen_altivec_dss (op0));
5896 /* Expand abs* operations. */
5897 d = (struct builtin_description *) bdesc_abs;
5898 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
5899 if (d->code == fcode)
5900 return altivec_expand_abs_builtin (d->icode, arglist, target);
5902 /* Expand the AltiVec predicates. */
5903 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
5904 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
5905 if (dp->code == fcode)
5906 return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target);
5908 /* LV* are funky. We initialized them differently. */
5911 case ALTIVEC_BUILTIN_LVSL:
5912 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
5914 case ALTIVEC_BUILTIN_LVSR:
5915 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
5917 case ALTIVEC_BUILTIN_LVEBX:
5918 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
5920 case ALTIVEC_BUILTIN_LVEHX:
5921 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
5923 case ALTIVEC_BUILTIN_LVEWX:
5924 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
5926 case ALTIVEC_BUILTIN_LVXL:
5927 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
5929 case ALTIVEC_BUILTIN_LVX:
5930 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
5941 /* Binops that need to be initialized manually, but can be expanded
5942 automagically by rs6000_expand_binop_builtin. */
5943 static struct builtin_description bdesc_2arg_spe[] =
5945 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
5946 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
5947 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
5948 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
5949 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
5950 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
5951 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
5952 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
5953 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
5954 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
5955 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
5956 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
5957 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
5958 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
5959 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
5960 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
5961 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
5962 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
5963 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
5964 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
5965 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
5966 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
5969 /* Expand the builtin in EXP and store the result in TARGET. Store
5970 true in *EXPANDEDP if we found a builtin to expand.
5972 This expands the SPE builtins that are not simple unary and binary
5975 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
5977 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
5978 tree arglist = TREE_OPERAND (exp, 1);
5980 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
5981 enum insn_code icode;
5982 enum machine_mode tmode, mode0;
5984 struct builtin_description *d;
5989 /* Syntax check for a 5-bit unsigned immediate. */
5992 case SPE_BUILTIN_EVSTDD:
5993 case SPE_BUILTIN_EVSTDH:
5994 case SPE_BUILTIN_EVSTDW:
5995 case SPE_BUILTIN_EVSTWHE:
5996 case SPE_BUILTIN_EVSTWHO:
5997 case SPE_BUILTIN_EVSTWWE:
5998 case SPE_BUILTIN_EVSTWWO:
5999 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6000 if (TREE_CODE (arg1) != INTEGER_CST
6001 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6003 error ("argument 2 must be a 5-bit unsigned literal");
6011 /* The evsplat*i instructions are not quite generic. */
6014 case SPE_BUILTIN_EVSPLATFI:
6015 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6017 case SPE_BUILTIN_EVSPLATI:
6018 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6024 d = (struct builtin_description *) bdesc_2arg_spe;
6025 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6026 if (d->code == fcode)
6027 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6029 d = (struct builtin_description *) bdesc_spe_predicates;
6030 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6031 if (d->code == fcode)
6032 return spe_expand_predicate_builtin (d->icode, arglist, target);
6034 d = (struct builtin_description *) bdesc_spe_evsel;
6035 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6036 if (d->code == fcode)
6037 return spe_expand_evsel_builtin (d->icode, arglist, target);
6041 case SPE_BUILTIN_EVSTDDX:
6042 return altivec_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
6043 case SPE_BUILTIN_EVSTDHX:
6044 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
6045 case SPE_BUILTIN_EVSTDWX:
6046 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
6047 case SPE_BUILTIN_EVSTWHEX:
6048 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
6049 case SPE_BUILTIN_EVSTWHOX:
6050 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
6051 case SPE_BUILTIN_EVSTWWEX:
6052 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
6053 case SPE_BUILTIN_EVSTWWOX:
6054 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
6055 case SPE_BUILTIN_EVSTDD:
6056 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
6057 case SPE_BUILTIN_EVSTDH:
6058 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
6059 case SPE_BUILTIN_EVSTDW:
6060 return altivec_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
6061 case SPE_BUILTIN_EVSTWHE:
6062 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
6063 case SPE_BUILTIN_EVSTWHO:
6064 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
6065 case SPE_BUILTIN_EVSTWWE:
6066 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
6067 case SPE_BUILTIN_EVSTWWO:
6068 return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
6069 case SPE_BUILTIN_MFSPEFSCR:
6070 icode = CODE_FOR_spe_mfspefscr;
6071 tmode = insn_data[icode].operand[0].mode;
6074 || GET_MODE (target) != tmode
6075 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6076 target = gen_reg_rtx (tmode);
6078 pat = GEN_FCN (icode) (target);
6083 case SPE_BUILTIN_MTSPEFSCR:
6084 icode = CODE_FOR_spe_mtspefscr;
6085 arg0 = TREE_VALUE (arglist);
6086 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6087 mode0 = insn_data[icode].operand[0].mode;
6089 if (arg0 == error_mark_node)
6092 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6093 op0 = copy_to_mode_reg (mode0, op0);
6095 pat = GEN_FCN (icode) (op0);
6108 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
6110 rtx pat, scratch, tmp;
6111 tree form = TREE_VALUE (arglist);
6112 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6113 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6114 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6115 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6116 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6117 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6121 if (TREE_CODE (form) != INTEGER_CST)
6123 error ("argument 1 of __builtin_spe_predicate must be a constant");
6127 form_int = TREE_INT_CST_LOW (form);
6132 if (arg0 == error_mark_node || arg1 == error_mark_node)
6136 || GET_MODE (target) != SImode
6137 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6138 target = gen_reg_rtx (SImode);
6140 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6141 op0 = copy_to_mode_reg (mode0, op0);
6142 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6143 op1 = copy_to_mode_reg (mode1, op1);
6145 scratch = gen_reg_rtx (CCmode);
6147 pat = GEN_FCN (icode) (scratch, op0, op1);
6152 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6153 _lower_. We use one compare, but look in different bits of the
6154 CR for each variant.
6156 There are 2 elements in each SPE simd type (upper/lower). The CR
6157 bits are set as follows:
6159 BIT0 | BIT 1 | BIT 2 | BIT 3
6160 U | L | (U | L) | (U & L)
6162 So, for an "all" relationship, BIT 3 would be set.
6163 For an "any" relationship, BIT 2 would be set. Etc.
6165 Following traditional nomenclature, these bits map to:
6167 BIT0 | BIT 1 | BIT 2 | BIT 3
6170 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6175 /* All variant. OV bit. */
6177 /* We need to get to the OV bit, which is the ORDERED bit. We
6178 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6179 that's ugly and will trigger a validate_condition_mode abort.
6180 So let's just use another pattern. */
6181 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6183 /* Any variant. EQ bit. */
6187 /* Upper variant. LT bit. */
6191 /* Lower variant. GT bit. */
6196 error ("argument 1 of __builtin_spe_predicate is out of range");
6200 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6201 emit_move_insn (target, tmp);
6206 /* The evsel builtins look like this:
6208 e = __builtin_spe_evsel_OP (a, b, c, d);
6212 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6213 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6217 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
6220 tree arg0 = TREE_VALUE (arglist);
6221 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6222 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6223 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6224 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6225 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6226 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6227 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6228 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6229 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6234 if (arg0 == error_mark_node || arg1 == error_mark_node
6235 || arg2 == error_mark_node || arg3 == error_mark_node)
6239 || GET_MODE (target) != mode0
6240 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6241 target = gen_reg_rtx (mode0);
6243 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6244 op0 = copy_to_mode_reg (mode0, op0);
6245 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6246 op1 = copy_to_mode_reg (mode0, op1);
6247 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6248 op2 = copy_to_mode_reg (mode0, op2);
6249 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6250 op3 = copy_to_mode_reg (mode0, op3);
6252 /* Generate the compare. */
6253 scratch = gen_reg_rtx (CCmode);
6254 pat = GEN_FCN (icode) (scratch, op0, op1);
6259 if (mode0 == V2SImode)
6260 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
6262 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
6267 /* Expand an expression EXP that calls a built-in function,
6268 with result going to TARGET if that's convenient
6269 (and in mode MODE if that's convenient).
6270 SUBTARGET may be used as the target for computing one of EXP's operands.
6271 IGNORE is nonzero if the value is to be ignored. */
6274 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
6275 enum machine_mode mode ATTRIBUTE_UNUSED,
6276 int ignore ATTRIBUTE_UNUSED)
6278 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6279 tree arglist = TREE_OPERAND (exp, 1);
6280 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6281 struct builtin_description *d;
6288 ret = altivec_expand_builtin (exp, target, &success);
6295 ret = spe_expand_builtin (exp, target, &success);
6301 if (TARGET_ALTIVEC || TARGET_SPE)
6303 /* Handle simple unary operations. */
6304 d = (struct builtin_description *) bdesc_1arg;
6305 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
6306 if (d->code == fcode)
6307 return rs6000_expand_unop_builtin (d->icode, arglist, target);
6309 /* Handle simple binary operations. */
6310 d = (struct builtin_description *) bdesc_2arg;
6311 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
6312 if (d->code == fcode)
6313 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6315 /* Handle simple ternary operations. */
6316 d = (struct builtin_description *) bdesc_3arg;
6317 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
6318 if (d->code == fcode)
6319 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
6327 rs6000_init_builtins (void)
6329 opaque_V2SI_type_node = copy_node (V2SI_type_node);
6330 opaque_V2SF_type_node = copy_node (V2SF_type_node);
6331 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
6334 spe_init_builtins ();
6336 altivec_init_builtins ();
6337 if (TARGET_ALTIVEC || TARGET_SPE)
6338 rs6000_common_init_builtins ();
6341 /* Search through a set of builtins and enable the mask bits.
6342 DESC is an array of builtins.
6343 SIZE is the total number of builtins.
6344 START is the builtin enum at which to start.
6345 END is the builtin enum at which to end. */
6347 enable_mask_for_builtins (struct builtin_description *desc, int size,
6348 enum rs6000_builtins start,
6349 enum rs6000_builtins end)
6353 for (i = 0; i < size; ++i)
6354 if (desc[i].code == start)
6360 for (; i < size; ++i)
6362 /* Flip all the bits on. */
6363 desc[i].mask = target_flags;
6364 if (desc[i].code == end)
6370 spe_init_builtins (void)
6372 tree endlink = void_list_node;
6373 tree puint_type_node = build_pointer_type (unsigned_type_node);
6374 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
6375 struct builtin_description *d;
6378 tree v2si_ftype_4_v2si
6379 = build_function_type
6380 (opaque_V2SI_type_node,
6381 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6382 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6383 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6384 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6387 tree v2sf_ftype_4_v2sf
6388 = build_function_type
6389 (opaque_V2SF_type_node,
6390 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6391 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6392 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6393 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6396 tree int_ftype_int_v2si_v2si
6397 = build_function_type
6399 tree_cons (NULL_TREE, integer_type_node,
6400 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6401 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6404 tree int_ftype_int_v2sf_v2sf
6405 = build_function_type
6407 tree_cons (NULL_TREE, integer_type_node,
6408 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6409 tree_cons (NULL_TREE, opaque_V2SF_type_node,
6412 tree void_ftype_v2si_puint_int
6413 = build_function_type (void_type_node,
6414 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6415 tree_cons (NULL_TREE, puint_type_node,
6416 tree_cons (NULL_TREE,
6420 tree void_ftype_v2si_puint_char
6421 = build_function_type (void_type_node,
6422 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6423 tree_cons (NULL_TREE, puint_type_node,
6424 tree_cons (NULL_TREE,
6428 tree void_ftype_v2si_pv2si_int
6429 = build_function_type (void_type_node,
6430 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6431 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6432 tree_cons (NULL_TREE,
6436 tree void_ftype_v2si_pv2si_char
6437 = build_function_type (void_type_node,
6438 tree_cons (NULL_TREE, opaque_V2SI_type_node,
6439 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6440 tree_cons (NULL_TREE,
6445 = build_function_type (void_type_node,
6446 tree_cons (NULL_TREE, integer_type_node, endlink));
6449 = build_function_type (integer_type_node, endlink);
6451 tree v2si_ftype_pv2si_int
6452 = build_function_type (opaque_V2SI_type_node,
6453 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
6454 tree_cons (NULL_TREE, integer_type_node,
6457 tree v2si_ftype_puint_int
6458 = build_function_type (opaque_V2SI_type_node,
6459 tree_cons (NULL_TREE, puint_type_node,
6460 tree_cons (NULL_TREE, integer_type_node,
6463 tree v2si_ftype_pushort_int
6464 = build_function_type (opaque_V2SI_type_node,
6465 tree_cons (NULL_TREE, pushort_type_node,
6466 tree_cons (NULL_TREE, integer_type_node,
6469 tree v2si_ftype_signed_char
6470 = build_function_type (opaque_V2SI_type_node,
6471 tree_cons (NULL_TREE, signed_char_type_node,
6474 /* The initialization of the simple binary and unary builtins is
6475 done in rs6000_common_init_builtins, but we have to enable the
6476 mask bits here manually because we have run out of `target_flags'
6477 bits. We really need to redesign this mask business. */
6479 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
6480 ARRAY_SIZE (bdesc_2arg),
6483 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
6484 ARRAY_SIZE (bdesc_1arg),
6486 SPE_BUILTIN_EVSUBFUSIAAW);
6487 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
6488 ARRAY_SIZE (bdesc_spe_predicates),
6489 SPE_BUILTIN_EVCMPEQ,
6490 SPE_BUILTIN_EVFSTSTLT);
6491 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
6492 ARRAY_SIZE (bdesc_spe_evsel),
6493 SPE_BUILTIN_EVSEL_CMPGTS,
6494 SPE_BUILTIN_EVSEL_FSTSTEQ);
6496 (*lang_hooks.decls.pushdecl)
6497 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
6498 opaque_V2SI_type_node));
6500 /* Initialize irregular SPE builtins. */
6502 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
6503 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
6504 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
6505 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
6506 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
6507 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
6508 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
6509 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
6510 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
6511 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
6512 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
6513 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
6514 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
6515 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
6516 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
6517 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
6518 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
6519 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
6522 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
6523 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
6524 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
6525 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
6526 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
6527 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
6528 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
6529 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
6530 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
6531 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
6532 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
6533 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
6534 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
6535 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
6536 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
6537 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
6538 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
6539 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
6540 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
6541 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
6542 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
6543 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
6546 d = (struct builtin_description *) bdesc_spe_predicates;
6547 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
6551 switch (insn_data[d->icode].operand[1].mode)
6554 type = int_ftype_int_v2si_v2si;
6557 type = int_ftype_int_v2sf_v2sf;
6563 def_builtin (d->mask, d->name, type, d->code);
6566 /* Evsel predicates. */
6567 d = (struct builtin_description *) bdesc_spe_evsel;
6568 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
6572 switch (insn_data[d->icode].operand[1].mode)
6575 type = v2si_ftype_4_v2si;
6578 type = v2sf_ftype_4_v2sf;
6584 def_builtin (d->mask, d->name, type, d->code);
6589 altivec_init_builtins (void)
6591 struct builtin_description *d;
6592 struct builtin_description_predicates *dp;
6594 tree pfloat_type_node = build_pointer_type (float_type_node);
6595 tree pint_type_node = build_pointer_type (integer_type_node);
6596 tree pshort_type_node = build_pointer_type (short_integer_type_node);
6597 tree pchar_type_node = build_pointer_type (char_type_node);
6599 tree pvoid_type_node = build_pointer_type (void_type_node);
6601 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
6602 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
6603 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
6604 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
6606 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
6608 tree int_ftype_int_v4si_v4si
6609 = build_function_type_list (integer_type_node,
6610 integer_type_node, V4SI_type_node,
6611 V4SI_type_node, NULL_TREE);
6612 tree v4sf_ftype_pcfloat
6613 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
6614 tree void_ftype_pfloat_v4sf
6615 = build_function_type_list (void_type_node,
6616 pfloat_type_node, V4SF_type_node, NULL_TREE);
6617 tree v4si_ftype_pcint
6618 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
6619 tree void_ftype_pint_v4si
6620 = build_function_type_list (void_type_node,
6621 pint_type_node, V4SI_type_node, NULL_TREE);
6622 tree v8hi_ftype_pcshort
6623 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
6624 tree void_ftype_pshort_v8hi
6625 = build_function_type_list (void_type_node,
6626 pshort_type_node, V8HI_type_node, NULL_TREE);
6627 tree v16qi_ftype_pcchar
6628 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
6629 tree void_ftype_pchar_v16qi
6630 = build_function_type_list (void_type_node,
6631 pchar_type_node, V16QI_type_node, NULL_TREE);
6632 tree void_ftype_v4si
6633 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
6634 tree v8hi_ftype_void
6635 = build_function_type (V8HI_type_node, void_list_node);
6636 tree void_ftype_void
6637 = build_function_type (void_type_node, void_list_node);
6639 = build_function_type_list (void_type_node, char_type_node, NULL_TREE);
6641 tree v16qi_ftype_long_pcvoid
6642 = build_function_type_list (V16QI_type_node,
6643 long_integer_type_node, pcvoid_type_node, NULL_TREE);
6644 tree v8hi_ftype_long_pcvoid
6645 = build_function_type_list (V8HI_type_node,
6646 long_integer_type_node, pcvoid_type_node, NULL_TREE);
6647 tree v4si_ftype_long_pcvoid
6648 = build_function_type_list (V4SI_type_node,
6649 long_integer_type_node, pcvoid_type_node, NULL_TREE);
6651 tree void_ftype_v4si_long_pvoid
6652 = build_function_type_list (void_type_node,
6653 V4SI_type_node, long_integer_type_node,
6654 pvoid_type_node, NULL_TREE);
6655 tree void_ftype_v16qi_long_pvoid
6656 = build_function_type_list (void_type_node,
6657 V16QI_type_node, long_integer_type_node,
6658 pvoid_type_node, NULL_TREE);
6659 tree void_ftype_v8hi_long_pvoid
6660 = build_function_type_list (void_type_node,
6661 V8HI_type_node, long_integer_type_node,
6662 pvoid_type_node, NULL_TREE);
6663 tree int_ftype_int_v8hi_v8hi
6664 = build_function_type_list (integer_type_node,
6665 integer_type_node, V8HI_type_node,
6666 V8HI_type_node, NULL_TREE);
6667 tree int_ftype_int_v16qi_v16qi
6668 = build_function_type_list (integer_type_node,
6669 integer_type_node, V16QI_type_node,
6670 V16QI_type_node, NULL_TREE);
6671 tree int_ftype_int_v4sf_v4sf
6672 = build_function_type_list (integer_type_node,
6673 integer_type_node, V4SF_type_node,
6674 V4SF_type_node, NULL_TREE);
6675 tree v4si_ftype_v4si
6676 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
6677 tree v8hi_ftype_v8hi
6678 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
6679 tree v16qi_ftype_v16qi
6680 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
6681 tree v4sf_ftype_v4sf
6682 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
6683 tree void_ftype_pcvoid_int_char
6684 = build_function_type_list (void_type_node,
6685 pcvoid_type_node, integer_type_node,
6686 char_type_node, NULL_TREE);
6688 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
6689 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
6690 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
6691 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
6692 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
6693 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
6694 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
6695 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
6696 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
6697 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
6698 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
6699 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
6700 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
6701 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
6702 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
6703 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
6704 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
6705 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
6706 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
6707 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS);
6708 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
6709 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
6710 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
6711 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
6712 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
6713 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
6714 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
6715 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
6716 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
6717 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
6718 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
6719 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
6721 /* Add the DST variants. */
6722 d = (struct builtin_description *) bdesc_dst;
6723 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6724 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_char, d->code);
6726 /* Initialize the predicates. */
6727 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6728 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6730 enum machine_mode mode1;
6733 mode1 = insn_data[dp->icode].operand[1].mode;
6738 type = int_ftype_int_v4si_v4si;
6741 type = int_ftype_int_v8hi_v8hi;
6744 type = int_ftype_int_v16qi_v16qi;
6747 type = int_ftype_int_v4sf_v4sf;
6753 def_builtin (dp->mask, dp->name, type, dp->code);
6756 /* Initialize the abs* operators. */
6757 d = (struct builtin_description *) bdesc_abs;
6758 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6760 enum machine_mode mode0;
6763 mode0 = insn_data[d->icode].operand[0].mode;
6768 type = v4si_ftype_v4si;
6771 type = v8hi_ftype_v8hi;
6774 type = v16qi_ftype_v16qi;
6777 type = v4sf_ftype_v4sf;
6783 def_builtin (d->mask, d->name, type, d->code);
6788 rs6000_common_init_builtins (void)
6790 struct builtin_description *d;
6793 tree v4sf_ftype_v4sf_v4sf_v16qi
6794 = build_function_type_list (V4SF_type_node,
6795 V4SF_type_node, V4SF_type_node,
6796 V16QI_type_node, NULL_TREE);
6797 tree v4si_ftype_v4si_v4si_v16qi
6798 = build_function_type_list (V4SI_type_node,
6799 V4SI_type_node, V4SI_type_node,
6800 V16QI_type_node, NULL_TREE);
6801 tree v8hi_ftype_v8hi_v8hi_v16qi
6802 = build_function_type_list (V8HI_type_node,
6803 V8HI_type_node, V8HI_type_node,
6804 V16QI_type_node, NULL_TREE);
6805 tree v16qi_ftype_v16qi_v16qi_v16qi
6806 = build_function_type_list (V16QI_type_node,
6807 V16QI_type_node, V16QI_type_node,
6808 V16QI_type_node, NULL_TREE);
6809 tree v4si_ftype_char
6810 = build_function_type_list (V4SI_type_node, char_type_node, NULL_TREE);
6811 tree v8hi_ftype_char
6812 = build_function_type_list (V8HI_type_node, char_type_node, NULL_TREE);
6813 tree v16qi_ftype_char
6814 = build_function_type_list (V16QI_type_node, char_type_node, NULL_TREE);
6815 tree v8hi_ftype_v16qi
6816 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
6817 tree v4sf_ftype_v4sf
6818 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
6820 tree v2si_ftype_v2si_v2si
6821 = build_function_type_list (opaque_V2SI_type_node,
6822 opaque_V2SI_type_node,
6823 opaque_V2SI_type_node, NULL_TREE);
6825 tree v2sf_ftype_v2sf_v2sf
6826 = build_function_type_list (opaque_V2SF_type_node,
6827 opaque_V2SF_type_node,
6828 opaque_V2SF_type_node, NULL_TREE);
6830 tree v2si_ftype_int_int
6831 = build_function_type_list (opaque_V2SI_type_node,
6832 integer_type_node, integer_type_node,
6835 tree v2si_ftype_v2si
6836 = build_function_type_list (opaque_V2SI_type_node,
6837 opaque_V2SI_type_node, NULL_TREE);
6839 tree v2sf_ftype_v2sf
6840 = build_function_type_list (opaque_V2SF_type_node,
6841 opaque_V2SF_type_node, NULL_TREE);
6843 tree v2sf_ftype_v2si
6844 = build_function_type_list (opaque_V2SF_type_node,
6845 opaque_V2SI_type_node, NULL_TREE);
6847 tree v2si_ftype_v2sf
6848 = build_function_type_list (opaque_V2SI_type_node,
6849 opaque_V2SF_type_node, NULL_TREE);
6851 tree v2si_ftype_v2si_char
6852 = build_function_type_list (opaque_V2SI_type_node,
6853 opaque_V2SI_type_node,
6854 char_type_node, NULL_TREE);
6856 tree v2si_ftype_int_char
6857 = build_function_type_list (opaque_V2SI_type_node,
6858 integer_type_node, char_type_node, NULL_TREE);
6860 tree v2si_ftype_char
6861 = build_function_type_list (opaque_V2SI_type_node,
6862 char_type_node, NULL_TREE);
6864 tree int_ftype_int_int
6865 = build_function_type_list (integer_type_node,
6866 integer_type_node, integer_type_node,
6869 tree v4si_ftype_v4si_v4si
6870 = build_function_type_list (V4SI_type_node,
6871 V4SI_type_node, V4SI_type_node, NULL_TREE);
6872 tree v4sf_ftype_v4si_char
6873 = build_function_type_list (V4SF_type_node,
6874 V4SI_type_node, char_type_node, NULL_TREE);
6875 tree v4si_ftype_v4sf_char
6876 = build_function_type_list (V4SI_type_node,
6877 V4SF_type_node, char_type_node, NULL_TREE);
6878 tree v4si_ftype_v4si_char
6879 = build_function_type_list (V4SI_type_node,
6880 V4SI_type_node, char_type_node, NULL_TREE);
6881 tree v8hi_ftype_v8hi_char
6882 = build_function_type_list (V8HI_type_node,
6883 V8HI_type_node, char_type_node, NULL_TREE);
6884 tree v16qi_ftype_v16qi_char
6885 = build_function_type_list (V16QI_type_node,
6886 V16QI_type_node, char_type_node, NULL_TREE);
6887 tree v16qi_ftype_v16qi_v16qi_char
6888 = build_function_type_list (V16QI_type_node,
6889 V16QI_type_node, V16QI_type_node,
6890 char_type_node, NULL_TREE);
6891 tree v8hi_ftype_v8hi_v8hi_char
6892 = build_function_type_list (V8HI_type_node,
6893 V8HI_type_node, V8HI_type_node,
6894 char_type_node, NULL_TREE);
6895 tree v4si_ftype_v4si_v4si_char
6896 = build_function_type_list (V4SI_type_node,
6897 V4SI_type_node, V4SI_type_node,
6898 char_type_node, NULL_TREE);
6899 tree v4sf_ftype_v4sf_v4sf_char
6900 = build_function_type_list (V4SF_type_node,
6901 V4SF_type_node, V4SF_type_node,
6902 char_type_node, NULL_TREE);
6903 tree v4sf_ftype_v4sf_v4sf
6904 = build_function_type_list (V4SF_type_node,
6905 V4SF_type_node, V4SF_type_node, NULL_TREE);
6906 tree v4sf_ftype_v4sf_v4sf_v4si
6907 = build_function_type_list (V4SF_type_node,
6908 V4SF_type_node, V4SF_type_node,
6909 V4SI_type_node, NULL_TREE);
6910 tree v4sf_ftype_v4sf_v4sf_v4sf
6911 = build_function_type_list (V4SF_type_node,
6912 V4SF_type_node, V4SF_type_node,
6913 V4SF_type_node, NULL_TREE);
6914 tree v4si_ftype_v4si_v4si_v4si
6915 = build_function_type_list (V4SI_type_node,
6916 V4SI_type_node, V4SI_type_node,
6917 V4SI_type_node, NULL_TREE);
6918 tree v8hi_ftype_v8hi_v8hi
6919 = build_function_type_list (V8HI_type_node,
6920 V8HI_type_node, V8HI_type_node, NULL_TREE);
6921 tree v8hi_ftype_v8hi_v8hi_v8hi
6922 = build_function_type_list (V8HI_type_node,
6923 V8HI_type_node, V8HI_type_node,
6924 V8HI_type_node, NULL_TREE);
6925 tree v4si_ftype_v8hi_v8hi_v4si
6926 = build_function_type_list (V4SI_type_node,
6927 V8HI_type_node, V8HI_type_node,
6928 V4SI_type_node, NULL_TREE);
6929 tree v4si_ftype_v16qi_v16qi_v4si
6930 = build_function_type_list (V4SI_type_node,
6931 V16QI_type_node, V16QI_type_node,
6932 V4SI_type_node, NULL_TREE);
6933 tree v16qi_ftype_v16qi_v16qi
6934 = build_function_type_list (V16QI_type_node,
6935 V16QI_type_node, V16QI_type_node, NULL_TREE);
6936 tree v4si_ftype_v4sf_v4sf
6937 = build_function_type_list (V4SI_type_node,
6938 V4SF_type_node, V4SF_type_node, NULL_TREE);
6939 tree v8hi_ftype_v16qi_v16qi
6940 = build_function_type_list (V8HI_type_node,
6941 V16QI_type_node, V16QI_type_node, NULL_TREE);
6942 tree v4si_ftype_v8hi_v8hi
6943 = build_function_type_list (V4SI_type_node,
6944 V8HI_type_node, V8HI_type_node, NULL_TREE);
6945 tree v8hi_ftype_v4si_v4si
6946 = build_function_type_list (V8HI_type_node,
6947 V4SI_type_node, V4SI_type_node, NULL_TREE);
6948 tree v16qi_ftype_v8hi_v8hi
6949 = build_function_type_list (V16QI_type_node,
6950 V8HI_type_node, V8HI_type_node, NULL_TREE);
6951 tree v4si_ftype_v16qi_v4si
6952 = build_function_type_list (V4SI_type_node,
6953 V16QI_type_node, V4SI_type_node, NULL_TREE);
6954 tree v4si_ftype_v16qi_v16qi
6955 = build_function_type_list (V4SI_type_node,
6956 V16QI_type_node, V16QI_type_node, NULL_TREE);
6957 tree v4si_ftype_v8hi_v4si
6958 = build_function_type_list (V4SI_type_node,
6959 V8HI_type_node, V4SI_type_node, NULL_TREE);
6960 tree v4si_ftype_v8hi
6961 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
6962 tree int_ftype_v4si_v4si
6963 = build_function_type_list (integer_type_node,
6964 V4SI_type_node, V4SI_type_node, NULL_TREE);
6965 tree int_ftype_v4sf_v4sf
6966 = build_function_type_list (integer_type_node,
6967 V4SF_type_node, V4SF_type_node, NULL_TREE);
6968 tree int_ftype_v16qi_v16qi
6969 = build_function_type_list (integer_type_node,
6970 V16QI_type_node, V16QI_type_node, NULL_TREE);
6971 tree int_ftype_v8hi_v8hi
6972 = build_function_type_list (integer_type_node,
6973 V8HI_type_node, V8HI_type_node, NULL_TREE);
6975 /* Add the simple ternary operators. */
6976 d = (struct builtin_description *) bdesc_3arg;
6977 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
6980 enum machine_mode mode0, mode1, mode2, mode3;
6983 if (d->name == 0 || d->icode == CODE_FOR_nothing)
6986 mode0 = insn_data[d->icode].operand[0].mode;
6987 mode1 = insn_data[d->icode].operand[1].mode;
6988 mode2 = insn_data[d->icode].operand[2].mode;
6989 mode3 = insn_data[d->icode].operand[3].mode;
6991 /* When all four are of the same mode. */
6992 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
6997 type = v4si_ftype_v4si_v4si_v4si;
7000 type = v4sf_ftype_v4sf_v4sf_v4sf;
7003 type = v8hi_ftype_v8hi_v8hi_v8hi;
7006 type = v16qi_ftype_v16qi_v16qi_v16qi;
7012 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
7017 type = v4si_ftype_v4si_v4si_v16qi;
7020 type = v4sf_ftype_v4sf_v4sf_v16qi;
7023 type = v8hi_ftype_v8hi_v8hi_v16qi;
7026 type = v16qi_ftype_v16qi_v16qi_v16qi;
7032 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
7033 && mode3 == V4SImode)
7034 type = v4si_ftype_v16qi_v16qi_v4si;
7035 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
7036 && mode3 == V4SImode)
7037 type = v4si_ftype_v8hi_v8hi_v4si;
7038 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
7039 && mode3 == V4SImode)
7040 type = v4sf_ftype_v4sf_v4sf_v4si;
7042 /* vchar, vchar, vchar, 4 bit literal. */
7043 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7045 type = v16qi_ftype_v16qi_v16qi_char;
7047 /* vshort, vshort, vshort, 4 bit literal. */
7048 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7050 type = v8hi_ftype_v8hi_v8hi_char;
7052 /* vint, vint, vint, 4 bit literal. */
7053 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7055 type = v4si_ftype_v4si_v4si_char;
7057 /* vfloat, vfloat, vfloat, 4 bit literal. */
7058 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7060 type = v4sf_ftype_v4sf_v4sf_char;
7065 def_builtin (d->mask, d->name, type, d->code);
7068 /* Add the simple binary operators. */
7069 d = (struct builtin_description *) bdesc_2arg;
7070 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7072 enum machine_mode mode0, mode1, mode2;
7075 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7078 mode0 = insn_data[d->icode].operand[0].mode;
7079 mode1 = insn_data[d->icode].operand[1].mode;
7080 mode2 = insn_data[d->icode].operand[2].mode;
7082 /* When all three operands are of the same mode. */
7083 if (mode0 == mode1 && mode1 == mode2)
7088 type = v4sf_ftype_v4sf_v4sf;
7091 type = v4si_ftype_v4si_v4si;
7094 type = v16qi_ftype_v16qi_v16qi;
7097 type = v8hi_ftype_v8hi_v8hi;
7100 type = v2si_ftype_v2si_v2si;
7103 type = v2sf_ftype_v2sf_v2sf;
7106 type = int_ftype_int_int;
7113 /* A few other combos we really don't want to do manually. */
7115 /* vint, vfloat, vfloat. */
7116 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
7117 type = v4si_ftype_v4sf_v4sf;
7119 /* vshort, vchar, vchar. */
7120 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
7121 type = v8hi_ftype_v16qi_v16qi;
7123 /* vint, vshort, vshort. */
7124 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
7125 type = v4si_ftype_v8hi_v8hi;
7127 /* vshort, vint, vint. */
7128 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
7129 type = v8hi_ftype_v4si_v4si;
7131 /* vchar, vshort, vshort. */
7132 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
7133 type = v16qi_ftype_v8hi_v8hi;
7135 /* vint, vchar, vint. */
7136 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
7137 type = v4si_ftype_v16qi_v4si;
7139 /* vint, vchar, vchar. */
7140 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
7141 type = v4si_ftype_v16qi_v16qi;
7143 /* vint, vshort, vint. */
7144 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
7145 type = v4si_ftype_v8hi_v4si;
7147 /* vint, vint, 5 bit literal. */
7148 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
7149 type = v4si_ftype_v4si_char;
7151 /* vshort, vshort, 5 bit literal. */
7152 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
7153 type = v8hi_ftype_v8hi_char;
7155 /* vchar, vchar, 5 bit literal. */
7156 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
7157 type = v16qi_ftype_v16qi_char;
7159 /* vfloat, vint, 5 bit literal. */
7160 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
7161 type = v4sf_ftype_v4si_char;
7163 /* vint, vfloat, 5 bit literal. */
7164 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
7165 type = v4si_ftype_v4sf_char;
7167 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
7168 type = v2si_ftype_int_int;
7170 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
7171 type = v2si_ftype_v2si_char;
7173 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
7174 type = v2si_ftype_int_char;
7177 else if (mode0 == SImode)
7182 type = int_ftype_v4si_v4si;
7185 type = int_ftype_v4sf_v4sf;
7188 type = int_ftype_v16qi_v16qi;
7191 type = int_ftype_v8hi_v8hi;
7201 def_builtin (d->mask, d->name, type, d->code);
7204 /* Add the simple unary operators. */
7205 d = (struct builtin_description *) bdesc_1arg;
7206 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7208 enum machine_mode mode0, mode1;
7211 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7214 mode0 = insn_data[d->icode].operand[0].mode;
7215 mode1 = insn_data[d->icode].operand[1].mode;
7217 if (mode0 == V4SImode && mode1 == QImode)
7218 type = v4si_ftype_char;
7219 else if (mode0 == V8HImode && mode1 == QImode)
7220 type = v8hi_ftype_char;
7221 else if (mode0 == V16QImode && mode1 == QImode)
7222 type = v16qi_ftype_char;
7223 else if (mode0 == V4SFmode && mode1 == V4SFmode)
7224 type = v4sf_ftype_v4sf;
7225 else if (mode0 == V8HImode && mode1 == V16QImode)
7226 type = v8hi_ftype_v16qi;
7227 else if (mode0 == V4SImode && mode1 == V8HImode)
7228 type = v4si_ftype_v8hi;
7229 else if (mode0 == V2SImode && mode1 == V2SImode)
7230 type = v2si_ftype_v2si;
7231 else if (mode0 == V2SFmode && mode1 == V2SFmode)
7232 type = v2sf_ftype_v2sf;
7233 else if (mode0 == V2SFmode && mode1 == V2SImode)
7234 type = v2sf_ftype_v2si;
7235 else if (mode0 == V2SImode && mode1 == V2SFmode)
7236 type = v2si_ftype_v2sf;
7237 else if (mode0 == V2SImode && mode1 == QImode)
7238 type = v2si_ftype_char;
7242 def_builtin (d->mask, d->name, type, d->code);
7247 rs6000_init_libfuncs (void)
7249 if (!TARGET_HARD_FLOAT)
7252 if (DEFAULT_ABI != ABI_V4)
7254 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
7256 /* AIX library routines for float->int conversion. */
7257 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
7258 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
7261 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
7262 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
7263 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
7264 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
7265 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
7269 /* 32-bit SVR4 quad floating point routines. */
7271 set_optab_libfunc (add_optab, TFmode, "_q_add");
7272 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
7273 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
7274 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
7275 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
7276 if (TARGET_PPC_GPOPT || TARGET_POWER2)
7277 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
7279 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
7280 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
7281 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
7282 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
7283 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
7284 set_optab_libfunc (le_optab, TFmode, "_q_fle");
7286 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
7287 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
7288 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
7289 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
7290 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
7291 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
7292 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
7296 /* Expand a block move operation, and return 1 if successful. Return 0
7297 if we should let the compiler generate normal code.
7299 operands[0] is the destination
7300 operands[1] is the source
7301 operands[2] is the length
7302 operands[3] is the alignment */
7304 #define MAX_MOVE_REG 4
7307 expand_block_move (rtx operands[])
7309 rtx orig_dest = operands[0];
7310 rtx orig_src = operands[1];
7311 rtx bytes_rtx = operands[2];
7312 rtx align_rtx = operands[3];
7313 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
7318 rtx stores[MAX_MOVE_REG];
7321 /* If this is not a fixed size move, just call memcpy */
7325 /* If this is not a fixed size alignment, abort */
7326 if (GET_CODE (align_rtx) != CONST_INT)
7328 align = INTVAL (align_rtx);
7330 /* Anything to move? */
7331 bytes = INTVAL (bytes_rtx);
7335 /* store_one_arg depends on expand_block_move to handle at least the size of
7336 reg_parm_stack_space. */
7337 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
7340 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
7343 rtx (*movstrsi) (rtx, rtx, rtx, rtx);
7344 rtx (*mov) (rtx, rtx);
7346 enum machine_mode mode = BLKmode;
7350 && bytes > 24 /* move up to 32 bytes at a time */
7358 && ! fixed_regs[12])
7360 move_bytes = (bytes > 32) ? 32 : bytes;
7361 gen_func.movstrsi = gen_movstrsi_8reg;
7363 else if (TARGET_STRING
7364 && bytes > 16 /* move up to 24 bytes at a time */
7370 && ! fixed_regs[10])
7372 move_bytes = (bytes > 24) ? 24 : bytes;
7373 gen_func.movstrsi = gen_movstrsi_6reg;
7375 else if (TARGET_STRING
7376 && bytes > 8 /* move up to 16 bytes at a time */
7382 move_bytes = (bytes > 16) ? 16 : bytes;
7383 gen_func.movstrsi = gen_movstrsi_4reg;
7385 else if (bytes >= 8 && TARGET_POWERPC64
7386 /* 64-bit loads and stores require word-aligned
7388 && (align >= 8 || (! STRICT_ALIGNMENT && align >= 4)))
7392 gen_func.mov = gen_movdi;
7394 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
7395 { /* move up to 8 bytes at a time */
7396 move_bytes = (bytes > 8) ? 8 : bytes;
7397 gen_func.movstrsi = gen_movstrsi_2reg;
7399 else if (bytes >= 4 && (align >= 4 || ! STRICT_ALIGNMENT))
7400 { /* move 4 bytes */
7403 gen_func.mov = gen_movsi;
7405 else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT))
7406 { /* move 2 bytes */
7409 gen_func.mov = gen_movhi;
7411 else if (TARGET_STRING && bytes > 1)
7412 { /* move up to 4 bytes at a time */
7413 move_bytes = (bytes > 4) ? 4 : bytes;
7414 gen_func.movstrsi = gen_movstrsi_1reg;
7416 else /* move 1 byte at a time */
7420 gen_func.mov = gen_movqi;
7423 src = adjust_address (orig_src, mode, offset);
7424 dest = adjust_address (orig_dest, mode, offset);
7426 if (mode != BLKmode)
7428 rtx tmp_reg = gen_reg_rtx (mode);
7430 emit_insn ((*gen_func.mov) (tmp_reg, src));
7431 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
7434 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
7437 for (i = 0; i < num_reg; i++)
7438 emit_insn (stores[i]);
7442 if (mode == BLKmode)
7444 /* Move the address into scratch registers. The movstrsi
7445 patterns require zero offset. */
7446 if (!REG_P (XEXP (src, 0)))
7448 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
7449 src = replace_equiv_address (src, src_reg);
7451 set_mem_size (src, GEN_INT (move_bytes));
7453 if (!REG_P (XEXP (dest, 0)))
7455 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
7456 dest = replace_equiv_address (dest, dest_reg);
7458 set_mem_size (dest, GEN_INT (move_bytes));
7460 emit_insn ((*gen_func.movstrsi) (dest, src,
7461 GEN_INT (move_bytes & 31),
7470 /* Return 1 if OP is a load multiple operation. It is known to be a
7471 PARALLEL and the first section will be tested. */
7474 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7476 int count = XVECLEN (op, 0);
7477 unsigned int dest_regno;
7481 /* Perform a quick check so we don't blow up below. */
7483 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7484 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7485 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
7488 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7489 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
7491 for (i = 1; i < count; i++)
7493 rtx elt = XVECEXP (op, 0, i);
7495 if (GET_CODE (elt) != SET
7496 || GET_CODE (SET_DEST (elt)) != REG
7497 || GET_MODE (SET_DEST (elt)) != SImode
7498 || REGNO (SET_DEST (elt)) != dest_regno + i
7499 || GET_CODE (SET_SRC (elt)) != MEM
7500 || GET_MODE (SET_SRC (elt)) != SImode
7501 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
7502 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
7503 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
7504 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
7511 /* Similar, but tests for store multiple. Here, the second vector element
7512 is a CLOBBER. It will be tested later. */
7515 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7517 int count = XVECLEN (op, 0) - 1;
7518 unsigned int src_regno;
7522 /* Perform a quick check so we don't blow up below. */
7524 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7525 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
7526 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
7529 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7530 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
7532 for (i = 1; i < count; i++)
7534 rtx elt = XVECEXP (op, 0, i + 1);
7536 if (GET_CODE (elt) != SET
7537 || GET_CODE (SET_SRC (elt)) != REG
7538 || GET_MODE (SET_SRC (elt)) != SImode
7539 || REGNO (SET_SRC (elt)) != src_regno + i
7540 || GET_CODE (SET_DEST (elt)) != MEM
7541 || GET_MODE (SET_DEST (elt)) != SImode
7542 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
7543 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
7544 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
7545 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
7552 /* Return a string to perform a load_multiple operation.
7553 operands[0] is the vector.
7554 operands[1] is the source address.
7555 operands[2] is the first destination register. */
7558 rs6000_output_load_multiple (rtx operands[3])
7560 /* We have to handle the case where the pseudo used to contain the address
7561 is assigned to one of the output registers. */
7563 int words = XVECLEN (operands[0], 0);
7566 if (XVECLEN (operands[0], 0) == 1)
7567 return "{l|lwz} %2,0(%1)";
7569 for (i = 0; i < words; i++)
7570 if (refers_to_regno_p (REGNO (operands[2]) + i,
7571 REGNO (operands[2]) + i + 1, operands[1], 0))
7575 xop[0] = GEN_INT (4 * (words-1));
7576 xop[1] = operands[1];
7577 xop[2] = operands[2];
7578 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
7583 xop[0] = GEN_INT (4 * (words-1));
7584 xop[1] = operands[1];
7585 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
7586 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
7591 for (j = 0; j < words; j++)
7594 xop[0] = GEN_INT (j * 4);
7595 xop[1] = operands[1];
7596 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
7597 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
7599 xop[0] = GEN_INT (i * 4);
7600 xop[1] = operands[1];
7601 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
7606 return "{lsi|lswi} %2,%1,%N0";
7609 /* Return 1 for a parallel vrsave operation. */
7612 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7614 int count = XVECLEN (op, 0);
7615 unsigned int dest_regno, src_regno;
7619 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7620 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7621 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
7624 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7625 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7627 if (dest_regno != VRSAVE_REGNO
7628 && src_regno != VRSAVE_REGNO)
7631 for (i = 1; i < count; i++)
7633 rtx elt = XVECEXP (op, 0, i);
7635 if (GET_CODE (elt) != CLOBBER
7636 && GET_CODE (elt) != SET)
7643 /* Return 1 for an PARALLEL suitable for mfcr. */
7646 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7648 int count = XVECLEN (op, 0);
7651 /* Perform a quick check so we don't blow up below. */
7653 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7654 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
7655 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
7658 for (i = 0; i < count; i++)
7660 rtx exp = XVECEXP (op, 0, i);
7665 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
7667 if (GET_CODE (src_reg) != REG
7668 || GET_MODE (src_reg) != CCmode
7669 || ! CR_REGNO_P (REGNO (src_reg)))
7672 if (GET_CODE (exp) != SET
7673 || GET_CODE (SET_DEST (exp)) != REG
7674 || GET_MODE (SET_DEST (exp)) != SImode
7675 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
7677 unspec = SET_SRC (exp);
7678 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
7680 if (GET_CODE (unspec) != UNSPEC
7681 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
7682 || XVECLEN (unspec, 0) != 2
7683 || XVECEXP (unspec, 0, 0) != src_reg
7684 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
7685 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
7691 /* Return 1 for an PARALLEL suitable for mtcrf. */
7694 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7696 int count = XVECLEN (op, 0);
7700 /* Perform a quick check so we don't blow up below. */
7702 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7703 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
7704 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
7706 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
7708 if (GET_CODE (src_reg) != REG
7709 || GET_MODE (src_reg) != SImode
7710 || ! INT_REGNO_P (REGNO (src_reg)))
7713 for (i = 0; i < count; i++)
7715 rtx exp = XVECEXP (op, 0, i);
7719 if (GET_CODE (exp) != SET
7720 || GET_CODE (SET_DEST (exp)) != REG
7721 || GET_MODE (SET_DEST (exp)) != CCmode
7722 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
7724 unspec = SET_SRC (exp);
7725 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
7727 if (GET_CODE (unspec) != UNSPEC
7728 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
7729 || XVECLEN (unspec, 0) != 2
7730 || XVECEXP (unspec, 0, 0) != src_reg
7731 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
7732 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
7738 /* Return 1 for an PARALLEL suitable for lmw. */
7741 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7743 int count = XVECLEN (op, 0);
7744 unsigned int dest_regno;
7746 unsigned int base_regno;
7747 HOST_WIDE_INT offset;
7750 /* Perform a quick check so we don't blow up below. */
7752 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7753 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
7754 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
7757 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
7758 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
7761 || count != 32 - (int) dest_regno)
7764 if (legitimate_indirect_address_p (src_addr, 0))
7767 base_regno = REGNO (src_addr);
7768 if (base_regno == 0)
7771 else if (legitimate_offset_address_p (SImode, src_addr, 0))
7773 offset = INTVAL (XEXP (src_addr, 1));
7774 base_regno = REGNO (XEXP (src_addr, 0));
7779 for (i = 0; i < count; i++)
7781 rtx elt = XVECEXP (op, 0, i);
7784 HOST_WIDE_INT newoffset;
7786 if (GET_CODE (elt) != SET
7787 || GET_CODE (SET_DEST (elt)) != REG
7788 || GET_MODE (SET_DEST (elt)) != SImode
7789 || REGNO (SET_DEST (elt)) != dest_regno + i
7790 || GET_CODE (SET_SRC (elt)) != MEM
7791 || GET_MODE (SET_SRC (elt)) != SImode)
7793 newaddr = XEXP (SET_SRC (elt), 0);
7794 if (legitimate_indirect_address_p (newaddr, 0))
7799 else if (legitimate_offset_address_p (SImode, newaddr, 0))
7801 addr_reg = XEXP (newaddr, 0);
7802 newoffset = INTVAL (XEXP (newaddr, 1));
7806 if (REGNO (addr_reg) != base_regno
7807 || newoffset != offset + 4 * i)
7814 /* Return 1 for an PARALLEL suitable for stmw. */
7817 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7819 int count = XVECLEN (op, 0);
7820 unsigned int src_regno;
7822 unsigned int base_regno;
7823 HOST_WIDE_INT offset;
7826 /* Perform a quick check so we don't blow up below. */
7828 || GET_CODE (XVECEXP (op, 0, 0)) != SET
7829 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
7830 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
7833 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
7834 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
7837 || count != 32 - (int) src_regno)
7840 if (legitimate_indirect_address_p (dest_addr, 0))
7843 base_regno = REGNO (dest_addr);
7844 if (base_regno == 0)
7847 else if (legitimate_offset_address_p (SImode, dest_addr, 0))
7849 offset = INTVAL (XEXP (dest_addr, 1));
7850 base_regno = REGNO (XEXP (dest_addr, 0));
7855 for (i = 0; i < count; i++)
7857 rtx elt = XVECEXP (op, 0, i);
7860 HOST_WIDE_INT newoffset;
7862 if (GET_CODE (elt) != SET
7863 || GET_CODE (SET_SRC (elt)) != REG
7864 || GET_MODE (SET_SRC (elt)) != SImode
7865 || REGNO (SET_SRC (elt)) != src_regno + i
7866 || GET_CODE (SET_DEST (elt)) != MEM
7867 || GET_MODE (SET_DEST (elt)) != SImode)
7869 newaddr = XEXP (SET_DEST (elt), 0);
7870 if (legitimate_indirect_address_p (newaddr, 0))
7875 else if (legitimate_offset_address_p (SImode, newaddr, 0))
7877 addr_reg = XEXP (newaddr, 0);
7878 newoffset = INTVAL (XEXP (newaddr, 1));
7882 if (REGNO (addr_reg) != base_regno
7883 || newoffset != offset + 4 * i)
7890 /* A validation routine: say whether CODE, a condition code, and MODE
7891 match. The other alternatives either don't make sense or should
7892 never be generated. */
7895 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
7897 if (GET_RTX_CLASS (code) != '<'
7898 || GET_MODE_CLASS (mode) != MODE_CC)
7901 /* These don't make sense. */
7902 if ((code == GT || code == LT || code == GE || code == LE)
7903 && mode == CCUNSmode)
7906 if ((code == GTU || code == LTU || code == GEU || code == LEU)
7907 && mode != CCUNSmode)
7910 if (mode != CCFPmode
7911 && (code == ORDERED || code == UNORDERED
7912 || code == UNEQ || code == LTGT
7913 || code == UNGT || code == UNLT
7914 || code == UNGE || code == UNLE))
7917 /* These should never be generated except for
7918 flag_finite_math_only. */
7919 if (mode == CCFPmode
7920 && ! flag_finite_math_only
7921 && (code == LE || code == GE
7922 || code == UNEQ || code == LTGT
7923 || code == UNGT || code == UNLT))
7926 /* These are invalid; the information is not there. */
7927 if (mode == CCEQmode
7928 && code != EQ && code != NE)
7932 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
7933 We only check the opcode against the mode of the CC value here. */
7936 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7938 enum rtx_code code = GET_CODE (op);
7939 enum machine_mode cc_mode;
7941 if (GET_RTX_CLASS (code) != '<')
7944 cc_mode = GET_MODE (XEXP (op, 0));
7945 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
7948 validate_condition_mode (code, cc_mode);
7953 /* Return 1 if OP is a comparison operation that is valid for a branch
7954 insn and which is true if the corresponding bit in the CC register
7958 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
7962 if (! branch_comparison_operator (op, mode))
7965 code = GET_CODE (op);
7966 return (code == EQ || code == LT || code == GT
7967 || (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE)
7968 || code == LTU || code == GTU
7969 || code == UNORDERED);
7972 /* Return 1 if OP is a comparison operation that is valid for an scc
7973 insn: it must be a positive comparison. */
7976 scc_comparison_operator (rtx op, enum machine_mode mode)
7978 return branch_positive_comparison_operator (op, mode);
7982 trap_comparison_operator (rtx op, enum machine_mode mode)
7984 if (mode != VOIDmode && mode != GET_MODE (op))
7986 return GET_RTX_CLASS (GET_CODE (op)) == '<';
7990 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7992 enum rtx_code code = GET_CODE (op);
7993 return (code == AND || code == IOR || code == XOR);
7997 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7999 enum rtx_code code = GET_CODE (op);
8000 return (code == IOR || code == XOR);
8004 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8006 enum rtx_code code = GET_CODE (op);
8007 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
8010 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8011 mask required to convert the result of a rotate insn into a shift
8012 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
8015 includes_lshift_p (rtx shiftop, rtx andop)
8017 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8019 shift_mask <<= INTVAL (shiftop);
8021 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8024 /* Similar, but for right shift. */
8027 includes_rshift_p (rtx shiftop, rtx andop)
8029 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8031 shift_mask >>= INTVAL (shiftop);
8033 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8036 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8037 to perform a left shift. It must have exactly SHIFTOP least
8038 significant 0's, then one or more 1's, then zero or more 0's. */
8041 includes_rldic_lshift_p (rtx shiftop, rtx andop)
8043 if (GET_CODE (andop) == CONST_INT)
8045 HOST_WIDE_INT c, lsb, shift_mask;
8048 if (c == 0 || c == ~0)
8052 shift_mask <<= INTVAL (shiftop);
8054 /* Find the least significant one bit. */
8057 /* It must coincide with the LSB of the shift mask. */
8058 if (-lsb != shift_mask)
8061 /* Invert to look for the next transition (if any). */
8064 /* Remove the low group of ones (originally low group of zeros). */
8067 /* Again find the lsb, and check we have all 1's above. */
8071 else if (GET_CODE (andop) == CONST_DOUBLE
8072 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8074 HOST_WIDE_INT low, high, lsb;
8075 HOST_WIDE_INT shift_mask_low, shift_mask_high;
8077 low = CONST_DOUBLE_LOW (andop);
8078 if (HOST_BITS_PER_WIDE_INT < 64)
8079 high = CONST_DOUBLE_HIGH (andop);
8081 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
8082 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
8085 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8087 shift_mask_high = ~0;
8088 if (INTVAL (shiftop) > 32)
8089 shift_mask_high <<= INTVAL (shiftop) - 32;
8093 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8100 return high == -lsb;
8103 shift_mask_low = ~0;
8104 shift_mask_low <<= INTVAL (shiftop);
8108 if (-lsb != shift_mask_low)
8111 if (HOST_BITS_PER_WIDE_INT < 64)
8116 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8119 return high == -lsb;
8123 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8129 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8130 to perform a left shift. It must have SHIFTOP or more least
8131 significant 0's, with the remainder of the word 1's. */
8134 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
8136 if (GET_CODE (andop) == CONST_INT)
8138 HOST_WIDE_INT c, lsb, shift_mask;
8141 shift_mask <<= INTVAL (shiftop);
8144 /* Find the least significant one bit. */
8147 /* It must be covered by the shift mask.
8148 This test also rejects c == 0. */
8149 if ((lsb & shift_mask) == 0)
8152 /* Check we have all 1's above the transition, and reject all 1's. */
8153 return c == -lsb && lsb != 1;
8155 else if (GET_CODE (andop) == CONST_DOUBLE
8156 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8158 HOST_WIDE_INT low, lsb, shift_mask_low;
8160 low = CONST_DOUBLE_LOW (andop);
8162 if (HOST_BITS_PER_WIDE_INT < 64)
8164 HOST_WIDE_INT high, shift_mask_high;
8166 high = CONST_DOUBLE_HIGH (andop);
8170 shift_mask_high = ~0;
8171 if (INTVAL (shiftop) > 32)
8172 shift_mask_high <<= INTVAL (shiftop) - 32;
8176 if ((lsb & shift_mask_high) == 0)
8179 return high == -lsb;
8185 shift_mask_low = ~0;
8186 shift_mask_low <<= INTVAL (shiftop);
8190 if ((lsb & shift_mask_low) == 0)
8193 return low == -lsb && lsb != 1;
8199 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
8200 for lfq and stfq insns.
8202 Note reg1 and reg2 *must* be hard registers. To be sure we will
8203 abort if we are passed pseudo registers. */
8206 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
8208 /* We might have been passed a SUBREG. */
8209 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8212 return (REGNO (reg1) == REGNO (reg2) - 1);
8215 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8216 addr1 and addr2 must be in consecutive memory locations
8217 (addr2 == addr1 + 8). */
8220 addrs_ok_for_quad_peep (rtx addr1, rtx addr2)
8225 /* Extract an offset (if used) from the first addr. */
8226 if (GET_CODE (addr1) == PLUS)
8228 /* If not a REG, return zero. */
8229 if (GET_CODE (XEXP (addr1, 0)) != REG)
8233 reg1 = REGNO (XEXP (addr1, 0));
8234 /* The offset must be constant! */
8235 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8237 offset1 = INTVAL (XEXP (addr1, 1));
8240 else if (GET_CODE (addr1) != REG)
8244 reg1 = REGNO (addr1);
8245 /* This was a simple (mem (reg)) expression. Offset is 0. */
8249 /* Make sure the second address is a (mem (plus (reg) (const_int)))
8250 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
8251 register as addr1. */
8252 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
8254 if (GET_CODE (addr2) != PLUS)
8257 if (GET_CODE (XEXP (addr2, 0)) != REG
8258 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8261 if (reg1 != REGNO (XEXP (addr2, 0)))
8264 /* The offset for the second addr must be 8 more than the first addr. */
8265 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8268 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
8273 /* Return the register class of a scratch register needed to copy IN into
8274 or out of a register in CLASS in MODE. If it can be done directly,
8275 NO_REGS is returned. */
8278 secondary_reload_class (enum reg_class class,
8279 enum machine_mode mode ATTRIBUTE_UNUSED,
8284 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8286 && MACHOPIC_INDIRECT
8290 /* We cannot copy a symbolic operand directly into anything
8291 other than BASE_REGS for TARGET_ELF. So indicate that a
8292 register from BASE_REGS is needed as an intermediate
8295 On Darwin, pic addresses require a load from memory, which
8296 needs a base register. */
8297 if (class != BASE_REGS
8298 && (GET_CODE (in) == SYMBOL_REF
8299 || GET_CODE (in) == HIGH
8300 || GET_CODE (in) == LABEL_REF
8301 || GET_CODE (in) == CONST))
8305 if (GET_CODE (in) == REG)
8308 if (regno >= FIRST_PSEUDO_REGISTER)
8310 regno = true_regnum (in);
8311 if (regno >= FIRST_PSEUDO_REGISTER)
8315 else if (GET_CODE (in) == SUBREG)
8317 regno = true_regnum (in);
8318 if (regno >= FIRST_PSEUDO_REGISTER)
8324 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8326 if (class == GENERAL_REGS || class == BASE_REGS
8327 || (regno >= 0 && INT_REGNO_P (regno)))
8330 /* Constants, memory, and FP registers can go into FP registers. */
8331 if ((regno == -1 || FP_REGNO_P (regno))
8332 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8335 /* Memory, and AltiVec registers can go into AltiVec registers. */
8336 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8337 && class == ALTIVEC_REGS)
8340 /* We can copy among the CR registers. */
8341 if ((class == CR_REGS || class == CR0_REGS)
8342 && regno >= 0 && CR_REGNO_P (regno))
8345 /* Otherwise, we need GENERAL_REGS. */
8346 return GENERAL_REGS;
8349 /* Given a comparison operation, return the bit number in CCR to test. We
8350 know this is a valid comparison.
8352 SCC_P is 1 if this is for an scc. That means that %D will have been
8353 used instead of %C, so the bits will be in different places.
8355 Return -1 if OP isn't a valid comparison for some reason. */
8358 ccr_bit (rtx op, int scc_p)
8360 enum rtx_code code = GET_CODE (op);
8361 enum machine_mode cc_mode;
8366 if (GET_RTX_CLASS (code) != '<')
8371 if (GET_CODE (reg) != REG
8372 || ! CR_REGNO_P (REGNO (reg)))
8375 cc_mode = GET_MODE (reg);
8376 cc_regnum = REGNO (reg);
8377 base_bit = 4 * (cc_regnum - CR0_REGNO);
8379 validate_condition_mode (code, cc_mode);
8381 /* When generating a sCOND operation, only positive conditions are
8383 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8384 && code != GTU && code != LTU)
8390 if (TARGET_E500 && !TARGET_FPRS
8391 && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
8392 return base_bit + 1;
8393 return scc_p ? base_bit + 3 : base_bit + 2;
8395 if (TARGET_E500 && !TARGET_FPRS
8396 && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
8397 return base_bit + 1;
8398 return base_bit + 2;
8399 case GT: case GTU: case UNLE:
8400 return base_bit + 1;
8401 case LT: case LTU: case UNGE:
8403 case ORDERED: case UNORDERED:
8404 return base_bit + 3;
8407 /* If scc, we will have done a cror to put the bit in the
8408 unordered position. So test that bit. For integer, this is ! LT
8409 unless this is an scc insn. */
8410 return scc_p ? base_bit + 3 : base_bit;
8413 return scc_p ? base_bit + 3 : base_bit + 1;
8420 /* Return the GOT register. */
8423 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
8425 /* The second flow pass currently (June 1999) can't update
8426 regs_ever_live without disturbing other parts of the compiler, so
8427 update it here to make the prolog/epilogue code happy. */
8428 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
8429 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
8431 current_function_uses_pic_offset_table = 1;
8433 return pic_offset_table_rtx;
8436 /* Function to init struct machine_function.
8437 This will be called, via a pointer variable,
8438 from push_function_context. */
8440 static struct machine_function *
8441 rs6000_init_machine_status (void)
8443 return ggc_alloc_cleared (sizeof (machine_function));
8446 /* These macros test for integers and extract the low-order bits. */
8448 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
8449 && GET_MODE (X) == VOIDmode)
8451 #define INT_LOWPART(X) \
8452 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
8458 unsigned long val = INT_LOWPART (op);
8460 /* If the high bit is zero, the value is the first 1 bit we find
8462 if ((val & 0x80000000) == 0)
8464 if ((val & 0xffffffff) == 0)
8468 while (((val <<= 1) & 0x80000000) == 0)
8473 /* If the high bit is set and the low bit is not, or the mask is all
8474 1's, the value is zero. */
8475 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
8478 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
8481 while (((val >>= 1) & 1) != 0)
8491 unsigned long val = INT_LOWPART (op);
8493 /* If the low bit is zero, the value is the first 1 bit we find from
8497 if ((val & 0xffffffff) == 0)
8501 while (((val >>= 1) & 1) == 0)
8507 /* If the low bit is set and the high bit is not, or the mask is all
8508 1's, the value is 31. */
8509 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
8512 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
8515 while (((val <<= 1) & 0x80000000) != 0)
8521 /* Locate some local-dynamic symbol still in use by this function
8522 so that we can print its name in some tls_ld pattern. */
8525 rs6000_get_some_local_dynamic_name (void)
8529 if (cfun->machine->some_ld_name)
8530 return cfun->machine->some_ld_name;
8532 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
8534 && for_each_rtx (&PATTERN (insn),
8535 rs6000_get_some_local_dynamic_name_1, 0))
8536 return cfun->machine->some_ld_name;
8541 /* Helper function for rs6000_get_some_local_dynamic_name. */
8544 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
8548 if (GET_CODE (x) == SYMBOL_REF)
8550 const char *str = XSTR (x, 0);
8551 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
8553 cfun->machine->some_ld_name = str;
8561 /* Print an operand. Recognize special options, documented below. */
8564 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
8565 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
8567 #define SMALL_DATA_RELOC "sda21"
8568 #define SMALL_DATA_REG 0
8572 print_operand (FILE *file, rtx x, int code)
8576 unsigned HOST_WIDE_INT uval;
8581 /* Write out an instruction after the call which may be replaced
8582 with glue code by the loader. This depends on the AIX version. */
8583 asm_fprintf (file, RS6000_CALL_GLUE);
8586 /* %a is output_address. */
8589 /* If X is a constant integer whose low-order 5 bits are zero,
8590 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
8591 in the AIX assembler where "sri" with a zero shift count
8592 writes a trash instruction. */
8593 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
8600 /* If constant, low-order 16 bits of constant, unsigned.
8601 Otherwise, write normally. */
8603 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
8605 print_operand (file, x, 0);
8609 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
8610 for 64-bit mask direction. */
8611 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
8614 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
8618 /* X is a CR register. Print the number of the EQ bit of the CR */
8619 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8620 output_operand_lossage ("invalid %%E value");
8622 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
8626 /* X is a CR register. Print the shift count needed to move it
8627 to the high-order four bits. */
8628 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8629 output_operand_lossage ("invalid %%f value");
8631 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
8635 /* Similar, but print the count for the rotate in the opposite
8637 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8638 output_operand_lossage ("invalid %%F value");
8640 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
8644 /* X is a constant integer. If it is negative, print "m",
8645 otherwise print "z". This is to make an aze or ame insn. */
8646 if (GET_CODE (x) != CONST_INT)
8647 output_operand_lossage ("invalid %%G value");
8648 else if (INTVAL (x) >= 0)
8655 /* If constant, output low-order five bits. Otherwise, write
8658 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
8660 print_operand (file, x, 0);
8664 /* If constant, output low-order six bits. Otherwise, write
8667 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
8669 print_operand (file, x, 0);
8673 /* Print `i' if this is a constant, else nothing. */
8679 /* Write the bit number in CCR for jump. */
8682 output_operand_lossage ("invalid %%j code");
8684 fprintf (file, "%d", i);
8688 /* Similar, but add one for shift count in rlinm for scc and pass
8689 scc flag to `ccr_bit'. */
8692 output_operand_lossage ("invalid %%J code");
8694 /* If we want bit 31, write a shift count of zero, not 32. */
8695 fprintf (file, "%d", i == 31 ? 0 : i + 1);
8699 /* X must be a constant. Write the 1's complement of the
8702 output_operand_lossage ("invalid %%k value");
8704 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
8708 /* X must be a symbolic constant on ELF. Write an
8709 expression suitable for an 'addi' that adds in the low 16
8711 if (GET_CODE (x) != CONST)
8713 print_operand_address (file, x);
8718 if (GET_CODE (XEXP (x, 0)) != PLUS
8719 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
8720 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
8721 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
8722 output_operand_lossage ("invalid %%K value");
8723 print_operand_address (file, XEXP (XEXP (x, 0), 0));
8725 /* For GNU as, there must be a non-alphanumeric character
8726 between 'l' and the number. The '-' is added by
8727 print_operand() already. */
8728 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
8730 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
8734 /* %l is output_asm_label. */
8737 /* Write second word of DImode or DFmode reference. Works on register
8738 or non-indexed memory only. */
8739 if (GET_CODE (x) == REG)
8740 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
8741 else if (GET_CODE (x) == MEM)
8743 /* Handle possible auto-increment. Since it is pre-increment and
8744 we have already done it, we can just use an offset of word. */
8745 if (GET_CODE (XEXP (x, 0)) == PRE_INC
8746 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
8747 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
8750 output_address (XEXP (adjust_address_nv (x, SImode,
8754 if (small_data_operand (x, GET_MODE (x)))
8755 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
8756 reg_names[SMALL_DATA_REG]);
8761 /* MB value for a mask operand. */
8762 if (! mask_operand (x, SImode))
8763 output_operand_lossage ("invalid %%m value");
8765 fprintf (file, "%d", extract_MB (x));
8769 /* ME value for a mask operand. */
8770 if (! mask_operand (x, SImode))
8771 output_operand_lossage ("invalid %%M value");
8773 fprintf (file, "%d", extract_ME (x));
8776 /* %n outputs the negative of its operand. */
8779 /* Write the number of elements in the vector times 4. */
8780 if (GET_CODE (x) != PARALLEL)
8781 output_operand_lossage ("invalid %%N value");
8783 fprintf (file, "%d", XVECLEN (x, 0) * 4);
8787 /* Similar, but subtract 1 first. */
8788 if (GET_CODE (x) != PARALLEL)
8789 output_operand_lossage ("invalid %%O value");
8791 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
8795 /* X is a CONST_INT that is a power of two. Output the logarithm. */
8797 || INT_LOWPART (x) < 0
8798 || (i = exact_log2 (INT_LOWPART (x))) < 0)
8799 output_operand_lossage ("invalid %%p value");
8801 fprintf (file, "%d", i);
8805 /* The operand must be an indirect memory reference. The result
8806 is the register number. */
8807 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
8808 || REGNO (XEXP (x, 0)) >= 32)
8809 output_operand_lossage ("invalid %%P value");
8811 fprintf (file, "%d", REGNO (XEXP (x, 0)));
8815 /* This outputs the logical code corresponding to a boolean
8816 expression. The expression may have one or both operands
8817 negated (if one, only the first one). For condition register
8818 logical operations, it will also treat the negated
8819 CR codes as NOTs, but not handle NOTs of them. */
8821 const char *const *t = 0;
8823 enum rtx_code code = GET_CODE (x);
8824 static const char * const tbl[3][3] = {
8825 { "and", "andc", "nor" },
8826 { "or", "orc", "nand" },
8827 { "xor", "eqv", "xor" } };
8831 else if (code == IOR)
8833 else if (code == XOR)
8836 output_operand_lossage ("invalid %%q value");
8838 if (GET_CODE (XEXP (x, 0)) != NOT)
8842 if (GET_CODE (XEXP (x, 1)) == NOT)
8860 /* X is a CR register. Print the mask for `mtcrf'. */
8861 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
8862 output_operand_lossage ("invalid %%R value");
8864 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
8868 /* Low 5 bits of 32 - value */
8870 output_operand_lossage ("invalid %%s value");
8872 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
8876 /* PowerPC64 mask position. All 0's is excluded.
8877 CONST_INT 32-bit mask is considered sign-extended so any
8878 transition must occur within the CONST_INT, not on the boundary. */
8879 if (! mask64_operand (x, DImode))
8880 output_operand_lossage ("invalid %%S value");
8882 uval = INT_LOWPART (x);
8884 if (uval & 1) /* Clear Left */
8886 #if HOST_BITS_PER_WIDE_INT > 64
8887 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
8891 else /* Clear Right */
8894 #if HOST_BITS_PER_WIDE_INT > 64
8895 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
8903 fprintf (file, "%d", i);
8907 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
8908 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
8911 /* Bit 3 is OV bit. */
8912 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
8914 /* If we want bit 31, write a shift count of zero, not 32. */
8915 fprintf (file, "%d", i == 31 ? 0 : i + 1);
8919 /* Print the symbolic name of a branch target register. */
8920 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
8921 && REGNO (x) != COUNT_REGISTER_REGNUM))
8922 output_operand_lossage ("invalid %%T value");
8923 else if (REGNO (x) == LINK_REGISTER_REGNUM)
8924 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
8926 fputs ("ctr", file);
8930 /* High-order 16 bits of constant for use in unsigned operand. */
8932 output_operand_lossage ("invalid %%u value");
8934 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
8935 (INT_LOWPART (x) >> 16) & 0xffff);
8939 /* High-order 16 bits of constant for use in signed operand. */
8941 output_operand_lossage ("invalid %%v value");
8943 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
8944 (INT_LOWPART (x) >> 16) & 0xffff);
8948 /* Print `u' if this has an auto-increment or auto-decrement. */
8949 if (GET_CODE (x) == MEM
8950 && (GET_CODE (XEXP (x, 0)) == PRE_INC
8951 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
8956 /* Print the trap code for this operand. */
8957 switch (GET_CODE (x))
8960 fputs ("eq", file); /* 4 */
8963 fputs ("ne", file); /* 24 */
8966 fputs ("lt", file); /* 16 */
8969 fputs ("le", file); /* 20 */
8972 fputs ("gt", file); /* 8 */
8975 fputs ("ge", file); /* 12 */
8978 fputs ("llt", file); /* 2 */
8981 fputs ("lle", file); /* 6 */
8984 fputs ("lgt", file); /* 1 */
8987 fputs ("lge", file); /* 5 */
8995 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
8998 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
8999 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9001 print_operand (file, x, 0);
9005 /* MB value for a PowerPC64 rldic operand. */
9006 val = (GET_CODE (x) == CONST_INT
9007 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9012 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9013 if ((val <<= 1) < 0)
9016 #if HOST_BITS_PER_WIDE_INT == 32
9017 if (GET_CODE (x) == CONST_INT && i >= 0)
9018 i += 32; /* zero-extend high-part was all 0's */
9019 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9021 val = CONST_DOUBLE_LOW (x);
9028 for ( ; i < 64; i++)
9029 if ((val <<= 1) < 0)
9034 fprintf (file, "%d", i + 1);
9038 if (GET_CODE (x) == MEM
9039 && legitimate_indexed_address_p (XEXP (x, 0), 0))
9044 /* Like 'L', for third word of TImode */
9045 if (GET_CODE (x) == REG)
9046 fprintf (file, "%s", reg_names[REGNO (x) + 2]);
9047 else if (GET_CODE (x) == MEM)
9049 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9050 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9051 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9053 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
9054 if (small_data_operand (x, GET_MODE (x)))
9055 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9056 reg_names[SMALL_DATA_REG]);
9061 /* X is a SYMBOL_REF. Write out the name preceded by a
9062 period and without any trailing data in brackets. Used for function
9063 names. If we are configured for System V (or the embedded ABI) on
9064 the PowerPC, do not emit the period, since those systems do not use
9065 TOCs and the like. */
9066 if (GET_CODE (x) != SYMBOL_REF)
9069 if (XSTR (x, 0)[0] != '.')
9071 switch (DEFAULT_ABI)
9086 RS6000_OUTPUT_BASENAME (file, XSTR (x, 0));
9088 assemble_name (file, XSTR (x, 0));
9092 /* Like 'L', for last word of TImode. */
9093 if (GET_CODE (x) == REG)
9094 fprintf (file, "%s", reg_names[REGNO (x) + 3]);
9095 else if (GET_CODE (x) == MEM)
9097 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9098 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9099 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9101 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
9102 if (small_data_operand (x, GET_MODE (x)))
9103 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9104 reg_names[SMALL_DATA_REG]);
9108 /* Print AltiVec or SPE memory operand. */
9113 if (GET_CODE (x) != MEM)
9121 if (GET_CODE (tmp) == REG)
9123 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9126 /* Handle [reg+UIMM]. */
9127 else if (GET_CODE (tmp) == PLUS &&
9128 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9132 if (GET_CODE (XEXP (tmp, 0)) != REG)
9135 x = INTVAL (XEXP (tmp, 1));
9136 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9140 /* Fall through. Must be [reg+reg]. */
9142 if (GET_CODE (tmp) == REG)
9143 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
9144 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9146 if (REGNO (XEXP (tmp, 0)) == 0)
9147 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9148 reg_names[ REGNO (XEXP (tmp, 0)) ]);
9150 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9151 reg_names[ REGNO (XEXP (tmp, 1)) ]);
9159 if (GET_CODE (x) == REG)
9160 fprintf (file, "%s", reg_names[REGNO (x)]);
9161 else if (GET_CODE (x) == MEM)
9163 /* We need to handle PRE_INC and PRE_DEC here, since we need to
9164 know the width from the mode. */
9165 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
9166 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9167 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9168 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
9169 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9170 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9172 output_address (XEXP (x, 0));
9175 output_addr_const (file, x);
9179 assemble_name (file, rs6000_get_some_local_dynamic_name ());
9183 output_operand_lossage ("invalid %%xn code");
9187 /* Print the address of an operand. */
9190 print_operand_address (FILE *file, rtx x)
9192 if (GET_CODE (x) == REG)
9193 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9194 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9195 || GET_CODE (x) == LABEL_REF)
9197 output_addr_const (file, x);
9198 if (small_data_operand (x, GET_MODE (x)))
9199 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9200 reg_names[SMALL_DATA_REG]);
9201 else if (TARGET_TOC)
9204 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9206 if (REGNO (XEXP (x, 0)) == 0)
9207 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9208 reg_names[ REGNO (XEXP (x, 0)) ]);
9210 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9211 reg_names[ REGNO (XEXP (x, 1)) ]);
9213 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
9214 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9215 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
9217 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9218 && CONSTANT_P (XEXP (x, 1)))
9220 output_addr_const (file, XEXP (x, 1));
9221 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9225 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9226 && CONSTANT_P (XEXP (x, 1)))
9228 fprintf (file, "lo16(");
9229 output_addr_const (file, XEXP (x, 1));
9230 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9233 else if (legitimate_constant_pool_address_p (x))
9235 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9237 rtx contains_minus = XEXP (x, 1);
9241 /* Find the (minus (sym) (toc)) buried in X, and temporarily
9242 turn it into (sym) for output_addr_const. */
9243 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9244 contains_minus = XEXP (contains_minus, 0);
9246 minus = XEXP (contains_minus, 0);
9247 symref = XEXP (minus, 0);
9248 XEXP (contains_minus, 0) = symref;
9253 name = XSTR (symref, 0);
9254 newname = alloca (strlen (name) + sizeof ("@toc"));
9255 strcpy (newname, name);
9256 strcat (newname, "@toc");
9257 XSTR (symref, 0) = newname;
9259 output_addr_const (file, XEXP (x, 1));
9261 XSTR (symref, 0) = name;
9262 XEXP (contains_minus, 0) = minus;
9265 output_addr_const (file, XEXP (x, 1));
9267 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9273 /* Target hook for assembling integer objects. The PowerPC version has
9274 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9275 is defined. It also needs to handle DI-mode objects on 64-bit
9279 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
9281 #ifdef RELOCATABLE_NEEDS_FIXUP
9282 /* Special handling for SI values. */
9283 if (size == 4 && aligned_p)
9285 extern int in_toc_section (void);
9286 static int recurse = 0;
9288 /* For -mrelocatable, we mark all addresses that need to be fixed up
9289 in the .fixup section. */
9290 if (TARGET_RELOCATABLE
9291 && !in_toc_section ()
9292 && !in_text_section ()
9294 && GET_CODE (x) != CONST_INT
9295 && GET_CODE (x) != CONST_DOUBLE
9301 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9303 ASM_OUTPUT_LABEL (asm_out_file, buf);
9304 fprintf (asm_out_file, "\t.long\t(");
9305 output_addr_const (asm_out_file, x);
9306 fprintf (asm_out_file, ")@fixup\n");
9307 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9308 ASM_OUTPUT_ALIGN (asm_out_file, 2);
9309 fprintf (asm_out_file, "\t.long\t");
9310 assemble_name (asm_out_file, buf);
9311 fprintf (asm_out_file, "\n\t.previous\n");
9315 /* Remove initial .'s to turn a -mcall-aixdesc function
9316 address into the address of the descriptor, not the function
9318 else if (GET_CODE (x) == SYMBOL_REF
9319 && XSTR (x, 0)[0] == '.'
9320 && DEFAULT_ABI == ABI_AIX)
9322 const char *name = XSTR (x, 0);
9323 while (*name == '.')
9326 fprintf (asm_out_file, "\t.long\t%s\n", name);
9330 #endif /* RELOCATABLE_NEEDS_FIXUP */
9331 return default_assemble_integer (x, size, aligned_p);
9334 #ifdef HAVE_GAS_HIDDEN
9335 /* Emit an assembler directive to set symbol visibility for DECL to
9339 rs6000_assemble_visibility (tree decl, int vis)
9341 /* Functions need to have their entry point symbol visibility set as
9342 well as their descriptor symbol visibility. */
9343 if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL)
9345 static const char * const visibility_types[] = {
9346 NULL, "internal", "hidden", "protected"
9349 const char *name, *type;
9351 name = ((* targetm.strip_name_encoding)
9352 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
9353 type = visibility_types[vis];
9355 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9356 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
9359 default_assemble_visibility (decl, vis);
9364 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
9366 /* Reversal of FP compares takes care -- an ordered compare
9367 becomes an unordered compare and vice versa. */
9368 if (mode == CCFPmode
9369 && (!flag_finite_math_only
9370 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
9371 || code == UNEQ || code == LTGT))
9372 return reverse_condition_maybe_unordered (code);
9374 return reverse_condition (code);
9377 /* Generate a compare for CODE. Return a brand-new rtx that
9378 represents the result of the compare. */
9381 rs6000_generate_compare (enum rtx_code code)
9383 enum machine_mode comp_mode;
9386 if (rs6000_compare_fp_p)
9387 comp_mode = CCFPmode;
9388 else if (code == GTU || code == LTU
9389 || code == GEU || code == LEU)
9390 comp_mode = CCUNSmode;
9394 /* First, the compare. */
9395 compare_result = gen_reg_rtx (comp_mode);
9397 /* SPE FP compare instructions on the GPRs. Yuck! */
9398 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
9399 && rs6000_compare_fp_p)
9401 rtx cmp, or1, or2, or_result, compare_result2;
9409 cmp = flag_finite_math_only
9410 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
9412 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
9413 rs6000_compare_op1);
9421 cmp = flag_finite_math_only
9422 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
9424 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
9425 rs6000_compare_op1);
9433 cmp = flag_finite_math_only
9434 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
9436 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
9437 rs6000_compare_op1);
9443 /* Synthesize LE and GE from LT/GT || EQ. */
9444 if (code == LE || code == GE || code == LEU || code == GEU)
9446 /* Synthesize GE/LE frome GT/LT || EQ. */
9452 case LE: code = LT; break;
9453 case GE: code = GT; break;
9454 case LEU: code = LT; break;
9455 case GEU: code = GT; break;
9459 or1 = gen_reg_rtx (SImode);
9460 or2 = gen_reg_rtx (SImode);
9461 or_result = gen_reg_rtx (CCEQmode);
9462 compare_result2 = gen_reg_rtx (CCFPmode);
9465 cmp = flag_finite_math_only
9466 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
9468 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
9469 rs6000_compare_op1);
9472 /* The MC8540 FP compare instructions set the CR bits
9473 differently than other PPC compare instructions. For
9474 that matter, there is no generic test instruction, but a
9475 testgt, testlt, and testeq. For a true condition, bit 2
9476 is set (x1xx) in the CR. Following the traditional CR
9482 ... bit 2 would be a GT CR alias, so later on we
9483 look in the GT bits for the branch instructions.
9484 However, we must be careful to emit correct RTL in
9485 the meantime, so optimizations don't get confused. */
9487 or1 = gen_rtx (NE, SImode, compare_result, const0_rtx);
9488 or2 = gen_rtx (NE, SImode, compare_result2, const0_rtx);
9490 /* OR them together. */
9491 cmp = gen_rtx_SET (VOIDmode, or_result,
9492 gen_rtx_COMPARE (CCEQmode,
9493 gen_rtx_IOR (SImode, or1, or2),
9495 compare_result = or_result;
9500 /* We only care about 1 bit (x1xx), so map everything to NE to
9501 maintain rtl sanity. We'll get to the right bit (x1xx) at
9502 code output time. */
9503 if (code == NE || code == LTGT)
9504 /* Do the inverse here because we have no cmpne
9505 instruction. We use the cmpeq instruction and expect
9506 to get a 0 instead. */
9515 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
9516 gen_rtx_COMPARE (comp_mode,
9518 rs6000_compare_op1)));
9520 /* Some kinds of FP comparisons need an OR operation;
9521 under flag_finite_math_only we don't bother. */
9522 if (rs6000_compare_fp_p
9523 && ! flag_finite_math_only
9524 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
9525 && (code == LE || code == GE
9526 || code == UNEQ || code == LTGT
9527 || code == UNGT || code == UNLT))
9529 enum rtx_code or1, or2;
9530 rtx or1_rtx, or2_rtx, compare2_rtx;
9531 rtx or_result = gen_reg_rtx (CCEQmode);
9535 case LE: or1 = LT; or2 = EQ; break;
9536 case GE: or1 = GT; or2 = EQ; break;
9537 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
9538 case LTGT: or1 = LT; or2 = GT; break;
9539 case UNGT: or1 = UNORDERED; or2 = GT; break;
9540 case UNLT: or1 = UNORDERED; or2 = LT; break;
9543 validate_condition_mode (or1, comp_mode);
9544 validate_condition_mode (or2, comp_mode);
9545 or1_rtx = gen_rtx (or1, SImode, compare_result, const0_rtx);
9546 or2_rtx = gen_rtx (or2, SImode, compare_result, const0_rtx);
9547 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
9548 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
9550 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
9552 compare_result = or_result;
9556 validate_condition_mode (code, GET_MODE (compare_result));
9558 return gen_rtx (code, VOIDmode, compare_result, const0_rtx);
9562 /* Emit the RTL for an sCOND pattern. */
9565 rs6000_emit_sCOND (enum rtx_code code, rtx result)
9568 enum machine_mode op_mode;
9569 enum rtx_code cond_code;
9571 condition_rtx = rs6000_generate_compare (code);
9572 cond_code = GET_CODE (condition_rtx);
9575 || cond_code == GE || cond_code == LE
9576 || cond_code == GEU || cond_code == LEU
9577 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
9579 rtx not_result = gen_reg_rtx (CCEQmode);
9580 rtx not_op, rev_cond_rtx;
9581 enum machine_mode cc_mode;
9583 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
9585 rev_cond_rtx = gen_rtx (rs6000_reverse_condition (cc_mode, cond_code),
9586 SImode, XEXP (condition_rtx, 0), const0_rtx);
9587 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
9588 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
9589 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
9592 op_mode = GET_MODE (rs6000_compare_op0);
9593 if (op_mode == VOIDmode)
9594 op_mode = GET_MODE (rs6000_compare_op1);
9596 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
9598 PUT_MODE (condition_rtx, DImode);
9599 convert_move (result, condition_rtx, 0);
9603 PUT_MODE (condition_rtx, SImode);
9604 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
9608 /* Emit a branch of kind CODE to location LOC. */
9611 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
9613 rtx condition_rtx, loc_ref;
9615 condition_rtx = rs6000_generate_compare (code);
9616 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
9617 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
9618 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
9622 /* Return the string to output a conditional branch to LABEL, which is
9623 the operand number of the label, or -1 if the branch is really a
9626 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
9627 condition code register and its mode specifies what kind of
9630 REVERSED is nonzero if we should reverse the sense of the comparison.
9632 INSN is the insn. */
9635 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
9637 static char string[64];
9638 enum rtx_code code = GET_CODE (op);
9639 rtx cc_reg = XEXP (op, 0);
9640 enum machine_mode mode = GET_MODE (cc_reg);
9641 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
9642 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
9643 int really_reversed = reversed ^ need_longbranch;
9649 validate_condition_mode (code, mode);
9651 /* Work out which way this really branches. We could use
9652 reverse_condition_maybe_unordered here always but this
9653 makes the resulting assembler clearer. */
9654 if (really_reversed)
9656 /* Reversal of FP compares takes care -- an ordered compare
9657 becomes an unordered compare and vice versa. */
9658 if (mode == CCFPmode)
9659 code = reverse_condition_maybe_unordered (code);
9661 code = reverse_condition (code);
9664 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
9666 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
9669 /* Opposite of GT. */
9671 else if (code == NE)
9679 /* Not all of these are actually distinct opcodes, but
9680 we distinguish them for clarity of the resulting assembler. */
9682 ccode = "ne"; break;
9684 ccode = "eq"; break;
9686 ccode = "ge"; break;
9687 case GT: case GTU: case UNGT:
9688 ccode = "gt"; break;
9690 ccode = "le"; break;
9691 case LT: case LTU: case UNLT:
9692 ccode = "lt"; break;
9693 case UNORDERED: ccode = "un"; break;
9694 case ORDERED: ccode = "nu"; break;
9695 case UNGE: ccode = "nl"; break;
9696 case UNLE: ccode = "ng"; break;
9701 /* Maybe we have a guess as to how likely the branch is.
9702 The old mnemonics don't have a way to specify this information. */
9704 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
9705 if (note != NULL_RTX)
9707 /* PROB is the difference from 50%. */
9708 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
9709 bool always_hint = rs6000_cpu != PROCESSOR_POWER4;
9711 /* Only hint for highly probable/improbable branches on newer
9712 cpus as static prediction overrides processor dynamic
9713 prediction. For older cpus we may as well always hint, but
9714 assume not taken for branches that are very close to 50% as a
9715 mispredicted taken branch is more expensive than a
9716 mispredicted not-taken branch. */
9718 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
9720 if (abs (prob) > REG_BR_PROB_BASE / 20
9721 && ((prob > 0) ^ need_longbranch))
9729 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
9731 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
9733 /* We need to escape any '%' characters in the reg_names string.
9734 Assume they'd only be the first character... */
9735 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
9737 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
9741 /* If the branch distance was too far, we may have to use an
9742 unconditional branch to go the distance. */
9743 if (need_longbranch)
9744 s += sprintf (s, ",$+8\n\tb %s", label);
9746 s += sprintf (s, ",%s", label);
9752 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
9753 operands of the last comparison is nonzero/true, FALSE_COND if it
9754 is zero/false. Return 0 if the hardware has no such operation. */
9757 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
9759 enum rtx_code code = GET_CODE (op);
9760 rtx op0 = rs6000_compare_op0;
9761 rtx op1 = rs6000_compare_op1;
9763 enum machine_mode compare_mode = GET_MODE (op0);
9764 enum machine_mode result_mode = GET_MODE (dest);
9767 /* These modes should always match. */
9768 if (GET_MODE (op1) != compare_mode
9769 /* In the isel case however, we can use a compare immediate, so
9770 op1 may be a small constant. */
9771 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
9773 if (GET_MODE (true_cond) != result_mode)
9775 if (GET_MODE (false_cond) != result_mode)
9778 /* First, work out if the hardware can do this at all, or
9779 if it's too slow... */
9780 if (! rs6000_compare_fp_p)
9783 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
9787 /* Eliminate half of the comparisons by switching operands, this
9788 makes the remaining code simpler. */
9789 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
9790 || code == LTGT || code == LT || code == UNLE)
9792 code = reverse_condition_maybe_unordered (code);
9794 true_cond = false_cond;
9798 /* UNEQ and LTGT take four instructions for a comparison with zero,
9799 it'll probably be faster to use a branch here too. */
9800 if (code == UNEQ && HONOR_NANS (compare_mode))
9803 if (GET_CODE (op1) == CONST_DOUBLE)
9804 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
9806 /* We're going to try to implement comparisons by performing
9807 a subtract, then comparing against zero. Unfortunately,
9808 Inf - Inf is NaN which is not zero, and so if we don't
9809 know that the operand is finite and the comparison
9810 would treat EQ different to UNORDERED, we can't do it. */
9811 if (HONOR_INFINITIES (compare_mode)
9812 && code != GT && code != UNGE
9813 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
9814 /* Constructs of the form (a OP b ? a : b) are safe. */
9815 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
9816 || (! rtx_equal_p (op0, true_cond)
9817 && ! rtx_equal_p (op1, true_cond))))
9819 /* At this point we know we can use fsel. */
9821 /* Reduce the comparison to a comparison against zero. */
9822 temp = gen_reg_rtx (compare_mode);
9823 emit_insn (gen_rtx_SET (VOIDmode, temp,
9824 gen_rtx_MINUS (compare_mode, op0, op1)));
9826 op1 = CONST0_RTX (compare_mode);
9828 /* If we don't care about NaNs we can reduce some of the comparisons
9829 down to faster ones. */
9830 if (! HONOR_NANS (compare_mode))
9836 true_cond = false_cond;
9849 /* Now, reduce everything down to a GE. */
9856 temp = gen_reg_rtx (compare_mode);
9857 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
9862 temp = gen_reg_rtx (compare_mode);
9863 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
9868 temp = gen_reg_rtx (compare_mode);
9869 emit_insn (gen_rtx_SET (VOIDmode, temp,
9870 gen_rtx_NEG (compare_mode,
9871 gen_rtx_ABS (compare_mode, op0))));
9876 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
9877 temp = gen_reg_rtx (result_mode);
9878 emit_insn (gen_rtx_SET (VOIDmode, temp,
9879 gen_rtx_IF_THEN_ELSE (result_mode,
9880 gen_rtx_GE (VOIDmode,
9882 true_cond, false_cond)));
9883 false_cond = true_cond;
9886 temp = gen_reg_rtx (compare_mode);
9887 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
9892 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
9893 temp = gen_reg_rtx (result_mode);
9894 emit_insn (gen_rtx_SET (VOIDmode, temp,
9895 gen_rtx_IF_THEN_ELSE (result_mode,
9896 gen_rtx_GE (VOIDmode,
9898 true_cond, false_cond)));
9899 true_cond = false_cond;
9902 temp = gen_reg_rtx (compare_mode);
9903 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
9911 emit_insn (gen_rtx_SET (VOIDmode, dest,
9912 gen_rtx_IF_THEN_ELSE (result_mode,
9913 gen_rtx_GE (VOIDmode,
9915 true_cond, false_cond)));
9919 /* Same as above, but for ints (isel). */
9922 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
9924 rtx condition_rtx, cr;
9926 /* All isel implementations thus far are 32-bits. */
9927 if (GET_MODE (rs6000_compare_op0) != SImode)
9930 /* We still have to do the compare, because isel doesn't do a
9931 compare, it just looks at the CRx bits set by a previous compare
9933 condition_rtx = rs6000_generate_compare (GET_CODE (op));
9934 cr = XEXP (condition_rtx, 0);
9936 if (GET_MODE (cr) == CCmode)
9937 emit_insn (gen_isel_signed (dest, condition_rtx,
9938 true_cond, false_cond, cr));
9940 emit_insn (gen_isel_unsigned (dest, condition_rtx,
9941 true_cond, false_cond, cr));
9947 output_isel (rtx *operands)
9951 code = GET_CODE (operands[1]);
9952 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
9954 PUT_CODE (operands[1], reverse_condition (code));
9955 return "isel %0,%3,%2,%j1";
9958 return "isel %0,%2,%3,%j1";
9962 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
9964 enum machine_mode mode = GET_MODE (op0);
9968 if (code == SMAX || code == SMIN)
9973 if (code == SMAX || code == UMAX)
9974 target = emit_conditional_move (dest, c, op0, op1, mode,
9977 target = emit_conditional_move (dest, c, op0, op1, mode,
9979 if (target == NULL_RTX)
9982 emit_move_insn (dest, target);
9985 /* Emit instructions to move SRC to DST. Called by splitters for
9986 multi-register moves. It will emit at most one instruction for
9987 each register that is accessed; that is, it won't emit li/lis pairs
9988 (or equivalent for 64-bit code). One of SRC or DST must be a hard
9992 rs6000_split_multireg_move (rtx dst, rtx src)
9994 /* The register number of the first register being moved. */
9996 /* The mode that is to be moved. */
9997 enum machine_mode mode;
9998 /* The mode that the move is being done in, and its size. */
9999 enum machine_mode reg_mode;
10001 /* The number of registers that will be moved. */
10004 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10005 mode = GET_MODE (dst);
10006 nregs = HARD_REGNO_NREGS (reg, mode);
10007 if (FP_REGNO_P (reg))
10009 else if (ALTIVEC_REGNO_P (reg))
10010 reg_mode = V16QImode;
10012 reg_mode = word_mode;
10013 reg_mode_size = GET_MODE_SIZE (reg_mode);
10015 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
10018 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
10020 /* Move register range backwards, if we might have destructive
10023 for (i = nregs - 1; i >= 0; i--)
10024 emit_insn (gen_rtx_SET (VOIDmode,
10025 simplify_gen_subreg (reg_mode, dst, mode,
10026 i * reg_mode_size),
10027 simplify_gen_subreg (reg_mode, src, mode,
10028 i * reg_mode_size)));
10034 bool used_update = false;
10036 if (GET_CODE (src) == MEM && INT_REGNO_P (reg))
10040 if (GET_CODE (XEXP (src, 0)) == PRE_INC
10041 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
10044 breg = XEXP (XEXP (src, 0), 0);
10045 delta_rtx = GET_CODE (XEXP (src, 0)) == PRE_INC
10046 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
10047 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)));
10048 emit_insn (TARGET_32BIT
10049 ? gen_addsi3 (breg, breg, delta_rtx)
10050 : gen_adddi3 (breg, breg, delta_rtx));
10051 src = gen_rtx_MEM (mode, breg);
10054 /* We have now address involving an base register only.
10055 If we use one of the registers to address memory,
10056 we have change that register last. */
10058 breg = (GET_CODE (XEXP (src, 0)) == PLUS
10059 ? XEXP (XEXP (src, 0), 0)
10065 if (REGNO (breg) >= REGNO (dst)
10066 && REGNO (breg) < REGNO (dst) + nregs)
10067 j = REGNO (breg) - REGNO (dst);
10070 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
10074 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
10075 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
10078 breg = XEXP (XEXP (dst, 0), 0);
10079 delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC
10080 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
10081 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)));
10083 /* We have to update the breg before doing the store.
10084 Use store with update, if available. */
10088 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
10089 emit_insn (TARGET_32BIT
10090 ? gen_movsi_update (breg, breg, delta_rtx, nsrc)
10091 : gen_movdi_update (breg, breg, delta_rtx, nsrc));
10092 used_update = true;
10095 emit_insn (TARGET_32BIT
10096 ? gen_addsi3 (breg, breg, delta_rtx)
10097 : gen_adddi3 (breg, breg, delta_rtx));
10098 dst = gen_rtx_MEM (mode, breg);
10102 for (i = 0; i < nregs; i++)
10104 /* Calculate index to next subword. */
10109 /* If compiler already emited move of first word by
10110 store with update, no need to do anything. */
10111 if (j == 0 && used_update)
10114 emit_insn (gen_rtx_SET (VOIDmode,
10115 simplify_gen_subreg (reg_mode, dst, mode,
10116 j * reg_mode_size),
10117 simplify_gen_subreg (reg_mode, src, mode,
10118 j * reg_mode_size)));
10124 /* This page contains routines that are used to determine what the
10125 function prologue and epilogue code will do and write them out. */
10127 /* Return the first fixed-point register that is required to be
10128 saved. 32 if none. */
10131 first_reg_to_save (void)
10135 /* Find lowest numbered live register. */
10136 for (first_reg = 13; first_reg <= 31; first_reg++)
10137 if (regs_ever_live[first_reg]
10138 && (! call_used_regs[first_reg]
10139 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
10140 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
10141 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))))
10146 && current_function_uses_pic_offset_table
10147 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
10148 return RS6000_PIC_OFFSET_TABLE_REGNUM;
10154 /* Similar, for FP regs. */
10157 first_fp_reg_to_save (void)
10161 /* Find lowest numbered live register. */
10162 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
10163 if (regs_ever_live[first_reg])
10169 /* Similar, for AltiVec regs. */
10172 first_altivec_reg_to_save (void)
10176 /* Stack frame remains as is unless we are in AltiVec ABI. */
10177 if (! TARGET_ALTIVEC_ABI)
10178 return LAST_ALTIVEC_REGNO + 1;
10180 /* Find lowest numbered live register. */
10181 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
10182 if (regs_ever_live[i])
10188 /* Return a 32-bit mask of the AltiVec registers we need to set in
10189 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
10190 the 32-bit word is 0. */
10192 static unsigned int
10193 compute_vrsave_mask (void)
10195 unsigned int i, mask = 0;
10197 /* First, find out if we use _any_ altivec registers. */
10198 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
10199 if (regs_ever_live[i])
10200 mask |= ALTIVEC_REG_BIT (i);
10205 /* Next, remove the argument registers from the set. These must
10206 be in the VRSAVE mask set by the caller, so we don't need to add
10207 them in again. More importantly, the mask we compute here is
10208 used to generate CLOBBERs in the set_vrsave insn, and we do not
10209 wish the argument registers to die. */
10210 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
10211 mask &= ~ALTIVEC_REG_BIT (i);
10213 /* Similarly, remove the return value from the set. */
10216 diddle_return_value (is_altivec_return_reg, &yes);
10218 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
10225 is_altivec_return_reg (rtx reg, void *xyes)
10227 bool *yes = (bool *) xyes;
10228 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
10233 /* Calculate the stack information for the current function. This is
10234 complicated by having two separate calling sequences, the AIX calling
10235 sequence and the V.4 calling sequence.
10237 AIX (and Darwin/Mac OS X) stack frames look like:
10239 SP----> +---------------------------------------+
10240 | back chain to caller | 0 0
10241 +---------------------------------------+
10242 | saved CR | 4 8 (8-11)
10243 +---------------------------------------+
10245 +---------------------------------------+
10246 | reserved for compilers | 12 24
10247 +---------------------------------------+
10248 | reserved for binders | 16 32
10249 +---------------------------------------+
10250 | saved TOC pointer | 20 40
10251 +---------------------------------------+
10252 | Parameter save area (P) | 24 48
10253 +---------------------------------------+
10254 | Alloca space (A) | 24+P etc.
10255 +---------------------------------------+
10256 | Local variable space (L) | 24+P+A
10257 +---------------------------------------+
10258 | Float/int conversion temporary (X) | 24+P+A+L
10259 +---------------------------------------+
10260 | Save area for AltiVec registers (W) | 24+P+A+L+X
10261 +---------------------------------------+
10262 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
10263 +---------------------------------------+
10264 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
10265 +---------------------------------------+
10266 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
10267 +---------------------------------------+
10268 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
10269 +---------------------------------------+
10270 old SP->| back chain to caller's caller |
10271 +---------------------------------------+
10273 The required alignment for AIX configurations is two words (i.e., 8
10277 V.4 stack frames look like:
10279 SP----> +---------------------------------------+
10280 | back chain to caller | 0
10281 +---------------------------------------+
10282 | caller's saved LR | 4
10283 +---------------------------------------+
10284 | Parameter save area (P) | 8
10285 +---------------------------------------+
10286 | Alloca space (A) | 8+P
10287 +---------------------------------------+
10288 | Varargs save area (V) | 8+P+A
10289 +---------------------------------------+
10290 | Local variable space (L) | 8+P+A+V
10291 +---------------------------------------+
10292 | Float/int conversion temporary (X) | 8+P+A+V+L
10293 +---------------------------------------+
10294 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
10295 +---------------------------------------+
10296 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
10297 +---------------------------------------+
10298 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
10299 +---------------------------------------+
10300 | SPE: area for 64-bit GP registers |
10301 +---------------------------------------+
10302 | SPE alignment padding |
10303 +---------------------------------------+
10304 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
10305 +---------------------------------------+
10306 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
10307 +---------------------------------------+
10308 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
10309 +---------------------------------------+
10310 old SP->| back chain to caller's caller |
10311 +---------------------------------------+
10313 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
10314 given. (But note below and in sysv4.h that we require only 8 and
10315 may round up the size of our stack frame anyways. The historical
10316 reason is early versions of powerpc-linux which didn't properly
10317 align the stack at program startup. A happy side-effect is that
10318 -mno-eabi libraries can be used with -meabi programs.)
10320 The EABI configuration defaults to the V.4 layout. However,
10321 the stack alignment requirements may differ. If -mno-eabi is not
10322 given, the required stack alignment is 8 bytes; if -mno-eabi is
10323 given, the required alignment is 16 bytes. (But see V.4 comment
10326 #ifndef ABI_STACK_BOUNDARY
10327 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
10330 static rs6000_stack_t *
10331 rs6000_stack_info (void)
10333 static rs6000_stack_t info, zero_info;
10334 rs6000_stack_t *info_ptr = &info;
10335 int reg_size = TARGET_POWERPC64 ? 8 : 4;
10337 HOST_WIDE_INT total_raw_size;
10339 /* Zero all fields portably. */
10344 /* Cache value so we don't rescan instruction chain over and over. */
10345 if (cfun->machine->insn_chain_scanned_p == 0)
10347 cfun->machine->insn_chain_scanned_p = 1;
10348 info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
10352 /* Select which calling sequence. */
10353 info_ptr->abi = DEFAULT_ABI;
10355 /* Calculate which registers need to be saved & save area size. */
10356 info_ptr->first_gp_reg_save = first_reg_to_save ();
10357 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
10358 even if it currently looks like we won't. */
10359 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
10360 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
10361 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
10362 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
10363 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
10365 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
10367 /* For the SPE, we have an additional upper 32-bits on each GPR.
10368 Ideally we should save the entire 64-bits only when the upper
10369 half is used in SIMD instructions. Since we only record
10370 registers live (not the size they are used in), this proves
10371 difficult because we'd have to traverse the instruction chain at
10372 the right time, taking reload into account. This is a real pain,
10373 so we opt to save the GPRs in 64-bits always if but one register
10374 gets used in 64-bits. Otherwise, all the registers in the frame
10375 get saved in 32-bits.
10377 So... since when we save all GPRs (except the SP) in 64-bits, the
10378 traditional GP save area will be empty. */
10379 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10380 info_ptr->gp_size = 0;
10382 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
10383 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
10385 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
10386 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
10387 - info_ptr->first_altivec_reg_save);
10389 /* Does this function call anything? */
10390 info_ptr->calls_p = (! current_function_is_leaf
10391 || cfun->machine->ra_needs_full_frame);
10393 /* Determine if we need to save the link register. */
10394 if (rs6000_ra_ever_killed ()
10395 || (DEFAULT_ABI == ABI_AIX
10396 && current_function_profile
10397 && !TARGET_PROFILE_KERNEL)
10398 #ifdef TARGET_RELOCATABLE
10399 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
10401 || (info_ptr->first_fp_reg_save != 64
10402 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
10403 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
10404 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
10405 || (DEFAULT_ABI == ABI_DARWIN
10407 && current_function_uses_pic_offset_table)
10408 || info_ptr->calls_p)
10410 info_ptr->lr_save_p = 1;
10411 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
10414 /* Determine if we need to save the condition code registers. */
10415 if (regs_ever_live[CR2_REGNO]
10416 || regs_ever_live[CR3_REGNO]
10417 || regs_ever_live[CR4_REGNO])
10419 info_ptr->cr_save_p = 1;
10420 if (DEFAULT_ABI == ABI_V4)
10421 info_ptr->cr_size = reg_size;
10424 /* If the current function calls __builtin_eh_return, then we need
10425 to allocate stack space for registers that will hold data for
10426 the exception handler. */
10427 if (current_function_calls_eh_return)
10430 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
10433 /* SPE saves EH registers in 64-bits. */
10434 ehrd_size = i * (TARGET_SPE_ABI
10435 && info_ptr->spe_64bit_regs_used != 0
10436 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
10441 /* Determine various sizes. */
10442 info_ptr->reg_size = reg_size;
10443 info_ptr->fixed_size = RS6000_SAVE_AREA;
10444 info_ptr->varargs_size = RS6000_VARARGS_AREA;
10445 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
10446 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
10449 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10450 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
10452 info_ptr->spe_gp_size = 0;
10454 if (TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE)
10456 info_ptr->vrsave_mask = compute_vrsave_mask ();
10457 info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0;
10461 info_ptr->vrsave_mask = 0;
10462 info_ptr->vrsave_size = 0;
10465 /* Calculate the offsets. */
10466 switch (DEFAULT_ABI)
10474 info_ptr->fp_save_offset = - info_ptr->fp_size;
10475 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
10477 if (TARGET_ALTIVEC_ABI)
10479 info_ptr->vrsave_save_offset
10480 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
10482 /* Align stack so vector save area is on a quadword boundary. */
10483 if (info_ptr->altivec_size != 0)
10484 info_ptr->altivec_padding_size
10485 = 16 - (-info_ptr->vrsave_save_offset % 16);
10487 info_ptr->altivec_padding_size = 0;
10489 info_ptr->altivec_save_offset
10490 = info_ptr->vrsave_save_offset
10491 - info_ptr->altivec_padding_size
10492 - info_ptr->altivec_size;
10494 /* Adjust for AltiVec case. */
10495 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
10498 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
10499 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
10500 info_ptr->lr_save_offset = 2*reg_size;
10504 info_ptr->fp_save_offset = - info_ptr->fp_size;
10505 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
10506 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
10508 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
10510 /* Align stack so SPE GPR save area is aligned on a
10511 double-word boundary. */
10512 if (info_ptr->spe_gp_size != 0)
10513 info_ptr->spe_padding_size
10514 = 8 - (-info_ptr->cr_save_offset % 8);
10516 info_ptr->spe_padding_size = 0;
10518 info_ptr->spe_gp_save_offset
10519 = info_ptr->cr_save_offset
10520 - info_ptr->spe_padding_size
10521 - info_ptr->spe_gp_size;
10523 /* Adjust for SPE case. */
10524 info_ptr->toc_save_offset
10525 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
10527 else if (TARGET_ALTIVEC_ABI)
10529 info_ptr->vrsave_save_offset
10530 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
10532 /* Align stack so vector save area is on a quadword boundary. */
10533 if (info_ptr->altivec_size != 0)
10534 info_ptr->altivec_padding_size
10535 = 16 - (-info_ptr->vrsave_save_offset % 16);
10537 info_ptr->altivec_padding_size = 0;
10539 info_ptr->altivec_save_offset
10540 = info_ptr->vrsave_save_offset
10541 - info_ptr->altivec_padding_size
10542 - info_ptr->altivec_size;
10544 /* Adjust for AltiVec case. */
10545 info_ptr->toc_save_offset
10546 = info_ptr->altivec_save_offset - info_ptr->toc_size;
10549 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
10550 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
10551 info_ptr->lr_save_offset = reg_size;
10555 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
10556 + info_ptr->gp_size
10557 + info_ptr->altivec_size
10558 + info_ptr->altivec_padding_size
10559 + info_ptr->spe_gp_size
10560 + info_ptr->spe_padding_size
10562 + info_ptr->cr_size
10563 + info_ptr->lr_size
10564 + info_ptr->vrsave_size
10565 + info_ptr->toc_size,
10566 (TARGET_ALTIVEC_ABI || ABI_DARWIN)
10569 total_raw_size = (info_ptr->vars_size
10570 + info_ptr->parm_size
10571 + info_ptr->save_size
10572 + info_ptr->varargs_size
10573 + info_ptr->fixed_size);
10575 info_ptr->total_size =
10576 RS6000_ALIGN (total_raw_size, ABI_STACK_BOUNDARY / BITS_PER_UNIT);
10578 /* Determine if we need to allocate any stack frame:
10580 For AIX we need to push the stack if a frame pointer is needed
10581 (because the stack might be dynamically adjusted), if we are
10582 debugging, if we make calls, or if the sum of fp_save, gp_save,
10583 and local variables are more than the space needed to save all
10584 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
10585 + 18*8 = 288 (GPR13 reserved).
10587 For V.4 we don't have the stack cushion that AIX uses, but assume
10588 that the debugger can handle stackless frames. */
10590 if (info_ptr->calls_p)
10591 info_ptr->push_p = 1;
10593 else if (DEFAULT_ABI == ABI_V4)
10594 info_ptr->push_p = total_raw_size > info_ptr->fixed_size;
10596 else if (frame_pointer_needed)
10597 info_ptr->push_p = 1;
10599 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
10600 info_ptr->push_p = 1;
10604 = total_raw_size - info_ptr->fixed_size > (TARGET_32BIT ? 220 : 288);
10606 /* Zero offsets if we're not saving those registers. */
10607 if (info_ptr->fp_size == 0)
10608 info_ptr->fp_save_offset = 0;
10610 if (info_ptr->gp_size == 0)
10611 info_ptr->gp_save_offset = 0;
10613 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
10614 info_ptr->altivec_save_offset = 0;
10616 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
10617 info_ptr->vrsave_save_offset = 0;
10619 if (! TARGET_SPE_ABI
10620 || info_ptr->spe_64bit_regs_used == 0
10621 || info_ptr->spe_gp_size == 0)
10622 info_ptr->spe_gp_save_offset = 0;
10624 if (! info_ptr->lr_save_p)
10625 info_ptr->lr_save_offset = 0;
10627 if (! info_ptr->cr_save_p)
10628 info_ptr->cr_save_offset = 0;
10630 if (! info_ptr->toc_save_p)
10631 info_ptr->toc_save_offset = 0;
10636 /* Return true if the current function uses any GPRs in 64-bit SIMD
10640 spe_func_has_64bit_regs_p (void)
10644 /* Functions that save and restore all the call-saved registers will
10645 need to save/restore the registers in 64-bits. */
10646 if (current_function_calls_eh_return
10647 || current_function_calls_setjmp
10648 || current_function_has_nonlocal_goto)
10651 insns = get_insns ();
10653 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
10659 i = PATTERN (insn);
10660 if (GET_CODE (i) == SET
10661 && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i))))
10670 debug_stack_info (rs6000_stack_t *info)
10672 const char *abi_string;
10675 info = rs6000_stack_info ();
10677 fprintf (stderr, "\nStack information for function %s:\n",
10678 ((current_function_decl && DECL_NAME (current_function_decl))
10679 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
10684 default: abi_string = "Unknown"; break;
10685 case ABI_NONE: abi_string = "NONE"; break;
10686 case ABI_AIX: abi_string = "AIX"; break;
10687 case ABI_DARWIN: abi_string = "Darwin"; break;
10688 case ABI_V4: abi_string = "V.4"; break;
10691 fprintf (stderr, "\tABI = %5s\n", abi_string);
10693 if (TARGET_ALTIVEC_ABI)
10694 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
10696 if (TARGET_SPE_ABI)
10697 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
10699 if (info->first_gp_reg_save != 32)
10700 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
10702 if (info->first_fp_reg_save != 64)
10703 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
10705 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
10706 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
10707 info->first_altivec_reg_save);
10709 if (info->lr_save_p)
10710 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
10712 if (info->cr_save_p)
10713 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
10715 if (info->toc_save_p)
10716 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
10718 if (info->vrsave_mask)
10719 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
10722 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
10725 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
10727 if (info->gp_save_offset)
10728 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
10730 if (info->fp_save_offset)
10731 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
10733 if (info->altivec_save_offset)
10734 fprintf (stderr, "\taltivec_save_offset = %5d\n",
10735 info->altivec_save_offset);
10737 if (info->spe_gp_save_offset)
10738 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
10739 info->spe_gp_save_offset);
10741 if (info->vrsave_save_offset)
10742 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
10743 info->vrsave_save_offset);
10745 if (info->lr_save_offset)
10746 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
10748 if (info->cr_save_offset)
10749 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
10751 if (info->toc_save_offset)
10752 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
10754 if (info->varargs_save_offset)
10755 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
10757 if (info->total_size)
10758 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
10761 if (info->varargs_size)
10762 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
10764 if (info->vars_size)
10765 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
10768 if (info->parm_size)
10769 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
10771 if (info->fixed_size)
10772 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
10775 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
10777 if (info->spe_gp_size)
10778 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
10781 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
10783 if (info->altivec_size)
10784 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
10786 if (info->vrsave_size)
10787 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
10789 if (info->altivec_padding_size)
10790 fprintf (stderr, "\taltivec_padding_size= %5d\n",
10791 info->altivec_padding_size);
10793 if (info->spe_padding_size)
10794 fprintf (stderr, "\tspe_padding_size = %5d\n",
10795 info->spe_padding_size);
10798 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
10801 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
10803 if (info->toc_size)
10804 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
10806 if (info->save_size)
10807 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
10809 if (info->reg_size != 4)
10810 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
10812 fprintf (stderr, "\n");
10816 rs6000_return_addr (int count, rtx frame)
10818 /* Currently we don't optimize very well between prolog and body
10819 code and for PIC code the code can be actually quite bad, so
10820 don't try to be too clever here. */
10821 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
10823 cfun->machine->ra_needs_full_frame = 1;
10830 plus_constant (copy_to_reg
10831 (gen_rtx_MEM (Pmode,
10832 memory_address (Pmode, frame))),
10833 RETURN_ADDRESS_OFFSET)));
10836 cfun->machine->ra_need_lr = 1;
10837 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
10840 /* Say whether a function is a candidate for sibcall handling or not.
10841 We do not allow indirect calls to be optimized into sibling calls.
10842 Also, we can't do it if there are any vector parameters; there's
10843 nowhere to put the VRsave code so it works; note that functions with
10844 vector parameters are required to have a prototype, so the argument
10845 type info must be available here. (The tail recursion case can work
10846 with vector parameters, but there's no way to distinguish here.) */
10848 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10853 if (TARGET_ALTIVEC_VRSAVE)
10855 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
10856 type; type = TREE_CHAIN (type))
10858 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
10862 if (DEFAULT_ABI == ABI_DARWIN
10863 || (*targetm.binds_local_p) (decl))
10865 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
10867 if (!lookup_attribute ("longcall", attr_list)
10868 || lookup_attribute ("shortcall", attr_list))
10876 rs6000_ra_ever_killed (void)
10882 /* Irritatingly, there are two kinds of thunks -- those created with
10883 TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go
10884 through the regular part of the compiler. This is a very hacky
10885 way to tell them apart. */
10886 if (current_function_is_thunk && !no_new_pseudos)
10889 /* regs_ever_live has LR marked as used if any sibcalls are present,
10890 but this should not force saving and restoring in the
10891 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
10892 clobbers LR, so that is inappropriate. */
10894 /* Also, the prologue can generate a store into LR that
10895 doesn't really count, like this:
10898 bcl to set PIC register
10902 When we're called from the epilogue, we need to avoid counting
10903 this as a store. */
10905 push_topmost_sequence ();
10906 top = get_insns ();
10907 pop_topmost_sequence ();
10908 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
10910 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
10914 if (FIND_REG_INC_NOTE (insn, reg))
10916 else if (GET_CODE (insn) == CALL_INSN
10917 && !SIBLING_CALL_P (insn))
10919 else if (set_of (reg, insn) != NULL_RTX
10920 && !prologue_epilogue_contains (insn))
10927 /* Add a REG_MAYBE_DEAD note to the insn. */
10929 rs6000_maybe_dead (rtx insn)
10931 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
10936 /* Emit instructions needed to load the TOC register.
10937 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
10938 a constant pool; or for SVR4 -fpic. */
10941 rs6000_emit_load_toc_table (int fromprolog)
10944 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10946 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10948 rtx temp = (fromprolog
10949 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
10950 : gen_reg_rtx (Pmode));
10951 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
10953 rs6000_maybe_dead (insn);
10954 insn = emit_move_insn (dest, temp);
10956 rs6000_maybe_dead (insn);
10958 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
10961 rtx tempLR = (fromprolog
10962 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
10963 : gen_reg_rtx (Pmode));
10964 rtx temp0 = (fromprolog
10965 ? gen_rtx_REG (Pmode, 0)
10966 : gen_reg_rtx (Pmode));
10969 /* possibly create the toc section */
10970 if (! toc_initialized)
10973 function_section (current_function_decl);
10980 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
10981 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10983 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
10984 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10986 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
10988 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
10989 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
10996 static int reload_toc_labelno = 0;
10998 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
11000 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
11001 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11003 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
11004 emit_move_insn (dest, tempLR);
11005 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
11007 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
11009 rs6000_maybe_dead (insn);
11011 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
11013 /* This is for AIX code running in non-PIC ELF32. */
11016 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
11017 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11019 insn = emit_insn (gen_elf_high (dest, realsym));
11021 rs6000_maybe_dead (insn);
11022 insn = emit_insn (gen_elf_low (dest, dest, realsym));
11024 rs6000_maybe_dead (insn);
11026 else if (DEFAULT_ABI == ABI_AIX)
11029 insn = emit_insn (gen_load_toc_aix_si (dest));
11031 insn = emit_insn (gen_load_toc_aix_di (dest));
11033 rs6000_maybe_dead (insn);
11039 /* Emit instructions to restore the link register after determining where
11040 its value has been stored. */
11043 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
11045 rs6000_stack_t *info = rs6000_stack_info ();
11048 operands[0] = source;
11049 operands[1] = scratch;
11051 if (info->lr_save_p)
11053 rtx frame_rtx = stack_pointer_rtx;
11054 HOST_WIDE_INT sp_offset = 0;
11057 if (frame_pointer_needed
11058 || current_function_calls_alloca
11059 || info->total_size > 32767)
11061 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
11062 frame_rtx = operands[1];
11064 else if (info->push_p)
11065 sp_offset = info->total_size;
11067 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
11068 tmp = gen_rtx_MEM (Pmode, tmp);
11069 emit_move_insn (tmp, operands[0]);
11072 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
11076 get_TOC_alias_set (void)
11078 static int set = -1;
11080 set = new_alias_set ();
11084 /* This returns nonzero if the current function uses the TOC. This is
11085 determined by the presence of (unspec ... UNSPEC_TOC) or
11086 use (unspec ... UNSPEC_TOC), which are generated by the various
11087 load_toc_* patterns. */
11094 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11097 rtx pat = PATTERN (insn);
11100 if (GET_CODE (pat) == PARALLEL)
11101 for (i = 0; i < XVECLEN (pat, 0); i++)
11103 rtx sub = XVECEXP (pat, 0, i);
11104 if (GET_CODE (sub) == USE)
11106 sub = XEXP (sub, 0);
11107 if (GET_CODE (sub) == UNSPEC
11108 && XINT (sub, 1) == UNSPEC_TOC)
11117 create_TOC_reference (rtx symbol)
11119 return gen_rtx_PLUS (Pmode,
11120 gen_rtx_REG (Pmode, TOC_REGISTER),
11121 gen_rtx_CONST (Pmode,
11122 gen_rtx_MINUS (Pmode, symbol,
11123 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
11126 /* If _Unwind_* has been called from within the same module,
11127 toc register is not guaranteed to be saved to 40(1) on function
11128 entry. Save it there in that case. */
11131 rs6000_aix_emit_builtin_unwind_init (void)
11134 rtx stack_top = gen_reg_rtx (Pmode);
11135 rtx opcode_addr = gen_reg_rtx (Pmode);
11136 rtx opcode = gen_reg_rtx (SImode);
11137 rtx tocompare = gen_reg_rtx (SImode);
11138 rtx no_toc_save_needed = gen_label_rtx ();
11140 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
11141 emit_move_insn (stack_top, mem);
11143 mem = gen_rtx_MEM (Pmode,
11144 gen_rtx_PLUS (Pmode, stack_top,
11145 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
11146 emit_move_insn (opcode_addr, mem);
11147 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
11148 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
11149 : 0xE8410028, SImode));
11151 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
11152 SImode, NULL_RTX, NULL_RTX,
11153 no_toc_save_needed);
11155 mem = gen_rtx_MEM (Pmode,
11156 gen_rtx_PLUS (Pmode, stack_top,
11157 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
11158 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
11159 emit_label (no_toc_save_needed);
11162 /* This ties together stack memory (MEM with an alias set of
11163 rs6000_sr_alias_set) and the change to the stack pointer. */
11166 rs6000_emit_stack_tie (void)
11168 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
11170 set_mem_alias_set (mem, rs6000_sr_alias_set);
11171 emit_insn (gen_stack_tie (mem));
11174 /* Emit the correct code for allocating stack space, as insns.
11175 If COPY_R12, make sure a copy of the old frame is left in r12.
11176 The generated code may use hard register 0 as a temporary. */
11179 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
11182 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11183 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
11184 rtx todec = GEN_INT (-size);
11186 if (current_function_limit_stack)
11188 if (REG_P (stack_limit_rtx)
11189 && REGNO (stack_limit_rtx) > 1
11190 && REGNO (stack_limit_rtx) <= 31)
11192 emit_insn (TARGET_32BIT
11193 ? gen_addsi3 (tmp_reg,
11196 : gen_adddi3 (tmp_reg,
11200 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11203 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
11205 && DEFAULT_ABI == ABI_V4)
11207 rtx toload = gen_rtx_CONST (VOIDmode,
11208 gen_rtx_PLUS (Pmode,
11212 emit_insn (gen_elf_high (tmp_reg, toload));
11213 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
11214 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
11218 warning ("stack limit expression is not supported");
11221 if (copy_r12 || ! TARGET_UPDATE)
11222 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
11228 /* Need a note here so that try_split doesn't get confused. */
11229 if (get_last_insn() == NULL_RTX)
11230 emit_note (NOTE_INSN_DELETED);
11231 insn = emit_move_insn (tmp_reg, todec);
11232 try_split (PATTERN (insn), insn, 0);
11236 insn = emit_insn (TARGET_32BIT
11237 ? gen_movsi_update (stack_reg, stack_reg,
11239 : gen_movdi_update (stack_reg, stack_reg,
11240 todec, stack_reg));
11244 insn = emit_insn (TARGET_32BIT
11245 ? gen_addsi3 (stack_reg, stack_reg, todec)
11246 : gen_adddi3 (stack_reg, stack_reg, todec));
11247 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
11248 gen_rtx_REG (Pmode, 12));
11251 RTX_FRAME_RELATED_P (insn) = 1;
11253 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11254 gen_rtx_SET (VOIDmode, stack_reg,
11255 gen_rtx_PLUS (Pmode, stack_reg,
11260 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
11261 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
11262 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
11263 deduce these equivalences by itself so it wasn't necessary to hold
11264 its hand so much. */
11267 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
11268 rtx reg2, rtx rreg)
11272 /* copy_rtx will not make unique copies of registers, so we need to
11273 ensure we don't have unwanted sharing here. */
11275 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11278 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
11280 real = copy_rtx (PATTERN (insn));
11282 if (reg2 != NULL_RTX)
11283 real = replace_rtx (real, reg2, rreg);
11285 real = replace_rtx (real, reg,
11286 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
11287 STACK_POINTER_REGNUM),
11290 /* We expect that 'real' is either a SET or a PARALLEL containing
11291 SETs (and possibly other stuff). In a PARALLEL, all the SETs
11292 are important so they all have to be marked RTX_FRAME_RELATED_P. */
11294 if (GET_CODE (real) == SET)
11298 temp = simplify_rtx (SET_SRC (set));
11300 SET_SRC (set) = temp;
11301 temp = simplify_rtx (SET_DEST (set));
11303 SET_DEST (set) = temp;
11304 if (GET_CODE (SET_DEST (set)) == MEM)
11306 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11308 XEXP (SET_DEST (set), 0) = temp;
11311 else if (GET_CODE (real) == PARALLEL)
11314 for (i = 0; i < XVECLEN (real, 0); i++)
11315 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
11317 rtx set = XVECEXP (real, 0, i);
11319 temp = simplify_rtx (SET_SRC (set));
11321 SET_SRC (set) = temp;
11322 temp = simplify_rtx (SET_DEST (set));
11324 SET_DEST (set) = temp;
11325 if (GET_CODE (SET_DEST (set)) == MEM)
11327 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
11329 XEXP (SET_DEST (set), 0) = temp;
11331 RTX_FRAME_RELATED_P (set) = 1;
11338 real = spe_synthesize_frame_save (real);
11340 RTX_FRAME_RELATED_P (insn) = 1;
11341 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
11346 /* Given an SPE frame note, return a PARALLEL of SETs with the
11347 original note, plus a synthetic register save. */
11350 spe_synthesize_frame_save (rtx real)
11352 rtx synth, offset, reg, real2;
11354 if (GET_CODE (real) != SET
11355 || GET_MODE (SET_SRC (real)) != V2SImode)
11358 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
11359 frame related note. The parallel contains a set of the register
11360 being saved, and another set to a synthetic register (n+1200).
11361 This is so we can differentiate between 64-bit and 32-bit saves.
11362 Words cannot describe this nastiness. */
11364 if (GET_CODE (SET_DEST (real)) != MEM
11365 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
11366 || GET_CODE (SET_SRC (real)) != REG)
11370 (set (mem (plus (reg x) (const y)))
11373 (set (mem (plus (reg x) (const y+4)))
11377 real2 = copy_rtx (real);
11378 PUT_MODE (SET_DEST (real2), SImode);
11379 reg = SET_SRC (real2);
11380 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
11381 synth = copy_rtx (real2);
11383 if (BYTES_BIG_ENDIAN)
11385 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
11386 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
11389 reg = SET_SRC (synth);
11391 synth = replace_rtx (synth, reg,
11392 gen_rtx_REG (SImode, REGNO (reg) + 1200));
11394 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
11395 synth = replace_rtx (synth, offset,
11396 GEN_INT (INTVAL (offset)
11397 + (BYTES_BIG_ENDIAN ? 0 : 4)));
11399 RTX_FRAME_RELATED_P (synth) = 1;
11400 RTX_FRAME_RELATED_P (real2) = 1;
11401 if (BYTES_BIG_ENDIAN)
11402 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
11404 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
11409 /* Returns an insn that has a vrsave set operation with the
11410 appropriate CLOBBERs. */
11413 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
11416 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
11417 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
11420 = gen_rtx_SET (VOIDmode,
11422 gen_rtx_UNSPEC_VOLATILE (SImode,
11423 gen_rtvec (2, reg, vrsave),
11428 /* We need to clobber the registers in the mask so the scheduler
11429 does not move sets to VRSAVE before sets of AltiVec registers.
11431 However, if the function receives nonlocal gotos, reload will set
11432 all call saved registers live. We will end up with:
11434 (set (reg 999) (mem))
11435 (parallel [ (set (reg vrsave) (unspec blah))
11436 (clobber (reg 999))])
11438 The clobber will cause the store into reg 999 to be dead, and
11439 flow will attempt to delete an epilogue insn. In this case, we
11440 need an unspec use/set of the register. */
11442 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11443 if (info->vrsave_mask != 0 && ALTIVEC_REG_BIT (i) != 0)
11445 if (!epiloguep || call_used_regs [i])
11446 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
11447 gen_rtx_REG (V4SImode, i));
11450 rtx reg = gen_rtx_REG (V4SImode, i);
11453 = gen_rtx_SET (VOIDmode,
11455 gen_rtx_UNSPEC (V4SImode,
11456 gen_rtvec (1, reg), 27));
11460 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
11462 for (i = 0; i < nclobs; ++i)
11463 XVECEXP (insn, 0, i) = clobs[i];
11468 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
11469 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
11472 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
11473 unsigned int regno, int offset, HOST_WIDE_INT total_size)
11475 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
11476 rtx replacea, replaceb;
11478 int_rtx = GEN_INT (offset);
11480 /* Some cases that need register indexed addressing. */
11481 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
11483 && SPE_VECTOR_MODE (mode)
11484 && !SPE_CONST_OFFSET_OK (offset)))
11486 /* Whomever calls us must make sure r11 is available in the
11487 flow path of instructions in the prologue. */
11488 offset_rtx = gen_rtx_REG (Pmode, 11);
11489 emit_move_insn (offset_rtx, int_rtx);
11491 replacea = offset_rtx;
11492 replaceb = int_rtx;
11496 offset_rtx = int_rtx;
11497 replacea = NULL_RTX;
11498 replaceb = NULL_RTX;
11501 reg = gen_rtx_REG (mode, regno);
11502 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
11503 mem = gen_rtx_MEM (mode, addr);
11504 set_mem_alias_set (mem, rs6000_sr_alias_set);
11506 insn = emit_move_insn (mem, reg);
11508 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
11511 /* Emit an offset memory reference suitable for a frame store, while
11512 converting to a valid addressing mode. */
11515 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
11517 rtx int_rtx, offset_rtx;
11519 int_rtx = GEN_INT (offset);
11521 if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
11523 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
11524 emit_move_insn (offset_rtx, int_rtx);
11527 offset_rtx = int_rtx;
11529 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
11532 /* Emit function prologue as insns. */
11535 rs6000_emit_prologue (void)
11537 rs6000_stack_t *info = rs6000_stack_info ();
11538 enum machine_mode reg_mode = Pmode;
11539 int reg_size = UNITS_PER_WORD;
11540 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
11541 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
11542 rtx frame_reg_rtx = sp_reg_rtx;
11543 rtx cr_save_rtx = NULL_RTX;
11545 int saving_FPRs_inline;
11546 int using_store_multiple;
11547 HOST_WIDE_INT sp_offset = 0;
11549 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
11551 reg_mode = V2SImode;
11555 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
11556 && (!TARGET_SPE_ABI
11557 || info->spe_64bit_regs_used == 0)
11558 && info->first_gp_reg_save < 31);
11559 saving_FPRs_inline = (info->first_fp_reg_save == 64
11560 || FP_SAVE_INLINE (info->first_fp_reg_save)
11561 || current_function_calls_eh_return
11562 || cfun->machine->ra_need_lr);
11564 /* For V.4, update stack before we do any saving and set back pointer. */
11566 && (DEFAULT_ABI == ABI_V4
11567 || current_function_calls_eh_return))
11569 if (info->total_size < 32767)
11570 sp_offset = info->total_size;
11572 frame_reg_rtx = frame_ptr_rtx;
11573 rs6000_emit_allocate_stack (info->total_size,
11574 (frame_reg_rtx != sp_reg_rtx
11575 && (info->cr_save_p
11577 || info->first_fp_reg_save < 64
11578 || info->first_gp_reg_save < 32
11580 if (frame_reg_rtx != sp_reg_rtx)
11581 rs6000_emit_stack_tie ();
11584 /* Save AltiVec registers if needed. */
11585 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
11589 /* There should be a non inline version of this, for when we
11590 are saving lots of vector registers. */
11591 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
11592 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
11594 rtx areg, savereg, mem;
11597 offset = info->altivec_save_offset + sp_offset
11598 + 16 * (i - info->first_altivec_reg_save);
11600 savereg = gen_rtx_REG (V4SImode, i);
11602 areg = gen_rtx_REG (Pmode, 0);
11603 emit_move_insn (areg, GEN_INT (offset));
11605 /* AltiVec addressing mode is [reg+reg]. */
11606 mem = gen_rtx_MEM (V4SImode,
11607 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
11609 set_mem_alias_set (mem, rs6000_sr_alias_set);
11611 insn = emit_move_insn (mem, savereg);
11613 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11614 areg, GEN_INT (offset));
11618 /* VRSAVE is a bit vector representing which AltiVec registers
11619 are used. The OS uses this to determine which vector
11620 registers to save on a context switch. We need to save
11621 VRSAVE on the stack frame, add whatever AltiVec registers we
11622 used in this function, and do the corresponding magic in the
11625 if (TARGET_ALTIVEC && info->vrsave_mask != 0)
11627 rtx reg, mem, vrsave;
11630 /* Get VRSAVE onto a GPR. */
11631 reg = gen_rtx_REG (SImode, 12);
11632 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
11634 emit_insn (gen_get_vrsave_internal (reg));
11636 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
11639 offset = info->vrsave_save_offset + sp_offset;
11641 = gen_rtx_MEM (SImode,
11642 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
11643 set_mem_alias_set (mem, rs6000_sr_alias_set);
11644 insn = emit_move_insn (mem, reg);
11646 /* Include the registers in the mask. */
11647 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
11649 insn = emit_insn (generate_set_vrsave (reg, info, 0));
11652 /* If we use the link register, get it into r0. */
11653 if (info->lr_save_p)
11654 emit_move_insn (gen_rtx_REG (Pmode, 0),
11655 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
11657 /* If we need to save CR, put it into r12. */
11658 if (info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
11660 cr_save_rtx = gen_rtx_REG (SImode, 12);
11661 emit_insn (gen_movesi_from_cr (cr_save_rtx));
11664 /* Do any required saving of fpr's. If only one or two to save, do
11665 it ourselves. Otherwise, call function. */
11666 if (saving_FPRs_inline)
11669 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
11670 if ((regs_ever_live[info->first_fp_reg_save+i]
11671 && ! call_used_regs[info->first_fp_reg_save+i]))
11672 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
11673 info->first_fp_reg_save + i,
11674 info->fp_save_offset + sp_offset + 8 * i,
11677 else if (info->first_fp_reg_save != 64)
11681 const char *alloc_rname;
11683 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
11685 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
11686 gen_rtx_REG (Pmode,
11687 LINK_REGISTER_REGNUM));
11688 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
11689 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
11690 alloc_rname = ggc_strdup (rname);
11691 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
11692 gen_rtx_SYMBOL_REF (Pmode,
11694 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
11696 rtx addr, reg, mem;
11697 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
11698 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11699 GEN_INT (info->fp_save_offset
11700 + sp_offset + 8*i));
11701 mem = gen_rtx_MEM (DFmode, addr);
11702 set_mem_alias_set (mem, rs6000_sr_alias_set);
11704 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
11706 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
11707 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11708 NULL_RTX, NULL_RTX);
11711 /* Save GPRs. This is done as a PARALLEL if we are using
11712 the store-multiple instructions. */
11713 if (using_store_multiple)
11717 p = rtvec_alloc (32 - info->first_gp_reg_save);
11718 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
11720 rtx addr, reg, mem;
11721 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
11722 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11723 GEN_INT (info->gp_save_offset
11726 mem = gen_rtx_MEM (reg_mode, addr);
11727 set_mem_alias_set (mem, rs6000_sr_alias_set);
11729 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
11731 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
11732 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11733 NULL_RTX, NULL_RTX);
11738 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
11739 if ((regs_ever_live[info->first_gp_reg_save+i]
11740 && ! call_used_regs[info->first_gp_reg_save+i])
11741 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
11742 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
11743 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
11745 rtx addr, reg, mem;
11746 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
11748 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
11750 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
11753 if (!SPE_CONST_OFFSET_OK (offset))
11755 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
11756 emit_move_insn (b, GEN_INT (offset));
11759 b = GEN_INT (offset);
11761 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
11762 mem = gen_rtx_MEM (V2SImode, addr);
11763 set_mem_alias_set (mem, rs6000_sr_alias_set);
11764 insn = emit_move_insn (mem, reg);
11766 if (GET_CODE (b) == CONST_INT)
11767 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11768 NULL_RTX, NULL_RTX);
11770 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11771 b, GEN_INT (offset));
11775 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11776 GEN_INT (info->gp_save_offset
11779 mem = gen_rtx_MEM (reg_mode, addr);
11780 set_mem_alias_set (mem, rs6000_sr_alias_set);
11782 insn = emit_move_insn (mem, reg);
11783 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11784 NULL_RTX, NULL_RTX);
11789 /* ??? There's no need to emit actual instructions here, but it's the
11790 easiest way to get the frame unwind information emitted. */
11791 if (current_function_calls_eh_return)
11793 unsigned int i, regno;
11795 /* In AIX ABI we need to pretend we save r2 here. */
11798 rtx addr, reg, mem;
11800 reg = gen_rtx_REG (reg_mode, 2);
11801 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11802 GEN_INT (sp_offset + 5 * reg_size));
11803 mem = gen_rtx_MEM (reg_mode, addr);
11804 set_mem_alias_set (mem, rs6000_sr_alias_set);
11806 insn = emit_move_insn (mem, reg);
11807 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11808 NULL_RTX, NULL_RTX);
11809 PATTERN (insn) = gen_blockage ();
11814 regno = EH_RETURN_DATA_REGNO (i);
11815 if (regno == INVALID_REGNUM)
11818 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
11819 info->ehrd_offset + sp_offset
11820 + reg_size * (int) i,
11825 /* Save lr if we used it. */
11826 if (info->lr_save_p)
11828 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11829 GEN_INT (info->lr_save_offset + sp_offset));
11830 rtx reg = gen_rtx_REG (Pmode, 0);
11831 rtx mem = gen_rtx_MEM (Pmode, addr);
11832 /* This should not be of rs6000_sr_alias_set, because of
11833 __builtin_return_address. */
11835 insn = emit_move_insn (mem, reg);
11836 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11837 reg, gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
11840 /* Save CR if we use any that must be preserved. */
11841 if (info->cr_save_p)
11843 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
11844 GEN_INT (info->cr_save_offset + sp_offset));
11845 rtx mem = gen_rtx_MEM (SImode, addr);
11847 set_mem_alias_set (mem, rs6000_sr_alias_set);
11849 /* If r12 was used to hold the original sp, copy cr into r0 now
11851 if (REGNO (frame_reg_rtx) == 12)
11853 cr_save_rtx = gen_rtx_REG (SImode, 0);
11854 emit_insn (gen_movesi_from_cr (cr_save_rtx));
11856 insn = emit_move_insn (mem, cr_save_rtx);
11858 /* Now, there's no way that dwarf2out_frame_debug_expr is going
11859 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
11860 But that's OK. All we have to do is specify that _one_ condition
11861 code register is saved in this stack slot. The thrower's epilogue
11862 will then restore all the call-saved registers.
11863 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
11864 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
11865 cr_save_rtx, gen_rtx_REG (SImode, CR2_REGNO));
11868 /* Update stack and set back pointer unless this is V.4,
11869 for which it was done previously. */
11871 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
11872 rs6000_emit_allocate_stack (info->total_size, FALSE);
11874 /* Set frame pointer, if needed. */
11875 if (frame_pointer_needed)
11877 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
11879 RTX_FRAME_RELATED_P (insn) = 1;
11882 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
11883 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
11884 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
11885 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
11887 /* If emit_load_toc_table will use the link register, we need to save
11888 it. We use R12 for this purpose because emit_load_toc_table
11889 can use register 0. This allows us to use a plain 'blr' to return
11890 from the procedure more often. */
11891 int save_LR_around_toc_setup = (TARGET_ELF
11892 && DEFAULT_ABI != ABI_AIX
11894 && ! info->lr_save_p
11895 && EXIT_BLOCK_PTR->pred != NULL);
11896 if (save_LR_around_toc_setup)
11898 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11899 rs6000_maybe_dead (emit_move_insn (frame_ptr_rtx, lr));
11900 rs6000_emit_load_toc_table (TRUE);
11901 rs6000_maybe_dead (emit_move_insn (lr, frame_ptr_rtx));
11904 rs6000_emit_load_toc_table (TRUE);
11908 if (DEFAULT_ABI == ABI_DARWIN
11909 && flag_pic && current_function_uses_pic_offset_table)
11911 rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11912 const char *picbase = machopic_function_base_name ();
11913 rtx src = gen_rtx_SYMBOL_REF (Pmode, picbase);
11915 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest, src)));
11917 rs6000_maybe_dead (
11918 emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM),
11919 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)));
11924 /* Write function prologue. */
11927 rs6000_output_function_prologue (FILE *file,
11928 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11930 rs6000_stack_t *info = rs6000_stack_info ();
11932 if (TARGET_DEBUG_STACK)
11933 debug_stack_info (info);
11935 /* Write .extern for any function we will call to save and restore
11937 if (info->first_fp_reg_save < 64
11938 && !FP_SAVE_INLINE (info->first_fp_reg_save))
11939 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
11940 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
11941 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
11942 RESTORE_FP_SUFFIX);
11944 /* Write .extern for AIX common mode routines, if needed. */
11945 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
11947 fputs ("\t.extern __mulh\n", file);
11948 fputs ("\t.extern __mull\n", file);
11949 fputs ("\t.extern __divss\n", file);
11950 fputs ("\t.extern __divus\n", file);
11951 fputs ("\t.extern __quoss\n", file);
11952 fputs ("\t.extern __quous\n", file);
11953 common_mode_defined = 1;
11956 if (! HAVE_prologue)
11960 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
11961 the "toplevel" insn chain. */
11962 emit_note (NOTE_INSN_DELETED);
11963 rs6000_emit_prologue ();
11964 emit_note (NOTE_INSN_DELETED);
11966 /* Expand INSN_ADDRESSES so final() doesn't crash. */
11970 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
11972 INSN_ADDRESSES_NEW (insn, addr);
11977 if (TARGET_DEBUG_STACK)
11978 debug_rtx_list (get_insns (), 100);
11979 final (get_insns (), file, FALSE, FALSE);
11983 rs6000_pic_labelno++;
11986 /* Emit function epilogue as insns.
11988 At present, dwarf2out_frame_debug_expr doesn't understand
11989 register restores, so we don't bother setting RTX_FRAME_RELATED_P
11990 anywhere in the epilogue. Most of the insns below would in any case
11991 need special notes to explain where r11 is in relation to the stack. */
11994 rs6000_emit_epilogue (int sibcall)
11996 rs6000_stack_t *info;
11997 int restoring_FPRs_inline;
11998 int using_load_multiple;
11999 int using_mfcr_multiple;
12000 int use_backchain_to_restore_sp;
12002 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
12003 rtx frame_reg_rtx = sp_reg_rtx;
12004 enum machine_mode reg_mode = Pmode;
12005 int reg_size = UNITS_PER_WORD;
12008 info = rs6000_stack_info ();
12010 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12012 reg_mode = V2SImode;
12016 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12017 && (!TARGET_SPE_ABI
12018 || info->spe_64bit_regs_used == 0)
12019 && info->first_gp_reg_save < 31);
12020 restoring_FPRs_inline = (sibcall
12021 || current_function_calls_eh_return
12022 || info->first_fp_reg_save == 64
12023 || FP_SAVE_INLINE (info->first_fp_reg_save));
12024 use_backchain_to_restore_sp = (frame_pointer_needed
12025 || current_function_calls_alloca
12026 || info->total_size > 32767);
12027 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
12028 || rs6000_cpu == PROCESSOR_PPC603
12029 || rs6000_cpu == PROCESSOR_PPC750
12032 /* If we have a frame pointer, a call to alloca, or a large stack
12033 frame, restore the old stack pointer using the backchain. Otherwise,
12034 we know what size to update it with. */
12035 if (use_backchain_to_restore_sp)
12037 /* Under V.4, don't reset the stack pointer until after we're done
12038 loading the saved registers. */
12039 if (DEFAULT_ABI == ABI_V4)
12040 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
12042 emit_move_insn (frame_reg_rtx,
12043 gen_rtx_MEM (Pmode, sp_reg_rtx));
12046 else if (info->push_p)
12048 if (DEFAULT_ABI == ABI_V4
12049 || current_function_calls_eh_return)
12050 sp_offset = info->total_size;
12053 emit_insn (TARGET_32BIT
12054 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12055 GEN_INT (info->total_size))
12056 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12057 GEN_INT (info->total_size)));
12061 /* Restore AltiVec registers if needed. */
12062 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
12066 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12067 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12069 rtx addr, areg, mem;
12071 areg = gen_rtx_REG (Pmode, 0);
12073 (areg, GEN_INT (info->altivec_save_offset
12075 + 16 * (i - info->first_altivec_reg_save)));
12077 /* AltiVec addressing mode is [reg+reg]. */
12078 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
12079 mem = gen_rtx_MEM (V4SImode, addr);
12080 set_mem_alias_set (mem, rs6000_sr_alias_set);
12082 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
12086 /* Restore VRSAVE if needed. */
12087 if (TARGET_ALTIVEC_ABI && info->vrsave_mask != 0)
12089 rtx addr, mem, reg;
12091 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12092 GEN_INT (info->vrsave_save_offset + sp_offset));
12093 mem = gen_rtx_MEM (SImode, addr);
12094 set_mem_alias_set (mem, rs6000_sr_alias_set);
12095 reg = gen_rtx_REG (SImode, 12);
12096 emit_move_insn (reg, mem);
12098 emit_insn (generate_set_vrsave (reg, info, 1));
12101 /* Get the old lr if we saved it. */
12102 if (info->lr_save_p)
12104 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
12105 info->lr_save_offset + sp_offset);
12107 set_mem_alias_set (mem, rs6000_sr_alias_set);
12109 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
12112 /* Get the old cr if we saved it. */
12113 if (info->cr_save_p)
12115 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12116 GEN_INT (info->cr_save_offset + sp_offset));
12117 rtx mem = gen_rtx_MEM (SImode, addr);
12119 set_mem_alias_set (mem, rs6000_sr_alias_set);
12121 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
12124 /* Set LR here to try to overlap restores below. */
12125 if (info->lr_save_p)
12126 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
12127 gen_rtx_REG (Pmode, 0));
12129 /* Load exception handler data registers, if needed. */
12130 if (current_function_calls_eh_return)
12132 unsigned int i, regno;
12136 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12137 GEN_INT (sp_offset + 5 * reg_size));
12138 rtx mem = gen_rtx_MEM (reg_mode, addr);
12140 set_mem_alias_set (mem, rs6000_sr_alias_set);
12142 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
12149 regno = EH_RETURN_DATA_REGNO (i);
12150 if (regno == INVALID_REGNUM)
12153 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
12154 info->ehrd_offset + sp_offset
12155 + reg_size * (int) i);
12156 set_mem_alias_set (mem, rs6000_sr_alias_set);
12158 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
12162 /* Restore GPRs. This is done as a PARALLEL if we are using
12163 the load-multiple instructions. */
12164 if (using_load_multiple)
12167 p = rtvec_alloc (32 - info->first_gp_reg_save);
12168 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12170 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12171 GEN_INT (info->gp_save_offset
12174 rtx mem = gen_rtx_MEM (reg_mode, addr);
12176 set_mem_alias_set (mem, rs6000_sr_alias_set);
12179 gen_rtx_SET (VOIDmode,
12180 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
12183 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12186 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12187 if ((regs_ever_live[info->first_gp_reg_save+i]
12188 && ! call_used_regs[info->first_gp_reg_save+i])
12189 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12190 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12191 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12193 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12194 GEN_INT (info->gp_save_offset
12197 rtx mem = gen_rtx_MEM (reg_mode, addr);
12199 /* Restore 64-bit quantities for SPE. */
12200 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12202 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12205 if (!SPE_CONST_OFFSET_OK (offset))
12207 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12208 emit_move_insn (b, GEN_INT (offset));
12211 b = GEN_INT (offset);
12213 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12214 mem = gen_rtx_MEM (V2SImode, addr);
12217 set_mem_alias_set (mem, rs6000_sr_alias_set);
12219 emit_move_insn (gen_rtx_REG (reg_mode,
12220 info->first_gp_reg_save + i), mem);
12223 /* Restore fpr's if we need to do it without calling a function. */
12224 if (restoring_FPRs_inline)
12225 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12226 if ((regs_ever_live[info->first_fp_reg_save+i]
12227 && ! call_used_regs[info->first_fp_reg_save+i]))
12230 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12231 GEN_INT (info->fp_save_offset
12234 mem = gen_rtx_MEM (DFmode, addr);
12235 set_mem_alias_set (mem, rs6000_sr_alias_set);
12237 emit_move_insn (gen_rtx_REG (DFmode,
12238 info->first_fp_reg_save + i),
12242 /* If we saved cr, restore it here. Just those that were used. */
12243 if (info->cr_save_p)
12245 rtx r12_rtx = gen_rtx_REG (SImode, 12);
12248 if (using_mfcr_multiple)
12250 for (i = 0; i < 8; i++)
12251 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12257 if (using_mfcr_multiple && count > 1)
12262 p = rtvec_alloc (count);
12265 for (i = 0; i < 8; i++)
12266 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12268 rtvec r = rtvec_alloc (2);
12269 RTVEC_ELT (r, 0) = r12_rtx;
12270 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
12271 RTVEC_ELT (p, ndx) =
12272 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
12273 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
12276 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12281 for (i = 0; i < 8; i++)
12282 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
12284 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
12290 /* If this is V.4, unwind the stack pointer after all of the loads
12291 have been done. We need to emit a block here so that sched
12292 doesn't decide to move the sp change before the register restores
12293 (which may not have any obvious dependency on the stack). This
12294 doesn't hurt performance, because there is no scheduling that can
12295 be done after this point. */
12296 if (DEFAULT_ABI == ABI_V4
12297 || current_function_calls_eh_return)
12299 if (frame_reg_rtx != sp_reg_rtx)
12300 rs6000_emit_stack_tie ();
12302 if (use_backchain_to_restore_sp)
12304 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
12306 else if (sp_offset != 0)
12308 emit_insn (TARGET_32BIT
12309 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
12310 GEN_INT (sp_offset))
12311 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
12312 GEN_INT (sp_offset)));
12316 if (current_function_calls_eh_return)
12318 rtx sa = EH_RETURN_STACKADJ_RTX;
12319 emit_insn (TARGET_32BIT
12320 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
12321 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
12327 if (! restoring_FPRs_inline)
12328 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
12330 p = rtvec_alloc (2);
12332 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
12333 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12334 gen_rtx_REG (Pmode,
12335 LINK_REGISTER_REGNUM));
12337 /* If we have to restore more than two FP registers, branch to the
12338 restore function. It will return to our caller. */
12339 if (! restoring_FPRs_inline)
12343 const char *alloc_rname;
12345 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
12346 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
12347 alloc_rname = ggc_strdup (rname);
12348 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
12349 gen_rtx_SYMBOL_REF (Pmode,
12352 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12355 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
12356 GEN_INT (info->fp_save_offset + 8*i));
12357 mem = gen_rtx_MEM (DFmode, addr);
12358 set_mem_alias_set (mem, rs6000_sr_alias_set);
12360 RTVEC_ELT (p, i+3) =
12361 gen_rtx_SET (VOIDmode,
12362 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
12367 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
12371 /* Write function epilogue. */
12374 rs6000_output_function_epilogue (FILE *file,
12375 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
12377 rs6000_stack_t *info = rs6000_stack_info ();
12379 if (! HAVE_epilogue)
12381 rtx insn = get_last_insn ();
12382 /* If the last insn was a BARRIER, we don't have to write anything except
12383 the trace table. */
12384 if (GET_CODE (insn) == NOTE)
12385 insn = prev_nonnote_insn (insn);
12386 if (insn == 0 || GET_CODE (insn) != BARRIER)
12388 /* This is slightly ugly, but at least we don't have two
12389 copies of the epilogue-emitting code. */
12392 /* A NOTE_INSN_DELETED is supposed to be at the start
12393 and end of the "toplevel" insn chain. */
12394 emit_note (NOTE_INSN_DELETED);
12395 rs6000_emit_epilogue (FALSE);
12396 emit_note (NOTE_INSN_DELETED);
12398 /* Expand INSN_ADDRESSES so final() doesn't crash. */
12402 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
12404 INSN_ADDRESSES_NEW (insn, addr);
12409 if (TARGET_DEBUG_STACK)
12410 debug_rtx_list (get_insns (), 100);
12411 final (get_insns (), file, FALSE, FALSE);
12417 macho_branch_islands ();
12418 /* Mach-O doesn't support labels at the end of objects, so if
12419 it looks like we might want one, insert a NOP. */
12421 rtx insn = get_last_insn ();
12424 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
12425 insn = PREV_INSN (insn);
12429 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
12430 fputs ("\tnop\n", file);
12434 /* Output a traceback table here. See /usr/include/sys/debug.h for info
12437 We don't output a traceback table if -finhibit-size-directive was
12438 used. The documentation for -finhibit-size-directive reads
12439 ``don't output a @code{.size} assembler directive, or anything
12440 else that would cause trouble if the function is split in the
12441 middle, and the two halves are placed at locations far apart in
12442 memory.'' The traceback table has this property, since it
12443 includes the offset from the start of the function to the
12444 traceback table itself.
12446 System V.4 Powerpc's (and the embedded ABI derived from it) use a
12447 different traceback table. */
12448 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
12449 && rs6000_traceback != traceback_none)
12451 const char *fname = NULL;
12452 const char *language_string = lang_hooks.name;
12453 int fixed_parms = 0, float_parms = 0, parm_info = 0;
12455 int optional_tbtab;
12457 if (rs6000_traceback == traceback_full)
12458 optional_tbtab = 1;
12459 else if (rs6000_traceback == traceback_part)
12460 optional_tbtab = 0;
12462 optional_tbtab = !optimize_size && !TARGET_ELF;
12464 if (optional_tbtab)
12466 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
12467 while (*fname == '.') /* V.4 encodes . in the name */
12470 /* Need label immediately before tbtab, so we can compute
12471 its offset from the function start. */
12472 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
12473 ASM_OUTPUT_LABEL (file, fname);
12476 /* The .tbtab pseudo-op can only be used for the first eight
12477 expressions, since it can't handle the possibly variable
12478 length fields that follow. However, if you omit the optional
12479 fields, the assembler outputs zeros for all optional fields
12480 anyways, giving each variable length field is minimum length
12481 (as defined in sys/debug.h). Thus we can not use the .tbtab
12482 pseudo-op at all. */
12484 /* An all-zero word flags the start of the tbtab, for debuggers
12485 that have to find it by searching forward from the entry
12486 point or from the current pc. */
12487 fputs ("\t.long 0\n", file);
12489 /* Tbtab format type. Use format type 0. */
12490 fputs ("\t.byte 0,", file);
12492 /* Language type. Unfortunately, there doesn't seem to be any
12493 official way to get this info, so we use language_string. C
12494 is 0. C++ is 9. No number defined for Obj-C, so use the
12495 value for C for now. There is no official value for Java,
12496 although IBM appears to be using 13. */
12497 if (! strcmp (language_string, "GNU C")
12498 || ! strcmp (language_string, "GNU Objective-C"))
12500 else if (! strcmp (language_string, "GNU F77"))
12502 else if (! strcmp (language_string, "GNU Ada"))
12504 else if (! strcmp (language_string, "GNU Pascal"))
12506 else if (! strcmp (language_string, "GNU C++"))
12508 else if (! strcmp (language_string, "GNU Java"))
12512 fprintf (file, "%d,", i);
12514 /* 8 single bit fields: global linkage (not set for C extern linkage,
12515 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
12516 from start of procedure stored in tbtab, internal function, function
12517 has controlled storage, function has no toc, function uses fp,
12518 function logs/aborts fp operations. */
12519 /* Assume that fp operations are used if any fp reg must be saved. */
12520 fprintf (file, "%d,",
12521 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
12523 /* 6 bitfields: function is interrupt handler, name present in
12524 proc table, function calls alloca, on condition directives
12525 (controls stack walks, 3 bits), saves condition reg, saves
12527 /* The `function calls alloca' bit seems to be set whenever reg 31 is
12528 set up as a frame pointer, even when there is no alloca call. */
12529 fprintf (file, "%d,",
12530 ((optional_tbtab << 6)
12531 | ((optional_tbtab & frame_pointer_needed) << 5)
12532 | (info->cr_save_p << 1)
12533 | (info->lr_save_p)));
12535 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
12537 fprintf (file, "%d,",
12538 (info->push_p << 7) | (64 - info->first_fp_reg_save));
12540 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
12541 fprintf (file, "%d,", (32 - first_reg_to_save ()));
12543 if (optional_tbtab)
12545 /* Compute the parameter info from the function decl argument
12548 int next_parm_info_bit = 31;
12550 for (decl = DECL_ARGUMENTS (current_function_decl);
12551 decl; decl = TREE_CHAIN (decl))
12553 rtx parameter = DECL_INCOMING_RTL (decl);
12554 enum machine_mode mode = GET_MODE (parameter);
12556 if (GET_CODE (parameter) == REG)
12558 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
12564 if (mode == SFmode)
12566 else if (mode == DFmode || mode == TFmode)
12571 /* If only one bit will fit, don't or in this entry. */
12572 if (next_parm_info_bit > 0)
12573 parm_info |= (bits << (next_parm_info_bit - 1));
12574 next_parm_info_bit -= 2;
12578 fixed_parms += ((GET_MODE_SIZE (mode)
12579 + (UNITS_PER_WORD - 1))
12581 next_parm_info_bit -= 1;
12587 /* Number of fixed point parameters. */
12588 /* This is actually the number of words of fixed point parameters; thus
12589 an 8 byte struct counts as 2; and thus the maximum value is 8. */
12590 fprintf (file, "%d,", fixed_parms);
12592 /* 2 bitfields: number of floating point parameters (7 bits), parameters
12594 /* This is actually the number of fp registers that hold parameters;
12595 and thus the maximum value is 13. */
12596 /* Set parameters on stack bit if parameters are not in their original
12597 registers, regardless of whether they are on the stack? Xlc
12598 seems to set the bit when not optimizing. */
12599 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
12601 if (! optional_tbtab)
12604 /* Optional fields follow. Some are variable length. */
12606 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
12607 11 double float. */
12608 /* There is an entry for each parameter in a register, in the order that
12609 they occur in the parameter list. Any intervening arguments on the
12610 stack are ignored. If the list overflows a long (max possible length
12611 34 bits) then completely leave off all elements that don't fit. */
12612 /* Only emit this long if there was at least one parameter. */
12613 if (fixed_parms || float_parms)
12614 fprintf (file, "\t.long %d\n", parm_info);
12616 /* Offset from start of code to tb table. */
12617 fputs ("\t.long ", file);
12618 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
12620 RS6000_OUTPUT_BASENAME (file, fname);
12622 assemble_name (file, fname);
12624 fputs ("-.", file);
12626 RS6000_OUTPUT_BASENAME (file, fname);
12628 assemble_name (file, fname);
12632 /* Interrupt handler mask. */
12633 /* Omit this long, since we never set the interrupt handler bit
12636 /* Number of CTL (controlled storage) anchors. */
12637 /* Omit this long, since the has_ctl bit is never set above. */
12639 /* Displacement into stack of each CTL anchor. */
12640 /* Omit this list of longs, because there are no CTL anchors. */
12642 /* Length of function name. */
12645 fprintf (file, "\t.short %d\n", (int) strlen (fname));
12647 /* Function name. */
12648 assemble_string (fname, strlen (fname));
12650 /* Register for alloca automatic storage; this is always reg 31.
12651 Only emit this if the alloca bit was set above. */
12652 if (frame_pointer_needed)
12653 fputs ("\t.byte 31\n", file);
12655 fputs ("\t.align 2\n", file);
12659 /* A C compound statement that outputs the assembler code for a thunk
12660 function, used to implement C++ virtual function calls with
12661 multiple inheritance. The thunk acts as a wrapper around a virtual
12662 function, adjusting the implicit object parameter before handing
12663 control off to the real function.
12665 First, emit code to add the integer DELTA to the location that
12666 contains the incoming first argument. Assume that this argument
12667 contains a pointer, and is the one used to pass the `this' pointer
12668 in C++. This is the incoming argument *before* the function
12669 prologue, e.g. `%o0' on a sparc. The addition must preserve the
12670 values of all other incoming arguments.
12672 After the addition, emit code to jump to FUNCTION, which is a
12673 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
12674 not touch the return address. Hence returning from FUNCTION will
12675 return to whoever called the current `thunk'.
12677 The effect must be as if FUNCTION had been called directly with the
12678 adjusted first argument. This macro is responsible for emitting
12679 all of the code for a thunk function; output_function_prologue()
12680 and output_function_epilogue() are not invoked.
12682 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
12683 been extracted from it.) It might possibly be useful on some
12684 targets, but probably not.
12686 If you do not define this macro, the target-independent code in the
12687 C++ frontend will generate a less efficient heavyweight thunk that
12688 calls FUNCTION instead of jumping to it. The generic approach does
12689 not support varargs. */
12692 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
12693 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
12696 rtx this, insn, funexp;
12698 reload_completed = 1;
12699 epilogue_completed = 1;
12700 no_new_pseudos = 1;
12702 /* Mark the end of the (empty) prologue. */
12703 emit_note (NOTE_INSN_PROLOGUE_END);
12705 /* Find the "this" pointer. If the function returns a structure,
12706 the structure return pointer is in r3. */
12707 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
12708 this = gen_rtx_REG (Pmode, 4);
12710 this = gen_rtx_REG (Pmode, 3);
12712 /* Apply the constant offset, if required. */
12715 rtx delta_rtx = GEN_INT (delta);
12716 emit_insn (TARGET_32BIT
12717 ? gen_addsi3 (this, this, delta_rtx)
12718 : gen_adddi3 (this, this, delta_rtx));
12721 /* Apply the offset from the vtable, if required. */
12724 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
12725 rtx tmp = gen_rtx_REG (Pmode, 12);
12727 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
12728 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
12730 emit_insn (TARGET_32BIT
12731 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
12732 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
12733 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
12737 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
12739 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
12741 emit_insn (TARGET_32BIT
12742 ? gen_addsi3 (this, this, tmp)
12743 : gen_adddi3 (this, this, tmp));
12746 /* Generate a tail call to the target function. */
12747 if (!TREE_USED (function))
12749 assemble_external (function);
12750 TREE_USED (function) = 1;
12752 funexp = XEXP (DECL_RTL (function), 0);
12753 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
12756 if (MACHOPIC_INDIRECT)
12757 funexp = machopic_indirect_call_target (funexp);
12760 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
12761 generate sibcall RTL explicitly to avoid constraint abort. */
12762 insn = emit_call_insn (
12763 gen_rtx_PARALLEL (VOIDmode,
12765 gen_rtx_CALL (VOIDmode,
12766 funexp, const0_rtx),
12767 gen_rtx_USE (VOIDmode, const0_rtx),
12768 gen_rtx_USE (VOIDmode,
12769 gen_rtx_REG (SImode,
12770 LINK_REGISTER_REGNUM)),
12771 gen_rtx_RETURN (VOIDmode))));
12772 SIBLING_CALL_P (insn) = 1;
12775 /* Run just enough of rest_of_compilation to get the insns emitted.
12776 There's not really enough bulk here to make other passes such as
12777 instruction scheduling worth while. Note that use_thunk calls
12778 assemble_start_function and assemble_end_function. */
12779 insn = get_insns ();
12780 insn_locators_initialize ();
12781 shorten_branches (insn);
12782 final_start_function (insn, file, 1);
12783 final (insn, file, 1, 0);
12784 final_end_function ();
12786 reload_completed = 0;
12787 epilogue_completed = 0;
12788 no_new_pseudos = 0;
12791 /* A quick summary of the various types of 'constant-pool tables'
12794 Target Flags Name One table per
12795 AIX (none) AIX TOC object file
12796 AIX -mfull-toc AIX TOC object file
12797 AIX -mminimal-toc AIX minimal TOC translation unit
12798 SVR4/EABI (none) SVR4 SDATA object file
12799 SVR4/EABI -fpic SVR4 pic object file
12800 SVR4/EABI -fPIC SVR4 PIC translation unit
12801 SVR4/EABI -mrelocatable EABI TOC function
12802 SVR4/EABI -maix AIX TOC object file
12803 SVR4/EABI -maix -mminimal-toc
12804 AIX minimal TOC translation unit
12806 Name Reg. Set by entries contains:
12807 made by addrs? fp? sum?
12809 AIX TOC 2 crt0 as Y option option
12810 AIX minimal TOC 30 prolog gcc Y Y option
12811 SVR4 SDATA 13 crt0 gcc N Y N
12812 SVR4 pic 30 prolog ld Y not yet N
12813 SVR4 PIC 30 prolog gcc Y option option
12814 EABI TOC 30 prolog gcc Y option option
12818 /* Hash functions for the hash table. */
12821 rs6000_hash_constant (rtx k)
12823 enum rtx_code code = GET_CODE (k);
12824 enum machine_mode mode = GET_MODE (k);
12825 unsigned result = (code << 3) ^ mode;
12826 const char *format;
12829 format = GET_RTX_FORMAT (code);
12830 flen = strlen (format);
12836 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
12839 if (mode != VOIDmode)
12840 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
12852 for (; fidx < flen; fidx++)
12853 switch (format[fidx])
12858 const char *str = XSTR (k, fidx);
12859 len = strlen (str);
12860 result = result * 613 + len;
12861 for (i = 0; i < len; i++)
12862 result = result * 613 + (unsigned) str[i];
12867 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
12871 result = result * 613 + (unsigned) XINT (k, fidx);
12874 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
12875 result = result * 613 + (unsigned) XWINT (k, fidx);
12879 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
12880 result = result * 613 + (unsigned) (XWINT (k, fidx)
12894 toc_hash_function (const void *hash_entry)
12896 const struct toc_hash_struct *thc =
12897 (const struct toc_hash_struct *) hash_entry;
12898 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
12901 /* Compare H1 and H2 for equivalence. */
12904 toc_hash_eq (const void *h1, const void *h2)
12906 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
12907 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
12909 if (((const struct toc_hash_struct *) h1)->key_mode
12910 != ((const struct toc_hash_struct *) h2)->key_mode)
12913 return rtx_equal_p (r1, r2);
12916 /* These are the names given by the C++ front-end to vtables, and
12917 vtable-like objects. Ideally, this logic should not be here;
12918 instead, there should be some programmatic way of inquiring as
12919 to whether or not an object is a vtable. */
12921 #define VTABLE_NAME_P(NAME) \
12922 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
12923 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
12924 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
12925 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
12928 rs6000_output_symbol_ref (FILE *file, rtx x)
12930 /* Currently C++ toc references to vtables can be emitted before it
12931 is decided whether the vtable is public or private. If this is
12932 the case, then the linker will eventually complain that there is
12933 a reference to an unknown section. Thus, for vtables only,
12934 we emit the TOC reference to reference the symbol and not the
12936 const char *name = XSTR (x, 0);
12938 if (VTABLE_NAME_P (name))
12940 RS6000_OUTPUT_BASENAME (file, name);
12943 assemble_name (file, name);
12946 /* Output a TOC entry. We derive the entry name from what is being
12950 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
12953 const char *name = buf;
12954 const char *real_name;
12961 /* When the linker won't eliminate them, don't output duplicate
12962 TOC entries (this happens on AIX if there is any kind of TOC,
12963 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
12965 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
12967 struct toc_hash_struct *h;
12970 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
12971 time because GGC is not initialized at that point. */
12972 if (toc_hash_table == NULL)
12973 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
12974 toc_hash_eq, NULL);
12976 h = ggc_alloc (sizeof (*h));
12978 h->key_mode = mode;
12979 h->labelno = labelno;
12981 found = htab_find_slot (toc_hash_table, h, 1);
12982 if (*found == NULL)
12984 else /* This is indeed a duplicate.
12985 Set this label equal to that label. */
12987 fputs ("\t.set ", file);
12988 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
12989 fprintf (file, "%d,", labelno);
12990 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
12991 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
12997 /* If we're going to put a double constant in the TOC, make sure it's
12998 aligned properly when strict alignment is on. */
12999 if (GET_CODE (x) == CONST_DOUBLE
13000 && STRICT_ALIGNMENT
13001 && GET_MODE_BITSIZE (mode) >= 64
13002 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
13003 ASM_OUTPUT_ALIGN (file, 3);
13006 (*targetm.asm_out.internal_label) (file, "LC", labelno);
13008 /* Handle FP constants specially. Note that if we have a minimal
13009 TOC, things we put here aren't actually in the TOC, so we can allow
13011 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
13013 REAL_VALUE_TYPE rv;
13016 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13017 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
13021 if (TARGET_MINIMAL_TOC)
13022 fputs (DOUBLE_INT_ASM_OP, file);
13024 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13025 k[0] & 0xffffffff, k[1] & 0xffffffff,
13026 k[2] & 0xffffffff, k[3] & 0xffffffff);
13027 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
13028 k[0] & 0xffffffff, k[1] & 0xffffffff,
13029 k[2] & 0xffffffff, k[3] & 0xffffffff);
13034 if (TARGET_MINIMAL_TOC)
13035 fputs ("\t.long ", file);
13037 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
13038 k[0] & 0xffffffff, k[1] & 0xffffffff,
13039 k[2] & 0xffffffff, k[3] & 0xffffffff);
13040 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
13041 k[0] & 0xffffffff, k[1] & 0xffffffff,
13042 k[2] & 0xffffffff, k[3] & 0xffffffff);
13046 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
13048 REAL_VALUE_TYPE rv;
13051 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13052 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
13056 if (TARGET_MINIMAL_TOC)
13057 fputs (DOUBLE_INT_ASM_OP, file);
13059 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13060 k[0] & 0xffffffff, k[1] & 0xffffffff);
13061 fprintf (file, "0x%lx%08lx\n",
13062 k[0] & 0xffffffff, k[1] & 0xffffffff);
13067 if (TARGET_MINIMAL_TOC)
13068 fputs ("\t.long ", file);
13070 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
13071 k[0] & 0xffffffff, k[1] & 0xffffffff);
13072 fprintf (file, "0x%lx,0x%lx\n",
13073 k[0] & 0xffffffff, k[1] & 0xffffffff);
13077 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
13079 REAL_VALUE_TYPE rv;
13082 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
13083 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
13087 if (TARGET_MINIMAL_TOC)
13088 fputs (DOUBLE_INT_ASM_OP, file);
13090 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13091 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
13096 if (TARGET_MINIMAL_TOC)
13097 fputs ("\t.long ", file);
13099 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
13100 fprintf (file, "0x%lx\n", l & 0xffffffff);
13104 else if (GET_MODE (x) == VOIDmode
13105 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
13107 unsigned HOST_WIDE_INT low;
13108 HOST_WIDE_INT high;
13110 if (GET_CODE (x) == CONST_DOUBLE)
13112 low = CONST_DOUBLE_LOW (x);
13113 high = CONST_DOUBLE_HIGH (x);
13116 #if HOST_BITS_PER_WIDE_INT == 32
13119 high = (low & 0x80000000) ? ~0 : 0;
13123 low = INTVAL (x) & 0xffffffff;
13124 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
13128 /* TOC entries are always Pmode-sized, but since this
13129 is a bigendian machine then if we're putting smaller
13130 integer constants in the TOC we have to pad them.
13131 (This is still a win over putting the constants in
13132 a separate constant pool, because then we'd have
13133 to have both a TOC entry _and_ the actual constant.)
13135 For a 32-bit target, CONST_INT values are loaded and shifted
13136 entirely within `low' and can be stored in one TOC entry. */
13138 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
13139 abort ();/* It would be easy to make this work, but it doesn't now. */
13141 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
13143 #if HOST_BITS_PER_WIDE_INT == 32
13144 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
13145 POINTER_SIZE, &low, &high, 0);
13148 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
13149 high = (HOST_WIDE_INT) low >> 32;
13156 if (TARGET_MINIMAL_TOC)
13157 fputs (DOUBLE_INT_ASM_OP, file);
13159 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13160 (long) high & 0xffffffff, (long) low & 0xffffffff);
13161 fprintf (file, "0x%lx%08lx\n",
13162 (long) high & 0xffffffff, (long) low & 0xffffffff);
13167 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
13169 if (TARGET_MINIMAL_TOC)
13170 fputs ("\t.long ", file);
13172 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
13173 (long) high & 0xffffffff, (long) low & 0xffffffff);
13174 fprintf (file, "0x%lx,0x%lx\n",
13175 (long) high & 0xffffffff, (long) low & 0xffffffff);
13179 if (TARGET_MINIMAL_TOC)
13180 fputs ("\t.long ", file);
13182 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
13183 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
13189 if (GET_CODE (x) == CONST)
13191 if (GET_CODE (XEXP (x, 0)) != PLUS)
13194 base = XEXP (XEXP (x, 0), 0);
13195 offset = INTVAL (XEXP (XEXP (x, 0), 1));
13198 if (GET_CODE (base) == SYMBOL_REF)
13199 name = XSTR (base, 0);
13200 else if (GET_CODE (base) == LABEL_REF)
13201 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
13202 else if (GET_CODE (base) == CODE_LABEL)
13203 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
13207 real_name = (*targetm.strip_name_encoding) (name);
13208 if (TARGET_MINIMAL_TOC)
13209 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
13212 fprintf (file, "\t.tc %s", real_name);
13215 fprintf (file, ".N%d", - offset);
13217 fprintf (file, ".P%d", offset);
13219 fputs ("[TC],", file);
13222 /* Currently C++ toc references to vtables can be emitted before it
13223 is decided whether the vtable is public or private. If this is
13224 the case, then the linker will eventually complain that there is
13225 a TOC reference to an unknown section. Thus, for vtables only,
13226 we emit the TOC reference to reference the symbol and not the
13228 if (VTABLE_NAME_P (name))
13230 RS6000_OUTPUT_BASENAME (file, name);
13232 fprintf (file, "%d", offset);
13233 else if (offset > 0)
13234 fprintf (file, "+%d", offset);
13237 output_addr_const (file, x);
13241 /* Output an assembler pseudo-op to write an ASCII string of N characters
13242 starting at P to FILE.
13244 On the RS/6000, we have to do this using the .byte operation and
13245 write out special characters outside the quoted string.
13246 Also, the assembler is broken; very long strings are truncated,
13247 so we must artificially break them up early. */
13250 output_ascii (FILE *file, const char *p, int n)
13253 int i, count_string;
13254 const char *for_string = "\t.byte \"";
13255 const char *for_decimal = "\t.byte ";
13256 const char *to_close = NULL;
13259 for (i = 0; i < n; i++)
13262 if (c >= ' ' && c < 0177)
13265 fputs (for_string, file);
13268 /* Write two quotes to get one. */
13276 for_decimal = "\"\n\t.byte ";
13280 if (count_string >= 512)
13282 fputs (to_close, file);
13284 for_string = "\t.byte \"";
13285 for_decimal = "\t.byte ";
13293 fputs (for_decimal, file);
13294 fprintf (file, "%d", c);
13296 for_string = "\n\t.byte \"";
13297 for_decimal = ", ";
13303 /* Now close the string if we have written one. Then end the line. */
13305 fputs (to_close, file);
13308 /* Generate a unique section name for FILENAME for a section type
13309 represented by SECTION_DESC. Output goes into BUF.
13311 SECTION_DESC can be any string, as long as it is different for each
13312 possible section type.
13314 We name the section in the same manner as xlc. The name begins with an
13315 underscore followed by the filename (after stripping any leading directory
13316 names) with the last period replaced by the string SECTION_DESC. If
13317 FILENAME does not contain a period, SECTION_DESC is appended to the end of
13321 rs6000_gen_section_name (char **buf, const char *filename,
13322 const char *section_desc)
13324 const char *q, *after_last_slash, *last_period = 0;
13328 after_last_slash = filename;
13329 for (q = filename; *q; q++)
13332 after_last_slash = q + 1;
13333 else if (*q == '.')
13337 len = strlen (after_last_slash) + strlen (section_desc) + 2;
13338 *buf = (char *) xmalloc (len);
13343 for (q = after_last_slash; *q; q++)
13345 if (q == last_period)
13347 strcpy (p, section_desc);
13348 p += strlen (section_desc);
13352 else if (ISALNUM (*q))
13356 if (last_period == 0)
13357 strcpy (p, section_desc);
13362 /* Emit profile function. */
13365 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
13367 if (TARGET_PROFILE_KERNEL)
13370 if (DEFAULT_ABI == ABI_AIX)
13372 #ifndef NO_PROFILE_COUNTERS
13373 # define NO_PROFILE_COUNTERS 0
13375 if (NO_PROFILE_COUNTERS)
13376 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
13380 const char *label_name;
13383 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13384 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
13385 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
13387 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
13391 else if (DEFAULT_ABI == ABI_DARWIN)
13393 const char *mcount_name = RS6000_MCOUNT;
13394 int caller_addr_regno = LINK_REGISTER_REGNUM;
13396 /* Be conservative and always set this, at least for now. */
13397 current_function_uses_pic_offset_table = 1;
13400 /* For PIC code, set up a stub and collect the caller's address
13401 from r0, which is where the prologue puts it. */
13402 if (MACHOPIC_INDIRECT)
13404 mcount_name = machopic_stub_name (mcount_name);
13405 if (current_function_uses_pic_offset_table)
13406 caller_addr_regno = 0;
13409 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
13411 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
13415 /* Write function profiler code. */
13418 output_function_profiler (FILE *file, int labelno)
13423 switch (DEFAULT_ABI)
13432 warning ("no profiling of 64-bit code for this ABI");
13435 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
13436 fprintf (file, "\tmflr %s\n", reg_names[0]);
13439 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
13440 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13441 reg_names[0], save_lr, reg_names[1]);
13442 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
13443 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
13444 assemble_name (file, buf);
13445 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
13447 else if (flag_pic > 1)
13449 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13450 reg_names[0], save_lr, reg_names[1]);
13451 /* Now, we need to get the address of the label. */
13452 fputs ("\tbl 1f\n\t.long ", file);
13453 assemble_name (file, buf);
13454 fputs ("-.\n1:", file);
13455 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
13456 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
13457 reg_names[0], reg_names[11]);
13458 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
13459 reg_names[0], reg_names[0], reg_names[11]);
13463 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
13464 assemble_name (file, buf);
13465 fputs ("@ha\n", file);
13466 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
13467 reg_names[0], save_lr, reg_names[1]);
13468 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
13469 assemble_name (file, buf);
13470 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
13473 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
13474 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13479 if (!TARGET_PROFILE_KERNEL)
13481 /* Don't do anything, done in output_profile_hook (). */
13488 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
13489 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
13491 if (current_function_needs_context)
13493 asm_fprintf (file, "\tstd %s,24(%s)\n",
13494 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13495 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13496 asm_fprintf (file, "\tld %s,24(%s)\n",
13497 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
13500 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
13508 rs6000_use_dfa_pipeline_interface (void)
13513 /* Power4 load update and store update instructions are cracked into a
13514 load or store and an integer insn which are executed in the same cycle.
13515 Branches have their own dispatch slot which does not count against the
13516 GCC issue rate, but it changes the program flow so there are no other
13517 instructions to issue in this cycle. */
13520 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
13521 int verbose ATTRIBUTE_UNUSED,
13522 rtx insn, int more)
13524 if (GET_CODE (PATTERN (insn)) == USE
13525 || GET_CODE (PATTERN (insn)) == CLOBBER)
13528 if (rs6000_cpu == PROCESSOR_POWER4)
13530 if (is_microcoded_insn (insn))
13532 else if (is_cracked_insn (insn))
13533 return more > 2 ? more - 2 : 0;
13539 /* Adjust the cost of a scheduling dependency. Return the new cost of
13540 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
13543 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED,
13546 if (! recog_memoized (insn))
13549 if (REG_NOTE_KIND (link) != 0)
13552 if (REG_NOTE_KIND (link) == 0)
13554 /* Data dependency; DEP_INSN writes a register that INSN reads
13555 some cycles later. */
13556 switch (get_attr_type (insn))
13559 /* Tell the first scheduling pass about the latency between
13560 a mtctr and bctr (and mtlr and br/blr). The first
13561 scheduling pass will not know about this latency since
13562 the mtctr instruction, which has the latency associated
13563 to it, will be generated by reload. */
13564 return TARGET_POWER ? 5 : 4;
13566 /* Leave some extra cycles between a compare and its
13567 dependent branch, to inhibit expensive mispredicts. */
13568 if ((rs6000_cpu_attr == CPU_PPC603
13569 || rs6000_cpu_attr == CPU_PPC604
13570 || rs6000_cpu_attr == CPU_PPC604E
13571 || rs6000_cpu_attr == CPU_PPC620
13572 || rs6000_cpu_attr == CPU_PPC630
13573 || rs6000_cpu_attr == CPU_PPC750
13574 || rs6000_cpu_attr == CPU_PPC7400
13575 || rs6000_cpu_attr == CPU_PPC7450
13576 || rs6000_cpu_attr == CPU_POWER4)
13577 && recog_memoized (dep_insn)
13578 && (INSN_CODE (dep_insn) >= 0)
13579 && (get_attr_type (dep_insn) == TYPE_CMP
13580 || get_attr_type (dep_insn) == TYPE_COMPARE
13581 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
13582 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
13583 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
13584 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
13585 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
13586 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
13591 /* Fall out to return default cost. */
13597 /* The function returns a true if INSN is microcoded.
13598 Return false otherwise. */
13601 is_microcoded_insn (rtx insn)
13603 if (!insn || !INSN_P (insn)
13604 || GET_CODE (PATTERN (insn)) == USE
13605 || GET_CODE (PATTERN (insn)) == CLOBBER)
13608 if (rs6000_cpu == PROCESSOR_POWER4)
13610 enum attr_type type = get_attr_type (insn);
13611 if (type == TYPE_LOAD_EXT_U
13612 || type == TYPE_LOAD_EXT_UX
13613 || type == TYPE_LOAD_UX
13614 || type == TYPE_STORE_UX
13615 || type == TYPE_MFCR)
13622 /* The function returns a nonzero value if INSN can be scheduled only
13623 as the first insn in a dispatch group ("dispatch-slot restricted").
13624 In this case, the returned value indicates how many dispatch slots
13625 the insn occupies (at the beginning of the group).
13626 Return 0 otherwise. */
13629 is_dispatch_slot_restricted (rtx insn)
13631 enum attr_type type;
13633 if (rs6000_cpu != PROCESSOR_POWER4)
13637 || insn == NULL_RTX
13638 || GET_CODE (insn) == NOTE
13639 || GET_CODE (PATTERN (insn)) == USE
13640 || GET_CODE (PATTERN (insn)) == CLOBBER)
13643 type = get_attr_type (insn);
13649 case TYPE_DELAYED_CR:
13650 case TYPE_CR_LOGICAL:
13662 /* The function returns true if INSN is cracked into 2 instructions
13663 by the processor (and therefore occupies 2 issue slots). */
13666 is_cracked_insn (rtx insn)
13668 if (!insn || !INSN_P (insn)
13669 || GET_CODE (PATTERN (insn)) == USE
13670 || GET_CODE (PATTERN (insn)) == CLOBBER)
13673 if (rs6000_cpu == PROCESSOR_POWER4)
13675 enum attr_type type = get_attr_type (insn);
13676 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
13677 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
13678 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
13679 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
13680 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
13681 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
13682 || type == TYPE_IDIV || type == TYPE_LDIV
13683 || type == TYPE_INSERT_WORD)
13690 /* The function returns true if INSN can be issued only from
13691 the branch slot. */
13694 is_branch_slot_insn (rtx insn)
13696 if (!insn || !INSN_P (insn)
13697 || GET_CODE (PATTERN (insn)) == USE
13698 || GET_CODE (PATTERN (insn)) == CLOBBER)
13701 if (rs6000_cpu == PROCESSOR_POWER4)
13703 enum attr_type type = get_attr_type (insn);
13704 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
13712 /* A C statement (sans semicolon) to update the integer scheduling
13713 priority INSN_PRIORITY (INSN). Increase the priority to execute the
13714 INSN earlier, reduce the priority to execute INSN later. Do not
13715 define this macro if you do not need to adjust the scheduling
13716 priorities of insns. */
13719 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
13721 /* On machines (like the 750) which have asymmetric integer units,
13722 where one integer unit can do multiply and divides and the other
13723 can't, reduce the priority of multiply/divide so it is scheduled
13724 before other integer operations. */
13727 if (! INSN_P (insn))
13730 if (GET_CODE (PATTERN (insn)) == USE)
13733 switch (rs6000_cpu_attr) {
13735 switch (get_attr_type (insn))
13742 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
13743 priority, priority);
13744 if (priority >= 0 && priority < 0x01000000)
13751 if (is_dispatch_slot_restricted (insn)
13752 && reload_completed
13753 && current_sched_info->sched_max_insns_priority
13754 && rs6000_sched_restricted_insns_priority)
13757 /* Prioritize insns that can be dispatched only in the first dispatch slot. */
13758 if (rs6000_sched_restricted_insns_priority == 1)
13759 /* Attach highest priority to insn. This means that in
13760 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
13761 precede 'priority' (critical path) considerations. */
13762 return current_sched_info->sched_max_insns_priority;
13763 else if (rs6000_sched_restricted_insns_priority == 2)
13764 /* Increase priority of insn by a minimal amount. This means that in
13765 haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations
13766 precede dispatch-slot restriction considerations. */
13767 return (priority + 1);
13773 /* Return how many instructions the machine can issue per cycle. */
13776 rs6000_issue_rate (void)
13778 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
13779 if (!reload_completed)
13782 switch (rs6000_cpu_attr) {
13783 case CPU_RIOS1: /* ? */
13785 case CPU_PPC601: /* ? */
13807 /* Return how many instructions to look ahead for better insn
13811 rs6000_use_sched_lookahead (void)
13813 if (rs6000_cpu_attr == CPU_PPC8540)
13818 /* Determine is PAT refers to memory. */
13821 is_mem_ref (rtx pat)
13827 if (GET_CODE (pat) == MEM)
13830 /* Recursively process the pattern. */
13831 fmt = GET_RTX_FORMAT (GET_CODE (pat));
13833 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
13836 ret |= is_mem_ref (XEXP (pat, i));
13837 else if (fmt[i] == 'E')
13838 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
13839 ret |= is_mem_ref (XVECEXP (pat, i, j));
13845 /* Determine if PAT is a PATTERN of a load insn. */
13848 is_load_insn1 (rtx pat)
13850 if (!pat || pat == NULL_RTX)
13853 if (GET_CODE (pat) == SET)
13854 return is_mem_ref (SET_SRC (pat));
13856 if (GET_CODE (pat) == PARALLEL)
13860 for (i = 0; i < XVECLEN (pat, 0); i++)
13861 if (is_load_insn1 (XVECEXP (pat, 0, i)))
13868 /* Determine if INSN loads from memory. */
13871 is_load_insn (rtx insn)
13873 if (!insn || !INSN_P (insn))
13876 if (GET_CODE (insn) == CALL_INSN)
13879 return is_load_insn1 (PATTERN (insn));
13882 /* Determine if PAT is a PATTERN of a store insn. */
13885 is_store_insn1 (rtx pat)
13887 if (!pat || pat == NULL_RTX)
13890 if (GET_CODE (pat) == SET)
13891 return is_mem_ref (SET_DEST (pat));
13893 if (GET_CODE (pat) == PARALLEL)
13897 for (i = 0; i < XVECLEN (pat, 0); i++)
13898 if (is_store_insn1 (XVECEXP (pat, 0, i)))
13905 /* Determine if INSN stores to memory. */
13908 is_store_insn (rtx insn)
13910 if (!insn || !INSN_P (insn))
13913 return is_store_insn1 (PATTERN (insn));
13916 /* Returns whether the dependence between INSN and NEXT is considered
13917 costly by the given target. */
13920 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distance)
13922 /* If the flag is not enbled - no dependence is considered costly;
13923 allow all dependent insns in the same group.
13924 This is the most aggressive option. */
13925 if (rs6000_sched_costly_dep == no_dep_costly)
13928 /* If the flag is set to 1 - a dependence is always considered costly;
13929 do not allow dependent instructions in the same group.
13930 This is the most conservative option. */
13931 if (rs6000_sched_costly_dep == all_deps_costly)
13934 if (rs6000_sched_costly_dep == store_to_load_dep_costly
13935 && is_load_insn (next)
13936 && is_store_insn (insn))
13937 /* Prevent load after store in the same group. */
13940 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
13941 && is_load_insn (next)
13942 && is_store_insn (insn)
13943 && (!link || (int) REG_NOTE_KIND (link) == 0))
13944 /* Prevent load after store in the same group if it is a true dependence. */
13947 /* The flag is set to X; dependences with latency >= X are considered costly,
13948 and will not be scheduled in the same group. */
13949 if (rs6000_sched_costly_dep <= max_dep_latency
13950 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
13956 /* Return the next insn after INSN that is found before TAIL is reached,
13957 skipping any "non-active" insns - insns that will not actually occupy
13958 an issue slot. Return NULL_RTX if such an insn is not found. */
13961 get_next_active_insn (rtx insn, rtx tail)
13965 if (!insn || insn == tail)
13968 next_insn = NEXT_INSN (insn);
13971 && next_insn != tail
13972 && (GET_CODE(next_insn) == NOTE
13973 || GET_CODE (PATTERN (next_insn)) == USE
13974 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
13976 next_insn = NEXT_INSN (next_insn);
13979 if (!next_insn || next_insn == tail)
13985 /* Return whether the presence of INSN causes a dispatch group termination
13986 of group WHICH_GROUP.
13988 If WHICH_GROUP == current_group, this function will return true if INSN
13989 causes the termination of the current group (i.e, the dispatch group to
13990 which INSN belongs). This means that INSN will be the last insn in the
13991 group it belongs to.
13993 If WHICH_GROUP == previous_group, this function will return true if INSN
13994 causes the termination of the previous group (i.e, the dispatch group that
13995 precedes the group to which INSN belongs). This means that INSN will be
13996 the first insn in the group it belongs to). */
13999 insn_terminates_group_p (rtx insn, enum group_termination which_group)
14001 enum attr_type type;
14006 type = get_attr_type (insn);
14008 if (is_microcoded_insn (insn))
14011 if (which_group == current_group)
14013 if (is_branch_slot_insn (insn))
14017 else if (which_group == previous_group)
14019 if (is_dispatch_slot_restricted (insn))
14027 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
14028 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
14031 is_costly_group (rtx *group_insns, rtx next_insn)
14036 int issue_rate = rs6000_issue_rate ();
14038 for (i = 0; i < issue_rate; i++)
14040 rtx insn = group_insns[i];
14043 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
14045 rtx next = XEXP (link, 0);
14046 if (next == next_insn)
14048 cost = insn_cost (insn, link, next_insn);
14049 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
14058 /* Utility of the function redefine_groups.
14059 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
14060 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
14061 to keep it "far" (in a separate group) from GROUP_INSNS, following
14062 one of the following schemes, depending on the value of the flag
14063 -minsert_sched_nops = X:
14064 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
14065 in order to force NEXT_INSN into a separate group.
14066 (2) X < sched_finish_regroup_exact: insert exactly X nops.
14067 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
14068 insertion (has a group just ended, how many vacant issue slots remain in the
14069 last group, and how many dispatch groups were encountered so far). */
14072 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn,
14073 bool *group_end, int can_issue_more, int *group_count)
14077 int issue_rate = rs6000_issue_rate ();
14078 bool end = *group_end;
14081 if (next_insn == NULL_RTX)
14082 return can_issue_more;
14084 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
14085 return can_issue_more;
14087 force = is_costly_group (group_insns, next_insn);
14089 return can_issue_more;
14091 if (sched_verbose > 6)
14092 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
14093 *group_count ,can_issue_more);
14095 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
14098 can_issue_more = 0;
14100 /* Since only a branch can be issued in the last issue_slot, it is
14101 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
14102 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
14103 in this case the last nop will start a new group and the branch will be
14104 forced to the new group. */
14105 if (can_issue_more && !is_branch_slot_insn (next_insn))
14108 while (can_issue_more > 0)
14111 emit_insn_before (nop, next_insn);
14119 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
14121 int n_nops = rs6000_sched_insert_nops;
14123 /* Nops can't be issued from the branch slot, so the effective
14124 issue_rate for nops is 'issue_rate - 1'. */
14125 if (can_issue_more == 0)
14126 can_issue_more = issue_rate;
14128 if (can_issue_more == 0)
14130 can_issue_more = issue_rate - 1;
14133 for (i = 0; i < issue_rate; i++)
14135 group_insns[i] = 0;
14142 emit_insn_before (nop, next_insn);
14143 if (can_issue_more == issue_rate - 1) /* new group begins */
14146 if (can_issue_more == 0)
14148 can_issue_more = issue_rate - 1;
14151 for (i = 0; i < issue_rate; i++)
14153 group_insns[i] = 0;
14159 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
14162 *group_end = /* Is next_insn going to start a new group? */
14164 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14165 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14166 || (can_issue_more < issue_rate &&
14167 insn_terminates_group_p (next_insn, previous_group)));
14168 if (*group_end && end)
14171 if (sched_verbose > 6)
14172 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
14173 *group_count, can_issue_more);
14174 return can_issue_more;
14177 return can_issue_more;
14180 /* This function tries to synch the dispatch groups that the compiler "sees"
14181 with the dispatch groups that the processor dispatcher is expected to
14182 form in practice. It tries to achieve this synchronization by forcing the
14183 estimated processor grouping on the compiler (as opposed to the function
14184 'pad_goups' which tries to force the scheduler's grouping on the processor).
14186 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
14187 examines the (estimated) dispatch groups that will be formed by the processor
14188 dispatcher. It marks these group boundaries to reflect the estimated
14189 processor grouping, overriding the grouping that the scheduler had marked.
14190 Depending on the value of the flag '-minsert-sched-nops' this function can
14191 force certain insns into separate groups or force a certain distance between
14192 them by inserting nops, for example, if there exists a "costly dependence"
14195 The function estimates the group boundaries that the processor will form as
14196 folllows: It keeps track of how many vacant issue slots are available after
14197 each insn. A subsequent insn will start a new group if one of the following
14199 - no more vacant issue slots remain in the current dispatch group.
14200 - only the last issue slot, which is the branch slot, is vacant, but the next
14201 insn is not a branch.
14202 - only the last 2 or less issue slots, including the branch slot, are vacant,
14203 which means that a cracked insn (which occupies two issue slots) can't be
14204 issued in this group.
14205 - less than 'issue_rate' slots are vacant, and the next insn always needs to
14206 start a new group. */
14209 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14211 rtx insn, next_insn;
14213 int can_issue_more;
14216 int group_count = 0;
14220 issue_rate = rs6000_issue_rate ();
14221 group_insns = alloca (issue_rate * sizeof (rtx));
14222 for (i = 0; i < issue_rate; i++)
14224 group_insns[i] = 0;
14226 can_issue_more = issue_rate;
14228 insn = get_next_active_insn (prev_head_insn, tail);
14231 while (insn != NULL_RTX)
14233 slot = (issue_rate - can_issue_more);
14234 group_insns[slot] = insn;
14236 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14237 if (insn_terminates_group_p (insn, current_group))
14238 can_issue_more = 0;
14240 next_insn = get_next_active_insn (insn, tail);
14241 if (next_insn == NULL_RTX)
14242 return group_count + 1;
14244 group_end = /* Is next_insn going to start a new group? */
14245 (can_issue_more == 0
14246 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
14247 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
14248 || (can_issue_more < issue_rate &&
14249 insn_terminates_group_p (next_insn, previous_group)));
14251 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
14252 next_insn, &group_end, can_issue_more, &group_count);
14257 can_issue_more = 0;
14258 for (i = 0; i < issue_rate; i++)
14260 group_insns[i] = 0;
14264 if (GET_MODE (next_insn) == TImode && can_issue_more)
14265 PUT_MODE(next_insn, VOIDmode);
14266 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
14267 PUT_MODE (next_insn, TImode);
14270 if (can_issue_more == 0)
14271 can_issue_more = issue_rate;
14274 return group_count;
14277 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
14278 dispatch group boundaries that the scheduler had marked. Pad with nops
14279 any dispatch groups which have vacant issue slots, in order to force the
14280 scheduler's grouping on the processor dispatcher. The function
14281 returns the number of dispatch groups found. */
14284 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
14286 rtx insn, next_insn;
14289 int can_issue_more;
14291 int group_count = 0;
14293 /* Initialize issue_rate. */
14294 issue_rate = rs6000_issue_rate ();
14295 can_issue_more = issue_rate;
14297 insn = get_next_active_insn (prev_head_insn, tail);
14298 next_insn = get_next_active_insn (insn, tail);
14300 while (insn != NULL_RTX)
14303 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
14305 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
14307 if (next_insn == NULL_RTX)
14312 /* If the scheduler had marked group termination at this location
14313 (between insn and next_indn), and neither insn nor next_insn will
14314 force group termination, pad the group with nops to force group
14317 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
14318 && !insn_terminates_group_p (insn, current_group)
14319 && !insn_terminates_group_p (next_insn, previous_group))
14321 if (!is_branch_slot_insn(next_insn))
14324 while (can_issue_more)
14327 emit_insn_before (nop, next_insn);
14332 can_issue_more = issue_rate;
14337 next_insn = get_next_active_insn (insn, tail);
14340 return group_count;
14343 /* The following function is called at the end of scheduling BB.
14344 After reload, it inserts nops at insn group bundling. */
14347 rs6000_sched_finish (FILE *dump, int sched_verbose)
14352 fprintf (dump, "=== Finishing schedule.\n");
14354 if (reload_completed && rs6000_cpu == PROCESSOR_POWER4)
14356 if (rs6000_sched_insert_nops == sched_finish_none)
14359 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
14360 n_groups = pad_groups (dump, sched_verbose,
14361 current_sched_info->prev_head,
14362 current_sched_info->next_tail);
14364 n_groups = redefine_groups (dump, sched_verbose,
14365 current_sched_info->prev_head,
14366 current_sched_info->next_tail);
14368 if (sched_verbose >= 6)
14370 fprintf (dump, "ngroups = %d\n", n_groups);
14371 print_rtl (dump, current_sched_info->prev_head);
14372 fprintf (dump, "Done finish_sched\n");
14377 /* Length in units of the trampoline for entering a nested function. */
14380 rs6000_trampoline_size (void)
14384 switch (DEFAULT_ABI)
14390 ret = (TARGET_32BIT) ? 12 : 24;
14395 ret = (TARGET_32BIT) ? 40 : 48;
14402 /* Emit RTL insns to initialize the variable parts of a trampoline.
14403 FNADDR is an RTX for the address of the function's pure code.
14404 CXT is an RTX for the static chain value for the function. */
14407 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
14409 enum machine_mode pmode = Pmode;
14410 int regsize = (TARGET_32BIT) ? 4 : 8;
14411 rtx ctx_reg = force_reg (pmode, cxt);
14413 switch (DEFAULT_ABI)
14418 /* Macros to shorten the code expansions below. */
14419 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
14420 #define MEM_PLUS(addr,offset) \
14421 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
14423 /* Under AIX, just build the 3 word function descriptor */
14426 rtx fn_reg = gen_reg_rtx (pmode);
14427 rtx toc_reg = gen_reg_rtx (pmode);
14428 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
14429 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
14430 emit_move_insn (MEM_DEREF (addr), fn_reg);
14431 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
14432 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
14436 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
14439 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
14440 FALSE, VOIDmode, 4,
14442 GEN_INT (rs6000_trampoline_size ()), SImode,
14452 /* Table of valid machine attributes. */
14454 const struct attribute_spec rs6000_attribute_table[] =
14456 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
14457 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
14458 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
14459 { NULL, 0, 0, false, false, false, NULL }
14462 /* Handle a "longcall" or "shortcall" attribute; arguments as in
14463 struct attribute_spec.handler. */
14466 rs6000_handle_longcall_attribute (tree *node, tree name,
14467 tree args ATTRIBUTE_UNUSED,
14468 int flags ATTRIBUTE_UNUSED,
14469 bool *no_add_attrs)
14471 if (TREE_CODE (*node) != FUNCTION_TYPE
14472 && TREE_CODE (*node) != FIELD_DECL
14473 && TREE_CODE (*node) != TYPE_DECL)
14475 warning ("`%s' attribute only applies to functions",
14476 IDENTIFIER_POINTER (name));
14477 *no_add_attrs = true;
14483 /* Set longcall attributes on all functions declared when
14484 rs6000_default_long_calls is true. */
14486 rs6000_set_default_type_attributes (tree type)
14488 if (rs6000_default_long_calls
14489 && (TREE_CODE (type) == FUNCTION_TYPE
14490 || TREE_CODE (type) == METHOD_TYPE))
14491 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
14493 TYPE_ATTRIBUTES (type));
14496 /* Return a reference suitable for calling a function with the
14497 longcall attribute. */
14500 rs6000_longcall_ref (rtx call_ref)
14502 const char *call_name;
14505 if (GET_CODE (call_ref) != SYMBOL_REF)
14508 /* System V adds '.' to the internal name, so skip them. */
14509 call_name = XSTR (call_ref, 0);
14510 if (*call_name == '.')
14512 while (*call_name == '.')
14515 node = get_identifier (call_name);
14516 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
14519 return force_reg (Pmode, call_ref);
14522 #ifdef USING_ELFOS_H
14524 /* A C statement or statements to switch to the appropriate section
14525 for output of RTX in mode MODE. You can assume that RTX is some
14526 kind of constant in RTL. The argument MODE is redundant except in
14527 the case of a `const_int' rtx. Select the section by calling
14528 `text_section' or one of the alternatives for other sections.
14530 Do not define this macro if you put all constants in the read-only
14534 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
14535 unsigned HOST_WIDE_INT align)
14537 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
14540 default_elf_select_rtx_section (mode, x, align);
14543 /* A C statement or statements to switch to the appropriate
14544 section for output of DECL. DECL is either a `VAR_DECL' node
14545 or a constant of some sort. RELOC indicates whether forming
14546 the initial value of DECL requires link-time relocations. */
14549 rs6000_elf_select_section (tree decl, int reloc,
14550 unsigned HOST_WIDE_INT align)
14552 /* Pretend that we're always building for a shared library when
14553 ABI_AIX, because otherwise we end up with dynamic relocations
14554 in read-only sections. This happens for function pointers,
14555 references to vtables in typeinfo, and probably other cases. */
14556 default_elf_select_section_1 (decl, reloc, align,
14557 flag_pic || DEFAULT_ABI == ABI_AIX);
14560 /* A C statement to build up a unique section name, expressed as a
14561 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
14562 RELOC indicates whether the initial value of EXP requires
14563 link-time relocations. If you do not define this macro, GCC will use
14564 the symbol name prefixed by `.' as the section name. Note - this
14565 macro can now be called for uninitialized data items as well as
14566 initialized data and functions. */
14569 rs6000_elf_unique_section (tree decl, int reloc)
14571 /* As above, pretend that we're always building for a shared library
14572 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
14573 default_unique_section_1 (decl, reloc,
14574 flag_pic || DEFAULT_ABI == ABI_AIX);
14577 /* For a SYMBOL_REF, set generic flags and then perform some
14578 target-specific processing.
14580 When the AIX ABI is requested on a non-AIX system, replace the
14581 function name with the real name (with a leading .) rather than the
14582 function descriptor name. This saves a lot of overriding code to
14583 read the prefixes. */
14586 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
14588 default_encode_section_info (decl, rtl, first);
14591 && TREE_CODE (decl) == FUNCTION_DECL
14593 && DEFAULT_ABI == ABI_AIX)
14595 rtx sym_ref = XEXP (rtl, 0);
14596 size_t len = strlen (XSTR (sym_ref, 0));
14597 char *str = alloca (len + 2);
14599 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
14600 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
14605 rs6000_elf_in_small_data_p (tree decl)
14607 if (rs6000_sdata == SDATA_NONE)
14610 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
14612 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
14613 if (strcmp (section, ".sdata") == 0
14614 || strcmp (section, ".sdata2") == 0
14615 || strcmp (section, ".sbss") == 0
14616 || strcmp (section, ".sbss2") == 0
14617 || strcmp (section, ".PPC.EMB.sdata0") == 0
14618 || strcmp (section, ".PPC.EMB.sbss0") == 0)
14623 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
14626 && (unsigned HOST_WIDE_INT) size <= g_switch_value
14627 /* If it's not public, and we're not going to reference it there,
14628 there's no need to put it in the small data section. */
14629 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
14636 #endif /* USING_ELFOS_H */
14639 /* Return a REG that occurs in ADDR with coefficient 1.
14640 ADDR can be effectively incremented by incrementing REG.
14642 r0 is special and we must not select it as an address
14643 register by this routine since our caller will try to
14644 increment the returned register via an "la" instruction. */
14647 find_addr_reg (rtx addr)
14649 while (GET_CODE (addr) == PLUS)
14651 if (GET_CODE (XEXP (addr, 0)) == REG
14652 && REGNO (XEXP (addr, 0)) != 0)
14653 addr = XEXP (addr, 0);
14654 else if (GET_CODE (XEXP (addr, 1)) == REG
14655 && REGNO (XEXP (addr, 1)) != 0)
14656 addr = XEXP (addr, 1);
14657 else if (CONSTANT_P (XEXP (addr, 0)))
14658 addr = XEXP (addr, 1);
14659 else if (CONSTANT_P (XEXP (addr, 1)))
14660 addr = XEXP (addr, 0);
14664 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
14670 rs6000_fatal_bad_address (rtx op)
14672 fatal_insn ("bad address", op);
14678 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
14679 reference and a constant. */
14682 symbolic_operand (rtx op)
14684 switch (GET_CODE (op))
14691 return (GET_CODE (op) == SYMBOL_REF ||
14692 (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
14693 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
14694 && GET_CODE (XEXP (op, 1)) == CONST_INT);
14703 static tree branch_island_list = 0;
14705 /* Remember to generate a branch island for far calls to the given
14709 add_compiler_branch_island (tree label_name, tree function_name, int line_number)
14711 tree branch_island = build_tree_list (function_name, label_name);
14712 TREE_TYPE (branch_island) = build_int_2 (line_number, 0);
14713 TREE_CHAIN (branch_island) = branch_island_list;
14714 branch_island_list = branch_island;
14717 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
14718 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
14719 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
14720 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
14722 /* Generate far-jump branch islands for everything on the
14723 branch_island_list. Invoked immediately after the last instruction
14724 of the epilogue has been emitted; the branch-islands must be
14725 appended to, and contiguous with, the function body. Mach-O stubs
14726 are generated in machopic_output_stub(). */
14729 macho_branch_islands (void)
14732 tree branch_island;
14734 for (branch_island = branch_island_list;
14736 branch_island = TREE_CHAIN (branch_island))
14738 const char *label =
14739 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
14741 darwin_strip_name_encoding (
14742 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island)));
14743 char name_buf[512];
14744 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
14745 if (name[0] == '*' || name[0] == '&')
14746 strcpy (name_buf, name+1);
14750 strcpy (name_buf+1, name);
14752 strcpy (tmp_buf, "\n");
14753 strcat (tmp_buf, label);
14754 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
14755 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
14756 fprintf (asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
14757 BRANCH_ISLAND_LINE_NUMBER(branch_island));
14758 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
14761 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
14762 strcat (tmp_buf, label);
14763 strcat (tmp_buf, "_pic\n");
14764 strcat (tmp_buf, label);
14765 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
14767 strcat (tmp_buf, "\taddis r11,r11,ha16(");
14768 strcat (tmp_buf, name_buf);
14769 strcat (tmp_buf, " - ");
14770 strcat (tmp_buf, label);
14771 strcat (tmp_buf, "_pic)\n");
14773 strcat (tmp_buf, "\tmtlr r0\n");
14775 strcat (tmp_buf, "\taddi r12,r11,lo16(");
14776 strcat (tmp_buf, name_buf);
14777 strcat (tmp_buf, " - ");
14778 strcat (tmp_buf, label);
14779 strcat (tmp_buf, "_pic)\n");
14781 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
14785 strcat (tmp_buf, ":\nlis r12,hi16(");
14786 strcat (tmp_buf, name_buf);
14787 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
14788 strcat (tmp_buf, name_buf);
14789 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
14791 output_asm_insn (tmp_buf, 0);
14792 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
14793 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
14794 fprintf(asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
14795 BRANCH_ISLAND_LINE_NUMBER (branch_island));
14796 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
14799 branch_island_list = 0;
14802 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
14803 already there or not. */
14806 no_previous_def (tree function_name)
14808 tree branch_island;
14809 for (branch_island = branch_island_list;
14811 branch_island = TREE_CHAIN (branch_island))
14812 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
14817 /* GET_PREV_LABEL gets the label name from the previous definition of
14821 get_prev_label (tree function_name)
14823 tree branch_island;
14824 for (branch_island = branch_island_list;
14826 branch_island = TREE_CHAIN (branch_island))
14827 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
14828 return BRANCH_ISLAND_LABEL_NAME (branch_island);
14832 /* INSN is either a function call or a millicode call. It may have an
14833 unconditional jump in its delay slot.
14835 CALL_DEST is the routine we are calling. */
14838 output_call (rtx insn, rtx *operands, int dest_operand_number, int cookie_operand_number)
14840 static char buf[256];
14841 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
14842 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
14845 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
14847 if (no_previous_def (funname))
14849 int line_number = 0;
14850 rtx label_rtx = gen_label_rtx ();
14851 char *label_buf, temp_buf[256];
14852 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
14853 CODE_LABEL_NUMBER (label_rtx));
14854 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
14855 labelname = get_identifier (label_buf);
14856 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
14858 line_number = NOTE_LINE_NUMBER (insn);
14859 add_compiler_branch_island (labelname, funname, line_number);
14862 labelname = get_prev_label (funname);
14864 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
14865 instruction will reach 'foo', otherwise link as 'bl L42'".
14866 "L42" should be a 'branch island', that will do a far jump to
14867 'foo'. Branch islands are generated in
14868 macho_branch_islands(). */
14869 sprintf (buf, "jbsr %%z%d,%.246s",
14870 dest_operand_number, IDENTIFIER_POINTER (labelname));
14873 sprintf (buf, "bl %%z%d", dest_operand_number);
14877 #endif /* TARGET_MACHO */
14879 /* Generate PIC and indirect symbol stubs. */
14882 machopic_output_stub (FILE *file, const char *symb, const char *stub)
14884 unsigned int length;
14885 char *symbol_name, *lazy_ptr_name;
14886 char *local_label_0;
14887 static int label = 0;
14889 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
14890 symb = (*targetm.strip_name_encoding) (symb);
14893 length = strlen (symb);
14894 symbol_name = alloca (length + 32);
14895 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
14897 lazy_ptr_name = alloca (length + 32);
14898 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
14901 machopic_picsymbol_stub1_section ();
14903 machopic_symbol_stub1_section ();
14904 fprintf (file, "\t.align 2\n");
14906 fprintf (file, "%s:\n", stub);
14907 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
14912 local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
14913 sprintf (local_label_0, "\"L%011d$spb\"", label);
14915 fprintf (file, "\tmflr r0\n");
14916 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
14917 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
14918 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
14919 lazy_ptr_name, local_label_0);
14920 fprintf (file, "\tmtlr r0\n");
14921 fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n",
14922 lazy_ptr_name, local_label_0);
14923 fprintf (file, "\tmtctr r12\n");
14924 fprintf (file, "\tbctr\n");
14928 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
14929 fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
14930 fprintf (file, "\tmtctr r12\n");
14931 fprintf (file, "\tbctr\n");
14934 machopic_lazy_symbol_ptr_section ();
14935 fprintf (file, "%s:\n", lazy_ptr_name);
14936 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
14937 fprintf (file, "\t.long dyld_stub_binding_helper\n");
14940 /* Legitimize PIC addresses. If the address is already
14941 position-independent, we return ORIG. Newly generated
14942 position-independent addresses go into a reg. This is REG if non
14943 zero, otherwise we allocate register(s) as necessary. */
14945 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
14948 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
14953 if (reg == NULL && ! reload_in_progress && ! reload_completed)
14954 reg = gen_reg_rtx (Pmode);
14956 if (GET_CODE (orig) == CONST)
14958 if (GET_CODE (XEXP (orig, 0)) == PLUS
14959 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
14962 if (GET_CODE (XEXP (orig, 0)) == PLUS)
14964 /* Use a different reg for the intermediate value, as
14965 it will be marked UNCHANGING. */
14966 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
14969 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
14972 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
14978 if (GET_CODE (offset) == CONST_INT)
14980 if (SMALL_INT (offset))
14981 return plus_constant (base, INTVAL (offset));
14982 else if (! reload_in_progress && ! reload_completed)
14983 offset = force_reg (Pmode, offset);
14986 rtx mem = force_const_mem (Pmode, orig);
14987 return machopic_legitimize_pic_address (mem, Pmode, reg);
14990 return gen_rtx (PLUS, Pmode, base, offset);
14993 /* Fall back on generic machopic code. */
14994 return machopic_legitimize_pic_address (orig, mode, reg);
14997 /* This is just a placeholder to make linking work without having to
14998 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
14999 ever needed for Darwin (not too likely!) this would have to get a
15000 real definition. */
15007 #endif /* TARGET_MACHO */
15010 static unsigned int
15011 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
15013 return default_section_type_flags_1 (decl, name, reloc,
15014 flag_pic || DEFAULT_ABI == ABI_AIX);
15017 /* Record an element in the table of global constructors. SYMBOL is
15018 a SYMBOL_REF of the function to be called; PRIORITY is a number
15019 between 0 and MAX_INIT_PRIORITY.
15021 This differs from default_named_section_asm_out_constructor in
15022 that we have special handling for -mrelocatable. */
15025 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
15027 const char *section = ".ctors";
15030 if (priority != DEFAULT_INIT_PRIORITY)
15032 sprintf (buf, ".ctors.%.5u",
15033 /* Invert the numbering so the linker puts us in the proper
15034 order; constructors are run from right to left, and the
15035 linker sorts in increasing order. */
15036 MAX_INIT_PRIORITY - priority);
15040 named_section_flags (section, SECTION_WRITE);
15041 assemble_align (POINTER_SIZE);
15043 if (TARGET_RELOCATABLE)
15045 fputs ("\t.long (", asm_out_file);
15046 output_addr_const (asm_out_file, symbol);
15047 fputs (")@fixup\n", asm_out_file);
15050 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15054 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
15056 const char *section = ".dtors";
15059 if (priority != DEFAULT_INIT_PRIORITY)
15061 sprintf (buf, ".dtors.%.5u",
15062 /* Invert the numbering so the linker puts us in the proper
15063 order; constructors are run from right to left, and the
15064 linker sorts in increasing order. */
15065 MAX_INIT_PRIORITY - priority);
15069 named_section_flags (section, SECTION_WRITE);
15070 assemble_align (POINTER_SIZE);
15072 if (TARGET_RELOCATABLE)
15074 fputs ("\t.long (", asm_out_file);
15075 output_addr_const (asm_out_file, symbol);
15076 fputs (")@fixup\n", asm_out_file);
15079 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
15083 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
15087 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
15088 ASM_OUTPUT_LABEL (file, name);
15089 fputs (DOUBLE_INT_ASM_OP, file);
15091 assemble_name (file, name);
15092 fputs (",.TOC.@tocbase,0\n\t.previous\n\t.size\t", file);
15093 assemble_name (file, name);
15094 fputs (",24\n\t.type\t.", file);
15095 assemble_name (file, name);
15096 fputs (",@function\n", file);
15097 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
15099 fputs ("\t.globl\t.", file);
15100 assemble_name (file, name);
15103 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15105 ASM_OUTPUT_LABEL (file, name);
15109 if (TARGET_RELOCATABLE
15110 && (get_pool_size () != 0 || current_function_profile)
15115 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
15117 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
15118 fprintf (file, "\t.long ");
15119 assemble_name (file, buf);
15121 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
15122 assemble_name (file, buf);
15126 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
15127 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
15129 if (DEFAULT_ABI == ABI_AIX)
15131 const char *desc_name, *orig_name;
15133 orig_name = (*targetm.strip_name_encoding) (name);
15134 desc_name = orig_name;
15135 while (*desc_name == '.')
15138 if (TREE_PUBLIC (decl))
15139 fprintf (file, "\t.globl %s\n", desc_name);
15141 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
15142 fprintf (file, "%s:\n", desc_name);
15143 fprintf (file, "\t.long %s\n", orig_name);
15144 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
15145 if (DEFAULT_ABI == ABI_AIX)
15146 fputs ("\t.long 0\n", file);
15147 fprintf (file, "\t.previous\n");
15149 ASM_OUTPUT_LABEL (file, name);
15155 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
15157 fputs (GLOBAL_ASM_OP, stream);
15158 RS6000_OUTPUT_BASENAME (stream, name);
15159 putc ('\n', stream);
15163 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags)
15166 static const char * const suffix[3] = { "PR", "RO", "RW" };
15168 if (flags & SECTION_CODE)
15170 else if (flags & SECTION_WRITE)
15175 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
15176 (flags & SECTION_CODE) ? "." : "",
15177 name, suffix[smclass], flags & SECTION_ENTSIZE);
15181 rs6000_xcoff_select_section (tree decl, int reloc,
15182 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15184 if (decl_readonly_section_1 (decl, reloc, 1))
15186 if (TREE_PUBLIC (decl))
15187 read_only_data_section ();
15189 read_only_private_data_section ();
15193 if (TREE_PUBLIC (decl))
15196 private_data_section ();
15201 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
15205 /* Use select_section for private and uninitialized data. */
15206 if (!TREE_PUBLIC (decl)
15207 || DECL_COMMON (decl)
15208 || DECL_INITIAL (decl) == NULL_TREE
15209 || DECL_INITIAL (decl) == error_mark_node
15210 || (flag_zero_initialized_in_bss
15211 && initializer_zerop (DECL_INITIAL (decl))))
15214 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
15215 name = (*targetm.strip_name_encoding) (name);
15216 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
15219 /* Select section for constant in constant pool.
15221 On RS/6000, all constants are in the private read-only data area.
15222 However, if this is being placed in the TOC it must be output as a
15226 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
15227 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
15229 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15232 read_only_private_data_section ();
15235 /* Remove any trailing [DS] or the like from the symbol name. */
15237 static const char *
15238 rs6000_xcoff_strip_name_encoding (const char *name)
15243 len = strlen (name);
15244 if (name[len - 1] == ']')
15245 return ggc_alloc_string (name, len - 4);
15250 /* Section attributes. AIX is always PIC. */
15252 static unsigned int
15253 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
15255 unsigned int align;
15256 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
15258 /* Align to at least UNIT size. */
15259 if (flags & SECTION_CODE)
15260 align = MIN_UNITS_PER_WORD;
15262 /* Increase alignment of large objects if not already stricter. */
15263 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
15264 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
15265 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
15267 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
15270 /* Output at beginning of assembler file.
15272 Initialize the section names for the RS/6000 at this point.
15274 Specify filename, including full path, to assembler.
15276 We want to go into the TOC section so at least one .toc will be emitted.
15277 Also, in order to output proper .bs/.es pairs, we need at least one static
15278 [RW] section emitted.
15280 Finally, declare mcount when profiling to make the assembler happy. */
15283 rs6000_xcoff_file_start (void)
15285 rs6000_gen_section_name (&xcoff_bss_section_name,
15286 main_input_filename, ".bss_");
15287 rs6000_gen_section_name (&xcoff_private_data_section_name,
15288 main_input_filename, ".rw_");
15289 rs6000_gen_section_name (&xcoff_read_only_section_name,
15290 main_input_filename, ".ro_");
15292 fputs ("\t.file\t", asm_out_file);
15293 output_quoted_string (asm_out_file, main_input_filename);
15294 fputc ('\n', asm_out_file);
15296 if (write_symbols != NO_DEBUG)
15297 private_data_section ();
15300 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
15301 rs6000_file_start ();
15304 /* Output at end of assembler file.
15305 On the RS/6000, referencing data should automatically pull in text. */
15308 rs6000_xcoff_file_end (void)
15311 fputs ("_section_.text:\n", asm_out_file);
15313 fputs (TARGET_32BIT
15314 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
15317 #endif /* TARGET_XCOFF */
15320 /* Cross-module name binding. Darwin does not support overriding
15321 functions at dynamic-link time. */
15324 rs6000_binds_local_p (tree decl)
15326 return default_binds_local_p_1 (decl, 0);
15330 /* Compute a (partial) cost for rtx X. Return true if the complete
15331 cost has been computed, and false if subexpressions should be
15332 scanned. In either case, *TOTAL contains the cost result. */
15335 rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED,
15340 /* On the RS/6000, if it is valid in the insn, it is free.
15341 So this always returns 0. */
15352 *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15353 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1))
15354 + 0x8000) >= 0x10000)
15355 && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15356 ? COSTS_N_INSNS (2)
15357 : COSTS_N_INSNS (1));
15363 *total = ((GET_CODE (XEXP (x, 1)) == CONST_INT
15364 && (INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0
15365 && ((INTVAL (XEXP (x, 1)) & 0xffff) != 0))
15366 ? COSTS_N_INSNS (2)
15367 : COSTS_N_INSNS (1));
15373 *total = COSTS_N_INSNS (2);
15376 switch (rs6000_cpu)
15378 case PROCESSOR_RIOS1:
15379 case PROCESSOR_PPC405:
15380 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15381 ? COSTS_N_INSNS (5)
15382 : (INTVAL (XEXP (x, 1)) >= -256
15383 && INTVAL (XEXP (x, 1)) <= 255)
15384 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15387 case PROCESSOR_PPC440:
15388 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15389 ? COSTS_N_INSNS (3)
15390 : COSTS_N_INSNS (2));
15393 case PROCESSOR_RS64A:
15394 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15395 ? GET_MODE (XEXP (x, 1)) != DImode
15396 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34)
15397 : (INTVAL (XEXP (x, 1)) >= -256
15398 && INTVAL (XEXP (x, 1)) <= 255)
15399 ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12));
15402 case PROCESSOR_RIOS2:
15403 case PROCESSOR_MPCCORE:
15404 case PROCESSOR_PPC604e:
15405 *total = COSTS_N_INSNS (2);
15408 case PROCESSOR_PPC601:
15409 *total = COSTS_N_INSNS (5);
15412 case PROCESSOR_PPC603:
15413 case PROCESSOR_PPC7400:
15414 case PROCESSOR_PPC750:
15415 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15416 ? COSTS_N_INSNS (5)
15417 : (INTVAL (XEXP (x, 1)) >= -256
15418 && INTVAL (XEXP (x, 1)) <= 255)
15419 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3));
15422 case PROCESSOR_PPC7450:
15423 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15424 ? COSTS_N_INSNS (4)
15425 : COSTS_N_INSNS (3));
15428 case PROCESSOR_PPC403:
15429 case PROCESSOR_PPC604:
15430 case PROCESSOR_PPC8540:
15431 *total = COSTS_N_INSNS (4);
15434 case PROCESSOR_PPC620:
15435 case PROCESSOR_PPC630:
15436 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15437 ? GET_MODE (XEXP (x, 1)) != DImode
15438 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7)
15439 : (INTVAL (XEXP (x, 1)) >= -256
15440 && INTVAL (XEXP (x, 1)) <= 255)
15441 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4));
15444 case PROCESSOR_POWER4:
15445 *total = (GET_CODE (XEXP (x, 1)) != CONST_INT
15446 ? GET_MODE (XEXP (x, 1)) != DImode
15447 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)
15448 : COSTS_N_INSNS (2));
15457 if (GET_CODE (XEXP (x, 1)) == CONST_INT
15458 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
15460 *total = COSTS_N_INSNS (2);
15467 switch (rs6000_cpu)
15469 case PROCESSOR_RIOS1:
15470 *total = COSTS_N_INSNS (19);
15473 case PROCESSOR_RIOS2:
15474 *total = COSTS_N_INSNS (13);
15477 case PROCESSOR_RS64A:
15478 *total = (GET_MODE (XEXP (x, 1)) != DImode
15479 ? COSTS_N_INSNS (65)
15480 : COSTS_N_INSNS (67));
15483 case PROCESSOR_MPCCORE:
15484 *total = COSTS_N_INSNS (6);
15487 case PROCESSOR_PPC403:
15488 *total = COSTS_N_INSNS (33);
15491 case PROCESSOR_PPC405:
15492 *total = COSTS_N_INSNS (35);
15495 case PROCESSOR_PPC440:
15496 *total = COSTS_N_INSNS (34);
15499 case PROCESSOR_PPC601:
15500 *total = COSTS_N_INSNS (36);
15503 case PROCESSOR_PPC603:
15504 *total = COSTS_N_INSNS (37);
15507 case PROCESSOR_PPC604:
15508 case PROCESSOR_PPC604e:
15509 *total = COSTS_N_INSNS (20);
15512 case PROCESSOR_PPC620:
15513 case PROCESSOR_PPC630:
15514 *total = (GET_MODE (XEXP (x, 1)) != DImode
15515 ? COSTS_N_INSNS (21)
15516 : COSTS_N_INSNS (37));
15519 case PROCESSOR_PPC750:
15520 case PROCESSOR_PPC8540:
15521 case PROCESSOR_PPC7400:
15522 *total = COSTS_N_INSNS (19);
15525 case PROCESSOR_PPC7450:
15526 *total = COSTS_N_INSNS (23);
15529 case PROCESSOR_POWER4:
15530 *total = (GET_MODE (XEXP (x, 1)) != DImode
15531 ? COSTS_N_INSNS (18)
15532 : COSTS_N_INSNS (34));
15540 *total = COSTS_N_INSNS (4);
15544 /* MEM should be slightly more expensive than (plus (reg) (const)) */
15553 /* A C expression returning the cost of moving data from a register of class
15554 CLASS1 to one of CLASS2. */
15557 rs6000_register_move_cost (enum machine_mode mode,
15558 enum reg_class from, enum reg_class to)
15560 /* Moves from/to GENERAL_REGS. */
15561 if (reg_classes_intersect_p (to, GENERAL_REGS)
15562 || reg_classes_intersect_p (from, GENERAL_REGS))
15564 if (! reg_classes_intersect_p (to, GENERAL_REGS))
15567 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
15568 return (rs6000_memory_move_cost (mode, from, 0)
15569 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
15571 /* It's more expensive to move CR_REGS than CR0_REGS because of the shift...*/
15572 else if (from == CR_REGS)
15576 /* A move will cost one instruction per GPR moved. */
15577 return 2 * HARD_REGNO_NREGS (0, mode);
15580 /* Moving between two similar registers is just one instruction. */
15581 else if (reg_classes_intersect_p (to, from))
15582 return mode == TFmode ? 4 : 2;
15584 /* Everything else has to go through GENERAL_REGS. */
15586 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
15587 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
15590 /* A C expressions returning the cost of moving data of MODE from a register to
15594 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
15595 int in ATTRIBUTE_UNUSED)
15597 if (reg_classes_intersect_p (class, GENERAL_REGS))
15598 return 4 * HARD_REGNO_NREGS (0, mode);
15599 else if (reg_classes_intersect_p (class, FLOAT_REGS))
15600 return 4 * HARD_REGNO_NREGS (32, mode);
15601 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
15602 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
15604 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
15607 /* Return an RTX representing where to find the function value of a
15608 function returning MODE. */
15610 rs6000_complex_function_value (enum machine_mode mode)
15612 unsigned int regno;
15614 enum machine_mode inner = GET_MODE_INNER (mode);
15616 if (FLOAT_MODE_P (mode))
15617 regno = FP_ARG_RETURN;
15620 regno = GP_ARG_RETURN;
15622 /* 32-bit is OK since it'll go in r3/r4. */
15624 && GET_MODE_BITSIZE (inner) >= 32)
15625 return gen_rtx_REG (mode, regno);
15628 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
15630 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
15631 GEN_INT (GET_MODE_UNIT_SIZE (inner)));
15632 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
15635 /* Define how to find the value returned by a function.
15636 VALTYPE is the data type of the value (as a tree).
15637 If the precise function being called is known, FUNC is its FUNCTION_DECL;
15638 otherwise, FUNC is 0.
15640 On the SPE, both FPs and vectors are returned in r3.
15642 On RS/6000 an integer value is in r3 and a floating-point value is in
15643 fp1, unless -msoft-float. */
15646 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
15648 enum machine_mode mode;
15649 unsigned int regno;
15651 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
15653 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
15654 return gen_rtx_PARALLEL (DImode,
15656 gen_rtx_EXPR_LIST (VOIDmode,
15657 gen_rtx_REG (SImode, GP_ARG_RETURN),
15659 gen_rtx_EXPR_LIST (VOIDmode,
15660 gen_rtx_REG (SImode,
15661 GP_ARG_RETURN + 1),
15665 if ((INTEGRAL_TYPE_P (valtype)
15666 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
15667 || POINTER_TYPE_P (valtype))
15668 mode = TARGET_32BIT ? SImode : DImode;
15670 mode = TYPE_MODE (valtype);
15672 if (TREE_CODE (valtype) == REAL_TYPE && TARGET_HARD_FLOAT && TARGET_FPRS)
15673 regno = FP_ARG_RETURN;
15674 else if (TREE_CODE (valtype) == COMPLEX_TYPE
15675 && TARGET_HARD_FLOAT
15676 && SPLIT_COMPLEX_ARGS)
15677 return rs6000_complex_function_value (mode);
15678 else if (TREE_CODE (valtype) == VECTOR_TYPE && TARGET_ALTIVEC)
15679 regno = ALTIVEC_ARG_RETURN;
15681 regno = GP_ARG_RETURN;
15683 return gen_rtx_REG (mode, regno);
15686 /* Define how to find the value returned by a library function
15687 assuming the value has mode MODE. */
15689 rs6000_libcall_value (enum machine_mode mode)
15691 unsigned int regno;
15693 if (GET_MODE_CLASS (mode) == MODE_FLOAT
15694 && TARGET_HARD_FLOAT && TARGET_FPRS)
15695 regno = FP_ARG_RETURN;
15696 else if (ALTIVEC_VECTOR_MODE (mode))
15697 regno = ALTIVEC_ARG_RETURN;
15698 else if (COMPLEX_MODE_P (mode) && SPLIT_COMPLEX_ARGS)
15699 return rs6000_complex_function_value (mode);
15701 regno = GP_ARG_RETURN;
15703 return gen_rtx_REG (mode, regno);
15706 /* Define the offset between two registers, FROM to be eliminated and its
15707 replacement TO, at the start of a routine. */
15709 rs6000_initial_elimination_offset (int from, int to)
15711 rs6000_stack_t *info = rs6000_stack_info ();
15712 HOST_WIDE_INT offset;
15714 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
15715 offset = info->push_p ? 0 : -info->total_size;
15716 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
15717 offset = info->total_size;
15718 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
15719 offset = info->push_p ? info->total_size : 0;
15720 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
15728 /* Return true if TYPE is of type __ev64_opaque__. */
15731 is_ev64_opaque_type (tree type)
15734 && (type == opaque_V2SI_type_node
15735 || type == opaque_V2SF_type_node
15736 || type == opaque_p_V2SI_type_node));
15740 rs6000_dwarf_register_span (rtx reg)
15744 if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg)))
15747 regno = REGNO (reg);
15749 /* The duality of the SPE register size wreaks all kinds of havoc.
15750 This is a way of distinguishing r0 in 32-bits from r0 in
15753 gen_rtx_PARALLEL (VOIDmode,
15756 gen_rtx_REG (SImode, regno + 1200),
15757 gen_rtx_REG (SImode, regno))
15759 gen_rtx_REG (SImode, regno),
15760 gen_rtx_REG (SImode, regno + 1200)));
15763 #include "gt-rs6000.h"