1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
42 #include "basic-block.h"
43 #include "integrate.h"
44 #include "diagnostic-core.h"
50 #include "target-def.h"
51 #include "common/common-target.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
56 #include "sched-int.h"
58 #include "tree-flow.h"
61 #include "tm-constrs.h"
64 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
67 #include "gstab.h" /* for N_SLINE */
70 #ifndef TARGET_NO_PROTOTYPE
71 #define TARGET_NO_PROTOTYPE 0
74 #define min(A,B) ((A) < (B) ? (A) : (B))
75 #define max(A,B) ((A) > (B) ? (A) : (B))
77 /* Structure used to define the rs6000 stack */
78 typedef struct rs6000_stack {
79 int reload_completed; /* stack info won't change from here on */
80 int first_gp_reg_save; /* first callee saved GP register used */
81 int first_fp_reg_save; /* first callee saved FP register used */
82 int first_altivec_reg_save; /* first callee saved AltiVec register used */
83 int lr_save_p; /* true if the link reg needs to be saved */
84 int cr_save_p; /* true if the CR reg needs to be saved */
85 unsigned int vrsave_mask; /* mask of vec registers to save */
86 int push_p; /* true if we need to allocate stack space */
87 int calls_p; /* true if the function makes any calls */
88 int world_save_p; /* true if we're saving *everything*:
89 r13-r31, cr, f14-f31, vrsave, v20-v31 */
90 enum rs6000_abi abi; /* which ABI to use */
91 int gp_save_offset; /* offset to save GP regs from initial SP */
92 int fp_save_offset; /* offset to save FP regs from initial SP */
93 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
94 int lr_save_offset; /* offset to save LR from initial SP */
95 int cr_save_offset; /* offset to save CR from initial SP */
96 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
97 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
98 int varargs_save_offset; /* offset to save the varargs registers */
99 int ehrd_offset; /* offset to EH return data */
100 int reg_size; /* register size (4 or 8) */
101 HOST_WIDE_INT vars_size; /* variable save area size */
102 int parm_size; /* outgoing parameter size */
103 int save_size; /* save area size */
104 int fixed_size; /* fixed size of stack frame */
105 int gp_size; /* size of saved GP registers */
106 int fp_size; /* size of saved FP registers */
107 int altivec_size; /* size of saved AltiVec registers */
108 int cr_size; /* size to hold CR if not in save_size */
109 int vrsave_size; /* size to hold VRSAVE if not in save_size */
110 int altivec_padding_size; /* size of altivec alignment padding if
112 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
113 int spe_padding_size;
114 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
115 int spe_64bit_regs_used;
119 /* A C structure for machine-specific, per-function data.
120 This is added to the cfun structure. */
121 typedef struct GTY(()) machine_function
123 /* Some local-dynamic symbol. */
124 const char *some_ld_name;
125 /* Whether the instruction chain has been scanned already. */
126 int insn_chain_scanned_p;
127 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
128 int ra_needs_full_frame;
129 /* Flags if __builtin_return_address (0) was used. */
131 /* Cache lr_save_p after expansion of builtin_eh_return. */
133 /* Whether we need to save the TOC to the reserved stack location in the
134 function prologue. */
135 bool save_toc_in_prologue;
136 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
137 varargs save area. */
138 HOST_WIDE_INT varargs_save_offset;
139 /* Temporary stack slot to use for SDmode copies. This slot is
140 64-bits wide and is allocated early enough so that the offset
141 does not overflow the 16-bit load/store offset field. */
142 rtx sdmode_stack_slot;
145 /* Support targetm.vectorize.builtin_mask_for_load. */
146 static GTY(()) tree altivec_builtin_mask_for_load;
148 /* Set to nonzero once AIX common-mode calls have been defined. */
149 static GTY(()) int common_mode_defined;
151 /* Label number of label created for -mrelocatable, to call to so we can
152 get the address of the GOT section */
153 static int rs6000_pic_labelno;
156 /* Counter for labels which are to be placed in .fixup. */
157 int fixuplabelno = 0;
160 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
163 /* Specify the machine mode that pointers have. After generation of rtl, the
164 compiler makes no further distinction between pointers and any other objects
165 of this machine mode. The type is unsigned since not all things that
166 include rs6000.h also include machmode.h. */
167 unsigned rs6000_pmode;
169 /* Width in bits of a pointer. */
170 unsigned rs6000_pointer_size;
172 #ifdef HAVE_AS_GNU_ATTRIBUTE
173 /* Flag whether floating point values have been passed/returned. */
174 static bool rs6000_passes_float;
175 /* Flag whether vector values have been passed/returned. */
176 static bool rs6000_passes_vector;
177 /* Flag whether small (<= 8 byte) structures have been returned. */
178 static bool rs6000_returns_struct;
181 /* Value is TRUE if register/mode pair is acceptable. */
182 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
184 /* Maximum number of registers needed for a given register class and mode. */
185 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
187 /* How many registers are needed for a given register and mode. */
188 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
190 /* Map register number to register class. */
191 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
193 /* Reload functions based on the type and the vector unit. */
194 static enum insn_code rs6000_vector_reload[NUM_MACHINE_MODES][2];
196 static int dbg_cost_ctrl;
198 /* Built in types. */
199 tree rs6000_builtin_types[RS6000_BTI_MAX];
200 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
202 /* Flag to say the TOC is initialized */
204 char toc_label_name[10];
206 /* Cached value of rs6000_variable_issue. This is cached in
207 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
208 static short cached_can_issue_more;
210 static GTY(()) section *read_only_data_section;
211 static GTY(()) section *private_data_section;
212 static GTY(()) section *read_only_private_data_section;
213 static GTY(()) section *sdata2_section;
214 static GTY(()) section *toc_section;
216 struct builtin_description
218 const unsigned int mask;
219 const enum insn_code icode;
220 const char *const name;
221 const enum rs6000_builtins code;
224 /* Describe the vector unit used for modes. */
225 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
226 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
228 /* Register classes for various constraints that are based on the target
230 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
232 /* Describe the alignment of a vector. */
233 int rs6000_vector_align[NUM_MACHINE_MODES];
235 /* Map selected modes to types for builtins. */
236 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
238 /* What modes to automatically generate reciprocal divide estimate (fre) and
239 reciprocal sqrt (frsqrte) for. */
240 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
242 /* Masks to determine which reciprocal esitmate instructions to generate
244 enum rs6000_recip_mask {
245 RECIP_SF_DIV = 0x001, /* Use divide estimate */
246 RECIP_DF_DIV = 0x002,
247 RECIP_V4SF_DIV = 0x004,
248 RECIP_V2DF_DIV = 0x008,
250 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
251 RECIP_DF_RSQRT = 0x020,
252 RECIP_V4SF_RSQRT = 0x040,
253 RECIP_V2DF_RSQRT = 0x080,
255 /* Various combination of flags for -mrecip=xxx. */
257 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
258 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
259 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
261 RECIP_HIGH_PRECISION = RECIP_ALL,
263 /* On low precision machines like the power5, don't enable double precision
264 reciprocal square root estimate, since it isn't accurate enough. */
265 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
268 /* -mrecip options. */
271 const char *string; /* option name */
272 unsigned int mask; /* mask bits to set */
273 } recip_options[] = {
274 { "all", RECIP_ALL },
275 { "none", RECIP_NONE },
276 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
278 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
279 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
280 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
281 | RECIP_V2DF_RSQRT) },
282 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
283 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
286 /* 2 argument gen function typedef. */
287 typedef rtx (*gen_2arg_fn_t) (rtx, rtx, rtx);
289 /* Pointer to function (in rs6000-c.c) that can define or undefine target
290 macros that have changed. Languages that don't support the preprocessor
291 don't link in rs6000-c.c, so we can't call it directly. */
292 void (*rs6000_target_modify_macros_ptr) (bool, int, unsigned);
295 /* Target cpu costs. */
297 struct processor_costs {
298 const int mulsi; /* cost of SImode multiplication. */
299 const int mulsi_const; /* cost of SImode multiplication by constant. */
300 const int mulsi_const9; /* cost of SImode mult by short constant. */
301 const int muldi; /* cost of DImode multiplication. */
302 const int divsi; /* cost of SImode division. */
303 const int divdi; /* cost of DImode division. */
304 const int fp; /* cost of simple SFmode and DFmode insns. */
305 const int dmul; /* cost of DFmode multiplication (and fmadd). */
306 const int sdiv; /* cost of SFmode division (fdivs). */
307 const int ddiv; /* cost of DFmode division (fdiv). */
308 const int cache_line_size; /* cache line size in bytes. */
309 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
310 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
311 const int simultaneous_prefetches; /* number of parallel prefetch
315 const struct processor_costs *rs6000_cost;
317 /* Processor costs (relative to an add) */
319 /* Instruction size costs on 32bit processors. */
321 struct processor_costs size32_cost = {
322 COSTS_N_INSNS (1), /* mulsi */
323 COSTS_N_INSNS (1), /* mulsi_const */
324 COSTS_N_INSNS (1), /* mulsi_const9 */
325 COSTS_N_INSNS (1), /* muldi */
326 COSTS_N_INSNS (1), /* divsi */
327 COSTS_N_INSNS (1), /* divdi */
328 COSTS_N_INSNS (1), /* fp */
329 COSTS_N_INSNS (1), /* dmul */
330 COSTS_N_INSNS (1), /* sdiv */
331 COSTS_N_INSNS (1), /* ddiv */
338 /* Instruction size costs on 64bit processors. */
340 struct processor_costs size64_cost = {
341 COSTS_N_INSNS (1), /* mulsi */
342 COSTS_N_INSNS (1), /* mulsi_const */
343 COSTS_N_INSNS (1), /* mulsi_const9 */
344 COSTS_N_INSNS (1), /* muldi */
345 COSTS_N_INSNS (1), /* divsi */
346 COSTS_N_INSNS (1), /* divdi */
347 COSTS_N_INSNS (1), /* fp */
348 COSTS_N_INSNS (1), /* dmul */
349 COSTS_N_INSNS (1), /* sdiv */
350 COSTS_N_INSNS (1), /* ddiv */
357 /* Instruction costs on RIOS1 processors. */
359 struct processor_costs rios1_cost = {
360 COSTS_N_INSNS (5), /* mulsi */
361 COSTS_N_INSNS (4), /* mulsi_const */
362 COSTS_N_INSNS (3), /* mulsi_const9 */
363 COSTS_N_INSNS (5), /* muldi */
364 COSTS_N_INSNS (19), /* divsi */
365 COSTS_N_INSNS (19), /* divdi */
366 COSTS_N_INSNS (2), /* fp */
367 COSTS_N_INSNS (2), /* dmul */
368 COSTS_N_INSNS (19), /* sdiv */
369 COSTS_N_INSNS (19), /* ddiv */
370 128, /* cache line size */
376 /* Instruction costs on RIOS2 processors. */
378 struct processor_costs rios2_cost = {
379 COSTS_N_INSNS (2), /* mulsi */
380 COSTS_N_INSNS (2), /* mulsi_const */
381 COSTS_N_INSNS (2), /* mulsi_const9 */
382 COSTS_N_INSNS (2), /* muldi */
383 COSTS_N_INSNS (13), /* divsi */
384 COSTS_N_INSNS (13), /* divdi */
385 COSTS_N_INSNS (2), /* fp */
386 COSTS_N_INSNS (2), /* dmul */
387 COSTS_N_INSNS (17), /* sdiv */
388 COSTS_N_INSNS (17), /* ddiv */
389 256, /* cache line size */
395 /* Instruction costs on RS64A processors. */
397 struct processor_costs rs64a_cost = {
398 COSTS_N_INSNS (20), /* mulsi */
399 COSTS_N_INSNS (12), /* mulsi_const */
400 COSTS_N_INSNS (8), /* mulsi_const9 */
401 COSTS_N_INSNS (34), /* muldi */
402 COSTS_N_INSNS (65), /* divsi */
403 COSTS_N_INSNS (67), /* divdi */
404 COSTS_N_INSNS (4), /* fp */
405 COSTS_N_INSNS (4), /* dmul */
406 COSTS_N_INSNS (31), /* sdiv */
407 COSTS_N_INSNS (31), /* ddiv */
408 128, /* cache line size */
414 /* Instruction costs on MPCCORE processors. */
416 struct processor_costs mpccore_cost = {
417 COSTS_N_INSNS (2), /* mulsi */
418 COSTS_N_INSNS (2), /* mulsi_const */
419 COSTS_N_INSNS (2), /* mulsi_const9 */
420 COSTS_N_INSNS (2), /* muldi */
421 COSTS_N_INSNS (6), /* divsi */
422 COSTS_N_INSNS (6), /* divdi */
423 COSTS_N_INSNS (4), /* fp */
424 COSTS_N_INSNS (5), /* dmul */
425 COSTS_N_INSNS (10), /* sdiv */
426 COSTS_N_INSNS (17), /* ddiv */
427 32, /* cache line size */
433 /* Instruction costs on PPC403 processors. */
435 struct processor_costs ppc403_cost = {
436 COSTS_N_INSNS (4), /* mulsi */
437 COSTS_N_INSNS (4), /* mulsi_const */
438 COSTS_N_INSNS (4), /* mulsi_const9 */
439 COSTS_N_INSNS (4), /* muldi */
440 COSTS_N_INSNS (33), /* divsi */
441 COSTS_N_INSNS (33), /* divdi */
442 COSTS_N_INSNS (11), /* fp */
443 COSTS_N_INSNS (11), /* dmul */
444 COSTS_N_INSNS (11), /* sdiv */
445 COSTS_N_INSNS (11), /* ddiv */
446 32, /* cache line size */
452 /* Instruction costs on PPC405 processors. */
454 struct processor_costs ppc405_cost = {
455 COSTS_N_INSNS (5), /* mulsi */
456 COSTS_N_INSNS (4), /* mulsi_const */
457 COSTS_N_INSNS (3), /* mulsi_const9 */
458 COSTS_N_INSNS (5), /* muldi */
459 COSTS_N_INSNS (35), /* divsi */
460 COSTS_N_INSNS (35), /* divdi */
461 COSTS_N_INSNS (11), /* fp */
462 COSTS_N_INSNS (11), /* dmul */
463 COSTS_N_INSNS (11), /* sdiv */
464 COSTS_N_INSNS (11), /* ddiv */
465 32, /* cache line size */
471 /* Instruction costs on PPC440 processors. */
473 struct processor_costs ppc440_cost = {
474 COSTS_N_INSNS (3), /* mulsi */
475 COSTS_N_INSNS (2), /* mulsi_const */
476 COSTS_N_INSNS (2), /* mulsi_const9 */
477 COSTS_N_INSNS (3), /* muldi */
478 COSTS_N_INSNS (34), /* divsi */
479 COSTS_N_INSNS (34), /* divdi */
480 COSTS_N_INSNS (5), /* fp */
481 COSTS_N_INSNS (5), /* dmul */
482 COSTS_N_INSNS (19), /* sdiv */
483 COSTS_N_INSNS (33), /* ddiv */
484 32, /* cache line size */
490 /* Instruction costs on PPC476 processors. */
492 struct processor_costs ppc476_cost = {
493 COSTS_N_INSNS (4), /* mulsi */
494 COSTS_N_INSNS (4), /* mulsi_const */
495 COSTS_N_INSNS (4), /* mulsi_const9 */
496 COSTS_N_INSNS (4), /* muldi */
497 COSTS_N_INSNS (11), /* divsi */
498 COSTS_N_INSNS (11), /* divdi */
499 COSTS_N_INSNS (6), /* fp */
500 COSTS_N_INSNS (6), /* dmul */
501 COSTS_N_INSNS (19), /* sdiv */
502 COSTS_N_INSNS (33), /* ddiv */
503 32, /* l1 cache line size */
509 /* Instruction costs on PPC601 processors. */
511 struct processor_costs ppc601_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (5), /* mulsi_const */
514 COSTS_N_INSNS (5), /* mulsi_const9 */
515 COSTS_N_INSNS (5), /* muldi */
516 COSTS_N_INSNS (36), /* divsi */
517 COSTS_N_INSNS (36), /* divdi */
518 COSTS_N_INSNS (4), /* fp */
519 COSTS_N_INSNS (5), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (31), /* ddiv */
522 32, /* cache line size */
528 /* Instruction costs on PPC603 processors. */
530 struct processor_costs ppc603_cost = {
531 COSTS_N_INSNS (5), /* mulsi */
532 COSTS_N_INSNS (3), /* mulsi_const */
533 COSTS_N_INSNS (2), /* mulsi_const9 */
534 COSTS_N_INSNS (5), /* muldi */
535 COSTS_N_INSNS (37), /* divsi */
536 COSTS_N_INSNS (37), /* divdi */
537 COSTS_N_INSNS (3), /* fp */
538 COSTS_N_INSNS (4), /* dmul */
539 COSTS_N_INSNS (18), /* sdiv */
540 COSTS_N_INSNS (33), /* ddiv */
541 32, /* cache line size */
547 /* Instruction costs on PPC604 processors. */
549 struct processor_costs ppc604_cost = {
550 COSTS_N_INSNS (4), /* mulsi */
551 COSTS_N_INSNS (4), /* mulsi_const */
552 COSTS_N_INSNS (4), /* mulsi_const9 */
553 COSTS_N_INSNS (4), /* muldi */
554 COSTS_N_INSNS (20), /* divsi */
555 COSTS_N_INSNS (20), /* divdi */
556 COSTS_N_INSNS (3), /* fp */
557 COSTS_N_INSNS (3), /* dmul */
558 COSTS_N_INSNS (18), /* sdiv */
559 COSTS_N_INSNS (32), /* ddiv */
560 32, /* cache line size */
566 /* Instruction costs on PPC604e processors. */
568 struct processor_costs ppc604e_cost = {
569 COSTS_N_INSNS (2), /* mulsi */
570 COSTS_N_INSNS (2), /* mulsi_const */
571 COSTS_N_INSNS (2), /* mulsi_const9 */
572 COSTS_N_INSNS (2), /* muldi */
573 COSTS_N_INSNS (20), /* divsi */
574 COSTS_N_INSNS (20), /* divdi */
575 COSTS_N_INSNS (3), /* fp */
576 COSTS_N_INSNS (3), /* dmul */
577 COSTS_N_INSNS (18), /* sdiv */
578 COSTS_N_INSNS (32), /* ddiv */
579 32, /* cache line size */
585 /* Instruction costs on PPC620 processors. */
587 struct processor_costs ppc620_cost = {
588 COSTS_N_INSNS (5), /* mulsi */
589 COSTS_N_INSNS (4), /* mulsi_const */
590 COSTS_N_INSNS (3), /* mulsi_const9 */
591 COSTS_N_INSNS (7), /* muldi */
592 COSTS_N_INSNS (21), /* divsi */
593 COSTS_N_INSNS (37), /* divdi */
594 COSTS_N_INSNS (3), /* fp */
595 COSTS_N_INSNS (3), /* dmul */
596 COSTS_N_INSNS (18), /* sdiv */
597 COSTS_N_INSNS (32), /* ddiv */
598 128, /* cache line size */
604 /* Instruction costs on PPC630 processors. */
606 struct processor_costs ppc630_cost = {
607 COSTS_N_INSNS (5), /* mulsi */
608 COSTS_N_INSNS (4), /* mulsi_const */
609 COSTS_N_INSNS (3), /* mulsi_const9 */
610 COSTS_N_INSNS (7), /* muldi */
611 COSTS_N_INSNS (21), /* divsi */
612 COSTS_N_INSNS (37), /* divdi */
613 COSTS_N_INSNS (3), /* fp */
614 COSTS_N_INSNS (3), /* dmul */
615 COSTS_N_INSNS (17), /* sdiv */
616 COSTS_N_INSNS (21), /* ddiv */
617 128, /* cache line size */
623 /* Instruction costs on Cell processor. */
624 /* COSTS_N_INSNS (1) ~ one add. */
626 struct processor_costs ppccell_cost = {
627 COSTS_N_INSNS (9/2)+2, /* mulsi */
628 COSTS_N_INSNS (6/2), /* mulsi_const */
629 COSTS_N_INSNS (6/2), /* mulsi_const9 */
630 COSTS_N_INSNS (15/2)+2, /* muldi */
631 COSTS_N_INSNS (38/2), /* divsi */
632 COSTS_N_INSNS (70/2), /* divdi */
633 COSTS_N_INSNS (10/2), /* fp */
634 COSTS_N_INSNS (10/2), /* dmul */
635 COSTS_N_INSNS (74/2), /* sdiv */
636 COSTS_N_INSNS (74/2), /* ddiv */
637 128, /* cache line size */
643 /* Instruction costs on PPC750 and PPC7400 processors. */
645 struct processor_costs ppc750_cost = {
646 COSTS_N_INSNS (5), /* mulsi */
647 COSTS_N_INSNS (3), /* mulsi_const */
648 COSTS_N_INSNS (2), /* mulsi_const9 */
649 COSTS_N_INSNS (5), /* muldi */
650 COSTS_N_INSNS (17), /* divsi */
651 COSTS_N_INSNS (17), /* divdi */
652 COSTS_N_INSNS (3), /* fp */
653 COSTS_N_INSNS (3), /* dmul */
654 COSTS_N_INSNS (17), /* sdiv */
655 COSTS_N_INSNS (31), /* ddiv */
656 32, /* cache line size */
662 /* Instruction costs on PPC7450 processors. */
664 struct processor_costs ppc7450_cost = {
665 COSTS_N_INSNS (4), /* mulsi */
666 COSTS_N_INSNS (3), /* mulsi_const */
667 COSTS_N_INSNS (3), /* mulsi_const9 */
668 COSTS_N_INSNS (4), /* muldi */
669 COSTS_N_INSNS (23), /* divsi */
670 COSTS_N_INSNS (23), /* divdi */
671 COSTS_N_INSNS (5), /* fp */
672 COSTS_N_INSNS (5), /* dmul */
673 COSTS_N_INSNS (21), /* sdiv */
674 COSTS_N_INSNS (35), /* ddiv */
675 32, /* cache line size */
681 /* Instruction costs on PPC8540 processors. */
683 struct processor_costs ppc8540_cost = {
684 COSTS_N_INSNS (4), /* mulsi */
685 COSTS_N_INSNS (4), /* mulsi_const */
686 COSTS_N_INSNS (4), /* mulsi_const9 */
687 COSTS_N_INSNS (4), /* muldi */
688 COSTS_N_INSNS (19), /* divsi */
689 COSTS_N_INSNS (19), /* divdi */
690 COSTS_N_INSNS (4), /* fp */
691 COSTS_N_INSNS (4), /* dmul */
692 COSTS_N_INSNS (29), /* sdiv */
693 COSTS_N_INSNS (29), /* ddiv */
694 32, /* cache line size */
697 1, /* prefetch streams /*/
700 /* Instruction costs on E300C2 and E300C3 cores. */
702 struct processor_costs ppce300c2c3_cost = {
703 COSTS_N_INSNS (4), /* mulsi */
704 COSTS_N_INSNS (4), /* mulsi_const */
705 COSTS_N_INSNS (4), /* mulsi_const9 */
706 COSTS_N_INSNS (4), /* muldi */
707 COSTS_N_INSNS (19), /* divsi */
708 COSTS_N_INSNS (19), /* divdi */
709 COSTS_N_INSNS (3), /* fp */
710 COSTS_N_INSNS (4), /* dmul */
711 COSTS_N_INSNS (18), /* sdiv */
712 COSTS_N_INSNS (33), /* ddiv */
716 1, /* prefetch streams /*/
719 /* Instruction costs on PPCE500MC processors. */
721 struct processor_costs ppce500mc_cost = {
722 COSTS_N_INSNS (4), /* mulsi */
723 COSTS_N_INSNS (4), /* mulsi_const */
724 COSTS_N_INSNS (4), /* mulsi_const9 */
725 COSTS_N_INSNS (4), /* muldi */
726 COSTS_N_INSNS (14), /* divsi */
727 COSTS_N_INSNS (14), /* divdi */
728 COSTS_N_INSNS (8), /* fp */
729 COSTS_N_INSNS (10), /* dmul */
730 COSTS_N_INSNS (36), /* sdiv */
731 COSTS_N_INSNS (66), /* ddiv */
732 64, /* cache line size */
735 1, /* prefetch streams /*/
738 /* Instruction costs on PPCE500MC64 processors. */
740 struct processor_costs ppce500mc64_cost = {
741 COSTS_N_INSNS (4), /* mulsi */
742 COSTS_N_INSNS (4), /* mulsi_const */
743 COSTS_N_INSNS (4), /* mulsi_const9 */
744 COSTS_N_INSNS (4), /* muldi */
745 COSTS_N_INSNS (14), /* divsi */
746 COSTS_N_INSNS (14), /* divdi */
747 COSTS_N_INSNS (4), /* fp */
748 COSTS_N_INSNS (10), /* dmul */
749 COSTS_N_INSNS (36), /* sdiv */
750 COSTS_N_INSNS (66), /* ddiv */
751 64, /* cache line size */
754 1, /* prefetch streams /*/
757 /* Instruction costs on AppliedMicro Titan processors. */
759 struct processor_costs titan_cost = {
760 COSTS_N_INSNS (5), /* mulsi */
761 COSTS_N_INSNS (5), /* mulsi_const */
762 COSTS_N_INSNS (5), /* mulsi_const9 */
763 COSTS_N_INSNS (5), /* muldi */
764 COSTS_N_INSNS (18), /* divsi */
765 COSTS_N_INSNS (18), /* divdi */
766 COSTS_N_INSNS (10), /* fp */
767 COSTS_N_INSNS (10), /* dmul */
768 COSTS_N_INSNS (46), /* sdiv */
769 COSTS_N_INSNS (72), /* ddiv */
770 32, /* cache line size */
773 1, /* prefetch streams /*/
776 /* Instruction costs on POWER4 and POWER5 processors. */
778 struct processor_costs power4_cost = {
779 COSTS_N_INSNS (3), /* mulsi */
780 COSTS_N_INSNS (2), /* mulsi_const */
781 COSTS_N_INSNS (2), /* mulsi_const9 */
782 COSTS_N_INSNS (4), /* muldi */
783 COSTS_N_INSNS (18), /* divsi */
784 COSTS_N_INSNS (34), /* divdi */
785 COSTS_N_INSNS (3), /* fp */
786 COSTS_N_INSNS (3), /* dmul */
787 COSTS_N_INSNS (17), /* sdiv */
788 COSTS_N_INSNS (17), /* ddiv */
789 128, /* cache line size */
792 8, /* prefetch streams /*/
795 /* Instruction costs on POWER6 processors. */
797 struct processor_costs power6_cost = {
798 COSTS_N_INSNS (8), /* mulsi */
799 COSTS_N_INSNS (8), /* mulsi_const */
800 COSTS_N_INSNS (8), /* mulsi_const9 */
801 COSTS_N_INSNS (8), /* muldi */
802 COSTS_N_INSNS (22), /* divsi */
803 COSTS_N_INSNS (28), /* divdi */
804 COSTS_N_INSNS (3), /* fp */
805 COSTS_N_INSNS (3), /* dmul */
806 COSTS_N_INSNS (13), /* sdiv */
807 COSTS_N_INSNS (16), /* ddiv */
808 128, /* cache line size */
811 16, /* prefetch streams */
814 /* Instruction costs on POWER7 processors. */
816 struct processor_costs power7_cost = {
817 COSTS_N_INSNS (2), /* mulsi */
818 COSTS_N_INSNS (2), /* mulsi_const */
819 COSTS_N_INSNS (2), /* mulsi_const9 */
820 COSTS_N_INSNS (2), /* muldi */
821 COSTS_N_INSNS (18), /* divsi */
822 COSTS_N_INSNS (34), /* divdi */
823 COSTS_N_INSNS (3), /* fp */
824 COSTS_N_INSNS (3), /* dmul */
825 COSTS_N_INSNS (13), /* sdiv */
826 COSTS_N_INSNS (16), /* ddiv */
827 128, /* cache line size */
830 12, /* prefetch streams */
833 /* Instruction costs on POWER A2 processors. */
835 struct processor_costs ppca2_cost = {
836 COSTS_N_INSNS (16), /* mulsi */
837 COSTS_N_INSNS (16), /* mulsi_const */
838 COSTS_N_INSNS (16), /* mulsi_const9 */
839 COSTS_N_INSNS (16), /* muldi */
840 COSTS_N_INSNS (22), /* divsi */
841 COSTS_N_INSNS (28), /* divdi */
842 COSTS_N_INSNS (3), /* fp */
843 COSTS_N_INSNS (3), /* dmul */
844 COSTS_N_INSNS (59), /* sdiv */
845 COSTS_N_INSNS (72), /* ddiv */
849 16, /* prefetch streams */
853 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
854 #undef RS6000_BUILTIN_1
855 #undef RS6000_BUILTIN_2
856 #undef RS6000_BUILTIN_3
857 #undef RS6000_BUILTIN_A
858 #undef RS6000_BUILTIN_D
859 #undef RS6000_BUILTIN_E
860 #undef RS6000_BUILTIN_P
861 #undef RS6000_BUILTIN_Q
862 #undef RS6000_BUILTIN_S
863 #undef RS6000_BUILTIN_X
865 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
866 { NAME, ICODE, MASK, ATTR },
868 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
869 { NAME, ICODE, MASK, ATTR },
871 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
872 { NAME, ICODE, MASK, ATTR },
874 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
875 { NAME, ICODE, MASK, ATTR },
877 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
878 { NAME, ICODE, MASK, ATTR },
880 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
881 { NAME, ICODE, MASK, ATTR },
883 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
884 { NAME, ICODE, MASK, ATTR },
886 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
887 { NAME, ICODE, MASK, ATTR },
889 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
890 { NAME, ICODE, MASK, ATTR },
892 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
893 { NAME, ICODE, MASK, ATTR },
895 struct rs6000_builtin_info_type {
897 const enum insn_code icode;
902 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
904 #include "rs6000-builtin.def"
907 #undef RS6000_BUILTIN_1
908 #undef RS6000_BUILTIN_2
909 #undef RS6000_BUILTIN_3
910 #undef RS6000_BUILTIN_A
911 #undef RS6000_BUILTIN_D
912 #undef RS6000_BUILTIN_E
913 #undef RS6000_BUILTIN_P
914 #undef RS6000_BUILTIN_Q
915 #undef RS6000_BUILTIN_S
916 #undef RS6000_BUILTIN_X
918 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
919 static tree (*rs6000_veclib_handler) (tree, tree, tree);
922 static bool rs6000_function_ok_for_sibcall (tree, tree);
923 static const char *rs6000_invalid_within_doloop (const_rtx);
924 static bool rs6000_legitimate_address_p (enum machine_mode, rtx, bool);
925 static bool rs6000_debug_legitimate_address_p (enum machine_mode, rtx, bool);
926 static rtx rs6000_generate_compare (rtx, enum machine_mode);
927 static void rs6000_emit_stack_tie (void);
928 static bool spe_func_has_64bit_regs_p (void);
929 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
930 static unsigned rs6000_hash_constant (rtx);
931 static unsigned toc_hash_function (const void *);
932 static int toc_hash_eq (const void *, const void *);
933 static bool reg_offset_addressing_ok_p (enum machine_mode);
934 static bool virtual_stack_registers_memory_p (rtx);
935 static bool constant_pool_expr_p (rtx);
936 static bool legitimate_small_data_p (enum machine_mode, rtx);
937 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
938 static struct machine_function * rs6000_init_machine_status (void);
939 static bool rs6000_assemble_integer (rtx, unsigned int, int);
940 static bool no_global_regs_above (int, bool);
941 #if defined (HAVE_GAS_HIDDEN) && !defined (TARGET_MACHO)
942 static void rs6000_assemble_visibility (tree, int);
944 static int rs6000_ra_ever_killed (void);
945 static bool rs6000_attribute_takes_identifier_p (const_tree);
946 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
947 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
948 static bool rs6000_ms_bitfield_layout_p (const_tree);
949 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
950 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
951 static const char *rs6000_mangle_type (const_tree);
952 static void rs6000_set_default_type_attributes (tree);
953 static rtx rs6000_savres_routine_sym (rs6000_stack_t *, bool, bool, bool);
954 static rtx rs6000_emit_stack_reset (rs6000_stack_t *, rtx, rtx, int, bool);
955 static bool rs6000_reg_live_or_pic_offset_p (int);
956 static tree rs6000_builtin_vectorized_libmass (tree, tree, tree);
957 static tree rs6000_builtin_vectorized_function (tree, tree, tree);
958 static void rs6000_restore_saved_cr (rtx, int);
959 static bool rs6000_output_addr_const_extra (FILE *, rtx);
960 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
961 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
962 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
964 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
965 static bool rs6000_return_in_memory (const_tree, const_tree);
966 static rtx rs6000_function_value (const_tree, const_tree, bool);
967 static void rs6000_file_start (void);
969 static int rs6000_elf_reloc_rw_mask (void);
970 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
971 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
972 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
973 static void rs6000_elf_asm_init_sections (void);
974 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
975 unsigned HOST_WIDE_INT);
976 static void rs6000_elf_encode_section_info (tree, rtx, int)
979 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, const_rtx);
980 static void rs6000_alloc_sdmode_stack_slot (void);
981 static void rs6000_instantiate_decls (void);
983 static void rs6000_xcoff_asm_output_anchor (rtx);
984 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
985 static void rs6000_xcoff_asm_init_sections (void);
986 static int rs6000_xcoff_reloc_rw_mask (void);
987 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
988 static section *rs6000_xcoff_select_section (tree, int,
989 unsigned HOST_WIDE_INT);
990 static void rs6000_xcoff_unique_section (tree, int);
991 static section *rs6000_xcoff_select_rtx_section
992 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
993 static const char * rs6000_xcoff_strip_name_encoding (const char *);
994 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
995 static void rs6000_xcoff_file_start (void);
996 static void rs6000_xcoff_file_end (void);
998 static int rs6000_variable_issue (FILE *, int, rtx, int);
999 static int rs6000_register_move_cost (enum machine_mode,
1000 reg_class_t, reg_class_t);
1001 static int rs6000_memory_move_cost (enum machine_mode, reg_class_t, bool);
1002 static bool rs6000_rtx_costs (rtx, int, int, int, int *, bool);
1003 static bool rs6000_debug_rtx_costs (rtx, int, int, int, int *, bool);
1004 static int rs6000_debug_address_cost (rtx, bool);
1005 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
1006 static int rs6000_debug_adjust_cost (rtx, rtx, rtx, int);
1007 static void rs6000_sched_init (FILE *, int, int);
1008 static bool is_microcoded_insn (rtx);
1009 static bool is_nonpipeline_insn (rtx);
1010 static bool is_cracked_insn (rtx);
1011 static bool is_branch_slot_insn (rtx);
1012 static bool is_load_insn (rtx);
1013 static rtx get_store_dest (rtx pat);
1014 static bool is_store_insn (rtx);
1015 static bool set_to_load_agen (rtx,rtx);
1016 static bool adjacent_mem_locations (rtx,rtx);
1017 static int rs6000_adjust_priority (rtx, int);
1018 static int rs6000_issue_rate (void);
1019 static bool rs6000_is_costly_dependence (dep_t, int, int);
1020 static rtx get_next_active_insn (rtx, rtx);
1021 static bool insn_terminates_group_p (rtx , enum group_termination);
1022 static bool insn_must_be_first_in_group (rtx);
1023 static bool insn_must_be_last_in_group (rtx);
1024 static bool is_costly_group (rtx *, rtx);
1025 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
1026 static int redefine_groups (FILE *, int, rtx, rtx);
1027 static int pad_groups (FILE *, int, rtx, rtx);
1028 static void rs6000_sched_finish (FILE *, int);
1029 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
1030 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
1031 static int rs6000_use_sched_lookahead (void);
1032 static int rs6000_use_sched_lookahead_guard (rtx);
1033 static void * rs6000_alloc_sched_context (void);
1034 static void rs6000_init_sched_context (void *, bool);
1035 static void rs6000_set_sched_context (void *);
1036 static void rs6000_free_sched_context (void *);
1037 static tree rs6000_builtin_reciprocal (unsigned int, bool, bool);
1038 static tree rs6000_builtin_mask_for_load (void);
1039 static tree rs6000_builtin_mul_widen_even (tree);
1040 static tree rs6000_builtin_mul_widen_odd (tree);
1041 static bool rs6000_builtin_support_vector_misalignment (enum
1045 static int rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt,
1047 static enum machine_mode rs6000_preferred_simd_mode (enum machine_mode);
1049 static void def_builtin (const char *, tree, enum rs6000_builtins);
1050 static bool rs6000_vector_alignment_reachable (const_tree, bool);
1051 static void rs6000_init_builtins (void);
1052 static tree rs6000_builtin_decl (unsigned, bool);
1054 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
1055 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
1056 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
1057 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
1058 static void altivec_init_builtins (void);
1059 static unsigned builtin_hash_function (const void *);
1060 static int builtin_hash_eq (const void *, const void *);
1061 static tree builtin_function_type (enum machine_mode, enum machine_mode,
1062 enum machine_mode, enum machine_mode,
1063 enum rs6000_builtins, const char *name);
1064 static void rs6000_common_init_builtins (void);
1065 static void rs6000_init_libfuncs (void);
1067 static void paired_init_builtins (void);
1068 static rtx paired_expand_builtin (tree, rtx, bool *);
1069 static rtx paired_expand_lv_builtin (enum insn_code, tree, rtx);
1070 static rtx paired_expand_stv_builtin (enum insn_code, tree);
1071 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
1073 static void spe_init_builtins (void);
1074 static rtx spe_expand_builtin (tree, rtx, bool *);
1075 static rtx spe_expand_stv_builtin (enum insn_code, tree);
1076 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
1077 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
1078 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
1079 static rs6000_stack_t *rs6000_stack_info (void);
1080 static void debug_stack_info (rs6000_stack_t *);
1082 static rtx altivec_expand_builtin (tree, rtx, bool *);
1083 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
1084 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
1085 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
1086 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
1087 static rtx altivec_expand_predicate_builtin (enum insn_code, tree, rtx);
1088 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
1089 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
1090 static rtx altivec_expand_vec_set_builtin (tree);
1091 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
1092 static int get_element_number (tree, tree);
1093 static void rs6000_option_override (void);
1094 static int rs6000_loop_align_max_skip (rtx);
1095 static int first_altivec_reg_to_save (void);
1096 static unsigned int compute_vrsave_mask (void);
1097 static void compute_save_world_info (rs6000_stack_t *info_ptr);
1098 static void is_altivec_return_reg (rtx, void *);
1099 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
1100 int easy_vector_constant (rtx, enum machine_mode);
1101 static rtx rs6000_dwarf_register_span (rtx);
1102 static void rs6000_init_dwarf_reg_sizes_extra (tree);
1103 static rtx rs6000_legitimize_address (rtx, rtx, enum machine_mode);
1104 static rtx rs6000_debug_legitimize_address (rtx, rtx, enum machine_mode);
1105 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1106 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
1107 static rtx rs6000_delegitimize_address (rtx);
1108 static rtx rs6000_tls_get_addr (void);
1109 static rtx rs6000_got_sym (void);
1110 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
1111 static const char *rs6000_get_some_local_dynamic_name (void);
1112 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
1113 static rtx rs6000_complex_function_value (enum machine_mode);
1114 static rtx rs6000_spe_function_arg (const CUMULATIVE_ARGS *,
1115 enum machine_mode, const_tree);
1116 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
1117 HOST_WIDE_INT, int);
1118 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
1121 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
1124 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
1125 const_tree, HOST_WIDE_INT,
1127 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree, bool, bool);
1128 static rtx rs6000_mixed_function_arg (enum machine_mode, const_tree, int);
1129 static void rs6000_function_arg_advance (cumulative_args_t, enum machine_mode,
1131 static rtx rs6000_function_arg (cumulative_args_t, enum machine_mode,
1133 static unsigned int rs6000_function_arg_boundary (enum machine_mode,
1135 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
1136 static void setup_incoming_varargs (cumulative_args_t,
1137 enum machine_mode, tree,
1139 static bool rs6000_pass_by_reference (cumulative_args_t, enum machine_mode,
1141 static int rs6000_arg_partial_bytes (cumulative_args_t, enum machine_mode,
1143 static const char *invalid_arg_for_unprototyped_fn (const_tree, const_tree, const_tree);
1145 static void macho_branch_islands (void);
1146 static int no_previous_def (tree function_name);
1147 static tree get_prev_label (tree function_name);
1148 static void rs6000_darwin_file_start (void);
1151 static tree rs6000_build_builtin_va_list (void);
1152 static void rs6000_va_start (tree, rtx);
1153 static tree rs6000_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *);
1154 static bool rs6000_must_pass_in_stack (enum machine_mode, const_tree);
1155 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
1156 static bool rs6000_vector_mode_supported_p (enum machine_mode);
1157 static rtx rs6000_emit_vector_compare_inner (enum rtx_code, rtx, rtx);
1158 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
1160 static tree rs6000_stack_protect_fail (void);
1162 static rtx rs6000_legitimize_reload_address (rtx, enum machine_mode, int, int,
1165 static rtx rs6000_debug_legitimize_reload_address (rtx, enum machine_mode, int,
1168 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, enum machine_mode, int, int,
1170 = rs6000_legitimize_reload_address;
1172 static bool rs6000_mode_dependent_address_p (const_rtx);
1173 static bool rs6000_mode_dependent_address (const_rtx);
1174 static bool rs6000_debug_mode_dependent_address (const_rtx);
1175 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1176 = rs6000_mode_dependent_address;
1178 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1179 enum machine_mode, rtx);
1180 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1183 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1184 enum machine_mode, rtx)
1185 = rs6000_secondary_reload_class;
1187 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1188 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1190 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1191 = rs6000_preferred_reload_class;
1193 static bool rs6000_secondary_memory_needed (enum reg_class, enum reg_class,
1196 static bool rs6000_debug_secondary_memory_needed (enum reg_class,
1200 bool (*rs6000_secondary_memory_needed_ptr) (enum reg_class, enum reg_class,
1202 = rs6000_secondary_memory_needed;
1204 static bool rs6000_cannot_change_mode_class (enum machine_mode,
1207 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode,
1211 bool (*rs6000_cannot_change_mode_class_ptr) (enum machine_mode,
1214 = rs6000_cannot_change_mode_class;
1216 static reg_class_t rs6000_secondary_reload (bool, rtx, reg_class_t,
1218 struct secondary_reload_info *);
1220 const int INSN_NOT_AVAILABLE = -1;
1221 static enum machine_mode rs6000_eh_return_filter_mode (void);
1222 static bool rs6000_can_eliminate (const int, const int);
1223 static void rs6000_conditional_register_usage (void);
1224 static void rs6000_trampoline_init (rtx, tree, rtx);
1225 static bool rs6000_cannot_force_const_mem (enum machine_mode, rtx);
1226 static bool rs6000_legitimate_constant_p (enum machine_mode, rtx);
1227 static bool rs6000_save_toc_in_prologue_p (void);
1228 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
1230 /* Hash table stuff for keeping track of TOC entries. */
1232 struct GTY(()) toc_hash_struct
1234 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1235 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1237 enum machine_mode key_mode;
1241 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
1243 /* Hash table to keep track of the argument types for builtin functions. */
1245 struct GTY(()) builtin_hash_struct
1248 enum machine_mode mode[4]; /* return value + 3 arguments. */
1249 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1252 static GTY ((param_is (struct builtin_hash_struct))) htab_t builtin_hash_table;
1254 static bool rs6000_valid_attribute_p (tree, tree, tree, int);
1255 static void rs6000_function_specific_save (struct cl_target_option *);
1256 static void rs6000_function_specific_restore (struct cl_target_option *);
1257 static void rs6000_function_specific_print (FILE *, int,
1258 struct cl_target_option *);
1259 static bool rs6000_can_inline_p (tree, tree);
1260 static void rs6000_set_current_function (tree);
1263 /* Default register names. */
1264 char rs6000_reg_names[][8] =
1266 "0", "1", "2", "3", "4", "5", "6", "7",
1267 "8", "9", "10", "11", "12", "13", "14", "15",
1268 "16", "17", "18", "19", "20", "21", "22", "23",
1269 "24", "25", "26", "27", "28", "29", "30", "31",
1270 "0", "1", "2", "3", "4", "5", "6", "7",
1271 "8", "9", "10", "11", "12", "13", "14", "15",
1272 "16", "17", "18", "19", "20", "21", "22", "23",
1273 "24", "25", "26", "27", "28", "29", "30", "31",
1274 "mq", "lr", "ctr","ap",
1275 "0", "1", "2", "3", "4", "5", "6", "7",
1277 /* AltiVec registers. */
1278 "0", "1", "2", "3", "4", "5", "6", "7",
1279 "8", "9", "10", "11", "12", "13", "14", "15",
1280 "16", "17", "18", "19", "20", "21", "22", "23",
1281 "24", "25", "26", "27", "28", "29", "30", "31",
1283 /* SPE registers. */
1284 "spe_acc", "spefscr",
1285 /* Soft frame pointer. */
1289 #ifdef TARGET_REGNAMES
1290 static const char alt_reg_names[][8] =
1292 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1293 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1294 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1295 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1296 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1297 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1298 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1299 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1300 "mq", "lr", "ctr", "ap",
1301 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1303 /* AltiVec registers. */
1304 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1305 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1306 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1307 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1309 /* SPE registers. */
1310 "spe_acc", "spefscr",
1311 /* Soft frame pointer. */
1316 /* Table of valid machine attributes. */
1318 static const struct attribute_spec rs6000_attribute_table[] =
1320 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1321 affects_type_identity } */
1322 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute,
1324 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1326 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1328 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1330 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1332 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1333 SUBTARGET_ATTRIBUTE_TABLE,
1335 { NULL, 0, 0, false, false, false, NULL, false }
1338 #ifndef MASK_STRICT_ALIGN
1339 #define MASK_STRICT_ALIGN 0
1341 #ifndef TARGET_PROFILE_KERNEL
1342 #define TARGET_PROFILE_KERNEL 0
1345 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1346 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1348 /* Initialize the GCC target structure. */
1349 #undef TARGET_ATTRIBUTE_TABLE
1350 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1351 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1352 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1353 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1354 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1356 #undef TARGET_ASM_ALIGNED_DI_OP
1357 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1359 /* Default unaligned ops are only provided for ELF. Find the ops needed
1360 for non-ELF systems. */
1361 #ifndef OBJECT_FORMAT_ELF
1363 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1365 #undef TARGET_ASM_UNALIGNED_HI_OP
1366 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1367 #undef TARGET_ASM_UNALIGNED_SI_OP
1368 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1369 #undef TARGET_ASM_UNALIGNED_DI_OP
1370 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1373 #undef TARGET_ASM_UNALIGNED_HI_OP
1374 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1375 #undef TARGET_ASM_UNALIGNED_SI_OP
1376 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1377 #undef TARGET_ASM_UNALIGNED_DI_OP
1378 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1379 #undef TARGET_ASM_ALIGNED_DI_OP
1380 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1384 /* This hook deals with fixups for relocatable code and DI-mode objects
1386 #undef TARGET_ASM_INTEGER
1387 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1389 #if defined (HAVE_GAS_HIDDEN) && !defined (TARGET_MACHO)
1390 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1391 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1394 #undef TARGET_HAVE_TLS
1395 #define TARGET_HAVE_TLS HAVE_AS_TLS
1397 #undef TARGET_CANNOT_FORCE_CONST_MEM
1398 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1400 #undef TARGET_DELEGITIMIZE_ADDRESS
1401 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1403 #undef TARGET_ASM_FUNCTION_PROLOGUE
1404 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1405 #undef TARGET_ASM_FUNCTION_EPILOGUE
1406 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1408 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1409 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1411 #undef TARGET_LEGITIMIZE_ADDRESS
1412 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1414 #undef TARGET_SCHED_VARIABLE_ISSUE
1415 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1417 #undef TARGET_SCHED_ISSUE_RATE
1418 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1419 #undef TARGET_SCHED_ADJUST_COST
1420 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1421 #undef TARGET_SCHED_ADJUST_PRIORITY
1422 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1423 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1424 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1425 #undef TARGET_SCHED_INIT
1426 #define TARGET_SCHED_INIT rs6000_sched_init
1427 #undef TARGET_SCHED_FINISH
1428 #define TARGET_SCHED_FINISH rs6000_sched_finish
1429 #undef TARGET_SCHED_REORDER
1430 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1431 #undef TARGET_SCHED_REORDER2
1432 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1434 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1435 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1437 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1438 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1440 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1441 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1442 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1443 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1444 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1445 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1446 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1447 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1449 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1450 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1451 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1452 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1453 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1454 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1455 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1456 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1457 rs6000_builtin_support_vector_misalignment
1458 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1459 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1460 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1461 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1462 rs6000_builtin_vectorization_cost
1463 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1464 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1465 rs6000_preferred_simd_mode
1467 #undef TARGET_INIT_BUILTINS
1468 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1469 #undef TARGET_BUILTIN_DECL
1470 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1472 #undef TARGET_EXPAND_BUILTIN
1473 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1475 #undef TARGET_MANGLE_TYPE
1476 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1478 #undef TARGET_INIT_LIBFUNCS
1479 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1482 #undef TARGET_BINDS_LOCAL_P
1483 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1486 #undef TARGET_MS_BITFIELD_LAYOUT_P
1487 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1489 #undef TARGET_ASM_OUTPUT_MI_THUNK
1490 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1492 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1493 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1495 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1496 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1498 #undef TARGET_INVALID_WITHIN_DOLOOP
1499 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1501 #undef TARGET_REGISTER_MOVE_COST
1502 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1503 #undef TARGET_MEMORY_MOVE_COST
1504 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1505 #undef TARGET_RTX_COSTS
1506 #define TARGET_RTX_COSTS rs6000_rtx_costs
1507 #undef TARGET_ADDRESS_COST
1508 #define TARGET_ADDRESS_COST hook_int_rtx_bool_0
1510 #undef TARGET_DWARF_REGISTER_SPAN
1511 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1513 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1514 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1516 /* On rs6000, function arguments are promoted, as are function return
1518 #undef TARGET_PROMOTE_FUNCTION_MODE
1519 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1521 #undef TARGET_RETURN_IN_MEMORY
1522 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1524 #undef TARGET_SETUP_INCOMING_VARARGS
1525 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1527 /* Always strict argument naming on rs6000. */
1528 #undef TARGET_STRICT_ARGUMENT_NAMING
1529 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1530 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1531 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1532 #undef TARGET_SPLIT_COMPLEX_ARG
1533 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1534 #undef TARGET_MUST_PASS_IN_STACK
1535 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1536 #undef TARGET_PASS_BY_REFERENCE
1537 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1538 #undef TARGET_ARG_PARTIAL_BYTES
1539 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1540 #undef TARGET_FUNCTION_ARG_ADVANCE
1541 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1542 #undef TARGET_FUNCTION_ARG
1543 #define TARGET_FUNCTION_ARG rs6000_function_arg
1544 #undef TARGET_FUNCTION_ARG_BOUNDARY
1545 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1547 #undef TARGET_BUILD_BUILTIN_VA_LIST
1548 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1550 #undef TARGET_EXPAND_BUILTIN_VA_START
1551 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1553 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1554 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1556 #undef TARGET_EH_RETURN_FILTER_MODE
1557 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1559 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1560 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1562 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1563 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1565 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1566 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1568 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1569 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1571 #undef TARGET_OPTION_OVERRIDE
1572 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1574 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1575 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1576 rs6000_builtin_vectorized_function
1578 #ifndef TARGET_MACHO
1579 #undef TARGET_STACK_PROTECT_FAIL
1580 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1583 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1584 The PowerPC architecture requires only weak consistency among
1585 processors--that is, memory accesses between processors need not be
1586 sequentially consistent and memory accesses among processors can occur
1587 in any order. The ability to order memory accesses weakly provides
1588 opportunities for more efficient use of the system bus. Unless a
1589 dependency exists, the 604e allows read operations to precede store
1591 #undef TARGET_RELAXED_ORDERING
1592 #define TARGET_RELAXED_ORDERING true
1595 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1596 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1599 /* Use a 32-bit anchor range. This leads to sequences like:
1601 addis tmp,anchor,high
1604 where tmp itself acts as an anchor, and can be shared between
1605 accesses to the same 64k page. */
1606 #undef TARGET_MIN_ANCHOR_OFFSET
1607 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1608 #undef TARGET_MAX_ANCHOR_OFFSET
1609 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1610 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1611 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1613 #undef TARGET_BUILTIN_RECIPROCAL
1614 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1616 #undef TARGET_EXPAND_TO_RTL_HOOK
1617 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1619 #undef TARGET_INSTANTIATE_DECLS
1620 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1622 #undef TARGET_SECONDARY_RELOAD
1623 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1625 #undef TARGET_LEGITIMATE_ADDRESS_P
1626 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1628 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1629 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1631 #undef TARGET_CAN_ELIMINATE
1632 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1634 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1635 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1637 #undef TARGET_TRAMPOLINE_INIT
1638 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1640 #undef TARGET_FUNCTION_VALUE
1641 #define TARGET_FUNCTION_VALUE rs6000_function_value
1643 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1644 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1646 #undef TARGET_OPTION_SAVE
1647 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1649 #undef TARGET_OPTION_RESTORE
1650 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1652 #undef TARGET_OPTION_PRINT
1653 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1655 #undef TARGET_CAN_INLINE_P
1656 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1658 #undef TARGET_SET_CURRENT_FUNCTION
1659 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1661 #undef TARGET_LEGITIMATE_CONSTANT_P
1662 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1664 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1665 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1668 /* Simplifications for entries below. */
1671 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1672 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1675 /* Some OSs don't support saving the high part of 64-bit registers on context
1676 switch. Other OSs don't support saving Altivec registers. On those OSs, we
1677 don't touch the MASK_POWERPC64 or MASK_ALTIVEC settings; if the user wants
1678 either, the user must explicitly specify them and we won't interfere with
1679 the user's specification. */
1682 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1683 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1684 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1685 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1686 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP
1687 | MASK_POPCNTD | MASK_VSX | MASK_ISEL | MASK_NO_UPDATE
1688 | MASK_RECIP_PRECISION)
1691 /* Masks for instructions set at various powerpc ISAs. */
1693 ISA_2_1_MASKS = MASK_MFCRF,
1694 ISA_2_2_MASKS = (ISA_2_1_MASKS | MASK_POPCNTB),
1695 ISA_2_4_MASKS = (ISA_2_2_MASKS | MASK_FPRND),
1697 /* For ISA 2.05, do not add MFPGPR, since it isn't in ISA 2.06, and don't add
1698 ALTIVEC, since in general it isn't a win on power6. In ISA 2.04, fsel,
1699 fre, fsqrt, etc. were no longer documented as optional. Group masks by
1700 server and embedded. */
1701 ISA_2_5_MASKS_EMBEDDED = (ISA_2_2_MASKS | MASK_CMPB | MASK_RECIP_PRECISION
1702 | MASK_PPC_GFXOPT | MASK_PPC_GPOPT),
1703 ISA_2_5_MASKS_SERVER = (ISA_2_5_MASKS_EMBEDDED | MASK_DFP),
1705 /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
1706 altivec is a win so enable it. */
1707 ISA_2_6_MASKS_EMBEDDED = (ISA_2_5_MASKS_EMBEDDED | MASK_POPCNTD),
1708 ISA_2_6_MASKS_SERVER = (ISA_2_5_MASKS_SERVER | MASK_POPCNTD | MASK_ALTIVEC
1714 const char *const name; /* Canonical processor name. */
1715 const enum processor_type processor; /* Processor type enum value. */
1716 const int target_enable; /* Target flags to enable. */
1719 static struct rs6000_ptt const processor_target_table[] =
1721 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1722 #include "rs6000-cpus.def"
1726 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1730 rs6000_cpu_name_lookup (const char *name)
1736 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
1737 if (! strcmp (name, processor_target_table[i].name))
1745 /* Return number of consecutive hard regs needed starting at reg REGNO
1746 to hold something of mode MODE.
1747 This is ordinarily the length in words of a value of mode MODE
1748 but can be less for certain modes in special long registers.
1750 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1751 scalar instructions. The upper 32 bits are only available to the
1754 POWER and PowerPC GPRs hold 32 bits worth;
1755 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1758 rs6000_hard_regno_nregs_internal (int regno, enum machine_mode mode)
1760 unsigned HOST_WIDE_INT reg_size;
1762 if (FP_REGNO_P (regno))
1763 reg_size = (VECTOR_MEM_VSX_P (mode)
1764 ? UNITS_PER_VSX_WORD
1765 : UNITS_PER_FP_WORD);
1767 else if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1768 reg_size = UNITS_PER_SPE_WORD;
1770 else if (ALTIVEC_REGNO_P (regno))
1771 reg_size = UNITS_PER_ALTIVEC_WORD;
1773 /* The value returned for SCmode in the E500 double case is 2 for
1774 ABI compatibility; storing an SCmode value in a single register
1775 would require function_arg and rs6000_spe_function_arg to handle
1776 SCmode so as to pass the value correctly in a pair of
1778 else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
1779 && !DECIMAL_FLOAT_MODE_P (mode))
1780 reg_size = UNITS_PER_FP_WORD;
1783 reg_size = UNITS_PER_WORD;
1785 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
1788 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1791 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1793 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
1795 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1796 implementations. Don't allow an item to be split between a FP register
1797 and an Altivec register. */
1798 if (VECTOR_MEM_VSX_P (mode))
1800 if (FP_REGNO_P (regno))
1801 return FP_REGNO_P (last_regno);
1803 if (ALTIVEC_REGNO_P (regno))
1804 return ALTIVEC_REGNO_P (last_regno);
1807 /* The GPRs can hold any mode, but values bigger than one register
1808 cannot go past R31. */
1809 if (INT_REGNO_P (regno))
1810 return INT_REGNO_P (last_regno);
1812 /* The float registers (except for VSX vector modes) can only hold floating
1813 modes and DImode. This excludes the 32-bit decimal float mode for
1815 if (FP_REGNO_P (regno))
1817 if (SCALAR_FLOAT_MODE_P (mode)
1818 && (mode != TDmode || (regno % 2) == 0)
1819 && FP_REGNO_P (last_regno))
1822 if (GET_MODE_CLASS (mode) == MODE_INT
1823 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1826 if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1827 && PAIRED_VECTOR_MODE (mode))
1833 /* The CR register can only hold CC modes. */
1834 if (CR_REGNO_P (regno))
1835 return GET_MODE_CLASS (mode) == MODE_CC;
1837 if (CA_REGNO_P (regno))
1838 return mode == BImode;
1840 /* AltiVec only in AldyVec registers. */
1841 if (ALTIVEC_REGNO_P (regno))
1842 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode);
1844 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1845 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1848 /* We cannot put TImode anywhere except general register and it must be able
1849 to fit within the register set. In the future, allow TImode in the
1850 Altivec or VSX registers. */
1852 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1855 /* Print interesting facts about registers. */
1857 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
1861 for (r = first_regno; r <= last_regno; ++r)
1863 const char *comma = "";
1866 if (first_regno == last_regno)
1867 fprintf (stderr, "%s:\t", reg_name);
1869 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
1872 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1873 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
1877 fprintf (stderr, ",\n\t");
1882 if (rs6000_hard_regno_nregs[m][r] > 1)
1883 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
1884 rs6000_hard_regno_nregs[m][r]);
1886 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
1891 if (call_used_regs[r])
1895 fprintf (stderr, ",\n\t");
1900 len += fprintf (stderr, "%s%s", comma, "call-used");
1908 fprintf (stderr, ",\n\t");
1913 len += fprintf (stderr, "%s%s", comma, "fixed");
1919 fprintf (stderr, ",\n\t");
1923 fprintf (stderr, "%sregno = %d\n", comma, r);
1927 #define DEBUG_FMT_D "%-32s= %d\n"
1928 #define DEBUG_FMT_X "%-32s= 0x%x\n"
1929 #define DEBUG_FMT_S "%-32s= %s\n"
1931 /* Print various interesting information with -mdebug=reg. */
1933 rs6000_debug_reg_global (void)
1935 static const char *const tf[2] = { "false", "true" };
1936 const char *nl = (const char *)0;
1938 char costly_num[20];
1940 const char *costly_str;
1941 const char *nop_str;
1942 const char *trace_str;
1943 const char *abi_str;
1944 const char *cmodel_str;
1946 /* Map enum rs6000_vector to string. */
1947 static const char *rs6000_debug_vector_unit[] = {
1956 fprintf (stderr, "Register information: (last virtual reg = %d)\n",
1957 LAST_VIRTUAL_REGISTER);
1958 rs6000_debug_reg_print (0, 31, "gr");
1959 rs6000_debug_reg_print (32, 63, "fp");
1960 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
1963 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
1964 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
1965 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
1966 rs6000_debug_reg_print (MQ_REGNO, MQ_REGNO, "mq");
1967 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
1968 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
1969 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
1970 rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
1971 rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
1975 "d reg_class = %s\n"
1976 "f reg_class = %s\n"
1977 "v reg_class = %s\n"
1978 "wa reg_class = %s\n"
1979 "wd reg_class = %s\n"
1980 "wf reg_class = %s\n"
1981 "ws reg_class = %s\n\n",
1982 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
1983 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
1984 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
1985 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
1986 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
1987 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
1988 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]]);
1990 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1991 if (rs6000_vector_unit[m] || rs6000_vector_mem[m])
1994 fprintf (stderr, "Vector mode: %-5s arithmetic: %-8s move: %-8s\n",
1996 rs6000_debug_vector_unit[ rs6000_vector_unit[m] ],
1997 rs6000_debug_vector_unit[ rs6000_vector_mem[m] ]);
2003 if (rs6000_recip_control)
2005 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2007 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2008 if (rs6000_recip_bits[m])
2011 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2013 (RS6000_RECIP_AUTO_RE_P (m)
2015 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2016 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2018 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2021 fputs ("\n", stderr);
2024 if (rs6000_cpu_index >= 0)
2025 fprintf (stderr, DEBUG_FMT_S, "cpu",
2026 processor_target_table[rs6000_cpu_index].name);
2028 if (rs6000_tune_index >= 0)
2029 fprintf (stderr, DEBUG_FMT_S, "tune",
2030 processor_target_table[rs6000_tune_index].name);
2032 switch (rs6000_sched_costly_dep)
2034 case max_dep_latency:
2035 costly_str = "max_dep_latency";
2039 costly_str = "no_dep_costly";
2042 case all_deps_costly:
2043 costly_str = "all_deps_costly";
2046 case true_store_to_load_dep_costly:
2047 costly_str = "true_store_to_load_dep_costly";
2050 case store_to_load_dep_costly:
2051 costly_str = "store_to_load_dep_costly";
2055 costly_str = costly_num;
2056 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2060 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2062 switch (rs6000_sched_insert_nops)
2064 case sched_finish_regroup_exact:
2065 nop_str = "sched_finish_regroup_exact";
2068 case sched_finish_pad_groups:
2069 nop_str = "sched_finish_pad_groups";
2072 case sched_finish_none:
2073 nop_str = "sched_finish_none";
2078 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2082 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2084 switch (rs6000_sdata)
2091 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2095 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2099 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2104 switch (rs6000_traceback)
2106 case traceback_default: trace_str = "default"; break;
2107 case traceback_none: trace_str = "none"; break;
2108 case traceback_part: trace_str = "part"; break;
2109 case traceback_full: trace_str = "full"; break;
2110 default: trace_str = "unknown"; break;
2113 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2115 switch (rs6000_current_cmodel)
2117 case CMODEL_SMALL: cmodel_str = "small"; break;
2118 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2119 case CMODEL_LARGE: cmodel_str = "large"; break;
2120 default: cmodel_str = "unknown"; break;
2123 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2125 switch (rs6000_current_abi)
2127 case ABI_NONE: abi_str = "none"; break;
2128 case ABI_AIX: abi_str = "aix"; break;
2129 case ABI_V4: abi_str = "V4"; break;
2130 case ABI_DARWIN: abi_str = "darwin"; break;
2131 default: abi_str = "unknown"; break;
2134 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2136 if (rs6000_altivec_abi)
2137 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2140 fprintf (stderr, DEBUG_FMT_S, "spe_abi", "true");
2142 if (rs6000_darwin64_abi)
2143 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2145 if (rs6000_float_gprs)
2146 fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
2148 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2149 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2150 tf[!!rs6000_align_branch_targets]);
2151 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2152 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2153 rs6000_long_double_type_size);
2154 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2155 (int)rs6000_sched_restricted_insns_priority);
2156 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2158 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2159 (int)RS6000_BUILTIN_COUNT);
2160 fprintf (stderr, DEBUG_FMT_X, "Builtin mask", rs6000_builtin_mask);
2163 /* Initialize the various global tables that are based on register size. */
2165 rs6000_init_hard_regno_mode_ok (bool global_init_p)
2171 /* Precalculate REGNO_REG_CLASS. */
2172 rs6000_regno_regclass[0] = GENERAL_REGS;
2173 for (r = 1; r < 32; ++r)
2174 rs6000_regno_regclass[r] = BASE_REGS;
2176 for (r = 32; r < 64; ++r)
2177 rs6000_regno_regclass[r] = FLOAT_REGS;
2179 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
2180 rs6000_regno_regclass[r] = NO_REGS;
2182 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
2183 rs6000_regno_regclass[r] = ALTIVEC_REGS;
2185 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
2186 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
2187 rs6000_regno_regclass[r] = CR_REGS;
2189 rs6000_regno_regclass[MQ_REGNO] = MQ_REGS;
2190 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
2191 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
2192 rs6000_regno_regclass[CA_REGNO] = CA_REGS;
2193 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
2194 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
2195 rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
2196 rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
2197 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
2198 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
2200 /* Precalculate vector information, this must be set up before the
2201 rs6000_hard_regno_nregs_internal below. */
2202 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2204 rs6000_vector_unit[m] = rs6000_vector_mem[m] = VECTOR_NONE;
2205 rs6000_vector_reload[m][0] = CODE_FOR_nothing;
2206 rs6000_vector_reload[m][1] = CODE_FOR_nothing;
2209 for (c = 0; c < (int)(int)RS6000_CONSTRAINT_MAX; c++)
2210 rs6000_constraints[c] = NO_REGS;
2212 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2213 believes it can use native alignment or still uses 128-bit alignment. */
2214 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
2225 /* V2DF mode, VSX only. */
2228 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
2229 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
2230 rs6000_vector_align[V2DFmode] = align64;
2233 /* V4SF mode, either VSX or Altivec. */
2236 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
2237 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
2238 rs6000_vector_align[V4SFmode] = align32;
2240 else if (TARGET_ALTIVEC)
2242 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
2243 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
2244 rs6000_vector_align[V4SFmode] = align32;
2247 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2251 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
2252 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
2253 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
2254 rs6000_vector_align[V4SImode] = align32;
2255 rs6000_vector_align[V8HImode] = align32;
2256 rs6000_vector_align[V16QImode] = align32;
2260 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
2261 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
2262 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
2266 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
2267 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
2268 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
2272 /* V2DImode, only allow under VSX, which can do V2DI insert/splat/extract.
2273 Altivec doesn't have 64-bit support. */
2276 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
2277 rs6000_vector_unit[V2DImode] = VECTOR_NONE;
2278 rs6000_vector_align[V2DImode] = align64;
2281 /* DFmode, see if we want to use the VSX unit. */
2282 if (TARGET_VSX && TARGET_VSX_SCALAR_DOUBLE)
2284 rs6000_vector_unit[DFmode] = VECTOR_VSX;
2285 rs6000_vector_mem[DFmode]
2286 = (TARGET_VSX_SCALAR_MEMORY ? VECTOR_VSX : VECTOR_NONE);
2287 rs6000_vector_align[DFmode] = align64;
2290 /* TODO add SPE and paired floating point vector support. */
2292 /* Register class constaints for the constraints that depend on compile
2294 if (TARGET_HARD_FLOAT && TARGET_FPRS)
2295 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS;
2297 if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
2298 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS;
2302 /* At present, we just use VSX_REGS, but we have different constraints
2303 based on the use, in case we want to fine tune the default register
2304 class used. wa = any VSX register, wf = register class to use for
2305 V4SF, wd = register class to use for V2DF, and ws = register classs to
2306 use for DF scalars. */
2307 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
2308 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS;
2309 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS;
2310 rs6000_constraints[RS6000_CONSTRAINT_ws] = (TARGET_VSX_SCALAR_MEMORY
2316 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
2318 /* Set up the reload helper functions. */
2319 if (TARGET_VSX || TARGET_ALTIVEC)
2323 rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_di_store;
2324 rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_di_load;
2325 rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_di_store;
2326 rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_di_load;
2327 rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_di_store;
2328 rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_di_load;
2329 rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_di_store;
2330 rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_di_load;
2331 rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_di_store;
2332 rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_di_load;
2333 rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_di_store;
2334 rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_di_load;
2338 rs6000_vector_reload[V16QImode][0] = CODE_FOR_reload_v16qi_si_store;
2339 rs6000_vector_reload[V16QImode][1] = CODE_FOR_reload_v16qi_si_load;
2340 rs6000_vector_reload[V8HImode][0] = CODE_FOR_reload_v8hi_si_store;
2341 rs6000_vector_reload[V8HImode][1] = CODE_FOR_reload_v8hi_si_load;
2342 rs6000_vector_reload[V4SImode][0] = CODE_FOR_reload_v4si_si_store;
2343 rs6000_vector_reload[V4SImode][1] = CODE_FOR_reload_v4si_si_load;
2344 rs6000_vector_reload[V2DImode][0] = CODE_FOR_reload_v2di_si_store;
2345 rs6000_vector_reload[V2DImode][1] = CODE_FOR_reload_v2di_si_load;
2346 rs6000_vector_reload[V4SFmode][0] = CODE_FOR_reload_v4sf_si_store;
2347 rs6000_vector_reload[V4SFmode][1] = CODE_FOR_reload_v4sf_si_load;
2348 rs6000_vector_reload[V2DFmode][0] = CODE_FOR_reload_v2df_si_store;
2349 rs6000_vector_reload[V2DFmode][1] = CODE_FOR_reload_v2df_si_load;
2353 /* Precalculate HARD_REGNO_NREGS. */
2354 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2355 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2356 rs6000_hard_regno_nregs[m][r]
2357 = rs6000_hard_regno_nregs_internal (r, (enum machine_mode)m);
2359 /* Precalculate HARD_REGNO_MODE_OK. */
2360 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2361 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2362 if (rs6000_hard_regno_mode_ok (r, (enum machine_mode)m))
2363 rs6000_hard_regno_mode_ok_p[m][r] = true;
2365 /* Precalculate CLASS_MAX_NREGS sizes. */
2366 for (c = 0; c < LIM_REG_CLASSES; ++c)
2370 if (TARGET_VSX && VSX_REG_CLASS_P (c))
2371 reg_size = UNITS_PER_VSX_WORD;
2373 else if (c == ALTIVEC_REGS)
2374 reg_size = UNITS_PER_ALTIVEC_WORD;
2376 else if (c == FLOAT_REGS)
2377 reg_size = UNITS_PER_FP_WORD;
2380 reg_size = UNITS_PER_WORD;
2382 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2383 rs6000_class_max_nregs[m][c]
2384 = (GET_MODE_SIZE (m) + reg_size - 1) / reg_size;
2387 if (TARGET_E500_DOUBLE)
2388 rs6000_class_max_nregs[DFmode][GENERAL_REGS] = 1;
2390 /* Calculate which modes to automatically generate code to use a the
2391 reciprocal divide and square root instructions. In the future, possibly
2392 automatically generate the instructions even if the user did not specify
2393 -mrecip. The older machines double precision reciprocal sqrt estimate is
2394 not accurate enough. */
2395 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
2397 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2399 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2400 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2401 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2402 if (VECTOR_UNIT_VSX_P (V2DFmode))
2403 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2405 if (TARGET_FRSQRTES)
2406 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2408 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2409 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2410 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2411 if (VECTOR_UNIT_VSX_P (V2DFmode))
2412 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2414 if (rs6000_recip_control)
2416 if (!flag_finite_math_only)
2417 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2418 if (flag_trapping_math)
2419 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2420 if (!flag_reciprocal_math)
2421 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2422 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
2424 if (RS6000_RECIP_HAVE_RE_P (SFmode)
2425 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
2426 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2428 if (RS6000_RECIP_HAVE_RE_P (DFmode)
2429 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
2430 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2432 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
2433 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
2434 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2436 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
2437 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
2438 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2440 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
2441 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
2442 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2444 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
2445 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
2446 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2448 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
2449 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
2450 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2452 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
2453 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
2454 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
2458 if (global_init_p || TARGET_DEBUG_TARGET)
2460 if (TARGET_DEBUG_REG)
2461 rs6000_debug_reg_global ();
2463 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
2465 "SImode variable mult cost = %d\n"
2466 "SImode constant mult cost = %d\n"
2467 "SImode short constant mult cost = %d\n"
2468 "DImode multipliciation cost = %d\n"
2469 "SImode division cost = %d\n"
2470 "DImode division cost = %d\n"
2471 "Simple fp operation cost = %d\n"
2472 "DFmode multiplication cost = %d\n"
2473 "SFmode division cost = %d\n"
2474 "DFmode division cost = %d\n"
2475 "cache line size = %d\n"
2476 "l1 cache size = %d\n"
2477 "l2 cache size = %d\n"
2478 "simultaneous prefetches = %d\n"
2481 rs6000_cost->mulsi_const,
2482 rs6000_cost->mulsi_const9,
2490 rs6000_cost->cache_line_size,
2491 rs6000_cost->l1_cache_size,
2492 rs6000_cost->l2_cache_size,
2493 rs6000_cost->simultaneous_prefetches);
2498 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2501 darwin_rs6000_override_options (void)
2503 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2505 rs6000_altivec_abi = 1;
2506 TARGET_ALTIVEC_VRSAVE = 1;
2507 rs6000_current_abi = ABI_DARWIN;
2509 if (DEFAULT_ABI == ABI_DARWIN
2511 darwin_one_byte_bool = 1;
2513 if (TARGET_64BIT && ! TARGET_POWERPC64)
2515 target_flags |= MASK_POWERPC64;
2516 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2520 rs6000_default_long_calls = 1;
2521 target_flags |= MASK_SOFT_FLOAT;
2524 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2526 if (!flag_mkernel && !flag_apple_kext
2528 && ! (target_flags_explicit & MASK_ALTIVEC))
2529 target_flags |= MASK_ALTIVEC;
2531 /* Unless the user (not the configurer) has explicitly overridden
2532 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2533 G4 unless targetting the kernel. */
2536 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
2537 && ! (target_flags_explicit & MASK_ALTIVEC)
2538 && ! global_options_set.x_rs6000_cpu_index)
2540 target_flags |= MASK_ALTIVEC;
2545 /* If not otherwise specified by a target, make 'long double' equivalent to
2548 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2549 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2552 /* Return the builtin mask of the various options used that could affect which
2553 builtins were used. In the past we used target_flags, but we've run out of
2554 bits, and some options like SPE and PAIRED are no longer in
2558 rs6000_builtin_mask_calculate (void)
2560 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
2561 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
2562 | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)
2563 | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
2564 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
2565 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
2566 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
2567 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
2568 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
2569 | ((TARGET_POWERPC) ? RS6000_BTM_POWERPC : 0)
2570 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0));
2573 /* Override command line options. Mostly we process the processor type and
2574 sometimes adjust other TARGET_ options. */
2577 rs6000_option_override_internal (bool global_init_p)
2580 const char *default_cpu = OPTION_TARGET_CPU_DEFAULT;
2584 struct cl_target_option *main_target_opt
2585 = ((global_init_p || target_option_default_node == NULL)
2586 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
2588 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
2589 library functions, so warn about it. The flag may be useful for
2590 performance studies from time to time though, so don't disable it
2592 if (global_options_set.x_rs6000_alignment_flags
2593 && rs6000_alignment_flags == MASK_ALIGN_POWER
2594 && DEFAULT_ABI == ABI_DARWIN
2596 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2597 " it is incompatible with the installed C and C++ libraries");
2599 if (global_options_set.x_rs6000_spe_abi
2602 error ("not configured for SPE ABI");
2604 /* Numerous experiment shows that IRA based loop pressure
2605 calculation works better for RTL loop invariant motion on targets
2606 with enough (>= 32) registers. It is an expensive optimization.
2607 So it is on only for peak performance. */
2608 if (optimize >= 3 && global_init_p)
2609 flag_ira_loop_pressure = 1;
2611 /* Set the pointer size. */
2614 rs6000_pmode = (int)DImode;
2615 rs6000_pointer_size = 64;
2619 rs6000_pmode = (int)SImode;
2620 rs6000_pointer_size = 32;
2623 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
2624 #ifdef OS_MISSING_POWERPC64
2625 if (OS_MISSING_POWERPC64)
2626 set_masks &= ~MASK_POWERPC64;
2628 #ifdef OS_MISSING_ALTIVEC
2629 if (OS_MISSING_ALTIVEC)
2630 set_masks &= ~MASK_ALTIVEC;
2633 /* Don't override by the processor default if given explicitly. */
2634 set_masks &= ~target_flags_explicit;
2636 /* Identify the processor type. */
2639 if (TARGET_POWERPC64)
2640 default_cpu = "powerpc64";
2641 else if (TARGET_POWERPC)
2642 default_cpu = "powerpc";
2645 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
2646 the cpu in a target attribute or pragma, but did not specify a tuning
2647 option, use the cpu for the tuning option rather than the option specified
2648 with -mtune on the command line. */
2649 if (rs6000_cpu_index > 0)
2650 cpu_index = rs6000_cpu_index;
2651 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index > 0)
2652 rs6000_cpu_index = cpu_index = main_target_opt->x_rs6000_cpu_index;
2654 rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
2656 if (rs6000_tune_index > 0)
2657 tune_index = rs6000_tune_index;
2659 rs6000_tune_index = tune_index = cpu_index;
2663 target_flags &= ~set_masks;
2664 target_flags |= (processor_target_table[cpu_index].target_enable
2668 rs6000_cpu = ((tune_index >= 0)
2669 ? processor_target_table[tune_index].processor
2671 ? PROCESSOR_DEFAULT64
2672 : PROCESSOR_DEFAULT));
2674 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
2675 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
2678 error ("AltiVec not supported in this target");
2680 error ("SPE not supported in this target");
2683 /* Disable Cell microcode if we are optimizing for the Cell
2684 and not optimizing for size. */
2685 if (rs6000_gen_cell_microcode == -1)
2686 rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
2689 /* If we are optimizing big endian systems for space and it's OK to
2690 use instructions that would be microcoded on the Cell, use the
2691 load/store multiple and string instructions. */
2692 if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
2693 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
2695 /* Don't allow -mmultiple or -mstring on little endian systems
2696 unless the cpu is a 750, because the hardware doesn't support the
2697 instructions used in little endian mode, and causes an alignment
2698 trap. The 750 does not cause an alignment trap (except when the
2699 target is unaligned). */
2701 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
2703 if (TARGET_MULTIPLE)
2705 target_flags &= ~MASK_MULTIPLE;
2706 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
2707 warning (0, "-mmultiple is not supported on little endian systems");
2712 target_flags &= ~MASK_STRING;
2713 if ((target_flags_explicit & MASK_STRING) != 0)
2714 warning (0, "-mstring is not supported on little endian systems");
2718 /* Add some warnings for VSX. */
2721 const char *msg = NULL;
2722 if (!TARGET_HARD_FLOAT || !TARGET_FPRS
2723 || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
2725 if (target_flags_explicit & MASK_VSX)
2726 msg = N_("-mvsx requires hardware floating point");
2728 target_flags &= ~ MASK_VSX;
2730 else if (TARGET_PAIRED_FLOAT)
2731 msg = N_("-mvsx and -mpaired are incompatible");
2732 /* The hardware will allow VSX and little endian, but until we make sure
2733 things like vector select, etc. work don't allow VSX on little endian
2734 systems at this point. */
2735 else if (!BYTES_BIG_ENDIAN)
2736 msg = N_("-mvsx used with little endian code");
2737 else if (TARGET_AVOID_XFORM > 0)
2738 msg = N_("-mvsx needs indexed addressing");
2739 else if (!TARGET_ALTIVEC && (target_flags_explicit & MASK_ALTIVEC))
2741 if (target_flags_explicit & MASK_VSX)
2742 msg = N_("-mvsx and -mno-altivec are incompatible");
2744 msg = N_("-mno-altivec disables vsx");
2750 target_flags &= ~ MASK_VSX;
2751 target_flags_explicit |= MASK_VSX;
2755 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
2756 unless the user explicitly used the -mno-<option> to disable the code. */
2758 target_flags |= (ISA_2_6_MASKS_SERVER & ~target_flags_explicit);
2759 else if (TARGET_POPCNTD)
2760 target_flags |= (ISA_2_6_MASKS_EMBEDDED & ~target_flags_explicit);
2761 else if (TARGET_DFP)
2762 target_flags |= (ISA_2_5_MASKS_SERVER & ~target_flags_explicit);
2763 else if (TARGET_CMPB)
2764 target_flags |= (ISA_2_5_MASKS_EMBEDDED & ~target_flags_explicit);
2765 else if (TARGET_FPRND)
2766 target_flags |= (ISA_2_4_MASKS & ~target_flags_explicit);
2767 else if (TARGET_POPCNTB)
2768 target_flags |= (ISA_2_2_MASKS & ~target_flags_explicit);
2769 else if (TARGET_ALTIVEC)
2770 target_flags |= (MASK_PPC_GFXOPT & ~target_flags_explicit);
2772 /* E500mc does "better" if we inline more aggressively. Respect the
2773 user's opinion, though. */
2774 if (rs6000_block_move_inline_limit == 0
2775 && (rs6000_cpu == PROCESSOR_PPCE500MC
2776 || rs6000_cpu == PROCESSOR_PPCE500MC64))
2777 rs6000_block_move_inline_limit = 128;
2779 /* store_one_arg depends on expand_block_move to handle at least the
2780 size of reg_parm_stack_space. */
2781 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
2782 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
2786 /* If the appropriate debug option is enabled, replace the target hooks
2787 with debug versions that call the real version and then prints
2788 debugging information. */
2789 if (TARGET_DEBUG_COST)
2791 targetm.rtx_costs = rs6000_debug_rtx_costs;
2792 targetm.address_cost = rs6000_debug_address_cost;
2793 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
2796 if (TARGET_DEBUG_ADDR)
2798 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
2799 targetm.legitimize_address = rs6000_debug_legitimize_address;
2800 rs6000_secondary_reload_class_ptr
2801 = rs6000_debug_secondary_reload_class;
2802 rs6000_secondary_memory_needed_ptr
2803 = rs6000_debug_secondary_memory_needed;
2804 rs6000_cannot_change_mode_class_ptr
2805 = rs6000_debug_cannot_change_mode_class;
2806 rs6000_preferred_reload_class_ptr
2807 = rs6000_debug_preferred_reload_class;
2808 rs6000_legitimize_reload_address_ptr
2809 = rs6000_debug_legitimize_reload_address;
2810 rs6000_mode_dependent_address_ptr
2811 = rs6000_debug_mode_dependent_address;
2814 if (rs6000_veclibabi_name)
2816 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
2817 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
2820 error ("unknown vectorization library ABI type (%s) for "
2821 "-mveclibabi= switch", rs6000_veclibabi_name);
2827 if (!global_options_set.x_rs6000_long_double_type_size)
2829 if (main_target_opt != NULL
2830 && (main_target_opt->x_rs6000_long_double_type_size
2831 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
2832 error ("target attribute or pragma changes long double size");
2834 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2837 #ifndef POWERPC_LINUX
2838 if (!global_options_set.x_rs6000_ieeequad)
2839 rs6000_ieeequad = 1;
2842 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
2843 target attribute or pragma which automatically enables both options,
2844 unless the altivec ABI was set. This is set by default for 64-bit, but
2846 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2847 target_flags &= ~((MASK_VSX | MASK_ALTIVEC) & ~target_flags_explicit);
2849 /* Enable Altivec ABI for AIX -maltivec. */
2850 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
2852 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
2853 error ("target attribute or pragma changes AltiVec ABI");
2855 rs6000_altivec_abi = 1;
2858 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
2859 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
2860 be explicitly overridden in either case. */
2863 if (!global_options_set.x_rs6000_altivec_abi
2864 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
2866 if (main_target_opt != NULL &&
2867 !main_target_opt->x_rs6000_altivec_abi)
2868 error ("target attribute or pragma changes AltiVec ABI");
2870 rs6000_altivec_abi = 1;
2873 /* Enable VRSAVE for AltiVec ABI, unless explicitly overridden. */
2874 if (!global_options_set.x_TARGET_ALTIVEC_VRSAVE)
2875 TARGET_ALTIVEC_VRSAVE = rs6000_altivec_abi;
2878 /* Set the Darwin64 ABI as default for 64-bit Darwin.
2879 So far, the only darwin64 targets are also MACH-O. */
2881 && DEFAULT_ABI == ABI_DARWIN
2884 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
2885 error ("target attribute or pragma changes darwin64 ABI");
2888 rs6000_darwin64_abi = 1;
2889 /* Default to natural alignment, for better performance. */
2890 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2894 /* Place FP constants in the constant pool instead of TOC
2895 if section anchors enabled. */
2896 if (flag_section_anchors)
2897 TARGET_NO_FP_IN_TOC = 1;
2899 #ifdef SUBTARGET_OVERRIDE_OPTIONS
2900 SUBTARGET_OVERRIDE_OPTIONS;
2902 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
2903 SUBSUBTARGET_OVERRIDE_OPTIONS;
2905 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
2906 SUB3TARGET_OVERRIDE_OPTIONS;
2909 if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC
2910 || rs6000_cpu == PROCESSOR_PPCE500MC64)
2912 /* The e500 and e500mc do not have string instructions, and we set
2913 MASK_STRING above when optimizing for size. */
2914 if ((target_flags & MASK_STRING) != 0)
2915 target_flags = target_flags & ~MASK_STRING;
2917 else if (global_options_set.x_rs6000_cpu_index)
2919 /* For the powerpc-eabispe configuration, we set all these by
2920 default, so let's unset them if we manually set another
2921 CPU that is not the E500. */
2922 if (main_target_opt != NULL
2923 && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
2924 || (main_target_opt->x_rs6000_spe != rs6000_spe)
2925 || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
2926 error ("target attribute or pragma changes SPE ABI");
2929 if (!global_options_set.x_rs6000_spe_abi)
2931 if (!global_options_set.x_rs6000_spe)
2933 if (!global_options_set.x_rs6000_float_gprs)
2934 rs6000_float_gprs = 0;
2936 if (!(target_flags_explicit & MASK_ISEL))
2937 target_flags &= ~MASK_ISEL;
2940 /* Detect invalid option combinations with E500. */
2943 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
2944 && rs6000_cpu != PROCESSOR_POWER5
2945 && rs6000_cpu != PROCESSOR_POWER6
2946 && rs6000_cpu != PROCESSOR_POWER7
2947 && rs6000_cpu != PROCESSOR_PPCA2
2948 && rs6000_cpu != PROCESSOR_CELL);
2949 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
2950 || rs6000_cpu == PROCESSOR_POWER5
2951 || rs6000_cpu == PROCESSOR_POWER7);
2952 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
2953 || rs6000_cpu == PROCESSOR_POWER5
2954 || rs6000_cpu == PROCESSOR_POWER6
2955 || rs6000_cpu == PROCESSOR_POWER7
2956 || rs6000_cpu == PROCESSOR_PPCE500MC
2957 || rs6000_cpu == PROCESSOR_PPCE500MC64);
2959 /* Allow debug switches to override the above settings. These are set to -1
2960 in rs6000.opt to indicate the user hasn't directly set the switch. */
2961 if (TARGET_ALWAYS_HINT >= 0)
2962 rs6000_always_hint = TARGET_ALWAYS_HINT;
2964 if (TARGET_SCHED_GROUPS >= 0)
2965 rs6000_sched_groups = TARGET_SCHED_GROUPS;
2967 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
2968 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
2970 rs6000_sched_restricted_insns_priority
2971 = (rs6000_sched_groups ? 1 : 0);
2973 /* Handle -msched-costly-dep option. */
2974 rs6000_sched_costly_dep
2975 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
2977 if (rs6000_sched_costly_dep_str)
2979 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
2980 rs6000_sched_costly_dep = no_dep_costly;
2981 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
2982 rs6000_sched_costly_dep = all_deps_costly;
2983 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
2984 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
2985 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
2986 rs6000_sched_costly_dep = store_to_load_dep_costly;
2988 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
2989 atoi (rs6000_sched_costly_dep_str));
2992 /* Handle -minsert-sched-nops option. */
2993 rs6000_sched_insert_nops
2994 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
2996 if (rs6000_sched_insert_nops_str)
2998 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
2999 rs6000_sched_insert_nops = sched_finish_none;
3000 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
3001 rs6000_sched_insert_nops = sched_finish_pad_groups;
3002 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
3003 rs6000_sched_insert_nops = sched_finish_regroup_exact;
3005 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
3006 atoi (rs6000_sched_insert_nops_str));
3011 #ifdef TARGET_REGNAMES
3012 /* If the user desires alternate register names, copy in the
3013 alternate names now. */
3014 if (TARGET_REGNAMES)
3015 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
3018 /* Set aix_struct_return last, after the ABI is determined.
3019 If -maix-struct-return or -msvr4-struct-return was explicitly
3020 used, don't override with the ABI default. */
3021 if (!global_options_set.x_aix_struct_return)
3022 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
3025 /* IBM XL compiler defaults to unsigned bitfields. */
3026 if (TARGET_XL_COMPAT)
3027 flag_signed_bitfields = 0;
3030 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
3031 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
3034 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
3036 /* We can only guarantee the availability of DI pseudo-ops when
3037 assembling for 64-bit targets. */
3040 targetm.asm_out.aligned_op.di = NULL;
3041 targetm.asm_out.unaligned_op.di = NULL;
3045 /* Set branch target alignment, if not optimizing for size. */
3048 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3049 aligned 8byte to avoid misprediction by the branch predictor. */
3050 if (rs6000_cpu == PROCESSOR_TITAN
3051 || rs6000_cpu == PROCESSOR_CELL)
3053 if (align_functions <= 0)
3054 align_functions = 8;
3055 if (align_jumps <= 0)
3057 if (align_loops <= 0)
3060 if (rs6000_align_branch_targets)
3062 if (align_functions <= 0)
3063 align_functions = 16;
3064 if (align_jumps <= 0)
3066 if (align_loops <= 0)
3068 can_override_loop_align = 1;
3072 if (align_jumps_max_skip <= 0)
3073 align_jumps_max_skip = 15;
3074 if (align_loops_max_skip <= 0)
3075 align_loops_max_skip = 15;
3078 /* Arrange to save and restore machine status around nested functions. */
3079 init_machine_status = rs6000_init_machine_status;
3081 /* We should always be splitting complex arguments, but we can't break
3082 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3083 if (DEFAULT_ABI != ABI_AIX)
3084 targetm.calls.split_complex_arg = NULL;
3087 /* Initialize rs6000_cost with the appropriate target costs. */
3089 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
3093 case PROCESSOR_RIOS1:
3094 rs6000_cost = &rios1_cost;
3097 case PROCESSOR_RIOS2:
3098 rs6000_cost = &rios2_cost;
3101 case PROCESSOR_RS64A:
3102 rs6000_cost = &rs64a_cost;
3105 case PROCESSOR_MPCCORE:
3106 rs6000_cost = &mpccore_cost;
3109 case PROCESSOR_PPC403:
3110 rs6000_cost = &ppc403_cost;
3113 case PROCESSOR_PPC405:
3114 rs6000_cost = &ppc405_cost;
3117 case PROCESSOR_PPC440:
3118 rs6000_cost = &ppc440_cost;
3121 case PROCESSOR_PPC476:
3122 rs6000_cost = &ppc476_cost;
3125 case PROCESSOR_PPC601:
3126 rs6000_cost = &ppc601_cost;
3129 case PROCESSOR_PPC603:
3130 rs6000_cost = &ppc603_cost;
3133 case PROCESSOR_PPC604:
3134 rs6000_cost = &ppc604_cost;
3137 case PROCESSOR_PPC604e:
3138 rs6000_cost = &ppc604e_cost;
3141 case PROCESSOR_PPC620:
3142 rs6000_cost = &ppc620_cost;
3145 case PROCESSOR_PPC630:
3146 rs6000_cost = &ppc630_cost;
3149 case PROCESSOR_CELL:
3150 rs6000_cost = &ppccell_cost;
3153 case PROCESSOR_PPC750:
3154 case PROCESSOR_PPC7400:
3155 rs6000_cost = &ppc750_cost;
3158 case PROCESSOR_PPC7450:
3159 rs6000_cost = &ppc7450_cost;
3162 case PROCESSOR_PPC8540:
3163 rs6000_cost = &ppc8540_cost;
3166 case PROCESSOR_PPCE300C2:
3167 case PROCESSOR_PPCE300C3:
3168 rs6000_cost = &ppce300c2c3_cost;
3171 case PROCESSOR_PPCE500MC:
3172 rs6000_cost = &ppce500mc_cost;
3175 case PROCESSOR_PPCE500MC64:
3176 rs6000_cost = &ppce500mc64_cost;
3179 case PROCESSOR_TITAN:
3180 rs6000_cost = &titan_cost;
3183 case PROCESSOR_POWER4:
3184 case PROCESSOR_POWER5:
3185 rs6000_cost = &power4_cost;
3188 case PROCESSOR_POWER6:
3189 rs6000_cost = &power6_cost;
3192 case PROCESSOR_POWER7:
3193 rs6000_cost = &power7_cost;
3196 case PROCESSOR_PPCA2:
3197 rs6000_cost = &ppca2_cost;
3206 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
3207 rs6000_cost->simultaneous_prefetches,
3208 global_options.x_param_values,
3209 global_options_set.x_param_values);
3210 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
3211 global_options.x_param_values,
3212 global_options_set.x_param_values);
3213 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
3214 rs6000_cost->cache_line_size,
3215 global_options.x_param_values,
3216 global_options_set.x_param_values);
3217 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
3218 global_options.x_param_values,
3219 global_options_set.x_param_values);
3221 /* If using typedef char *va_list, signal that
3222 __builtin_va_start (&ap, 0) can be optimized to
3223 ap = __builtin_next_arg (0). */
3224 if (DEFAULT_ABI != ABI_V4)
3225 targetm.expand_builtin_va_start = NULL;
3228 /* Set up single/double float flags.
3229 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3230 then set both flags. */
3231 if (TARGET_HARD_FLOAT && TARGET_FPRS
3232 && rs6000_single_float == 0 && rs6000_double_float == 0)
3233 rs6000_single_float = rs6000_double_float = 1;
3235 /* Reset single and double FP flags if target is E500. */
3238 rs6000_single_float = rs6000_double_float = 0;
3239 if (TARGET_E500_SINGLE)
3240 rs6000_single_float = 1;
3241 if (TARGET_E500_DOUBLE)
3242 rs6000_single_float = rs6000_double_float = 1;
3245 if (main_target_opt)
3247 if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
3248 error ("target attribute or pragma changes single precision floating "
3250 if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
3251 error ("target attribute or pragma changes double precision floating "
3255 /* If not explicitly specified via option, decide whether to generate indexed
3256 load/store instructions. */
3257 if (TARGET_AVOID_XFORM == -1)
3258 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3259 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3260 need indexed accesses and the type used is the scalar type of the element
3261 being loaded or stored. */
3262 TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB
3263 && !TARGET_ALTIVEC);
3265 /* Set the -mrecip options. */
3266 if (rs6000_recip_name)
3268 char *p = ASTRDUP (rs6000_recip_name);
3270 unsigned int mask, i;
3273 while ((q = strtok (p, ",")) != NULL)
3284 if (!strcmp (q, "default"))
3285 mask = ((TARGET_RECIP_PRECISION)
3286 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
3289 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
3290 if (!strcmp (q, recip_options[i].string))
3292 mask = recip_options[i].mask;
3296 if (i == ARRAY_SIZE (recip_options))
3298 error ("unknown option for -mrecip=%s", q);
3306 rs6000_recip_control &= ~mask;
3308 rs6000_recip_control |= mask;
3312 /* Set the builtin mask of the various options used that could affect which
3313 builtins were used. In the past we used target_flags, but we've run out
3314 of bits, and some options like SPE and PAIRED are no longer in
3316 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
3317 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
3318 fprintf (stderr, "new builtin mask = 0x%x%s%s%s%s\n", rs6000_builtin_mask,
3319 (rs6000_builtin_mask & RS6000_BTM_ALTIVEC) ? ", altivec" : "",
3320 (rs6000_builtin_mask & RS6000_BTM_VSX) ? ", vsx" : "",
3321 (rs6000_builtin_mask & RS6000_BTM_PAIRED) ? ", paired" : "",
3322 (rs6000_builtin_mask & RS6000_BTM_SPE) ? ", spe" : "");
3324 /* Initialize all of the registers. */
3325 rs6000_init_hard_regno_mode_ok (global_init_p);
3327 /* Save the initial options in case the user does function specific options */
3329 target_option_default_node = target_option_current_node
3330 = build_target_option_node ();
3332 /* If not explicitly specified via option, decide whether to generate the
3333 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3334 if (TARGET_LINK_STACK == -1)
3335 SET_TARGET_LINK_STACK (rs6000_cpu == PROCESSOR_PPC476 && flag_pic);
3340 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3341 define the target cpu type. */
3344 rs6000_option_override (void)
3346 (void) rs6000_option_override_internal (true);
3350 /* Implement targetm.vectorize.builtin_mask_for_load. */
3352 rs6000_builtin_mask_for_load (void)
3354 if (TARGET_ALTIVEC || TARGET_VSX)
3355 return altivec_builtin_mask_for_load;
3360 /* Implement LOOP_ALIGN. */
3362 rs6000_loop_align (rtx label)
3367 /* Don't override loop alignment if -falign-loops was specified. */
3368 if (!can_override_loop_align)
3369 return align_loops_log;
3371 bb = BLOCK_FOR_INSN (label);
3372 ninsns = num_loop_insns(bb->loop_father);
3374 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3375 if (ninsns > 4 && ninsns <= 8
3376 && (rs6000_cpu == PROCESSOR_POWER4
3377 || rs6000_cpu == PROCESSOR_POWER5
3378 || rs6000_cpu == PROCESSOR_POWER6
3379 || rs6000_cpu == PROCESSOR_POWER7))
3382 return align_loops_log;
3385 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3387 rs6000_loop_align_max_skip (rtx label)
3389 return (1 << rs6000_loop_align (label)) - 1;
3392 /* Implement targetm.vectorize.builtin_mul_widen_even. */
3394 rs6000_builtin_mul_widen_even (tree type)
3396 if (!TARGET_ALTIVEC)
3399 switch (TYPE_MODE (type))
3402 return TYPE_UNSIGNED (type)
3403 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH_UNS]
3404 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
3407 return TYPE_UNSIGNED (type)
3408 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB_UNS]
3409 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
3415 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
3417 rs6000_builtin_mul_widen_odd (tree type)
3419 if (!TARGET_ALTIVEC)
3422 switch (TYPE_MODE (type))
3425 return TYPE_UNSIGNED (type)
3426 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH_UNS]
3427 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
3430 return TYPE_UNSIGNED (type)
3431 ? rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB_UNS]
3432 : rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
3439 /* Return true iff, data reference of TYPE can reach vector alignment (16)
3440 after applying N number of iterations. This routine does not determine
3441 how may iterations are required to reach desired alignment. */
3444 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
3451 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
3454 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
3464 /* Assuming that all other types are naturally aligned. CHECKME! */
3469 /* Return true if the vector misalignment factor is supported by the
3472 rs6000_builtin_support_vector_misalignment (enum machine_mode mode,
3479 /* Return if movmisalign pattern is not supported for this mode. */
3480 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
3483 if (misalignment == -1)
3485 /* Misalignment factor is unknown at compile time but we know
3486 it's word aligned. */
3487 if (rs6000_vector_alignment_reachable (type, is_packed))
3489 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
3491 if (element_size == 64 || element_size == 32)
3498 /* VSX supports word-aligned vector. */
3499 if (misalignment % 4 == 0)
3505 /* Implement targetm.vectorize.builtin_vectorization_cost. */
3507 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
3508 tree vectype, int misalign)
3512 switch (type_of_cost)
3522 case cond_branch_not_taken:
3526 case cond_branch_taken:
3529 case unaligned_load:
3530 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3532 elements = TYPE_VECTOR_SUBPARTS (vectype);
3534 /* Double word aligned. */
3542 /* Double word aligned. */
3546 /* Unknown misalignment. */
3559 /* Misaligned loads are not supported. */
3564 case unaligned_store:
3565 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
3567 elements = TYPE_VECTOR_SUBPARTS (vectype);
3569 /* Double word aligned. */
3577 /* Double word aligned. */
3581 /* Unknown misalignment. */
3594 /* Misaligned stores are not supported. */
3604 /* Implement targetm.vectorize.preferred_simd_mode. */
3606 static enum machine_mode
3607 rs6000_preferred_simd_mode (enum machine_mode mode)
3616 if (TARGET_ALTIVEC || TARGET_VSX)
3640 if (TARGET_PAIRED_FLOAT
3646 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
3647 library with vectorized intrinsics. */
3650 rs6000_builtin_vectorized_libmass (tree fndecl, tree type_out, tree type_in)
3653 const char *suffix = NULL;
3654 tree fntype, new_fndecl, bdecl = NULL_TREE;
3657 enum machine_mode el_mode, in_mode;
3660 /* Libmass is suitable for unsafe math only as it does not correctly support
3661 parts of IEEE with the required precision such as denormals. Only support
3662 it if we have VSX to use the simd d2 or f4 functions.
3663 XXX: Add variable length support. */
3664 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
3667 el_mode = TYPE_MODE (TREE_TYPE (type_out));
3668 n = TYPE_VECTOR_SUBPARTS (type_out);
3669 in_mode = TYPE_MODE (TREE_TYPE (type_in));
3670 in_n = TYPE_VECTOR_SUBPARTS (type_in);
3671 if (el_mode != in_mode
3675 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3677 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3680 case BUILT_IN_ATAN2:
3681 case BUILT_IN_HYPOT:
3687 case BUILT_IN_ACOSH:
3689 case BUILT_IN_ASINH:
3691 case BUILT_IN_ATANH:
3699 case BUILT_IN_EXPM1:
3700 case BUILT_IN_LGAMMA:
3701 case BUILT_IN_LOG10:
3702 case BUILT_IN_LOG1P:
3710 bdecl = builtin_decl_implicit (fn);
3711 suffix = "d2"; /* pow -> powd2 */
3712 if (el_mode != DFmode
3717 case BUILT_IN_ATAN2F:
3718 case BUILT_IN_HYPOTF:
3723 case BUILT_IN_ACOSF:
3724 case BUILT_IN_ACOSHF:
3725 case BUILT_IN_ASINF:
3726 case BUILT_IN_ASINHF:
3727 case BUILT_IN_ATANF:
3728 case BUILT_IN_ATANHF:
3729 case BUILT_IN_CBRTF:
3731 case BUILT_IN_COSHF:
3733 case BUILT_IN_ERFCF:
3734 case BUILT_IN_EXP2F:
3736 case BUILT_IN_EXPM1F:
3737 case BUILT_IN_LGAMMAF:
3738 case BUILT_IN_LOG10F:
3739 case BUILT_IN_LOG1PF:
3740 case BUILT_IN_LOG2F:
3743 case BUILT_IN_SINHF:
3744 case BUILT_IN_SQRTF:
3746 case BUILT_IN_TANHF:
3747 bdecl = builtin_decl_implicit (fn);
3748 suffix = "4"; /* powf -> powf4 */
3749 if (el_mode != SFmode
3761 gcc_assert (suffix != NULL);
3762 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
3763 strcpy (name, bname + sizeof ("__builtin_") - 1);
3764 strcat (name, suffix);
3767 fntype = build_function_type_list (type_out, type_in, NULL);
3768 else if (n_args == 2)
3769 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
3773 /* Build a function declaration for the vectorized function. */
3774 new_fndecl = build_decl (BUILTINS_LOCATION,
3775 FUNCTION_DECL, get_identifier (name), fntype);
3776 TREE_PUBLIC (new_fndecl) = 1;
3777 DECL_EXTERNAL (new_fndecl) = 1;
3778 DECL_IS_NOVOPS (new_fndecl) = 1;
3779 TREE_READONLY (new_fndecl) = 1;
3784 /* Returns a function decl for a vectorized version of the builtin function
3785 with builtin function code FN and the result vector type TYPE, or NULL_TREE
3786 if it is not available. */
3789 rs6000_builtin_vectorized_function (tree fndecl, tree type_out,
3792 enum machine_mode in_mode, out_mode;
3795 if (TARGET_DEBUG_BUILTIN)
3796 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
3797 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
3798 GET_MODE_NAME (TYPE_MODE (type_out)),
3799 GET_MODE_NAME (TYPE_MODE (type_in)));
3801 if (TREE_CODE (type_out) != VECTOR_TYPE
3802 || TREE_CODE (type_in) != VECTOR_TYPE
3803 || !TARGET_VECTORIZE_BUILTINS)
3806 out_mode = TYPE_MODE (TREE_TYPE (type_out));
3807 out_n = TYPE_VECTOR_SUBPARTS (type_out);
3808 in_mode = TYPE_MODE (TREE_TYPE (type_in));
3809 in_n = TYPE_VECTOR_SUBPARTS (type_in);
3811 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
3813 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
3816 case BUILT_IN_COPYSIGN:
3817 if (VECTOR_UNIT_VSX_P (V2DFmode)
3818 && out_mode == DFmode && out_n == 2
3819 && in_mode == DFmode && in_n == 2)
3820 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
3822 case BUILT_IN_COPYSIGNF:
3823 if (out_mode != SFmode || out_n != 4
3824 || in_mode != SFmode || in_n != 4)
3826 if (VECTOR_UNIT_VSX_P (V4SFmode))
3827 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
3828 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3829 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
3832 if (VECTOR_UNIT_VSX_P (V2DFmode)
3833 && out_mode == DFmode && out_n == 2
3834 && in_mode == DFmode && in_n == 2)
3835 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTDP];
3837 case BUILT_IN_SQRTF:
3838 if (VECTOR_UNIT_VSX_P (V4SFmode)
3839 && out_mode == SFmode && out_n == 4
3840 && in_mode == SFmode && in_n == 4)
3841 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTSP];
3844 if (VECTOR_UNIT_VSX_P (V2DFmode)
3845 && out_mode == DFmode && out_n == 2
3846 && in_mode == DFmode && in_n == 2)
3847 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
3849 case BUILT_IN_CEILF:
3850 if (out_mode != SFmode || out_n != 4
3851 || in_mode != SFmode || in_n != 4)
3853 if (VECTOR_UNIT_VSX_P (V4SFmode))
3854 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
3855 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3856 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
3858 case BUILT_IN_FLOOR:
3859 if (VECTOR_UNIT_VSX_P (V2DFmode)
3860 && out_mode == DFmode && out_n == 2
3861 && in_mode == DFmode && in_n == 2)
3862 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
3864 case BUILT_IN_FLOORF:
3865 if (out_mode != SFmode || out_n != 4
3866 || in_mode != SFmode || in_n != 4)
3868 if (VECTOR_UNIT_VSX_P (V4SFmode))
3869 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
3870 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3871 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
3874 if (VECTOR_UNIT_VSX_P (V2DFmode)
3875 && out_mode == DFmode && out_n == 2
3876 && in_mode == DFmode && in_n == 2)
3877 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
3880 if (VECTOR_UNIT_VSX_P (V4SFmode)
3881 && out_mode == SFmode && out_n == 4
3882 && in_mode == SFmode && in_n == 4)
3883 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
3884 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
3885 && out_mode == SFmode && out_n == 4
3886 && in_mode == SFmode && in_n == 4)
3887 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
3889 case BUILT_IN_TRUNC:
3890 if (VECTOR_UNIT_VSX_P (V2DFmode)
3891 && out_mode == DFmode && out_n == 2
3892 && in_mode == DFmode && in_n == 2)
3893 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
3895 case BUILT_IN_TRUNCF:
3896 if (out_mode != SFmode || out_n != 4
3897 || in_mode != SFmode || in_n != 4)
3899 if (VECTOR_UNIT_VSX_P (V4SFmode))
3900 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
3901 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
3902 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
3904 case BUILT_IN_NEARBYINT:
3905 if (VECTOR_UNIT_VSX_P (V2DFmode)
3906 && flag_unsafe_math_optimizations
3907 && out_mode == DFmode && out_n == 2
3908 && in_mode == DFmode && in_n == 2)
3909 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
3911 case BUILT_IN_NEARBYINTF:
3912 if (VECTOR_UNIT_VSX_P (V4SFmode)
3913 && flag_unsafe_math_optimizations
3914 && out_mode == SFmode && out_n == 4
3915 && in_mode == SFmode && in_n == 4)
3916 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
3919 if (VECTOR_UNIT_VSX_P (V2DFmode)
3920 && !flag_trapping_math
3921 && out_mode == DFmode && out_n == 2
3922 && in_mode == DFmode && in_n == 2)
3923 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
3925 case BUILT_IN_RINTF:
3926 if (VECTOR_UNIT_VSX_P (V4SFmode)
3927 && !flag_trapping_math
3928 && out_mode == SFmode && out_n == 4
3929 && in_mode == SFmode && in_n == 4)
3930 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
3937 else if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
3939 enum rs6000_builtins fn
3940 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
3943 case RS6000_BUILTIN_RSQRTF:
3944 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3945 && out_mode == SFmode && out_n == 4
3946 && in_mode == SFmode && in_n == 4)
3947 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
3949 case RS6000_BUILTIN_RSQRT:
3950 if (VECTOR_UNIT_VSX_P (V2DFmode)
3951 && out_mode == DFmode && out_n == 2
3952 && in_mode == DFmode && in_n == 2)
3953 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
3955 case RS6000_BUILTIN_RECIPF:
3956 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
3957 && out_mode == SFmode && out_n == 4
3958 && in_mode == SFmode && in_n == 4)
3959 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
3961 case RS6000_BUILTIN_RECIP:
3962 if (VECTOR_UNIT_VSX_P (V2DFmode)
3963 && out_mode == DFmode && out_n == 2
3964 && in_mode == DFmode && in_n == 2)
3965 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
3972 /* Generate calls to libmass if appropriate. */
3973 if (rs6000_veclib_handler)
3974 return rs6000_veclib_handler (fndecl, type_out, type_in);
3979 /* Default CPU string for rs6000*_file_start functions. */
3980 static const char *rs6000_default_cpu;
3982 /* Do anything needed at the start of the asm file. */
3985 rs6000_file_start (void)
3988 const char *start = buffer;
3989 FILE *file = asm_out_file;
3991 rs6000_default_cpu = TARGET_CPU_DEFAULT;
3993 default_file_start ();
3995 #ifdef TARGET_BI_ARCH
3996 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
3997 rs6000_default_cpu = 0;
4000 if (flag_verbose_asm)
4002 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
4004 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
4006 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
4010 if (global_options_set.x_rs6000_cpu_index)
4012 fprintf (file, "%s -mcpu=%s", start,
4013 processor_target_table[rs6000_cpu_index].name);
4017 if (global_options_set.x_rs6000_tune_index)
4019 fprintf (file, "%s -mtune=%s", start,
4020 processor_target_table[rs6000_tune_index].name);
4024 if (PPC405_ERRATUM77)
4026 fprintf (file, "%s PPC405CR_ERRATUM77", start);
4030 #ifdef USING_ELFOS_H
4031 switch (rs6000_sdata)
4033 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
4034 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
4035 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
4036 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
4039 if (rs6000_sdata && g_switch_value)
4041 fprintf (file, "%s -G %d", start,
4051 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
4053 switch_to_section (toc_section);
4054 switch_to_section (text_section);
4059 /* Return nonzero if this function is known to have a null epilogue. */
4062 direct_return (void)
4064 if (reload_completed)
4066 rs6000_stack_t *info = rs6000_stack_info ();
4068 if (info->first_gp_reg_save == 32
4069 && info->first_fp_reg_save == 64
4070 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
4071 && ! info->lr_save_p
4072 && ! info->cr_save_p
4073 && info->vrsave_mask == 0
4081 /* Return the number of instructions it takes to form a constant in an
4082 integer register. */
4085 num_insns_constant_wide (HOST_WIDE_INT value)
4087 /* signed constant loadable with {cal|addi} */
4088 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
4091 /* constant loadable with {cau|addis} */
4092 else if ((value & 0xffff) == 0
4093 && (value >> 31 == -1 || value >> 31 == 0))
4096 #if HOST_BITS_PER_WIDE_INT == 64
4097 else if (TARGET_POWERPC64)
4099 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
4100 HOST_WIDE_INT high = value >> 31;
4102 if (high == 0 || high == -1)
4108 return num_insns_constant_wide (high) + 1;
4110 return num_insns_constant_wide (low) + 1;
4112 return (num_insns_constant_wide (high)
4113 + num_insns_constant_wide (low) + 1);
4122 num_insns_constant (rtx op, enum machine_mode mode)
4124 HOST_WIDE_INT low, high;
4126 switch (GET_CODE (op))
4129 #if HOST_BITS_PER_WIDE_INT == 64
4130 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
4131 && mask64_operand (op, mode))
4135 return num_insns_constant_wide (INTVAL (op));
4138 if (mode == SFmode || mode == SDmode)
4143 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4144 if (DECIMAL_FLOAT_MODE_P (mode))
4145 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
4147 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
4148 return num_insns_constant_wide ((HOST_WIDE_INT) l);
4151 if (mode == VOIDmode || mode == DImode)
4153 high = CONST_DOUBLE_HIGH (op);
4154 low = CONST_DOUBLE_LOW (op);
4161 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
4162 if (DECIMAL_FLOAT_MODE_P (mode))
4163 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
4165 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
4166 high = l[WORDS_BIG_ENDIAN == 0];
4167 low = l[WORDS_BIG_ENDIAN != 0];
4171 return (num_insns_constant_wide (low)
4172 + num_insns_constant_wide (high));
4175 if ((high == 0 && low >= 0)
4176 || (high == -1 && low < 0))
4177 return num_insns_constant_wide (low);
4179 else if (mask64_operand (op, mode))
4183 return num_insns_constant_wide (high) + 1;
4186 return (num_insns_constant_wide (high)
4187 + num_insns_constant_wide (low) + 1);
4195 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4196 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4197 corresponding element of the vector, but for V4SFmode and V2SFmode,
4198 the corresponding "float" is interpreted as an SImode integer. */
4201 const_vector_elt_as_int (rtx op, unsigned int elt)
4205 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4206 gcc_assert (GET_MODE (op) != V2DImode
4207 && GET_MODE (op) != V2DFmode);
4209 tmp = CONST_VECTOR_ELT (op, elt);
4210 if (GET_MODE (op) == V4SFmode
4211 || GET_MODE (op) == V2SFmode)
4212 tmp = gen_lowpart (SImode, tmp);
4213 return INTVAL (tmp);
4216 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4217 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4218 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4219 all items are set to the same value and contain COPIES replicas of the
4220 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4221 operand and the others are set to the value of the operand's msb. */
4224 vspltis_constant (rtx op, unsigned step, unsigned copies)
4226 enum machine_mode mode = GET_MODE (op);
4227 enum machine_mode inner = GET_MODE_INNER (mode);
4235 HOST_WIDE_INT splat_val;
4236 HOST_WIDE_INT msb_val;
4238 if (mode == V2DImode || mode == V2DFmode)
4241 nunits = GET_MODE_NUNITS (mode);
4242 bitsize = GET_MODE_BITSIZE (inner);
4243 mask = GET_MODE_MASK (inner);
4245 val = const_vector_elt_as_int (op, nunits - 1);
4247 msb_val = val > 0 ? 0 : -1;
4249 /* Construct the value to be splatted, if possible. If not, return 0. */
4250 for (i = 2; i <= copies; i *= 2)
4252 HOST_WIDE_INT small_val;
4254 small_val = splat_val >> bitsize;
4256 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
4258 splat_val = small_val;
4261 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
4262 if (EASY_VECTOR_15 (splat_val))
4265 /* Also check if we can splat, and then add the result to itself. Do so if
4266 the value is positive, of if the splat instruction is using OP's mode;
4267 for splat_val < 0, the splat and the add should use the same mode. */
4268 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
4269 && (splat_val >= 0 || (step == 1 && copies == 1)))
4272 /* Also check if are loading up the most significant bit which can be done by
4273 loading up -1 and shifting the value left by -1. */
4274 else if (EASY_VECTOR_MSB (splat_val, inner))
4280 /* Check if VAL is present in every STEP-th element, and the
4281 other elements are filled with its most significant bit. */
4282 for (i = 0; i < nunits - 1; ++i)
4284 HOST_WIDE_INT desired_val;
4285 if (((i + 1) & (step - 1)) == 0)
4288 desired_val = msb_val;
4290 if (desired_val != const_vector_elt_as_int (op, i))
4298 /* Return true if OP is of the given MODE and can be synthesized
4299 with a vspltisb, vspltish or vspltisw. */
4302 easy_altivec_constant (rtx op, enum machine_mode mode)
4304 unsigned step, copies;
4306 if (mode == VOIDmode)
4307 mode = GET_MODE (op);
4308 else if (mode != GET_MODE (op))
4311 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
4313 if (mode == V2DFmode)
4314 return zero_constant (op, mode);
4316 if (mode == V2DImode)
4318 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
4320 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
4321 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
4324 if (zero_constant (op, mode))
4327 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
4328 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
4334 /* Start with a vspltisw. */
4335 step = GET_MODE_NUNITS (mode) / 4;
4338 if (vspltis_constant (op, step, copies))
4341 /* Then try with a vspltish. */
4347 if (vspltis_constant (op, step, copies))
4350 /* And finally a vspltisb. */
4356 if (vspltis_constant (op, step, copies))
4362 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
4363 result is OP. Abort if it is not possible. */
4366 gen_easy_altivec_constant (rtx op)
4368 enum machine_mode mode = GET_MODE (op);
4369 int nunits = GET_MODE_NUNITS (mode);
4370 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
4371 unsigned step = nunits / 4;
4372 unsigned copies = 1;
4374 /* Start with a vspltisw. */
4375 if (vspltis_constant (op, step, copies))
4376 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
4378 /* Then try with a vspltish. */
4384 if (vspltis_constant (op, step, copies))
4385 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
4387 /* And finally a vspltisb. */
4393 if (vspltis_constant (op, step, copies))
4394 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
4400 output_vec_const_move (rtx *operands)
4403 enum machine_mode mode;
4408 mode = GET_MODE (dest);
4412 if (zero_constant (vec, mode))
4413 return "xxlxor %x0,%x0,%x0";
4415 if (mode == V2DImode
4416 && INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1
4417 && INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1)
4418 return "vspltisw %0,-1";
4424 if (zero_constant (vec, mode))
4425 return "vxor %0,%0,%0";
4427 splat_vec = gen_easy_altivec_constant (vec);
4428 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
4429 operands[1] = XEXP (splat_vec, 0);
4430 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
4433 switch (GET_MODE (splat_vec))
4436 return "vspltisw %0,%1";
4439 return "vspltish %0,%1";
4442 return "vspltisb %0,%1";
4449 gcc_assert (TARGET_SPE);
4451 /* Vector constant 0 is handled as a splitter of V2SI, and in the
4452 pattern of V1DI, V4HI, and V2SF.
4454 FIXME: We should probably return # and add post reload
4455 splitters for these, but this way is so easy ;-). */
4456 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
4457 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
4458 operands[1] = CONST_VECTOR_ELT (vec, 0);
4459 operands[2] = CONST_VECTOR_ELT (vec, 1);
4461 return "li %0,%1\n\tevmergelo %0,%0,%0";
4463 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
4466 /* Initialize TARGET of vector PAIRED to VALS. */
4469 paired_expand_vector_init (rtx target, rtx vals)
4471 enum machine_mode mode = GET_MODE (target);
4472 int n_elts = GET_MODE_NUNITS (mode);
4474 rtx x, new_rtx, tmp, constant_op, op1, op2;
4477 for (i = 0; i < n_elts; ++i)
4479 x = XVECEXP (vals, 0, i);
4480 if (!(CONST_INT_P (x)
4481 || GET_CODE (x) == CONST_DOUBLE
4482 || GET_CODE (x) == CONST_FIXED))
4487 /* Load from constant pool. */
4488 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
4494 /* The vector is initialized only with non-constants. */
4495 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
4496 XVECEXP (vals, 0, 1));
4498 emit_move_insn (target, new_rtx);
4502 /* One field is non-constant and the other one is a constant. Load the
4503 constant from the constant pool and use ps_merge instruction to
4504 construct the whole vector. */
4505 op1 = XVECEXP (vals, 0, 0);
4506 op2 = XVECEXP (vals, 0, 1);
4508 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
4510 tmp = gen_reg_rtx (GET_MODE (constant_op));
4511 emit_move_insn (tmp, constant_op);
4513 if (CONSTANT_P (op1))
4514 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
4516 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
4518 emit_move_insn (target, new_rtx);
4522 paired_expand_vector_move (rtx operands[])
4524 rtx op0 = operands[0], op1 = operands[1];
4526 emit_move_insn (op0, op1);
4529 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
4530 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
4531 operands for the relation operation COND. This is a recursive
4535 paired_emit_vector_compare (enum rtx_code rcode,
4536 rtx dest, rtx op0, rtx op1,
4537 rtx cc_op0, rtx cc_op1)
4539 rtx tmp = gen_reg_rtx (V2SFmode);
4542 gcc_assert (TARGET_PAIRED_FLOAT);
4543 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
4549 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4553 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4554 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
4558 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
4561 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4564 tmp1 = gen_reg_rtx (V2SFmode);
4565 max = gen_reg_rtx (V2SFmode);
4566 min = gen_reg_rtx (V2SFmode);
4567 gen_reg_rtx (V2SFmode);
4569 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
4570 emit_insn (gen_selv2sf4
4571 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4572 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
4573 emit_insn (gen_selv2sf4
4574 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
4575 emit_insn (gen_subv2sf3 (tmp1, min, max));
4576 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
4579 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
4582 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
4585 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
4588 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
4591 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
4600 /* Emit vector conditional expression.
4601 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
4602 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
4605 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
4606 rtx cond, rtx cc_op0, rtx cc_op1)
4608 enum rtx_code rcode = GET_CODE (cond);
4610 if (!TARGET_PAIRED_FLOAT)
4613 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
4618 /* Initialize vector TARGET to VALS. */
4621 rs6000_expand_vector_init (rtx target, rtx vals)
4623 enum machine_mode mode = GET_MODE (target);
4624 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4625 int n_elts = GET_MODE_NUNITS (mode);
4626 int n_var = 0, one_var = -1;
4627 bool all_same = true, all_const_zero = true;
4631 for (i = 0; i < n_elts; ++i)
4633 x = XVECEXP (vals, 0, i);
4634 if (!(CONST_INT_P (x)
4635 || GET_CODE (x) == CONST_DOUBLE
4636 || GET_CODE (x) == CONST_FIXED))
4637 ++n_var, one_var = i;
4638 else if (x != CONST0_RTX (inner_mode))
4639 all_const_zero = false;
4641 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
4647 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
4648 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
4649 if ((int_vector_p || TARGET_VSX) && all_const_zero)
4651 /* Zero register. */
4652 emit_insn (gen_rtx_SET (VOIDmode, target,
4653 gen_rtx_XOR (mode, target, target)));
4656 else if (int_vector_p && easy_vector_constant (const_vec, mode))
4658 /* Splat immediate. */
4659 emit_insn (gen_rtx_SET (VOIDmode, target, const_vec));
4664 /* Load from constant pool. */
4665 emit_move_insn (target, const_vec);
4670 /* Double word values on VSX can use xxpermdi or lxvdsx. */
4671 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4675 rtx element = XVECEXP (vals, 0, 0);
4676 if (mode == V2DFmode)
4677 emit_insn (gen_vsx_splat_v2df (target, element));
4679 emit_insn (gen_vsx_splat_v2di (target, element));
4683 if (mode == V2DFmode)
4685 rtx op0 = copy_to_mode_reg (DFmode, XVECEXP (vals, 0, 0));
4686 rtx op1 = copy_to_mode_reg (DFmode, XVECEXP (vals, 0, 1));
4687 emit_insn (gen_vsx_concat_v2df (target, op0, op1));
4691 rtx op0 = copy_to_mode_reg (DImode, XVECEXP (vals, 0, 0));
4692 rtx op1 = copy_to_mode_reg (DImode, XVECEXP (vals, 0, 1));
4693 emit_insn (gen_vsx_concat_v2di (target, op0, op1));
4699 /* With single precision floating point on VSX, know that internally single
4700 precision is actually represented as a double, and either make 2 V2DF
4701 vectors, and convert these vectors to single precision, or do one
4702 conversion, and splat the result to the other elements. */
4703 if (mode == V4SFmode && VECTOR_MEM_VSX_P (mode))
4707 rtx freg = gen_reg_rtx (V4SFmode);
4708 rtx sreg = copy_to_reg (XVECEXP (vals, 0, 0));
4710 emit_insn (gen_vsx_xscvdpsp_scalar (freg, sreg));
4711 emit_insn (gen_vsx_xxspltw_v4sf (target, freg, const0_rtx));
4715 rtx dbl_even = gen_reg_rtx (V2DFmode);
4716 rtx dbl_odd = gen_reg_rtx (V2DFmode);
4717 rtx flt_even = gen_reg_rtx (V4SFmode);
4718 rtx flt_odd = gen_reg_rtx (V4SFmode);
4720 emit_insn (gen_vsx_concat_v2sf (dbl_even,
4721 copy_to_reg (XVECEXP (vals, 0, 0)),
4722 copy_to_reg (XVECEXP (vals, 0, 1))));
4723 emit_insn (gen_vsx_concat_v2sf (dbl_odd,
4724 copy_to_reg (XVECEXP (vals, 0, 2)),
4725 copy_to_reg (XVECEXP (vals, 0, 3))));
4726 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
4727 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
4728 rs6000_expand_extract_even (target, flt_even, flt_odd);
4733 /* Store value to stack temp. Load vector element. Splat. However, splat
4734 of 64-bit items is not supported on Altivec. */
4735 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
4737 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
4738 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
4739 XVECEXP (vals, 0, 0));
4740 x = gen_rtx_UNSPEC (VOIDmode,
4741 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4742 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4744 gen_rtx_SET (VOIDmode,
4747 x = gen_rtx_VEC_SELECT (inner_mode, target,
4748 gen_rtx_PARALLEL (VOIDmode,
4749 gen_rtvec (1, const0_rtx)));
4750 emit_insn (gen_rtx_SET (VOIDmode, target,
4751 gen_rtx_VEC_DUPLICATE (mode, x)));
4755 /* One field is non-constant. Load constant then overwrite
4759 rtx copy = copy_rtx (vals);
4761 /* Load constant part of vector, substitute neighboring value for
4763 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
4764 rs6000_expand_vector_init (target, copy);
4766 /* Insert variable. */
4767 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
4771 /* Construct the vector in memory one field at a time
4772 and load the whole vector. */
4773 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
4774 for (i = 0; i < n_elts; i++)
4775 emit_move_insn (adjust_address_nv (mem, inner_mode,
4776 i * GET_MODE_SIZE (inner_mode)),
4777 XVECEXP (vals, 0, i));
4778 emit_move_insn (target, mem);
4781 /* Set field ELT of TARGET to VAL. */
4784 rs6000_expand_vector_set (rtx target, rtx val, int elt)
4786 enum machine_mode mode = GET_MODE (target);
4787 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4788 rtx reg = gen_reg_rtx (mode);
4790 int width = GET_MODE_SIZE (inner_mode);
4793 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
4795 rtx (*set_func) (rtx, rtx, rtx, rtx)
4796 = ((mode == V2DFmode) ? gen_vsx_set_v2df : gen_vsx_set_v2di);
4797 emit_insn (set_func (target, target, val, GEN_INT (elt)));
4801 /* Load single variable value. */
4802 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
4803 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
4804 x = gen_rtx_UNSPEC (VOIDmode,
4805 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
4806 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4808 gen_rtx_SET (VOIDmode,
4812 /* Linear sequence. */
4813 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
4814 for (i = 0; i < 16; ++i)
4815 XVECEXP (mask, 0, i) = GEN_INT (i);
4817 /* Set permute mask to insert element into target. */
4818 for (i = 0; i < width; ++i)
4819 XVECEXP (mask, 0, elt*width + i)
4820 = GEN_INT (i + 0x10);
4821 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
4822 x = gen_rtx_UNSPEC (mode,
4823 gen_rtvec (3, target, reg,
4824 force_reg (V16QImode, x)),
4826 emit_insn (gen_rtx_SET (VOIDmode, target, x));
4829 /* Extract field ELT from VEC into TARGET. */
4832 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
4834 enum machine_mode mode = GET_MODE (vec);
4835 enum machine_mode inner_mode = GET_MODE_INNER (mode);
4838 if (VECTOR_MEM_VSX_P (mode))
4845 emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt)));
4848 emit_insn (gen_vsx_extract_v2di (target, vec, GEN_INT (elt)));
4851 emit_insn (gen_vsx_extract_v4sf (target, vec, GEN_INT (elt)));
4856 /* Allocate mode-sized buffer. */
4857 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
4859 emit_move_insn (mem, vec);
4861 /* Add offset to field within buffer matching vector element. */
4862 mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode));
4864 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
4867 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
4868 implement ANDing by the mask IN. */
4870 build_mask64_2_operands (rtx in, rtx *out)
4872 #if HOST_BITS_PER_WIDE_INT >= 64
4873 unsigned HOST_WIDE_INT c, lsb, m1, m2;
4876 gcc_assert (GET_CODE (in) == CONST_INT);
4881 /* Assume c initially something like 0x00fff000000fffff. The idea
4882 is to rotate the word so that the middle ^^^^^^ group of zeros
4883 is at the MS end and can be cleared with an rldicl mask. We then
4884 rotate back and clear off the MS ^^ group of zeros with a
4886 c = ~c; /* c == 0xff000ffffff00000 */
4887 lsb = c & -c; /* lsb == 0x0000000000100000 */
4888 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
4889 c = ~c; /* c == 0x00fff000000fffff */
4890 c &= -lsb; /* c == 0x00fff00000000000 */
4891 lsb = c & -c; /* lsb == 0x0000100000000000 */
4892 c = ~c; /* c == 0xff000fffffffffff */
4893 c &= -lsb; /* c == 0xff00000000000000 */
4895 while ((lsb >>= 1) != 0)
4896 shift++; /* shift == 44 on exit from loop */
4897 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
4898 m1 = ~m1; /* m1 == 0x000000ffffffffff */
4899 m2 = ~c; /* m2 == 0x00ffffffffffffff */
4903 /* Assume c initially something like 0xff000f0000000000. The idea
4904 is to rotate the word so that the ^^^ middle group of zeros
4905 is at the LS end and can be cleared with an rldicr mask. We then
4906 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
4908 lsb = c & -c; /* lsb == 0x0000010000000000 */
4909 m2 = -lsb; /* m2 == 0xffffff0000000000 */
4910 c = ~c; /* c == 0x00fff0ffffffffff */
4911 c &= -lsb; /* c == 0x00fff00000000000 */
4912 lsb = c & -c; /* lsb == 0x0000100000000000 */
4913 c = ~c; /* c == 0xff000fffffffffff */
4914 c &= -lsb; /* c == 0xff00000000000000 */
4916 while ((lsb >>= 1) != 0)
4917 shift++; /* shift == 44 on exit from loop */
4918 m1 = ~c; /* m1 == 0x00ffffffffffffff */
4919 m1 >>= shift; /* m1 == 0x0000000000000fff */
4920 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
4923 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
4924 masks will be all 1's. We are guaranteed more than one transition. */
4925 out[0] = GEN_INT (64 - shift);
4926 out[1] = GEN_INT (m1);
4927 out[2] = GEN_INT (shift);
4928 out[3] = GEN_INT (m2);
4936 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
4939 invalid_e500_subreg (rtx op, enum machine_mode mode)
4941 if (TARGET_E500_DOUBLE)
4943 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
4944 subreg:TI and reg:TF. Decimal float modes are like integer
4945 modes (only low part of each register used) for this
4947 if (GET_CODE (op) == SUBREG
4948 && (mode == SImode || mode == DImode || mode == TImode
4949 || mode == DDmode || mode == TDmode)
4950 && REG_P (SUBREG_REG (op))
4951 && (GET_MODE (SUBREG_REG (op)) == DFmode
4952 || GET_MODE (SUBREG_REG (op)) == TFmode))
4955 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
4957 if (GET_CODE (op) == SUBREG
4958 && (mode == DFmode || mode == TFmode)
4959 && REG_P (SUBREG_REG (op))
4960 && (GET_MODE (SUBREG_REG (op)) == DImode
4961 || GET_MODE (SUBREG_REG (op)) == TImode
4962 || GET_MODE (SUBREG_REG (op)) == DDmode
4963 || GET_MODE (SUBREG_REG (op)) == TDmode))
4968 && GET_CODE (op) == SUBREG
4970 && REG_P (SUBREG_REG (op))
4971 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
4977 /* AIX increases natural record alignment to doubleword if the first
4978 field is an FP double while the FP fields remain word aligned. */
4981 rs6000_special_round_type_align (tree type, unsigned int computed,
4982 unsigned int specified)
4984 unsigned int align = MAX (computed, specified);
4985 tree field = TYPE_FIELDS (type);
4987 /* Skip all non field decls */
4988 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
4989 field = DECL_CHAIN (field);
4991 if (field != NULL && field != type)
4993 type = TREE_TYPE (field);
4994 while (TREE_CODE (type) == ARRAY_TYPE)
4995 type = TREE_TYPE (type);
4997 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
4998 align = MAX (align, 64);
5004 /* Darwin increases record alignment to the natural alignment of
5008 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
5009 unsigned int specified)
5011 unsigned int align = MAX (computed, specified);
5013 if (TYPE_PACKED (type))
5016 /* Find the first field, looking down into aggregates. */
5018 tree field = TYPE_FIELDS (type);
5019 /* Skip all non field decls */
5020 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
5021 field = DECL_CHAIN (field);
5024 /* A packed field does not contribute any extra alignment. */
5025 if (DECL_PACKED (field))
5027 type = TREE_TYPE (field);
5028 while (TREE_CODE (type) == ARRAY_TYPE)
5029 type = TREE_TYPE (type);
5030 } while (AGGREGATE_TYPE_P (type));
5032 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
5033 align = MAX (align, TYPE_ALIGN (type));
5038 /* Return 1 for an operand in small memory on V.4/eabi. */
5041 small_data_operand (rtx op ATTRIBUTE_UNUSED,
5042 enum machine_mode mode ATTRIBUTE_UNUSED)
5047 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
5050 if (DEFAULT_ABI != ABI_V4)
5053 /* Vector and float memory instructions have a limited offset on the
5054 SPE, so using a vector or float variable directly as an operand is
5057 && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
5060 if (GET_CODE (op) == SYMBOL_REF)
5063 else if (GET_CODE (op) != CONST
5064 || GET_CODE (XEXP (op, 0)) != PLUS
5065 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
5066 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
5071 rtx sum = XEXP (op, 0);
5072 HOST_WIDE_INT summand;
5074 /* We have to be careful here, because it is the referenced address
5075 that must be 32k from _SDA_BASE_, not just the symbol. */
5076 summand = INTVAL (XEXP (sum, 1));
5077 if (summand < 0 || summand > g_switch_value)
5080 sym_ref = XEXP (sum, 0);
5083 return SYMBOL_REF_SMALL_P (sym_ref);
5089 /* Return true if either operand is a general purpose register. */
5092 gpr_or_gpr_p (rtx op0, rtx op1)
5094 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
5095 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
5099 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
5102 reg_offset_addressing_ok_p (enum machine_mode mode)
5112 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. */
5113 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
5121 /* Paired vector modes. Only reg+reg addressing is valid. */
5122 if (TARGET_PAIRED_FLOAT)
5134 virtual_stack_registers_memory_p (rtx op)
5138 if (GET_CODE (op) == REG)
5139 regnum = REGNO (op);
5141 else if (GET_CODE (op) == PLUS
5142 && GET_CODE (XEXP (op, 0)) == REG
5143 && GET_CODE (XEXP (op, 1)) == CONST_INT)
5144 regnum = REGNO (XEXP (op, 0));
5149 return (regnum >= FIRST_VIRTUAL_REGISTER
5150 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
5153 /* Return true if memory accesses to OP are known to never straddle
5157 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
5158 enum machine_mode mode)
5161 unsigned HOST_WIDE_INT dsize, dalign;
5163 if (GET_CODE (op) != SYMBOL_REF)
5166 decl = SYMBOL_REF_DECL (op);
5169 if (GET_MODE_SIZE (mode) == 0)
5172 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
5173 replacing memory addresses with an anchor plus offset. We
5174 could find the decl by rummaging around in the block->objects
5175 VEC for the given offset but that seems like too much work. */
5177 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
5178 && SYMBOL_REF_ANCHOR_P (op)
5179 && SYMBOL_REF_BLOCK (op) != NULL)
5181 struct object_block *block = SYMBOL_REF_BLOCK (op);
5182 HOST_WIDE_INT lsb, mask;
5184 /* Given the alignment of the block.. */
5185 dalign = block->alignment;
5186 mask = dalign / BITS_PER_UNIT - 1;
5188 /* ..and the combined offset of the anchor and any offset
5189 to this block object.. */
5190 offset += SYMBOL_REF_BLOCK_OFFSET (op);
5191 lsb = offset & -offset;
5193 /* ..find how many bits of the alignment we know for the
5198 return dalign >= GET_MODE_SIZE (mode);
5203 if (TREE_CODE (decl) == FUNCTION_DECL)
5206 if (!DECL_SIZE_UNIT (decl))
5209 if (!host_integerp (DECL_SIZE_UNIT (decl), 1))
5212 dsize = tree_low_cst (DECL_SIZE_UNIT (decl), 1);
5216 dalign = DECL_ALIGN_UNIT (decl);
5217 return dalign >= dsize;
5220 type = TREE_TYPE (decl);
5222 if (TREE_CODE (decl) == STRING_CST)
5223 dsize = TREE_STRING_LENGTH (decl);
5224 else if (TYPE_SIZE_UNIT (type)
5225 && host_integerp (TYPE_SIZE_UNIT (type), 1))
5226 dsize = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
5232 dalign = TYPE_ALIGN (type);
5233 if (CONSTANT_CLASS_P (decl))
5234 dalign = CONSTANT_ALIGNMENT (decl, dalign);
5236 dalign = DATA_ALIGNMENT (decl, dalign);
5237 dalign /= BITS_PER_UNIT;
5238 return dalign >= dsize;
5242 constant_pool_expr_p (rtx op)
5246 split_const (op, &base, &offset);
5247 return (GET_CODE (base) == SYMBOL_REF
5248 && CONSTANT_POOL_ADDRESS_P (base)
5249 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
5252 static rtx tocrel_base, tocrel_offset;
5255 toc_relative_expr_p (rtx op)
5257 if (GET_CODE (op) != CONST)
5260 split_const (op, &tocrel_base, &tocrel_offset);
5261 return (GET_CODE (tocrel_base) == UNSPEC
5262 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
5265 /* Return true if X is a constant pool address, and also for cmodel=medium
5266 if X is a toc-relative address known to be offsettable within MODE. */
5269 legitimate_constant_pool_address_p (const_rtx x, enum machine_mode mode,
5273 && (GET_CODE (x) == PLUS || GET_CODE (x) == LO_SUM)
5274 && GET_CODE (XEXP (x, 0)) == REG
5275 && (REGNO (XEXP (x, 0)) == TOC_REGISTER
5276 || ((TARGET_MINIMAL_TOC
5277 || TARGET_CMODEL != CMODEL_SMALL)
5278 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict)))
5279 && toc_relative_expr_p (XEXP (x, 1))
5280 && (TARGET_CMODEL != CMODEL_MEDIUM
5281 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
5283 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
5284 INTVAL (tocrel_offset), mode)));
5288 legitimate_small_data_p (enum machine_mode mode, rtx x)
5290 return (DEFAULT_ABI == ABI_V4
5291 && !flag_pic && !TARGET_TOC
5292 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
5293 && small_data_operand (x, mode));
5296 /* SPE offset addressing is limited to 5-bits worth of double words. */
5297 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
5300 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
5302 unsigned HOST_WIDE_INT offset, extra;
5304 if (GET_CODE (x) != PLUS)
5306 if (GET_CODE (XEXP (x, 0)) != REG)
5308 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5310 if (!reg_offset_addressing_ok_p (mode))
5311 return virtual_stack_registers_memory_p (x);
5312 if (legitimate_constant_pool_address_p (x, mode, strict))
5314 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5317 offset = INTVAL (XEXP (x, 1));
5325 /* SPE vector modes. */
5326 return SPE_CONST_OFFSET_OK (offset);
5329 if (TARGET_E500_DOUBLE)
5330 return SPE_CONST_OFFSET_OK (offset);
5332 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
5334 if (VECTOR_MEM_VSX_P (DFmode))
5339 /* On e500v2, we may have:
5341 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
5343 Which gets addressed with evldd instructions. */
5344 if (TARGET_E500_DOUBLE)
5345 return SPE_CONST_OFFSET_OK (offset);
5347 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
5349 else if (offset & 3)
5354 if (TARGET_E500_DOUBLE)
5355 return (SPE_CONST_OFFSET_OK (offset)
5356 && SPE_CONST_OFFSET_OK (offset + 8));
5360 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
5362 else if (offset & 3)
5373 return offset < 0x10000 - extra;
5377 legitimate_indexed_address_p (rtx x, int strict)
5381 if (GET_CODE (x) != PLUS)
5387 /* Recognize the rtl generated by reload which we know will later be
5388 replaced with proper base and index regs. */
5390 && reload_in_progress
5391 && (REG_P (op0) || GET_CODE (op0) == PLUS)
5395 return (REG_P (op0) && REG_P (op1)
5396 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
5397 && INT_REG_OK_FOR_INDEX_P (op1, strict))
5398 || (INT_REG_OK_FOR_BASE_P (op1, strict)
5399 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
5403 avoiding_indexed_address_p (enum machine_mode mode)
5405 /* Avoid indexed addressing for modes that have non-indexed
5406 load/store instruction forms. */
5407 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
5411 legitimate_indirect_address_p (rtx x, int strict)
5413 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
5417 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
5419 if (!TARGET_MACHO || !flag_pic
5420 || mode != SImode || GET_CODE (x) != MEM)
5424 if (GET_CODE (x) != LO_SUM)
5426 if (GET_CODE (XEXP (x, 0)) != REG)
5428 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
5432 return CONSTANT_P (x);
5436 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
5438 if (GET_CODE (x) != LO_SUM)
5440 if (GET_CODE (XEXP (x, 0)) != REG)
5442 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
5444 /* Restrict addressing for DI because of our SUBREG hackery. */
5445 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5446 || mode == DDmode || mode == TDmode
5451 if (TARGET_ELF || TARGET_MACHO)
5453 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
5457 if (GET_MODE_NUNITS (mode) != 1)
5459 if (GET_MODE_BITSIZE (mode) > 64
5460 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
5461 && !(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5462 && (mode == DFmode || mode == DDmode))))
5465 return CONSTANT_P (x);
5472 /* Try machine-dependent ways of modifying an illegitimate address
5473 to be legitimate. If we find one, return the new, valid address.
5474 This is used from only one place: `memory_address' in explow.c.
5476 OLDX is the address as it was before break_out_memory_refs was
5477 called. In some cases it is useful to look at this to decide what
5480 It is always safe for this function to do nothing. It exists to
5481 recognize opportunities to optimize the output.
5483 On RS/6000, first check for the sum of a register with a constant
5484 integer that is out of range. If so, generate code to add the
5485 constant with the low-order 16 bits masked to the register and force
5486 this result into another register (this can be done with `cau').
5487 Then generate an address of REG+(CONST&0xffff), allowing for the
5488 possibility of bit 16 being a one.
5490 Then check for the sum of a register and something not constant, try to
5491 load the other things into a register and return the sum. */
5494 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
5495 enum machine_mode mode)
5497 unsigned int extra = 0;
5499 if (!reg_offset_addressing_ok_p (mode))
5501 if (virtual_stack_registers_memory_p (x))
5504 /* In theory we should not be seeing addresses of the form reg+0,
5505 but just in case it is generated, optimize it away. */
5506 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
5507 return force_reg (Pmode, XEXP (x, 0));
5509 /* Make sure both operands are registers. */
5510 else if (GET_CODE (x) == PLUS)
5511 return gen_rtx_PLUS (Pmode,
5512 force_reg (Pmode, XEXP (x, 0)),
5513 force_reg (Pmode, XEXP (x, 1)));
5515 return force_reg (Pmode, x);
5517 if (GET_CODE (x) == SYMBOL_REF)
5519 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
5521 return rs6000_legitimize_tls_address (x, model);
5531 if (!TARGET_POWERPC64)
5539 extra = TARGET_POWERPC64 ? 8 : 12;
5545 if (GET_CODE (x) == PLUS
5546 && GET_CODE (XEXP (x, 0)) == REG
5547 && GET_CODE (XEXP (x, 1)) == CONST_INT
5548 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
5550 && !((TARGET_POWERPC64
5551 && (mode == DImode || mode == TImode)
5552 && (INTVAL (XEXP (x, 1)) & 3) != 0)
5553 || SPE_VECTOR_MODE (mode)
5554 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5555 || mode == DImode || mode == DDmode
5556 || mode == TDmode))))
5558 HOST_WIDE_INT high_int, low_int;
5560 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
5561 if (low_int >= 0x8000 - extra)
5563 high_int = INTVAL (XEXP (x, 1)) - low_int;
5564 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
5565 GEN_INT (high_int)), 0);
5566 return plus_constant (sum, low_int);
5568 else if (GET_CODE (x) == PLUS
5569 && GET_CODE (XEXP (x, 0)) == REG
5570 && GET_CODE (XEXP (x, 1)) != CONST_INT
5571 && GET_MODE_NUNITS (mode) == 1
5572 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5574 || ((mode != DImode && mode != DFmode && mode != DDmode)
5575 || (TARGET_E500_DOUBLE && mode != DDmode)))
5576 && (TARGET_POWERPC64 || mode != DImode)
5577 && !avoiding_indexed_address_p (mode)
5582 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
5583 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
5585 else if (SPE_VECTOR_MODE (mode)
5586 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
5587 || mode == DDmode || mode == TDmode
5588 || mode == DImode)))
5592 /* We accept [reg + reg] and [reg + OFFSET]. */
5594 if (GET_CODE (x) == PLUS)
5596 rtx op1 = XEXP (x, 0);
5597 rtx op2 = XEXP (x, 1);
5600 op1 = force_reg (Pmode, op1);
5602 if (GET_CODE (op2) != REG
5603 && (GET_CODE (op2) != CONST_INT
5604 || !SPE_CONST_OFFSET_OK (INTVAL (op2))
5605 || (GET_MODE_SIZE (mode) > 8
5606 && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
5607 op2 = force_reg (Pmode, op2);
5609 /* We can't always do [reg + reg] for these, because [reg +
5610 reg + offset] is not a legitimate addressing mode. */
5611 y = gen_rtx_PLUS (Pmode, op1, op2);
5613 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
5614 return force_reg (Pmode, y);
5619 return force_reg (Pmode, x);
5625 && GET_CODE (x) != CONST_INT
5626 && GET_CODE (x) != CONST_DOUBLE
5628 && GET_MODE_NUNITS (mode) == 1
5629 && (GET_MODE_BITSIZE (mode) <= 32
5630 || ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5631 && (mode == DFmode || mode == DDmode))))
5633 rtx reg = gen_reg_rtx (Pmode);
5634 emit_insn (gen_elf_high (reg, x));
5635 return gen_rtx_LO_SUM (Pmode, reg, x);
5637 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
5640 && ! MACHO_DYNAMIC_NO_PIC_P
5642 && GET_CODE (x) != CONST_INT
5643 && GET_CODE (x) != CONST_DOUBLE
5645 && GET_MODE_NUNITS (mode) == 1
5646 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
5647 || (mode != DFmode && mode != DDmode))
5651 rtx reg = gen_reg_rtx (Pmode);
5652 emit_insn (gen_macho_high (reg, x));
5653 return gen_rtx_LO_SUM (Pmode, reg, x);
5656 && GET_CODE (x) == SYMBOL_REF
5657 && constant_pool_expr_p (x)
5658 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
5660 rtx reg = TARGET_CMODEL != CMODEL_SMALL ? gen_reg_rtx (Pmode) : NULL_RTX;
5661 return create_TOC_reference (x, reg);
5667 /* Debug version of rs6000_legitimize_address. */
5669 rs6000_debug_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
5675 ret = rs6000_legitimize_address (x, oldx, mode);
5676 insns = get_insns ();
5682 "\nrs6000_legitimize_address: mode %s, old code %s, "
5683 "new code %s, modified\n",
5684 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
5685 GET_RTX_NAME (GET_CODE (ret)));
5687 fprintf (stderr, "Original address:\n");
5690 fprintf (stderr, "oldx:\n");
5693 fprintf (stderr, "New address:\n");
5698 fprintf (stderr, "Insns added:\n");
5699 debug_rtx_list (insns, 20);
5705 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
5706 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
5717 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5718 We need to emit DTP-relative relocations. */
5721 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
5726 fputs ("\t.long\t", file);
5729 fputs (DOUBLE_INT_ASM_OP, file);
5734 output_addr_const (file, x);
5735 fputs ("@dtprel+0x8000", file);
5738 /* In the name of slightly smaller debug output, and to cater to
5739 general assembler lossage, recognize various UNSPEC sequences
5740 and turn them back into a direct symbol reference. */
5743 rs6000_delegitimize_address (rtx orig_x)
5747 orig_x = delegitimize_mem_from_attrs (orig_x);
5752 if (GET_CODE (x) == (TARGET_CMODEL != CMODEL_SMALL ? LO_SUM : PLUS)
5753 && GET_CODE (XEXP (x, 1)) == CONST)
5755 rtx offset = NULL_RTX;
5757 y = XEXP (XEXP (x, 1), 0);
5758 if (GET_CODE (y) == PLUS
5759 && GET_MODE (y) == Pmode
5760 && CONST_INT_P (XEXP (y, 1)))
5762 offset = XEXP (y, 1);
5765 if (GET_CODE (y) == UNSPEC
5766 && XINT (y, 1) == UNSPEC_TOCREL
5767 && ((GET_CODE (XEXP (x, 0)) == REG
5768 && (REGNO (XEXP (x, 0)) == TOC_REGISTER
5769 || TARGET_MINIMAL_TOC
5770 || TARGET_CMODEL != CMODEL_SMALL))
5771 || (TARGET_CMODEL != CMODEL_SMALL
5772 && GET_CODE (XEXP (x, 0)) == CONST
5773 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
5774 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == REG
5775 && REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0)) == TOC_REGISTER
5776 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == HIGH
5777 && rtx_equal_p (XEXP (x, 1),
5778 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 1), 0)))))
5780 y = XVECEXP (y, 0, 0);
5781 if (offset != NULL_RTX)
5782 y = gen_rtx_PLUS (Pmode, y, offset);
5783 if (!MEM_P (orig_x))
5786 return replace_equiv_address_nv (orig_x, y);
5791 && GET_CODE (orig_x) == LO_SUM
5792 && GET_CODE (XEXP (orig_x, 1)) == CONST)
5794 y = XEXP (XEXP (orig_x, 1), 0);
5795 if (GET_CODE (y) == UNSPEC
5796 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
5797 return XVECEXP (y, 0, 0);
5803 /* Construct the SYMBOL_REF for the tls_get_addr function. */
5805 static GTY(()) rtx rs6000_tls_symbol;
5807 rs6000_tls_get_addr (void)
5809 if (!rs6000_tls_symbol)
5810 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
5812 return rs6000_tls_symbol;
5815 /* Construct the SYMBOL_REF for TLS GOT references. */
5817 static GTY(()) rtx rs6000_got_symbol;
5819 rs6000_got_sym (void)
5821 if (!rs6000_got_symbol)
5823 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
5824 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
5825 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
5828 return rs6000_got_symbol;
5831 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
5832 this (thread-local) address. */
5835 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
5839 dest = gen_reg_rtx (Pmode);
5840 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
5846 tlsreg = gen_rtx_REG (Pmode, 13);
5847 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
5851 tlsreg = gen_rtx_REG (Pmode, 2);
5852 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
5856 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
5860 tmp = gen_reg_rtx (Pmode);
5863 tlsreg = gen_rtx_REG (Pmode, 13);
5864 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
5868 tlsreg = gen_rtx_REG (Pmode, 2);
5869 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
5873 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
5875 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
5880 rtx r3, got, tga, tmp1, tmp2, call_insn;
5882 /* We currently use relocations like @got@tlsgd for tls, which
5883 means the linker will handle allocation of tls entries, placing
5884 them in the .got section. So use a pointer to the .got section,
5885 not one to secondary TOC sections used by 64-bit -mminimal-toc,
5886 or to secondary GOT sections used by 32-bit -fPIC. */
5888 got = gen_rtx_REG (Pmode, 2);
5892 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
5895 rtx gsym = rs6000_got_sym ();
5896 got = gen_reg_rtx (Pmode);
5898 rs6000_emit_move (got, gsym, Pmode);
5903 tmp1 = gen_reg_rtx (Pmode);
5904 tmp2 = gen_reg_rtx (Pmode);
5905 mem = gen_const_mem (Pmode, tmp1);
5906 lab = gen_label_rtx ();
5907 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
5908 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
5909 if (TARGET_LINK_STACK)
5910 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
5911 emit_move_insn (tmp2, mem);
5912 last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
5913 set_unique_reg_note (last, REG_EQUAL, gsym);
5918 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
5920 tga = rs6000_tls_get_addr ();
5921 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
5922 1, const0_rtx, Pmode);
5924 r3 = gen_rtx_REG (Pmode, 3);
5925 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5926 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
5927 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
5928 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
5929 else if (DEFAULT_ABI == ABI_V4)
5930 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
5933 call_insn = last_call_insn ();
5934 PATTERN (call_insn) = insn;
5935 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
5936 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5937 pic_offset_table_rtx);
5939 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
5941 tga = rs6000_tls_get_addr ();
5942 tmp1 = gen_reg_rtx (Pmode);
5943 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
5944 1, const0_rtx, Pmode);
5946 r3 = gen_rtx_REG (Pmode, 3);
5947 if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5948 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
5949 else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
5950 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
5951 else if (DEFAULT_ABI == ABI_V4)
5952 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
5955 call_insn = last_call_insn ();
5956 PATTERN (call_insn) = insn;
5957 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
5958 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
5959 pic_offset_table_rtx);
5961 if (rs6000_tls_size == 16)
5964 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
5966 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
5968 else if (rs6000_tls_size == 32)
5970 tmp2 = gen_reg_rtx (Pmode);
5972 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
5974 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
5977 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
5979 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
5983 tmp2 = gen_reg_rtx (Pmode);
5985 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
5987 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
5989 insn = gen_rtx_SET (Pmode, dest,
5990 gen_rtx_PLUS (Pmode, tmp2, tmp1));
5996 /* IE, or 64-bit offset LE. */
5997 tmp2 = gen_reg_rtx (Pmode);
5999 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
6001 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
6004 insn = gen_tls_tls_64 (dest, tmp2, addr);
6006 insn = gen_tls_tls_32 (dest, tmp2, addr);
6014 /* Return 1 if X contains a thread-local symbol. */
6017 rs6000_tls_referenced_p (rtx x)
6019 if (! TARGET_HAVE_TLS)
6022 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
6025 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
6028 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
6030 if (GET_CODE (x) == CONST
6031 && GET_CODE (XEXP (x, 0)) == PLUS
6032 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH)
6035 return rs6000_tls_referenced_p (x);
6038 /* Return 1 if *X is a thread-local symbol. This is the same as
6039 rs6000_tls_symbol_ref except for the type of the unused argument. */
6042 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
6044 return RS6000_SYMBOL_REF_TLS_P (*x);
6047 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
6048 replace the input X, or the original X if no replacement is called for.
6049 The output parameter *WIN is 1 if the calling macro should goto WIN,
6052 For RS/6000, we wish to handle large displacements off a base
6053 register by splitting the addend across an addiu/addis and the mem insn.
6054 This cuts number of extra insns needed from 3 to 1.
6056 On Darwin, we use this to generate code for floating point constants.
6057 A movsf_low is generated so we wind up with 2 instructions rather than 3.
6058 The Darwin code is inside #if TARGET_MACHO because only then are the
6059 machopic_* functions defined. */
6061 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
6062 int opnum, int type,
6063 int ind_levels ATTRIBUTE_UNUSED, int *win)
6065 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6067 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
6068 DFmode/DImode MEM. */
6071 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
6072 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)))
6073 reg_offset_p = false;
6075 /* We must recognize output that we have already generated ourselves. */
6076 if (GET_CODE (x) == PLUS
6077 && GET_CODE (XEXP (x, 0)) == PLUS
6078 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6079 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6080 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6082 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6083 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6084 opnum, (enum reload_type)type);
6089 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
6090 if (GET_CODE (x) == LO_SUM
6091 && GET_CODE (XEXP (x, 0)) == HIGH)
6093 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6094 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6095 opnum, (enum reload_type)type);
6101 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
6102 && GET_CODE (x) == LO_SUM
6103 && GET_CODE (XEXP (x, 0)) == PLUS
6104 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
6105 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
6106 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
6107 && machopic_operand_p (XEXP (x, 1)))
6109 /* Result of previous invocation of this function on Darwin
6110 floating point constant. */
6111 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6112 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6113 opnum, (enum reload_type)type);
6119 if (TARGET_CMODEL != CMODEL_SMALL
6120 && GET_CODE (x) == LO_SUM
6121 && GET_CODE (XEXP (x, 0)) == PLUS
6122 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6123 && REGNO (XEXP (XEXP (x, 0), 0)) == TOC_REGISTER
6124 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST
6125 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == HIGH
6126 && GET_CODE (XEXP (x, 1)) == CONST
6127 && GET_CODE (XEXP (XEXP (x, 1), 0)) == UNSPEC
6128 && XINT (XEXP (XEXP (x, 1), 0), 1) == UNSPEC_TOCREL
6129 && rtx_equal_p (XEXP (XEXP (XEXP (XEXP (x, 0), 1), 0), 0), XEXP (x, 1)))
6131 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6132 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6133 opnum, (enum reload_type) type);
6138 /* Force ld/std non-word aligned offset into base register by wrapping
6140 if (GET_CODE (x) == PLUS
6141 && GET_CODE (XEXP (x, 0)) == REG
6142 && REGNO (XEXP (x, 0)) < 32
6143 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
6144 && GET_CODE (XEXP (x, 1)) == CONST_INT
6146 && (INTVAL (XEXP (x, 1)) & 3) != 0
6147 && VECTOR_MEM_NONE_P (mode)
6148 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
6149 && TARGET_POWERPC64)
6151 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
6152 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6153 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6154 opnum, (enum reload_type) type);
6159 if (GET_CODE (x) == PLUS
6160 && GET_CODE (XEXP (x, 0)) == REG
6161 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
6162 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
6163 && GET_CODE (XEXP (x, 1)) == CONST_INT
6165 && !SPE_VECTOR_MODE (mode)
6166 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
6167 || mode == DDmode || mode == TDmode
6169 && VECTOR_MEM_NONE_P (mode))
6171 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
6172 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
6174 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
6176 /* Check for 32-bit overflow. */
6177 if (high + low != val)
6183 /* Reload the high part into a base reg; leave the low part
6184 in the mem directly. */
6186 x = gen_rtx_PLUS (GET_MODE (x),
6187 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
6191 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6192 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
6193 opnum, (enum reload_type)type);
6198 if (GET_CODE (x) == SYMBOL_REF
6200 && VECTOR_MEM_NONE_P (mode)
6201 && !SPE_VECTOR_MODE (mode)
6203 && DEFAULT_ABI == ABI_DARWIN
6204 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
6205 && machopic_symbol_defined_p (x)
6207 && DEFAULT_ABI == ABI_V4
6210 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
6211 The same goes for DImode without 64-bit gprs and DFmode and DDmode
6215 && (mode != DImode || TARGET_POWERPC64)
6216 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
6217 || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
6222 rtx offset = machopic_gen_offset (x);
6223 x = gen_rtx_LO_SUM (GET_MODE (x),
6224 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
6225 gen_rtx_HIGH (Pmode, offset)), offset);
6229 x = gen_rtx_LO_SUM (GET_MODE (x),
6230 gen_rtx_HIGH (Pmode, x), x);
6232 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6233 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6234 opnum, (enum reload_type)type);
6239 /* Reload an offset address wrapped by an AND that represents the
6240 masking of the lower bits. Strip the outer AND and let reload
6241 convert the offset address into an indirect address. For VSX,
6242 force reload to create the address with an AND in a separate
6243 register, because we can't guarantee an altivec register will
6245 if (VECTOR_MEM_ALTIVEC_P (mode)
6246 && GET_CODE (x) == AND
6247 && GET_CODE (XEXP (x, 0)) == PLUS
6248 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
6249 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6250 && GET_CODE (XEXP (x, 1)) == CONST_INT
6251 && INTVAL (XEXP (x, 1)) == -16)
6260 && GET_CODE (x) == SYMBOL_REF
6261 && constant_pool_expr_p (x)
6262 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
6264 x = create_TOC_reference (x, NULL_RTX);
6265 if (TARGET_CMODEL != CMODEL_SMALL)
6266 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
6267 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
6268 opnum, (enum reload_type) type);
6276 /* Debug version of rs6000_legitimize_reload_address. */
6278 rs6000_debug_legitimize_reload_address (rtx x, enum machine_mode mode,
6279 int opnum, int type,
6280 int ind_levels, int *win)
6282 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
6285 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
6286 "type = %d, ind_levels = %d, win = %d, original addr:\n",
6287 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
6291 fprintf (stderr, "Same address returned\n");
6293 fprintf (stderr, "NULL returned\n");
6296 fprintf (stderr, "New address:\n");
6303 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
6304 that is a valid memory address for an instruction.
6305 The MODE argument is the machine mode for the MEM expression
6306 that wants to use this address.
6308 On the RS/6000, there are four valid address: a SYMBOL_REF that
6309 refers to a constant pool entry of an address (or the sum of it
6310 plus a constant), a short (16-bit signed) constant plus a register,
6311 the sum of two registers, or a register indirect, possibly with an
6312 auto-increment. For DFmode, DDmode and DImode with a constant plus
6313 register, we must ensure that both words are addressable or PowerPC64
6314 with offset word aligned.
6316 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
6317 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
6318 because adjacent memory cells are accessed by adding word-sized offsets
6319 during assembly output. */
6321 rs6000_legitimate_address_p (enum machine_mode mode, rtx x, bool reg_ok_strict)
6323 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
6325 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
6326 if (VECTOR_MEM_ALTIVEC_P (mode)
6327 && GET_CODE (x) == AND
6328 && GET_CODE (XEXP (x, 1)) == CONST_INT
6329 && INTVAL (XEXP (x, 1)) == -16)
6332 if (RS6000_SYMBOL_REF_TLS_P (x))
6334 if (legitimate_indirect_address_p (x, reg_ok_strict))
6336 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
6337 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6338 && !SPE_VECTOR_MODE (mode)
6341 /* Restrict addressing for DI because of our SUBREG hackery. */
6342 && !(TARGET_E500_DOUBLE
6343 && (mode == DFmode || mode == DDmode || mode == DImode))
6345 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
6347 if (virtual_stack_registers_memory_p (x))
6349 if (reg_offset_p && legitimate_small_data_p (mode, x))
6352 && legitimate_constant_pool_address_p (x, mode, reg_ok_strict))
6354 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
6357 && GET_CODE (x) == PLUS
6358 && GET_CODE (XEXP (x, 0)) == REG
6359 && (XEXP (x, 0) == virtual_stack_vars_rtx
6360 || XEXP (x, 0) == arg_pointer_rtx)
6361 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6363 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
6368 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6370 || (mode != DFmode && mode != DDmode)
6371 || (TARGET_E500_DOUBLE && mode != DDmode))
6372 && (TARGET_POWERPC64 || mode != DImode)
6373 && !avoiding_indexed_address_p (mode)
6374 && legitimate_indexed_address_p (x, reg_ok_strict))
6376 if (GET_CODE (x) == PRE_MODIFY
6380 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6382 || ((mode != DFmode && mode != DDmode) || TARGET_E500_DOUBLE))
6383 && (TARGET_POWERPC64 || mode != DImode)
6384 && !VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
6385 && !SPE_VECTOR_MODE (mode)
6386 /* Restrict addressing for DI because of our SUBREG hackery. */
6387 && !(TARGET_E500_DOUBLE
6388 && (mode == DFmode || mode == DDmode || mode == DImode))
6390 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
6391 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
6392 || (!avoiding_indexed_address_p (mode)
6393 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
6394 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6396 if (reg_offset_p && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
6401 /* Debug version of rs6000_legitimate_address_p. */
6403 rs6000_debug_legitimate_address_p (enum machine_mode mode, rtx x,
6406 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
6408 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
6409 "strict = %d, code = %s\n",
6410 ret ? "true" : "false",
6411 GET_MODE_NAME (mode),
6413 GET_RTX_NAME (GET_CODE (x)));
6419 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
6422 rs6000_mode_dependent_address_p (const_rtx addr)
6424 return rs6000_mode_dependent_address_ptr (addr);
6427 /* Go to LABEL if ADDR (a legitimate address expression)
6428 has an effect that depends on the machine mode it is used for.
6430 On the RS/6000 this is true of all integral offsets (since AltiVec
6431 and VSX modes don't allow them) or is a pre-increment or decrement.
6433 ??? Except that due to conceptual problems in offsettable_address_p
6434 we can't really report the problems of integral offsets. So leave
6435 this assuming that the adjustable offset must be valid for the
6436 sub-words of a TFmode operand, which is what we had before. */
6439 rs6000_mode_dependent_address (const_rtx addr)
6441 switch (GET_CODE (addr))
6444 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
6445 is considered a legitimate address before reload, so there
6446 are no offset restrictions in that case. Note that this
6447 condition is safe in strict mode because any address involving
6448 virtual_stack_vars_rtx or arg_pointer_rtx would already have
6449 been rejected as illegitimate. */
6450 if (XEXP (addr, 0) != virtual_stack_vars_rtx
6451 && XEXP (addr, 0) != arg_pointer_rtx
6452 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
6454 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
6455 return val + 12 + 0x8000 >= 0x10000;
6460 /* Anything in the constant pool is sufficiently aligned that
6461 all bytes have the same high part address. */
6462 return !legitimate_constant_pool_address_p (addr, QImode, false);
6464 /* Auto-increment cases are now treated generically in recog.c. */
6466 return TARGET_UPDATE;
6468 /* AND is only allowed in Altivec loads. */
6479 /* Debug version of rs6000_mode_dependent_address. */
6481 rs6000_debug_mode_dependent_address (const_rtx addr)
6483 bool ret = rs6000_mode_dependent_address (addr);
6485 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
6486 ret ? "true" : "false");
6492 /* Implement FIND_BASE_TERM. */
6495 rs6000_find_base_term (rtx op)
6499 split_const (op, &base, &offset);
6500 if (GET_CODE (base) == UNSPEC)
6501 switch (XINT (base, 1))
6504 case UNSPEC_MACHOPIC_OFFSET:
6505 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
6506 for aliasing purposes. */
6507 return XVECEXP (base, 0, 0);
6513 /* More elaborate version of recog's offsettable_memref_p predicate
6514 that works around the ??? note of rs6000_mode_dependent_address.
6515 In particular it accepts
6517 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
6519 in 32-bit mode, that the recog predicate rejects. */
6522 rs6000_offsettable_memref_p (rtx op)
6527 /* First mimic offsettable_memref_p. */
6528 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
6531 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
6532 the latter predicate knows nothing about the mode of the memory
6533 reference and, therefore, assumes that it is the largest supported
6534 mode (TFmode). As a consequence, legitimate offsettable memory
6535 references are rejected. rs6000_legitimate_offset_address_p contains
6536 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
6537 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
6540 /* Change register usage conditional on target flags. */
6542 rs6000_conditional_register_usage (void)
6546 if (TARGET_DEBUG_TARGET)
6547 fprintf (stderr, "rs6000_conditional_register_usage called\n");
6549 /* Set MQ register fixed (already call_used) if not POWER
6550 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
6555 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
6557 fixed_regs[13] = call_used_regs[13]
6558 = call_really_used_regs[13] = 1;
6560 /* Conditionally disable FPRs. */
6561 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
6562 for (i = 32; i < 64; i++)
6563 fixed_regs[i] = call_used_regs[i]
6564 = call_really_used_regs[i] = 1;
6566 /* The TOC register is not killed across calls in a way that is
6567 visible to the compiler. */
6568 if (DEFAULT_ABI == ABI_AIX)
6569 call_really_used_regs[2] = 0;
6571 if (DEFAULT_ABI == ABI_V4
6572 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6574 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6576 if (DEFAULT_ABI == ABI_V4
6577 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
6579 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6580 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6581 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6583 if (DEFAULT_ABI == ABI_DARWIN
6584 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
6585 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6586 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6587 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6589 if (TARGET_TOC && TARGET_MINIMAL_TOC)
6590 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
6591 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
6595 global_regs[SPEFSCR_REGNO] = 1;
6596 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
6597 registers in prologues and epilogues. We no longer use r14
6598 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
6599 pool for link-compatibility with older versions of GCC. Once
6600 "old" code has died out, we can return r14 to the allocation
6603 = call_used_regs[14]
6604 = call_really_used_regs[14] = 1;
6607 if (!TARGET_ALTIVEC && !TARGET_VSX)
6609 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
6610 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6611 call_really_used_regs[VRSAVE_REGNO] = 1;
6614 if (TARGET_ALTIVEC || TARGET_VSX)
6615 global_regs[VSCR_REGNO] = 1;
6617 if (TARGET_ALTIVEC_ABI)
6619 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
6620 call_used_regs[i] = call_really_used_regs[i] = 1;
6622 /* AIX reserves VR20:31 in non-extended ABI mode. */
6624 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
6625 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
6629 /* Try to output insns to set TARGET equal to the constant C if it can
6630 be done in less than N insns. Do all computations in MODE.
6631 Returns the place where the output has been placed if it can be
6632 done and the insns have been emitted. If it would take more than N
6633 insns, zero is returned and no insns and emitted. */
6636 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
6637 rtx source, int n ATTRIBUTE_UNUSED)
6639 rtx result, insn, set;
6640 HOST_WIDE_INT c0, c1;
6647 dest = gen_reg_rtx (mode);
6648 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
6652 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
6654 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
6655 GEN_INT (INTVAL (source)
6656 & (~ (HOST_WIDE_INT) 0xffff))));
6657 emit_insn (gen_rtx_SET (VOIDmode, dest,
6658 gen_rtx_IOR (SImode, copy_rtx (result),
6659 GEN_INT (INTVAL (source) & 0xffff))));
6664 switch (GET_CODE (source))
6667 c0 = INTVAL (source);
6672 #if HOST_BITS_PER_WIDE_INT >= 64
6673 c0 = CONST_DOUBLE_LOW (source);
6676 c0 = CONST_DOUBLE_LOW (source);
6677 c1 = CONST_DOUBLE_HIGH (source);
6685 result = rs6000_emit_set_long_const (dest, c0, c1);
6692 insn = get_last_insn ();
6693 set = single_set (insn);
6694 if (! CONSTANT_P (SET_SRC (set)))
6695 set_unique_reg_note (insn, REG_EQUAL, source);
6700 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
6701 fall back to a straight forward decomposition. We do this to avoid
6702 exponential run times encountered when looking for longer sequences
6703 with rs6000_emit_set_const. */
6705 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
6707 if (!TARGET_POWERPC64)
6709 rtx operand1, operand2;
6711 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
6713 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
6715 emit_move_insn (operand1, GEN_INT (c1));
6716 emit_move_insn (operand2, GEN_INT (c2));
6720 HOST_WIDE_INT ud1, ud2, ud3, ud4;
6723 ud2 = (c1 & 0xffff0000) >> 16;
6724 #if HOST_BITS_PER_WIDE_INT >= 64
6728 ud4 = (c2 & 0xffff0000) >> 16;
6730 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
6731 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
6734 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
6736 emit_move_insn (dest, GEN_INT (ud1));
6739 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
6740 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
6743 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6746 emit_move_insn (dest, GEN_INT (ud2 << 16));
6748 emit_move_insn (copy_rtx (dest),
6749 gen_rtx_IOR (DImode, copy_rtx (dest),
6752 else if (ud3 == 0 && ud4 == 0)
6754 gcc_assert (ud2 & 0x8000);
6755 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
6758 emit_move_insn (copy_rtx (dest),
6759 gen_rtx_IOR (DImode, copy_rtx (dest),
6761 emit_move_insn (copy_rtx (dest),
6762 gen_rtx_ZERO_EXTEND (DImode,
6763 gen_lowpart (SImode,
6766 else if ((ud4 == 0xffff && (ud3 & 0x8000))
6767 || (ud4 == 0 && ! (ud3 & 0x8000)))
6770 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
6773 emit_move_insn (dest, GEN_INT (ud3 << 16));
6776 emit_move_insn (copy_rtx (dest),
6777 gen_rtx_IOR (DImode, copy_rtx (dest),
6779 emit_move_insn (copy_rtx (dest),
6780 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6783 emit_move_insn (copy_rtx (dest),
6784 gen_rtx_IOR (DImode, copy_rtx (dest),
6790 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
6793 emit_move_insn (dest, GEN_INT (ud4 << 16));
6796 emit_move_insn (copy_rtx (dest),
6797 gen_rtx_IOR (DImode, copy_rtx (dest),
6800 emit_move_insn (copy_rtx (dest),
6801 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
6804 emit_move_insn (copy_rtx (dest),
6805 gen_rtx_IOR (DImode, copy_rtx (dest),
6806 GEN_INT (ud2 << 16)));
6808 emit_move_insn (copy_rtx (dest),
6809 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
6815 /* Helper for the following. Get rid of [r+r] memory refs
6816 in cases where it won't work (TImode, TFmode, TDmode). */
6819 rs6000_eliminate_indexed_memrefs (rtx operands[2])
6821 if (reload_in_progress)
6824 if (GET_CODE (operands[0]) == MEM
6825 && GET_CODE (XEXP (operands[0], 0)) != REG
6826 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
6827 GET_MODE (operands[0]), false))
6829 = replace_equiv_address (operands[0],
6830 copy_addr_to_reg (XEXP (operands[0], 0)));
6832 if (GET_CODE (operands[1]) == MEM
6833 && GET_CODE (XEXP (operands[1], 0)) != REG
6834 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
6835 GET_MODE (operands[1]), false))
6837 = replace_equiv_address (operands[1],
6838 copy_addr_to_reg (XEXP (operands[1], 0)));
6841 /* Emit a move from SOURCE to DEST in mode MODE. */
6843 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
6847 operands[1] = source;
6849 if (TARGET_DEBUG_ADDR)
6852 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
6853 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
6854 GET_MODE_NAME (mode),
6857 can_create_pseudo_p ());
6859 fprintf (stderr, "source:\n");
6863 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
6864 if (GET_CODE (operands[1]) == CONST_DOUBLE
6865 && ! FLOAT_MODE_P (mode)
6866 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6868 /* FIXME. This should never happen. */
6869 /* Since it seems that it does, do the safe thing and convert
6871 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
6873 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
6874 || FLOAT_MODE_P (mode)
6875 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
6876 || CONST_DOUBLE_LOW (operands[1]) < 0)
6877 && (CONST_DOUBLE_HIGH (operands[1]) != -1
6878 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
6880 /* Check if GCC is setting up a block move that will end up using FP
6881 registers as temporaries. We must make sure this is acceptable. */
6882 if (GET_CODE (operands[0]) == MEM
6883 && GET_CODE (operands[1]) == MEM
6885 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
6886 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
6887 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
6888 ? 32 : MEM_ALIGN (operands[0])))
6889 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
6891 : MEM_ALIGN (operands[1]))))
6892 && ! MEM_VOLATILE_P (operands [0])
6893 && ! MEM_VOLATILE_P (operands [1]))
6895 emit_move_insn (adjust_address (operands[0], SImode, 0),
6896 adjust_address (operands[1], SImode, 0));
6897 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
6898 adjust_address (copy_rtx (operands[1]), SImode, 4));
6902 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
6903 && !gpc_reg_operand (operands[1], mode))
6904 operands[1] = force_reg (mode, operands[1]);
6906 if (mode == SFmode && ! TARGET_POWERPC
6907 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6908 && GET_CODE (operands[0]) == MEM)
6912 if (reload_in_progress || reload_completed)
6913 regnum = true_regnum (operands[1]);
6914 else if (GET_CODE (operands[1]) == REG)
6915 regnum = REGNO (operands[1]);
6919 /* If operands[1] is a register, on POWER it may have
6920 double-precision data in it, so truncate it to single
6922 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
6925 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
6926 : gen_reg_rtx (mode));
6927 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
6928 operands[1] = newreg;
6932 /* Recognize the case where operand[1] is a reference to thread-local
6933 data and load its address to a register. */
6934 if (rs6000_tls_referenced_p (operands[1]))
6936 enum tls_model model;
6937 rtx tmp = operands[1];
6940 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
6942 addend = XEXP (XEXP (tmp, 0), 1);
6943 tmp = XEXP (XEXP (tmp, 0), 0);
6946 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
6947 model = SYMBOL_REF_TLS_MODEL (tmp);
6948 gcc_assert (model != 0);
6950 tmp = rs6000_legitimize_tls_address (tmp, model);
6953 tmp = gen_rtx_PLUS (mode, tmp, addend);
6954 tmp = force_operand (tmp, operands[0]);
6959 /* Handle the case where reload calls us with an invalid address. */
6960 if (reload_in_progress && mode == Pmode
6961 && (! general_operand (operands[1], mode)
6962 || ! nonimmediate_operand (operands[0], mode)))
6965 /* 128-bit constant floating-point values on Darwin should really be
6966 loaded as two parts. */
6967 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
6968 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
6970 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
6971 know how to get a DFmode SUBREG of a TFmode. */
6972 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
6973 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
6974 simplify_gen_subreg (imode, operands[1], mode, 0),
6976 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
6977 GET_MODE_SIZE (imode)),
6978 simplify_gen_subreg (imode, operands[1], mode,
6979 GET_MODE_SIZE (imode)),
6984 if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX)
6985 cfun->machine->sdmode_stack_slot =
6986 eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
6988 if (reload_in_progress
6990 && MEM_P (operands[0])
6991 && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
6992 && REG_P (operands[1]))
6994 if (FP_REGNO_P (REGNO (operands[1])))
6996 rtx mem = adjust_address_nv (operands[0], DDmode, 0);
6997 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
6998 emit_insn (gen_movsd_store (mem, operands[1]));
7000 else if (INT_REGNO_P (REGNO (operands[1])))
7002 rtx mem = adjust_address_nv (operands[0], mode, 4);
7003 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7004 emit_insn (gen_movsd_hardfloat (mem, operands[1]));
7010 if (reload_in_progress
7012 && REG_P (operands[0])
7013 && MEM_P (operands[1])
7014 && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
7016 if (FP_REGNO_P (REGNO (operands[0])))
7018 rtx mem = adjust_address_nv (operands[1], DDmode, 0);
7019 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7020 emit_insn (gen_movsd_load (operands[0], mem));
7022 else if (INT_REGNO_P (REGNO (operands[0])))
7024 rtx mem = adjust_address_nv (operands[1], mode, 4);
7025 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
7026 emit_insn (gen_movsd_hardfloat (operands[0], mem));
7033 /* FIXME: In the long term, this switch statement should go away
7034 and be replaced by a sequence of tests based on things like
7040 if (CONSTANT_P (operands[1])
7041 && GET_CODE (operands[1]) != CONST_INT)
7042 operands[1] = force_const_mem (mode, operands[1]);
7047 rs6000_eliminate_indexed_memrefs (operands);
7054 if (CONSTANT_P (operands[1])
7055 && ! easy_fp_constant (operands[1], mode))
7056 operands[1] = force_const_mem (mode, operands[1]);
7069 if (CONSTANT_P (operands[1])
7070 && !easy_vector_constant (operands[1], mode))
7071 operands[1] = force_const_mem (mode, operands[1]);
7076 /* Use default pattern for address of ELF small data */
7079 && DEFAULT_ABI == ABI_V4
7080 && (GET_CODE (operands[1]) == SYMBOL_REF
7081 || GET_CODE (operands[1]) == CONST)
7082 && small_data_operand (operands[1], mode))
7084 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7088 if (DEFAULT_ABI == ABI_V4
7089 && mode == Pmode && mode == SImode
7090 && flag_pic == 1 && got_operand (operands[1], mode))
7092 emit_insn (gen_movsi_got (operands[0], operands[1]));
7096 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
7100 && CONSTANT_P (operands[1])
7101 && GET_CODE (operands[1]) != HIGH
7102 && GET_CODE (operands[1]) != CONST_INT)
7104 rtx target = (!can_create_pseudo_p ()
7106 : gen_reg_rtx (mode));
7108 /* If this is a function address on -mcall-aixdesc,
7109 convert it to the address of the descriptor. */
7110 if (DEFAULT_ABI == ABI_AIX
7111 && GET_CODE (operands[1]) == SYMBOL_REF
7112 && XSTR (operands[1], 0)[0] == '.')
7114 const char *name = XSTR (operands[1], 0);
7116 while (*name == '.')
7118 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
7119 CONSTANT_POOL_ADDRESS_P (new_ref)
7120 = CONSTANT_POOL_ADDRESS_P (operands[1]);
7121 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
7122 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
7123 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
7124 operands[1] = new_ref;
7127 if (DEFAULT_ABI == ABI_DARWIN)
7130 if (MACHO_DYNAMIC_NO_PIC_P)
7132 /* Take care of any required data indirection. */
7133 operands[1] = rs6000_machopic_legitimize_pic_address (
7134 operands[1], mode, operands[0]);
7135 if (operands[0] != operands[1])
7136 emit_insn (gen_rtx_SET (VOIDmode,
7137 operands[0], operands[1]));
7141 emit_insn (gen_macho_high (target, operands[1]));
7142 emit_insn (gen_macho_low (operands[0], target, operands[1]));
7146 emit_insn (gen_elf_high (target, operands[1]));
7147 emit_insn (gen_elf_low (operands[0], target, operands[1]));
7151 /* If this is a SYMBOL_REF that refers to a constant pool entry,
7152 and we have put it in the TOC, we just need to make a TOC-relative
7155 && GET_CODE (operands[1]) == SYMBOL_REF
7156 && constant_pool_expr_p (operands[1])
7157 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
7158 get_pool_mode (operands[1])))
7159 || (TARGET_CMODEL == CMODEL_MEDIUM
7160 && GET_CODE (operands[1]) == SYMBOL_REF
7161 && !CONSTANT_POOL_ADDRESS_P (operands[1])
7162 && SYMBOL_REF_LOCAL_P (operands[1])))
7165 if (TARGET_CMODEL != CMODEL_SMALL)
7167 if (can_create_pseudo_p ())
7168 reg = gen_reg_rtx (Pmode);
7172 operands[1] = create_TOC_reference (operands[1], reg);
7174 else if (mode == Pmode
7175 && CONSTANT_P (operands[1])
7176 && GET_CODE (operands[1]) != HIGH
7177 && !(TARGET_CMODEL != CMODEL_SMALL
7178 && GET_CODE (operands[1]) == CONST
7179 && GET_CODE (XEXP (operands[1], 0)) == PLUS
7180 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == HIGH)
7181 && ((GET_CODE (operands[1]) != CONST_INT
7182 && ! easy_fp_constant (operands[1], mode))
7183 || (GET_CODE (operands[1]) == CONST_INT
7184 && (num_insns_constant (operands[1], mode)
7185 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
7186 || (GET_CODE (operands[0]) == REG
7187 && FP_REGNO_P (REGNO (operands[0]))))
7188 && ! legitimate_constant_pool_address_p (operands[1], mode,
7190 && ! toc_relative_expr_p (operands[1])
7191 && (TARGET_CMODEL == CMODEL_SMALL
7192 || can_create_pseudo_p ()
7193 || (REG_P (operands[0])
7194 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
7198 /* Darwin uses a special PIC legitimizer. */
7199 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
7202 rs6000_machopic_legitimize_pic_address (operands[1], mode,
7204 if (operands[0] != operands[1])
7205 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7210 /* If we are to limit the number of things we put in the TOC and
7211 this is a symbol plus a constant we can add in one insn,
7212 just put the symbol in the TOC and add the constant. Don't do
7213 this if reload is in progress. */
7214 if (GET_CODE (operands[1]) == CONST
7215 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
7216 && GET_CODE (XEXP (operands[1], 0)) == PLUS
7217 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
7218 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
7219 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
7220 && ! side_effects_p (operands[0]))
7223 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
7224 rtx other = XEXP (XEXP (operands[1], 0), 1);
7226 sym = force_reg (mode, sym);
7227 emit_insn (gen_add3_insn (operands[0], sym, other));
7231 operands[1] = force_const_mem (mode, operands[1]);
7234 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7235 && constant_pool_expr_p (XEXP (operands[1], 0))
7236 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
7237 get_pool_constant (XEXP (operands[1], 0)),
7238 get_pool_mode (XEXP (operands[1], 0))))
7242 if (TARGET_CMODEL != CMODEL_SMALL)
7244 if (can_create_pseudo_p ())
7245 reg = gen_reg_rtx (Pmode);
7249 tocref = create_TOC_reference (XEXP (operands[1], 0), reg);
7250 operands[1] = gen_const_mem (mode, tocref);
7251 set_mem_alias_set (operands[1], get_TOC_alias_set ());
7257 rs6000_eliminate_indexed_memrefs (operands);
7261 emit_insn (gen_rtx_PARALLEL (VOIDmode,
7263 gen_rtx_SET (VOIDmode,
7264 operands[0], operands[1]),
7265 gen_rtx_CLOBBER (VOIDmode,
7266 gen_rtx_SCRATCH (SImode)))));
7272 fatal_insn ("bad move", gen_rtx_SET (VOIDmode, dest, source));
7275 /* Above, we may have called force_const_mem which may have returned
7276 an invalid address. If we can, fix this up; otherwise, reload will
7277 have to deal with it. */
7278 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
7279 operands[1] = validize_mem (operands[1]);
7282 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
7285 /* Nonzero if we can use a floating-point register to pass this arg. */
7286 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
7287 (SCALAR_FLOAT_MODE_P (MODE) \
7288 && (CUM)->fregno <= FP_ARG_MAX_REG \
7289 && TARGET_HARD_FLOAT && TARGET_FPRS)
7291 /* Nonzero if we can use an AltiVec register to pass this arg. */
7292 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
7293 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
7294 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
7295 && TARGET_ALTIVEC_ABI \
7298 /* Return a nonzero value to say to return the function value in
7299 memory, just as large structures are always returned. TYPE will be
7300 the data type of the value, and FNTYPE will be the type of the
7301 function doing the returning, or @code{NULL} for libcalls.
7303 The AIX ABI for the RS/6000 specifies that all structures are
7304 returned in memory. The Darwin ABI does the same.
7306 For the Darwin 64 Bit ABI, a function result can be returned in
7307 registers or in memory, depending on the size of the return data
7308 type. If it is returned in registers, the value occupies the same
7309 registers as it would if it were the first and only function
7310 argument. Otherwise, the function places its result in memory at
7311 the location pointed to by GPR3.
7313 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
7314 but a draft put them in memory, and GCC used to implement the draft
7315 instead of the final standard. Therefore, aix_struct_return
7316 controls this instead of DEFAULT_ABI; V.4 targets needing backward
7317 compatibility can change DRAFT_V4_STRUCT_RET to override the
7318 default, and -m switches get the final word. See
7319 rs6000_option_override_internal for more details.
7321 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
7322 long double support is enabled. These values are returned in memory.
7324 int_size_in_bytes returns -1 for variable size objects, which go in
7325 memory always. The cast to unsigned makes -1 > 8. */
7328 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
7330 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
7332 && rs6000_darwin64_abi
7333 && TREE_CODE (type) == RECORD_TYPE
7334 && int_size_in_bytes (type) > 0)
7336 CUMULATIVE_ARGS valcum;
7340 valcum.fregno = FP_ARG_MIN_REG;
7341 valcum.vregno = ALTIVEC_ARG_MIN_REG;
7342 /* Do a trial code generation as if this were going to be passed
7343 as an argument; if any part goes in memory, we return NULL. */
7344 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
7347 /* Otherwise fall through to more conventional ABI rules. */
7350 if (AGGREGATE_TYPE_P (type)
7351 && (aix_struct_return
7352 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
7355 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
7356 modes only exist for GCC vector types if -maltivec. */
7357 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
7358 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
7361 /* Return synthetic vectors in memory. */
7362 if (TREE_CODE (type) == VECTOR_TYPE
7363 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
7365 static bool warned_for_return_big_vectors = false;
7366 if (!warned_for_return_big_vectors)
7368 warning (0, "GCC vector returned by reference: "
7369 "non-standard ABI extension with no compatibility guarantee");
7370 warned_for_return_big_vectors = true;
7375 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
7381 #ifdef HAVE_AS_GNU_ATTRIBUTE
7382 /* Return TRUE if a call to function FNDECL may be one that
7383 potentially affects the function calling ABI of the object file. */
7386 call_ABI_of_interest (tree fndecl)
7388 if (cgraph_state == CGRAPH_STATE_EXPANSION)
7390 struct cgraph_node *c_node;
7392 /* Libcalls are always interesting. */
7393 if (fndecl == NULL_TREE)
7396 /* Any call to an external function is interesting. */
7397 if (DECL_EXTERNAL (fndecl))
7400 /* Interesting functions that we are emitting in this object file. */
7401 c_node = cgraph_get_node (fndecl);
7402 c_node = cgraph_function_or_thunk_node (c_node, NULL);
7403 return !cgraph_only_called_directly_p (c_node);
7409 /* Initialize a variable CUM of type CUMULATIVE_ARGS
7410 for a call to a function whose data type is FNTYPE.
7411 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
7413 For incoming args we set the number of arguments in the prototype large
7414 so we never return a PARALLEL. */
7417 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
7418 rtx libname ATTRIBUTE_UNUSED, int incoming,
7419 int libcall, int n_named_args,
7420 tree fndecl ATTRIBUTE_UNUSED,
7421 enum machine_mode return_mode ATTRIBUTE_UNUSED)
7423 static CUMULATIVE_ARGS zero_cumulative;
7425 *cum = zero_cumulative;
7427 cum->fregno = FP_ARG_MIN_REG;
7428 cum->vregno = ALTIVEC_ARG_MIN_REG;
7429 cum->prototype = (fntype && prototype_p (fntype));
7430 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
7431 ? CALL_LIBCALL : CALL_NORMAL);
7432 cum->sysv_gregno = GP_ARG_MIN_REG;
7433 cum->stdarg = stdarg_p (fntype);
7435 cum->nargs_prototype = 0;
7436 if (incoming || cum->prototype)
7437 cum->nargs_prototype = n_named_args;
7439 /* Check for a longcall attribute. */
7440 if ((!fntype && rs6000_default_long_calls)
7442 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
7443 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
7444 cum->call_cookie |= CALL_LONG;
7446 if (TARGET_DEBUG_ARG)
7448 fprintf (stderr, "\ninit_cumulative_args:");
7451 tree ret_type = TREE_TYPE (fntype);
7452 fprintf (stderr, " ret code = %s,",
7453 tree_code_name[ (int)TREE_CODE (ret_type) ]);
7456 if (cum->call_cookie & CALL_LONG)
7457 fprintf (stderr, " longcall,");
7459 fprintf (stderr, " proto = %d, nargs = %d\n",
7460 cum->prototype, cum->nargs_prototype);
7463 #ifdef HAVE_AS_GNU_ATTRIBUTE
7464 if (DEFAULT_ABI == ABI_V4)
7466 cum->escapes = call_ABI_of_interest (fndecl);
7473 return_type = TREE_TYPE (fntype);
7474 return_mode = TYPE_MODE (return_type);
7477 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
7479 if (return_type != NULL)
7481 if (TREE_CODE (return_type) == RECORD_TYPE
7482 && TYPE_TRANSPARENT_AGGR (return_type))
7484 return_type = TREE_TYPE (first_field (return_type));
7485 return_mode = TYPE_MODE (return_type);
7487 if (AGGREGATE_TYPE_P (return_type)
7488 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
7490 rs6000_returns_struct = true;
7492 if (SCALAR_FLOAT_MODE_P (return_mode))
7493 rs6000_passes_float = true;
7494 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
7495 || SPE_VECTOR_MODE (return_mode))
7496 rs6000_passes_vector = true;
7503 && TARGET_ALTIVEC_ABI
7504 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
7506 error ("cannot return value in vector register because"
7507 " altivec instructions are disabled, use -maltivec"
7512 /* Return true if TYPE must be passed on the stack and not in registers. */
7515 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
7517 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
7518 return must_pass_in_stack_var_size (mode, type);
7520 return must_pass_in_stack_var_size_or_pad (mode, type);
7523 /* If defined, a C expression which determines whether, and in which
7524 direction, to pad out an argument with extra space. The value
7525 should be of type `enum direction': either `upward' to pad above
7526 the argument, `downward' to pad below, or `none' to inhibit
7529 For the AIX ABI structs are always stored left shifted in their
7533 function_arg_padding (enum machine_mode mode, const_tree type)
7535 #ifndef AGGREGATE_PADDING_FIXED
7536 #define AGGREGATE_PADDING_FIXED 0
7538 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
7539 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
7542 if (!AGGREGATE_PADDING_FIXED)
7544 /* GCC used to pass structures of the same size as integer types as
7545 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
7546 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
7547 passed padded downward, except that -mstrict-align further
7548 muddied the water in that multi-component structures of 2 and 4
7549 bytes in size were passed padded upward.
7551 The following arranges for best compatibility with previous
7552 versions of gcc, but removes the -mstrict-align dependency. */
7553 if (BYTES_BIG_ENDIAN)
7555 HOST_WIDE_INT size = 0;
7557 if (mode == BLKmode)
7559 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
7560 size = int_size_in_bytes (type);
7563 size = GET_MODE_SIZE (mode);
7565 if (size == 1 || size == 2 || size == 4)
7571 if (AGGREGATES_PAD_UPWARD_ALWAYS)
7573 if (type != 0 && AGGREGATE_TYPE_P (type))
7577 /* Fall back to the default. */
7578 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
7581 /* If defined, a C expression that gives the alignment boundary, in bits,
7582 of an argument with the specified mode and type. If it is not defined,
7583 PARM_BOUNDARY is used for all arguments.
7585 V.4 wants long longs and doubles to be double word aligned. Just
7586 testing the mode size is a boneheaded way to do this as it means
7587 that other types such as complex int are also double word aligned.
7588 However, we're stuck with this because changing the ABI might break
7589 existing library interfaces.
7591 Doubleword align SPE vectors.
7592 Quadword align Altivec/VSX vectors.
7593 Quadword align large synthetic vector types. */
7596 rs6000_function_arg_boundary (enum machine_mode mode, const_tree type)
7598 if (DEFAULT_ABI == ABI_V4
7599 && (GET_MODE_SIZE (mode) == 8
7600 || (TARGET_HARD_FLOAT
7602 && (mode == TFmode || mode == TDmode))))
7604 else if (SPE_VECTOR_MODE (mode)
7605 || (type && TREE_CODE (type) == VECTOR_TYPE
7606 && int_size_in_bytes (type) >= 8
7607 && int_size_in_bytes (type) < 16))
7609 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7610 || (type && TREE_CODE (type) == VECTOR_TYPE
7611 && int_size_in_bytes (type) >= 16))
7613 else if (TARGET_MACHO
7614 && rs6000_darwin64_abi
7616 && type && TYPE_ALIGN (type) > 64)
7619 return PARM_BOUNDARY;
7622 /* For a function parm of MODE and TYPE, return the starting word in
7623 the parameter area. NWORDS of the parameter area are already used. */
7626 rs6000_parm_start (enum machine_mode mode, const_tree type,
7627 unsigned int nwords)
7630 unsigned int parm_offset;
7632 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
7633 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
7634 return nwords + (-(parm_offset + nwords) & align);
7637 /* Compute the size (in words) of a function argument. */
7639 static unsigned long
7640 rs6000_arg_size (enum machine_mode mode, const_tree type)
7644 if (mode != BLKmode)
7645 size = GET_MODE_SIZE (mode);
7647 size = int_size_in_bytes (type);
7650 return (size + 3) >> 2;
7652 return (size + 7) >> 3;
7655 /* Use this to flush pending int fields. */
7658 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
7659 HOST_WIDE_INT bitpos, int final)
7661 unsigned int startbit, endbit;
7662 int intregs, intoffset;
7663 enum machine_mode mode;
7665 /* Handle the situations where a float is taking up the first half
7666 of the GPR, and the other half is empty (typically due to
7667 alignment restrictions). We can detect this by a 8-byte-aligned
7668 int field, or by seeing that this is the final flush for this
7669 argument. Count the word and continue on. */
7670 if (cum->floats_in_gpr == 1
7671 && (cum->intoffset % 64 == 0
7672 || (cum->intoffset == -1 && final)))
7675 cum->floats_in_gpr = 0;
7678 if (cum->intoffset == -1)
7681 intoffset = cum->intoffset;
7682 cum->intoffset = -1;
7683 cum->floats_in_gpr = 0;
7685 if (intoffset % BITS_PER_WORD != 0)
7687 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
7689 if (mode == BLKmode)
7691 /* We couldn't find an appropriate mode, which happens,
7692 e.g., in packed structs when there are 3 bytes to load.
7693 Back intoffset back to the beginning of the word in this
7695 intoffset = intoffset & -BITS_PER_WORD;
7699 startbit = intoffset & -BITS_PER_WORD;
7700 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
7701 intregs = (endbit - startbit) / BITS_PER_WORD;
7702 cum->words += intregs;
7703 /* words should be unsigned. */
7704 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
7706 int pad = (endbit/BITS_PER_WORD) - cum->words;
7711 /* The darwin64 ABI calls for us to recurse down through structs,
7712 looking for elements passed in registers. Unfortunately, we have
7713 to track int register count here also because of misalignments
7714 in powerpc alignment mode. */
7717 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
7719 HOST_WIDE_INT startbitpos)
7723 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
7724 if (TREE_CODE (f) == FIELD_DECL)
7726 HOST_WIDE_INT bitpos = startbitpos;
7727 tree ftype = TREE_TYPE (f);
7728 enum machine_mode mode;
7729 if (ftype == error_mark_node)
7731 mode = TYPE_MODE (ftype);
7733 if (DECL_SIZE (f) != 0
7734 && host_integerp (bit_position (f), 1))
7735 bitpos += int_bit_position (f);
7737 /* ??? FIXME: else assume zero offset. */
7739 if (TREE_CODE (ftype) == RECORD_TYPE)
7740 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
7741 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
7743 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
7744 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7745 cum->fregno += n_fpregs;
7746 /* Single-precision floats present a special problem for
7747 us, because they are smaller than an 8-byte GPR, and so
7748 the structure-packing rules combined with the standard
7749 varargs behavior mean that we want to pack float/float
7750 and float/int combinations into a single register's
7751 space. This is complicated by the arg advance flushing,
7752 which works on arbitrarily large groups of int-type
7756 if (cum->floats_in_gpr == 1)
7758 /* Two floats in a word; count the word and reset
7761 cum->floats_in_gpr = 0;
7763 else if (bitpos % 64 == 0)
7765 /* A float at the beginning of an 8-byte word;
7766 count it and put off adjusting cum->words until
7767 we see if a arg advance flush is going to do it
7769 cum->floats_in_gpr++;
7773 /* The float is at the end of a word, preceded
7774 by integer fields, so the arg advance flush
7775 just above has already set cum->words and
7776 everything is taken care of. */
7780 cum->words += n_fpregs;
7782 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
7784 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
7788 else if (cum->intoffset == -1)
7789 cum->intoffset = bitpos;
7793 /* Check for an item that needs to be considered specially under the darwin 64
7794 bit ABI. These are record types where the mode is BLK or the structure is
7797 rs6000_darwin64_struct_check_p (enum machine_mode mode, const_tree type)
7799 return rs6000_darwin64_abi
7800 && ((mode == BLKmode
7801 && TREE_CODE (type) == RECORD_TYPE
7802 && int_size_in_bytes (type) > 0)
7803 || (type && TREE_CODE (type) == RECORD_TYPE
7804 && int_size_in_bytes (type) == 8)) ? 1 : 0;
7807 /* Update the data in CUM to advance over an argument
7808 of mode MODE and data type TYPE.
7809 (TYPE is null for libcalls where that information may not be available.)
7811 Note that for args passed by reference, function_arg will be called
7812 with MODE and TYPE set to that of the pointer to the arg, not the arg
7816 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, enum machine_mode mode,
7817 const_tree type, bool named, int depth)
7819 /* Only tick off an argument if we're not recursing. */
7821 cum->nargs_prototype--;
7823 #ifdef HAVE_AS_GNU_ATTRIBUTE
7824 if (DEFAULT_ABI == ABI_V4
7827 if (SCALAR_FLOAT_MODE_P (mode))
7828 rs6000_passes_float = true;
7829 else if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
7830 rs6000_passes_vector = true;
7831 else if (SPE_VECTOR_MODE (mode)
7833 && cum->sysv_gregno <= GP_ARG_MAX_REG)
7834 rs6000_passes_vector = true;
7838 if (TARGET_ALTIVEC_ABI
7839 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
7840 || (type && TREE_CODE (type) == VECTOR_TYPE
7841 && int_size_in_bytes (type) == 16)))
7845 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
7848 if (!TARGET_ALTIVEC)
7849 error ("cannot pass argument in vector register because"
7850 " altivec instructions are disabled, use -maltivec"
7853 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
7854 even if it is going to be passed in a vector register.
7855 Darwin does the same for variable-argument functions. */
7856 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
7857 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
7867 /* Vector parameters must be 16-byte aligned. This places
7868 them at 2 mod 4 in terms of words in 32-bit mode, since
7869 the parameter save area starts at offset 24 from the
7870 stack. In 64-bit mode, they just have to start on an
7871 even word, since the parameter save area is 16-byte
7872 aligned. Space for GPRs is reserved even if the argument
7873 will be passed in memory. */
7875 align = (2 - cum->words) & 3;
7877 align = cum->words & 1;
7878 cum->words += align + rs6000_arg_size (mode, type);
7880 if (TARGET_DEBUG_ARG)
7882 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
7884 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
7885 cum->nargs_prototype, cum->prototype,
7886 GET_MODE_NAME (mode));
7890 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
7892 && cum->sysv_gregno <= GP_ARG_MAX_REG)
7895 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
7897 int size = int_size_in_bytes (type);
7898 /* Variable sized types have size == -1 and are
7899 treated as if consisting entirely of ints.
7900 Pad to 16 byte boundary if needed. */
7901 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
7902 && (cum->words % 2) != 0)
7904 /* For varargs, we can just go up by the size of the struct. */
7906 cum->words += (size + 7) / 8;
7909 /* It is tempting to say int register count just goes up by
7910 sizeof(type)/8, but this is wrong in a case such as
7911 { int; double; int; } [powerpc alignment]. We have to
7912 grovel through the fields for these too. */
7914 cum->floats_in_gpr = 0;
7915 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
7916 rs6000_darwin64_record_arg_advance_flush (cum,
7917 size * BITS_PER_UNIT, 1);
7919 if (TARGET_DEBUG_ARG)
7921 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
7922 cum->words, TYPE_ALIGN (type), size);
7924 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
7925 cum->nargs_prototype, cum->prototype,
7926 GET_MODE_NAME (mode));
7929 else if (DEFAULT_ABI == ABI_V4)
7931 if (TARGET_HARD_FLOAT && TARGET_FPRS
7932 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
7933 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
7934 || (mode == TFmode && !TARGET_IEEEQUAD)
7935 || mode == SDmode || mode == DDmode || mode == TDmode))
7937 /* _Decimal128 must use an even/odd register pair. This assumes
7938 that the register number is odd when fregno is odd. */
7939 if (mode == TDmode && (cum->fregno % 2) == 1)
7942 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
7943 <= FP_ARG_V4_MAX_REG)
7944 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
7947 cum->fregno = FP_ARG_V4_MAX_REG + 1;
7948 if (mode == DFmode || mode == TFmode
7949 || mode == DDmode || mode == TDmode)
7950 cum->words += cum->words & 1;
7951 cum->words += rs6000_arg_size (mode, type);
7956 int n_words = rs6000_arg_size (mode, type);
7957 int gregno = cum->sysv_gregno;
7959 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
7960 (r7,r8) or (r9,r10). As does any other 2 word item such
7961 as complex int due to a historical mistake. */
7963 gregno += (1 - gregno) & 1;
7965 /* Multi-reg args are not split between registers and stack. */
7966 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
7968 /* Long long and SPE vectors are aligned on the stack.
7969 So are other 2 word items such as complex int due to
7970 a historical mistake. */
7972 cum->words += cum->words & 1;
7973 cum->words += n_words;
7976 /* Note: continuing to accumulate gregno past when we've started
7977 spilling to the stack indicates the fact that we've started
7978 spilling to the stack to expand_builtin_saveregs. */
7979 cum->sysv_gregno = gregno + n_words;
7982 if (TARGET_DEBUG_ARG)
7984 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
7985 cum->words, cum->fregno);
7986 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
7987 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
7988 fprintf (stderr, "mode = %4s, named = %d\n",
7989 GET_MODE_NAME (mode), named);
7994 int n_words = rs6000_arg_size (mode, type);
7995 int start_words = cum->words;
7996 int align_words = rs6000_parm_start (mode, type, start_words);
7998 cum->words = align_words + n_words;
8000 if (SCALAR_FLOAT_MODE_P (mode)
8001 && TARGET_HARD_FLOAT && TARGET_FPRS)
8003 /* _Decimal128 must be passed in an even/odd float register pair.
8004 This assumes that the register number is odd when fregno is
8006 if (mode == TDmode && (cum->fregno % 2) == 1)
8008 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
8011 if (TARGET_DEBUG_ARG)
8013 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
8014 cum->words, cum->fregno);
8015 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
8016 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
8017 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
8018 named, align_words - start_words, depth);
8024 rs6000_function_arg_advance (cumulative_args_t cum, enum machine_mode mode,
8025 const_tree type, bool named)
8027 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
8032 spe_build_register_parallel (enum machine_mode mode, int gregno)
8039 r1 = gen_rtx_REG (DImode, gregno);
8040 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8041 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
8045 r1 = gen_rtx_REG (DImode, gregno);
8046 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8047 r3 = gen_rtx_REG (DImode, gregno + 2);
8048 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
8049 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
8052 r1 = gen_rtx_REG (DImode, gregno);
8053 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
8054 r3 = gen_rtx_REG (DImode, gregno + 2);
8055 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
8056 r5 = gen_rtx_REG (DImode, gregno + 4);
8057 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
8058 r7 = gen_rtx_REG (DImode, gregno + 6);
8059 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
8060 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
8067 /* Determine where to put a SIMD argument on the SPE. */
8069 rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
8072 int gregno = cum->sysv_gregno;
8074 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
8075 are passed and returned in a pair of GPRs for ABI compatibility. */
8076 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
8077 || mode == DCmode || mode == TCmode))
8079 int n_words = rs6000_arg_size (mode, type);
8081 /* Doubles go in an odd/even register pair (r5/r6, etc). */
8083 gregno += (1 - gregno) & 1;
8085 /* Multi-reg args are not split between registers and stack. */
8086 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8089 return spe_build_register_parallel (mode, gregno);
8093 int n_words = rs6000_arg_size (mode, type);
8095 /* SPE vectors are put in odd registers. */
8096 if (n_words == 2 && (gregno & 1) == 0)
8099 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
8102 enum machine_mode m = SImode;
8104 r1 = gen_rtx_REG (m, gregno);
8105 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
8106 r2 = gen_rtx_REG (m, gregno + 1);
8107 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
8108 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
8115 if (gregno <= GP_ARG_MAX_REG)
8116 return gen_rtx_REG (mode, gregno);
8122 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
8123 structure between cum->intoffset and bitpos to integer registers. */
8126 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
8127 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
8129 enum machine_mode mode;
8131 unsigned int startbit, endbit;
8132 int this_regno, intregs, intoffset;
8135 if (cum->intoffset == -1)
8138 intoffset = cum->intoffset;
8139 cum->intoffset = -1;
8141 /* If this is the trailing part of a word, try to only load that
8142 much into the register. Otherwise load the whole register. Note
8143 that in the latter case we may pick up unwanted bits. It's not a
8144 problem at the moment but may wish to revisit. */
8146 if (intoffset % BITS_PER_WORD != 0)
8148 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
8150 if (mode == BLKmode)
8152 /* We couldn't find an appropriate mode, which happens,
8153 e.g., in packed structs when there are 3 bytes to load.
8154 Back intoffset back to the beginning of the word in this
8156 intoffset = intoffset & -BITS_PER_WORD;
8163 startbit = intoffset & -BITS_PER_WORD;
8164 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
8165 intregs = (endbit - startbit) / BITS_PER_WORD;
8166 this_regno = cum->words + intoffset / BITS_PER_WORD;
8168 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
8171 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
8175 intoffset /= BITS_PER_UNIT;
8178 regno = GP_ARG_MIN_REG + this_regno;
8179 reg = gen_rtx_REG (mode, regno);
8181 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
8184 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
8188 while (intregs > 0);
8191 /* Recursive workhorse for the following. */
8194 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
8195 HOST_WIDE_INT startbitpos, rtx rvec[],
8200 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
8201 if (TREE_CODE (f) == FIELD_DECL)
8203 HOST_WIDE_INT bitpos = startbitpos;
8204 tree ftype = TREE_TYPE (f);
8205 enum machine_mode mode;
8206 if (ftype == error_mark_node)
8208 mode = TYPE_MODE (ftype);
8210 if (DECL_SIZE (f) != 0
8211 && host_integerp (bit_position (f), 1))
8212 bitpos += int_bit_position (f);
8214 /* ??? FIXME: else assume zero offset. */
8216 if (TREE_CODE (ftype) == RECORD_TYPE)
8217 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
8218 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
8220 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8224 case SCmode: mode = SFmode; break;
8225 case DCmode: mode = DFmode; break;
8226 case TCmode: mode = TFmode; break;
8230 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8231 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8233 gcc_assert (cum->fregno == FP_ARG_MAX_REG
8234 && (mode == TFmode || mode == TDmode));
8235 /* Long double or _Decimal128 split over regs and memory. */
8236 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
8240 = gen_rtx_EXPR_LIST (VOIDmode,
8241 gen_rtx_REG (mode, cum->fregno++),
8242 GEN_INT (bitpos / BITS_PER_UNIT));
8243 if (mode == TFmode || mode == TDmode)
8246 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
8248 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
8250 = gen_rtx_EXPR_LIST (VOIDmode,
8251 gen_rtx_REG (mode, cum->vregno++),
8252 GEN_INT (bitpos / BITS_PER_UNIT));
8254 else if (cum->intoffset == -1)
8255 cum->intoffset = bitpos;
8259 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
8260 the register(s) to be used for each field and subfield of a struct
8261 being passed by value, along with the offset of where the
8262 register's value may be found in the block. FP fields go in FP
8263 register, vector fields go in vector registers, and everything
8264 else goes in int registers, packed as in memory.
8266 This code is also used for function return values. RETVAL indicates
8267 whether this is the case.
8269 Much of this is taken from the SPARC V9 port, which has a similar
8270 calling convention. */
8273 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
8274 bool named, bool retval)
8276 rtx rvec[FIRST_PSEUDO_REGISTER];
8277 int k = 1, kbase = 1;
8278 HOST_WIDE_INT typesize = int_size_in_bytes (type);
8279 /* This is a copy; modifications are not visible to our caller. */
8280 CUMULATIVE_ARGS copy_cum = *orig_cum;
8281 CUMULATIVE_ARGS *cum = ©_cum;
8283 /* Pad to 16 byte boundary if needed. */
8284 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
8285 && (cum->words % 2) != 0)
8292 /* Put entries into rvec[] for individual FP and vector fields, and
8293 for the chunks of memory that go in int regs. Note we start at
8294 element 1; 0 is reserved for an indication of using memory, and
8295 may or may not be filled in below. */
8296 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
8297 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
8299 /* If any part of the struct went on the stack put all of it there.
8300 This hack is because the generic code for
8301 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
8302 parts of the struct are not at the beginning. */
8306 return NULL_RTX; /* doesn't go in registers at all */
8308 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8310 if (k > 1 || cum->use_stack)
8311 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
8316 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
8319 rs6000_mixed_function_arg (enum machine_mode mode, const_tree type,
8324 rtx rvec[GP_ARG_NUM_REG + 1];
8326 if (align_words >= GP_ARG_NUM_REG)
8329 n_units = rs6000_arg_size (mode, type);
8331 /* Optimize the simple case where the arg fits in one gpr, except in
8332 the case of BLKmode due to assign_parms assuming that registers are
8333 BITS_PER_WORD wide. */
8335 || (n_units == 1 && mode != BLKmode))
8336 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8339 if (align_words + n_units > GP_ARG_NUM_REG)
8340 /* Not all of the arg fits in gprs. Say that it goes in memory too,
8341 using a magic NULL_RTX component.
8342 This is not strictly correct. Only some of the arg belongs in
8343 memory, not all of it. However, the normal scheme using
8344 function_arg_partial_nregs can result in unusual subregs, eg.
8345 (subreg:SI (reg:DF) 4), which are not handled well. The code to
8346 store the whole arg to memory is often more efficient than code
8347 to store pieces, and we know that space is available in the right
8348 place for the whole arg. */
8349 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8354 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
8355 rtx off = GEN_INT (i++ * 4);
8356 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8358 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
8360 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8363 /* Determine where to put an argument to a function.
8364 Value is zero to push the argument on the stack,
8365 or a hard register in which to store the argument.
8367 MODE is the argument's machine mode.
8368 TYPE is the data type of the argument (as a tree).
8369 This is null for libcalls where that information may
8371 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8372 the preceding args and about the function being called. It is
8373 not modified in this routine.
8374 NAMED is nonzero if this argument is a named parameter
8375 (otherwise it is an extra parameter matching an ellipsis).
8377 On RS/6000 the first eight words of non-FP are normally in registers
8378 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
8379 Under V.4, the first 8 FP args are in registers.
8381 If this is floating-point and no prototype is specified, we use
8382 both an FP and integer register (or possibly FP reg and stack). Library
8383 functions (when CALL_LIBCALL is set) always have the proper types for args,
8384 so we can pass the FP value just in one register. emit_library_function
8385 doesn't support PARALLEL anyway.
8387 Note that for args passed by reference, function_arg will be called
8388 with MODE and TYPE set to that of the pointer to the arg, not the arg
8392 rs6000_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
8393 const_tree type, bool named)
8395 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8396 enum rs6000_abi abi = DEFAULT_ABI;
8398 /* Return a marker to indicate whether CR1 needs to set or clear the
8399 bit that V.4 uses to say fp args were passed in registers.
8400 Assume that we don't need the marker for software floating point,
8401 or compiler generated library calls. */
8402 if (mode == VOIDmode)
8405 && (cum->call_cookie & CALL_LIBCALL) == 0
8407 || (cum->nargs_prototype < 0
8408 && (cum->prototype || TARGET_NO_PROTOTYPE))))
8410 /* For the SPE, we need to crxor CR6 always. */
8412 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
8413 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
8414 return GEN_INT (cum->call_cookie
8415 | ((cum->fregno == FP_ARG_MIN_REG)
8416 ? CALL_V4_SET_FP_ARGS
8417 : CALL_V4_CLEAR_FP_ARGS));
8420 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
8423 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8425 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
8426 if (rslt != NULL_RTX)
8428 /* Else fall through to usual handling. */
8431 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
8432 if (TARGET_64BIT && ! cum->prototype)
8434 /* Vector parameters get passed in vector register
8435 and also in GPRs or memory, in absence of prototype. */
8438 align_words = (cum->words + 1) & ~1;
8440 if (align_words >= GP_ARG_NUM_REG)
8446 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8448 return gen_rtx_PARALLEL (mode,
8450 gen_rtx_EXPR_LIST (VOIDmode,
8452 gen_rtx_EXPR_LIST (VOIDmode,
8453 gen_rtx_REG (mode, cum->vregno),
8457 return gen_rtx_REG (mode, cum->vregno);
8458 else if (TARGET_ALTIVEC_ABI
8459 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
8460 || (type && TREE_CODE (type) == VECTOR_TYPE
8461 && int_size_in_bytes (type) == 16)))
8463 if (named || abi == ABI_V4)
8467 /* Vector parameters to varargs functions under AIX or Darwin
8468 get passed in memory and possibly also in GPRs. */
8469 int align, align_words, n_words;
8470 enum machine_mode part_mode;
8472 /* Vector parameters must be 16-byte aligned. This places them at
8473 2 mod 4 in terms of words in 32-bit mode, since the parameter
8474 save area starts at offset 24 from the stack. In 64-bit mode,
8475 they just have to start on an even word, since the parameter
8476 save area is 16-byte aligned. */
8478 align = (2 - cum->words) & 3;
8480 align = cum->words & 1;
8481 align_words = cum->words + align;
8483 /* Out of registers? Memory, then. */
8484 if (align_words >= GP_ARG_NUM_REG)
8487 if (TARGET_32BIT && TARGET_POWERPC64)
8488 return rs6000_mixed_function_arg (mode, type, align_words);
8490 /* The vector value goes in GPRs. Only the part of the
8491 value in GPRs is reported here. */
8493 n_words = rs6000_arg_size (mode, type);
8494 if (align_words + n_words > GP_ARG_NUM_REG)
8495 /* Fortunately, there are only two possibilities, the value
8496 is either wholly in GPRs or half in GPRs and half not. */
8499 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
8502 else if (TARGET_SPE_ABI && TARGET_SPE
8503 && (SPE_VECTOR_MODE (mode)
8504 || (TARGET_E500_DOUBLE && (mode == DFmode
8507 || mode == TCmode))))
8508 return rs6000_spe_function_arg (cum, mode, type);
8510 else if (abi == ABI_V4)
8512 if (TARGET_HARD_FLOAT && TARGET_FPRS
8513 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
8514 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
8515 || (mode == TFmode && !TARGET_IEEEQUAD)
8516 || mode == SDmode || mode == DDmode || mode == TDmode))
8518 /* _Decimal128 must use an even/odd register pair. This assumes
8519 that the register number is odd when fregno is odd. */
8520 if (mode == TDmode && (cum->fregno % 2) == 1)
8523 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
8524 <= FP_ARG_V4_MAX_REG)
8525 return gen_rtx_REG (mode, cum->fregno);
8531 int n_words = rs6000_arg_size (mode, type);
8532 int gregno = cum->sysv_gregno;
8534 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
8535 (r7,r8) or (r9,r10). As does any other 2 word item such
8536 as complex int due to a historical mistake. */
8538 gregno += (1 - gregno) & 1;
8540 /* Multi-reg args are not split between registers and stack. */
8541 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
8544 if (TARGET_32BIT && TARGET_POWERPC64)
8545 return rs6000_mixed_function_arg (mode, type,
8546 gregno - GP_ARG_MIN_REG);
8547 return gen_rtx_REG (mode, gregno);
8552 int align_words = rs6000_parm_start (mode, type, cum->words);
8554 /* _Decimal128 must be passed in an even/odd float register pair.
8555 This assumes that the register number is odd when fregno is odd. */
8556 if (mode == TDmode && (cum->fregno % 2) == 1)
8559 if (USE_FP_FOR_ARG_P (cum, mode, type))
8561 rtx rvec[GP_ARG_NUM_REG + 1];
8565 enum machine_mode fmode = mode;
8566 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
8568 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
8570 /* Currently, we only ever need one reg here because complex
8571 doubles are split. */
8572 gcc_assert (cum->fregno == FP_ARG_MAX_REG
8573 && (fmode == TFmode || fmode == TDmode));
8575 /* Long double or _Decimal128 split over regs and memory. */
8576 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
8579 /* Do we also need to pass this arg in the parameter save
8582 && (cum->nargs_prototype <= 0
8583 || (DEFAULT_ABI == ABI_AIX
8585 && align_words >= GP_ARG_NUM_REG)));
8587 if (!needs_psave && mode == fmode)
8588 return gen_rtx_REG (fmode, cum->fregno);
8593 /* Describe the part that goes in gprs or the stack.
8594 This piece must come first, before the fprs. */
8595 if (align_words < GP_ARG_NUM_REG)
8597 unsigned long n_words = rs6000_arg_size (mode, type);
8599 if (align_words + n_words > GP_ARG_NUM_REG
8600 || (TARGET_32BIT && TARGET_POWERPC64))
8602 /* If this is partially on the stack, then we only
8603 include the portion actually in registers here. */
8604 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
8607 if (align_words + n_words > GP_ARG_NUM_REG)
8608 /* Not all of the arg fits in gprs. Say that it
8609 goes in memory too, using a magic NULL_RTX
8610 component. Also see comment in
8611 rs6000_mixed_function_arg for why the normal
8612 function_arg_partial_nregs scheme doesn't work
8614 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
8618 r = gen_rtx_REG (rmode,
8619 GP_ARG_MIN_REG + align_words);
8620 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
8621 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
8623 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
8627 /* The whole arg fits in gprs. */
8628 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8629 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8633 /* It's entirely in memory. */
8634 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
8637 /* Describe where this piece goes in the fprs. */
8638 r = gen_rtx_REG (fmode, cum->fregno);
8639 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
8641 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
8643 else if (align_words < GP_ARG_NUM_REG)
8645 if (TARGET_32BIT && TARGET_POWERPC64)
8646 return rs6000_mixed_function_arg (mode, type, align_words);
8648 if (mode == BLKmode)
8651 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
8658 /* For an arg passed partly in registers and partly in memory, this is
8659 the number of bytes passed in registers. For args passed entirely in
8660 registers or entirely in memory, zero. When an arg is described by a
8661 PARALLEL, perhaps using more than one register type, this function
8662 returns the number of bytes used by the first element of the PARALLEL. */
8665 rs6000_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
8666 tree type, bool named)
8668 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
8672 if (DEFAULT_ABI == ABI_V4)
8675 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
8676 && cum->nargs_prototype >= 0)
8679 /* In this complicated case we just disable the partial_nregs code. */
8680 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
8683 align_words = rs6000_parm_start (mode, type, cum->words);
8685 if (USE_FP_FOR_ARG_P (cum, mode, type))
8687 /* If we are passing this arg in the fixed parameter save area
8688 (gprs or memory) as well as fprs, then this function should
8689 return the number of partial bytes passed in the parameter
8690 save area rather than partial bytes passed in fprs. */
8692 && (cum->nargs_prototype <= 0
8693 || (DEFAULT_ABI == ABI_AIX
8695 && align_words >= GP_ARG_NUM_REG)))
8697 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
8698 > FP_ARG_MAX_REG + 1)
8699 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
8700 else if (cum->nargs_prototype >= 0)
8704 if (align_words < GP_ARG_NUM_REG
8705 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
8706 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
8708 if (ret != 0 && TARGET_DEBUG_ARG)
8709 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
8714 /* A C expression that indicates when an argument must be passed by
8715 reference. If nonzero for an argument, a copy of that argument is
8716 made in memory and a pointer to the argument is passed instead of
8717 the argument itself. The pointer is passed in whatever way is
8718 appropriate for passing a pointer to that type.
8720 Under V.4, aggregates and long double are passed by reference.
8722 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
8723 reference unless the AltiVec vector extension ABI is in force.
8725 As an extension to all ABIs, variable sized types are passed by
8729 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
8730 enum machine_mode mode, const_tree type,
8731 bool named ATTRIBUTE_UNUSED)
8733 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
8735 if (TARGET_DEBUG_ARG)
8736 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
8743 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
8745 if (TARGET_DEBUG_ARG)
8746 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
8750 if (int_size_in_bytes (type) < 0)
8752 if (TARGET_DEBUG_ARG)
8753 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
8757 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8758 modes only exist for GCC vector types if -maltivec. */
8759 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
8761 if (TARGET_DEBUG_ARG)
8762 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
8766 /* Pass synthetic vectors in memory. */
8767 if (TREE_CODE (type) == VECTOR_TYPE
8768 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
8770 static bool warned_for_pass_big_vectors = false;
8771 if (TARGET_DEBUG_ARG)
8772 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
8773 if (!warned_for_pass_big_vectors)
8775 warning (0, "GCC vector passed by reference: "
8776 "non-standard ABI extension with no compatibility guarantee");
8777 warned_for_pass_big_vectors = true;
8786 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
8789 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
8794 for (i = 0; i < nregs; i++)
8796 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
8797 if (reload_completed)
8799 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
8802 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
8803 i * GET_MODE_SIZE (reg_mode));
8806 tem = replace_equiv_address (tem, XEXP (tem, 0));
8810 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
8814 /* Perform any needed actions needed for a function that is receiving a
8815 variable number of arguments.
8819 MODE and TYPE are the mode and type of the current parameter.
8821 PRETEND_SIZE is a variable that should be set to the amount of stack
8822 that must be pushed by the prolog to pretend that our caller pushed
8825 Normally, this macro will push all remaining incoming registers on the
8826 stack and set PRETEND_SIZE to the length of the registers pushed. */
8829 setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
8830 tree type, int *pretend_size ATTRIBUTE_UNUSED,
8833 CUMULATIVE_ARGS next_cum;
8834 int reg_size = TARGET_32BIT ? 4 : 8;
8835 rtx save_area = NULL_RTX, mem;
8836 int first_reg_offset;
8839 /* Skip the last named argument. */
8840 next_cum = *get_cumulative_args (cum);
8841 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
8843 if (DEFAULT_ABI == ABI_V4)
8845 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
8849 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
8850 HOST_WIDE_INT offset = 0;
8852 /* Try to optimize the size of the varargs save area.
8853 The ABI requires that ap.reg_save_area is doubleword
8854 aligned, but we don't need to allocate space for all
8855 the bytes, only those to which we actually will save
8857 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
8858 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
8859 if (TARGET_HARD_FLOAT && TARGET_FPRS
8860 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8861 && cfun->va_list_fpr_size)
8864 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
8865 * UNITS_PER_FP_WORD;
8866 if (cfun->va_list_fpr_size
8867 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8868 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
8870 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
8871 * UNITS_PER_FP_WORD;
8875 offset = -((first_reg_offset * reg_size) & ~7);
8876 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
8878 gpr_reg_num = cfun->va_list_gpr_size;
8879 if (reg_size == 4 && (first_reg_offset & 1))
8882 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
8885 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
8887 - (int) (GP_ARG_NUM_REG * reg_size);
8889 if (gpr_size + fpr_size)
8892 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
8893 gcc_assert (GET_CODE (reg_save_area) == MEM);
8894 reg_save_area = XEXP (reg_save_area, 0);
8895 if (GET_CODE (reg_save_area) == PLUS)
8897 gcc_assert (XEXP (reg_save_area, 0)
8898 == virtual_stack_vars_rtx);
8899 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
8900 offset += INTVAL (XEXP (reg_save_area, 1));
8903 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
8906 cfun->machine->varargs_save_offset = offset;
8907 save_area = plus_constant (virtual_stack_vars_rtx, offset);
8912 first_reg_offset = next_cum.words;
8913 save_area = virtual_incoming_args_rtx;
8915 if (targetm.calls.must_pass_in_stack (mode, type))
8916 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
8919 set = get_varargs_alias_set ();
8920 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
8921 && cfun->va_list_gpr_size)
8923 int nregs = GP_ARG_NUM_REG - first_reg_offset;
8925 if (va_list_gpr_counter_field)
8927 /* V4 va_list_gpr_size counts number of registers needed. */
8928 if (nregs > cfun->va_list_gpr_size)
8929 nregs = cfun->va_list_gpr_size;
8933 /* char * va_list instead counts number of bytes needed. */
8934 if (nregs > cfun->va_list_gpr_size / reg_size)
8935 nregs = cfun->va_list_gpr_size / reg_size;
8938 mem = gen_rtx_MEM (BLKmode,
8939 plus_constant (save_area,
8940 first_reg_offset * reg_size));
8941 MEM_NOTRAP_P (mem) = 1;
8942 set_mem_alias_set (mem, set);
8943 set_mem_align (mem, BITS_PER_WORD);
8945 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
8949 /* Save FP registers if needed. */
8950 if (DEFAULT_ABI == ABI_V4
8951 && TARGET_HARD_FLOAT && TARGET_FPRS
8953 && next_cum.fregno <= FP_ARG_V4_MAX_REG
8954 && cfun->va_list_fpr_size)
8956 int fregno = next_cum.fregno, nregs;
8957 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
8958 rtx lab = gen_label_rtx ();
8959 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
8960 * UNITS_PER_FP_WORD);
8963 (gen_rtx_SET (VOIDmode,
8965 gen_rtx_IF_THEN_ELSE (VOIDmode,
8966 gen_rtx_NE (VOIDmode, cr1,
8968 gen_rtx_LABEL_REF (VOIDmode, lab),
8972 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
8973 fregno++, off += UNITS_PER_FP_WORD, nregs++)
8975 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8977 plus_constant (save_area, off));
8978 MEM_NOTRAP_P (mem) = 1;
8979 set_mem_alias_set (mem, set);
8980 set_mem_align (mem, GET_MODE_ALIGNMENT (
8981 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8982 ? DFmode : SFmode));
8983 emit_move_insn (mem, gen_rtx_REG (
8984 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
8985 ? DFmode : SFmode, fregno));
8992 /* Create the va_list data type. */
8995 rs6000_build_builtin_va_list (void)
8997 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
8999 /* For AIX, prefer 'char *' because that's what the system
9000 header files like. */
9001 if (DEFAULT_ABI != ABI_V4)
9002 return build_pointer_type (char_type_node);
9004 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
9005 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
9006 get_identifier ("__va_list_tag"), record);
9008 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
9009 unsigned_char_type_node);
9010 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
9011 unsigned_char_type_node);
9012 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
9014 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9015 get_identifier ("reserved"), short_unsigned_type_node);
9016 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9017 get_identifier ("overflow_arg_area"),
9019 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
9020 get_identifier ("reg_save_area"),
9023 va_list_gpr_counter_field = f_gpr;
9024 va_list_fpr_counter_field = f_fpr;
9026 DECL_FIELD_CONTEXT (f_gpr) = record;
9027 DECL_FIELD_CONTEXT (f_fpr) = record;
9028 DECL_FIELD_CONTEXT (f_res) = record;
9029 DECL_FIELD_CONTEXT (f_ovf) = record;
9030 DECL_FIELD_CONTEXT (f_sav) = record;
9032 TYPE_STUB_DECL (record) = type_decl;
9033 TYPE_NAME (record) = type_decl;
9034 TYPE_FIELDS (record) = f_gpr;
9035 DECL_CHAIN (f_gpr) = f_fpr;
9036 DECL_CHAIN (f_fpr) = f_res;
9037 DECL_CHAIN (f_res) = f_ovf;
9038 DECL_CHAIN (f_ovf) = f_sav;
9040 layout_type (record);
9042 /* The correct type is an array type of one element. */
9043 return build_array_type (record, build_index_type (size_zero_node));
9046 /* Implement va_start. */
9049 rs6000_va_start (tree valist, rtx nextarg)
9051 HOST_WIDE_INT words, n_gpr, n_fpr;
9052 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
9053 tree gpr, fpr, ovf, sav, t;
9055 /* Only SVR4 needs something special. */
9056 if (DEFAULT_ABI != ABI_V4)
9058 std_expand_builtin_va_start (valist, nextarg);
9062 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9063 f_fpr = DECL_CHAIN (f_gpr);
9064 f_res = DECL_CHAIN (f_fpr);
9065 f_ovf = DECL_CHAIN (f_res);
9066 f_sav = DECL_CHAIN (f_ovf);
9068 valist = build_simple_mem_ref (valist);
9069 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9070 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9072 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9074 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9077 /* Count number of gp and fp argument registers used. */
9078 words = crtl->args.info.words;
9079 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
9081 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
9084 if (TARGET_DEBUG_ARG)
9085 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
9086 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
9087 words, n_gpr, n_fpr);
9089 if (cfun->va_list_gpr_size)
9091 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9092 build_int_cst (NULL_TREE, n_gpr));
9093 TREE_SIDE_EFFECTS (t) = 1;
9094 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9097 if (cfun->va_list_fpr_size)
9099 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9100 build_int_cst (NULL_TREE, n_fpr));
9101 TREE_SIDE_EFFECTS (t) = 1;
9102 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9104 #ifdef HAVE_AS_GNU_ATTRIBUTE
9105 if (call_ABI_of_interest (cfun->decl))
9106 rs6000_passes_float = true;
9110 /* Find the overflow area. */
9111 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9113 t = fold_build_pointer_plus_hwi (t, words * UNITS_PER_WORD);
9114 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9115 TREE_SIDE_EFFECTS (t) = 1;
9116 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9118 /* If there were no va_arg invocations, don't set up the register
9120 if (!cfun->va_list_gpr_size
9121 && !cfun->va_list_fpr_size
9122 && n_gpr < GP_ARG_NUM_REG
9123 && n_fpr < FP_ARG_V4_MAX_REG)
9126 /* Find the register save area. */
9127 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
9128 if (cfun->machine->varargs_save_offset)
9129 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
9130 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9131 TREE_SIDE_EFFECTS (t) = 1;
9132 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9135 /* Implement va_arg. */
9138 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9141 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
9142 tree gpr, fpr, ovf, sav, reg, t, u;
9143 int size, rsize, n_reg, sav_ofs, sav_scale;
9144 tree lab_false, lab_over, addr;
9146 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
9150 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9152 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
9153 return build_va_arg_indirect_ref (t);
9156 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
9157 earlier version of gcc, with the property that it always applied alignment
9158 adjustments to the va-args (even for zero-sized types). The cheapest way
9159 to deal with this is to replicate the effect of the part of
9160 std_gimplify_va_arg_expr that carries out the align adjust, for the case
9162 We don't need to check for pass-by-reference because of the test above.
9163 We can return a simplifed answer, since we know there's no offset to add. */
9166 && rs6000_darwin64_abi
9167 && integer_zerop (TYPE_SIZE (type)))
9169 unsigned HOST_WIDE_INT align, boundary;
9170 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
9171 align = PARM_BOUNDARY / BITS_PER_UNIT;
9172 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
9173 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
9174 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
9175 boundary /= BITS_PER_UNIT;
9176 if (boundary > align)
9179 /* This updates arg ptr by the amount that would be necessary
9180 to align the zero-sized (but not zero-alignment) item. */
9181 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9182 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
9183 gimplify_and_add (t, pre_p);
9185 t = fold_convert (sizetype, valist_tmp);
9186 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
9187 fold_convert (TREE_TYPE (valist),
9188 fold_build2 (BIT_AND_EXPR, sizetype, t,
9189 size_int (-boundary))));
9190 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
9191 gimplify_and_add (t, pre_p);
9193 /* Since it is zero-sized there's no increment for the item itself. */
9194 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
9195 return build_va_arg_indirect_ref (valist_tmp);
9198 if (DEFAULT_ABI != ABI_V4)
9200 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
9202 tree elem_type = TREE_TYPE (type);
9203 enum machine_mode elem_mode = TYPE_MODE (elem_type);
9204 int elem_size = GET_MODE_SIZE (elem_mode);
9206 if (elem_size < UNITS_PER_WORD)
9208 tree real_part, imag_part;
9209 gimple_seq post = NULL;
9211 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9213 /* Copy the value into a temporary, lest the formal temporary
9214 be reused out from under us. */
9215 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
9216 gimple_seq_add_seq (pre_p, post);
9218 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
9221 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
9225 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
9228 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9229 f_fpr = DECL_CHAIN (f_gpr);
9230 f_res = DECL_CHAIN (f_fpr);
9231 f_ovf = DECL_CHAIN (f_res);
9232 f_sav = DECL_CHAIN (f_ovf);
9234 valist = build_va_arg_indirect_ref (valist);
9235 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9236 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
9238 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
9240 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
9243 size = int_size_in_bytes (type);
9244 rsize = (size + 3) / 4;
9247 if (TARGET_HARD_FLOAT && TARGET_FPRS
9248 && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode)
9249 || (TARGET_DOUBLE_FLOAT
9250 && (TYPE_MODE (type) == DFmode
9251 || TYPE_MODE (type) == TFmode
9252 || TYPE_MODE (type) == SDmode
9253 || TYPE_MODE (type) == DDmode
9254 || TYPE_MODE (type) == TDmode))))
9256 /* FP args go in FP registers, if present. */
9258 n_reg = (size + 7) / 8;
9259 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
9260 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
9261 if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
9266 /* Otherwise into GP registers. */
9275 /* Pull the value out of the saved registers.... */
9278 addr = create_tmp_var (ptr_type_node, "addr");
9280 /* AltiVec vectors never go in registers when -mabi=altivec. */
9281 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
9285 lab_false = create_artificial_label (input_location);
9286 lab_over = create_artificial_label (input_location);
9288 /* Long long and SPE vectors are aligned in the registers.
9289 As are any other 2 gpr item such as complex int due to a
9290 historical mistake. */
9292 if (n_reg == 2 && reg == gpr)
9295 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9296 build_int_cst (TREE_TYPE (reg), n_reg - 1));
9297 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
9298 unshare_expr (reg), u);
9300 /* _Decimal128 is passed in even/odd fpr pairs; the stored
9301 reg number is 0 for f1, so we want to make it odd. */
9302 else if (reg == fpr && TYPE_MODE (type) == TDmode)
9304 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9305 build_int_cst (TREE_TYPE (reg), 1));
9306 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
9309 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
9310 t = build2 (GE_EXPR, boolean_type_node, u, t);
9311 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9312 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9313 gimplify_and_add (t, pre_p);
9317 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9319 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
9320 build_int_cst (TREE_TYPE (reg), n_reg));
9321 u = fold_convert (sizetype, u);
9322 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
9323 t = fold_build_pointer_plus (t, u);
9325 /* _Decimal32 varargs are located in the second word of the 64-bit
9326 FP register for 32-bit binaries. */
9327 if (!TARGET_POWERPC64
9328 && TARGET_HARD_FLOAT && TARGET_FPRS
9329 && TYPE_MODE (type) == SDmode)
9330 t = fold_build_pointer_plus_hwi (t, size);
9332 gimplify_assign (addr, t, pre_p);
9334 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9336 stmt = gimple_build_label (lab_false);
9337 gimple_seq_add_stmt (pre_p, stmt);
9339 if ((n_reg == 2 && !regalign) || n_reg > 2)
9341 /* Ensure that we don't find any more args in regs.
9342 Alignment has taken care of for special cases. */
9343 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
9347 /* ... otherwise out of the overflow area. */
9349 /* Care for on-stack alignment if needed. */
9353 t = fold_build_pointer_plus_hwi (t, align - 1);
9354 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
9355 build_int_cst (TREE_TYPE (t), -align));
9357 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9359 gimplify_assign (unshare_expr (addr), t, pre_p);
9361 t = fold_build_pointer_plus_hwi (t, size);
9362 gimplify_assign (unshare_expr (ovf), t, pre_p);
9366 stmt = gimple_build_label (lab_over);
9367 gimple_seq_add_stmt (pre_p, stmt);
9370 if (STRICT_ALIGNMENT
9371 && (TYPE_ALIGN (type)
9372 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
9374 /* The value (of type complex double, for example) may not be
9375 aligned in memory in the saved registers, so copy via a
9376 temporary. (This is the same code as used for SPARC.) */
9377 tree tmp = create_tmp_var (type, "va_arg_tmp");
9378 tree dest_addr = build_fold_addr_expr (tmp);
9380 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
9381 3, dest_addr, addr, size_int (rsize * 4));
9383 gimplify_and_add (copy, pre_p);
9387 addr = fold_convert (ptrtype, addr);
9388 return build_va_arg_indirect_ref (addr);
9394 def_builtin (const char *name, tree type, enum rs6000_builtins code)
9397 unsigned classify = rs6000_builtin_info[(int)code].attr;
9398 const char *attr_string = "";
9400 gcc_assert (name != NULL);
9401 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
9403 if (rs6000_builtin_decls[(int)code])
9404 fatal_error ("internal error: builtin function %s already processed", name);
9406 rs6000_builtin_decls[(int)code] = t =
9407 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
9409 /* Set any special attributes. */
9410 if ((classify & RS6000_BTC_CONST) != 0)
9412 /* const function, function only depends on the inputs. */
9413 TREE_READONLY (t) = 1;
9414 TREE_NOTHROW (t) = 1;
9415 attr_string = ", pure";
9417 else if ((classify & RS6000_BTC_PURE) != 0)
9419 /* pure function, function can read global memory, but does not set any
9421 DECL_PURE_P (t) = 1;
9422 TREE_NOTHROW (t) = 1;
9423 attr_string = ", const";
9425 else if ((classify & RS6000_BTC_FP) != 0)
9427 /* Function is a math function. If rounding mode is on, then treat the
9428 function as not reading global memory, but it can have arbitrary side
9429 effects. If it is off, then assume the function is a const function.
9430 This mimics the ATTR_MATHFN_FPROUNDING attribute in
9431 builtin-attribute.def that is used for the math functions. */
9432 TREE_NOTHROW (t) = 1;
9433 if (flag_rounding_math)
9435 DECL_PURE_P (t) = 1;
9436 DECL_IS_NOVOPS (t) = 1;
9437 attr_string = ", fp, pure";
9441 TREE_READONLY (t) = 1;
9442 attr_string = ", fp, const";
9445 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
9448 if (TARGET_DEBUG_BUILTIN)
9449 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
9450 (int)code, name, attr_string);
9453 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
9455 #undef RS6000_BUILTIN_1
9456 #undef RS6000_BUILTIN_2
9457 #undef RS6000_BUILTIN_3
9458 #undef RS6000_BUILTIN_A
9459 #undef RS6000_BUILTIN_D
9460 #undef RS6000_BUILTIN_E
9461 #undef RS6000_BUILTIN_P
9462 #undef RS6000_BUILTIN_Q
9463 #undef RS6000_BUILTIN_S
9464 #undef RS6000_BUILTIN_X
9466 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9467 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9468 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
9469 { MASK, ICODE, NAME, ENUM },
9471 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9472 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9473 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9474 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9475 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9476 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9477 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9479 static const struct builtin_description bdesc_3arg[] =
9481 #include "rs6000-builtin.def"
9484 /* DST operations: void foo (void *, const int, const char). */
9486 #undef RS6000_BUILTIN_1
9487 #undef RS6000_BUILTIN_2
9488 #undef RS6000_BUILTIN_3
9489 #undef RS6000_BUILTIN_A
9490 #undef RS6000_BUILTIN_D
9491 #undef RS6000_BUILTIN_E
9492 #undef RS6000_BUILTIN_P
9493 #undef RS6000_BUILTIN_Q
9494 #undef RS6000_BUILTIN_S
9495 #undef RS6000_BUILTIN_X
9497 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9498 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9499 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9500 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9501 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
9502 { MASK, ICODE, NAME, ENUM },
9504 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9505 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9506 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9507 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9508 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9510 static const struct builtin_description bdesc_dst[] =
9512 #include "rs6000-builtin.def"
9515 /* Simple binary operations: VECc = foo (VECa, VECb). */
9517 #undef RS6000_BUILTIN_1
9518 #undef RS6000_BUILTIN_2
9519 #undef RS6000_BUILTIN_3
9520 #undef RS6000_BUILTIN_A
9521 #undef RS6000_BUILTIN_D
9522 #undef RS6000_BUILTIN_E
9523 #undef RS6000_BUILTIN_P
9524 #undef RS6000_BUILTIN_Q
9525 #undef RS6000_BUILTIN_S
9526 #undef RS6000_BUILTIN_X
9528 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9529 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
9530 { MASK, ICODE, NAME, ENUM },
9532 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9533 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9534 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9535 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9536 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9537 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9538 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9539 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9541 static const struct builtin_description bdesc_2arg[] =
9543 #include "rs6000-builtin.def"
9546 #undef RS6000_BUILTIN_1
9547 #undef RS6000_BUILTIN_2
9548 #undef RS6000_BUILTIN_3
9549 #undef RS6000_BUILTIN_A
9550 #undef RS6000_BUILTIN_D
9551 #undef RS6000_BUILTIN_E
9552 #undef RS6000_BUILTIN_P
9553 #undef RS6000_BUILTIN_Q
9554 #undef RS6000_BUILTIN_S
9555 #undef RS6000_BUILTIN_X
9557 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9558 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9559 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9560 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9561 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9562 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9563 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
9564 { MASK, ICODE, NAME, ENUM },
9566 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9567 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9568 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9570 /* AltiVec predicates. */
9572 static const struct builtin_description bdesc_altivec_preds[] =
9574 #include "rs6000-builtin.def"
9577 /* SPE predicates. */
9578 #undef RS6000_BUILTIN_1
9579 #undef RS6000_BUILTIN_2
9580 #undef RS6000_BUILTIN_3
9581 #undef RS6000_BUILTIN_A
9582 #undef RS6000_BUILTIN_D
9583 #undef RS6000_BUILTIN_E
9584 #undef RS6000_BUILTIN_P
9585 #undef RS6000_BUILTIN_Q
9586 #undef RS6000_BUILTIN_S
9587 #undef RS6000_BUILTIN_X
9589 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9590 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9591 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9592 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9593 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9594 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9595 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9596 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9597 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
9598 { MASK, ICODE, NAME, ENUM },
9600 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9602 static const struct builtin_description bdesc_spe_predicates[] =
9604 #include "rs6000-builtin.def"
9607 /* SPE evsel predicates. */
9608 #undef RS6000_BUILTIN_1
9609 #undef RS6000_BUILTIN_2
9610 #undef RS6000_BUILTIN_3
9611 #undef RS6000_BUILTIN_A
9612 #undef RS6000_BUILTIN_D
9613 #undef RS6000_BUILTIN_E
9614 #undef RS6000_BUILTIN_P
9615 #undef RS6000_BUILTIN_Q
9616 #undef RS6000_BUILTIN_S
9617 #undef RS6000_BUILTIN_X
9619 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9620 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9621 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9622 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9623 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9624 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
9625 { MASK, ICODE, NAME, ENUM },
9627 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9628 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9629 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9630 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9632 static const struct builtin_description bdesc_spe_evsel[] =
9634 #include "rs6000-builtin.def"
9637 /* PAIRED predicates. */
9638 #undef RS6000_BUILTIN_1
9639 #undef RS6000_BUILTIN_2
9640 #undef RS6000_BUILTIN_3
9641 #undef RS6000_BUILTIN_A
9642 #undef RS6000_BUILTIN_D
9643 #undef RS6000_BUILTIN_E
9644 #undef RS6000_BUILTIN_P
9645 #undef RS6000_BUILTIN_Q
9646 #undef RS6000_BUILTIN_S
9647 #undef RS6000_BUILTIN_X
9649 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9650 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9651 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9652 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9653 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9654 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9655 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9656 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
9657 { MASK, ICODE, NAME, ENUM },
9659 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9660 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9662 static const struct builtin_description bdesc_paired_preds[] =
9664 #include "rs6000-builtin.def"
9667 /* ABS* operations. */
9669 #undef RS6000_BUILTIN_1
9670 #undef RS6000_BUILTIN_2
9671 #undef RS6000_BUILTIN_3
9672 #undef RS6000_BUILTIN_A
9673 #undef RS6000_BUILTIN_D
9674 #undef RS6000_BUILTIN_E
9675 #undef RS6000_BUILTIN_P
9676 #undef RS6000_BUILTIN_Q
9677 #undef RS6000_BUILTIN_S
9678 #undef RS6000_BUILTIN_X
9680 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
9681 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9682 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9683 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
9684 { MASK, ICODE, NAME, ENUM },
9686 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9687 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9688 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9689 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9690 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9691 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9693 static const struct builtin_description bdesc_abs[] =
9695 #include "rs6000-builtin.def"
9698 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
9701 #undef RS6000_BUILTIN_1
9702 #undef RS6000_BUILTIN_2
9703 #undef RS6000_BUILTIN_3
9704 #undef RS6000_BUILTIN_A
9705 #undef RS6000_BUILTIN_E
9706 #undef RS6000_BUILTIN_D
9707 #undef RS6000_BUILTIN_P
9708 #undef RS6000_BUILTIN_Q
9709 #undef RS6000_BUILTIN_S
9710 #undef RS6000_BUILTIN_X
9712 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
9713 { MASK, ICODE, NAME, ENUM },
9715 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
9716 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
9717 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
9718 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
9719 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
9720 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
9721 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
9722 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
9723 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
9725 static const struct builtin_description bdesc_1arg[] =
9727 #include "rs6000-builtin.def"
9730 #undef RS6000_BUILTIN_1
9731 #undef RS6000_BUILTIN_2
9732 #undef RS6000_BUILTIN_3
9733 #undef RS6000_BUILTIN_A
9734 #undef RS6000_BUILTIN_D
9735 #undef RS6000_BUILTIN_E
9736 #undef RS6000_BUILTIN_P
9737 #undef RS6000_BUILTIN_Q
9738 #undef RS6000_BUILTIN_S
9739 #undef RS6000_BUILTIN_X
9741 /* Return true if a builtin function is overloaded. */
9743 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
9745 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
9750 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
9753 tree arg0 = CALL_EXPR_ARG (exp, 0);
9754 rtx op0 = expand_normal (arg0);
9755 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9756 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9758 if (icode == CODE_FOR_nothing)
9759 /* Builtin not supported on this processor. */
9762 /* If we got invalid arguments bail out before generating bad rtl. */
9763 if (arg0 == error_mark_node)
9766 if (icode == CODE_FOR_altivec_vspltisb
9767 || icode == CODE_FOR_altivec_vspltish
9768 || icode == CODE_FOR_altivec_vspltisw
9769 || icode == CODE_FOR_spe_evsplatfi
9770 || icode == CODE_FOR_spe_evsplati)
9772 /* Only allow 5-bit *signed* literals. */
9773 if (GET_CODE (op0) != CONST_INT
9774 || INTVAL (op0) > 15
9775 || INTVAL (op0) < -16)
9777 error ("argument 1 must be a 5-bit signed literal");
9783 || GET_MODE (target) != tmode
9784 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9785 target = gen_reg_rtx (tmode);
9787 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9788 op0 = copy_to_mode_reg (mode0, op0);
9790 pat = GEN_FCN (icode) (target, op0);
9799 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
9801 rtx pat, scratch1, scratch2;
9802 tree arg0 = CALL_EXPR_ARG (exp, 0);
9803 rtx op0 = expand_normal (arg0);
9804 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9805 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9807 /* If we have invalid arguments, bail out before generating bad rtl. */
9808 if (arg0 == error_mark_node)
9812 || GET_MODE (target) != tmode
9813 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9814 target = gen_reg_rtx (tmode);
9816 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9817 op0 = copy_to_mode_reg (mode0, op0);
9819 scratch1 = gen_reg_rtx (mode0);
9820 scratch2 = gen_reg_rtx (mode0);
9822 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
9831 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
9834 tree arg0 = CALL_EXPR_ARG (exp, 0);
9835 tree arg1 = CALL_EXPR_ARG (exp, 1);
9836 rtx op0 = expand_normal (arg0);
9837 rtx op1 = expand_normal (arg1);
9838 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9839 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9840 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9842 if (icode == CODE_FOR_nothing)
9843 /* Builtin not supported on this processor. */
9846 /* If we got invalid arguments bail out before generating bad rtl. */
9847 if (arg0 == error_mark_node || arg1 == error_mark_node)
9850 if (icode == CODE_FOR_altivec_vcfux
9851 || icode == CODE_FOR_altivec_vcfsx
9852 || icode == CODE_FOR_altivec_vctsxs
9853 || icode == CODE_FOR_altivec_vctuxs
9854 || icode == CODE_FOR_altivec_vspltb
9855 || icode == CODE_FOR_altivec_vsplth
9856 || icode == CODE_FOR_altivec_vspltw
9857 || icode == CODE_FOR_spe_evaddiw
9858 || icode == CODE_FOR_spe_evldd
9859 || icode == CODE_FOR_spe_evldh
9860 || icode == CODE_FOR_spe_evldw
9861 || icode == CODE_FOR_spe_evlhhesplat
9862 || icode == CODE_FOR_spe_evlhhossplat
9863 || icode == CODE_FOR_spe_evlhhousplat
9864 || icode == CODE_FOR_spe_evlwhe
9865 || icode == CODE_FOR_spe_evlwhos
9866 || icode == CODE_FOR_spe_evlwhou
9867 || icode == CODE_FOR_spe_evlwhsplat
9868 || icode == CODE_FOR_spe_evlwwsplat
9869 || icode == CODE_FOR_spe_evrlwi
9870 || icode == CODE_FOR_spe_evslwi
9871 || icode == CODE_FOR_spe_evsrwis
9872 || icode == CODE_FOR_spe_evsubifw
9873 || icode == CODE_FOR_spe_evsrwiu)
9875 /* Only allow 5-bit unsigned literals. */
9877 if (TREE_CODE (arg1) != INTEGER_CST
9878 || TREE_INT_CST_LOW (arg1) & ~0x1f)
9880 error ("argument 2 must be a 5-bit unsigned literal");
9886 || GET_MODE (target) != tmode
9887 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9888 target = gen_reg_rtx (tmode);
9890 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9891 op0 = copy_to_mode_reg (mode0, op0);
9892 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9893 op1 = copy_to_mode_reg (mode1, op1);
9895 pat = GEN_FCN (icode) (target, op0, op1);
9904 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
9907 tree cr6_form = CALL_EXPR_ARG (exp, 0);
9908 tree arg0 = CALL_EXPR_ARG (exp, 1);
9909 tree arg1 = CALL_EXPR_ARG (exp, 2);
9910 rtx op0 = expand_normal (arg0);
9911 rtx op1 = expand_normal (arg1);
9912 enum machine_mode tmode = SImode;
9913 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
9914 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
9917 if (TREE_CODE (cr6_form) != INTEGER_CST)
9919 error ("argument 1 of __builtin_altivec_predicate must be a constant");
9923 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
9925 gcc_assert (mode0 == mode1);
9927 /* If we have invalid arguments, bail out before generating bad rtl. */
9928 if (arg0 == error_mark_node || arg1 == error_mark_node)
9932 || GET_MODE (target) != tmode
9933 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
9934 target = gen_reg_rtx (tmode);
9936 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
9937 op0 = copy_to_mode_reg (mode0, op0);
9938 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
9939 op1 = copy_to_mode_reg (mode1, op1);
9941 scratch = gen_reg_rtx (mode0);
9943 pat = GEN_FCN (icode) (scratch, op0, op1);
9948 /* The vec_any* and vec_all* predicates use the same opcodes for two
9949 different operations, but the bits in CR6 will be different
9950 depending on what information we want. So we have to play tricks
9951 with CR6 to get the right bits out.
9953 If you think this is disgusting, look at the specs for the
9954 AltiVec predicates. */
9956 switch (cr6_form_int)
9959 emit_insn (gen_cr6_test_for_zero (target));
9962 emit_insn (gen_cr6_test_for_zero_reverse (target));
9965 emit_insn (gen_cr6_test_for_lt (target));
9968 emit_insn (gen_cr6_test_for_lt_reverse (target));
9971 error ("argument 1 of __builtin_altivec_predicate is out of range");
9979 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
9982 tree arg0 = CALL_EXPR_ARG (exp, 0);
9983 tree arg1 = CALL_EXPR_ARG (exp, 1);
9984 enum machine_mode tmode = insn_data[icode].operand[0].mode;
9985 enum machine_mode mode0 = Pmode;
9986 enum machine_mode mode1 = Pmode;
9987 rtx op0 = expand_normal (arg0);
9988 rtx op1 = expand_normal (arg1);
9990 if (icode == CODE_FOR_nothing)
9991 /* Builtin not supported on this processor. */
9994 /* If we got invalid arguments bail out before generating bad rtl. */
9995 if (arg0 == error_mark_node || arg1 == error_mark_node)
9999 || GET_MODE (target) != tmode
10000 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10001 target = gen_reg_rtx (tmode);
10003 op1 = copy_to_mode_reg (mode1, op1);
10005 if (op0 == const0_rtx)
10007 addr = gen_rtx_MEM (tmode, op1);
10011 op0 = copy_to_mode_reg (mode0, op0);
10012 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
10015 pat = GEN_FCN (icode) (target, addr);
10025 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
10028 tree arg0 = CALL_EXPR_ARG (exp, 0);
10029 tree arg1 = CALL_EXPR_ARG (exp, 1);
10030 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10031 enum machine_mode mode0 = Pmode;
10032 enum machine_mode mode1 = Pmode;
10033 rtx op0 = expand_normal (arg0);
10034 rtx op1 = expand_normal (arg1);
10036 if (icode == CODE_FOR_nothing)
10037 /* Builtin not supported on this processor. */
10040 /* If we got invalid arguments bail out before generating bad rtl. */
10041 if (arg0 == error_mark_node || arg1 == error_mark_node)
10045 || GET_MODE (target) != tmode
10046 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10047 target = gen_reg_rtx (tmode);
10049 op1 = copy_to_mode_reg (mode1, op1);
10051 if (op0 == const0_rtx)
10053 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
10057 op0 = copy_to_mode_reg (mode0, op0);
10058 addr = gen_rtx_MEM (blk ? BLKmode : tmode, gen_rtx_PLUS (Pmode, op0, op1));
10061 pat = GEN_FCN (icode) (target, addr);
10071 spe_expand_stv_builtin (enum insn_code icode, tree exp)
10073 tree arg0 = CALL_EXPR_ARG (exp, 0);
10074 tree arg1 = CALL_EXPR_ARG (exp, 1);
10075 tree arg2 = CALL_EXPR_ARG (exp, 2);
10076 rtx op0 = expand_normal (arg0);
10077 rtx op1 = expand_normal (arg1);
10078 rtx op2 = expand_normal (arg2);
10080 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
10081 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
10082 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
10084 /* Invalid arguments. Bail before doing anything stoopid! */
10085 if (arg0 == error_mark_node
10086 || arg1 == error_mark_node
10087 || arg2 == error_mark_node)
10090 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
10091 op0 = copy_to_mode_reg (mode2, op0);
10092 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
10093 op1 = copy_to_mode_reg (mode0, op1);
10094 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
10095 op2 = copy_to_mode_reg (mode1, op2);
10097 pat = GEN_FCN (icode) (op1, op2, op0);
10104 paired_expand_stv_builtin (enum insn_code icode, tree exp)
10106 tree arg0 = CALL_EXPR_ARG (exp, 0);
10107 tree arg1 = CALL_EXPR_ARG (exp, 1);
10108 tree arg2 = CALL_EXPR_ARG (exp, 2);
10109 rtx op0 = expand_normal (arg0);
10110 rtx op1 = expand_normal (arg1);
10111 rtx op2 = expand_normal (arg2);
10113 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10114 enum machine_mode mode1 = Pmode;
10115 enum machine_mode mode2 = Pmode;
10117 /* Invalid arguments. Bail before doing anything stoopid! */
10118 if (arg0 == error_mark_node
10119 || arg1 == error_mark_node
10120 || arg2 == error_mark_node)
10123 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
10124 op0 = copy_to_mode_reg (tmode, op0);
10126 op2 = copy_to_mode_reg (mode2, op2);
10128 if (op1 == const0_rtx)
10130 addr = gen_rtx_MEM (tmode, op2);
10134 op1 = copy_to_mode_reg (mode1, op1);
10135 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10138 pat = GEN_FCN (icode) (addr, op0);
10145 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
10147 tree arg0 = CALL_EXPR_ARG (exp, 0);
10148 tree arg1 = CALL_EXPR_ARG (exp, 1);
10149 tree arg2 = CALL_EXPR_ARG (exp, 2);
10150 rtx op0 = expand_normal (arg0);
10151 rtx op1 = expand_normal (arg1);
10152 rtx op2 = expand_normal (arg2);
10154 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10155 enum machine_mode smode = insn_data[icode].operand[1].mode;
10156 enum machine_mode mode1 = Pmode;
10157 enum machine_mode mode2 = Pmode;
10159 /* Invalid arguments. Bail before doing anything stoopid! */
10160 if (arg0 == error_mark_node
10161 || arg1 == error_mark_node
10162 || arg2 == error_mark_node)
10165 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
10166 op0 = copy_to_mode_reg (smode, op0);
10168 op2 = copy_to_mode_reg (mode2, op2);
10170 if (op1 == const0_rtx)
10172 addr = gen_rtx_MEM (tmode, op2);
10176 op1 = copy_to_mode_reg (mode1, op1);
10177 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
10180 pat = GEN_FCN (icode) (addr, op0);
10187 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
10190 tree arg0 = CALL_EXPR_ARG (exp, 0);
10191 tree arg1 = CALL_EXPR_ARG (exp, 1);
10192 tree arg2 = CALL_EXPR_ARG (exp, 2);
10193 rtx op0 = expand_normal (arg0);
10194 rtx op1 = expand_normal (arg1);
10195 rtx op2 = expand_normal (arg2);
10196 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10197 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
10198 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
10199 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
10201 if (icode == CODE_FOR_nothing)
10202 /* Builtin not supported on this processor. */
10205 /* If we got invalid arguments bail out before generating bad rtl. */
10206 if (arg0 == error_mark_node
10207 || arg1 == error_mark_node
10208 || arg2 == error_mark_node)
10211 /* Check and prepare argument depending on the instruction code.
10213 Note that a switch statement instead of the sequence of tests
10214 would be incorrect as many of the CODE_FOR values could be
10215 CODE_FOR_nothing and that would yield multiple alternatives
10216 with identical values. We'd never reach here at runtime in
10218 if (icode == CODE_FOR_altivec_vsldoi_v4sf
10219 || icode == CODE_FOR_altivec_vsldoi_v4si
10220 || icode == CODE_FOR_altivec_vsldoi_v8hi
10221 || icode == CODE_FOR_altivec_vsldoi_v16qi)
10223 /* Only allow 4-bit unsigned literals. */
10225 if (TREE_CODE (arg2) != INTEGER_CST
10226 || TREE_INT_CST_LOW (arg2) & ~0xf)
10228 error ("argument 3 must be a 4-bit unsigned literal");
10232 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
10233 || icode == CODE_FOR_vsx_xxpermdi_v2di
10234 || icode == CODE_FOR_vsx_xxsldwi_v16qi
10235 || icode == CODE_FOR_vsx_xxsldwi_v8hi
10236 || icode == CODE_FOR_vsx_xxsldwi_v4si
10237 || icode == CODE_FOR_vsx_xxsldwi_v4sf
10238 || icode == CODE_FOR_vsx_xxsldwi_v2di
10239 || icode == CODE_FOR_vsx_xxsldwi_v2df)
10241 /* Only allow 2-bit unsigned literals. */
10243 if (TREE_CODE (arg2) != INTEGER_CST
10244 || TREE_INT_CST_LOW (arg2) & ~0x3)
10246 error ("argument 3 must be a 2-bit unsigned literal");
10250 else if (icode == CODE_FOR_vsx_set_v2df
10251 || icode == CODE_FOR_vsx_set_v2di)
10253 /* Only allow 1-bit unsigned literals. */
10255 if (TREE_CODE (arg2) != INTEGER_CST
10256 || TREE_INT_CST_LOW (arg2) & ~0x1)
10258 error ("argument 3 must be a 1-bit unsigned literal");
10264 || GET_MODE (target) != tmode
10265 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10266 target = gen_reg_rtx (tmode);
10268 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10269 op0 = copy_to_mode_reg (mode0, op0);
10270 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
10271 op1 = copy_to_mode_reg (mode1, op1);
10272 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
10273 op2 = copy_to_mode_reg (mode2, op2);
10275 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
10276 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
10278 pat = GEN_FCN (icode) (target, op0, op1, op2);
10286 /* Expand the lvx builtins. */
10288 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
10290 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10291 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10293 enum machine_mode tmode, mode0;
10295 enum insn_code icode;
10299 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
10300 icode = CODE_FOR_vector_altivec_load_v16qi;
10302 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
10303 icode = CODE_FOR_vector_altivec_load_v8hi;
10305 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
10306 icode = CODE_FOR_vector_altivec_load_v4si;
10308 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
10309 icode = CODE_FOR_vector_altivec_load_v4sf;
10311 case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
10312 icode = CODE_FOR_vector_altivec_load_v2df;
10314 case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
10315 icode = CODE_FOR_vector_altivec_load_v2di;
10318 *expandedp = false;
10324 arg0 = CALL_EXPR_ARG (exp, 0);
10325 op0 = expand_normal (arg0);
10326 tmode = insn_data[icode].operand[0].mode;
10327 mode0 = insn_data[icode].operand[1].mode;
10330 || GET_MODE (target) != tmode
10331 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10332 target = gen_reg_rtx (tmode);
10334 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
10335 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10337 pat = GEN_FCN (icode) (target, op0);
10344 /* Expand the stvx builtins. */
10346 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10349 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10350 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10352 enum machine_mode mode0, mode1;
10354 enum insn_code icode;
10358 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
10359 icode = CODE_FOR_vector_altivec_store_v16qi;
10361 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
10362 icode = CODE_FOR_vector_altivec_store_v8hi;
10364 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
10365 icode = CODE_FOR_vector_altivec_store_v4si;
10367 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
10368 icode = CODE_FOR_vector_altivec_store_v4sf;
10370 case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
10371 icode = CODE_FOR_vector_altivec_store_v2df;
10373 case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
10374 icode = CODE_FOR_vector_altivec_store_v2di;
10377 *expandedp = false;
10381 arg0 = CALL_EXPR_ARG (exp, 0);
10382 arg1 = CALL_EXPR_ARG (exp, 1);
10383 op0 = expand_normal (arg0);
10384 op1 = expand_normal (arg1);
10385 mode0 = insn_data[icode].operand[0].mode;
10386 mode1 = insn_data[icode].operand[1].mode;
10388 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10389 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
10390 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
10391 op1 = copy_to_mode_reg (mode1, op1);
10393 pat = GEN_FCN (icode) (op0, op1);
10401 /* Expand the dst builtins. */
10403 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
10406 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10407 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10408 tree arg0, arg1, arg2;
10409 enum machine_mode mode0, mode1;
10410 rtx pat, op0, op1, op2;
10411 const struct builtin_description *d;
10414 *expandedp = false;
10416 /* Handle DST variants. */
10418 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
10419 if (d->code == fcode)
10421 arg0 = CALL_EXPR_ARG (exp, 0);
10422 arg1 = CALL_EXPR_ARG (exp, 1);
10423 arg2 = CALL_EXPR_ARG (exp, 2);
10424 op0 = expand_normal (arg0);
10425 op1 = expand_normal (arg1);
10426 op2 = expand_normal (arg2);
10427 mode0 = insn_data[d->icode].operand[0].mode;
10428 mode1 = insn_data[d->icode].operand[1].mode;
10430 /* Invalid arguments, bail out before generating bad rtl. */
10431 if (arg0 == error_mark_node
10432 || arg1 == error_mark_node
10433 || arg2 == error_mark_node)
10438 if (TREE_CODE (arg2) != INTEGER_CST
10439 || TREE_INT_CST_LOW (arg2) & ~0x3)
10441 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
10445 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
10446 op0 = copy_to_mode_reg (Pmode, op0);
10447 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
10448 op1 = copy_to_mode_reg (mode1, op1);
10450 pat = GEN_FCN (d->icode) (op0, op1, op2);
10460 /* Expand vec_init builtin. */
10462 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
10464 enum machine_mode tmode = TYPE_MODE (type);
10465 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
10466 int i, n_elt = GET_MODE_NUNITS (tmode);
10467 rtvec v = rtvec_alloc (n_elt);
10469 gcc_assert (VECTOR_MODE_P (tmode));
10470 gcc_assert (n_elt == call_expr_nargs (exp));
10472 for (i = 0; i < n_elt; ++i)
10474 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
10475 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
10478 if (!target || !register_operand (target, tmode))
10479 target = gen_reg_rtx (tmode);
10481 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
10485 /* Return the integer constant in ARG. Constrain it to be in the range
10486 of the subparts of VEC_TYPE; issue an error if not. */
10489 get_element_number (tree vec_type, tree arg)
10491 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
10493 if (!host_integerp (arg, 1)
10494 || (elt = tree_low_cst (arg, 1), elt > max))
10496 error ("selector must be an integer constant in the range 0..%wi", max);
10503 /* Expand vec_set builtin. */
10505 altivec_expand_vec_set_builtin (tree exp)
10507 enum machine_mode tmode, mode1;
10508 tree arg0, arg1, arg2;
10512 arg0 = CALL_EXPR_ARG (exp, 0);
10513 arg1 = CALL_EXPR_ARG (exp, 1);
10514 arg2 = CALL_EXPR_ARG (exp, 2);
10516 tmode = TYPE_MODE (TREE_TYPE (arg0));
10517 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10518 gcc_assert (VECTOR_MODE_P (tmode));
10520 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
10521 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
10522 elt = get_element_number (TREE_TYPE (arg0), arg2);
10524 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
10525 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
10527 op0 = force_reg (tmode, op0);
10528 op1 = force_reg (mode1, op1);
10530 rs6000_expand_vector_set (op0, op1, elt);
10535 /* Expand vec_ext builtin. */
10537 altivec_expand_vec_ext_builtin (tree exp, rtx target)
10539 enum machine_mode tmode, mode0;
10544 arg0 = CALL_EXPR_ARG (exp, 0);
10545 arg1 = CALL_EXPR_ARG (exp, 1);
10547 op0 = expand_normal (arg0);
10548 elt = get_element_number (TREE_TYPE (arg0), arg1);
10550 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
10551 mode0 = TYPE_MODE (TREE_TYPE (arg0));
10552 gcc_assert (VECTOR_MODE_P (mode0));
10554 op0 = force_reg (mode0, op0);
10556 if (optimize || !target || !register_operand (target, tmode))
10557 target = gen_reg_rtx (tmode);
10559 rs6000_expand_vector_extract (target, op0, elt);
10564 /* Expand the builtin in EXP and store the result in TARGET. Store
10565 true in *EXPANDEDP if we found a builtin to expand. */
10567 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
10569 const struct builtin_description *d;
10571 enum insn_code icode;
10572 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10575 enum machine_mode tmode, mode0;
10576 enum rs6000_builtins fcode
10577 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
10579 if (rs6000_overloaded_builtin_p (fcode))
10582 error ("unresolved overload for Altivec builtin %qF", fndecl);
10584 /* Given it is invalid, just generate a normal call. */
10585 return expand_call (exp, target, false);
10588 target = altivec_expand_ld_builtin (exp, target, expandedp);
10592 target = altivec_expand_st_builtin (exp, target, expandedp);
10596 target = altivec_expand_dst_builtin (exp, target, expandedp);
10604 case ALTIVEC_BUILTIN_STVX:
10605 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
10606 case ALTIVEC_BUILTIN_STVEBX:
10607 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
10608 case ALTIVEC_BUILTIN_STVEHX:
10609 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
10610 case ALTIVEC_BUILTIN_STVEWX:
10611 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
10612 case ALTIVEC_BUILTIN_STVXL:
10613 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
10615 case ALTIVEC_BUILTIN_STVLX:
10616 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
10617 case ALTIVEC_BUILTIN_STVLXL:
10618 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
10619 case ALTIVEC_BUILTIN_STVRX:
10620 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
10621 case ALTIVEC_BUILTIN_STVRXL:
10622 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
10624 case VSX_BUILTIN_STXVD2X_V2DF:
10625 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
10626 case VSX_BUILTIN_STXVD2X_V2DI:
10627 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
10628 case VSX_BUILTIN_STXVW4X_V4SF:
10629 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
10630 case VSX_BUILTIN_STXVW4X_V4SI:
10631 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
10632 case VSX_BUILTIN_STXVW4X_V8HI:
10633 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
10634 case VSX_BUILTIN_STXVW4X_V16QI:
10635 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
10637 case ALTIVEC_BUILTIN_MFVSCR:
10638 icode = CODE_FOR_altivec_mfvscr;
10639 tmode = insn_data[icode].operand[0].mode;
10642 || GET_MODE (target) != tmode
10643 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10644 target = gen_reg_rtx (tmode);
10646 pat = GEN_FCN (icode) (target);
10652 case ALTIVEC_BUILTIN_MTVSCR:
10653 icode = CODE_FOR_altivec_mtvscr;
10654 arg0 = CALL_EXPR_ARG (exp, 0);
10655 op0 = expand_normal (arg0);
10656 mode0 = insn_data[icode].operand[0].mode;
10658 /* If we got invalid arguments bail out before generating bad rtl. */
10659 if (arg0 == error_mark_node)
10662 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10663 op0 = copy_to_mode_reg (mode0, op0);
10665 pat = GEN_FCN (icode) (op0);
10670 case ALTIVEC_BUILTIN_DSSALL:
10671 emit_insn (gen_altivec_dssall ());
10674 case ALTIVEC_BUILTIN_DSS:
10675 icode = CODE_FOR_altivec_dss;
10676 arg0 = CALL_EXPR_ARG (exp, 0);
10678 op0 = expand_normal (arg0);
10679 mode0 = insn_data[icode].operand[0].mode;
10681 /* If we got invalid arguments bail out before generating bad rtl. */
10682 if (arg0 == error_mark_node)
10685 if (TREE_CODE (arg0) != INTEGER_CST
10686 || TREE_INT_CST_LOW (arg0) & ~0x3)
10688 error ("argument to dss must be a 2-bit unsigned literal");
10692 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10693 op0 = copy_to_mode_reg (mode0, op0);
10695 emit_insn (gen_altivec_dss (op0));
10698 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
10699 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
10700 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
10701 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
10702 case VSX_BUILTIN_VEC_INIT_V2DF:
10703 case VSX_BUILTIN_VEC_INIT_V2DI:
10704 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
10706 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
10707 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
10708 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
10709 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
10710 case VSX_BUILTIN_VEC_SET_V2DF:
10711 case VSX_BUILTIN_VEC_SET_V2DI:
10712 return altivec_expand_vec_set_builtin (exp);
10714 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
10715 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
10716 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
10717 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
10718 case VSX_BUILTIN_VEC_EXT_V2DF:
10719 case VSX_BUILTIN_VEC_EXT_V2DI:
10720 return altivec_expand_vec_ext_builtin (exp, target);
10724 /* Fall through. */
10727 /* Expand abs* operations. */
10729 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
10730 if (d->code == fcode)
10731 return altivec_expand_abs_builtin (d->icode, exp, target);
10733 /* Expand the AltiVec predicates. */
10734 d = bdesc_altivec_preds;
10735 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
10736 if (d->code == fcode)
10737 return altivec_expand_predicate_builtin (d->icode, exp, target);
10739 /* LV* are funky. We initialized them differently. */
10742 case ALTIVEC_BUILTIN_LVSL:
10743 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
10744 exp, target, false);
10745 case ALTIVEC_BUILTIN_LVSR:
10746 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
10747 exp, target, false);
10748 case ALTIVEC_BUILTIN_LVEBX:
10749 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
10750 exp, target, false);
10751 case ALTIVEC_BUILTIN_LVEHX:
10752 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
10753 exp, target, false);
10754 case ALTIVEC_BUILTIN_LVEWX:
10755 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
10756 exp, target, false);
10757 case ALTIVEC_BUILTIN_LVXL:
10758 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
10759 exp, target, false);
10760 case ALTIVEC_BUILTIN_LVX:
10761 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
10762 exp, target, false);
10763 case ALTIVEC_BUILTIN_LVLX:
10764 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
10765 exp, target, true);
10766 case ALTIVEC_BUILTIN_LVLXL:
10767 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
10768 exp, target, true);
10769 case ALTIVEC_BUILTIN_LVRX:
10770 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
10771 exp, target, true);
10772 case ALTIVEC_BUILTIN_LVRXL:
10773 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
10774 exp, target, true);
10775 case VSX_BUILTIN_LXVD2X_V2DF:
10776 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
10777 exp, target, false);
10778 case VSX_BUILTIN_LXVD2X_V2DI:
10779 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
10780 exp, target, false);
10781 case VSX_BUILTIN_LXVW4X_V4SF:
10782 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
10783 exp, target, false);
10784 case VSX_BUILTIN_LXVW4X_V4SI:
10785 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
10786 exp, target, false);
10787 case VSX_BUILTIN_LXVW4X_V8HI:
10788 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
10789 exp, target, false);
10790 case VSX_BUILTIN_LXVW4X_V16QI:
10791 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
10792 exp, target, false);
10796 /* Fall through. */
10799 *expandedp = false;
10803 /* Expand the builtin in EXP and store the result in TARGET. Store
10804 true in *EXPANDEDP if we found a builtin to expand. */
10806 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
10808 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10809 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10810 const struct builtin_description *d;
10817 case PAIRED_BUILTIN_STX:
10818 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
10819 case PAIRED_BUILTIN_LX:
10820 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
10823 /* Fall through. */
10826 /* Expand the paired predicates. */
10827 d = bdesc_paired_preds;
10828 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
10829 if (d->code == fcode)
10830 return paired_expand_predicate_builtin (d->icode, exp, target);
10832 *expandedp = false;
10836 /* Binops that need to be initialized manually, but can be expanded
10837 automagically by rs6000_expand_binop_builtin. */
10838 static const struct builtin_description bdesc_2arg_spe[] =
10840 { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
10841 { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
10842 { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
10843 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
10844 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
10845 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
10846 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
10847 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
10848 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
10849 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
10850 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
10851 { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
10852 { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
10853 { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
10854 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
10855 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
10856 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
10857 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
10858 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
10859 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
10860 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
10861 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
10864 /* Expand the builtin in EXP and store the result in TARGET. Store
10865 true in *EXPANDEDP if we found a builtin to expand.
10867 This expands the SPE builtins that are not simple unary and binary
10870 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
10872 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10874 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10875 enum insn_code icode;
10876 enum machine_mode tmode, mode0;
10878 const struct builtin_description *d;
10883 /* Syntax check for a 5-bit unsigned immediate. */
10886 case SPE_BUILTIN_EVSTDD:
10887 case SPE_BUILTIN_EVSTDH:
10888 case SPE_BUILTIN_EVSTDW:
10889 case SPE_BUILTIN_EVSTWHE:
10890 case SPE_BUILTIN_EVSTWHO:
10891 case SPE_BUILTIN_EVSTWWE:
10892 case SPE_BUILTIN_EVSTWWO:
10893 arg1 = CALL_EXPR_ARG (exp, 2);
10894 if (TREE_CODE (arg1) != INTEGER_CST
10895 || TREE_INT_CST_LOW (arg1) & ~0x1f)
10897 error ("argument 2 must be a 5-bit unsigned literal");
10905 /* The evsplat*i instructions are not quite generic. */
10908 case SPE_BUILTIN_EVSPLATFI:
10909 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
10911 case SPE_BUILTIN_EVSPLATI:
10912 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
10918 d = bdesc_2arg_spe;
10919 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
10920 if (d->code == fcode)
10921 return rs6000_expand_binop_builtin (d->icode, exp, target);
10923 d = bdesc_spe_predicates;
10924 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
10925 if (d->code == fcode)
10926 return spe_expand_predicate_builtin (d->icode, exp, target);
10928 d = bdesc_spe_evsel;
10929 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
10930 if (d->code == fcode)
10931 return spe_expand_evsel_builtin (d->icode, exp, target);
10935 case SPE_BUILTIN_EVSTDDX:
10936 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
10937 case SPE_BUILTIN_EVSTDHX:
10938 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
10939 case SPE_BUILTIN_EVSTDWX:
10940 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
10941 case SPE_BUILTIN_EVSTWHEX:
10942 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
10943 case SPE_BUILTIN_EVSTWHOX:
10944 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
10945 case SPE_BUILTIN_EVSTWWEX:
10946 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
10947 case SPE_BUILTIN_EVSTWWOX:
10948 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
10949 case SPE_BUILTIN_EVSTDD:
10950 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
10951 case SPE_BUILTIN_EVSTDH:
10952 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
10953 case SPE_BUILTIN_EVSTDW:
10954 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
10955 case SPE_BUILTIN_EVSTWHE:
10956 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
10957 case SPE_BUILTIN_EVSTWHO:
10958 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
10959 case SPE_BUILTIN_EVSTWWE:
10960 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
10961 case SPE_BUILTIN_EVSTWWO:
10962 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
10963 case SPE_BUILTIN_MFSPEFSCR:
10964 icode = CODE_FOR_spe_mfspefscr;
10965 tmode = insn_data[icode].operand[0].mode;
10968 || GET_MODE (target) != tmode
10969 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10970 target = gen_reg_rtx (tmode);
10972 pat = GEN_FCN (icode) (target);
10977 case SPE_BUILTIN_MTSPEFSCR:
10978 icode = CODE_FOR_spe_mtspefscr;
10979 arg0 = CALL_EXPR_ARG (exp, 0);
10980 op0 = expand_normal (arg0);
10981 mode0 = insn_data[icode].operand[0].mode;
10983 if (arg0 == error_mark_node)
10986 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
10987 op0 = copy_to_mode_reg (mode0, op0);
10989 pat = GEN_FCN (icode) (op0);
10997 *expandedp = false;
11002 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
11004 rtx pat, scratch, tmp;
11005 tree form = CALL_EXPR_ARG (exp, 0);
11006 tree arg0 = CALL_EXPR_ARG (exp, 1);
11007 tree arg1 = CALL_EXPR_ARG (exp, 2);
11008 rtx op0 = expand_normal (arg0);
11009 rtx op1 = expand_normal (arg1);
11010 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11011 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11013 enum rtx_code code;
11015 if (TREE_CODE (form) != INTEGER_CST)
11017 error ("argument 1 of __builtin_paired_predicate must be a constant");
11021 form_int = TREE_INT_CST_LOW (form);
11023 gcc_assert (mode0 == mode1);
11025 if (arg0 == error_mark_node || arg1 == error_mark_node)
11029 || GET_MODE (target) != SImode
11030 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
11031 target = gen_reg_rtx (SImode);
11032 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
11033 op0 = copy_to_mode_reg (mode0, op0);
11034 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
11035 op1 = copy_to_mode_reg (mode1, op1);
11037 scratch = gen_reg_rtx (CCFPmode);
11039 pat = GEN_FCN (icode) (scratch, op0, op1);
11061 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
11064 error ("argument 1 of __builtin_paired_predicate is out of range");
11068 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
11069 emit_move_insn (target, tmp);
11074 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
11076 rtx pat, scratch, tmp;
11077 tree form = CALL_EXPR_ARG (exp, 0);
11078 tree arg0 = CALL_EXPR_ARG (exp, 1);
11079 tree arg1 = CALL_EXPR_ARG (exp, 2);
11080 rtx op0 = expand_normal (arg0);
11081 rtx op1 = expand_normal (arg1);
11082 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11083 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11085 enum rtx_code code;
11087 if (TREE_CODE (form) != INTEGER_CST)
11089 error ("argument 1 of __builtin_spe_predicate must be a constant");
11093 form_int = TREE_INT_CST_LOW (form);
11095 gcc_assert (mode0 == mode1);
11097 if (arg0 == error_mark_node || arg1 == error_mark_node)
11101 || GET_MODE (target) != SImode
11102 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
11103 target = gen_reg_rtx (SImode);
11105 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11106 op0 = copy_to_mode_reg (mode0, op0);
11107 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
11108 op1 = copy_to_mode_reg (mode1, op1);
11110 scratch = gen_reg_rtx (CCmode);
11112 pat = GEN_FCN (icode) (scratch, op0, op1);
11117 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
11118 _lower_. We use one compare, but look in different bits of the
11119 CR for each variant.
11121 There are 2 elements in each SPE simd type (upper/lower). The CR
11122 bits are set as follows:
11124 BIT0 | BIT 1 | BIT 2 | BIT 3
11125 U | L | (U | L) | (U & L)
11127 So, for an "all" relationship, BIT 3 would be set.
11128 For an "any" relationship, BIT 2 would be set. Etc.
11130 Following traditional nomenclature, these bits map to:
11132 BIT0 | BIT 1 | BIT 2 | BIT 3
11135 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
11140 /* All variant. OV bit. */
11142 /* We need to get to the OV bit, which is the ORDERED bit. We
11143 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
11144 that's ugly and will make validate_condition_mode die.
11145 So let's just use another pattern. */
11146 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
11148 /* Any variant. EQ bit. */
11152 /* Upper variant. LT bit. */
11156 /* Lower variant. GT bit. */
11161 error ("argument 1 of __builtin_spe_predicate is out of range");
11165 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
11166 emit_move_insn (target, tmp);
11171 /* The evsel builtins look like this:
11173 e = __builtin_spe_evsel_OP (a, b, c, d);
11175 and work like this:
11177 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
11178 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
11182 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
11185 tree arg0 = CALL_EXPR_ARG (exp, 0);
11186 tree arg1 = CALL_EXPR_ARG (exp, 1);
11187 tree arg2 = CALL_EXPR_ARG (exp, 2);
11188 tree arg3 = CALL_EXPR_ARG (exp, 3);
11189 rtx op0 = expand_normal (arg0);
11190 rtx op1 = expand_normal (arg1);
11191 rtx op2 = expand_normal (arg2);
11192 rtx op3 = expand_normal (arg3);
11193 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
11194 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
11196 gcc_assert (mode0 == mode1);
11198 if (arg0 == error_mark_node || arg1 == error_mark_node
11199 || arg2 == error_mark_node || arg3 == error_mark_node)
11203 || GET_MODE (target) != mode0
11204 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
11205 target = gen_reg_rtx (mode0);
11207 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
11208 op0 = copy_to_mode_reg (mode0, op0);
11209 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
11210 op1 = copy_to_mode_reg (mode0, op1);
11211 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
11212 op2 = copy_to_mode_reg (mode0, op2);
11213 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
11214 op3 = copy_to_mode_reg (mode0, op3);
11216 /* Generate the compare. */
11217 scratch = gen_reg_rtx (CCmode);
11218 pat = GEN_FCN (icode) (scratch, op0, op1);
11223 if (mode0 == V2SImode)
11224 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
11226 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
11231 /* Raise an error message for a builtin function that is called without the
11232 appropriate target options being set. */
11235 rs6000_invalid_builtin (enum rs6000_builtins fncode)
11237 size_t uns_fncode = (size_t)fncode;
11238 const char *name = rs6000_builtin_info[uns_fncode].name;
11239 unsigned fnmask = rs6000_builtin_info[uns_fncode].mask;
11241 gcc_assert (name != NULL);
11242 if ((fnmask & RS6000_BTM_CELL) != 0)
11243 error ("Builtin function %s is only valid for the cell processor", name);
11244 else if ((fnmask & RS6000_BTM_VSX) != 0)
11245 error ("Builtin function %s requires the -mvsx option", name);
11246 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
11247 error ("Builtin function %s requires the -maltivec option", name);
11248 else if ((fnmask & RS6000_BTM_PAIRED) != 0)
11249 error ("Builtin function %s requires the -mpaired option", name);
11250 else if ((fnmask & RS6000_BTM_SPE) != 0)
11251 error ("Builtin function %s requires the -mspe option", name);
11253 error ("Builtin function %s is not supported with the current options",
11257 /* Expand an expression EXP that calls a built-in function,
11258 with result going to TARGET if that's convenient
11259 (and in mode MODE if that's convenient).
11260 SUBTARGET may be used as the target for computing one of EXP's operands.
11261 IGNORE is nonzero if the value is to be ignored. */
11264 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
11265 enum machine_mode mode ATTRIBUTE_UNUSED,
11266 int ignore ATTRIBUTE_UNUSED)
11268 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
11269 enum rs6000_builtins fcode
11270 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
11271 size_t uns_fcode = (size_t)fcode;
11272 const struct builtin_description *d;
11276 unsigned mask = rs6000_builtin_info[uns_fcode].mask;
11277 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
11279 if (TARGET_DEBUG_BUILTIN)
11281 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
11282 const char *name1 = rs6000_builtin_info[uns_fcode].name;
11283 const char *name2 = ((icode != CODE_FOR_nothing)
11284 ? get_insn_name ((int)icode)
11288 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
11290 default: name3 = "unknown"; break;
11291 case RS6000_BTC_SPECIAL: name3 = "special"; break;
11292 case RS6000_BTC_UNARY: name3 = "unary"; break;
11293 case RS6000_BTC_BINARY: name3 = "binary"; break;
11294 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
11295 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
11296 case RS6000_BTC_ABS: name3 = "abs"; break;
11297 case RS6000_BTC_EVSEL: name3 = "evsel"; break;
11298 case RS6000_BTC_DST: name3 = "dst"; break;
11303 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
11304 (name1) ? name1 : "---", fcode,
11305 (name2) ? name2 : "---", (int)icode,
11307 func_valid_p ? "" : ", not valid");
11312 rs6000_invalid_builtin (fcode);
11314 /* Given it is invalid, just generate a normal call. */
11315 return expand_call (exp, target, ignore);
11320 case RS6000_BUILTIN_RECIP:
11321 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
11323 case RS6000_BUILTIN_RECIPF:
11324 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
11326 case RS6000_BUILTIN_RSQRTF:
11327 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
11329 case RS6000_BUILTIN_RSQRT:
11330 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
11332 case RS6000_BUILTIN_BSWAP_HI:
11333 return rs6000_expand_unop_builtin (CODE_FOR_bswaphi2, exp, target);
11335 case POWER7_BUILTIN_BPERMD:
11336 return rs6000_expand_binop_builtin (((TARGET_64BIT)
11337 ? CODE_FOR_bpermd_di
11338 : CODE_FOR_bpermd_si), exp, target);
11340 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
11341 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
11343 int icode = (int) CODE_FOR_altivec_lvsr;
11344 enum machine_mode tmode = insn_data[icode].operand[0].mode;
11345 enum machine_mode mode = insn_data[icode].operand[1].mode;
11349 gcc_assert (TARGET_ALTIVEC);
11351 arg = CALL_EXPR_ARG (exp, 0);
11352 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
11353 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
11354 addr = memory_address (mode, op);
11355 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
11359 /* For the load case need to negate the address. */
11360 op = gen_reg_rtx (GET_MODE (addr));
11361 emit_insn (gen_rtx_SET (VOIDmode, op,
11362 gen_rtx_NEG (GET_MODE (addr), addr)));
11364 op = gen_rtx_MEM (mode, op);
11367 || GET_MODE (target) != tmode
11368 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11369 target = gen_reg_rtx (tmode);
11371 /*pat = gen_altivec_lvsr (target, op);*/
11372 pat = GEN_FCN (icode) (target, op);
11380 case ALTIVEC_BUILTIN_VCFUX:
11381 case ALTIVEC_BUILTIN_VCFSX:
11382 case ALTIVEC_BUILTIN_VCTUXS:
11383 case ALTIVEC_BUILTIN_VCTSXS:
11384 /* FIXME: There's got to be a nicer way to handle this case than
11385 constructing a new CALL_EXPR. */
11386 if (call_expr_nargs (exp) == 1)
11388 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
11389 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
11397 if (TARGET_ALTIVEC)
11399 ret = altivec_expand_builtin (exp, target, &success);
11406 ret = spe_expand_builtin (exp, target, &success);
11411 if (TARGET_PAIRED_FLOAT)
11413 ret = paired_expand_builtin (exp, target, &success);
11419 gcc_assert (TARGET_ALTIVEC || TARGET_VSX || TARGET_SPE || TARGET_PAIRED_FLOAT);
11421 /* Handle simple unary operations. */
11423 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
11424 if (d->code == fcode)
11425 return rs6000_expand_unop_builtin (d->icode, exp, target);
11427 /* Handle simple binary operations. */
11429 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
11430 if (d->code == fcode)
11431 return rs6000_expand_binop_builtin (d->icode, exp, target);
11433 /* Handle simple ternary operations. */
11435 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
11436 if (d->code == fcode)
11437 return rs6000_expand_ternop_builtin (d->icode, exp, target);
11439 gcc_unreachable ();
11443 rs6000_init_builtins (void)
11447 enum machine_mode mode;
11449 if (TARGET_DEBUG_BUILTIN)
11450 fprintf (stderr, "rs6000_init_builtins%s%s%s%s\n",
11451 (TARGET_PAIRED_FLOAT) ? ", paired" : "",
11452 (TARGET_SPE) ? ", spe" : "",
11453 (TARGET_ALTIVEC) ? ", altivec" : "",
11454 (TARGET_VSX) ? ", vsx" : "");
11456 V2SI_type_node = build_vector_type (intSI_type_node, 2);
11457 V2SF_type_node = build_vector_type (float_type_node, 2);
11458 V2DI_type_node = build_vector_type (intDI_type_node, 2);
11459 V2DF_type_node = build_vector_type (double_type_node, 2);
11460 V4HI_type_node = build_vector_type (intHI_type_node, 4);
11461 V4SI_type_node = build_vector_type (intSI_type_node, 4);
11462 V4SF_type_node = build_vector_type (float_type_node, 4);
11463 V8HI_type_node = build_vector_type (intHI_type_node, 8);
11464 V16QI_type_node = build_vector_type (intQI_type_node, 16);
11466 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
11467 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
11468 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
11469 unsigned_V2DI_type_node = build_vector_type (unsigned_intDI_type_node, 2);
11471 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
11472 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
11473 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
11474 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
11476 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
11477 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
11478 'vector unsigned short'. */
11480 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
11481 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11482 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
11483 bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
11484 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
11486 long_integer_type_internal_node = long_integer_type_node;
11487 long_unsigned_type_internal_node = long_unsigned_type_node;
11488 long_long_integer_type_internal_node = long_long_integer_type_node;
11489 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
11490 intQI_type_internal_node = intQI_type_node;
11491 uintQI_type_internal_node = unsigned_intQI_type_node;
11492 intHI_type_internal_node = intHI_type_node;
11493 uintHI_type_internal_node = unsigned_intHI_type_node;
11494 intSI_type_internal_node = intSI_type_node;
11495 uintSI_type_internal_node = unsigned_intSI_type_node;
11496 intDI_type_internal_node = intDI_type_node;
11497 uintDI_type_internal_node = unsigned_intDI_type_node;
11498 float_type_internal_node = float_type_node;
11499 double_type_internal_node = double_type_node;
11500 void_type_internal_node = void_type_node;
11502 /* Initialize the modes for builtin_function_type, mapping a machine mode to
11504 builtin_mode_to_type[QImode][0] = integer_type_node;
11505 builtin_mode_to_type[HImode][0] = integer_type_node;
11506 builtin_mode_to_type[SImode][0] = intSI_type_node;
11507 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
11508 builtin_mode_to_type[DImode][0] = intDI_type_node;
11509 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
11510 builtin_mode_to_type[SFmode][0] = float_type_node;
11511 builtin_mode_to_type[DFmode][0] = double_type_node;
11512 builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
11513 builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
11514 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
11515 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
11516 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
11517 builtin_mode_to_type[V4HImode][0] = V4HI_type_node;
11518 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
11519 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
11520 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
11521 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
11522 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
11523 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
11524 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
11526 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11527 get_identifier ("__bool char"),
11528 bool_char_type_node);
11529 TYPE_NAME (bool_char_type_node) = tdecl;
11530 (*lang_hooks.decls.pushdecl) (tdecl);
11531 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11532 get_identifier ("__bool short"),
11533 bool_short_type_node);
11534 TYPE_NAME (bool_short_type_node) = tdecl;
11535 (*lang_hooks.decls.pushdecl) (tdecl);
11536 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11537 get_identifier ("__bool int"),
11538 bool_int_type_node);
11539 TYPE_NAME (bool_int_type_node) = tdecl;
11540 (*lang_hooks.decls.pushdecl) (tdecl);
11541 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL, get_identifier ("__pixel"),
11543 TYPE_NAME (pixel_type_node) = tdecl;
11544 (*lang_hooks.decls.pushdecl) (tdecl);
11546 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
11547 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
11548 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
11549 bool_V2DI_type_node = build_vector_type (bool_long_type_node, 2);
11550 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
11552 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11553 get_identifier ("__vector unsigned char"),
11554 unsigned_V16QI_type_node);
11555 TYPE_NAME (unsigned_V16QI_type_node) = tdecl;
11556 (*lang_hooks.decls.pushdecl) (tdecl);
11557 tdecl = build_decl (BUILTINS_LOCATION,
11558 TYPE_DECL, get_identifier ("__vector signed char"),
11560 TYPE_NAME (V16QI_type_node) = tdecl;
11561 (*lang_hooks.decls.pushdecl) (tdecl);
11562 tdecl = build_decl (BUILTINS_LOCATION,
11563 TYPE_DECL, get_identifier ("__vector __bool char"),
11564 bool_V16QI_type_node);
11565 TYPE_NAME ( bool_V16QI_type_node) = tdecl;
11566 (*lang_hooks.decls.pushdecl) (tdecl);
11568 tdecl = build_decl (BUILTINS_LOCATION,
11569 TYPE_DECL, get_identifier ("__vector unsigned short"),
11570 unsigned_V8HI_type_node);
11571 TYPE_NAME (unsigned_V8HI_type_node) = tdecl;
11572 (*lang_hooks.decls.pushdecl) (tdecl);
11573 tdecl = build_decl (BUILTINS_LOCATION,
11574 TYPE_DECL, get_identifier ("__vector signed short"),
11576 TYPE_NAME (V8HI_type_node) = tdecl;
11577 (*lang_hooks.decls.pushdecl) (tdecl);
11578 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11579 get_identifier ("__vector __bool short"),
11580 bool_V8HI_type_node);
11581 TYPE_NAME (bool_V8HI_type_node) = tdecl;
11582 (*lang_hooks.decls.pushdecl) (tdecl);
11584 tdecl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11585 get_identifier ("__vector unsigned int"),
11586 unsigned_V4SI_type_node);
11587 TYPE_NAME (unsigned_V4SI_type_node) = tdecl;
11588 (*lang_hooks.decls.pushdecl) (tdecl);
11589 tdecl = build_decl (BUILTINS_LOCATION,
11590 TYPE_DECL, get_identifier ("__vector signed int"),
11592 TYPE_NAME (V4SI_type_node) = tdecl;
11593 (*lang_hooks.decls.pushdecl) (tdecl);
11594 tdecl = build_decl (BUILTINS_LOCATION,
11595 TYPE_DECL, get_identifier ("__vector __bool int"),
11596 bool_V4SI_type_node);
11597 TYPE_NAME (bool_V4SI_type_node) = tdecl;
11598 (*lang_hooks.decls.pushdecl) (tdecl);
11600 tdecl = build_decl (BUILTINS_LOCATION,
11601 TYPE_DECL, get_identifier ("__vector float"),
11603 TYPE_NAME (V4SF_type_node) = tdecl;
11604 (*lang_hooks.decls.pushdecl) (tdecl);
11605 tdecl = build_decl (BUILTINS_LOCATION,
11606 TYPE_DECL, get_identifier ("__vector __pixel"),
11607 pixel_V8HI_type_node);
11608 TYPE_NAME (pixel_V8HI_type_node) = tdecl;
11609 (*lang_hooks.decls.pushdecl) (tdecl);
11611 tdecl = build_decl (BUILTINS_LOCATION,
11612 TYPE_DECL, get_identifier ("__vector double"),
11614 TYPE_NAME (V2DF_type_node) = tdecl;
11615 (*lang_hooks.decls.pushdecl) (tdecl);
11617 tdecl = build_decl (BUILTINS_LOCATION,
11618 TYPE_DECL, get_identifier ("__vector long"),
11620 TYPE_NAME (V2DI_type_node) = tdecl;
11621 (*lang_hooks.decls.pushdecl) (tdecl);
11623 tdecl = build_decl (BUILTINS_LOCATION,
11624 TYPE_DECL, get_identifier ("__vector unsigned long"),
11625 unsigned_V2DI_type_node);
11626 TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
11627 (*lang_hooks.decls.pushdecl) (tdecl);
11629 tdecl = build_decl (BUILTINS_LOCATION,
11630 TYPE_DECL, get_identifier ("__vector __bool long"),
11631 bool_V2DI_type_node);
11632 TYPE_NAME (bool_V2DI_type_node) = tdecl;
11633 (*lang_hooks.decls.pushdecl) (tdecl);
11635 /* Paired and SPE builtins are only available if you build a compiler with
11636 the appropriate options, so only create those builtins with the
11637 appropriate compiler option. Create Altivec and VSX builtins on machines
11638 with at least the general purpose extensions (970 and newer) to allow the
11639 use of the target attribute. */
11640 if (TARGET_PAIRED_FLOAT)
11641 paired_init_builtins ();
11643 spe_init_builtins ();
11644 if (TARGET_EXTRA_BUILTINS)
11645 altivec_init_builtins ();
11646 if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
11647 rs6000_common_init_builtins ();
11649 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
11650 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
11651 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
11653 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
11654 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
11655 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
11657 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
11658 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
11659 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
11661 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
11662 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
11663 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
11665 mode = (TARGET_64BIT) ? DImode : SImode;
11666 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
11667 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
11668 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
11670 /* Don't use builtin_function_type here, as it maps HI/QI to SI. */
11671 ftype = build_function_type_list (unsigned_intHI_type_node,
11672 unsigned_intHI_type_node,
11674 def_builtin ("__builtin_bswap16", ftype, RS6000_BUILTIN_BSWAP_HI);
11677 /* AIX libm provides clog as __clog. */
11678 if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
11679 set_user_assembler_name (tdecl, "__clog");
11682 #ifdef SUBTARGET_INIT_BUILTINS
11683 SUBTARGET_INIT_BUILTINS;
11687 /* Returns the rs6000 builtin decl for CODE. */
11690 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
11694 if (code >= RS6000_BUILTIN_COUNT)
11695 return error_mark_node;
11697 fnmask = rs6000_builtin_info[code].mask;
11698 if ((fnmask & rs6000_builtin_mask) != fnmask)
11700 rs6000_invalid_builtin ((enum rs6000_builtins)code);
11701 return error_mark_node;
11704 return rs6000_builtin_decls[code];
11708 spe_init_builtins (void)
11710 tree puint_type_node = build_pointer_type (unsigned_type_node);
11711 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
11712 const struct builtin_description *d;
11715 tree v2si_ftype_4_v2si
11716 = build_function_type_list (opaque_V2SI_type_node,
11717 opaque_V2SI_type_node,
11718 opaque_V2SI_type_node,
11719 opaque_V2SI_type_node,
11720 opaque_V2SI_type_node,
11723 tree v2sf_ftype_4_v2sf
11724 = build_function_type_list (opaque_V2SF_type_node,
11725 opaque_V2SF_type_node,
11726 opaque_V2SF_type_node,
11727 opaque_V2SF_type_node,
11728 opaque_V2SF_type_node,
11731 tree int_ftype_int_v2si_v2si
11732 = build_function_type_list (integer_type_node,
11734 opaque_V2SI_type_node,
11735 opaque_V2SI_type_node,
11738 tree int_ftype_int_v2sf_v2sf
11739 = build_function_type_list (integer_type_node,
11741 opaque_V2SF_type_node,
11742 opaque_V2SF_type_node,
11745 tree void_ftype_v2si_puint_int
11746 = build_function_type_list (void_type_node,
11747 opaque_V2SI_type_node,
11752 tree void_ftype_v2si_puint_char
11753 = build_function_type_list (void_type_node,
11754 opaque_V2SI_type_node,
11759 tree void_ftype_v2si_pv2si_int
11760 = build_function_type_list (void_type_node,
11761 opaque_V2SI_type_node,
11762 opaque_p_V2SI_type_node,
11766 tree void_ftype_v2si_pv2si_char
11767 = build_function_type_list (void_type_node,
11768 opaque_V2SI_type_node,
11769 opaque_p_V2SI_type_node,
11773 tree void_ftype_int
11774 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
11776 tree int_ftype_void
11777 = build_function_type_list (integer_type_node, NULL_TREE);
11779 tree v2si_ftype_pv2si_int
11780 = build_function_type_list (opaque_V2SI_type_node,
11781 opaque_p_V2SI_type_node,
11785 tree v2si_ftype_puint_int
11786 = build_function_type_list (opaque_V2SI_type_node,
11791 tree v2si_ftype_pushort_int
11792 = build_function_type_list (opaque_V2SI_type_node,
11797 tree v2si_ftype_signed_char
11798 = build_function_type_list (opaque_V2SI_type_node,
11799 signed_char_type_node,
11802 (*lang_hooks.decls.pushdecl)
11803 (build_decl (BUILTINS_LOCATION, TYPE_DECL,
11804 get_identifier ("__ev64_opaque__"),
11805 opaque_V2SI_type_node));
11807 /* Initialize irregular SPE builtins. */
11809 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
11810 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
11811 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
11812 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
11813 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
11814 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
11815 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
11816 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
11817 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
11818 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
11819 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
11820 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
11821 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
11822 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
11823 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
11824 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
11825 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
11826 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
11829 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
11830 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
11831 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
11832 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
11833 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
11834 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
11835 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
11836 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
11837 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
11838 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
11839 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
11840 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
11841 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
11842 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
11843 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
11844 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
11845 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
11846 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
11847 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
11848 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
11849 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
11850 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
11853 d = bdesc_spe_predicates;
11854 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
11858 switch (insn_data[d->icode].operand[1].mode)
11861 type = int_ftype_int_v2si_v2si;
11864 type = int_ftype_int_v2sf_v2sf;
11867 gcc_unreachable ();
11870 def_builtin (d->name, type, d->code);
11873 /* Evsel predicates. */
11874 d = bdesc_spe_evsel;
11875 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
11879 switch (insn_data[d->icode].operand[1].mode)
11882 type = v2si_ftype_4_v2si;
11885 type = v2sf_ftype_4_v2sf;
11888 gcc_unreachable ();
11891 def_builtin (d->name, type, d->code);
11896 paired_init_builtins (void)
11898 const struct builtin_description *d;
11901 tree int_ftype_int_v2sf_v2sf
11902 = build_function_type_list (integer_type_node,
11907 tree pcfloat_type_node =
11908 build_pointer_type (build_qualified_type
11909 (float_type_node, TYPE_QUAL_CONST));
11911 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
11912 long_integer_type_node,
11915 tree void_ftype_v2sf_long_pcfloat =
11916 build_function_type_list (void_type_node,
11918 long_integer_type_node,
11923 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
11924 PAIRED_BUILTIN_LX);
11927 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
11928 PAIRED_BUILTIN_STX);
11931 d = bdesc_paired_preds;
11932 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
11936 if (TARGET_DEBUG_BUILTIN)
11937 fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
11938 (int)i, get_insn_name (d->icode), (int)d->icode,
11939 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
11941 switch (insn_data[d->icode].operand[1].mode)
11944 type = int_ftype_int_v2sf_v2sf;
11947 gcc_unreachable ();
11950 def_builtin (d->name, type, d->code);
11955 altivec_init_builtins (void)
11957 const struct builtin_description *d;
11962 tree pvoid_type_node = build_pointer_type (void_type_node);
11964 tree pcvoid_type_node
11965 = build_pointer_type (build_qualified_type (void_type_node,
11968 tree int_ftype_opaque
11969 = build_function_type_list (integer_type_node,
11970 opaque_V4SI_type_node, NULL_TREE);
11971 tree opaque_ftype_opaque
11972 = build_function_type_list (integer_type_node, NULL_TREE);
11973 tree opaque_ftype_opaque_int
11974 = build_function_type_list (opaque_V4SI_type_node,
11975 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
11976 tree opaque_ftype_opaque_opaque_int
11977 = build_function_type_list (opaque_V4SI_type_node,
11978 opaque_V4SI_type_node, opaque_V4SI_type_node,
11979 integer_type_node, NULL_TREE);
11980 tree int_ftype_int_opaque_opaque
11981 = build_function_type_list (integer_type_node,
11982 integer_type_node, opaque_V4SI_type_node,
11983 opaque_V4SI_type_node, NULL_TREE);
11984 tree int_ftype_int_v4si_v4si
11985 = build_function_type_list (integer_type_node,
11986 integer_type_node, V4SI_type_node,
11987 V4SI_type_node, NULL_TREE);
11988 tree void_ftype_v4si
11989 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
11990 tree v8hi_ftype_void
11991 = build_function_type_list (V8HI_type_node, NULL_TREE);
11992 tree void_ftype_void
11993 = build_function_type_list (void_type_node, NULL_TREE);
11994 tree void_ftype_int
11995 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
11997 tree opaque_ftype_long_pcvoid
11998 = build_function_type_list (opaque_V4SI_type_node,
11999 long_integer_type_node, pcvoid_type_node,
12001 tree v16qi_ftype_long_pcvoid
12002 = build_function_type_list (V16QI_type_node,
12003 long_integer_type_node, pcvoid_type_node,
12005 tree v8hi_ftype_long_pcvoid
12006 = build_function_type_list (V8HI_type_node,
12007 long_integer_type_node, pcvoid_type_node,
12009 tree v4si_ftype_long_pcvoid
12010 = build_function_type_list (V4SI_type_node,
12011 long_integer_type_node, pcvoid_type_node,
12013 tree v4sf_ftype_long_pcvoid
12014 = build_function_type_list (V4SF_type_node,
12015 long_integer_type_node, pcvoid_type_node,
12017 tree v2df_ftype_long_pcvoid
12018 = build_function_type_list (V2DF_type_node,
12019 long_integer_type_node, pcvoid_type_node,
12021 tree v2di_ftype_long_pcvoid
12022 = build_function_type_list (V2DI_type_node,
12023 long_integer_type_node, pcvoid_type_node,
12026 tree void_ftype_opaque_long_pvoid
12027 = build_function_type_list (void_type_node,
12028 opaque_V4SI_type_node, long_integer_type_node,
12029 pvoid_type_node, NULL_TREE);
12030 tree void_ftype_v4si_long_pvoid
12031 = build_function_type_list (void_type_node,
12032 V4SI_type_node, long_integer_type_node,
12033 pvoid_type_node, NULL_TREE);
12034 tree void_ftype_v16qi_long_pvoid
12035 = build_function_type_list (void_type_node,
12036 V16QI_type_node, long_integer_type_node,
12037 pvoid_type_node, NULL_TREE);
12038 tree void_ftype_v8hi_long_pvoid
12039 = build_function_type_list (void_type_node,
12040 V8HI_type_node, long_integer_type_node,
12041 pvoid_type_node, NULL_TREE);
12042 tree void_ftype_v4sf_long_pvoid
12043 = build_function_type_list (void_type_node,
12044 V4SF_type_node, long_integer_type_node,
12045 pvoid_type_node, NULL_TREE);
12046 tree void_ftype_v2df_long_pvoid
12047 = build_function_type_list (void_type_node,
12048 V2DF_type_node, long_integer_type_node,
12049 pvoid_type_node, NULL_TREE);
12050 tree void_ftype_v2di_long_pvoid
12051 = build_function_type_list (void_type_node,
12052 V2DI_type_node, long_integer_type_node,
12053 pvoid_type_node, NULL_TREE);
12054 tree int_ftype_int_v8hi_v8hi
12055 = build_function_type_list (integer_type_node,
12056 integer_type_node, V8HI_type_node,
12057 V8HI_type_node, NULL_TREE);
12058 tree int_ftype_int_v16qi_v16qi
12059 = build_function_type_list (integer_type_node,
12060 integer_type_node, V16QI_type_node,
12061 V16QI_type_node, NULL_TREE);
12062 tree int_ftype_int_v4sf_v4sf
12063 = build_function_type_list (integer_type_node,
12064 integer_type_node, V4SF_type_node,
12065 V4SF_type_node, NULL_TREE);
12066 tree int_ftype_int_v2df_v2df
12067 = build_function_type_list (integer_type_node,
12068 integer_type_node, V2DF_type_node,
12069 V2DF_type_node, NULL_TREE);
12070 tree v4si_ftype_v4si
12071 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
12072 tree v8hi_ftype_v8hi
12073 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
12074 tree v16qi_ftype_v16qi
12075 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
12076 tree v4sf_ftype_v4sf
12077 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
12078 tree v2df_ftype_v2df
12079 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
12080 tree void_ftype_pcvoid_int_int
12081 = build_function_type_list (void_type_node,
12082 pcvoid_type_node, integer_type_node,
12083 integer_type_node, NULL_TREE);
12085 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
12086 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
12087 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
12088 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
12089 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
12090 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
12091 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
12092 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
12093 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
12094 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
12095 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
12096 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
12097 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
12098 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
12099 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
12100 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
12101 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
12102 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
12103 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
12104 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
12105 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
12106 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
12107 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
12108 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
12109 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
12110 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
12111 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
12112 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
12113 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
12114 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
12116 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
12117 VSX_BUILTIN_LXVD2X_V2DF);
12118 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
12119 VSX_BUILTIN_LXVD2X_V2DI);
12120 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
12121 VSX_BUILTIN_LXVW4X_V4SF);
12122 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
12123 VSX_BUILTIN_LXVW4X_V4SI);
12124 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
12125 VSX_BUILTIN_LXVW4X_V8HI);
12126 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
12127 VSX_BUILTIN_LXVW4X_V16QI);
12128 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
12129 VSX_BUILTIN_STXVD2X_V2DF);
12130 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
12131 VSX_BUILTIN_STXVD2X_V2DI);
12132 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
12133 VSX_BUILTIN_STXVW4X_V4SF);
12134 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
12135 VSX_BUILTIN_STXVW4X_V4SI);
12136 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
12137 VSX_BUILTIN_STXVW4X_V8HI);
12138 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
12139 VSX_BUILTIN_STXVW4X_V16QI);
12140 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
12141 VSX_BUILTIN_VEC_LD);
12142 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
12143 VSX_BUILTIN_VEC_ST);
12145 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
12146 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
12147 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
12149 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
12150 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
12151 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
12152 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
12153 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
12154 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
12155 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
12156 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
12157 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
12158 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
12159 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
12160 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
12162 /* Cell builtins. */
12163 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
12164 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
12165 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
12166 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
12168 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
12169 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
12170 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
12171 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
12173 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
12174 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
12175 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
12176 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
12178 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
12179 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
12180 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
12181 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
12183 /* Add the DST variants. */
12185 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
12186 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
12188 /* Initialize the predicates. */
12189 d = bdesc_altivec_preds;
12190 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
12192 enum machine_mode mode1;
12195 if (rs6000_overloaded_builtin_p (d->code))
12198 mode1 = insn_data[d->icode].operand[1].mode;
12203 type = int_ftype_int_opaque_opaque;
12206 type = int_ftype_int_v4si_v4si;
12209 type = int_ftype_int_v8hi_v8hi;
12212 type = int_ftype_int_v16qi_v16qi;
12215 type = int_ftype_int_v4sf_v4sf;
12218 type = int_ftype_int_v2df_v2df;
12221 gcc_unreachable ();
12224 def_builtin (d->name, type, d->code);
12227 /* Initialize the abs* operators. */
12229 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
12231 enum machine_mode mode0;
12234 mode0 = insn_data[d->icode].operand[0].mode;
12239 type = v4si_ftype_v4si;
12242 type = v8hi_ftype_v8hi;
12245 type = v16qi_ftype_v16qi;
12248 type = v4sf_ftype_v4sf;
12251 type = v2df_ftype_v2df;
12254 gcc_unreachable ();
12257 def_builtin (d->name, type, d->code);
12260 /* Initialize target builtin that implements
12261 targetm.vectorize.builtin_mask_for_load. */
12263 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
12264 v16qi_ftype_long_pcvoid,
12265 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
12266 BUILT_IN_MD, NULL, NULL_TREE);
12267 TREE_READONLY (decl) = 1;
12268 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
12269 altivec_builtin_mask_for_load = decl;
12271 /* Access to the vec_init patterns. */
12272 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
12273 integer_type_node, integer_type_node,
12274 integer_type_node, NULL_TREE);
12275 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
12277 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
12278 short_integer_type_node,
12279 short_integer_type_node,
12280 short_integer_type_node,
12281 short_integer_type_node,
12282 short_integer_type_node,
12283 short_integer_type_node,
12284 short_integer_type_node, NULL_TREE);
12285 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
12287 ftype = build_function_type_list (V16QI_type_node, char_type_node,
12288 char_type_node, char_type_node,
12289 char_type_node, char_type_node,
12290 char_type_node, char_type_node,
12291 char_type_node, char_type_node,
12292 char_type_node, char_type_node,
12293 char_type_node, char_type_node,
12294 char_type_node, char_type_node,
12295 char_type_node, NULL_TREE);
12296 def_builtin ("__builtin_vec_init_v16qi", ftype,
12297 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
12299 ftype = build_function_type_list (V4SF_type_node, float_type_node,
12300 float_type_node, float_type_node,
12301 float_type_node, NULL_TREE);
12302 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
12304 /* VSX builtins. */
12305 ftype = build_function_type_list (V2DF_type_node, double_type_node,
12306 double_type_node, NULL_TREE);
12307 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
12309 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
12310 intDI_type_node, NULL_TREE);
12311 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
12313 /* Access to the vec_set patterns. */
12314 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
12316 integer_type_node, NULL_TREE);
12317 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
12319 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
12321 integer_type_node, NULL_TREE);
12322 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
12324 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
12326 integer_type_node, NULL_TREE);
12327 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
12329 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
12331 integer_type_node, NULL_TREE);
12332 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
12334 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
12336 integer_type_node, NULL_TREE);
12337 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
12339 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
12341 integer_type_node, NULL_TREE);
12342 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
12344 /* Access to the vec_extract patterns. */
12345 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
12346 integer_type_node, NULL_TREE);
12347 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
12349 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
12350 integer_type_node, NULL_TREE);
12351 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
12353 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
12354 integer_type_node, NULL_TREE);
12355 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
12357 ftype = build_function_type_list (float_type_node, V4SF_type_node,
12358 integer_type_node, NULL_TREE);
12359 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
12361 ftype = build_function_type_list (double_type_node, V2DF_type_node,
12362 integer_type_node, NULL_TREE);
12363 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
12365 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
12366 integer_type_node, NULL_TREE);
12367 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
12370 /* Hash function for builtin functions with up to 3 arguments and a return
12373 builtin_hash_function (const void *hash_entry)
12377 const struct builtin_hash_struct *bh =
12378 (const struct builtin_hash_struct *) hash_entry;
12380 for (i = 0; i < 4; i++)
12382 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
12383 ret = (ret * 2) + bh->uns_p[i];
12389 /* Compare builtin hash entries H1 and H2 for equivalence. */
12391 builtin_hash_eq (const void *h1, const void *h2)
12393 const struct builtin_hash_struct *p1 = (const struct builtin_hash_struct *) h1;
12394 const struct builtin_hash_struct *p2 = (const struct builtin_hash_struct *) h2;
12396 return ((p1->mode[0] == p2->mode[0])
12397 && (p1->mode[1] == p2->mode[1])
12398 && (p1->mode[2] == p2->mode[2])
12399 && (p1->mode[3] == p2->mode[3])
12400 && (p1->uns_p[0] == p2->uns_p[0])
12401 && (p1->uns_p[1] == p2->uns_p[1])
12402 && (p1->uns_p[2] == p2->uns_p[2])
12403 && (p1->uns_p[3] == p2->uns_p[3]));
12406 /* Map types for builtin functions with an explicit return type and up to 3
12407 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
12408 of the argument. */
12410 builtin_function_type (enum machine_mode mode_ret, enum machine_mode mode_arg0,
12411 enum machine_mode mode_arg1, enum machine_mode mode_arg2,
12412 enum rs6000_builtins builtin, const char *name)
12414 struct builtin_hash_struct h;
12415 struct builtin_hash_struct *h2;
12419 tree ret_type = NULL_TREE;
12420 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
12422 /* Create builtin_hash_table. */
12423 if (builtin_hash_table == NULL)
12424 builtin_hash_table = htab_create_ggc (1500, builtin_hash_function,
12425 builtin_hash_eq, NULL);
12427 h.type = NULL_TREE;
12428 h.mode[0] = mode_ret;
12429 h.mode[1] = mode_arg0;
12430 h.mode[2] = mode_arg1;
12431 h.mode[3] = mode_arg2;
12437 /* If the builtin is a type that produces unsigned results or takes unsigned
12438 arguments, and it is returned as a decl for the vectorizer (such as
12439 widening multiplies, permute), make sure the arguments and return value
12440 are type correct. */
12443 /* unsigned 2 argument functions. */
12444 case ALTIVEC_BUILTIN_VMULEUB_UNS:
12445 case ALTIVEC_BUILTIN_VMULEUH_UNS:
12446 case ALTIVEC_BUILTIN_VMULOUB_UNS:
12447 case ALTIVEC_BUILTIN_VMULOUH_UNS:
12453 /* unsigned 3 argument functions. */
12454 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
12455 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
12456 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
12457 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
12458 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
12459 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
12460 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
12461 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
12462 case VSX_BUILTIN_VPERM_16QI_UNS:
12463 case VSX_BUILTIN_VPERM_8HI_UNS:
12464 case VSX_BUILTIN_VPERM_4SI_UNS:
12465 case VSX_BUILTIN_VPERM_2DI_UNS:
12466 case VSX_BUILTIN_XXSEL_16QI_UNS:
12467 case VSX_BUILTIN_XXSEL_8HI_UNS:
12468 case VSX_BUILTIN_XXSEL_4SI_UNS:
12469 case VSX_BUILTIN_XXSEL_2DI_UNS:
12476 /* signed permute functions with unsigned char mask. */
12477 case ALTIVEC_BUILTIN_VPERM_16QI:
12478 case ALTIVEC_BUILTIN_VPERM_8HI:
12479 case ALTIVEC_BUILTIN_VPERM_4SI:
12480 case ALTIVEC_BUILTIN_VPERM_4SF:
12481 case ALTIVEC_BUILTIN_VPERM_2DI:
12482 case ALTIVEC_BUILTIN_VPERM_2DF:
12483 case VSX_BUILTIN_VPERM_16QI:
12484 case VSX_BUILTIN_VPERM_8HI:
12485 case VSX_BUILTIN_VPERM_4SI:
12486 case VSX_BUILTIN_VPERM_4SF:
12487 case VSX_BUILTIN_VPERM_2DI:
12488 case VSX_BUILTIN_VPERM_2DF:
12492 /* unsigned args, signed return. */
12493 case VSX_BUILTIN_XVCVUXDDP_UNS:
12494 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
12498 /* signed args, unsigned return. */
12499 case VSX_BUILTIN_XVCVDPUXDS_UNS:
12500 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
12508 /* Figure out how many args are present. */
12509 while (num_args > 0 && h.mode[num_args] == VOIDmode)
12513 fatal_error ("internal error: builtin function %s had no type", name);
12515 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
12516 if (!ret_type && h.uns_p[0])
12517 ret_type = builtin_mode_to_type[h.mode[0]][0];
12520 fatal_error ("internal error: builtin function %s had an unexpected "
12521 "return type %s", name, GET_MODE_NAME (h.mode[0]));
12523 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
12524 arg_type[i] = NULL_TREE;
12526 for (i = 0; i < num_args; i++)
12528 int m = (int) h.mode[i+1];
12529 int uns_p = h.uns_p[i+1];
12531 arg_type[i] = builtin_mode_to_type[m][uns_p];
12532 if (!arg_type[i] && uns_p)
12533 arg_type[i] = builtin_mode_to_type[m][0];
12536 fatal_error ("internal error: builtin function %s, argument %d "
12537 "had unexpected argument type %s", name, i,
12538 GET_MODE_NAME (m));
12541 found = htab_find_slot (builtin_hash_table, &h, INSERT);
12542 if (*found == NULL)
12544 h2 = ggc_alloc_builtin_hash_struct ();
12546 *found = (void *)h2;
12548 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
12549 arg_type[2], NULL_TREE);
12552 return ((struct builtin_hash_struct *)(*found))->type;
12556 rs6000_common_init_builtins (void)
12558 const struct builtin_description *d;
12561 tree opaque_ftype_opaque = NULL_TREE;
12562 tree opaque_ftype_opaque_opaque = NULL_TREE;
12563 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
12564 tree v2si_ftype_qi = NULL_TREE;
12565 tree v2si_ftype_v2si_qi = NULL_TREE;
12566 tree v2si_ftype_int_qi = NULL_TREE;
12567 unsigned builtin_mask = rs6000_builtin_mask;
12569 if (!TARGET_PAIRED_FLOAT)
12571 builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
12572 builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
12575 /* Paired and SPE builtins are only available if you build a compiler with
12576 the appropriate options, so only create those builtins with the
12577 appropriate compiler option. Create Altivec and VSX builtins on machines
12578 with at least the general purpose extensions (970 and newer) to allow the
12579 use of the target attribute.. */
12581 if (TARGET_EXTRA_BUILTINS)
12582 builtin_mask |= RS6000_BTM_COMMON;
12584 /* Add the ternary operators. */
12586 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
12589 unsigned mask = d->mask;
12591 if ((mask & builtin_mask) != mask)
12593 if (TARGET_DEBUG_BUILTIN)
12594 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
12598 if (rs6000_overloaded_builtin_p (d->code))
12600 if (! (type = opaque_ftype_opaque_opaque_opaque))
12601 type = opaque_ftype_opaque_opaque_opaque
12602 = build_function_type_list (opaque_V4SI_type_node,
12603 opaque_V4SI_type_node,
12604 opaque_V4SI_type_node,
12605 opaque_V4SI_type_node,
12610 enum insn_code icode = d->icode;
12611 if (d->name == 0 || icode == CODE_FOR_nothing)
12614 type = builtin_function_type (insn_data[icode].operand[0].mode,
12615 insn_data[icode].operand[1].mode,
12616 insn_data[icode].operand[2].mode,
12617 insn_data[icode].operand[3].mode,
12621 def_builtin (d->name, type, d->code);
12624 /* Add the binary operators. */
12626 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
12628 enum machine_mode mode0, mode1, mode2;
12630 unsigned mask = d->mask;
12632 if ((mask & builtin_mask) != mask)
12634 if (TARGET_DEBUG_BUILTIN)
12635 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
12639 if (rs6000_overloaded_builtin_p (d->code))
12641 if (! (type = opaque_ftype_opaque_opaque))
12642 type = opaque_ftype_opaque_opaque
12643 = build_function_type_list (opaque_V4SI_type_node,
12644 opaque_V4SI_type_node,
12645 opaque_V4SI_type_node,
12650 enum insn_code icode = d->icode;
12651 if (d->name == 0 || icode == CODE_FOR_nothing)
12654 mode0 = insn_data[icode].operand[0].mode;
12655 mode1 = insn_data[icode].operand[1].mode;
12656 mode2 = insn_data[icode].operand[2].mode;
12658 if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
12660 if (! (type = v2si_ftype_v2si_qi))
12661 type = v2si_ftype_v2si_qi
12662 = build_function_type_list (opaque_V2SI_type_node,
12663 opaque_V2SI_type_node,
12668 else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
12669 && mode2 == QImode)
12671 if (! (type = v2si_ftype_int_qi))
12672 type = v2si_ftype_int_qi
12673 = build_function_type_list (opaque_V2SI_type_node,
12680 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
12684 def_builtin (d->name, type, d->code);
12687 /* Add the simple unary operators. */
12689 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
12691 enum machine_mode mode0, mode1;
12693 unsigned mask = d->mask;
12695 if ((mask & builtin_mask) != mask)
12697 if (TARGET_DEBUG_BUILTIN)
12698 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
12702 if (rs6000_overloaded_builtin_p (d->code))
12704 if (! (type = opaque_ftype_opaque))
12705 type = opaque_ftype_opaque
12706 = build_function_type_list (opaque_V4SI_type_node,
12707 opaque_V4SI_type_node,
12712 enum insn_code icode = d->icode;
12713 if (d->name == 0 || icode == CODE_FOR_nothing)
12716 mode0 = insn_data[icode].operand[0].mode;
12717 mode1 = insn_data[icode].operand[1].mode;
12719 if (mode0 == V2SImode && mode1 == QImode)
12721 if (! (type = v2si_ftype_qi))
12722 type = v2si_ftype_qi
12723 = build_function_type_list (opaque_V2SI_type_node,
12729 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
12733 def_builtin (d->name, type, d->code);
12738 rs6000_init_libfuncs (void)
12740 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
12741 && !TARGET_POWER2 && !TARGET_POWERPC)
12743 /* AIX library routines for float->int conversion. */
12744 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
12745 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
12746 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
12747 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
12750 if (!TARGET_IEEEQUAD)
12751 /* AIX/Darwin/64-bit Linux quad floating point routines. */
12752 if (!TARGET_XL_COMPAT)
12754 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
12755 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
12756 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
12757 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
12759 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
12761 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
12762 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
12763 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
12764 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
12765 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
12766 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
12767 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
12769 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
12770 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
12771 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
12772 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
12773 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
12774 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
12775 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
12776 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
12779 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
12780 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
12784 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
12785 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
12786 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
12787 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
12791 /* 32-bit SVR4 quad floating point routines. */
12793 set_optab_libfunc (add_optab, TFmode, "_q_add");
12794 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
12795 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
12796 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
12797 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
12798 if (TARGET_PPC_GPOPT || TARGET_POWER2)
12799 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
12801 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
12802 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
12803 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
12804 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
12805 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
12806 set_optab_libfunc (le_optab, TFmode, "_q_fle");
12808 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
12809 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
12810 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
12811 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
12812 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
12813 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
12814 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
12815 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
12820 /* Expand a block clear operation, and return 1 if successful. Return 0
12821 if we should let the compiler generate normal code.
12823 operands[0] is the destination
12824 operands[1] is the length
12825 operands[3] is the alignment */
12828 expand_block_clear (rtx operands[])
12830 rtx orig_dest = operands[0];
12831 rtx bytes_rtx = operands[1];
12832 rtx align_rtx = operands[3];
12833 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
12834 HOST_WIDE_INT align;
12835 HOST_WIDE_INT bytes;
12840 /* If this is not a fixed size move, just call memcpy */
12844 /* This must be a fixed size alignment */
12845 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
12846 align = INTVAL (align_rtx) * BITS_PER_UNIT;
12848 /* Anything to clear? */
12849 bytes = INTVAL (bytes_rtx);
12853 /* Use the builtin memset after a point, to avoid huge code bloat.
12854 When optimize_size, avoid any significant code bloat; calling
12855 memset is about 4 instructions, so allow for one instruction to
12856 load zero and three to do clearing. */
12857 if (TARGET_ALTIVEC && align >= 128)
12859 else if (TARGET_POWERPC64 && align >= 32)
12861 else if (TARGET_SPE && align >= 64)
12866 if (optimize_size && bytes > 3 * clear_step)
12868 if (! optimize_size && bytes > 8 * clear_step)
12871 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
12873 enum machine_mode mode = BLKmode;
12876 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
12881 else if (bytes >= 8 && TARGET_SPE && align >= 64)
12886 else if (bytes >= 8 && TARGET_POWERPC64
12887 /* 64-bit loads and stores require word-aligned
12889 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
12894 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
12895 { /* move 4 bytes */
12899 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
12900 { /* move 2 bytes */
12904 else /* move 1 byte at a time */
12910 dest = adjust_address (orig_dest, mode, offset);
12912 emit_move_insn (dest, CONST0_RTX (mode));
12919 /* Expand a block move operation, and return 1 if successful. Return 0
12920 if we should let the compiler generate normal code.
12922 operands[0] is the destination
12923 operands[1] is the source
12924 operands[2] is the length
12925 operands[3] is the alignment */
12927 #define MAX_MOVE_REG 4
12930 expand_block_move (rtx operands[])
12932 rtx orig_dest = operands[0];
12933 rtx orig_src = operands[1];
12934 rtx bytes_rtx = operands[2];
12935 rtx align_rtx = operands[3];
12936 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
12941 rtx stores[MAX_MOVE_REG];
12944 /* If this is not a fixed size move, just call memcpy */
12948 /* This must be a fixed size alignment */
12949 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
12950 align = INTVAL (align_rtx) * BITS_PER_UNIT;
12952 /* Anything to move? */
12953 bytes = INTVAL (bytes_rtx);
12957 if (bytes > rs6000_block_move_inline_limit)
12960 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
12963 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
12964 rtx (*mov) (rtx, rtx);
12966 enum machine_mode mode = BLKmode;
12969 /* Altivec first, since it will be faster than a string move
12970 when it applies, and usually not significantly larger. */
12971 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
12975 gen_func.mov = gen_movv4si;
12977 else if (TARGET_SPE && bytes >= 8 && align >= 64)
12981 gen_func.mov = gen_movv2si;
12983 else if (TARGET_STRING
12984 && bytes > 24 /* move up to 32 bytes at a time */
12990 && ! fixed_regs[10]
12991 && ! fixed_regs[11]
12992 && ! fixed_regs[12])
12994 move_bytes = (bytes > 32) ? 32 : bytes;
12995 gen_func.movmemsi = gen_movmemsi_8reg;
12997 else if (TARGET_STRING
12998 && bytes > 16 /* move up to 24 bytes at a time */
13004 && ! fixed_regs[10])
13006 move_bytes = (bytes > 24) ? 24 : bytes;
13007 gen_func.movmemsi = gen_movmemsi_6reg;
13009 else if (TARGET_STRING
13010 && bytes > 8 /* move up to 16 bytes at a time */
13014 && ! fixed_regs[8])
13016 move_bytes = (bytes > 16) ? 16 : bytes;
13017 gen_func.movmemsi = gen_movmemsi_4reg;
13019 else if (bytes >= 8 && TARGET_POWERPC64
13020 /* 64-bit loads and stores require word-aligned
13022 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
13026 gen_func.mov = gen_movdi;
13028 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
13029 { /* move up to 8 bytes at a time */
13030 move_bytes = (bytes > 8) ? 8 : bytes;
13031 gen_func.movmemsi = gen_movmemsi_2reg;
13033 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
13034 { /* move 4 bytes */
13037 gen_func.mov = gen_movsi;
13039 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
13040 { /* move 2 bytes */
13043 gen_func.mov = gen_movhi;
13045 else if (TARGET_STRING && bytes > 1)
13046 { /* move up to 4 bytes at a time */
13047 move_bytes = (bytes > 4) ? 4 : bytes;
13048 gen_func.movmemsi = gen_movmemsi_1reg;
13050 else /* move 1 byte at a time */
13054 gen_func.mov = gen_movqi;
13057 src = adjust_address (orig_src, mode, offset);
13058 dest = adjust_address (orig_dest, mode, offset);
13060 if (mode != BLKmode)
13062 rtx tmp_reg = gen_reg_rtx (mode);
13064 emit_insn ((*gen_func.mov) (tmp_reg, src));
13065 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
13068 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
13071 for (i = 0; i < num_reg; i++)
13072 emit_insn (stores[i]);
13076 if (mode == BLKmode)
13078 /* Move the address into scratch registers. The movmemsi
13079 patterns require zero offset. */
13080 if (!REG_P (XEXP (src, 0)))
13082 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
13083 src = replace_equiv_address (src, src_reg);
13085 set_mem_size (src, move_bytes);
13087 if (!REG_P (XEXP (dest, 0)))
13089 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
13090 dest = replace_equiv_address (dest, dest_reg);
13092 set_mem_size (dest, move_bytes);
13094 emit_insn ((*gen_func.movmemsi) (dest, src,
13095 GEN_INT (move_bytes & 31),
13104 /* Return a string to perform a load_multiple operation.
13105 operands[0] is the vector.
13106 operands[1] is the source address.
13107 operands[2] is the first destination register. */
13110 rs6000_output_load_multiple (rtx operands[3])
13112 /* We have to handle the case where the pseudo used to contain the address
13113 is assigned to one of the output registers. */
13115 int words = XVECLEN (operands[0], 0);
13118 if (XVECLEN (operands[0], 0) == 1)
13119 return "{l|lwz} %2,0(%1)";
13121 for (i = 0; i < words; i++)
13122 if (refers_to_regno_p (REGNO (operands[2]) + i,
13123 REGNO (operands[2]) + i + 1, operands[1], 0))
13127 xop[0] = GEN_INT (4 * (words-1));
13128 xop[1] = operands[1];
13129 xop[2] = operands[2];
13130 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
13135 xop[0] = GEN_INT (4 * (words-1));
13136 xop[1] = operands[1];
13137 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
13138 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
13143 for (j = 0; j < words; j++)
13146 xop[0] = GEN_INT (j * 4);
13147 xop[1] = operands[1];
13148 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
13149 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
13151 xop[0] = GEN_INT (i * 4);
13152 xop[1] = operands[1];
13153 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
13158 return "{lsi|lswi} %2,%1,%N0";
13162 /* A validation routine: say whether CODE, a condition code, and MODE
13163 match. The other alternatives either don't make sense or should
13164 never be generated. */
13167 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
13169 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
13170 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
13171 && GET_MODE_CLASS (mode) == MODE_CC);
13173 /* These don't make sense. */
13174 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
13175 || mode != CCUNSmode);
13177 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
13178 || mode == CCUNSmode);
13180 gcc_assert (mode == CCFPmode
13181 || (code != ORDERED && code != UNORDERED
13182 && code != UNEQ && code != LTGT
13183 && code != UNGT && code != UNLT
13184 && code != UNGE && code != UNLE));
13186 /* These should never be generated except for
13187 flag_finite_math_only. */
13188 gcc_assert (mode != CCFPmode
13189 || flag_finite_math_only
13190 || (code != LE && code != GE
13191 && code != UNEQ && code != LTGT
13192 && code != UNGT && code != UNLT));
13194 /* These are invalid; the information is not there. */
13195 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
13199 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
13200 mask required to convert the result of a rotate insn into a shift
13201 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
13204 includes_lshift_p (rtx shiftop, rtx andop)
13206 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13208 shift_mask <<= INTVAL (shiftop);
13210 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13213 /* Similar, but for right shift. */
13216 includes_rshift_p (rtx shiftop, rtx andop)
13218 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
13220 shift_mask >>= INTVAL (shiftop);
13222 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
13225 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
13226 to perform a left shift. It must have exactly SHIFTOP least
13227 significant 0's, then one or more 1's, then zero or more 0's. */
13230 includes_rldic_lshift_p (rtx shiftop, rtx andop)
13232 if (GET_CODE (andop) == CONST_INT)
13234 HOST_WIDE_INT c, lsb, shift_mask;
13236 c = INTVAL (andop);
13237 if (c == 0 || c == ~0)
13241 shift_mask <<= INTVAL (shiftop);
13243 /* Find the least significant one bit. */
13246 /* It must coincide with the LSB of the shift mask. */
13247 if (-lsb != shift_mask)
13250 /* Invert to look for the next transition (if any). */
13253 /* Remove the low group of ones (originally low group of zeros). */
13256 /* Again find the lsb, and check we have all 1's above. */
13260 else if (GET_CODE (andop) == CONST_DOUBLE
13261 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13263 HOST_WIDE_INT low, high, lsb;
13264 HOST_WIDE_INT shift_mask_low, shift_mask_high;
13266 low = CONST_DOUBLE_LOW (andop);
13267 if (HOST_BITS_PER_WIDE_INT < 64)
13268 high = CONST_DOUBLE_HIGH (andop);
13270 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
13271 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
13274 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13276 shift_mask_high = ~0;
13277 if (INTVAL (shiftop) > 32)
13278 shift_mask_high <<= INTVAL (shiftop) - 32;
13280 lsb = high & -high;
13282 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
13288 lsb = high & -high;
13289 return high == -lsb;
13292 shift_mask_low = ~0;
13293 shift_mask_low <<= INTVAL (shiftop);
13297 if (-lsb != shift_mask_low)
13300 if (HOST_BITS_PER_WIDE_INT < 64)
13305 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
13307 lsb = high & -high;
13308 return high == -lsb;
13312 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
13318 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
13319 to perform a left shift. It must have SHIFTOP or more least
13320 significant 0's, with the remainder of the word 1's. */
13323 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
13325 if (GET_CODE (andop) == CONST_INT)
13327 HOST_WIDE_INT c, lsb, shift_mask;
13330 shift_mask <<= INTVAL (shiftop);
13331 c = INTVAL (andop);
13333 /* Find the least significant one bit. */
13336 /* It must be covered by the shift mask.
13337 This test also rejects c == 0. */
13338 if ((lsb & shift_mask) == 0)
13341 /* Check we have all 1's above the transition, and reject all 1's. */
13342 return c == -lsb && lsb != 1;
13344 else if (GET_CODE (andop) == CONST_DOUBLE
13345 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
13347 HOST_WIDE_INT low, lsb, shift_mask_low;
13349 low = CONST_DOUBLE_LOW (andop);
13351 if (HOST_BITS_PER_WIDE_INT < 64)
13353 HOST_WIDE_INT high, shift_mask_high;
13355 high = CONST_DOUBLE_HIGH (andop);
13359 shift_mask_high = ~0;
13360 if (INTVAL (shiftop) > 32)
13361 shift_mask_high <<= INTVAL (shiftop) - 32;
13363 lsb = high & -high;
13365 if ((lsb & shift_mask_high) == 0)
13368 return high == -lsb;
13374 shift_mask_low = ~0;
13375 shift_mask_low <<= INTVAL (shiftop);
13379 if ((lsb & shift_mask_low) == 0)
13382 return low == -lsb && lsb != 1;
13388 /* Return 1 if operands will generate a valid arguments to rlwimi
13389 instruction for insert with right shift in 64-bit mode. The mask may
13390 not start on the first bit or stop on the last bit because wrap-around
13391 effects of instruction do not correspond to semantics of RTL insn. */
13394 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
13396 if (INTVAL (startop) > 32
13397 && INTVAL (startop) < 64
13398 && INTVAL (sizeop) > 1
13399 && INTVAL (sizeop) + INTVAL (startop) < 64
13400 && INTVAL (shiftop) > 0
13401 && INTVAL (sizeop) + INTVAL (shiftop) < 32
13402 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
13408 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
13409 for lfq and stfq insns iff the registers are hard registers. */
13412 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
13414 /* We might have been passed a SUBREG. */
13415 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
13418 /* We might have been passed non floating point registers. */
13419 if (!FP_REGNO_P (REGNO (reg1))
13420 || !FP_REGNO_P (REGNO (reg2)))
13423 return (REGNO (reg1) == REGNO (reg2) - 1);
13426 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
13427 addr1 and addr2 must be in consecutive memory locations
13428 (addr2 == addr1 + 8). */
13431 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
13434 unsigned int reg1, reg2;
13435 int offset1, offset2;
13437 /* The mems cannot be volatile. */
13438 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
13441 addr1 = XEXP (mem1, 0);
13442 addr2 = XEXP (mem2, 0);
13444 /* Extract an offset (if used) from the first addr. */
13445 if (GET_CODE (addr1) == PLUS)
13447 /* If not a REG, return zero. */
13448 if (GET_CODE (XEXP (addr1, 0)) != REG)
13452 reg1 = REGNO (XEXP (addr1, 0));
13453 /* The offset must be constant! */
13454 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
13456 offset1 = INTVAL (XEXP (addr1, 1));
13459 else if (GET_CODE (addr1) != REG)
13463 reg1 = REGNO (addr1);
13464 /* This was a simple (mem (reg)) expression. Offset is 0. */
13468 /* And now for the second addr. */
13469 if (GET_CODE (addr2) == PLUS)
13471 /* If not a REG, return zero. */
13472 if (GET_CODE (XEXP (addr2, 0)) != REG)
13476 reg2 = REGNO (XEXP (addr2, 0));
13477 /* The offset must be constant. */
13478 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
13480 offset2 = INTVAL (XEXP (addr2, 1));
13483 else if (GET_CODE (addr2) != REG)
13487 reg2 = REGNO (addr2);
13488 /* This was a simple (mem (reg)) expression. Offset is 0. */
13492 /* Both of these must have the same base register. */
13496 /* The offset for the second addr must be 8 more than the first addr. */
13497 if (offset2 != offset1 + 8)
13500 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
13507 rs6000_secondary_memory_needed_rtx (enum machine_mode mode)
13509 static bool eliminated = false;
13512 if (mode != SDmode)
13513 ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
13516 rtx mem = cfun->machine->sdmode_stack_slot;
13517 gcc_assert (mem != NULL_RTX);
13521 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
13522 cfun->machine->sdmode_stack_slot = mem;
13528 if (TARGET_DEBUG_ADDR)
13530 fprintf (stderr, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
13531 GET_MODE_NAME (mode));
13533 fprintf (stderr, "\tNULL_RTX\n");
13542 rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
13544 /* Don't walk into types. */
13545 if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp))
13547 *walk_subtrees = 0;
13551 switch (TREE_CODE (*tp))
13560 case VIEW_CONVERT_EXPR:
13561 if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode)
13571 enum reload_reg_type {
13573 VECTOR_REGISTER_TYPE,
13574 OTHER_REGISTER_TYPE
13577 static enum reload_reg_type
13578 rs6000_reload_register_type (enum reg_class rclass)
13584 return GPR_REGISTER_TYPE;
13589 return VECTOR_REGISTER_TYPE;
13592 return OTHER_REGISTER_TYPE;
13596 /* Inform reload about cases where moving X with a mode MODE to a register in
13597 RCLASS requires an extra scratch or immediate register. Return the class
13598 needed for the immediate register.
13600 For VSX and Altivec, we may need a register to convert sp+offset into
13603 For misaligned 64-bit gpr loads and stores we need a register to
13604 convert an offset address to indirect. */
13607 rs6000_secondary_reload (bool in_p,
13609 reg_class_t rclass_i,
13610 enum machine_mode mode,
13611 secondary_reload_info *sri)
13613 enum reg_class rclass = (enum reg_class) rclass_i;
13614 reg_class_t ret = ALL_REGS;
13615 enum insn_code icode;
13616 bool default_p = false;
13618 sri->icode = CODE_FOR_nothing;
13620 /* Convert vector loads and stores into gprs to use an additional base
13622 icode = rs6000_vector_reload[mode][in_p != false];
13623 if (icode != CODE_FOR_nothing)
13626 sri->icode = CODE_FOR_nothing;
13627 sri->extra_cost = 0;
13629 if (GET_CODE (x) == MEM)
13631 rtx addr = XEXP (x, 0);
13633 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
13634 an extra register in that case, but it would need an extra
13635 register if the addressing is reg+reg or (reg+reg)&(-16). */
13636 if (rclass == GENERAL_REGS || rclass == BASE_REGS)
13638 if (!legitimate_indirect_address_p (addr, false)
13639 && !rs6000_legitimate_offset_address_p (TImode, addr, false))
13641 sri->icode = icode;
13642 /* account for splitting the loads, and converting the
13643 address from reg+reg to reg. */
13644 sri->extra_cost = (((TARGET_64BIT) ? 3 : 5)
13645 + ((GET_CODE (addr) == AND) ? 1 : 0));
13648 /* Loads to and stores from vector registers can only do reg+reg
13649 addressing. Altivec registers can also do (reg+reg)&(-16). */
13650 else if (rclass == VSX_REGS || rclass == ALTIVEC_REGS
13651 || rclass == FLOAT_REGS || rclass == NO_REGS)
13653 if (!VECTOR_MEM_ALTIVEC_P (mode)
13654 && GET_CODE (addr) == AND
13655 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13656 && INTVAL (XEXP (addr, 1)) == -16
13657 && (legitimate_indirect_address_p (XEXP (addr, 0), false)
13658 || legitimate_indexed_address_p (XEXP (addr, 0), false)))
13660 sri->icode = icode;
13661 sri->extra_cost = ((GET_CODE (XEXP (addr, 0)) == PLUS)
13664 else if (!legitimate_indirect_address_p (addr, false)
13665 && (rclass == NO_REGS
13666 || !legitimate_indexed_address_p (addr, false)))
13668 sri->icode = icode;
13669 sri->extra_cost = 1;
13672 icode = CODE_FOR_nothing;
13674 /* Any other loads, including to pseudo registers which haven't been
13675 assigned to a register yet, default to require a scratch
13679 sri->icode = icode;
13680 sri->extra_cost = 2;
13683 else if (REG_P (x))
13685 int regno = true_regnum (x);
13687 icode = CODE_FOR_nothing;
13688 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
13692 enum reg_class xclass = REGNO_REG_CLASS (regno);
13693 enum reload_reg_type rtype1 = rs6000_reload_register_type (rclass);
13694 enum reload_reg_type rtype2 = rs6000_reload_register_type (xclass);
13696 /* If memory is needed, use default_secondary_reload to create the
13698 if (rtype1 != rtype2 || rtype1 == OTHER_REGISTER_TYPE)
13707 else if (TARGET_POWERPC64
13708 && rs6000_reload_register_type (rclass) == GPR_REGISTER_TYPE
13710 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
13712 rtx addr = XEXP (x, 0);
13714 if (GET_CODE (addr) == PRE_MODIFY)
13715 addr = XEXP (addr, 1);
13716 else if (GET_CODE (addr) == LO_SUM
13717 && GET_CODE (XEXP (addr, 0)) == REG
13718 && GET_CODE (XEXP (addr, 1)) == CONST)
13719 addr = XEXP (XEXP (addr, 1), 0);
13721 if (GET_CODE (addr) == PLUS
13722 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13723 && (INTVAL (XEXP (addr, 1)) & 3) != 0)
13726 sri->icode = CODE_FOR_reload_di_load;
13728 sri->icode = CODE_FOR_reload_di_store;
13729 sri->extra_cost = 2;
13739 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
13741 gcc_assert (ret != ALL_REGS);
13743 if (TARGET_DEBUG_ADDR)
13746 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
13748 reg_class_names[ret],
13749 in_p ? "true" : "false",
13750 reg_class_names[rclass],
13751 GET_MODE_NAME (mode));
13754 fprintf (stderr, ", default secondary reload");
13756 if (sri->icode != CODE_FOR_nothing)
13757 fprintf (stderr, ", reload func = %s, extra cost = %d\n",
13758 insn_data[sri->icode].name, sri->extra_cost);
13760 fprintf (stderr, "\n");
13768 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
13769 to SP+reg addressing. */
13772 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
13774 int regno = true_regnum (reg);
13775 enum machine_mode mode = GET_MODE (reg);
13776 enum reg_class rclass;
13778 rtx and_op2 = NULL_RTX;
13781 rtx scratch_or_premodify = scratch;
13785 if (TARGET_DEBUG_ADDR)
13787 fprintf (stderr, "\nrs6000_secondary_reload_inner, type = %s\n",
13788 store_p ? "store" : "load");
13789 fprintf (stderr, "reg:\n");
13791 fprintf (stderr, "mem:\n");
13793 fprintf (stderr, "scratch:\n");
13794 debug_rtx (scratch);
13797 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
13798 gcc_assert (GET_CODE (mem) == MEM);
13799 rclass = REGNO_REG_CLASS (regno);
13800 addr = XEXP (mem, 0);
13804 /* GPRs can handle reg + small constant, all other addresses need to use
13805 the scratch register. */
13808 if (GET_CODE (addr) == AND)
13810 and_op2 = XEXP (addr, 1);
13811 addr = XEXP (addr, 0);
13814 if (GET_CODE (addr) == PRE_MODIFY)
13816 scratch_or_premodify = XEXP (addr, 0);
13817 gcc_assert (REG_P (scratch_or_premodify));
13818 gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
13819 addr = XEXP (addr, 1);
13822 if (GET_CODE (addr) == PLUS
13823 && (!rs6000_legitimate_offset_address_p (TImode, addr, false)
13824 || and_op2 != NULL_RTX))
13826 addr_op1 = XEXP (addr, 0);
13827 addr_op2 = XEXP (addr, 1);
13828 gcc_assert (legitimate_indirect_address_p (addr_op1, false));
13830 if (!REG_P (addr_op2)
13831 && (GET_CODE (addr_op2) != CONST_INT
13832 || !satisfies_constraint_I (addr_op2)))
13834 if (TARGET_DEBUG_ADDR)
13837 "\nMove plus addr to register %s, mode = %s: ",
13838 rs6000_reg_names[REGNO (scratch)],
13839 GET_MODE_NAME (mode));
13840 debug_rtx (addr_op2);
13842 rs6000_emit_move (scratch, addr_op2, Pmode);
13843 addr_op2 = scratch;
13846 emit_insn (gen_rtx_SET (VOIDmode,
13847 scratch_or_premodify,
13848 gen_rtx_PLUS (Pmode,
13852 addr = scratch_or_premodify;
13853 scratch_or_premodify = scratch;
13855 else if (!legitimate_indirect_address_p (addr, false)
13856 && !rs6000_legitimate_offset_address_p (TImode, addr, false))
13858 if (TARGET_DEBUG_ADDR)
13860 fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
13861 rs6000_reg_names[REGNO (scratch_or_premodify)],
13862 GET_MODE_NAME (mode));
13865 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13866 addr = scratch_or_premodify;
13867 scratch_or_premodify = scratch;
13871 /* Float/Altivec registers can only handle reg+reg addressing. Move
13872 other addresses into a scratch register. */
13877 /* With float regs, we need to handle the AND ourselves, since we can't
13878 use the Altivec instruction with an implicit AND -16. Allow scalar
13879 loads to float registers to use reg+offset even if VSX. */
13880 if (GET_CODE (addr) == AND
13881 && (rclass != ALTIVEC_REGS || GET_MODE_SIZE (mode) != 16
13882 || GET_CODE (XEXP (addr, 1)) != CONST_INT
13883 || INTVAL (XEXP (addr, 1)) != -16
13884 || !VECTOR_MEM_ALTIVEC_P (mode)))
13886 and_op2 = XEXP (addr, 1);
13887 addr = XEXP (addr, 0);
13890 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
13891 as the address later. */
13892 if (GET_CODE (addr) == PRE_MODIFY
13893 && (!VECTOR_MEM_VSX_P (mode)
13894 || and_op2 != NULL_RTX
13895 || !legitimate_indexed_address_p (XEXP (addr, 1), false)))
13897 scratch_or_premodify = XEXP (addr, 0);
13898 gcc_assert (legitimate_indirect_address_p (scratch_or_premodify,
13900 gcc_assert (GET_CODE (XEXP (addr, 1)) == PLUS);
13901 addr = XEXP (addr, 1);
13904 if (legitimate_indirect_address_p (addr, false) /* reg */
13905 || legitimate_indexed_address_p (addr, false) /* reg+reg */
13906 || GET_CODE (addr) == PRE_MODIFY /* VSX pre-modify */
13907 || (GET_CODE (addr) == AND /* Altivec memory */
13908 && GET_CODE (XEXP (addr, 1)) == CONST_INT
13909 && INTVAL (XEXP (addr, 1)) == -16
13910 && VECTOR_MEM_ALTIVEC_P (mode))
13911 || (rclass == FLOAT_REGS /* legacy float mem */
13912 && GET_MODE_SIZE (mode) == 8
13913 && and_op2 == NULL_RTX
13914 && scratch_or_premodify == scratch
13915 && rs6000_legitimate_offset_address_p (mode, addr, false)))
13918 else if (GET_CODE (addr) == PLUS)
13920 addr_op1 = XEXP (addr, 0);
13921 addr_op2 = XEXP (addr, 1);
13922 gcc_assert (REG_P (addr_op1));
13924 if (TARGET_DEBUG_ADDR)
13926 fprintf (stderr, "\nMove plus addr to register %s, mode = %s: ",
13927 rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
13928 debug_rtx (addr_op2);
13930 rs6000_emit_move (scratch, addr_op2, Pmode);
13931 emit_insn (gen_rtx_SET (VOIDmode,
13932 scratch_or_premodify,
13933 gen_rtx_PLUS (Pmode,
13936 addr = scratch_or_premodify;
13937 scratch_or_premodify = scratch;
13940 else if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == CONST
13941 || GET_CODE (addr) == CONST_INT || REG_P (addr))
13943 if (TARGET_DEBUG_ADDR)
13945 fprintf (stderr, "\nMove addr to register %s, mode = %s: ",
13946 rs6000_reg_names[REGNO (scratch_or_premodify)],
13947 GET_MODE_NAME (mode));
13951 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
13952 addr = scratch_or_premodify;
13953 scratch_or_premodify = scratch;
13957 gcc_unreachable ();
13962 gcc_unreachable ();
13965 /* If the original address involved a pre-modify that we couldn't use the VSX
13966 memory instruction with update, and we haven't taken care of already,
13967 store the address in the pre-modify register and use that as the
13969 if (scratch_or_premodify != scratch && scratch_or_premodify != addr)
13971 emit_insn (gen_rtx_SET (VOIDmode, scratch_or_premodify, addr));
13972 addr = scratch_or_premodify;
13975 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
13976 memory instruction, recreate the AND now, including the clobber which is
13977 generated by the general ANDSI3/ANDDI3 patterns for the
13978 andi. instruction. */
13979 if (and_op2 != NULL_RTX)
13981 if (! legitimate_indirect_address_p (addr, false))
13983 emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
13987 if (TARGET_DEBUG_ADDR)
13989 fprintf (stderr, "\nAnd addr to register %s, mode = %s: ",
13990 rs6000_reg_names[REGNO (scratch)], GET_MODE_NAME (mode));
13991 debug_rtx (and_op2);
13994 and_rtx = gen_rtx_SET (VOIDmode,
13996 gen_rtx_AND (Pmode,
14000 cc_clobber = gen_rtx_CLOBBER (CCmode, gen_rtx_SCRATCH (CCmode));
14001 emit_insn (gen_rtx_PARALLEL (VOIDmode,
14002 gen_rtvec (2, and_rtx, cc_clobber)));
14006 /* Adjust the address if it changed. */
14007 if (addr != XEXP (mem, 0))
14009 mem = change_address (mem, mode, addr);
14010 if (TARGET_DEBUG_ADDR)
14011 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
14014 /* Now create the move. */
14016 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
14018 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
14023 /* Convert reloads involving 64-bit gprs and misaligned offset
14024 addressing to use indirect addressing. */
14027 rs6000_secondary_reload_ppc64 (rtx reg, rtx mem, rtx scratch, bool store_p)
14029 int regno = true_regnum (reg);
14030 enum reg_class rclass;
14032 rtx scratch_or_premodify = scratch;
14034 if (TARGET_DEBUG_ADDR)
14036 fprintf (stderr, "\nrs6000_secondary_reload_ppc64, type = %s\n",
14037 store_p ? "store" : "load");
14038 fprintf (stderr, "reg:\n");
14040 fprintf (stderr, "mem:\n");
14042 fprintf (stderr, "scratch:\n");
14043 debug_rtx (scratch);
14046 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
14047 gcc_assert (GET_CODE (mem) == MEM);
14048 rclass = REGNO_REG_CLASS (regno);
14049 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
14050 addr = XEXP (mem, 0);
14052 if (GET_CODE (addr) == PRE_MODIFY)
14054 scratch_or_premodify = XEXP (addr, 0);
14055 gcc_assert (REG_P (scratch_or_premodify));
14056 addr = XEXP (addr, 1);
14058 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
14060 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
14062 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
14064 /* Now create the move. */
14066 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
14068 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
14073 /* Allocate a 64-bit stack slot to be used for copying SDmode
14074 values through if this function has any SDmode references. */
14077 rs6000_alloc_sdmode_stack_slot (void)
14081 gimple_stmt_iterator gsi;
14083 gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
14086 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
14088 tree ret = walk_gimple_op (gsi_stmt (gsi), rs6000_check_sdmode, NULL);
14091 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
14092 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
14098 /* Check for any SDmode parameters of the function. */
14099 for (t = DECL_ARGUMENTS (cfun->decl); t; t = DECL_CHAIN (t))
14101 if (TREE_TYPE (t) == error_mark_node)
14104 if (TYPE_MODE (TREE_TYPE (t)) == SDmode
14105 || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode)
14107 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
14108 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
14116 rs6000_instantiate_decls (void)
14118 if (cfun->machine->sdmode_stack_slot != NULL_RTX)
14119 instantiate_decl_rtl (cfun->machine->sdmode_stack_slot);
14122 /* Given an rtx X being reloaded into a reg required to be
14123 in class CLASS, return the class of reg to actually use.
14124 In general this is just CLASS; but on some machines
14125 in some cases it is preferable to use a more restrictive class.
14127 On the RS/6000, we have to return NO_REGS when we want to reload a
14128 floating-point CONST_DOUBLE to force it to be copied to memory.
14130 We also don't want to reload integer values into floating-point
14131 registers if we can at all help it. In fact, this can
14132 cause reload to die, if it tries to generate a reload of CTR
14133 into a FP register and discovers it doesn't have the memory location
14136 ??? Would it be a good idea to have reload do the converse, that is
14137 try to reload floating modes into FP registers if possible?
14140 static enum reg_class
14141 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
14143 enum machine_mode mode = GET_MODE (x);
14145 if (VECTOR_UNIT_VSX_P (mode)
14146 && x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
14149 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
14150 && (rclass == ALTIVEC_REGS || rclass == VSX_REGS)
14151 && easy_vector_constant (x, mode))
14152 return ALTIVEC_REGS;
14154 if (CONSTANT_P (x) && reg_classes_intersect_p (rclass, FLOAT_REGS))
14157 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
14158 return GENERAL_REGS;
14160 /* For VSX, prefer the traditional registers for 64-bit values because we can
14161 use the non-VSX loads. Prefer the Altivec registers if Altivec is
14162 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
14163 prefer Altivec loads.. */
14164 if (rclass == VSX_REGS)
14166 if (GET_MODE_SIZE (mode) <= 8)
14169 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode))
14170 return ALTIVEC_REGS;
14178 /* Debug version of rs6000_preferred_reload_class. */
14179 static enum reg_class
14180 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
14182 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
14185 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
14187 reg_class_names[ret], reg_class_names[rclass],
14188 GET_MODE_NAME (GET_MODE (x)));
14194 /* If we are copying between FP or AltiVec registers and anything else, we need
14195 a memory location. The exception is when we are targeting ppc64 and the
14196 move to/from fpr to gpr instructions are available. Also, under VSX, you
14197 can copy vector registers from the FP register set to the Altivec register
14198 set and vice versa. */
14201 rs6000_secondary_memory_needed (enum reg_class class1,
14202 enum reg_class class2,
14203 enum machine_mode mode)
14205 if (class1 == class2)
14208 /* Under VSX, there are 3 register classes that values could be in (VSX_REGS,
14209 ALTIVEC_REGS, and FLOAT_REGS). We don't need to use memory to copy
14210 between these classes. But we need memory for other things that can go in
14211 FLOAT_REGS like SFmode. */
14213 && (VECTOR_MEM_VSX_P (mode) || VECTOR_UNIT_VSX_P (mode))
14214 && (class1 == VSX_REGS || class1 == ALTIVEC_REGS
14215 || class1 == FLOAT_REGS))
14216 return (class2 != VSX_REGS && class2 != ALTIVEC_REGS
14217 && class2 != FLOAT_REGS);
14219 if (class1 == VSX_REGS || class2 == VSX_REGS)
14222 if (class1 == FLOAT_REGS
14223 && (!TARGET_MFPGPR || !TARGET_POWERPC64
14224 || ((mode != DFmode)
14225 && (mode != DDmode)
14226 && (mode != DImode))))
14229 if (class2 == FLOAT_REGS
14230 && (!TARGET_MFPGPR || !TARGET_POWERPC64
14231 || ((mode != DFmode)
14232 && (mode != DDmode)
14233 && (mode != DImode))))
14236 if (class1 == ALTIVEC_REGS || class2 == ALTIVEC_REGS)
14242 /* Debug version of rs6000_secondary_memory_needed. */
14244 rs6000_debug_secondary_memory_needed (enum reg_class class1,
14245 enum reg_class class2,
14246 enum machine_mode mode)
14248 bool ret = rs6000_secondary_memory_needed (class1, class2, mode);
14251 "rs6000_secondary_memory_needed, return: %s, class1 = %s, "
14252 "class2 = %s, mode = %s\n",
14253 ret ? "true" : "false", reg_class_names[class1],
14254 reg_class_names[class2], GET_MODE_NAME (mode));
14259 /* Return the register class of a scratch register needed to copy IN into
14260 or out of a register in RCLASS in MODE. If it can be done directly,
14261 NO_REGS is returned. */
14263 static enum reg_class
14264 rs6000_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
14269 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
14271 && MACHOPIC_INDIRECT
14275 /* We cannot copy a symbolic operand directly into anything
14276 other than BASE_REGS for TARGET_ELF. So indicate that a
14277 register from BASE_REGS is needed as an intermediate
14280 On Darwin, pic addresses require a load from memory, which
14281 needs a base register. */
14282 if (rclass != BASE_REGS
14283 && (GET_CODE (in) == SYMBOL_REF
14284 || GET_CODE (in) == HIGH
14285 || GET_CODE (in) == LABEL_REF
14286 || GET_CODE (in) == CONST))
14290 if (GET_CODE (in) == REG)
14292 regno = REGNO (in);
14293 if (regno >= FIRST_PSEUDO_REGISTER)
14295 regno = true_regnum (in);
14296 if (regno >= FIRST_PSEUDO_REGISTER)
14300 else if (GET_CODE (in) == SUBREG)
14302 regno = true_regnum (in);
14303 if (regno >= FIRST_PSEUDO_REGISTER)
14309 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
14311 if (rclass == GENERAL_REGS || rclass == BASE_REGS
14312 || (regno >= 0 && INT_REGNO_P (regno)))
14315 /* Constants, memory, and FP registers can go into FP registers. */
14316 if ((regno == -1 || FP_REGNO_P (regno))
14317 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
14318 return (mode != SDmode) ? NO_REGS : GENERAL_REGS;
14320 /* Memory, and FP/altivec registers can go into fp/altivec registers under
14323 && (regno == -1 || VSX_REGNO_P (regno))
14324 && VSX_REG_CLASS_P (rclass))
14327 /* Memory, and AltiVec registers can go into AltiVec registers. */
14328 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
14329 && rclass == ALTIVEC_REGS)
14332 /* We can copy among the CR registers. */
14333 if ((rclass == CR_REGS || rclass == CR0_REGS)
14334 && regno >= 0 && CR_REGNO_P (regno))
14337 /* Otherwise, we need GENERAL_REGS. */
14338 return GENERAL_REGS;
14341 /* Debug version of rs6000_secondary_reload_class. */
14342 static enum reg_class
14343 rs6000_debug_secondary_reload_class (enum reg_class rclass,
14344 enum machine_mode mode, rtx in)
14346 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
14348 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
14349 "mode = %s, input rtx:\n",
14350 reg_class_names[ret], reg_class_names[rclass],
14351 GET_MODE_NAME (mode));
14357 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
14360 rs6000_cannot_change_mode_class (enum machine_mode from,
14361 enum machine_mode to,
14362 enum reg_class rclass)
14364 unsigned from_size = GET_MODE_SIZE (from);
14365 unsigned to_size = GET_MODE_SIZE (to);
14367 if (from_size != to_size)
14369 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
14370 return ((from_size < 8 || to_size < 8 || TARGET_IEEEQUAD)
14371 && reg_classes_intersect_p (xclass, rclass));
14374 if (TARGET_E500_DOUBLE
14375 && ((((to) == DFmode) + ((from) == DFmode)) == 1
14376 || (((to) == TFmode) + ((from) == TFmode)) == 1
14377 || (((to) == DDmode) + ((from) == DDmode)) == 1
14378 || (((to) == TDmode) + ((from) == TDmode)) == 1
14379 || (((to) == DImode) + ((from) == DImode)) == 1))
14382 /* Since the VSX register set includes traditional floating point registers
14383 and altivec registers, just check for the size being different instead of
14384 trying to check whether the modes are vector modes. Otherwise it won't
14385 allow say DF and DI to change classes. */
14386 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
14387 return (from_size != 8 && from_size != 16);
14389 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
14390 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
14393 if (TARGET_SPE && (SPE_VECTOR_MODE (from) + SPE_VECTOR_MODE (to)) == 1
14394 && reg_classes_intersect_p (GENERAL_REGS, rclass))
14400 /* Debug version of rs6000_cannot_change_mode_class. */
14402 rs6000_debug_cannot_change_mode_class (enum machine_mode from,
14403 enum machine_mode to,
14404 enum reg_class rclass)
14406 bool ret = rs6000_cannot_change_mode_class (from, to, rclass);
14409 "rs6000_cannot_change_mode_class, return %s, from = %s, "
14410 "to = %s, rclass = %s\n",
14411 ret ? "true" : "false",
14412 GET_MODE_NAME (from), GET_MODE_NAME (to),
14413 reg_class_names[rclass]);
14418 /* Given a comparison operation, return the bit number in CCR to test. We
14419 know this is a valid comparison.
14421 SCC_P is 1 if this is for an scc. That means that %D will have been
14422 used instead of %C, so the bits will be in different places.
14424 Return -1 if OP isn't a valid comparison for some reason. */
14427 ccr_bit (rtx op, int scc_p)
14429 enum rtx_code code = GET_CODE (op);
14430 enum machine_mode cc_mode;
14435 if (!COMPARISON_P (op))
14438 reg = XEXP (op, 0);
14440 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
14442 cc_mode = GET_MODE (reg);
14443 cc_regnum = REGNO (reg);
14444 base_bit = 4 * (cc_regnum - CR0_REGNO);
14446 validate_condition_mode (code, cc_mode);
14448 /* When generating a sCOND operation, only positive conditions are
14451 || code == EQ || code == GT || code == LT || code == UNORDERED
14452 || code == GTU || code == LTU);
14457 return scc_p ? base_bit + 3 : base_bit + 2;
14459 return base_bit + 2;
14460 case GT: case GTU: case UNLE:
14461 return base_bit + 1;
14462 case LT: case LTU: case UNGE:
14464 case ORDERED: case UNORDERED:
14465 return base_bit + 3;
14468 /* If scc, we will have done a cror to put the bit in the
14469 unordered position. So test that bit. For integer, this is ! LT
14470 unless this is an scc insn. */
14471 return scc_p ? base_bit + 3 : base_bit;
14474 return scc_p ? base_bit + 3 : base_bit + 1;
14477 gcc_unreachable ();
14481 /* Return the GOT register. */
14484 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
14486 /* The second flow pass currently (June 1999) can't update
14487 regs_ever_live without disturbing other parts of the compiler, so
14488 update it here to make the prolog/epilogue code happy. */
14489 if (!can_create_pseudo_p ()
14490 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
14491 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
14493 crtl->uses_pic_offset_table = 1;
14495 return pic_offset_table_rtx;
14498 static rs6000_stack_t stack_info;
14500 /* Function to init struct machine_function.
14501 This will be called, via a pointer variable,
14502 from push_function_context. */
14504 static struct machine_function *
14505 rs6000_init_machine_status (void)
14507 stack_info.reload_completed = 0;
14508 return ggc_alloc_cleared_machine_function ();
14511 /* These macros test for integers and extract the low-order bits. */
14513 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
14514 && GET_MODE (X) == VOIDmode)
14516 #define INT_LOWPART(X) \
14517 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
14520 extract_MB (rtx op)
14523 unsigned long val = INT_LOWPART (op);
14525 /* If the high bit is zero, the value is the first 1 bit we find
14527 if ((val & 0x80000000) == 0)
14529 gcc_assert (val & 0xffffffff);
14532 while (((val <<= 1) & 0x80000000) == 0)
14537 /* If the high bit is set and the low bit is not, or the mask is all
14538 1's, the value is zero. */
14539 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
14542 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14545 while (((val >>= 1) & 1) != 0)
14552 extract_ME (rtx op)
14555 unsigned long val = INT_LOWPART (op);
14557 /* If the low bit is zero, the value is the first 1 bit we find from
14559 if ((val & 1) == 0)
14561 gcc_assert (val & 0xffffffff);
14564 while (((val >>= 1) & 1) == 0)
14570 /* If the low bit is set and the high bit is not, or the mask is all
14571 1's, the value is 31. */
14572 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
14575 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
14578 while (((val <<= 1) & 0x80000000) != 0)
14584 /* Locate some local-dynamic symbol still in use by this function
14585 so that we can print its name in some tls_ld pattern. */
14587 static const char *
14588 rs6000_get_some_local_dynamic_name (void)
14592 if (cfun->machine->some_ld_name)
14593 return cfun->machine->some_ld_name;
14595 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
14597 && for_each_rtx (&PATTERN (insn),
14598 rs6000_get_some_local_dynamic_name_1, 0))
14599 return cfun->machine->some_ld_name;
14601 gcc_unreachable ();
14604 /* Helper function for rs6000_get_some_local_dynamic_name. */
14607 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
14611 if (GET_CODE (x) == SYMBOL_REF)
14613 const char *str = XSTR (x, 0);
14614 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
14616 cfun->machine->some_ld_name = str;
14624 /* Write out a function code label. */
14627 rs6000_output_function_entry (FILE *file, const char *fname)
14629 if (fname[0] != '.')
14631 switch (DEFAULT_ABI)
14634 gcc_unreachable ();
14640 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
14649 RS6000_OUTPUT_BASENAME (file, fname);
14652 /* Print an operand. Recognize special options, documented below. */
14655 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
14656 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
14658 #define SMALL_DATA_RELOC "sda21"
14659 #define SMALL_DATA_REG 0
14663 print_operand (FILE *file, rtx x, int code)
14667 unsigned HOST_WIDE_INT uval;
14672 /* Write out an instruction after the call which may be replaced
14673 with glue code by the loader. This depends on the AIX version. */
14674 asm_fprintf (file, RS6000_CALL_GLUE);
14677 /* %a is output_address. */
14680 /* If X is a constant integer whose low-order 5 bits are zero,
14681 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
14682 in the AIX assembler where "sri" with a zero shift count
14683 writes a trash instruction. */
14684 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
14691 /* If constant, low-order 16 bits of constant, unsigned.
14692 Otherwise, write normally. */
14694 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
14696 print_operand (file, x, 0);
14700 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
14701 for 64-bit mask direction. */
14702 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
14705 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
14709 /* X is a CR register. Print the number of the GT bit of the CR. */
14710 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14711 output_operand_lossage ("invalid %%c value");
14713 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
14717 /* Like 'J' but get to the GT bit only. */
14718 gcc_assert (GET_CODE (x) == REG);
14720 /* Bit 1 is GT bit. */
14721 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
14723 /* Add one for shift count in rlinm for scc. */
14724 fprintf (file, "%d", i + 1);
14728 /* X is a CR register. Print the number of the EQ bit of the CR */
14729 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14730 output_operand_lossage ("invalid %%E value");
14732 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
14736 /* X is a CR register. Print the shift count needed to move it
14737 to the high-order four bits. */
14738 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14739 output_operand_lossage ("invalid %%f value");
14741 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
14745 /* Similar, but print the count for the rotate in the opposite
14747 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14748 output_operand_lossage ("invalid %%F value");
14750 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
14754 /* X is a constant integer. If it is negative, print "m",
14755 otherwise print "z". This is to make an aze or ame insn. */
14756 if (GET_CODE (x) != CONST_INT)
14757 output_operand_lossage ("invalid %%G value");
14758 else if (INTVAL (x) >= 0)
14765 /* If constant, output low-order five bits. Otherwise, write
14768 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
14770 print_operand (file, x, 0);
14774 /* If constant, output low-order six bits. Otherwise, write
14777 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
14779 print_operand (file, x, 0);
14783 /* Print `i' if this is a constant, else nothing. */
14789 /* Write the bit number in CCR for jump. */
14790 i = ccr_bit (x, 0);
14792 output_operand_lossage ("invalid %%j code");
14794 fprintf (file, "%d", i);
14798 /* Similar, but add one for shift count in rlinm for scc and pass
14799 scc flag to `ccr_bit'. */
14800 i = ccr_bit (x, 1);
14802 output_operand_lossage ("invalid %%J code");
14804 /* If we want bit 31, write a shift count of zero, not 32. */
14805 fprintf (file, "%d", i == 31 ? 0 : i + 1);
14809 /* X must be a constant. Write the 1's complement of the
14812 output_operand_lossage ("invalid %%k value");
14814 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
14818 /* X must be a symbolic constant on ELF. Write an
14819 expression suitable for an 'addi' that adds in the low 16
14820 bits of the MEM. */
14821 if (GET_CODE (x) == CONST)
14823 if (GET_CODE (XEXP (x, 0)) != PLUS
14824 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
14825 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
14826 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
14827 output_operand_lossage ("invalid %%K value");
14829 print_operand_address (file, x);
14830 fputs ("@l", file);
14833 /* %l is output_asm_label. */
14836 /* Write second word of DImode or DFmode reference. Works on register
14837 or non-indexed memory only. */
14838 if (GET_CODE (x) == REG)
14839 fputs (reg_names[REGNO (x) + 1], file);
14840 else if (GET_CODE (x) == MEM)
14842 /* Handle possible auto-increment. Since it is pre-increment and
14843 we have already done it, we can just use an offset of word. */
14844 if (GET_CODE (XEXP (x, 0)) == PRE_INC
14845 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
14846 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
14848 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
14849 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
14852 output_address (XEXP (adjust_address_nv (x, SImode,
14856 if (small_data_operand (x, GET_MODE (x)))
14857 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
14858 reg_names[SMALL_DATA_REG]);
14863 /* MB value for a mask operand. */
14864 if (! mask_operand (x, SImode))
14865 output_operand_lossage ("invalid %%m value");
14867 fprintf (file, "%d", extract_MB (x));
14871 /* ME value for a mask operand. */
14872 if (! mask_operand (x, SImode))
14873 output_operand_lossage ("invalid %%M value");
14875 fprintf (file, "%d", extract_ME (x));
14878 /* %n outputs the negative of its operand. */
14881 /* Write the number of elements in the vector times 4. */
14882 if (GET_CODE (x) != PARALLEL)
14883 output_operand_lossage ("invalid %%N value");
14885 fprintf (file, "%d", XVECLEN (x, 0) * 4);
14889 /* Similar, but subtract 1 first. */
14890 if (GET_CODE (x) != PARALLEL)
14891 output_operand_lossage ("invalid %%O value");
14893 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
14897 /* X is a CONST_INT that is a power of two. Output the logarithm. */
14899 || INT_LOWPART (x) < 0
14900 || (i = exact_log2 (INT_LOWPART (x))) < 0)
14901 output_operand_lossage ("invalid %%p value");
14903 fprintf (file, "%d", i);
14907 /* The operand must be an indirect memory reference. The result
14908 is the register name. */
14909 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
14910 || REGNO (XEXP (x, 0)) >= 32)
14911 output_operand_lossage ("invalid %%P value");
14913 fputs (reg_names[REGNO (XEXP (x, 0))], file);
14917 /* This outputs the logical code corresponding to a boolean
14918 expression. The expression may have one or both operands
14919 negated (if one, only the first one). For condition register
14920 logical operations, it will also treat the negated
14921 CR codes as NOTs, but not handle NOTs of them. */
14923 const char *const *t = 0;
14925 enum rtx_code code = GET_CODE (x);
14926 static const char * const tbl[3][3] = {
14927 { "and", "andc", "nor" },
14928 { "or", "orc", "nand" },
14929 { "xor", "eqv", "xor" } };
14933 else if (code == IOR)
14935 else if (code == XOR)
14938 output_operand_lossage ("invalid %%q value");
14940 if (GET_CODE (XEXP (x, 0)) != NOT)
14944 if (GET_CODE (XEXP (x, 1)) == NOT)
14962 /* X is a CR register. Print the mask for `mtcrf'. */
14963 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
14964 output_operand_lossage ("invalid %%R value");
14966 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
14970 /* Low 5 bits of 32 - value */
14972 output_operand_lossage ("invalid %%s value");
14974 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
14978 /* PowerPC64 mask position. All 0's is excluded.
14979 CONST_INT 32-bit mask is considered sign-extended so any
14980 transition must occur within the CONST_INT, not on the boundary. */
14981 if (! mask64_operand (x, DImode))
14982 output_operand_lossage ("invalid %%S value");
14984 uval = INT_LOWPART (x);
14986 if (uval & 1) /* Clear Left */
14988 #if HOST_BITS_PER_WIDE_INT > 64
14989 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
14993 else /* Clear Right */
14996 #if HOST_BITS_PER_WIDE_INT > 64
14997 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
15003 gcc_assert (i >= 0);
15004 fprintf (file, "%d", i);
15008 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
15009 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
15011 /* Bit 3 is OV bit. */
15012 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
15014 /* If we want bit 31, write a shift count of zero, not 32. */
15015 fprintf (file, "%d", i == 31 ? 0 : i + 1);
15019 /* Print the symbolic name of a branch target register. */
15020 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
15021 && REGNO (x) != CTR_REGNO))
15022 output_operand_lossage ("invalid %%T value");
15023 else if (REGNO (x) == LR_REGNO)
15024 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
15026 fputs ("ctr", file);
15030 /* High-order 16 bits of constant for use in unsigned operand. */
15032 output_operand_lossage ("invalid %%u value");
15034 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
15035 (INT_LOWPART (x) >> 16) & 0xffff);
15039 /* High-order 16 bits of constant for use in signed operand. */
15041 output_operand_lossage ("invalid %%v value");
15043 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
15044 (INT_LOWPART (x) >> 16) & 0xffff);
15048 /* Print `u' if this has an auto-increment or auto-decrement. */
15049 if (GET_CODE (x) == MEM
15050 && (GET_CODE (XEXP (x, 0)) == PRE_INC
15051 || GET_CODE (XEXP (x, 0)) == PRE_DEC
15052 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
15057 /* Print the trap code for this operand. */
15058 switch (GET_CODE (x))
15061 fputs ("eq", file); /* 4 */
15064 fputs ("ne", file); /* 24 */
15067 fputs ("lt", file); /* 16 */
15070 fputs ("le", file); /* 20 */
15073 fputs ("gt", file); /* 8 */
15076 fputs ("ge", file); /* 12 */
15079 fputs ("llt", file); /* 2 */
15082 fputs ("lle", file); /* 6 */
15085 fputs ("lgt", file); /* 1 */
15088 fputs ("lge", file); /* 5 */
15091 gcc_unreachable ();
15096 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
15099 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
15100 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
15102 print_operand (file, x, 0);
15106 /* MB value for a PowerPC64 rldic operand. */
15107 val = (GET_CODE (x) == CONST_INT
15108 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
15113 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
15114 if ((val <<= 1) < 0)
15117 #if HOST_BITS_PER_WIDE_INT == 32
15118 if (GET_CODE (x) == CONST_INT && i >= 0)
15119 i += 32; /* zero-extend high-part was all 0's */
15120 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
15122 val = CONST_DOUBLE_LOW (x);
15128 for ( ; i < 64; i++)
15129 if ((val <<= 1) < 0)
15134 fprintf (file, "%d", i + 1);
15138 /* X is a FPR or Altivec register used in a VSX context. */
15139 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
15140 output_operand_lossage ("invalid %%x value");
15143 int reg = REGNO (x);
15144 int vsx_reg = (FP_REGNO_P (reg)
15146 : reg - FIRST_ALTIVEC_REGNO + 32);
15148 #ifdef TARGET_REGNAMES
15149 if (TARGET_REGNAMES)
15150 fprintf (file, "%%vs%d", vsx_reg);
15153 fprintf (file, "%d", vsx_reg);
15158 if (GET_CODE (x) == MEM
15159 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
15160 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
15161 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
15166 /* Like 'L', for third word of TImode */
15167 if (GET_CODE (x) == REG)
15168 fputs (reg_names[REGNO (x) + 2], file);
15169 else if (GET_CODE (x) == MEM)
15171 if (GET_CODE (XEXP (x, 0)) == PRE_INC
15172 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15173 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
15174 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15175 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
15177 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
15178 if (small_data_operand (x, GET_MODE (x)))
15179 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15180 reg_names[SMALL_DATA_REG]);
15185 /* X is a SYMBOL_REF. Write out the name preceded by a
15186 period and without any trailing data in brackets. Used for function
15187 names. If we are configured for System V (or the embedded ABI) on
15188 the PowerPC, do not emit the period, since those systems do not use
15189 TOCs and the like. */
15190 gcc_assert (GET_CODE (x) == SYMBOL_REF);
15192 /* Mark the decl as referenced so that cgraph will output the
15194 if (SYMBOL_REF_DECL (x))
15195 mark_decl_referenced (SYMBOL_REF_DECL (x));
15197 /* For macho, check to see if we need a stub. */
15200 const char *name = XSTR (x, 0);
15202 if (darwin_emit_branch_islands
15203 && MACHOPIC_INDIRECT
15204 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
15205 name = machopic_indirection_name (x, /*stub_p=*/true);
15207 assemble_name (file, name);
15209 else if (!DOT_SYMBOLS)
15210 assemble_name (file, XSTR (x, 0));
15212 rs6000_output_function_entry (file, XSTR (x, 0));
15216 /* Like 'L', for last word of TImode. */
15217 if (GET_CODE (x) == REG)
15218 fputs (reg_names[REGNO (x) + 3], file);
15219 else if (GET_CODE (x) == MEM)
15221 if (GET_CODE (XEXP (x, 0)) == PRE_INC
15222 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
15223 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
15224 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15225 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
15227 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
15228 if (small_data_operand (x, GET_MODE (x)))
15229 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15230 reg_names[SMALL_DATA_REG]);
15234 /* Print AltiVec or SPE memory operand. */
15239 gcc_assert (GET_CODE (x) == MEM);
15243 /* Ugly hack because %y is overloaded. */
15244 if ((TARGET_SPE || TARGET_E500_DOUBLE)
15245 && (GET_MODE_SIZE (GET_MODE (x)) == 8
15246 || GET_MODE (x) == TFmode
15247 || GET_MODE (x) == TImode))
15249 /* Handle [reg]. */
15250 if (GET_CODE (tmp) == REG)
15252 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
15255 /* Handle [reg+UIMM]. */
15256 else if (GET_CODE (tmp) == PLUS &&
15257 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
15261 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
15263 x = INTVAL (XEXP (tmp, 1));
15264 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
15268 /* Fall through. Must be [reg+reg]. */
15270 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
15271 && GET_CODE (tmp) == AND
15272 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
15273 && INTVAL (XEXP (tmp, 1)) == -16)
15274 tmp = XEXP (tmp, 0);
15275 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
15276 && GET_CODE (tmp) == PRE_MODIFY)
15277 tmp = XEXP (tmp, 1);
15278 if (GET_CODE (tmp) == REG)
15279 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
15282 if (!GET_CODE (tmp) == PLUS
15283 || !REG_P (XEXP (tmp, 0))
15284 || !REG_P (XEXP (tmp, 1)))
15286 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
15290 if (REGNO (XEXP (tmp, 0)) == 0)
15291 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
15292 reg_names[ REGNO (XEXP (tmp, 0)) ]);
15294 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
15295 reg_names[ REGNO (XEXP (tmp, 1)) ]);
15301 if (GET_CODE (x) == REG)
15302 fprintf (file, "%s", reg_names[REGNO (x)]);
15303 else if (GET_CODE (x) == MEM)
15305 /* We need to handle PRE_INC and PRE_DEC here, since we need to
15306 know the width from the mode. */
15307 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
15308 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
15309 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15310 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
15311 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
15312 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
15313 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
15314 output_address (XEXP (XEXP (x, 0), 1));
15316 output_address (XEXP (x, 0));
15320 if (toc_relative_expr_p (x))
15321 /* This hack along with a corresponding hack in
15322 rs6000_output_addr_const_extra arranges to output addends
15323 where the assembler expects to find them. eg.
15324 (const (plus (unspec [symbol_ref ("x") tocrel]) 4))
15325 without this hack would be output as "x@toc+4". We
15327 output_addr_const (file, tocrel_base);
15329 output_addr_const (file, x);
15334 assemble_name (file, rs6000_get_some_local_dynamic_name ());
15338 output_operand_lossage ("invalid %%xn code");
15342 /* Print the address of an operand. */
15345 print_operand_address (FILE *file, rtx x)
15347 if (GET_CODE (x) == REG)
15348 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
15349 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
15350 || GET_CODE (x) == LABEL_REF)
15352 output_addr_const (file, x);
15353 if (small_data_operand (x, GET_MODE (x)))
15354 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
15355 reg_names[SMALL_DATA_REG]);
15357 gcc_assert (!TARGET_TOC);
15359 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
15361 gcc_assert (REG_P (XEXP (x, 0)));
15362 if (REGNO (XEXP (x, 0)) == 0)
15363 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
15364 reg_names[ REGNO (XEXP (x, 0)) ]);
15366 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
15367 reg_names[ REGNO (XEXP (x, 1)) ]);
15369 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
15370 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
15371 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
15373 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
15374 && CONSTANT_P (XEXP (x, 1)))
15376 fprintf (file, "lo16(");
15377 output_addr_const (file, XEXP (x, 1));
15378 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15381 else if (legitimate_constant_pool_address_p (x, QImode, true))
15383 /* This hack along with a corresponding hack in
15384 rs6000_output_addr_const_extra arranges to output addends
15385 where the assembler expects to find them. eg.
15387 . (const (plus (unspec [symbol_ref ("x") tocrel]) 8)))
15388 without this hack would be output as "x@toc+8@l(9)". We
15389 want "x+8@toc@l(9)". */
15390 output_addr_const (file, tocrel_base);
15391 if (GET_CODE (x) == LO_SUM)
15392 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15394 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
15397 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
15398 && CONSTANT_P (XEXP (x, 1)))
15400 output_addr_const (file, XEXP (x, 1));
15401 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
15405 gcc_unreachable ();
15408 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
15411 rs6000_output_addr_const_extra (FILE *file, rtx x)
15413 if (GET_CODE (x) == UNSPEC)
15414 switch (XINT (x, 1))
15416 case UNSPEC_TOCREL:
15417 gcc_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF);
15418 output_addr_const (file, XVECEXP (x, 0, 0));
15419 if (x == tocrel_base && tocrel_offset != const0_rtx)
15421 if (INTVAL (tocrel_offset) >= 0)
15422 fprintf (file, "+");
15423 output_addr_const (file, tocrel_offset);
15425 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
15428 assemble_name (file, toc_label_name);
15430 else if (TARGET_ELF)
15431 fputs ("@toc", file);
15435 case UNSPEC_MACHOPIC_OFFSET:
15436 output_addr_const (file, XVECEXP (x, 0, 0));
15438 machopic_output_function_base_name (file);
15445 /* Target hook for assembling integer objects. The PowerPC version has
15446 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
15447 is defined. It also needs to handle DI-mode objects on 64-bit
15451 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
15453 #ifdef RELOCATABLE_NEEDS_FIXUP
15454 /* Special handling for SI values. */
15455 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
15457 static int recurse = 0;
15459 /* For -mrelocatable, we mark all addresses that need to be fixed up
15460 in the .fixup section. */
15461 if (TARGET_RELOCATABLE
15462 && in_section != toc_section
15463 && in_section != text_section
15464 && (in_section && (in_section->common.flags & SECTION_CODE)) == 0
15466 && GET_CODE (x) != CONST_INT
15467 && GET_CODE (x) != CONST_DOUBLE
15473 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
15475 ASM_OUTPUT_LABEL (asm_out_file, buf);
15476 fprintf (asm_out_file, "\t.long\t(");
15477 output_addr_const (asm_out_file, x);
15478 fprintf (asm_out_file, ")@fixup\n");
15479 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
15480 ASM_OUTPUT_ALIGN (asm_out_file, 2);
15481 fprintf (asm_out_file, "\t.long\t");
15482 assemble_name (asm_out_file, buf);
15483 fprintf (asm_out_file, "\n\t.previous\n");
15487 /* Remove initial .'s to turn a -mcall-aixdesc function
15488 address into the address of the descriptor, not the function
15490 else if (GET_CODE (x) == SYMBOL_REF
15491 && XSTR (x, 0)[0] == '.'
15492 && DEFAULT_ABI == ABI_AIX)
15494 const char *name = XSTR (x, 0);
15495 while (*name == '.')
15498 fprintf (asm_out_file, "\t.long\t%s\n", name);
15502 #endif /* RELOCATABLE_NEEDS_FIXUP */
15503 return default_assemble_integer (x, size, aligned_p);
15506 #if defined (HAVE_GAS_HIDDEN) && !defined (TARGET_MACHO)
15507 /* Emit an assembler directive to set symbol visibility for DECL to
15508 VISIBILITY_TYPE. */
15511 rs6000_assemble_visibility (tree decl, int vis)
15513 /* Functions need to have their entry point symbol visibility set as
15514 well as their descriptor symbol visibility. */
15515 if (DEFAULT_ABI == ABI_AIX
15517 && TREE_CODE (decl) == FUNCTION_DECL)
15519 static const char * const visibility_types[] = {
15520 NULL, "internal", "hidden", "protected"
15523 const char *name, *type;
15525 name = ((* targetm.strip_name_encoding)
15526 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
15527 type = visibility_types[vis];
15529 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
15530 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
15533 default_assemble_visibility (decl, vis);
15538 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
15540 /* Reversal of FP compares takes care -- an ordered compare
15541 becomes an unordered compare and vice versa. */
15542 if (mode == CCFPmode
15543 && (!flag_finite_math_only
15544 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
15545 || code == UNEQ || code == LTGT))
15546 return reverse_condition_maybe_unordered (code);
15548 return reverse_condition (code);
15551 /* Generate a compare for CODE. Return a brand-new rtx that
15552 represents the result of the compare. */
15555 rs6000_generate_compare (rtx cmp, enum machine_mode mode)
15557 enum machine_mode comp_mode;
15558 rtx compare_result;
15559 enum rtx_code code = GET_CODE (cmp);
15560 rtx op0 = XEXP (cmp, 0);
15561 rtx op1 = XEXP (cmp, 1);
15563 if (FLOAT_MODE_P (mode))
15564 comp_mode = CCFPmode;
15565 else if (code == GTU || code == LTU
15566 || code == GEU || code == LEU)
15567 comp_mode = CCUNSmode;
15568 else if ((code == EQ || code == NE)
15569 && GET_CODE (op0) == SUBREG
15570 && GET_CODE (op1) == SUBREG
15571 && SUBREG_PROMOTED_UNSIGNED_P (op0)
15572 && SUBREG_PROMOTED_UNSIGNED_P (op1))
15573 /* These are unsigned values, perhaps there will be a later
15574 ordering compare that can be shared with this one.
15575 Unfortunately we cannot detect the signedness of the operands
15576 for non-subregs. */
15577 comp_mode = CCUNSmode;
15579 comp_mode = CCmode;
15581 /* First, the compare. */
15582 compare_result = gen_reg_rtx (comp_mode);
15584 /* E500 FP compare instructions on the GPRs. Yuck! */
15585 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
15586 && FLOAT_MODE_P (mode))
15588 rtx cmp, or_result, compare_result2;
15589 enum machine_mode op_mode = GET_MODE (op0);
15591 if (op_mode == VOIDmode)
15592 op_mode = GET_MODE (op1);
15594 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
15595 This explains the following mess. */
15599 case EQ: case UNEQ: case NE: case LTGT:
15603 cmp = (flag_finite_math_only && !flag_trapping_math)
15604 ? gen_tstsfeq_gpr (compare_result, op0, op1)
15605 : gen_cmpsfeq_gpr (compare_result, op0, op1);
15609 cmp = (flag_finite_math_only && !flag_trapping_math)
15610 ? gen_tstdfeq_gpr (compare_result, op0, op1)
15611 : gen_cmpdfeq_gpr (compare_result, op0, op1);
15615 cmp = (flag_finite_math_only && !flag_trapping_math)
15616 ? gen_tsttfeq_gpr (compare_result, op0, op1)
15617 : gen_cmptfeq_gpr (compare_result, op0, op1);
15621 gcc_unreachable ();
15625 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
15629 cmp = (flag_finite_math_only && !flag_trapping_math)
15630 ? gen_tstsfgt_gpr (compare_result, op0, op1)
15631 : gen_cmpsfgt_gpr (compare_result, op0, op1);
15635 cmp = (flag_finite_math_only && !flag_trapping_math)
15636 ? gen_tstdfgt_gpr (compare_result, op0, op1)
15637 : gen_cmpdfgt_gpr (compare_result, op0, op1);
15641 cmp = (flag_finite_math_only && !flag_trapping_math)
15642 ? gen_tsttfgt_gpr (compare_result, op0, op1)
15643 : gen_cmptfgt_gpr (compare_result, op0, op1);
15647 gcc_unreachable ();
15651 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
15655 cmp = (flag_finite_math_only && !flag_trapping_math)
15656 ? gen_tstsflt_gpr (compare_result, op0, op1)
15657 : gen_cmpsflt_gpr (compare_result, op0, op1);
15661 cmp = (flag_finite_math_only && !flag_trapping_math)
15662 ? gen_tstdflt_gpr (compare_result, op0, op1)
15663 : gen_cmpdflt_gpr (compare_result, op0, op1);
15667 cmp = (flag_finite_math_only && !flag_trapping_math)
15668 ? gen_tsttflt_gpr (compare_result, op0, op1)
15669 : gen_cmptflt_gpr (compare_result, op0, op1);
15673 gcc_unreachable ();
15677 gcc_unreachable ();
15680 /* Synthesize LE and GE from LT/GT || EQ. */
15681 if (code == LE || code == GE || code == LEU || code == GEU)
15687 case LE: code = LT; break;
15688 case GE: code = GT; break;
15689 case LEU: code = LT; break;
15690 case GEU: code = GT; break;
15691 default: gcc_unreachable ();
15694 compare_result2 = gen_reg_rtx (CCFPmode);
15700 cmp = (flag_finite_math_only && !flag_trapping_math)
15701 ? gen_tstsfeq_gpr (compare_result2, op0, op1)
15702 : gen_cmpsfeq_gpr (compare_result2, op0, op1);
15706 cmp = (flag_finite_math_only && !flag_trapping_math)
15707 ? gen_tstdfeq_gpr (compare_result2, op0, op1)
15708 : gen_cmpdfeq_gpr (compare_result2, op0, op1);
15712 cmp = (flag_finite_math_only && !flag_trapping_math)
15713 ? gen_tsttfeq_gpr (compare_result2, op0, op1)
15714 : gen_cmptfeq_gpr (compare_result2, op0, op1);
15718 gcc_unreachable ();
15722 /* OR them together. */
15723 or_result = gen_reg_rtx (CCFPmode);
15724 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
15726 compare_result = or_result;
15731 if (code == NE || code == LTGT)
15741 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
15742 CLOBBERs to match cmptf_internal2 pattern. */
15743 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
15744 && GET_MODE (op0) == TFmode
15745 && !TARGET_IEEEQUAD
15746 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
15747 emit_insn (gen_rtx_PARALLEL (VOIDmode,
15749 gen_rtx_SET (VOIDmode,
15751 gen_rtx_COMPARE (comp_mode, op0, op1)),
15752 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15753 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15754 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15755 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15756 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15757 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15758 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15759 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
15760 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
15761 else if (GET_CODE (op1) == UNSPEC
15762 && XINT (op1, 1) == UNSPEC_SP_TEST)
15764 rtx op1b = XVECEXP (op1, 0, 0);
15765 comp_mode = CCEQmode;
15766 compare_result = gen_reg_rtx (CCEQmode);
15768 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
15770 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
15773 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
15774 gen_rtx_COMPARE (comp_mode, op0, op1)));
15777 /* Some kinds of FP comparisons need an OR operation;
15778 under flag_finite_math_only we don't bother. */
15779 if (FLOAT_MODE_P (mode)
15780 && !flag_finite_math_only
15781 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
15782 && (code == LE || code == GE
15783 || code == UNEQ || code == LTGT
15784 || code == UNGT || code == UNLT))
15786 enum rtx_code or1, or2;
15787 rtx or1_rtx, or2_rtx, compare2_rtx;
15788 rtx or_result = gen_reg_rtx (CCEQmode);
15792 case LE: or1 = LT; or2 = EQ; break;
15793 case GE: or1 = GT; or2 = EQ; break;
15794 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
15795 case LTGT: or1 = LT; or2 = GT; break;
15796 case UNGT: or1 = UNORDERED; or2 = GT; break;
15797 case UNLT: or1 = UNORDERED; or2 = LT; break;
15798 default: gcc_unreachable ();
15800 validate_condition_mode (or1, comp_mode);
15801 validate_condition_mode (or2, comp_mode);
15802 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
15803 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
15804 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
15805 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
15807 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
15809 compare_result = or_result;
15813 validate_condition_mode (code, GET_MODE (compare_result));
15815 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
15819 /* Emit the RTL for an sISEL pattern. */
15822 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED, rtx operands[])
15824 rs6000_emit_int_cmove (operands[0], operands[1], const1_rtx, const0_rtx);
15828 rs6000_emit_sCOND (enum machine_mode mode, rtx operands[])
15831 enum machine_mode op_mode;
15832 enum rtx_code cond_code;
15833 rtx result = operands[0];
15835 if (TARGET_ISEL && (mode == SImode || mode == DImode))
15837 rs6000_emit_sISEL (mode, operands);
15841 condition_rtx = rs6000_generate_compare (operands[1], mode);
15842 cond_code = GET_CODE (condition_rtx);
15844 if (FLOAT_MODE_P (mode)
15845 && !TARGET_FPRS && TARGET_HARD_FLOAT)
15849 PUT_MODE (condition_rtx, SImode);
15850 t = XEXP (condition_rtx, 0);
15852 gcc_assert (cond_code == NE || cond_code == EQ);
15854 if (cond_code == NE)
15855 emit_insn (gen_e500_flip_gt_bit (t, t));
15857 emit_insn (gen_move_from_CR_gt_bit (result, t));
15861 if (cond_code == NE
15862 || cond_code == GE || cond_code == LE
15863 || cond_code == GEU || cond_code == LEU
15864 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
15866 rtx not_result = gen_reg_rtx (CCEQmode);
15867 rtx not_op, rev_cond_rtx;
15868 enum machine_mode cc_mode;
15870 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
15872 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
15873 SImode, XEXP (condition_rtx, 0), const0_rtx);
15874 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
15875 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
15876 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
15879 op_mode = GET_MODE (XEXP (operands[1], 0));
15880 if (op_mode == VOIDmode)
15881 op_mode = GET_MODE (XEXP (operands[1], 1));
15883 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
15885 PUT_MODE (condition_rtx, DImode);
15886 convert_move (result, condition_rtx, 0);
15890 PUT_MODE (condition_rtx, SImode);
15891 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
15895 /* Emit a branch of kind CODE to location LOC. */
15898 rs6000_emit_cbranch (enum machine_mode mode, rtx operands[])
15900 rtx condition_rtx, loc_ref;
15902 condition_rtx = rs6000_generate_compare (operands[0], mode);
15903 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
15904 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
15905 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
15906 loc_ref, pc_rtx)));
15909 /* Return the string to output a conditional branch to LABEL, which is
15910 the operand number of the label, or -1 if the branch is really a
15911 conditional return.
15913 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
15914 condition code register and its mode specifies what kind of
15915 comparison we made.
15917 REVERSED is nonzero if we should reverse the sense of the comparison.
15919 INSN is the insn. */
15922 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
15924 static char string[64];
15925 enum rtx_code code = GET_CODE (op);
15926 rtx cc_reg = XEXP (op, 0);
15927 enum machine_mode mode = GET_MODE (cc_reg);
15928 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
15929 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
15930 int really_reversed = reversed ^ need_longbranch;
15936 validate_condition_mode (code, mode);
15938 /* Work out which way this really branches. We could use
15939 reverse_condition_maybe_unordered here always but this
15940 makes the resulting assembler clearer. */
15941 if (really_reversed)
15943 /* Reversal of FP compares takes care -- an ordered compare
15944 becomes an unordered compare and vice versa. */
15945 if (mode == CCFPmode)
15946 code = reverse_condition_maybe_unordered (code);
15948 code = reverse_condition (code);
15951 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
15953 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
15958 /* Opposite of GT. */
15967 gcc_unreachable ();
15973 /* Not all of these are actually distinct opcodes, but
15974 we distinguish them for clarity of the resulting assembler. */
15975 case NE: case LTGT:
15976 ccode = "ne"; break;
15977 case EQ: case UNEQ:
15978 ccode = "eq"; break;
15980 ccode = "ge"; break;
15981 case GT: case GTU: case UNGT:
15982 ccode = "gt"; break;
15984 ccode = "le"; break;
15985 case LT: case LTU: case UNLT:
15986 ccode = "lt"; break;
15987 case UNORDERED: ccode = "un"; break;
15988 case ORDERED: ccode = "nu"; break;
15989 case UNGE: ccode = "nl"; break;
15990 case UNLE: ccode = "ng"; break;
15992 gcc_unreachable ();
15995 /* Maybe we have a guess as to how likely the branch is.
15996 The old mnemonics don't have a way to specify this information. */
15998 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
15999 if (note != NULL_RTX)
16001 /* PROB is the difference from 50%. */
16002 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
16004 /* Only hint for highly probable/improbable branches on newer
16005 cpus as static prediction overrides processor dynamic
16006 prediction. For older cpus we may as well always hint, but
16007 assume not taken for branches that are very close to 50% as a
16008 mispredicted taken branch is more expensive than a
16009 mispredicted not-taken branch. */
16010 if (rs6000_always_hint
16011 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
16012 && br_prob_note_reliable_p (note)))
16014 if (abs (prob) > REG_BR_PROB_BASE / 20
16015 && ((prob > 0) ^ need_longbranch))
16023 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
16025 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
16027 /* We need to escape any '%' characters in the reg_names string.
16028 Assume they'd only be the first character.... */
16029 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
16031 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
16035 /* If the branch distance was too far, we may have to use an
16036 unconditional branch to go the distance. */
16037 if (need_longbranch)
16038 s += sprintf (s, ",$+8\n\tb %s", label);
16040 s += sprintf (s, ",%s", label);
16046 /* Return the string to flip the GT bit on a CR. */
16048 output_e500_flip_gt_bit (rtx dst, rtx src)
16050 static char string[64];
16053 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
16054 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
16057 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
16058 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
16060 sprintf (string, "crnot %d,%d", a, b);
16064 /* Return insn for VSX or Altivec comparisons. */
16067 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
16070 enum machine_mode mode = GET_MODE (op0);
16078 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
16084 mask = gen_reg_rtx (mode);
16085 emit_insn (gen_rtx_SET (VOIDmode,
16087 gen_rtx_fmt_ee (code, mode, op0, op1)));
16094 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
16095 DMODE is expected destination mode. This is a recursive function. */
16098 rs6000_emit_vector_compare (enum rtx_code rcode,
16100 enum machine_mode dmode)
16103 bool swap_operands = false;
16104 bool try_again = false;
16106 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
16107 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
16109 /* See if the comparison works as is. */
16110 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
16118 swap_operands = true;
16123 swap_operands = true;
16131 /* Invert condition and try again.
16132 e.g., A != B becomes ~(A==B). */
16134 enum rtx_code rev_code;
16135 enum insn_code nor_code;
16138 rev_code = reverse_condition_maybe_unordered (rcode);
16139 if (rev_code == UNKNOWN)
16142 nor_code = optab_handler (one_cmpl_optab, dmode);
16143 if (nor_code == CODE_FOR_nothing)
16146 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
16150 mask = gen_reg_rtx (dmode);
16151 emit_insn (GEN_FCN (nor_code) (mask, mask2));
16159 /* Try GT/GTU/LT/LTU OR EQ */
16162 enum insn_code ior_code;
16163 enum rtx_code new_code;
16184 gcc_unreachable ();
16187 ior_code = optab_handler (ior_optab, dmode);
16188 if (ior_code == CODE_FOR_nothing)
16191 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
16195 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
16199 mask = gen_reg_rtx (dmode);
16200 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
16218 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
16223 /* You only get two chances. */
16227 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
16228 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
16229 operands for the relation operation COND. */
16232 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
16233 rtx cond, rtx cc_op0, rtx cc_op1)
16235 enum machine_mode dest_mode = GET_MODE (dest);
16236 enum machine_mode mask_mode = GET_MODE (cc_op0);
16237 enum rtx_code rcode = GET_CODE (cond);
16238 enum machine_mode cc_mode = CCmode;
16242 bool invert_move = false;
16244 if (VECTOR_UNIT_NONE_P (dest_mode))
16247 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
16248 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
16252 /* Swap operands if we can, and fall back to doing the operation as
16253 specified, and doing a NOR to invert the test. */
16259 /* Invert condition and try again.
16260 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
16261 invert_move = true;
16262 rcode = reverse_condition_maybe_unordered (rcode);
16263 if (rcode == UNKNOWN)
16267 /* Mark unsigned tests with CCUNSmode. */
16272 cc_mode = CCUNSmode;
16279 /* Get the vector mask for the given relational operations. */
16280 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
16288 op_true = op_false;
16292 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
16293 CONST0_RTX (dest_mode));
16294 emit_insn (gen_rtx_SET (VOIDmode,
16296 gen_rtx_IF_THEN_ELSE (dest_mode,
16303 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
16304 operands of the last comparison is nonzero/true, FALSE_COND if it
16305 is zero/false. Return 0 if the hardware has no such operation. */
16308 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16310 enum rtx_code code = GET_CODE (op);
16311 rtx op0 = XEXP (op, 0);
16312 rtx op1 = XEXP (op, 1);
16313 REAL_VALUE_TYPE c1;
16314 enum machine_mode compare_mode = GET_MODE (op0);
16315 enum machine_mode result_mode = GET_MODE (dest);
16317 bool is_against_zero;
16319 /* These modes should always match. */
16320 if (GET_MODE (op1) != compare_mode
16321 /* In the isel case however, we can use a compare immediate, so
16322 op1 may be a small constant. */
16323 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
16325 if (GET_MODE (true_cond) != result_mode)
16327 if (GET_MODE (false_cond) != result_mode)
16330 /* First, work out if the hardware can do this at all, or
16331 if it's too slow.... */
16332 if (!FLOAT_MODE_P (compare_mode))
16335 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
16338 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
16339 && SCALAR_FLOAT_MODE_P (compare_mode))
16342 is_against_zero = op1 == CONST0_RTX (compare_mode);
16344 /* A floating-point subtract might overflow, underflow, or produce
16345 an inexact result, thus changing the floating-point flags, so it
16346 can't be generated if we care about that. It's safe if one side
16347 of the construct is zero, since then no subtract will be
16349 if (SCALAR_FLOAT_MODE_P (compare_mode)
16350 && flag_trapping_math && ! is_against_zero)
16353 /* Eliminate half of the comparisons by switching operands, this
16354 makes the remaining code simpler. */
16355 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
16356 || code == LTGT || code == LT || code == UNLE)
16358 code = reverse_condition_maybe_unordered (code);
16360 true_cond = false_cond;
16364 /* UNEQ and LTGT take four instructions for a comparison with zero,
16365 it'll probably be faster to use a branch here too. */
16366 if (code == UNEQ && HONOR_NANS (compare_mode))
16369 if (GET_CODE (op1) == CONST_DOUBLE)
16370 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
16372 /* We're going to try to implement comparisons by performing
16373 a subtract, then comparing against zero. Unfortunately,
16374 Inf - Inf is NaN which is not zero, and so if we don't
16375 know that the operand is finite and the comparison
16376 would treat EQ different to UNORDERED, we can't do it. */
16377 if (HONOR_INFINITIES (compare_mode)
16378 && code != GT && code != UNGE
16379 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
16380 /* Constructs of the form (a OP b ? a : b) are safe. */
16381 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
16382 || (! rtx_equal_p (op0, true_cond)
16383 && ! rtx_equal_p (op1, true_cond))))
16386 /* At this point we know we can use fsel. */
16388 /* Reduce the comparison to a comparison against zero. */
16389 if (! is_against_zero)
16391 temp = gen_reg_rtx (compare_mode);
16392 emit_insn (gen_rtx_SET (VOIDmode, temp,
16393 gen_rtx_MINUS (compare_mode, op0, op1)));
16395 op1 = CONST0_RTX (compare_mode);
16398 /* If we don't care about NaNs we can reduce some of the comparisons
16399 down to faster ones. */
16400 if (! HONOR_NANS (compare_mode))
16406 true_cond = false_cond;
16419 /* Now, reduce everything down to a GE. */
16426 temp = gen_reg_rtx (compare_mode);
16427 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16432 temp = gen_reg_rtx (compare_mode);
16433 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
16438 temp = gen_reg_rtx (compare_mode);
16439 emit_insn (gen_rtx_SET (VOIDmode, temp,
16440 gen_rtx_NEG (compare_mode,
16441 gen_rtx_ABS (compare_mode, op0))));
16446 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
16447 temp = gen_reg_rtx (result_mode);
16448 emit_insn (gen_rtx_SET (VOIDmode, temp,
16449 gen_rtx_IF_THEN_ELSE (result_mode,
16450 gen_rtx_GE (VOIDmode,
16452 true_cond, false_cond)));
16453 false_cond = true_cond;
16456 temp = gen_reg_rtx (compare_mode);
16457 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16462 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
16463 temp = gen_reg_rtx (result_mode);
16464 emit_insn (gen_rtx_SET (VOIDmode, temp,
16465 gen_rtx_IF_THEN_ELSE (result_mode,
16466 gen_rtx_GE (VOIDmode,
16468 true_cond, false_cond)));
16469 true_cond = false_cond;
16472 temp = gen_reg_rtx (compare_mode);
16473 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
16478 gcc_unreachable ();
16481 emit_insn (gen_rtx_SET (VOIDmode, dest,
16482 gen_rtx_IF_THEN_ELSE (result_mode,
16483 gen_rtx_GE (VOIDmode,
16485 true_cond, false_cond)));
16489 /* Same as above, but for ints (isel). */
16492 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
16494 rtx condition_rtx, cr;
16495 enum machine_mode mode = GET_MODE (dest);
16496 enum rtx_code cond_code;
16497 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
16500 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
16503 /* We still have to do the compare, because isel doesn't do a
16504 compare, it just looks at the CRx bits set by a previous compare
16506 condition_rtx = rs6000_generate_compare (op, mode);
16507 cond_code = GET_CODE (condition_rtx);
16508 cr = XEXP (condition_rtx, 0);
16509 signedp = GET_MODE (cr) == CCmode;
16511 isel_func = (mode == SImode
16512 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
16513 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
16517 case LT: case GT: case LTU: case GTU: case EQ:
16518 /* isel handles these directly. */
16522 /* We need to swap the sense of the comparison. */
16525 true_cond = false_cond;
16527 PUT_CODE (condition_rtx, reverse_condition (cond_code));
16532 false_cond = force_reg (mode, false_cond);
16533 if (true_cond != const0_rtx)
16534 true_cond = force_reg (mode, true_cond);
16536 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
16542 output_isel (rtx *operands)
16544 enum rtx_code code;
16546 code = GET_CODE (operands[1]);
16548 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
16550 gcc_assert (GET_CODE (operands[2]) == REG
16551 && GET_CODE (operands[3]) == REG);
16552 PUT_CODE (operands[1], reverse_condition (code));
16553 return "isel %0,%3,%2,%j1";
16556 return "isel %0,%2,%3,%j1";
16560 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
16562 enum machine_mode mode = GET_MODE (op0);
16566 /* VSX/altivec have direct min/max insns. */
16567 if ((code == SMAX || code == SMIN)
16568 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
16569 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
16571 emit_insn (gen_rtx_SET (VOIDmode,
16573 gen_rtx_fmt_ee (code, mode, op0, op1)));
16577 if (code == SMAX || code == SMIN)
16582 if (code == SMAX || code == UMAX)
16583 target = emit_conditional_move (dest, c, op0, op1, mode,
16584 op0, op1, mode, 0);
16586 target = emit_conditional_move (dest, c, op0, op1, mode,
16587 op1, op0, mode, 0);
16588 gcc_assert (target);
16589 if (target != dest)
16590 emit_move_insn (dest, target);
16593 /* A subroutine of the atomic operation splitters. Jump to LABEL if
16594 COND is true. Mark the jump as unlikely to be taken. */
16597 emit_unlikely_jump (rtx cond, rtx label)
16599 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
16602 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
16603 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
16604 add_reg_note (x, REG_BR_PROB, very_unlikely);
16607 /* A subroutine of the atomic operation splitters. Emit a load-locked
16608 instruction in MODE. */
16611 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
16613 rtx (*fn) (rtx, rtx) = NULL;
16618 fn = gen_load_lockedsi;
16621 fn = gen_load_lockeddi;
16624 gcc_unreachable ();
16626 emit_insn (fn (reg, mem));
16629 /* A subroutine of the atomic operation splitters. Emit a store-conditional
16630 instruction in MODE. */
16633 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
16635 rtx (*fn) (rtx, rtx, rtx) = NULL;
16640 fn = gen_store_conditionalsi;
16643 fn = gen_store_conditionaldi;
16646 gcc_unreachable ();
16649 /* Emit sync before stwcx. to address PPC405 Erratum. */
16650 if (PPC405_ERRATUM77)
16651 emit_insn (gen_hwsync ());
16653 emit_insn (fn (res, mem, val));
16656 /* Expand barriers before and after a load_locked/store_cond sequence. */
16659 rs6000_pre_atomic_barrier (enum memmodel model)
16663 case MEMMODEL_RELAXED:
16664 case MEMMODEL_CONSUME:
16665 case MEMMODEL_ACQUIRE:
16667 case MEMMODEL_RELEASE:
16668 case MEMMODEL_ACQ_REL:
16669 emit_insn (gen_lwsync ());
16671 case MEMMODEL_SEQ_CST:
16672 emit_insn (gen_hwsync ());
16675 gcc_unreachable ();
16680 rs6000_post_atomic_barrier (enum memmodel model)
16684 case MEMMODEL_RELAXED:
16685 case MEMMODEL_CONSUME:
16686 case MEMMODEL_RELEASE:
16688 case MEMMODEL_ACQUIRE:
16689 case MEMMODEL_ACQ_REL:
16690 case MEMMODEL_SEQ_CST:
16691 emit_insn (gen_isync ());
16694 gcc_unreachable ();
16698 /* A subroutine of the various atomic expanders. For sub-word operations,
16699 we must adjust things to operate on SImode. Given the original MEM,
16700 return a new aligned memory. Also build and return the quantities by
16701 which to shift and mask. */
16704 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
16706 rtx addr, align, shift, mask, mem;
16707 HOST_WIDE_INT shift_mask;
16708 enum machine_mode mode = GET_MODE (orig_mem);
16710 /* For smaller modes, we have to implement this via SImode. */
16711 shift_mask = (mode == QImode ? 0x18 : 0x10);
16713 addr = XEXP (orig_mem, 0);
16714 addr = force_reg (GET_MODE (addr), addr);
16716 /* Aligned memory containing subword. Generate a new memory. We
16717 do not want any of the existing MEM_ATTR data, as we're now
16718 accessing memory outside the original object. */
16719 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
16720 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16721 mem = gen_rtx_MEM (SImode, align);
16722 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
16723 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
16724 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
16726 /* Shift amount for subword relative to aligned word. */
16727 shift = gen_reg_rtx (SImode);
16728 addr = gen_lowpart (SImode, addr);
16729 emit_insn (gen_rlwinm (shift, addr, GEN_INT (3), GEN_INT (shift_mask)));
16730 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
16731 shift, 1, OPTAB_LIB_WIDEN);
16734 /* Mask for insertion. */
16735 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
16736 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
16742 /* A subroutine of the various atomic expanders. For sub-word operands,
16743 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
16746 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
16750 x = gen_reg_rtx (SImode);
16751 emit_insn (gen_rtx_SET (VOIDmode, x,
16752 gen_rtx_AND (SImode,
16753 gen_rtx_NOT (SImode, mask),
16756 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
16761 /* A subroutine of the various atomic expanders. For sub-word operands,
16762 extract WIDE to NARROW via SHIFT. */
16765 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
16767 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
16768 wide, 1, OPTAB_LIB_WIDEN);
16769 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
16772 /* Expand an atomic compare and swap operation. */
16775 rs6000_expand_atomic_compare_and_swap (rtx operands[])
16777 rtx boolval, retval, mem, oldval, newval, cond;
16778 rtx label1, label2, x, mask, shift;
16779 enum machine_mode mode;
16780 enum memmodel mod_s, mod_f;
16783 boolval = operands[0];
16784 retval = operands[1];
16786 oldval = operands[3];
16787 newval = operands[4];
16788 is_weak = (INTVAL (operands[5]) != 0);
16789 mod_s = (enum memmodel) INTVAL (operands[6]);
16790 mod_f = (enum memmodel) INTVAL (operands[7]);
16791 mode = GET_MODE (mem);
16793 mask = shift = NULL_RTX;
16794 if (mode == QImode || mode == HImode)
16796 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16798 /* Shift and mask OLDVAL into position with the word. */
16799 oldval = convert_modes (SImode, mode, oldval, 1);
16800 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
16801 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16803 /* Shift and mask NEWVAL into position within the word. */
16804 newval = convert_modes (SImode, mode, newval, 1);
16805 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
16806 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16808 /* Prepare to adjust the return value. */
16809 retval = gen_reg_rtx (SImode);
16812 else if (reg_overlap_mentioned_p (retval, oldval))
16813 oldval = copy_to_reg (oldval);
16815 rs6000_pre_atomic_barrier (mod_s);
16820 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16821 emit_label (XEXP (label1, 0));
16823 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16825 emit_load_locked (mode, retval, mem);
16830 x = expand_simple_binop (SImode, AND, retval, mask,
16831 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16834 cond = gen_reg_rtx (CCmode);
16835 x = gen_rtx_COMPARE (CCmode, x, oldval);
16836 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
16838 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16839 emit_unlikely_jump (x, label2);
16843 x = rs6000_mask_atomic_subword (retval, newval, mask);
16845 emit_store_conditional (mode, cond, mem, x);
16849 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16850 emit_unlikely_jump (x, label1);
16853 if (mod_f != MEMMODEL_RELAXED)
16854 emit_label (XEXP (label2, 0));
16856 rs6000_post_atomic_barrier (mod_s);
16858 if (mod_f == MEMMODEL_RELAXED)
16859 emit_label (XEXP (label2, 0));
16862 rs6000_finish_atomic_subword (operands[1], retval, shift);
16864 /* In all cases, CR0 contains EQ on success, and NE on failure. */
16865 x = gen_rtx_EQ (SImode, cond, const0_rtx);
16866 emit_insn (gen_rtx_SET (VOIDmode, boolval, x));
16869 /* Expand an atomic exchange operation. */
16872 rs6000_expand_atomic_exchange (rtx operands[])
16874 rtx retval, mem, val, cond;
16875 enum machine_mode mode;
16876 enum memmodel model;
16877 rtx label, x, mask, shift;
16879 retval = operands[0];
16882 model = (enum memmodel) INTVAL (operands[3]);
16883 mode = GET_MODE (mem);
16885 mask = shift = NULL_RTX;
16886 if (mode == QImode || mode == HImode)
16888 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16890 /* Shift and mask VAL into position with the word. */
16891 val = convert_modes (SImode, mode, val, 1);
16892 val = expand_simple_binop (SImode, ASHIFT, val, shift,
16893 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16895 /* Prepare to adjust the return value. */
16896 retval = gen_reg_rtx (SImode);
16900 rs6000_pre_atomic_barrier (model);
16902 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
16903 emit_label (XEXP (label, 0));
16905 emit_load_locked (mode, retval, mem);
16909 x = rs6000_mask_atomic_subword (retval, val, mask);
16911 cond = gen_reg_rtx (CCmode);
16912 emit_store_conditional (mode, cond, mem, x);
16914 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
16915 emit_unlikely_jump (x, label);
16917 rs6000_post_atomic_barrier (model);
16920 rs6000_finish_atomic_subword (operands[0], retval, shift);
16923 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
16924 to perform. MEM is the memory on which to operate. VAL is the second
16925 operand of the binary operator. BEFORE and AFTER are optional locations to
16926 return the value of MEM either before of after the operation. MODEL_RTX
16927 is a CONST_INT containing the memory model to use. */
16930 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
16931 rtx orig_before, rtx orig_after, rtx model_rtx)
16933 enum memmodel model = (enum memmodel) INTVAL (model_rtx);
16934 enum machine_mode mode = GET_MODE (mem);
16935 rtx label, x, cond, mask, shift;
16936 rtx before = orig_before, after = orig_after;
16938 mask = shift = NULL_RTX;
16939 if (mode == QImode || mode == HImode)
16941 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
16943 /* Shift and mask VAL into position with the word. */
16944 val = convert_modes (SImode, mode, val, 1);
16945 val = expand_simple_binop (SImode, ASHIFT, val, shift,
16946 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16952 /* We've already zero-extended VAL. That is sufficient to
16953 make certain that it does not affect other bits. */
16958 /* If we make certain that all of the other bits in VAL are
16959 set, that will be sufficient to not affect other bits. */
16960 x = gen_rtx_NOT (SImode, mask);
16961 x = gen_rtx_IOR (SImode, x, val);
16962 emit_insn (gen_rtx_SET (VOIDmode, val, x));
16969 /* These will all affect bits outside the field and need
16970 adjustment via MASK within the loop. */
16974 gcc_unreachable ();
16977 /* Prepare to adjust the return value. */
16978 before = gen_reg_rtx (SImode);
16980 after = gen_reg_rtx (SImode);
16984 rs6000_pre_atomic_barrier (model);
16986 label = gen_label_rtx ();
16987 emit_label (label);
16988 label = gen_rtx_LABEL_REF (VOIDmode, label);
16990 if (before == NULL_RTX)
16991 before = gen_reg_rtx (mode);
16993 emit_load_locked (mode, before, mem);
16997 x = expand_simple_binop (mode, AND, before, val,
16998 NULL_RTX, 1, OPTAB_LIB_WIDEN);
16999 after = expand_simple_unop (mode, NOT, x, after, 1);
17003 after = expand_simple_binop (mode, code, before, val,
17004 after, 1, OPTAB_LIB_WIDEN);
17010 x = expand_simple_binop (SImode, AND, after, mask,
17011 NULL_RTX, 1, OPTAB_LIB_WIDEN);
17012 x = rs6000_mask_atomic_subword (before, x, mask);
17015 cond = gen_reg_rtx (CCmode);
17016 emit_store_conditional (mode, cond, mem, x);
17018 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
17019 emit_unlikely_jump (x, label);
17021 rs6000_post_atomic_barrier (model);
17026 rs6000_finish_atomic_subword (orig_before, before, shift);
17028 rs6000_finish_atomic_subword (orig_after, after, shift);
17030 else if (orig_after && after != orig_after)
17031 emit_move_insn (orig_after, after);
17034 /* Emit instructions to move SRC to DST. Called by splitters for
17035 multi-register moves. It will emit at most one instruction for
17036 each register that is accessed; that is, it won't emit li/lis pairs
17037 (or equivalent for 64-bit code). One of SRC or DST must be a hard
17041 rs6000_split_multireg_move (rtx dst, rtx src)
17043 /* The register number of the first register being moved. */
17045 /* The mode that is to be moved. */
17046 enum machine_mode mode;
17047 /* The mode that the move is being done in, and its size. */
17048 enum machine_mode reg_mode;
17050 /* The number of registers that will be moved. */
17053 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
17054 mode = GET_MODE (dst);
17055 nregs = hard_regno_nregs[reg][mode];
17056 if (FP_REGNO_P (reg))
17057 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
17058 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
17059 else if (ALTIVEC_REGNO_P (reg))
17060 reg_mode = V16QImode;
17061 else if (TARGET_E500_DOUBLE && mode == TFmode)
17064 reg_mode = word_mode;
17065 reg_mode_size = GET_MODE_SIZE (reg_mode);
17067 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
17069 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
17071 /* Move register range backwards, if we might have destructive
17074 for (i = nregs - 1; i >= 0; i--)
17075 emit_insn (gen_rtx_SET (VOIDmode,
17076 simplify_gen_subreg (reg_mode, dst, mode,
17077 i * reg_mode_size),
17078 simplify_gen_subreg (reg_mode, src, mode,
17079 i * reg_mode_size)));
17085 bool used_update = false;
17086 rtx restore_basereg = NULL_RTX;
17088 if (MEM_P (src) && INT_REGNO_P (reg))
17092 if (GET_CODE (XEXP (src, 0)) == PRE_INC
17093 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
17096 breg = XEXP (XEXP (src, 0), 0);
17097 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
17098 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
17099 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
17100 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
17101 src = replace_equiv_address (src, breg);
17103 else if (! rs6000_offsettable_memref_p (src))
17105 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
17107 rtx basereg = XEXP (XEXP (src, 0), 0);
17110 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
17111 emit_insn (gen_rtx_SET (VOIDmode, ndst,
17112 gen_rtx_MEM (reg_mode, XEXP (src, 0))));
17113 used_update = true;
17116 emit_insn (gen_rtx_SET (VOIDmode, basereg,
17117 XEXP (XEXP (src, 0), 1)));
17118 src = replace_equiv_address (src, basereg);
17122 rtx basereg = gen_rtx_REG (Pmode, reg);
17123 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
17124 src = replace_equiv_address (src, basereg);
17128 breg = XEXP (src, 0);
17129 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
17130 breg = XEXP (breg, 0);
17132 /* If the base register we are using to address memory is
17133 also a destination reg, then change that register last. */
17135 && REGNO (breg) >= REGNO (dst)
17136 && REGNO (breg) < REGNO (dst) + nregs)
17137 j = REGNO (breg) - REGNO (dst);
17139 else if (MEM_P (dst) && INT_REGNO_P (reg))
17143 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
17144 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
17147 breg = XEXP (XEXP (dst, 0), 0);
17148 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
17149 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
17150 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
17152 /* We have to update the breg before doing the store.
17153 Use store with update, if available. */
17157 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
17158 emit_insn (TARGET_32BIT
17159 ? (TARGET_POWERPC64
17160 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
17161 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
17162 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
17163 used_update = true;
17166 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
17167 dst = replace_equiv_address (dst, breg);
17169 else if (!rs6000_offsettable_memref_p (dst)
17170 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
17172 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
17174 rtx basereg = XEXP (XEXP (dst, 0), 0);
17177 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
17178 emit_insn (gen_rtx_SET (VOIDmode,
17179 gen_rtx_MEM (reg_mode, XEXP (dst, 0)), nsrc));
17180 used_update = true;
17183 emit_insn (gen_rtx_SET (VOIDmode, basereg,
17184 XEXP (XEXP (dst, 0), 1)));
17185 dst = replace_equiv_address (dst, basereg);
17189 rtx basereg = XEXP (XEXP (dst, 0), 0);
17190 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
17191 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
17193 && REG_P (offsetreg)
17194 && REGNO (basereg) != REGNO (offsetreg));
17195 if (REGNO (basereg) == 0)
17197 rtx tmp = offsetreg;
17198 offsetreg = basereg;
17201 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
17202 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
17203 dst = replace_equiv_address (dst, basereg);
17206 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
17207 gcc_assert (rs6000_offsettable_memref_p (dst));
17210 for (i = 0; i < nregs; i++)
17212 /* Calculate index to next subword. */
17217 /* If compiler already emitted move of first word by
17218 store with update, no need to do anything. */
17219 if (j == 0 && used_update)
17222 emit_insn (gen_rtx_SET (VOIDmode,
17223 simplify_gen_subreg (reg_mode, dst, mode,
17224 j * reg_mode_size),
17225 simplify_gen_subreg (reg_mode, src, mode,
17226 j * reg_mode_size)));
17228 if (restore_basereg != NULL_RTX)
17229 emit_insn (restore_basereg);
17234 /* This page contains routines that are used to determine what the
17235 function prologue and epilogue code will do and write them out. */
17237 /* Return the first fixed-point register that is required to be
17238 saved. 32 if none. */
17241 first_reg_to_save (void)
17245 /* Find lowest numbered live register. */
17246 for (first_reg = 13; first_reg <= 31; first_reg++)
17247 if (df_regs_ever_live_p (first_reg)
17248 && (! call_used_regs[first_reg]
17249 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
17250 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
17251 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
17252 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
17257 && crtl->uses_pic_offset_table
17258 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
17259 return RS6000_PIC_OFFSET_TABLE_REGNUM;
17265 /* Similar, for FP regs. */
17268 first_fp_reg_to_save (void)
17272 /* Find lowest numbered live register. */
17273 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
17274 if (df_regs_ever_live_p (first_reg))
17280 /* Similar, for AltiVec regs. */
17283 first_altivec_reg_to_save (void)
17287 /* Stack frame remains as is unless we are in AltiVec ABI. */
17288 if (! TARGET_ALTIVEC_ABI)
17289 return LAST_ALTIVEC_REGNO + 1;
17291 /* On Darwin, the unwind routines are compiled without
17292 TARGET_ALTIVEC, and use save_world to save/restore the
17293 altivec registers when necessary. */
17294 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17295 && ! TARGET_ALTIVEC)
17296 return FIRST_ALTIVEC_REGNO + 20;
17298 /* Find lowest numbered live register. */
17299 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
17300 if (df_regs_ever_live_p (i))
17306 /* Return a 32-bit mask of the AltiVec registers we need to set in
17307 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
17308 the 32-bit word is 0. */
17310 static unsigned int
17311 compute_vrsave_mask (void)
17313 unsigned int i, mask = 0;
17315 /* On Darwin, the unwind routines are compiled without
17316 TARGET_ALTIVEC, and use save_world to save/restore the
17317 call-saved altivec registers when necessary. */
17318 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
17319 && ! TARGET_ALTIVEC)
17322 /* First, find out if we use _any_ altivec registers. */
17323 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
17324 if (df_regs_ever_live_p (i))
17325 mask |= ALTIVEC_REG_BIT (i);
17330 /* Next, remove the argument registers from the set. These must
17331 be in the VRSAVE mask set by the caller, so we don't need to add
17332 them in again. More importantly, the mask we compute here is
17333 used to generate CLOBBERs in the set_vrsave insn, and we do not
17334 wish the argument registers to die. */
17335 for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
17336 mask &= ~ALTIVEC_REG_BIT (i);
17338 /* Similarly, remove the return value from the set. */
17341 diddle_return_value (is_altivec_return_reg, &yes);
17343 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
17349 /* For a very restricted set of circumstances, we can cut down the
17350 size of prologues/epilogues by calling our own save/restore-the-world
17354 compute_save_world_info (rs6000_stack_t *info_ptr)
17356 info_ptr->world_save_p = 1;
17357 info_ptr->world_save_p
17358 = (WORLD_SAVE_P (info_ptr)
17359 && DEFAULT_ABI == ABI_DARWIN
17360 && !cfun->has_nonlocal_label
17361 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
17362 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
17363 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
17364 && info_ptr->cr_save_p);
17366 /* This will not work in conjunction with sibcalls. Make sure there
17367 are none. (This check is expensive, but seldom executed.) */
17368 if (WORLD_SAVE_P (info_ptr))
17371 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
17372 if ( GET_CODE (insn) == CALL_INSN
17373 && SIBLING_CALL_P (insn))
17375 info_ptr->world_save_p = 0;
17380 if (WORLD_SAVE_P (info_ptr))
17382 /* Even if we're not touching VRsave, make sure there's room on the
17383 stack for it, if it looks like we're calling SAVE_WORLD, which
17384 will attempt to save it. */
17385 info_ptr->vrsave_size = 4;
17387 /* If we are going to save the world, we need to save the link register too. */
17388 info_ptr->lr_save_p = 1;
17390 /* "Save" the VRsave register too if we're saving the world. */
17391 if (info_ptr->vrsave_mask == 0)
17392 info_ptr->vrsave_mask = compute_vrsave_mask ();
17394 /* Because the Darwin register save/restore routines only handle
17395 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
17397 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
17398 && (info_ptr->first_altivec_reg_save
17399 >= FIRST_SAVED_ALTIVEC_REGNO));
17406 is_altivec_return_reg (rtx reg, void *xyes)
17408 bool *yes = (bool *) xyes;
17409 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
17414 /* Determine the strategy for savings/restoring registers. */
17417 SAVRES_MULTIPLE = 0x1,
17418 SAVE_INLINE_FPRS = 0x2,
17419 SAVE_INLINE_GPRS = 0x4,
17420 REST_INLINE_FPRS = 0x8,
17421 REST_INLINE_GPRS = 0x10,
17422 SAVE_NOINLINE_GPRS_SAVES_LR = 0x20,
17423 SAVE_NOINLINE_FPRS_SAVES_LR = 0x40,
17424 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x80
17428 rs6000_savres_strategy (rs6000_stack_t *info,
17429 bool using_static_chain_p)
17433 if (TARGET_MULTIPLE
17434 && !TARGET_POWERPC64
17435 && !(TARGET_SPE_ABI && info->spe_64bit_regs_used)
17436 && info->first_gp_reg_save < 31
17437 && no_global_regs_above (info->first_gp_reg_save, /*gpr=*/true))
17438 strategy |= SAVRES_MULTIPLE;
17440 if (crtl->calls_eh_return
17441 || cfun->machine->ra_need_lr
17442 || info->total_size > 32767)
17443 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
17444 | SAVE_INLINE_GPRS | REST_INLINE_GPRS);
17446 if (info->first_fp_reg_save == 64
17447 || FP_SAVE_INLINE (info->first_fp_reg_save)
17448 /* The out-of-line FP routines use double-precision stores;
17449 we can't use those routines if we don't have such stores. */
17450 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT)
17451 || !no_global_regs_above (info->first_fp_reg_save, /*gpr=*/false))
17452 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
17454 if (info->first_gp_reg_save == 32
17455 || GP_SAVE_INLINE (info->first_gp_reg_save)
17456 || !((strategy & SAVRES_MULTIPLE)
17457 || no_global_regs_above (info->first_gp_reg_save, /*gpr=*/true)))
17458 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
17460 /* Don't bother to try to save things out-of-line if r11 is occupied
17461 by the static chain. It would require too much fiddling and the
17462 static chain is rarely used anyway. FPRs are saved w.r.t the stack
17463 pointer on Darwin. */
17464 if (using_static_chain_p)
17465 strategy |= (DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
17466 | SAVE_INLINE_GPRS;
17468 /* If we are going to use store multiple, then don't even bother
17469 with the out-of-line routines, since the store-multiple
17470 instruction will always be smaller. */
17471 if ((strategy & SAVRES_MULTIPLE))
17472 strategy |= SAVE_INLINE_GPRS;
17474 /* The situation is more complicated with load multiple. We'd
17475 prefer to use the out-of-line routines for restores, since the
17476 "exit" out-of-line routines can handle the restore of LR and the
17477 frame teardown. However if doesn't make sense to use the
17478 out-of-line routine if that is the only reason we'd need to save
17479 LR, and we can't use the "exit" out-of-line gpr restore if we
17480 have saved some fprs; In those cases it is advantageous to use
17481 load multiple when available. */
17482 if ((strategy & SAVRES_MULTIPLE)
17483 && (!info->lr_save_p
17484 || info->first_fp_reg_save != 64))
17485 strategy |= REST_INLINE_GPRS;
17487 /* We can only use load multiple or the out-of-line routines to
17488 restore if we've used store multiple or out-of-line routines
17489 in the prologue, i.e. if we've saved all the registers from
17490 first_gp_reg_save. Otherwise, we risk loading garbage. */
17491 if ((strategy & (SAVE_INLINE_GPRS | SAVRES_MULTIPLE)) == SAVE_INLINE_GPRS)
17492 strategy |= REST_INLINE_GPRS;
17494 /* Saving CR interferes with the exit routines used on the SPE, so
17497 && info->spe_64bit_regs_used
17498 && info->cr_save_p)
17499 strategy |= REST_INLINE_GPRS;
17501 #ifdef POWERPC_LINUX
17504 if (!(strategy & SAVE_INLINE_FPRS))
17505 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17506 else if (!(strategy & SAVE_INLINE_GPRS)
17507 && info->first_fp_reg_save == 64)
17508 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
17511 if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
17512 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
17514 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
17515 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
17520 /* Calculate the stack information for the current function. This is
17521 complicated by having two separate calling sequences, the AIX calling
17522 sequence and the V.4 calling sequence.
17524 AIX (and Darwin/Mac OS X) stack frames look like:
17526 SP----> +---------------------------------------+
17527 | back chain to caller | 0 0
17528 +---------------------------------------+
17529 | saved CR | 4 8 (8-11)
17530 +---------------------------------------+
17532 +---------------------------------------+
17533 | reserved for compilers | 12 24
17534 +---------------------------------------+
17535 | reserved for binders | 16 32
17536 +---------------------------------------+
17537 | saved TOC pointer | 20 40
17538 +---------------------------------------+
17539 | Parameter save area (P) | 24 48
17540 +---------------------------------------+
17541 | Alloca space (A) | 24+P etc.
17542 +---------------------------------------+
17543 | Local variable space (L) | 24+P+A
17544 +---------------------------------------+
17545 | Float/int conversion temporary (X) | 24+P+A+L
17546 +---------------------------------------+
17547 | Save area for AltiVec registers (W) | 24+P+A+L+X
17548 +---------------------------------------+
17549 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
17550 +---------------------------------------+
17551 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
17552 +---------------------------------------+
17553 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
17554 +---------------------------------------+
17555 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
17556 +---------------------------------------+
17557 old SP->| back chain to caller's caller |
17558 +---------------------------------------+
17560 The required alignment for AIX configurations is two words (i.e., 8
17564 V.4 stack frames look like:
17566 SP----> +---------------------------------------+
17567 | back chain to caller | 0
17568 +---------------------------------------+
17569 | caller's saved LR | 4
17570 +---------------------------------------+
17571 | Parameter save area (P) | 8
17572 +---------------------------------------+
17573 | Alloca space (A) | 8+P
17574 +---------------------------------------+
17575 | Varargs save area (V) | 8+P+A
17576 +---------------------------------------+
17577 | Local variable space (L) | 8+P+A+V
17578 +---------------------------------------+
17579 | Float/int conversion temporary (X) | 8+P+A+V+L
17580 +---------------------------------------+
17581 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
17582 +---------------------------------------+
17583 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
17584 +---------------------------------------+
17585 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
17586 +---------------------------------------+
17587 | SPE: area for 64-bit GP registers |
17588 +---------------------------------------+
17589 | SPE alignment padding |
17590 +---------------------------------------+
17591 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
17592 +---------------------------------------+
17593 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
17594 +---------------------------------------+
17595 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
17596 +---------------------------------------+
17597 old SP->| back chain to caller's caller |
17598 +---------------------------------------+
17600 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
17601 given. (But note below and in sysv4.h that we require only 8 and
17602 may round up the size of our stack frame anyways. The historical
17603 reason is early versions of powerpc-linux which didn't properly
17604 align the stack at program startup. A happy side-effect is that
17605 -mno-eabi libraries can be used with -meabi programs.)
17607 The EABI configuration defaults to the V.4 layout. However,
17608 the stack alignment requirements may differ. If -mno-eabi is not
17609 given, the required stack alignment is 8 bytes; if -mno-eabi is
17610 given, the required alignment is 16 bytes. (But see V.4 comment
17613 #ifndef ABI_STACK_BOUNDARY
17614 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
17617 static rs6000_stack_t *
17618 rs6000_stack_info (void)
17620 rs6000_stack_t *info_ptr = &stack_info;
17621 int reg_size = TARGET_32BIT ? 4 : 8;
17625 HOST_WIDE_INT non_fixed_size;
17626 bool using_static_chain_p;
17628 if (reload_completed && info_ptr->reload_completed)
17631 memset (info_ptr, 0, sizeof (*info_ptr));
17632 info_ptr->reload_completed = reload_completed;
17636 /* Cache value so we don't rescan instruction chain over and over. */
17637 if (cfun->machine->insn_chain_scanned_p == 0)
17638 cfun->machine->insn_chain_scanned_p
17639 = spe_func_has_64bit_regs_p () + 1;
17640 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
17643 /* Select which calling sequence. */
17644 info_ptr->abi = DEFAULT_ABI;
17646 /* Calculate which registers need to be saved & save area size. */
17647 info_ptr->first_gp_reg_save = first_reg_to_save ();
17648 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
17649 even if it currently looks like we won't. Reload may need it to
17650 get at a constant; if so, it will have already created a constant
17651 pool entry for it. */
17652 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
17653 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
17654 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
17655 && crtl->uses_const_pool
17656 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
17657 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
17659 first_gp = info_ptr->first_gp_reg_save;
17661 info_ptr->gp_size = reg_size * (32 - first_gp);
17663 /* For the SPE, we have an additional upper 32-bits on each GPR.
17664 Ideally we should save the entire 64-bits only when the upper
17665 half is used in SIMD instructions. Since we only record
17666 registers live (not the size they are used in), this proves
17667 difficult because we'd have to traverse the instruction chain at
17668 the right time, taking reload into account. This is a real pain,
17669 so we opt to save the GPRs in 64-bits always if but one register
17670 gets used in 64-bits. Otherwise, all the registers in the frame
17671 get saved in 32-bits.
17673 So... since when we save all GPRs (except the SP) in 64-bits, the
17674 traditional GP save area will be empty. */
17675 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17676 info_ptr->gp_size = 0;
17678 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
17679 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
17681 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
17682 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
17683 - info_ptr->first_altivec_reg_save);
17685 /* Does this function call anything? */
17686 info_ptr->calls_p = (! current_function_is_leaf
17687 || cfun->machine->ra_needs_full_frame);
17689 /* Determine if we need to save the condition code registers. */
17690 if (df_regs_ever_live_p (CR2_REGNO)
17691 || df_regs_ever_live_p (CR3_REGNO)
17692 || df_regs_ever_live_p (CR4_REGNO))
17694 info_ptr->cr_save_p = 1;
17695 if (DEFAULT_ABI == ABI_V4)
17696 info_ptr->cr_size = reg_size;
17699 /* If the current function calls __builtin_eh_return, then we need
17700 to allocate stack space for registers that will hold data for
17701 the exception handler. */
17702 if (crtl->calls_eh_return)
17705 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
17708 /* SPE saves EH registers in 64-bits. */
17709 ehrd_size = i * (TARGET_SPE_ABI
17710 && info_ptr->spe_64bit_regs_used != 0
17711 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
17716 /* Determine various sizes. */
17717 info_ptr->reg_size = reg_size;
17718 info_ptr->fixed_size = RS6000_SAVE_AREA;
17719 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
17720 info_ptr->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
17721 TARGET_ALTIVEC ? 16 : 8);
17722 if (FRAME_GROWS_DOWNWARD)
17723 info_ptr->vars_size
17724 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
17725 + info_ptr->parm_size,
17726 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
17727 - (info_ptr->fixed_size + info_ptr->vars_size
17728 + info_ptr->parm_size);
17730 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17731 info_ptr->spe_gp_size = 8 * (32 - first_gp);
17733 info_ptr->spe_gp_size = 0;
17735 if (TARGET_ALTIVEC_ABI)
17736 info_ptr->vrsave_mask = compute_vrsave_mask ();
17738 info_ptr->vrsave_mask = 0;
17740 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
17741 info_ptr->vrsave_size = 4;
17743 info_ptr->vrsave_size = 0;
17745 compute_save_world_info (info_ptr);
17747 /* Calculate the offsets. */
17748 switch (DEFAULT_ABI)
17752 gcc_unreachable ();
17756 info_ptr->fp_save_offset = - info_ptr->fp_size;
17757 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
17759 if (TARGET_ALTIVEC_ABI)
17761 info_ptr->vrsave_save_offset
17762 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
17764 /* Align stack so vector save area is on a quadword boundary.
17765 The padding goes above the vectors. */
17766 if (info_ptr->altivec_size != 0)
17767 info_ptr->altivec_padding_size
17768 = info_ptr->vrsave_save_offset & 0xF;
17770 info_ptr->altivec_padding_size = 0;
17772 info_ptr->altivec_save_offset
17773 = info_ptr->vrsave_save_offset
17774 - info_ptr->altivec_padding_size
17775 - info_ptr->altivec_size;
17776 gcc_assert (info_ptr->altivec_size == 0
17777 || info_ptr->altivec_save_offset % 16 == 0);
17779 /* Adjust for AltiVec case. */
17780 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
17783 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
17784 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
17785 info_ptr->lr_save_offset = 2*reg_size;
17789 info_ptr->fp_save_offset = - info_ptr->fp_size;
17790 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
17791 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
17793 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
17795 /* Align stack so SPE GPR save area is aligned on a
17796 double-word boundary. */
17797 if (info_ptr->spe_gp_size != 0 && info_ptr->cr_save_offset != 0)
17798 info_ptr->spe_padding_size
17799 = 8 - (-info_ptr->cr_save_offset % 8);
17801 info_ptr->spe_padding_size = 0;
17803 info_ptr->spe_gp_save_offset
17804 = info_ptr->cr_save_offset
17805 - info_ptr->spe_padding_size
17806 - info_ptr->spe_gp_size;
17808 /* Adjust for SPE case. */
17809 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
17811 else if (TARGET_ALTIVEC_ABI)
17813 info_ptr->vrsave_save_offset
17814 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
17816 /* Align stack so vector save area is on a quadword boundary. */
17817 if (info_ptr->altivec_size != 0)
17818 info_ptr->altivec_padding_size
17819 = 16 - (-info_ptr->vrsave_save_offset % 16);
17821 info_ptr->altivec_padding_size = 0;
17823 info_ptr->altivec_save_offset
17824 = info_ptr->vrsave_save_offset
17825 - info_ptr->altivec_padding_size
17826 - info_ptr->altivec_size;
17828 /* Adjust for AltiVec case. */
17829 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
17832 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
17833 info_ptr->ehrd_offset -= ehrd_size;
17834 info_ptr->lr_save_offset = reg_size;
17838 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
17839 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
17840 + info_ptr->gp_size
17841 + info_ptr->altivec_size
17842 + info_ptr->altivec_padding_size
17843 + info_ptr->spe_gp_size
17844 + info_ptr->spe_padding_size
17846 + info_ptr->cr_size
17847 + info_ptr->vrsave_size,
17850 non_fixed_size = (info_ptr->vars_size
17851 + info_ptr->parm_size
17852 + info_ptr->save_size);
17854 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
17855 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
17857 /* Determine if we need to save the link register. */
17858 if (info_ptr->calls_p
17859 || (DEFAULT_ABI == ABI_AIX
17861 && !TARGET_PROFILE_KERNEL)
17862 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
17863 #ifdef TARGET_RELOCATABLE
17864 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
17866 || rs6000_ra_ever_killed ())
17867 info_ptr->lr_save_p = 1;
17869 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
17870 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
17871 && call_used_regs[STATIC_CHAIN_REGNUM]);
17872 info_ptr->savres_strategy = rs6000_savres_strategy (info_ptr,
17873 using_static_chain_p);
17875 if (!(info_ptr->savres_strategy & SAVE_INLINE_GPRS)
17876 || !(info_ptr->savres_strategy & SAVE_INLINE_FPRS)
17877 || !(info_ptr->savres_strategy & REST_INLINE_GPRS)
17878 || !(info_ptr->savres_strategy & REST_INLINE_FPRS))
17879 info_ptr->lr_save_p = 1;
17881 if (info_ptr->lr_save_p)
17882 df_set_regs_ever_live (LR_REGNO, true);
17884 /* Determine if we need to allocate any stack frame:
17886 For AIX we need to push the stack if a frame pointer is needed
17887 (because the stack might be dynamically adjusted), if we are
17888 debugging, if we make calls, or if the sum of fp_save, gp_save,
17889 and local variables are more than the space needed to save all
17890 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
17891 + 18*8 = 288 (GPR13 reserved).
17893 For V.4 we don't have the stack cushion that AIX uses, but assume
17894 that the debugger can handle stackless frames. */
17896 if (info_ptr->calls_p)
17897 info_ptr->push_p = 1;
17899 else if (DEFAULT_ABI == ABI_V4)
17900 info_ptr->push_p = non_fixed_size != 0;
17902 else if (frame_pointer_needed)
17903 info_ptr->push_p = 1;
17905 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
17906 info_ptr->push_p = 1;
17909 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
17911 /* Zero offsets if we're not saving those registers. */
17912 if (info_ptr->fp_size == 0)
17913 info_ptr->fp_save_offset = 0;
17915 if (info_ptr->gp_size == 0)
17916 info_ptr->gp_save_offset = 0;
17918 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
17919 info_ptr->altivec_save_offset = 0;
17921 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
17922 info_ptr->vrsave_save_offset = 0;
17924 if (! TARGET_SPE_ABI
17925 || info_ptr->spe_64bit_regs_used == 0
17926 || info_ptr->spe_gp_size == 0)
17927 info_ptr->spe_gp_save_offset = 0;
17929 if (! info_ptr->lr_save_p)
17930 info_ptr->lr_save_offset = 0;
17932 if (! info_ptr->cr_save_p)
17933 info_ptr->cr_save_offset = 0;
17938 /* Return true if the current function uses any GPRs in 64-bit SIMD
17942 spe_func_has_64bit_regs_p (void)
17946 /* Functions that save and restore all the call-saved registers will
17947 need to save/restore the registers in 64-bits. */
17948 if (crtl->calls_eh_return
17949 || cfun->calls_setjmp
17950 || crtl->has_nonlocal_goto)
17953 insns = get_insns ();
17955 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
17961 /* FIXME: This should be implemented with attributes...
17963 (set_attr "spe64" "true")....then,
17964 if (get_spe64(insn)) return true;
17966 It's the only reliable way to do the stuff below. */
17968 i = PATTERN (insn);
17969 if (GET_CODE (i) == SET)
17971 enum machine_mode mode = GET_MODE (SET_SRC (i));
17973 if (SPE_VECTOR_MODE (mode))
17975 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
17985 debug_stack_info (rs6000_stack_t *info)
17987 const char *abi_string;
17990 info = rs6000_stack_info ();
17992 fprintf (stderr, "\nStack information for function %s:\n",
17993 ((current_function_decl && DECL_NAME (current_function_decl))
17994 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
17999 default: abi_string = "Unknown"; break;
18000 case ABI_NONE: abi_string = "NONE"; break;
18001 case ABI_AIX: abi_string = "AIX"; break;
18002 case ABI_DARWIN: abi_string = "Darwin"; break;
18003 case ABI_V4: abi_string = "V.4"; break;
18006 fprintf (stderr, "\tABI = %5s\n", abi_string);
18008 if (TARGET_ALTIVEC_ABI)
18009 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
18011 if (TARGET_SPE_ABI)
18012 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
18014 if (info->first_gp_reg_save != 32)
18015 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
18017 if (info->first_fp_reg_save != 64)
18018 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
18020 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
18021 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
18022 info->first_altivec_reg_save);
18024 if (info->lr_save_p)
18025 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
18027 if (info->cr_save_p)
18028 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
18030 if (info->vrsave_mask)
18031 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
18034 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
18037 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
18039 if (info->gp_save_offset)
18040 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
18042 if (info->fp_save_offset)
18043 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
18045 if (info->altivec_save_offset)
18046 fprintf (stderr, "\taltivec_save_offset = %5d\n",
18047 info->altivec_save_offset);
18049 if (info->spe_gp_save_offset)
18050 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
18051 info->spe_gp_save_offset);
18053 if (info->vrsave_save_offset)
18054 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
18055 info->vrsave_save_offset);
18057 if (info->lr_save_offset)
18058 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
18060 if (info->cr_save_offset)
18061 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
18063 if (info->varargs_save_offset)
18064 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
18066 if (info->total_size)
18067 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
18070 if (info->vars_size)
18071 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
18074 if (info->parm_size)
18075 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
18077 if (info->fixed_size)
18078 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
18081 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
18083 if (info->spe_gp_size)
18084 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
18087 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
18089 if (info->altivec_size)
18090 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
18092 if (info->vrsave_size)
18093 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
18095 if (info->altivec_padding_size)
18096 fprintf (stderr, "\taltivec_padding_size= %5d\n",
18097 info->altivec_padding_size);
18099 if (info->spe_padding_size)
18100 fprintf (stderr, "\tspe_padding_size = %5d\n",
18101 info->spe_padding_size);
18104 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
18106 if (info->save_size)
18107 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
18109 if (info->reg_size != 4)
18110 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
18112 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
18114 fprintf (stderr, "\n");
18118 rs6000_return_addr (int count, rtx frame)
18120 /* Currently we don't optimize very well between prolog and body
18121 code and for PIC code the code can be actually quite bad, so
18122 don't try to be too clever here. */
18123 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
18125 cfun->machine->ra_needs_full_frame = 1;
18132 plus_constant (copy_to_reg
18133 (gen_rtx_MEM (Pmode,
18134 memory_address (Pmode, frame))),
18135 RETURN_ADDRESS_OFFSET)));
18138 cfun->machine->ra_need_lr = 1;
18139 return get_hard_reg_initial_val (Pmode, LR_REGNO);
18142 /* Say whether a function is a candidate for sibcall handling or not. */
18145 rs6000_function_ok_for_sibcall (tree decl, tree exp)
18150 fntype = TREE_TYPE (decl);
18152 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
18154 /* We can't do it if the called function has more vector parameters
18155 than the current function; there's nowhere to put the VRsave code. */
18156 if (TARGET_ALTIVEC_ABI
18157 && TARGET_ALTIVEC_VRSAVE
18158 && !(decl && decl == current_function_decl))
18160 function_args_iterator args_iter;
18164 /* Functions with vector parameters are required to have a
18165 prototype, so the argument type info must be available
18167 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
18168 if (TREE_CODE (type) == VECTOR_TYPE
18169 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18172 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
18173 if (TREE_CODE (type) == VECTOR_TYPE
18174 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
18181 /* Under the AIX ABI we can't allow calls to non-local functions,
18182 because the callee may have a different TOC pointer to the
18183 caller and there's no way to ensure we restore the TOC when we
18184 return. With the secure-plt SYSV ABI we can't make non-local
18185 calls when -fpic/PIC because the plt call stubs use r30. */
18186 if (DEFAULT_ABI == ABI_DARWIN
18187 || (DEFAULT_ABI == ABI_AIX
18189 && !DECL_EXTERNAL (decl)
18190 && (*targetm.binds_local_p) (decl))
18191 || (DEFAULT_ABI == ABI_V4
18192 && (!TARGET_SECURE_PLT
18195 && (*targetm.binds_local_p) (decl)))))
18197 tree attr_list = TYPE_ATTRIBUTES (fntype);
18199 if (!lookup_attribute ("longcall", attr_list)
18200 || lookup_attribute ("shortcall", attr_list))
18207 /* NULL if INSN insn is valid within a low-overhead loop.
18208 Otherwise return why doloop cannot be applied.
18209 PowerPC uses the COUNT register for branch on table instructions. */
18211 static const char *
18212 rs6000_invalid_within_doloop (const_rtx insn)
18215 return "Function call in the loop.";
18218 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
18219 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
18220 return "Computed branch in the loop.";
18226 rs6000_ra_ever_killed (void)
18232 if (cfun->is_thunk)
18235 if (cfun->machine->lr_save_state)
18236 return cfun->machine->lr_save_state - 1;
18238 /* regs_ever_live has LR marked as used if any sibcalls are present,
18239 but this should not force saving and restoring in the
18240 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
18241 clobbers LR, so that is inappropriate. */
18243 /* Also, the prologue can generate a store into LR that
18244 doesn't really count, like this:
18247 bcl to set PIC register
18251 When we're called from the epilogue, we need to avoid counting
18252 this as a store. */
18254 push_topmost_sequence ();
18255 top = get_insns ();
18256 pop_topmost_sequence ();
18257 reg = gen_rtx_REG (Pmode, LR_REGNO);
18259 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
18265 if (!SIBLING_CALL_P (insn))
18268 else if (find_regno_note (insn, REG_INC, LR_REGNO))
18270 else if (set_of (reg, insn) != NULL_RTX
18271 && !prologue_epilogue_contains (insn))
18278 /* Emit instructions needed to load the TOC register.
18279 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
18280 a constant pool; or for SVR4 -fpic. */
18283 rs6000_emit_load_toc_table (int fromprolog)
18286 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
18288 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
18291 rtx lab, tmp1, tmp2, got;
18293 lab = gen_label_rtx ();
18294 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
18295 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18297 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18299 got = rs6000_got_sym ();
18300 tmp1 = tmp2 = dest;
18303 tmp1 = gen_reg_rtx (Pmode);
18304 tmp2 = gen_reg_rtx (Pmode);
18306 emit_insn (gen_load_toc_v4_PIC_1 (lab));
18307 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
18308 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
18309 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
18311 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
18313 emit_insn (gen_load_toc_v4_pic_si ());
18314 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18316 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
18319 rtx temp0 = (fromprolog
18320 ? gen_rtx_REG (Pmode, 0)
18321 : gen_reg_rtx (Pmode));
18327 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18328 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18330 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
18331 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18333 emit_insn (gen_load_toc_v4_PIC_1 (symF));
18334 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18335 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
18341 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
18342 lab = gen_label_rtx ();
18343 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
18344 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
18345 if (TARGET_LINK_STACK)
18346 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
18347 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
18349 emit_insn (gen_addsi3 (dest, temp0, dest));
18351 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
18353 /* This is for AIX code running in non-PIC ELF32. */
18356 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18357 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
18359 emit_insn (gen_elf_high (dest, realsym));
18360 emit_insn (gen_elf_low (dest, dest, realsym));
18364 gcc_assert (DEFAULT_ABI == ABI_AIX);
18367 emit_insn (gen_load_toc_aix_si (dest));
18369 emit_insn (gen_load_toc_aix_di (dest));
18373 /* Emit instructions to restore the link register after determining where
18374 its value has been stored. */
18377 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
18379 rs6000_stack_t *info = rs6000_stack_info ();
18382 operands[0] = source;
18383 operands[1] = scratch;
18385 if (info->lr_save_p)
18387 rtx frame_rtx = stack_pointer_rtx;
18388 HOST_WIDE_INT sp_offset = 0;
18391 if (frame_pointer_needed
18392 || cfun->calls_alloca
18393 || info->total_size > 32767)
18395 tmp = gen_frame_mem (Pmode, frame_rtx);
18396 emit_move_insn (operands[1], tmp);
18397 frame_rtx = operands[1];
18399 else if (info->push_p)
18400 sp_offset = info->total_size;
18402 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
18403 tmp = gen_frame_mem (Pmode, tmp);
18404 emit_move_insn (tmp, operands[0]);
18407 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
18409 /* Freeze lr_save_p. We've just emitted rtl that depends on the
18410 state of lr_save_p so any change from here on would be a bug. In
18411 particular, stop rs6000_ra_ever_killed from considering the SET
18412 of lr we may have added just above. */
18413 cfun->machine->lr_save_state = info->lr_save_p + 1;
18416 static GTY(()) alias_set_type set = -1;
18419 get_TOC_alias_set (void)
18422 set = new_alias_set ();
18426 /* This returns nonzero if the current function uses the TOC. This is
18427 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
18428 is generated by the ABI_V4 load_toc_* patterns. */
18435 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
18438 rtx pat = PATTERN (insn);
18441 if (GET_CODE (pat) == PARALLEL)
18442 for (i = 0; i < XVECLEN (pat, 0); i++)
18444 rtx sub = XVECEXP (pat, 0, i);
18445 if (GET_CODE (sub) == USE)
18447 sub = XEXP (sub, 0);
18448 if (GET_CODE (sub) == UNSPEC
18449 && XINT (sub, 1) == UNSPEC_TOC)
18459 create_TOC_reference (rtx symbol, rtx largetoc_reg)
18461 rtx tocrel, tocreg;
18463 if (TARGET_DEBUG_ADDR)
18465 if (GET_CODE (symbol) == SYMBOL_REF)
18466 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
18470 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
18471 GET_RTX_NAME (GET_CODE (symbol)));
18472 debug_rtx (symbol);
18476 if (!can_create_pseudo_p ())
18477 df_set_regs_ever_live (TOC_REGISTER, true);
18479 tocrel = gen_rtx_CONST (Pmode,
18480 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, symbol),
18482 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
18483 if (TARGET_CMODEL != CMODEL_SMALL)
18485 rtx hi = gen_rtx_CONST (Pmode,
18486 gen_rtx_PLUS (Pmode, tocreg,
18487 gen_rtx_HIGH (Pmode, tocrel)));
18488 if (largetoc_reg != NULL)
18490 emit_move_insn (largetoc_reg, hi);
18493 return gen_rtx_LO_SUM (Pmode, hi, copy_rtx (tocrel));
18496 return gen_rtx_PLUS (Pmode, tocreg, tocrel);
18499 /* Issue assembly directives that create a reference to the given DWARF
18500 FRAME_TABLE_LABEL from the current function section. */
18502 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
18504 fprintf (asm_out_file, "\t.ref %s\n",
18505 TARGET_STRIP_NAME_ENCODING (frame_table_label));
18508 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
18509 and the change to the stack pointer. */
18512 rs6000_emit_stack_tie (void)
18514 rtx mem = gen_frame_mem (BLKmode,
18515 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
18517 emit_insn (gen_stack_tie (mem));
18520 /* Emit the correct code for allocating stack space, as insns.
18521 If COPY_REG, make sure a copy of the old frame is left there.
18522 The generated code may use hard register 0 as a temporary. */
18525 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg)
18528 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
18529 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
18530 rtx todec = gen_int_mode (-size, Pmode);
18533 if (INTVAL (todec) != -size)
18535 warning (0, "stack frame too large");
18536 emit_insn (gen_trap ());
18540 if (crtl->limit_stack)
18542 if (REG_P (stack_limit_rtx)
18543 && REGNO (stack_limit_rtx) > 1
18544 && REGNO (stack_limit_rtx) <= 31)
18546 emit_insn (gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size)));
18547 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18550 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
18552 && DEFAULT_ABI == ABI_V4)
18554 rtx toload = gen_rtx_CONST (VOIDmode,
18555 gen_rtx_PLUS (Pmode,
18559 emit_insn (gen_elf_high (tmp_reg, toload));
18560 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
18561 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
18565 warning (0, "stack limit expression is not supported");
18569 emit_move_insn (copy_reg, stack_reg);
18573 /* Need a note here so that try_split doesn't get confused. */
18574 if (get_last_insn () == NULL_RTX)
18575 emit_note (NOTE_INSN_DELETED);
18576 insn = emit_move_insn (tmp_reg, todec);
18577 try_split (PATTERN (insn), insn, 0);
18581 insn = emit_insn (TARGET_32BIT
18582 ? gen_movsi_update_stack (stack_reg, stack_reg,
18584 : gen_movdi_di_update_stack (stack_reg, stack_reg,
18585 todec, stack_reg));
18586 /* Since we didn't use gen_frame_mem to generate the MEM, grab
18587 it now and set the alias set/attributes. The above gen_*_update
18588 calls will generate a PARALLEL with the MEM set being the first
18590 par = PATTERN (insn);
18591 gcc_assert (GET_CODE (par) == PARALLEL);
18592 set = XVECEXP (par, 0, 0);
18593 gcc_assert (GET_CODE (set) == SET);
18594 mem = SET_DEST (set);
18595 gcc_assert (MEM_P (mem));
18596 MEM_NOTRAP_P (mem) = 1;
18597 set_mem_alias_set (mem, get_frame_alias_set ());
18599 RTX_FRAME_RELATED_P (insn) = 1;
18600 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
18601 gen_rtx_SET (VOIDmode, stack_reg,
18602 gen_rtx_PLUS (Pmode, stack_reg,
18603 GEN_INT (-size))));
18606 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
18608 #if PROBE_INTERVAL > 32768
18609 #error Cannot use indexed addressing mode for stack probing
18612 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
18613 inclusive. These are offsets from the current stack pointer. */
18616 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
18618 /* See if we have a constant small number of probes to generate. If so,
18619 that's the easy case. */
18620 if (first + size <= 32768)
18624 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
18625 it exceeds SIZE. If only one probe is needed, this will not
18626 generate any code. Then probe at FIRST + SIZE. */
18627 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
18628 emit_stack_probe (plus_constant (stack_pointer_rtx, -(first + i)));
18630 emit_stack_probe (plus_constant (stack_pointer_rtx, -(first + size)));
18633 /* Otherwise, do the same as above, but in a loop. Note that we must be
18634 extra careful with variables wrapping around because we might be at
18635 the very top (or the very bottom) of the address space and we have
18636 to be able to handle this case properly; in particular, we use an
18637 equality test for the loop condition. */
18640 HOST_WIDE_INT rounded_size;
18641 rtx r12 = gen_rtx_REG (Pmode, 12);
18642 rtx r0 = gen_rtx_REG (Pmode, 0);
18644 /* Sanity check for the addressing mode we're going to use. */
18645 gcc_assert (first <= 32768);
18647 /* Step 1: round SIZE to the previous multiple of the interval. */
18649 rounded_size = size & -PROBE_INTERVAL;
18652 /* Step 2: compute initial and final value of the loop counter. */
18654 /* TEST_ADDR = SP + FIRST. */
18655 emit_insn (gen_rtx_SET (VOIDmode, r12,
18656 plus_constant (stack_pointer_rtx, -first)));
18658 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
18659 if (rounded_size > 32768)
18661 emit_move_insn (r0, GEN_INT (-rounded_size));
18662 emit_insn (gen_rtx_SET (VOIDmode, r0,
18663 gen_rtx_PLUS (Pmode, r12, r0)));
18666 emit_insn (gen_rtx_SET (VOIDmode, r0,
18667 plus_constant (r12, -rounded_size)));
18670 /* Step 3: the loop
18672 while (TEST_ADDR != LAST_ADDR)
18674 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
18678 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
18679 until it is equal to ROUNDED_SIZE. */
18682 emit_insn (gen_probe_stack_rangedi (r12, r12, r0));
18684 emit_insn (gen_probe_stack_rangesi (r12, r12, r0));
18687 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
18688 that SIZE is equal to ROUNDED_SIZE. */
18690 if (size != rounded_size)
18691 emit_stack_probe (plus_constant (r12, rounded_size - size));
18695 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
18696 absolute addresses. */
18699 output_probe_stack_range (rtx reg1, rtx reg2)
18701 static int labelno = 0;
18702 char loop_lab[32], end_lab[32];
18705 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
18706 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
18708 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
18710 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
18714 output_asm_insn ("{cmp|cmpd} 0,%0,%1", xops);
18716 output_asm_insn ("{cmp|cmpw} 0,%0,%1", xops);
18718 fputs ("\tbeq 0,", asm_out_file);
18719 assemble_name_raw (asm_out_file, end_lab);
18720 fputc ('\n', asm_out_file);
18722 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
18723 xops[1] = GEN_INT (-PROBE_INTERVAL);
18724 output_asm_insn ("{cal %0,%1(%0)|addi %0,%0,%1}", xops);
18726 /* Probe at TEST_ADDR and branch. */
18727 xops[1] = gen_rtx_REG (Pmode, 0);
18728 output_asm_insn ("{st|stw} %1,0(%0)", xops);
18729 fprintf (asm_out_file, "\tb ");
18730 assemble_name_raw (asm_out_file, loop_lab);
18731 fputc ('\n', asm_out_file);
18733 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
18738 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
18739 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
18740 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
18741 deduce these equivalences by itself so it wasn't necessary to hold
18742 its hand so much. */
18745 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
18746 rtx reg2, rtx rreg)
18750 /* copy_rtx will not make unique copies of registers, so we need to
18751 ensure we don't have unwanted sharing here. */
18753 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
18756 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
18758 real = copy_rtx (PATTERN (insn));
18760 if (reg2 != NULL_RTX)
18761 real = replace_rtx (real, reg2, rreg);
18763 real = replace_rtx (real, reg,
18764 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
18765 STACK_POINTER_REGNUM),
18768 /* We expect that 'real' is either a SET or a PARALLEL containing
18769 SETs (and possibly other stuff). In a PARALLEL, all the SETs
18770 are important so they all have to be marked RTX_FRAME_RELATED_P. */
18772 if (GET_CODE (real) == SET)
18776 temp = simplify_rtx (SET_SRC (set));
18778 SET_SRC (set) = temp;
18779 temp = simplify_rtx (SET_DEST (set));
18781 SET_DEST (set) = temp;
18782 if (GET_CODE (SET_DEST (set)) == MEM)
18784 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
18786 XEXP (SET_DEST (set), 0) = temp;
18793 gcc_assert (GET_CODE (real) == PARALLEL);
18794 for (i = 0; i < XVECLEN (real, 0); i++)
18795 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
18797 rtx set = XVECEXP (real, 0, i);
18799 temp = simplify_rtx (SET_SRC (set));
18801 SET_SRC (set) = temp;
18802 temp = simplify_rtx (SET_DEST (set));
18804 SET_DEST (set) = temp;
18805 if (GET_CODE (SET_DEST (set)) == MEM)
18807 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
18809 XEXP (SET_DEST (set), 0) = temp;
18811 RTX_FRAME_RELATED_P (set) = 1;
18815 RTX_FRAME_RELATED_P (insn) = 1;
18816 add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);
18821 /* Returns an insn that has a vrsave set operation with the
18822 appropriate CLOBBERs. */
18825 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
18828 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
18829 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
18832 = gen_rtx_SET (VOIDmode,
18834 gen_rtx_UNSPEC_VOLATILE (SImode,
18835 gen_rtvec (2, reg, vrsave),
18836 UNSPECV_SET_VRSAVE));
18840 /* We need to clobber the registers in the mask so the scheduler
18841 does not move sets to VRSAVE before sets of AltiVec registers.
18843 However, if the function receives nonlocal gotos, reload will set
18844 all call saved registers live. We will end up with:
18846 (set (reg 999) (mem))
18847 (parallel [ (set (reg vrsave) (unspec blah))
18848 (clobber (reg 999))])
18850 The clobber will cause the store into reg 999 to be dead, and
18851 flow will attempt to delete an epilogue insn. In this case, we
18852 need an unspec use/set of the register. */
18854 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
18855 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
18857 if (!epiloguep || call_used_regs [i])
18858 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
18859 gen_rtx_REG (V4SImode, i));
18862 rtx reg = gen_rtx_REG (V4SImode, i);
18865 = gen_rtx_SET (VOIDmode,
18867 gen_rtx_UNSPEC (V4SImode,
18868 gen_rtvec (1, reg), 27));
18872 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
18874 for (i = 0; i < nclobs; ++i)
18875 XVECEXP (insn, 0, i) = clobs[i];
18880 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
18881 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
18884 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
18885 unsigned int regno, int offset, HOST_WIDE_INT total_size)
18887 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
18888 rtx replacea, replaceb;
18890 int_rtx = GEN_INT (offset);
18892 /* Some cases that need register indexed addressing. */
18893 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
18894 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
18895 || (TARGET_E500_DOUBLE && mode == DFmode)
18897 && SPE_VECTOR_MODE (mode)
18898 && !SPE_CONST_OFFSET_OK (offset)))
18900 /* Whomever calls us must make sure r11 is available in the
18901 flow path of instructions in the prologue. */
18902 offset_rtx = gen_rtx_REG (Pmode, 11);
18903 emit_move_insn (offset_rtx, int_rtx);
18905 replacea = offset_rtx;
18906 replaceb = int_rtx;
18910 offset_rtx = int_rtx;
18911 replacea = NULL_RTX;
18912 replaceb = NULL_RTX;
18915 reg = gen_rtx_REG (mode, regno);
18916 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
18917 mem = gen_frame_mem (mode, addr);
18919 insn = emit_move_insn (mem, reg);
18921 return rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
18924 /* Emit an offset memory reference suitable for a frame store, while
18925 converting to a valid addressing mode. */
18928 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
18930 rtx int_rtx, offset_rtx;
18932 int_rtx = GEN_INT (offset);
18934 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
18935 || (TARGET_E500_DOUBLE && mode == DFmode))
18937 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
18938 emit_move_insn (offset_rtx, int_rtx);
18941 offset_rtx = int_rtx;
18943 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
18946 /* Look for user-defined global regs. We should not save and restore these,
18947 and cannot use stmw/lmw if there are any in its range. */
18950 no_global_regs_above (int first, bool gpr)
18953 int last = gpr ? 32 : 64;
18954 for (i = first; i < last; i++)
18955 if (global_regs[i])
18960 #ifndef TARGET_FIX_AND_CONTINUE
18961 #define TARGET_FIX_AND_CONTINUE 0
18964 /* It's really GPR 13 and FPR 14, but we need the smaller of the two. */
18965 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
18966 #define LAST_SAVRES_REGISTER 31
18967 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
18969 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][8];
18971 /* Temporary holding space for an out-of-line register save/restore
18973 static char savres_routine_name[30];
18975 /* Return the name for an out-of-line register save/restore routine.
18976 We are saving/restoring GPRs if GPR is true. */
18979 rs6000_savres_routine_name (rs6000_stack_t *info, int regno,
18980 bool savep, bool gpr, bool lr)
18982 const char *prefix = "";
18983 const char *suffix = "";
18985 /* Different targets are supposed to define
18986 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
18987 routine name could be defined with:
18989 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
18991 This is a nice idea in practice, but in reality, things are
18992 complicated in several ways:
18994 - ELF targets have save/restore routines for GPRs.
18996 - SPE targets use different prefixes for 32/64-bit registers, and
18997 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
18999 - PPC64 ELF targets have routines for save/restore of GPRs that
19000 differ in what they do with the link register, so having a set
19001 prefix doesn't work. (We only use one of the save routines at
19002 the moment, though.)
19004 - PPC32 elf targets have "exit" versions of the restore routines
19005 that restore the link register and can save some extra space.
19006 These require an extra suffix. (There are also "tail" versions
19007 of the restore routines and "GOT" versions of the save routines,
19008 but we don't generate those at present. Same problems apply,
19011 We deal with all this by synthesizing our own prefix/suffix and
19012 using that for the simple sprintf call shown above. */
19015 /* No floating point saves on the SPE. */
19019 prefix = info->spe_64bit_regs_used ? "_save64gpr_" : "_save32gpr_";
19021 prefix = info->spe_64bit_regs_used ? "_rest64gpr_" : "_rest32gpr_";
19026 else if (DEFAULT_ABI == ABI_V4)
19032 prefix = savep ? "_savegpr_" : "_restgpr_";
19034 prefix = savep ? "_savefpr_" : "_restfpr_";
19039 else if (DEFAULT_ABI == ABI_AIX)
19041 #ifndef POWERPC_LINUX
19042 /* No out-of-line save/restore routines for GPRs on AIX. */
19043 gcc_assert (!TARGET_AIX || !gpr);
19049 ? (lr ? "_savegpr0_" : "_savegpr1_")
19050 : (lr ? "_restgpr0_" : "_restgpr1_"));
19051 #ifdef POWERPC_LINUX
19053 prefix = (savep ? "_savefpr_" : "_restfpr_");
19057 prefix = savep ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
19058 suffix = savep ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
19062 if (DEFAULT_ABI == ABI_DARWIN)
19064 /* The Darwin approach is (slightly) different, in order to be
19065 compatible with code generated by the system toolchain. There is a
19066 single symbol for the start of save sequence, and the code here
19067 embeds an offset into that code on the basis of the first register
19069 prefix = savep ? "save" : "rest" ;
19071 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31",
19072 prefix, (lr ? "x" : ""), (regno == 13 ? "" : "+"),
19073 (regno-13) * 4, prefix, regno);
19075 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31",
19076 prefix, (regno == 14 ? "" : "+"), (regno-14) * 4, prefix, regno);
19079 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
19081 return savres_routine_name;
19084 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
19085 We are saving/restoring GPRs if GPR is true. */
19088 rs6000_savres_routine_sym (rs6000_stack_t *info, bool savep,
19091 int regno = gpr ? info->first_gp_reg_save : (info->first_fp_reg_save - 32);
19093 int select = ((savep ? 1 : 0) << 2
19095 /* On the SPE, we never have any FPRs, but we do have
19096 32/64-bit versions of the routines. */
19097 ? (info->spe_64bit_regs_used ? 1 : 0)
19098 : (gpr ? 1 : 0)) << 1)
19101 /* Don't generate bogus routine names. */
19102 gcc_assert (FIRST_SAVRES_REGISTER <= regno
19103 && regno <= LAST_SAVRES_REGISTER);
19105 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
19111 name = rs6000_savres_routine_name (info, regno, savep, gpr, lr);
19113 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
19114 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
19115 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
19121 /* Emit a sequence of insns, including a stack tie if needed, for
19122 resetting the stack pointer. If SAVRES is true, then don't reset the
19123 stack pointer, but move the base of the frame into r11 for use by
19124 out-of-line register restore routines. */
19127 rs6000_emit_stack_reset (rs6000_stack_t *info,
19128 rtx sp_reg_rtx, rtx frame_reg_rtx,
19129 int sp_offset, bool savres)
19131 /* This blockage is needed so that sched doesn't decide to move
19132 the sp change before the register restores. */
19133 if (DEFAULT_ABI == ABI_V4
19135 && info->spe_64bit_regs_used != 0
19136 && info->first_gp_reg_save != 32))
19137 rs6000_emit_stack_tie ();
19139 if (frame_reg_rtx != sp_reg_rtx)
19141 if (sp_offset != 0)
19143 rtx dest_reg = savres ? gen_rtx_REG (Pmode, 11) : sp_reg_rtx;
19144 rtx insn = emit_insn (gen_add3_insn (dest_reg, frame_reg_rtx,
19145 GEN_INT (sp_offset)));
19150 return emit_move_insn (sp_reg_rtx, frame_reg_rtx);
19152 else if (sp_offset != 0)
19154 /* If we are restoring registers out-of-line, we will be using the
19155 "exit" variants of the restore routines, which will reset the
19156 stack for us. But we do need to point r11 into the right place
19157 for those routines. */
19158 rtx dest_reg = (savres
19159 ? gen_rtx_REG (Pmode, 11)
19162 rtx insn = emit_insn (gen_add3_insn (dest_reg, sp_reg_rtx,
19163 GEN_INT (sp_offset)));
19170 /* Construct a parallel rtx describing the effect of a call to an
19171 out-of-line register save/restore routine, and emit the insn
19172 or jump_insn as appropriate. */
19175 rs6000_emit_savres_rtx (rs6000_stack_t *info,
19176 rtx frame_reg_rtx, int save_area_offset,
19177 enum machine_mode reg_mode,
19178 bool savep, bool gpr, bool lr)
19181 int offset, start_reg, end_reg, n_regs, use_reg;
19182 int reg_size = GET_MODE_SIZE (reg_mode);
19189 ? info->first_gp_reg_save
19190 : info->first_fp_reg_save);
19191 end_reg = gpr ? 32 : 64;
19192 n_regs = end_reg - start_reg;
19193 p = rtvec_alloc ((lr ? 4 : 3) + n_regs);
19196 RTVEC_ELT (p, offset++) = ret_rtx;
19198 RTVEC_ELT (p, offset++)
19199 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
19201 sym = rs6000_savres_routine_sym (info, savep, gpr, lr);
19202 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
19203 use_reg = DEFAULT_ABI == ABI_AIX ? (gpr && !lr ? 12 : 1)
19204 : DEFAULT_ABI == ABI_DARWIN && !gpr ? 1
19206 RTVEC_ELT (p, offset++)
19207 = gen_rtx_USE (VOIDmode,
19208 gen_rtx_REG (Pmode, use_reg));
19210 for (i = 0; i < end_reg - start_reg; i++)
19212 rtx addr, reg, mem;
19213 reg = gen_rtx_REG (reg_mode, start_reg + i);
19214 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19215 GEN_INT (save_area_offset + reg_size*i));
19216 mem = gen_frame_mem (reg_mode, addr);
19218 RTVEC_ELT (p, i + offset) = gen_rtx_SET (VOIDmode,
19220 savep ? reg : mem);
19225 rtx addr, reg, mem;
19226 reg = gen_rtx_REG (Pmode, 0);
19227 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19228 GEN_INT (info->lr_save_offset));
19229 mem = gen_frame_mem (Pmode, addr);
19230 RTVEC_ELT (p, i + offset) = gen_rtx_SET (VOIDmode, mem, reg);
19233 par = gen_rtx_PARALLEL (VOIDmode, p);
19237 insn = emit_jump_insn (par);
19238 JUMP_LABEL (insn) = ret_rtx;
19241 insn = emit_insn (par);
19245 /* Determine whether the gp REG is really used. */
19248 rs6000_reg_live_or_pic_offset_p (int reg)
19250 /* If the function calls eh_return, claim used all the registers that would
19251 be checked for liveness otherwise. This is required for the PIC offset
19252 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
19253 register allocation purposes in this case. */
19255 return (((crtl->calls_eh_return || df_regs_ever_live_p (reg))
19256 && (!call_used_regs[reg]
19257 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19258 && !TARGET_SINGLE_PIC_BASE
19259 && TARGET_TOC && TARGET_MINIMAL_TOC)))
19260 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
19261 && !TARGET_SINGLE_PIC_BASE
19262 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
19263 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
19266 /* Emit function prologue as insns. */
19269 rs6000_emit_prologue (void)
19271 rs6000_stack_t *info = rs6000_stack_info ();
19272 enum machine_mode reg_mode = Pmode;
19273 int reg_size = TARGET_32BIT ? 4 : 8;
19274 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
19275 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
19276 rtx frame_reg_rtx = sp_reg_rtx;
19277 rtx cr_save_rtx = NULL_RTX;
19280 int saving_FPRs_inline;
19281 int saving_GPRs_inline;
19282 int using_store_multiple;
19283 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
19284 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
19285 && call_used_regs[STATIC_CHAIN_REGNUM]);
19286 HOST_WIDE_INT sp_offset = 0;
19288 if (flag_stack_usage_info)
19289 current_function_static_stack_size = info->total_size;
19291 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK && info->total_size)
19292 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT, info->total_size);
19294 if (TARGET_FIX_AND_CONTINUE)
19296 /* gdb on darwin arranges to forward a function from the old
19297 address by modifying the first 5 instructions of the function
19298 to branch to the overriding function. This is necessary to
19299 permit function pointers that point to the old function to
19300 actually forward to the new function. */
19301 emit_insn (gen_nop ());
19302 emit_insn (gen_nop ());
19303 emit_insn (gen_nop ());
19304 emit_insn (gen_nop ());
19305 emit_insn (gen_nop ());
19308 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
19310 reg_mode = V2SImode;
19314 strategy = info->savres_strategy;
19315 using_store_multiple = strategy & SAVRES_MULTIPLE;
19316 saving_FPRs_inline = strategy & SAVE_INLINE_FPRS;
19317 saving_GPRs_inline = strategy & SAVE_INLINE_GPRS;
19319 /* For V.4, update stack before we do any saving and set back pointer. */
19320 if (! WORLD_SAVE_P (info)
19322 && (DEFAULT_ABI == ABI_V4
19323 || crtl->calls_eh_return))
19325 bool need_r11 = (TARGET_SPE
19326 ? (!saving_GPRs_inline
19327 && info->spe_64bit_regs_used == 0)
19328 : (!saving_FPRs_inline || !saving_GPRs_inline));
19329 rtx copy_reg = need_r11 ? gen_rtx_REG (Pmode, 11) : NULL;
19331 if (info->total_size < 32767)
19332 sp_offset = info->total_size;
19334 frame_reg_rtx = copy_reg;
19335 else if (info->cr_save_p
19337 || info->first_fp_reg_save < 64
19338 || info->first_gp_reg_save < 32
19339 || info->altivec_size != 0
19340 || info->vrsave_mask != 0
19341 || crtl->calls_eh_return)
19343 copy_reg = frame_ptr_rtx;
19344 frame_reg_rtx = copy_reg;
19348 /* The prologue won't be saving any regs so there is no need
19349 to set up a frame register to access any frame save area.
19350 We also won't be using sp_offset anywhere below, but set
19351 the correct value anyway to protect against future
19352 changes to this function. */
19353 sp_offset = info->total_size;
19355 rs6000_emit_allocate_stack (info->total_size, copy_reg);
19356 if (frame_reg_rtx != sp_reg_rtx)
19357 rs6000_emit_stack_tie ();
19360 /* Handle world saves specially here. */
19361 if (WORLD_SAVE_P (info))
19368 /* save_world expects lr in r0. */
19369 reg0 = gen_rtx_REG (Pmode, 0);
19370 if (info->lr_save_p)
19372 insn = emit_move_insn (reg0,
19373 gen_rtx_REG (Pmode, LR_REGNO));
19374 RTX_FRAME_RELATED_P (insn) = 1;
19377 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
19378 assumptions about the offsets of various bits of the stack
19380 gcc_assert (info->gp_save_offset == -220
19381 && info->fp_save_offset == -144
19382 && info->lr_save_offset == 8
19383 && info->cr_save_offset == 4
19386 && (!crtl->calls_eh_return
19387 || info->ehrd_offset == -432)
19388 && info->vrsave_save_offset == -224
19389 && info->altivec_save_offset == -416);
19391 treg = gen_rtx_REG (SImode, 11);
19392 emit_move_insn (treg, GEN_INT (-info->total_size));
19394 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
19395 in R11. It also clobbers R12, so beware! */
19397 /* Preserve CR2 for save_world prologues */
19399 sz += 32 - info->first_gp_reg_save;
19400 sz += 64 - info->first_fp_reg_save;
19401 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
19402 p = rtvec_alloc (sz);
19404 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
19405 gen_rtx_REG (SImode,
19407 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
19408 gen_rtx_SYMBOL_REF (Pmode,
19410 /* We do floats first so that the instruction pattern matches
19412 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19414 rtx reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
19415 ? DFmode : SFmode),
19416 info->first_fp_reg_save + i);
19417 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19418 GEN_INT (info->fp_save_offset
19419 + sp_offset + 8 * i));
19420 rtx mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
19421 ? DFmode : SFmode), addr);
19423 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
19425 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
19427 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
19428 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19429 GEN_INT (info->altivec_save_offset
19430 + sp_offset + 16 * i));
19431 rtx mem = gen_frame_mem (V4SImode, addr);
19433 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
19435 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19437 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
19438 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19439 GEN_INT (info->gp_save_offset
19440 + sp_offset + reg_size * i));
19441 rtx mem = gen_frame_mem (reg_mode, addr);
19443 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
19447 /* CR register traditionally saved as CR2. */
19448 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
19449 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19450 GEN_INT (info->cr_save_offset
19452 rtx mem = gen_frame_mem (reg_mode, addr);
19454 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
19456 /* Explain about use of R0. */
19457 if (info->lr_save_p)
19459 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19460 GEN_INT (info->lr_save_offset
19462 rtx mem = gen_frame_mem (reg_mode, addr);
19464 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
19466 /* Explain what happens to the stack pointer. */
19468 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
19469 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
19472 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19473 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19474 treg, GEN_INT (-info->total_size));
19475 sp_offset = info->total_size;
19478 /* If we use the link register, get it into r0. */
19479 if (!WORLD_SAVE_P (info) && info->lr_save_p)
19481 rtx addr, reg, mem;
19483 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
19484 gen_rtx_REG (Pmode, LR_REGNO));
19485 RTX_FRAME_RELATED_P (insn) = 1;
19487 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
19488 | SAVE_NOINLINE_FPRS_SAVES_LR)))
19490 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19491 GEN_INT (info->lr_save_offset + sp_offset));
19492 reg = gen_rtx_REG (Pmode, 0);
19493 mem = gen_rtx_MEM (Pmode, addr);
19494 /* This should not be of rs6000_sr_alias_set, because of
19495 __builtin_return_address. */
19497 insn = emit_move_insn (mem, reg);
19498 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19499 NULL_RTX, NULL_RTX);
19503 /* If we need to save CR, put it into r12 or r11. */
19504 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
19509 = gen_rtx_REG (SImode, DEFAULT_ABI == ABI_AIX && !saving_GPRs_inline
19511 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
19512 RTX_FRAME_RELATED_P (insn) = 1;
19513 /* Now, there's no way that dwarf2out_frame_debug_expr is going
19514 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
19515 But that's OK. All we have to do is specify that _one_ condition
19516 code register is saved in this stack slot. The thrower's epilogue
19517 will then restore all the call-saved registers.
19518 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
19519 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
19520 gen_rtx_REG (SImode, CR2_REGNO));
19521 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
19524 /* Do any required saving of fpr's. If only one or two to save, do
19525 it ourselves. Otherwise, call function. */
19526 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
19529 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19530 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
19531 && ! call_used_regs[info->first_fp_reg_save+i]))
19532 emit_frame_save (frame_reg_rtx, frame_ptr_rtx,
19533 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
19535 info->first_fp_reg_save + i,
19536 info->fp_save_offset + sp_offset + 8 * i,
19539 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
19541 insn = rs6000_emit_savres_rtx (info, frame_reg_rtx,
19542 info->fp_save_offset + sp_offset,
19544 /*savep=*/true, /*gpr=*/false,
19546 & SAVE_NOINLINE_FPRS_SAVES_LR)
19548 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19549 NULL_RTX, NULL_RTX);
19552 /* Save GPRs. This is done as a PARALLEL if we are using
19553 the store-multiple instructions. */
19554 if (!WORLD_SAVE_P (info)
19556 && info->spe_64bit_regs_used != 0
19557 && info->first_gp_reg_save != 32)
19560 rtx spe_save_area_ptr;
19561 int save_ptr_to_sp;
19562 int ool_adjust = 0;
19564 /* Determine whether we can address all of the registers that need
19565 to be saved with an offset from frame_reg_rtx that fits in
19566 the small const field for SPE memory instructions. */
19567 int spe_regs_addressable
19568 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + sp_offset
19569 + reg_size * (32 - info->first_gp_reg_save - 1))
19570 && saving_GPRs_inline);
19573 if (spe_regs_addressable)
19575 spe_save_area_ptr = frame_reg_rtx;
19576 save_ptr_to_sp = info->total_size - sp_offset;
19577 spe_offset = info->spe_gp_save_offset + sp_offset;
19581 /* Make r11 point to the start of the SPE save area. We need
19582 to be careful here if r11 is holding the static chain. If
19583 it is, then temporarily save it in r0. */
19586 if (!saving_GPRs_inline)
19587 ool_adjust = 8 * (info->first_gp_reg_save
19588 - (FIRST_SAVRES_REGISTER + 1));
19589 offset = info->spe_gp_save_offset + sp_offset - ool_adjust;
19590 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
19591 save_ptr_to_sp = info->total_size - sp_offset + offset;
19594 if (using_static_chain_p)
19596 rtx r0 = gen_rtx_REG (Pmode, 0);
19597 gcc_assert (info->first_gp_reg_save > 11);
19599 emit_move_insn (r0, spe_save_area_ptr);
19601 emit_insn (gen_addsi3 (spe_save_area_ptr,
19602 frame_reg_rtx, GEN_INT (offset)));
19603 if (REGNO (frame_reg_rtx) == 11)
19604 sp_offset = -info->spe_gp_save_offset + ool_adjust;
19607 if (saving_GPRs_inline)
19609 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19610 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
19612 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
19613 rtx offset, addr, mem;
19615 /* We're doing all this to ensure that the offset fits into
19616 the immediate offset of 'evstdd'. */
19617 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
19619 offset = GEN_INT (reg_size * i + spe_offset);
19620 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
19621 mem = gen_rtx_MEM (V2SImode, addr);
19623 insn = emit_move_insn (mem, reg);
19625 rs6000_frame_related (insn,
19626 spe_save_area_ptr, save_ptr_to_sp,
19627 NULL_RTX, NULL_RTX);
19632 insn = rs6000_emit_savres_rtx (info, spe_save_area_ptr,
19633 ool_adjust, reg_mode,
19634 /*savep=*/true, /*gpr=*/true,
19637 rs6000_frame_related (insn, spe_save_area_ptr, save_ptr_to_sp,
19638 NULL_RTX, NULL_RTX);
19641 /* Move the static chain pointer back. */
19642 if (using_static_chain_p && !spe_regs_addressable)
19643 emit_move_insn (spe_save_area_ptr, gen_rtx_REG (Pmode, 0));
19645 else if (!WORLD_SAVE_P (info) && !saving_GPRs_inline)
19647 if (DEFAULT_ABI == ABI_DARWIN)
19649 rtx dest_reg = gen_rtx_REG (Pmode, 11);
19650 if (info->first_fp_reg_save == 64)
19652 /* we only need a copy, no fprs were saved. */
19653 if (dest_reg != frame_reg_rtx)
19654 emit_move_insn (dest_reg, frame_reg_rtx);
19658 int save_off = 8 * (64 - info->first_fp_reg_save);
19659 rtx offset = GEN_INT (sp_offset - save_off);
19661 if (REGNO (dest_reg) == REGNO (frame_reg_rtx))
19662 sp_offset = save_off;
19663 emit_insn (gen_add3_insn (dest_reg, frame_reg_rtx, offset));
19666 /* Need to adjust r11 (r12) if we saved any FPRs. */
19667 else if (info->first_fp_reg_save != 64)
19669 rtx dest_reg = gen_rtx_REG (Pmode, DEFAULT_ABI == ABI_AIX ? 12 : 11);
19670 int save_off = 8 * (64 - info->first_fp_reg_save);
19671 rtx offset = GEN_INT (sp_offset - save_off);
19673 if (REGNO (dest_reg) == REGNO (frame_reg_rtx))
19674 sp_offset = save_off;
19675 emit_insn (gen_add3_insn (dest_reg, frame_reg_rtx, offset));
19678 insn = rs6000_emit_savres_rtx (info, frame_reg_rtx,
19679 info->gp_save_offset + sp_offset,
19681 /*savep=*/true, /*gpr=*/true,
19683 & SAVE_NOINLINE_GPRS_SAVES_LR)
19685 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19686 NULL_RTX, NULL_RTX);
19688 else if (!WORLD_SAVE_P (info) && using_store_multiple)
19692 p = rtvec_alloc (32 - info->first_gp_reg_save);
19693 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19695 rtx addr, reg, mem;
19696 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
19697 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19698 GEN_INT (info->gp_save_offset
19701 mem = gen_frame_mem (reg_mode, addr);
19703 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
19705 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
19706 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19707 NULL_RTX, NULL_RTX);
19709 else if (!WORLD_SAVE_P (info))
19712 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
19713 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
19715 rtx addr, reg, mem;
19716 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
19718 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19719 GEN_INT (info->gp_save_offset
19722 mem = gen_frame_mem (reg_mode, addr);
19724 insn = emit_move_insn (mem, reg);
19725 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19726 NULL_RTX, NULL_RTX);
19730 /* ??? There's no need to emit actual instructions here, but it's the
19731 easiest way to get the frame unwind information emitted. */
19732 if (crtl->calls_eh_return)
19734 unsigned int i, regno;
19738 regno = EH_RETURN_DATA_REGNO (i);
19739 if (regno == INVALID_REGNUM)
19742 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
19743 info->ehrd_offset + sp_offset
19744 + reg_size * (int) i,
19749 /* In AIX ABI we need to make sure r2 is really saved. */
19750 if (TARGET_AIX && crtl->calls_eh_return)
19752 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
19753 rtx save_insn, join_insn, note;
19754 long toc_restore_insn;
19756 gcc_assert (frame_reg_rtx == frame_ptr_rtx
19757 || frame_reg_rtx == sp_reg_rtx);
19758 tmp_reg = gen_rtx_REG (Pmode, 11);
19759 tmp_reg_si = gen_rtx_REG (SImode, 11);
19760 if (using_static_chain_p)
19761 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
19762 gcc_assert (saving_GPRs_inline && saving_FPRs_inline);
19763 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
19764 /* Peek at instruction to which this function returns. If it's
19765 restoring r2, then we know we've already saved r2. We can't
19766 unconditionally save r2 because the value we have will already
19767 be updated if we arrived at this function via a plt call or
19768 toc adjusting stub. */
19769 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
19770 toc_restore_insn = TARGET_32BIT ? 0x80410014 : 0xE8410028;
19771 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
19772 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
19773 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
19774 validate_condition_mode (EQ, CCUNSmode);
19775 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
19776 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
19777 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
19778 toc_save_done = gen_label_rtx ();
19779 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
19780 gen_rtx_EQ (VOIDmode, compare_result,
19782 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
19784 jump = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, jump));
19785 JUMP_LABEL (jump) = toc_save_done;
19786 LABEL_NUSES (toc_save_done) += 1;
19788 save_insn = emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode,
19789 TOC_REGNUM, sp_offset + 5 * reg_size,
19792 emit_label (toc_save_done);
19794 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
19795 have a CFG that has different saves along different paths.
19796 Move the note to a dummy blockage insn, which describes that
19797 R2 is unconditionally saved after the label. */
19798 /* ??? An alternate representation might be a special insn pattern
19799 containing both the branch and the store. That might let the
19800 code that minimizes the number of DW_CFA_advance opcodes better
19801 freedom in placing the annotations. */
19802 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
19804 remove_note (save_insn, note);
19805 RTX_FRAME_RELATED_P (save_insn) = 0;
19807 join_insn = emit_insn (gen_blockage ());
19808 REG_NOTES (join_insn) = note;
19809 RTX_FRAME_RELATED_P (join_insn) = 1;
19811 if (using_static_chain_p)
19812 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
19815 /* Save CR if we use any that must be preserved. */
19816 if (!WORLD_SAVE_P (info) && info->cr_save_p)
19818 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
19819 GEN_INT (info->cr_save_offset + sp_offset));
19820 rtx mem = gen_frame_mem (SImode, addr);
19821 /* See the large comment above about why CR2_REGNO is used. */
19822 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
19824 /* If r12 was used to hold the original sp, copy cr into r0 now
19826 if (REGNO (frame_reg_rtx) == 12)
19830 cr_save_rtx = gen_rtx_REG (SImode, 0);
19831 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
19832 RTX_FRAME_RELATED_P (insn) = 1;
19833 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
19834 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
19836 insn = emit_move_insn (mem, cr_save_rtx);
19838 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19839 NULL_RTX, NULL_RTX);
19842 /* Update stack and set back pointer unless this is V.4,
19843 for which it was done previously. */
19844 if (!WORLD_SAVE_P (info) && info->push_p
19845 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
19847 rtx copy_reg = NULL;
19849 if (info->total_size < 32767)
19850 sp_offset = info->total_size;
19851 else if (info->altivec_size != 0
19852 || info->vrsave_mask != 0)
19854 copy_reg = frame_ptr_rtx;
19855 frame_reg_rtx = copy_reg;
19858 sp_offset = info->total_size;
19859 rs6000_emit_allocate_stack (info->total_size, copy_reg);
19860 if (frame_reg_rtx != sp_reg_rtx)
19861 rs6000_emit_stack_tie ();
19864 /* Set frame pointer, if needed. */
19865 if (frame_pointer_needed)
19867 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
19869 RTX_FRAME_RELATED_P (insn) = 1;
19872 /* Save AltiVec registers if needed. Save here because the red zone does
19873 not include AltiVec registers. */
19874 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
19878 /* There should be a non inline version of this, for when we
19879 are saving lots of vector registers. */
19880 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
19881 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
19883 rtx areg, savereg, mem;
19886 offset = info->altivec_save_offset + sp_offset
19887 + 16 * (i - info->first_altivec_reg_save);
19889 savereg = gen_rtx_REG (V4SImode, i);
19891 areg = gen_rtx_REG (Pmode, 0);
19892 emit_move_insn (areg, GEN_INT (offset));
19894 /* AltiVec addressing mode is [reg+reg]. */
19895 mem = gen_frame_mem (V4SImode,
19896 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
19898 insn = emit_move_insn (mem, savereg);
19900 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
19901 areg, GEN_INT (offset));
19905 /* VRSAVE is a bit vector representing which AltiVec registers
19906 are used. The OS uses this to determine which vector
19907 registers to save on a context switch. We need to save
19908 VRSAVE on the stack frame, add whatever AltiVec registers we
19909 used in this function, and do the corresponding magic in the
19912 if (!WORLD_SAVE_P (info)
19914 && TARGET_ALTIVEC_VRSAVE
19915 && info->vrsave_mask != 0)
19917 rtx reg, mem, vrsave;
19920 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
19921 as frame_reg_rtx and r11 as the static chain pointer for
19922 nested functions. */
19923 reg = gen_rtx_REG (SImode, 0);
19924 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
19926 emit_insn (gen_get_vrsave_internal (reg));
19928 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
19931 offset = info->vrsave_save_offset + sp_offset;
19932 mem = gen_frame_mem (SImode,
19933 gen_rtx_PLUS (Pmode, frame_reg_rtx,
19934 GEN_INT (offset)));
19935 insn = emit_move_insn (mem, reg);
19937 /* Include the registers in the mask. */
19938 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
19940 insn = emit_insn (generate_set_vrsave (reg, info, 0));
19943 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
19944 if (!TARGET_SINGLE_PIC_BASE
19945 && ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
19946 || (DEFAULT_ABI == ABI_V4
19947 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
19948 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
19950 /* If emit_load_toc_table will use the link register, we need to save
19951 it. We use R12 for this purpose because emit_load_toc_table
19952 can use register 0. This allows us to use a plain 'blr' to return
19953 from the procedure more often. */
19954 int save_LR_around_toc_setup = (TARGET_ELF
19955 && DEFAULT_ABI != ABI_AIX
19957 && ! info->lr_save_p
19958 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
19959 if (save_LR_around_toc_setup)
19961 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
19963 insn = emit_move_insn (frame_ptr_rtx, lr);
19964 RTX_FRAME_RELATED_P (insn) = 1;
19966 rs6000_emit_load_toc_table (TRUE);
19968 insn = emit_move_insn (lr, frame_ptr_rtx);
19969 add_reg_note (insn, REG_CFA_RESTORE, lr);
19970 RTX_FRAME_RELATED_P (insn) = 1;
19973 rs6000_emit_load_toc_table (TRUE);
19977 if (!TARGET_SINGLE_PIC_BASE
19978 && DEFAULT_ABI == ABI_DARWIN
19979 && flag_pic && crtl->uses_pic_offset_table)
19981 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
19982 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
19984 /* Save and restore LR locally around this call (in R0). */
19985 if (!info->lr_save_p)
19986 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
19988 emit_insn (gen_load_macho_picbase (src));
19990 emit_move_insn (gen_rtx_REG (Pmode,
19991 RS6000_PIC_OFFSET_TABLE_REGNUM),
19994 if (!info->lr_save_p)
19995 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
19999 /* If we need to, save the TOC register after doing the stack setup.
20000 Do not emit eh frame info for this save. The unwinder wants info,
20001 conceptually attached to instructions in this function, about
20002 register values in the caller of this function. This R2 may have
20003 already been changed from the value in the caller.
20004 We don't attempt to write accurate DWARF EH frame info for R2
20005 because code emitted by gcc for a (non-pointer) function call
20006 doesn't save and restore R2. Instead, R2 is managed out-of-line
20007 by a linker generated plt call stub when the function resides in
20008 a shared library. This behaviour is costly to describe in DWARF,
20009 both in terms of the size of DWARF info and the time taken in the
20010 unwinder to interpret it. R2 changes, apart from the
20011 calls_eh_return case earlier in this function, are handled by
20012 linux-unwind.h frob_update_context. */
20013 if (rs6000_save_toc_in_prologue_p ())
20015 rtx addr = gen_rtx_PLUS (Pmode, sp_reg_rtx, GEN_INT (5 * reg_size));
20016 rtx mem = gen_frame_mem (reg_mode, addr);
20017 emit_move_insn (mem, gen_rtx_REG (reg_mode, TOC_REGNUM));
20021 /* Write function prologue. */
20024 rs6000_output_function_prologue (FILE *file,
20025 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
20027 rs6000_stack_t *info = rs6000_stack_info ();
20029 if (TARGET_DEBUG_STACK)
20030 debug_stack_info (info);
20032 /* Write .extern for any function we will call to save and restore
20034 if (info->first_fp_reg_save < 64
20038 int regno = info->first_fp_reg_save - 32;
20040 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
20042 name = rs6000_savres_routine_name (info, regno, /*savep=*/true,
20043 /*gpr=*/false, /*lr=*/false);
20044 fprintf (file, "\t.extern %s\n", name);
20046 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
20048 name = rs6000_savres_routine_name (info, regno, /*savep=*/false,
20049 /*gpr=*/false, /*lr=*/true);
20050 fprintf (file, "\t.extern %s\n", name);
20054 /* Write .extern for AIX common mode routines, if needed. */
20055 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
20057 fputs ("\t.extern __mulh\n", file);
20058 fputs ("\t.extern __mull\n", file);
20059 fputs ("\t.extern __divss\n", file);
20060 fputs ("\t.extern __divus\n", file);
20061 fputs ("\t.extern __quoss\n", file);
20062 fputs ("\t.extern __quous\n", file);
20063 common_mode_defined = 1;
20066 rs6000_pic_labelno++;
20069 /* Non-zero if vmx regs are restored before the frame pop, zero if
20070 we restore after the pop when possible. */
20071 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
20073 /* Reload CR from REG. */
20076 rs6000_restore_saved_cr (rtx reg, int using_mfcr_multiple)
20081 if (using_mfcr_multiple)
20083 for (i = 0; i < 8; i++)
20084 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
20086 gcc_assert (count);
20089 if (using_mfcr_multiple && count > 1)
20094 p = rtvec_alloc (count);
20097 for (i = 0; i < 8; i++)
20098 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
20100 rtvec r = rtvec_alloc (2);
20101 RTVEC_ELT (r, 0) = reg;
20102 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
20103 RTVEC_ELT (p, ndx) =
20104 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
20105 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
20108 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20109 gcc_assert (ndx == count);
20112 for (i = 0; i < 8; i++)
20113 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
20115 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
20121 /* Return true if OFFSET from stack pointer can be clobbered by signals.
20122 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
20123 below stack pointer not cloberred by signals. */
20126 offset_below_red_zone_p (HOST_WIDE_INT offset)
20128 return offset < (DEFAULT_ABI == ABI_V4
20130 : TARGET_32BIT ? -220 : -288);
20133 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
20136 emit_cfa_restores (rtx cfa_restores)
20138 rtx insn = get_last_insn ();
20139 rtx *loc = ®_NOTES (insn);
20142 loc = &XEXP (*loc, 1);
20143 *loc = cfa_restores;
20144 RTX_FRAME_RELATED_P (insn) = 1;
20147 /* Emit function epilogue as insns. */
20150 rs6000_emit_epilogue (int sibcall)
20152 rs6000_stack_t *info;
20153 int restoring_GPRs_inline;
20154 int restoring_FPRs_inline;
20155 int using_load_multiple;
20156 int using_mtcr_multiple;
20157 int use_backchain_to_restore_sp;
20161 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
20162 rtx frame_reg_rtx = sp_reg_rtx;
20163 rtx cfa_restores = NULL_RTX;
20165 rtx cr_save_reg = NULL_RTX;
20166 enum machine_mode reg_mode = Pmode;
20167 int reg_size = TARGET_32BIT ? 4 : 8;
20170 info = rs6000_stack_info ();
20172 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
20174 reg_mode = V2SImode;
20178 strategy = info->savres_strategy;
20179 using_load_multiple = strategy & SAVRES_MULTIPLE;
20180 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
20181 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
20182 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
20183 || rs6000_cpu == PROCESSOR_PPC603
20184 || rs6000_cpu == PROCESSOR_PPC750
20186 /* Restore via the backchain when we have a large frame, since this
20187 is more efficient than an addis, addi pair. The second condition
20188 here will not trigger at the moment; We don't actually need a
20189 frame pointer for alloca, but the generic parts of the compiler
20190 give us one anyway. */
20191 use_backchain_to_restore_sp = (info->total_size > 32767 - info->lr_save_offset
20192 || (cfun->calls_alloca
20193 && !frame_pointer_needed));
20194 restore_lr = (info->lr_save_p
20195 && (restoring_FPRs_inline
20196 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
20197 && (restoring_GPRs_inline
20198 || info->first_fp_reg_save < 64));
20200 if (WORLD_SAVE_P (info))
20204 const char *alloc_rname;
20207 /* eh_rest_world_r10 will return to the location saved in the LR
20208 stack slot (which is not likely to be our caller.)
20209 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
20210 rest_world is similar, except any R10 parameter is ignored.
20211 The exception-handling stuff that was here in 2.95 is no
20212 longer necessary. */
20216 + 32 - info->first_gp_reg_save
20217 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
20218 + 63 + 1 - info->first_fp_reg_save);
20220 strcpy (rname, ((crtl->calls_eh_return) ?
20221 "*eh_rest_world_r10" : "*rest_world"));
20222 alloc_rname = ggc_strdup (rname);
20225 RTVEC_ELT (p, j++) = ret_rtx;
20226 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
20227 gen_rtx_REG (Pmode,
20230 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
20231 /* The instruction pattern requires a clobber here;
20232 it is shared with the restVEC helper. */
20234 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
20237 /* CR register traditionally saved as CR2. */
20238 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
20239 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20240 GEN_INT (info->cr_save_offset));
20241 rtx mem = gen_frame_mem (reg_mode, addr);
20243 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
20245 if (flag_shrink_wrap)
20247 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20248 gen_rtx_REG (Pmode, LR_REGNO),
20250 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20254 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20256 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20257 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20258 GEN_INT (info->gp_save_offset
20260 rtx mem = gen_frame_mem (reg_mode, addr);
20262 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
20263 if (flag_shrink_wrap)
20264 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20266 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
20268 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
20269 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20270 GEN_INT (info->altivec_save_offset
20272 rtx mem = gen_frame_mem (V4SImode, addr);
20274 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
20275 if (flag_shrink_wrap)
20276 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20278 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
20280 rtx reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
20281 ? DFmode : SFmode),
20282 info->first_fp_reg_save + i);
20283 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20284 GEN_INT (info->fp_save_offset
20286 rtx mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
20287 ? DFmode : SFmode), addr);
20289 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
20290 if (flag_shrink_wrap)
20291 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20294 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
20296 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
20298 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
20300 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
20302 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
20303 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
20305 if (flag_shrink_wrap)
20307 REG_NOTES (insn) = cfa_restores;
20308 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20309 RTX_FRAME_RELATED_P (insn) = 1;
20314 /* frame_reg_rtx + sp_offset points to the top of this stack frame. */
20316 sp_offset = info->total_size;
20318 /* Restore AltiVec registers if we must do so before adjusting the
20320 if (TARGET_ALTIVEC_ABI
20321 && info->altivec_size != 0
20322 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20323 || (DEFAULT_ABI != ABI_V4
20324 && offset_below_red_zone_p (info->altivec_save_offset))))
20328 if (use_backchain_to_restore_sp)
20330 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20331 emit_move_insn (frame_reg_rtx,
20332 gen_rtx_MEM (Pmode, sp_reg_rtx));
20335 else if (frame_pointer_needed)
20336 frame_reg_rtx = hard_frame_pointer_rtx;
20338 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20339 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20341 rtx addr, areg, mem, reg;
20343 areg = gen_rtx_REG (Pmode, 0);
20345 (areg, GEN_INT (info->altivec_save_offset
20347 + 16 * (i - info->first_altivec_reg_save)));
20349 /* AltiVec addressing mode is [reg+reg]. */
20350 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
20351 mem = gen_frame_mem (V4SImode, addr);
20353 reg = gen_rtx_REG (V4SImode, i);
20354 emit_move_insn (reg, mem);
20355 if (flag_shrink_wrap
20356 || offset_below_red_zone_p (info->altivec_save_offset
20357 + (i - info->first_altivec_reg_save)
20359 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
20364 /* Restore VRSAVE if we must do so before adjusting the stack. */
20366 && TARGET_ALTIVEC_VRSAVE
20367 && info->vrsave_mask != 0
20368 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20369 || (DEFAULT_ABI != ABI_V4
20370 && offset_below_red_zone_p (info->vrsave_save_offset))))
20372 rtx addr, mem, reg;
20374 if (frame_reg_rtx == sp_reg_rtx)
20376 if (use_backchain_to_restore_sp)
20378 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20379 emit_move_insn (frame_reg_rtx,
20380 gen_rtx_MEM (Pmode, sp_reg_rtx));
20383 else if (frame_pointer_needed)
20384 frame_reg_rtx = hard_frame_pointer_rtx;
20387 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20388 GEN_INT (info->vrsave_save_offset + sp_offset));
20389 mem = gen_frame_mem (SImode, addr);
20390 reg = gen_rtx_REG (SImode, 12);
20391 emit_move_insn (reg, mem);
20393 emit_insn (generate_set_vrsave (reg, info, 1));
20397 /* If we have a large stack frame, restore the old stack pointer
20398 using the backchain. */
20399 if (use_backchain_to_restore_sp)
20401 if (frame_reg_rtx == sp_reg_rtx)
20403 /* Under V.4, don't reset the stack pointer until after we're done
20404 loading the saved registers. */
20405 if (DEFAULT_ABI == ABI_V4)
20406 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20408 insn = emit_move_insn (frame_reg_rtx,
20409 gen_rtx_MEM (Pmode, sp_reg_rtx));
20412 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20413 && DEFAULT_ABI == ABI_V4)
20414 /* frame_reg_rtx has been set up by the altivec restore. */
20418 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
20419 frame_reg_rtx = sp_reg_rtx;
20422 /* If we have a frame pointer, we can restore the old stack pointer
20424 else if (frame_pointer_needed)
20426 frame_reg_rtx = sp_reg_rtx;
20427 if (DEFAULT_ABI == ABI_V4)
20428 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20429 /* Prevent reordering memory accesses against stack pointer restore. */
20430 else if (cfun->calls_alloca
20431 || offset_below_red_zone_p (-info->total_size))
20433 rtx mem1 = gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx);
20434 rtx mem2 = gen_rtx_MEM (BLKmode, sp_reg_rtx);
20435 MEM_NOTRAP_P (mem1) = 1;
20436 MEM_NOTRAP_P (mem2) = 1;
20437 emit_insn (gen_frame_tie (mem1, mem2));
20440 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
20441 GEN_INT (info->total_size)));
20444 else if (info->push_p
20445 && DEFAULT_ABI != ABI_V4
20446 && !crtl->calls_eh_return)
20448 /* Prevent reordering memory accesses against stack pointer restore. */
20449 if (cfun->calls_alloca
20450 || offset_below_red_zone_p (-info->total_size))
20452 rtx mem = gen_rtx_MEM (BLKmode, sp_reg_rtx);
20453 MEM_NOTRAP_P (mem) = 1;
20454 emit_insn (gen_stack_tie (mem));
20456 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
20457 GEN_INT (info->total_size)));
20460 if (insn && frame_reg_rtx == sp_reg_rtx)
20464 REG_NOTES (insn) = cfa_restores;
20465 cfa_restores = NULL_RTX;
20467 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20468 RTX_FRAME_RELATED_P (insn) = 1;
20471 /* Restore AltiVec registers if we have not done so already. */
20472 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20473 && TARGET_ALTIVEC_ABI
20474 && info->altivec_size != 0
20475 && (DEFAULT_ABI == ABI_V4
20476 || !offset_below_red_zone_p (info->altivec_save_offset)))
20480 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
20481 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
20483 rtx addr, areg, mem, reg;
20485 areg = gen_rtx_REG (Pmode, 0);
20487 (areg, GEN_INT (info->altivec_save_offset
20489 + 16 * (i - info->first_altivec_reg_save)));
20491 /* AltiVec addressing mode is [reg+reg]. */
20492 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
20493 mem = gen_frame_mem (V4SImode, addr);
20495 reg = gen_rtx_REG (V4SImode, i);
20496 emit_move_insn (reg, mem);
20497 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20498 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
20503 /* Restore VRSAVE if we have not done so already. */
20504 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
20506 && TARGET_ALTIVEC_VRSAVE
20507 && info->vrsave_mask != 0
20508 && (DEFAULT_ABI == ABI_V4
20509 || !offset_below_red_zone_p (info->vrsave_save_offset)))
20511 rtx addr, mem, reg;
20513 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20514 GEN_INT (info->vrsave_save_offset + sp_offset));
20515 mem = gen_frame_mem (SImode, addr);
20516 reg = gen_rtx_REG (SImode, 12);
20517 emit_move_insn (reg, mem);
20519 emit_insn (generate_set_vrsave (reg, info, 1));
20522 /* Get the old lr if we saved it. If we are restoring registers
20523 out-of-line, then the out-of-line routines can do this for us. */
20524 if (restore_lr && restoring_GPRs_inline)
20526 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
20527 info->lr_save_offset + sp_offset);
20529 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
20532 /* Get the old cr if we saved it. */
20533 if (info->cr_save_p)
20535 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20536 GEN_INT (info->cr_save_offset + sp_offset));
20537 rtx mem = gen_frame_mem (SImode, addr);
20539 cr_save_reg = gen_rtx_REG (SImode,
20540 DEFAULT_ABI == ABI_AIX
20541 && !restoring_GPRs_inline
20542 && info->first_fp_reg_save < 64
20544 emit_move_insn (cr_save_reg, mem);
20547 /* Set LR here to try to overlap restores below. */
20548 if (restore_lr && restoring_GPRs_inline)
20549 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
20550 gen_rtx_REG (Pmode, 0));
20552 /* Load exception handler data registers, if needed. */
20553 if (crtl->calls_eh_return)
20555 unsigned int i, regno;
20559 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20560 GEN_INT (sp_offset + 5 * reg_size));
20561 rtx mem = gen_frame_mem (reg_mode, addr);
20563 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
20570 regno = EH_RETURN_DATA_REGNO (i);
20571 if (regno == INVALID_REGNUM)
20574 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
20575 info->ehrd_offset + sp_offset
20576 + reg_size * (int) i);
20578 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
20582 /* Restore GPRs. This is done as a PARALLEL if we are using
20583 the load-multiple instructions. */
20585 && info->spe_64bit_regs_used
20586 && info->first_gp_reg_save != 32)
20588 /* Determine whether we can address all of the registers that need
20589 to be saved with an offset from frame_reg_rtx that fits in
20590 the small const field for SPE memory instructions. */
20591 int spe_regs_addressable
20592 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + sp_offset
20593 + reg_size * (32 - info->first_gp_reg_save - 1))
20594 && restoring_GPRs_inline);
20596 int ool_adjust = 0;
20598 if (spe_regs_addressable)
20599 spe_offset = info->spe_gp_save_offset + sp_offset;
20602 rtx old_frame_reg_rtx = frame_reg_rtx;
20603 /* Make r11 point to the start of the SPE save area. We worried about
20604 not clobbering it when we were saving registers in the prologue.
20605 There's no need to worry here because the static chain is passed
20606 anew to every function. */
20608 if (!restoring_GPRs_inline)
20609 ool_adjust = 8 * (info->first_gp_reg_save
20610 - (FIRST_SAVRES_REGISTER + 1));
20611 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
20612 emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
20613 GEN_INT (info->spe_gp_save_offset
20616 /* Keep the invariant that frame_reg_rtx + sp_offset points
20617 at the top of the stack frame. */
20618 sp_offset = -info->spe_gp_save_offset + ool_adjust;
20623 if (restoring_GPRs_inline)
20625 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20626 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
20628 rtx offset, addr, mem, reg;
20630 /* We're doing all this to ensure that the immediate offset
20631 fits into the immediate field of 'evldd'. */
20632 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
20634 offset = GEN_INT (spe_offset + reg_size * i);
20635 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
20636 mem = gen_rtx_MEM (V2SImode, addr);
20637 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20639 emit_move_insn (reg, mem);
20643 rs6000_emit_savres_rtx (info, frame_reg_rtx,
20644 ool_adjust, reg_mode,
20645 /*savep=*/false, /*gpr=*/true,
20648 else if (!restoring_GPRs_inline)
20650 /* We are jumping to an out-of-line function. */
20651 bool can_use_exit = info->first_fp_reg_save == 64;
20653 /* Emit stack reset code if we need it. */
20656 rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
20657 sp_offset, can_use_exit);
20658 if (DEFAULT_ABI == ABI_DARWIN)
20659 /* we only need a copy, no fprs were saved. */
20660 emit_move_insn (gen_rtx_REG (Pmode, 11), frame_reg_rtx);
20662 if (info->cr_save_p)
20663 rs6000_restore_saved_cr (cr_save_reg, using_mtcr_multiple);
20667 rtx src_reg = gen_rtx_REG (Pmode, DEFAULT_ABI == ABI_AIX ? 12 : 11);
20669 emit_insn (gen_add3_insn (src_reg, frame_reg_rtx,
20670 GEN_INT (sp_offset - info->fp_size)));
20671 if (REGNO (frame_reg_rtx) == REGNO (src_reg))
20672 sp_offset = info->fp_size;
20675 rs6000_emit_savres_rtx (info, frame_reg_rtx,
20676 info->gp_save_offset, reg_mode,
20677 /*savep=*/false, /*gpr=*/true,
20678 /*lr=*/can_use_exit);
20680 else if (using_load_multiple)
20683 p = rtvec_alloc (32 - info->first_gp_reg_save);
20684 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20686 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20687 GEN_INT (info->gp_save_offset
20690 rtx mem = gen_frame_mem (reg_mode, addr);
20691 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20693 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, reg, mem);
20695 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
20699 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
20700 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
20702 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20703 GEN_INT (info->gp_save_offset
20706 rtx mem = gen_frame_mem (reg_mode, addr);
20707 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
20709 emit_move_insn (reg, mem);
20713 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20715 /* If the frame pointer was used then we can't delay emitting
20716 a REG_CFA_DEF_CFA note. This must happen on the insn that
20717 restores the frame pointer, r31. We may have already emitted
20718 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
20719 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
20720 be harmless if emitted. */
20721 if (frame_pointer_needed)
20723 insn = get_last_insn ();
20724 add_reg_note (insn, REG_CFA_DEF_CFA,
20725 plus_constant (frame_reg_rtx, sp_offset));
20726 RTX_FRAME_RELATED_P (insn) = 1;
20729 /* Set up cfa_restores. We always need these when
20730 shrink-wrapping. If not shrink-wrapping then we only need
20731 the cfa_restore when the stack location is no longer valid.
20732 The cfa_restores must be emitted on or before the insn that
20733 invalidates the stack, and of course must not be emitted
20734 before the insn that actually does the restore. The latter
20735 is why the LR cfa_restore condition below is a little
20736 complicated. It's also why it is a bad idea to emit the
20737 cfa_restores as a group on the last instruction here that
20738 actually does a restore: That insn may be reordered with
20739 respect to others doing restores. */
20740 if (info->cr_save_p)
20741 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20742 gen_rtx_REG (SImode, CR2_REGNO),
20744 if (flag_shrink_wrap
20746 || (info->lr_save_p
20747 && !restoring_GPRs_inline
20748 && info->first_fp_reg_save == 64)))
20749 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20750 gen_rtx_REG (Pmode, LR_REGNO),
20753 for (i = info->first_gp_reg_save; i < 32; i++)
20754 if (!restoring_GPRs_inline
20755 || using_load_multiple
20756 || rs6000_reg_live_or_pic_offset_p (i))
20758 rtx reg = gen_rtx_REG (reg_mode, i);
20760 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20764 if (!restoring_GPRs_inline
20765 && info->first_fp_reg_save == 64)
20767 /* We are jumping to an out-of-line function. */
20769 emit_cfa_restores (cfa_restores);
20773 if (restore_lr && !restoring_GPRs_inline)
20775 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
20776 info->lr_save_offset + sp_offset);
20778 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
20779 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
20780 gen_rtx_REG (Pmode, 0));
20783 /* Restore fpr's if we need to do it without calling a function. */
20784 if (restoring_FPRs_inline)
20785 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
20786 if ((df_regs_ever_live_p (info->first_fp_reg_save + i)
20787 && !call_used_regs[info->first_fp_reg_save + i]))
20789 rtx addr, mem, reg;
20790 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
20791 GEN_INT (info->fp_save_offset
20794 mem = gen_frame_mem (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
20795 ? DFmode : SFmode), addr);
20796 reg = gen_rtx_REG (((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
20797 ? DFmode : SFmode),
20798 info->first_fp_reg_save + i);
20800 emit_move_insn (reg, mem);
20801 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20802 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
20805 /* If we saved cr, restore it here. Just those that were used. */
20806 if (info->cr_save_p)
20807 rs6000_restore_saved_cr (cr_save_reg, using_mtcr_multiple);
20809 /* If this is V.4, unwind the stack pointer after all of the loads
20811 insn = rs6000_emit_stack_reset (info, sp_reg_rtx, frame_reg_rtx,
20812 sp_offset, !restoring_FPRs_inline);
20817 REG_NOTES (insn) = cfa_restores;
20818 cfa_restores = NULL_RTX;
20820 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
20821 RTX_FRAME_RELATED_P (insn) = 1;
20824 if (crtl->calls_eh_return)
20826 rtx sa = EH_RETURN_STACKADJ_RTX;
20827 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
20833 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
20834 if (! restoring_FPRs_inline)
20836 p = rtvec_alloc (4 + 64 - info->first_fp_reg_save);
20837 RTVEC_ELT (p, 0) = ret_rtx;
20843 /* We can't hang the cfa_restores off a simple return,
20844 since the shrink-wrap code sometimes uses an existing
20845 return. This means there might be a path from
20846 pre-prologue code to this return, and dwarf2cfi code
20847 wants the eh_frame unwinder state to be the same on
20848 all paths to any point. So we need to emit the
20849 cfa_restores before the return. For -m64 we really
20850 don't need epilogue cfa_restores at all, except for
20851 this irritating dwarf2cfi with shrink-wrap
20852 requirement; The stack red-zone means eh_frame info
20853 from the prologue telling the unwinder to restore
20854 from the stack is perfectly good right to the end of
20856 emit_insn (gen_blockage ());
20857 emit_cfa_restores (cfa_restores);
20858 cfa_restores = NULL_RTX;
20860 p = rtvec_alloc (2);
20861 RTVEC_ELT (p, 0) = simple_return_rtx;
20864 RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr)
20865 ? gen_rtx_USE (VOIDmode,
20866 gen_rtx_REG (Pmode, LR_REGNO))
20867 : gen_rtx_CLOBBER (VOIDmode,
20868 gen_rtx_REG (Pmode, LR_REGNO)));
20870 /* If we have to restore more than two FP registers, branch to the
20871 restore function. It will return to our caller. */
20872 if (! restoring_FPRs_inline)
20877 if ((DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20879 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
20880 gen_rtx_REG (Pmode, LR_REGNO),
20883 sym = rs6000_savres_routine_sym (info,
20887 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
20888 RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode,
20889 gen_rtx_REG (Pmode,
20890 DEFAULT_ABI == ABI_AIX
20892 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
20894 rtx addr, mem, reg;
20896 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
20897 GEN_INT (info->fp_save_offset + 8 * i));
20898 mem = gen_frame_mem (DFmode, addr);
20899 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
20901 RTVEC_ELT (p, i + 4) = gen_rtx_SET (VOIDmode, reg, mem);
20902 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
20903 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
20908 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
20914 /* Ensure the cfa_restores are hung off an insn that won't
20915 be reordered above other restores. */
20916 emit_insn (gen_blockage ());
20918 emit_cfa_restores (cfa_restores);
20922 /* Write function epilogue. */
20925 rs6000_output_function_epilogue (FILE *file,
20926 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
20929 macho_branch_islands ();
20930 /* Mach-O doesn't support labels at the end of objects, so if
20931 it looks like we might want one, insert a NOP. */
20933 rtx insn = get_last_insn ();
20934 rtx deleted_debug_label = NULL_RTX;
20937 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
20939 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
20940 notes only, instead set their CODE_LABEL_NUMBER to -1,
20941 otherwise there would be code generation differences
20942 in between -g and -g0. */
20943 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
20944 deleted_debug_label = insn;
20945 insn = PREV_INSN (insn);
20950 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
20951 fputs ("\tnop\n", file);
20952 else if (deleted_debug_label)
20953 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
20954 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
20955 CODE_LABEL_NUMBER (insn) = -1;
20959 /* Output a traceback table here. See /usr/include/sys/debug.h for info
20962 We don't output a traceback table if -finhibit-size-directive was
20963 used. The documentation for -finhibit-size-directive reads
20964 ``don't output a @code{.size} assembler directive, or anything
20965 else that would cause trouble if the function is split in the
20966 middle, and the two halves are placed at locations far apart in
20967 memory.'' The traceback table has this property, since it
20968 includes the offset from the start of the function to the
20969 traceback table itself.
20971 System V.4 Powerpc's (and the embedded ABI derived from it) use a
20972 different traceback table. */
20973 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
20974 && rs6000_traceback != traceback_none && !cfun->is_thunk)
20976 const char *fname = NULL;
20977 const char *language_string = lang_hooks.name;
20978 int fixed_parms = 0, float_parms = 0, parm_info = 0;
20980 int optional_tbtab;
20981 rs6000_stack_t *info = rs6000_stack_info ();
20983 if (rs6000_traceback == traceback_full)
20984 optional_tbtab = 1;
20985 else if (rs6000_traceback == traceback_part)
20986 optional_tbtab = 0;
20988 optional_tbtab = !optimize_size && !TARGET_ELF;
20990 if (optional_tbtab)
20992 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
20993 while (*fname == '.') /* V.4 encodes . in the name */
20996 /* Need label immediately before tbtab, so we can compute
20997 its offset from the function start. */
20998 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
20999 ASM_OUTPUT_LABEL (file, fname);
21002 /* The .tbtab pseudo-op can only be used for the first eight
21003 expressions, since it can't handle the possibly variable
21004 length fields that follow. However, if you omit the optional
21005 fields, the assembler outputs zeros for all optional fields
21006 anyways, giving each variable length field is minimum length
21007 (as defined in sys/debug.h). Thus we can not use the .tbtab
21008 pseudo-op at all. */
21010 /* An all-zero word flags the start of the tbtab, for debuggers
21011 that have to find it by searching forward from the entry
21012 point or from the current pc. */
21013 fputs ("\t.long 0\n", file);
21015 /* Tbtab format type. Use format type 0. */
21016 fputs ("\t.byte 0,", file);
21018 /* Language type. Unfortunately, there does not seem to be any
21019 official way to discover the language being compiled, so we
21020 use language_string.
21021 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
21022 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
21023 a number, so for now use 9. LTO and Go aren't assigned numbers
21024 either, so for now use 0. */
21025 if (! strcmp (language_string, "GNU C")
21026 || ! strcmp (language_string, "GNU GIMPLE")
21027 || ! strcmp (language_string, "GNU Go"))
21029 else if (! strcmp (language_string, "GNU F77")
21030 || ! strcmp (language_string, "GNU Fortran"))
21032 else if (! strcmp (language_string, "GNU Pascal"))
21034 else if (! strcmp (language_string, "GNU Ada"))
21036 else if (! strcmp (language_string, "GNU C++")
21037 || ! strcmp (language_string, "GNU Objective-C++"))
21039 else if (! strcmp (language_string, "GNU Java"))
21041 else if (! strcmp (language_string, "GNU Objective-C"))
21044 gcc_unreachable ();
21045 fprintf (file, "%d,", i);
21047 /* 8 single bit fields: global linkage (not set for C extern linkage,
21048 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
21049 from start of procedure stored in tbtab, internal function, function
21050 has controlled storage, function has no toc, function uses fp,
21051 function logs/aborts fp operations. */
21052 /* Assume that fp operations are used if any fp reg must be saved. */
21053 fprintf (file, "%d,",
21054 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
21056 /* 6 bitfields: function is interrupt handler, name present in
21057 proc table, function calls alloca, on condition directives
21058 (controls stack walks, 3 bits), saves condition reg, saves
21060 /* The `function calls alloca' bit seems to be set whenever reg 31 is
21061 set up as a frame pointer, even when there is no alloca call. */
21062 fprintf (file, "%d,",
21063 ((optional_tbtab << 6)
21064 | ((optional_tbtab & frame_pointer_needed) << 5)
21065 | (info->cr_save_p << 1)
21066 | (info->lr_save_p)));
21068 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
21070 fprintf (file, "%d,",
21071 (info->push_p << 7) | (64 - info->first_fp_reg_save));
21073 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
21074 fprintf (file, "%d,", (32 - first_reg_to_save ()));
21076 if (optional_tbtab)
21078 /* Compute the parameter info from the function decl argument
21081 int next_parm_info_bit = 31;
21083 for (decl = DECL_ARGUMENTS (current_function_decl);
21084 decl; decl = DECL_CHAIN (decl))
21086 rtx parameter = DECL_INCOMING_RTL (decl);
21087 enum machine_mode mode = GET_MODE (parameter);
21089 if (GET_CODE (parameter) == REG)
21091 if (SCALAR_FLOAT_MODE_P (mode))
21112 gcc_unreachable ();
21115 /* If only one bit will fit, don't or in this entry. */
21116 if (next_parm_info_bit > 0)
21117 parm_info |= (bits << (next_parm_info_bit - 1));
21118 next_parm_info_bit -= 2;
21122 fixed_parms += ((GET_MODE_SIZE (mode)
21123 + (UNITS_PER_WORD - 1))
21125 next_parm_info_bit -= 1;
21131 /* Number of fixed point parameters. */
21132 /* This is actually the number of words of fixed point parameters; thus
21133 an 8 byte struct counts as 2; and thus the maximum value is 8. */
21134 fprintf (file, "%d,", fixed_parms);
21136 /* 2 bitfields: number of floating point parameters (7 bits), parameters
21138 /* This is actually the number of fp registers that hold parameters;
21139 and thus the maximum value is 13. */
21140 /* Set parameters on stack bit if parameters are not in their original
21141 registers, regardless of whether they are on the stack? Xlc
21142 seems to set the bit when not optimizing. */
21143 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
21145 if (! optional_tbtab)
21148 /* Optional fields follow. Some are variable length. */
21150 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
21151 11 double float. */
21152 /* There is an entry for each parameter in a register, in the order that
21153 they occur in the parameter list. Any intervening arguments on the
21154 stack are ignored. If the list overflows a long (max possible length
21155 34 bits) then completely leave off all elements that don't fit. */
21156 /* Only emit this long if there was at least one parameter. */
21157 if (fixed_parms || float_parms)
21158 fprintf (file, "\t.long %d\n", parm_info);
21160 /* Offset from start of code to tb table. */
21161 fputs ("\t.long ", file);
21162 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
21163 RS6000_OUTPUT_BASENAME (file, fname);
21165 rs6000_output_function_entry (file, fname);
21168 /* Interrupt handler mask. */
21169 /* Omit this long, since we never set the interrupt handler bit
21172 /* Number of CTL (controlled storage) anchors. */
21173 /* Omit this long, since the has_ctl bit is never set above. */
21175 /* Displacement into stack of each CTL anchor. */
21176 /* Omit this list of longs, because there are no CTL anchors. */
21178 /* Length of function name. */
21181 fprintf (file, "\t.short %d\n", (int) strlen (fname));
21183 /* Function name. */
21184 assemble_string (fname, strlen (fname));
21186 /* Register for alloca automatic storage; this is always reg 31.
21187 Only emit this if the alloca bit was set above. */
21188 if (frame_pointer_needed)
21189 fputs ("\t.byte 31\n", file);
21191 fputs ("\t.align 2\n", file);
21195 /* A C compound statement that outputs the assembler code for a thunk
21196 function, used to implement C++ virtual function calls with
21197 multiple inheritance. The thunk acts as a wrapper around a virtual
21198 function, adjusting the implicit object parameter before handing
21199 control off to the real function.
21201 First, emit code to add the integer DELTA to the location that
21202 contains the incoming first argument. Assume that this argument
21203 contains a pointer, and is the one used to pass the `this' pointer
21204 in C++. This is the incoming argument *before* the function
21205 prologue, e.g. `%o0' on a sparc. The addition must preserve the
21206 values of all other incoming arguments.
21208 After the addition, emit code to jump to FUNCTION, which is a
21209 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
21210 not touch the return address. Hence returning from FUNCTION will
21211 return to whoever called the current `thunk'.
21213 The effect must be as if FUNCTION had been called directly with the
21214 adjusted first argument. This macro is responsible for emitting
21215 all of the code for a thunk function; output_function_prologue()
21216 and output_function_epilogue() are not invoked.
21218 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
21219 been extracted from it.) It might possibly be useful on some
21220 targets, but probably not.
21222 If you do not define this macro, the target-independent code in the
21223 C++ frontend will generate a less efficient heavyweight thunk that
21224 calls FUNCTION instead of jumping to it. The generic approach does
21225 not support varargs. */
21228 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
21229 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
21232 rtx this_rtx, insn, funexp;
21234 reload_completed = 1;
21235 epilogue_completed = 1;
21237 /* Mark the end of the (empty) prologue. */
21238 emit_note (NOTE_INSN_PROLOGUE_END);
21240 /* Find the "this" pointer. If the function returns a structure,
21241 the structure return pointer is in r3. */
21242 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
21243 this_rtx = gen_rtx_REG (Pmode, 4);
21245 this_rtx = gen_rtx_REG (Pmode, 3);
21247 /* Apply the constant offset, if required. */
21249 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
21251 /* Apply the offset from the vtable, if required. */
21254 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
21255 rtx tmp = gen_rtx_REG (Pmode, 12);
21257 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
21258 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
21260 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
21261 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
21265 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
21267 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
21269 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
21272 /* Generate a tail call to the target function. */
21273 if (!TREE_USED (function))
21275 assemble_external (function);
21276 TREE_USED (function) = 1;
21278 funexp = XEXP (DECL_RTL (function), 0);
21279 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
21282 if (MACHOPIC_INDIRECT)
21283 funexp = machopic_indirect_call_target (funexp);
21286 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
21287 generate sibcall RTL explicitly. */
21288 insn = emit_call_insn (
21289 gen_rtx_PARALLEL (VOIDmode,
21291 gen_rtx_CALL (VOIDmode,
21292 funexp, const0_rtx),
21293 gen_rtx_USE (VOIDmode, const0_rtx),
21294 gen_rtx_USE (VOIDmode,
21295 gen_rtx_REG (SImode,
21297 simple_return_rtx)));
21298 SIBLING_CALL_P (insn) = 1;
21301 /* Run just enough of rest_of_compilation to get the insns emitted.
21302 There's not really enough bulk here to make other passes such as
21303 instruction scheduling worth while. Note that use_thunk calls
21304 assemble_start_function and assemble_end_function. */
21305 insn = get_insns ();
21306 insn_locators_alloc ();
21307 shorten_branches (insn);
21308 final_start_function (insn, file, 1);
21309 final (insn, file, 1);
21310 final_end_function ();
21312 reload_completed = 0;
21313 epilogue_completed = 0;
21316 /* A quick summary of the various types of 'constant-pool tables'
21319 Target Flags Name One table per
21320 AIX (none) AIX TOC object file
21321 AIX -mfull-toc AIX TOC object file
21322 AIX -mminimal-toc AIX minimal TOC translation unit
21323 SVR4/EABI (none) SVR4 SDATA object file
21324 SVR4/EABI -fpic SVR4 pic object file
21325 SVR4/EABI -fPIC SVR4 PIC translation unit
21326 SVR4/EABI -mrelocatable EABI TOC function
21327 SVR4/EABI -maix AIX TOC object file
21328 SVR4/EABI -maix -mminimal-toc
21329 AIX minimal TOC translation unit
21331 Name Reg. Set by entries contains:
21332 made by addrs? fp? sum?
21334 AIX TOC 2 crt0 as Y option option
21335 AIX minimal TOC 30 prolog gcc Y Y option
21336 SVR4 SDATA 13 crt0 gcc N Y N
21337 SVR4 pic 30 prolog ld Y not yet N
21338 SVR4 PIC 30 prolog gcc Y option option
21339 EABI TOC 30 prolog gcc Y option option
21343 /* Hash functions for the hash table. */
21346 rs6000_hash_constant (rtx k)
21348 enum rtx_code code = GET_CODE (k);
21349 enum machine_mode mode = GET_MODE (k);
21350 unsigned result = (code << 3) ^ mode;
21351 const char *format;
21354 format = GET_RTX_FORMAT (code);
21355 flen = strlen (format);
21361 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
21364 if (mode != VOIDmode)
21365 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
21377 for (; fidx < flen; fidx++)
21378 switch (format[fidx])
21383 const char *str = XSTR (k, fidx);
21384 len = strlen (str);
21385 result = result * 613 + len;
21386 for (i = 0; i < len; i++)
21387 result = result * 613 + (unsigned) str[i];
21392 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
21396 result = result * 613 + (unsigned) XINT (k, fidx);
21399 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
21400 result = result * 613 + (unsigned) XWINT (k, fidx);
21404 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
21405 result = result * 613 + (unsigned) (XWINT (k, fidx)
21412 gcc_unreachable ();
21419 toc_hash_function (const void *hash_entry)
21421 const struct toc_hash_struct *thc =
21422 (const struct toc_hash_struct *) hash_entry;
21423 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
21426 /* Compare H1 and H2 for equivalence. */
21429 toc_hash_eq (const void *h1, const void *h2)
21431 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
21432 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
21434 if (((const struct toc_hash_struct *) h1)->key_mode
21435 != ((const struct toc_hash_struct *) h2)->key_mode)
21438 return rtx_equal_p (r1, r2);
21441 /* These are the names given by the C++ front-end to vtables, and
21442 vtable-like objects. Ideally, this logic should not be here;
21443 instead, there should be some programmatic way of inquiring as
21444 to whether or not an object is a vtable. */
21446 #define VTABLE_NAME_P(NAME) \
21447 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
21448 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
21449 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
21450 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
21451 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
21453 #ifdef NO_DOLLAR_IN_LABEL
21454 /* Return a GGC-allocated character string translating dollar signs in
21455 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
21458 rs6000_xcoff_strip_dollar (const char *name)
21464 q = (const char *) strchr (name, '$');
21466 if (q == 0 || q == name)
21469 len = strlen (name);
21470 strip = XALLOCAVEC (char, len + 1);
21471 strcpy (strip, name);
21472 p = strip + (q - name);
21476 p = strchr (p + 1, '$');
21479 return ggc_alloc_string (strip, len);
21484 rs6000_output_symbol_ref (FILE *file, rtx x)
21486 /* Currently C++ toc references to vtables can be emitted before it
21487 is decided whether the vtable is public or private. If this is
21488 the case, then the linker will eventually complain that there is
21489 a reference to an unknown section. Thus, for vtables only,
21490 we emit the TOC reference to reference the symbol and not the
21492 const char *name = XSTR (x, 0);
21494 if (VTABLE_NAME_P (name))
21496 RS6000_OUTPUT_BASENAME (file, name);
21499 assemble_name (file, name);
21502 /* Output a TOC entry. We derive the entry name from what is being
21506 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
21509 const char *name = buf;
21511 HOST_WIDE_INT offset = 0;
21513 gcc_assert (!TARGET_NO_TOC);
21515 /* When the linker won't eliminate them, don't output duplicate
21516 TOC entries (this happens on AIX if there is any kind of TOC,
21517 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
21519 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
21521 struct toc_hash_struct *h;
21524 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
21525 time because GGC is not initialized at that point. */
21526 if (toc_hash_table == NULL)
21527 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
21528 toc_hash_eq, NULL);
21530 h = ggc_alloc_toc_hash_struct ();
21532 h->key_mode = mode;
21533 h->labelno = labelno;
21535 found = htab_find_slot (toc_hash_table, h, INSERT);
21536 if (*found == NULL)
21538 else /* This is indeed a duplicate.
21539 Set this label equal to that label. */
21541 fputs ("\t.set ", file);
21542 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
21543 fprintf (file, "%d,", labelno);
21544 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
21545 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
21551 /* If we're going to put a double constant in the TOC, make sure it's
21552 aligned properly when strict alignment is on. */
21553 if (GET_CODE (x) == CONST_DOUBLE
21554 && STRICT_ALIGNMENT
21555 && GET_MODE_BITSIZE (mode) >= 64
21556 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
21557 ASM_OUTPUT_ALIGN (file, 3);
21560 (*targetm.asm_out.internal_label) (file, "LC", labelno);
21562 /* Handle FP constants specially. Note that if we have a minimal
21563 TOC, things we put here aren't actually in the TOC, so we can allow
21565 if (GET_CODE (x) == CONST_DOUBLE &&
21566 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
21568 REAL_VALUE_TYPE rv;
21571 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21572 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21573 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
21575 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
21579 if (TARGET_MINIMAL_TOC)
21580 fputs (DOUBLE_INT_ASM_OP, file);
21582 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
21583 k[0] & 0xffffffff, k[1] & 0xffffffff,
21584 k[2] & 0xffffffff, k[3] & 0xffffffff);
21585 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
21586 k[0] & 0xffffffff, k[1] & 0xffffffff,
21587 k[2] & 0xffffffff, k[3] & 0xffffffff);
21592 if (TARGET_MINIMAL_TOC)
21593 fputs ("\t.long ", file);
21595 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
21596 k[0] & 0xffffffff, k[1] & 0xffffffff,
21597 k[2] & 0xffffffff, k[3] & 0xffffffff);
21598 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
21599 k[0] & 0xffffffff, k[1] & 0xffffffff,
21600 k[2] & 0xffffffff, k[3] & 0xffffffff);
21604 else if (GET_CODE (x) == CONST_DOUBLE &&
21605 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
21607 REAL_VALUE_TYPE rv;
21610 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21612 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21613 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
21615 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
21619 if (TARGET_MINIMAL_TOC)
21620 fputs (DOUBLE_INT_ASM_OP, file);
21622 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
21623 k[0] & 0xffffffff, k[1] & 0xffffffff);
21624 fprintf (file, "0x%lx%08lx\n",
21625 k[0] & 0xffffffff, k[1] & 0xffffffff);
21630 if (TARGET_MINIMAL_TOC)
21631 fputs ("\t.long ", file);
21633 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
21634 k[0] & 0xffffffff, k[1] & 0xffffffff);
21635 fprintf (file, "0x%lx,0x%lx\n",
21636 k[0] & 0xffffffff, k[1] & 0xffffffff);
21640 else if (GET_CODE (x) == CONST_DOUBLE &&
21641 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
21643 REAL_VALUE_TYPE rv;
21646 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
21647 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
21648 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
21650 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
21654 if (TARGET_MINIMAL_TOC)
21655 fputs (DOUBLE_INT_ASM_OP, file);
21657 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
21658 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
21663 if (TARGET_MINIMAL_TOC)
21664 fputs ("\t.long ", file);
21666 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
21667 fprintf (file, "0x%lx\n", l & 0xffffffff);
21671 else if (GET_MODE (x) == VOIDmode
21672 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
21674 unsigned HOST_WIDE_INT low;
21675 HOST_WIDE_INT high;
21677 if (GET_CODE (x) == CONST_DOUBLE)
21679 low = CONST_DOUBLE_LOW (x);
21680 high = CONST_DOUBLE_HIGH (x);
21683 #if HOST_BITS_PER_WIDE_INT == 32
21686 high = (low & 0x80000000) ? ~0 : 0;
21690 low = INTVAL (x) & 0xffffffff;
21691 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
21695 /* TOC entries are always Pmode-sized, but since this
21696 is a bigendian machine then if we're putting smaller
21697 integer constants in the TOC we have to pad them.
21698 (This is still a win over putting the constants in
21699 a separate constant pool, because then we'd have
21700 to have both a TOC entry _and_ the actual constant.)
21702 For a 32-bit target, CONST_INT values are loaded and shifted
21703 entirely within `low' and can be stored in one TOC entry. */
21705 /* It would be easy to make this work, but it doesn't now. */
21706 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
21708 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
21710 #if HOST_BITS_PER_WIDE_INT == 32
21711 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
21712 POINTER_SIZE, &low, &high, 0);
21715 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
21716 high = (HOST_WIDE_INT) low >> 32;
21723 if (TARGET_MINIMAL_TOC)
21724 fputs (DOUBLE_INT_ASM_OP, file);
21726 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
21727 (long) high & 0xffffffff, (long) low & 0xffffffff);
21728 fprintf (file, "0x%lx%08lx\n",
21729 (long) high & 0xffffffff, (long) low & 0xffffffff);
21734 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
21736 if (TARGET_MINIMAL_TOC)
21737 fputs ("\t.long ", file);
21739 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
21740 (long) high & 0xffffffff, (long) low & 0xffffffff);
21741 fprintf (file, "0x%lx,0x%lx\n",
21742 (long) high & 0xffffffff, (long) low & 0xffffffff);
21746 if (TARGET_MINIMAL_TOC)
21747 fputs ("\t.long ", file);
21749 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
21750 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
21756 if (GET_CODE (x) == CONST)
21758 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
21759 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
21761 base = XEXP (XEXP (x, 0), 0);
21762 offset = INTVAL (XEXP (XEXP (x, 0), 1));
21765 switch (GET_CODE (base))
21768 name = XSTR (base, 0);
21772 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
21773 CODE_LABEL_NUMBER (XEXP (base, 0)));
21777 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
21781 gcc_unreachable ();
21784 if (TARGET_MINIMAL_TOC)
21785 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
21788 fputs ("\t.tc ", file);
21789 RS6000_OUTPUT_BASENAME (file, name);
21792 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
21794 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
21796 fputs ("[TC],", file);
21799 /* Currently C++ toc references to vtables can be emitted before it
21800 is decided whether the vtable is public or private. If this is
21801 the case, then the linker will eventually complain that there is
21802 a TOC reference to an unknown section. Thus, for vtables only,
21803 we emit the TOC reference to reference the symbol and not the
21805 if (VTABLE_NAME_P (name))
21807 RS6000_OUTPUT_BASENAME (file, name);
21809 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
21810 else if (offset > 0)
21811 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
21814 output_addr_const (file, x);
21818 /* Output an assembler pseudo-op to write an ASCII string of N characters
21819 starting at P to FILE.
21821 On the RS/6000, we have to do this using the .byte operation and
21822 write out special characters outside the quoted string.
21823 Also, the assembler is broken; very long strings are truncated,
21824 so we must artificially break them up early. */
21827 output_ascii (FILE *file, const char *p, int n)
21830 int i, count_string;
21831 const char *for_string = "\t.byte \"";
21832 const char *for_decimal = "\t.byte ";
21833 const char *to_close = NULL;
21836 for (i = 0; i < n; i++)
21839 if (c >= ' ' && c < 0177)
21842 fputs (for_string, file);
21845 /* Write two quotes to get one. */
21853 for_decimal = "\"\n\t.byte ";
21857 if (count_string >= 512)
21859 fputs (to_close, file);
21861 for_string = "\t.byte \"";
21862 for_decimal = "\t.byte ";
21870 fputs (for_decimal, file);
21871 fprintf (file, "%d", c);
21873 for_string = "\n\t.byte \"";
21874 for_decimal = ", ";
21880 /* Now close the string if we have written one. Then end the line. */
21882 fputs (to_close, file);
21885 /* Generate a unique section name for FILENAME for a section type
21886 represented by SECTION_DESC. Output goes into BUF.
21888 SECTION_DESC can be any string, as long as it is different for each
21889 possible section type.
21891 We name the section in the same manner as xlc. The name begins with an
21892 underscore followed by the filename (after stripping any leading directory
21893 names) with the last period replaced by the string SECTION_DESC. If
21894 FILENAME does not contain a period, SECTION_DESC is appended to the end of
21898 rs6000_gen_section_name (char **buf, const char *filename,
21899 const char *section_desc)
21901 const char *q, *after_last_slash, *last_period = 0;
21905 after_last_slash = filename;
21906 for (q = filename; *q; q++)
21909 after_last_slash = q + 1;
21910 else if (*q == '.')
21914 len = strlen (after_last_slash) + strlen (section_desc) + 2;
21915 *buf = (char *) xmalloc (len);
21920 for (q = after_last_slash; *q; q++)
21922 if (q == last_period)
21924 strcpy (p, section_desc);
21925 p += strlen (section_desc);
21929 else if (ISALNUM (*q))
21933 if (last_period == 0)
21934 strcpy (p, section_desc);
21939 /* Emit profile function. */
21942 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
21944 /* Non-standard profiling for kernels, which just saves LR then calls
21945 _mcount without worrying about arg saves. The idea is to change
21946 the function prologue as little as possible as it isn't easy to
21947 account for arg save/restore code added just for _mcount. */
21948 if (TARGET_PROFILE_KERNEL)
21951 if (DEFAULT_ABI == ABI_AIX)
21953 #ifndef NO_PROFILE_COUNTERS
21954 # define NO_PROFILE_COUNTERS 0
21956 if (NO_PROFILE_COUNTERS)
21957 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
21958 LCT_NORMAL, VOIDmode, 0);
21962 const char *label_name;
21965 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
21966 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
21967 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
21969 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
21970 LCT_NORMAL, VOIDmode, 1, fun, Pmode);
21973 else if (DEFAULT_ABI == ABI_DARWIN)
21975 const char *mcount_name = RS6000_MCOUNT;
21976 int caller_addr_regno = LR_REGNO;
21978 /* Be conservative and always set this, at least for now. */
21979 crtl->uses_pic_offset_table = 1;
21982 /* For PIC code, set up a stub and collect the caller's address
21983 from r0, which is where the prologue puts it. */
21984 if (MACHOPIC_INDIRECT
21985 && crtl->uses_pic_offset_table)
21986 caller_addr_regno = 0;
21988 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
21989 LCT_NORMAL, VOIDmode, 1,
21990 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
21994 /* Write function profiler code. */
21997 output_function_profiler (FILE *file, int labelno)
22001 switch (DEFAULT_ABI)
22004 gcc_unreachable ();
22009 warning (0, "no profiling of 64-bit code for this ABI");
22012 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
22013 fprintf (file, "\tmflr %s\n", reg_names[0]);
22014 if (NO_PROFILE_COUNTERS)
22016 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22017 reg_names[0], reg_names[1]);
22019 else if (TARGET_SECURE_PLT && flag_pic)
22021 if (TARGET_LINK_STACK)
22024 get_ppc476_thunk_name (name);
22025 asm_fprintf (file, "\tbl %s\n", name);
22028 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
22029 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22030 reg_names[0], reg_names[1]);
22031 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22032 asm_fprintf (file, "\t{cau|addis} %s,%s,",
22033 reg_names[12], reg_names[12]);
22034 assemble_name (file, buf);
22035 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
22036 assemble_name (file, buf);
22037 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
22039 else if (flag_pic == 1)
22041 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
22042 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22043 reg_names[0], reg_names[1]);
22044 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
22045 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
22046 assemble_name (file, buf);
22047 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
22049 else if (flag_pic > 1)
22051 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22052 reg_names[0], reg_names[1]);
22053 /* Now, we need to get the address of the label. */
22054 if (TARGET_LINK_STACK)
22057 get_ppc476_thunk_name (name);
22058 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
22059 assemble_name (file, buf);
22060 fputs ("-.\n1:", file);
22061 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22062 asm_fprintf (file, "\taddi %s,%s,4\n",
22063 reg_names[11], reg_names[11]);
22067 fputs ("\tbcl 20,31,1f\n\t.long ", file);
22068 assemble_name (file, buf);
22069 fputs ("-.\n1:", file);
22070 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
22072 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
22073 reg_names[0], reg_names[11]);
22074 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
22075 reg_names[0], reg_names[0], reg_names[11]);
22079 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
22080 assemble_name (file, buf);
22081 fputs ("@ha\n", file);
22082 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
22083 reg_names[0], reg_names[1]);
22084 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
22085 assemble_name (file, buf);
22086 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
22089 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
22090 fprintf (file, "\tbl %s%s\n",
22091 RS6000_MCOUNT, flag_pic ? "@plt" : "");
22096 if (!TARGET_PROFILE_KERNEL)
22098 /* Don't do anything, done in output_profile_hook (). */
22102 gcc_assert (!TARGET_32BIT);
22104 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
22105 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
22107 if (cfun->static_chain_decl != NULL)
22109 asm_fprintf (file, "\tstd %s,24(%s)\n",
22110 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22111 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22112 asm_fprintf (file, "\tld %s,24(%s)\n",
22113 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
22116 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
22124 /* The following variable value is the last issued insn. */
22126 static rtx last_scheduled_insn;
22128 /* The following variable helps to balance issuing of load and
22129 store instructions */
22131 static int load_store_pendulum;
22133 /* Power4 load update and store update instructions are cracked into a
22134 load or store and an integer insn which are executed in the same cycle.
22135 Branches have their own dispatch slot which does not count against the
22136 GCC issue rate, but it changes the program flow so there are no other
22137 instructions to issue in this cycle. */
22140 rs6000_variable_issue_1 (rtx insn, int more)
22142 last_scheduled_insn = insn;
22143 if (GET_CODE (PATTERN (insn)) == USE
22144 || GET_CODE (PATTERN (insn)) == CLOBBER)
22146 cached_can_issue_more = more;
22147 return cached_can_issue_more;
22150 if (insn_terminates_group_p (insn, current_group))
22152 cached_can_issue_more = 0;
22153 return cached_can_issue_more;
22156 /* If no reservation, but reach here */
22157 if (recog_memoized (insn) < 0)
22160 if (rs6000_sched_groups)
22162 if (is_microcoded_insn (insn))
22163 cached_can_issue_more = 0;
22164 else if (is_cracked_insn (insn))
22165 cached_can_issue_more = more > 2 ? more - 2 : 0;
22167 cached_can_issue_more = more - 1;
22169 return cached_can_issue_more;
22172 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
22175 cached_can_issue_more = more - 1;
22176 return cached_can_issue_more;
22180 rs6000_variable_issue (FILE *stream, int verbose, rtx insn, int more)
22182 int r = rs6000_variable_issue_1 (insn, more);
22184 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
22188 /* Adjust the cost of a scheduling dependency. Return the new cost of
22189 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
22192 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
22194 enum attr_type attr_type;
22196 if (! recog_memoized (insn))
22199 switch (REG_NOTE_KIND (link))
22203 /* Data dependency; DEP_INSN writes a register that INSN reads
22204 some cycles later. */
22206 /* Separate a load from a narrower, dependent store. */
22207 if (rs6000_sched_groups
22208 && GET_CODE (PATTERN (insn)) == SET
22209 && GET_CODE (PATTERN (dep_insn)) == SET
22210 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
22211 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
22212 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
22213 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
22216 attr_type = get_attr_type (insn);
22221 /* Tell the first scheduling pass about the latency between
22222 a mtctr and bctr (and mtlr and br/blr). The first
22223 scheduling pass will not know about this latency since
22224 the mtctr instruction, which has the latency associated
22225 to it, will be generated by reload. */
22226 return TARGET_POWER ? 5 : 4;
22228 /* Leave some extra cycles between a compare and its
22229 dependent branch, to inhibit expensive mispredicts. */
22230 if ((rs6000_cpu_attr == CPU_PPC603
22231 || rs6000_cpu_attr == CPU_PPC604
22232 || rs6000_cpu_attr == CPU_PPC604E
22233 || rs6000_cpu_attr == CPU_PPC620
22234 || rs6000_cpu_attr == CPU_PPC630
22235 || rs6000_cpu_attr == CPU_PPC750
22236 || rs6000_cpu_attr == CPU_PPC7400
22237 || rs6000_cpu_attr == CPU_PPC7450
22238 || rs6000_cpu_attr == CPU_POWER4
22239 || rs6000_cpu_attr == CPU_POWER5
22240 || rs6000_cpu_attr == CPU_POWER7
22241 || rs6000_cpu_attr == CPU_CELL)
22242 && recog_memoized (dep_insn)
22243 && (INSN_CODE (dep_insn) >= 0))
22245 switch (get_attr_type (dep_insn))
22249 case TYPE_DELAYED_COMPARE:
22250 case TYPE_IMUL_COMPARE:
22251 case TYPE_LMUL_COMPARE:
22252 case TYPE_FPCOMPARE:
22253 case TYPE_CR_LOGICAL:
22254 case TYPE_DELAYED_CR:
22263 case TYPE_STORE_UX:
22265 case TYPE_FPSTORE_U:
22266 case TYPE_FPSTORE_UX:
22267 if ((rs6000_cpu == PROCESSOR_POWER6)
22268 && recog_memoized (dep_insn)
22269 && (INSN_CODE (dep_insn) >= 0))
22272 if (GET_CODE (PATTERN (insn)) != SET)
22273 /* If this happens, we have to extend this to schedule
22274 optimally. Return default for now. */
22277 /* Adjust the cost for the case where the value written
22278 by a fixed point operation is used as the address
22279 gen value on a store. */
22280 switch (get_attr_type (dep_insn))
22287 if (! store_data_bypass_p (dep_insn, insn))
22291 case TYPE_LOAD_EXT:
22292 case TYPE_LOAD_EXT_U:
22293 case TYPE_LOAD_EXT_UX:
22294 case TYPE_VAR_SHIFT_ROTATE:
22295 case TYPE_VAR_DELAYED_COMPARE:
22297 if (! store_data_bypass_p (dep_insn, insn))
22303 case TYPE_FAST_COMPARE:
22306 case TYPE_INSERT_WORD:
22307 case TYPE_INSERT_DWORD:
22308 case TYPE_FPLOAD_U:
22309 case TYPE_FPLOAD_UX:
22311 case TYPE_STORE_UX:
22312 case TYPE_FPSTORE_U:
22313 case TYPE_FPSTORE_UX:
22315 if (! store_data_bypass_p (dep_insn, insn))
22323 case TYPE_IMUL_COMPARE:
22324 case TYPE_LMUL_COMPARE:
22326 if (! store_data_bypass_p (dep_insn, insn))
22332 if (! store_data_bypass_p (dep_insn, insn))
22338 if (! store_data_bypass_p (dep_insn, insn))
22351 case TYPE_LOAD_EXT:
22352 case TYPE_LOAD_EXT_U:
22353 case TYPE_LOAD_EXT_UX:
22354 if ((rs6000_cpu == PROCESSOR_POWER6)
22355 && recog_memoized (dep_insn)
22356 && (INSN_CODE (dep_insn) >= 0))
22359 /* Adjust the cost for the case where the value written
22360 by a fixed point instruction is used within the address
22361 gen portion of a subsequent load(u)(x) */
22362 switch (get_attr_type (dep_insn))
22369 if (set_to_load_agen (dep_insn, insn))
22373 case TYPE_LOAD_EXT:
22374 case TYPE_LOAD_EXT_U:
22375 case TYPE_LOAD_EXT_UX:
22376 case TYPE_VAR_SHIFT_ROTATE:
22377 case TYPE_VAR_DELAYED_COMPARE:
22379 if (set_to_load_agen (dep_insn, insn))
22385 case TYPE_FAST_COMPARE:
22388 case TYPE_INSERT_WORD:
22389 case TYPE_INSERT_DWORD:
22390 case TYPE_FPLOAD_U:
22391 case TYPE_FPLOAD_UX:
22393 case TYPE_STORE_UX:
22394 case TYPE_FPSTORE_U:
22395 case TYPE_FPSTORE_UX:
22397 if (set_to_load_agen (dep_insn, insn))
22405 case TYPE_IMUL_COMPARE:
22406 case TYPE_LMUL_COMPARE:
22408 if (set_to_load_agen (dep_insn, insn))
22414 if (set_to_load_agen (dep_insn, insn))
22420 if (set_to_load_agen (dep_insn, insn))
22431 if ((rs6000_cpu == PROCESSOR_POWER6)
22432 && recog_memoized (dep_insn)
22433 && (INSN_CODE (dep_insn) >= 0)
22434 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
22441 /* Fall out to return default cost. */
22445 case REG_DEP_OUTPUT:
22446 /* Output dependency; DEP_INSN writes a register that INSN writes some
22448 if ((rs6000_cpu == PROCESSOR_POWER6)
22449 && recog_memoized (dep_insn)
22450 && (INSN_CODE (dep_insn) >= 0))
22452 attr_type = get_attr_type (insn);
22457 if (get_attr_type (dep_insn) == TYPE_FP)
22461 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
22469 /* Anti dependency; DEP_INSN reads a register that INSN writes some
22474 gcc_unreachable ();
22480 /* Debug version of rs6000_adjust_cost. */
22483 rs6000_debug_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
22485 int ret = rs6000_adjust_cost (insn, link, dep_insn, cost);
22491 switch (REG_NOTE_KIND (link))
22493 default: dep = "unknown depencency"; break;
22494 case REG_DEP_TRUE: dep = "data dependency"; break;
22495 case REG_DEP_OUTPUT: dep = "output dependency"; break;
22496 case REG_DEP_ANTI: dep = "anti depencency"; break;
22500 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
22501 "%s, insn:\n", ret, cost, dep);
22509 /* The function returns a true if INSN is microcoded.
22510 Return false otherwise. */
22513 is_microcoded_insn (rtx insn)
22515 if (!insn || !NONDEBUG_INSN_P (insn)
22516 || GET_CODE (PATTERN (insn)) == USE
22517 || GET_CODE (PATTERN (insn)) == CLOBBER)
22520 if (rs6000_cpu_attr == CPU_CELL)
22521 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
22523 if (rs6000_sched_groups)
22525 enum attr_type type = get_attr_type (insn);
22526 if (type == TYPE_LOAD_EXT_U
22527 || type == TYPE_LOAD_EXT_UX
22528 || type == TYPE_LOAD_UX
22529 || type == TYPE_STORE_UX
22530 || type == TYPE_MFCR)
22537 /* The function returns true if INSN is cracked into 2 instructions
22538 by the processor (and therefore occupies 2 issue slots). */
22541 is_cracked_insn (rtx insn)
22543 if (!insn || !NONDEBUG_INSN_P (insn)
22544 || GET_CODE (PATTERN (insn)) == USE
22545 || GET_CODE (PATTERN (insn)) == CLOBBER)
22548 if (rs6000_sched_groups)
22550 enum attr_type type = get_attr_type (insn);
22551 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
22552 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
22553 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
22554 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
22555 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
22556 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
22557 || type == TYPE_IDIV || type == TYPE_LDIV
22558 || type == TYPE_INSERT_WORD)
22565 /* The function returns true if INSN can be issued only from
22566 the branch slot. */
22569 is_branch_slot_insn (rtx insn)
22571 if (!insn || !NONDEBUG_INSN_P (insn)
22572 || GET_CODE (PATTERN (insn)) == USE
22573 || GET_CODE (PATTERN (insn)) == CLOBBER)
22576 if (rs6000_sched_groups)
22578 enum attr_type type = get_attr_type (insn);
22579 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
22587 /* The function returns true if out_inst sets a value that is
22588 used in the address generation computation of in_insn */
22590 set_to_load_agen (rtx out_insn, rtx in_insn)
22592 rtx out_set, in_set;
22594 /* For performance reasons, only handle the simple case where
22595 both loads are a single_set. */
22596 out_set = single_set (out_insn);
22599 in_set = single_set (in_insn);
22601 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
22607 /* The function returns true if the target storage location of
22608 out_insn is adjacent to the target storage location of in_insn */
22609 /* Return 1 if memory locations are adjacent. */
22612 adjacent_mem_locations (rtx insn1, rtx insn2)
22615 rtx a = get_store_dest (PATTERN (insn1));
22616 rtx b = get_store_dest (PATTERN (insn2));
22618 if ((GET_CODE (XEXP (a, 0)) == REG
22619 || (GET_CODE (XEXP (a, 0)) == PLUS
22620 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
22621 && (GET_CODE (XEXP (b, 0)) == REG
22622 || (GET_CODE (XEXP (b, 0)) == PLUS
22623 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
22625 HOST_WIDE_INT val0 = 0, val1 = 0, val_diff;
22628 if (GET_CODE (XEXP (a, 0)) == PLUS)
22630 reg0 = XEXP (XEXP (a, 0), 0);
22631 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
22634 reg0 = XEXP (a, 0);
22636 if (GET_CODE (XEXP (b, 0)) == PLUS)
22638 reg1 = XEXP (XEXP (b, 0), 0);
22639 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
22642 reg1 = XEXP (b, 0);
22644 val_diff = val1 - val0;
22646 return ((REGNO (reg0) == REGNO (reg1))
22647 && ((MEM_SIZE_KNOWN_P (a) && val_diff == MEM_SIZE (a))
22648 || (MEM_SIZE_KNOWN_P (b) && val_diff == -MEM_SIZE (b))));
22654 /* A C statement (sans semicolon) to update the integer scheduling
22655 priority INSN_PRIORITY (INSN). Increase the priority to execute the
22656 INSN earlier, reduce the priority to execute INSN later. Do not
22657 define this macro if you do not need to adjust the scheduling
22658 priorities of insns. */
22661 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
22663 /* On machines (like the 750) which have asymmetric integer units,
22664 where one integer unit can do multiply and divides and the other
22665 can't, reduce the priority of multiply/divide so it is scheduled
22666 before other integer operations. */
22669 if (! INSN_P (insn))
22672 if (GET_CODE (PATTERN (insn)) == USE)
22675 switch (rs6000_cpu_attr) {
22677 switch (get_attr_type (insn))
22684 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
22685 priority, priority);
22686 if (priority >= 0 && priority < 0x01000000)
22693 if (insn_must_be_first_in_group (insn)
22694 && reload_completed
22695 && current_sched_info->sched_max_insns_priority
22696 && rs6000_sched_restricted_insns_priority)
22699 /* Prioritize insns that can be dispatched only in the first
22701 if (rs6000_sched_restricted_insns_priority == 1)
22702 /* Attach highest priority to insn. This means that in
22703 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
22704 precede 'priority' (critical path) considerations. */
22705 return current_sched_info->sched_max_insns_priority;
22706 else if (rs6000_sched_restricted_insns_priority == 2)
22707 /* Increase priority of insn by a minimal amount. This means that in
22708 haifa-sched.c:ready_sort(), only 'priority' (critical path)
22709 considerations precede dispatch-slot restriction considerations. */
22710 return (priority + 1);
22713 if (rs6000_cpu == PROCESSOR_POWER6
22714 && ((load_store_pendulum == -2 && is_load_insn (insn))
22715 || (load_store_pendulum == 2 && is_store_insn (insn))))
22716 /* Attach highest priority to insn if the scheduler has just issued two
22717 stores and this instruction is a load, or two loads and this instruction
22718 is a store. Power6 wants loads and stores scheduled alternately
22720 return current_sched_info->sched_max_insns_priority;
22725 /* Return true if the instruction is nonpipelined on the Cell. */
22727 is_nonpipeline_insn (rtx insn)
22729 enum attr_type type;
22730 if (!insn || !NONDEBUG_INSN_P (insn)
22731 || GET_CODE (PATTERN (insn)) == USE
22732 || GET_CODE (PATTERN (insn)) == CLOBBER)
22735 type = get_attr_type (insn);
22736 if (type == TYPE_IMUL
22737 || type == TYPE_IMUL2
22738 || type == TYPE_IMUL3
22739 || type == TYPE_LMUL
22740 || type == TYPE_IDIV
22741 || type == TYPE_LDIV
22742 || type == TYPE_SDIV
22743 || type == TYPE_DDIV
22744 || type == TYPE_SSQRT
22745 || type == TYPE_DSQRT
22746 || type == TYPE_MFCR
22747 || type == TYPE_MFCRF
22748 || type == TYPE_MFJMPR)
22756 /* Return how many instructions the machine can issue per cycle. */
22759 rs6000_issue_rate (void)
22761 /* Unless scheduling for register pressure, use issue rate of 1 for
22762 first scheduling pass to decrease degradation. */
22763 if (!reload_completed && !flag_sched_pressure)
22766 switch (rs6000_cpu_attr) {
22767 case CPU_RIOS1: /* ? */
22769 case CPU_PPC601: /* ? */
22778 case CPU_PPCE300C2:
22779 case CPU_PPCE300C3:
22780 case CPU_PPCE500MC:
22781 case CPU_PPCE500MC64:
22801 /* Return how many instructions to look ahead for better insn
22805 rs6000_use_sched_lookahead (void)
22807 if (rs6000_cpu_attr == CPU_PPC8540)
22809 if (rs6000_cpu_attr == CPU_CELL)
22810 return (reload_completed ? 8 : 0);
22814 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
22816 rs6000_use_sched_lookahead_guard (rtx insn)
22818 if (rs6000_cpu_attr != CPU_CELL)
22821 if (insn == NULL_RTX || !INSN_P (insn))
22824 if (!reload_completed
22825 || is_nonpipeline_insn (insn)
22826 || is_microcoded_insn (insn))
22832 /* Determine is PAT refers to memory. */
22835 is_mem_ref (rtx pat)
22841 /* stack_tie does not produce any real memory traffic. */
22842 if (GET_CODE (pat) == UNSPEC
22843 && XINT (pat, 1) == UNSPEC_TIE)
22846 if (GET_CODE (pat) == MEM)
22849 /* Recursively process the pattern. */
22850 fmt = GET_RTX_FORMAT (GET_CODE (pat));
22852 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
22855 ret |= is_mem_ref (XEXP (pat, i));
22856 else if (fmt[i] == 'E')
22857 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
22858 ret |= is_mem_ref (XVECEXP (pat, i, j));
22864 /* Determine if PAT is a PATTERN of a load insn. */
22867 is_load_insn1 (rtx pat)
22869 if (!pat || pat == NULL_RTX)
22872 if (GET_CODE (pat) == SET)
22873 return is_mem_ref (SET_SRC (pat));
22875 if (GET_CODE (pat) == PARALLEL)
22879 for (i = 0; i < XVECLEN (pat, 0); i++)
22880 if (is_load_insn1 (XVECEXP (pat, 0, i)))
22887 /* Determine if INSN loads from memory. */
22890 is_load_insn (rtx insn)
22892 if (!insn || !INSN_P (insn))
22895 if (GET_CODE (insn) == CALL_INSN)
22898 return is_load_insn1 (PATTERN (insn));
22901 /* Determine if PAT is a PATTERN of a store insn. */
22904 is_store_insn1 (rtx pat)
22906 if (!pat || pat == NULL_RTX)
22909 if (GET_CODE (pat) == SET)
22910 return is_mem_ref (SET_DEST (pat));
22912 if (GET_CODE (pat) == PARALLEL)
22916 for (i = 0; i < XVECLEN (pat, 0); i++)
22917 if (is_store_insn1 (XVECEXP (pat, 0, i)))
22924 /* Determine if INSN stores to memory. */
22927 is_store_insn (rtx insn)
22929 if (!insn || !INSN_P (insn))
22932 return is_store_insn1 (PATTERN (insn));
22935 /* Return the dest of a store insn. */
22938 get_store_dest (rtx pat)
22940 gcc_assert (is_store_insn1 (pat));
22942 if (GET_CODE (pat) == SET)
22943 return SET_DEST (pat);
22944 else if (GET_CODE (pat) == PARALLEL)
22948 for (i = 0; i < XVECLEN (pat, 0); i++)
22950 rtx inner_pat = XVECEXP (pat, 0, i);
22951 if (GET_CODE (inner_pat) == SET
22952 && is_mem_ref (SET_DEST (inner_pat)))
22956 /* We shouldn't get here, because we should have either a simple
22957 store insn or a store with update which are covered above. */
22961 /* Returns whether the dependence between INSN and NEXT is considered
22962 costly by the given target. */
22965 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
22970 /* If the flag is not enabled - no dependence is considered costly;
22971 allow all dependent insns in the same group.
22972 This is the most aggressive option. */
22973 if (rs6000_sched_costly_dep == no_dep_costly)
22976 /* If the flag is set to 1 - a dependence is always considered costly;
22977 do not allow dependent instructions in the same group.
22978 This is the most conservative option. */
22979 if (rs6000_sched_costly_dep == all_deps_costly)
22982 insn = DEP_PRO (dep);
22983 next = DEP_CON (dep);
22985 if (rs6000_sched_costly_dep == store_to_load_dep_costly
22986 && is_load_insn (next)
22987 && is_store_insn (insn))
22988 /* Prevent load after store in the same group. */
22991 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
22992 && is_load_insn (next)
22993 && is_store_insn (insn)
22994 && DEP_TYPE (dep) == REG_DEP_TRUE)
22995 /* Prevent load after store in the same group if it is a true
22999 /* The flag is set to X; dependences with latency >= X are considered costly,
23000 and will not be scheduled in the same group. */
23001 if (rs6000_sched_costly_dep <= max_dep_latency
23002 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
23008 /* Return the next insn after INSN that is found before TAIL is reached,
23009 skipping any "non-active" insns - insns that will not actually occupy
23010 an issue slot. Return NULL_RTX if such an insn is not found. */
23013 get_next_active_insn (rtx insn, rtx tail)
23015 if (insn == NULL_RTX || insn == tail)
23020 insn = NEXT_INSN (insn);
23021 if (insn == NULL_RTX || insn == tail)
23026 || (NONJUMP_INSN_P (insn)
23027 && GET_CODE (PATTERN (insn)) != USE
23028 && GET_CODE (PATTERN (insn)) != CLOBBER
23029 && INSN_CODE (insn) != CODE_FOR_stack_tie))
23035 /* We are about to begin issuing insns for this clock cycle. */
23038 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
23039 rtx *ready ATTRIBUTE_UNUSED,
23040 int *pn_ready ATTRIBUTE_UNUSED,
23041 int clock_var ATTRIBUTE_UNUSED)
23043 int n_ready = *pn_ready;
23046 fprintf (dump, "// rs6000_sched_reorder :\n");
23048 /* Reorder the ready list, if the second to last ready insn
23049 is a nonepipeline insn. */
23050 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
23052 if (is_nonpipeline_insn (ready[n_ready - 1])
23053 && (recog_memoized (ready[n_ready - 2]) > 0))
23054 /* Simply swap first two insns. */
23056 rtx tmp = ready[n_ready - 1];
23057 ready[n_ready - 1] = ready[n_ready - 2];
23058 ready[n_ready - 2] = tmp;
23062 if (rs6000_cpu == PROCESSOR_POWER6)
23063 load_store_pendulum = 0;
23065 return rs6000_issue_rate ();
23068 /* Like rs6000_sched_reorder, but called after issuing each insn. */
23071 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
23072 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
23075 fprintf (dump, "// rs6000_sched_reorder2 :\n");
23077 /* For Power6, we need to handle some special cases to try and keep the
23078 store queue from overflowing and triggering expensive flushes.
23080 This code monitors how load and store instructions are being issued
23081 and skews the ready list one way or the other to increase the likelihood
23082 that a desired instruction is issued at the proper time.
23084 A couple of things are done. First, we maintain a "load_store_pendulum"
23085 to track the current state of load/store issue.
23087 - If the pendulum is at zero, then no loads or stores have been
23088 issued in the current cycle so we do nothing.
23090 - If the pendulum is 1, then a single load has been issued in this
23091 cycle and we attempt to locate another load in the ready list to
23094 - If the pendulum is -2, then two stores have already been
23095 issued in this cycle, so we increase the priority of the first load
23096 in the ready list to increase it's likelihood of being chosen first
23099 - If the pendulum is -1, then a single store has been issued in this
23100 cycle and we attempt to locate another store in the ready list to
23101 issue with it, preferring a store to an adjacent memory location to
23102 facilitate store pairing in the store queue.
23104 - If the pendulum is 2, then two loads have already been
23105 issued in this cycle, so we increase the priority of the first store
23106 in the ready list to increase it's likelihood of being chosen first
23109 - If the pendulum < -2 or > 2, then do nothing.
23111 Note: This code covers the most common scenarios. There exist non
23112 load/store instructions which make use of the LSU and which
23113 would need to be accounted for to strictly model the behavior
23114 of the machine. Those instructions are currently unaccounted
23115 for to help minimize compile time overhead of this code.
23117 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
23123 if (is_store_insn (last_scheduled_insn))
23124 /* Issuing a store, swing the load_store_pendulum to the left */
23125 load_store_pendulum--;
23126 else if (is_load_insn (last_scheduled_insn))
23127 /* Issuing a load, swing the load_store_pendulum to the right */
23128 load_store_pendulum++;
23130 return cached_can_issue_more;
23132 /* If the pendulum is balanced, or there is only one instruction on
23133 the ready list, then all is well, so return. */
23134 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
23135 return cached_can_issue_more;
23137 if (load_store_pendulum == 1)
23139 /* A load has been issued in this cycle. Scan the ready list
23140 for another load to issue with it */
23145 if (is_load_insn (ready[pos]))
23147 /* Found a load. Move it to the head of the ready list,
23148 and adjust it's priority so that it is more likely to
23151 for (i=pos; i<*pn_ready-1; i++)
23152 ready[i] = ready[i + 1];
23153 ready[*pn_ready-1] = tmp;
23155 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23156 INSN_PRIORITY (tmp)++;
23162 else if (load_store_pendulum == -2)
23164 /* Two stores have been issued in this cycle. Increase the
23165 priority of the first load in the ready list to favor it for
23166 issuing in the next cycle. */
23171 if (is_load_insn (ready[pos])
23173 && INSN_PRIORITY_KNOWN (ready[pos]))
23175 INSN_PRIORITY (ready[pos])++;
23177 /* Adjust the pendulum to account for the fact that a load
23178 was found and increased in priority. This is to prevent
23179 increasing the priority of multiple loads */
23180 load_store_pendulum--;
23187 else if (load_store_pendulum == -1)
23189 /* A store has been issued in this cycle. Scan the ready list for
23190 another store to issue with it, preferring a store to an adjacent
23192 int first_store_pos = -1;
23198 if (is_store_insn (ready[pos]))
23200 /* Maintain the index of the first store found on the
23202 if (first_store_pos == -1)
23203 first_store_pos = pos;
23205 if (is_store_insn (last_scheduled_insn)
23206 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
23208 /* Found an adjacent store. Move it to the head of the
23209 ready list, and adjust it's priority so that it is
23210 more likely to stay there */
23212 for (i=pos; i<*pn_ready-1; i++)
23213 ready[i] = ready[i + 1];
23214 ready[*pn_ready-1] = tmp;
23216 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23217 INSN_PRIORITY (tmp)++;
23219 first_store_pos = -1;
23227 if (first_store_pos >= 0)
23229 /* An adjacent store wasn't found, but a non-adjacent store was,
23230 so move the non-adjacent store to the front of the ready
23231 list, and adjust its priority so that it is more likely to
23233 tmp = ready[first_store_pos];
23234 for (i=first_store_pos; i<*pn_ready-1; i++)
23235 ready[i] = ready[i + 1];
23236 ready[*pn_ready-1] = tmp;
23237 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
23238 INSN_PRIORITY (tmp)++;
23241 else if (load_store_pendulum == 2)
23243 /* Two loads have been issued in this cycle. Increase the priority
23244 of the first store in the ready list to favor it for issuing in
23250 if (is_store_insn (ready[pos])
23252 && INSN_PRIORITY_KNOWN (ready[pos]))
23254 INSN_PRIORITY (ready[pos])++;
23256 /* Adjust the pendulum to account for the fact that a store
23257 was found and increased in priority. This is to prevent
23258 increasing the priority of multiple stores */
23259 load_store_pendulum++;
23268 return cached_can_issue_more;
23271 /* Return whether the presence of INSN causes a dispatch group termination
23272 of group WHICH_GROUP.
23274 If WHICH_GROUP == current_group, this function will return true if INSN
23275 causes the termination of the current group (i.e, the dispatch group to
23276 which INSN belongs). This means that INSN will be the last insn in the
23277 group it belongs to.
23279 If WHICH_GROUP == previous_group, this function will return true if INSN
23280 causes the termination of the previous group (i.e, the dispatch group that
23281 precedes the group to which INSN belongs). This means that INSN will be
23282 the first insn in the group it belongs to). */
23285 insn_terminates_group_p (rtx insn, enum group_termination which_group)
23292 first = insn_must_be_first_in_group (insn);
23293 last = insn_must_be_last_in_group (insn);
23298 if (which_group == current_group)
23300 else if (which_group == previous_group)
23308 insn_must_be_first_in_group (rtx insn)
23310 enum attr_type type;
23313 || GET_CODE (insn) == NOTE
23314 || DEBUG_INSN_P (insn)
23315 || GET_CODE (PATTERN (insn)) == USE
23316 || GET_CODE (PATTERN (insn)) == CLOBBER)
23319 switch (rs6000_cpu)
23321 case PROCESSOR_POWER5:
23322 if (is_cracked_insn (insn))
23324 case PROCESSOR_POWER4:
23325 if (is_microcoded_insn (insn))
23328 if (!rs6000_sched_groups)
23331 type = get_attr_type (insn);
23338 case TYPE_DELAYED_CR:
23339 case TYPE_CR_LOGICAL:
23353 case PROCESSOR_POWER6:
23354 type = get_attr_type (insn);
23358 case TYPE_INSERT_DWORD:
23362 case TYPE_VAR_SHIFT_ROTATE:
23369 case TYPE_INSERT_WORD:
23370 case TYPE_DELAYED_COMPARE:
23371 case TYPE_IMUL_COMPARE:
23372 case TYPE_LMUL_COMPARE:
23373 case TYPE_FPCOMPARE:
23384 case TYPE_LOAD_EXT_UX:
23386 case TYPE_STORE_UX:
23387 case TYPE_FPLOAD_U:
23388 case TYPE_FPLOAD_UX:
23389 case TYPE_FPSTORE_U:
23390 case TYPE_FPSTORE_UX:
23396 case PROCESSOR_POWER7:
23397 type = get_attr_type (insn);
23401 case TYPE_CR_LOGICAL:
23408 case TYPE_DELAYED_COMPARE:
23409 case TYPE_VAR_DELAYED_COMPARE:
23415 case TYPE_LOAD_EXT:
23416 case TYPE_LOAD_EXT_U:
23417 case TYPE_LOAD_EXT_UX:
23419 case TYPE_STORE_UX:
23420 case TYPE_FPLOAD_U:
23421 case TYPE_FPLOAD_UX:
23422 case TYPE_FPSTORE_U:
23423 case TYPE_FPSTORE_UX:
23439 insn_must_be_last_in_group (rtx insn)
23441 enum attr_type type;
23444 || GET_CODE (insn) == NOTE
23445 || DEBUG_INSN_P (insn)
23446 || GET_CODE (PATTERN (insn)) == USE
23447 || GET_CODE (PATTERN (insn)) == CLOBBER)
23450 switch (rs6000_cpu) {
23451 case PROCESSOR_POWER4:
23452 case PROCESSOR_POWER5:
23453 if (is_microcoded_insn (insn))
23456 if (is_branch_slot_insn (insn))
23460 case PROCESSOR_POWER6:
23461 type = get_attr_type (insn);
23468 case TYPE_VAR_SHIFT_ROTATE:
23475 case TYPE_DELAYED_COMPARE:
23476 case TYPE_IMUL_COMPARE:
23477 case TYPE_LMUL_COMPARE:
23478 case TYPE_FPCOMPARE:
23492 case PROCESSOR_POWER7:
23493 type = get_attr_type (insn);
23501 case TYPE_LOAD_EXT_U:
23502 case TYPE_LOAD_EXT_UX:
23503 case TYPE_STORE_UX:
23516 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
23517 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
23520 is_costly_group (rtx *group_insns, rtx next_insn)
23523 int issue_rate = rs6000_issue_rate ();
23525 for (i = 0; i < issue_rate; i++)
23527 sd_iterator_def sd_it;
23529 rtx insn = group_insns[i];
23534 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
23536 rtx next = DEP_CON (dep);
23538 if (next == next_insn
23539 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
23547 /* Utility of the function redefine_groups.
23548 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
23549 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
23550 to keep it "far" (in a separate group) from GROUP_INSNS, following
23551 one of the following schemes, depending on the value of the flag
23552 -minsert_sched_nops = X:
23553 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
23554 in order to force NEXT_INSN into a separate group.
23555 (2) X < sched_finish_regroup_exact: insert exactly X nops.
23556 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
23557 insertion (has a group just ended, how many vacant issue slots remain in the
23558 last group, and how many dispatch groups were encountered so far). */
23561 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
23562 rtx next_insn, bool *group_end, int can_issue_more,
23567 int issue_rate = rs6000_issue_rate ();
23568 bool end = *group_end;
23571 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
23572 return can_issue_more;
23574 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
23575 return can_issue_more;
23577 force = is_costly_group (group_insns, next_insn);
23579 return can_issue_more;
23581 if (sched_verbose > 6)
23582 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
23583 *group_count ,can_issue_more);
23585 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
23588 can_issue_more = 0;
23590 /* Since only a branch can be issued in the last issue_slot, it is
23591 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
23592 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
23593 in this case the last nop will start a new group and the branch
23594 will be forced to the new group. */
23595 if (can_issue_more && !is_branch_slot_insn (next_insn))
23598 while (can_issue_more > 0)
23601 emit_insn_before (nop, next_insn);
23609 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
23611 int n_nops = rs6000_sched_insert_nops;
23613 /* Nops can't be issued from the branch slot, so the effective
23614 issue_rate for nops is 'issue_rate - 1'. */
23615 if (can_issue_more == 0)
23616 can_issue_more = issue_rate;
23618 if (can_issue_more == 0)
23620 can_issue_more = issue_rate - 1;
23623 for (i = 0; i < issue_rate; i++)
23625 group_insns[i] = 0;
23632 emit_insn_before (nop, next_insn);
23633 if (can_issue_more == issue_rate - 1) /* new group begins */
23636 if (can_issue_more == 0)
23638 can_issue_more = issue_rate - 1;
23641 for (i = 0; i < issue_rate; i++)
23643 group_insns[i] = 0;
23649 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
23652 /* Is next_insn going to start a new group? */
23655 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
23656 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
23657 || (can_issue_more < issue_rate &&
23658 insn_terminates_group_p (next_insn, previous_group)));
23659 if (*group_end && end)
23662 if (sched_verbose > 6)
23663 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
23664 *group_count, can_issue_more);
23665 return can_issue_more;
23668 return can_issue_more;
23671 /* This function tries to synch the dispatch groups that the compiler "sees"
23672 with the dispatch groups that the processor dispatcher is expected to
23673 form in practice. It tries to achieve this synchronization by forcing the
23674 estimated processor grouping on the compiler (as opposed to the function
23675 'pad_goups' which tries to force the scheduler's grouping on the processor).
23677 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
23678 examines the (estimated) dispatch groups that will be formed by the processor
23679 dispatcher. It marks these group boundaries to reflect the estimated
23680 processor grouping, overriding the grouping that the scheduler had marked.
23681 Depending on the value of the flag '-minsert-sched-nops' this function can
23682 force certain insns into separate groups or force a certain distance between
23683 them by inserting nops, for example, if there exists a "costly dependence"
23686 The function estimates the group boundaries that the processor will form as
23687 follows: It keeps track of how many vacant issue slots are available after
23688 each insn. A subsequent insn will start a new group if one of the following
23690 - no more vacant issue slots remain in the current dispatch group.
23691 - only the last issue slot, which is the branch slot, is vacant, but the next
23692 insn is not a branch.
23693 - only the last 2 or less issue slots, including the branch slot, are vacant,
23694 which means that a cracked insn (which occupies two issue slots) can't be
23695 issued in this group.
23696 - less than 'issue_rate' slots are vacant, and the next insn always needs to
23697 start a new group. */
23700 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
23702 rtx insn, next_insn;
23704 int can_issue_more;
23707 int group_count = 0;
23711 issue_rate = rs6000_issue_rate ();
23712 group_insns = XALLOCAVEC (rtx, issue_rate);
23713 for (i = 0; i < issue_rate; i++)
23715 group_insns[i] = 0;
23717 can_issue_more = issue_rate;
23719 insn = get_next_active_insn (prev_head_insn, tail);
23722 while (insn != NULL_RTX)
23724 slot = (issue_rate - can_issue_more);
23725 group_insns[slot] = insn;
23727 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
23728 if (insn_terminates_group_p (insn, current_group))
23729 can_issue_more = 0;
23731 next_insn = get_next_active_insn (insn, tail);
23732 if (next_insn == NULL_RTX)
23733 return group_count + 1;
23735 /* Is next_insn going to start a new group? */
23737 = (can_issue_more == 0
23738 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
23739 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
23740 || (can_issue_more < issue_rate &&
23741 insn_terminates_group_p (next_insn, previous_group)));
23743 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
23744 next_insn, &group_end, can_issue_more,
23750 can_issue_more = 0;
23751 for (i = 0; i < issue_rate; i++)
23753 group_insns[i] = 0;
23757 if (GET_MODE (next_insn) == TImode && can_issue_more)
23758 PUT_MODE (next_insn, VOIDmode);
23759 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
23760 PUT_MODE (next_insn, TImode);
23763 if (can_issue_more == 0)
23764 can_issue_more = issue_rate;
23767 return group_count;
23770 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
23771 dispatch group boundaries that the scheduler had marked. Pad with nops
23772 any dispatch groups which have vacant issue slots, in order to force the
23773 scheduler's grouping on the processor dispatcher. The function
23774 returns the number of dispatch groups found. */
23777 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
23779 rtx insn, next_insn;
23782 int can_issue_more;
23784 int group_count = 0;
23786 /* Initialize issue_rate. */
23787 issue_rate = rs6000_issue_rate ();
23788 can_issue_more = issue_rate;
23790 insn = get_next_active_insn (prev_head_insn, tail);
23791 next_insn = get_next_active_insn (insn, tail);
23793 while (insn != NULL_RTX)
23796 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
23798 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
23800 if (next_insn == NULL_RTX)
23805 /* If the scheduler had marked group termination at this location
23806 (between insn and next_insn), and neither insn nor next_insn will
23807 force group termination, pad the group with nops to force group
23810 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
23811 && !insn_terminates_group_p (insn, current_group)
23812 && !insn_terminates_group_p (next_insn, previous_group))
23814 if (!is_branch_slot_insn (next_insn))
23817 while (can_issue_more)
23820 emit_insn_before (nop, next_insn);
23825 can_issue_more = issue_rate;
23830 next_insn = get_next_active_insn (insn, tail);
23833 return group_count;
23836 /* We're beginning a new block. Initialize data structures as necessary. */
23839 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
23840 int sched_verbose ATTRIBUTE_UNUSED,
23841 int max_ready ATTRIBUTE_UNUSED)
23843 last_scheduled_insn = NULL_RTX;
23844 load_store_pendulum = 0;
23847 /* The following function is called at the end of scheduling BB.
23848 After reload, it inserts nops at insn group bundling. */
23851 rs6000_sched_finish (FILE *dump, int sched_verbose)
23856 fprintf (dump, "=== Finishing schedule.\n");
23858 if (reload_completed && rs6000_sched_groups)
23860 /* Do not run sched_finish hook when selective scheduling enabled. */
23861 if (sel_sched_p ())
23864 if (rs6000_sched_insert_nops == sched_finish_none)
23867 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
23868 n_groups = pad_groups (dump, sched_verbose,
23869 current_sched_info->prev_head,
23870 current_sched_info->next_tail);
23872 n_groups = redefine_groups (dump, sched_verbose,
23873 current_sched_info->prev_head,
23874 current_sched_info->next_tail);
23876 if (sched_verbose >= 6)
23878 fprintf (dump, "ngroups = %d\n", n_groups);
23879 print_rtl (dump, current_sched_info->prev_head);
23880 fprintf (dump, "Done finish_sched\n");
23885 struct _rs6000_sched_context
23887 short cached_can_issue_more;
23888 rtx last_scheduled_insn;
23889 int load_store_pendulum;
23892 typedef struct _rs6000_sched_context rs6000_sched_context_def;
23893 typedef rs6000_sched_context_def *rs6000_sched_context_t;
23895 /* Allocate store for new scheduling context. */
23897 rs6000_alloc_sched_context (void)
23899 return xmalloc (sizeof (rs6000_sched_context_def));
23902 /* If CLEAN_P is true then initializes _SC with clean data,
23903 and from the global context otherwise. */
23905 rs6000_init_sched_context (void *_sc, bool clean_p)
23907 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
23911 sc->cached_can_issue_more = 0;
23912 sc->last_scheduled_insn = NULL_RTX;
23913 sc->load_store_pendulum = 0;
23917 sc->cached_can_issue_more = cached_can_issue_more;
23918 sc->last_scheduled_insn = last_scheduled_insn;
23919 sc->load_store_pendulum = load_store_pendulum;
23923 /* Sets the global scheduling context to the one pointed to by _SC. */
23925 rs6000_set_sched_context (void *_sc)
23927 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
23929 gcc_assert (sc != NULL);
23931 cached_can_issue_more = sc->cached_can_issue_more;
23932 last_scheduled_insn = sc->last_scheduled_insn;
23933 load_store_pendulum = sc->load_store_pendulum;
23938 rs6000_free_sched_context (void *_sc)
23940 gcc_assert (_sc != NULL);
23946 /* Length in units of the trampoline for entering a nested function. */
23949 rs6000_trampoline_size (void)
23953 switch (DEFAULT_ABI)
23956 gcc_unreachable ();
23959 ret = (TARGET_32BIT) ? 12 : 24;
23964 ret = (TARGET_32BIT) ? 40 : 48;
23971 /* Emit RTL insns to initialize the variable parts of a trampoline.
23972 FNADDR is an RTX for the address of the function's pure code.
23973 CXT is an RTX for the static chain value for the function. */
23976 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
23978 int regsize = (TARGET_32BIT) ? 4 : 8;
23979 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
23980 rtx ctx_reg = force_reg (Pmode, cxt);
23981 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
23983 switch (DEFAULT_ABI)
23986 gcc_unreachable ();
23988 /* Under AIX, just build the 3 word function descriptor */
23991 rtx fnmem, fn_reg, toc_reg;
23993 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
23994 error ("-mno-r11 must not be used if you have trampolines");
23996 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
23997 fn_reg = gen_reg_rtx (Pmode);
23998 toc_reg = gen_reg_rtx (Pmode);
24000 /* Macro to shorten the code expansions below. */
24001 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
24003 m_tramp = replace_equiv_address (m_tramp, addr);
24005 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
24006 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
24007 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
24008 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
24009 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
24015 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
24018 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
24019 LCT_NORMAL, VOIDmode, 4,
24021 GEN_INT (rs6000_trampoline_size ()), SImode,
24029 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
24030 identifier as an argument, so the front end shouldn't look it up. */
24033 rs6000_attribute_takes_identifier_p (const_tree attr_id)
24035 return is_attribute_p ("altivec", attr_id);
24038 /* Handle the "altivec" attribute. The attribute may have
24039 arguments as follows:
24041 __attribute__((altivec(vector__)))
24042 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
24043 __attribute__((altivec(bool__))) (always followed by 'unsigned')
24045 and may appear more than once (e.g., 'vector bool char') in a
24046 given declaration. */
24049 rs6000_handle_altivec_attribute (tree *node,
24050 tree name ATTRIBUTE_UNUSED,
24052 int flags ATTRIBUTE_UNUSED,
24053 bool *no_add_attrs)
24055 tree type = *node, result = NULL_TREE;
24056 enum machine_mode mode;
24059 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
24060 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
24061 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
24064 while (POINTER_TYPE_P (type)
24065 || TREE_CODE (type) == FUNCTION_TYPE
24066 || TREE_CODE (type) == METHOD_TYPE
24067 || TREE_CODE (type) == ARRAY_TYPE)
24068 type = TREE_TYPE (type);
24070 mode = TYPE_MODE (type);
24072 /* Check for invalid AltiVec type qualifiers. */
24073 if (type == long_double_type_node)
24074 error ("use of %<long double%> in AltiVec types is invalid");
24075 else if (type == boolean_type_node)
24076 error ("use of boolean types in AltiVec types is invalid");
24077 else if (TREE_CODE (type) == COMPLEX_TYPE)
24078 error ("use of %<complex%> in AltiVec types is invalid");
24079 else if (DECIMAL_FLOAT_MODE_P (mode))
24080 error ("use of decimal floating point types in AltiVec types is invalid");
24081 else if (!TARGET_VSX)
24083 if (type == long_unsigned_type_node || type == long_integer_type_node)
24086 error ("use of %<long%> in AltiVec types is invalid for "
24087 "64-bit code without -mvsx");
24088 else if (rs6000_warn_altivec_long)
24089 warning (0, "use of %<long%> in AltiVec types is deprecated; "
24092 else if (type == long_long_unsigned_type_node
24093 || type == long_long_integer_type_node)
24094 error ("use of %<long long%> in AltiVec types is invalid without "
24096 else if (type == double_type_node)
24097 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
24100 switch (altivec_type)
24103 unsigned_p = TYPE_UNSIGNED (type);
24107 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
24110 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
24113 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
24116 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
24118 case SFmode: result = V4SF_type_node; break;
24119 case DFmode: result = V2DF_type_node; break;
24120 /* If the user says 'vector int bool', we may be handed the 'bool'
24121 attribute _before_ the 'vector' attribute, and so select the
24122 proper type in the 'b' case below. */
24123 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
24124 case V2DImode: case V2DFmode:
24132 case DImode: case V2DImode: result = bool_V2DI_type_node; break;
24133 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
24134 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
24135 case QImode: case V16QImode: result = bool_V16QI_type_node;
24142 case V8HImode: result = pixel_V8HI_type_node;
24148 /* Propagate qualifiers attached to the element type
24149 onto the vector type. */
24150 if (result && result != type && TYPE_QUALS (type))
24151 result = build_qualified_type (result, TYPE_QUALS (type));
24153 *no_add_attrs = true; /* No need to hang on to the attribute. */
24156 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
24161 /* AltiVec defines four built-in scalar types that serve as vector
24162 elements; we must teach the compiler how to mangle them. */
24164 static const char *
24165 rs6000_mangle_type (const_tree type)
24167 type = TYPE_MAIN_VARIANT (type);
24169 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
24170 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
24173 if (type == bool_char_type_node) return "U6__boolc";
24174 if (type == bool_short_type_node) return "U6__bools";
24175 if (type == pixel_type_node) return "u7__pixel";
24176 if (type == bool_int_type_node) return "U6__booli";
24177 if (type == bool_long_type_node) return "U6__booll";
24179 /* Mangle IBM extended float long double as `g' (__float128) on
24180 powerpc*-linux where long-double-64 previously was the default. */
24181 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
24183 && TARGET_LONG_DOUBLE_128
24184 && !TARGET_IEEEQUAD)
24187 /* For all other types, use normal C++ mangling. */
24191 /* Handle a "longcall" or "shortcall" attribute; arguments as in
24192 struct attribute_spec.handler. */
24195 rs6000_handle_longcall_attribute (tree *node, tree name,
24196 tree args ATTRIBUTE_UNUSED,
24197 int flags ATTRIBUTE_UNUSED,
24198 bool *no_add_attrs)
24200 if (TREE_CODE (*node) != FUNCTION_TYPE
24201 && TREE_CODE (*node) != FIELD_DECL
24202 && TREE_CODE (*node) != TYPE_DECL)
24204 warning (OPT_Wattributes, "%qE attribute only applies to functions",
24206 *no_add_attrs = true;
24212 /* Set longcall attributes on all functions declared when
24213 rs6000_default_long_calls is true. */
24215 rs6000_set_default_type_attributes (tree type)
24217 if (rs6000_default_long_calls
24218 && (TREE_CODE (type) == FUNCTION_TYPE
24219 || TREE_CODE (type) == METHOD_TYPE))
24220 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
24222 TYPE_ATTRIBUTES (type));
24225 darwin_set_default_type_attributes (type);
24229 /* Return a reference suitable for calling a function with the
24230 longcall attribute. */
24233 rs6000_longcall_ref (rtx call_ref)
24235 const char *call_name;
24238 if (GET_CODE (call_ref) != SYMBOL_REF)
24241 /* System V adds '.' to the internal name, so skip them. */
24242 call_name = XSTR (call_ref, 0);
24243 if (*call_name == '.')
24245 while (*call_name == '.')
24248 node = get_identifier (call_name);
24249 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
24252 return force_reg (Pmode, call_ref);
24255 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
24256 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
24259 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
24260 struct attribute_spec.handler. */
24262 rs6000_handle_struct_attribute (tree *node, tree name,
24263 tree args ATTRIBUTE_UNUSED,
24264 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
24267 if (DECL_P (*node))
24269 if (TREE_CODE (*node) == TYPE_DECL)
24270 type = &TREE_TYPE (*node);
24275 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
24276 || TREE_CODE (*type) == UNION_TYPE)))
24278 warning (OPT_Wattributes, "%qE attribute ignored", name);
24279 *no_add_attrs = true;
24282 else if ((is_attribute_p ("ms_struct", name)
24283 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
24284 || ((is_attribute_p ("gcc_struct", name)
24285 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
24287 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
24289 *no_add_attrs = true;
24296 rs6000_ms_bitfield_layout_p (const_tree record_type)
24298 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
24299 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
24300 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
24303 #ifdef USING_ELFOS_H
24305 /* A get_unnamed_section callback, used for switching to toc_section. */
24308 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
24310 if (DEFAULT_ABI == ABI_AIX
24311 && TARGET_MINIMAL_TOC
24312 && !TARGET_RELOCATABLE)
24314 if (!toc_initialized)
24316 toc_initialized = 1;
24317 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24318 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
24319 fprintf (asm_out_file, "\t.tc ");
24320 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
24321 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24322 fprintf (asm_out_file, "\n");
24324 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24325 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24326 fprintf (asm_out_file, " = .+32768\n");
24329 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24331 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
24332 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
24335 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
24336 if (!toc_initialized)
24338 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
24339 fprintf (asm_out_file, " = .+32768\n");
24340 toc_initialized = 1;
24345 /* Implement TARGET_ASM_INIT_SECTIONS. */
24348 rs6000_elf_asm_init_sections (void)
24351 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
24354 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
24355 SDATA2_SECTION_ASM_OP);
24358 /* Implement TARGET_SELECT_RTX_SECTION. */
24361 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
24362 unsigned HOST_WIDE_INT align)
24364 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
24365 return toc_section;
24367 return default_elf_select_rtx_section (mode, x, align);
24370 /* For a SYMBOL_REF, set generic flags and then perform some
24371 target-specific processing.
24373 When the AIX ABI is requested on a non-AIX system, replace the
24374 function name with the real name (with a leading .) rather than the
24375 function descriptor name. This saves a lot of overriding code to
24376 read the prefixes. */
24379 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
24381 default_encode_section_info (decl, rtl, first);
24384 && TREE_CODE (decl) == FUNCTION_DECL
24386 && DEFAULT_ABI == ABI_AIX)
24388 rtx sym_ref = XEXP (rtl, 0);
24389 size_t len = strlen (XSTR (sym_ref, 0));
24390 char *str = XALLOCAVEC (char, len + 2);
24392 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
24393 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
24398 compare_section_name (const char *section, const char *templ)
24402 len = strlen (templ);
24403 return (strncmp (section, templ, len) == 0
24404 && (section[len] == 0 || section[len] == '.'));
24408 rs6000_elf_in_small_data_p (const_tree decl)
24410 if (rs6000_sdata == SDATA_NONE)
24413 /* We want to merge strings, so we never consider them small data. */
24414 if (TREE_CODE (decl) == STRING_CST)
24417 /* Functions are never in the small data area. */
24418 if (TREE_CODE (decl) == FUNCTION_DECL)
24421 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
24423 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
24424 if (compare_section_name (section, ".sdata")
24425 || compare_section_name (section, ".sdata2")
24426 || compare_section_name (section, ".gnu.linkonce.s")
24427 || compare_section_name (section, ".sbss")
24428 || compare_section_name (section, ".sbss2")
24429 || compare_section_name (section, ".gnu.linkonce.sb")
24430 || strcmp (section, ".PPC.EMB.sdata0") == 0
24431 || strcmp (section, ".PPC.EMB.sbss0") == 0)
24436 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
24439 && size <= g_switch_value
24440 /* If it's not public, and we're not going to reference it there,
24441 there's no need to put it in the small data section. */
24442 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
24449 #endif /* USING_ELFOS_H */
24451 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
24454 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
24456 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
24459 /* Return a REG that occurs in ADDR with coefficient 1.
24460 ADDR can be effectively incremented by incrementing REG.
24462 r0 is special and we must not select it as an address
24463 register by this routine since our caller will try to
24464 increment the returned register via an "la" instruction. */
24467 find_addr_reg (rtx addr)
24469 while (GET_CODE (addr) == PLUS)
24471 if (GET_CODE (XEXP (addr, 0)) == REG
24472 && REGNO (XEXP (addr, 0)) != 0)
24473 addr = XEXP (addr, 0);
24474 else if (GET_CODE (XEXP (addr, 1)) == REG
24475 && REGNO (XEXP (addr, 1)) != 0)
24476 addr = XEXP (addr, 1);
24477 else if (CONSTANT_P (XEXP (addr, 0)))
24478 addr = XEXP (addr, 1);
24479 else if (CONSTANT_P (XEXP (addr, 1)))
24480 addr = XEXP (addr, 0);
24482 gcc_unreachable ();
24484 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
24489 rs6000_fatal_bad_address (rtx op)
24491 fatal_insn ("bad address", op);
24496 typedef struct branch_island_d {
24497 tree function_name;
24502 DEF_VEC_O(branch_island);
24503 DEF_VEC_ALLOC_O(branch_island,gc);
24505 static VEC(branch_island,gc) *branch_islands;
24507 /* Remember to generate a branch island for far calls to the given
24511 add_compiler_branch_island (tree label_name, tree function_name,
24514 branch_island *bi = VEC_safe_push (branch_island, gc, branch_islands, NULL);
24516 bi->function_name = function_name;
24517 bi->label_name = label_name;
24518 bi->line_number = line_number;
24521 /* Generate far-jump branch islands for everything recorded in
24522 branch_islands. Invoked immediately after the last instruction of
24523 the epilogue has been emitted; the branch islands must be appended
24524 to, and contiguous with, the function body. Mach-O stubs are
24525 generated in machopic_output_stub(). */
24528 macho_branch_islands (void)
24532 while (!VEC_empty (branch_island, branch_islands))
24534 branch_island *bi = VEC_last (branch_island, branch_islands);
24535 const char *label = IDENTIFIER_POINTER (bi->label_name);
24536 const char *name = IDENTIFIER_POINTER (bi->function_name);
24537 char name_buf[512];
24538 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
24539 if (name[0] == '*' || name[0] == '&')
24540 strcpy (name_buf, name+1);
24544 strcpy (name_buf+1, name);
24546 strcpy (tmp_buf, "\n");
24547 strcat (tmp_buf, label);
24548 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
24549 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
24550 dbxout_stabd (N_SLINE, bi->line_number);
24551 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
24554 if (TARGET_LINK_STACK)
24557 get_ppc476_thunk_name (name);
24558 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
24559 strcat (tmp_buf, name);
24560 strcat (tmp_buf, "\n");
24561 strcat (tmp_buf, label);
24562 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
24566 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
24567 strcat (tmp_buf, label);
24568 strcat (tmp_buf, "_pic\n");
24569 strcat (tmp_buf, label);
24570 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
24573 strcat (tmp_buf, "\taddis r11,r11,ha16(");
24574 strcat (tmp_buf, name_buf);
24575 strcat (tmp_buf, " - ");
24576 strcat (tmp_buf, label);
24577 strcat (tmp_buf, "_pic)\n");
24579 strcat (tmp_buf, "\tmtlr r0\n");
24581 strcat (tmp_buf, "\taddi r12,r11,lo16(");
24582 strcat (tmp_buf, name_buf);
24583 strcat (tmp_buf, " - ");
24584 strcat (tmp_buf, label);
24585 strcat (tmp_buf, "_pic)\n");
24587 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
24591 strcat (tmp_buf, ":\nlis r12,hi16(");
24592 strcat (tmp_buf, name_buf);
24593 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
24594 strcat (tmp_buf, name_buf);
24595 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
24597 output_asm_insn (tmp_buf, 0);
24598 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
24599 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
24600 dbxout_stabd (N_SLINE, bi->line_number);
24601 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
24602 VEC_pop (branch_island, branch_islands);
24606 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
24607 already there or not. */
24610 no_previous_def (tree function_name)
24615 FOR_EACH_VEC_ELT (branch_island, branch_islands, ix, bi)
24616 if (function_name == bi->function_name)
24621 /* GET_PREV_LABEL gets the label name from the previous definition of
24625 get_prev_label (tree function_name)
24630 FOR_EACH_VEC_ELT (branch_island, branch_islands, ix, bi)
24631 if (function_name == bi->function_name)
24632 return bi->label_name;
24636 /* INSN is either a function call or a millicode call. It may have an
24637 unconditional jump in its delay slot.
24639 CALL_DEST is the routine we are calling. */
24642 output_call (rtx insn, rtx *operands, int dest_operand_number,
24643 int cookie_operand_number)
24645 static char buf[256];
24646 if (darwin_emit_branch_islands
24647 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
24648 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
24651 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
24653 if (no_previous_def (funname))
24655 rtx label_rtx = gen_label_rtx ();
24656 char *label_buf, temp_buf[256];
24657 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
24658 CODE_LABEL_NUMBER (label_rtx));
24659 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
24660 labelname = get_identifier (label_buf);
24661 add_compiler_branch_island (labelname, funname, insn_line (insn));
24664 labelname = get_prev_label (funname);
24666 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
24667 instruction will reach 'foo', otherwise link as 'bl L42'".
24668 "L42" should be a 'branch island', that will do a far jump to
24669 'foo'. Branch islands are generated in
24670 macho_branch_islands(). */
24671 sprintf (buf, "jbsr %%z%d,%.246s",
24672 dest_operand_number, IDENTIFIER_POINTER (labelname));
24675 sprintf (buf, "bl %%z%d", dest_operand_number);
24679 /* Generate PIC and indirect symbol stubs. */
24682 machopic_output_stub (FILE *file, const char *symb, const char *stub)
24684 unsigned int length;
24685 char *symbol_name, *lazy_ptr_name;
24686 char *local_label_0;
24687 static int label = 0;
24689 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
24690 symb = (*targetm.strip_name_encoding) (symb);
24693 length = strlen (symb);
24694 symbol_name = XALLOCAVEC (char, length + 32);
24695 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
24697 lazy_ptr_name = XALLOCAVEC (char, length + 32);
24698 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
24701 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
24703 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
24707 fprintf (file, "\t.align 5\n");
24709 fprintf (file, "%s:\n", stub);
24710 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24713 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
24714 sprintf (local_label_0, "\"L%011d$spb\"", label);
24716 fprintf (file, "\tmflr r0\n");
24717 if (TARGET_LINK_STACK)
24720 get_ppc476_thunk_name (name);
24721 fprintf (file, "\tbl %s\n", name);
24722 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
24726 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
24727 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
24729 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
24730 lazy_ptr_name, local_label_0);
24731 fprintf (file, "\tmtlr r0\n");
24732 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
24733 (TARGET_64BIT ? "ldu" : "lwzu"),
24734 lazy_ptr_name, local_label_0);
24735 fprintf (file, "\tmtctr r12\n");
24736 fprintf (file, "\tbctr\n");
24740 fprintf (file, "\t.align 4\n");
24742 fprintf (file, "%s:\n", stub);
24743 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24745 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
24746 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
24747 (TARGET_64BIT ? "ldu" : "lwzu"),
24749 fprintf (file, "\tmtctr r12\n");
24750 fprintf (file, "\tbctr\n");
24753 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
24754 fprintf (file, "%s:\n", lazy_ptr_name);
24755 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
24756 fprintf (file, "%sdyld_stub_binding_helper\n",
24757 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
24760 /* Legitimize PIC addresses. If the address is already
24761 position-independent, we return ORIG. Newly generated
24762 position-independent addresses go into a reg. This is REG if non
24763 zero, otherwise we allocate register(s) as necessary. */
24765 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
24768 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
24773 if (reg == NULL && ! reload_in_progress && ! reload_completed)
24774 reg = gen_reg_rtx (Pmode);
24776 if (GET_CODE (orig) == CONST)
24780 if (GET_CODE (XEXP (orig, 0)) == PLUS
24781 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
24784 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
24786 /* Use a different reg for the intermediate value, as
24787 it will be marked UNCHANGING. */
24788 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
24789 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
24792 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
24795 if (GET_CODE (offset) == CONST_INT)
24797 if (SMALL_INT (offset))
24798 return plus_constant (base, INTVAL (offset));
24799 else if (! reload_in_progress && ! reload_completed)
24800 offset = force_reg (Pmode, offset);
24803 rtx mem = force_const_mem (Pmode, orig);
24804 return machopic_legitimize_pic_address (mem, Pmode, reg);
24807 return gen_rtx_PLUS (Pmode, base, offset);
24810 /* Fall back on generic machopic code. */
24811 return machopic_legitimize_pic_address (orig, mode, reg);
24814 /* Output a .machine directive for the Darwin assembler, and call
24815 the generic start_file routine. */
24818 rs6000_darwin_file_start (void)
24820 static const struct
24826 { "ppc64", "ppc64", MASK_64BIT },
24827 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
24828 { "power4", "ppc970", 0 },
24829 { "G5", "ppc970", 0 },
24830 { "7450", "ppc7450", 0 },
24831 { "7400", "ppc7400", MASK_ALTIVEC },
24832 { "G4", "ppc7400", 0 },
24833 { "750", "ppc750", 0 },
24834 { "740", "ppc750", 0 },
24835 { "G3", "ppc750", 0 },
24836 { "604e", "ppc604e", 0 },
24837 { "604", "ppc604", 0 },
24838 { "603e", "ppc603", 0 },
24839 { "603", "ppc603", 0 },
24840 { "601", "ppc601", 0 },
24841 { NULL, "ppc", 0 } };
24842 const char *cpu_id = "";
24845 rs6000_file_start ();
24846 darwin_file_start ();
24848 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
24850 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
24851 cpu_id = rs6000_default_cpu;
24853 if (global_options_set.x_rs6000_cpu_index)
24854 cpu_id = processor_target_table[rs6000_cpu_index].name;
24856 /* Look through the mapping array. Pick the first name that either
24857 matches the argument, has a bit set in IF_SET that is also set
24858 in the target flags, or has a NULL name. */
24861 while (mapping[i].arg != NULL
24862 && strcmp (mapping[i].arg, cpu_id) != 0
24863 && (mapping[i].if_set & target_flags) == 0)
24866 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
24869 #endif /* TARGET_MACHO */
24873 rs6000_elf_reloc_rw_mask (void)
24877 else if (DEFAULT_ABI == ABI_AIX)
24883 /* Record an element in the table of global constructors. SYMBOL is
24884 a SYMBOL_REF of the function to be called; PRIORITY is a number
24885 between 0 and MAX_INIT_PRIORITY.
24887 This differs from default_named_section_asm_out_constructor in
24888 that we have special handling for -mrelocatable. */
24891 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
24893 const char *section = ".ctors";
24896 if (priority != DEFAULT_INIT_PRIORITY)
24898 sprintf (buf, ".ctors.%.5u",
24899 /* Invert the numbering so the linker puts us in the proper
24900 order; constructors are run from right to left, and the
24901 linker sorts in increasing order. */
24902 MAX_INIT_PRIORITY - priority);
24906 switch_to_section (get_section (section, SECTION_WRITE, NULL));
24907 assemble_align (POINTER_SIZE);
24909 if (TARGET_RELOCATABLE)
24911 fputs ("\t.long (", asm_out_file);
24912 output_addr_const (asm_out_file, symbol);
24913 fputs (")@fixup\n", asm_out_file);
24916 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
24920 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
24922 const char *section = ".dtors";
24925 if (priority != DEFAULT_INIT_PRIORITY)
24927 sprintf (buf, ".dtors.%.5u",
24928 /* Invert the numbering so the linker puts us in the proper
24929 order; constructors are run from right to left, and the
24930 linker sorts in increasing order. */
24931 MAX_INIT_PRIORITY - priority);
24935 switch_to_section (get_section (section, SECTION_WRITE, NULL));
24936 assemble_align (POINTER_SIZE);
24938 if (TARGET_RELOCATABLE)
24940 fputs ("\t.long (", asm_out_file);
24941 output_addr_const (asm_out_file, symbol);
24942 fputs (")@fixup\n", asm_out_file);
24945 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
24949 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
24953 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
24954 ASM_OUTPUT_LABEL (file, name);
24955 fputs (DOUBLE_INT_ASM_OP, file);
24956 rs6000_output_function_entry (file, name);
24957 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
24960 fputs ("\t.size\t", file);
24961 assemble_name (file, name);
24962 fputs (",24\n\t.type\t.", file);
24963 assemble_name (file, name);
24964 fputs (",@function\n", file);
24965 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
24967 fputs ("\t.globl\t.", file);
24968 assemble_name (file, name);
24973 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
24974 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
24975 rs6000_output_function_entry (file, name);
24976 fputs (":\n", file);
24980 if (TARGET_RELOCATABLE
24981 && !TARGET_SECURE_PLT
24982 && (get_pool_size () != 0 || crtl->profile)
24987 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
24989 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
24990 fprintf (file, "\t.long ");
24991 assemble_name (file, buf);
24993 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
24994 assemble_name (file, buf);
24998 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
24999 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
25001 if (DEFAULT_ABI == ABI_AIX)
25003 const char *desc_name, *orig_name;
25005 orig_name = (*targetm.strip_name_encoding) (name);
25006 desc_name = orig_name;
25007 while (*desc_name == '.')
25010 if (TREE_PUBLIC (decl))
25011 fprintf (file, "\t.globl %s\n", desc_name);
25013 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
25014 fprintf (file, "%s:\n", desc_name);
25015 fprintf (file, "\t.long %s\n", orig_name);
25016 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
25017 if (DEFAULT_ABI == ABI_AIX)
25018 fputs ("\t.long 0\n", file);
25019 fprintf (file, "\t.previous\n");
25021 ASM_OUTPUT_LABEL (file, name);
25025 rs6000_elf_file_end (void)
25027 #ifdef HAVE_AS_GNU_ATTRIBUTE
25028 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
25030 if (rs6000_passes_float)
25031 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
25032 ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) ? 1
25033 : (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT) ? 3
25035 if (rs6000_passes_vector)
25036 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
25037 (TARGET_ALTIVEC_ABI ? 2
25038 : TARGET_SPE_ABI ? 3
25040 if (rs6000_returns_struct)
25041 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
25042 aix_struct_return ? 2 : 1);
25045 #ifdef POWERPC_LINUX
25047 file_end_indicate_exec_stack ();
25054 rs6000_xcoff_asm_output_anchor (rtx symbol)
25058 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
25059 SYMBOL_REF_BLOCK_OFFSET (symbol));
25060 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
25064 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
25066 fputs (GLOBAL_ASM_OP, stream);
25067 RS6000_OUTPUT_BASENAME (stream, name);
25068 putc ('\n', stream);
25071 /* A get_unnamed_decl callback, used for read-only sections. PTR
25072 points to the section string variable. */
25075 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
25077 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
25078 *(const char *const *) directive,
25079 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25082 /* Likewise for read-write sections. */
25085 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
25087 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
25088 *(const char *const *) directive,
25089 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
25092 /* A get_unnamed_section callback, used for switching to toc_section. */
25095 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
25097 if (TARGET_MINIMAL_TOC)
25099 /* toc_section is always selected at least once from
25100 rs6000_xcoff_file_start, so this is guaranteed to
25101 always be defined once and only once in each file. */
25102 if (!toc_initialized)
25104 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
25105 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
25106 toc_initialized = 1;
25108 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
25109 (TARGET_32BIT ? "" : ",3"));
25112 fputs ("\t.toc\n", asm_out_file);
25115 /* Implement TARGET_ASM_INIT_SECTIONS. */
25118 rs6000_xcoff_asm_init_sections (void)
25120 read_only_data_section
25121 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25122 &xcoff_read_only_section_name);
25124 private_data_section
25125 = get_unnamed_section (SECTION_WRITE,
25126 rs6000_xcoff_output_readwrite_section_asm_op,
25127 &xcoff_private_data_section_name);
25129 read_only_private_data_section
25130 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
25131 &xcoff_private_data_section_name);
25134 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
25136 readonly_data_section = read_only_data_section;
25137 exception_section = data_section;
25141 rs6000_xcoff_reloc_rw_mask (void)
25147 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
25148 tree decl ATTRIBUTE_UNUSED)
25151 static const char * const suffix[3] = { "PR", "RO", "RW" };
25153 if (flags & SECTION_CODE)
25155 else if (flags & SECTION_WRITE)
25160 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
25161 (flags & SECTION_CODE) ? "." : "",
25162 name, suffix[smclass], flags & SECTION_ENTSIZE);
25166 rs6000_xcoff_select_section (tree decl, int reloc,
25167 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25169 if (decl_readonly_section (decl, reloc))
25171 if (TREE_PUBLIC (decl))
25172 return read_only_data_section;
25174 return read_only_private_data_section;
25178 if (TREE_PUBLIC (decl))
25179 return data_section;
25181 return private_data_section;
25186 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
25190 /* Use select_section for private and uninitialized data. */
25191 if (!TREE_PUBLIC (decl)
25192 || DECL_COMMON (decl)
25193 || DECL_INITIAL (decl) == NULL_TREE
25194 || DECL_INITIAL (decl) == error_mark_node
25195 || (flag_zero_initialized_in_bss
25196 && initializer_zerop (DECL_INITIAL (decl))))
25199 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
25200 name = (*targetm.strip_name_encoding) (name);
25201 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
25204 /* Select section for constant in constant pool.
25206 On RS/6000, all constants are in the private read-only data area.
25207 However, if this is being placed in the TOC it must be output as a
25211 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
25212 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
25214 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
25215 return toc_section;
25217 return read_only_private_data_section;
25220 /* Remove any trailing [DS] or the like from the symbol name. */
25222 static const char *
25223 rs6000_xcoff_strip_name_encoding (const char *name)
25228 len = strlen (name);
25229 if (name[len - 1] == ']')
25230 return ggc_alloc_string (name, len - 4);
25235 /* Section attributes. AIX is always PIC. */
25237 static unsigned int
25238 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
25240 unsigned int align;
25241 unsigned int flags = default_section_type_flags (decl, name, reloc);
25243 /* Align to at least UNIT size. */
25244 if (flags & SECTION_CODE || !decl)
25245 align = MIN_UNITS_PER_WORD;
25247 /* Increase alignment of large objects if not already stricter. */
25248 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
25249 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
25250 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
25252 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
25255 /* Output at beginning of assembler file.
25257 Initialize the section names for the RS/6000 at this point.
25259 Specify filename, including full path, to assembler.
25261 We want to go into the TOC section so at least one .toc will be emitted.
25262 Also, in order to output proper .bs/.es pairs, we need at least one static
25263 [RW] section emitted.
25265 Finally, declare mcount when profiling to make the assembler happy. */
25268 rs6000_xcoff_file_start (void)
25270 rs6000_gen_section_name (&xcoff_bss_section_name,
25271 main_input_filename, ".bss_");
25272 rs6000_gen_section_name (&xcoff_private_data_section_name,
25273 main_input_filename, ".rw_");
25274 rs6000_gen_section_name (&xcoff_read_only_section_name,
25275 main_input_filename, ".ro_");
25277 fputs ("\t.file\t", asm_out_file);
25278 output_quoted_string (asm_out_file, main_input_filename);
25279 fputc ('\n', asm_out_file);
25280 if (write_symbols != NO_DEBUG)
25281 switch_to_section (private_data_section);
25282 switch_to_section (text_section);
25284 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
25285 rs6000_file_start ();
25288 /* Output at end of assembler file.
25289 On the RS/6000, referencing data should automatically pull in text. */
25292 rs6000_xcoff_file_end (void)
25294 switch_to_section (text_section);
25295 fputs ("_section_.text:\n", asm_out_file);
25296 switch_to_section (data_section);
25297 fputs (TARGET_32BIT
25298 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
25301 #endif /* TARGET_XCOFF */
25303 /* Compute a (partial) cost for rtx X. Return true if the complete
25304 cost has been computed, and false if subexpressions should be
25305 scanned. In either case, *TOTAL contains the cost result. */
25308 rs6000_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
25309 int *total, bool speed)
25311 enum machine_mode mode = GET_MODE (x);
25315 /* On the RS/6000, if it is valid in the insn, it is free. */
25317 if (((outer_code == SET
25318 || outer_code == PLUS
25319 || outer_code == MINUS)
25320 && (satisfies_constraint_I (x)
25321 || satisfies_constraint_L (x)))
25322 || (outer_code == AND
25323 && (satisfies_constraint_K (x)
25325 ? satisfies_constraint_L (x)
25326 : satisfies_constraint_J (x))
25327 || mask_operand (x, mode)
25329 && mask64_operand (x, DImode))))
25330 || ((outer_code == IOR || outer_code == XOR)
25331 && (satisfies_constraint_K (x)
25333 ? satisfies_constraint_L (x)
25334 : satisfies_constraint_J (x))))
25335 || outer_code == ASHIFT
25336 || outer_code == ASHIFTRT
25337 || outer_code == LSHIFTRT
25338 || outer_code == ROTATE
25339 || outer_code == ROTATERT
25340 || outer_code == ZERO_EXTRACT
25341 || (outer_code == MULT
25342 && satisfies_constraint_I (x))
25343 || ((outer_code == DIV || outer_code == UDIV
25344 || outer_code == MOD || outer_code == UMOD)
25345 && exact_log2 (INTVAL (x)) >= 0)
25346 || (outer_code == COMPARE
25347 && (satisfies_constraint_I (x)
25348 || satisfies_constraint_K (x)))
25349 || ((outer_code == EQ || outer_code == NE)
25350 && (satisfies_constraint_I (x)
25351 || satisfies_constraint_K (x)
25353 ? satisfies_constraint_L (x)
25354 : satisfies_constraint_J (x))))
25355 || (outer_code == GTU
25356 && satisfies_constraint_I (x))
25357 || (outer_code == LTU
25358 && satisfies_constraint_P (x)))
25363 else if ((outer_code == PLUS
25364 && reg_or_add_cint_operand (x, VOIDmode))
25365 || (outer_code == MINUS
25366 && reg_or_sub_cint_operand (x, VOIDmode))
25367 || ((outer_code == SET
25368 || outer_code == IOR
25369 || outer_code == XOR)
25371 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
25373 *total = COSTS_N_INSNS (1);
25379 if (mode == DImode && code == CONST_DOUBLE)
25381 if ((outer_code == IOR || outer_code == XOR)
25382 && CONST_DOUBLE_HIGH (x) == 0
25383 && (CONST_DOUBLE_LOW (x)
25384 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
25389 else if ((outer_code == AND && and64_2_operand (x, DImode))
25390 || ((outer_code == SET
25391 || outer_code == IOR
25392 || outer_code == XOR)
25393 && CONST_DOUBLE_HIGH (x) == 0))
25395 *total = COSTS_N_INSNS (1);
25405 /* When optimizing for size, MEM should be slightly more expensive
25406 than generating address, e.g., (plus (reg) (const)).
25407 L1 cache latency is about two instructions. */
25408 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
25417 if (FLOAT_MODE_P (mode))
25418 *total = rs6000_cost->fp;
25420 *total = COSTS_N_INSNS (1);
25424 if (GET_CODE (XEXP (x, 1)) == CONST_INT
25425 && satisfies_constraint_I (XEXP (x, 1)))
25427 if (INTVAL (XEXP (x, 1)) >= -256
25428 && INTVAL (XEXP (x, 1)) <= 255)
25429 *total = rs6000_cost->mulsi_const9;
25431 *total = rs6000_cost->mulsi_const;
25433 else if (mode == SFmode)
25434 *total = rs6000_cost->fp;
25435 else if (FLOAT_MODE_P (mode))
25436 *total = rs6000_cost->dmul;
25437 else if (mode == DImode)
25438 *total = rs6000_cost->muldi;
25440 *total = rs6000_cost->mulsi;
25444 if (mode == SFmode)
25445 *total = rs6000_cost->fp;
25447 *total = rs6000_cost->dmul;
25452 if (FLOAT_MODE_P (mode))
25454 *total = mode == DFmode ? rs6000_cost->ddiv
25455 : rs6000_cost->sdiv;
25462 if (GET_CODE (XEXP (x, 1)) == CONST_INT
25463 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
25465 if (code == DIV || code == MOD)
25467 *total = COSTS_N_INSNS (2);
25470 *total = COSTS_N_INSNS (1);
25474 if (GET_MODE (XEXP (x, 1)) == DImode)
25475 *total = rs6000_cost->divdi;
25477 *total = rs6000_cost->divsi;
25479 /* Add in shift and subtract for MOD. */
25480 if (code == MOD || code == UMOD)
25481 *total += COSTS_N_INSNS (2);
25486 *total = COSTS_N_INSNS (4);
25490 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
25494 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
25498 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
25510 *total = COSTS_N_INSNS (1);
25518 /* Handle mul_highpart. */
25519 if (outer_code == TRUNCATE
25520 && GET_CODE (XEXP (x, 0)) == MULT)
25522 if (mode == DImode)
25523 *total = rs6000_cost->muldi;
25525 *total = rs6000_cost->mulsi;
25528 else if (outer_code == AND)
25531 *total = COSTS_N_INSNS (1);
25536 if (GET_CODE (XEXP (x, 0)) == MEM)
25539 *total = COSTS_N_INSNS (1);
25545 if (!FLOAT_MODE_P (mode))
25547 *total = COSTS_N_INSNS (1);
25553 case UNSIGNED_FLOAT:
25556 case FLOAT_TRUNCATE:
25557 *total = rs6000_cost->fp;
25561 if (mode == DFmode)
25564 *total = rs6000_cost->fp;
25568 switch (XINT (x, 1))
25571 *total = rs6000_cost->fp;
25583 *total = COSTS_N_INSNS (1);
25586 else if (FLOAT_MODE_P (mode)
25587 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
25589 *total = rs6000_cost->fp;
25597 /* Carry bit requires mode == Pmode.
25598 NEG or PLUS already counted so only add one. */
25600 && (outer_code == NEG || outer_code == PLUS))
25602 *total = COSTS_N_INSNS (1);
25605 if (outer_code == SET)
25607 if (XEXP (x, 1) == const0_rtx)
25609 if (TARGET_ISEL && !TARGET_MFCRF)
25610 *total = COSTS_N_INSNS (8);
25612 *total = COSTS_N_INSNS (2);
25615 else if (mode == Pmode)
25617 *total = COSTS_N_INSNS (3);
25626 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
25628 if (TARGET_ISEL && !TARGET_MFCRF)
25629 *total = COSTS_N_INSNS (8);
25631 *total = COSTS_N_INSNS (2);
25635 if (outer_code == COMPARE)
25649 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
25652 rs6000_debug_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
25655 bool ret = rs6000_rtx_costs (x, code, outer_code, opno, total, speed);
25658 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
25659 "opno = %d, total = %d, speed = %s, x:\n",
25660 ret ? "complete" : "scan inner",
25661 GET_RTX_NAME (code),
25662 GET_RTX_NAME (outer_code),
25665 speed ? "true" : "false");
25672 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
25675 rs6000_debug_address_cost (rtx x, bool speed)
25677 int ret = TARGET_ADDRESS_COST (x, speed);
25679 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
25680 ret, speed ? "true" : "false");
25687 /* A C expression returning the cost of moving data from a register of class
25688 CLASS1 to one of CLASS2. */
25691 rs6000_register_move_cost (enum machine_mode mode,
25692 reg_class_t from, reg_class_t to)
25696 if (TARGET_DEBUG_COST)
25699 /* Moves from/to GENERAL_REGS. */
25700 if (reg_classes_intersect_p (to, GENERAL_REGS)
25701 || reg_classes_intersect_p (from, GENERAL_REGS))
25703 reg_class_t rclass = from;
25705 if (! reg_classes_intersect_p (to, GENERAL_REGS))
25708 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
25709 ret = (rs6000_memory_move_cost (mode, rclass, false)
25710 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
25712 /* It's more expensive to move CR_REGS than CR0_REGS because of the
25714 else if (rclass == CR_REGS)
25717 /* For those processors that have slow LR/CTR moves, make them more
25718 expensive than memory in order to bias spills to memory .*/
25719 else if ((rs6000_cpu == PROCESSOR_POWER6
25720 || rs6000_cpu == PROCESSOR_POWER7)
25721 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
25722 ret = 6 * hard_regno_nregs[0][mode];
25725 /* A move will cost one instruction per GPR moved. */
25726 ret = 2 * hard_regno_nregs[0][mode];
25729 /* If we have VSX, we can easily move between FPR or Altivec registers. */
25730 else if (VECTOR_UNIT_VSX_P (mode)
25731 && reg_classes_intersect_p (to, VSX_REGS)
25732 && reg_classes_intersect_p (from, VSX_REGS))
25733 ret = 2 * hard_regno_nregs[32][mode];
25735 /* Moving between two similar registers is just one instruction. */
25736 else if (reg_classes_intersect_p (to, from))
25737 ret = (mode == TFmode || mode == TDmode) ? 4 : 2;
25739 /* Everything else has to go through GENERAL_REGS. */
25741 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
25742 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
25744 if (TARGET_DEBUG_COST)
25746 if (dbg_cost_ctrl == 1)
25748 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
25749 ret, GET_MODE_NAME (mode), reg_class_names[from],
25750 reg_class_names[to]);
25757 /* A C expressions returning the cost of moving data of MODE from a register to
25761 rs6000_memory_move_cost (enum machine_mode mode, reg_class_t rclass,
25762 bool in ATTRIBUTE_UNUSED)
25766 if (TARGET_DEBUG_COST)
25769 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
25770 ret = 4 * hard_regno_nregs[0][mode];
25771 else if (reg_classes_intersect_p (rclass, FLOAT_REGS))
25772 ret = 4 * hard_regno_nregs[32][mode];
25773 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
25774 ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
25776 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
25778 if (TARGET_DEBUG_COST)
25780 if (dbg_cost_ctrl == 1)
25782 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
25783 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
25790 /* Returns a code for a target-specific builtin that implements
25791 reciprocal of the function, or NULL_TREE if not available. */
25794 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
25795 bool sqrt ATTRIBUTE_UNUSED)
25797 if (optimize_insn_for_size_p ())
25803 case VSX_BUILTIN_XVSQRTDP:
25804 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
25807 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
25809 case VSX_BUILTIN_XVSQRTSP:
25810 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
25813 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
25822 case BUILT_IN_SQRT:
25823 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode))
25826 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRT];
25828 case BUILT_IN_SQRTF:
25829 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode))
25832 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
25839 /* Load up a constant. If the mode is a vector mode, splat the value across
25840 all of the vector elements. */
25843 rs6000_load_constant_and_splat (enum machine_mode mode, REAL_VALUE_TYPE dconst)
25847 if (mode == SFmode || mode == DFmode)
25849 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, mode);
25850 reg = force_reg (mode, d);
25852 else if (mode == V4SFmode)
25854 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, SFmode);
25855 rtvec v = gen_rtvec (4, d, d, d, d);
25856 reg = gen_reg_rtx (mode);
25857 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
25859 else if (mode == V2DFmode)
25861 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, DFmode);
25862 rtvec v = gen_rtvec (2, d, d);
25863 reg = gen_reg_rtx (mode);
25864 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
25867 gcc_unreachable ();
25872 /* Generate an FMA instruction. */
25875 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
25877 enum machine_mode mode = GET_MODE (target);
25880 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
25881 gcc_assert (dst != NULL);
25884 emit_move_insn (target, dst);
25887 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
25890 rs6000_emit_msub (rtx target, rtx m1, rtx m2, rtx a)
25892 enum machine_mode mode = GET_MODE (target);
25895 /* Altivec does not support fms directly;
25896 generate in terms of fma in that case. */
25897 if (optab_handler (fms_optab, mode) != CODE_FOR_nothing)
25898 dst = expand_ternary_op (mode, fms_optab, m1, m2, a, target, 0);
25901 a = expand_unop (mode, neg_optab, a, NULL_RTX, 0);
25902 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
25904 gcc_assert (dst != NULL);
25907 emit_move_insn (target, dst);
25910 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
25913 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
25915 enum machine_mode mode = GET_MODE (dst);
25918 /* This is a tad more complicated, since the fnma_optab is for
25919 a different expression: fma(-m1, m2, a), which is the same
25920 thing except in the case of signed zeros.
25922 Fortunately we know that if FMA is supported that FNMSUB is
25923 also supported in the ISA. Just expand it directly. */
25925 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
25927 r = gen_rtx_NEG (mode, a);
25928 r = gen_rtx_FMA (mode, m1, m2, r);
25929 r = gen_rtx_NEG (mode, r);
25930 emit_insn (gen_rtx_SET (VOIDmode, dst, r));
25933 /* Newton-Raphson approximation of floating point divide with just 2 passes
25934 (either single precision floating point, or newer machines with higher
25935 accuracy estimates). Support both scalar and vector divide. Assumes no
25936 trapping math and finite arguments. */
25939 rs6000_emit_swdiv_high_precision (rtx dst, rtx n, rtx d)
25941 enum machine_mode mode = GET_MODE (dst);
25942 rtx x0, e0, e1, y1, u0, v0;
25943 enum insn_code code = optab_handler (smul_optab, mode);
25944 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
25945 rtx one = rs6000_load_constant_and_splat (mode, dconst1);
25947 gcc_assert (code != CODE_FOR_nothing);
25949 /* x0 = 1./d estimate */
25950 x0 = gen_reg_rtx (mode);
25951 emit_insn (gen_rtx_SET (VOIDmode, x0,
25952 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
25955 e0 = gen_reg_rtx (mode);
25956 rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - (d * x0) */
25958 e1 = gen_reg_rtx (mode);
25959 rs6000_emit_madd (e1, e0, e0, e0); /* e1 = (e0 * e0) + e0 */
25961 y1 = gen_reg_rtx (mode);
25962 rs6000_emit_madd (y1, e1, x0, x0); /* y1 = (e1 * x0) + x0 */
25964 u0 = gen_reg_rtx (mode);
25965 emit_insn (gen_mul (u0, n, y1)); /* u0 = n * y1 */
25967 v0 = gen_reg_rtx (mode);
25968 rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - (d * u0) */
25970 rs6000_emit_madd (dst, v0, y1, u0); /* dst = (v0 * y1) + u0 */
25973 /* Newton-Raphson approximation of floating point divide that has a low
25974 precision estimate. Assumes no trapping math and finite arguments. */
25977 rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d)
25979 enum machine_mode mode = GET_MODE (dst);
25980 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
25981 enum insn_code code = optab_handler (smul_optab, mode);
25982 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
25984 gcc_assert (code != CODE_FOR_nothing);
25986 one = rs6000_load_constant_and_splat (mode, dconst1);
25988 /* x0 = 1./d estimate */
25989 x0 = gen_reg_rtx (mode);
25990 emit_insn (gen_rtx_SET (VOIDmode, x0,
25991 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
25994 e0 = gen_reg_rtx (mode);
25995 rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - d * x0 */
25997 y1 = gen_reg_rtx (mode);
25998 rs6000_emit_madd (y1, e0, x0, x0); /* y1 = x0 + e0 * x0 */
26000 e1 = gen_reg_rtx (mode);
26001 emit_insn (gen_mul (e1, e0, e0)); /* e1 = e0 * e0 */
26003 y2 = gen_reg_rtx (mode);
26004 rs6000_emit_madd (y2, e1, y1, y1); /* y2 = y1 + e1 * y1 */
26006 e2 = gen_reg_rtx (mode);
26007 emit_insn (gen_mul (e2, e1, e1)); /* e2 = e1 * e1 */
26009 y3 = gen_reg_rtx (mode);
26010 rs6000_emit_madd (y3, e2, y2, y2); /* y3 = y2 + e2 * y2 */
26012 u0 = gen_reg_rtx (mode);
26013 emit_insn (gen_mul (u0, n, y3)); /* u0 = n * y3 */
26015 v0 = gen_reg_rtx (mode);
26016 rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - d * u0 */
26018 rs6000_emit_madd (dst, v0, y3, u0); /* dst = u0 + v0 * y3 */
26021 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
26022 add a reg_note saying that this was a division. Support both scalar and
26023 vector divide. Assumes no trapping math and finite arguments. */
26026 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
26028 enum machine_mode mode = GET_MODE (dst);
26030 if (RS6000_RECIP_HIGH_PRECISION_P (mode))
26031 rs6000_emit_swdiv_high_precision (dst, n, d);
26033 rs6000_emit_swdiv_low_precision (dst, n, d);
26036 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
26039 /* Newton-Raphson approximation of single/double-precision floating point
26040 rsqrt. Assumes no trapping math and finite arguments. */
26043 rs6000_emit_swrsqrt (rtx dst, rtx src)
26045 enum machine_mode mode = GET_MODE (src);
26046 rtx x0 = gen_reg_rtx (mode);
26047 rtx y = gen_reg_rtx (mode);
26048 int passes = (TARGET_RECIP_PRECISION) ? 2 : 3;
26049 REAL_VALUE_TYPE dconst3_2;
26052 enum insn_code code = optab_handler (smul_optab, mode);
26053 gen_2arg_fn_t gen_mul = (gen_2arg_fn_t) GEN_FCN (code);
26055 gcc_assert (code != CODE_FOR_nothing);
26057 /* Load up the constant 1.5 either as a scalar, or as a vector. */
26058 real_from_integer (&dconst3_2, VOIDmode, 3, 0, 0);
26059 SET_REAL_EXP (&dconst3_2, REAL_EXP (&dconst3_2) - 1);
26061 halfthree = rs6000_load_constant_and_splat (mode, dconst3_2);
26063 /* x0 = rsqrt estimate */
26064 emit_insn (gen_rtx_SET (VOIDmode, x0,
26065 gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
26068 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
26069 rs6000_emit_msub (y, src, halfthree, src);
26071 for (i = 0; i < passes; i++)
26073 rtx x1 = gen_reg_rtx (mode);
26074 rtx u = gen_reg_rtx (mode);
26075 rtx v = gen_reg_rtx (mode);
26077 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
26078 emit_insn (gen_mul (u, x0, x0));
26079 rs6000_emit_nmsub (v, y, u, halfthree);
26080 emit_insn (gen_mul (x1, x0, v));
26084 emit_move_insn (dst, x0);
26088 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
26089 (Power7) targets. DST is the target, and SRC is the argument operand. */
26092 rs6000_emit_popcount (rtx dst, rtx src)
26094 enum machine_mode mode = GET_MODE (dst);
26097 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
26098 if (TARGET_POPCNTD)
26100 if (mode == SImode)
26101 emit_insn (gen_popcntdsi2 (dst, src));
26103 emit_insn (gen_popcntddi2 (dst, src));
26107 tmp1 = gen_reg_rtx (mode);
26109 if (mode == SImode)
26111 emit_insn (gen_popcntbsi2 (tmp1, src));
26112 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
26114 tmp2 = force_reg (SImode, tmp2);
26115 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
26119 emit_insn (gen_popcntbdi2 (tmp1, src));
26120 tmp2 = expand_mult (DImode, tmp1,
26121 GEN_INT ((HOST_WIDE_INT)
26122 0x01010101 << 32 | 0x01010101),
26124 tmp2 = force_reg (DImode, tmp2);
26125 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
26130 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
26131 target, and SRC is the argument operand. */
26134 rs6000_emit_parity (rtx dst, rtx src)
26136 enum machine_mode mode = GET_MODE (dst);
26139 tmp = gen_reg_rtx (mode);
26141 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
26144 if (mode == SImode)
26146 emit_insn (gen_popcntbsi2 (tmp, src));
26147 emit_insn (gen_paritysi2_cmpb (dst, tmp));
26151 emit_insn (gen_popcntbdi2 (tmp, src));
26152 emit_insn (gen_paritydi2_cmpb (dst, tmp));
26157 if (mode == SImode)
26159 /* Is mult+shift >= shift+xor+shift+xor? */
26160 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
26162 rtx tmp1, tmp2, tmp3, tmp4;
26164 tmp1 = gen_reg_rtx (SImode);
26165 emit_insn (gen_popcntbsi2 (tmp1, src));
26167 tmp2 = gen_reg_rtx (SImode);
26168 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
26169 tmp3 = gen_reg_rtx (SImode);
26170 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
26172 tmp4 = gen_reg_rtx (SImode);
26173 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
26174 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
26177 rs6000_emit_popcount (tmp, src);
26178 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
26182 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
26183 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
26185 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
26187 tmp1 = gen_reg_rtx (DImode);
26188 emit_insn (gen_popcntbdi2 (tmp1, src));
26190 tmp2 = gen_reg_rtx (DImode);
26191 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
26192 tmp3 = gen_reg_rtx (DImode);
26193 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
26195 tmp4 = gen_reg_rtx (DImode);
26196 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
26197 tmp5 = gen_reg_rtx (DImode);
26198 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
26200 tmp6 = gen_reg_rtx (DImode);
26201 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
26202 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
26205 rs6000_emit_popcount (tmp, src);
26206 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
26210 /* Expand an Altivec constant permutation. Return true if we match
26211 an efficient implementation; false to fall back to VPERM. */
26214 altivec_expand_vec_perm_const (rtx operands[4])
26216 struct altivec_perm_insn {
26217 enum insn_code impl;
26218 unsigned char perm[16];
26220 static const struct altivec_perm_insn patterns[] = {
26221 { CODE_FOR_altivec_vpkuhum,
26222 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
26223 { CODE_FOR_altivec_vpkuwum,
26224 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
26225 { CODE_FOR_altivec_vmrghb,
26226 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
26227 { CODE_FOR_altivec_vmrghh,
26228 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
26229 { CODE_FOR_altivec_vmrghw,
26230 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
26231 { CODE_FOR_altivec_vmrglb,
26232 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
26233 { CODE_FOR_altivec_vmrglh,
26234 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
26235 { CODE_FOR_altivec_vmrglw,
26236 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }
26239 unsigned int i, j, elt, which;
26240 unsigned char perm[16];
26241 rtx target, op0, op1, sel, x;
26244 target = operands[0];
26249 /* Unpack the constant selector. */
26250 for (i = which = 0; i < 16; ++i)
26252 rtx e = XVECEXP (sel, 0, i);
26253 elt = INTVAL (e) & 31;
26254 which |= (elt < 16 ? 1 : 2);
26258 /* Simplify the constant selector based on operands. */
26262 gcc_unreachable ();
26266 if (!rtx_equal_p (op0, op1))
26271 for (i = 0; i < 16; ++i)
26283 /* Look for splat patterns. */
26288 for (i = 0; i < 16; ++i)
26289 if (perm[i] != elt)
26293 emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt)));
26299 for (i = 0; i < 16; i += 2)
26300 if (perm[i] != elt || perm[i + 1] != elt + 1)
26304 x = gen_reg_rtx (V8HImode);
26305 emit_insn (gen_altivec_vsplth (x, gen_lowpart (V8HImode, op0),
26306 GEN_INT (elt / 2)));
26307 emit_move_insn (target, gen_lowpart (V16QImode, x));
26314 for (i = 0; i < 16; i += 4)
26316 || perm[i + 1] != elt + 1
26317 || perm[i + 2] != elt + 2
26318 || perm[i + 3] != elt + 3)
26322 x = gen_reg_rtx (V4SImode);
26323 emit_insn (gen_altivec_vspltw (x, gen_lowpart (V4SImode, op0),
26324 GEN_INT (elt / 4)));
26325 emit_move_insn (target, gen_lowpart (V16QImode, x));
26331 /* Look for merge and pack patterns. */
26332 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
26336 elt = patterns[j].perm[0];
26337 if (perm[0] == elt)
26339 else if (perm[0] == elt + 16)
26343 for (i = 1; i < 16; ++i)
26345 elt = patterns[j].perm[i];
26347 elt = (elt >= 16 ? elt - 16 : elt + 16);
26348 else if (one_vec && elt >= 16)
26350 if (perm[i] != elt)
26355 enum insn_code icode = patterns[j].impl;
26356 enum machine_mode omode = insn_data[icode].operand[0].mode;
26357 enum machine_mode imode = insn_data[icode].operand[1].mode;
26360 x = op0, op0 = op1, op1 = x;
26361 if (imode != V16QImode)
26363 op0 = gen_lowpart (imode, op0);
26364 op1 = gen_lowpart (imode, op1);
26366 if (omode == V16QImode)
26369 x = gen_reg_rtx (omode);
26370 emit_insn (GEN_FCN (icode) (x, op0, op1));
26371 if (omode != V16QImode)
26372 emit_move_insn (target, gen_lowpart (V16QImode, x));
26380 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
26381 Return true if we match an efficient implementation. */
26384 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
26385 unsigned char perm0, unsigned char perm1)
26389 /* If both selectors come from the same operand, fold to single op. */
26390 if ((perm0 & 2) == (perm1 & 2))
26397 /* If both operands are equal, fold to simpler permutation. */
26398 if (rtx_equal_p (op0, op1))
26401 perm1 = (perm1 & 1) + 2;
26403 /* If the first selector comes from the second operand, swap. */
26404 else if (perm0 & 2)
26410 x = op0, op0 = op1, op1 = x;
26412 /* If the second selector does not come from the second operand, fail. */
26413 else if ((perm1 & 2) == 0)
26417 if (target != NULL)
26419 enum machine_mode vmode, dmode;
26422 vmode = GET_MODE (target);
26423 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
26424 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4);
26426 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
26427 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
26428 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
26429 emit_insn (gen_rtx_SET (VOIDmode, target, x));
26435 rs6000_expand_vec_perm_const (rtx operands[4])
26437 rtx target, op0, op1, sel;
26438 unsigned char perm0, perm1;
26440 target = operands[0];
26445 /* Unpack the constant selector. */
26446 perm0 = INTVAL (XVECEXP (sel, 0, 0)) & 3;
26447 perm1 = INTVAL (XVECEXP (sel, 0, 1)) & 3;
26449 return rs6000_expand_vec_perm_const_1 (target, op0, op1, perm0, perm1);
26452 /* Test whether a constant permutation is supported. */
26455 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode,
26456 const unsigned char *sel)
26458 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
26459 if (TARGET_ALTIVEC)
26462 /* Check for ps_merge* or evmerge* insns. */
26463 if ((TARGET_PAIRED_FLOAT && vmode == V2SFmode)
26464 || (TARGET_SPE && vmode == V2SImode))
26466 rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
26467 rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
26468 return rs6000_expand_vec_perm_const_1 (NULL, op0, op1, sel[0], sel[1]);
26474 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
26477 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
26478 enum machine_mode vmode, unsigned nelt, rtx perm[])
26480 enum machine_mode imode;
26484 if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT)
26486 imode = GET_MODE_INNER (vmode);
26487 imode = mode_for_size (GET_MODE_BITSIZE (imode), MODE_INT, 0);
26488 imode = mode_for_vector (imode, nelt);
26491 x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm));
26492 x = expand_vec_perm (vmode, op0, op1, x, target);
26494 emit_move_insn (target, x);
26497 /* Expand an extract even operation. */
26500 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
26502 enum machine_mode vmode = GET_MODE (target);
26503 unsigned i, nelt = GET_MODE_NUNITS (vmode);
26506 for (i = 0; i < nelt; i++)
26507 perm[i] = GEN_INT (i * 2);
26509 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
26512 /* Expand a vector interleave operation. */
26515 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
26517 enum machine_mode vmode = GET_MODE (target);
26518 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
26521 high = (highp == BYTES_BIG_ENDIAN ? 0 : nelt / 2);
26522 for (i = 0; i < nelt / 2; i++)
26524 perm[i * 2] = GEN_INT (i + high);
26525 perm[i * 2 + 1] = GEN_INT (i + nelt + high);
26528 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
26531 /* Return an RTX representing where to find the function value of a
26532 function returning MODE. */
26534 rs6000_complex_function_value (enum machine_mode mode)
26536 unsigned int regno;
26538 enum machine_mode inner = GET_MODE_INNER (mode);
26539 unsigned int inner_bytes = GET_MODE_SIZE (inner);
26541 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26542 regno = FP_ARG_RETURN;
26545 regno = GP_ARG_RETURN;
26547 /* 32-bit is OK since it'll go in r3/r4. */
26548 if (TARGET_32BIT && inner_bytes >= 4)
26549 return gen_rtx_REG (mode, regno);
26552 if (inner_bytes >= 8)
26553 return gen_rtx_REG (mode, regno);
26555 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
26557 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
26558 GEN_INT (inner_bytes));
26559 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
26562 /* Target hook for TARGET_FUNCTION_VALUE.
26564 On the SPE, both FPs and vectors are returned in r3.
26566 On RS/6000 an integer value is in r3 and a floating-point value is in
26567 fp1, unless -msoft-float. */
26570 rs6000_function_value (const_tree valtype,
26571 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
26572 bool outgoing ATTRIBUTE_UNUSED)
26574 enum machine_mode mode;
26575 unsigned int regno;
26577 /* Special handling for structs in darwin64. */
26579 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
26581 CUMULATIVE_ARGS valcum;
26585 valcum.fregno = FP_ARG_MIN_REG;
26586 valcum.vregno = ALTIVEC_ARG_MIN_REG;
26587 /* Do a trial code generation as if this were going to be passed as
26588 an argument; if any part goes in memory, we return NULL. */
26589 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
26592 /* Otherwise fall through to standard ABI rules. */
26595 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
26597 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
26598 return gen_rtx_PARALLEL (DImode,
26600 gen_rtx_EXPR_LIST (VOIDmode,
26601 gen_rtx_REG (SImode, GP_ARG_RETURN),
26603 gen_rtx_EXPR_LIST (VOIDmode,
26604 gen_rtx_REG (SImode,
26605 GP_ARG_RETURN + 1),
26608 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
26610 return gen_rtx_PARALLEL (DCmode,
26612 gen_rtx_EXPR_LIST (VOIDmode,
26613 gen_rtx_REG (SImode, GP_ARG_RETURN),
26615 gen_rtx_EXPR_LIST (VOIDmode,
26616 gen_rtx_REG (SImode,
26617 GP_ARG_RETURN + 1),
26619 gen_rtx_EXPR_LIST (VOIDmode,
26620 gen_rtx_REG (SImode,
26621 GP_ARG_RETURN + 2),
26623 gen_rtx_EXPR_LIST (VOIDmode,
26624 gen_rtx_REG (SImode,
26625 GP_ARG_RETURN + 3),
26629 mode = TYPE_MODE (valtype);
26630 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
26631 || POINTER_TYPE_P (valtype))
26632 mode = TARGET_32BIT ? SImode : DImode;
26634 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26635 /* _Decimal128 must use an even/odd register pair. */
26636 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
26637 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS
26638 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
26639 regno = FP_ARG_RETURN;
26640 else if (TREE_CODE (valtype) == COMPLEX_TYPE
26641 && targetm.calls.split_complex_arg)
26642 return rs6000_complex_function_value (mode);
26643 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
26644 return register is used in both cases, and we won't see V2DImode/V2DFmode
26645 for pure altivec, combine the two cases. */
26646 else if (TREE_CODE (valtype) == VECTOR_TYPE
26647 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
26648 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
26649 regno = ALTIVEC_ARG_RETURN;
26650 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
26651 && (mode == DFmode || mode == DCmode
26652 || mode == TFmode || mode == TCmode))
26653 return spe_build_register_parallel (mode, GP_ARG_RETURN);
26655 regno = GP_ARG_RETURN;
26657 return gen_rtx_REG (mode, regno);
26660 /* Define how to find the value returned by a library function
26661 assuming the value has mode MODE. */
26663 rs6000_libcall_value (enum machine_mode mode)
26665 unsigned int regno;
26667 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
26669 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
26670 return gen_rtx_PARALLEL (DImode,
26672 gen_rtx_EXPR_LIST (VOIDmode,
26673 gen_rtx_REG (SImode, GP_ARG_RETURN),
26675 gen_rtx_EXPR_LIST (VOIDmode,
26676 gen_rtx_REG (SImode,
26677 GP_ARG_RETURN + 1),
26681 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
26682 /* _Decimal128 must use an even/odd register pair. */
26683 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
26684 else if (SCALAR_FLOAT_MODE_P (mode)
26685 && TARGET_HARD_FLOAT && TARGET_FPRS
26686 && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
26687 regno = FP_ARG_RETURN;
26688 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
26689 return register is used in both cases, and we won't see V2DImode/V2DFmode
26690 for pure altivec, combine the two cases. */
26691 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
26692 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
26693 regno = ALTIVEC_ARG_RETURN;
26694 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
26695 return rs6000_complex_function_value (mode);
26696 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
26697 && (mode == DFmode || mode == DCmode
26698 || mode == TFmode || mode == TCmode))
26699 return spe_build_register_parallel (mode, GP_ARG_RETURN);
26701 regno = GP_ARG_RETURN;
26703 return gen_rtx_REG (mode, regno);
26707 /* Given FROM and TO register numbers, say whether this elimination is allowed.
26708 Frame pointer elimination is automatically handled.
26710 For the RS/6000, if frame pointer elimination is being done, we would like
26711 to convert ap into fp, not sp.
26713 We need r30 if -mminimal-toc was specified, and there are constant pool
26717 rs6000_can_eliminate (const int from, const int to)
26719 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
26720 ? ! frame_pointer_needed
26721 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
26722 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0
26726 /* Define the offset between two registers, FROM to be eliminated and its
26727 replacement TO, at the start of a routine. */
26729 rs6000_initial_elimination_offset (int from, int to)
26731 rs6000_stack_t *info = rs6000_stack_info ();
26732 HOST_WIDE_INT offset;
26734 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
26735 offset = info->push_p ? 0 : -info->total_size;
26736 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
26738 offset = info->push_p ? 0 : -info->total_size;
26739 if (FRAME_GROWS_DOWNWARD)
26740 offset += info->fixed_size + info->vars_size + info->parm_size;
26742 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
26743 offset = FRAME_GROWS_DOWNWARD
26744 ? info->fixed_size + info->vars_size + info->parm_size
26746 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
26747 offset = info->total_size;
26748 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
26749 offset = info->push_p ? info->total_size : 0;
26750 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
26753 gcc_unreachable ();
26759 rs6000_dwarf_register_span (rtx reg)
26763 unsigned regno = REGNO (reg);
26764 enum machine_mode mode = GET_MODE (reg);
26768 && (SPE_VECTOR_MODE (GET_MODE (reg))
26769 || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
26770 && mode != SFmode && mode != SDmode && mode != SCmode)))
26775 regno = REGNO (reg);
26777 /* The duality of the SPE register size wreaks all kinds of havoc.
26778 This is a way of distinguishing r0 in 32-bits from r0 in
26780 words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
26781 gcc_assert (words <= 4);
26782 for (i = 0; i < words; i++, regno++)
26784 if (BYTES_BIG_ENDIAN)
26786 parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
26787 parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
26791 parts[2 * i] = gen_rtx_REG (SImode, regno);
26792 parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
26796 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
26799 /* Fill in sizes for SPE register high parts in table used by unwinder. */
26802 rs6000_init_dwarf_reg_sizes_extra (tree address)
26807 enum machine_mode mode = TYPE_MODE (char_type_node);
26808 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
26809 rtx mem = gen_rtx_MEM (BLKmode, addr);
26810 rtx value = gen_int_mode (4, mode);
26812 for (i = 1201; i < 1232; i++)
26814 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
26815 HOST_WIDE_INT offset
26816 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
26818 emit_move_insn (adjust_address (mem, mode, offset), value);
26823 /* Map internal gcc register numbers to DWARF2 register numbers. */
26826 rs6000_dbx_register_number (unsigned int regno)
26828 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
26830 if (regno == MQ_REGNO)
26832 if (regno == LR_REGNO)
26834 if (regno == CTR_REGNO)
26836 if (CR_REGNO_P (regno))
26837 return regno - CR0_REGNO + 86;
26838 if (regno == CA_REGNO)
26839 return 101; /* XER */
26840 if (ALTIVEC_REGNO_P (regno))
26841 return regno - FIRST_ALTIVEC_REGNO + 1124;
26842 if (regno == VRSAVE_REGNO)
26844 if (regno == VSCR_REGNO)
26846 if (regno == SPE_ACC_REGNO)
26848 if (regno == SPEFSCR_REGNO)
26850 /* SPE high reg number. We get these values of regno from
26851 rs6000_dwarf_register_span. */
26852 gcc_assert (regno >= 1200 && regno < 1232);
26856 /* target hook eh_return_filter_mode */
26857 static enum machine_mode
26858 rs6000_eh_return_filter_mode (void)
26860 return TARGET_32BIT ? SImode : word_mode;
26863 /* Target hook for scalar_mode_supported_p. */
26865 rs6000_scalar_mode_supported_p (enum machine_mode mode)
26867 if (DECIMAL_FLOAT_MODE_P (mode))
26868 return default_decimal_float_supported_p ();
26870 return default_scalar_mode_supported_p (mode);
26873 /* Target hook for vector_mode_supported_p. */
26875 rs6000_vector_mode_supported_p (enum machine_mode mode)
26878 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
26881 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
26884 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
26891 /* Target hook for invalid_arg_for_unprototyped_fn. */
26892 static const char *
26893 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
26895 return (!rs6000_darwin64_abi
26897 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
26898 && (funcdecl == NULL_TREE
26899 || (TREE_CODE (funcdecl) == FUNCTION_DECL
26900 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
26901 ? N_("AltiVec argument passed to unprototyped function")
26905 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
26906 setup by using __stack_chk_fail_local hidden function instead of
26907 calling __stack_chk_fail directly. Otherwise it is better to call
26908 __stack_chk_fail directly. */
26910 static tree ATTRIBUTE_UNUSED
26911 rs6000_stack_protect_fail (void)
26913 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
26914 ? default_hidden_stack_protect_fail ()
26915 : default_external_stack_protect_fail ();
26919 rs6000_final_prescan_insn (rtx insn, rtx *operand ATTRIBUTE_UNUSED,
26920 int num_operands ATTRIBUTE_UNUSED)
26922 if (rs6000_warn_cell_microcode)
26925 int insn_code_number = recog_memoized (insn);
26926 location_t location = locator_location (INSN_LOCATOR (insn));
26928 /* Punt on insns we cannot recognize. */
26929 if (insn_code_number < 0)
26932 temp = get_insn_template (insn_code_number, insn);
26934 if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
26935 warning_at (location, OPT_mwarn_cell_microcode,
26936 "emitting microcode insn %s\t[%s] #%d",
26937 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
26938 else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
26939 warning_at (location, OPT_mwarn_cell_microcode,
26940 "emitting conditional microcode insn %s\t[%s] #%d",
26941 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
26946 /* Mask options that we want to support inside of attribute((target)) and
26947 #pragma GCC target operations. Note, we do not include things like
26948 64/32-bit, endianess, hard/soft floating point, etc. that would have
26949 different calling sequences. */
26951 struct rs6000_opt_mask {
26952 const char *name; /* option name */
26953 int mask; /* mask to set */
26954 bool invert; /* invert sense of mask */
26955 bool valid_target; /* option is a target option */
26958 static struct rs6000_opt_mask const rs6000_opt_masks[] =
26960 { "altivec", MASK_ALTIVEC, false, true },
26961 { "cmpb", MASK_CMPB, false, true },
26962 { "dlmzb", MASK_DLMZB, false, true },
26963 { "fprnd", MASK_FPRND, false, true },
26964 { "hard-dfp", MASK_DFP, false, true },
26965 { "isel", MASK_ISEL, false, true },
26966 { "mfcrf", MASK_MFCRF, false, true },
26967 { "mfpgpr", MASK_MFPGPR, false, true },
26968 { "mulhw", MASK_MULHW, false, true },
26969 { "multiple", MASK_MULTIPLE, false, true },
26970 { "update", MASK_NO_UPDATE, true , true },
26971 { "popcntb", MASK_POPCNTB, false, true },
26972 { "popcntd", MASK_POPCNTD, false, true },
26973 { "powerpc-gfxopt", MASK_PPC_GFXOPT, false, true },
26974 { "powerpc-gpopt", MASK_PPC_GPOPT, false, true },
26975 { "recip-precision", MASK_RECIP_PRECISION, false, true },
26976 { "string", MASK_STRING, false, true },
26977 { "vsx", MASK_VSX, false, true },
26980 { "aix64", MASK_64BIT, false, false },
26981 { "aix32", MASK_64BIT, true, false },
26983 { "64", MASK_64BIT, false, false },
26984 { "32", MASK_64BIT, true, false },
26988 { "eabi", MASK_EABI, false, false },
26990 #ifdef MASK_LITTLE_ENDIAN
26991 { "little", MASK_LITTLE_ENDIAN, false, false },
26992 { "big", MASK_LITTLE_ENDIAN, true, false },
26994 #ifdef MASK_RELOCATABLE
26995 { "relocatable", MASK_RELOCATABLE, false, false },
26997 #ifdef MASK_STRICT_ALIGN
26998 { "strict-align", MASK_STRICT_ALIGN, false, false },
27000 { "power", MASK_POWER, false, false },
27001 { "power2", MASK_POWER2, false, false },
27002 { "powerpc", MASK_POWERPC, false, false },
27003 { "soft-float", MASK_SOFT_FLOAT, false, false },
27004 { "string", MASK_STRING, false, false },
27007 /* Builtin mask mapping for printing the flags. */
27008 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
27010 { "altivec", RS6000_BTM_ALTIVEC, false, false },
27011 { "vsx", RS6000_BTM_VSX, false, false },
27012 { "spe", RS6000_BTM_SPE, false, false },
27013 { "paired", RS6000_BTM_PAIRED, false, false },
27014 { "fre", RS6000_BTM_FRE, false, false },
27015 { "fres", RS6000_BTM_FRES, false, false },
27016 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
27017 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
27018 { "popcntd", RS6000_BTM_POPCNTD, false, false },
27019 { "powerpc", RS6000_BTM_POWERPC, false, false },
27020 { "cell", RS6000_BTM_CELL, false, false },
27023 /* Option variables that we want to support inside attribute((target)) and
27024 #pragma GCC target operations. */
27026 struct rs6000_opt_var {
27027 const char *name; /* option name */
27028 size_t global_offset; /* offset of the option in global_options. */
27029 size_t target_offset; /* offset of the option in target optiosn. */
27032 static struct rs6000_opt_var const rs6000_opt_vars[] =
27035 offsetof (struct gcc_options, x_TARGET_FRIZ),
27036 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
27037 { "avoid-indexed-addresses",
27038 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
27039 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
27041 offsetof (struct gcc_options, x_rs6000_paired_float),
27042 offsetof (struct cl_target_option, x_rs6000_paired_float), },
27044 offsetof (struct gcc_options, x_rs6000_default_long_calls),
27045 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
27048 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
27049 parsing. Return true if there were no errors. */
27052 rs6000_inner_target_options (tree args, bool attr_p)
27056 if (args == NULL_TREE)
27059 else if (TREE_CODE (args) == STRING_CST)
27061 char *p = ASTRDUP (TREE_STRING_POINTER (args));
27064 while ((q = strtok (p, ",")) != NULL)
27066 bool error_p = false;
27067 bool not_valid_p = false;
27068 const char *cpu_opt = NULL;
27071 if (strncmp (q, "cpu=", 4) == 0)
27073 int cpu_index = rs6000_cpu_name_lookup (q+4);
27074 if (cpu_index >= 0)
27075 rs6000_cpu_index = cpu_index;
27082 else if (strncmp (q, "tune=", 5) == 0)
27084 int tune_index = rs6000_cpu_name_lookup (q+5);
27085 if (tune_index >= 0)
27086 rs6000_tune_index = tune_index;
27096 bool invert = false;
27100 if (strncmp (r, "no-", 3) == 0)
27106 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
27107 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
27109 int mask = rs6000_opt_masks[i].mask;
27111 if (!rs6000_opt_masks[i].valid_target)
27112 not_valid_p = true;
27116 target_flags_explicit |= mask;
27118 /* VSX needs altivec, so -mvsx automagically sets
27120 if (mask == MASK_VSX && !invert)
27121 mask |= MASK_ALTIVEC;
27123 if (rs6000_opt_masks[i].invert)
27127 target_flags &= ~mask;
27129 target_flags |= mask;
27134 if (error_p && !not_valid_p)
27136 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
27137 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
27139 size_t j = rs6000_opt_vars[i].global_offset;
27140 ((int *) &global_options)[j] = !invert;
27149 const char *eprefix, *esuffix;
27154 eprefix = "__attribute__((__target__(";
27159 eprefix = "#pragma GCC target ";
27164 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt, eprefix,
27166 else if (not_valid_p)
27167 error ("%s\"%s\"%s is not allowed", eprefix, q, esuffix);
27169 error ("%s\"%s\"%s is invalid", eprefix, q, esuffix);
27174 else if (TREE_CODE (args) == TREE_LIST)
27178 tree value = TREE_VALUE (args);
27181 bool ret2 = rs6000_inner_target_options (value, attr_p);
27185 args = TREE_CHAIN (args);
27187 while (args != NULL_TREE);
27191 gcc_unreachable ();
27196 /* Print out the target options as a list for -mdebug=target. */
27199 rs6000_debug_target_options (tree args, const char *prefix)
27201 if (args == NULL_TREE)
27202 fprintf (stderr, "%s<NULL>", prefix);
27204 else if (TREE_CODE (args) == STRING_CST)
27206 char *p = ASTRDUP (TREE_STRING_POINTER (args));
27209 while ((q = strtok (p, ",")) != NULL)
27212 fprintf (stderr, "%s\"%s\"", prefix, q);
27217 else if (TREE_CODE (args) == TREE_LIST)
27221 tree value = TREE_VALUE (args);
27224 rs6000_debug_target_options (value, prefix);
27227 args = TREE_CHAIN (args);
27229 while (args != NULL_TREE);
27233 gcc_unreachable ();
27239 /* Hook to validate attribute((target("..."))). */
27242 rs6000_valid_attribute_p (tree fndecl,
27243 tree ARG_UNUSED (name),
27247 struct cl_target_option cur_target;
27249 tree old_optimize = build_optimization_node ();
27250 tree new_target, new_optimize;
27251 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
27253 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
27255 if (TARGET_DEBUG_TARGET)
27257 tree tname = DECL_NAME (fndecl);
27258 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
27260 fprintf (stderr, "function: %.*s\n",
27261 (int) IDENTIFIER_LENGTH (tname),
27262 IDENTIFIER_POINTER (tname));
27264 fprintf (stderr, "function: unknown\n");
27266 fprintf (stderr, "args:");
27267 rs6000_debug_target_options (args, " ");
27268 fprintf (stderr, "\n");
27271 fprintf (stderr, "flags: 0x%x\n", flags);
27273 fprintf (stderr, "--------------------\n");
27276 old_optimize = build_optimization_node ();
27277 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
27279 /* If the function changed the optimization levels as well as setting target
27280 options, start with the optimizations specified. */
27281 if (func_optimize && func_optimize != old_optimize)
27282 cl_optimization_restore (&global_options,
27283 TREE_OPTIMIZATION (func_optimize));
27285 /* The target attributes may also change some optimization flags, so update
27286 the optimization options if necessary. */
27287 cl_target_option_save (&cur_target, &global_options);
27288 rs6000_cpu_index = rs6000_tune_index = -1;
27289 ret = rs6000_inner_target_options (args, true);
27291 /* Set up any additional state. */
27294 ret = rs6000_option_override_internal (false);
27295 new_target = build_target_option_node ();
27300 new_optimize = build_optimization_node ();
27307 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
27309 if (old_optimize != new_optimize)
27310 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
27313 cl_target_option_restore (&global_options, &cur_target);
27315 if (old_optimize != new_optimize)
27316 cl_optimization_restore (&global_options,
27317 TREE_OPTIMIZATION (old_optimize));
27323 /* Hook to validate the current #pragma GCC target and set the state, and
27324 update the macros based on what was changed. If ARGS is NULL, then
27325 POP_TARGET is used to reset the options. */
27328 rs6000_pragma_target_parse (tree args, tree pop_target)
27330 tree prev_tree = build_target_option_node ();
27332 struct cl_target_option *prev_opt, *cur_opt;
27333 unsigned prev_bumask, cur_bumask, diff_bumask;
27334 int prev_flags, cur_flags, diff_flags;
27336 if (TARGET_DEBUG_TARGET)
27338 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
27339 fprintf (stderr, "args:");
27340 rs6000_debug_target_options (args, " ");
27341 fprintf (stderr, "\n");
27345 fprintf (stderr, "pop_target:\n");
27346 debug_tree (pop_target);
27349 fprintf (stderr, "pop_target: <NULL>\n");
27351 fprintf (stderr, "--------------------\n");
27356 cur_tree = ((pop_target)
27358 : target_option_default_node);
27359 cl_target_option_restore (&global_options,
27360 TREE_TARGET_OPTION (cur_tree));
27364 rs6000_cpu_index = rs6000_tune_index = -1;
27365 if (!rs6000_inner_target_options (args, false)
27366 || !rs6000_option_override_internal (false)
27367 || (cur_tree = build_target_option_node ()) == NULL_TREE)
27369 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
27370 fprintf (stderr, "invalid pragma\n");
27376 target_option_current_node = cur_tree;
27378 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
27379 change the macros that are defined. */
27380 if (rs6000_target_modify_macros_ptr)
27382 prev_opt = TREE_TARGET_OPTION (prev_tree);
27383 prev_bumask = prev_opt->x_rs6000_builtin_mask;
27384 prev_flags = prev_opt->x_target_flags;
27386 cur_opt = TREE_TARGET_OPTION (cur_tree);
27387 cur_flags = cur_opt->x_target_flags;
27388 cur_bumask = cur_opt->x_rs6000_builtin_mask;
27390 diff_bumask = (prev_bumask ^ cur_bumask);
27391 diff_flags = (prev_flags ^ cur_flags);
27393 if ((diff_flags != 0) || (diff_bumask != 0))
27395 /* Delete old macros. */
27396 rs6000_target_modify_macros_ptr (false,
27397 prev_flags & diff_flags,
27398 prev_bumask & diff_bumask);
27400 /* Define new macros. */
27401 rs6000_target_modify_macros_ptr (true,
27402 cur_flags & diff_flags,
27403 cur_bumask & diff_bumask);
27411 /* Remember the last target of rs6000_set_current_function. */
27412 static GTY(()) tree rs6000_previous_fndecl;
27414 /* Establish appropriate back-end context for processing the function
27415 FNDECL. The argument might be NULL to indicate processing at top
27416 level, outside of any function scope. */
27418 rs6000_set_current_function (tree fndecl)
27420 tree old_tree = (rs6000_previous_fndecl
27421 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl)
27424 tree new_tree = (fndecl
27425 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
27428 if (TARGET_DEBUG_TARGET)
27430 bool print_final = false;
27431 fprintf (stderr, "\n==================== rs6000_set_current_function");
27434 fprintf (stderr, ", fndecl %s (%p)",
27435 (DECL_NAME (fndecl)
27436 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
27437 : "<unknown>"), (void *)fndecl);
27439 if (rs6000_previous_fndecl)
27440 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
27442 fprintf (stderr, "\n");
27445 fprintf (stderr, "\nnew fndecl target specific options:\n");
27446 debug_tree (new_tree);
27447 print_final = true;
27452 fprintf (stderr, "\nold fndecl target specific options:\n");
27453 debug_tree (old_tree);
27454 print_final = true;
27458 fprintf (stderr, "--------------------\n");
27461 /* Only change the context if the function changes. This hook is called
27462 several times in the course of compiling a function, and we don't want to
27463 slow things down too much or call target_reinit when it isn't safe. */
27464 if (fndecl && fndecl != rs6000_previous_fndecl)
27466 rs6000_previous_fndecl = fndecl;
27467 if (old_tree == new_tree)
27472 cl_target_option_restore (&global_options,
27473 TREE_TARGET_OPTION (new_tree));
27479 struct cl_target_option *def
27480 = TREE_TARGET_OPTION (target_option_current_node);
27482 cl_target_option_restore (&global_options, def);
27489 /* Save the current options */
27492 rs6000_function_specific_save (struct cl_target_option *ptr)
27494 ptr->rs6000_target_flags_explicit = target_flags_explicit;
27497 /* Restore the current options */
27500 rs6000_function_specific_restore (struct cl_target_option *ptr)
27502 target_flags_explicit = ptr->rs6000_target_flags_explicit;
27503 (void) rs6000_option_override_internal (false);
27506 /* Print the current options */
27509 rs6000_function_specific_print (FILE *file, int indent,
27510 struct cl_target_option *ptr)
27513 int flags = ptr->x_target_flags;
27514 unsigned bu_mask = ptr->x_rs6000_builtin_mask;
27516 /* Print the various mask options. */
27517 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
27518 if ((flags & rs6000_opt_masks[i].mask) != 0)
27520 flags &= ~ rs6000_opt_masks[i].mask;
27521 fprintf (file, "%*s-m%s%s\n", indent, "",
27522 rs6000_opt_masks[i].invert ? "no-" : "",
27523 rs6000_opt_masks[i].name);
27526 /* Print the various options that are variables. */
27527 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
27529 size_t j = rs6000_opt_vars[i].target_offset;
27530 if (((signed char *) ptr)[j])
27531 fprintf (file, "%*s-m%s\n", indent, "",
27532 rs6000_opt_vars[i].name);
27535 /* Print the various builtin flags. */
27536 fprintf (file, "%*sbuiltin mask = 0x%x\n", indent, "", bu_mask);
27537 for (i = 0; i < ARRAY_SIZE (rs6000_builtin_mask_names); i++)
27538 if ((bu_mask & rs6000_builtin_mask_names[i].mask) != 0)
27540 fprintf (file, "%*s%s builtins supported\n", indent, "",
27541 rs6000_builtin_mask_names[i].name);
27546 /* Hook to determine if one function can safely inline another. */
27549 rs6000_can_inline_p (tree caller, tree callee)
27552 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
27553 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
27555 /* If callee has no option attributes, then it is ok to inline. */
27559 /* If caller has no option attributes, but callee does then it is not ok to
27561 else if (!caller_tree)
27566 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
27567 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
27569 /* Callee's options should a subset of the caller's, i.e. a vsx function
27570 can inline an altivec function but a non-vsx function can't inline a
27572 if ((caller_opts->x_target_flags & callee_opts->x_target_flags)
27573 == callee_opts->x_target_flags)
27577 if (TARGET_DEBUG_TARGET)
27578 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
27579 (DECL_NAME (caller)
27580 ? IDENTIFIER_POINTER (DECL_NAME (caller))
27582 (DECL_NAME (callee)
27583 ? IDENTIFIER_POINTER (DECL_NAME (callee))
27585 (ret ? "can" : "cannot"));
27590 /* Allocate a stack temp and fixup the address so it meets the particular
27591 memory requirements (either offetable or REG+REG addressing). */
27594 rs6000_allocate_stack_temp (enum machine_mode mode,
27595 bool offsettable_p,
27598 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
27599 rtx addr = XEXP (stack, 0);
27600 int strict_p = (reload_in_progress || reload_completed);
27602 if (!legitimate_indirect_address_p (addr, strict_p))
27605 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p))
27606 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
27608 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
27609 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
27615 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
27616 to such a form to deal with memory reference instructions like STFIWX that
27617 only take reg+reg addressing. */
27620 rs6000_address_for_fpconvert (rtx x)
27622 int strict_p = (reload_in_progress || reload_completed);
27625 gcc_assert (MEM_P (x));
27626 addr = XEXP (x, 0);
27627 if (! legitimate_indirect_address_p (addr, strict_p)
27628 && ! legitimate_indexed_address_p (addr, strict_p))
27630 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
27632 rtx reg = XEXP (addr, 0);
27633 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
27634 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
27635 gcc_assert (REG_P (reg));
27636 emit_insn (gen_add3_insn (reg, reg, size_rtx));
27639 else if (GET_CODE (addr) == PRE_MODIFY)
27641 rtx reg = XEXP (addr, 0);
27642 rtx expr = XEXP (addr, 1);
27643 gcc_assert (REG_P (reg));
27644 gcc_assert (GET_CODE (expr) == PLUS);
27645 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
27649 x = replace_equiv_address (x, copy_addr_to_reg (addr));
27655 /* Given a memory reference, if it is not in the form for altivec memory
27656 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
27657 convert to the altivec format. */
27660 rs6000_address_for_altivec (rtx x)
27662 gcc_assert (MEM_P (x));
27663 if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
27665 rtx addr = XEXP (x, 0);
27666 int strict_p = (reload_in_progress || reload_completed);
27668 if (!legitimate_indexed_address_p (addr, strict_p)
27669 && !legitimate_indirect_address_p (addr, strict_p))
27670 addr = copy_to_mode_reg (Pmode, addr);
27672 addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
27673 x = change_address (x, GET_MODE (x), addr);
27679 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
27681 On the RS/6000, all integer constants are acceptable, most won't be valid
27682 for particular insns, though. Only easy FP constants are acceptable. */
27685 rs6000_legitimate_constant_p (enum machine_mode mode, rtx x)
27687 if (rs6000_tls_referenced_p (x))
27690 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
27691 || GET_MODE (x) == VOIDmode
27692 || (TARGET_POWERPC64 && mode == DImode)
27693 || easy_fp_constant (x, mode)
27694 || easy_vector_constant (x, mode));
27698 /* A function pointer under AIX is a pointer to a data area whose first word
27699 contains the actual address of the function, whose second word contains a
27700 pointer to its TOC, and whose third word contains a value to place in the
27701 static chain register (r11). Note that if we load the static chain, our
27702 "trampoline" need not have any executable code. */
27705 rs6000_call_indirect_aix (rtx value, rtx func_desc, rtx flag)
27711 rtx stack_toc_offset;
27713 rtx func_toc_offset;
27715 rtx func_sc_offset;
27718 rtx (*call_func) (rtx, rtx, rtx, rtx);
27719 rtx (*call_value_func) (rtx, rtx, rtx, rtx, rtx);
27721 stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
27722 toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
27724 /* Load up address of the actual function. */
27725 func_desc = force_reg (Pmode, func_desc);
27726 func_addr = gen_reg_rtx (Pmode);
27727 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
27732 stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_32BIT);
27733 func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_32BIT);
27734 func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_32BIT);
27735 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
27737 call_func = gen_call_indirect_aix32bit;
27738 call_value_func = gen_call_value_indirect_aix32bit;
27742 call_func = gen_call_indirect_aix32bit_nor11;
27743 call_value_func = gen_call_value_indirect_aix32bit_nor11;
27748 stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_64BIT);
27749 func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_64BIT);
27750 func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_64BIT);
27751 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
27753 call_func = gen_call_indirect_aix64bit;
27754 call_value_func = gen_call_value_indirect_aix64bit;
27758 call_func = gen_call_indirect_aix64bit_nor11;
27759 call_value_func = gen_call_value_indirect_aix64bit_nor11;
27763 /* Reserved spot to store the TOC. */
27764 stack_toc_mem = gen_frame_mem (Pmode,
27765 gen_rtx_PLUS (Pmode,
27767 stack_toc_offset));
27770 gcc_assert (cfun->machine);
27772 /* Can we optimize saving the TOC in the prologue or do we need to do it at
27774 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
27775 cfun->machine->save_toc_in_prologue = true;
27779 MEM_VOLATILE_P (stack_toc_mem) = 1;
27780 emit_move_insn (stack_toc_mem, toc_reg);
27783 /* Calculate the address to load the TOC of the called function. We don't
27784 actually load this until the split after reload. */
27785 func_toc_mem = gen_rtx_MEM (Pmode,
27786 gen_rtx_PLUS (Pmode,
27790 /* If we have a static chain, load it up. */
27791 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS)
27793 func_sc_mem = gen_rtx_MEM (Pmode,
27794 gen_rtx_PLUS (Pmode,
27798 sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
27799 emit_move_insn (sc_reg, func_sc_mem);
27802 /* Create the call. */
27804 insn = call_value_func (value, func_addr, flag, func_toc_mem,
27807 insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem);
27809 emit_call_insn (insn);
27812 /* Return whether we need to always update the saved TOC pointer when we update
27813 the stack pointer. */
27816 rs6000_save_toc_in_prologue_p (void)
27818 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
27821 #ifdef HAVE_GAS_HIDDEN
27822 # define USE_HIDDEN_LINKONCE 1
27824 # define USE_HIDDEN_LINKONCE 0
27827 /* Fills in the label name that should be used for a 476 link stack thunk. */
27830 get_ppc476_thunk_name (char name[32])
27832 gcc_assert (TARGET_LINK_STACK);
27834 if (USE_HIDDEN_LINKONCE)
27835 sprintf (name, "__ppc476.get_thunk");
27837 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
27840 /* This function emits the simple thunk routine that is used to preserve
27841 the link stack on the 476 cpu. */
27844 rs6000_code_end (void)
27849 if (!TARGET_LINK_STACK)
27852 get_ppc476_thunk_name (name);
27854 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
27855 build_function_type_list (void_type_node, NULL_TREE));
27856 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
27857 NULL_TREE, void_type_node);
27858 TREE_PUBLIC (decl) = 1;
27859 TREE_STATIC (decl) = 1;
27861 if (USE_HIDDEN_LINKONCE)
27863 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
27864 targetm.asm_out.unique_section (decl, 0);
27865 switch_to_section (get_named_section (decl, NULL, 0));
27866 DECL_WEAK (decl) = 1;
27867 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
27868 targetm.asm_out.globalize_label (asm_out_file, name);
27869 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
27870 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
27874 switch_to_section (text_section);
27875 ASM_OUTPUT_LABEL (asm_out_file, name);
27878 DECL_INITIAL (decl) = make_node (BLOCK);
27879 current_function_decl = decl;
27880 init_function_start (decl);
27881 first_function_block_is_cold = false;
27882 /* Make sure unwind info is emitted for the thunk if needed. */
27883 final_start_function (emit_barrier (), asm_out_file, 1);
27885 fputs ("\tblr\n", asm_out_file);
27887 final_end_function ();
27888 init_insn_lengths ();
27889 free_after_compilation (cfun);
27891 current_function_decl = NULL;
27894 struct gcc_target targetm = TARGET_INITIALIZER;
27896 #include "gt-rs6000.h"