1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2014 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
35 #include "stringpool.h"
36 #include "stor-layout.h"
38 #include "print-tree.h"
41 #include "insn-codes.h"
53 #include "dominance.h"
59 #include "cfgcleanup.h"
60 #include "basic-block.h"
61 #include "diagnostic-core.h"
66 #include "target-def.h"
67 #include "common/common-target.h"
68 #include "langhooks.h"
71 #include "sched-int.h"
72 #include "hash-table.h"
73 #include "tree-ssa-alias.h"
74 #include "internal-fn.h"
75 #include "gimple-fold.h"
77 #include "gimple-expr.h"
81 #include "gimple-iterator.h"
82 #include "gimple-walk.h"
85 #include "tm-constrs.h"
88 #include "tree-vectorizer.h"
91 #include "plugin-api.h"
94 #include "target-globals.h"
97 #include "tree-pass.h"
100 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
103 #include "gstab.h" /* for N_SLINE */
106 #ifndef TARGET_NO_PROTOTYPE
107 #define TARGET_NO_PROTOTYPE 0
110 #define min(A,B) ((A) < (B) ? (A) : (B))
111 #define max(A,B) ((A) > (B) ? (A) : (B))
113 /* Structure used to define the rs6000 stack */
114 typedef struct rs6000_stack {
115 int reload_completed; /* stack info won't change from here on */
116 int first_gp_reg_save; /* first callee saved GP register used */
117 int first_fp_reg_save; /* first callee saved FP register used */
118 int first_altivec_reg_save; /* first callee saved AltiVec register used */
119 int lr_save_p; /* true if the link reg needs to be saved */
120 int cr_save_p; /* true if the CR reg needs to be saved */
121 unsigned int vrsave_mask; /* mask of vec registers to save */
122 int push_p; /* true if we need to allocate stack space */
123 int calls_p; /* true if the function makes any calls */
124 int world_save_p; /* true if we're saving *everything*:
125 r13-r31, cr, f14-f31, vrsave, v20-v31 */
126 enum rs6000_abi abi; /* which ABI to use */
127 int gp_save_offset; /* offset to save GP regs from initial SP */
128 int fp_save_offset; /* offset to save FP regs from initial SP */
129 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
130 int lr_save_offset; /* offset to save LR from initial SP */
131 int cr_save_offset; /* offset to save CR from initial SP */
132 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
133 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
134 int varargs_save_offset; /* offset to save the varargs registers */
135 int ehrd_offset; /* offset to EH return data */
136 int ehcr_offset; /* offset to EH CR field data */
137 int reg_size; /* register size (4 or 8) */
138 HOST_WIDE_INT vars_size; /* variable save area size */
139 int parm_size; /* outgoing parameter size */
140 int save_size; /* save area size */
141 int fixed_size; /* fixed size of stack frame */
142 int gp_size; /* size of saved GP registers */
143 int fp_size; /* size of saved FP registers */
144 int altivec_size; /* size of saved AltiVec registers */
145 int cr_size; /* size to hold CR if not in save_size */
146 int vrsave_size; /* size to hold VRSAVE if not in save_size */
147 int altivec_padding_size; /* size of altivec alignment padding if
149 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
150 int spe_padding_size;
151 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
152 int spe_64bit_regs_used;
156 /* A C structure for machine-specific, per-function data.
157 This is added to the cfun structure. */
158 typedef struct GTY(()) machine_function
160 /* Whether the instruction chain has been scanned already. */
161 int insn_chain_scanned_p;
162 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
163 int ra_needs_full_frame;
164 /* Flags if __builtin_return_address (0) was used. */
166 /* Cache lr_save_p after expansion of builtin_eh_return. */
168 /* Whether we need to save the TOC to the reserved stack location in the
169 function prologue. */
170 bool save_toc_in_prologue;
171 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
172 varargs save area. */
173 HOST_WIDE_INT varargs_save_offset;
174 /* Temporary stack slot to use for SDmode copies. This slot is
175 64-bits wide and is allocated early enough so that the offset
176 does not overflow the 16-bit load/store offset field. */
177 rtx sdmode_stack_slot;
178 /* Flag if r2 setup is needed with ELFv2 ABI. */
179 bool r2_setup_needed;
182 /* Support targetm.vectorize.builtin_mask_for_load. */
183 static GTY(()) tree altivec_builtin_mask_for_load;
185 /* Set to nonzero once AIX common-mode calls have been defined. */
186 static GTY(()) int common_mode_defined;
188 /* Label number of label created for -mrelocatable, to call to so we can
189 get the address of the GOT section */
190 static int rs6000_pic_labelno;
193 /* Counter for labels which are to be placed in .fixup. */
194 int fixuplabelno = 0;
197 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
200 /* Specify the machine mode that pointers have. After generation of rtl, the
201 compiler makes no further distinction between pointers and any other objects
202 of this machine mode. The type is unsigned since not all things that
203 include rs6000.h also include machmode.h. */
204 unsigned rs6000_pmode;
206 /* Width in bits of a pointer. */
207 unsigned rs6000_pointer_size;
209 #ifdef HAVE_AS_GNU_ATTRIBUTE
210 /* Flag whether floating point values have been passed/returned. */
211 static bool rs6000_passes_float;
212 /* Flag whether vector values have been passed/returned. */
213 static bool rs6000_passes_vector;
214 /* Flag whether small (<= 8 byte) structures have been returned. */
215 static bool rs6000_returns_struct;
218 /* Value is TRUE if register/mode pair is acceptable. */
219 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
221 /* Maximum number of registers needed for a given register class and mode. */
222 unsigned char rs6000_class_max_nregs[NUM_MACHINE_MODES][LIM_REG_CLASSES];
224 /* How many registers are needed for a given register and mode. */
225 unsigned char rs6000_hard_regno_nregs[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
227 /* Map register number to register class. */
228 enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
230 static int dbg_cost_ctrl;
232 /* Built in types. */
233 tree rs6000_builtin_types[RS6000_BTI_MAX];
234 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
236 /* Flag to say the TOC is initialized */
238 char toc_label_name[10];
240 /* Cached value of rs6000_variable_issue. This is cached in
241 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
242 static short cached_can_issue_more;
244 static GTY(()) section *read_only_data_section;
245 static GTY(()) section *private_data_section;
246 static GTY(()) section *tls_data_section;
247 static GTY(()) section *tls_private_data_section;
248 static GTY(()) section *read_only_private_data_section;
249 static GTY(()) section *sdata2_section;
250 static GTY(()) section *toc_section;
252 struct builtin_description
254 const HOST_WIDE_INT mask;
255 const enum insn_code icode;
256 const char *const name;
257 const enum rs6000_builtins code;
260 /* Describe the vector unit used for modes. */
261 enum rs6000_vector rs6000_vector_unit[NUM_MACHINE_MODES];
262 enum rs6000_vector rs6000_vector_mem[NUM_MACHINE_MODES];
264 /* Register classes for various constraints that are based on the target
266 enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
268 /* Describe the alignment of a vector. */
269 int rs6000_vector_align[NUM_MACHINE_MODES];
271 /* Map selected modes to types for builtins. */
272 static GTY(()) tree builtin_mode_to_type[MAX_MACHINE_MODE][2];
274 /* What modes to automatically generate reciprocal divide estimate (fre) and
275 reciprocal sqrt (frsqrte) for. */
276 unsigned char rs6000_recip_bits[MAX_MACHINE_MODE];
278 /* Masks to determine which reciprocal esitmate instructions to generate
280 enum rs6000_recip_mask {
281 RECIP_SF_DIV = 0x001, /* Use divide estimate */
282 RECIP_DF_DIV = 0x002,
283 RECIP_V4SF_DIV = 0x004,
284 RECIP_V2DF_DIV = 0x008,
286 RECIP_SF_RSQRT = 0x010, /* Use reciprocal sqrt estimate. */
287 RECIP_DF_RSQRT = 0x020,
288 RECIP_V4SF_RSQRT = 0x040,
289 RECIP_V2DF_RSQRT = 0x080,
291 /* Various combination of flags for -mrecip=xxx. */
293 RECIP_ALL = (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
294 | RECIP_V2DF_DIV | RECIP_SF_RSQRT | RECIP_DF_RSQRT
295 | RECIP_V4SF_RSQRT | RECIP_V2DF_RSQRT),
297 RECIP_HIGH_PRECISION = RECIP_ALL,
299 /* On low precision machines like the power5, don't enable double precision
300 reciprocal square root estimate, since it isn't accurate enough. */
301 RECIP_LOW_PRECISION = (RECIP_ALL & ~(RECIP_DF_RSQRT | RECIP_V2DF_RSQRT))
304 /* -mrecip options. */
307 const char *string; /* option name */
308 unsigned int mask; /* mask bits to set */
309 } recip_options[] = {
310 { "all", RECIP_ALL },
311 { "none", RECIP_NONE },
312 { "div", (RECIP_SF_DIV | RECIP_DF_DIV | RECIP_V4SF_DIV
314 { "divf", (RECIP_SF_DIV | RECIP_V4SF_DIV) },
315 { "divd", (RECIP_DF_DIV | RECIP_V2DF_DIV) },
316 { "rsqrt", (RECIP_SF_RSQRT | RECIP_DF_RSQRT | RECIP_V4SF_RSQRT
317 | RECIP_V2DF_RSQRT) },
318 { "rsqrtf", (RECIP_SF_RSQRT | RECIP_V4SF_RSQRT) },
319 { "rsqrtd", (RECIP_DF_RSQRT | RECIP_V2DF_RSQRT) },
322 /* Pointer to function (in rs6000-c.c) that can define or undefine target
323 macros that have changed. Languages that don't support the preprocessor
324 don't link in rs6000-c.c, so we can't call it directly. */
325 void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
327 /* Simplfy register classes into simpler classifications. We assume
328 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
329 check for standard register classes (gpr/floating/altivec/vsx) and
330 floating/vector classes (float/altivec/vsx). */
332 enum rs6000_reg_type {
345 /* Map register class to register type. */
346 static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES];
348 /* First/last register type for the 'normal' register types (i.e. general
349 purpose, floating point, altivec, and VSX registers). */
350 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
352 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
355 /* Register classes we care about in secondary reload or go if legitimate
356 address. We only need to worry about GPR, FPR, and Altivec registers here,
357 along an ANY field that is the OR of the 3 register classes. */
359 enum rs6000_reload_reg_type {
360 RELOAD_REG_GPR, /* General purpose registers. */
361 RELOAD_REG_FPR, /* Traditional floating point regs. */
362 RELOAD_REG_VMX, /* Altivec (VMX) registers. */
363 RELOAD_REG_ANY, /* OR of GPR, FPR, Altivec masks. */
367 /* For setting up register classes, loop through the 3 register classes mapping
368 into real registers, and skip the ANY class, which is just an OR of the
370 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
371 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
373 /* Map reload register type to a register in the register class. */
374 struct reload_reg_map_type {
375 const char *name; /* Register class name. */
376 int reg; /* Register in the register class. */
379 static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = {
380 { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */
381 { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */
382 { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */
383 { "Any", -1 }, /* RELOAD_REG_ANY. */
386 /* Mask bits for each register class, indexed per mode. Historically the
387 compiler has been more restrictive which types can do PRE_MODIFY instead of
388 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
389 typedef unsigned char addr_mask_type;
391 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
392 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
393 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
394 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
395 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
396 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
397 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
399 /* Register type masks based on the type, of valid addressing modes. */
400 struct rs6000_reg_addr {
401 enum insn_code reload_load; /* INSN to reload for loading. */
402 enum insn_code reload_store; /* INSN to reload for storing. */
403 enum insn_code reload_fpr_gpr; /* INSN to move from FPR to GPR. */
404 enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */
405 enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */
406 addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */
407 bool scalar_in_vmx_p; /* Scalar value can go in VMX. */
410 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
412 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
414 mode_supports_pre_incdec_p (machine_mode mode)
416 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
420 /* Helper function to say whether a mode supports PRE_MODIFY. */
422 mode_supports_pre_modify_p (machine_mode mode)
424 return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
429 /* Target cpu costs. */
431 struct processor_costs {
432 const int mulsi; /* cost of SImode multiplication. */
433 const int mulsi_const; /* cost of SImode multiplication by constant. */
434 const int mulsi_const9; /* cost of SImode mult by short constant. */
435 const int muldi; /* cost of DImode multiplication. */
436 const int divsi; /* cost of SImode division. */
437 const int divdi; /* cost of DImode division. */
438 const int fp; /* cost of simple SFmode and DFmode insns. */
439 const int dmul; /* cost of DFmode multiplication (and fmadd). */
440 const int sdiv; /* cost of SFmode division (fdivs). */
441 const int ddiv; /* cost of DFmode division (fdiv). */
442 const int cache_line_size; /* cache line size in bytes. */
443 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
444 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
445 const int simultaneous_prefetches; /* number of parallel prefetch
449 const struct processor_costs *rs6000_cost;
451 /* Processor costs (relative to an add) */
453 /* Instruction size costs on 32bit processors. */
455 struct processor_costs size32_cost = {
456 COSTS_N_INSNS (1), /* mulsi */
457 COSTS_N_INSNS (1), /* mulsi_const */
458 COSTS_N_INSNS (1), /* mulsi_const9 */
459 COSTS_N_INSNS (1), /* muldi */
460 COSTS_N_INSNS (1), /* divsi */
461 COSTS_N_INSNS (1), /* divdi */
462 COSTS_N_INSNS (1), /* fp */
463 COSTS_N_INSNS (1), /* dmul */
464 COSTS_N_INSNS (1), /* sdiv */
465 COSTS_N_INSNS (1), /* ddiv */
472 /* Instruction size costs on 64bit processors. */
474 struct processor_costs size64_cost = {
475 COSTS_N_INSNS (1), /* mulsi */
476 COSTS_N_INSNS (1), /* mulsi_const */
477 COSTS_N_INSNS (1), /* mulsi_const9 */
478 COSTS_N_INSNS (1), /* muldi */
479 COSTS_N_INSNS (1), /* divsi */
480 COSTS_N_INSNS (1), /* divdi */
481 COSTS_N_INSNS (1), /* fp */
482 COSTS_N_INSNS (1), /* dmul */
483 COSTS_N_INSNS (1), /* sdiv */
484 COSTS_N_INSNS (1), /* ddiv */
491 /* Instruction costs on RS64A processors. */
493 struct processor_costs rs64a_cost = {
494 COSTS_N_INSNS (20), /* mulsi */
495 COSTS_N_INSNS (12), /* mulsi_const */
496 COSTS_N_INSNS (8), /* mulsi_const9 */
497 COSTS_N_INSNS (34), /* muldi */
498 COSTS_N_INSNS (65), /* divsi */
499 COSTS_N_INSNS (67), /* divdi */
500 COSTS_N_INSNS (4), /* fp */
501 COSTS_N_INSNS (4), /* dmul */
502 COSTS_N_INSNS (31), /* sdiv */
503 COSTS_N_INSNS (31), /* ddiv */
504 128, /* cache line size */
510 /* Instruction costs on MPCCORE processors. */
512 struct processor_costs mpccore_cost = {
513 COSTS_N_INSNS (2), /* mulsi */
514 COSTS_N_INSNS (2), /* mulsi_const */
515 COSTS_N_INSNS (2), /* mulsi_const9 */
516 COSTS_N_INSNS (2), /* muldi */
517 COSTS_N_INSNS (6), /* divsi */
518 COSTS_N_INSNS (6), /* divdi */
519 COSTS_N_INSNS (4), /* fp */
520 COSTS_N_INSNS (5), /* dmul */
521 COSTS_N_INSNS (10), /* sdiv */
522 COSTS_N_INSNS (17), /* ddiv */
523 32, /* cache line size */
529 /* Instruction costs on PPC403 processors. */
531 struct processor_costs ppc403_cost = {
532 COSTS_N_INSNS (4), /* mulsi */
533 COSTS_N_INSNS (4), /* mulsi_const */
534 COSTS_N_INSNS (4), /* mulsi_const9 */
535 COSTS_N_INSNS (4), /* muldi */
536 COSTS_N_INSNS (33), /* divsi */
537 COSTS_N_INSNS (33), /* divdi */
538 COSTS_N_INSNS (11), /* fp */
539 COSTS_N_INSNS (11), /* dmul */
540 COSTS_N_INSNS (11), /* sdiv */
541 COSTS_N_INSNS (11), /* ddiv */
542 32, /* cache line size */
548 /* Instruction costs on PPC405 processors. */
550 struct processor_costs ppc405_cost = {
551 COSTS_N_INSNS (5), /* mulsi */
552 COSTS_N_INSNS (4), /* mulsi_const */
553 COSTS_N_INSNS (3), /* mulsi_const9 */
554 COSTS_N_INSNS (5), /* muldi */
555 COSTS_N_INSNS (35), /* divsi */
556 COSTS_N_INSNS (35), /* divdi */
557 COSTS_N_INSNS (11), /* fp */
558 COSTS_N_INSNS (11), /* dmul */
559 COSTS_N_INSNS (11), /* sdiv */
560 COSTS_N_INSNS (11), /* ddiv */
561 32, /* cache line size */
567 /* Instruction costs on PPC440 processors. */
569 struct processor_costs ppc440_cost = {
570 COSTS_N_INSNS (3), /* mulsi */
571 COSTS_N_INSNS (2), /* mulsi_const */
572 COSTS_N_INSNS (2), /* mulsi_const9 */
573 COSTS_N_INSNS (3), /* muldi */
574 COSTS_N_INSNS (34), /* divsi */
575 COSTS_N_INSNS (34), /* divdi */
576 COSTS_N_INSNS (5), /* fp */
577 COSTS_N_INSNS (5), /* dmul */
578 COSTS_N_INSNS (19), /* sdiv */
579 COSTS_N_INSNS (33), /* ddiv */
580 32, /* cache line size */
586 /* Instruction costs on PPC476 processors. */
588 struct processor_costs ppc476_cost = {
589 COSTS_N_INSNS (4), /* mulsi */
590 COSTS_N_INSNS (4), /* mulsi_const */
591 COSTS_N_INSNS (4), /* mulsi_const9 */
592 COSTS_N_INSNS (4), /* muldi */
593 COSTS_N_INSNS (11), /* divsi */
594 COSTS_N_INSNS (11), /* divdi */
595 COSTS_N_INSNS (6), /* fp */
596 COSTS_N_INSNS (6), /* dmul */
597 COSTS_N_INSNS (19), /* sdiv */
598 COSTS_N_INSNS (33), /* ddiv */
599 32, /* l1 cache line size */
605 /* Instruction costs on PPC601 processors. */
607 struct processor_costs ppc601_cost = {
608 COSTS_N_INSNS (5), /* mulsi */
609 COSTS_N_INSNS (5), /* mulsi_const */
610 COSTS_N_INSNS (5), /* mulsi_const9 */
611 COSTS_N_INSNS (5), /* muldi */
612 COSTS_N_INSNS (36), /* divsi */
613 COSTS_N_INSNS (36), /* divdi */
614 COSTS_N_INSNS (4), /* fp */
615 COSTS_N_INSNS (5), /* dmul */
616 COSTS_N_INSNS (17), /* sdiv */
617 COSTS_N_INSNS (31), /* ddiv */
618 32, /* cache line size */
624 /* Instruction costs on PPC603 processors. */
626 struct processor_costs ppc603_cost = {
627 COSTS_N_INSNS (5), /* mulsi */
628 COSTS_N_INSNS (3), /* mulsi_const */
629 COSTS_N_INSNS (2), /* mulsi_const9 */
630 COSTS_N_INSNS (5), /* muldi */
631 COSTS_N_INSNS (37), /* divsi */
632 COSTS_N_INSNS (37), /* divdi */
633 COSTS_N_INSNS (3), /* fp */
634 COSTS_N_INSNS (4), /* dmul */
635 COSTS_N_INSNS (18), /* sdiv */
636 COSTS_N_INSNS (33), /* ddiv */
637 32, /* cache line size */
643 /* Instruction costs on PPC604 processors. */
645 struct processor_costs ppc604_cost = {
646 COSTS_N_INSNS (4), /* mulsi */
647 COSTS_N_INSNS (4), /* mulsi_const */
648 COSTS_N_INSNS (4), /* mulsi_const9 */
649 COSTS_N_INSNS (4), /* muldi */
650 COSTS_N_INSNS (20), /* divsi */
651 COSTS_N_INSNS (20), /* divdi */
652 COSTS_N_INSNS (3), /* fp */
653 COSTS_N_INSNS (3), /* dmul */
654 COSTS_N_INSNS (18), /* sdiv */
655 COSTS_N_INSNS (32), /* ddiv */
656 32, /* cache line size */
662 /* Instruction costs on PPC604e processors. */
664 struct processor_costs ppc604e_cost = {
665 COSTS_N_INSNS (2), /* mulsi */
666 COSTS_N_INSNS (2), /* mulsi_const */
667 COSTS_N_INSNS (2), /* mulsi_const9 */
668 COSTS_N_INSNS (2), /* muldi */
669 COSTS_N_INSNS (20), /* divsi */
670 COSTS_N_INSNS (20), /* divdi */
671 COSTS_N_INSNS (3), /* fp */
672 COSTS_N_INSNS (3), /* dmul */
673 COSTS_N_INSNS (18), /* sdiv */
674 COSTS_N_INSNS (32), /* ddiv */
675 32, /* cache line size */
681 /* Instruction costs on PPC620 processors. */
683 struct processor_costs ppc620_cost = {
684 COSTS_N_INSNS (5), /* mulsi */
685 COSTS_N_INSNS (4), /* mulsi_const */
686 COSTS_N_INSNS (3), /* mulsi_const9 */
687 COSTS_N_INSNS (7), /* muldi */
688 COSTS_N_INSNS (21), /* divsi */
689 COSTS_N_INSNS (37), /* divdi */
690 COSTS_N_INSNS (3), /* fp */
691 COSTS_N_INSNS (3), /* dmul */
692 COSTS_N_INSNS (18), /* sdiv */
693 COSTS_N_INSNS (32), /* ddiv */
694 128, /* cache line size */
700 /* Instruction costs on PPC630 processors. */
702 struct processor_costs ppc630_cost = {
703 COSTS_N_INSNS (5), /* mulsi */
704 COSTS_N_INSNS (4), /* mulsi_const */
705 COSTS_N_INSNS (3), /* mulsi_const9 */
706 COSTS_N_INSNS (7), /* muldi */
707 COSTS_N_INSNS (21), /* divsi */
708 COSTS_N_INSNS (37), /* divdi */
709 COSTS_N_INSNS (3), /* fp */
710 COSTS_N_INSNS (3), /* dmul */
711 COSTS_N_INSNS (17), /* sdiv */
712 COSTS_N_INSNS (21), /* ddiv */
713 128, /* cache line size */
719 /* Instruction costs on Cell processor. */
720 /* COSTS_N_INSNS (1) ~ one add. */
722 struct processor_costs ppccell_cost = {
723 COSTS_N_INSNS (9/2)+2, /* mulsi */
724 COSTS_N_INSNS (6/2), /* mulsi_const */
725 COSTS_N_INSNS (6/2), /* mulsi_const9 */
726 COSTS_N_INSNS (15/2)+2, /* muldi */
727 COSTS_N_INSNS (38/2), /* divsi */
728 COSTS_N_INSNS (70/2), /* divdi */
729 COSTS_N_INSNS (10/2), /* fp */
730 COSTS_N_INSNS (10/2), /* dmul */
731 COSTS_N_INSNS (74/2), /* sdiv */
732 COSTS_N_INSNS (74/2), /* ddiv */
733 128, /* cache line size */
739 /* Instruction costs on PPC750 and PPC7400 processors. */
741 struct processor_costs ppc750_cost = {
742 COSTS_N_INSNS (5), /* mulsi */
743 COSTS_N_INSNS (3), /* mulsi_const */
744 COSTS_N_INSNS (2), /* mulsi_const9 */
745 COSTS_N_INSNS (5), /* muldi */
746 COSTS_N_INSNS (17), /* divsi */
747 COSTS_N_INSNS (17), /* divdi */
748 COSTS_N_INSNS (3), /* fp */
749 COSTS_N_INSNS (3), /* dmul */
750 COSTS_N_INSNS (17), /* sdiv */
751 COSTS_N_INSNS (31), /* ddiv */
752 32, /* cache line size */
758 /* Instruction costs on PPC7450 processors. */
760 struct processor_costs ppc7450_cost = {
761 COSTS_N_INSNS (4), /* mulsi */
762 COSTS_N_INSNS (3), /* mulsi_const */
763 COSTS_N_INSNS (3), /* mulsi_const9 */
764 COSTS_N_INSNS (4), /* muldi */
765 COSTS_N_INSNS (23), /* divsi */
766 COSTS_N_INSNS (23), /* divdi */
767 COSTS_N_INSNS (5), /* fp */
768 COSTS_N_INSNS (5), /* dmul */
769 COSTS_N_INSNS (21), /* sdiv */
770 COSTS_N_INSNS (35), /* ddiv */
771 32, /* cache line size */
777 /* Instruction costs on PPC8540 processors. */
779 struct processor_costs ppc8540_cost = {
780 COSTS_N_INSNS (4), /* mulsi */
781 COSTS_N_INSNS (4), /* mulsi_const */
782 COSTS_N_INSNS (4), /* mulsi_const9 */
783 COSTS_N_INSNS (4), /* muldi */
784 COSTS_N_INSNS (19), /* divsi */
785 COSTS_N_INSNS (19), /* divdi */
786 COSTS_N_INSNS (4), /* fp */
787 COSTS_N_INSNS (4), /* dmul */
788 COSTS_N_INSNS (29), /* sdiv */
789 COSTS_N_INSNS (29), /* ddiv */
790 32, /* cache line size */
793 1, /* prefetch streams /*/
796 /* Instruction costs on E300C2 and E300C3 cores. */
798 struct processor_costs ppce300c2c3_cost = {
799 COSTS_N_INSNS (4), /* mulsi */
800 COSTS_N_INSNS (4), /* mulsi_const */
801 COSTS_N_INSNS (4), /* mulsi_const9 */
802 COSTS_N_INSNS (4), /* muldi */
803 COSTS_N_INSNS (19), /* divsi */
804 COSTS_N_INSNS (19), /* divdi */
805 COSTS_N_INSNS (3), /* fp */
806 COSTS_N_INSNS (4), /* dmul */
807 COSTS_N_INSNS (18), /* sdiv */
808 COSTS_N_INSNS (33), /* ddiv */
812 1, /* prefetch streams /*/
815 /* Instruction costs on PPCE500MC processors. */
817 struct processor_costs ppce500mc_cost = {
818 COSTS_N_INSNS (4), /* mulsi */
819 COSTS_N_INSNS (4), /* mulsi_const */
820 COSTS_N_INSNS (4), /* mulsi_const9 */
821 COSTS_N_INSNS (4), /* muldi */
822 COSTS_N_INSNS (14), /* divsi */
823 COSTS_N_INSNS (14), /* divdi */
824 COSTS_N_INSNS (8), /* fp */
825 COSTS_N_INSNS (10), /* dmul */
826 COSTS_N_INSNS (36), /* sdiv */
827 COSTS_N_INSNS (66), /* ddiv */
828 64, /* cache line size */
831 1, /* prefetch streams /*/
834 /* Instruction costs on PPCE500MC64 processors. */
836 struct processor_costs ppce500mc64_cost = {
837 COSTS_N_INSNS (4), /* mulsi */
838 COSTS_N_INSNS (4), /* mulsi_const */
839 COSTS_N_INSNS (4), /* mulsi_const9 */
840 COSTS_N_INSNS (4), /* muldi */
841 COSTS_N_INSNS (14), /* divsi */
842 COSTS_N_INSNS (14), /* divdi */
843 COSTS_N_INSNS (4), /* fp */
844 COSTS_N_INSNS (10), /* dmul */
845 COSTS_N_INSNS (36), /* sdiv */
846 COSTS_N_INSNS (66), /* ddiv */
847 64, /* cache line size */
850 1, /* prefetch streams /*/
853 /* Instruction costs on PPCE5500 processors. */
855 struct processor_costs ppce5500_cost = {
856 COSTS_N_INSNS (5), /* mulsi */
857 COSTS_N_INSNS (5), /* mulsi_const */
858 COSTS_N_INSNS (4), /* mulsi_const9 */
859 COSTS_N_INSNS (5), /* muldi */
860 COSTS_N_INSNS (14), /* divsi */
861 COSTS_N_INSNS (14), /* divdi */
862 COSTS_N_INSNS (7), /* fp */
863 COSTS_N_INSNS (10), /* dmul */
864 COSTS_N_INSNS (36), /* sdiv */
865 COSTS_N_INSNS (66), /* ddiv */
866 64, /* cache line size */
869 1, /* prefetch streams /*/
872 /* Instruction costs on PPCE6500 processors. */
874 struct processor_costs ppce6500_cost = {
875 COSTS_N_INSNS (5), /* mulsi */
876 COSTS_N_INSNS (5), /* mulsi_const */
877 COSTS_N_INSNS (4), /* mulsi_const9 */
878 COSTS_N_INSNS (5), /* muldi */
879 COSTS_N_INSNS (14), /* divsi */
880 COSTS_N_INSNS (14), /* divdi */
881 COSTS_N_INSNS (7), /* fp */
882 COSTS_N_INSNS (10), /* dmul */
883 COSTS_N_INSNS (36), /* sdiv */
884 COSTS_N_INSNS (66), /* ddiv */
885 64, /* cache line size */
888 1, /* prefetch streams /*/
891 /* Instruction costs on AppliedMicro Titan processors. */
893 struct processor_costs titan_cost = {
894 COSTS_N_INSNS (5), /* mulsi */
895 COSTS_N_INSNS (5), /* mulsi_const */
896 COSTS_N_INSNS (5), /* mulsi_const9 */
897 COSTS_N_INSNS (5), /* muldi */
898 COSTS_N_INSNS (18), /* divsi */
899 COSTS_N_INSNS (18), /* divdi */
900 COSTS_N_INSNS (10), /* fp */
901 COSTS_N_INSNS (10), /* dmul */
902 COSTS_N_INSNS (46), /* sdiv */
903 COSTS_N_INSNS (72), /* ddiv */
904 32, /* cache line size */
907 1, /* prefetch streams /*/
910 /* Instruction costs on POWER4 and POWER5 processors. */
912 struct processor_costs power4_cost = {
913 COSTS_N_INSNS (3), /* mulsi */
914 COSTS_N_INSNS (2), /* mulsi_const */
915 COSTS_N_INSNS (2), /* mulsi_const9 */
916 COSTS_N_INSNS (4), /* muldi */
917 COSTS_N_INSNS (18), /* divsi */
918 COSTS_N_INSNS (34), /* divdi */
919 COSTS_N_INSNS (3), /* fp */
920 COSTS_N_INSNS (3), /* dmul */
921 COSTS_N_INSNS (17), /* sdiv */
922 COSTS_N_INSNS (17), /* ddiv */
923 128, /* cache line size */
926 8, /* prefetch streams /*/
929 /* Instruction costs on POWER6 processors. */
931 struct processor_costs power6_cost = {
932 COSTS_N_INSNS (8), /* mulsi */
933 COSTS_N_INSNS (8), /* mulsi_const */
934 COSTS_N_INSNS (8), /* mulsi_const9 */
935 COSTS_N_INSNS (8), /* muldi */
936 COSTS_N_INSNS (22), /* divsi */
937 COSTS_N_INSNS (28), /* divdi */
938 COSTS_N_INSNS (3), /* fp */
939 COSTS_N_INSNS (3), /* dmul */
940 COSTS_N_INSNS (13), /* sdiv */
941 COSTS_N_INSNS (16), /* ddiv */
942 128, /* cache line size */
945 16, /* prefetch streams */
948 /* Instruction costs on POWER7 processors. */
950 struct processor_costs power7_cost = {
951 COSTS_N_INSNS (2), /* mulsi */
952 COSTS_N_INSNS (2), /* mulsi_const */
953 COSTS_N_INSNS (2), /* mulsi_const9 */
954 COSTS_N_INSNS (2), /* muldi */
955 COSTS_N_INSNS (18), /* divsi */
956 COSTS_N_INSNS (34), /* divdi */
957 COSTS_N_INSNS (3), /* fp */
958 COSTS_N_INSNS (3), /* dmul */
959 COSTS_N_INSNS (13), /* sdiv */
960 COSTS_N_INSNS (16), /* ddiv */
961 128, /* cache line size */
964 12, /* prefetch streams */
967 /* Instruction costs on POWER8 processors. */
969 struct processor_costs power8_cost = {
970 COSTS_N_INSNS (3), /* mulsi */
971 COSTS_N_INSNS (3), /* mulsi_const */
972 COSTS_N_INSNS (3), /* mulsi_const9 */
973 COSTS_N_INSNS (3), /* muldi */
974 COSTS_N_INSNS (19), /* divsi */
975 COSTS_N_INSNS (35), /* divdi */
976 COSTS_N_INSNS (3), /* fp */
977 COSTS_N_INSNS (3), /* dmul */
978 COSTS_N_INSNS (14), /* sdiv */
979 COSTS_N_INSNS (17), /* ddiv */
980 128, /* cache line size */
983 12, /* prefetch streams */
986 /* Instruction costs on POWER A2 processors. */
988 struct processor_costs ppca2_cost = {
989 COSTS_N_INSNS (16), /* mulsi */
990 COSTS_N_INSNS (16), /* mulsi_const */
991 COSTS_N_INSNS (16), /* mulsi_const9 */
992 COSTS_N_INSNS (16), /* muldi */
993 COSTS_N_INSNS (22), /* divsi */
994 COSTS_N_INSNS (28), /* divdi */
995 COSTS_N_INSNS (3), /* fp */
996 COSTS_N_INSNS (3), /* dmul */
997 COSTS_N_INSNS (59), /* sdiv */
998 COSTS_N_INSNS (72), /* ddiv */
1001 2048, /* l2 cache */
1002 16, /* prefetch streams */
1006 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1007 #undef RS6000_BUILTIN_1
1008 #undef RS6000_BUILTIN_2
1009 #undef RS6000_BUILTIN_3
1010 #undef RS6000_BUILTIN_A
1011 #undef RS6000_BUILTIN_D
1012 #undef RS6000_BUILTIN_E
1013 #undef RS6000_BUILTIN_H
1014 #undef RS6000_BUILTIN_P
1015 #undef RS6000_BUILTIN_Q
1016 #undef RS6000_BUILTIN_S
1017 #undef RS6000_BUILTIN_X
1019 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1020 { NAME, ICODE, MASK, ATTR },
1022 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1023 { NAME, ICODE, MASK, ATTR },
1025 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1026 { NAME, ICODE, MASK, ATTR },
1028 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1029 { NAME, ICODE, MASK, ATTR },
1031 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1032 { NAME, ICODE, MASK, ATTR },
1034 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
1035 { NAME, ICODE, MASK, ATTR },
1037 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1038 { NAME, ICODE, MASK, ATTR },
1040 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1041 { NAME, ICODE, MASK, ATTR },
1043 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1044 { NAME, ICODE, MASK, ATTR },
1046 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1047 { NAME, ICODE, MASK, ATTR },
1049 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1050 { NAME, ICODE, MASK, ATTR },
1052 struct rs6000_builtin_info_type {
1054 const enum insn_code icode;
1055 const HOST_WIDE_INT mask;
1056 const unsigned attr;
1059 static const struct rs6000_builtin_info_type rs6000_builtin_info[] =
1061 #include "rs6000-builtin.def"
1064 #undef RS6000_BUILTIN_1
1065 #undef RS6000_BUILTIN_2
1066 #undef RS6000_BUILTIN_3
1067 #undef RS6000_BUILTIN_A
1068 #undef RS6000_BUILTIN_D
1069 #undef RS6000_BUILTIN_E
1070 #undef RS6000_BUILTIN_H
1071 #undef RS6000_BUILTIN_P
1072 #undef RS6000_BUILTIN_Q
1073 #undef RS6000_BUILTIN_S
1074 #undef RS6000_BUILTIN_X
1076 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1077 static tree (*rs6000_veclib_handler) (tree, tree, tree);
1080 static bool rs6000_debug_legitimate_address_p (machine_mode, rtx, bool);
1081 static bool spe_func_has_64bit_regs_p (void);
1082 static struct machine_function * rs6000_init_machine_status (void);
1083 static int rs6000_ra_ever_killed (void);
1084 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
1085 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
1086 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
1087 static tree rs6000_builtin_vectorized_libmass (tree, tree, tree);
1088 static void rs6000_emit_set_long_const (rtx, HOST_WIDE_INT);
1089 static int rs6000_memory_move_cost (machine_mode, reg_class_t, bool);
1090 static bool rs6000_debug_rtx_costs (rtx, int, int, int, int *, bool);
1091 static int rs6000_debug_address_cost (rtx, machine_mode, addr_space_t,
1093 static int rs6000_debug_adjust_cost (rtx_insn *, rtx, rtx_insn *, int);
1094 static bool is_microcoded_insn (rtx_insn *);
1095 static bool is_nonpipeline_insn (rtx_insn *);
1096 static bool is_cracked_insn (rtx_insn *);
1097 static bool is_load_insn (rtx, rtx *);
1098 static bool is_store_insn (rtx, rtx *);
1099 static bool set_to_load_agen (rtx_insn *,rtx_insn *);
1100 static bool insn_terminates_group_p (rtx_insn *, enum group_termination);
1101 static bool insn_must_be_first_in_group (rtx_insn *);
1102 static bool insn_must_be_last_in_group (rtx_insn *);
1103 static void altivec_init_builtins (void);
1104 static tree builtin_function_type (machine_mode, machine_mode,
1105 machine_mode, machine_mode,
1106 enum rs6000_builtins, const char *name);
1107 static void rs6000_common_init_builtins (void);
1108 static void paired_init_builtins (void);
1109 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
1110 static void spe_init_builtins (void);
1111 static void htm_init_builtins (void);
1112 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
1113 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
1114 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
1115 static rs6000_stack_t *rs6000_stack_info (void);
1116 static void is_altivec_return_reg (rtx, void *);
1117 int easy_vector_constant (rtx, machine_mode);
1118 static rtx rs6000_debug_legitimize_address (rtx, rtx, machine_mode);
1119 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
1120 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree,
1123 static void macho_branch_islands (void);
1125 static rtx rs6000_legitimize_reload_address (rtx, machine_mode, int, int,
1127 static rtx rs6000_debug_legitimize_reload_address (rtx, machine_mode, int,
1129 static bool rs6000_mode_dependent_address (const_rtx);
1130 static bool rs6000_debug_mode_dependent_address (const_rtx);
1131 static enum reg_class rs6000_secondary_reload_class (enum reg_class,
1133 static enum reg_class rs6000_debug_secondary_reload_class (enum reg_class,
1136 static enum reg_class rs6000_preferred_reload_class (rtx, enum reg_class);
1137 static enum reg_class rs6000_debug_preferred_reload_class (rtx,
1139 static bool rs6000_secondary_memory_needed (enum reg_class, enum reg_class,
1141 static bool rs6000_debug_secondary_memory_needed (enum reg_class,
1144 static bool rs6000_cannot_change_mode_class (machine_mode,
1147 static bool rs6000_debug_cannot_change_mode_class (machine_mode,
1150 static bool rs6000_save_toc_in_prologue_p (void);
1152 rtx (*rs6000_legitimize_reload_address_ptr) (rtx, machine_mode, int, int,
1154 = rs6000_legitimize_reload_address;
1156 static bool (*rs6000_mode_dependent_address_ptr) (const_rtx)
1157 = rs6000_mode_dependent_address;
1159 enum reg_class (*rs6000_secondary_reload_class_ptr) (enum reg_class,
1161 = rs6000_secondary_reload_class;
1163 enum reg_class (*rs6000_preferred_reload_class_ptr) (rtx, enum reg_class)
1164 = rs6000_preferred_reload_class;
1166 bool (*rs6000_secondary_memory_needed_ptr) (enum reg_class, enum reg_class,
1168 = rs6000_secondary_memory_needed;
1170 bool (*rs6000_cannot_change_mode_class_ptr) (machine_mode,
1173 = rs6000_cannot_change_mode_class;
1175 const int INSN_NOT_AVAILABLE = -1;
1177 static void rs6000_print_isa_options (FILE *, int, const char *,
1179 static void rs6000_print_builtin_options (FILE *, int, const char *,
1182 static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
1183 static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
1184 enum rs6000_reg_type,
1186 secondary_reload_info *,
1188 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
1190 /* Hash table stuff for keeping track of TOC entries. */
1192 struct GTY((for_user)) toc_hash_struct
1194 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1195 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1197 machine_mode key_mode;
1201 struct toc_hasher : ggc_hasher<toc_hash_struct *>
1203 static hashval_t hash (toc_hash_struct *);
1204 static bool equal (toc_hash_struct *, toc_hash_struct *);
1207 static GTY (()) hash_table<toc_hasher> *toc_hash_table;
1209 /* Hash table to keep track of the argument types for builtin functions. */
1211 struct GTY((for_user)) builtin_hash_struct
1214 machine_mode mode[4]; /* return value + 3 arguments. */
1215 unsigned char uns_p[4]; /* and whether the types are unsigned. */
1218 struct builtin_hasher : ggc_hasher<builtin_hash_struct *>
1220 static hashval_t hash (builtin_hash_struct *);
1221 static bool equal (builtin_hash_struct *, builtin_hash_struct *);
1224 static GTY (()) hash_table<builtin_hasher> *builtin_hash_table;
1227 /* Default register names. */
1228 char rs6000_reg_names[][8] =
1230 "0", "1", "2", "3", "4", "5", "6", "7",
1231 "8", "9", "10", "11", "12", "13", "14", "15",
1232 "16", "17", "18", "19", "20", "21", "22", "23",
1233 "24", "25", "26", "27", "28", "29", "30", "31",
1234 "0", "1", "2", "3", "4", "5", "6", "7",
1235 "8", "9", "10", "11", "12", "13", "14", "15",
1236 "16", "17", "18", "19", "20", "21", "22", "23",
1237 "24", "25", "26", "27", "28", "29", "30", "31",
1238 "mq", "lr", "ctr","ap",
1239 "0", "1", "2", "3", "4", "5", "6", "7",
1241 /* AltiVec registers. */
1242 "0", "1", "2", "3", "4", "5", "6", "7",
1243 "8", "9", "10", "11", "12", "13", "14", "15",
1244 "16", "17", "18", "19", "20", "21", "22", "23",
1245 "24", "25", "26", "27", "28", "29", "30", "31",
1247 /* SPE registers. */
1248 "spe_acc", "spefscr",
1249 /* Soft frame pointer. */
1251 /* HTM SPR registers. */
1252 "tfhar", "tfiar", "texasr",
1253 /* SPE High registers. */
1254 "0", "1", "2", "3", "4", "5", "6", "7",
1255 "8", "9", "10", "11", "12", "13", "14", "15",
1256 "16", "17", "18", "19", "20", "21", "22", "23",
1257 "24", "25", "26", "27", "28", "29", "30", "31"
1260 #ifdef TARGET_REGNAMES
1261 static const char alt_reg_names[][8] =
1263 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1264 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1265 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1266 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1267 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1268 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1269 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1270 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1271 "mq", "lr", "ctr", "ap",
1272 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1274 /* AltiVec registers. */
1275 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1276 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1277 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1278 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1280 /* SPE registers. */
1281 "spe_acc", "spefscr",
1282 /* Soft frame pointer. */
1284 /* HTM SPR registers. */
1285 "tfhar", "tfiar", "texasr",
1286 /* SPE High registers. */
1287 "%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7",
1288 "%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15",
1289 "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
1290 "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
1294 /* Table of valid machine attributes. */
1296 static const struct attribute_spec rs6000_attribute_table[] =
1298 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1299 affects_type_identity } */
1300 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute,
1302 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1304 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute,
1306 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1308 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute,
1310 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1311 SUBTARGET_ATTRIBUTE_TABLE,
1313 { NULL, 0, 0, false, false, false, NULL, false }
1316 #ifndef TARGET_PROFILE_KERNEL
1317 #define TARGET_PROFILE_KERNEL 0
1320 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1321 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1323 /* Initialize the GCC target structure. */
1324 #undef TARGET_ATTRIBUTE_TABLE
1325 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1326 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1327 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1328 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1329 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1331 #undef TARGET_ASM_ALIGNED_DI_OP
1332 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1334 /* Default unaligned ops are only provided for ELF. Find the ops needed
1335 for non-ELF systems. */
1336 #ifndef OBJECT_FORMAT_ELF
1338 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1340 #undef TARGET_ASM_UNALIGNED_HI_OP
1341 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1342 #undef TARGET_ASM_UNALIGNED_SI_OP
1343 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1344 #undef TARGET_ASM_UNALIGNED_DI_OP
1345 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1348 #undef TARGET_ASM_UNALIGNED_HI_OP
1349 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1350 #undef TARGET_ASM_UNALIGNED_SI_OP
1351 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1352 #undef TARGET_ASM_UNALIGNED_DI_OP
1353 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1354 #undef TARGET_ASM_ALIGNED_DI_OP
1355 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1359 /* This hook deals with fixups for relocatable code and DI-mode objects
1361 #undef TARGET_ASM_INTEGER
1362 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1364 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1365 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1366 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1369 #undef TARGET_SET_UP_BY_PROLOGUE
1370 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1372 #undef TARGET_HAVE_TLS
1373 #define TARGET_HAVE_TLS HAVE_AS_TLS
1375 #undef TARGET_CANNOT_FORCE_CONST_MEM
1376 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1378 #undef TARGET_DELEGITIMIZE_ADDRESS
1379 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1381 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1382 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1384 #undef TARGET_ASM_FUNCTION_PROLOGUE
1385 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1386 #undef TARGET_ASM_FUNCTION_EPILOGUE
1387 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1389 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1390 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1392 #undef TARGET_LEGITIMIZE_ADDRESS
1393 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1395 #undef TARGET_SCHED_VARIABLE_ISSUE
1396 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1398 #undef TARGET_SCHED_ISSUE_RATE
1399 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1400 #undef TARGET_SCHED_ADJUST_COST
1401 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1402 #undef TARGET_SCHED_ADJUST_PRIORITY
1403 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1404 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1405 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1406 #undef TARGET_SCHED_INIT
1407 #define TARGET_SCHED_INIT rs6000_sched_init
1408 #undef TARGET_SCHED_FINISH
1409 #define TARGET_SCHED_FINISH rs6000_sched_finish
1410 #undef TARGET_SCHED_REORDER
1411 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1412 #undef TARGET_SCHED_REORDER2
1413 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1415 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1416 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1418 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1419 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1421 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1422 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1423 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1424 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1425 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1426 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1427 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1428 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1430 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1431 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1432 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1433 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1434 rs6000_builtin_support_vector_misalignment
1435 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1436 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1437 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1438 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1439 rs6000_builtin_vectorization_cost
1440 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1441 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1442 rs6000_preferred_simd_mode
1443 #undef TARGET_VECTORIZE_INIT_COST
1444 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1445 #undef TARGET_VECTORIZE_ADD_STMT_COST
1446 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1447 #undef TARGET_VECTORIZE_FINISH_COST
1448 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1449 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1450 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1452 #undef TARGET_INIT_BUILTINS
1453 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1454 #undef TARGET_BUILTIN_DECL
1455 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1457 #undef TARGET_EXPAND_BUILTIN
1458 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1460 #undef TARGET_MANGLE_TYPE
1461 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1463 #undef TARGET_INIT_LIBFUNCS
1464 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1467 #undef TARGET_BINDS_LOCAL_P
1468 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1471 #undef TARGET_MS_BITFIELD_LAYOUT_P
1472 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1474 #undef TARGET_ASM_OUTPUT_MI_THUNK
1475 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1477 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1478 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1480 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1481 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1483 #undef TARGET_REGISTER_MOVE_COST
1484 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1485 #undef TARGET_MEMORY_MOVE_COST
1486 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1487 #undef TARGET_RTX_COSTS
1488 #define TARGET_RTX_COSTS rs6000_rtx_costs
1489 #undef TARGET_ADDRESS_COST
1490 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1492 #undef TARGET_DWARF_REGISTER_SPAN
1493 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1495 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1496 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1498 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1499 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1501 /* On rs6000, function arguments are promoted, as are function return
1503 #undef TARGET_PROMOTE_FUNCTION_MODE
1504 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1506 #undef TARGET_RETURN_IN_MEMORY
1507 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1509 #undef TARGET_RETURN_IN_MSB
1510 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1512 #undef TARGET_SETUP_INCOMING_VARARGS
1513 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1515 /* Always strict argument naming on rs6000. */
1516 #undef TARGET_STRICT_ARGUMENT_NAMING
1517 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1518 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1519 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1520 #undef TARGET_SPLIT_COMPLEX_ARG
1521 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1522 #undef TARGET_MUST_PASS_IN_STACK
1523 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1524 #undef TARGET_PASS_BY_REFERENCE
1525 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1526 #undef TARGET_ARG_PARTIAL_BYTES
1527 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1528 #undef TARGET_FUNCTION_ARG_ADVANCE
1529 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1530 #undef TARGET_FUNCTION_ARG
1531 #define TARGET_FUNCTION_ARG rs6000_function_arg
1532 #undef TARGET_FUNCTION_ARG_BOUNDARY
1533 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1535 #undef TARGET_BUILD_BUILTIN_VA_LIST
1536 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1538 #undef TARGET_EXPAND_BUILTIN_VA_START
1539 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1541 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1542 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1544 #undef TARGET_EH_RETURN_FILTER_MODE
1545 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1547 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1548 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1550 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1551 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1553 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1554 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1556 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1557 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1559 #undef TARGET_MD_ASM_CLOBBERS
1560 #define TARGET_MD_ASM_CLOBBERS rs6000_md_asm_clobbers
1562 #undef TARGET_OPTION_OVERRIDE
1563 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1565 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1566 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1567 rs6000_builtin_vectorized_function
1570 #undef TARGET_STACK_PROTECT_FAIL
1571 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1574 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1575 The PowerPC architecture requires only weak consistency among
1576 processors--that is, memory accesses between processors need not be
1577 sequentially consistent and memory accesses among processors can occur
1578 in any order. The ability to order memory accesses weakly provides
1579 opportunities for more efficient use of the system bus. Unless a
1580 dependency exists, the 604e allows read operations to precede store
1582 #undef TARGET_RELAXED_ORDERING
1583 #define TARGET_RELAXED_ORDERING true
1586 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1587 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1590 /* Use a 32-bit anchor range. This leads to sequences like:
1592 addis tmp,anchor,high
1595 where tmp itself acts as an anchor, and can be shared between
1596 accesses to the same 64k page. */
1597 #undef TARGET_MIN_ANCHOR_OFFSET
1598 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1599 #undef TARGET_MAX_ANCHOR_OFFSET
1600 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1601 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1602 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1603 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1604 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1606 #undef TARGET_BUILTIN_RECIPROCAL
1607 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1609 #undef TARGET_EXPAND_TO_RTL_HOOK
1610 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1612 #undef TARGET_INSTANTIATE_DECLS
1613 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1615 #undef TARGET_SECONDARY_RELOAD
1616 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1618 #undef TARGET_LEGITIMATE_ADDRESS_P
1619 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1621 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1622 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1625 #define TARGET_LRA_P rs6000_lra_p
1627 #undef TARGET_CAN_ELIMINATE
1628 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1630 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1631 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1633 #undef TARGET_TRAMPOLINE_INIT
1634 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1636 #undef TARGET_FUNCTION_VALUE
1637 #define TARGET_FUNCTION_VALUE rs6000_function_value
1639 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1640 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1642 #undef TARGET_OPTION_SAVE
1643 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1645 #undef TARGET_OPTION_RESTORE
1646 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1648 #undef TARGET_OPTION_PRINT
1649 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1651 #undef TARGET_CAN_INLINE_P
1652 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1654 #undef TARGET_SET_CURRENT_FUNCTION
1655 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1657 #undef TARGET_LEGITIMATE_CONSTANT_P
1658 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1660 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1661 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1663 #undef TARGET_CAN_USE_DOLOOP_P
1664 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1666 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1667 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1670 /* Processor table. */
1673 const char *const name; /* Canonical processor name. */
1674 const enum processor_type processor; /* Processor type enum value. */
1675 const HOST_WIDE_INT target_enable; /* Target flags to enable. */
1678 static struct rs6000_ptt const processor_target_table[] =
1680 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1681 #include "rs6000-cpus.def"
1685 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1689 rs6000_cpu_name_lookup (const char *name)
1695 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
1696 if (! strcmp (name, processor_target_table[i].name))
1704 /* Return number of consecutive hard regs needed starting at reg REGNO
1705 to hold something of mode MODE.
1706 This is ordinarily the length in words of a value of mode MODE
1707 but can be less for certain modes in special long registers.
1709 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1710 scalar instructions. The upper 32 bits are only available to the
1713 POWER and PowerPC GPRs hold 32 bits worth;
1714 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1717 rs6000_hard_regno_nregs_internal (int regno, machine_mode mode)
1719 unsigned HOST_WIDE_INT reg_size;
1721 /* TF/TD modes are special in that they always take 2 registers. */
1722 if (FP_REGNO_P (regno))
1723 reg_size = ((VECTOR_MEM_VSX_P (mode) && mode != TDmode && mode != TFmode)
1724 ? UNITS_PER_VSX_WORD
1725 : UNITS_PER_FP_WORD);
1727 else if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1728 reg_size = UNITS_PER_SPE_WORD;
1730 else if (ALTIVEC_REGNO_P (regno))
1731 reg_size = UNITS_PER_ALTIVEC_WORD;
1733 /* The value returned for SCmode in the E500 double case is 2 for
1734 ABI compatibility; storing an SCmode value in a single register
1735 would require function_arg and rs6000_spe_function_arg to handle
1736 SCmode so as to pass the value correctly in a pair of
1738 else if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode
1739 && !DECIMAL_FLOAT_MODE_P (mode) && SPE_SIMD_REGNO_P (regno))
1740 reg_size = UNITS_PER_FP_WORD;
1743 reg_size = UNITS_PER_WORD;
1745 return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size;
1748 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1751 rs6000_hard_regno_mode_ok (int regno, machine_mode mode)
1753 int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
1755 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1756 register combinations, and use PTImode where we need to deal with quad
1757 word memory operations. Don't allow quad words in the argument or frame
1758 pointer registers, just registers 0..31. */
1759 if (mode == PTImode)
1760 return (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
1761 && IN_RANGE (last_regno, FIRST_GPR_REGNO, LAST_GPR_REGNO)
1762 && ((regno & 1) == 0));
1764 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1765 implementations. Don't allow an item to be split between a FP register
1766 and an Altivec register. Allow TImode in all VSX registers if the user
1768 if (TARGET_VSX && VSX_REGNO_P (regno)
1769 && (VECTOR_MEM_VSX_P (mode)
1770 || reg_addr[mode].scalar_in_vmx_p
1771 || (TARGET_VSX_TIMODE && mode == TImode)
1772 || (TARGET_VADDUQM && mode == V1TImode)))
1774 if (FP_REGNO_P (regno))
1775 return FP_REGNO_P (last_regno);
1777 if (ALTIVEC_REGNO_P (regno))
1779 if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p)
1782 return ALTIVEC_REGNO_P (last_regno);
1786 /* The GPRs can hold any mode, but values bigger than one register
1787 cannot go past R31. */
1788 if (INT_REGNO_P (regno))
1789 return INT_REGNO_P (last_regno);
1791 /* The float registers (except for VSX vector modes) can only hold floating
1792 modes and DImode. */
1793 if (FP_REGNO_P (regno))
1795 if (SCALAR_FLOAT_MODE_P (mode)
1796 && (mode != TDmode || (regno % 2) == 0)
1797 && FP_REGNO_P (last_regno))
1800 if (GET_MODE_CLASS (mode) == MODE_INT
1801 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1804 if (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1805 && PAIRED_VECTOR_MODE (mode))
1811 /* The CR register can only hold CC modes. */
1812 if (CR_REGNO_P (regno))
1813 return GET_MODE_CLASS (mode) == MODE_CC;
1815 if (CA_REGNO_P (regno))
1816 return mode == Pmode || mode == SImode;
1818 /* AltiVec only in AldyVec registers. */
1819 if (ALTIVEC_REGNO_P (regno))
1820 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
1821 || mode == V1TImode);
1823 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1824 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1827 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1828 and it must be able to fit within the register set. */
1830 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1833 /* Print interesting facts about registers. */
1835 rs6000_debug_reg_print (int first_regno, int last_regno, const char *reg_name)
1839 for (r = first_regno; r <= last_regno; ++r)
1841 const char *comma = "";
1844 if (first_regno == last_regno)
1845 fprintf (stderr, "%s:\t", reg_name);
1847 fprintf (stderr, "%s%d:\t", reg_name, r - first_regno);
1850 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1851 if (rs6000_hard_regno_mode_ok_p[m][r] && rs6000_hard_regno_nregs[m][r])
1855 fprintf (stderr, ",\n\t");
1860 if (rs6000_hard_regno_nregs[m][r] > 1)
1861 len += fprintf (stderr, "%s%s/%d", comma, GET_MODE_NAME (m),
1862 rs6000_hard_regno_nregs[m][r]);
1864 len += fprintf (stderr, "%s%s", comma, GET_MODE_NAME (m));
1869 if (call_used_regs[r])
1873 fprintf (stderr, ",\n\t");
1878 len += fprintf (stderr, "%s%s", comma, "call-used");
1886 fprintf (stderr, ",\n\t");
1891 len += fprintf (stderr, "%s%s", comma, "fixed");
1897 fprintf (stderr, ",\n\t");
1901 len += fprintf (stderr, "%sreg-class = %s", comma,
1902 reg_class_names[(int)rs6000_regno_regclass[r]]);
1907 fprintf (stderr, ",\n\t");
1911 fprintf (stderr, "%sregno = %d\n", comma, r);
1916 rs6000_debug_vector_unit (enum rs6000_vector v)
1922 case VECTOR_NONE: ret = "none"; break;
1923 case VECTOR_ALTIVEC: ret = "altivec"; break;
1924 case VECTOR_VSX: ret = "vsx"; break;
1925 case VECTOR_P8_VECTOR: ret = "p8_vector"; break;
1926 case VECTOR_PAIRED: ret = "paired"; break;
1927 case VECTOR_SPE: ret = "spe"; break;
1928 case VECTOR_OTHER: ret = "other"; break;
1929 default: ret = "unknown"; break;
1935 /* Inner function printing just the address mask for a particular reload
1937 DEBUG_FUNCTION char *
1938 rs6000_debug_addr_mask (addr_mask_type mask, bool keep_spaces)
1943 if ((mask & RELOAD_REG_VALID) != 0)
1945 else if (keep_spaces)
1948 if ((mask & RELOAD_REG_MULTIPLE) != 0)
1950 else if (keep_spaces)
1953 if ((mask & RELOAD_REG_INDEXED) != 0)
1955 else if (keep_spaces)
1958 if ((mask & RELOAD_REG_OFFSET) != 0)
1960 else if (keep_spaces)
1963 if ((mask & RELOAD_REG_PRE_INCDEC) != 0)
1965 else if (keep_spaces)
1968 if ((mask & RELOAD_REG_PRE_MODIFY) != 0)
1970 else if (keep_spaces)
1973 if ((mask & RELOAD_REG_AND_M16) != 0)
1975 else if (keep_spaces)
1983 /* Print the address masks in a human readble fashion. */
1985 rs6000_debug_print_mode (ssize_t m)
1989 fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
1990 for (rc = 0; rc < N_RELOAD_REG; rc++)
1991 fprintf (stderr, " %s: %s", reload_reg_map[rc].name,
1992 rs6000_debug_addr_mask (reg_addr[m].addr_mask[rc], true));
1994 if (rs6000_vector_unit[m] != VECTOR_NONE
1995 || rs6000_vector_mem[m] != VECTOR_NONE
1996 || (reg_addr[m].reload_store != CODE_FOR_nothing)
1997 || (reg_addr[m].reload_load != CODE_FOR_nothing)
1998 || reg_addr[m].scalar_in_vmx_p)
2001 " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c Upper=%c",
2002 rs6000_debug_vector_unit (rs6000_vector_unit[m]),
2003 rs6000_debug_vector_unit (rs6000_vector_mem[m]),
2004 (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*',
2005 (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*',
2006 (reg_addr[m].scalar_in_vmx_p) ? 'y' : 'n');
2009 fputs ("\n", stderr);
2012 #define DEBUG_FMT_ID "%-32s= "
2013 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2014 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2015 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2017 /* Print various interesting information with -mdebug=reg. */
2019 rs6000_debug_reg_global (void)
2021 static const char *const tf[2] = { "false", "true" };
2022 const char *nl = (const char *)0;
2025 char costly_num[20];
2027 char flags_buffer[40];
2028 const char *costly_str;
2029 const char *nop_str;
2030 const char *trace_str;
2031 const char *abi_str;
2032 const char *cmodel_str;
2033 struct cl_target_option cl_opts;
2035 /* Modes we want tieable information on. */
2036 static const machine_mode print_tieable_modes[] = {
2072 /* Virtual regs we are interested in. */
2073 const static struct {
2074 int regno; /* register number. */
2075 const char *name; /* register name. */
2076 } virtual_regs[] = {
2077 { STACK_POINTER_REGNUM, "stack pointer:" },
2078 { TOC_REGNUM, "toc: " },
2079 { STATIC_CHAIN_REGNUM, "static chain: " },
2080 { RS6000_PIC_OFFSET_TABLE_REGNUM, "pic offset: " },
2081 { HARD_FRAME_POINTER_REGNUM, "hard frame: " },
2082 { ARG_POINTER_REGNUM, "arg pointer: " },
2083 { FRAME_POINTER_REGNUM, "frame pointer:" },
2084 { FIRST_PSEUDO_REGISTER, "first pseudo: " },
2085 { FIRST_VIRTUAL_REGISTER, "first virtual:" },
2086 { VIRTUAL_INCOMING_ARGS_REGNUM, "incoming_args:" },
2087 { VIRTUAL_STACK_VARS_REGNUM, "stack_vars: " },
2088 { VIRTUAL_STACK_DYNAMIC_REGNUM, "stack_dynamic:" },
2089 { VIRTUAL_OUTGOING_ARGS_REGNUM, "outgoing_args:" },
2090 { VIRTUAL_CFA_REGNUM, "cfa (frame): " },
2091 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM, "stack boundry:" },
2092 { LAST_VIRTUAL_REGISTER, "last virtual: " },
2095 fputs ("\nHard register information:\n", stderr);
2096 rs6000_debug_reg_print (FIRST_GPR_REGNO, LAST_GPR_REGNO, "gr");
2097 rs6000_debug_reg_print (FIRST_FPR_REGNO, LAST_FPR_REGNO, "fp");
2098 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO,
2101 rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
2102 rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
2103 rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
2104 rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
2105 rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
2106 rs6000_debug_reg_print (VSCR_REGNO, VSCR_REGNO, "vscr");
2107 rs6000_debug_reg_print (SPE_ACC_REGNO, SPE_ACC_REGNO, "spe_a");
2108 rs6000_debug_reg_print (SPEFSCR_REGNO, SPEFSCR_REGNO, "spe_f");
2110 fputs ("\nVirtual/stack/frame registers:\n", stderr);
2111 for (v = 0; v < ARRAY_SIZE (virtual_regs); v++)
2112 fprintf (stderr, "%s regno = %3d\n", virtual_regs[v].name, virtual_regs[v].regno);
2116 "d reg_class = %s\n"
2117 "f reg_class = %s\n"
2118 "v reg_class = %s\n"
2119 "wa reg_class = %s\n"
2120 "wd reg_class = %s\n"
2121 "wf reg_class = %s\n"
2122 "wg reg_class = %s\n"
2123 "wh reg_class = %s\n"
2124 "wi reg_class = %s\n"
2125 "wj reg_class = %s\n"
2126 "wk reg_class = %s\n"
2127 "wl reg_class = %s\n"
2128 "wm reg_class = %s\n"
2129 "wr reg_class = %s\n"
2130 "ws reg_class = %s\n"
2131 "wt reg_class = %s\n"
2132 "wu reg_class = %s\n"
2133 "wv reg_class = %s\n"
2134 "ww reg_class = %s\n"
2135 "wx reg_class = %s\n"
2136 "wy reg_class = %s\n"
2137 "wz reg_class = %s\n"
2139 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_d]],
2140 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_f]],
2141 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_v]],
2142 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
2143 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]],
2144 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]],
2145 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]],
2146 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]],
2147 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]],
2148 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]],
2149 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]],
2150 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]],
2151 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]],
2152 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
2153 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ws]],
2154 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
2155 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wu]],
2156 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wv]],
2157 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
2158 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
2159 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
2160 reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]]);
2163 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2164 rs6000_debug_print_mode (m);
2166 fputs ("\n", stderr);
2168 for (m1 = 0; m1 < ARRAY_SIZE (print_tieable_modes); m1++)
2170 machine_mode mode1 = print_tieable_modes[m1];
2171 bool first_time = true;
2173 nl = (const char *)0;
2174 for (m2 = 0; m2 < ARRAY_SIZE (print_tieable_modes); m2++)
2176 machine_mode mode2 = print_tieable_modes[m2];
2177 if (mode1 != mode2 && MODES_TIEABLE_P (mode1, mode2))
2181 fprintf (stderr, "Tieable modes %s:", GET_MODE_NAME (mode1));
2186 fprintf (stderr, " %s", GET_MODE_NAME (mode2));
2191 fputs ("\n", stderr);
2197 if (rs6000_recip_control)
2199 fprintf (stderr, "\nReciprocal mask = 0x%x\n", rs6000_recip_control);
2201 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2202 if (rs6000_recip_bits[m])
2205 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2207 (RS6000_RECIP_AUTO_RE_P (m)
2209 : (RS6000_RECIP_HAVE_RE_P (m) ? "have" : "none")),
2210 (RS6000_RECIP_AUTO_RSQRTE_P (m)
2212 : (RS6000_RECIP_HAVE_RSQRTE_P (m) ? "have" : "none")));
2215 fputs ("\n", stderr);
2218 if (rs6000_cpu_index >= 0)
2220 const char *name = processor_target_table[rs6000_cpu_index].name;
2222 = processor_target_table[rs6000_cpu_index].target_enable;
2224 sprintf (flags_buffer, "-mcpu=%s flags", name);
2225 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2228 fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
2230 if (rs6000_tune_index >= 0)
2232 const char *name = processor_target_table[rs6000_tune_index].name;
2234 = processor_target_table[rs6000_tune_index].target_enable;
2236 sprintf (flags_buffer, "-mtune=%s flags", name);
2237 rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
2240 fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
2242 cl_target_option_save (&cl_opts, &global_options);
2243 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
2246 rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
2247 rs6000_isa_flags_explicit);
2249 rs6000_print_builtin_options (stderr, 0, "rs6000_builtin_mask",
2250 rs6000_builtin_mask);
2252 rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
2254 fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
2255 OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
2257 switch (rs6000_sched_costly_dep)
2259 case max_dep_latency:
2260 costly_str = "max_dep_latency";
2264 costly_str = "no_dep_costly";
2267 case all_deps_costly:
2268 costly_str = "all_deps_costly";
2271 case true_store_to_load_dep_costly:
2272 costly_str = "true_store_to_load_dep_costly";
2275 case store_to_load_dep_costly:
2276 costly_str = "store_to_load_dep_costly";
2280 costly_str = costly_num;
2281 sprintf (costly_num, "%d", (int)rs6000_sched_costly_dep);
2285 fprintf (stderr, DEBUG_FMT_S, "sched_costly_dep", costly_str);
2287 switch (rs6000_sched_insert_nops)
2289 case sched_finish_regroup_exact:
2290 nop_str = "sched_finish_regroup_exact";
2293 case sched_finish_pad_groups:
2294 nop_str = "sched_finish_pad_groups";
2297 case sched_finish_none:
2298 nop_str = "sched_finish_none";
2303 sprintf (nop_num, "%d", (int)rs6000_sched_insert_nops);
2307 fprintf (stderr, DEBUG_FMT_S, "sched_insert_nops", nop_str);
2309 switch (rs6000_sdata)
2316 fprintf (stderr, DEBUG_FMT_S, "sdata", "data");
2320 fprintf (stderr, DEBUG_FMT_S, "sdata", "sysv");
2324 fprintf (stderr, DEBUG_FMT_S, "sdata", "eabi");
2329 switch (rs6000_traceback)
2331 case traceback_default: trace_str = "default"; break;
2332 case traceback_none: trace_str = "none"; break;
2333 case traceback_part: trace_str = "part"; break;
2334 case traceback_full: trace_str = "full"; break;
2335 default: trace_str = "unknown"; break;
2338 fprintf (stderr, DEBUG_FMT_S, "traceback", trace_str);
2340 switch (rs6000_current_cmodel)
2342 case CMODEL_SMALL: cmodel_str = "small"; break;
2343 case CMODEL_MEDIUM: cmodel_str = "medium"; break;
2344 case CMODEL_LARGE: cmodel_str = "large"; break;
2345 default: cmodel_str = "unknown"; break;
2348 fprintf (stderr, DEBUG_FMT_S, "cmodel", cmodel_str);
2350 switch (rs6000_current_abi)
2352 case ABI_NONE: abi_str = "none"; break;
2353 case ABI_AIX: abi_str = "aix"; break;
2354 case ABI_ELFv2: abi_str = "ELFv2"; break;
2355 case ABI_V4: abi_str = "V4"; break;
2356 case ABI_DARWIN: abi_str = "darwin"; break;
2357 default: abi_str = "unknown"; break;
2360 fprintf (stderr, DEBUG_FMT_S, "abi", abi_str);
2362 if (rs6000_altivec_abi)
2363 fprintf (stderr, DEBUG_FMT_S, "altivec_abi", "true");
2366 fprintf (stderr, DEBUG_FMT_S, "spe_abi", "true");
2368 if (rs6000_darwin64_abi)
2369 fprintf (stderr, DEBUG_FMT_S, "darwin64_abi", "true");
2371 if (rs6000_float_gprs)
2372 fprintf (stderr, DEBUG_FMT_S, "float_gprs", "true");
2374 fprintf (stderr, DEBUG_FMT_S, "fprs",
2375 (TARGET_FPRS ? "true" : "false"));
2377 fprintf (stderr, DEBUG_FMT_S, "single_float",
2378 (TARGET_SINGLE_FLOAT ? "true" : "false"));
2380 fprintf (stderr, DEBUG_FMT_S, "double_float",
2381 (TARGET_DOUBLE_FLOAT ? "true" : "false"));
2383 fprintf (stderr, DEBUG_FMT_S, "soft_float",
2384 (TARGET_SOFT_FLOAT ? "true" : "false"));
2386 fprintf (stderr, DEBUG_FMT_S, "e500_single",
2387 (TARGET_E500_SINGLE ? "true" : "false"));
2389 fprintf (stderr, DEBUG_FMT_S, "e500_double",
2390 (TARGET_E500_DOUBLE ? "true" : "false"));
2392 if (TARGET_LINK_STACK)
2393 fprintf (stderr, DEBUG_FMT_S, "link_stack", "true");
2395 if (targetm.lra_p ())
2396 fprintf (stderr, DEBUG_FMT_S, "lra", "true");
2398 if (TARGET_P8_FUSION)
2399 fprintf (stderr, DEBUG_FMT_S, "p8 fusion",
2400 (TARGET_P8_FUSION_SIGN) ? "zero+sign" : "zero");
2402 fprintf (stderr, DEBUG_FMT_S, "plt-format",
2403 TARGET_SECURE_PLT ? "secure" : "bss");
2404 fprintf (stderr, DEBUG_FMT_S, "struct-return",
2405 aix_struct_return ? "aix" : "sysv");
2406 fprintf (stderr, DEBUG_FMT_S, "always_hint", tf[!!rs6000_always_hint]);
2407 fprintf (stderr, DEBUG_FMT_S, "sched_groups", tf[!!rs6000_sched_groups]);
2408 fprintf (stderr, DEBUG_FMT_S, "align_branch",
2409 tf[!!rs6000_align_branch_targets]);
2410 fprintf (stderr, DEBUG_FMT_D, "tls_size", rs6000_tls_size);
2411 fprintf (stderr, DEBUG_FMT_D, "long_double_size",
2412 rs6000_long_double_type_size);
2413 fprintf (stderr, DEBUG_FMT_D, "sched_restricted_insns_priority",
2414 (int)rs6000_sched_restricted_insns_priority);
2415 fprintf (stderr, DEBUG_FMT_D, "Number of standard builtins",
2417 fprintf (stderr, DEBUG_FMT_D, "Number of rs6000 builtins",
2418 (int)RS6000_BUILTIN_COUNT);
2421 fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit scalar element",
2422 (int)VECTOR_ELEMENT_SCALAR_64BIT);
2426 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2427 legitimate address support to figure out the appropriate addressing to
2431 rs6000_setup_reg_addr_masks (void)
2433 ssize_t rc, reg, m, nregs;
2434 addr_mask_type any_addr_mask, addr_mask;
2436 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2438 machine_mode m2 = (machine_mode)m;
2440 /* SDmode is special in that we want to access it only via REG+REG
2441 addressing on power7 and above, since we want to use the LFIWZX and
2442 STFIWZX instructions to load it. */
2443 bool indexed_only_p = (m == SDmode && TARGET_NO_SDMODE_STACK);
2446 for (rc = FIRST_RELOAD_REG_CLASS; rc <= LAST_RELOAD_REG_CLASS; rc++)
2449 reg = reload_reg_map[rc].reg;
2451 /* Can mode values go in the GPR/FPR/Altivec registers? */
2452 if (reg >= 0 && rs6000_hard_regno_mode_ok_p[m][reg])
2454 nregs = rs6000_hard_regno_nregs[m][reg];
2455 addr_mask |= RELOAD_REG_VALID;
2457 /* Indicate if the mode takes more than 1 physical register. If
2458 it takes a single register, indicate it can do REG+REG
2460 if (nregs > 1 || m == BLKmode)
2461 addr_mask |= RELOAD_REG_MULTIPLE;
2463 addr_mask |= RELOAD_REG_INDEXED;
2465 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2466 addressing. Restrict addressing on SPE for 64-bit types
2467 because of the SUBREG hackery used to address 64-bit floats in
2471 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR)
2472 && GET_MODE_SIZE (m2) <= 8
2473 && !VECTOR_MODE_P (m2)
2474 && !COMPLEX_MODE_P (m2)
2476 && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m2) == 8))
2478 addr_mask |= RELOAD_REG_PRE_INCDEC;
2480 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2481 we don't allow PRE_MODIFY for some multi-register
2486 addr_mask |= RELOAD_REG_PRE_MODIFY;
2490 if (TARGET_POWERPC64)
2491 addr_mask |= RELOAD_REG_PRE_MODIFY;
2497 addr_mask |= RELOAD_REG_PRE_MODIFY;
2503 /* GPR and FPR registers can do REG+OFFSET addressing, except
2504 possibly for SDmode. */
2505 if ((addr_mask != 0) && !indexed_only_p
2506 && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR))
2507 addr_mask |= RELOAD_REG_OFFSET;
2509 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2510 addressing on 128-bit types. */
2511 if (rc == RELOAD_REG_VMX && GET_MODE_SIZE (m2) == 16
2512 && (addr_mask & RELOAD_REG_VALID) != 0)
2513 addr_mask |= RELOAD_REG_AND_M16;
2515 reg_addr[m].addr_mask[rc] = addr_mask;
2516 any_addr_mask |= addr_mask;
2519 reg_addr[m].addr_mask[RELOAD_REG_ANY] = any_addr_mask;
2524 /* Initialize the various global tables that are based on register size. */
2526 rs6000_init_hard_regno_mode_ok (bool global_init_p)
2532 /* Precalculate REGNO_REG_CLASS. */
2533 rs6000_regno_regclass[0] = GENERAL_REGS;
2534 for (r = 1; r < 32; ++r)
2535 rs6000_regno_regclass[r] = BASE_REGS;
2537 for (r = 32; r < 64; ++r)
2538 rs6000_regno_regclass[r] = FLOAT_REGS;
2540 for (r = 64; r < FIRST_PSEUDO_REGISTER; ++r)
2541 rs6000_regno_regclass[r] = NO_REGS;
2543 for (r = FIRST_ALTIVEC_REGNO; r <= LAST_ALTIVEC_REGNO; ++r)
2544 rs6000_regno_regclass[r] = ALTIVEC_REGS;
2546 rs6000_regno_regclass[CR0_REGNO] = CR0_REGS;
2547 for (r = CR1_REGNO; r <= CR7_REGNO; ++r)
2548 rs6000_regno_regclass[r] = CR_REGS;
2550 rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
2551 rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
2552 rs6000_regno_regclass[CA_REGNO] = NO_REGS;
2553 rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
2554 rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
2555 rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;
2556 rs6000_regno_regclass[SPEFSCR_REGNO] = SPEFSCR_REGS;
2557 rs6000_regno_regclass[TFHAR_REGNO] = SPR_REGS;
2558 rs6000_regno_regclass[TFIAR_REGNO] = SPR_REGS;
2559 rs6000_regno_regclass[TEXASR_REGNO] = SPR_REGS;
2560 rs6000_regno_regclass[ARG_POINTER_REGNUM] = BASE_REGS;
2561 rs6000_regno_regclass[FRAME_POINTER_REGNUM] = BASE_REGS;
2563 /* Precalculate register class to simpler reload register class. We don't
2564 need all of the register classes that are combinations of different
2565 classes, just the simple ones that have constraint letters. */
2566 for (c = 0; c < N_REG_CLASSES; c++)
2567 reg_class_to_reg_type[c] = NO_REG_TYPE;
2569 reg_class_to_reg_type[(int)GENERAL_REGS] = GPR_REG_TYPE;
2570 reg_class_to_reg_type[(int)BASE_REGS] = GPR_REG_TYPE;
2571 reg_class_to_reg_type[(int)VSX_REGS] = VSX_REG_TYPE;
2572 reg_class_to_reg_type[(int)VRSAVE_REGS] = SPR_REG_TYPE;
2573 reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
2574 reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
2575 reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
2576 reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
2577 reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
2578 reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
2579 reg_class_to_reg_type[(int)SPE_ACC_REGS] = SPE_ACC_TYPE;
2580 reg_class_to_reg_type[(int)SPEFSCR_REGS] = SPEFSCR_REG_TYPE;
2584 reg_class_to_reg_type[(int)FLOAT_REGS] = VSX_REG_TYPE;
2585 reg_class_to_reg_type[(int)ALTIVEC_REGS] = VSX_REG_TYPE;
2589 reg_class_to_reg_type[(int)FLOAT_REGS] = FPR_REG_TYPE;
2590 reg_class_to_reg_type[(int)ALTIVEC_REGS] = ALTIVEC_REG_TYPE;
2593 /* Precalculate the valid memory formats as well as the vector information,
2594 this must be set up before the rs6000_hard_regno_nregs_internal calls
2596 gcc_assert ((int)VECTOR_NONE == 0);
2597 memset ((void *) &rs6000_vector_unit[0], '\0', sizeof (rs6000_vector_unit));
2598 memset ((void *) &rs6000_vector_mem[0], '\0', sizeof (rs6000_vector_unit));
2600 gcc_assert ((int)CODE_FOR_nothing == 0);
2601 memset ((void *) ®_addr[0], '\0', sizeof (reg_addr));
2603 gcc_assert ((int)NO_REGS == 0);
2604 memset ((void *) &rs6000_constraints[0], '\0', sizeof (rs6000_constraints));
2606 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2607 believes it can use native alignment or still uses 128-bit alignment. */
2608 if (TARGET_VSX && !TARGET_VSX_ALIGN_128)
2619 /* V2DF mode, VSX only. */
2622 rs6000_vector_unit[V2DFmode] = VECTOR_VSX;
2623 rs6000_vector_mem[V2DFmode] = VECTOR_VSX;
2624 rs6000_vector_align[V2DFmode] = align64;
2627 /* V4SF mode, either VSX or Altivec. */
2630 rs6000_vector_unit[V4SFmode] = VECTOR_VSX;
2631 rs6000_vector_mem[V4SFmode] = VECTOR_VSX;
2632 rs6000_vector_align[V4SFmode] = align32;
2634 else if (TARGET_ALTIVEC)
2636 rs6000_vector_unit[V4SFmode] = VECTOR_ALTIVEC;
2637 rs6000_vector_mem[V4SFmode] = VECTOR_ALTIVEC;
2638 rs6000_vector_align[V4SFmode] = align32;
2641 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2645 rs6000_vector_unit[V4SImode] = VECTOR_ALTIVEC;
2646 rs6000_vector_unit[V8HImode] = VECTOR_ALTIVEC;
2647 rs6000_vector_unit[V16QImode] = VECTOR_ALTIVEC;
2648 rs6000_vector_align[V4SImode] = align32;
2649 rs6000_vector_align[V8HImode] = align32;
2650 rs6000_vector_align[V16QImode] = align32;
2654 rs6000_vector_mem[V4SImode] = VECTOR_VSX;
2655 rs6000_vector_mem[V8HImode] = VECTOR_VSX;
2656 rs6000_vector_mem[V16QImode] = VECTOR_VSX;
2660 rs6000_vector_mem[V4SImode] = VECTOR_ALTIVEC;
2661 rs6000_vector_mem[V8HImode] = VECTOR_ALTIVEC;
2662 rs6000_vector_mem[V16QImode] = VECTOR_ALTIVEC;
2666 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2667 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2670 rs6000_vector_mem[V2DImode] = VECTOR_VSX;
2671 rs6000_vector_unit[V2DImode]
2672 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
2673 rs6000_vector_align[V2DImode] = align64;
2675 rs6000_vector_mem[V1TImode] = VECTOR_VSX;
2676 rs6000_vector_unit[V1TImode]
2677 = (TARGET_P8_VECTOR) ? VECTOR_P8_VECTOR : VECTOR_NONE;
2678 rs6000_vector_align[V1TImode] = 128;
2681 /* DFmode, see if we want to use the VSX unit. Memory is handled
2682 differently, so don't set rs6000_vector_mem. */
2683 if (TARGET_VSX && TARGET_VSX_SCALAR_DOUBLE)
2685 rs6000_vector_unit[DFmode] = VECTOR_VSX;
2686 rs6000_vector_align[DFmode] = 64;
2689 /* SFmode, see if we want to use the VSX unit. */
2690 if (TARGET_P8_VECTOR && TARGET_VSX_SCALAR_FLOAT)
2692 rs6000_vector_unit[SFmode] = VECTOR_VSX;
2693 rs6000_vector_align[SFmode] = 32;
2696 /* Allow TImode in VSX register and set the VSX memory macros. */
2697 if (TARGET_VSX && TARGET_VSX_TIMODE)
2699 rs6000_vector_mem[TImode] = VECTOR_VSX;
2700 rs6000_vector_align[TImode] = align64;
2703 /* TODO add SPE and paired floating point vector support. */
2705 /* Register class constraints for the constraints that depend on compile
2706 switches. When the VSX code was added, different constraints were added
2707 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
2708 of the VSX registers are used. The register classes for scalar floating
2709 point types is set, based on whether we allow that type into the upper
2710 (Altivec) registers. GCC has register classes to target the Altivec
2711 registers for load/store operations, to select using a VSX memory
2712 operation instead of the traditional floating point operation. The
2715 d - Register class to use with traditional DFmode instructions.
2716 f - Register class to use with traditional SFmode instructions.
2717 v - Altivec register.
2718 wa - Any VSX register.
2719 wc - Reserved to represent individual CR bits (used in LLVM).
2720 wd - Preferred register class for V2DFmode.
2721 wf - Preferred register class for V4SFmode.
2722 wg - Float register for power6x move insns.
2723 wh - FP register for direct move instructions.
2724 wi - FP or VSX register to hold 64-bit integers for VSX insns.
2725 wj - FP or VSX register to hold 64-bit integers for direct moves.
2726 wk - FP or VSX register to hold 64-bit doubles for direct moves.
2727 wl - Float register if we can do 32-bit signed int loads.
2728 wm - VSX register for ISA 2.07 direct move operations.
2729 wn - always NO_REGS.
2730 wr - GPR if 64-bit mode is permitted.
2731 ws - Register class to do ISA 2.06 DF operations.
2732 wt - VSX register for TImode in VSX registers.
2733 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
2734 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
2735 ww - Register class to do SF conversions in with VSX operations.
2736 wx - Float register if we can do 32-bit int stores.
2737 wy - Register class to do ISA 2.07 SF operations.
2738 wz - Float register if we can do 32-bit unsigned int loads. */
2740 if (TARGET_HARD_FLOAT && TARGET_FPRS)
2741 rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */
2743 if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
2744 rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */
2748 rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS;
2749 rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */
2750 rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */
2751 rs6000_constraints[RS6000_CONSTRAINT_wi] = FLOAT_REGS; /* DImode */
2753 if (TARGET_VSX_TIMODE)
2754 rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */
2756 if (TARGET_UPPER_REGS_DF) /* DFmode */
2758 rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS;
2759 rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS;
2762 rs6000_constraints[RS6000_CONSTRAINT_ws] = FLOAT_REGS;
2765 /* Add conditional constraints based on various options, to allow us to
2766 collapse multiple insn patterns. */
2768 rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS;
2770 if (TARGET_MFPGPR) /* DFmode */
2771 rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS;
2774 rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */
2776 if (TARGET_DIRECT_MOVE)
2778 rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS;
2779 rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */
2780 = rs6000_constraints[RS6000_CONSTRAINT_wi];
2781 rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */
2782 = rs6000_constraints[RS6000_CONSTRAINT_ws];
2783 rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS;
2786 if (TARGET_POWERPC64)
2787 rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
2789 if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) /* SFmode */
2791 rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS;
2792 rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS;
2793 rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
2795 else if (TARGET_P8_VECTOR)
2797 rs6000_constraints[RS6000_CONSTRAINT_wy] = FLOAT_REGS;
2798 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
2800 else if (TARGET_VSX)
2801 rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
2804 rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
2807 rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */
2809 /* Set up the reload helper and direct move functions. */
2810 if (TARGET_VSX || TARGET_ALTIVEC)
2814 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_di_store;
2815 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_di_load;
2816 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_di_store;
2817 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_di_load;
2818 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_di_store;
2819 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_di_load;
2820 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_di_store;
2821 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_di_load;
2822 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_di_store;
2823 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_di_load;
2824 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_di_store;
2825 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_di_load;
2826 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_di_store;
2827 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load;
2828 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store;
2829 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load;
2830 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store;
2831 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load;
2832 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_di_store;
2833 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load;
2834 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store;
2835 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load;
2837 if (TARGET_VSX_TIMODE)
2839 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_di_store;
2840 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_di_load;
2843 if (TARGET_DIRECT_MOVE)
2845 reg_addr[TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxti;
2846 reg_addr[V1TImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv1ti;
2847 reg_addr[V2DFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2df;
2848 reg_addr[V2DImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv2di;
2849 reg_addr[V4SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4sf;
2850 reg_addr[V4SImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv4si;
2851 reg_addr[V8HImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv8hi;
2852 reg_addr[V16QImode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxv16qi;
2853 reg_addr[SFmode].reload_gpr_vsx = CODE_FOR_reload_gpr_from_vsxsf;
2855 reg_addr[TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprti;
2856 reg_addr[V1TImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv1ti;
2857 reg_addr[V2DFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2df;
2858 reg_addr[V2DImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv2di;
2859 reg_addr[V4SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4sf;
2860 reg_addr[V4SImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv4si;
2861 reg_addr[V8HImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv8hi;
2862 reg_addr[V16QImode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprv16qi;
2863 reg_addr[SFmode].reload_vsx_gpr = CODE_FOR_reload_vsx_from_gprsf;
2868 reg_addr[V16QImode].reload_store = CODE_FOR_reload_v16qi_si_store;
2869 reg_addr[V16QImode].reload_load = CODE_FOR_reload_v16qi_si_load;
2870 reg_addr[V8HImode].reload_store = CODE_FOR_reload_v8hi_si_store;
2871 reg_addr[V8HImode].reload_load = CODE_FOR_reload_v8hi_si_load;
2872 reg_addr[V4SImode].reload_store = CODE_FOR_reload_v4si_si_store;
2873 reg_addr[V4SImode].reload_load = CODE_FOR_reload_v4si_si_load;
2874 reg_addr[V2DImode].reload_store = CODE_FOR_reload_v2di_si_store;
2875 reg_addr[V2DImode].reload_load = CODE_FOR_reload_v2di_si_load;
2876 reg_addr[V1TImode].reload_store = CODE_FOR_reload_v1ti_si_store;
2877 reg_addr[V1TImode].reload_load = CODE_FOR_reload_v1ti_si_load;
2878 reg_addr[V4SFmode].reload_store = CODE_FOR_reload_v4sf_si_store;
2879 reg_addr[V4SFmode].reload_load = CODE_FOR_reload_v4sf_si_load;
2880 reg_addr[V2DFmode].reload_store = CODE_FOR_reload_v2df_si_store;
2881 reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load;
2882 reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store;
2883 reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load;
2884 reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store;
2885 reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load;
2886 reg_addr[SFmode].reload_store = CODE_FOR_reload_sf_si_store;
2887 reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load;
2888 reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store;
2889 reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load;
2891 if (TARGET_VSX_TIMODE)
2893 reg_addr[TImode].reload_store = CODE_FOR_reload_ti_si_store;
2894 reg_addr[TImode].reload_load = CODE_FOR_reload_ti_si_load;
2897 if (TARGET_DIRECT_MOVE)
2899 reg_addr[DImode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdi;
2900 reg_addr[DDmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdd;
2901 reg_addr[DFmode].reload_fpr_gpr = CODE_FOR_reload_fpr_from_gprdf;
2905 if (TARGET_UPPER_REGS_DF)
2906 reg_addr[DFmode].scalar_in_vmx_p = true;
2908 if (TARGET_UPPER_REGS_SF)
2909 reg_addr[SFmode].scalar_in_vmx_p = true;
2912 /* Precalculate HARD_REGNO_NREGS. */
2913 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2914 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2915 rs6000_hard_regno_nregs[m][r]
2916 = rs6000_hard_regno_nregs_internal (r, (machine_mode)m);
2918 /* Precalculate HARD_REGNO_MODE_OK. */
2919 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
2920 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2921 if (rs6000_hard_regno_mode_ok (r, (machine_mode)m))
2922 rs6000_hard_regno_mode_ok_p[m][r] = true;
2924 /* Precalculate CLASS_MAX_NREGS sizes. */
2925 for (c = 0; c < LIM_REG_CLASSES; ++c)
2929 if (TARGET_VSX && VSX_REG_CLASS_P (c))
2930 reg_size = UNITS_PER_VSX_WORD;
2932 else if (c == ALTIVEC_REGS)
2933 reg_size = UNITS_PER_ALTIVEC_WORD;
2935 else if (c == FLOAT_REGS)
2936 reg_size = UNITS_PER_FP_WORD;
2939 reg_size = UNITS_PER_WORD;
2941 for (m = 0; m < NUM_MACHINE_MODES; ++m)
2943 machine_mode m2 = (machine_mode)m;
2944 int reg_size2 = reg_size;
2946 /* TFmode/TDmode always takes 2 registers, even in VSX. */
2947 if (TARGET_VSX && VSX_REG_CLASS_P (c)
2948 && (m == TDmode || m == TFmode))
2949 reg_size2 = UNITS_PER_FP_WORD;
2951 rs6000_class_max_nregs[m][c]
2952 = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2;
2956 if (TARGET_E500_DOUBLE)
2957 rs6000_class_max_nregs[DFmode][GENERAL_REGS] = 1;
2959 /* Calculate which modes to automatically generate code to use a the
2960 reciprocal divide and square root instructions. In the future, possibly
2961 automatically generate the instructions even if the user did not specify
2962 -mrecip. The older machines double precision reciprocal sqrt estimate is
2963 not accurate enough. */
2964 memset (rs6000_recip_bits, 0, sizeof (rs6000_recip_bits));
2966 rs6000_recip_bits[SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2968 rs6000_recip_bits[DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2969 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2970 rs6000_recip_bits[V4SFmode] = RS6000_RECIP_MASK_HAVE_RE;
2971 if (VECTOR_UNIT_VSX_P (V2DFmode))
2972 rs6000_recip_bits[V2DFmode] = RS6000_RECIP_MASK_HAVE_RE;
2974 if (TARGET_FRSQRTES)
2975 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2977 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2978 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode))
2979 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2980 if (VECTOR_UNIT_VSX_P (V2DFmode))
2981 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_HAVE_RSQRTE;
2983 if (rs6000_recip_control)
2985 if (!flag_finite_math_only)
2986 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2987 if (flag_trapping_math)
2988 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2989 if (!flag_reciprocal_math)
2990 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2991 if (flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math)
2993 if (RS6000_RECIP_HAVE_RE_P (SFmode)
2994 && (rs6000_recip_control & RECIP_SF_DIV) != 0)
2995 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
2997 if (RS6000_RECIP_HAVE_RE_P (DFmode)
2998 && (rs6000_recip_control & RECIP_DF_DIV) != 0)
2999 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3001 if (RS6000_RECIP_HAVE_RE_P (V4SFmode)
3002 && (rs6000_recip_control & RECIP_V4SF_DIV) != 0)
3003 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3005 if (RS6000_RECIP_HAVE_RE_P (V2DFmode)
3006 && (rs6000_recip_control & RECIP_V2DF_DIV) != 0)
3007 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RE;
3009 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode)
3010 && (rs6000_recip_control & RECIP_SF_RSQRT) != 0)
3011 rs6000_recip_bits[SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3013 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode)
3014 && (rs6000_recip_control & RECIP_DF_RSQRT) != 0)
3015 rs6000_recip_bits[DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3017 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode)
3018 && (rs6000_recip_control & RECIP_V4SF_RSQRT) != 0)
3019 rs6000_recip_bits[V4SFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3021 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode)
3022 && (rs6000_recip_control & RECIP_V2DF_RSQRT) != 0)
3023 rs6000_recip_bits[V2DFmode] |= RS6000_RECIP_MASK_AUTO_RSQRTE;
3027 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3028 legitimate address support to figure out the appropriate addressing to
3030 rs6000_setup_reg_addr_masks ();
3032 if (global_init_p || TARGET_DEBUG_TARGET)
3034 if (TARGET_DEBUG_REG)
3035 rs6000_debug_reg_global ();
3037 if (TARGET_DEBUG_COST || TARGET_DEBUG_REG)
3039 "SImode variable mult cost = %d\n"
3040 "SImode constant mult cost = %d\n"
3041 "SImode short constant mult cost = %d\n"
3042 "DImode multipliciation cost = %d\n"
3043 "SImode division cost = %d\n"
3044 "DImode division cost = %d\n"
3045 "Simple fp operation cost = %d\n"
3046 "DFmode multiplication cost = %d\n"
3047 "SFmode division cost = %d\n"
3048 "DFmode division cost = %d\n"
3049 "cache line size = %d\n"
3050 "l1 cache size = %d\n"
3051 "l2 cache size = %d\n"
3052 "simultaneous prefetches = %d\n"
3055 rs6000_cost->mulsi_const,
3056 rs6000_cost->mulsi_const9,
3064 rs6000_cost->cache_line_size,
3065 rs6000_cost->l1_cache_size,
3066 rs6000_cost->l2_cache_size,
3067 rs6000_cost->simultaneous_prefetches);
3072 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3075 darwin_rs6000_override_options (void)
3077 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3079 rs6000_altivec_abi = 1;
3080 TARGET_ALTIVEC_VRSAVE = 1;
3081 rs6000_current_abi = ABI_DARWIN;
3083 if (DEFAULT_ABI == ABI_DARWIN
3085 darwin_one_byte_bool = 1;
3087 if (TARGET_64BIT && ! TARGET_POWERPC64)
3089 rs6000_isa_flags |= OPTION_MASK_POWERPC64;
3090 warning (0, "-m64 requires PowerPC64 architecture, enabling");
3094 rs6000_default_long_calls = 1;
3095 rs6000_isa_flags |= OPTION_MASK_SOFT_FLOAT;
3098 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3100 if (!flag_mkernel && !flag_apple_kext
3102 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC))
3103 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3105 /* Unless the user (not the configurer) has explicitly overridden
3106 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3107 G4 unless targeting the kernel. */
3110 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
3111 && ! (rs6000_isa_flags_explicit & OPTION_MASK_ALTIVEC)
3112 && ! global_options_set.x_rs6000_cpu_index)
3114 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3119 /* If not otherwise specified by a target, make 'long double' equivalent to
3122 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3123 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3126 /* Return the builtin mask of the various options used that could affect which
3127 builtins were used. In the past we used target_flags, but we've run out of
3128 bits, and some options like SPE and PAIRED are no longer in
3132 rs6000_builtin_mask_calculate (void)
3134 return (((TARGET_ALTIVEC) ? RS6000_BTM_ALTIVEC : 0)
3135 | ((TARGET_VSX) ? RS6000_BTM_VSX : 0)
3136 | ((TARGET_SPE) ? RS6000_BTM_SPE : 0)
3137 | ((TARGET_PAIRED_FLOAT) ? RS6000_BTM_PAIRED : 0)
3138 | ((TARGET_FRE) ? RS6000_BTM_FRE : 0)
3139 | ((TARGET_FRES) ? RS6000_BTM_FRES : 0)
3140 | ((TARGET_FRSQRTE) ? RS6000_BTM_FRSQRTE : 0)
3141 | ((TARGET_FRSQRTES) ? RS6000_BTM_FRSQRTES : 0)
3142 | ((TARGET_POPCNTD) ? RS6000_BTM_POPCNTD : 0)
3143 | ((rs6000_cpu == PROCESSOR_CELL) ? RS6000_BTM_CELL : 0)
3144 | ((TARGET_P8_VECTOR) ? RS6000_BTM_P8_VECTOR : 0)
3145 | ((TARGET_CRYPTO) ? RS6000_BTM_CRYPTO : 0)
3146 | ((TARGET_HTM) ? RS6000_BTM_HTM : 0)
3147 | ((TARGET_DFP) ? RS6000_BTM_DFP : 0)
3148 | ((TARGET_HARD_FLOAT) ? RS6000_BTM_HARD_FLOAT : 0)
3149 | ((TARGET_LONG_DOUBLE_128) ? RS6000_BTM_LDBL128 : 0));
3152 /* Implement TARGET_MD_ASM_CLOBBERS. All asm statements are considered
3153 to clobber the XER[CA] bit because clobbering that bit without telling
3154 the compiler worked just fine with versions of GCC before GCC 5, and
3155 breaking a lot of older code in ways that are hard to track down is
3156 not such a great idea. */
3159 rs6000_md_asm_clobbers (tree, tree, tree clobbers)
3161 tree s = build_string (strlen (reg_names[CA_REGNO]), reg_names[CA_REGNO]);
3162 return tree_cons (NULL_TREE, s, clobbers);
3165 /* Override command line options. Mostly we process the processor type and
3166 sometimes adjust other TARGET_ options. */
3169 rs6000_option_override_internal (bool global_init_p)
3172 bool have_cpu = false;
3174 /* The default cpu requested at configure time, if any. */
3175 const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT;
3177 HOST_WIDE_INT set_masks;
3180 struct cl_target_option *main_target_opt
3181 = ((global_init_p || target_option_default_node == NULL)
3182 ? NULL : TREE_TARGET_OPTION (target_option_default_node));
3184 /* Remember the explicit arguments. */
3186 rs6000_isa_flags_explicit = global_options_set.x_rs6000_isa_flags;
3188 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3189 library functions, so warn about it. The flag may be useful for
3190 performance studies from time to time though, so don't disable it
3192 if (global_options_set.x_rs6000_alignment_flags
3193 && rs6000_alignment_flags == MASK_ALIGN_POWER
3194 && DEFAULT_ABI == ABI_DARWIN
3196 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3197 " it is incompatible with the installed C and C++ libraries");
3199 /* Numerous experiment shows that IRA based loop pressure
3200 calculation works better for RTL loop invariant motion on targets
3201 with enough (>= 32) registers. It is an expensive optimization.
3202 So it is on only for peak performance. */
3203 if (optimize >= 3 && global_init_p
3204 && !global_options_set.x_flag_ira_loop_pressure)
3205 flag_ira_loop_pressure = 1;
3207 /* Set the pointer size. */
3210 rs6000_pmode = (int)DImode;
3211 rs6000_pointer_size = 64;
3215 rs6000_pmode = (int)SImode;
3216 rs6000_pointer_size = 32;
3219 /* Some OSs don't support saving the high part of 64-bit registers on context
3220 switch. Other OSs don't support saving Altivec registers. On those OSs,
3221 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3222 if the user wants either, the user must explicitly specify them and we
3223 won't interfere with the user's specification. */
3225 set_masks = POWERPC_MASKS;
3226 #ifdef OS_MISSING_POWERPC64
3227 if (OS_MISSING_POWERPC64)
3228 set_masks &= ~OPTION_MASK_POWERPC64;
3230 #ifdef OS_MISSING_ALTIVEC
3231 if (OS_MISSING_ALTIVEC)
3232 set_masks &= ~(OPTION_MASK_ALTIVEC | OPTION_MASK_VSX);
3235 /* Don't override by the processor default if given explicitly. */
3236 set_masks &= ~rs6000_isa_flags_explicit;
3238 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3239 the cpu in a target attribute or pragma, but did not specify a tuning
3240 option, use the cpu for the tuning option rather than the option specified
3241 with -mtune on the command line. Process a '--with-cpu' configuration
3242 request as an implicit --cpu. */
3243 if (rs6000_cpu_index >= 0)
3245 cpu_index = rs6000_cpu_index;
3248 else if (main_target_opt != NULL && main_target_opt->x_rs6000_cpu_index >= 0)
3250 rs6000_cpu_index = cpu_index = main_target_opt->x_rs6000_cpu_index;
3253 else if (implicit_cpu)
3255 rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (implicit_cpu);
3260 const char *default_cpu = (TARGET_POWERPC64 ? "powerpc64" : "powerpc");
3261 rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
3265 gcc_assert (cpu_index >= 0);
3267 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3268 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3269 with those from the cpu, except for options that were explicitly set. If
3270 we don't have a cpu, do not override the target bits set in
3274 rs6000_isa_flags &= ~set_masks;
3275 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
3279 rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
3280 & ~rs6000_isa_flags_explicit);
3282 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3283 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3284 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3285 to using rs6000_isa_flags, we need to do the initialization here. */
3287 rs6000_isa_flags |= (TARGET_DEFAULT & ~rs6000_isa_flags_explicit);
3289 if (rs6000_tune_index >= 0)
3290 tune_index = rs6000_tune_index;
3292 rs6000_tune_index = tune_index = cpu_index;
3296 enum processor_type tune_proc
3297 = (TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT);
3300 for (i = 0; i < ARRAY_SIZE (processor_target_table); i++)
3301 if (processor_target_table[i].processor == tune_proc)
3303 rs6000_tune_index = tune_index = i;
3308 gcc_assert (tune_index >= 0);
3309 rs6000_cpu = processor_target_table[tune_index].processor;
3311 /* Pick defaults for SPE related control flags. Do this early to make sure
3312 that the TARGET_ macros are representative ASAP. */
3314 int spe_capable_cpu =
3315 (rs6000_cpu == PROCESSOR_PPC8540
3316 || rs6000_cpu == PROCESSOR_PPC8548);
3318 if (!global_options_set.x_rs6000_spe_abi)
3319 rs6000_spe_abi = spe_capable_cpu;
3321 if (!global_options_set.x_rs6000_spe)
3322 rs6000_spe = spe_capable_cpu;
3324 if (!global_options_set.x_rs6000_float_gprs)
3326 (rs6000_cpu == PROCESSOR_PPC8540 ? 1
3327 : rs6000_cpu == PROCESSOR_PPC8548 ? 2
3331 if (global_options_set.x_rs6000_spe_abi
3334 error ("not configured for SPE ABI");
3336 if (global_options_set.x_rs6000_spe
3339 error ("not configured for SPE instruction set");
3341 if (main_target_opt != NULL
3342 && ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
3343 || (main_target_opt->x_rs6000_spe != rs6000_spe)
3344 || (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
3345 error ("target attribute or pragma changes SPE ABI");
3347 if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
3348 || rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64
3349 || rs6000_cpu == PROCESSOR_PPCE5500)
3352 error ("AltiVec not supported in this target");
3354 error ("SPE not supported in this target");
3356 if (rs6000_cpu == PROCESSOR_PPCE6500)
3359 error ("SPE not supported in this target");
3362 /* Disable Cell microcode if we are optimizing for the Cell
3363 and not optimizing for size. */
3364 if (rs6000_gen_cell_microcode == -1)
3365 rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
3368 /* If we are optimizing big endian systems for space and it's OK to
3369 use instructions that would be microcoded on the Cell, use the
3370 load/store multiple and string instructions. */
3371 if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
3372 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE
3373 | OPTION_MASK_STRING);
3375 /* Don't allow -mmultiple or -mstring on little endian systems
3376 unless the cpu is a 750, because the hardware doesn't support the
3377 instructions used in little endian mode, and causes an alignment
3378 trap. The 750 does not cause an alignment trap (except when the
3379 target is unaligned). */
3381 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
3383 if (TARGET_MULTIPLE)
3385 rs6000_isa_flags &= ~OPTION_MASK_MULTIPLE;
3386 if ((rs6000_isa_flags_explicit & OPTION_MASK_MULTIPLE) != 0)
3387 warning (0, "-mmultiple is not supported on little endian systems");
3392 rs6000_isa_flags &= ~OPTION_MASK_STRING;
3393 if ((rs6000_isa_flags_explicit & OPTION_MASK_STRING) != 0)
3394 warning (0, "-mstring is not supported on little endian systems");
3398 /* If little-endian, default to -mstrict-align on older processors.
3399 Testing for htm matches power8 and later. */
3400 if (!BYTES_BIG_ENDIAN
3401 && !(processor_target_table[tune_index].target_enable & OPTION_MASK_HTM))
3402 rs6000_isa_flags |= ~rs6000_isa_flags_explicit & OPTION_MASK_STRICT_ALIGN;
3404 /* -maltivec={le,be} implies -maltivec. */
3405 if (rs6000_altivec_element_order != 0)
3406 rs6000_isa_flags |= OPTION_MASK_ALTIVEC;
3408 /* Disallow -maltivec=le in big endian mode for now. This is not
3409 known to be useful for anyone. */
3410 if (BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 1)
3412 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
3413 rs6000_altivec_element_order = 0;
3416 /* Add some warnings for VSX. */
3419 const char *msg = NULL;
3420 if (!TARGET_HARD_FLOAT || !TARGET_FPRS
3421 || !TARGET_SINGLE_FLOAT || !TARGET_DOUBLE_FLOAT)
3423 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3424 msg = N_("-mvsx requires hardware floating point");
3427 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3428 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3431 else if (TARGET_PAIRED_FLOAT)
3432 msg = N_("-mvsx and -mpaired are incompatible");
3433 else if (TARGET_AVOID_XFORM > 0)
3434 msg = N_("-mvsx needs indexed addressing");
3435 else if (!TARGET_ALTIVEC && (rs6000_isa_flags_explicit
3436 & OPTION_MASK_ALTIVEC))
3438 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX)
3439 msg = N_("-mvsx and -mno-altivec are incompatible");
3441 msg = N_("-mno-altivec disables vsx");
3447 rs6000_isa_flags &= ~ OPTION_MASK_VSX;
3448 rs6000_isa_flags_explicit |= OPTION_MASK_VSX;
3452 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3453 the -mcpu setting to enable options that conflict. */
3454 if ((!TARGET_HARD_FLOAT || !TARGET_ALTIVEC || !TARGET_VSX)
3455 && (rs6000_isa_flags_explicit & (OPTION_MASK_SOFT_FLOAT
3456 | OPTION_MASK_ALTIVEC
3457 | OPTION_MASK_VSX)) != 0)
3458 rs6000_isa_flags &= ~((OPTION_MASK_P8_VECTOR | OPTION_MASK_CRYPTO
3459 | OPTION_MASK_DIRECT_MOVE)
3460 & ~rs6000_isa_flags_explicit);
3462 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
3463 rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags);
3465 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3466 unless the user explicitly used the -mno-<option> to disable the code. */
3467 if (TARGET_P8_VECTOR || TARGET_DIRECT_MOVE || TARGET_CRYPTO)
3468 rs6000_isa_flags |= (ISA_2_7_MASKS_SERVER & ~rs6000_isa_flags_explicit);
3469 else if (TARGET_VSX)
3470 rs6000_isa_flags |= (ISA_2_6_MASKS_SERVER & ~rs6000_isa_flags_explicit);
3471 else if (TARGET_POPCNTD)
3472 rs6000_isa_flags |= (ISA_2_6_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
3473 else if (TARGET_DFP)
3474 rs6000_isa_flags |= (ISA_2_5_MASKS_SERVER & ~rs6000_isa_flags_explicit);
3475 else if (TARGET_CMPB)
3476 rs6000_isa_flags |= (ISA_2_5_MASKS_EMBEDDED & ~rs6000_isa_flags_explicit);
3477 else if (TARGET_FPRND)
3478 rs6000_isa_flags |= (ISA_2_4_MASKS & ~rs6000_isa_flags_explicit);
3479 else if (TARGET_POPCNTB)
3480 rs6000_isa_flags |= (ISA_2_2_MASKS & ~rs6000_isa_flags_explicit);
3481 else if (TARGET_ALTIVEC)
3482 rs6000_isa_flags |= (OPTION_MASK_PPC_GFXOPT & ~rs6000_isa_flags_explicit);
3484 if (TARGET_CRYPTO && !TARGET_ALTIVEC)
3486 if (rs6000_isa_flags_explicit & OPTION_MASK_CRYPTO)
3487 error ("-mcrypto requires -maltivec");
3488 rs6000_isa_flags &= ~OPTION_MASK_CRYPTO;
3491 if (TARGET_DIRECT_MOVE && !TARGET_VSX)
3493 if (rs6000_isa_flags_explicit & OPTION_MASK_DIRECT_MOVE)
3494 error ("-mdirect-move requires -mvsx");
3495 rs6000_isa_flags &= ~OPTION_MASK_DIRECT_MOVE;
3498 if (TARGET_P8_VECTOR && !TARGET_ALTIVEC)
3500 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
3501 error ("-mpower8-vector requires -maltivec");
3502 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
3505 if (TARGET_P8_VECTOR && !TARGET_VSX)
3507 if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
3508 error ("-mpower8-vector requires -mvsx");
3509 rs6000_isa_flags &= ~OPTION_MASK_P8_VECTOR;
3512 if (TARGET_VSX_TIMODE && !TARGET_VSX)
3514 if (rs6000_isa_flags_explicit & OPTION_MASK_VSX_TIMODE)
3515 error ("-mvsx-timode requires -mvsx");
3516 rs6000_isa_flags &= ~OPTION_MASK_VSX_TIMODE;
3519 if (TARGET_DFP && !TARGET_HARD_FLOAT)
3521 if (rs6000_isa_flags_explicit & OPTION_MASK_DFP)
3522 error ("-mhard-dfp requires -mhard-float");
3523 rs6000_isa_flags &= ~OPTION_MASK_DFP;
3526 /* Allow an explicit -mupper-regs to set both -mupper-regs-df and
3527 -mupper-regs-sf, depending on the cpu, unless the user explicitly also set
3528 the individual option. */
3529 if (TARGET_UPPER_REGS > 0)
3532 && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF))
3534 rs6000_isa_flags |= OPTION_MASK_UPPER_REGS_DF;
3535 rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DF;
3537 if (TARGET_P8_VECTOR
3538 && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF))
3540 rs6000_isa_flags |= OPTION_MASK_UPPER_REGS_SF;
3541 rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_SF;
3544 else if (TARGET_UPPER_REGS == 0)
3547 && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF))
3549 rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DF;
3550 rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_DF;
3552 if (TARGET_P8_VECTOR
3553 && !(rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF))
3555 rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_SF;
3556 rs6000_isa_flags_explicit |= OPTION_MASK_UPPER_REGS_SF;
3560 if (TARGET_UPPER_REGS_DF && !TARGET_VSX)
3562 if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF)
3563 error ("-mupper-regs-df requires -mvsx");
3564 rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_DF;
3567 if (TARGET_UPPER_REGS_SF && !TARGET_P8_VECTOR)
3569 if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_SF)
3570 error ("-mupper-regs-sf requires -mpower8-vector");
3571 rs6000_isa_flags &= ~OPTION_MASK_UPPER_REGS_SF;
3574 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3575 silently turn off quad memory mode. */
3576 if ((TARGET_QUAD_MEMORY || TARGET_QUAD_MEMORY_ATOMIC) && !TARGET_POWERPC64)
3578 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
3579 warning (0, N_("-mquad-memory requires 64-bit mode"));
3581 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0)
3582 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
3584 rs6000_isa_flags &= ~(OPTION_MASK_QUAD_MEMORY
3585 | OPTION_MASK_QUAD_MEMORY_ATOMIC);
3588 /* Non-atomic quad memory load/store are disabled for little endian, since
3589 the words are reversed, but atomic operations can still be done by
3590 swapping the words. */
3591 if (TARGET_QUAD_MEMORY && !WORDS_BIG_ENDIAN)
3593 if ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY) != 0)
3594 warning (0, N_("-mquad-memory is not available in little endian mode"));
3596 rs6000_isa_flags &= ~OPTION_MASK_QUAD_MEMORY;
3599 /* Assume if the user asked for normal quad memory instructions, they want
3600 the atomic versions as well, unless they explicity told us not to use quad
3601 word atomic instructions. */
3602 if (TARGET_QUAD_MEMORY
3603 && !TARGET_QUAD_MEMORY_ATOMIC
3604 && ((rs6000_isa_flags_explicit & OPTION_MASK_QUAD_MEMORY_ATOMIC) == 0))
3605 rs6000_isa_flags |= OPTION_MASK_QUAD_MEMORY_ATOMIC;
3607 /* Enable power8 fusion if we are tuning for power8, even if we aren't
3608 generating power8 instructions. */
3609 if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
3610 rs6000_isa_flags |= (processor_target_table[tune_index].target_enable
3611 & OPTION_MASK_P8_FUSION);
3613 /* Power8 does not fuse sign extended loads with the addis. If we are
3614 optimizing at high levels for speed, convert a sign extended load into a
3615 zero extending load, and an explicit sign extension. */
3616 if (TARGET_P8_FUSION
3617 && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
3618 && optimize_function_for_speed_p (cfun)
3620 rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
3622 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
3623 rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
3625 /* E500mc does "better" if we inline more aggressively. Respect the
3626 user's opinion, though. */
3627 if (rs6000_block_move_inline_limit == 0
3628 && (rs6000_cpu == PROCESSOR_PPCE500MC
3629 || rs6000_cpu == PROCESSOR_PPCE500MC64
3630 || rs6000_cpu == PROCESSOR_PPCE5500
3631 || rs6000_cpu == PROCESSOR_PPCE6500))
3632 rs6000_block_move_inline_limit = 128;
3634 /* store_one_arg depends on expand_block_move to handle at least the
3635 size of reg_parm_stack_space. */
3636 if (rs6000_block_move_inline_limit < (TARGET_POWERPC64 ? 64 : 32))
3637 rs6000_block_move_inline_limit = (TARGET_POWERPC64 ? 64 : 32);
3641 /* If the appropriate debug option is enabled, replace the target hooks
3642 with debug versions that call the real version and then prints
3643 debugging information. */
3644 if (TARGET_DEBUG_COST)
3646 targetm.rtx_costs = rs6000_debug_rtx_costs;
3647 targetm.address_cost = rs6000_debug_address_cost;
3648 targetm.sched.adjust_cost = rs6000_debug_adjust_cost;
3651 if (TARGET_DEBUG_ADDR)
3653 targetm.legitimate_address_p = rs6000_debug_legitimate_address_p;
3654 targetm.legitimize_address = rs6000_debug_legitimize_address;
3655 rs6000_secondary_reload_class_ptr
3656 = rs6000_debug_secondary_reload_class;
3657 rs6000_secondary_memory_needed_ptr
3658 = rs6000_debug_secondary_memory_needed;
3659 rs6000_cannot_change_mode_class_ptr
3660 = rs6000_debug_cannot_change_mode_class;
3661 rs6000_preferred_reload_class_ptr
3662 = rs6000_debug_preferred_reload_class;
3663 rs6000_legitimize_reload_address_ptr
3664 = rs6000_debug_legitimize_reload_address;
3665 rs6000_mode_dependent_address_ptr
3666 = rs6000_debug_mode_dependent_address;
3669 if (rs6000_veclibabi_name)
3671 if (strcmp (rs6000_veclibabi_name, "mass") == 0)
3672 rs6000_veclib_handler = rs6000_builtin_vectorized_libmass;
3675 error ("unknown vectorization library ABI type (%s) for "
3676 "-mveclibabi= switch", rs6000_veclibabi_name);
3682 if (!global_options_set.x_rs6000_long_double_type_size)
3684 if (main_target_opt != NULL
3685 && (main_target_opt->x_rs6000_long_double_type_size
3686 != RS6000_DEFAULT_LONG_DOUBLE_SIZE))
3687 error ("target attribute or pragma changes long double size");
3689 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
3692 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3693 if (!global_options_set.x_rs6000_ieeequad)
3694 rs6000_ieeequad = 1;
3697 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3698 target attribute or pragma which automatically enables both options,
3699 unless the altivec ABI was set. This is set by default for 64-bit, but
3701 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
3702 rs6000_isa_flags &= ~((OPTION_MASK_VSX | OPTION_MASK_ALTIVEC)
3703 & ~rs6000_isa_flags_explicit);
3705 /* Enable Altivec ABI for AIX -maltivec. */
3706 if (TARGET_XCOFF && (TARGET_ALTIVEC || TARGET_VSX))
3708 if (main_target_opt != NULL && !main_target_opt->x_rs6000_altivec_abi)
3709 error ("target attribute or pragma changes AltiVec ABI");
3711 rs6000_altivec_abi = 1;
3714 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3715 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3716 be explicitly overridden in either case. */
3719 if (!global_options_set.x_rs6000_altivec_abi
3720 && (TARGET_64BIT || TARGET_ALTIVEC || TARGET_VSX))
3722 if (main_target_opt != NULL &&
3723 !main_target_opt->x_rs6000_altivec_abi)
3724 error ("target attribute or pragma changes AltiVec ABI");
3726 rs6000_altivec_abi = 1;
3730 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3731 So far, the only darwin64 targets are also MACH-O. */
3733 && DEFAULT_ABI == ABI_DARWIN
3736 if (main_target_opt != NULL && !main_target_opt->x_rs6000_darwin64_abi)
3737 error ("target attribute or pragma changes darwin64 ABI");
3740 rs6000_darwin64_abi = 1;
3741 /* Default to natural alignment, for better performance. */
3742 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
3746 /* Place FP constants in the constant pool instead of TOC
3747 if section anchors enabled. */
3748 if (flag_section_anchors
3749 && !global_options_set.x_TARGET_NO_FP_IN_TOC)
3750 TARGET_NO_FP_IN_TOC = 1;
3752 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
3753 rs6000_print_isa_options (stderr, 0, "before subtarget", rs6000_isa_flags);
3755 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3756 SUBTARGET_OVERRIDE_OPTIONS;
3758 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3759 SUBSUBTARGET_OVERRIDE_OPTIONS;
3761 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3762 SUB3TARGET_OVERRIDE_OPTIONS;
3765 if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
3766 rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
3768 /* For the E500 family of cores, reset the single/double FP flags to let us
3769 check that they remain constant across attributes or pragmas. Also,
3770 clear a possible request for string instructions, not supported and which
3771 we might have silently queried above for -Os.
3773 For other families, clear ISEL in case it was set implicitly.
3778 case PROCESSOR_PPC8540:
3779 case PROCESSOR_PPC8548:
3780 case PROCESSOR_PPCE500MC:
3781 case PROCESSOR_PPCE500MC64:
3782 case PROCESSOR_PPCE5500:
3783 case PROCESSOR_PPCE6500:
3785 rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
3786 rs6000_double_float = TARGET_E500_DOUBLE;
3788 rs6000_isa_flags &= ~OPTION_MASK_STRING;
3794 if (have_cpu && !(rs6000_isa_flags_explicit & OPTION_MASK_ISEL))
3795 rs6000_isa_flags &= ~OPTION_MASK_ISEL;
3800 if (main_target_opt)
3802 if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
3803 error ("target attribute or pragma changes single precision floating "
3805 if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
3806 error ("target attribute or pragma changes double precision floating "
3810 /* Detect invalid option combinations with E500. */
3813 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
3814 && rs6000_cpu != PROCESSOR_POWER5
3815 && rs6000_cpu != PROCESSOR_POWER6
3816 && rs6000_cpu != PROCESSOR_POWER7
3817 && rs6000_cpu != PROCESSOR_POWER8
3818 && rs6000_cpu != PROCESSOR_PPCA2
3819 && rs6000_cpu != PROCESSOR_CELL
3820 && rs6000_cpu != PROCESSOR_PPC476);
3821 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
3822 || rs6000_cpu == PROCESSOR_POWER5
3823 || rs6000_cpu == PROCESSOR_POWER7
3824 || rs6000_cpu == PROCESSOR_POWER8);
3825 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
3826 || rs6000_cpu == PROCESSOR_POWER5
3827 || rs6000_cpu == PROCESSOR_POWER6
3828 || rs6000_cpu == PROCESSOR_POWER7
3829 || rs6000_cpu == PROCESSOR_POWER8
3830 || rs6000_cpu == PROCESSOR_PPCE500MC
3831 || rs6000_cpu == PROCESSOR_PPCE500MC64
3832 || rs6000_cpu == PROCESSOR_PPCE5500
3833 || rs6000_cpu == PROCESSOR_PPCE6500);
3835 /* Allow debug switches to override the above settings. These are set to -1
3836 in rs6000.opt to indicate the user hasn't directly set the switch. */
3837 if (TARGET_ALWAYS_HINT >= 0)
3838 rs6000_always_hint = TARGET_ALWAYS_HINT;
3840 if (TARGET_SCHED_GROUPS >= 0)
3841 rs6000_sched_groups = TARGET_SCHED_GROUPS;
3843 if (TARGET_ALIGN_BRANCH_TARGETS >= 0)
3844 rs6000_align_branch_targets = TARGET_ALIGN_BRANCH_TARGETS;
3846 rs6000_sched_restricted_insns_priority
3847 = (rs6000_sched_groups ? 1 : 0);
3849 /* Handle -msched-costly-dep option. */
3850 rs6000_sched_costly_dep
3851 = (rs6000_sched_groups ? true_store_to_load_dep_costly : no_dep_costly);
3853 if (rs6000_sched_costly_dep_str)
3855 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
3856 rs6000_sched_costly_dep = no_dep_costly;
3857 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
3858 rs6000_sched_costly_dep = all_deps_costly;
3859 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
3860 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
3861 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
3862 rs6000_sched_costly_dep = store_to_load_dep_costly;
3864 rs6000_sched_costly_dep = ((enum rs6000_dependence_cost)
3865 atoi (rs6000_sched_costly_dep_str));
3868 /* Handle -minsert-sched-nops option. */
3869 rs6000_sched_insert_nops
3870 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
3872 if (rs6000_sched_insert_nops_str)
3874 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
3875 rs6000_sched_insert_nops = sched_finish_none;
3876 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
3877 rs6000_sched_insert_nops = sched_finish_pad_groups;
3878 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
3879 rs6000_sched_insert_nops = sched_finish_regroup_exact;
3881 rs6000_sched_insert_nops = ((enum rs6000_nop_insertion)
3882 atoi (rs6000_sched_insert_nops_str));
3887 #ifdef TARGET_REGNAMES
3888 /* If the user desires alternate register names, copy in the
3889 alternate names now. */
3890 if (TARGET_REGNAMES)
3891 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
3894 /* Set aix_struct_return last, after the ABI is determined.
3895 If -maix-struct-return or -msvr4-struct-return was explicitly
3896 used, don't override with the ABI default. */
3897 if (!global_options_set.x_aix_struct_return)
3898 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
3901 /* IBM XL compiler defaults to unsigned bitfields. */
3902 if (TARGET_XL_COMPAT)
3903 flag_signed_bitfields = 0;
3906 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
3907 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
3910 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
3912 /* We can only guarantee the availability of DI pseudo-ops when
3913 assembling for 64-bit targets. */
3916 targetm.asm_out.aligned_op.di = NULL;
3917 targetm.asm_out.unaligned_op.di = NULL;
3921 /* Set branch target alignment, if not optimizing for size. */
3924 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3925 aligned 8byte to avoid misprediction by the branch predictor. */
3926 if (rs6000_cpu == PROCESSOR_TITAN
3927 || rs6000_cpu == PROCESSOR_CELL)
3929 if (align_functions <= 0)
3930 align_functions = 8;
3931 if (align_jumps <= 0)
3933 if (align_loops <= 0)
3936 if (rs6000_align_branch_targets)
3938 if (align_functions <= 0)
3939 align_functions = 16;
3940 if (align_jumps <= 0)
3942 if (align_loops <= 0)
3944 can_override_loop_align = 1;
3948 if (align_jumps_max_skip <= 0)
3949 align_jumps_max_skip = 15;
3950 if (align_loops_max_skip <= 0)
3951 align_loops_max_skip = 15;
3954 /* Arrange to save and restore machine status around nested functions. */
3955 init_machine_status = rs6000_init_machine_status;
3957 /* We should always be splitting complex arguments, but we can't break
3958 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3959 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN)
3960 targetm.calls.split_complex_arg = NULL;
3963 /* Initialize rs6000_cost with the appropriate target costs. */
3965 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
3969 case PROCESSOR_RS64A:
3970 rs6000_cost = &rs64a_cost;
3973 case PROCESSOR_MPCCORE:
3974 rs6000_cost = &mpccore_cost;
3977 case PROCESSOR_PPC403:
3978 rs6000_cost = &ppc403_cost;
3981 case PROCESSOR_PPC405:
3982 rs6000_cost = &ppc405_cost;
3985 case PROCESSOR_PPC440:
3986 rs6000_cost = &ppc440_cost;
3989 case PROCESSOR_PPC476:
3990 rs6000_cost = &ppc476_cost;
3993 case PROCESSOR_PPC601:
3994 rs6000_cost = &ppc601_cost;
3997 case PROCESSOR_PPC603:
3998 rs6000_cost = &ppc603_cost;
4001 case PROCESSOR_PPC604:
4002 rs6000_cost = &ppc604_cost;
4005 case PROCESSOR_PPC604e:
4006 rs6000_cost = &ppc604e_cost;
4009 case PROCESSOR_PPC620:
4010 rs6000_cost = &ppc620_cost;
4013 case PROCESSOR_PPC630:
4014 rs6000_cost = &ppc630_cost;
4017 case PROCESSOR_CELL:
4018 rs6000_cost = &ppccell_cost;
4021 case PROCESSOR_PPC750:
4022 case PROCESSOR_PPC7400:
4023 rs6000_cost = &ppc750_cost;
4026 case PROCESSOR_PPC7450:
4027 rs6000_cost = &ppc7450_cost;
4030 case PROCESSOR_PPC8540:
4031 case PROCESSOR_PPC8548:
4032 rs6000_cost = &ppc8540_cost;
4035 case PROCESSOR_PPCE300C2:
4036 case PROCESSOR_PPCE300C3:
4037 rs6000_cost = &ppce300c2c3_cost;
4040 case PROCESSOR_PPCE500MC:
4041 rs6000_cost = &ppce500mc_cost;
4044 case PROCESSOR_PPCE500MC64:
4045 rs6000_cost = &ppce500mc64_cost;
4048 case PROCESSOR_PPCE5500:
4049 rs6000_cost = &ppce5500_cost;
4052 case PROCESSOR_PPCE6500:
4053 rs6000_cost = &ppce6500_cost;
4056 case PROCESSOR_TITAN:
4057 rs6000_cost = &titan_cost;
4060 case PROCESSOR_POWER4:
4061 case PROCESSOR_POWER5:
4062 rs6000_cost = &power4_cost;
4065 case PROCESSOR_POWER6:
4066 rs6000_cost = &power6_cost;
4069 case PROCESSOR_POWER7:
4070 rs6000_cost = &power7_cost;
4073 case PROCESSOR_POWER8:
4074 rs6000_cost = &power8_cost;
4077 case PROCESSOR_PPCA2:
4078 rs6000_cost = &ppca2_cost;
4087 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES,
4088 rs6000_cost->simultaneous_prefetches,
4089 global_options.x_param_values,
4090 global_options_set.x_param_values);
4091 maybe_set_param_value (PARAM_L1_CACHE_SIZE, rs6000_cost->l1_cache_size,
4092 global_options.x_param_values,
4093 global_options_set.x_param_values);
4094 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE,
4095 rs6000_cost->cache_line_size,
4096 global_options.x_param_values,
4097 global_options_set.x_param_values);
4098 maybe_set_param_value (PARAM_L2_CACHE_SIZE, rs6000_cost->l2_cache_size,
4099 global_options.x_param_values,
4100 global_options_set.x_param_values);
4102 /* Increase loop peeling limits based on performance analysis. */
4103 maybe_set_param_value (PARAM_MAX_PEELED_INSNS, 400,
4104 global_options.x_param_values,
4105 global_options_set.x_param_values);
4106 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 400,
4107 global_options.x_param_values,
4108 global_options_set.x_param_values);
4110 /* If using typedef char *va_list, signal that
4111 __builtin_va_start (&ap, 0) can be optimized to
4112 ap = __builtin_next_arg (0). */
4113 if (DEFAULT_ABI != ABI_V4)
4114 targetm.expand_builtin_va_start = NULL;
4117 /* Set up single/double float flags.
4118 If TARGET_HARD_FLOAT is set, but neither single or double is set,
4119 then set both flags. */
4120 if (TARGET_HARD_FLOAT && TARGET_FPRS
4121 && rs6000_single_float == 0 && rs6000_double_float == 0)
4122 rs6000_single_float = rs6000_double_float = 1;
4124 /* If not explicitly specified via option, decide whether to generate indexed
4125 load/store instructions. */
4126 if (TARGET_AVOID_XFORM == -1)
4127 /* Avoid indexed addressing when targeting Power6 in order to avoid the
4128 DERAT mispredict penalty. However the LVE and STVE altivec instructions
4129 need indexed accesses and the type used is the scalar type of the element
4130 being loaded or stored. */
4131 TARGET_AVOID_XFORM = (rs6000_cpu == PROCESSOR_POWER6 && TARGET_CMPB
4132 && !TARGET_ALTIVEC);
4134 /* Set the -mrecip options. */
4135 if (rs6000_recip_name)
4137 char *p = ASTRDUP (rs6000_recip_name);
4139 unsigned int mask, i;
4142 while ((q = strtok (p, ",")) != NULL)
4153 if (!strcmp (q, "default"))
4154 mask = ((TARGET_RECIP_PRECISION)
4155 ? RECIP_HIGH_PRECISION : RECIP_LOW_PRECISION);
4158 for (i = 0; i < ARRAY_SIZE (recip_options); i++)
4159 if (!strcmp (q, recip_options[i].string))
4161 mask = recip_options[i].mask;
4165 if (i == ARRAY_SIZE (recip_options))
4167 error ("unknown option for -mrecip=%s", q);
4175 rs6000_recip_control &= ~mask;
4177 rs6000_recip_control |= mask;
4181 /* Set the builtin mask of the various options used that could affect which
4182 builtins were used. In the past we used target_flags, but we've run out
4183 of bits, and some options like SPE and PAIRED are no longer in
4185 rs6000_builtin_mask = rs6000_builtin_mask_calculate ();
4186 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
4189 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX ", ",
4190 rs6000_builtin_mask);
4191 rs6000_print_builtin_options (stderr, 0, NULL, rs6000_builtin_mask);
4194 /* Initialize all of the registers. */
4195 rs6000_init_hard_regno_mode_ok (global_init_p);
4197 /* Save the initial options in case the user does function specific options */
4199 target_option_default_node = target_option_current_node
4200 = build_target_option_node (&global_options);
4202 /* If not explicitly specified via option, decide whether to generate the
4203 extra blr's required to preserve the link stack on some cpus (eg, 476). */
4204 if (TARGET_LINK_STACK == -1)
4205 SET_TARGET_LINK_STACK (rs6000_cpu == PROCESSOR_PPC476 && flag_pic);
4210 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
4211 define the target cpu type. */
4214 rs6000_option_override (void)
4216 (void) rs6000_option_override_internal (true);
4218 /* Register machine-specific passes. This needs to be done at start-up.
4219 It's convenient to do it here (like i386 does). */
4220 opt_pass *pass_analyze_swaps = make_pass_analyze_swaps (g);
4222 struct register_pass_info analyze_swaps_info
4223 = { pass_analyze_swaps, "cse1", 1, PASS_POS_INSERT_BEFORE };
4225 register_pass (&analyze_swaps_info);
4229 /* Implement targetm.vectorize.builtin_mask_for_load. */
4231 rs6000_builtin_mask_for_load (void)
4233 if (TARGET_ALTIVEC || TARGET_VSX)
4234 return altivec_builtin_mask_for_load;
4239 /* Implement LOOP_ALIGN. */
4241 rs6000_loop_align (rtx label)
4246 /* Don't override loop alignment if -falign-loops was specified. */
4247 if (!can_override_loop_align)
4248 return align_loops_log;
4250 bb = BLOCK_FOR_INSN (label);
4251 ninsns = num_loop_insns(bb->loop_father);
4253 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
4254 if (ninsns > 4 && ninsns <= 8
4255 && (rs6000_cpu == PROCESSOR_POWER4
4256 || rs6000_cpu == PROCESSOR_POWER5
4257 || rs6000_cpu == PROCESSOR_POWER6
4258 || rs6000_cpu == PROCESSOR_POWER7
4259 || rs6000_cpu == PROCESSOR_POWER8))
4262 return align_loops_log;
4265 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
4267 rs6000_loop_align_max_skip (rtx_insn *label)
4269 return (1 << rs6000_loop_align (label)) - 1;
4272 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4273 after applying N number of iterations. This routine does not determine
4274 how may iterations are required to reach desired alignment. */
4277 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
4284 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
4287 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
4297 /* Assuming that all other types are naturally aligned. CHECKME! */
4302 /* Return true if the vector misalignment factor is supported by the
4305 rs6000_builtin_support_vector_misalignment (machine_mode mode,
4312 /* Return if movmisalign pattern is not supported for this mode. */
4313 if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing)
4316 if (misalignment == -1)
4318 /* Misalignment factor is unknown at compile time but we know
4319 it's word aligned. */
4320 if (rs6000_vector_alignment_reachable (type, is_packed))
4322 int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type));
4324 if (element_size == 64 || element_size == 32)
4331 /* VSX supports word-aligned vector. */
4332 if (misalignment % 4 == 0)
4338 /* Implement targetm.vectorize.builtin_vectorization_cost. */
4340 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
4341 tree vectype, int misalign)
4346 switch (type_of_cost)
4356 case cond_branch_not_taken:
4365 case vec_promote_demote:
4371 case cond_branch_taken:
4374 case unaligned_load:
4375 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
4377 elements = TYPE_VECTOR_SUBPARTS (vectype);
4379 /* Double word aligned. */
4387 /* Double word aligned. */
4391 /* Unknown misalignment. */
4404 /* Misaligned loads are not supported. */
4409 case unaligned_store:
4410 if (TARGET_VSX && TARGET_ALLOW_MOVMISALIGN)
4412 elements = TYPE_VECTOR_SUBPARTS (vectype);
4414 /* Double word aligned. */
4422 /* Double word aligned. */
4426 /* Unknown misalignment. */
4439 /* Misaligned stores are not supported. */
4445 elements = TYPE_VECTOR_SUBPARTS (vectype);
4446 elem_type = TREE_TYPE (vectype);
4447 /* 32-bit vectors loaded into registers are stored as double
4448 precision, so we need n/2 converts in addition to the usual
4449 n/2 merges to construct a vector of short floats from them. */
4450 if (SCALAR_FLOAT_TYPE_P (elem_type)
4451 && TYPE_PRECISION (elem_type) == 32)
4452 return elements + 1;
4454 return elements / 2 + 1;
4461 /* Implement targetm.vectorize.preferred_simd_mode. */
4464 rs6000_preferred_simd_mode (machine_mode mode)
4473 if (TARGET_ALTIVEC || TARGET_VSX)
4499 if (TARGET_PAIRED_FLOAT
4505 typedef struct _rs6000_cost_data
4507 struct loop *loop_info;
4511 /* Test for likely overcommitment of vector hardware resources. If a
4512 loop iteration is relatively large, and too large a percentage of
4513 instructions in the loop are vectorized, the cost model may not
4514 adequately reflect delays from unavailable vector resources.
4515 Penalize the loop body cost for this case. */
4518 rs6000_density_test (rs6000_cost_data *data)
4520 const int DENSITY_PCT_THRESHOLD = 85;
4521 const int DENSITY_SIZE_THRESHOLD = 70;
4522 const int DENSITY_PENALTY = 10;
4523 struct loop *loop = data->loop_info;
4524 basic_block *bbs = get_loop_body (loop);
4525 int nbbs = loop->num_nodes;
4526 int vec_cost = data->cost[vect_body], not_vec_cost = 0;
4529 for (i = 0; i < nbbs; i++)
4531 basic_block bb = bbs[i];
4532 gimple_stmt_iterator gsi;
4534 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
4536 gimple stmt = gsi_stmt (gsi);
4537 stmt_vec_info stmt_info = vinfo_for_stmt (stmt);
4539 if (!STMT_VINFO_RELEVANT_P (stmt_info)
4540 && !STMT_VINFO_IN_PATTERN_P (stmt_info))
4546 density_pct = (vec_cost * 100) / (vec_cost + not_vec_cost);
4548 if (density_pct > DENSITY_PCT_THRESHOLD
4549 && vec_cost + not_vec_cost > DENSITY_SIZE_THRESHOLD)
4551 data->cost[vect_body] = vec_cost * (100 + DENSITY_PENALTY) / 100;
4552 if (dump_enabled_p ())
4553 dump_printf_loc (MSG_NOTE, vect_location,
4554 "density %d%%, cost %d exceeds threshold, penalizing "
4555 "loop body cost by %d%%", density_pct,
4556 vec_cost + not_vec_cost, DENSITY_PENALTY);
4560 /* Implement targetm.vectorize.init_cost. */
4563 rs6000_init_cost (struct loop *loop_info)
4565 rs6000_cost_data *data = XNEW (struct _rs6000_cost_data);
4566 data->loop_info = loop_info;
4567 data->cost[vect_prologue] = 0;
4568 data->cost[vect_body] = 0;
4569 data->cost[vect_epilogue] = 0;
4573 /* Implement targetm.vectorize.add_stmt_cost. */
4576 rs6000_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
4577 struct _stmt_vec_info *stmt_info, int misalign,
4578 enum vect_cost_model_location where)
4580 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
4581 unsigned retval = 0;
4583 if (flag_vect_cost_model)
4585 tree vectype = stmt_info ? stmt_vectype (stmt_info) : NULL_TREE;
4586 int stmt_cost = rs6000_builtin_vectorization_cost (kind, vectype,
4588 /* Statements in an inner loop relative to the loop being
4589 vectorized are weighted more heavily. The value here is
4590 arbitrary and could potentially be improved with analysis. */
4591 if (where == vect_body && stmt_info && stmt_in_inner_loop_p (stmt_info))
4592 count *= 50; /* FIXME. */
4594 retval = (unsigned) (count * stmt_cost);
4595 cost_data->cost[where] += retval;
4601 /* Implement targetm.vectorize.finish_cost. */
4604 rs6000_finish_cost (void *data, unsigned *prologue_cost,
4605 unsigned *body_cost, unsigned *epilogue_cost)
4607 rs6000_cost_data *cost_data = (rs6000_cost_data*) data;
4609 if (cost_data->loop_info)
4610 rs6000_density_test (cost_data);
4612 *prologue_cost = cost_data->cost[vect_prologue];
4613 *body_cost = cost_data->cost[vect_body];
4614 *epilogue_cost = cost_data->cost[vect_epilogue];
4617 /* Implement targetm.vectorize.destroy_cost_data. */
4620 rs6000_destroy_cost_data (void *data)
4625 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4626 library with vectorized intrinsics. */
4629 rs6000_builtin_vectorized_libmass (tree fndecl, tree type_out, tree type_in)
4632 const char *suffix = NULL;
4633 tree fntype, new_fndecl, bdecl = NULL_TREE;
4636 machine_mode el_mode, in_mode;
4639 /* Libmass is suitable for unsafe math only as it does not correctly support
4640 parts of IEEE with the required precision such as denormals. Only support
4641 it if we have VSX to use the simd d2 or f4 functions.
4642 XXX: Add variable length support. */
4643 if (!flag_unsafe_math_optimizations || !TARGET_VSX)
4646 el_mode = TYPE_MODE (TREE_TYPE (type_out));
4647 n = TYPE_VECTOR_SUBPARTS (type_out);
4648 in_mode = TYPE_MODE (TREE_TYPE (type_in));
4649 in_n = TYPE_VECTOR_SUBPARTS (type_in);
4650 if (el_mode != in_mode
4654 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
4656 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
4659 case BUILT_IN_ATAN2:
4660 case BUILT_IN_HYPOT:
4666 case BUILT_IN_ACOSH:
4668 case BUILT_IN_ASINH:
4670 case BUILT_IN_ATANH:
4678 case BUILT_IN_EXPM1:
4679 case BUILT_IN_LGAMMA:
4680 case BUILT_IN_LOG10:
4681 case BUILT_IN_LOG1P:
4689 bdecl = builtin_decl_implicit (fn);
4690 suffix = "d2"; /* pow -> powd2 */
4691 if (el_mode != DFmode
4697 case BUILT_IN_ATAN2F:
4698 case BUILT_IN_HYPOTF:
4703 case BUILT_IN_ACOSF:
4704 case BUILT_IN_ACOSHF:
4705 case BUILT_IN_ASINF:
4706 case BUILT_IN_ASINHF:
4707 case BUILT_IN_ATANF:
4708 case BUILT_IN_ATANHF:
4709 case BUILT_IN_CBRTF:
4711 case BUILT_IN_COSHF:
4713 case BUILT_IN_ERFCF:
4714 case BUILT_IN_EXP2F:
4716 case BUILT_IN_EXPM1F:
4717 case BUILT_IN_LGAMMAF:
4718 case BUILT_IN_LOG10F:
4719 case BUILT_IN_LOG1PF:
4720 case BUILT_IN_LOG2F:
4723 case BUILT_IN_SINHF:
4724 case BUILT_IN_SQRTF:
4726 case BUILT_IN_TANHF:
4727 bdecl = builtin_decl_implicit (fn);
4728 suffix = "4"; /* powf -> powf4 */
4729 if (el_mode != SFmode
4742 gcc_assert (suffix != NULL);
4743 bname = IDENTIFIER_POINTER (DECL_NAME (bdecl));
4747 strcpy (name, bname + sizeof ("__builtin_") - 1);
4748 strcat (name, suffix);
4751 fntype = build_function_type_list (type_out, type_in, NULL);
4752 else if (n_args == 2)
4753 fntype = build_function_type_list (type_out, type_in, type_in, NULL);
4757 /* Build a function declaration for the vectorized function. */
4758 new_fndecl = build_decl (BUILTINS_LOCATION,
4759 FUNCTION_DECL, get_identifier (name), fntype);
4760 TREE_PUBLIC (new_fndecl) = 1;
4761 DECL_EXTERNAL (new_fndecl) = 1;
4762 DECL_IS_NOVOPS (new_fndecl) = 1;
4763 TREE_READONLY (new_fndecl) = 1;
4768 /* Returns a function decl for a vectorized version of the builtin function
4769 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4770 if it is not available. */
4773 rs6000_builtin_vectorized_function (tree fndecl, tree type_out,
4776 machine_mode in_mode, out_mode;
4779 if (TARGET_DEBUG_BUILTIN)
4780 fprintf (stderr, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4781 IDENTIFIER_POINTER (DECL_NAME (fndecl)),
4782 GET_MODE_NAME (TYPE_MODE (type_out)),
4783 GET_MODE_NAME (TYPE_MODE (type_in)));
4785 if (TREE_CODE (type_out) != VECTOR_TYPE
4786 || TREE_CODE (type_in) != VECTOR_TYPE
4787 || !TARGET_VECTORIZE_BUILTINS)
4790 out_mode = TYPE_MODE (TREE_TYPE (type_out));
4791 out_n = TYPE_VECTOR_SUBPARTS (type_out);
4792 in_mode = TYPE_MODE (TREE_TYPE (type_in));
4793 in_n = TYPE_VECTOR_SUBPARTS (type_in);
4795 if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_NORMAL)
4797 enum built_in_function fn = DECL_FUNCTION_CODE (fndecl);
4800 case BUILT_IN_CLZIMAX:
4801 case BUILT_IN_CLZLL:
4804 if (TARGET_P8_VECTOR && in_mode == out_mode && out_n == in_n)
4806 if (out_mode == QImode && out_n == 16)
4807 return rs6000_builtin_decls[P8V_BUILTIN_VCLZB];
4808 else if (out_mode == HImode && out_n == 8)
4809 return rs6000_builtin_decls[P8V_BUILTIN_VCLZH];
4810 else if (out_mode == SImode && out_n == 4)
4811 return rs6000_builtin_decls[P8V_BUILTIN_VCLZW];
4812 else if (out_mode == DImode && out_n == 2)
4813 return rs6000_builtin_decls[P8V_BUILTIN_VCLZD];
4816 case BUILT_IN_COPYSIGN:
4817 if (VECTOR_UNIT_VSX_P (V2DFmode)
4818 && out_mode == DFmode && out_n == 2
4819 && in_mode == DFmode && in_n == 2)
4820 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNDP];
4822 case BUILT_IN_COPYSIGNF:
4823 if (out_mode != SFmode || out_n != 4
4824 || in_mode != SFmode || in_n != 4)
4826 if (VECTOR_UNIT_VSX_P (V4SFmode))
4827 return rs6000_builtin_decls[VSX_BUILTIN_CPSGNSP];
4828 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
4829 return rs6000_builtin_decls[ALTIVEC_BUILTIN_COPYSIGN_V4SF];
4831 case BUILT_IN_POPCOUNTIMAX:
4832 case BUILT_IN_POPCOUNTLL:
4833 case BUILT_IN_POPCOUNTL:
4834 case BUILT_IN_POPCOUNT:
4835 if (TARGET_P8_VECTOR && in_mode == out_mode && out_n == in_n)
4837 if (out_mode == QImode && out_n == 16)
4838 return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTB];
4839 else if (out_mode == HImode && out_n == 8)
4840 return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTH];
4841 else if (out_mode == SImode && out_n == 4)
4842 return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTW];
4843 else if (out_mode == DImode && out_n == 2)
4844 return rs6000_builtin_decls[P8V_BUILTIN_VPOPCNTD];
4848 if (VECTOR_UNIT_VSX_P (V2DFmode)
4849 && out_mode == DFmode && out_n == 2
4850 && in_mode == DFmode && in_n == 2)
4851 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTDP];
4853 case BUILT_IN_SQRTF:
4854 if (VECTOR_UNIT_VSX_P (V4SFmode)
4855 && out_mode == SFmode && out_n == 4
4856 && in_mode == SFmode && in_n == 4)
4857 return rs6000_builtin_decls[VSX_BUILTIN_XVSQRTSP];
4860 if (VECTOR_UNIT_VSX_P (V2DFmode)
4861 && out_mode == DFmode && out_n == 2
4862 && in_mode == DFmode && in_n == 2)
4863 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIP];
4865 case BUILT_IN_CEILF:
4866 if (out_mode != SFmode || out_n != 4
4867 || in_mode != SFmode || in_n != 4)
4869 if (VECTOR_UNIT_VSX_P (V4SFmode))
4870 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIP];
4871 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
4872 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIP];
4874 case BUILT_IN_FLOOR:
4875 if (VECTOR_UNIT_VSX_P (V2DFmode)
4876 && out_mode == DFmode && out_n == 2
4877 && in_mode == DFmode && in_n == 2)
4878 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIM];
4880 case BUILT_IN_FLOORF:
4881 if (out_mode != SFmode || out_n != 4
4882 || in_mode != SFmode || in_n != 4)
4884 if (VECTOR_UNIT_VSX_P (V4SFmode))
4885 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIM];
4886 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
4887 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIM];
4890 if (VECTOR_UNIT_VSX_P (V2DFmode)
4891 && out_mode == DFmode && out_n == 2
4892 && in_mode == DFmode && in_n == 2)
4893 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDDP];
4896 if (VECTOR_UNIT_VSX_P (V4SFmode)
4897 && out_mode == SFmode && out_n == 4
4898 && in_mode == SFmode && in_n == 4)
4899 return rs6000_builtin_decls[VSX_BUILTIN_XVMADDSP];
4900 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode)
4901 && out_mode == SFmode && out_n == 4
4902 && in_mode == SFmode && in_n == 4)
4903 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VMADDFP];
4905 case BUILT_IN_TRUNC:
4906 if (VECTOR_UNIT_VSX_P (V2DFmode)
4907 && out_mode == DFmode && out_n == 2
4908 && in_mode == DFmode && in_n == 2)
4909 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIZ];
4911 case BUILT_IN_TRUNCF:
4912 if (out_mode != SFmode || out_n != 4
4913 || in_mode != SFmode || in_n != 4)
4915 if (VECTOR_UNIT_VSX_P (V4SFmode))
4916 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIZ];
4917 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode))
4918 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRFIZ];
4920 case BUILT_IN_NEARBYINT:
4921 if (VECTOR_UNIT_VSX_P (V2DFmode)
4922 && flag_unsafe_math_optimizations
4923 && out_mode == DFmode && out_n == 2
4924 && in_mode == DFmode && in_n == 2)
4925 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPI];
4927 case BUILT_IN_NEARBYINTF:
4928 if (VECTOR_UNIT_VSX_P (V4SFmode)
4929 && flag_unsafe_math_optimizations
4930 && out_mode == SFmode && out_n == 4
4931 && in_mode == SFmode && in_n == 4)
4932 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPI];
4935 if (VECTOR_UNIT_VSX_P (V2DFmode)
4936 && !flag_trapping_math
4937 && out_mode == DFmode && out_n == 2
4938 && in_mode == DFmode && in_n == 2)
4939 return rs6000_builtin_decls[VSX_BUILTIN_XVRDPIC];
4941 case BUILT_IN_RINTF:
4942 if (VECTOR_UNIT_VSX_P (V4SFmode)
4943 && !flag_trapping_math
4944 && out_mode == SFmode && out_n == 4
4945 && in_mode == SFmode && in_n == 4)
4946 return rs6000_builtin_decls[VSX_BUILTIN_XVRSPIC];
4953 else if (DECL_BUILT_IN_CLASS (fndecl) == BUILT_IN_MD)
4955 enum rs6000_builtins fn
4956 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
4959 case RS6000_BUILTIN_RSQRTF:
4960 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
4961 && out_mode == SFmode && out_n == 4
4962 && in_mode == SFmode && in_n == 4)
4963 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRSQRTFP];
4965 case RS6000_BUILTIN_RSQRT:
4966 if (VECTOR_UNIT_VSX_P (V2DFmode)
4967 && out_mode == DFmode && out_n == 2
4968 && in_mode == DFmode && in_n == 2)
4969 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
4971 case RS6000_BUILTIN_RECIPF:
4972 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
4973 && out_mode == SFmode && out_n == 4
4974 && in_mode == SFmode && in_n == 4)
4975 return rs6000_builtin_decls[ALTIVEC_BUILTIN_VRECIPFP];
4977 case RS6000_BUILTIN_RECIP:
4978 if (VECTOR_UNIT_VSX_P (V2DFmode)
4979 && out_mode == DFmode && out_n == 2
4980 && in_mode == DFmode && in_n == 2)
4981 return rs6000_builtin_decls[VSX_BUILTIN_RECIP_V2DF];
4988 /* Generate calls to libmass if appropriate. */
4989 if (rs6000_veclib_handler)
4990 return rs6000_veclib_handler (fndecl, type_out, type_in);
4995 /* Default CPU string for rs6000*_file_start functions. */
4996 static const char *rs6000_default_cpu;
4998 /* Do anything needed at the start of the asm file. */
5001 rs6000_file_start (void)
5004 const char *start = buffer;
5005 FILE *file = asm_out_file;
5007 rs6000_default_cpu = TARGET_CPU_DEFAULT;
5009 default_file_start ();
5011 if (flag_verbose_asm)
5013 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
5015 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
5017 fprintf (file, "%s --with-cpu=%s", start, rs6000_default_cpu);
5021 if (global_options_set.x_rs6000_cpu_index)
5023 fprintf (file, "%s -mcpu=%s", start,
5024 processor_target_table[rs6000_cpu_index].name);
5028 if (global_options_set.x_rs6000_tune_index)
5030 fprintf (file, "%s -mtune=%s", start,
5031 processor_target_table[rs6000_tune_index].name);
5035 if (PPC405_ERRATUM77)
5037 fprintf (file, "%s PPC405CR_ERRATUM77", start);
5041 #ifdef USING_ELFOS_H
5042 switch (rs6000_sdata)
5044 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
5045 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
5046 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
5047 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
5050 if (rs6000_sdata && g_switch_value)
5052 fprintf (file, "%s -G %d", start,
5062 if (DEFAULT_ABI == ABI_ELFv2)
5063 fprintf (file, "\t.abiversion 2\n");
5065 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2
5066 || (TARGET_ELF && flag_pic == 2))
5068 switch_to_section (toc_section);
5069 switch_to_section (text_section);
5074 /* Return nonzero if this function is known to have a null epilogue. */
5077 direct_return (void)
5079 if (reload_completed)
5081 rs6000_stack_t *info = rs6000_stack_info ();
5083 if (info->first_gp_reg_save == 32
5084 && info->first_fp_reg_save == 64
5085 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
5086 && ! info->lr_save_p
5087 && ! info->cr_save_p
5088 && info->vrsave_mask == 0
5096 /* Return the number of instructions it takes to form a constant in an
5097 integer register. */
5100 num_insns_constant_wide (HOST_WIDE_INT value)
5102 /* signed constant loadable with addi */
5103 if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
5106 /* constant loadable with addis */
5107 else if ((value & 0xffff) == 0
5108 && (value >> 31 == -1 || value >> 31 == 0))
5111 else if (TARGET_POWERPC64)
5113 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
5114 HOST_WIDE_INT high = value >> 31;
5116 if (high == 0 || high == -1)
5122 return num_insns_constant_wide (high) + 1;
5124 return num_insns_constant_wide (low) + 1;
5126 return (num_insns_constant_wide (high)
5127 + num_insns_constant_wide (low) + 1);
5135 num_insns_constant (rtx op, machine_mode mode)
5137 HOST_WIDE_INT low, high;
5139 switch (GET_CODE (op))
5142 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
5143 && mask64_operand (op, mode))
5146 return num_insns_constant_wide (INTVAL (op));
5148 case CONST_WIDE_INT:
5151 int ins = CONST_WIDE_INT_NUNITS (op) - 1;
5152 for (i = 0; i < CONST_WIDE_INT_NUNITS (op); i++)
5153 ins += num_insns_constant_wide (CONST_WIDE_INT_ELT (op, i));
5158 if (mode == SFmode || mode == SDmode)
5163 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
5164 if (DECIMAL_FLOAT_MODE_P (mode))
5165 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
5167 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5168 return num_insns_constant_wide ((HOST_WIDE_INT) l);
5174 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
5175 if (DECIMAL_FLOAT_MODE_P (mode))
5176 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
5178 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
5179 high = l[WORDS_BIG_ENDIAN == 0];
5180 low = l[WORDS_BIG_ENDIAN != 0];
5183 return (num_insns_constant_wide (low)
5184 + num_insns_constant_wide (high));
5187 if ((high == 0 && low >= 0)
5188 || (high == -1 && low < 0))
5189 return num_insns_constant_wide (low);
5191 else if (mask64_operand (op, mode))
5195 return num_insns_constant_wide (high) + 1;
5198 return (num_insns_constant_wide (high)
5199 + num_insns_constant_wide (low) + 1);
5207 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
5208 If the mode of OP is MODE_VECTOR_INT, this simply returns the
5209 corresponding element of the vector, but for V4SFmode and V2SFmode,
5210 the corresponding "float" is interpreted as an SImode integer. */
5213 const_vector_elt_as_int (rtx op, unsigned int elt)
5217 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
5218 gcc_assert (GET_MODE (op) != V2DImode
5219 && GET_MODE (op) != V2DFmode);
5221 tmp = CONST_VECTOR_ELT (op, elt);
5222 if (GET_MODE (op) == V4SFmode
5223 || GET_MODE (op) == V2SFmode)
5224 tmp = gen_lowpart (SImode, tmp);
5225 return INTVAL (tmp);
5228 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
5229 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
5230 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
5231 all items are set to the same value and contain COPIES replicas of the
5232 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
5233 operand and the others are set to the value of the operand's msb. */
5236 vspltis_constant (rtx op, unsigned step, unsigned copies)
5238 machine_mode mode = GET_MODE (op);
5239 machine_mode inner = GET_MODE_INNER (mode);
5247 HOST_WIDE_INT splat_val;
5248 HOST_WIDE_INT msb_val;
5250 if (mode == V2DImode || mode == V2DFmode || mode == V1TImode)
5253 nunits = GET_MODE_NUNITS (mode);
5254 bitsize = GET_MODE_BITSIZE (inner);
5255 mask = GET_MODE_MASK (inner);
5257 val = const_vector_elt_as_int (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
5259 msb_val = val >= 0 ? 0 : -1;
5261 /* Construct the value to be splatted, if possible. If not, return 0. */
5262 for (i = 2; i <= copies; i *= 2)
5264 HOST_WIDE_INT small_val;
5266 small_val = splat_val >> bitsize;
5268 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
5270 splat_val = small_val;
5273 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5274 if (EASY_VECTOR_15 (splat_val))
5277 /* Also check if we can splat, and then add the result to itself. Do so if
5278 the value is positive, of if the splat instruction is using OP's mode;
5279 for splat_val < 0, the splat and the add should use the same mode. */
5280 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
5281 && (splat_val >= 0 || (step == 1 && copies == 1)))
5284 /* Also check if are loading up the most significant bit which can be done by
5285 loading up -1 and shifting the value left by -1. */
5286 else if (EASY_VECTOR_MSB (splat_val, inner))
5292 /* Check if VAL is present in every STEP-th element, and the
5293 other elements are filled with its most significant bit. */
5294 for (i = 1; i < nunits; ++i)
5296 HOST_WIDE_INT desired_val;
5297 unsigned elt = BYTES_BIG_ENDIAN ? nunits - 1 - i : i;
5298 if ((i & (step - 1)) == 0)
5301 desired_val = msb_val;
5303 if (desired_val != const_vector_elt_as_int (op, elt))
5311 /* Return true if OP is of the given MODE and can be synthesized
5312 with a vspltisb, vspltish or vspltisw. */
5315 easy_altivec_constant (rtx op, machine_mode mode)
5317 unsigned step, copies;
5319 if (mode == VOIDmode)
5320 mode = GET_MODE (op);
5321 else if (mode != GET_MODE (op))
5324 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5326 if (mode == V2DFmode)
5327 return zero_constant (op, mode);
5329 else if (mode == V2DImode)
5331 if (GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
5332 || GET_CODE (CONST_VECTOR_ELT (op, 1)) != CONST_INT)
5335 if (zero_constant (op, mode))
5338 if (INTVAL (CONST_VECTOR_ELT (op, 0)) == -1
5339 && INTVAL (CONST_VECTOR_ELT (op, 1)) == -1)
5345 /* V1TImode is a special container for TImode. Ignore for now. */
5346 else if (mode == V1TImode)
5349 /* Start with a vspltisw. */
5350 step = GET_MODE_NUNITS (mode) / 4;
5353 if (vspltis_constant (op, step, copies))
5356 /* Then try with a vspltish. */
5362 if (vspltis_constant (op, step, copies))
5365 /* And finally a vspltisb. */
5371 if (vspltis_constant (op, step, copies))
5377 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
5378 result is OP. Abort if it is not possible. */
5381 gen_easy_altivec_constant (rtx op)
5383 machine_mode mode = GET_MODE (op);
5384 int nunits = GET_MODE_NUNITS (mode);
5385 rtx val = CONST_VECTOR_ELT (op, BYTES_BIG_ENDIAN ? nunits - 1 : 0);
5386 unsigned step = nunits / 4;
5387 unsigned copies = 1;
5389 /* Start with a vspltisw. */
5390 if (vspltis_constant (op, step, copies))
5391 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, val));
5393 /* Then try with a vspltish. */
5399 if (vspltis_constant (op, step, copies))
5400 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, val));
5402 /* And finally a vspltisb. */
5408 if (vspltis_constant (op, step, copies))
5409 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, val));
5415 output_vec_const_move (rtx *operands)
5423 mode = GET_MODE (dest);
5427 if (zero_constant (vec, mode))
5428 return "xxlxor %x0,%x0,%x0";
5430 if ((mode == V2DImode || mode == V1TImode)
5431 && INTVAL (CONST_VECTOR_ELT (vec, 0)) == -1
5432 && INTVAL (CONST_VECTOR_ELT (vec, 1)) == -1)
5433 return "vspltisw %0,-1";
5439 if (zero_constant (vec, mode))
5440 return "vxor %0,%0,%0";
5442 splat_vec = gen_easy_altivec_constant (vec);
5443 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
5444 operands[1] = XEXP (splat_vec, 0);
5445 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
5448 switch (GET_MODE (splat_vec))
5451 return "vspltisw %0,%1";
5454 return "vspltish %0,%1";
5457 return "vspltisb %0,%1";
5464 gcc_assert (TARGET_SPE);
5466 /* Vector constant 0 is handled as a splitter of V2SI, and in the
5467 pattern of V1DI, V4HI, and V2SF.
5469 FIXME: We should probably return # and add post reload
5470 splitters for these, but this way is so easy ;-). */
5471 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
5472 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
5473 operands[1] = CONST_VECTOR_ELT (vec, 0);
5474 operands[2] = CONST_VECTOR_ELT (vec, 1);
5476 return "li %0,%1\n\tevmergelo %0,%0,%0";
5477 else if (WORDS_BIG_ENDIAN)
5478 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
5480 return "li %0,%2\n\tevmergelo %0,%0,%0\n\tli %0,%1";
5483 /* Initialize TARGET of vector PAIRED to VALS. */
5486 paired_expand_vector_init (rtx target, rtx vals)
5488 machine_mode mode = GET_MODE (target);
5489 int n_elts = GET_MODE_NUNITS (mode);
5491 rtx x, new_rtx, tmp, constant_op, op1, op2;
5494 for (i = 0; i < n_elts; ++i)
5496 x = XVECEXP (vals, 0, i);
5497 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
5502 /* Load from constant pool. */
5503 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
5509 /* The vector is initialized only with non-constants. */
5510 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
5511 XVECEXP (vals, 0, 1));
5513 emit_move_insn (target, new_rtx);
5517 /* One field is non-constant and the other one is a constant. Load the
5518 constant from the constant pool and use ps_merge instruction to
5519 construct the whole vector. */
5520 op1 = XVECEXP (vals, 0, 0);
5521 op2 = XVECEXP (vals, 0, 1);
5523 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
5525 tmp = gen_reg_rtx (GET_MODE (constant_op));
5526 emit_move_insn (tmp, constant_op);
5528 if (CONSTANT_P (op1))
5529 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
5531 new_rtx = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
5533 emit_move_insn (target, new_rtx);
5537 paired_expand_vector_move (rtx operands[])
5539 rtx op0 = operands[0], op1 = operands[1];
5541 emit_move_insn (op0, op1);
5544 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
5545 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
5546 operands for the relation operation COND. This is a recursive
5550 paired_emit_vector_compare (enum rtx_code rcode,
5551 rtx dest, rtx op0, rtx op1,
5552 rtx cc_op0, rtx cc_op1)
5554 rtx tmp = gen_reg_rtx (V2SFmode);
5557 gcc_assert (TARGET_PAIRED_FLOAT);
5558 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
5564 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
5568 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
5569 emit_insn (gen_selv2sf4 (dest, tmp, op0, op1, CONST0_RTX (SFmode)));
5573 paired_emit_vector_compare (GE, dest, op0, op1, cc_op1, cc_op0);
5576 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
5579 tmp1 = gen_reg_rtx (V2SFmode);
5580 max = gen_reg_rtx (V2SFmode);
5581 min = gen_reg_rtx (V2SFmode);
5582 gen_reg_rtx (V2SFmode);
5584 emit_insn (gen_subv2sf3 (tmp, cc_op0, cc_op1));
5585 emit_insn (gen_selv2sf4
5586 (max, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
5587 emit_insn (gen_subv2sf3 (tmp, cc_op1, cc_op0));
5588 emit_insn (gen_selv2sf4
5589 (min, tmp, cc_op0, cc_op1, CONST0_RTX (SFmode)));
5590 emit_insn (gen_subv2sf3 (tmp1, min, max));
5591 emit_insn (gen_selv2sf4 (dest, tmp1, op0, op1, CONST0_RTX (SFmode)));
5594 paired_emit_vector_compare (EQ, dest, op1, op0, cc_op0, cc_op1);
5597 paired_emit_vector_compare (LE, dest, op1, op0, cc_op0, cc_op1);
5600 paired_emit_vector_compare (LT, dest, op1, op0, cc_op0, cc_op1);
5603 paired_emit_vector_compare (GE, dest, op1, op0, cc_op0, cc_op1);
5606 paired_emit_vector_compare (GT, dest, op1, op0, cc_op0, cc_op1);
5615 /* Emit vector conditional expression.
5616 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5617 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5620 paired_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
5621 rtx cond, rtx cc_op0, rtx cc_op1)
5623 enum rtx_code rcode = GET_CODE (cond);
5625 if (!TARGET_PAIRED_FLOAT)
5628 paired_emit_vector_compare (rcode, dest, op1, op2, cc_op0, cc_op1);
5633 /* Initialize vector TARGET to VALS. */
5636 rs6000_expand_vector_init (rtx target, rtx vals)
5638 machine_mode mode = GET_MODE (target);
5639 machine_mode inner_mode = GET_MODE_INNER (mode);
5640 int n_elts = GET_MODE_NUNITS (mode);
5641 int n_var = 0, one_var = -1;
5642 bool all_same = true, all_const_zero = true;
5646 for (i = 0; i < n_elts; ++i)
5648 x = XVECEXP (vals, 0, i);
5649 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x)))
5650 ++n_var, one_var = i;
5651 else if (x != CONST0_RTX (inner_mode))
5652 all_const_zero = false;
5654 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
5660 rtx const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0));
5661 bool int_vector_p = (GET_MODE_CLASS (mode) == MODE_VECTOR_INT);
5662 if ((int_vector_p || TARGET_VSX) && all_const_zero)
5664 /* Zero register. */
5665 emit_insn (gen_rtx_SET (VOIDmode, target,
5666 gen_rtx_XOR (mode, target, target)));
5669 else if (int_vector_p && easy_vector_constant (const_vec, mode))
5671 /* Splat immediate. */
5672 emit_insn (gen_rtx_SET (VOIDmode, target, const_vec));
5677 /* Load from constant pool. */
5678 emit_move_insn (target, const_vec);
5683 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5684 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
5686 rtx op0 = XVECEXP (vals, 0, 0);
5687 rtx op1 = XVECEXP (vals, 0, 1);
5690 if (!MEM_P (op0) && !REG_P (op0))
5691 op0 = force_reg (inner_mode, op0);
5692 if (mode == V2DFmode)
5693 emit_insn (gen_vsx_splat_v2df (target, op0));
5695 emit_insn (gen_vsx_splat_v2di (target, op0));
5699 op0 = force_reg (inner_mode, op0);
5700 op1 = force_reg (inner_mode, op1);
5701 if (mode == V2DFmode)
5702 emit_insn (gen_vsx_concat_v2df (target, op0, op1));
5704 emit_insn (gen_vsx_concat_v2di (target, op0, op1));
5709 /* With single precision floating point on VSX, know that internally single
5710 precision is actually represented as a double, and either make 2 V2DF
5711 vectors, and convert these vectors to single precision, or do one
5712 conversion, and splat the result to the other elements. */
5713 if (mode == V4SFmode && VECTOR_MEM_VSX_P (mode))
5717 rtx freg = gen_reg_rtx (V4SFmode);
5718 rtx sreg = force_reg (SFmode, XVECEXP (vals, 0, 0));
5719 rtx cvt = ((TARGET_XSCVDPSPN)
5720 ? gen_vsx_xscvdpspn_scalar (freg, sreg)
5721 : gen_vsx_xscvdpsp_scalar (freg, sreg));
5724 emit_insn (gen_vsx_xxspltw_v4sf_direct (target, freg, const0_rtx));
5728 rtx dbl_even = gen_reg_rtx (V2DFmode);
5729 rtx dbl_odd = gen_reg_rtx (V2DFmode);
5730 rtx flt_even = gen_reg_rtx (V4SFmode);
5731 rtx flt_odd = gen_reg_rtx (V4SFmode);
5732 rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
5733 rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
5734 rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
5735 rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
5737 emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
5738 emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
5739 emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
5740 emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
5741 rs6000_expand_extract_even (target, flt_even, flt_odd);
5746 /* Store value to stack temp. Load vector element. Splat. However, splat
5747 of 64-bit items is not supported on Altivec. */
5748 if (all_same && GET_MODE_SIZE (inner_mode) <= 4)
5750 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
5751 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
5752 XVECEXP (vals, 0, 0));
5753 x = gen_rtx_UNSPEC (VOIDmode,
5754 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
5755 emit_insn (gen_rtx_PARALLEL (VOIDmode,
5757 gen_rtx_SET (VOIDmode,
5760 x = gen_rtx_VEC_SELECT (inner_mode, target,
5761 gen_rtx_PARALLEL (VOIDmode,
5762 gen_rtvec (1, const0_rtx)));
5763 emit_insn (gen_rtx_SET (VOIDmode, target,
5764 gen_rtx_VEC_DUPLICATE (mode, x)));
5768 /* One field is non-constant. Load constant then overwrite
5772 rtx copy = copy_rtx (vals);
5774 /* Load constant part of vector, substitute neighboring value for
5776 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
5777 rs6000_expand_vector_init (target, copy);
5779 /* Insert variable. */
5780 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
5784 /* Construct the vector in memory one field at a time
5785 and load the whole vector. */
5786 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
5787 for (i = 0; i < n_elts; i++)
5788 emit_move_insn (adjust_address_nv (mem, inner_mode,
5789 i * GET_MODE_SIZE (inner_mode)),
5790 XVECEXP (vals, 0, i));
5791 emit_move_insn (target, mem);
5794 /* Set field ELT of TARGET to VAL. */
5797 rs6000_expand_vector_set (rtx target, rtx val, int elt)
5799 machine_mode mode = GET_MODE (target);
5800 machine_mode inner_mode = GET_MODE_INNER (mode);
5801 rtx reg = gen_reg_rtx (mode);
5803 int width = GET_MODE_SIZE (inner_mode);
5806 if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
5808 rtx (*set_func) (rtx, rtx, rtx, rtx)
5809 = ((mode == V2DFmode) ? gen_vsx_set_v2df : gen_vsx_set_v2di);
5810 emit_insn (set_func (target, target, val, GEN_INT (elt)));
5814 /* Simplify setting single element vectors like V1TImode. */
5815 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE (inner_mode) && elt == 0)
5817 emit_move_insn (target, gen_lowpart (mode, val));
5821 /* Load single variable value. */
5822 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode));
5823 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
5824 x = gen_rtx_UNSPEC (VOIDmode,
5825 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
5826 emit_insn (gen_rtx_PARALLEL (VOIDmode,
5828 gen_rtx_SET (VOIDmode,
5832 /* Linear sequence. */
5833 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
5834 for (i = 0; i < 16; ++i)
5835 XVECEXP (mask, 0, i) = GEN_INT (i);
5837 /* Set permute mask to insert element into target. */
5838 for (i = 0; i < width; ++i)
5839 XVECEXP (mask, 0, elt*width + i)
5840 = GEN_INT (i + 0x10);
5841 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
5843 if (BYTES_BIG_ENDIAN)
5844 x = gen_rtx_UNSPEC (mode,
5845 gen_rtvec (3, target, reg,
5846 force_reg (V16QImode, x)),
5850 /* Invert selector. We prefer to generate VNAND on P8 so
5851 that future fusion opportunities can kick in, but must
5852 generate VNOR elsewhere. */
5853 rtx notx = gen_rtx_NOT (V16QImode, force_reg (V16QImode, x));
5854 rtx iorx = (TARGET_P8_VECTOR
5855 ? gen_rtx_IOR (V16QImode, notx, notx)
5856 : gen_rtx_AND (V16QImode, notx, notx));
5857 rtx tmp = gen_reg_rtx (V16QImode);
5858 emit_insn (gen_rtx_SET (VOIDmode, tmp, iorx));
5860 /* Permute with operands reversed and adjusted selector. */
5861 x = gen_rtx_UNSPEC (mode, gen_rtvec (3, reg, target, tmp),
5865 emit_insn (gen_rtx_SET (VOIDmode, target, x));
5868 /* Extract field ELT from VEC into TARGET. */
5871 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
5873 machine_mode mode = GET_MODE (vec);
5874 machine_mode inner_mode = GET_MODE_INNER (mode);
5877 if (VECTOR_MEM_VSX_P (mode))
5884 gcc_assert (elt == 0 && inner_mode == TImode);
5885 emit_move_insn (target, gen_lowpart (TImode, vec));
5888 emit_insn (gen_vsx_extract_v2df (target, vec, GEN_INT (elt)));
5891 emit_insn (gen_vsx_extract_v2di (target, vec, GEN_INT (elt)));
5894 emit_insn (gen_vsx_extract_v4sf (target, vec, GEN_INT (elt)));
5899 /* Allocate mode-sized buffer. */
5900 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode));
5902 emit_move_insn (mem, vec);
5904 /* Add offset to field within buffer matching vector element. */
5905 mem = adjust_address_nv (mem, inner_mode, elt * GET_MODE_SIZE (inner_mode));
5907 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
5910 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
5911 implement ANDing by the mask IN. */
5913 build_mask64_2_operands (rtx in, rtx *out)
5915 unsigned HOST_WIDE_INT c, lsb, m1, m2;
5918 gcc_assert (GET_CODE (in) == CONST_INT);
5923 /* Assume c initially something like 0x00fff000000fffff. The idea
5924 is to rotate the word so that the middle ^^^^^^ group of zeros
5925 is at the MS end and can be cleared with an rldicl mask. We then
5926 rotate back and clear off the MS ^^ group of zeros with a
5928 c = ~c; /* c == 0xff000ffffff00000 */
5929 lsb = c & -c; /* lsb == 0x0000000000100000 */
5930 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
5931 c = ~c; /* c == 0x00fff000000fffff */
5932 c &= -lsb; /* c == 0x00fff00000000000 */
5933 lsb = c & -c; /* lsb == 0x0000100000000000 */
5934 c = ~c; /* c == 0xff000fffffffffff */
5935 c &= -lsb; /* c == 0xff00000000000000 */
5937 while ((lsb >>= 1) != 0)
5938 shift++; /* shift == 44 on exit from loop */
5939 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
5940 m1 = ~m1; /* m1 == 0x000000ffffffffff */
5941 m2 = ~c; /* m2 == 0x00ffffffffffffff */
5945 /* Assume c initially something like 0xff000f0000000000. The idea
5946 is to rotate the word so that the ^^^ middle group of zeros
5947 is at the LS end and can be cleared with an rldicr mask. We then
5948 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
5950 lsb = c & -c; /* lsb == 0x0000010000000000 */
5951 m2 = -lsb; /* m2 == 0xffffff0000000000 */
5952 c = ~c; /* c == 0x00fff0ffffffffff */
5953 c &= -lsb; /* c == 0x00fff00000000000 */
5954 lsb = c & -c; /* lsb == 0x0000100000000000 */
5955 c = ~c; /* c == 0xff000fffffffffff */
5956 c &= -lsb; /* c == 0xff00000000000000 */
5958 while ((lsb >>= 1) != 0)
5959 shift++; /* shift == 44 on exit from loop */
5960 m1 = ~c; /* m1 == 0x00ffffffffffffff */
5961 m1 >>= shift; /* m1 == 0x0000000000000fff */
5962 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
5965 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
5966 masks will be all 1's. We are guaranteed more than one transition. */
5967 out[0] = GEN_INT (64 - shift);
5968 out[1] = GEN_INT (m1);
5969 out[2] = GEN_INT (shift);
5970 out[3] = GEN_INT (m2);
5973 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
5976 invalid_e500_subreg (rtx op, machine_mode mode)
5978 if (TARGET_E500_DOUBLE)
5980 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
5981 subreg:TI and reg:TF. Decimal float modes are like integer
5982 modes (only low part of each register used) for this
5984 if (GET_CODE (op) == SUBREG
5985 && (mode == SImode || mode == DImode || mode == TImode
5986 || mode == DDmode || mode == TDmode || mode == PTImode)
5987 && REG_P (SUBREG_REG (op))
5988 && (GET_MODE (SUBREG_REG (op)) == DFmode
5989 || GET_MODE (SUBREG_REG (op)) == TFmode))
5992 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
5994 if (GET_CODE (op) == SUBREG
5995 && (mode == DFmode || mode == TFmode)
5996 && REG_P (SUBREG_REG (op))
5997 && (GET_MODE (SUBREG_REG (op)) == DImode
5998 || GET_MODE (SUBREG_REG (op)) == TImode
5999 || GET_MODE (SUBREG_REG (op)) == PTImode
6000 || GET_MODE (SUBREG_REG (op)) == DDmode
6001 || GET_MODE (SUBREG_REG (op)) == TDmode))
6006 && GET_CODE (op) == SUBREG
6008 && REG_P (SUBREG_REG (op))
6009 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
6015 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
6016 selects whether the alignment is abi mandated, optional, or
6017 both abi and optional alignment. */
6020 rs6000_data_alignment (tree type, unsigned int align, enum data_align how)
6022 if (how != align_opt)
6024 if (TREE_CODE (type) == VECTOR_TYPE)
6026 if ((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (type)))
6027 || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (type))))
6032 else if (align < 128)
6035 else if (TARGET_E500_DOUBLE
6036 && TREE_CODE (type) == REAL_TYPE
6037 && TYPE_MODE (type) == DFmode)
6044 if (how != align_abi)
6046 if (TREE_CODE (type) == ARRAY_TYPE
6047 && TYPE_MODE (TREE_TYPE (type)) == QImode)
6049 if (align < BITS_PER_WORD)
6050 align = BITS_PER_WORD;
6057 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
6060 rs6000_special_adjust_field_align_p (tree field, unsigned int computed)
6062 if (TARGET_ALTIVEC && TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
6064 if (computed != 128)
6067 if (!warned && warn_psabi)
6070 inform (input_location,
6071 "the layout of aggregates containing vectors with"
6072 " %d-byte alignment has changed in GCC 5",
6073 computed / BITS_PER_UNIT);
6076 /* In current GCC there is no special case. */
6083 /* AIX increases natural record alignment to doubleword if the first
6084 field is an FP double while the FP fields remain word aligned. */
6087 rs6000_special_round_type_align (tree type, unsigned int computed,
6088 unsigned int specified)
6090 unsigned int align = MAX (computed, specified);
6091 tree field = TYPE_FIELDS (type);
6093 /* Skip all non field decls */
6094 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
6095 field = DECL_CHAIN (field);
6097 if (field != NULL && field != type)
6099 type = TREE_TYPE (field);
6100 while (TREE_CODE (type) == ARRAY_TYPE)
6101 type = TREE_TYPE (type);
6103 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
6104 align = MAX (align, 64);
6110 /* Darwin increases record alignment to the natural alignment of
6114 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
6115 unsigned int specified)
6117 unsigned int align = MAX (computed, specified);
6119 if (TYPE_PACKED (type))
6122 /* Find the first field, looking down into aggregates. */
6124 tree field = TYPE_FIELDS (type);
6125 /* Skip all non field decls */
6126 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
6127 field = DECL_CHAIN (field);
6130 /* A packed field does not contribute any extra alignment. */
6131 if (DECL_PACKED (field))
6133 type = TREE_TYPE (field);
6134 while (TREE_CODE (type) == ARRAY_TYPE)
6135 type = TREE_TYPE (type);
6136 } while (AGGREGATE_TYPE_P (type));
6138 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
6139 align = MAX (align, TYPE_ALIGN (type));
6144 /* Return 1 for an operand in small memory on V.4/eabi. */
6147 small_data_operand (rtx op ATTRIBUTE_UNUSED,
6148 machine_mode mode ATTRIBUTE_UNUSED)
6153 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
6156 if (DEFAULT_ABI != ABI_V4)
6159 /* Vector and float memory instructions have a limited offset on the
6160 SPE, so using a vector or float variable directly as an operand is
6163 && (SPE_VECTOR_MODE (mode) || FLOAT_MODE_P (mode)))
6166 if (GET_CODE (op) == SYMBOL_REF)
6169 else if (GET_CODE (op) != CONST
6170 || GET_CODE (XEXP (op, 0)) != PLUS
6171 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
6172 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
6177 rtx sum = XEXP (op, 0);
6178 HOST_WIDE_INT summand;
6180 /* We have to be careful here, because it is the referenced address
6181 that must be 32k from _SDA_BASE_, not just the symbol. */
6182 summand = INTVAL (XEXP (sum, 1));
6183 if (summand < 0 || summand > g_switch_value)
6186 sym_ref = XEXP (sum, 0);
6189 return SYMBOL_REF_SMALL_P (sym_ref);
6195 /* Return true if either operand is a general purpose register. */
6198 gpr_or_gpr_p (rtx op0, rtx op1)
6200 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
6201 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
6204 /* Return true if this is a move direct operation between GPR registers and
6205 floating point/VSX registers. */
6208 direct_move_p (rtx op0, rtx op1)
6212 if (!REG_P (op0) || !REG_P (op1))
6215 if (!TARGET_DIRECT_MOVE && !TARGET_MFPGPR)
6218 regno0 = REGNO (op0);
6219 regno1 = REGNO (op1);
6220 if (regno0 >= FIRST_PSEUDO_REGISTER || regno1 >= FIRST_PSEUDO_REGISTER)
6223 if (INT_REGNO_P (regno0))
6224 return (TARGET_DIRECT_MOVE) ? VSX_REGNO_P (regno1) : FP_REGNO_P (regno1);
6226 else if (INT_REGNO_P (regno1))
6228 if (TARGET_MFPGPR && FP_REGNO_P (regno0))
6231 else if (TARGET_DIRECT_MOVE && VSX_REGNO_P (regno0))
6238 /* Return true if this is a load or store quad operation. This function does
6239 not handle the atomic quad memory instructions. */
6242 quad_load_store_p (rtx op0, rtx op1)
6246 if (!TARGET_QUAD_MEMORY)
6249 else if (REG_P (op0) && MEM_P (op1))
6250 ret = (quad_int_reg_operand (op0, GET_MODE (op0))
6251 && quad_memory_operand (op1, GET_MODE (op1))
6252 && !reg_overlap_mentioned_p (op0, op1));
6254 else if (MEM_P (op0) && REG_P (op1))
6255 ret = (quad_memory_operand (op0, GET_MODE (op0))
6256 && quad_int_reg_operand (op1, GET_MODE (op1)));
6261 if (TARGET_DEBUG_ADDR)
6263 fprintf (stderr, "\n========== quad_load_store, return %s\n",
6264 ret ? "true" : "false");
6265 debug_rtx (gen_rtx_SET (VOIDmode, op0, op1));
6271 /* Given an address, return a constant offset term if one exists. */
6274 address_offset (rtx op)
6276 if (GET_CODE (op) == PRE_INC
6277 || GET_CODE (op) == PRE_DEC)
6279 else if (GET_CODE (op) == PRE_MODIFY
6280 || GET_CODE (op) == LO_SUM)
6283 if (GET_CODE (op) == CONST)
6286 if (GET_CODE (op) == PLUS)
6289 if (CONST_INT_P (op))
6295 /* Return true if the MEM operand is a memory operand suitable for use
6296 with a (full width, possibly multiple) gpr load/store. On
6297 powerpc64 this means the offset must be divisible by 4.
6298 Implements 'Y' constraint.
6300 Accept direct, indexed, offset, lo_sum and tocref. Since this is
6301 a constraint function we know the operand has satisfied a suitable
6302 memory predicate. Also accept some odd rtl generated by reload
6303 (see rs6000_legitimize_reload_address for various forms). It is
6304 important that reload rtl be accepted by appropriate constraints
6305 but not by the operand predicate.
6307 Offsetting a lo_sum should not be allowed, except where we know by
6308 alignment that a 32k boundary is not crossed, but see the ???
6309 comment in rs6000_legitimize_reload_address. Note that by
6310 "offsetting" here we mean a further offset to access parts of the
6311 MEM. It's fine to have a lo_sum where the inner address is offset
6312 from a sym, since the same sym+offset will appear in the high part
6313 of the address calculation. */
6316 mem_operand_gpr (rtx op, machine_mode mode)
6318 unsigned HOST_WIDE_INT offset;
6320 rtx addr = XEXP (op, 0);
6322 op = address_offset (addr);
6326 offset = INTVAL (op);
6327 if (TARGET_POWERPC64 && (offset & 3) != 0)
6330 extra = GET_MODE_SIZE (mode) - UNITS_PER_WORD;
6334 if (GET_CODE (addr) == LO_SUM)
6335 /* For lo_sum addresses, we must allow any offset except one that
6336 causes a wrap, so test only the low 16 bits. */
6337 offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
6339 return offset + 0x8000 < 0x10000u - extra;
6342 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
6345 reg_offset_addressing_ok_p (machine_mode mode)
6357 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
6358 TImode is not a vector mode, if we want to use the VSX registers to
6359 move it around, we need to restrict ourselves to reg+reg
6361 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
6369 /* Paired vector modes. Only reg+reg addressing is valid. */
6370 if (TARGET_PAIRED_FLOAT)
6375 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
6376 addressing for the LFIWZX and STFIWX instructions. */
6377 if (TARGET_NO_SDMODE_STACK)
6389 virtual_stack_registers_memory_p (rtx op)
6393 if (GET_CODE (op) == REG)
6394 regnum = REGNO (op);
6396 else if (GET_CODE (op) == PLUS
6397 && GET_CODE (XEXP (op, 0)) == REG
6398 && GET_CODE (XEXP (op, 1)) == CONST_INT)
6399 regnum = REGNO (XEXP (op, 0));
6404 return (regnum >= FIRST_VIRTUAL_REGISTER
6405 && regnum <= LAST_VIRTUAL_POINTER_REGISTER);
6408 /* Return true if a MODE sized memory accesses to OP plus OFFSET
6409 is known to not straddle a 32k boundary. */
6412 offsettable_ok_by_alignment (rtx op, HOST_WIDE_INT offset,
6416 unsigned HOST_WIDE_INT dsize, dalign, lsb, mask;
6418 if (GET_CODE (op) != SYMBOL_REF)
6421 dsize = GET_MODE_SIZE (mode);
6422 decl = SYMBOL_REF_DECL (op);
6428 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
6429 replacing memory addresses with an anchor plus offset. We
6430 could find the decl by rummaging around in the block->objects
6431 VEC for the given offset but that seems like too much work. */
6432 dalign = BITS_PER_UNIT;
6433 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op)
6434 && SYMBOL_REF_ANCHOR_P (op)
6435 && SYMBOL_REF_BLOCK (op) != NULL)
6437 struct object_block *block = SYMBOL_REF_BLOCK (op);
6439 dalign = block->alignment;
6440 offset += SYMBOL_REF_BLOCK_OFFSET (op);
6442 else if (CONSTANT_POOL_ADDRESS_P (op))
6444 /* It would be nice to have get_pool_align().. */
6445 machine_mode cmode = get_pool_mode (op);
6447 dalign = GET_MODE_ALIGNMENT (cmode);
6450 else if (DECL_P (decl))
6452 dalign = DECL_ALIGN (decl);
6456 /* Allow BLKmode when the entire object is known to not
6457 cross a 32k boundary. */
6458 if (!DECL_SIZE_UNIT (decl))
6461 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl)))
6464 dsize = tree_to_uhwi (DECL_SIZE_UNIT (decl));
6468 return dalign / BITS_PER_UNIT >= dsize;
6473 type = TREE_TYPE (decl);
6475 dalign = TYPE_ALIGN (type);
6476 if (CONSTANT_CLASS_P (decl))
6477 dalign = CONSTANT_ALIGNMENT (decl, dalign);
6479 dalign = DATA_ALIGNMENT (decl, dalign);
6483 /* BLKmode, check the entire object. */
6484 if (TREE_CODE (decl) == STRING_CST)
6485 dsize = TREE_STRING_LENGTH (decl);
6486 else if (TYPE_SIZE_UNIT (type)
6487 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type)))
6488 dsize = tree_to_uhwi (TYPE_SIZE_UNIT (type));
6494 return dalign / BITS_PER_UNIT >= dsize;
6498 /* Find how many bits of the alignment we know for this access. */
6499 mask = dalign / BITS_PER_UNIT - 1;
6500 lsb = offset & -offset;
6504 return dalign >= dsize;
6508 constant_pool_expr_p (rtx op)
6512 split_const (op, &base, &offset);
6513 return (GET_CODE (base) == SYMBOL_REF
6514 && CONSTANT_POOL_ADDRESS_P (base)
6515 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base), Pmode));
6518 static const_rtx tocrel_base, tocrel_offset;
6520 /* Return true if OP is a toc pointer relative address (the output
6521 of create_TOC_reference). If STRICT, do not match high part or
6522 non-split -mcmodel=large/medium toc pointer relative addresses. */
6525 toc_relative_expr_p (const_rtx op, bool strict)
6530 if (TARGET_CMODEL != CMODEL_SMALL)
6532 /* Only match the low part. */
6533 if (GET_CODE (op) == LO_SUM
6534 && REG_P (XEXP (op, 0))
6535 && INT_REG_OK_FOR_BASE_P (XEXP (op, 0), strict))
6542 tocrel_offset = const0_rtx;
6543 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), GET_MODE (op)))
6545 tocrel_base = XEXP (op, 0);
6546 tocrel_offset = XEXP (op, 1);
6549 return (GET_CODE (tocrel_base) == UNSPEC
6550 && XINT (tocrel_base, 1) == UNSPEC_TOCREL);
6553 /* Return true if X is a constant pool address, and also for cmodel=medium
6554 if X is a toc-relative address known to be offsettable within MODE. */
6557 legitimate_constant_pool_address_p (const_rtx x, machine_mode mode,
6560 return (toc_relative_expr_p (x, strict)
6561 && (TARGET_CMODEL != CMODEL_MEDIUM
6562 || constant_pool_expr_p (XVECEXP (tocrel_base, 0, 0))
6564 || offsettable_ok_by_alignment (XVECEXP (tocrel_base, 0, 0),
6565 INTVAL (tocrel_offset), mode)));
6569 legitimate_small_data_p (machine_mode mode, rtx x)
6571 return (DEFAULT_ABI == ABI_V4
6572 && !flag_pic && !TARGET_TOC
6573 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
6574 && small_data_operand (x, mode));
6577 /* SPE offset addressing is limited to 5-bits worth of double words. */
6578 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
6581 rs6000_legitimate_offset_address_p (machine_mode mode, rtx x,
6582 bool strict, bool worst_case)
6584 unsigned HOST_WIDE_INT offset;
6587 if (GET_CODE (x) != PLUS)
6589 if (!REG_P (XEXP (x, 0)))
6591 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
6593 if (!reg_offset_addressing_ok_p (mode))
6594 return virtual_stack_registers_memory_p (x);
6595 if (legitimate_constant_pool_address_p (x, mode, strict || lra_in_progress))
6597 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6600 offset = INTVAL (XEXP (x, 1));
6608 /* SPE vector modes. */
6609 return SPE_CONST_OFFSET_OK (offset);
6614 /* On e500v2, we may have:
6616 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
6618 Which gets addressed with evldd instructions. */
6619 if (TARGET_E500_DOUBLE)
6620 return SPE_CONST_OFFSET_OK (offset);
6622 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
6624 if (VECTOR_MEM_VSX_P (mode))
6629 if (!TARGET_POWERPC64)
6631 else if (offset & 3)
6636 if (TARGET_E500_DOUBLE)
6637 return (SPE_CONST_OFFSET_OK (offset)
6638 && SPE_CONST_OFFSET_OK (offset + 8));
6647 if (!TARGET_POWERPC64)
6649 else if (offset & 3)
6658 return offset < 0x10000 - extra;
6662 legitimate_indexed_address_p (rtx x, int strict)
6666 if (GET_CODE (x) != PLUS)
6672 /* Recognize the rtl generated by reload which we know will later be
6673 replaced with proper base and index regs. */
6675 && reload_in_progress
6676 && (REG_P (op0) || GET_CODE (op0) == PLUS)
6680 return (REG_P (op0) && REG_P (op1)
6681 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
6682 && INT_REG_OK_FOR_INDEX_P (op1, strict))
6683 || (INT_REG_OK_FOR_BASE_P (op1, strict)
6684 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
6688 avoiding_indexed_address_p (machine_mode mode)
6690 /* Avoid indexed addressing for modes that have non-indexed
6691 load/store instruction forms. */
6692 return (TARGET_AVOID_XFORM && VECTOR_MEM_NONE_P (mode));
6696 legitimate_indirect_address_p (rtx x, int strict)
6698 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
6702 macho_lo_sum_memory_operand (rtx x, machine_mode mode)
6704 if (!TARGET_MACHO || !flag_pic
6705 || mode != SImode || GET_CODE (x) != MEM)
6709 if (GET_CODE (x) != LO_SUM)
6711 if (GET_CODE (XEXP (x, 0)) != REG)
6713 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
6717 return CONSTANT_P (x);
6721 legitimate_lo_sum_address_p (machine_mode mode, rtx x, int strict)
6723 if (GET_CODE (x) != LO_SUM)
6725 if (GET_CODE (XEXP (x, 0)) != REG)
6727 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
6729 /* Restrict addressing for DI because of our SUBREG hackery. */
6730 if (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
6734 if (TARGET_ELF || TARGET_MACHO)
6738 if (DEFAULT_ABI == ABI_V4 && flag_pic)
6740 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
6741 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
6742 recognizes some LO_SUM addresses as valid although this
6743 function says opposite. In most cases, LRA through different
6744 transformations can generate correct code for address reloads.
6745 It can not manage only some LO_SUM cases. So we need to add
6746 code analogous to one in rs6000_legitimize_reload_address for
6747 LOW_SUM here saying that some addresses are still valid. */
6748 large_toc_ok = (lra_in_progress && TARGET_CMODEL != CMODEL_SMALL
6749 && small_toc_ref (x, VOIDmode));
6750 if (TARGET_TOC && ! large_toc_ok)
6752 if (GET_MODE_NUNITS (mode) != 1)
6754 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
6755 && !(/* ??? Assume floating point reg based on mode? */
6756 TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6757 && (mode == DFmode || mode == DDmode)))
6760 return CONSTANT_P (x) || large_toc_ok;
6767 /* Try machine-dependent ways of modifying an illegitimate address
6768 to be legitimate. If we find one, return the new, valid address.
6769 This is used from only one place: `memory_address' in explow.c.
6771 OLDX is the address as it was before break_out_memory_refs was
6772 called. In some cases it is useful to look at this to decide what
6775 It is always safe for this function to do nothing. It exists to
6776 recognize opportunities to optimize the output.
6778 On RS/6000, first check for the sum of a register with a constant
6779 integer that is out of range. If so, generate code to add the
6780 constant with the low-order 16 bits masked to the register and force
6781 this result into another register (this can be done with `cau').
6782 Then generate an address of REG+(CONST&0xffff), allowing for the
6783 possibility of bit 16 being a one.
6785 Then check for the sum of a register and something not constant, try to
6786 load the other things into a register and return the sum. */
6789 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
6794 if (!reg_offset_addressing_ok_p (mode))
6796 if (virtual_stack_registers_memory_p (x))
6799 /* In theory we should not be seeing addresses of the form reg+0,
6800 but just in case it is generated, optimize it away. */
6801 if (GET_CODE (x) == PLUS && XEXP (x, 1) == const0_rtx)
6802 return force_reg (Pmode, XEXP (x, 0));
6804 /* For TImode with load/store quad, restrict addresses to just a single
6805 pointer, so it works with both GPRs and VSX registers. */
6806 /* Make sure both operands are registers. */
6807 else if (GET_CODE (x) == PLUS
6808 && (mode != TImode || !TARGET_QUAD_MEMORY))
6809 return gen_rtx_PLUS (Pmode,
6810 force_reg (Pmode, XEXP (x, 0)),
6811 force_reg (Pmode, XEXP (x, 1)));
6813 return force_reg (Pmode, x);
6815 if (GET_CODE (x) == SYMBOL_REF)
6817 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
6819 return rs6000_legitimize_tls_address (x, model);
6829 /* As in legitimate_offset_address_p we do not assume
6830 worst-case. The mode here is just a hint as to the registers
6831 used. A TImode is usually in gprs, but may actually be in
6832 fprs. Leave worst-case scenario for reload to handle via
6833 insn constraints. PTImode is only GPRs. */
6840 if (GET_CODE (x) == PLUS
6841 && GET_CODE (XEXP (x, 0)) == REG
6842 && GET_CODE (XEXP (x, 1)) == CONST_INT
6843 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000)
6845 && !(SPE_VECTOR_MODE (mode)
6846 || (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)))
6848 HOST_WIDE_INT high_int, low_int;
6850 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
6851 if (low_int >= 0x8000 - extra)
6853 high_int = INTVAL (XEXP (x, 1)) - low_int;
6854 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
6855 GEN_INT (high_int)), 0);
6856 return plus_constant (Pmode, sum, low_int);
6858 else if (GET_CODE (x) == PLUS
6859 && GET_CODE (XEXP (x, 0)) == REG
6860 && GET_CODE (XEXP (x, 1)) != CONST_INT
6861 && GET_MODE_NUNITS (mode) == 1
6862 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
6863 || (/* ??? Assume floating point reg based on mode? */
6864 (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6865 && (mode == DFmode || mode == DDmode)))
6866 && !avoiding_indexed_address_p (mode))
6868 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
6869 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
6871 else if (SPE_VECTOR_MODE (mode)
6872 || (TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD))
6876 /* We accept [reg + reg] and [reg + OFFSET]. */
6878 if (GET_CODE (x) == PLUS)
6880 rtx op1 = XEXP (x, 0);
6881 rtx op2 = XEXP (x, 1);
6884 op1 = force_reg (Pmode, op1);
6886 if (GET_CODE (op2) != REG
6887 && (GET_CODE (op2) != CONST_INT
6888 || !SPE_CONST_OFFSET_OK (INTVAL (op2))
6889 || (GET_MODE_SIZE (mode) > 8
6890 && !SPE_CONST_OFFSET_OK (INTVAL (op2) + 8))))
6891 op2 = force_reg (Pmode, op2);
6893 /* We can't always do [reg + reg] for these, because [reg +
6894 reg + offset] is not a legitimate addressing mode. */
6895 y = gen_rtx_PLUS (Pmode, op1, op2);
6897 if ((GET_MODE_SIZE (mode) > 8 || mode == DDmode) && REG_P (op2))
6898 return force_reg (Pmode, y);
6903 return force_reg (Pmode, x);
6905 else if ((TARGET_ELF
6907 || !MACHO_DYNAMIC_NO_PIC_P
6913 && GET_CODE (x) != CONST_INT
6914 && GET_CODE (x) != CONST_WIDE_INT
6915 && GET_CODE (x) != CONST_DOUBLE
6917 && GET_MODE_NUNITS (mode) == 1
6918 && (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
6919 || (/* ??? Assume floating point reg based on mode? */
6920 (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
6921 && (mode == DFmode || mode == DDmode))))
6923 rtx reg = gen_reg_rtx (Pmode);
6925 emit_insn (gen_elf_high (reg, x));
6927 emit_insn (gen_macho_high (reg, x));
6928 return gen_rtx_LO_SUM (Pmode, reg, x);
6931 && GET_CODE (x) == SYMBOL_REF
6932 && constant_pool_expr_p (x)
6933 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
6934 return create_TOC_reference (x, NULL_RTX);
6939 /* Debug version of rs6000_legitimize_address. */
6941 rs6000_debug_legitimize_address (rtx x, rtx oldx, machine_mode mode)
6947 ret = rs6000_legitimize_address (x, oldx, mode);
6948 insns = get_insns ();
6954 "\nrs6000_legitimize_address: mode %s, old code %s, "
6955 "new code %s, modified\n",
6956 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)),
6957 GET_RTX_NAME (GET_CODE (ret)));
6959 fprintf (stderr, "Original address:\n");
6962 fprintf (stderr, "oldx:\n");
6965 fprintf (stderr, "New address:\n");
6970 fprintf (stderr, "Insns added:\n");
6971 debug_rtx_list (insns, 20);
6977 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
6978 GET_MODE_NAME (mode), GET_RTX_NAME (GET_CODE (x)));
6989 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6990 We need to emit DTP-relative relocations. */
6992 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
6994 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
6999 fputs ("\t.long\t", file);
7002 fputs (DOUBLE_INT_ASM_OP, file);
7007 output_addr_const (file, x);
7008 fputs ("@dtprel+0x8000", file);
7011 /* Return true if X is a symbol that refers to real (rather than emulated)
7015 rs6000_real_tls_symbol_ref_p (rtx x)
7017 return (GET_CODE (x) == SYMBOL_REF
7018 && SYMBOL_REF_TLS_MODEL (x) >= TLS_MODEL_REAL);
7021 /* In the name of slightly smaller debug output, and to cater to
7022 general assembler lossage, recognize various UNSPEC sequences
7023 and turn them back into a direct symbol reference. */
7026 rs6000_delegitimize_address (rtx orig_x)
7030 orig_x = delegitimize_mem_from_attrs (orig_x);
7036 if (TARGET_CMODEL != CMODEL_SMALL
7037 && GET_CODE (y) == LO_SUM)
7041 if (GET_CODE (y) == PLUS
7042 && GET_MODE (y) == Pmode
7043 && CONST_INT_P (XEXP (y, 1)))
7045 offset = XEXP (y, 1);
7049 if (GET_CODE (y) == UNSPEC
7050 && XINT (y, 1) == UNSPEC_TOCREL)
7052 y = XVECEXP (y, 0, 0);
7055 /* Do not associate thread-local symbols with the original
7056 constant pool symbol. */
7058 && GET_CODE (y) == SYMBOL_REF
7059 && CONSTANT_POOL_ADDRESS_P (y)
7060 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y)))
7064 if (offset != NULL_RTX)
7065 y = gen_rtx_PLUS (Pmode, y, offset);
7066 if (!MEM_P (orig_x))
7069 return replace_equiv_address_nv (orig_x, y);
7073 && GET_CODE (orig_x) == LO_SUM
7074 && GET_CODE (XEXP (orig_x, 1)) == CONST)
7076 y = XEXP (XEXP (orig_x, 1), 0);
7077 if (GET_CODE (y) == UNSPEC
7078 && XINT (y, 1) == UNSPEC_MACHOPIC_OFFSET)
7079 return XVECEXP (y, 0, 0);
7085 /* Return true if X shouldn't be emitted into the debug info.
7086 The linker doesn't like .toc section references from
7087 .debug_* sections, so reject .toc section symbols. */
7090 rs6000_const_not_ok_for_debug_p (rtx x)
7092 if (GET_CODE (x) == SYMBOL_REF
7093 && CONSTANT_POOL_ADDRESS_P (x))
7095 rtx c = get_pool_constant (x);
7096 machine_mode cmode = get_pool_mode (x);
7097 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c, cmode))
7104 /* Construct the SYMBOL_REF for the tls_get_addr function. */
7106 static GTY(()) rtx rs6000_tls_symbol;
7108 rs6000_tls_get_addr (void)
7110 if (!rs6000_tls_symbol)
7111 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
7113 return rs6000_tls_symbol;
7116 /* Construct the SYMBOL_REF for TLS GOT references. */
7118 static GTY(()) rtx rs6000_got_symbol;
7120 rs6000_got_sym (void)
7122 if (!rs6000_got_symbol)
7124 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
7125 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
7126 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
7129 return rs6000_got_symbol;
7132 /* AIX Thread-Local Address support. */
7135 rs6000_legitimize_tls_address_aix (rtx addr, enum tls_model model)
7137 rtx sym, mem, tocref, tlsreg, tmpreg, dest, tlsaddr;
7141 name = XSTR (addr, 0);
7142 /* Append TLS CSECT qualifier, unless the symbol already is qualified
7143 or the symbol will be in TLS private data section. */
7144 if (name[strlen (name) - 1] != ']'
7145 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr))
7146 || bss_initializer_p (SYMBOL_REF_DECL (addr))))
7148 tlsname = XALLOCAVEC (char, strlen (name) + 4);
7149 strcpy (tlsname, name);
7151 bss_initializer_p (SYMBOL_REF_DECL (addr)) ? "[UL]" : "[TL]");
7152 tlsaddr = copy_rtx (addr);
7153 XSTR (tlsaddr, 0) = ggc_strdup (tlsname);
7158 /* Place addr into TOC constant pool. */
7159 sym = force_const_mem (GET_MODE (tlsaddr), tlsaddr);
7161 /* Output the TOC entry and create the MEM referencing the value. */
7162 if (constant_pool_expr_p (XEXP (sym, 0))
7163 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym, 0)), Pmode))
7165 tocref = create_TOC_reference (XEXP (sym, 0), NULL_RTX);
7166 mem = gen_const_mem (Pmode, tocref);
7167 set_mem_alias_set (mem, get_TOC_alias_set ());
7172 /* Use global-dynamic for local-dynamic. */
7173 if (model == TLS_MODEL_GLOBAL_DYNAMIC
7174 || model == TLS_MODEL_LOCAL_DYNAMIC)
7176 /* Create new TOC reference for @m symbol. */
7177 name = XSTR (XVECEXP (XEXP (mem, 0), 0, 0), 0);
7178 tlsname = XALLOCAVEC (char, strlen (name) + 1);
7179 strcpy (tlsname, "*LCM");
7180 strcat (tlsname, name + 3);
7181 rtx modaddr = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tlsname));
7182 SYMBOL_REF_FLAGS (modaddr) |= SYMBOL_FLAG_LOCAL;
7183 tocref = create_TOC_reference (modaddr, NULL_RTX);
7184 rtx modmem = gen_const_mem (Pmode, tocref);
7185 set_mem_alias_set (modmem, get_TOC_alias_set ());
7187 rtx modreg = gen_reg_rtx (Pmode);
7188 emit_insn (gen_rtx_SET (VOIDmode, modreg, modmem));
7190 tmpreg = gen_reg_rtx (Pmode);
7191 emit_insn (gen_rtx_SET (VOIDmode, tmpreg, mem));
7193 dest = gen_reg_rtx (Pmode);
7195 emit_insn (gen_tls_get_addrsi (dest, modreg, tmpreg));
7197 emit_insn (gen_tls_get_addrdi (dest, modreg, tmpreg));
7200 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
7201 else if (TARGET_32BIT)
7203 tlsreg = gen_reg_rtx (SImode);
7204 emit_insn (gen_tls_get_tpointer (tlsreg));
7207 tlsreg = gen_rtx_REG (DImode, 13);
7209 /* Load the TOC value into temporary register. */
7210 tmpreg = gen_reg_rtx (Pmode);
7211 emit_insn (gen_rtx_SET (VOIDmode, tmpreg, mem));
7212 set_unique_reg_note (get_last_insn (), REG_EQUAL,
7213 gen_rtx_MINUS (Pmode, addr, tlsreg));
7215 /* Add TOC symbol value to TLS pointer. */
7216 dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tmpreg, tlsreg));
7221 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
7222 this (thread-local) address. */
7225 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
7230 return rs6000_legitimize_tls_address_aix (addr, model);
7232 dest = gen_reg_rtx (Pmode);
7233 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
7239 tlsreg = gen_rtx_REG (Pmode, 13);
7240 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
7244 tlsreg = gen_rtx_REG (Pmode, 2);
7245 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
7249 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
7253 tmp = gen_reg_rtx (Pmode);
7256 tlsreg = gen_rtx_REG (Pmode, 13);
7257 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
7261 tlsreg = gen_rtx_REG (Pmode, 2);
7262 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
7266 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
7268 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
7273 rtx r3, got, tga, tmp1, tmp2, call_insn;
7275 /* We currently use relocations like @got@tlsgd for tls, which
7276 means the linker will handle allocation of tls entries, placing
7277 them in the .got section. So use a pointer to the .got section,
7278 not one to secondary TOC sections used by 64-bit -mminimal-toc,
7279 or to secondary GOT sections used by 32-bit -fPIC. */
7281 got = gen_rtx_REG (Pmode, 2);
7285 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
7288 rtx gsym = rs6000_got_sym ();
7289 got = gen_reg_rtx (Pmode);
7291 rs6000_emit_move (got, gsym, Pmode);
7296 tmp1 = gen_reg_rtx (Pmode);
7297 tmp2 = gen_reg_rtx (Pmode);
7298 mem = gen_const_mem (Pmode, tmp1);
7299 lab = gen_label_rtx ();
7300 emit_insn (gen_load_toc_v4_PIC_1b (gsym, lab));
7301 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
7302 if (TARGET_LINK_STACK)
7303 emit_insn (gen_addsi3 (tmp1, tmp1, GEN_INT (4)));
7304 emit_move_insn (tmp2, mem);
7305 last = emit_insn (gen_addsi3 (got, tmp1, tmp2));
7306 set_unique_reg_note (last, REG_EQUAL, gsym);
7311 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
7313 tga = rs6000_tls_get_addr ();
7314 emit_library_call_value (tga, dest, LCT_CONST, Pmode,
7315 1, const0_rtx, Pmode);
7317 r3 = gen_rtx_REG (Pmode, 3);
7318 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
7321 insn = gen_tls_gd_aix64 (r3, got, addr, tga, const0_rtx);
7323 insn = gen_tls_gd_aix32 (r3, got, addr, tga, const0_rtx);
7325 else if (DEFAULT_ABI == ABI_V4)
7326 insn = gen_tls_gd_sysvsi (r3, got, addr, tga, const0_rtx);
7329 call_insn = last_call_insn ();
7330 PATTERN (call_insn) = insn;
7331 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
7332 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
7333 pic_offset_table_rtx);
7335 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
7337 tga = rs6000_tls_get_addr ();
7338 tmp1 = gen_reg_rtx (Pmode);
7339 emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
7340 1, const0_rtx, Pmode);
7342 r3 = gen_rtx_REG (Pmode, 3);
7343 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
7346 insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
7348 insn = gen_tls_ld_aix32 (r3, got, tga, const0_rtx);
7350 else if (DEFAULT_ABI == ABI_V4)
7351 insn = gen_tls_ld_sysvsi (r3, got, tga, const0_rtx);
7354 call_insn = last_call_insn ();
7355 PATTERN (call_insn) = insn;
7356 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
7357 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
7358 pic_offset_table_rtx);
7360 if (rs6000_tls_size == 16)
7363 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
7365 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
7367 else if (rs6000_tls_size == 32)
7369 tmp2 = gen_reg_rtx (Pmode);
7371 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
7373 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
7376 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
7378 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
7382 tmp2 = gen_reg_rtx (Pmode);
7384 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
7386 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
7388 insn = gen_rtx_SET (Pmode, dest,
7389 gen_rtx_PLUS (Pmode, tmp2, tmp1));
7395 /* IE, or 64-bit offset LE. */
7396 tmp2 = gen_reg_rtx (Pmode);
7398 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
7400 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
7403 insn = gen_tls_tls_64 (dest, tmp2, addr);
7405 insn = gen_tls_tls_32 (dest, tmp2, addr);
7413 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7416 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
7418 if (GET_CODE (x) == HIGH
7419 && GET_CODE (XEXP (x, 0)) == UNSPEC)
7422 /* A TLS symbol in the TOC cannot contain a sum. */
7423 if (GET_CODE (x) == CONST
7424 && GET_CODE (XEXP (x, 0)) == PLUS
7425 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
7426 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) != 0)
7429 /* Do not place an ELF TLS symbol in the constant pool. */
7430 return TARGET_ELF && tls_referenced_p (x);
7433 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
7434 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
7435 can be addressed relative to the toc pointer. */
7438 use_toc_relative_ref (rtx sym)
7440 return ((constant_pool_expr_p (sym)
7441 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym),
7442 get_pool_mode (sym)))
7443 || (TARGET_CMODEL == CMODEL_MEDIUM
7444 && SYMBOL_REF_LOCAL_P (sym)));
7447 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
7448 replace the input X, or the original X if no replacement is called for.
7449 The output parameter *WIN is 1 if the calling macro should goto WIN,
7452 For RS/6000, we wish to handle large displacements off a base
7453 register by splitting the addend across an addiu/addis and the mem insn.
7454 This cuts number of extra insns needed from 3 to 1.
7456 On Darwin, we use this to generate code for floating point constants.
7457 A movsf_low is generated so we wind up with 2 instructions rather than 3.
7458 The Darwin code is inside #if TARGET_MACHO because only then are the
7459 machopic_* functions defined. */
7461 rs6000_legitimize_reload_address (rtx x, machine_mode mode,
7462 int opnum, int type,
7463 int ind_levels ATTRIBUTE_UNUSED, int *win)
7465 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
7467 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
7468 DFmode/DImode MEM. */
7471 && ((mode == DFmode && recog_data.operand_mode[0] == V2DFmode)
7472 || (mode == DImode && recog_data.operand_mode[0] == V2DImode)))
7473 reg_offset_p = false;
7475 /* We must recognize output that we have already generated ourselves. */
7476 if (GET_CODE (x) == PLUS
7477 && GET_CODE (XEXP (x, 0)) == PLUS
7478 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
7479 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7480 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7482 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
7483 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
7484 opnum, (enum reload_type) type);
7489 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
7490 if (GET_CODE (x) == LO_SUM
7491 && GET_CODE (XEXP (x, 0)) == HIGH)
7493 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
7494 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
7495 opnum, (enum reload_type) type);
7501 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
7502 && GET_CODE (x) == LO_SUM
7503 && GET_CODE (XEXP (x, 0)) == PLUS
7504 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
7505 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
7506 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
7507 && machopic_operand_p (XEXP (x, 1)))
7509 /* Result of previous invocation of this function on Darwin
7510 floating point constant. */
7511 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
7512 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
7513 opnum, (enum reload_type) type);
7519 if (TARGET_CMODEL != CMODEL_SMALL
7521 && small_toc_ref (x, VOIDmode))
7523 rtx hi = gen_rtx_HIGH (Pmode, copy_rtx (x));
7524 x = gen_rtx_LO_SUM (Pmode, hi, x);
7525 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
7526 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
7527 opnum, (enum reload_type) type);
7532 if (GET_CODE (x) == PLUS
7533 && GET_CODE (XEXP (x, 0)) == REG
7534 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
7535 && INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 1)
7536 && GET_CODE (XEXP (x, 1)) == CONST_INT
7538 && !SPE_VECTOR_MODE (mode)
7539 && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (mode) > UNITS_PER_WORD)
7540 && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode)))
7542 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
7543 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
7545 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7547 /* Check for 32-bit overflow. */
7548 if (high + low != val)
7554 /* Reload the high part into a base reg; leave the low part
7555 in the mem directly. */
7557 x = gen_rtx_PLUS (GET_MODE (x),
7558 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
7562 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
7563 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
7564 opnum, (enum reload_type) type);
7569 if (GET_CODE (x) == SYMBOL_REF
7571 && (!VECTOR_MODE_P (mode) || VECTOR_MEM_NONE_P (mode))
7572 && !SPE_VECTOR_MODE (mode)
7574 && DEFAULT_ABI == ABI_DARWIN
7575 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
7576 && machopic_symbol_defined_p (x)
7578 && DEFAULT_ABI == ABI_V4
7581 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
7582 The same goes for DImode without 64-bit gprs and DFmode and DDmode
7584 ??? Assume floating point reg based on mode? This assumption is
7585 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
7586 where reload ends up doing a DFmode load of a constant from
7587 mem using two gprs. Unfortunately, at this point reload
7588 hasn't yet selected regs so poking around in reload data
7589 won't help and even if we could figure out the regs reliably,
7590 we'd still want to allow this transformation when the mem is
7591 naturally aligned. Since we say the address is good here, we
7592 can't disable offsets from LO_SUMs in mem_operand_gpr.
7593 FIXME: Allow offset from lo_sum for other modes too, when
7594 mem is sufficiently aligned.
7596 Also disallow this if the type can go in VMX/Altivec registers, since
7597 those registers do not have d-form (reg+offset) address modes. */
7598 && !reg_addr[mode].scalar_in_vmx_p
7601 && (mode != TImode || !TARGET_VSX_TIMODE)
7603 && (mode != DImode || TARGET_POWERPC64)
7604 && ((mode != DFmode && mode != DDmode) || TARGET_POWERPC64
7605 || (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)))
7610 rtx offset = machopic_gen_offset (x);
7611 x = gen_rtx_LO_SUM (GET_MODE (x),
7612 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
7613 gen_rtx_HIGH (Pmode, offset)), offset);
7617 x = gen_rtx_LO_SUM (GET_MODE (x),
7618 gen_rtx_HIGH (Pmode, x), x);
7620 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
7621 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
7622 opnum, (enum reload_type) type);
7627 /* Reload an offset address wrapped by an AND that represents the
7628 masking of the lower bits. Strip the outer AND and let reload
7629 convert the offset address into an indirect address. For VSX,
7630 force reload to create the address with an AND in a separate
7631 register, because we can't guarantee an altivec register will
7633 if (VECTOR_MEM_ALTIVEC_P (mode)
7634 && GET_CODE (x) == AND
7635 && GET_CODE (XEXP (x, 0)) == PLUS
7636 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
7637 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7638 && GET_CODE (XEXP (x, 1)) == CONST_INT
7639 && INTVAL (XEXP (x, 1)) == -16)
7648 && GET_CODE (x) == SYMBOL_REF
7649 && use_toc_relative_ref (x))
7651 x = create_TOC_reference (x, NULL_RTX);
7652 if (TARGET_CMODEL != CMODEL_SMALL)
7653 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
7654 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
7655 opnum, (enum reload_type) type);
7663 /* Debug version of rs6000_legitimize_reload_address. */
7665 rs6000_debug_legitimize_reload_address (rtx x, machine_mode mode,
7666 int opnum, int type,
7667 int ind_levels, int *win)
7669 rtx ret = rs6000_legitimize_reload_address (x, mode, opnum, type,
7672 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
7673 "type = %d, ind_levels = %d, win = %d, original addr:\n",
7674 GET_MODE_NAME (mode), opnum, type, ind_levels, *win);
7678 fprintf (stderr, "Same address returned\n");
7680 fprintf (stderr, "NULL returned\n");
7683 fprintf (stderr, "New address:\n");
7690 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
7691 that is a valid memory address for an instruction.
7692 The MODE argument is the machine mode for the MEM expression
7693 that wants to use this address.
7695 On the RS/6000, there are four valid address: a SYMBOL_REF that
7696 refers to a constant pool entry of an address (or the sum of it
7697 plus a constant), a short (16-bit signed) constant plus a register,
7698 the sum of two registers, or a register indirect, possibly with an
7699 auto-increment. For DFmode, DDmode and DImode with a constant plus
7700 register, we must ensure that both words are addressable or PowerPC64
7701 with offset word aligned.
7703 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7704 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7705 because adjacent memory cells are accessed by adding word-sized offsets
7706 during assembly output. */
7708 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
7710 bool reg_offset_p = reg_offset_addressing_ok_p (mode);
7712 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7713 if (VECTOR_MEM_ALTIVEC_P (mode)
7714 && GET_CODE (x) == AND
7715 && GET_CODE (XEXP (x, 1)) == CONST_INT
7716 && INTVAL (XEXP (x, 1)) == -16)
7719 if (TARGET_ELF && RS6000_SYMBOL_REF_TLS_P (x))
7721 if (legitimate_indirect_address_p (x, reg_ok_strict))
7724 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
7725 && mode_supports_pre_incdec_p (mode)
7726 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
7728 if (virtual_stack_registers_memory_p (x))
7730 if (reg_offset_p && legitimate_small_data_p (mode, x))
7733 && legitimate_constant_pool_address_p (x, mode,
7734 reg_ok_strict || lra_in_progress))
7736 /* For TImode, if we have load/store quad and TImode in VSX registers, only
7737 allow register indirect addresses. This will allow the values to go in
7738 either GPRs or VSX registers without reloading. The vector types would
7739 tend to go into VSX registers, so we allow REG+REG, while TImode seems
7740 somewhat split, in that some uses are GPR based, and some VSX based. */
7741 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE)
7743 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7746 && GET_CODE (x) == PLUS
7747 && GET_CODE (XEXP (x, 0)) == REG
7748 && (XEXP (x, 0) == virtual_stack_vars_rtx
7749 || XEXP (x, 0) == arg_pointer_rtx)
7750 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7752 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict, false))
7756 && ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
7758 || (mode != DFmode && mode != DDmode)
7759 || (TARGET_E500_DOUBLE && mode != DDmode))
7760 && (TARGET_POWERPC64 || mode != DImode)
7761 && (mode != TImode || VECTOR_MEM_VSX_P (TImode))
7763 && !avoiding_indexed_address_p (mode)
7764 && legitimate_indexed_address_p (x, reg_ok_strict))
7766 if (TARGET_UPDATE && GET_CODE (x) == PRE_MODIFY
7767 && mode_supports_pre_modify_p (mode)
7768 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
7769 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1),
7770 reg_ok_strict, false)
7771 || (!avoiding_indexed_address_p (mode)
7772 && legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict)))
7773 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
7775 if (reg_offset_p && legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
7780 /* Debug version of rs6000_legitimate_address_p. */
7782 rs6000_debug_legitimate_address_p (machine_mode mode, rtx x,
7785 bool ret = rs6000_legitimate_address_p (mode, x, reg_ok_strict);
7787 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
7788 "strict = %d, reload = %s, code = %s\n",
7789 ret ? "true" : "false",
7790 GET_MODE_NAME (mode),
7794 : (reload_in_progress ? "progress" : "before")),
7795 GET_RTX_NAME (GET_CODE (x)));
7801 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
7804 rs6000_mode_dependent_address_p (const_rtx addr,
7805 addr_space_t as ATTRIBUTE_UNUSED)
7807 return rs6000_mode_dependent_address_ptr (addr);
7810 /* Go to LABEL if ADDR (a legitimate address expression)
7811 has an effect that depends on the machine mode it is used for.
7813 On the RS/6000 this is true of all integral offsets (since AltiVec
7814 and VSX modes don't allow them) or is a pre-increment or decrement.
7816 ??? Except that due to conceptual problems in offsettable_address_p
7817 we can't really report the problems of integral offsets. So leave
7818 this assuming that the adjustable offset must be valid for the
7819 sub-words of a TFmode operand, which is what we had before. */
7822 rs6000_mode_dependent_address (const_rtx addr)
7824 switch (GET_CODE (addr))
7827 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
7828 is considered a legitimate address before reload, so there
7829 are no offset restrictions in that case. Note that this
7830 condition is safe in strict mode because any address involving
7831 virtual_stack_vars_rtx or arg_pointer_rtx would already have
7832 been rejected as illegitimate. */
7833 if (XEXP (addr, 0) != virtual_stack_vars_rtx
7834 && XEXP (addr, 0) != arg_pointer_rtx
7835 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
7837 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
7838 return val + 0x8000 >= 0x10000 - (TARGET_POWERPC64 ? 8 : 12);
7843 /* Anything in the constant pool is sufficiently aligned that
7844 all bytes have the same high part address. */
7845 return !legitimate_constant_pool_address_p (addr, QImode, false);
7847 /* Auto-increment cases are now treated generically in recog.c. */
7849 return TARGET_UPDATE;
7851 /* AND is only allowed in Altivec loads. */
7862 /* Debug version of rs6000_mode_dependent_address. */
7864 rs6000_debug_mode_dependent_address (const_rtx addr)
7866 bool ret = rs6000_mode_dependent_address (addr);
7868 fprintf (stderr, "\nrs6000_mode_dependent_address: ret = %s\n",
7869 ret ? "true" : "false");
7875 /* Implement FIND_BASE_TERM. */
7878 rs6000_find_base_term (rtx op)
7883 if (GET_CODE (base) == CONST)
7884 base = XEXP (base, 0);
7885 if (GET_CODE (base) == PLUS)
7886 base = XEXP (base, 0);
7887 if (GET_CODE (base) == UNSPEC)
7888 switch (XINT (base, 1))
7891 case UNSPEC_MACHOPIC_OFFSET:
7892 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
7893 for aliasing purposes. */
7894 return XVECEXP (base, 0, 0);
7900 /* More elaborate version of recog's offsettable_memref_p predicate
7901 that works around the ??? note of rs6000_mode_dependent_address.
7902 In particular it accepts
7904 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
7906 in 32-bit mode, that the recog predicate rejects. */
7909 rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode)
7916 /* First mimic offsettable_memref_p. */
7917 if (offsettable_address_p (true, GET_MODE (op), XEXP (op, 0)))
7920 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
7921 the latter predicate knows nothing about the mode of the memory
7922 reference and, therefore, assumes that it is the largest supported
7923 mode (TFmode). As a consequence, legitimate offsettable memory
7924 references are rejected. rs6000_legitimate_offset_address_p contains
7925 the correct logic for the PLUS case of rs6000_mode_dependent_address,
7926 at least with a little bit of help here given that we know the
7927 actual registers used. */
7928 worst_case = ((TARGET_POWERPC64 && GET_MODE_CLASS (reg_mode) == MODE_INT)
7929 || GET_MODE_SIZE (reg_mode) == 4);
7930 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0),
7934 /* Change register usage conditional on target flags. */
7936 rs6000_conditional_register_usage (void)
7940 if (TARGET_DEBUG_TARGET)
7941 fprintf (stderr, "rs6000_conditional_register_usage called\n");
7943 /* Set MQ register fixed (already call_used) so that it will not be
7947 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
7949 fixed_regs[13] = call_used_regs[13]
7950 = call_really_used_regs[13] = 1;
7952 /* Conditionally disable FPRs. */
7953 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
7954 for (i = 32; i < 64; i++)
7955 fixed_regs[i] = call_used_regs[i]
7956 = call_really_used_regs[i] = 1;
7958 /* The TOC register is not killed across calls in a way that is
7959 visible to the compiler. */
7960 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
7961 call_really_used_regs[2] = 0;
7963 if (DEFAULT_ABI == ABI_V4
7964 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
7966 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
7968 if (DEFAULT_ABI == ABI_V4
7969 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
7971 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
7972 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
7973 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
7975 if (DEFAULT_ABI == ABI_DARWIN
7976 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
7977 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
7978 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
7979 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
7981 if (TARGET_TOC && TARGET_MINIMAL_TOC)
7982 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
7983 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
7987 global_regs[SPEFSCR_REGNO] = 1;
7988 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
7989 registers in prologues and epilogues. We no longer use r14
7990 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
7991 pool for link-compatibility with older versions of GCC. Once
7992 "old" code has died out, we can return r14 to the allocation
7995 = call_used_regs[14]
7996 = call_really_used_regs[14] = 1;
7999 if (!TARGET_ALTIVEC && !TARGET_VSX)
8001 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
8002 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
8003 call_really_used_regs[VRSAVE_REGNO] = 1;
8006 if (TARGET_ALTIVEC || TARGET_VSX)
8007 global_regs[VSCR_REGNO] = 1;
8009 if (TARGET_ALTIVEC_ABI)
8011 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
8012 call_used_regs[i] = call_really_used_regs[i] = 1;
8014 /* AIX reserves VR20:31 in non-extended ABI mode. */
8016 for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
8017 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
8022 /* Output insns to set DEST equal to the constant SOURCE as a series of
8023 lis, ori and shl instructions and return TRUE. */
8026 rs6000_emit_set_const (rtx dest, rtx source)
8028 machine_mode mode = GET_MODE (dest);
8033 gcc_checking_assert (CONST_INT_P (source));
8034 c = INTVAL (source);
8039 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
8043 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
8045 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (temp),
8046 GEN_INT (c & ~(HOST_WIDE_INT) 0xffff)));
8047 emit_insn (gen_rtx_SET (VOIDmode, dest,
8048 gen_rtx_IOR (SImode, copy_rtx (temp),
8049 GEN_INT (c & 0xffff))));
8053 if (!TARGET_POWERPC64)
8057 hi = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN == 0,
8059 lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
8061 emit_move_insn (hi, GEN_INT (c >> 32));
8062 c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
8063 emit_move_insn (lo, GEN_INT (c));
8066 rs6000_emit_set_long_const (dest, c);
8073 insn = get_last_insn ();
8074 set = single_set (insn);
8075 if (! CONSTANT_P (SET_SRC (set)))
8076 set_unique_reg_note (insn, REG_EQUAL, GEN_INT (c));
8081 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
8082 Output insns to set DEST equal to the constant C as a series of
8083 lis, ori and shl instructions. */
8086 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c)
8089 HOST_WIDE_INT ud1, ud2, ud3, ud4;
8099 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
8100 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
8101 emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
8103 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
8104 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
8106 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
8108 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
8109 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
8111 emit_move_insn (dest,
8112 gen_rtx_IOR (DImode, copy_rtx (temp),
8115 else if (ud3 == 0 && ud4 == 0)
8117 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
8119 gcc_assert (ud2 & 0x8000);
8120 emit_move_insn (copy_rtx (temp),
8121 GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
8123 emit_move_insn (copy_rtx (temp),
8124 gen_rtx_IOR (DImode, copy_rtx (temp),
8126 emit_move_insn (dest,
8127 gen_rtx_ZERO_EXTEND (DImode,
8128 gen_lowpart (SImode,
8131 else if ((ud4 == 0xffff && (ud3 & 0x8000))
8132 || (ud4 == 0 && ! (ud3 & 0x8000)))
8134 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
8136 emit_move_insn (copy_rtx (temp),
8137 GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
8139 emit_move_insn (copy_rtx (temp),
8140 gen_rtx_IOR (DImode, copy_rtx (temp),
8142 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
8143 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
8146 emit_move_insn (dest,
8147 gen_rtx_IOR (DImode, copy_rtx (temp),
8152 temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
8154 emit_move_insn (copy_rtx (temp),
8155 GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
8157 emit_move_insn (copy_rtx (temp),
8158 gen_rtx_IOR (DImode, copy_rtx (temp),
8161 emit_move_insn (ud2 != 0 || ud1 != 0 ? copy_rtx (temp) : dest,
8162 gen_rtx_ASHIFT (DImode, copy_rtx (temp),
8165 emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
8166 gen_rtx_IOR (DImode, copy_rtx (temp),
8167 GEN_INT (ud2 << 16)));
8169 emit_move_insn (dest,
8170 gen_rtx_IOR (DImode, copy_rtx (temp),
8175 /* Helper for the following. Get rid of [r+r] memory refs
8176 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
8179 rs6000_eliminate_indexed_memrefs (rtx operands[2])
8181 if (reload_in_progress)
8184 if (GET_CODE (operands[0]) == MEM
8185 && GET_CODE (XEXP (operands[0], 0)) != REG
8186 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0),
8187 GET_MODE (operands[0]), false))
8189 = replace_equiv_address (operands[0],
8190 copy_addr_to_reg (XEXP (operands[0], 0)));
8192 if (GET_CODE (operands[1]) == MEM
8193 && GET_CODE (XEXP (operands[1], 0)) != REG
8194 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0),
8195 GET_MODE (operands[1]), false))
8197 = replace_equiv_address (operands[1],
8198 copy_addr_to_reg (XEXP (operands[1], 0)));
8201 /* Generate a vector of constants to permute MODE for a little-endian
8202 storage operation by swapping the two halves of a vector. */
8204 rs6000_const_vec (machine_mode mode)
8232 v = rtvec_alloc (subparts);
8234 for (i = 0; i < subparts / 2; ++i)
8235 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i + subparts / 2);
8236 for (i = subparts / 2; i < subparts; ++i)
8237 RTVEC_ELT (v, i) = gen_rtx_CONST_INT (DImode, i - subparts / 2);
8242 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
8243 for a VSX load or store operation. */
8245 rs6000_gen_le_vsx_permute (rtx source, machine_mode mode)
8247 rtx par = gen_rtx_PARALLEL (VOIDmode, rs6000_const_vec (mode));
8248 return gen_rtx_VEC_SELECT (mode, source, par);
8251 /* Emit a little-endian load from vector memory location SOURCE to VSX
8252 register DEST in mode MODE. The load is done with two permuting
8253 insn's that represent an lxvd2x and xxpermdi. */
8255 rs6000_emit_le_vsx_load (rtx dest, rtx source, machine_mode mode)
8257 rtx tmp, permute_mem, permute_reg;
8259 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8261 if (mode == TImode || mode == V1TImode)
8264 dest = gen_lowpart (V2DImode, dest);
8265 source = adjust_address (source, V2DImode, 0);
8268 tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest) : dest;
8269 permute_mem = rs6000_gen_le_vsx_permute (source, mode);
8270 permute_reg = rs6000_gen_le_vsx_permute (tmp, mode);
8271 emit_insn (gen_rtx_SET (VOIDmode, tmp, permute_mem));
8272 emit_insn (gen_rtx_SET (VOIDmode, dest, permute_reg));
8275 /* Emit a little-endian store to vector memory location DEST from VSX
8276 register SOURCE in mode MODE. The store is done with two permuting
8277 insn's that represent an xxpermdi and an stxvd2x. */
8279 rs6000_emit_le_vsx_store (rtx dest, rtx source, machine_mode mode)
8281 rtx tmp, permute_src, permute_tmp;
8283 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
8285 if (mode == TImode || mode == V1TImode)
8288 dest = adjust_address (dest, V2DImode, 0);
8289 source = gen_lowpart (V2DImode, source);
8292 tmp = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source) : source;
8293 permute_src = rs6000_gen_le_vsx_permute (source, mode);
8294 permute_tmp = rs6000_gen_le_vsx_permute (tmp, mode);
8295 emit_insn (gen_rtx_SET (VOIDmode, tmp, permute_src));
8296 emit_insn (gen_rtx_SET (VOIDmode, dest, permute_tmp));
8299 /* Emit a sequence representing a little-endian VSX load or store,
8300 moving data from SOURCE to DEST in mode MODE. This is done
8301 separately from rs6000_emit_move to ensure it is called only
8302 during expand. LE VSX loads and stores introduced later are
8303 handled with a split. The expand-time RTL generation allows
8304 us to optimize away redundant pairs of register-permutes. */
8306 rs6000_emit_le_vsx_move (rtx dest, rtx source, machine_mode mode)
8308 gcc_assert (!BYTES_BIG_ENDIAN
8309 && VECTOR_MEM_VSX_P (mode)
8310 && !gpr_or_gpr_p (dest, source)
8311 && (MEM_P (source) ^ MEM_P (dest)));
8315 gcc_assert (REG_P (dest) || GET_CODE (dest) == SUBREG);
8316 rs6000_emit_le_vsx_load (dest, source, mode);
8320 if (!REG_P (source))
8321 source = force_reg (mode, source);
8322 rs6000_emit_le_vsx_store (dest, source, mode);
8326 /* Emit a move from SOURCE to DEST in mode MODE. */
8328 rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
8332 operands[1] = source;
8334 if (TARGET_DEBUG_ADDR)
8337 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
8338 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
8339 GET_MODE_NAME (mode),
8342 can_create_pseudo_p ());
8344 fprintf (stderr, "source:\n");
8348 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
8349 if (CONST_WIDE_INT_P (operands[1])
8350 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8352 /* This should be fixed with the introduction of CONST_WIDE_INT. */
8356 /* Check if GCC is setting up a block move that will end up using FP
8357 registers as temporaries. We must make sure this is acceptable. */
8358 if (GET_CODE (operands[0]) == MEM
8359 && GET_CODE (operands[1]) == MEM
8361 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
8362 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
8363 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
8364 ? 32 : MEM_ALIGN (operands[0])))
8365 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
8367 : MEM_ALIGN (operands[1]))))
8368 && ! MEM_VOLATILE_P (operands [0])
8369 && ! MEM_VOLATILE_P (operands [1]))
8371 emit_move_insn (adjust_address (operands[0], SImode, 0),
8372 adjust_address (operands[1], SImode, 0));
8373 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
8374 adjust_address (copy_rtx (operands[1]), SImode, 4));
8378 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
8379 && !gpc_reg_operand (operands[1], mode))
8380 operands[1] = force_reg (mode, operands[1]);
8382 /* Recognize the case where operand[1] is a reference to thread-local
8383 data and load its address to a register. */
8384 if (tls_referenced_p (operands[1]))
8386 enum tls_model model;
8387 rtx tmp = operands[1];
8390 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
8392 addend = XEXP (XEXP (tmp, 0), 1);
8393 tmp = XEXP (XEXP (tmp, 0), 0);
8396 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
8397 model = SYMBOL_REF_TLS_MODEL (tmp);
8398 gcc_assert (model != 0);
8400 tmp = rs6000_legitimize_tls_address (tmp, model);
8403 tmp = gen_rtx_PLUS (mode, tmp, addend);
8404 tmp = force_operand (tmp, operands[0]);
8409 /* Handle the case where reload calls us with an invalid address. */
8410 if (reload_in_progress && mode == Pmode
8411 && (! general_operand (operands[1], mode)
8412 || ! nonimmediate_operand (operands[0], mode)))
8415 /* 128-bit constant floating-point values on Darwin should really be loaded
8416 as two parts. However, this premature splitting is a problem when DFmode
8417 values can go into Altivec registers. */
8418 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
8419 && !reg_addr[DFmode].scalar_in_vmx_p
8420 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
8422 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode, 0),
8423 simplify_gen_subreg (DFmode, operands[1], mode, 0),
8425 rs6000_emit_move (simplify_gen_subreg (DFmode, operands[0], mode,
8426 GET_MODE_SIZE (DFmode)),
8427 simplify_gen_subreg (DFmode, operands[1], mode,
8428 GET_MODE_SIZE (DFmode)),
8433 if (reload_in_progress && cfun->machine->sdmode_stack_slot != NULL_RTX)
8434 cfun->machine->sdmode_stack_slot =
8435 eliminate_regs (cfun->machine->sdmode_stack_slot, VOIDmode, NULL_RTX);
8438 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
8439 p1:SD) if p1 is not of floating point class and p0 is spilled as
8440 we can have no analogous movsd_store for this. */
8441 if (lra_in_progress && mode == DDmode
8442 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
8443 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
8444 && GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))
8445 && GET_MODE (SUBREG_REG (operands[1])) == SDmode)
8448 int regno = REGNO (SUBREG_REG (operands[1]));
8450 if (regno >= FIRST_PSEUDO_REGISTER)
8452 cl = reg_preferred_class (regno);
8453 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][1];
8455 if (regno >= 0 && ! FP_REGNO_P (regno))
8458 operands[0] = gen_lowpart_SUBREG (SDmode, operands[0]);
8459 operands[1] = SUBREG_REG (operands[1]);
8464 && REG_P (operands[0]) && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER
8465 && reg_preferred_class (REGNO (operands[0])) == NO_REGS
8466 && (REG_P (operands[1])
8467 || (GET_CODE (operands[1]) == SUBREG
8468 && REG_P (SUBREG_REG (operands[1])))))
8470 int regno = REGNO (GET_CODE (operands[1]) == SUBREG
8471 ? SUBREG_REG (operands[1]) : operands[1]);
8474 if (regno >= FIRST_PSEUDO_REGISTER)
8476 cl = reg_preferred_class (regno);
8477 gcc_assert (cl != NO_REGS);
8478 regno = ira_class_hard_regs[cl][0];
8480 if (FP_REGNO_P (regno))
8482 if (GET_MODE (operands[0]) != DDmode)
8483 operands[0] = gen_rtx_SUBREG (DDmode, operands[0], 0);
8484 emit_insn (gen_movsd_store (operands[0], operands[1]));
8486 else if (INT_REGNO_P (regno))
8487 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
8492 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
8493 p:DD)) if p0 is not of floating point class and p1 is spilled as
8494 we can have no analogous movsd_load for this. */
8495 if (lra_in_progress && mode == DDmode
8496 && GET_CODE (operands[0]) == SUBREG && REG_P (SUBREG_REG (operands[0]))
8497 && GET_MODE (SUBREG_REG (operands[0])) == SDmode
8498 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
8499 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
8502 int regno = REGNO (SUBREG_REG (operands[0]));
8504 if (regno >= FIRST_PSEUDO_REGISTER)
8506 cl = reg_preferred_class (regno);
8507 regno = cl == NO_REGS ? -1 : ira_class_hard_regs[cl][0];
8509 if (regno >= 0 && ! FP_REGNO_P (regno))
8512 operands[0] = SUBREG_REG (operands[0]);
8513 operands[1] = gen_lowpart_SUBREG (SDmode, operands[1]);
8518 && (REG_P (operands[0])
8519 || (GET_CODE (operands[0]) == SUBREG
8520 && REG_P (SUBREG_REG (operands[0]))))
8521 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
8522 && reg_preferred_class (REGNO (operands[1])) == NO_REGS)
8524 int regno = REGNO (GET_CODE (operands[0]) == SUBREG
8525 ? SUBREG_REG (operands[0]) : operands[0]);
8528 if (regno >= FIRST_PSEUDO_REGISTER)
8530 cl = reg_preferred_class (regno);
8531 gcc_assert (cl != NO_REGS);
8532 regno = ira_class_hard_regs[cl][0];
8534 if (FP_REGNO_P (regno))
8536 if (GET_MODE (operands[1]) != DDmode)
8537 operands[1] = gen_rtx_SUBREG (DDmode, operands[1], 0);
8538 emit_insn (gen_movsd_load (operands[0], operands[1]));
8540 else if (INT_REGNO_P (regno))
8541 emit_insn (gen_movsd_hardfloat (operands[0], operands[1]));
8547 if (reload_in_progress
8549 && cfun->machine->sdmode_stack_slot != NULL_RTX
8550 && MEM_P (operands[0])
8551 && rtx_equal_p (operands[0], cfun->machine->sdmode_stack_slot)
8552 && REG_P (operands[1]))
8554 if (FP_REGNO_P (REGNO (operands[1])))
8556 rtx mem = adjust_address_nv (operands[0], DDmode, 0);
8557 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
8558 emit_insn (gen_movsd_store (mem, operands[1]));
8560 else if (INT_REGNO_P (REGNO (operands[1])))
8562 rtx mem = operands[0];
8563 if (BYTES_BIG_ENDIAN)
8564 mem = adjust_address_nv (mem, mode, 4);
8565 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
8566 emit_insn (gen_movsd_hardfloat (mem, operands[1]));
8572 if (reload_in_progress
8574 && REG_P (operands[0])
8575 && MEM_P (operands[1])
8576 && cfun->machine->sdmode_stack_slot != NULL_RTX
8577 && rtx_equal_p (operands[1], cfun->machine->sdmode_stack_slot))
8579 if (FP_REGNO_P (REGNO (operands[0])))
8581 rtx mem = adjust_address_nv (operands[1], DDmode, 0);
8582 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
8583 emit_insn (gen_movsd_load (operands[0], mem));
8585 else if (INT_REGNO_P (REGNO (operands[0])))
8587 rtx mem = operands[1];
8588 if (BYTES_BIG_ENDIAN)
8589 mem = adjust_address_nv (mem, mode, 4);
8590 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
8591 emit_insn (gen_movsd_hardfloat (operands[0], mem));
8598 /* FIXME: In the long term, this switch statement should go away
8599 and be replaced by a sequence of tests based on things like
8605 if (CONSTANT_P (operands[1])
8606 && GET_CODE (operands[1]) != CONST_INT)
8607 operands[1] = force_const_mem (mode, operands[1]);
8612 rs6000_eliminate_indexed_memrefs (operands);
8619 if (CONSTANT_P (operands[1])
8620 && ! easy_fp_constant (operands[1], mode))
8621 operands[1] = force_const_mem (mode, operands[1]);
8635 if (CONSTANT_P (operands[1])
8636 && !easy_vector_constant (operands[1], mode))
8637 operands[1] = force_const_mem (mode, operands[1]);
8642 /* Use default pattern for address of ELF small data */
8645 && DEFAULT_ABI == ABI_V4
8646 && (GET_CODE (operands[1]) == SYMBOL_REF
8647 || GET_CODE (operands[1]) == CONST)
8648 && small_data_operand (operands[1], mode))
8650 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
8654 if (DEFAULT_ABI == ABI_V4
8655 && mode == Pmode && mode == SImode
8656 && flag_pic == 1 && got_operand (operands[1], mode))
8658 emit_insn (gen_movsi_got (operands[0], operands[1]));
8662 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
8666 && CONSTANT_P (operands[1])
8667 && GET_CODE (operands[1]) != HIGH
8668 && GET_CODE (operands[1]) != CONST_INT)
8670 rtx target = (!can_create_pseudo_p ()
8672 : gen_reg_rtx (mode));
8674 /* If this is a function address on -mcall-aixdesc,
8675 convert it to the address of the descriptor. */
8676 if (DEFAULT_ABI == ABI_AIX
8677 && GET_CODE (operands[1]) == SYMBOL_REF
8678 && XSTR (operands[1], 0)[0] == '.')
8680 const char *name = XSTR (operands[1], 0);
8682 while (*name == '.')
8684 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
8685 CONSTANT_POOL_ADDRESS_P (new_ref)
8686 = CONSTANT_POOL_ADDRESS_P (operands[1]);
8687 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
8688 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
8689 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
8690 operands[1] = new_ref;
8693 if (DEFAULT_ABI == ABI_DARWIN)
8696 if (MACHO_DYNAMIC_NO_PIC_P)
8698 /* Take care of any required data indirection. */
8699 operands[1] = rs6000_machopic_legitimize_pic_address (
8700 operands[1], mode, operands[0]);
8701 if (operands[0] != operands[1])
8702 emit_insn (gen_rtx_SET (VOIDmode,
8703 operands[0], operands[1]));
8707 emit_insn (gen_macho_high (target, operands[1]));
8708 emit_insn (gen_macho_low (operands[0], target, operands[1]));
8712 emit_insn (gen_elf_high (target, operands[1]));
8713 emit_insn (gen_elf_low (operands[0], target, operands[1]));
8717 /* If this is a SYMBOL_REF that refers to a constant pool entry,
8718 and we have put it in the TOC, we just need to make a TOC-relative
8721 && GET_CODE (operands[1]) == SYMBOL_REF
8722 && use_toc_relative_ref (operands[1]))
8723 operands[1] = create_TOC_reference (operands[1], operands[0]);
8724 else if (mode == Pmode
8725 && CONSTANT_P (operands[1])
8726 && GET_CODE (operands[1]) != HIGH
8727 && ((GET_CODE (operands[1]) != CONST_INT
8728 && ! easy_fp_constant (operands[1], mode))
8729 || (GET_CODE (operands[1]) == CONST_INT
8730 && (num_insns_constant (operands[1], mode)
8731 > (TARGET_CMODEL != CMODEL_SMALL ? 3 : 2)))
8732 || (GET_CODE (operands[0]) == REG
8733 && FP_REGNO_P (REGNO (operands[0]))))
8734 && !toc_relative_expr_p (operands[1], false)
8735 && (TARGET_CMODEL == CMODEL_SMALL
8736 || can_create_pseudo_p ()
8737 || (REG_P (operands[0])
8738 && INT_REG_OK_FOR_BASE_P (operands[0], true))))
8742 /* Darwin uses a special PIC legitimizer. */
8743 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
8746 rs6000_machopic_legitimize_pic_address (operands[1], mode,
8748 if (operands[0] != operands[1])
8749 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
8754 /* If we are to limit the number of things we put in the TOC and
8755 this is a symbol plus a constant we can add in one insn,
8756 just put the symbol in the TOC and add the constant. Don't do
8757 this if reload is in progress. */
8758 if (GET_CODE (operands[1]) == CONST
8759 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
8760 && GET_CODE (XEXP (operands[1], 0)) == PLUS
8761 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
8762 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
8763 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
8764 && ! side_effects_p (operands[0]))
8767 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
8768 rtx other = XEXP (XEXP (operands[1], 0), 1);
8770 sym = force_reg (mode, sym);
8771 emit_insn (gen_add3_insn (operands[0], sym, other));
8775 operands[1] = force_const_mem (mode, operands[1]);
8778 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
8779 && constant_pool_expr_p (XEXP (operands[1], 0))
8780 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
8781 get_pool_constant (XEXP (operands[1], 0)),
8782 get_pool_mode (XEXP (operands[1], 0))))
8784 rtx tocref = create_TOC_reference (XEXP (operands[1], 0),
8786 operands[1] = gen_const_mem (mode, tocref);
8787 set_mem_alias_set (operands[1], get_TOC_alias_set ());
8793 if (!VECTOR_MEM_VSX_P (TImode))
8794 rs6000_eliminate_indexed_memrefs (operands);
8798 rs6000_eliminate_indexed_memrefs (operands);
8802 fatal_insn ("bad move", gen_rtx_SET (VOIDmode, dest, source));
8805 /* Above, we may have called force_const_mem which may have returned
8806 an invalid address. If we can, fix this up; otherwise, reload will
8807 have to deal with it. */
8808 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
8809 operands[1] = validize_mem (operands[1]);
8812 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
8815 /* Return true if a structure, union or array containing FIELD should be
8816 accessed using `BLKMODE'.
8818 For the SPE, simd types are V2SI, and gcc can be tempted to put the
8819 entire thing in a DI and use subregs to access the internals.
8820 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
8821 back-end. Because a single GPR can hold a V2SI, but not a DI, the
8822 best thing to do is set structs to BLKmode and avoid Severe Tire
8825 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
8826 fit into 1, whereas DI still needs two. */
8829 rs6000_member_type_forces_blk (const_tree field, machine_mode mode)
8831 return ((TARGET_SPE && TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE)
8832 || (TARGET_E500_DOUBLE && mode == DFmode));
8835 /* Nonzero if we can use a floating-point register to pass this arg. */
8836 #define USE_FP_FOR_ARG_P(CUM,MODE) \
8837 (SCALAR_FLOAT_MODE_P (MODE) \
8838 && (CUM)->fregno <= FP_ARG_MAX_REG \
8839 && TARGET_HARD_FLOAT && TARGET_FPRS)
8841 /* Nonzero if we can use an AltiVec register to pass this arg. */
8842 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
8843 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
8844 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
8845 && TARGET_ALTIVEC_ABI \
8848 /* Walk down the type tree of TYPE counting consecutive base elements.
8849 If *MODEP is VOIDmode, then set it to the first valid floating point
8850 or vector type. If a non-floating point or vector type is found, or
8851 if a floating point or vector type that doesn't match a non-VOIDmode
8852 *MODEP is found, then return -1, otherwise return the count in the
8856 rs6000_aggregate_candidate (const_tree type, machine_mode *modep)
8861 switch (TREE_CODE (type))
8864 mode = TYPE_MODE (type);
8865 if (!SCALAR_FLOAT_MODE_P (mode))
8868 if (*modep == VOIDmode)
8877 mode = TYPE_MODE (TREE_TYPE (type));
8878 if (!SCALAR_FLOAT_MODE_P (mode))
8881 if (*modep == VOIDmode)
8890 if (!TARGET_ALTIVEC_ABI || !TARGET_ALTIVEC)
8893 /* Use V4SImode as representative of all 128-bit vector types. */
8894 size = int_size_in_bytes (type);
8904 if (*modep == VOIDmode)
8907 /* Vector modes are considered to be opaque: two vectors are
8908 equivalent for the purposes of being homogeneous aggregates
8909 if they are the same size. */
8918 tree index = TYPE_DOMAIN (type);
8920 /* Can't handle incomplete types nor sizes that are not
8922 if (!COMPLETE_TYPE_P (type)
8923 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
8926 count = rs6000_aggregate_candidate (TREE_TYPE (type), modep);
8929 || !TYPE_MAX_VALUE (index)
8930 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index))
8931 || !TYPE_MIN_VALUE (index)
8932 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index))
8936 count *= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index))
8937 - tree_to_uhwi (TYPE_MIN_VALUE (index)));
8939 /* There must be no padding. */
8940 if (wi::ne_p (TYPE_SIZE (type), count * GET_MODE_BITSIZE (*modep)))
8952 /* Can't handle incomplete types nor sizes that are not
8954 if (!COMPLETE_TYPE_P (type)
8955 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
8958 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
8960 if (TREE_CODE (field) != FIELD_DECL)
8963 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
8969 /* There must be no padding. */
8970 if (wi::ne_p (TYPE_SIZE (type), count * GET_MODE_BITSIZE (*modep)))
8977 case QUAL_UNION_TYPE:
8979 /* These aren't very interesting except in a degenerate case. */
8984 /* Can't handle incomplete types nor sizes that are not
8986 if (!COMPLETE_TYPE_P (type)
8987 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)
8990 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
8992 if (TREE_CODE (field) != FIELD_DECL)
8995 sub_count = rs6000_aggregate_candidate (TREE_TYPE (field), modep);
8998 count = count > sub_count ? count : sub_count;
9001 /* There must be no padding. */
9002 if (wi::ne_p (TYPE_SIZE (type), count * GET_MODE_BITSIZE (*modep)))
9015 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
9016 float or vector aggregate that shall be passed in FP/vector registers
9017 according to the ELFv2 ABI, return the homogeneous element mode in
9018 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
9020 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
9023 rs6000_discover_homogeneous_aggregate (machine_mode mode, const_tree type,
9024 machine_mode *elt_mode,
9027 /* Note that we do not accept complex types at the top level as
9028 homogeneous aggregates; these types are handled via the
9029 targetm.calls.split_complex_arg mechanism. Complex types
9030 can be elements of homogeneous aggregates, however. */
9031 if (DEFAULT_ABI == ABI_ELFv2 && type && AGGREGATE_TYPE_P (type))
9033 machine_mode field_mode = VOIDmode;
9034 int field_count = rs6000_aggregate_candidate (type, &field_mode);
9036 if (field_count > 0)
9038 int n_regs = (SCALAR_FLOAT_MODE_P (field_mode)?
9039 (GET_MODE_SIZE (field_mode) + 7) >> 3 : 1);
9041 /* The ELFv2 ABI allows homogeneous aggregates to occupy
9042 up to AGGR_ARG_NUM_REG registers. */
9043 if (field_count * n_regs <= AGGR_ARG_NUM_REG)
9046 *elt_mode = field_mode;
9048 *n_elts = field_count;
9061 /* Return a nonzero value to say to return the function value in
9062 memory, just as large structures are always returned. TYPE will be
9063 the data type of the value, and FNTYPE will be the type of the
9064 function doing the returning, or @code{NULL} for libcalls.
9066 The AIX ABI for the RS/6000 specifies that all structures are
9067 returned in memory. The Darwin ABI does the same.
9069 For the Darwin 64 Bit ABI, a function result can be returned in
9070 registers or in memory, depending on the size of the return data
9071 type. If it is returned in registers, the value occupies the same
9072 registers as it would if it were the first and only function
9073 argument. Otherwise, the function places its result in memory at
9074 the location pointed to by GPR3.
9076 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
9077 but a draft put them in memory, and GCC used to implement the draft
9078 instead of the final standard. Therefore, aix_struct_return
9079 controls this instead of DEFAULT_ABI; V.4 targets needing backward
9080 compatibility can change DRAFT_V4_STRUCT_RET to override the
9081 default, and -m switches get the final word. See
9082 rs6000_option_override_internal for more details.
9084 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
9085 long double support is enabled. These values are returned in memory.
9087 int_size_in_bytes returns -1 for variable size objects, which go in
9088 memory always. The cast to unsigned makes -1 > 8. */
9091 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
9093 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
9095 && rs6000_darwin64_abi
9096 && TREE_CODE (type) == RECORD_TYPE
9097 && int_size_in_bytes (type) > 0)
9099 CUMULATIVE_ARGS valcum;
9103 valcum.fregno = FP_ARG_MIN_REG;
9104 valcum.vregno = ALTIVEC_ARG_MIN_REG;
9105 /* Do a trial code generation as if this were going to be passed
9106 as an argument; if any part goes in memory, we return NULL. */
9107 valret = rs6000_darwin64_record_arg (&valcum, type, true, true);
9110 /* Otherwise fall through to more conventional ABI rules. */
9113 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
9114 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type), type,
9118 /* The ELFv2 ABI returns aggregates up to 16B in registers */
9119 if (DEFAULT_ABI == ABI_ELFv2 && AGGREGATE_TYPE_P (type)
9120 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 16)
9123 if (AGGREGATE_TYPE_P (type)
9124 && (aix_struct_return
9125 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
9128 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
9129 modes only exist for GCC vector types if -maltivec. */
9130 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
9131 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
9134 /* Return synthetic vectors in memory. */
9135 if (TREE_CODE (type) == VECTOR_TYPE
9136 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
9138 static bool warned_for_return_big_vectors = false;
9139 if (!warned_for_return_big_vectors)
9141 warning (0, "GCC vector returned by reference: "
9142 "non-standard ABI extension with no compatibility guarantee");
9143 warned_for_return_big_vectors = true;
9148 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
9154 /* Specify whether values returned in registers should be at the most
9155 significant end of a register. We want aggregates returned by
9156 value to match the way aggregates are passed to functions. */
9159 rs6000_return_in_msb (const_tree valtype)
9161 return (DEFAULT_ABI == ABI_ELFv2
9163 && AGGREGATE_TYPE_P (valtype)
9164 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype), valtype) == upward);
9167 #ifdef HAVE_AS_GNU_ATTRIBUTE
9168 /* Return TRUE if a call to function FNDECL may be one that
9169 potentially affects the function calling ABI of the object file. */
9172 call_ABI_of_interest (tree fndecl)
9174 if (symtab->state == EXPANSION)
9176 struct cgraph_node *c_node;
9178 /* Libcalls are always interesting. */
9179 if (fndecl == NULL_TREE)
9182 /* Any call to an external function is interesting. */
9183 if (DECL_EXTERNAL (fndecl))
9186 /* Interesting functions that we are emitting in this object file. */
9187 c_node = cgraph_node::get (fndecl);
9188 c_node = c_node->ultimate_alias_target ();
9189 return !c_node->only_called_directly_p ();
9195 /* Initialize a variable CUM of type CUMULATIVE_ARGS
9196 for a call to a function whose data type is FNTYPE.
9197 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
9199 For incoming args we set the number of arguments in the prototype large
9200 so we never return a PARALLEL. */
9203 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
9204 rtx libname ATTRIBUTE_UNUSED, int incoming,
9205 int libcall, int n_named_args,
9206 tree fndecl ATTRIBUTE_UNUSED,
9207 machine_mode return_mode ATTRIBUTE_UNUSED)
9209 static CUMULATIVE_ARGS zero_cumulative;
9211 *cum = zero_cumulative;
9213 cum->fregno = FP_ARG_MIN_REG;
9214 cum->vregno = ALTIVEC_ARG_MIN_REG;
9215 cum->prototype = (fntype && prototype_p (fntype));
9216 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
9217 ? CALL_LIBCALL : CALL_NORMAL);
9218 cum->sysv_gregno = GP_ARG_MIN_REG;
9219 cum->stdarg = stdarg_p (fntype);
9221 cum->nargs_prototype = 0;
9222 if (incoming || cum->prototype)
9223 cum->nargs_prototype = n_named_args;
9225 /* Check for a longcall attribute. */
9226 if ((!fntype && rs6000_default_long_calls)
9228 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
9229 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
9230 cum->call_cookie |= CALL_LONG;
9232 if (TARGET_DEBUG_ARG)
9234 fprintf (stderr, "\ninit_cumulative_args:");
9237 tree ret_type = TREE_TYPE (fntype);
9238 fprintf (stderr, " ret code = %s,",
9239 get_tree_code_name (TREE_CODE (ret_type)));
9242 if (cum->call_cookie & CALL_LONG)
9243 fprintf (stderr, " longcall,");
9245 fprintf (stderr, " proto = %d, nargs = %d\n",
9246 cum->prototype, cum->nargs_prototype);
9249 #ifdef HAVE_AS_GNU_ATTRIBUTE
9250 if (DEFAULT_ABI == ABI_V4)
9252 cum->escapes = call_ABI_of_interest (fndecl);
9259 return_type = TREE_TYPE (fntype);
9260 return_mode = TYPE_MODE (return_type);
9263 return_type = lang_hooks.types.type_for_mode (return_mode, 0);
9265 if (return_type != NULL)
9267 if (TREE_CODE (return_type) == RECORD_TYPE
9268 && TYPE_TRANSPARENT_AGGR (return_type))
9270 return_type = TREE_TYPE (first_field (return_type));
9271 return_mode = TYPE_MODE (return_type);
9273 if (AGGREGATE_TYPE_P (return_type)
9274 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (return_type)
9276 rs6000_returns_struct = true;
9278 if (SCALAR_FLOAT_MODE_P (return_mode))
9279 rs6000_passes_float = true;
9280 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode)
9281 || SPE_VECTOR_MODE (return_mode))
9282 rs6000_passes_vector = true;
9289 && TARGET_ALTIVEC_ABI
9290 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
9292 error ("cannot return value in vector register because"
9293 " altivec instructions are disabled, use -maltivec"
9298 /* Return true if TYPE must be passed on the stack and not in registers. */
9301 rs6000_must_pass_in_stack (machine_mode mode, const_tree type)
9303 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2 || TARGET_64BIT)
9304 return must_pass_in_stack_var_size (mode, type);
9306 return must_pass_in_stack_var_size_or_pad (mode, type);
9309 /* If defined, a C expression which determines whether, and in which
9310 direction, to pad out an argument with extra space. The value
9311 should be of type `enum direction': either `upward' to pad above
9312 the argument, `downward' to pad below, or `none' to inhibit
9315 For the AIX ABI structs are always stored left shifted in their
9319 function_arg_padding (machine_mode mode, const_tree type)
9321 #ifndef AGGREGATE_PADDING_FIXED
9322 #define AGGREGATE_PADDING_FIXED 0
9324 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
9325 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
9328 if (!AGGREGATE_PADDING_FIXED)
9330 /* GCC used to pass structures of the same size as integer types as
9331 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
9332 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
9333 passed padded downward, except that -mstrict-align further
9334 muddied the water in that multi-component structures of 2 and 4
9335 bytes in size were passed padded upward.
9337 The following arranges for best compatibility with previous
9338 versions of gcc, but removes the -mstrict-align dependency. */
9339 if (BYTES_BIG_ENDIAN)
9341 HOST_WIDE_INT size = 0;
9343 if (mode == BLKmode)
9345 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
9346 size = int_size_in_bytes (type);
9349 size = GET_MODE_SIZE (mode);
9351 if (size == 1 || size == 2 || size == 4)
9357 if (AGGREGATES_PAD_UPWARD_ALWAYS)
9359 if (type != 0 && AGGREGATE_TYPE_P (type))
9363 /* Fall back to the default. */
9364 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
9367 /* If defined, a C expression that gives the alignment boundary, in bits,
9368 of an argument with the specified mode and type. If it is not defined,
9369 PARM_BOUNDARY is used for all arguments.
9371 V.4 wants long longs and doubles to be double word aligned. Just
9372 testing the mode size is a boneheaded way to do this as it means
9373 that other types such as complex int are also double word aligned.
9374 However, we're stuck with this because changing the ABI might break
9375 existing library interfaces.
9377 Doubleword align SPE vectors.
9378 Quadword align Altivec/VSX vectors.
9379 Quadword align large synthetic vector types. */
9382 rs6000_function_arg_boundary (machine_mode mode, const_tree type)
9384 machine_mode elt_mode;
9387 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
9389 if (DEFAULT_ABI == ABI_V4
9390 && (GET_MODE_SIZE (mode) == 8
9391 || (TARGET_HARD_FLOAT
9393 && (mode == TFmode || mode == TDmode))))
9395 else if (SPE_VECTOR_MODE (mode)
9396 || (type && TREE_CODE (type) == VECTOR_TYPE
9397 && int_size_in_bytes (type) >= 8
9398 && int_size_in_bytes (type) < 16))
9400 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
9401 || (type && TREE_CODE (type) == VECTOR_TYPE
9402 && int_size_in_bytes (type) >= 16))
9405 /* Aggregate types that need > 8 byte alignment are quadword-aligned
9406 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
9407 -mcompat-align-parm is used. */
9408 if (((DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)
9409 || DEFAULT_ABI == ABI_ELFv2)
9410 && type && TYPE_ALIGN (type) > 64)
9412 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
9413 or homogeneous float/vector aggregates here. We already handled
9414 vector aggregates above, but still need to check for float here. */
9415 bool aggregate_p = (AGGREGATE_TYPE_P (type)
9416 && !SCALAR_FLOAT_MODE_P (elt_mode));
9418 /* We used to check for BLKmode instead of the above aggregate type
9419 check. Warn when this results in any difference to the ABI. */
9420 if (aggregate_p != (mode == BLKmode))
9423 if (!warned && warn_psabi)
9426 inform (input_location,
9427 "the ABI of passing aggregates with %d-byte alignment"
9428 " has changed in GCC 5",
9429 (int) TYPE_ALIGN (type) / BITS_PER_UNIT);
9437 /* Similar for the Darwin64 ABI. Note that for historical reasons we
9438 implement the "aggregate type" check as a BLKmode check here; this
9439 means certain aggregate types are in fact not aligned. */
9440 if (TARGET_MACHO && rs6000_darwin64_abi
9442 && type && TYPE_ALIGN (type) > 64)
9445 return PARM_BOUNDARY;
9448 /* The offset in words to the start of the parameter save area. */
9451 rs6000_parm_offset (void)
9453 return (DEFAULT_ABI == ABI_V4 ? 2
9454 : DEFAULT_ABI == ABI_ELFv2 ? 4
9458 /* For a function parm of MODE and TYPE, return the starting word in
9459 the parameter area. NWORDS of the parameter area are already used. */
9462 rs6000_parm_start (machine_mode mode, const_tree type,
9463 unsigned int nwords)
9467 align = rs6000_function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
9468 return nwords + (-(rs6000_parm_offset () + nwords) & align);
9471 /* Compute the size (in words) of a function argument. */
9473 static unsigned long
9474 rs6000_arg_size (machine_mode mode, const_tree type)
9478 if (mode != BLKmode)
9479 size = GET_MODE_SIZE (mode);
9481 size = int_size_in_bytes (type);
9484 return (size + 3) >> 2;
9486 return (size + 7) >> 3;
9489 /* Use this to flush pending int fields. */
9492 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
9493 HOST_WIDE_INT bitpos, int final)
9495 unsigned int startbit, endbit;
9496 int intregs, intoffset;
9499 /* Handle the situations where a float is taking up the first half
9500 of the GPR, and the other half is empty (typically due to
9501 alignment restrictions). We can detect this by a 8-byte-aligned
9502 int field, or by seeing that this is the final flush for this
9503 argument. Count the word and continue on. */
9504 if (cum->floats_in_gpr == 1
9505 && (cum->intoffset % 64 == 0
9506 || (cum->intoffset == -1 && final)))
9509 cum->floats_in_gpr = 0;
9512 if (cum->intoffset == -1)
9515 intoffset = cum->intoffset;
9516 cum->intoffset = -1;
9517 cum->floats_in_gpr = 0;
9519 if (intoffset % BITS_PER_WORD != 0)
9521 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
9523 if (mode == BLKmode)
9525 /* We couldn't find an appropriate mode, which happens,
9526 e.g., in packed structs when there are 3 bytes to load.
9527 Back intoffset back to the beginning of the word in this
9529 intoffset = intoffset & -BITS_PER_WORD;
9533 startbit = intoffset & -BITS_PER_WORD;
9534 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
9535 intregs = (endbit - startbit) / BITS_PER_WORD;
9536 cum->words += intregs;
9537 /* words should be unsigned. */
9538 if ((unsigned)cum->words < (endbit/BITS_PER_WORD))
9540 int pad = (endbit/BITS_PER_WORD) - cum->words;
9545 /* The darwin64 ABI calls for us to recurse down through structs,
9546 looking for elements passed in registers. Unfortunately, we have
9547 to track int register count here also because of misalignments
9548 in powerpc alignment mode. */
9551 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
9553 HOST_WIDE_INT startbitpos)
9557 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
9558 if (TREE_CODE (f) == FIELD_DECL)
9560 HOST_WIDE_INT bitpos = startbitpos;
9561 tree ftype = TREE_TYPE (f);
9563 if (ftype == error_mark_node)
9565 mode = TYPE_MODE (ftype);
9567 if (DECL_SIZE (f) != 0
9568 && tree_fits_uhwi_p (bit_position (f)))
9569 bitpos += int_bit_position (f);
9571 /* ??? FIXME: else assume zero offset. */
9573 if (TREE_CODE (ftype) == RECORD_TYPE)
9574 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
9575 else if (USE_FP_FOR_ARG_P (cum, mode))
9577 unsigned n_fpregs = (GET_MODE_SIZE (mode) + 7) >> 3;
9578 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
9579 cum->fregno += n_fpregs;
9580 /* Single-precision floats present a special problem for
9581 us, because they are smaller than an 8-byte GPR, and so
9582 the structure-packing rules combined with the standard
9583 varargs behavior mean that we want to pack float/float
9584 and float/int combinations into a single register's
9585 space. This is complicated by the arg advance flushing,
9586 which works on arbitrarily large groups of int-type
9590 if (cum->floats_in_gpr == 1)
9592 /* Two floats in a word; count the word and reset
9595 cum->floats_in_gpr = 0;
9597 else if (bitpos % 64 == 0)
9599 /* A float at the beginning of an 8-byte word;
9600 count it and put off adjusting cum->words until
9601 we see if a arg advance flush is going to do it
9603 cum->floats_in_gpr++;
9607 /* The float is at the end of a word, preceded
9608 by integer fields, so the arg advance flush
9609 just above has already set cum->words and
9610 everything is taken care of. */
9614 cum->words += n_fpregs;
9616 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
9618 rs6000_darwin64_record_arg_advance_flush (cum, bitpos, 0);
9622 else if (cum->intoffset == -1)
9623 cum->intoffset = bitpos;
9627 /* Check for an item that needs to be considered specially under the darwin 64
9628 bit ABI. These are record types where the mode is BLK or the structure is
9631 rs6000_darwin64_struct_check_p (machine_mode mode, const_tree type)
9633 return rs6000_darwin64_abi
9634 && ((mode == BLKmode
9635 && TREE_CODE (type) == RECORD_TYPE
9636 && int_size_in_bytes (type) > 0)
9637 || (type && TREE_CODE (type) == RECORD_TYPE
9638 && int_size_in_bytes (type) == 8)) ? 1 : 0;
9641 /* Update the data in CUM to advance over an argument
9642 of mode MODE and data type TYPE.
9643 (TYPE is null for libcalls where that information may not be available.)
9645 Note that for args passed by reference, function_arg will be called
9646 with MODE and TYPE set to that of the pointer to the arg, not the arg
9650 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS *cum, machine_mode mode,
9651 const_tree type, bool named, int depth)
9653 machine_mode elt_mode;
9656 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
9658 /* Only tick off an argument if we're not recursing. */
9660 cum->nargs_prototype--;
9662 #ifdef HAVE_AS_GNU_ATTRIBUTE
9663 if (DEFAULT_ABI == ABI_V4
9666 if (SCALAR_FLOAT_MODE_P (mode))
9667 rs6000_passes_float = true;
9668 else if (named && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
9669 rs6000_passes_vector = true;
9670 else if (SPE_VECTOR_MODE (mode)
9672 && cum->sysv_gregno <= GP_ARG_MAX_REG)
9673 rs6000_passes_vector = true;
9677 if (TARGET_ALTIVEC_ABI
9678 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode)
9679 || (type && TREE_CODE (type) == VECTOR_TYPE
9680 && int_size_in_bytes (type) == 16)))
9684 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
9686 cum->vregno += n_elts;
9688 if (!TARGET_ALTIVEC)
9689 error ("cannot pass argument in vector register because"
9690 " altivec instructions are disabled, use -maltivec"
9693 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
9694 even if it is going to be passed in a vector register.
9695 Darwin does the same for variable-argument functions. */
9696 if (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
9698 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
9708 /* Vector parameters must be 16-byte aligned. In 32-bit
9709 mode this means we need to take into account the offset
9710 to the parameter save area. In 64-bit mode, they just
9711 have to start on an even word, since the parameter save
9712 area is 16-byte aligned. */
9714 align = -(rs6000_parm_offset () + cum->words) & 3;
9716 align = cum->words & 1;
9717 cum->words += align + rs6000_arg_size (mode, type);
9719 if (TARGET_DEBUG_ARG)
9721 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
9723 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
9724 cum->nargs_prototype, cum->prototype,
9725 GET_MODE_NAME (mode));
9729 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
9731 && cum->sysv_gregno <= GP_ARG_MAX_REG)
9734 else if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
9736 int size = int_size_in_bytes (type);
9737 /* Variable sized types have size == -1 and are
9738 treated as if consisting entirely of ints.
9739 Pad to 16 byte boundary if needed. */
9740 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
9741 && (cum->words % 2) != 0)
9743 /* For varargs, we can just go up by the size of the struct. */
9745 cum->words += (size + 7) / 8;
9748 /* It is tempting to say int register count just goes up by
9749 sizeof(type)/8, but this is wrong in a case such as
9750 { int; double; int; } [powerpc alignment]. We have to
9751 grovel through the fields for these too. */
9753 cum->floats_in_gpr = 0;
9754 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
9755 rs6000_darwin64_record_arg_advance_flush (cum,
9756 size * BITS_PER_UNIT, 1);
9758 if (TARGET_DEBUG_ARG)
9760 fprintf (stderr, "function_adv: words = %2d, align=%d, size=%d",
9761 cum->words, TYPE_ALIGN (type), size);
9763 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
9764 cum->nargs_prototype, cum->prototype,
9765 GET_MODE_NAME (mode));
9768 else if (DEFAULT_ABI == ABI_V4)
9770 if (TARGET_HARD_FLOAT && TARGET_FPRS
9771 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
9772 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
9773 || (mode == TFmode && !TARGET_IEEEQUAD)
9774 || mode == SDmode || mode == DDmode || mode == TDmode))
9776 /* _Decimal128 must use an even/odd register pair. This assumes
9777 that the register number is odd when fregno is odd. */
9778 if (mode == TDmode && (cum->fregno % 2) == 1)
9781 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
9782 <= FP_ARG_V4_MAX_REG)
9783 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
9786 cum->fregno = FP_ARG_V4_MAX_REG + 1;
9787 if (mode == DFmode || mode == TFmode
9788 || mode == DDmode || mode == TDmode)
9789 cum->words += cum->words & 1;
9790 cum->words += rs6000_arg_size (mode, type);
9795 int n_words = rs6000_arg_size (mode, type);
9796 int gregno = cum->sysv_gregno;
9798 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9799 (r7,r8) or (r9,r10). As does any other 2 word item such
9800 as complex int due to a historical mistake. */
9802 gregno += (1 - gregno) & 1;
9804 /* Multi-reg args are not split between registers and stack. */
9805 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
9807 /* Long long and SPE vectors are aligned on the stack.
9808 So are other 2 word items such as complex int due to
9809 a historical mistake. */
9811 cum->words += cum->words & 1;
9812 cum->words += n_words;
9815 /* Note: continuing to accumulate gregno past when we've started
9816 spilling to the stack indicates the fact that we've started
9817 spilling to the stack to expand_builtin_saveregs. */
9818 cum->sysv_gregno = gregno + n_words;
9821 if (TARGET_DEBUG_ARG)
9823 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
9824 cum->words, cum->fregno);
9825 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
9826 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
9827 fprintf (stderr, "mode = %4s, named = %d\n",
9828 GET_MODE_NAME (mode), named);
9833 int n_words = rs6000_arg_size (mode, type);
9834 int start_words = cum->words;
9835 int align_words = rs6000_parm_start (mode, type, start_words);
9837 cum->words = align_words + n_words;
9839 if (SCALAR_FLOAT_MODE_P (elt_mode)
9840 && TARGET_HARD_FLOAT && TARGET_FPRS)
9842 /* _Decimal128 must be passed in an even/odd float register pair.
9843 This assumes that the register number is odd when fregno is
9845 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
9847 cum->fregno += n_elts * ((GET_MODE_SIZE (elt_mode) + 7) >> 3);
9850 if (TARGET_DEBUG_ARG)
9852 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
9853 cum->words, cum->fregno);
9854 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
9855 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
9856 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
9857 named, align_words - start_words, depth);
9863 rs6000_function_arg_advance (cumulative_args_t cum, machine_mode mode,
9864 const_tree type, bool named)
9866 rs6000_function_arg_advance_1 (get_cumulative_args (cum), mode, type, named,
9871 spe_build_register_parallel (machine_mode mode, int gregno)
9878 r1 = gen_rtx_REG (DImode, gregno);
9879 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
9880 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
9884 r1 = gen_rtx_REG (DImode, gregno);
9885 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
9886 r3 = gen_rtx_REG (DImode, gregno + 2);
9887 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
9888 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
9891 r1 = gen_rtx_REG (DImode, gregno);
9892 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
9893 r3 = gen_rtx_REG (DImode, gregno + 2);
9894 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
9895 r5 = gen_rtx_REG (DImode, gregno + 4);
9896 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
9897 r7 = gen_rtx_REG (DImode, gregno + 6);
9898 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
9899 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
9906 /* Determine where to put a SIMD argument on the SPE. */
9908 rs6000_spe_function_arg (const CUMULATIVE_ARGS *cum, machine_mode mode,
9911 int gregno = cum->sysv_gregno;
9913 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
9914 are passed and returned in a pair of GPRs for ABI compatibility. */
9915 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
9916 || mode == DCmode || mode == TCmode))
9918 int n_words = rs6000_arg_size (mode, type);
9920 /* Doubles go in an odd/even register pair (r5/r6, etc). */
9922 gregno += (1 - gregno) & 1;
9924 /* Multi-reg args are not split between registers and stack. */
9925 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
9928 return spe_build_register_parallel (mode, gregno);
9932 int n_words = rs6000_arg_size (mode, type);
9934 /* SPE vectors are put in odd registers. */
9935 if (n_words == 2 && (gregno & 1) == 0)
9938 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
9941 machine_mode m = SImode;
9943 r1 = gen_rtx_REG (m, gregno);
9944 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
9945 r2 = gen_rtx_REG (m, gregno + 1);
9946 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
9947 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
9954 if (gregno <= GP_ARG_MAX_REG)
9955 return gen_rtx_REG (mode, gregno);
9961 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
9962 structure between cum->intoffset and bitpos to integer registers. */
9965 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
9966 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
9970 unsigned int startbit, endbit;
9971 int this_regno, intregs, intoffset;
9974 if (cum->intoffset == -1)
9977 intoffset = cum->intoffset;
9978 cum->intoffset = -1;
9980 /* If this is the trailing part of a word, try to only load that
9981 much into the register. Otherwise load the whole register. Note
9982 that in the latter case we may pick up unwanted bits. It's not a
9983 problem at the moment but may wish to revisit. */
9985 if (intoffset % BITS_PER_WORD != 0)
9987 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
9989 if (mode == BLKmode)
9991 /* We couldn't find an appropriate mode, which happens,
9992 e.g., in packed structs when there are 3 bytes to load.
9993 Back intoffset back to the beginning of the word in this
9995 intoffset = intoffset & -BITS_PER_WORD;
10002 startbit = intoffset & -BITS_PER_WORD;
10003 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
10004 intregs = (endbit - startbit) / BITS_PER_WORD;
10005 this_regno = cum->words + intoffset / BITS_PER_WORD;
10007 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
10008 cum->use_stack = 1;
10010 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
10014 intoffset /= BITS_PER_UNIT;
10017 regno = GP_ARG_MIN_REG + this_regno;
10018 reg = gen_rtx_REG (mode, regno);
10020 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
10023 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
10027 while (intregs > 0);
10030 /* Recursive workhorse for the following. */
10033 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
10034 HOST_WIDE_INT startbitpos, rtx rvec[],
10039 for (f = TYPE_FIELDS (type); f ; f = DECL_CHAIN (f))
10040 if (TREE_CODE (f) == FIELD_DECL)
10042 HOST_WIDE_INT bitpos = startbitpos;
10043 tree ftype = TREE_TYPE (f);
10045 if (ftype == error_mark_node)
10047 mode = TYPE_MODE (ftype);
10049 if (DECL_SIZE (f) != 0
10050 && tree_fits_uhwi_p (bit_position (f)))
10051 bitpos += int_bit_position (f);
10053 /* ??? FIXME: else assume zero offset. */
10055 if (TREE_CODE (ftype) == RECORD_TYPE)
10056 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
10057 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode))
10059 unsigned n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
10063 case SCmode: mode = SFmode; break;
10064 case DCmode: mode = DFmode; break;
10065 case TCmode: mode = TFmode; break;
10069 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
10070 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
10072 gcc_assert (cum->fregno == FP_ARG_MAX_REG
10073 && (mode == TFmode || mode == TDmode));
10074 /* Long double or _Decimal128 split over regs and memory. */
10075 mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
10079 = gen_rtx_EXPR_LIST (VOIDmode,
10080 gen_rtx_REG (mode, cum->fregno++),
10081 GEN_INT (bitpos / BITS_PER_UNIT));
10082 if (mode == TFmode || mode == TDmode)
10085 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, 1))
10087 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
10089 = gen_rtx_EXPR_LIST (VOIDmode,
10090 gen_rtx_REG (mode, cum->vregno++),
10091 GEN_INT (bitpos / BITS_PER_UNIT));
10093 else if (cum->intoffset == -1)
10094 cum->intoffset = bitpos;
10098 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
10099 the register(s) to be used for each field and subfield of a struct
10100 being passed by value, along with the offset of where the
10101 register's value may be found in the block. FP fields go in FP
10102 register, vector fields go in vector registers, and everything
10103 else goes in int registers, packed as in memory.
10105 This code is also used for function return values. RETVAL indicates
10106 whether this is the case.
10108 Much of this is taken from the SPARC V9 port, which has a similar
10109 calling convention. */
10112 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
10113 bool named, bool retval)
10115 rtx rvec[FIRST_PSEUDO_REGISTER];
10116 int k = 1, kbase = 1;
10117 HOST_WIDE_INT typesize = int_size_in_bytes (type);
10118 /* This is a copy; modifications are not visible to our caller. */
10119 CUMULATIVE_ARGS copy_cum = *orig_cum;
10120 CUMULATIVE_ARGS *cum = ©_cum;
10122 /* Pad to 16 byte boundary if needed. */
10123 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
10124 && (cum->words % 2) != 0)
10127 cum->intoffset = 0;
10128 cum->use_stack = 0;
10129 cum->named = named;
10131 /* Put entries into rvec[] for individual FP and vector fields, and
10132 for the chunks of memory that go in int regs. Note we start at
10133 element 1; 0 is reserved for an indication of using memory, and
10134 may or may not be filled in below. */
10135 rs6000_darwin64_record_arg_recurse (cum, type, /* startbit pos= */ 0, rvec, &k);
10136 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
10138 /* If any part of the struct went on the stack put all of it there.
10139 This hack is because the generic code for
10140 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
10141 parts of the struct are not at the beginning. */
10142 if (cum->use_stack)
10145 return NULL_RTX; /* doesn't go in registers at all */
10147 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
10149 if (k > 1 || cum->use_stack)
10150 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
10155 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
10158 rs6000_mixed_function_arg (machine_mode mode, const_tree type,
10163 rtx rvec[GP_ARG_NUM_REG + 1];
10165 if (align_words >= GP_ARG_NUM_REG)
10168 n_units = rs6000_arg_size (mode, type);
10170 /* Optimize the simple case where the arg fits in one gpr, except in
10171 the case of BLKmode due to assign_parms assuming that registers are
10172 BITS_PER_WORD wide. */
10174 || (n_units == 1 && mode != BLKmode))
10175 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
10178 if (align_words + n_units > GP_ARG_NUM_REG)
10179 /* Not all of the arg fits in gprs. Say that it goes in memory too,
10180 using a magic NULL_RTX component.
10181 This is not strictly correct. Only some of the arg belongs in
10182 memory, not all of it. However, the normal scheme using
10183 function_arg_partial_nregs can result in unusual subregs, eg.
10184 (subreg:SI (reg:DF) 4), which are not handled well. The code to
10185 store the whole arg to memory is often more efficient than code
10186 to store pieces, and we know that space is available in the right
10187 place for the whole arg. */
10188 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
10193 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
10194 rtx off = GEN_INT (i++ * 4);
10195 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
10197 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
10199 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
10202 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
10203 but must also be copied into the parameter save area starting at
10204 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
10205 to the GPRs and/or memory. Return the number of elements used. */
10208 rs6000_psave_function_arg (machine_mode mode, const_tree type,
10209 int align_words, rtx *rvec)
10213 if (align_words < GP_ARG_NUM_REG)
10215 int n_words = rs6000_arg_size (mode, type);
10217 if (align_words + n_words > GP_ARG_NUM_REG
10219 || (TARGET_32BIT && TARGET_POWERPC64))
10221 /* If this is partially on the stack, then we only
10222 include the portion actually in registers here. */
10223 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
10226 if (align_words + n_words > GP_ARG_NUM_REG)
10228 /* Not all of the arg fits in gprs. Say that it goes in memory
10229 too, using a magic NULL_RTX component. Also see comment in
10230 rs6000_mixed_function_arg for why the normal
10231 function_arg_partial_nregs scheme doesn't work in this case. */
10232 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
10237 rtx r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
10238 rtx off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
10239 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
10241 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
10245 /* The whole arg fits in gprs. */
10246 rtx r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
10247 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
10252 /* It's entirely in memory. */
10253 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
10259 /* RVEC is a vector of K components of an argument of mode MODE.
10260 Construct the final function_arg return value from it. */
10263 rs6000_finish_function_arg (machine_mode mode, rtx *rvec, int k)
10265 gcc_assert (k >= 1);
10267 /* Avoid returning a PARALLEL in the trivial cases. */
10270 if (XEXP (rvec[0], 0) == NULL_RTX)
10273 if (GET_MODE (XEXP (rvec[0], 0)) == mode)
10274 return XEXP (rvec[0], 0);
10277 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
10280 /* Determine where to put an argument to a function.
10281 Value is zero to push the argument on the stack,
10282 or a hard register in which to store the argument.
10284 MODE is the argument's machine mode.
10285 TYPE is the data type of the argument (as a tree).
10286 This is null for libcalls where that information may
10288 CUM is a variable of type CUMULATIVE_ARGS which gives info about
10289 the preceding args and about the function being called. It is
10290 not modified in this routine.
10291 NAMED is nonzero if this argument is a named parameter
10292 (otherwise it is an extra parameter matching an ellipsis).
10294 On RS/6000 the first eight words of non-FP are normally in registers
10295 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
10296 Under V.4, the first 8 FP args are in registers.
10298 If this is floating-point and no prototype is specified, we use
10299 both an FP and integer register (or possibly FP reg and stack). Library
10300 functions (when CALL_LIBCALL is set) always have the proper types for args,
10301 so we can pass the FP value just in one register. emit_library_function
10302 doesn't support PARALLEL anyway.
10304 Note that for args passed by reference, function_arg will be called
10305 with MODE and TYPE set to that of the pointer to the arg, not the arg
10309 rs6000_function_arg (cumulative_args_t cum_v, machine_mode mode,
10310 const_tree type, bool named)
10312 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
10313 enum rs6000_abi abi = DEFAULT_ABI;
10314 machine_mode elt_mode;
10317 /* Return a marker to indicate whether CR1 needs to set or clear the
10318 bit that V.4 uses to say fp args were passed in registers.
10319 Assume that we don't need the marker for software floating point,
10320 or compiler generated library calls. */
10321 if (mode == VOIDmode)
10324 && (cum->call_cookie & CALL_LIBCALL) == 0
10326 || (cum->nargs_prototype < 0
10327 && (cum->prototype || TARGET_NO_PROTOTYPE))))
10329 /* For the SPE, we need to crxor CR6 always. */
10330 if (TARGET_SPE_ABI)
10331 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
10332 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
10333 return GEN_INT (cum->call_cookie
10334 | ((cum->fregno == FP_ARG_MIN_REG)
10335 ? CALL_V4_SET_FP_ARGS
10336 : CALL_V4_CLEAR_FP_ARGS));
10339 return GEN_INT (cum->call_cookie & ~CALL_LIBCALL);
10342 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10344 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
10346 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, /*retval= */false);
10347 if (rslt != NULL_RTX)
10349 /* Else fall through to usual handling. */
10352 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
10354 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
10358 /* Do we also need to pass this argument in the parameter
10360 if (TARGET_64BIT && ! cum->prototype)
10362 int align_words = (cum->words + 1) & ~1;
10363 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
10366 /* Describe where this argument goes in the vector registers. */
10367 for (i = 0; i < n_elts && cum->vregno + i <= ALTIVEC_ARG_MAX_REG; i++)
10369 r = gen_rtx_REG (elt_mode, cum->vregno + i);
10370 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
10371 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
10374 return rs6000_finish_function_arg (mode, rvec, k);
10376 else if (TARGET_ALTIVEC_ABI
10377 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
10378 || (type && TREE_CODE (type) == VECTOR_TYPE
10379 && int_size_in_bytes (type) == 16)))
10381 if (named || abi == ABI_V4)
10385 /* Vector parameters to varargs functions under AIX or Darwin
10386 get passed in memory and possibly also in GPRs. */
10387 int align, align_words, n_words;
10388 machine_mode part_mode;
10390 /* Vector parameters must be 16-byte aligned. In 32-bit
10391 mode this means we need to take into account the offset
10392 to the parameter save area. In 64-bit mode, they just
10393 have to start on an even word, since the parameter save
10394 area is 16-byte aligned. */
10396 align = -(rs6000_parm_offset () + cum->words) & 3;
10398 align = cum->words & 1;
10399 align_words = cum->words + align;
10401 /* Out of registers? Memory, then. */
10402 if (align_words >= GP_ARG_NUM_REG)
10405 if (TARGET_32BIT && TARGET_POWERPC64)
10406 return rs6000_mixed_function_arg (mode, type, align_words);
10408 /* The vector value goes in GPRs. Only the part of the
10409 value in GPRs is reported here. */
10411 n_words = rs6000_arg_size (mode, type);
10412 if (align_words + n_words > GP_ARG_NUM_REG)
10413 /* Fortunately, there are only two possibilities, the value
10414 is either wholly in GPRs or half in GPRs and half not. */
10415 part_mode = DImode;
10417 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
10420 else if (TARGET_SPE_ABI && TARGET_SPE
10421 && (SPE_VECTOR_MODE (mode)
10422 || (TARGET_E500_DOUBLE && (mode == DFmode
10425 || mode == TCmode))))
10426 return rs6000_spe_function_arg (cum, mode, type);
10428 else if (abi == ABI_V4)
10430 if (TARGET_HARD_FLOAT && TARGET_FPRS
10431 && ((TARGET_SINGLE_FLOAT && mode == SFmode)
10432 || (TARGET_DOUBLE_FLOAT && mode == DFmode)
10433 || (mode == TFmode && !TARGET_IEEEQUAD)
10434 || mode == SDmode || mode == DDmode || mode == TDmode))
10436 /* _Decimal128 must use an even/odd register pair. This assumes
10437 that the register number is odd when fregno is odd. */
10438 if (mode == TDmode && (cum->fregno % 2) == 1)
10441 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
10442 <= FP_ARG_V4_MAX_REG)
10443 return gen_rtx_REG (mode, cum->fregno);
10449 int n_words = rs6000_arg_size (mode, type);
10450 int gregno = cum->sysv_gregno;
10452 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
10453 (r7,r8) or (r9,r10). As does any other 2 word item such
10454 as complex int due to a historical mistake. */
10456 gregno += (1 - gregno) & 1;
10458 /* Multi-reg args are not split between registers and stack. */
10459 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
10462 if (TARGET_32BIT && TARGET_POWERPC64)
10463 return rs6000_mixed_function_arg (mode, type,
10464 gregno - GP_ARG_MIN_REG);
10465 return gen_rtx_REG (mode, gregno);
10470 int align_words = rs6000_parm_start (mode, type, cum->words);
10472 /* _Decimal128 must be passed in an even/odd float register pair.
10473 This assumes that the register number is odd when fregno is odd. */
10474 if (elt_mode == TDmode && (cum->fregno % 2) == 1)
10477 if (USE_FP_FOR_ARG_P (cum, elt_mode))
10479 rtx rvec[GP_ARG_NUM_REG + AGGR_ARG_NUM_REG + 1];
10482 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
10485 /* Do we also need to pass this argument in the parameter
10487 if (type && (cum->nargs_prototype <= 0
10488 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10489 && TARGET_XL_COMPAT
10490 && align_words >= GP_ARG_NUM_REG)))
10491 k = rs6000_psave_function_arg (mode, type, align_words, rvec);
10493 /* Describe where this argument goes in the fprs. */
10494 for (i = 0; i < n_elts
10495 && cum->fregno + i * n_fpreg <= FP_ARG_MAX_REG; i++)
10497 /* Check if the argument is split over registers and memory.
10498 This can only ever happen for long double or _Decimal128;
10499 complex types are handled via split_complex_arg. */
10500 machine_mode fmode = elt_mode;
10501 if (cum->fregno + (i + 1) * n_fpreg > FP_ARG_MAX_REG + 1)
10503 gcc_assert (fmode == TFmode || fmode == TDmode);
10504 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
10507 r = gen_rtx_REG (fmode, cum->fregno + i * n_fpreg);
10508 off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
10509 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
10512 /* If there were not enough FPRs to hold the argument, the rest
10513 usually goes into memory. However, if the current position
10514 is still within the register parameter area, a portion may
10515 actually have to go into GPRs.
10517 Note that it may happen that the portion of the argument
10518 passed in the first "half" of the first GPR was already
10519 passed in the last FPR as well.
10521 For unnamed arguments, we already set up GPRs to cover the
10522 whole argument in rs6000_psave_function_arg, so there is
10523 nothing further to do at this point. */
10524 fpr_words = (i * GET_MODE_SIZE (elt_mode)) / (TARGET_32BIT ? 4 : 8);
10525 if (i < n_elts && align_words + fpr_words < GP_ARG_NUM_REG
10526 && cum->nargs_prototype > 0)
10528 static bool warned;
10530 machine_mode rmode = TARGET_32BIT ? SImode : DImode;
10531 int n_words = rs6000_arg_size (mode, type);
10533 align_words += fpr_words;
10534 n_words -= fpr_words;
10538 r = gen_rtx_REG (rmode, GP_ARG_MIN_REG + align_words);
10539 off = GEN_INT (fpr_words++ * GET_MODE_SIZE (rmode));
10540 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
10542 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
10544 if (!warned && warn_psabi)
10547 inform (input_location,
10548 "the ABI of passing homogeneous float aggregates"
10549 " has changed in GCC 5");
10553 return rs6000_finish_function_arg (mode, rvec, k);
10555 else if (align_words < GP_ARG_NUM_REG)
10557 if (TARGET_32BIT && TARGET_POWERPC64)
10558 return rs6000_mixed_function_arg (mode, type, align_words);
10560 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
10567 /* For an arg passed partly in registers and partly in memory, this is
10568 the number of bytes passed in registers. For args passed entirely in
10569 registers or entirely in memory, zero. When an arg is described by a
10570 PARALLEL, perhaps using more than one register type, this function
10571 returns the number of bytes used by the first element of the PARALLEL. */
10574 rs6000_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
10575 tree type, bool named)
10577 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
10578 bool passed_in_gprs = true;
10581 machine_mode elt_mode;
10584 rs6000_discover_homogeneous_aggregate (mode, type, &elt_mode, &n_elts);
10586 if (DEFAULT_ABI == ABI_V4)
10589 if (USE_ALTIVEC_FOR_ARG_P (cum, elt_mode, named))
10591 /* If we are passing this arg in the fixed parameter save area
10592 (gprs or memory) as well as VRs, we do not use the partial
10593 bytes mechanism; instead, rs6000_function_arg will return a
10594 PARALLEL including a memory element as necessary. */
10595 if (TARGET_64BIT && ! cum->prototype)
10598 /* Otherwise, we pass in VRs only. Check for partial copies. */
10599 passed_in_gprs = false;
10600 if (cum->vregno + n_elts > ALTIVEC_ARG_MAX_REG + 1)
10601 ret = (ALTIVEC_ARG_MAX_REG + 1 - cum->vregno) * 16;
10604 /* In this complicated case we just disable the partial_nregs code. */
10605 if (TARGET_MACHO && rs6000_darwin64_struct_check_p (mode, type))
10608 align_words = rs6000_parm_start (mode, type, cum->words);
10610 if (USE_FP_FOR_ARG_P (cum, elt_mode))
10612 unsigned long n_fpreg = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
10614 /* If we are passing this arg in the fixed parameter save area
10615 (gprs or memory) as well as FPRs, we do not use the partial
10616 bytes mechanism; instead, rs6000_function_arg will return a
10617 PARALLEL including a memory element as necessary. */
10619 && (cum->nargs_prototype <= 0
10620 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
10621 && TARGET_XL_COMPAT
10622 && align_words >= GP_ARG_NUM_REG)))
10625 /* Otherwise, we pass in FPRs only. Check for partial copies. */
10626 passed_in_gprs = false;
10627 if (cum->fregno + n_elts * n_fpreg > FP_ARG_MAX_REG + 1)
10629 /* Compute number of bytes / words passed in FPRs. If there
10630 is still space available in the register parameter area
10631 *after* that amount, a part of the argument will be passed
10632 in GPRs. In that case, the total amount passed in any
10633 registers is equal to the amount that would have been passed
10634 in GPRs if everything were passed there, so we fall back to
10635 the GPR code below to compute the appropriate value. */
10636 int fpr = ((FP_ARG_MAX_REG + 1 - cum->fregno)
10637 * MIN (8, GET_MODE_SIZE (elt_mode)));
10638 int fpr_words = fpr / (TARGET_32BIT ? 4 : 8);
10640 if (align_words + fpr_words < GP_ARG_NUM_REG)
10641 passed_in_gprs = true;
10648 && align_words < GP_ARG_NUM_REG
10649 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
10650 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
10652 if (ret != 0 && TARGET_DEBUG_ARG)
10653 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
10658 /* A C expression that indicates when an argument must be passed by
10659 reference. If nonzero for an argument, a copy of that argument is
10660 made in memory and a pointer to the argument is passed instead of
10661 the argument itself. The pointer is passed in whatever way is
10662 appropriate for passing a pointer to that type.
10664 Under V.4, aggregates and long double are passed by reference.
10666 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
10667 reference unless the AltiVec vector extension ABI is in force.
10669 As an extension to all ABIs, variable sized types are passed by
10673 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
10674 machine_mode mode, const_tree type,
10675 bool named ATTRIBUTE_UNUSED)
10677 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
10679 if (TARGET_DEBUG_ARG)
10680 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
10687 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
10689 if (TARGET_DEBUG_ARG)
10690 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
10694 if (int_size_in_bytes (type) < 0)
10696 if (TARGET_DEBUG_ARG)
10697 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
10701 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10702 modes only exist for GCC vector types if -maltivec. */
10703 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
10705 if (TARGET_DEBUG_ARG)
10706 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
10710 /* Pass synthetic vectors in memory. */
10711 if (TREE_CODE (type) == VECTOR_TYPE
10712 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
10714 static bool warned_for_pass_big_vectors = false;
10715 if (TARGET_DEBUG_ARG)
10716 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
10717 if (!warned_for_pass_big_vectors)
10719 warning (0, "GCC vector passed by reference: "
10720 "non-standard ABI extension with no compatibility guarantee");
10721 warned_for_pass_big_vectors = true;
10729 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
10730 already processes. Return true if the parameter must be passed
10731 (fully or partially) on the stack. */
10734 rs6000_parm_needs_stack (cumulative_args_t args_so_far, tree type)
10740 /* Catch errors. */
10741 if (type == NULL || type == error_mark_node)
10744 /* Handle types with no storage requirement. */
10745 if (TYPE_MODE (type) == VOIDmode)
10748 /* Handle complex types. */
10749 if (TREE_CODE (type) == COMPLEX_TYPE)
10750 return (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type))
10751 || rs6000_parm_needs_stack (args_so_far, TREE_TYPE (type)));
10753 /* Handle transparent aggregates. */
10754 if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
10755 && TYPE_TRANSPARENT_AGGR (type))
10756 type = TREE_TYPE (first_field (type));
10758 /* See if this arg was passed by invisible reference. */
10759 if (pass_by_reference (get_cumulative_args (args_so_far),
10760 TYPE_MODE (type), type, true))
10761 type = build_pointer_type (type);
10763 /* Find mode as it is passed by the ABI. */
10764 unsignedp = TYPE_UNSIGNED (type);
10765 mode = promote_mode (type, TYPE_MODE (type), &unsignedp);
10767 /* If we must pass in stack, we need a stack. */
10768 if (rs6000_must_pass_in_stack (mode, type))
10771 /* If there is no incoming register, we need a stack. */
10772 entry_parm = rs6000_function_arg (args_so_far, mode, type, true);
10773 if (entry_parm == NULL)
10776 /* Likewise if we need to pass both in registers and on the stack. */
10777 if (GET_CODE (entry_parm) == PARALLEL
10778 && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
10781 /* Also true if we're partially in registers and partially not. */
10782 if (rs6000_arg_partial_bytes (args_so_far, mode, type, true) != 0)
10785 /* Update info on where next arg arrives in registers. */
10786 rs6000_function_arg_advance (args_so_far, mode, type, true);
10790 /* Return true if FUN has no prototype, has a variable argument
10791 list, or passes any parameter in memory. */
10794 rs6000_function_parms_need_stack (tree fun, bool incoming)
10796 tree fntype, result;
10797 CUMULATIVE_ARGS args_so_far_v;
10798 cumulative_args_t args_so_far;
10801 /* Must be a libcall, all of which only use reg parms. */
10806 fntype = TREE_TYPE (fun);
10808 /* Varargs functions need the parameter save area. */
10809 if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
10812 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v, fntype, NULL_RTX);
10813 args_so_far = pack_cumulative_args (&args_so_far_v);
10815 /* When incoming, we will have been passed the function decl.
10816 It is necessary to use the decl to handle K&R style functions,
10817 where TYPE_ARG_TYPES may not be available. */
10820 gcc_assert (DECL_P (fun));
10821 result = DECL_RESULT (fun);
10824 result = TREE_TYPE (fntype);
10826 if (result && aggregate_value_p (result, fntype))
10828 if (!TYPE_P (result))
10829 result = TREE_TYPE (result);
10830 result = build_pointer_type (result);
10831 rs6000_parm_needs_stack (args_so_far, result);
10838 for (parm = DECL_ARGUMENTS (fun);
10839 parm && parm != void_list_node;
10840 parm = TREE_CHAIN (parm))
10841 if (rs6000_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
10846 function_args_iterator args_iter;
10849 FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
10850 if (rs6000_parm_needs_stack (args_so_far, arg_type))
10857 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
10858 usually a constant depending on the ABI. However, in the ELFv2 ABI
10859 the register parameter area is optional when calling a function that
10860 has a prototype is scope, has no variable argument list, and passes
10861 all parameters in registers. */
10864 rs6000_reg_parm_stack_space (tree fun, bool incoming)
10866 int reg_parm_stack_space;
10868 switch (DEFAULT_ABI)
10871 reg_parm_stack_space = 0;
10876 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
10880 /* ??? Recomputing this every time is a bit expensive. Is there
10881 a place to cache this information? */
10882 if (rs6000_function_parms_need_stack (fun, incoming))
10883 reg_parm_stack_space = TARGET_64BIT ? 64 : 32;
10885 reg_parm_stack_space = 0;
10889 return reg_parm_stack_space;
10893 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
10896 machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
10901 for (i = 0; i < nregs; i++)
10903 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
10904 if (reload_completed)
10906 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
10909 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
10910 i * GET_MODE_SIZE (reg_mode));
10913 tem = replace_equiv_address (tem, XEXP (tem, 0));
10917 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
10921 /* Perform any needed actions needed for a function that is receiving a
10922 variable number of arguments.
10926 MODE and TYPE are the mode and type of the current parameter.
10928 PRETEND_SIZE is a variable that should be set to the amount of stack
10929 that must be pushed by the prolog to pretend that our caller pushed
10932 Normally, this macro will push all remaining incoming registers on the
10933 stack and set PRETEND_SIZE to the length of the registers pushed. */
10936 setup_incoming_varargs (cumulative_args_t cum, machine_mode mode,
10937 tree type, int *pretend_size ATTRIBUTE_UNUSED,
10940 CUMULATIVE_ARGS next_cum;
10941 int reg_size = TARGET_32BIT ? 4 : 8;
10942 rtx save_area = NULL_RTX, mem;
10943 int first_reg_offset;
10944 alias_set_type set;
10946 /* Skip the last named argument. */
10947 next_cum = *get_cumulative_args (cum);
10948 rs6000_function_arg_advance_1 (&next_cum, mode, type, true, 0);
10950 if (DEFAULT_ABI == ABI_V4)
10952 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
10956 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
10957 HOST_WIDE_INT offset = 0;
10959 /* Try to optimize the size of the varargs save area.
10960 The ABI requires that ap.reg_save_area is doubleword
10961 aligned, but we don't need to allocate space for all
10962 the bytes, only those to which we actually will save
10964 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
10965 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
10966 if (TARGET_HARD_FLOAT && TARGET_FPRS
10967 && next_cum.fregno <= FP_ARG_V4_MAX_REG
10968 && cfun->va_list_fpr_size)
10971 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
10972 * UNITS_PER_FP_WORD;
10973 if (cfun->va_list_fpr_size
10974 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
10975 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
10977 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
10978 * UNITS_PER_FP_WORD;
10982 offset = -((first_reg_offset * reg_size) & ~7);
10983 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
10985 gpr_reg_num = cfun->va_list_gpr_size;
10986 if (reg_size == 4 && (first_reg_offset & 1))
10989 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
10992 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
10993 * UNITS_PER_FP_WORD
10994 - (int) (GP_ARG_NUM_REG * reg_size);
10996 if (gpr_size + fpr_size)
10999 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
11000 gcc_assert (GET_CODE (reg_save_area) == MEM);
11001 reg_save_area = XEXP (reg_save_area, 0);
11002 if (GET_CODE (reg_save_area) == PLUS)
11004 gcc_assert (XEXP (reg_save_area, 0)
11005 == virtual_stack_vars_rtx);
11006 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
11007 offset += INTVAL (XEXP (reg_save_area, 1));
11010 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
11013 cfun->machine->varargs_save_offset = offset;
11014 save_area = plus_constant (Pmode, virtual_stack_vars_rtx, offset);
11019 first_reg_offset = next_cum.words;
11020 save_area = virtual_incoming_args_rtx;
11022 if (targetm.calls.must_pass_in_stack (mode, type))
11023 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
11026 set = get_varargs_alias_set ();
11027 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
11028 && cfun->va_list_gpr_size)
11030 int n_gpr, nregs = GP_ARG_NUM_REG - first_reg_offset;
11032 if (va_list_gpr_counter_field)
11033 /* V4 va_list_gpr_size counts number of registers needed. */
11034 n_gpr = cfun->va_list_gpr_size;
11036 /* char * va_list instead counts number of bytes needed. */
11037 n_gpr = (cfun->va_list_gpr_size + reg_size - 1) / reg_size;
11042 mem = gen_rtx_MEM (BLKmode,
11043 plus_constant (Pmode, save_area,
11044 first_reg_offset * reg_size));
11045 MEM_NOTRAP_P (mem) = 1;
11046 set_mem_alias_set (mem, set);
11047 set_mem_align (mem, BITS_PER_WORD);
11049 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
11053 /* Save FP registers if needed. */
11054 if (DEFAULT_ABI == ABI_V4
11055 && TARGET_HARD_FLOAT && TARGET_FPRS
11057 && next_cum.fregno <= FP_ARG_V4_MAX_REG
11058 && cfun->va_list_fpr_size)
11060 int fregno = next_cum.fregno, nregs;
11061 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
11062 rtx lab = gen_label_rtx ();
11063 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
11064 * UNITS_PER_FP_WORD);
11067 (gen_rtx_SET (VOIDmode,
11069 gen_rtx_IF_THEN_ELSE (VOIDmode,
11070 gen_rtx_NE (VOIDmode, cr1,
11072 gen_rtx_LABEL_REF (VOIDmode, lab),
11076 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
11077 fregno++, off += UNITS_PER_FP_WORD, nregs++)
11079 mem = gen_rtx_MEM ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
11081 plus_constant (Pmode, save_area, off));
11082 MEM_NOTRAP_P (mem) = 1;
11083 set_mem_alias_set (mem, set);
11084 set_mem_align (mem, GET_MODE_ALIGNMENT (
11085 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
11086 ? DFmode : SFmode));
11087 emit_move_insn (mem, gen_rtx_REG (
11088 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT)
11089 ? DFmode : SFmode, fregno));
11096 /* Create the va_list data type. */
11099 rs6000_build_builtin_va_list (void)
11101 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
11103 /* For AIX, prefer 'char *' because that's what the system
11104 header files like. */
11105 if (DEFAULT_ABI != ABI_V4)
11106 return build_pointer_type (char_type_node);
11108 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
11109 type_decl = build_decl (BUILTINS_LOCATION, TYPE_DECL,
11110 get_identifier ("__va_list_tag"), record);
11112 f_gpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("gpr"),
11113 unsigned_char_type_node);
11114 f_fpr = build_decl (BUILTINS_LOCATION, FIELD_DECL, get_identifier ("fpr"),
11115 unsigned_char_type_node);
11116 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
11117 every user file. */
11118 f_res = build_decl (BUILTINS_LOCATION, FIELD_DECL,
11119 get_identifier ("reserved"), short_unsigned_type_node);
11120 f_ovf = build_decl (BUILTINS_LOCATION, FIELD_DECL,
11121 get_identifier ("overflow_arg_area"),
11123 f_sav = build_decl (BUILTINS_LOCATION, FIELD_DECL,
11124 get_identifier ("reg_save_area"),
11127 va_list_gpr_counter_field = f_gpr;
11128 va_list_fpr_counter_field = f_fpr;
11130 DECL_FIELD_CONTEXT (f_gpr) = record;
11131 DECL_FIELD_CONTEXT (f_fpr) = record;
11132 DECL_FIELD_CONTEXT (f_res) = record;
11133 DECL_FIELD_CONTEXT (f_ovf) = record;
11134 DECL_FIELD_CONTEXT (f_sav) = record;
11136 TYPE_STUB_DECL (record) = type_decl;
11137 TYPE_NAME (record) = type_decl;
11138 TYPE_FIELDS (record) = f_gpr;
11139 DECL_CHAIN (f_gpr) = f_fpr;
11140 DECL_CHAIN (f_fpr) = f_res;
11141 DECL_CHAIN (f_res) = f_ovf;
11142 DECL_CHAIN (f_ovf) = f_sav;
11144 layout_type (record);
11146 /* The correct type is an array type of one element. */
11147 return build_array_type (record, build_index_type (size_zero_node));
11150 /* Implement va_start. */
11153 rs6000_va_start (tree valist, rtx nextarg)
11155 HOST_WIDE_INT words, n_gpr, n_fpr;
11156 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
11157 tree gpr, fpr, ovf, sav, t;
11159 /* Only SVR4 needs something special. */
11160 if (DEFAULT_ABI != ABI_V4)
11162 std_expand_builtin_va_start (valist, nextarg);
11166 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
11167 f_fpr = DECL_CHAIN (f_gpr);
11168 f_res = DECL_CHAIN (f_fpr);
11169 f_ovf = DECL_CHAIN (f_res);
11170 f_sav = DECL_CHAIN (f_ovf);
11172 valist = build_simple_mem_ref (valist);
11173 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
11174 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
11176 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
11178 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
11181 /* Count number of gp and fp argument registers used. */
11182 words = crtl->args.info.words;
11183 n_gpr = MIN (crtl->args.info.sysv_gregno - GP_ARG_MIN_REG,
11185 n_fpr = MIN (crtl->args.info.fregno - FP_ARG_MIN_REG,
11188 if (TARGET_DEBUG_ARG)
11189 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
11190 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
11191 words, n_gpr, n_fpr);
11193 if (cfun->va_list_gpr_size)
11195 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
11196 build_int_cst (NULL_TREE, n_gpr));
11197 TREE_SIDE_EFFECTS (t) = 1;
11198 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
11201 if (cfun->va_list_fpr_size)
11203 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
11204 build_int_cst (NULL_TREE, n_fpr));
11205 TREE_SIDE_EFFECTS (t) = 1;
11206 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
11208 #ifdef HAVE_AS_GNU_ATTRIBUTE
11209 if (call_ABI_of_interest (cfun->decl))
11210 rs6000_passes_float = true;
11214 /* Find the overflow area. */
11215 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
11217 t = fold_build_pointer_plus_hwi (t, words * UNITS_PER_WORD);
11218 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
11219 TREE_SIDE_EFFECTS (t) = 1;
11220 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
11222 /* If there were no va_arg invocations, don't set up the register
11224 if (!cfun->va_list_gpr_size
11225 && !cfun->va_list_fpr_size
11226 && n_gpr < GP_ARG_NUM_REG
11227 && n_fpr < FP_ARG_V4_MAX_REG)
11230 /* Find the register save area. */
11231 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
11232 if (cfun->machine->varargs_save_offset)
11233 t = fold_build_pointer_plus_hwi (t, cfun->machine->varargs_save_offset);
11234 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
11235 TREE_SIDE_EFFECTS (t) = 1;
11236 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
11239 /* Implement va_arg. */
11242 rs6000_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
11243 gimple_seq *post_p)
11245 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
11246 tree gpr, fpr, ovf, sav, reg, t, u;
11247 int size, rsize, n_reg, sav_ofs, sav_scale;
11248 tree lab_false, lab_over, addr;
11250 tree ptrtype = build_pointer_type_for_mode (type, ptr_mode, true);
11254 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
11256 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
11257 return build_va_arg_indirect_ref (t);
11260 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
11261 earlier version of gcc, with the property that it always applied alignment
11262 adjustments to the va-args (even for zero-sized types). The cheapest way
11263 to deal with this is to replicate the effect of the part of
11264 std_gimplify_va_arg_expr that carries out the align adjust, for the case
11266 We don't need to check for pass-by-reference because of the test above.
11267 We can return a simplifed answer, since we know there's no offset to add. */
11270 && rs6000_darwin64_abi)
11271 || DEFAULT_ABI == ABI_ELFv2
11272 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm))
11273 && integer_zerop (TYPE_SIZE (type)))
11275 unsigned HOST_WIDE_INT align, boundary;
11276 tree valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
11277 align = PARM_BOUNDARY / BITS_PER_UNIT;
11278 boundary = rs6000_function_arg_boundary (TYPE_MODE (type), type);
11279 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
11280 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
11281 boundary /= BITS_PER_UNIT;
11282 if (boundary > align)
11285 /* This updates arg ptr by the amount that would be necessary
11286 to align the zero-sized (but not zero-alignment) item. */
11287 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
11288 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
11289 gimplify_and_add (t, pre_p);
11291 t = fold_convert (sizetype, valist_tmp);
11292 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
11293 fold_convert (TREE_TYPE (valist),
11294 fold_build2 (BIT_AND_EXPR, sizetype, t,
11295 size_int (-boundary))));
11296 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
11297 gimplify_and_add (t, pre_p);
11299 /* Since it is zero-sized there's no increment for the item itself. */
11300 valist_tmp = fold_convert (build_pointer_type (type), valist_tmp);
11301 return build_va_arg_indirect_ref (valist_tmp);
11304 if (DEFAULT_ABI != ABI_V4)
11306 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
11308 tree elem_type = TREE_TYPE (type);
11309 machine_mode elem_mode = TYPE_MODE (elem_type);
11310 int elem_size = GET_MODE_SIZE (elem_mode);
11312 if (elem_size < UNITS_PER_WORD)
11314 tree real_part, imag_part;
11315 gimple_seq post = NULL;
11317 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
11319 /* Copy the value into a temporary, lest the formal temporary
11320 be reused out from under us. */
11321 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
11322 gimple_seq_add_seq (pre_p, post);
11324 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
11327 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
11331 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
11334 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
11335 f_fpr = DECL_CHAIN (f_gpr);
11336 f_res = DECL_CHAIN (f_fpr);
11337 f_ovf = DECL_CHAIN (f_res);
11338 f_sav = DECL_CHAIN (f_ovf);
11340 valist = build_va_arg_indirect_ref (valist);
11341 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
11342 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), unshare_expr (valist),
11344 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), unshare_expr (valist),
11346 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), unshare_expr (valist),
11349 size = int_size_in_bytes (type);
11350 rsize = (size + 3) / 4;
11353 if (TARGET_HARD_FLOAT && TARGET_FPRS
11354 && ((TARGET_SINGLE_FLOAT && TYPE_MODE (type) == SFmode)
11355 || (TARGET_DOUBLE_FLOAT
11356 && (TYPE_MODE (type) == DFmode
11357 || TYPE_MODE (type) == TFmode
11358 || TYPE_MODE (type) == SDmode
11359 || TYPE_MODE (type) == DDmode
11360 || TYPE_MODE (type) == TDmode))))
11362 /* FP args go in FP registers, if present. */
11364 n_reg = (size + 7) / 8;
11365 sav_ofs = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4) * 4;
11366 sav_scale = ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? 8 : 4);
11367 if (TYPE_MODE (type) != SFmode && TYPE_MODE (type) != SDmode)
11372 /* Otherwise into GP registers. */
11381 /* Pull the value out of the saved registers.... */
11384 addr = create_tmp_var (ptr_type_node, "addr");
11386 /* AltiVec vectors never go in registers when -mabi=altivec. */
11387 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
11391 lab_false = create_artificial_label (input_location);
11392 lab_over = create_artificial_label (input_location);
11394 /* Long long and SPE vectors are aligned in the registers.
11395 As are any other 2 gpr item such as complex int due to a
11396 historical mistake. */
11398 if (n_reg == 2 && reg == gpr)
11401 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), unshare_expr (reg),
11402 build_int_cst (TREE_TYPE (reg), n_reg - 1));
11403 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg),
11404 unshare_expr (reg), u);
11406 /* _Decimal128 is passed in even/odd fpr pairs; the stored
11407 reg number is 0 for f1, so we want to make it odd. */
11408 else if (reg == fpr && TYPE_MODE (type) == TDmode)
11410 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), unshare_expr (reg),
11411 build_int_cst (TREE_TYPE (reg), 1));
11412 u = build2 (MODIFY_EXPR, void_type_node, unshare_expr (reg), t);
11415 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
11416 t = build2 (GE_EXPR, boolean_type_node, u, t);
11417 u = build1 (GOTO_EXPR, void_type_node, lab_false);
11418 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
11419 gimplify_and_add (t, pre_p);
11423 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
11425 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), unshare_expr (reg),
11426 build_int_cst (TREE_TYPE (reg), n_reg));
11427 u = fold_convert (sizetype, u);
11428 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
11429 t = fold_build_pointer_plus (t, u);
11431 /* _Decimal32 varargs are located in the second word of the 64-bit
11432 FP register for 32-bit binaries. */
11433 if (!TARGET_POWERPC64
11434 && TARGET_HARD_FLOAT && TARGET_FPRS
11435 && TYPE_MODE (type) == SDmode)
11436 t = fold_build_pointer_plus_hwi (t, size);
11438 gimplify_assign (addr, t, pre_p);
11440 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
11442 stmt = gimple_build_label (lab_false);
11443 gimple_seq_add_stmt (pre_p, stmt);
11445 if ((n_reg == 2 && !regalign) || n_reg > 2)
11447 /* Ensure that we don't find any more args in regs.
11448 Alignment has taken care of for special cases. */
11449 gimplify_assign (reg, build_int_cst (TREE_TYPE (reg), 8), pre_p);
11453 /* ... otherwise out of the overflow area. */
11455 /* Care for on-stack alignment if needed. */
11459 t = fold_build_pointer_plus_hwi (t, align - 1);
11460 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
11461 build_int_cst (TREE_TYPE (t), -align));
11463 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
11465 gimplify_assign (unshare_expr (addr), t, pre_p);
11467 t = fold_build_pointer_plus_hwi (t, size);
11468 gimplify_assign (unshare_expr (ovf), t, pre_p);
11472 stmt = gimple_build_label (lab_over);
11473 gimple_seq_add_stmt (pre_p, stmt);
11476 if (STRICT_ALIGNMENT
11477 && (TYPE_ALIGN (type)
11478 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
11480 /* The value (of type complex double, for example) may not be
11481 aligned in memory in the saved registers, so copy via a
11482 temporary. (This is the same code as used for SPARC.) */
11483 tree tmp = create_tmp_var (type, "va_arg_tmp");
11484 tree dest_addr = build_fold_addr_expr (tmp);
11486 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY),
11487 3, dest_addr, addr, size_int (rsize * 4));
11489 gimplify_and_add (copy, pre_p);
11493 addr = fold_convert (ptrtype, addr);
11494 return build_va_arg_indirect_ref (addr);
11500 def_builtin (const char *name, tree type, enum rs6000_builtins code)
11503 unsigned classify = rs6000_builtin_info[(int)code].attr;
11504 const char *attr_string = "";
11506 gcc_assert (name != NULL);
11507 gcc_assert (IN_RANGE ((int)code, 0, (int)RS6000_BUILTIN_COUNT));
11509 if (rs6000_builtin_decls[(int)code])
11510 fatal_error ("internal error: builtin function %s already processed", name);
11512 rs6000_builtin_decls[(int)code] = t =
11513 add_builtin_function (name, type, (int)code, BUILT_IN_MD, NULL, NULL_TREE);
11515 /* Set any special attributes. */
11516 if ((classify & RS6000_BTC_CONST) != 0)
11518 /* const function, function only depends on the inputs. */
11519 TREE_READONLY (t) = 1;
11520 TREE_NOTHROW (t) = 1;
11521 attr_string = ", pure";
11523 else if ((classify & RS6000_BTC_PURE) != 0)
11525 /* pure function, function can read global memory, but does not set any
11527 DECL_PURE_P (t) = 1;
11528 TREE_NOTHROW (t) = 1;
11529 attr_string = ", const";
11531 else if ((classify & RS6000_BTC_FP) != 0)
11533 /* Function is a math function. If rounding mode is on, then treat the
11534 function as not reading global memory, but it can have arbitrary side
11535 effects. If it is off, then assume the function is a const function.
11536 This mimics the ATTR_MATHFN_FPROUNDING attribute in
11537 builtin-attribute.def that is used for the math functions. */
11538 TREE_NOTHROW (t) = 1;
11539 if (flag_rounding_math)
11541 DECL_PURE_P (t) = 1;
11542 DECL_IS_NOVOPS (t) = 1;
11543 attr_string = ", fp, pure";
11547 TREE_READONLY (t) = 1;
11548 attr_string = ", fp, const";
11551 else if ((classify & RS6000_BTC_ATTR_MASK) != 0)
11552 gcc_unreachable ();
11554 if (TARGET_DEBUG_BUILTIN)
11555 fprintf (stderr, "rs6000_builtin, code = %4d, %s%s\n",
11556 (int)code, name, attr_string);
11559 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
11561 #undef RS6000_BUILTIN_1
11562 #undef RS6000_BUILTIN_2
11563 #undef RS6000_BUILTIN_3
11564 #undef RS6000_BUILTIN_A
11565 #undef RS6000_BUILTIN_D
11566 #undef RS6000_BUILTIN_E
11567 #undef RS6000_BUILTIN_H
11568 #undef RS6000_BUILTIN_P
11569 #undef RS6000_BUILTIN_Q
11570 #undef RS6000_BUILTIN_S
11571 #undef RS6000_BUILTIN_X
11573 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11574 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11575 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
11576 { MASK, ICODE, NAME, ENUM },
11578 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11579 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11580 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11581 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11582 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11583 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11584 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11585 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11587 static const struct builtin_description bdesc_3arg[] =
11589 #include "rs6000-builtin.def"
11592 /* DST operations: void foo (void *, const int, const char). */
11594 #undef RS6000_BUILTIN_1
11595 #undef RS6000_BUILTIN_2
11596 #undef RS6000_BUILTIN_3
11597 #undef RS6000_BUILTIN_A
11598 #undef RS6000_BUILTIN_D
11599 #undef RS6000_BUILTIN_E
11600 #undef RS6000_BUILTIN_H
11601 #undef RS6000_BUILTIN_P
11602 #undef RS6000_BUILTIN_Q
11603 #undef RS6000_BUILTIN_S
11604 #undef RS6000_BUILTIN_X
11606 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11607 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11608 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11609 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11610 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
11611 { MASK, ICODE, NAME, ENUM },
11613 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11614 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11615 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11616 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11617 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11618 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11620 static const struct builtin_description bdesc_dst[] =
11622 #include "rs6000-builtin.def"
11625 /* Simple binary operations: VECc = foo (VECa, VECb). */
11627 #undef RS6000_BUILTIN_1
11628 #undef RS6000_BUILTIN_2
11629 #undef RS6000_BUILTIN_3
11630 #undef RS6000_BUILTIN_A
11631 #undef RS6000_BUILTIN_D
11632 #undef RS6000_BUILTIN_E
11633 #undef RS6000_BUILTIN_H
11634 #undef RS6000_BUILTIN_P
11635 #undef RS6000_BUILTIN_Q
11636 #undef RS6000_BUILTIN_S
11637 #undef RS6000_BUILTIN_X
11639 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11640 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
11641 { MASK, ICODE, NAME, ENUM },
11643 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11644 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11645 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11646 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11647 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11648 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11649 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11650 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11651 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11653 static const struct builtin_description bdesc_2arg[] =
11655 #include "rs6000-builtin.def"
11658 #undef RS6000_BUILTIN_1
11659 #undef RS6000_BUILTIN_2
11660 #undef RS6000_BUILTIN_3
11661 #undef RS6000_BUILTIN_A
11662 #undef RS6000_BUILTIN_D
11663 #undef RS6000_BUILTIN_E
11664 #undef RS6000_BUILTIN_H
11665 #undef RS6000_BUILTIN_P
11666 #undef RS6000_BUILTIN_Q
11667 #undef RS6000_BUILTIN_S
11668 #undef RS6000_BUILTIN_X
11670 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11671 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11672 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11673 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11674 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11675 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11676 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11677 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
11678 { MASK, ICODE, NAME, ENUM },
11680 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11681 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11682 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11684 /* AltiVec predicates. */
11686 static const struct builtin_description bdesc_altivec_preds[] =
11688 #include "rs6000-builtin.def"
11691 /* SPE predicates. */
11692 #undef RS6000_BUILTIN_1
11693 #undef RS6000_BUILTIN_2
11694 #undef RS6000_BUILTIN_3
11695 #undef RS6000_BUILTIN_A
11696 #undef RS6000_BUILTIN_D
11697 #undef RS6000_BUILTIN_E
11698 #undef RS6000_BUILTIN_H
11699 #undef RS6000_BUILTIN_P
11700 #undef RS6000_BUILTIN_Q
11701 #undef RS6000_BUILTIN_S
11702 #undef RS6000_BUILTIN_X
11704 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11705 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11706 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11707 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11708 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11709 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11710 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11711 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11712 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11713 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
11714 { MASK, ICODE, NAME, ENUM },
11716 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11718 static const struct builtin_description bdesc_spe_predicates[] =
11720 #include "rs6000-builtin.def"
11723 /* SPE evsel predicates. */
11724 #undef RS6000_BUILTIN_1
11725 #undef RS6000_BUILTIN_2
11726 #undef RS6000_BUILTIN_3
11727 #undef RS6000_BUILTIN_A
11728 #undef RS6000_BUILTIN_D
11729 #undef RS6000_BUILTIN_E
11730 #undef RS6000_BUILTIN_H
11731 #undef RS6000_BUILTIN_P
11732 #undef RS6000_BUILTIN_Q
11733 #undef RS6000_BUILTIN_S
11734 #undef RS6000_BUILTIN_X
11736 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11737 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11738 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11739 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11740 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11741 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
11742 { MASK, ICODE, NAME, ENUM },
11744 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11745 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11746 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11747 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11748 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11750 static const struct builtin_description bdesc_spe_evsel[] =
11752 #include "rs6000-builtin.def"
11755 /* PAIRED predicates. */
11756 #undef RS6000_BUILTIN_1
11757 #undef RS6000_BUILTIN_2
11758 #undef RS6000_BUILTIN_3
11759 #undef RS6000_BUILTIN_A
11760 #undef RS6000_BUILTIN_D
11761 #undef RS6000_BUILTIN_E
11762 #undef RS6000_BUILTIN_H
11763 #undef RS6000_BUILTIN_P
11764 #undef RS6000_BUILTIN_Q
11765 #undef RS6000_BUILTIN_S
11766 #undef RS6000_BUILTIN_X
11768 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11769 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11770 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11771 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11772 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11773 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11774 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11775 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11776 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
11777 { MASK, ICODE, NAME, ENUM },
11779 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11780 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11782 static const struct builtin_description bdesc_paired_preds[] =
11784 #include "rs6000-builtin.def"
11787 /* ABS* operations. */
11789 #undef RS6000_BUILTIN_1
11790 #undef RS6000_BUILTIN_2
11791 #undef RS6000_BUILTIN_3
11792 #undef RS6000_BUILTIN_A
11793 #undef RS6000_BUILTIN_D
11794 #undef RS6000_BUILTIN_E
11795 #undef RS6000_BUILTIN_H
11796 #undef RS6000_BUILTIN_P
11797 #undef RS6000_BUILTIN_Q
11798 #undef RS6000_BUILTIN_S
11799 #undef RS6000_BUILTIN_X
11801 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11802 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11803 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11804 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
11805 { MASK, ICODE, NAME, ENUM },
11807 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11808 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11809 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11810 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11811 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11812 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11813 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11815 static const struct builtin_description bdesc_abs[] =
11817 #include "rs6000-builtin.def"
11820 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
11823 #undef RS6000_BUILTIN_1
11824 #undef RS6000_BUILTIN_2
11825 #undef RS6000_BUILTIN_3
11826 #undef RS6000_BUILTIN_A
11827 #undef RS6000_BUILTIN_D
11828 #undef RS6000_BUILTIN_E
11829 #undef RS6000_BUILTIN_H
11830 #undef RS6000_BUILTIN_P
11831 #undef RS6000_BUILTIN_Q
11832 #undef RS6000_BUILTIN_S
11833 #undef RS6000_BUILTIN_X
11835 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
11836 { MASK, ICODE, NAME, ENUM },
11838 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11839 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11840 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11841 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11842 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11843 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11844 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11845 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11846 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11847 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11849 static const struct builtin_description bdesc_1arg[] =
11851 #include "rs6000-builtin.def"
11854 /* HTM builtins. */
11855 #undef RS6000_BUILTIN_1
11856 #undef RS6000_BUILTIN_2
11857 #undef RS6000_BUILTIN_3
11858 #undef RS6000_BUILTIN_A
11859 #undef RS6000_BUILTIN_D
11860 #undef RS6000_BUILTIN_E
11861 #undef RS6000_BUILTIN_H
11862 #undef RS6000_BUILTIN_P
11863 #undef RS6000_BUILTIN_Q
11864 #undef RS6000_BUILTIN_S
11865 #undef RS6000_BUILTIN_X
11867 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11868 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11869 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11870 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11871 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11872 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11873 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
11874 { MASK, ICODE, NAME, ENUM },
11876 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11877 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11878 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11879 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11881 static const struct builtin_description bdesc_htm[] =
11883 #include "rs6000-builtin.def"
11886 #undef RS6000_BUILTIN_1
11887 #undef RS6000_BUILTIN_2
11888 #undef RS6000_BUILTIN_3
11889 #undef RS6000_BUILTIN_A
11890 #undef RS6000_BUILTIN_D
11891 #undef RS6000_BUILTIN_E
11892 #undef RS6000_BUILTIN_H
11893 #undef RS6000_BUILTIN_P
11894 #undef RS6000_BUILTIN_Q
11895 #undef RS6000_BUILTIN_S
11897 /* Return true if a builtin function is overloaded. */
11899 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode)
11901 return (rs6000_builtin_info[(int)fncode].attr & RS6000_BTC_OVERLOADED) != 0;
11904 /* Expand an expression EXP that calls a builtin without arguments. */
11906 rs6000_expand_zeroop_builtin (enum insn_code icode, rtx target)
11909 machine_mode tmode = insn_data[icode].operand[0].mode;
11911 if (icode == CODE_FOR_nothing)
11912 /* Builtin not supported on this processor. */
11916 || GET_MODE (target) != tmode
11917 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
11918 target = gen_reg_rtx (tmode);
11920 pat = GEN_FCN (icode) (target);
11930 rs6000_expand_mtfsf_builtin (enum insn_code icode, tree exp)
11933 tree arg0 = CALL_EXPR_ARG (exp, 0);
11934 tree arg1 = CALL_EXPR_ARG (exp, 1);
11935 rtx op0 = expand_normal (arg0);
11936 rtx op1 = expand_normal (arg1);
11937 machine_mode mode0 = insn_data[icode].operand[0].mode;
11938 machine_mode mode1 = insn_data[icode].operand[1].mode;
11940 if (icode == CODE_FOR_nothing)
11941 /* Builtin not supported on this processor. */
11944 /* If we got invalid arguments bail out before generating bad rtl. */
11945 if (arg0 == error_mark_node || arg1 == error_mark_node)
11948 if (GET_CODE (op0) != CONST_INT
11949 || INTVAL (op0) > 255
11950 || INTVAL (op0) < 0)
11952 error ("argument 1 must be an 8-bit field value");
11956 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
11957 op0 = copy_to_mode_reg (mode0, op0);
11959 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
11960 op1 = copy_to_mode_reg (mode1, op1);
11962 pat = GEN_FCN (icode) (op0, op1);
11972 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
11975 tree arg0 = CALL_EXPR_ARG (exp, 0);
11976 rtx op0 = expand_normal (arg0);
11977 machine_mode tmode = insn_data[icode].operand[0].mode;
11978 machine_mode mode0 = insn_data[icode].operand[1].mode;
11980 if (icode == CODE_FOR_nothing)
11981 /* Builtin not supported on this processor. */
11984 /* If we got invalid arguments bail out before generating bad rtl. */
11985 if (arg0 == error_mark_node)
11988 if (icode == CODE_FOR_altivec_vspltisb
11989 || icode == CODE_FOR_altivec_vspltish
11990 || icode == CODE_FOR_altivec_vspltisw
11991 || icode == CODE_FOR_spe_evsplatfi
11992 || icode == CODE_FOR_spe_evsplati)
11994 /* Only allow 5-bit *signed* literals. */
11995 if (GET_CODE (op0) != CONST_INT
11996 || INTVAL (op0) > 15
11997 || INTVAL (op0) < -16)
11999 error ("argument 1 must be a 5-bit signed literal");
12005 || GET_MODE (target) != tmode
12006 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12007 target = gen_reg_rtx (tmode);
12009 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12010 op0 = copy_to_mode_reg (mode0, op0);
12012 pat = GEN_FCN (icode) (target, op0);
12021 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
12023 rtx pat, scratch1, scratch2;
12024 tree arg0 = CALL_EXPR_ARG (exp, 0);
12025 rtx op0 = expand_normal (arg0);
12026 machine_mode tmode = insn_data[icode].operand[0].mode;
12027 machine_mode mode0 = insn_data[icode].operand[1].mode;
12029 /* If we have invalid arguments, bail out before generating bad rtl. */
12030 if (arg0 == error_mark_node)
12034 || GET_MODE (target) != tmode
12035 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12036 target = gen_reg_rtx (tmode);
12038 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12039 op0 = copy_to_mode_reg (mode0, op0);
12041 scratch1 = gen_reg_rtx (mode0);
12042 scratch2 = gen_reg_rtx (mode0);
12044 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
12053 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
12056 tree arg0 = CALL_EXPR_ARG (exp, 0);
12057 tree arg1 = CALL_EXPR_ARG (exp, 1);
12058 rtx op0 = expand_normal (arg0);
12059 rtx op1 = expand_normal (arg1);
12060 machine_mode tmode = insn_data[icode].operand[0].mode;
12061 machine_mode mode0 = insn_data[icode].operand[1].mode;
12062 machine_mode mode1 = insn_data[icode].operand[2].mode;
12064 if (icode == CODE_FOR_nothing)
12065 /* Builtin not supported on this processor. */
12068 /* If we got invalid arguments bail out before generating bad rtl. */
12069 if (arg0 == error_mark_node || arg1 == error_mark_node)
12072 if (icode == CODE_FOR_altivec_vcfux
12073 || icode == CODE_FOR_altivec_vcfsx
12074 || icode == CODE_FOR_altivec_vctsxs
12075 || icode == CODE_FOR_altivec_vctuxs
12076 || icode == CODE_FOR_altivec_vspltb
12077 || icode == CODE_FOR_altivec_vsplth
12078 || icode == CODE_FOR_altivec_vspltw
12079 || icode == CODE_FOR_spe_evaddiw
12080 || icode == CODE_FOR_spe_evldd
12081 || icode == CODE_FOR_spe_evldh
12082 || icode == CODE_FOR_spe_evldw
12083 || icode == CODE_FOR_spe_evlhhesplat
12084 || icode == CODE_FOR_spe_evlhhossplat
12085 || icode == CODE_FOR_spe_evlhhousplat
12086 || icode == CODE_FOR_spe_evlwhe
12087 || icode == CODE_FOR_spe_evlwhos
12088 || icode == CODE_FOR_spe_evlwhou
12089 || icode == CODE_FOR_spe_evlwhsplat
12090 || icode == CODE_FOR_spe_evlwwsplat
12091 || icode == CODE_FOR_spe_evrlwi
12092 || icode == CODE_FOR_spe_evslwi
12093 || icode == CODE_FOR_spe_evsrwis
12094 || icode == CODE_FOR_spe_evsubifw
12095 || icode == CODE_FOR_spe_evsrwiu)
12097 /* Only allow 5-bit unsigned literals. */
12099 if (TREE_CODE (arg1) != INTEGER_CST
12100 || TREE_INT_CST_LOW (arg1) & ~0x1f)
12102 error ("argument 2 must be a 5-bit unsigned literal");
12108 || GET_MODE (target) != tmode
12109 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12110 target = gen_reg_rtx (tmode);
12112 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12113 op0 = copy_to_mode_reg (mode0, op0);
12114 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12115 op1 = copy_to_mode_reg (mode1, op1);
12117 pat = GEN_FCN (icode) (target, op0, op1);
12126 altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
12129 tree cr6_form = CALL_EXPR_ARG (exp, 0);
12130 tree arg0 = CALL_EXPR_ARG (exp, 1);
12131 tree arg1 = CALL_EXPR_ARG (exp, 2);
12132 rtx op0 = expand_normal (arg0);
12133 rtx op1 = expand_normal (arg1);
12134 machine_mode tmode = SImode;
12135 machine_mode mode0 = insn_data[icode].operand[1].mode;
12136 machine_mode mode1 = insn_data[icode].operand[2].mode;
12139 if (TREE_CODE (cr6_form) != INTEGER_CST)
12141 error ("argument 1 of __builtin_altivec_predicate must be a constant");
12145 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
12147 gcc_assert (mode0 == mode1);
12149 /* If we have invalid arguments, bail out before generating bad rtl. */
12150 if (arg0 == error_mark_node || arg1 == error_mark_node)
12154 || GET_MODE (target) != tmode
12155 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12156 target = gen_reg_rtx (tmode);
12158 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12159 op0 = copy_to_mode_reg (mode0, op0);
12160 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12161 op1 = copy_to_mode_reg (mode1, op1);
12163 scratch = gen_reg_rtx (mode0);
12165 pat = GEN_FCN (icode) (scratch, op0, op1);
12170 /* The vec_any* and vec_all* predicates use the same opcodes for two
12171 different operations, but the bits in CR6 will be different
12172 depending on what information we want. So we have to play tricks
12173 with CR6 to get the right bits out.
12175 If you think this is disgusting, look at the specs for the
12176 AltiVec predicates. */
12178 switch (cr6_form_int)
12181 emit_insn (gen_cr6_test_for_zero (target));
12184 emit_insn (gen_cr6_test_for_zero_reverse (target));
12187 emit_insn (gen_cr6_test_for_lt (target));
12190 emit_insn (gen_cr6_test_for_lt_reverse (target));
12193 error ("argument 1 of __builtin_altivec_predicate is out of range");
12201 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
12204 tree arg0 = CALL_EXPR_ARG (exp, 0);
12205 tree arg1 = CALL_EXPR_ARG (exp, 1);
12206 machine_mode tmode = insn_data[icode].operand[0].mode;
12207 machine_mode mode0 = Pmode;
12208 machine_mode mode1 = Pmode;
12209 rtx op0 = expand_normal (arg0);
12210 rtx op1 = expand_normal (arg1);
12212 if (icode == CODE_FOR_nothing)
12213 /* Builtin not supported on this processor. */
12216 /* If we got invalid arguments bail out before generating bad rtl. */
12217 if (arg0 == error_mark_node || arg1 == error_mark_node)
12221 || GET_MODE (target) != tmode
12222 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12223 target = gen_reg_rtx (tmode);
12225 op1 = copy_to_mode_reg (mode1, op1);
12227 if (op0 == const0_rtx)
12229 addr = gen_rtx_MEM (tmode, op1);
12233 op0 = copy_to_mode_reg (mode0, op0);
12234 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
12237 pat = GEN_FCN (icode) (target, addr);
12246 /* Return a constant vector for use as a little-endian permute control vector
12247 to reverse the order of elements of the given vector mode. */
12249 swap_selector_for_mode (machine_mode mode)
12251 /* These are little endian vectors, so their elements are reversed
12252 from what you would normally expect for a permute control vector. */
12253 unsigned int swap2[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
12254 unsigned int swap4[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
12255 unsigned int swap8[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
12256 unsigned int swap16[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
12257 unsigned int *swaparray, i;
12274 swaparray = swap16;
12277 gcc_unreachable ();
12280 for (i = 0; i < 16; ++i)
12281 perm[i] = GEN_INT (swaparray[i]);
12283 return force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)));
12286 /* Generate code for an "lvx", "lvxl", or "lve*x" built-in for a little endian target
12287 with -maltivec=be specified. Issue the load followed by an element-reversing
12290 altivec_expand_lvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
12292 rtx tmp = gen_reg_rtx (mode);
12293 rtx load = gen_rtx_SET (VOIDmode, tmp, op1);
12294 rtx lvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
12295 rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, load, lvx));
12296 rtx sel = swap_selector_for_mode (mode);
12297 rtx vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, tmp, tmp, sel), UNSPEC_VPERM);
12299 gcc_assert (REG_P (op0));
12301 emit_insn (gen_rtx_SET (VOIDmode, op0, vperm));
12304 /* Generate code for a "stvx" or "stvxl" built-in for a little endian target
12305 with -maltivec=be specified. Issue the store preceded by an element-reversing
12308 altivec_expand_stvx_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
12310 rtx tmp = gen_reg_rtx (mode);
12311 rtx store = gen_rtx_SET (VOIDmode, op0, tmp);
12312 rtx stvx = gen_rtx_UNSPEC (mode, gen_rtvec (1, const0_rtx), unspec);
12313 rtx par = gen_rtx_PARALLEL (mode, gen_rtvec (2, store, stvx));
12314 rtx sel = swap_selector_for_mode (mode);
12317 gcc_assert (REG_P (op1));
12318 vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
12319 emit_insn (gen_rtx_SET (VOIDmode, tmp, vperm));
12323 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
12324 specified. Issue the store preceded by an element-reversing permute. */
12326 altivec_expand_stvex_be (rtx op0, rtx op1, machine_mode mode, unsigned unspec)
12328 machine_mode inner_mode = GET_MODE_INNER (mode);
12329 rtx tmp = gen_reg_rtx (mode);
12330 rtx stvx = gen_rtx_UNSPEC (inner_mode, gen_rtvec (1, tmp), unspec);
12331 rtx sel = swap_selector_for_mode (mode);
12334 gcc_assert (REG_P (op1));
12335 vperm = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op1, sel), UNSPEC_VPERM);
12336 emit_insn (gen_rtx_SET (VOIDmode, tmp, vperm));
12337 emit_insn (gen_rtx_SET (VOIDmode, op0, stvx));
12341 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target, bool blk)
12344 tree arg0 = CALL_EXPR_ARG (exp, 0);
12345 tree arg1 = CALL_EXPR_ARG (exp, 1);
12346 machine_mode tmode = insn_data[icode].operand[0].mode;
12347 machine_mode mode0 = Pmode;
12348 machine_mode mode1 = Pmode;
12349 rtx op0 = expand_normal (arg0);
12350 rtx op1 = expand_normal (arg1);
12352 if (icode == CODE_FOR_nothing)
12353 /* Builtin not supported on this processor. */
12356 /* If we got invalid arguments bail out before generating bad rtl. */
12357 if (arg0 == error_mark_node || arg1 == error_mark_node)
12361 || GET_MODE (target) != tmode
12362 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12363 target = gen_reg_rtx (tmode);
12365 op1 = copy_to_mode_reg (mode1, op1);
12367 if (op0 == const0_rtx)
12369 addr = gen_rtx_MEM (blk ? BLKmode : tmode, op1);
12373 op0 = copy_to_mode_reg (mode0, op0);
12374 addr = gen_rtx_MEM (blk ? BLKmode : tmode, gen_rtx_PLUS (Pmode, op0, op1));
12377 pat = GEN_FCN (icode) (target, addr);
12387 spe_expand_stv_builtin (enum insn_code icode, tree exp)
12389 tree arg0 = CALL_EXPR_ARG (exp, 0);
12390 tree arg1 = CALL_EXPR_ARG (exp, 1);
12391 tree arg2 = CALL_EXPR_ARG (exp, 2);
12392 rtx op0 = expand_normal (arg0);
12393 rtx op1 = expand_normal (arg1);
12394 rtx op2 = expand_normal (arg2);
12396 machine_mode mode0 = insn_data[icode].operand[0].mode;
12397 machine_mode mode1 = insn_data[icode].operand[1].mode;
12398 machine_mode mode2 = insn_data[icode].operand[2].mode;
12400 /* Invalid arguments. Bail before doing anything stoopid! */
12401 if (arg0 == error_mark_node
12402 || arg1 == error_mark_node
12403 || arg2 == error_mark_node)
12406 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
12407 op0 = copy_to_mode_reg (mode2, op0);
12408 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
12409 op1 = copy_to_mode_reg (mode0, op1);
12410 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
12411 op2 = copy_to_mode_reg (mode1, op2);
12413 pat = GEN_FCN (icode) (op1, op2, op0);
12420 paired_expand_stv_builtin (enum insn_code icode, tree exp)
12422 tree arg0 = CALL_EXPR_ARG (exp, 0);
12423 tree arg1 = CALL_EXPR_ARG (exp, 1);
12424 tree arg2 = CALL_EXPR_ARG (exp, 2);
12425 rtx op0 = expand_normal (arg0);
12426 rtx op1 = expand_normal (arg1);
12427 rtx op2 = expand_normal (arg2);
12429 machine_mode tmode = insn_data[icode].operand[0].mode;
12430 machine_mode mode1 = Pmode;
12431 machine_mode mode2 = Pmode;
12433 /* Invalid arguments. Bail before doing anything stoopid! */
12434 if (arg0 == error_mark_node
12435 || arg1 == error_mark_node
12436 || arg2 == error_mark_node)
12439 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
12440 op0 = copy_to_mode_reg (tmode, op0);
12442 op2 = copy_to_mode_reg (mode2, op2);
12444 if (op1 == const0_rtx)
12446 addr = gen_rtx_MEM (tmode, op2);
12450 op1 = copy_to_mode_reg (mode1, op1);
12451 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
12454 pat = GEN_FCN (icode) (addr, op0);
12461 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
12463 tree arg0 = CALL_EXPR_ARG (exp, 0);
12464 tree arg1 = CALL_EXPR_ARG (exp, 1);
12465 tree arg2 = CALL_EXPR_ARG (exp, 2);
12466 rtx op0 = expand_normal (arg0);
12467 rtx op1 = expand_normal (arg1);
12468 rtx op2 = expand_normal (arg2);
12470 machine_mode tmode = insn_data[icode].operand[0].mode;
12471 machine_mode smode = insn_data[icode].operand[1].mode;
12472 machine_mode mode1 = Pmode;
12473 machine_mode mode2 = Pmode;
12475 /* Invalid arguments. Bail before doing anything stoopid! */
12476 if (arg0 == error_mark_node
12477 || arg1 == error_mark_node
12478 || arg2 == error_mark_node)
12481 if (! (*insn_data[icode].operand[1].predicate) (op0, smode))
12482 op0 = copy_to_mode_reg (smode, op0);
12484 op2 = copy_to_mode_reg (mode2, op2);
12486 if (op1 == const0_rtx)
12488 addr = gen_rtx_MEM (tmode, op2);
12492 op1 = copy_to_mode_reg (mode1, op1);
12493 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
12496 pat = GEN_FCN (icode) (addr, op0);
12502 /* Return the appropriate SPR number associated with the given builtin. */
12503 static inline HOST_WIDE_INT
12504 htm_spr_num (enum rs6000_builtins code)
12506 if (code == HTM_BUILTIN_GET_TFHAR
12507 || code == HTM_BUILTIN_SET_TFHAR)
12509 else if (code == HTM_BUILTIN_GET_TFIAR
12510 || code == HTM_BUILTIN_SET_TFIAR)
12512 else if (code == HTM_BUILTIN_GET_TEXASR
12513 || code == HTM_BUILTIN_SET_TEXASR)
12515 gcc_assert (code == HTM_BUILTIN_GET_TEXASRU
12516 || code == HTM_BUILTIN_SET_TEXASRU);
12517 return TEXASRU_SPR;
12520 /* Return the appropriate SPR regno associated with the given builtin. */
12521 static inline HOST_WIDE_INT
12522 htm_spr_regno (enum rs6000_builtins code)
12524 if (code == HTM_BUILTIN_GET_TFHAR
12525 || code == HTM_BUILTIN_SET_TFHAR)
12526 return TFHAR_REGNO;
12527 else if (code == HTM_BUILTIN_GET_TFIAR
12528 || code == HTM_BUILTIN_SET_TFIAR)
12529 return TFIAR_REGNO;
12530 gcc_assert (code == HTM_BUILTIN_GET_TEXASR
12531 || code == HTM_BUILTIN_SET_TEXASR
12532 || code == HTM_BUILTIN_GET_TEXASRU
12533 || code == HTM_BUILTIN_SET_TEXASRU);
12534 return TEXASR_REGNO;
12537 /* Return the correct ICODE value depending on whether we are
12538 setting or reading the HTM SPRs. */
12539 static inline enum insn_code
12540 rs6000_htm_spr_icode (bool nonvoid)
12543 return (TARGET_64BIT) ? CODE_FOR_htm_mfspr_di : CODE_FOR_htm_mfspr_si;
12545 return (TARGET_64BIT) ? CODE_FOR_htm_mtspr_di : CODE_FOR_htm_mtspr_si;
12548 /* Expand the HTM builtin in EXP and store the result in TARGET.
12549 Store true in *EXPANDEDP if we found a builtin to expand. */
12551 htm_expand_builtin (tree exp, rtx target, bool * expandedp)
12553 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
12554 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
12555 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
12556 const struct builtin_description *d;
12559 *expandedp = false;
12561 /* Expand the HTM builtins. */
12563 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
12564 if (d->code == fcode)
12566 rtx op[MAX_HTM_OPERANDS], pat;
12569 call_expr_arg_iterator iter;
12570 unsigned attr = rs6000_builtin_info[fcode].attr;
12571 enum insn_code icode = d->icode;
12573 if (attr & RS6000_BTC_SPR)
12574 icode = rs6000_htm_spr_icode (nonvoid);
12578 machine_mode tmode = insn_data[icode].operand[0].mode;
12580 || GET_MODE (target) != tmode
12581 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
12582 target = gen_reg_rtx (tmode);
12583 op[nopnds++] = target;
12586 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
12588 const struct insn_operand_data *insn_op;
12590 if (arg == error_mark_node || nopnds >= MAX_HTM_OPERANDS)
12593 insn_op = &insn_data[icode].operand[nopnds];
12595 op[nopnds] = expand_normal (arg);
12597 if (!(*insn_op->predicate) (op[nopnds], insn_op->mode))
12599 if (!strcmp (insn_op->constraint, "n"))
12601 int arg_num = (nonvoid) ? nopnds : nopnds + 1;
12602 if (!CONST_INT_P (op[nopnds]))
12603 error ("argument %d must be an unsigned literal", arg_num);
12605 error ("argument %d is an unsigned literal that is "
12606 "out of range", arg_num);
12609 op[nopnds] = copy_to_mode_reg (insn_op->mode, op[nopnds]);
12615 /* Handle the builtins for extended mnemonics. These accept
12616 no arguments, but map to builtins that take arguments. */
12619 case HTM_BUILTIN_TENDALL: /* Alias for: tend. 1 */
12620 case HTM_BUILTIN_TRESUME: /* Alias for: tsr. 1 */
12621 op[nopnds++] = GEN_INT (1);
12622 #ifdef ENABLE_CHECKING
12623 attr |= RS6000_BTC_UNARY;
12626 case HTM_BUILTIN_TSUSPEND: /* Alias for: tsr. 0 */
12627 op[nopnds++] = GEN_INT (0);
12628 #ifdef ENABLE_CHECKING
12629 attr |= RS6000_BTC_UNARY;
12636 /* If this builtin accesses SPRs, then pass in the appropriate
12637 SPR number and SPR regno as the last two operands. */
12638 if (attr & RS6000_BTC_SPR)
12640 op[nopnds++] = gen_rtx_CONST_INT (Pmode, htm_spr_num (fcode));
12641 op[nopnds++] = gen_rtx_REG (Pmode, htm_spr_regno (fcode));
12644 #ifdef ENABLE_CHECKING
12645 int expected_nopnds = 0;
12646 if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_UNARY)
12647 expected_nopnds = 1;
12648 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_BINARY)
12649 expected_nopnds = 2;
12650 else if ((attr & RS6000_BTC_TYPE_MASK) == RS6000_BTC_TERNARY)
12651 expected_nopnds = 3;
12652 if (!(attr & RS6000_BTC_VOID))
12653 expected_nopnds += 1;
12654 if (attr & RS6000_BTC_SPR)
12655 expected_nopnds += 2;
12657 gcc_assert (nopnds == expected_nopnds && nopnds <= MAX_HTM_OPERANDS);
12663 pat = GEN_FCN (icode) (op[0]);
12666 pat = GEN_FCN (icode) (op[0], op[1]);
12669 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
12672 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
12675 gcc_unreachable ();
12691 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
12694 tree arg0 = CALL_EXPR_ARG (exp, 0);
12695 tree arg1 = CALL_EXPR_ARG (exp, 1);
12696 tree arg2 = CALL_EXPR_ARG (exp, 2);
12697 rtx op0 = expand_normal (arg0);
12698 rtx op1 = expand_normal (arg1);
12699 rtx op2 = expand_normal (arg2);
12700 machine_mode tmode = insn_data[icode].operand[0].mode;
12701 machine_mode mode0 = insn_data[icode].operand[1].mode;
12702 machine_mode mode1 = insn_data[icode].operand[2].mode;
12703 machine_mode mode2 = insn_data[icode].operand[3].mode;
12705 if (icode == CODE_FOR_nothing)
12706 /* Builtin not supported on this processor. */
12709 /* If we got invalid arguments bail out before generating bad rtl. */
12710 if (arg0 == error_mark_node
12711 || arg1 == error_mark_node
12712 || arg2 == error_mark_node)
12715 /* Check and prepare argument depending on the instruction code.
12717 Note that a switch statement instead of the sequence of tests
12718 would be incorrect as many of the CODE_FOR values could be
12719 CODE_FOR_nothing and that would yield multiple alternatives
12720 with identical values. We'd never reach here at runtime in
12722 if (icode == CODE_FOR_altivec_vsldoi_v4sf
12723 || icode == CODE_FOR_altivec_vsldoi_v4si
12724 || icode == CODE_FOR_altivec_vsldoi_v8hi
12725 || icode == CODE_FOR_altivec_vsldoi_v16qi)
12727 /* Only allow 4-bit unsigned literals. */
12729 if (TREE_CODE (arg2) != INTEGER_CST
12730 || TREE_INT_CST_LOW (arg2) & ~0xf)
12732 error ("argument 3 must be a 4-bit unsigned literal");
12736 else if (icode == CODE_FOR_vsx_xxpermdi_v2df
12737 || icode == CODE_FOR_vsx_xxpermdi_v2di
12738 || icode == CODE_FOR_vsx_xxsldwi_v16qi
12739 || icode == CODE_FOR_vsx_xxsldwi_v8hi
12740 || icode == CODE_FOR_vsx_xxsldwi_v4si
12741 || icode == CODE_FOR_vsx_xxsldwi_v4sf
12742 || icode == CODE_FOR_vsx_xxsldwi_v2di
12743 || icode == CODE_FOR_vsx_xxsldwi_v2df)
12745 /* Only allow 2-bit unsigned literals. */
12747 if (TREE_CODE (arg2) != INTEGER_CST
12748 || TREE_INT_CST_LOW (arg2) & ~0x3)
12750 error ("argument 3 must be a 2-bit unsigned literal");
12754 else if (icode == CODE_FOR_vsx_set_v2df
12755 || icode == CODE_FOR_vsx_set_v2di
12756 || icode == CODE_FOR_bcdadd
12757 || icode == CODE_FOR_bcdadd_lt
12758 || icode == CODE_FOR_bcdadd_eq
12759 || icode == CODE_FOR_bcdadd_gt
12760 || icode == CODE_FOR_bcdsub
12761 || icode == CODE_FOR_bcdsub_lt
12762 || icode == CODE_FOR_bcdsub_eq
12763 || icode == CODE_FOR_bcdsub_gt)
12765 /* Only allow 1-bit unsigned literals. */
12767 if (TREE_CODE (arg2) != INTEGER_CST
12768 || TREE_INT_CST_LOW (arg2) & ~0x1)
12770 error ("argument 3 must be a 1-bit unsigned literal");
12774 else if (icode == CODE_FOR_dfp_ddedpd_dd
12775 || icode == CODE_FOR_dfp_ddedpd_td)
12777 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
12779 if (TREE_CODE (arg0) != INTEGER_CST
12780 || TREE_INT_CST_LOW (arg2) & ~0x3)
12782 error ("argument 1 must be 0 or 2");
12786 else if (icode == CODE_FOR_dfp_denbcd_dd
12787 || icode == CODE_FOR_dfp_denbcd_td)
12789 /* Only allow 1-bit unsigned literals. */
12791 if (TREE_CODE (arg0) != INTEGER_CST
12792 || TREE_INT_CST_LOW (arg0) & ~0x1)
12794 error ("argument 1 must be a 1-bit unsigned literal");
12798 else if (icode == CODE_FOR_dfp_dscli_dd
12799 || icode == CODE_FOR_dfp_dscli_td
12800 || icode == CODE_FOR_dfp_dscri_dd
12801 || icode == CODE_FOR_dfp_dscri_td)
12803 /* Only allow 6-bit unsigned literals. */
12805 if (TREE_CODE (arg1) != INTEGER_CST
12806 || TREE_INT_CST_LOW (arg1) & ~0x3f)
12808 error ("argument 2 must be a 6-bit unsigned literal");
12812 else if (icode == CODE_FOR_crypto_vshasigmaw
12813 || icode == CODE_FOR_crypto_vshasigmad)
12815 /* Check whether the 2nd and 3rd arguments are integer constants and in
12816 range and prepare arguments. */
12818 if (TREE_CODE (arg1) != INTEGER_CST || wi::geu_p (arg1, 2))
12820 error ("argument 2 must be 0 or 1");
12825 if (TREE_CODE (arg2) != INTEGER_CST || wi::geu_p (arg1, 16))
12827 error ("argument 3 must be in the range 0..15");
12833 || GET_MODE (target) != tmode
12834 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12835 target = gen_reg_rtx (tmode);
12837 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12838 op0 = copy_to_mode_reg (mode0, op0);
12839 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
12840 op1 = copy_to_mode_reg (mode1, op1);
12841 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
12842 op2 = copy_to_mode_reg (mode2, op2);
12844 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
12845 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
12847 pat = GEN_FCN (icode) (target, op0, op1, op2);
12855 /* Expand the lvx builtins. */
12857 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
12859 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
12860 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
12862 machine_mode tmode, mode0;
12864 enum insn_code icode;
12868 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
12869 icode = CODE_FOR_vector_altivec_load_v16qi;
12871 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
12872 icode = CODE_FOR_vector_altivec_load_v8hi;
12874 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
12875 icode = CODE_FOR_vector_altivec_load_v4si;
12877 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
12878 icode = CODE_FOR_vector_altivec_load_v4sf;
12880 case ALTIVEC_BUILTIN_LD_INTERNAL_2df:
12881 icode = CODE_FOR_vector_altivec_load_v2df;
12883 case ALTIVEC_BUILTIN_LD_INTERNAL_2di:
12884 icode = CODE_FOR_vector_altivec_load_v2di;
12885 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti:
12886 icode = CODE_FOR_vector_altivec_load_v1ti;
12889 *expandedp = false;
12895 arg0 = CALL_EXPR_ARG (exp, 0);
12896 op0 = expand_normal (arg0);
12897 tmode = insn_data[icode].operand[0].mode;
12898 mode0 = insn_data[icode].operand[1].mode;
12901 || GET_MODE (target) != tmode
12902 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
12903 target = gen_reg_rtx (tmode);
12905 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
12906 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12908 pat = GEN_FCN (icode) (target, op0);
12915 /* Expand the stvx builtins. */
12917 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
12920 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
12921 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
12923 machine_mode mode0, mode1;
12925 enum insn_code icode;
12929 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
12930 icode = CODE_FOR_vector_altivec_store_v16qi;
12932 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
12933 icode = CODE_FOR_vector_altivec_store_v8hi;
12935 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
12936 icode = CODE_FOR_vector_altivec_store_v4si;
12938 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
12939 icode = CODE_FOR_vector_altivec_store_v4sf;
12941 case ALTIVEC_BUILTIN_ST_INTERNAL_2df:
12942 icode = CODE_FOR_vector_altivec_store_v2df;
12944 case ALTIVEC_BUILTIN_ST_INTERNAL_2di:
12945 icode = CODE_FOR_vector_altivec_store_v2di;
12946 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti:
12947 icode = CODE_FOR_vector_altivec_store_v1ti;
12950 *expandedp = false;
12954 arg0 = CALL_EXPR_ARG (exp, 0);
12955 arg1 = CALL_EXPR_ARG (exp, 1);
12956 op0 = expand_normal (arg0);
12957 op1 = expand_normal (arg1);
12958 mode0 = insn_data[icode].operand[0].mode;
12959 mode1 = insn_data[icode].operand[1].mode;
12961 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
12962 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
12963 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
12964 op1 = copy_to_mode_reg (mode1, op1);
12966 pat = GEN_FCN (icode) (op0, op1);
12974 /* Expand the dst builtins. */
12976 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
12979 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
12980 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
12981 tree arg0, arg1, arg2;
12982 machine_mode mode0, mode1;
12983 rtx pat, op0, op1, op2;
12984 const struct builtin_description *d;
12987 *expandedp = false;
12989 /* Handle DST variants. */
12991 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
12992 if (d->code == fcode)
12994 arg0 = CALL_EXPR_ARG (exp, 0);
12995 arg1 = CALL_EXPR_ARG (exp, 1);
12996 arg2 = CALL_EXPR_ARG (exp, 2);
12997 op0 = expand_normal (arg0);
12998 op1 = expand_normal (arg1);
12999 op2 = expand_normal (arg2);
13000 mode0 = insn_data[d->icode].operand[0].mode;
13001 mode1 = insn_data[d->icode].operand[1].mode;
13003 /* Invalid arguments, bail out before generating bad rtl. */
13004 if (arg0 == error_mark_node
13005 || arg1 == error_mark_node
13006 || arg2 == error_mark_node)
13011 if (TREE_CODE (arg2) != INTEGER_CST
13012 || TREE_INT_CST_LOW (arg2) & ~0x3)
13014 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
13018 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
13019 op0 = copy_to_mode_reg (Pmode, op0);
13020 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
13021 op1 = copy_to_mode_reg (mode1, op1);
13023 pat = GEN_FCN (d->icode) (op0, op1, op2);
13033 /* Expand vec_init builtin. */
13035 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
13037 machine_mode tmode = TYPE_MODE (type);
13038 machine_mode inner_mode = GET_MODE_INNER (tmode);
13039 int i, n_elt = GET_MODE_NUNITS (tmode);
13041 gcc_assert (VECTOR_MODE_P (tmode));
13042 gcc_assert (n_elt == call_expr_nargs (exp));
13044 if (!target || !register_operand (target, tmode))
13045 target = gen_reg_rtx (tmode);
13047 /* If we have a vector compromised of a single element, such as V1TImode, do
13048 the initialization directly. */
13049 if (n_elt == 1 && GET_MODE_SIZE (tmode) == GET_MODE_SIZE (inner_mode))
13051 rtx x = expand_normal (CALL_EXPR_ARG (exp, 0));
13052 emit_move_insn (target, gen_lowpart (tmode, x));
13056 rtvec v = rtvec_alloc (n_elt);
13058 for (i = 0; i < n_elt; ++i)
13060 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
13061 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
13064 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
13070 /* Return the integer constant in ARG. Constrain it to be in the range
13071 of the subparts of VEC_TYPE; issue an error if not. */
13074 get_element_number (tree vec_type, tree arg)
13076 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
13078 if (!tree_fits_uhwi_p (arg)
13079 || (elt = tree_to_uhwi (arg), elt > max))
13081 error ("selector must be an integer constant in the range 0..%wi", max);
13088 /* Expand vec_set builtin. */
13090 altivec_expand_vec_set_builtin (tree exp)
13092 machine_mode tmode, mode1;
13093 tree arg0, arg1, arg2;
13097 arg0 = CALL_EXPR_ARG (exp, 0);
13098 arg1 = CALL_EXPR_ARG (exp, 1);
13099 arg2 = CALL_EXPR_ARG (exp, 2);
13101 tmode = TYPE_MODE (TREE_TYPE (arg0));
13102 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
13103 gcc_assert (VECTOR_MODE_P (tmode));
13105 op0 = expand_expr (arg0, NULL_RTX, tmode, EXPAND_NORMAL);
13106 op1 = expand_expr (arg1, NULL_RTX, mode1, EXPAND_NORMAL);
13107 elt = get_element_number (TREE_TYPE (arg0), arg2);
13109 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
13110 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
13112 op0 = force_reg (tmode, op0);
13113 op1 = force_reg (mode1, op1);
13115 rs6000_expand_vector_set (op0, op1, elt);
13120 /* Expand vec_ext builtin. */
13122 altivec_expand_vec_ext_builtin (tree exp, rtx target)
13124 machine_mode tmode, mode0;
13129 arg0 = CALL_EXPR_ARG (exp, 0);
13130 arg1 = CALL_EXPR_ARG (exp, 1);
13132 op0 = expand_normal (arg0);
13133 elt = get_element_number (TREE_TYPE (arg0), arg1);
13135 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
13136 mode0 = TYPE_MODE (TREE_TYPE (arg0));
13137 gcc_assert (VECTOR_MODE_P (mode0));
13139 op0 = force_reg (mode0, op0);
13141 if (optimize || !target || !register_operand (target, tmode))
13142 target = gen_reg_rtx (tmode);
13144 rs6000_expand_vector_extract (target, op0, elt);
13149 /* Expand the builtin in EXP and store the result in TARGET. Store
13150 true in *EXPANDEDP if we found a builtin to expand. */
13152 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
13154 const struct builtin_description *d;
13156 enum insn_code icode;
13157 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13160 machine_mode tmode, mode0;
13161 enum rs6000_builtins fcode
13162 = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
13164 if (rs6000_overloaded_builtin_p (fcode))
13167 error ("unresolved overload for Altivec builtin %qF", fndecl);
13169 /* Given it is invalid, just generate a normal call. */
13170 return expand_call (exp, target, false);
13173 target = altivec_expand_ld_builtin (exp, target, expandedp);
13177 target = altivec_expand_st_builtin (exp, target, expandedp);
13181 target = altivec_expand_dst_builtin (exp, target, expandedp);
13189 case ALTIVEC_BUILTIN_STVX_V2DF:
13190 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df, exp);
13191 case ALTIVEC_BUILTIN_STVX_V2DI:
13192 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di, exp);
13193 case ALTIVEC_BUILTIN_STVX_V4SF:
13194 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf, exp);
13195 case ALTIVEC_BUILTIN_STVX:
13196 case ALTIVEC_BUILTIN_STVX_V4SI:
13197 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si, exp);
13198 case ALTIVEC_BUILTIN_STVX_V8HI:
13199 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi, exp);
13200 case ALTIVEC_BUILTIN_STVX_V16QI:
13201 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi, exp);
13202 case ALTIVEC_BUILTIN_STVEBX:
13203 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
13204 case ALTIVEC_BUILTIN_STVEHX:
13205 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
13206 case ALTIVEC_BUILTIN_STVEWX:
13207 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
13208 case ALTIVEC_BUILTIN_STVXL_V2DF:
13209 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df, exp);
13210 case ALTIVEC_BUILTIN_STVXL_V2DI:
13211 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di, exp);
13212 case ALTIVEC_BUILTIN_STVXL_V4SF:
13213 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf, exp);
13214 case ALTIVEC_BUILTIN_STVXL:
13215 case ALTIVEC_BUILTIN_STVXL_V4SI:
13216 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si, exp);
13217 case ALTIVEC_BUILTIN_STVXL_V8HI:
13218 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi, exp);
13219 case ALTIVEC_BUILTIN_STVXL_V16QI:
13220 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi, exp);
13222 case ALTIVEC_BUILTIN_STVLX:
13223 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx, exp);
13224 case ALTIVEC_BUILTIN_STVLXL:
13225 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl, exp);
13226 case ALTIVEC_BUILTIN_STVRX:
13227 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx, exp);
13228 case ALTIVEC_BUILTIN_STVRXL:
13229 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl, exp);
13231 case VSX_BUILTIN_STXVD2X_V1TI:
13232 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti, exp);
13233 case VSX_BUILTIN_STXVD2X_V2DF:
13234 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df, exp);
13235 case VSX_BUILTIN_STXVD2X_V2DI:
13236 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di, exp);
13237 case VSX_BUILTIN_STXVW4X_V4SF:
13238 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf, exp);
13239 case VSX_BUILTIN_STXVW4X_V4SI:
13240 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si, exp);
13241 case VSX_BUILTIN_STXVW4X_V8HI:
13242 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi, exp);
13243 case VSX_BUILTIN_STXVW4X_V16QI:
13244 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi, exp);
13246 case ALTIVEC_BUILTIN_MFVSCR:
13247 icode = CODE_FOR_altivec_mfvscr;
13248 tmode = insn_data[icode].operand[0].mode;
13251 || GET_MODE (target) != tmode
13252 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13253 target = gen_reg_rtx (tmode);
13255 pat = GEN_FCN (icode) (target);
13261 case ALTIVEC_BUILTIN_MTVSCR:
13262 icode = CODE_FOR_altivec_mtvscr;
13263 arg0 = CALL_EXPR_ARG (exp, 0);
13264 op0 = expand_normal (arg0);
13265 mode0 = insn_data[icode].operand[0].mode;
13267 /* If we got invalid arguments bail out before generating bad rtl. */
13268 if (arg0 == error_mark_node)
13271 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13272 op0 = copy_to_mode_reg (mode0, op0);
13274 pat = GEN_FCN (icode) (op0);
13279 case ALTIVEC_BUILTIN_DSSALL:
13280 emit_insn (gen_altivec_dssall ());
13283 case ALTIVEC_BUILTIN_DSS:
13284 icode = CODE_FOR_altivec_dss;
13285 arg0 = CALL_EXPR_ARG (exp, 0);
13287 op0 = expand_normal (arg0);
13288 mode0 = insn_data[icode].operand[0].mode;
13290 /* If we got invalid arguments bail out before generating bad rtl. */
13291 if (arg0 == error_mark_node)
13294 if (TREE_CODE (arg0) != INTEGER_CST
13295 || TREE_INT_CST_LOW (arg0) & ~0x3)
13297 error ("argument to dss must be a 2-bit unsigned literal");
13301 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13302 op0 = copy_to_mode_reg (mode0, op0);
13304 emit_insn (gen_altivec_dss (op0));
13307 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
13308 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
13309 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
13310 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
13311 case VSX_BUILTIN_VEC_INIT_V2DF:
13312 case VSX_BUILTIN_VEC_INIT_V2DI:
13313 case VSX_BUILTIN_VEC_INIT_V1TI:
13314 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
13316 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
13317 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
13318 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
13319 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
13320 case VSX_BUILTIN_VEC_SET_V2DF:
13321 case VSX_BUILTIN_VEC_SET_V2DI:
13322 case VSX_BUILTIN_VEC_SET_V1TI:
13323 return altivec_expand_vec_set_builtin (exp);
13325 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
13326 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
13327 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
13328 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
13329 case VSX_BUILTIN_VEC_EXT_V2DF:
13330 case VSX_BUILTIN_VEC_EXT_V2DI:
13331 case VSX_BUILTIN_VEC_EXT_V1TI:
13332 return altivec_expand_vec_ext_builtin (exp, target);
13336 /* Fall through. */
13339 /* Expand abs* operations. */
13341 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
13342 if (d->code == fcode)
13343 return altivec_expand_abs_builtin (d->icode, exp, target);
13345 /* Expand the AltiVec predicates. */
13346 d = bdesc_altivec_preds;
13347 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
13348 if (d->code == fcode)
13349 return altivec_expand_predicate_builtin (d->icode, exp, target);
13351 /* LV* are funky. We initialized them differently. */
13354 case ALTIVEC_BUILTIN_LVSL:
13355 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
13356 exp, target, false);
13357 case ALTIVEC_BUILTIN_LVSR:
13358 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
13359 exp, target, false);
13360 case ALTIVEC_BUILTIN_LVEBX:
13361 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
13362 exp, target, false);
13363 case ALTIVEC_BUILTIN_LVEHX:
13364 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
13365 exp, target, false);
13366 case ALTIVEC_BUILTIN_LVEWX:
13367 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
13368 exp, target, false);
13369 case ALTIVEC_BUILTIN_LVXL_V2DF:
13370 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df,
13371 exp, target, false);
13372 case ALTIVEC_BUILTIN_LVXL_V2DI:
13373 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di,
13374 exp, target, false);
13375 case ALTIVEC_BUILTIN_LVXL_V4SF:
13376 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf,
13377 exp, target, false);
13378 case ALTIVEC_BUILTIN_LVXL:
13379 case ALTIVEC_BUILTIN_LVXL_V4SI:
13380 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si,
13381 exp, target, false);
13382 case ALTIVEC_BUILTIN_LVXL_V8HI:
13383 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi,
13384 exp, target, false);
13385 case ALTIVEC_BUILTIN_LVXL_V16QI:
13386 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi,
13387 exp, target, false);
13388 case ALTIVEC_BUILTIN_LVX_V2DF:
13389 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df,
13390 exp, target, false);
13391 case ALTIVEC_BUILTIN_LVX_V2DI:
13392 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di,
13393 exp, target, false);
13394 case ALTIVEC_BUILTIN_LVX_V4SF:
13395 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf,
13396 exp, target, false);
13397 case ALTIVEC_BUILTIN_LVX:
13398 case ALTIVEC_BUILTIN_LVX_V4SI:
13399 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si,
13400 exp, target, false);
13401 case ALTIVEC_BUILTIN_LVX_V8HI:
13402 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi,
13403 exp, target, false);
13404 case ALTIVEC_BUILTIN_LVX_V16QI:
13405 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi,
13406 exp, target, false);
13407 case ALTIVEC_BUILTIN_LVLX:
13408 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx,
13409 exp, target, true);
13410 case ALTIVEC_BUILTIN_LVLXL:
13411 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl,
13412 exp, target, true);
13413 case ALTIVEC_BUILTIN_LVRX:
13414 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx,
13415 exp, target, true);
13416 case ALTIVEC_BUILTIN_LVRXL:
13417 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl,
13418 exp, target, true);
13419 case VSX_BUILTIN_LXVD2X_V1TI:
13420 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti,
13421 exp, target, false);
13422 case VSX_BUILTIN_LXVD2X_V2DF:
13423 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df,
13424 exp, target, false);
13425 case VSX_BUILTIN_LXVD2X_V2DI:
13426 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di,
13427 exp, target, false);
13428 case VSX_BUILTIN_LXVW4X_V4SF:
13429 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf,
13430 exp, target, false);
13431 case VSX_BUILTIN_LXVW4X_V4SI:
13432 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si,
13433 exp, target, false);
13434 case VSX_BUILTIN_LXVW4X_V8HI:
13435 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi,
13436 exp, target, false);
13437 case VSX_BUILTIN_LXVW4X_V16QI:
13438 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi,
13439 exp, target, false);
13443 /* Fall through. */
13446 *expandedp = false;
13450 /* Expand the builtin in EXP and store the result in TARGET. Store
13451 true in *EXPANDEDP if we found a builtin to expand. */
13453 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
13455 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13456 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
13457 const struct builtin_description *d;
13464 case PAIRED_BUILTIN_STX:
13465 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
13466 case PAIRED_BUILTIN_LX:
13467 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
13470 /* Fall through. */
13473 /* Expand the paired predicates. */
13474 d = bdesc_paired_preds;
13475 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
13476 if (d->code == fcode)
13477 return paired_expand_predicate_builtin (d->icode, exp, target);
13479 *expandedp = false;
13483 /* Binops that need to be initialized manually, but can be expanded
13484 automagically by rs6000_expand_binop_builtin. */
13485 static const struct builtin_description bdesc_2arg_spe[] =
13487 { RS6000_BTM_SPE, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
13488 { RS6000_BTM_SPE, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
13489 { RS6000_BTM_SPE, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
13490 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
13491 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
13492 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
13493 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
13494 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
13495 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
13496 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
13497 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
13498 { RS6000_BTM_SPE, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
13499 { RS6000_BTM_SPE, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
13500 { RS6000_BTM_SPE, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
13501 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
13502 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
13503 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
13504 { RS6000_BTM_SPE, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
13505 { RS6000_BTM_SPE, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
13506 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
13507 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
13508 { RS6000_BTM_SPE, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
13511 /* Expand the builtin in EXP and store the result in TARGET. Store
13512 true in *EXPANDEDP if we found a builtin to expand.
13514 This expands the SPE builtins that are not simple unary and binary
13517 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
13519 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13521 enum rs6000_builtins fcode = (enum rs6000_builtins) DECL_FUNCTION_CODE (fndecl);
13522 enum insn_code icode;
13523 machine_mode tmode, mode0;
13525 const struct builtin_description *d;
13530 /* Syntax check for a 5-bit unsigned immediate. */
13533 case SPE_BUILTIN_EVSTDD:
13534 case SPE_BUILTIN_EVSTDH:
13535 case SPE_BUILTIN_EVSTDW:
13536 case SPE_BUILTIN_EVSTWHE:
13537 case SPE_BUILTIN_EVSTWHO:
13538 case SPE_BUILTIN_EVSTWWE:
13539 case SPE_BUILTIN_EVSTWWO:
13540 arg1 = CALL_EXPR_ARG (exp, 2);
13541 if (TREE_CODE (arg1) != INTEGER_CST
13542 || TREE_INT_CST_LOW (arg1) & ~0x1f)
13544 error ("argument 2 must be a 5-bit unsigned literal");
13552 /* The evsplat*i instructions are not quite generic. */
13555 case SPE_BUILTIN_EVSPLATFI:
13556 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
13558 case SPE_BUILTIN_EVSPLATI:
13559 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
13565 d = bdesc_2arg_spe;
13566 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
13567 if (d->code == fcode)
13568 return rs6000_expand_binop_builtin (d->icode, exp, target);
13570 d = bdesc_spe_predicates;
13571 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
13572 if (d->code == fcode)
13573 return spe_expand_predicate_builtin (d->icode, exp, target);
13575 d = bdesc_spe_evsel;
13576 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
13577 if (d->code == fcode)
13578 return spe_expand_evsel_builtin (d->icode, exp, target);
13582 case SPE_BUILTIN_EVSTDDX:
13583 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
13584 case SPE_BUILTIN_EVSTDHX:
13585 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
13586 case SPE_BUILTIN_EVSTDWX:
13587 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
13588 case SPE_BUILTIN_EVSTWHEX:
13589 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
13590 case SPE_BUILTIN_EVSTWHOX:
13591 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
13592 case SPE_BUILTIN_EVSTWWEX:
13593 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
13594 case SPE_BUILTIN_EVSTWWOX:
13595 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
13596 case SPE_BUILTIN_EVSTDD:
13597 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
13598 case SPE_BUILTIN_EVSTDH:
13599 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
13600 case SPE_BUILTIN_EVSTDW:
13601 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
13602 case SPE_BUILTIN_EVSTWHE:
13603 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
13604 case SPE_BUILTIN_EVSTWHO:
13605 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
13606 case SPE_BUILTIN_EVSTWWE:
13607 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
13608 case SPE_BUILTIN_EVSTWWO:
13609 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
13610 case SPE_BUILTIN_MFSPEFSCR:
13611 icode = CODE_FOR_spe_mfspefscr;
13612 tmode = insn_data[icode].operand[0].mode;
13615 || GET_MODE (target) != tmode
13616 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
13617 target = gen_reg_rtx (tmode);
13619 pat = GEN_FCN (icode) (target);
13624 case SPE_BUILTIN_MTSPEFSCR:
13625 icode = CODE_FOR_spe_mtspefscr;
13626 arg0 = CALL_EXPR_ARG (exp, 0);
13627 op0 = expand_normal (arg0);
13628 mode0 = insn_data[icode].operand[0].mode;
13630 if (arg0 == error_mark_node)
13633 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
13634 op0 = copy_to_mode_reg (mode0, op0);
13636 pat = GEN_FCN (icode) (op0);
13644 *expandedp = false;
13649 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
13651 rtx pat, scratch, tmp;
13652 tree form = CALL_EXPR_ARG (exp, 0);
13653 tree arg0 = CALL_EXPR_ARG (exp, 1);
13654 tree arg1 = CALL_EXPR_ARG (exp, 2);
13655 rtx op0 = expand_normal (arg0);
13656 rtx op1 = expand_normal (arg1);
13657 machine_mode mode0 = insn_data[icode].operand[1].mode;
13658 machine_mode mode1 = insn_data[icode].operand[2].mode;
13660 enum rtx_code code;
13662 if (TREE_CODE (form) != INTEGER_CST)
13664 error ("argument 1 of __builtin_paired_predicate must be a constant");
13668 form_int = TREE_INT_CST_LOW (form);
13670 gcc_assert (mode0 == mode1);
13672 if (arg0 == error_mark_node || arg1 == error_mark_node)
13676 || GET_MODE (target) != SImode
13677 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
13678 target = gen_reg_rtx (SImode);
13679 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
13680 op0 = copy_to_mode_reg (mode0, op0);
13681 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
13682 op1 = copy_to_mode_reg (mode1, op1);
13684 scratch = gen_reg_rtx (CCFPmode);
13686 pat = GEN_FCN (icode) (scratch, op0, op1);
13708 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
13711 error ("argument 1 of __builtin_paired_predicate is out of range");
13715 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
13716 emit_move_insn (target, tmp);
13721 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
13723 rtx pat, scratch, tmp;
13724 tree form = CALL_EXPR_ARG (exp, 0);
13725 tree arg0 = CALL_EXPR_ARG (exp, 1);
13726 tree arg1 = CALL_EXPR_ARG (exp, 2);
13727 rtx op0 = expand_normal (arg0);
13728 rtx op1 = expand_normal (arg1);
13729 machine_mode mode0 = insn_data[icode].operand[1].mode;
13730 machine_mode mode1 = insn_data[icode].operand[2].mode;
13732 enum rtx_code code;
13734 if (TREE_CODE (form) != INTEGER_CST)
13736 error ("argument 1 of __builtin_spe_predicate must be a constant");
13740 form_int = TREE_INT_CST_LOW (form);
13742 gcc_assert (mode0 == mode1);
13744 if (arg0 == error_mark_node || arg1 == error_mark_node)
13748 || GET_MODE (target) != SImode
13749 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
13750 target = gen_reg_rtx (SImode);
13752 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13753 op0 = copy_to_mode_reg (mode0, op0);
13754 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
13755 op1 = copy_to_mode_reg (mode1, op1);
13757 scratch = gen_reg_rtx (CCmode);
13759 pat = GEN_FCN (icode) (scratch, op0, op1);
13764 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
13765 _lower_. We use one compare, but look in different bits of the
13766 CR for each variant.
13768 There are 2 elements in each SPE simd type (upper/lower). The CR
13769 bits are set as follows:
13771 BIT0 | BIT 1 | BIT 2 | BIT 3
13772 U | L | (U | L) | (U & L)
13774 So, for an "all" relationship, BIT 3 would be set.
13775 For an "any" relationship, BIT 2 would be set. Etc.
13777 Following traditional nomenclature, these bits map to:
13779 BIT0 | BIT 1 | BIT 2 | BIT 3
13782 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
13787 /* All variant. OV bit. */
13789 /* We need to get to the OV bit, which is the ORDERED bit. We
13790 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
13791 that's ugly and will make validate_condition_mode die.
13792 So let's just use another pattern. */
13793 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
13795 /* Any variant. EQ bit. */
13799 /* Upper variant. LT bit. */
13803 /* Lower variant. GT bit. */
13808 error ("argument 1 of __builtin_spe_predicate is out of range");
13812 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
13813 emit_move_insn (target, tmp);
13818 /* The evsel builtins look like this:
13820 e = __builtin_spe_evsel_OP (a, b, c, d);
13822 and work like this:
13824 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
13825 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
13829 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
13832 tree arg0 = CALL_EXPR_ARG (exp, 0);
13833 tree arg1 = CALL_EXPR_ARG (exp, 1);
13834 tree arg2 = CALL_EXPR_ARG (exp, 2);
13835 tree arg3 = CALL_EXPR_ARG (exp, 3);
13836 rtx op0 = expand_normal (arg0);
13837 rtx op1 = expand_normal (arg1);
13838 rtx op2 = expand_normal (arg2);
13839 rtx op3 = expand_normal (arg3);
13840 machine_mode mode0 = insn_data[icode].operand[1].mode;
13841 machine_mode mode1 = insn_data[icode].operand[2].mode;
13843 gcc_assert (mode0 == mode1);
13845 if (arg0 == error_mark_node || arg1 == error_mark_node
13846 || arg2 == error_mark_node || arg3 == error_mark_node)
13850 || GET_MODE (target) != mode0
13851 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
13852 target = gen_reg_rtx (mode0);
13854 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
13855 op0 = copy_to_mode_reg (mode0, op0);
13856 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
13857 op1 = copy_to_mode_reg (mode0, op1);
13858 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
13859 op2 = copy_to_mode_reg (mode0, op2);
13860 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
13861 op3 = copy_to_mode_reg (mode0, op3);
13863 /* Generate the compare. */
13864 scratch = gen_reg_rtx (CCmode);
13865 pat = GEN_FCN (icode) (scratch, op0, op1);
13870 if (mode0 == V2SImode)
13871 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
13873 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
13878 /* Raise an error message for a builtin function that is called without the
13879 appropriate target options being set. */
13882 rs6000_invalid_builtin (enum rs6000_builtins fncode)
13884 size_t uns_fncode = (size_t)fncode;
13885 const char *name = rs6000_builtin_info[uns_fncode].name;
13886 HOST_WIDE_INT fnmask = rs6000_builtin_info[uns_fncode].mask;
13888 gcc_assert (name != NULL);
13889 if ((fnmask & RS6000_BTM_CELL) != 0)
13890 error ("Builtin function %s is only valid for the cell processor", name);
13891 else if ((fnmask & RS6000_BTM_VSX) != 0)
13892 error ("Builtin function %s requires the -mvsx option", name);
13893 else if ((fnmask & RS6000_BTM_HTM) != 0)
13894 error ("Builtin function %s requires the -mhtm option", name);
13895 else if ((fnmask & RS6000_BTM_ALTIVEC) != 0)
13896 error ("Builtin function %s requires the -maltivec option", name);
13897 else if ((fnmask & RS6000_BTM_PAIRED) != 0)
13898 error ("Builtin function %s requires the -mpaired option", name);
13899 else if ((fnmask & RS6000_BTM_SPE) != 0)
13900 error ("Builtin function %s requires the -mspe option", name);
13901 else if ((fnmask & (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
13902 == (RS6000_BTM_DFP | RS6000_BTM_P8_VECTOR))
13903 error ("Builtin function %s requires the -mhard-dfp and"
13904 " -mpower8-vector options", name);
13905 else if ((fnmask & RS6000_BTM_DFP) != 0)
13906 error ("Builtin function %s requires the -mhard-dfp option", name);
13907 else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
13908 error ("Builtin function %s requires the -mpower8-vector option", name);
13909 else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
13910 == (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
13911 error ("Builtin function %s requires the -mhard-float and"
13912 " -mlong-double-128 options", name);
13913 else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
13914 error ("Builtin function %s requires the -mhard-float option", name);
13916 error ("Builtin function %s is not supported with the current options",
13920 /* Expand an expression EXP that calls a built-in function,
13921 with result going to TARGET if that's convenient
13922 (and in mode MODE if that's convenient).
13923 SUBTARGET may be used as the target for computing one of EXP's operands.
13924 IGNORE is nonzero if the value is to be ignored. */
13927 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
13928 machine_mode mode ATTRIBUTE_UNUSED,
13929 int ignore ATTRIBUTE_UNUSED)
13931 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
13932 enum rs6000_builtins fcode
13933 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl);
13934 size_t uns_fcode = (size_t)fcode;
13935 const struct builtin_description *d;
13939 HOST_WIDE_INT mask = rs6000_builtin_info[uns_fcode].mask;
13940 bool func_valid_p = ((rs6000_builtin_mask & mask) == mask);
13942 if (TARGET_DEBUG_BUILTIN)
13944 enum insn_code icode = rs6000_builtin_info[uns_fcode].icode;
13945 const char *name1 = rs6000_builtin_info[uns_fcode].name;
13946 const char *name2 = ((icode != CODE_FOR_nothing)
13947 ? get_insn_name ((int)icode)
13951 switch (rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK)
13953 default: name3 = "unknown"; break;
13954 case RS6000_BTC_SPECIAL: name3 = "special"; break;
13955 case RS6000_BTC_UNARY: name3 = "unary"; break;
13956 case RS6000_BTC_BINARY: name3 = "binary"; break;
13957 case RS6000_BTC_TERNARY: name3 = "ternary"; break;
13958 case RS6000_BTC_PREDICATE: name3 = "predicate"; break;
13959 case RS6000_BTC_ABS: name3 = "abs"; break;
13960 case RS6000_BTC_EVSEL: name3 = "evsel"; break;
13961 case RS6000_BTC_DST: name3 = "dst"; break;
13966 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
13967 (name1) ? name1 : "---", fcode,
13968 (name2) ? name2 : "---", (int)icode,
13970 func_valid_p ? "" : ", not valid");
13975 rs6000_invalid_builtin (fcode);
13977 /* Given it is invalid, just generate a normal call. */
13978 return expand_call (exp, target, ignore);
13983 case RS6000_BUILTIN_RECIP:
13984 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
13986 case RS6000_BUILTIN_RECIPF:
13987 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
13989 case RS6000_BUILTIN_RSQRTF:
13990 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
13992 case RS6000_BUILTIN_RSQRT:
13993 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2, exp, target);
13995 case POWER7_BUILTIN_BPERMD:
13996 return rs6000_expand_binop_builtin (((TARGET_64BIT)
13997 ? CODE_FOR_bpermd_di
13998 : CODE_FOR_bpermd_si), exp, target);
14000 case RS6000_BUILTIN_GET_TB:
14001 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase,
14004 case RS6000_BUILTIN_MFTB:
14005 return rs6000_expand_zeroop_builtin (((TARGET_64BIT)
14006 ? CODE_FOR_rs6000_mftb_di
14007 : CODE_FOR_rs6000_mftb_si),
14010 case RS6000_BUILTIN_MFFS:
14011 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs, target);
14013 case RS6000_BUILTIN_MTFSF:
14014 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf, exp);
14016 case ALTIVEC_BUILTIN_MASK_FOR_LOAD:
14017 case ALTIVEC_BUILTIN_MASK_FOR_STORE:
14019 int icode = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct
14020 : (int) CODE_FOR_altivec_lvsl_direct);
14021 machine_mode tmode = insn_data[icode].operand[0].mode;
14022 machine_mode mode = insn_data[icode].operand[1].mode;
14026 gcc_assert (TARGET_ALTIVEC);
14028 arg = CALL_EXPR_ARG (exp, 0);
14029 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg)));
14030 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
14031 addr = memory_address (mode, op);
14032 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
14036 /* For the load case need to negate the address. */
14037 op = gen_reg_rtx (GET_MODE (addr));
14038 emit_insn (gen_rtx_SET (VOIDmode, op,
14039 gen_rtx_NEG (GET_MODE (addr), addr)));
14041 op = gen_rtx_MEM (mode, op);
14044 || GET_MODE (target) != tmode
14045 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
14046 target = gen_reg_rtx (tmode);
14048 pat = GEN_FCN (icode) (target, op);
14056 case ALTIVEC_BUILTIN_VCFUX:
14057 case ALTIVEC_BUILTIN_VCFSX:
14058 case ALTIVEC_BUILTIN_VCTUXS:
14059 case ALTIVEC_BUILTIN_VCTSXS:
14060 /* FIXME: There's got to be a nicer way to handle this case than
14061 constructing a new CALL_EXPR. */
14062 if (call_expr_nargs (exp) == 1)
14064 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
14065 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
14073 if (TARGET_ALTIVEC)
14075 ret = altivec_expand_builtin (exp, target, &success);
14082 ret = spe_expand_builtin (exp, target, &success);
14087 if (TARGET_PAIRED_FLOAT)
14089 ret = paired_expand_builtin (exp, target, &success);
14096 ret = htm_expand_builtin (exp, target, &success);
14102 unsigned attr = rs6000_builtin_info[uns_fcode].attr & RS6000_BTC_TYPE_MASK;
14103 gcc_assert (attr == RS6000_BTC_UNARY
14104 || attr == RS6000_BTC_BINARY
14105 || attr == RS6000_BTC_TERNARY);
14107 /* Handle simple unary operations. */
14109 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
14110 if (d->code == fcode)
14111 return rs6000_expand_unop_builtin (d->icode, exp, target);
14113 /* Handle simple binary operations. */
14115 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
14116 if (d->code == fcode)
14117 return rs6000_expand_binop_builtin (d->icode, exp, target);
14119 /* Handle simple ternary operations. */
14121 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
14122 if (d->code == fcode)
14123 return rs6000_expand_ternop_builtin (d->icode, exp, target);
14125 gcc_unreachable ();
14129 rs6000_init_builtins (void)
14135 if (TARGET_DEBUG_BUILTIN)
14136 fprintf (stderr, "rs6000_init_builtins%s%s%s%s\n",
14137 (TARGET_PAIRED_FLOAT) ? ", paired" : "",
14138 (TARGET_SPE) ? ", spe" : "",
14139 (TARGET_ALTIVEC) ? ", altivec" : "",
14140 (TARGET_VSX) ? ", vsx" : "");
14142 V2SI_type_node = build_vector_type (intSI_type_node, 2);
14143 V2SF_type_node = build_vector_type (float_type_node, 2);
14144 V2DI_type_node = build_vector_type (intDI_type_node, 2);
14145 V2DF_type_node = build_vector_type (double_type_node, 2);
14146 V4HI_type_node = build_vector_type (intHI_type_node, 4);
14147 V4SI_type_node = build_vector_type (intSI_type_node, 4);
14148 V4SF_type_node = build_vector_type (float_type_node, 4);
14149 V8HI_type_node = build_vector_type (intHI_type_node, 8);
14150 V16QI_type_node = build_vector_type (intQI_type_node, 16);
14152 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
14153 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
14154 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
14155 unsigned_V2DI_type_node = build_vector_type (unsigned_intDI_type_node, 2);
14157 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
14158 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
14159 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
14160 opaque_V4SI_type_node = build_opaque_vector_type (intSI_type_node, 4);
14162 /* We use V1TI mode as a special container to hold __int128_t items that
14163 must live in VSX registers. */
14164 if (intTI_type_node)
14166 V1TI_type_node = build_vector_type (intTI_type_node, 1);
14167 unsigned_V1TI_type_node = build_vector_type (unsigned_intTI_type_node, 1);
14170 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
14171 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
14172 'vector unsigned short'. */
14174 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
14175 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
14176 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
14177 bool_long_type_node = build_distinct_type_copy (unsigned_intDI_type_node);
14178 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
14180 long_integer_type_internal_node = long_integer_type_node;
14181 long_unsigned_type_internal_node = long_unsigned_type_node;
14182 long_long_integer_type_internal_node = long_long_integer_type_node;
14183 long_long_unsigned_type_internal_node = long_long_unsigned_type_node;
14184 intQI_type_internal_node = intQI_type_node;
14185 uintQI_type_internal_node = unsigned_intQI_type_node;
14186 intHI_type_internal_node = intHI_type_node;
14187 uintHI_type_internal_node = unsigned_intHI_type_node;
14188 intSI_type_internal_node = intSI_type_node;
14189 uintSI_type_internal_node = unsigned_intSI_type_node;
14190 intDI_type_internal_node = intDI_type_node;
14191 uintDI_type_internal_node = unsigned_intDI_type_node;
14192 intTI_type_internal_node = intTI_type_node;
14193 uintTI_type_internal_node = unsigned_intTI_type_node;
14194 float_type_internal_node = float_type_node;
14195 double_type_internal_node = double_type_node;
14196 long_double_type_internal_node = long_double_type_node;
14197 dfloat64_type_internal_node = dfloat64_type_node;
14198 dfloat128_type_internal_node = dfloat128_type_node;
14199 void_type_internal_node = void_type_node;
14201 /* Initialize the modes for builtin_function_type, mapping a machine mode to
14203 builtin_mode_to_type[QImode][0] = integer_type_node;
14204 builtin_mode_to_type[HImode][0] = integer_type_node;
14205 builtin_mode_to_type[SImode][0] = intSI_type_node;
14206 builtin_mode_to_type[SImode][1] = unsigned_intSI_type_node;
14207 builtin_mode_to_type[DImode][0] = intDI_type_node;
14208 builtin_mode_to_type[DImode][1] = unsigned_intDI_type_node;
14209 builtin_mode_to_type[TImode][0] = intTI_type_node;
14210 builtin_mode_to_type[TImode][1] = unsigned_intTI_type_node;
14211 builtin_mode_to_type[SFmode][0] = float_type_node;
14212 builtin_mode_to_type[DFmode][0] = double_type_node;
14213 builtin_mode_to_type[TFmode][0] = long_double_type_node;
14214 builtin_mode_to_type[DDmode][0] = dfloat64_type_node;
14215 builtin_mode_to_type[TDmode][0] = dfloat128_type_node;
14216 builtin_mode_to_type[V1TImode][0] = V1TI_type_node;
14217 builtin_mode_to_type[V1TImode][1] = unsigned_V1TI_type_node;
14218 builtin_mode_to_type[V2SImode][0] = V2SI_type_node;
14219 builtin_mode_to_type[V2SFmode][0] = V2SF_type_node;
14220 builtin_mode_to_type[V2DImode][0] = V2DI_type_node;
14221 builtin_mode_to_type[V2DImode][1] = unsigned_V2DI_type_node;
14222 builtin_mode_to_type[V2DFmode][0] = V2DF_type_node;
14223 builtin_mode_to_type[V4HImode][0] = V4HI_type_node;
14224 builtin_mode_to_type[V4SImode][0] = V4SI_type_node;
14225 builtin_mode_to_type[V4SImode][1] = unsigned_V4SI_type_node;
14226 builtin_mode_to_type[V4SFmode][0] = V4SF_type_node;
14227 builtin_mode_to_type[V8HImode][0] = V8HI_type_node;
14228 builtin_mode_to_type[V8HImode][1] = unsigned_V8HI_type_node;
14229 builtin_mode_to_type[V16QImode][0] = V16QI_type_node;
14230 builtin_mode_to_type[V16QImode][1] = unsigned_V16QI_type_node;
14232 tdecl = add_builtin_type ("__bool char", bool_char_type_node);
14233 TYPE_NAME (bool_char_type_node) = tdecl;
14235 tdecl = add_builtin_type ("__bool short", bool_short_type_node);
14236 TYPE_NAME (bool_short_type_node) = tdecl;
14238 tdecl = add_builtin_type ("__bool int", bool_int_type_node);
14239 TYPE_NAME (bool_int_type_node) = tdecl;
14241 tdecl = add_builtin_type ("__pixel", pixel_type_node);
14242 TYPE_NAME (pixel_type_node) = tdecl;
14244 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
14245 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
14246 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
14247 bool_V2DI_type_node = build_vector_type (bool_long_type_node, 2);
14248 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
14250 tdecl = add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node);
14251 TYPE_NAME (unsigned_V16QI_type_node) = tdecl;
14253 tdecl = add_builtin_type ("__vector signed char", V16QI_type_node);
14254 TYPE_NAME (V16QI_type_node) = tdecl;
14256 tdecl = add_builtin_type ("__vector __bool char", bool_V16QI_type_node);
14257 TYPE_NAME ( bool_V16QI_type_node) = tdecl;
14259 tdecl = add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node);
14260 TYPE_NAME (unsigned_V8HI_type_node) = tdecl;
14262 tdecl = add_builtin_type ("__vector signed short", V8HI_type_node);
14263 TYPE_NAME (V8HI_type_node) = tdecl;
14265 tdecl = add_builtin_type ("__vector __bool short", bool_V8HI_type_node);
14266 TYPE_NAME (bool_V8HI_type_node) = tdecl;
14268 tdecl = add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node);
14269 TYPE_NAME (unsigned_V4SI_type_node) = tdecl;
14271 tdecl = add_builtin_type ("__vector signed int", V4SI_type_node);
14272 TYPE_NAME (V4SI_type_node) = tdecl;
14274 tdecl = add_builtin_type ("__vector __bool int", bool_V4SI_type_node);
14275 TYPE_NAME (bool_V4SI_type_node) = tdecl;
14277 tdecl = add_builtin_type ("__vector float", V4SF_type_node);
14278 TYPE_NAME (V4SF_type_node) = tdecl;
14280 tdecl = add_builtin_type ("__vector __pixel", pixel_V8HI_type_node);
14281 TYPE_NAME (pixel_V8HI_type_node) = tdecl;
14283 tdecl = add_builtin_type ("__vector double", V2DF_type_node);
14284 TYPE_NAME (V2DF_type_node) = tdecl;
14286 if (TARGET_POWERPC64)
14288 tdecl = add_builtin_type ("__vector long", V2DI_type_node);
14289 TYPE_NAME (V2DI_type_node) = tdecl;
14291 tdecl = add_builtin_type ("__vector unsigned long",
14292 unsigned_V2DI_type_node);
14293 TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
14295 tdecl = add_builtin_type ("__vector __bool long", bool_V2DI_type_node);
14296 TYPE_NAME (bool_V2DI_type_node) = tdecl;
14300 tdecl = add_builtin_type ("__vector long long", V2DI_type_node);
14301 TYPE_NAME (V2DI_type_node) = tdecl;
14303 tdecl = add_builtin_type ("__vector unsigned long long",
14304 unsigned_V2DI_type_node);
14305 TYPE_NAME (unsigned_V2DI_type_node) = tdecl;
14307 tdecl = add_builtin_type ("__vector __bool long long",
14308 bool_V2DI_type_node);
14309 TYPE_NAME (bool_V2DI_type_node) = tdecl;
14312 if (V1TI_type_node)
14314 tdecl = add_builtin_type ("__vector __int128", V1TI_type_node);
14315 TYPE_NAME (V1TI_type_node) = tdecl;
14317 tdecl = add_builtin_type ("__vector unsigned __int128",
14318 unsigned_V1TI_type_node);
14319 TYPE_NAME (unsigned_V1TI_type_node) = tdecl;
14322 /* Paired and SPE builtins are only available if you build a compiler with
14323 the appropriate options, so only create those builtins with the
14324 appropriate compiler option. Create Altivec and VSX builtins on machines
14325 with at least the general purpose extensions (970 and newer) to allow the
14326 use of the target attribute. */
14327 if (TARGET_PAIRED_FLOAT)
14328 paired_init_builtins ();
14330 spe_init_builtins ();
14331 if (TARGET_EXTRA_BUILTINS)
14332 altivec_init_builtins ();
14334 htm_init_builtins ();
14336 if (TARGET_EXTRA_BUILTINS || TARGET_SPE || TARGET_PAIRED_FLOAT)
14337 rs6000_common_init_builtins ();
14339 ftype = builtin_function_type (DFmode, DFmode, DFmode, VOIDmode,
14340 RS6000_BUILTIN_RECIP, "__builtin_recipdiv");
14341 def_builtin ("__builtin_recipdiv", ftype, RS6000_BUILTIN_RECIP);
14343 ftype = builtin_function_type (SFmode, SFmode, SFmode, VOIDmode,
14344 RS6000_BUILTIN_RECIPF, "__builtin_recipdivf");
14345 def_builtin ("__builtin_recipdivf", ftype, RS6000_BUILTIN_RECIPF);
14347 ftype = builtin_function_type (DFmode, DFmode, VOIDmode, VOIDmode,
14348 RS6000_BUILTIN_RSQRT, "__builtin_rsqrt");
14349 def_builtin ("__builtin_rsqrt", ftype, RS6000_BUILTIN_RSQRT);
14351 ftype = builtin_function_type (SFmode, SFmode, VOIDmode, VOIDmode,
14352 RS6000_BUILTIN_RSQRTF, "__builtin_rsqrtf");
14353 def_builtin ("__builtin_rsqrtf", ftype, RS6000_BUILTIN_RSQRTF);
14355 mode = (TARGET_64BIT) ? DImode : SImode;
14356 ftype = builtin_function_type (mode, mode, mode, VOIDmode,
14357 POWER7_BUILTIN_BPERMD, "__builtin_bpermd");
14358 def_builtin ("__builtin_bpermd", ftype, POWER7_BUILTIN_BPERMD);
14360 ftype = build_function_type_list (unsigned_intDI_type_node,
14362 def_builtin ("__builtin_ppc_get_timebase", ftype, RS6000_BUILTIN_GET_TB);
14365 ftype = build_function_type_list (unsigned_intDI_type_node,
14368 ftype = build_function_type_list (unsigned_intSI_type_node,
14370 def_builtin ("__builtin_ppc_mftb", ftype, RS6000_BUILTIN_MFTB);
14372 ftype = build_function_type_list (double_type_node, NULL_TREE);
14373 def_builtin ("__builtin_mffs", ftype, RS6000_BUILTIN_MFFS);
14375 ftype = build_function_type_list (void_type_node,
14376 intSI_type_node, double_type_node,
14378 def_builtin ("__builtin_mtfsf", ftype, RS6000_BUILTIN_MTFSF);
14381 /* AIX libm provides clog as __clog. */
14382 if ((tdecl = builtin_decl_explicit (BUILT_IN_CLOG)) != NULL_TREE)
14383 set_user_assembler_name (tdecl, "__clog");
14386 #ifdef SUBTARGET_INIT_BUILTINS
14387 SUBTARGET_INIT_BUILTINS;
14391 /* Returns the rs6000 builtin decl for CODE. */
14394 rs6000_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
14396 HOST_WIDE_INT fnmask;
14398 if (code >= RS6000_BUILTIN_COUNT)
14399 return error_mark_node;
14401 fnmask = rs6000_builtin_info[code].mask;
14402 if ((fnmask & rs6000_builtin_mask) != fnmask)
14404 rs6000_invalid_builtin ((enum rs6000_builtins)code);
14405 return error_mark_node;
14408 return rs6000_builtin_decls[code];
14412 spe_init_builtins (void)
14414 tree puint_type_node = build_pointer_type (unsigned_type_node);
14415 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
14416 const struct builtin_description *d;
14419 tree v2si_ftype_4_v2si
14420 = build_function_type_list (opaque_V2SI_type_node,
14421 opaque_V2SI_type_node,
14422 opaque_V2SI_type_node,
14423 opaque_V2SI_type_node,
14424 opaque_V2SI_type_node,
14427 tree v2sf_ftype_4_v2sf
14428 = build_function_type_list (opaque_V2SF_type_node,
14429 opaque_V2SF_type_node,
14430 opaque_V2SF_type_node,
14431 opaque_V2SF_type_node,
14432 opaque_V2SF_type_node,
14435 tree int_ftype_int_v2si_v2si
14436 = build_function_type_list (integer_type_node,
14438 opaque_V2SI_type_node,
14439 opaque_V2SI_type_node,
14442 tree int_ftype_int_v2sf_v2sf
14443 = build_function_type_list (integer_type_node,
14445 opaque_V2SF_type_node,
14446 opaque_V2SF_type_node,
14449 tree void_ftype_v2si_puint_int
14450 = build_function_type_list (void_type_node,
14451 opaque_V2SI_type_node,
14456 tree void_ftype_v2si_puint_char
14457 = build_function_type_list (void_type_node,
14458 opaque_V2SI_type_node,
14463 tree void_ftype_v2si_pv2si_int
14464 = build_function_type_list (void_type_node,
14465 opaque_V2SI_type_node,
14466 opaque_p_V2SI_type_node,
14470 tree void_ftype_v2si_pv2si_char
14471 = build_function_type_list (void_type_node,
14472 opaque_V2SI_type_node,
14473 opaque_p_V2SI_type_node,
14477 tree void_ftype_int
14478 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
14480 tree int_ftype_void
14481 = build_function_type_list (integer_type_node, NULL_TREE);
14483 tree v2si_ftype_pv2si_int
14484 = build_function_type_list (opaque_V2SI_type_node,
14485 opaque_p_V2SI_type_node,
14489 tree v2si_ftype_puint_int
14490 = build_function_type_list (opaque_V2SI_type_node,
14495 tree v2si_ftype_pushort_int
14496 = build_function_type_list (opaque_V2SI_type_node,
14501 tree v2si_ftype_signed_char
14502 = build_function_type_list (opaque_V2SI_type_node,
14503 signed_char_type_node,
14506 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node);
14508 /* Initialize irregular SPE builtins. */
14510 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
14511 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
14512 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
14513 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
14514 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
14515 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
14516 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
14517 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
14518 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
14519 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
14520 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
14521 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
14522 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
14523 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
14524 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
14525 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
14526 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
14527 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
14530 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
14531 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
14532 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
14533 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
14534 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
14535 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
14536 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
14537 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
14538 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
14539 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
14540 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
14541 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
14542 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
14543 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
14544 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
14545 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
14546 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
14547 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
14548 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
14549 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
14550 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
14551 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
14554 d = bdesc_spe_predicates;
14555 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
14559 switch (insn_data[d->icode].operand[1].mode)
14562 type = int_ftype_int_v2si_v2si;
14565 type = int_ftype_int_v2sf_v2sf;
14568 gcc_unreachable ();
14571 def_builtin (d->name, type, d->code);
14574 /* Evsel predicates. */
14575 d = bdesc_spe_evsel;
14576 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
14580 switch (insn_data[d->icode].operand[1].mode)
14583 type = v2si_ftype_4_v2si;
14586 type = v2sf_ftype_4_v2sf;
14589 gcc_unreachable ();
14592 def_builtin (d->name, type, d->code);
14597 paired_init_builtins (void)
14599 const struct builtin_description *d;
14602 tree int_ftype_int_v2sf_v2sf
14603 = build_function_type_list (integer_type_node,
14608 tree pcfloat_type_node =
14609 build_pointer_type (build_qualified_type
14610 (float_type_node, TYPE_QUAL_CONST));
14612 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
14613 long_integer_type_node,
14616 tree void_ftype_v2sf_long_pcfloat =
14617 build_function_type_list (void_type_node,
14619 long_integer_type_node,
14624 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat,
14625 PAIRED_BUILTIN_LX);
14628 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
14629 PAIRED_BUILTIN_STX);
14632 d = bdesc_paired_preds;
14633 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
14637 if (TARGET_DEBUG_BUILTIN)
14638 fprintf (stderr, "paired pred #%d, insn = %s [%d], mode = %s\n",
14639 (int)i, get_insn_name (d->icode), (int)d->icode,
14640 GET_MODE_NAME (insn_data[d->icode].operand[1].mode));
14642 switch (insn_data[d->icode].operand[1].mode)
14645 type = int_ftype_int_v2sf_v2sf;
14648 gcc_unreachable ();
14651 def_builtin (d->name, type, d->code);
14656 altivec_init_builtins (void)
14658 const struct builtin_description *d;
14663 tree pvoid_type_node = build_pointer_type (void_type_node);
14665 tree pcvoid_type_node
14666 = build_pointer_type (build_qualified_type (void_type_node,
14669 tree int_ftype_opaque
14670 = build_function_type_list (integer_type_node,
14671 opaque_V4SI_type_node, NULL_TREE);
14672 tree opaque_ftype_opaque
14673 = build_function_type_list (integer_type_node, NULL_TREE);
14674 tree opaque_ftype_opaque_int
14675 = build_function_type_list (opaque_V4SI_type_node,
14676 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
14677 tree opaque_ftype_opaque_opaque_int
14678 = build_function_type_list (opaque_V4SI_type_node,
14679 opaque_V4SI_type_node, opaque_V4SI_type_node,
14680 integer_type_node, NULL_TREE);
14681 tree int_ftype_int_opaque_opaque
14682 = build_function_type_list (integer_type_node,
14683 integer_type_node, opaque_V4SI_type_node,
14684 opaque_V4SI_type_node, NULL_TREE);
14685 tree int_ftype_int_v4si_v4si
14686 = build_function_type_list (integer_type_node,
14687 integer_type_node, V4SI_type_node,
14688 V4SI_type_node, NULL_TREE);
14689 tree int_ftype_int_v2di_v2di
14690 = build_function_type_list (integer_type_node,
14691 integer_type_node, V2DI_type_node,
14692 V2DI_type_node, NULL_TREE);
14693 tree void_ftype_v4si
14694 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
14695 tree v8hi_ftype_void
14696 = build_function_type_list (V8HI_type_node, NULL_TREE);
14697 tree void_ftype_void
14698 = build_function_type_list (void_type_node, NULL_TREE);
14699 tree void_ftype_int
14700 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
14702 tree opaque_ftype_long_pcvoid
14703 = build_function_type_list (opaque_V4SI_type_node,
14704 long_integer_type_node, pcvoid_type_node,
14706 tree v16qi_ftype_long_pcvoid
14707 = build_function_type_list (V16QI_type_node,
14708 long_integer_type_node, pcvoid_type_node,
14710 tree v8hi_ftype_long_pcvoid
14711 = build_function_type_list (V8HI_type_node,
14712 long_integer_type_node, pcvoid_type_node,
14714 tree v4si_ftype_long_pcvoid
14715 = build_function_type_list (V4SI_type_node,
14716 long_integer_type_node, pcvoid_type_node,
14718 tree v4sf_ftype_long_pcvoid
14719 = build_function_type_list (V4SF_type_node,
14720 long_integer_type_node, pcvoid_type_node,
14722 tree v2df_ftype_long_pcvoid
14723 = build_function_type_list (V2DF_type_node,
14724 long_integer_type_node, pcvoid_type_node,
14726 tree v2di_ftype_long_pcvoid
14727 = build_function_type_list (V2DI_type_node,
14728 long_integer_type_node, pcvoid_type_node,
14731 tree void_ftype_opaque_long_pvoid
14732 = build_function_type_list (void_type_node,
14733 opaque_V4SI_type_node, long_integer_type_node,
14734 pvoid_type_node, NULL_TREE);
14735 tree void_ftype_v4si_long_pvoid
14736 = build_function_type_list (void_type_node,
14737 V4SI_type_node, long_integer_type_node,
14738 pvoid_type_node, NULL_TREE);
14739 tree void_ftype_v16qi_long_pvoid
14740 = build_function_type_list (void_type_node,
14741 V16QI_type_node, long_integer_type_node,
14742 pvoid_type_node, NULL_TREE);
14743 tree void_ftype_v8hi_long_pvoid
14744 = build_function_type_list (void_type_node,
14745 V8HI_type_node, long_integer_type_node,
14746 pvoid_type_node, NULL_TREE);
14747 tree void_ftype_v4sf_long_pvoid
14748 = build_function_type_list (void_type_node,
14749 V4SF_type_node, long_integer_type_node,
14750 pvoid_type_node, NULL_TREE);
14751 tree void_ftype_v2df_long_pvoid
14752 = build_function_type_list (void_type_node,
14753 V2DF_type_node, long_integer_type_node,
14754 pvoid_type_node, NULL_TREE);
14755 tree void_ftype_v2di_long_pvoid
14756 = build_function_type_list (void_type_node,
14757 V2DI_type_node, long_integer_type_node,
14758 pvoid_type_node, NULL_TREE);
14759 tree int_ftype_int_v8hi_v8hi
14760 = build_function_type_list (integer_type_node,
14761 integer_type_node, V8HI_type_node,
14762 V8HI_type_node, NULL_TREE);
14763 tree int_ftype_int_v16qi_v16qi
14764 = build_function_type_list (integer_type_node,
14765 integer_type_node, V16QI_type_node,
14766 V16QI_type_node, NULL_TREE);
14767 tree int_ftype_int_v4sf_v4sf
14768 = build_function_type_list (integer_type_node,
14769 integer_type_node, V4SF_type_node,
14770 V4SF_type_node, NULL_TREE);
14771 tree int_ftype_int_v2df_v2df
14772 = build_function_type_list (integer_type_node,
14773 integer_type_node, V2DF_type_node,
14774 V2DF_type_node, NULL_TREE);
14775 tree v2di_ftype_v2di
14776 = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
14777 tree v4si_ftype_v4si
14778 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
14779 tree v8hi_ftype_v8hi
14780 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
14781 tree v16qi_ftype_v16qi
14782 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
14783 tree v4sf_ftype_v4sf
14784 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
14785 tree v2df_ftype_v2df
14786 = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE);
14787 tree void_ftype_pcvoid_int_int
14788 = build_function_type_list (void_type_node,
14789 pcvoid_type_node, integer_type_node,
14790 integer_type_node, NULL_TREE);
14792 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
14793 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
14794 def_builtin ("__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
14795 def_builtin ("__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
14796 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
14797 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
14798 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
14799 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
14800 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
14801 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
14802 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid,
14803 ALTIVEC_BUILTIN_LVXL_V2DF);
14804 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid,
14805 ALTIVEC_BUILTIN_LVXL_V2DI);
14806 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid,
14807 ALTIVEC_BUILTIN_LVXL_V4SF);
14808 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid,
14809 ALTIVEC_BUILTIN_LVXL_V4SI);
14810 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid,
14811 ALTIVEC_BUILTIN_LVXL_V8HI);
14812 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid,
14813 ALTIVEC_BUILTIN_LVXL_V16QI);
14814 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
14815 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid,
14816 ALTIVEC_BUILTIN_LVX_V2DF);
14817 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid,
14818 ALTIVEC_BUILTIN_LVX_V2DI);
14819 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid,
14820 ALTIVEC_BUILTIN_LVX_V4SF);
14821 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid,
14822 ALTIVEC_BUILTIN_LVX_V4SI);
14823 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid,
14824 ALTIVEC_BUILTIN_LVX_V8HI);
14825 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid,
14826 ALTIVEC_BUILTIN_LVX_V16QI);
14827 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
14828 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid,
14829 ALTIVEC_BUILTIN_STVX_V2DF);
14830 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid,
14831 ALTIVEC_BUILTIN_STVX_V2DI);
14832 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid,
14833 ALTIVEC_BUILTIN_STVX_V4SF);
14834 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid,
14835 ALTIVEC_BUILTIN_STVX_V4SI);
14836 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid,
14837 ALTIVEC_BUILTIN_STVX_V8HI);
14838 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid,
14839 ALTIVEC_BUILTIN_STVX_V16QI);
14840 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
14841 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
14842 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid,
14843 ALTIVEC_BUILTIN_STVXL_V2DF);
14844 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid,
14845 ALTIVEC_BUILTIN_STVXL_V2DI);
14846 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid,
14847 ALTIVEC_BUILTIN_STVXL_V4SF);
14848 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid,
14849 ALTIVEC_BUILTIN_STVXL_V4SI);
14850 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid,
14851 ALTIVEC_BUILTIN_STVXL_V8HI);
14852 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid,
14853 ALTIVEC_BUILTIN_STVXL_V16QI);
14854 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
14855 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
14856 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
14857 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
14858 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
14859 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
14860 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
14861 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
14862 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
14863 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
14864 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
14865 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
14866 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
14867 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
14868 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
14869 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
14871 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid,
14872 VSX_BUILTIN_LXVD2X_V2DF);
14873 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid,
14874 VSX_BUILTIN_LXVD2X_V2DI);
14875 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid,
14876 VSX_BUILTIN_LXVW4X_V4SF);
14877 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid,
14878 VSX_BUILTIN_LXVW4X_V4SI);
14879 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid,
14880 VSX_BUILTIN_LXVW4X_V8HI);
14881 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid,
14882 VSX_BUILTIN_LXVW4X_V16QI);
14883 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid,
14884 VSX_BUILTIN_STXVD2X_V2DF);
14885 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid,
14886 VSX_BUILTIN_STXVD2X_V2DI);
14887 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid,
14888 VSX_BUILTIN_STXVW4X_V4SF);
14889 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid,
14890 VSX_BUILTIN_STXVW4X_V4SI);
14891 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid,
14892 VSX_BUILTIN_STXVW4X_V8HI);
14893 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid,
14894 VSX_BUILTIN_STXVW4X_V16QI);
14895 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid,
14896 VSX_BUILTIN_VEC_LD);
14897 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid,
14898 VSX_BUILTIN_VEC_ST);
14900 def_builtin ("__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
14901 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_SPLATS);
14902 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque, ALTIVEC_BUILTIN_VEC_PROMOTE);
14904 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
14905 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
14906 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_EXTRACT);
14907 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_INSERT);
14908 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
14909 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
14910 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
14911 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
14912 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
14913 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
14914 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
14915 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
14917 /* Cell builtins. */
14918 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLX);
14919 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVLXL);
14920 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRX);
14921 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVRXL);
14923 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLX);
14924 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVLXL);
14925 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRX);
14926 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVRXL);
14928 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLX);
14929 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVLXL);
14930 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRX);
14931 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVRXL);
14933 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLX);
14934 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVLXL);
14935 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
14936 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
14938 /* Add the DST variants. */
14940 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
14941 def_builtin (d->name, void_ftype_pcvoid_int_int, d->code);
14943 /* Initialize the predicates. */
14944 d = bdesc_altivec_preds;
14945 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, d++)
14947 machine_mode mode1;
14950 if (rs6000_overloaded_builtin_p (d->code))
14953 mode1 = insn_data[d->icode].operand[1].mode;
14958 type = int_ftype_int_opaque_opaque;
14961 type = int_ftype_int_v2di_v2di;
14964 type = int_ftype_int_v4si_v4si;
14967 type = int_ftype_int_v8hi_v8hi;
14970 type = int_ftype_int_v16qi_v16qi;
14973 type = int_ftype_int_v4sf_v4sf;
14976 type = int_ftype_int_v2df_v2df;
14979 gcc_unreachable ();
14982 def_builtin (d->name, type, d->code);
14985 /* Initialize the abs* operators. */
14987 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
14989 machine_mode mode0;
14992 mode0 = insn_data[d->icode].operand[0].mode;
14997 type = v2di_ftype_v2di;
15000 type = v4si_ftype_v4si;
15003 type = v8hi_ftype_v8hi;
15006 type = v16qi_ftype_v16qi;
15009 type = v4sf_ftype_v4sf;
15012 type = v2df_ftype_v2df;
15015 gcc_unreachable ();
15018 def_builtin (d->name, type, d->code);
15021 /* Initialize target builtin that implements
15022 targetm.vectorize.builtin_mask_for_load. */
15024 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
15025 v16qi_ftype_long_pcvoid,
15026 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
15027 BUILT_IN_MD, NULL, NULL_TREE);
15028 TREE_READONLY (decl) = 1;
15029 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
15030 altivec_builtin_mask_for_load = decl;
15032 /* Access to the vec_init patterns. */
15033 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
15034 integer_type_node, integer_type_node,
15035 integer_type_node, NULL_TREE);
15036 def_builtin ("__builtin_vec_init_v4si", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SI);
15038 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
15039 short_integer_type_node,
15040 short_integer_type_node,
15041 short_integer_type_node,
15042 short_integer_type_node,
15043 short_integer_type_node,
15044 short_integer_type_node,
15045 short_integer_type_node, NULL_TREE);
15046 def_builtin ("__builtin_vec_init_v8hi", ftype, ALTIVEC_BUILTIN_VEC_INIT_V8HI);
15048 ftype = build_function_type_list (V16QI_type_node, char_type_node,
15049 char_type_node, char_type_node,
15050 char_type_node, char_type_node,
15051 char_type_node, char_type_node,
15052 char_type_node, char_type_node,
15053 char_type_node, char_type_node,
15054 char_type_node, char_type_node,
15055 char_type_node, char_type_node,
15056 char_type_node, NULL_TREE);
15057 def_builtin ("__builtin_vec_init_v16qi", ftype,
15058 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
15060 ftype = build_function_type_list (V4SF_type_node, float_type_node,
15061 float_type_node, float_type_node,
15062 float_type_node, NULL_TREE);
15063 def_builtin ("__builtin_vec_init_v4sf", ftype, ALTIVEC_BUILTIN_VEC_INIT_V4SF);
15065 /* VSX builtins. */
15066 ftype = build_function_type_list (V2DF_type_node, double_type_node,
15067 double_type_node, NULL_TREE);
15068 def_builtin ("__builtin_vec_init_v2df", ftype, VSX_BUILTIN_VEC_INIT_V2DF);
15070 ftype = build_function_type_list (V2DI_type_node, intDI_type_node,
15071 intDI_type_node, NULL_TREE);
15072 def_builtin ("__builtin_vec_init_v2di", ftype, VSX_BUILTIN_VEC_INIT_V2DI);
15074 /* Access to the vec_set patterns. */
15075 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
15077 integer_type_node, NULL_TREE);
15078 def_builtin ("__builtin_vec_set_v4si", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SI);
15080 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
15082 integer_type_node, NULL_TREE);
15083 def_builtin ("__builtin_vec_set_v8hi", ftype, ALTIVEC_BUILTIN_VEC_SET_V8HI);
15085 ftype = build_function_type_list (V16QI_type_node, V16QI_type_node,
15087 integer_type_node, NULL_TREE);
15088 def_builtin ("__builtin_vec_set_v16qi", ftype, ALTIVEC_BUILTIN_VEC_SET_V16QI);
15090 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
15092 integer_type_node, NULL_TREE);
15093 def_builtin ("__builtin_vec_set_v4sf", ftype, ALTIVEC_BUILTIN_VEC_SET_V4SF);
15095 ftype = build_function_type_list (V2DF_type_node, V2DF_type_node,
15097 integer_type_node, NULL_TREE);
15098 def_builtin ("__builtin_vec_set_v2df", ftype, VSX_BUILTIN_VEC_SET_V2DF);
15100 ftype = build_function_type_list (V2DI_type_node, V2DI_type_node,
15102 integer_type_node, NULL_TREE);
15103 def_builtin ("__builtin_vec_set_v2di", ftype, VSX_BUILTIN_VEC_SET_V2DI);
15105 /* Access to the vec_extract patterns. */
15106 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
15107 integer_type_node, NULL_TREE);
15108 def_builtin ("__builtin_vec_ext_v4si", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SI);
15110 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
15111 integer_type_node, NULL_TREE);
15112 def_builtin ("__builtin_vec_ext_v8hi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V8HI);
15114 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
15115 integer_type_node, NULL_TREE);
15116 def_builtin ("__builtin_vec_ext_v16qi", ftype, ALTIVEC_BUILTIN_VEC_EXT_V16QI);
15118 ftype = build_function_type_list (float_type_node, V4SF_type_node,
15119 integer_type_node, NULL_TREE);
15120 def_builtin ("__builtin_vec_ext_v4sf", ftype, ALTIVEC_BUILTIN_VEC_EXT_V4SF);
15122 ftype = build_function_type_list (double_type_node, V2DF_type_node,
15123 integer_type_node, NULL_TREE);
15124 def_builtin ("__builtin_vec_ext_v2df", ftype, VSX_BUILTIN_VEC_EXT_V2DF);
15126 ftype = build_function_type_list (intDI_type_node, V2DI_type_node,
15127 integer_type_node, NULL_TREE);
15128 def_builtin ("__builtin_vec_ext_v2di", ftype, VSX_BUILTIN_VEC_EXT_V2DI);
15131 if (V1TI_type_node)
15133 tree v1ti_ftype_long_pcvoid
15134 = build_function_type_list (V1TI_type_node,
15135 long_integer_type_node, pcvoid_type_node,
15137 tree void_ftype_v1ti_long_pvoid
15138 = build_function_type_list (void_type_node,
15139 V1TI_type_node, long_integer_type_node,
15140 pvoid_type_node, NULL_TREE);
15141 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid,
15142 VSX_BUILTIN_LXVD2X_V1TI);
15143 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid,
15144 VSX_BUILTIN_STXVD2X_V1TI);
15145 ftype = build_function_type_list (V1TI_type_node, intTI_type_node,
15146 NULL_TREE, NULL_TREE);
15147 def_builtin ("__builtin_vec_init_v1ti", ftype, VSX_BUILTIN_VEC_INIT_V1TI);
15148 ftype = build_function_type_list (V1TI_type_node, V1TI_type_node,
15150 integer_type_node, NULL_TREE);
15151 def_builtin ("__builtin_vec_set_v1ti", ftype, VSX_BUILTIN_VEC_SET_V1TI);
15152 ftype = build_function_type_list (intTI_type_node, V1TI_type_node,
15153 integer_type_node, NULL_TREE);
15154 def_builtin ("__builtin_vec_ext_v1ti", ftype, VSX_BUILTIN_VEC_EXT_V1TI);
15160 htm_init_builtins (void)
15162 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
15163 const struct builtin_description *d;
15167 for (i = 0; i < ARRAY_SIZE (bdesc_htm); i++, d++)
15169 tree op[MAX_HTM_OPERANDS], type;
15170 HOST_WIDE_INT mask = d->mask;
15171 unsigned attr = rs6000_builtin_info[d->code].attr;
15172 bool void_func = (attr & RS6000_BTC_VOID);
15173 int attr_args = (attr & RS6000_BTC_TYPE_MASK);
15175 tree argtype = (attr & RS6000_BTC_SPR) ? long_unsigned_type_node
15176 : unsigned_type_node;
15178 if ((mask & builtin_mask) != mask)
15180 if (TARGET_DEBUG_BUILTIN)
15181 fprintf (stderr, "htm_builtin, skip binary %s\n", d->name);
15187 if (TARGET_DEBUG_BUILTIN)
15188 fprintf (stderr, "htm_builtin, bdesc_htm[%ld] no name\n",
15189 (long unsigned) i);
15193 op[nopnds++] = (void_func) ? void_type_node : argtype;
15195 if (attr_args == RS6000_BTC_UNARY)
15196 op[nopnds++] = argtype;
15197 else if (attr_args == RS6000_BTC_BINARY)
15199 op[nopnds++] = argtype;
15200 op[nopnds++] = argtype;
15202 else if (attr_args == RS6000_BTC_TERNARY)
15204 op[nopnds++] = argtype;
15205 op[nopnds++] = argtype;
15206 op[nopnds++] = argtype;
15212 type = build_function_type_list (op[0], NULL_TREE);
15215 type = build_function_type_list (op[0], op[1], NULL_TREE);
15218 type = build_function_type_list (op[0], op[1], op[2], NULL_TREE);
15221 type = build_function_type_list (op[0], op[1], op[2], op[3],
15225 gcc_unreachable ();
15228 def_builtin (d->name, type, d->code);
15232 /* Hash function for builtin functions with up to 3 arguments and a return
15235 builtin_hasher::hash (builtin_hash_struct *bh)
15240 for (i = 0; i < 4; i++)
15242 ret = (ret * (unsigned)MAX_MACHINE_MODE) + ((unsigned)bh->mode[i]);
15243 ret = (ret * 2) + bh->uns_p[i];
15249 /* Compare builtin hash entries H1 and H2 for equivalence. */
15251 builtin_hasher::equal (builtin_hash_struct *p1, builtin_hash_struct *p2)
15253 return ((p1->mode[0] == p2->mode[0])
15254 && (p1->mode[1] == p2->mode[1])
15255 && (p1->mode[2] == p2->mode[2])
15256 && (p1->mode[3] == p2->mode[3])
15257 && (p1->uns_p[0] == p2->uns_p[0])
15258 && (p1->uns_p[1] == p2->uns_p[1])
15259 && (p1->uns_p[2] == p2->uns_p[2])
15260 && (p1->uns_p[3] == p2->uns_p[3]));
15263 /* Map types for builtin functions with an explicit return type and up to 3
15264 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
15265 of the argument. */
15267 builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
15268 machine_mode mode_arg1, machine_mode mode_arg2,
15269 enum rs6000_builtins builtin, const char *name)
15271 struct builtin_hash_struct h;
15272 struct builtin_hash_struct *h2;
15275 tree ret_type = NULL_TREE;
15276 tree arg_type[3] = { NULL_TREE, NULL_TREE, NULL_TREE };
15278 /* Create builtin_hash_table. */
15279 if (builtin_hash_table == NULL)
15280 builtin_hash_table = hash_table<builtin_hasher>::create_ggc (1500);
15282 h.type = NULL_TREE;
15283 h.mode[0] = mode_ret;
15284 h.mode[1] = mode_arg0;
15285 h.mode[2] = mode_arg1;
15286 h.mode[3] = mode_arg2;
15292 /* If the builtin is a type that produces unsigned results or takes unsigned
15293 arguments, and it is returned as a decl for the vectorizer (such as
15294 widening multiplies, permute), make sure the arguments and return value
15295 are type correct. */
15298 /* unsigned 1 argument functions. */
15299 case CRYPTO_BUILTIN_VSBOX:
15300 case P8V_BUILTIN_VGBBD:
15301 case MISC_BUILTIN_CDTBCD:
15302 case MISC_BUILTIN_CBCDTD:
15307 /* unsigned 2 argument functions. */
15308 case ALTIVEC_BUILTIN_VMULEUB_UNS:
15309 case ALTIVEC_BUILTIN_VMULEUH_UNS:
15310 case ALTIVEC_BUILTIN_VMULOUB_UNS:
15311 case ALTIVEC_BUILTIN_VMULOUH_UNS:
15312 case CRYPTO_BUILTIN_VCIPHER:
15313 case CRYPTO_BUILTIN_VCIPHERLAST:
15314 case CRYPTO_BUILTIN_VNCIPHER:
15315 case CRYPTO_BUILTIN_VNCIPHERLAST:
15316 case CRYPTO_BUILTIN_VPMSUMB:
15317 case CRYPTO_BUILTIN_VPMSUMH:
15318 case CRYPTO_BUILTIN_VPMSUMW:
15319 case CRYPTO_BUILTIN_VPMSUMD:
15320 case CRYPTO_BUILTIN_VPMSUM:
15321 case MISC_BUILTIN_ADDG6S:
15322 case MISC_BUILTIN_DIVWEU:
15323 case MISC_BUILTIN_DIVWEUO:
15324 case MISC_BUILTIN_DIVDEU:
15325 case MISC_BUILTIN_DIVDEUO:
15331 /* unsigned 3 argument functions. */
15332 case ALTIVEC_BUILTIN_VPERM_16QI_UNS:
15333 case ALTIVEC_BUILTIN_VPERM_8HI_UNS:
15334 case ALTIVEC_BUILTIN_VPERM_4SI_UNS:
15335 case ALTIVEC_BUILTIN_VPERM_2DI_UNS:
15336 case ALTIVEC_BUILTIN_VSEL_16QI_UNS:
15337 case ALTIVEC_BUILTIN_VSEL_8HI_UNS:
15338 case ALTIVEC_BUILTIN_VSEL_4SI_UNS:
15339 case ALTIVEC_BUILTIN_VSEL_2DI_UNS:
15340 case VSX_BUILTIN_VPERM_16QI_UNS:
15341 case VSX_BUILTIN_VPERM_8HI_UNS:
15342 case VSX_BUILTIN_VPERM_4SI_UNS:
15343 case VSX_BUILTIN_VPERM_2DI_UNS:
15344 case VSX_BUILTIN_XXSEL_16QI_UNS:
15345 case VSX_BUILTIN_XXSEL_8HI_UNS:
15346 case VSX_BUILTIN_XXSEL_4SI_UNS:
15347 case VSX_BUILTIN_XXSEL_2DI_UNS:
15348 case CRYPTO_BUILTIN_VPERMXOR:
15349 case CRYPTO_BUILTIN_VPERMXOR_V2DI:
15350 case CRYPTO_BUILTIN_VPERMXOR_V4SI:
15351 case CRYPTO_BUILTIN_VPERMXOR_V8HI:
15352 case CRYPTO_BUILTIN_VPERMXOR_V16QI:
15353 case CRYPTO_BUILTIN_VSHASIGMAW:
15354 case CRYPTO_BUILTIN_VSHASIGMAD:
15355 case CRYPTO_BUILTIN_VSHASIGMA:
15362 /* signed permute functions with unsigned char mask. */
15363 case ALTIVEC_BUILTIN_VPERM_16QI:
15364 case ALTIVEC_BUILTIN_VPERM_8HI:
15365 case ALTIVEC_BUILTIN_VPERM_4SI:
15366 case ALTIVEC_BUILTIN_VPERM_4SF:
15367 case ALTIVEC_BUILTIN_VPERM_2DI:
15368 case ALTIVEC_BUILTIN_VPERM_2DF:
15369 case VSX_BUILTIN_VPERM_16QI:
15370 case VSX_BUILTIN_VPERM_8HI:
15371 case VSX_BUILTIN_VPERM_4SI:
15372 case VSX_BUILTIN_VPERM_4SF:
15373 case VSX_BUILTIN_VPERM_2DI:
15374 case VSX_BUILTIN_VPERM_2DF:
15378 /* unsigned args, signed return. */
15379 case VSX_BUILTIN_XVCVUXDDP_UNS:
15380 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF:
15384 /* signed args, unsigned return. */
15385 case VSX_BUILTIN_XVCVDPUXDS_UNS:
15386 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI:
15387 case MISC_BUILTIN_UNPACK_TD:
15388 case MISC_BUILTIN_UNPACK_V1TI:
15392 /* unsigned arguments for 128-bit pack instructions. */
15393 case MISC_BUILTIN_PACK_TD:
15394 case MISC_BUILTIN_PACK_V1TI:
15403 /* Figure out how many args are present. */
15404 while (num_args > 0 && h.mode[num_args] == VOIDmode)
15408 fatal_error ("internal error: builtin function %s had no type", name);
15410 ret_type = builtin_mode_to_type[h.mode[0]][h.uns_p[0]];
15411 if (!ret_type && h.uns_p[0])
15412 ret_type = builtin_mode_to_type[h.mode[0]][0];
15415 fatal_error ("internal error: builtin function %s had an unexpected "
15416 "return type %s", name, GET_MODE_NAME (h.mode[0]));
15418 for (i = 0; i < (int) ARRAY_SIZE (arg_type); i++)
15419 arg_type[i] = NULL_TREE;
15421 for (i = 0; i < num_args; i++)
15423 int m = (int) h.mode[i+1];
15424 int uns_p = h.uns_p[i+1];
15426 arg_type[i] = builtin_mode_to_type[m][uns_p];
15427 if (!arg_type[i] && uns_p)
15428 arg_type[i] = builtin_mode_to_type[m][0];
15431 fatal_error ("internal error: builtin function %s, argument %d "
15432 "had unexpected argument type %s", name, i,
15433 GET_MODE_NAME (m));
15436 builtin_hash_struct **found = builtin_hash_table->find_slot (&h, INSERT);
15437 if (*found == NULL)
15439 h2 = ggc_alloc<builtin_hash_struct> ();
15443 h2->type = build_function_type_list (ret_type, arg_type[0], arg_type[1],
15444 arg_type[2], NULL_TREE);
15447 return (*found)->type;
15451 rs6000_common_init_builtins (void)
15453 const struct builtin_description *d;
15456 tree opaque_ftype_opaque = NULL_TREE;
15457 tree opaque_ftype_opaque_opaque = NULL_TREE;
15458 tree opaque_ftype_opaque_opaque_opaque = NULL_TREE;
15459 tree v2si_ftype_qi = NULL_TREE;
15460 tree v2si_ftype_v2si_qi = NULL_TREE;
15461 tree v2si_ftype_int_qi = NULL_TREE;
15462 HOST_WIDE_INT builtin_mask = rs6000_builtin_mask;
15464 if (!TARGET_PAIRED_FLOAT)
15466 builtin_mode_to_type[V2SImode][0] = opaque_V2SI_type_node;
15467 builtin_mode_to_type[V2SFmode][0] = opaque_V2SF_type_node;
15470 /* Paired and SPE builtins are only available if you build a compiler with
15471 the appropriate options, so only create those builtins with the
15472 appropriate compiler option. Create Altivec and VSX builtins on machines
15473 with at least the general purpose extensions (970 and newer) to allow the
15474 use of the target attribute.. */
15476 if (TARGET_EXTRA_BUILTINS)
15477 builtin_mask |= RS6000_BTM_COMMON;
15479 /* Add the ternary operators. */
15481 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
15484 HOST_WIDE_INT mask = d->mask;
15486 if ((mask & builtin_mask) != mask)
15488 if (TARGET_DEBUG_BUILTIN)
15489 fprintf (stderr, "rs6000_builtin, skip ternary %s\n", d->name);
15493 if (rs6000_overloaded_builtin_p (d->code))
15495 if (! (type = opaque_ftype_opaque_opaque_opaque))
15496 type = opaque_ftype_opaque_opaque_opaque
15497 = build_function_type_list (opaque_V4SI_type_node,
15498 opaque_V4SI_type_node,
15499 opaque_V4SI_type_node,
15500 opaque_V4SI_type_node,
15505 enum insn_code icode = d->icode;
15508 if (TARGET_DEBUG_BUILTIN)
15509 fprintf (stderr, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
15515 if (icode == CODE_FOR_nothing)
15517 if (TARGET_DEBUG_BUILTIN)
15518 fprintf (stderr, "rs6000_builtin, skip ternary %s (no code)\n",
15524 type = builtin_function_type (insn_data[icode].operand[0].mode,
15525 insn_data[icode].operand[1].mode,
15526 insn_data[icode].operand[2].mode,
15527 insn_data[icode].operand[3].mode,
15531 def_builtin (d->name, type, d->code);
15534 /* Add the binary operators. */
15536 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
15538 machine_mode mode0, mode1, mode2;
15540 HOST_WIDE_INT mask = d->mask;
15542 if ((mask & builtin_mask) != mask)
15544 if (TARGET_DEBUG_BUILTIN)
15545 fprintf (stderr, "rs6000_builtin, skip binary %s\n", d->name);
15549 if (rs6000_overloaded_builtin_p (d->code))
15551 if (! (type = opaque_ftype_opaque_opaque))
15552 type = opaque_ftype_opaque_opaque
15553 = build_function_type_list (opaque_V4SI_type_node,
15554 opaque_V4SI_type_node,
15555 opaque_V4SI_type_node,
15560 enum insn_code icode = d->icode;
15563 if (TARGET_DEBUG_BUILTIN)
15564 fprintf (stderr, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
15570 if (icode == CODE_FOR_nothing)
15572 if (TARGET_DEBUG_BUILTIN)
15573 fprintf (stderr, "rs6000_builtin, skip binary %s (no code)\n",
15579 mode0 = insn_data[icode].operand[0].mode;
15580 mode1 = insn_data[icode].operand[1].mode;
15581 mode2 = insn_data[icode].operand[2].mode;
15583 if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
15585 if (! (type = v2si_ftype_v2si_qi))
15586 type = v2si_ftype_v2si_qi
15587 = build_function_type_list (opaque_V2SI_type_node,
15588 opaque_V2SI_type_node,
15593 else if (mode0 == V2SImode && GET_MODE_CLASS (mode1) == MODE_INT
15594 && mode2 == QImode)
15596 if (! (type = v2si_ftype_int_qi))
15597 type = v2si_ftype_int_qi
15598 = build_function_type_list (opaque_V2SI_type_node,
15605 type = builtin_function_type (mode0, mode1, mode2, VOIDmode,
15609 def_builtin (d->name, type, d->code);
15612 /* Add the simple unary operators. */
15614 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
15616 machine_mode mode0, mode1;
15618 HOST_WIDE_INT mask = d->mask;
15620 if ((mask & builtin_mask) != mask)
15622 if (TARGET_DEBUG_BUILTIN)
15623 fprintf (stderr, "rs6000_builtin, skip unary %s\n", d->name);
15627 if (rs6000_overloaded_builtin_p (d->code))
15629 if (! (type = opaque_ftype_opaque))
15630 type = opaque_ftype_opaque
15631 = build_function_type_list (opaque_V4SI_type_node,
15632 opaque_V4SI_type_node,
15637 enum insn_code icode = d->icode;
15640 if (TARGET_DEBUG_BUILTIN)
15641 fprintf (stderr, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
15647 if (icode == CODE_FOR_nothing)
15649 if (TARGET_DEBUG_BUILTIN)
15650 fprintf (stderr, "rs6000_builtin, skip unary %s (no code)\n",
15656 mode0 = insn_data[icode].operand[0].mode;
15657 mode1 = insn_data[icode].operand[1].mode;
15659 if (mode0 == V2SImode && mode1 == QImode)
15661 if (! (type = v2si_ftype_qi))
15662 type = v2si_ftype_qi
15663 = build_function_type_list (opaque_V2SI_type_node,
15669 type = builtin_function_type (mode0, mode1, VOIDmode, VOIDmode,
15673 def_builtin (d->name, type, d->code);
15678 rs6000_init_libfuncs (void)
15680 if (!TARGET_IEEEQUAD)
15681 /* AIX/Darwin/64-bit Linux quad floating point routines. */
15682 if (!TARGET_XL_COMPAT)
15684 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
15685 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
15686 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
15687 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
15689 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
15691 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
15692 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
15693 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
15694 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
15695 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
15696 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
15697 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
15699 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
15700 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
15701 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
15702 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
15703 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
15704 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
15705 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
15706 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
15709 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
15710 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
15714 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
15715 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
15716 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
15717 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
15721 /* 32-bit SVR4 quad floating point routines. */
15723 set_optab_libfunc (add_optab, TFmode, "_q_add");
15724 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
15725 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
15726 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
15727 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
15728 if (TARGET_PPC_GPOPT)
15729 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
15731 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
15732 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
15733 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
15734 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
15735 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
15736 set_optab_libfunc (le_optab, TFmode, "_q_fle");
15738 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
15739 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
15740 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
15741 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
15742 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
15743 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
15744 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
15745 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
15750 /* Expand a block clear operation, and return 1 if successful. Return 0
15751 if we should let the compiler generate normal code.
15753 operands[0] is the destination
15754 operands[1] is the length
15755 operands[3] is the alignment */
15758 expand_block_clear (rtx operands[])
15760 rtx orig_dest = operands[0];
15761 rtx bytes_rtx = operands[1];
15762 rtx align_rtx = operands[3];
15763 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
15764 HOST_WIDE_INT align;
15765 HOST_WIDE_INT bytes;
15770 /* If this is not a fixed size move, just call memcpy */
15774 /* This must be a fixed size alignment */
15775 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
15776 align = INTVAL (align_rtx) * BITS_PER_UNIT;
15778 /* Anything to clear? */
15779 bytes = INTVAL (bytes_rtx);
15783 /* Use the builtin memset after a point, to avoid huge code bloat.
15784 When optimize_size, avoid any significant code bloat; calling
15785 memset is about 4 instructions, so allow for one instruction to
15786 load zero and three to do clearing. */
15787 if (TARGET_ALTIVEC && align >= 128)
15789 else if (TARGET_POWERPC64 && (align >= 64 || !STRICT_ALIGNMENT))
15791 else if (TARGET_SPE && align >= 64)
15796 if (optimize_size && bytes > 3 * clear_step)
15798 if (! optimize_size && bytes > 8 * clear_step)
15801 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
15803 machine_mode mode = BLKmode;
15806 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
15811 else if (bytes >= 8 && TARGET_SPE && align >= 64)
15816 else if (bytes >= 8 && TARGET_POWERPC64
15817 && (align >= 64 || !STRICT_ALIGNMENT))
15821 if (offset == 0 && align < 64)
15825 /* If the address form is reg+offset with offset not a
15826 multiple of four, reload into reg indirect form here
15827 rather than waiting for reload. This way we get one
15828 reload, not one per store. */
15829 addr = XEXP (orig_dest, 0);
15830 if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
15831 && GET_CODE (XEXP (addr, 1)) == CONST_INT
15832 && (INTVAL (XEXP (addr, 1)) & 3) != 0)
15834 addr = copy_addr_to_reg (addr);
15835 orig_dest = replace_equiv_address (orig_dest, addr);
15839 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
15840 { /* move 4 bytes */
15844 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
15845 { /* move 2 bytes */
15849 else /* move 1 byte at a time */
15855 dest = adjust_address (orig_dest, mode, offset);
15857 emit_move_insn (dest, CONST0_RTX (mode));
15864 /* Expand a block move operation, and return 1 if successful. Return 0
15865 if we should let the compiler generate normal code.
15867 operands[0] is the destination
15868 operands[1] is the source
15869 operands[2] is the length
15870 operands[3] is the alignment */
15872 #define MAX_MOVE_REG 4
15875 expand_block_move (rtx operands[])
15877 rtx orig_dest = operands[0];
15878 rtx orig_src = operands[1];
15879 rtx bytes_rtx = operands[2];
15880 rtx align_rtx = operands[3];
15881 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
15886 rtx stores[MAX_MOVE_REG];
15889 /* If this is not a fixed size move, just call memcpy */
15893 /* This must be a fixed size alignment */
15894 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
15895 align = INTVAL (align_rtx) * BITS_PER_UNIT;
15897 /* Anything to move? */
15898 bytes = INTVAL (bytes_rtx);
15902 if (bytes > rs6000_block_move_inline_limit)
15905 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
15908 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
15909 rtx (*mov) (rtx, rtx);
15911 machine_mode mode = BLKmode;
15914 /* Altivec first, since it will be faster than a string move
15915 when it applies, and usually not significantly larger. */
15916 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
15920 gen_func.mov = gen_movv4si;
15922 else if (TARGET_SPE && bytes >= 8 && align >= 64)
15926 gen_func.mov = gen_movv2si;
15928 else if (TARGET_STRING
15929 && bytes > 24 /* move up to 32 bytes at a time */
15935 && ! fixed_regs[10]
15936 && ! fixed_regs[11]
15937 && ! fixed_regs[12])
15939 move_bytes = (bytes > 32) ? 32 : bytes;
15940 gen_func.movmemsi = gen_movmemsi_8reg;
15942 else if (TARGET_STRING
15943 && bytes > 16 /* move up to 24 bytes at a time */
15949 && ! fixed_regs[10])
15951 move_bytes = (bytes > 24) ? 24 : bytes;
15952 gen_func.movmemsi = gen_movmemsi_6reg;
15954 else if (TARGET_STRING
15955 && bytes > 8 /* move up to 16 bytes at a time */
15959 && ! fixed_regs[8])
15961 move_bytes = (bytes > 16) ? 16 : bytes;
15962 gen_func.movmemsi = gen_movmemsi_4reg;
15964 else if (bytes >= 8 && TARGET_POWERPC64
15965 && (align >= 64 || !STRICT_ALIGNMENT))
15969 gen_func.mov = gen_movdi;
15970 if (offset == 0 && align < 64)
15974 /* If the address form is reg+offset with offset not a
15975 multiple of four, reload into reg indirect form here
15976 rather than waiting for reload. This way we get one
15977 reload, not one per load and/or store. */
15978 addr = XEXP (orig_dest, 0);
15979 if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
15980 && GET_CODE (XEXP (addr, 1)) == CONST_INT
15981 && (INTVAL (XEXP (addr, 1)) & 3) != 0)
15983 addr = copy_addr_to_reg (addr);
15984 orig_dest = replace_equiv_address (orig_dest, addr);
15986 addr = XEXP (orig_src, 0);
15987 if ((GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM)
15988 && GET_CODE (XEXP (addr, 1)) == CONST_INT
15989 && (INTVAL (XEXP (addr, 1)) & 3) != 0)
15991 addr = copy_addr_to_reg (addr);
15992 orig_src = replace_equiv_address (orig_src, addr);
15996 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
15997 { /* move up to 8 bytes at a time */
15998 move_bytes = (bytes > 8) ? 8 : bytes;
15999 gen_func.movmemsi = gen_movmemsi_2reg;
16001 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
16002 { /* move 4 bytes */
16005 gen_func.mov = gen_movsi;
16007 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
16008 { /* move 2 bytes */
16011 gen_func.mov = gen_movhi;
16013 else if (TARGET_STRING && bytes > 1)
16014 { /* move up to 4 bytes at a time */
16015 move_bytes = (bytes > 4) ? 4 : bytes;
16016 gen_func.movmemsi = gen_movmemsi_1reg;
16018 else /* move 1 byte at a time */
16022 gen_func.mov = gen_movqi;
16025 src = adjust_address (orig_src, mode, offset);
16026 dest = adjust_address (orig_dest, mode, offset);
16028 if (mode != BLKmode)
16030 rtx tmp_reg = gen_reg_rtx (mode);
16032 emit_insn ((*gen_func.mov) (tmp_reg, src));
16033 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
16036 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
16039 for (i = 0; i < num_reg; i++)
16040 emit_insn (stores[i]);
16044 if (mode == BLKmode)
16046 /* Move the address into scratch registers. The movmemsi
16047 patterns require zero offset. */
16048 if (!REG_P (XEXP (src, 0)))
16050 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
16051 src = replace_equiv_address (src, src_reg);
16053 set_mem_size (src, move_bytes);
16055 if (!REG_P (XEXP (dest, 0)))
16057 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
16058 dest = replace_equiv_address (dest, dest_reg);
16060 set_mem_size (dest, move_bytes);
16062 emit_insn ((*gen_func.movmemsi) (dest, src,
16063 GEN_INT (move_bytes & 31),
16072 /* Return a string to perform a load_multiple operation.
16073 operands[0] is the vector.
16074 operands[1] is the source address.
16075 operands[2] is the first destination register. */
16078 rs6000_output_load_multiple (rtx operands[3])
16080 /* We have to handle the case where the pseudo used to contain the address
16081 is assigned to one of the output registers. */
16083 int words = XVECLEN (operands[0], 0);
16086 if (XVECLEN (operands[0], 0) == 1)
16087 return "lwz %2,0(%1)";
16089 for (i = 0; i < words; i++)
16090 if (refers_to_regno_p (REGNO (operands[2]) + i,
16091 REGNO (operands[2]) + i + 1, operands[1], 0))
16095 xop[0] = GEN_INT (4 * (words-1));
16096 xop[1] = operands[1];
16097 xop[2] = operands[2];
16098 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop);
16103 xop[0] = GEN_INT (4 * (words-1));
16104 xop[1] = operands[1];
16105 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
16106 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop);
16111 for (j = 0; j < words; j++)
16114 xop[0] = GEN_INT (j * 4);
16115 xop[1] = operands[1];
16116 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
16117 output_asm_insn ("lwz %2,%0(%1)", xop);
16119 xop[0] = GEN_INT (i * 4);
16120 xop[1] = operands[1];
16121 output_asm_insn ("lwz %1,%0(%1)", xop);
16126 return "lswi %2,%1,%N0";
16130 /* A validation routine: say whether CODE, a condition code, and MODE
16131 match. The other alternatives either don't make sense or should
16132 never be generated. */
16135 validate_condition_mode (enum rtx_code code, machine_mode mode)
16137 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
16138 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
16139 && GET_MODE_CLASS (mode) == MODE_CC);
16141 /* These don't make sense. */
16142 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
16143 || mode != CCUNSmode);
16145 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
16146 || mode == CCUNSmode);
16148 gcc_assert (mode == CCFPmode
16149 || (code != ORDERED && code != UNORDERED
16150 && code != UNEQ && code != LTGT
16151 && code != UNGT && code != UNLT
16152 && code != UNGE && code != UNLE));
16154 /* These should never be generated except for
16155 flag_finite_math_only. */
16156 gcc_assert (mode != CCFPmode
16157 || flag_finite_math_only
16158 || (code != LE && code != GE
16159 && code != UNEQ && code != LTGT
16160 && code != UNGT && code != UNLT));
16162 /* These are invalid; the information is not there. */
16163 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
16167 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
16168 mask required to convert the result of a rotate insn into a shift
16169 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
16172 includes_lshift_p (rtx shiftop, rtx andop)
16174 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
16176 shift_mask <<= INTVAL (shiftop);
16178 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
16181 /* Similar, but for right shift. */
16184 includes_rshift_p (rtx shiftop, rtx andop)
16186 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
16188 shift_mask >>= INTVAL (shiftop);
16190 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
16193 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
16194 to perform a left shift. It must have exactly SHIFTOP least
16195 significant 0's, then one or more 1's, then zero or more 0's. */
16198 includes_rldic_lshift_p (rtx shiftop, rtx andop)
16200 if (GET_CODE (andop) == CONST_INT)
16202 unsigned HOST_WIDE_INT c, lsb, shift_mask;
16204 c = INTVAL (andop);
16205 if (c == 0 || c == HOST_WIDE_INT_M1U)
16208 shift_mask = HOST_WIDE_INT_M1U;
16209 shift_mask <<= INTVAL (shiftop);
16211 /* Find the least significant one bit. */
16214 /* It must coincide with the LSB of the shift mask. */
16215 if (-lsb != shift_mask)
16218 /* Invert to look for the next transition (if any). */
16221 /* Remove the low group of ones (originally low group of zeros). */
16224 /* Again find the lsb, and check we have all 1's above. */
16232 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
16233 to perform a left shift. It must have SHIFTOP or more least
16234 significant 0's, with the remainder of the word 1's. */
16237 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
16239 if (GET_CODE (andop) == CONST_INT)
16241 unsigned HOST_WIDE_INT c, lsb, shift_mask;
16243 shift_mask = HOST_WIDE_INT_M1U;
16244 shift_mask <<= INTVAL (shiftop);
16245 c = INTVAL (andop);
16247 /* Find the least significant one bit. */
16250 /* It must be covered by the shift mask.
16251 This test also rejects c == 0. */
16252 if ((lsb & shift_mask) == 0)
16255 /* Check we have all 1's above the transition, and reject all 1's. */
16256 return c == -lsb && lsb != 1;
16262 /* Return 1 if operands will generate a valid arguments to rlwimi
16263 instruction for insert with right shift in 64-bit mode. The mask may
16264 not start on the first bit or stop on the last bit because wrap-around
16265 effects of instruction do not correspond to semantics of RTL insn. */
16268 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
16270 if (INTVAL (startop) > 32
16271 && INTVAL (startop) < 64
16272 && INTVAL (sizeop) > 1
16273 && INTVAL (sizeop) + INTVAL (startop) < 64
16274 && INTVAL (shiftop) > 0
16275 && INTVAL (sizeop) + INTVAL (shiftop) < 32
16276 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
16282 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
16283 for lfq and stfq insns iff the registers are hard registers. */
16286 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
16288 /* We might have been passed a SUBREG. */
16289 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
16292 /* We might have been passed non floating point registers. */
16293 if (!FP_REGNO_P (REGNO (reg1))
16294 || !FP_REGNO_P (REGNO (reg2)))
16297 return (REGNO (reg1) == REGNO (reg2) - 1);
16300 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
16301 addr1 and addr2 must be in consecutive memory locations
16302 (addr2 == addr1 + 8). */
16305 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
16308 unsigned int reg1, reg2;
16309 int offset1, offset2;
16311 /* The mems cannot be volatile. */
16312 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
16315 addr1 = XEXP (mem1, 0);
16316 addr2 = XEXP (mem2, 0);
16318 /* Extract an offset (if used) from the first addr. */
16319 if (GET_CODE (addr1) == PLUS)
16321 /* If not a REG, return zero. */
16322 if (GET_CODE (XEXP (addr1, 0)) != REG)
16326 reg1 = REGNO (XEXP (addr1, 0));
16327 /* The offset must be constant! */
16328 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
16330 offset1 = INTVAL (XEXP (addr1, 1));
16333 else if (GET_CODE (addr1) != REG)
16337 reg1 = REGNO (addr1);
16338 /* This was a simple (mem (reg)) expression. Offset is 0. */
16342 /* And now for the second addr. */
16343 if (GET_CODE (addr2) == PLUS)
16345 /* If not a REG, return zero. */
16346 if (GET_CODE (XEXP (addr2, 0)) != REG)
16350 reg2 = REGNO (XEXP (addr2, 0));
16351 /* The offset must be constant. */
16352 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
16354 offset2 = INTVAL (XEXP (addr2, 1));
16357 else if (GET_CODE (addr2) != REG)
16361 reg2 = REGNO (addr2);
16362 /* This was a simple (mem (reg)) expression. Offset is 0. */
16366 /* Both of these must have the same base register. */
16370 /* The offset for the second addr must be 8 more than the first addr. */
16371 if (offset2 != offset1 + 8)
16374 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
16381 rs6000_secondary_memory_needed_rtx (machine_mode mode)
16383 static bool eliminated = false;
16386 if (mode != SDmode || TARGET_NO_SDMODE_STACK)
16387 ret = assign_stack_local (mode, GET_MODE_SIZE (mode), 0);
16390 rtx mem = cfun->machine->sdmode_stack_slot;
16391 gcc_assert (mem != NULL_RTX);
16395 mem = eliminate_regs (mem, VOIDmode, NULL_RTX);
16396 cfun->machine->sdmode_stack_slot = mem;
16402 if (TARGET_DEBUG_ADDR)
16404 fprintf (stderr, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
16405 GET_MODE_NAME (mode));
16407 fprintf (stderr, "\tNULL_RTX\n");
16415 /* Return the mode to be used for memory when a secondary memory
16416 location is needed. For SDmode values we need to use DDmode, in
16417 all other cases we can use the same mode. */
16419 rs6000_secondary_memory_needed_mode (machine_mode mode)
16421 if (lra_in_progress && mode == SDmode)
16427 rs6000_check_sdmode (tree *tp, int *walk_subtrees, void *data ATTRIBUTE_UNUSED)
16429 /* Don't walk into types. */
16430 if (*tp == NULL_TREE || *tp == error_mark_node || TYPE_P (*tp))
16432 *walk_subtrees = 0;
16436 switch (TREE_CODE (*tp))
16445 case VIEW_CONVERT_EXPR:
16446 if (TYPE_MODE (TREE_TYPE (*tp)) == SDmode)
16456 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
16457 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
16458 only work on the traditional altivec registers, note if an altivec register
16461 static enum rs6000_reg_type
16462 register_to_reg_type (rtx reg, bool *is_altivec)
16464 HOST_WIDE_INT regno;
16465 enum reg_class rclass;
16467 if (GET_CODE (reg) == SUBREG)
16468 reg = SUBREG_REG (reg);
16471 return NO_REG_TYPE;
16473 regno = REGNO (reg);
16474 if (regno >= FIRST_PSEUDO_REGISTER)
16476 if (!lra_in_progress && !reload_in_progress && !reload_completed)
16477 return PSEUDO_REG_TYPE;
16479 regno = true_regnum (reg);
16480 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER)
16481 return PSEUDO_REG_TYPE;
16484 gcc_assert (regno >= 0);
16486 if (is_altivec && ALTIVEC_REGNO_P (regno))
16487 *is_altivec = true;
16489 rclass = rs6000_regno_regclass[regno];
16490 return reg_class_to_reg_type[(int)rclass];
16493 /* Helper function to return the cost of adding a TOC entry address. */
16496 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask)
16500 if (TARGET_CMODEL != CMODEL_SMALL)
16501 ret = ((addr_mask & RELOAD_REG_OFFSET) == 0) ? 1 : 2;
16504 ret = (TARGET_MINIMAL_TOC) ? 6 : 3;
16509 /* Helper function for rs6000_secondary_reload to determine whether the memory
16510 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
16511 needs reloading. Return negative if the memory is not handled by the memory
16512 helper functions and to try a different reload method, 0 if no additional
16513 instructions are need, and positive to give the extra cost for the
16517 rs6000_secondary_reload_memory (rtx addr,
16518 enum reg_class rclass,
16519 enum machine_mode mode)
16521 int extra_cost = 0;
16522 rtx reg, and_arg, plus_arg0, plus_arg1;
16523 addr_mask_type addr_mask;
16524 const char *type = NULL;
16525 const char *fail_msg = NULL;
16527 if (GPR_REG_CLASS_P (rclass))
16528 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
16530 else if (rclass == FLOAT_REGS)
16531 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
16533 else if (rclass == ALTIVEC_REGS)
16534 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
16536 /* For the combined VSX_REGS, turn off Altivec AND -16. */
16537 else if (rclass == VSX_REGS)
16538 addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX]
16539 & ~RELOAD_REG_AND_M16);
16543 if (TARGET_DEBUG_ADDR)
16545 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
16546 "class is not GPR, FPR, VMX\n",
16547 GET_MODE_NAME (mode), reg_class_names[rclass]);
16552 /* If the register isn't valid in this register class, just return now. */
16553 if ((addr_mask & RELOAD_REG_VALID) == 0)
16555 if (TARGET_DEBUG_ADDR)
16557 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
16558 "not valid in class\n",
16559 GET_MODE_NAME (mode), reg_class_names[rclass]);
16564 switch (GET_CODE (addr))
16566 /* Does the register class supports auto update forms for this mode? We
16567 don't need a scratch register, since the powerpc only supports
16568 PRE_INC, PRE_DEC, and PRE_MODIFY. */
16571 reg = XEXP (addr, 0);
16572 if (!base_reg_operand (addr, GET_MODE (reg)))
16574 fail_msg = "no base register #1";
16578 else if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
16586 reg = XEXP (addr, 0);
16587 plus_arg1 = XEXP (addr, 1);
16588 if (!base_reg_operand (reg, GET_MODE (reg))
16589 || GET_CODE (plus_arg1) != PLUS
16590 || !rtx_equal_p (reg, XEXP (plus_arg1, 0)))
16592 fail_msg = "bad PRE_MODIFY";
16596 else if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
16603 /* Do we need to simulate AND -16 to clear the bottom address bits used
16604 in VMX load/stores? Only allow the AND for vector sizes. */
16606 and_arg = XEXP (addr, 0);
16607 if (GET_MODE_SIZE (mode) != 16
16608 || GET_CODE (XEXP (addr, 1)) != CONST_INT
16609 || INTVAL (XEXP (addr, 1)) != -16)
16611 fail_msg = "bad Altivec AND #1";
16615 if (rclass != ALTIVEC_REGS)
16617 if (legitimate_indirect_address_p (and_arg, false))
16620 else if (legitimate_indexed_address_p (and_arg, false))
16625 fail_msg = "bad Altivec AND #2";
16633 /* If this is an indirect address, make sure it is a base register. */
16636 if (!legitimate_indirect_address_p (addr, false))
16643 /* If this is an indexed address, make sure the register class can handle
16644 indexed addresses for this mode. */
16646 plus_arg0 = XEXP (addr, 0);
16647 plus_arg1 = XEXP (addr, 1);
16649 /* (plus (plus (reg) (constant)) (constant)) is generated during
16650 push_reload processing, so handle it now. */
16651 if (GET_CODE (plus_arg0) == PLUS && CONST_INT_P (plus_arg1))
16653 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
16660 /* (plus (plus (reg) (constant)) (reg)) is also generated during
16661 push_reload processing, so handle it now. */
16662 else if (GET_CODE (plus_arg0) == PLUS && REG_P (plus_arg1))
16664 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
16667 type = "indexed #2";
16671 else if (!base_reg_operand (plus_arg0, GET_MODE (plus_arg0)))
16673 fail_msg = "no base register #2";
16677 else if (int_reg_operand (plus_arg1, GET_MODE (plus_arg1)))
16679 if ((addr_mask & RELOAD_REG_INDEXED) == 0
16680 || !legitimate_indexed_address_p (addr, false))
16687 /* Make sure the register class can handle offset addresses. */
16688 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
16690 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
16699 fail_msg = "bad PLUS";
16706 if (!legitimate_lo_sum_address_p (mode, addr, false))
16708 fail_msg = "bad LO_SUM";
16712 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
16719 /* Static addresses need to create a TOC entry. */
16724 extra_cost = rs6000_secondary_reload_toc_costs (addr_mask);
16727 /* TOC references look like offsetable memory. */
16729 if (TARGET_CMODEL == CMODEL_SMALL || XINT (addr, 1) != UNSPEC_TOCREL)
16731 fail_msg = "bad UNSPEC";
16735 else if ((addr_mask & RELOAD_REG_OFFSET) == 0)
16738 type = "toc reference";
16744 fail_msg = "bad address";
16749 if (TARGET_DEBUG_ADDR /* && extra_cost != 0 */)
16751 if (extra_cost < 0)
16753 "rs6000_secondary_reload_memory error: mode = %s, "
16754 "class = %s, addr_mask = '%s', %s\n",
16755 GET_MODE_NAME (mode),
16756 reg_class_names[rclass],
16757 rs6000_debug_addr_mask (addr_mask, false),
16758 (fail_msg != NULL) ? fail_msg : "<bad address>");
16762 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
16763 "addr_mask = '%s', extra cost = %d, %s\n",
16764 GET_MODE_NAME (mode),
16765 reg_class_names[rclass],
16766 rs6000_debug_addr_mask (addr_mask, false),
16768 (type) ? type : "<none>");
16776 /* Helper function for rs6000_secondary_reload to return true if a move to a
16777 different register classe is really a simple move. */
16780 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type,
16781 enum rs6000_reg_type from_type,
16786 /* Add support for various direct moves available. In this function, we only
16787 look at cases where we don't need any extra registers, and one or more
16788 simple move insns are issued. At present, 32-bit integers are not allowed
16789 in FPR/VSX registers. Single precision binary floating is not a simple
16790 move because we need to convert to the single precision memory layout.
16791 The 4-byte SDmode can be moved. */
16792 size = GET_MODE_SIZE (mode);
16793 if (TARGET_DIRECT_MOVE
16794 && ((mode == SDmode) || (TARGET_POWERPC64 && size == 8))
16795 && ((to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
16796 || (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)))
16799 else if (TARGET_MFPGPR && TARGET_POWERPC64 && size == 8
16800 && ((to_type == GPR_REG_TYPE && from_type == FPR_REG_TYPE)
16801 || (to_type == FPR_REG_TYPE && from_type == GPR_REG_TYPE)))
16804 else if ((size == 4 || (TARGET_POWERPC64 && size == 8))
16805 && ((to_type == GPR_REG_TYPE && from_type == SPR_REG_TYPE)
16806 || (to_type == SPR_REG_TYPE && from_type == GPR_REG_TYPE)))
16812 /* Power8 helper function for rs6000_secondary_reload, handle all of the
16813 special direct moves that involve allocating an extra register, return the
16814 insn code of the helper function if there is such a function or
16815 CODE_FOR_nothing if not. */
16818 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type,
16819 enum rs6000_reg_type from_type,
16821 secondary_reload_info *sri,
16825 enum insn_code icode = CODE_FOR_nothing;
16827 int size = GET_MODE_SIZE (mode);
16829 if (TARGET_POWERPC64)
16833 /* Handle moving 128-bit values from GPRs to VSX point registers on
16834 power8 when running in 64-bit mode using XXPERMDI to glue the two
16835 64-bit values back together. */
16836 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
16838 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
16839 icode = reg_addr[mode].reload_vsx_gpr;
16842 /* Handle moving 128-bit values from VSX point registers to GPRs on
16843 power8 when running in 64-bit mode using XXPERMDI to get access to the
16844 bottom 64-bit value. */
16845 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
16847 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
16848 icode = reg_addr[mode].reload_gpr_vsx;
16852 else if (mode == SFmode)
16854 if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
16856 cost = 3; /* xscvdpspn, mfvsrd, and. */
16857 icode = reg_addr[mode].reload_gpr_vsx;
16860 else if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
16862 cost = 2; /* mtvsrz, xscvspdpn. */
16863 icode = reg_addr[mode].reload_vsx_gpr;
16868 if (TARGET_POWERPC64 && size == 16)
16870 /* Handle moving 128-bit values from GPRs to VSX point registers on
16871 power8 when running in 64-bit mode using XXPERMDI to glue the two
16872 64-bit values back together. */
16873 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE)
16875 cost = 3; /* 2 mtvsrd's, 1 xxpermdi. */
16876 icode = reg_addr[mode].reload_vsx_gpr;
16879 /* Handle moving 128-bit values from VSX point registers to GPRs on
16880 power8 when running in 64-bit mode using XXPERMDI to get access to the
16881 bottom 64-bit value. */
16882 else if (to_type == GPR_REG_TYPE && from_type == VSX_REG_TYPE)
16884 cost = 3; /* 2 mfvsrd's, 1 xxpermdi. */
16885 icode = reg_addr[mode].reload_gpr_vsx;
16889 else if (!TARGET_POWERPC64 && size == 8)
16891 /* Handle moving 64-bit values from GPRs to floating point registers on
16892 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
16893 values back together. Altivec register classes must be handled
16894 specially since a different instruction is used, and the secondary
16895 reload support requires a single instruction class in the scratch
16896 register constraint. However, right now TFmode is not allowed in
16897 Altivec registers, so the pattern will never match. */
16898 if (to_type == VSX_REG_TYPE && from_type == GPR_REG_TYPE && !altivec_p)
16900 cost = 3; /* 2 mtvsrwz's, 1 fmrgow. */
16901 icode = reg_addr[mode].reload_fpr_gpr;
16905 if (icode != CODE_FOR_nothing)
16910 sri->icode = icode;
16911 sri->extra_cost = cost;
16918 /* Return whether a move between two register classes can be done either
16919 directly (simple move) or via a pattern that uses a single extra temporary
16920 (using power8's direct move in this case. */
16923 rs6000_secondary_reload_move (enum rs6000_reg_type to_type,
16924 enum rs6000_reg_type from_type,
16926 secondary_reload_info *sri,
16929 /* Fall back to load/store reloads if either type is not a register. */
16930 if (to_type == NO_REG_TYPE || from_type == NO_REG_TYPE)
16933 /* If we haven't allocated registers yet, assume the move can be done for the
16934 standard register types. */
16935 if ((to_type == PSEUDO_REG_TYPE && from_type == PSEUDO_REG_TYPE)
16936 || (to_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (from_type))
16937 || (from_type == PSEUDO_REG_TYPE && IS_STD_REG_TYPE (to_type)))
16940 /* Moves to the same set of registers is a simple move for non-specialized
16942 if (to_type == from_type && IS_STD_REG_TYPE (to_type))
16945 /* Check whether a simple move can be done directly. */
16946 if (rs6000_secondary_reload_simple_move (to_type, from_type, mode))
16950 sri->icode = CODE_FOR_nothing;
16951 sri->extra_cost = 0;
16956 /* Now check if we can do it in a few steps. */
16957 return rs6000_secondary_reload_direct_move (to_type, from_type, mode, sri,
16961 /* Inform reload about cases where moving X with a mode MODE to a register in
16962 RCLASS requires an extra scratch or immediate register. Return the class
16963 needed for the immediate register.
16965 For VSX and Altivec, we may need a register to convert sp+offset into
16968 For misaligned 64-bit gpr loads and stores we need a register to
16969 convert an offset address to indirect. */
16972 rs6000_secondary_reload (bool in_p,
16974 reg_class_t rclass_i,
16976 secondary_reload_info *sri)
16978 enum reg_class rclass = (enum reg_class) rclass_i;
16979 reg_class_t ret = ALL_REGS;
16980 enum insn_code icode;
16981 bool default_p = false;
16982 bool done_p = false;
16984 /* Allow subreg of memory before/during reload. */
16985 bool memory_p = (MEM_P (x)
16986 || (!reload_completed && GET_CODE (x) == SUBREG
16987 && MEM_P (SUBREG_REG (x))));
16989 sri->icode = CODE_FOR_nothing;
16990 sri->extra_cost = 0;
16992 ? reg_addr[mode].reload_load
16993 : reg_addr[mode].reload_store);
16995 if (REG_P (x) || register_operand (x, mode))
16997 enum rs6000_reg_type to_type = reg_class_to_reg_type[(int)rclass];
16998 bool altivec_p = (rclass == ALTIVEC_REGS);
16999 enum rs6000_reg_type from_type = register_to_reg_type (x, &altivec_p);
17003 enum rs6000_reg_type exchange = to_type;
17004 to_type = from_type;
17005 from_type = exchange;
17008 /* Can we do a direct move of some sort? */
17009 if (rs6000_secondary_reload_move (to_type, from_type, mode, sri,
17012 icode = (enum insn_code)sri->icode;
17019 /* Make sure 0.0 is not reloaded or forced into memory. */
17020 if (x == CONST0_RTX (mode) && VSX_REG_CLASS_P (rclass))
17027 /* If this is a scalar floating point value and we want to load it into the
17028 traditional Altivec registers, do it via a move via a traditional floating
17029 point register. Also make sure that non-zero constants use a FPR. */
17030 if (!done_p && reg_addr[mode].scalar_in_vmx_p
17031 && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
17032 && (memory_p || (GET_CODE (x) == CONST_DOUBLE)))
17039 /* Handle reload of load/stores if we have reload helper functions. */
17040 if (!done_p && icode != CODE_FOR_nothing && memory_p)
17042 int extra_cost = rs6000_secondary_reload_memory (XEXP (x, 0), rclass,
17045 if (extra_cost >= 0)
17049 if (extra_cost > 0)
17051 sri->extra_cost = extra_cost;
17052 sri->icode = icode;
17057 /* Handle unaligned loads and stores of integer registers. */
17058 if (!done_p && TARGET_POWERPC64
17059 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
17061 && GET_MODE_SIZE (GET_MODE (x)) >= UNITS_PER_WORD)
17063 rtx addr = XEXP (x, 0);
17064 rtx off = address_offset (addr);
17066 if (off != NULL_RTX)
17068 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
17069 unsigned HOST_WIDE_INT offset = INTVAL (off);
17071 /* We need a secondary reload when our legitimate_address_p
17072 says the address is good (as otherwise the entire address
17073 will be reloaded), and the offset is not a multiple of
17074 four or we have an address wrap. Address wrap will only
17075 occur for LO_SUMs since legitimate_offset_address_p
17076 rejects addresses for 16-byte mems that will wrap. */
17077 if (GET_CODE (addr) == LO_SUM
17078 ? (1 /* legitimate_address_p allows any offset for lo_sum */
17079 && ((offset & 3) != 0
17080 || ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra))
17081 : (offset + 0x8000 < 0x10000 - extra /* legitimate_address_p */
17082 && (offset & 3) != 0))
17085 sri->icode = CODE_FOR_reload_di_load;
17087 sri->icode = CODE_FOR_reload_di_store;
17088 sri->extra_cost = 2;
17099 if (!done_p && !TARGET_POWERPC64
17100 && reg_class_to_reg_type[(int)rclass] == GPR_REG_TYPE
17102 && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
17104 rtx addr = XEXP (x, 0);
17105 rtx off = address_offset (addr);
17107 if (off != NULL_RTX)
17109 unsigned int extra = GET_MODE_SIZE (GET_MODE (x)) - UNITS_PER_WORD;
17110 unsigned HOST_WIDE_INT offset = INTVAL (off);
17112 /* We need a secondary reload when our legitimate_address_p
17113 says the address is good (as otherwise the entire address
17114 will be reloaded), and we have a wrap.
17116 legitimate_lo_sum_address_p allows LO_SUM addresses to
17117 have any offset so test for wrap in the low 16 bits.
17119 legitimate_offset_address_p checks for the range
17120 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
17121 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
17122 [0x7ff4,0x7fff] respectively, so test for the
17123 intersection of these ranges, [0x7ffc,0x7fff] and
17124 [0x7ff4,0x7ff7] respectively.
17126 Note that the address we see here may have been
17127 manipulated by legitimize_reload_address. */
17128 if (GET_CODE (addr) == LO_SUM
17129 ? ((offset & 0xffff) ^ 0x8000) >= 0x10000 - extra
17130 : offset - (0x8000 - extra) < UNITS_PER_WORD)
17133 sri->icode = CODE_FOR_reload_si_load;
17135 sri->icode = CODE_FOR_reload_si_store;
17136 sri->extra_cost = 2;
17151 ret = default_secondary_reload (in_p, x, rclass, mode, sri);
17153 gcc_assert (ret != ALL_REGS);
17155 if (TARGET_DEBUG_ADDR)
17158 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
17160 reg_class_names[ret],
17161 in_p ? "true" : "false",
17162 reg_class_names[rclass],
17163 GET_MODE_NAME (mode));
17165 if (reload_completed)
17166 fputs (", after reload", stderr);
17169 fputs (", done_p not set", stderr);
17172 fputs (", default secondary reload", stderr);
17174 if (sri->icode != CODE_FOR_nothing)
17175 fprintf (stderr, ", reload func = %s, extra cost = %d",
17176 insn_data[sri->icode].name, sri->extra_cost);
17178 fputs ("\n", stderr);
17185 /* Better tracing for rs6000_secondary_reload_inner. */
17188 rs6000_secondary_reload_trace (int line, rtx reg, rtx mem, rtx scratch,
17193 gcc_assert (reg != NULL_RTX && mem != NULL_RTX && scratch != NULL_RTX);
17195 fprintf (stderr, "rs6000_secondary_reload_inner:%d, type = %s\n", line,
17196 store_p ? "store" : "load");
17199 set = gen_rtx_SET (VOIDmode, mem, reg);
17201 set = gen_rtx_SET (VOIDmode, reg, mem);
17203 clobber = gen_rtx_CLOBBER (VOIDmode, scratch);
17204 debug_rtx (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, clobber)));
17207 static void rs6000_secondary_reload_fail (int, rtx, rtx, rtx, bool)
17208 ATTRIBUTE_NORETURN;
17211 rs6000_secondary_reload_fail (int line, rtx reg, rtx mem, rtx scratch,
17214 rs6000_secondary_reload_trace (line, reg, mem, scratch, store_p);
17215 gcc_unreachable ();
17218 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
17219 reload helper functions. These were identified in
17220 rs6000_secondary_reload_memory, and if reload decided to use the secondary
17221 reload, it calls the insns:
17222 reload_<RELOAD:mode>_<P:mptrsize>_store
17223 reload_<RELOAD:mode>_<P:mptrsize>_load
17225 which in turn calls this function, to do whatever is necessary to create
17226 valid addresses. */
17229 rs6000_secondary_reload_inner (rtx reg, rtx mem, rtx scratch, bool store_p)
17231 int regno = true_regnum (reg);
17232 machine_mode mode = GET_MODE (reg);
17233 addr_mask_type addr_mask;
17236 rtx op_reg, op0, op1;
17241 if (regno < 0 || regno >= FIRST_PSEUDO_REGISTER || !MEM_P (mem)
17242 || !base_reg_operand (scratch, GET_MODE (scratch)))
17243 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
17245 if (IN_RANGE (regno, FIRST_GPR_REGNO, LAST_GPR_REGNO))
17246 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
17248 else if (IN_RANGE (regno, FIRST_FPR_REGNO, LAST_FPR_REGNO))
17249 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
17251 else if (IN_RANGE (regno, FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO))
17252 addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
17255 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
17257 /* Make sure the mode is valid in this register class. */
17258 if ((addr_mask & RELOAD_REG_VALID) == 0)
17259 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
17261 if (TARGET_DEBUG_ADDR)
17262 rs6000_secondary_reload_trace (__LINE__, reg, mem, scratch, store_p);
17264 new_addr = addr = XEXP (mem, 0);
17265 switch (GET_CODE (addr))
17267 /* Does the register class support auto update forms for this mode? If
17268 not, do the update now. We don't need a scratch register, since the
17269 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
17272 op_reg = XEXP (addr, 0);
17273 if (!base_reg_operand (op_reg, Pmode))
17274 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
17276 if ((addr_mask & RELOAD_REG_PRE_INCDEC) == 0)
17278 emit_insn (gen_add2_insn (op_reg, GEN_INT (GET_MODE_SIZE (mode))));
17284 op0 = XEXP (addr, 0);
17285 op1 = XEXP (addr, 1);
17286 if (!base_reg_operand (op0, Pmode)
17287 || GET_CODE (op1) != PLUS
17288 || !rtx_equal_p (op0, XEXP (op1, 0)))
17289 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
17291 if ((addr_mask & RELOAD_REG_PRE_MODIFY) == 0)
17293 emit_insn (gen_rtx_SET (VOIDmode, op0, op1));
17298 /* Do we need to simulate AND -16 to clear the bottom address bits used
17299 in VMX load/stores? */
17301 op0 = XEXP (addr, 0);
17302 op1 = XEXP (addr, 1);
17303 if ((addr_mask & RELOAD_REG_AND_M16) == 0)
17305 if (REG_P (op0) || GET_CODE (op0) == SUBREG)
17308 else if (GET_CODE (op1) == PLUS)
17310 emit_insn (gen_rtx_SET (VOIDmode, scratch, op1));
17315 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
17317 and_op = gen_rtx_AND (GET_MODE (scratch), op_reg, op1);
17318 cc_clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
17319 rv = gen_rtvec (2, gen_rtx_SET (VOIDmode, scratch, and_op), cc_clobber);
17320 emit_insn (gen_rtx_PARALLEL (VOIDmode, rv));
17321 new_addr = scratch;
17325 /* If this is an indirect address, make sure it is a base register. */
17328 if (!base_reg_operand (addr, GET_MODE (addr)))
17330 emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
17331 new_addr = scratch;
17335 /* If this is an indexed address, make sure the register class can handle
17336 indexed addresses for this mode. */
17338 op0 = XEXP (addr, 0);
17339 op1 = XEXP (addr, 1);
17340 if (!base_reg_operand (op0, Pmode))
17341 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
17343 else if (int_reg_operand (op1, Pmode))
17345 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
17347 emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
17348 new_addr = scratch;
17352 /* Make sure the register class can handle offset addresses. */
17353 else if (rs6000_legitimate_offset_address_p (mode, addr, false, true))
17355 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
17357 emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
17358 new_addr = scratch;
17363 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
17368 op0 = XEXP (addr, 0);
17369 op1 = XEXP (addr, 1);
17370 if (!base_reg_operand (op0, Pmode))
17371 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
17373 else if (int_reg_operand (op1, Pmode))
17375 if ((addr_mask & RELOAD_REG_INDEXED) == 0)
17377 emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
17378 new_addr = scratch;
17382 /* Make sure the register class can handle offset addresses. */
17383 else if (legitimate_lo_sum_address_p (mode, addr, false))
17385 if ((addr_mask & RELOAD_REG_OFFSET) == 0)
17387 emit_insn (gen_rtx_SET (VOIDmode, scratch, addr));
17388 new_addr = scratch;
17393 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
17400 rs6000_emit_move (scratch, addr, Pmode);
17401 new_addr = scratch;
17405 rs6000_secondary_reload_fail (__LINE__, reg, mem, scratch, store_p);
17408 /* Adjust the address if it changed. */
17409 if (addr != new_addr)
17411 mem = replace_equiv_address_nv (mem, new_addr);
17412 if (TARGET_DEBUG_ADDR)
17413 fprintf (stderr, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
17416 /* Now create the move. */
17418 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
17420 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
17425 /* Convert reloads involving 64-bit gprs and misaligned offset
17426 addressing, or multiple 32-bit gprs and offsets that are too large,
17427 to use indirect addressing. */
17430 rs6000_secondary_reload_gpr (rtx reg, rtx mem, rtx scratch, bool store_p)
17432 int regno = true_regnum (reg);
17433 enum reg_class rclass;
17435 rtx scratch_or_premodify = scratch;
17437 if (TARGET_DEBUG_ADDR)
17439 fprintf (stderr, "\nrs6000_secondary_reload_gpr, type = %s\n",
17440 store_p ? "store" : "load");
17441 fprintf (stderr, "reg:\n");
17443 fprintf (stderr, "mem:\n");
17445 fprintf (stderr, "scratch:\n");
17446 debug_rtx (scratch);
17449 gcc_assert (regno >= 0 && regno < FIRST_PSEUDO_REGISTER);
17450 gcc_assert (GET_CODE (mem) == MEM);
17451 rclass = REGNO_REG_CLASS (regno);
17452 gcc_assert (rclass == GENERAL_REGS || rclass == BASE_REGS);
17453 addr = XEXP (mem, 0);
17455 if (GET_CODE (addr) == PRE_MODIFY)
17457 scratch_or_premodify = XEXP (addr, 0);
17458 gcc_assert (REG_P (scratch_or_premodify));
17459 addr = XEXP (addr, 1);
17461 gcc_assert (GET_CODE (addr) == PLUS || GET_CODE (addr) == LO_SUM);
17463 rs6000_emit_move (scratch_or_premodify, addr, Pmode);
17465 mem = replace_equiv_address_nv (mem, scratch_or_premodify);
17467 /* Now create the move. */
17469 emit_insn (gen_rtx_SET (VOIDmode, mem, reg));
17471 emit_insn (gen_rtx_SET (VOIDmode, reg, mem));
17476 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
17477 this function has any SDmode references. If we are on a power7 or later, we
17478 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
17479 can load/store the value. */
17482 rs6000_alloc_sdmode_stack_slot (void)
17486 gimple_stmt_iterator gsi;
17488 gcc_assert (cfun->machine->sdmode_stack_slot == NULL_RTX);
17489 /* We use a different approach for dealing with the secondary
17494 if (TARGET_NO_SDMODE_STACK)
17497 FOR_EACH_BB_FN (bb, cfun)
17498 for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
17500 tree ret = walk_gimple_op (gsi_stmt (gsi), rs6000_check_sdmode, NULL);
17503 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
17504 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
17510 /* Check for any SDmode parameters of the function. */
17511 for (t = DECL_ARGUMENTS (cfun->decl); t; t = DECL_CHAIN (t))
17513 if (TREE_TYPE (t) == error_mark_node)
17516 if (TYPE_MODE (TREE_TYPE (t)) == SDmode
17517 || TYPE_MODE (DECL_ARG_TYPE (t)) == SDmode)
17519 rtx stack = assign_stack_local (DDmode, GET_MODE_SIZE (DDmode), 0);
17520 cfun->machine->sdmode_stack_slot = adjust_address_nv (stack,
17528 rs6000_instantiate_decls (void)
17530 if (cfun->machine->sdmode_stack_slot != NULL_RTX)
17531 instantiate_decl_rtl (cfun->machine->sdmode_stack_slot);
17534 /* Given an rtx X being reloaded into a reg required to be
17535 in class CLASS, return the class of reg to actually use.
17536 In general this is just CLASS; but on some machines
17537 in some cases it is preferable to use a more restrictive class.
17539 On the RS/6000, we have to return NO_REGS when we want to reload a
17540 floating-point CONST_DOUBLE to force it to be copied to memory.
17542 We also don't want to reload integer values into floating-point
17543 registers if we can at all help it. In fact, this can
17544 cause reload to die, if it tries to generate a reload of CTR
17545 into a FP register and discovers it doesn't have the memory location
17548 ??? Would it be a good idea to have reload do the converse, that is
17549 try to reload floating modes into FP registers if possible?
17552 static enum reg_class
17553 rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
17555 machine_mode mode = GET_MODE (x);
17556 bool is_constant = CONSTANT_P (x);
17558 /* Do VSX tests before handling traditional floaitng point registers. */
17559 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
17563 /* Zero is always allowed in all VSX registers. */
17564 if (x == CONST0_RTX (mode))
17567 /* If this is a vector constant that can be formed with a few Altivec
17568 instructions, we want altivec registers. */
17569 if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
17570 return ALTIVEC_REGS;
17572 /* Force constant to memory. */
17576 /* If this is a scalar floating point value, prefer the traditional
17577 floating point registers so that we can use D-form (register+offset)
17579 if (GET_MODE_SIZE (mode) < 16)
17582 /* Prefer the Altivec registers if Altivec is handling the vector
17583 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
17585 if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode)
17586 || mode == V1TImode)
17587 return ALTIVEC_REGS;
17592 if (is_constant || GET_CODE (x) == PLUS)
17594 if (reg_class_subset_p (GENERAL_REGS, rclass))
17595 return GENERAL_REGS;
17596 if (reg_class_subset_p (BASE_REGS, rclass))
17601 if (GET_MODE_CLASS (mode) == MODE_INT && rclass == NON_SPECIAL_REGS)
17602 return GENERAL_REGS;
17607 /* Debug version of rs6000_preferred_reload_class. */
17608 static enum reg_class
17609 rs6000_debug_preferred_reload_class (rtx x, enum reg_class rclass)
17611 enum reg_class ret = rs6000_preferred_reload_class (x, rclass);
17614 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
17616 reg_class_names[ret], reg_class_names[rclass],
17617 GET_MODE_NAME (GET_MODE (x)));
17623 /* If we are copying between FP or AltiVec registers and anything else, we need
17624 a memory location. The exception is when we are targeting ppc64 and the
17625 move to/from fpr to gpr instructions are available. Also, under VSX, you
17626 can copy vector registers from the FP register set to the Altivec register
17627 set and vice versa. */
17630 rs6000_secondary_memory_needed (enum reg_class from_class,
17631 enum reg_class to_class,
17634 enum rs6000_reg_type from_type, to_type;
17635 bool altivec_p = ((from_class == ALTIVEC_REGS)
17636 || (to_class == ALTIVEC_REGS));
17638 /* If a simple/direct move is available, we don't need secondary memory */
17639 from_type = reg_class_to_reg_type[(int)from_class];
17640 to_type = reg_class_to_reg_type[(int)to_class];
17642 if (rs6000_secondary_reload_move (to_type, from_type, mode,
17643 (secondary_reload_info *)0, altivec_p))
17646 /* If we have a floating point or vector register class, we need to use
17647 memory to transfer the data. */
17648 if (IS_FP_VECT_REG_TYPE (from_type) || IS_FP_VECT_REG_TYPE (to_type))
17654 /* Debug version of rs6000_secondary_memory_needed. */
17656 rs6000_debug_secondary_memory_needed (enum reg_class from_class,
17657 enum reg_class to_class,
17660 bool ret = rs6000_secondary_memory_needed (from_class, to_class, mode);
17663 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
17664 "to_class = %s, mode = %s\n",
17665 ret ? "true" : "false",
17666 reg_class_names[from_class],
17667 reg_class_names[to_class],
17668 GET_MODE_NAME (mode));
17673 /* Return the register class of a scratch register needed to copy IN into
17674 or out of a register in RCLASS in MODE. If it can be done directly,
17675 NO_REGS is returned. */
17677 static enum reg_class
17678 rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
17683 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
17685 && MACHOPIC_INDIRECT
17689 /* We cannot copy a symbolic operand directly into anything
17690 other than BASE_REGS for TARGET_ELF. So indicate that a
17691 register from BASE_REGS is needed as an intermediate
17694 On Darwin, pic addresses require a load from memory, which
17695 needs a base register. */
17696 if (rclass != BASE_REGS
17697 && (GET_CODE (in) == SYMBOL_REF
17698 || GET_CODE (in) == HIGH
17699 || GET_CODE (in) == LABEL_REF
17700 || GET_CODE (in) == CONST))
17704 if (GET_CODE (in) == REG)
17706 regno = REGNO (in);
17707 if (regno >= FIRST_PSEUDO_REGISTER)
17709 regno = true_regnum (in);
17710 if (regno >= FIRST_PSEUDO_REGISTER)
17714 else if (GET_CODE (in) == SUBREG)
17716 regno = true_regnum (in);
17717 if (regno >= FIRST_PSEUDO_REGISTER)
17723 /* If we have VSX register moves, prefer moving scalar values between
17724 Altivec registers and GPR by going via an FPR (and then via memory)
17725 instead of reloading the secondary memory address for Altivec moves. */
17727 && GET_MODE_SIZE (mode) < 16
17728 && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
17729 && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
17730 || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)
17731 && (regno >= 0 && INT_REGNO_P (regno)))))
17734 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
17736 if (rclass == GENERAL_REGS || rclass == BASE_REGS
17737 || (regno >= 0 && INT_REGNO_P (regno)))
17740 /* Constants, memory, and VSX registers can go into VSX registers (both the
17741 traditional floating point and the altivec registers). */
17742 if (rclass == VSX_REGS
17743 && (regno == -1 || VSX_REGNO_P (regno)))
17746 /* Constants, memory, and FP registers can go into FP registers. */
17747 if ((regno == -1 || FP_REGNO_P (regno))
17748 && (rclass == FLOAT_REGS || rclass == NON_SPECIAL_REGS))
17749 return (mode != SDmode || lra_in_progress) ? NO_REGS : GENERAL_REGS;
17751 /* Memory, and AltiVec registers can go into AltiVec registers. */
17752 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
17753 && rclass == ALTIVEC_REGS)
17756 /* We can copy among the CR registers. */
17757 if ((rclass == CR_REGS || rclass == CR0_REGS)
17758 && regno >= 0 && CR_REGNO_P (regno))
17761 /* Otherwise, we need GENERAL_REGS. */
17762 return GENERAL_REGS;
17765 /* Debug version of rs6000_secondary_reload_class. */
17766 static enum reg_class
17767 rs6000_debug_secondary_reload_class (enum reg_class rclass,
17768 machine_mode mode, rtx in)
17770 enum reg_class ret = rs6000_secondary_reload_class (rclass, mode, in);
17772 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
17773 "mode = %s, input rtx:\n",
17774 reg_class_names[ret], reg_class_names[rclass],
17775 GET_MODE_NAME (mode));
17781 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
17784 rs6000_cannot_change_mode_class (machine_mode from,
17786 enum reg_class rclass)
17788 unsigned from_size = GET_MODE_SIZE (from);
17789 unsigned to_size = GET_MODE_SIZE (to);
17791 if (from_size != to_size)
17793 enum reg_class xclass = (TARGET_VSX) ? VSX_REGS : FLOAT_REGS;
17795 if (reg_classes_intersect_p (xclass, rclass))
17797 unsigned to_nregs = hard_regno_nregs[FIRST_FPR_REGNO][to];
17798 unsigned from_nregs = hard_regno_nregs[FIRST_FPR_REGNO][from];
17800 /* Don't allow 64-bit types to overlap with 128-bit types that take a
17801 single register under VSX because the scalar part of the register
17802 is in the upper 64-bits, and not the lower 64-bits. Types like
17803 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
17804 IEEE floating point can't overlap, and neither can small
17807 if (TARGET_IEEEQUAD && (to == TFmode || from == TFmode))
17810 /* TDmode in floating-mode registers must always go into a register
17811 pair with the most significant word in the even-numbered register
17812 to match ISA requirements. In little-endian mode, this does not
17813 match subreg numbering, so we cannot allow subregs. */
17814 if (!BYTES_BIG_ENDIAN && (to == TDmode || from == TDmode))
17817 if (from_size < 8 || to_size < 8)
17820 if (from_size == 8 && (8 * to_nregs) != to_size)
17823 if (to_size == 8 && (8 * from_nregs) != from_size)
17832 if (TARGET_E500_DOUBLE
17833 && ((((to) == DFmode) + ((from) == DFmode)) == 1
17834 || (((to) == TFmode) + ((from) == TFmode)) == 1
17835 || (((to) == DDmode) + ((from) == DDmode)) == 1
17836 || (((to) == TDmode) + ((from) == TDmode)) == 1
17837 || (((to) == DImode) + ((from) == DImode)) == 1))
17840 /* Since the VSX register set includes traditional floating point registers
17841 and altivec registers, just check for the size being different instead of
17842 trying to check whether the modes are vector modes. Otherwise it won't
17843 allow say DF and DI to change classes. For types like TFmode and TDmode
17844 that take 2 64-bit registers, rather than a single 128-bit register, don't
17845 allow subregs of those types to other 128 bit types. */
17846 if (TARGET_VSX && VSX_REG_CLASS_P (rclass))
17848 unsigned num_regs = (from_size + 15) / 16;
17849 if (hard_regno_nregs[FIRST_FPR_REGNO][to] > num_regs
17850 || hard_regno_nregs[FIRST_FPR_REGNO][from] > num_regs)
17853 return (from_size != 8 && from_size != 16);
17856 if (TARGET_ALTIVEC && rclass == ALTIVEC_REGS
17857 && (ALTIVEC_VECTOR_MODE (from) + ALTIVEC_VECTOR_MODE (to)) == 1)
17860 if (TARGET_SPE && (SPE_VECTOR_MODE (from) + SPE_VECTOR_MODE (to)) == 1
17861 && reg_classes_intersect_p (GENERAL_REGS, rclass))
17867 /* Debug version of rs6000_cannot_change_mode_class. */
17869 rs6000_debug_cannot_change_mode_class (machine_mode from,
17871 enum reg_class rclass)
17873 bool ret = rs6000_cannot_change_mode_class (from, to, rclass);
17876 "rs6000_cannot_change_mode_class, return %s, from = %s, "
17877 "to = %s, rclass = %s\n",
17878 ret ? "true" : "false",
17879 GET_MODE_NAME (from), GET_MODE_NAME (to),
17880 reg_class_names[rclass]);
17885 /* Return a string to do a move operation of 128 bits of data. */
17888 rs6000_output_move_128bit (rtx operands[])
17890 rtx dest = operands[0];
17891 rtx src = operands[1];
17892 machine_mode mode = GET_MODE (dest);
17895 bool dest_gpr_p, dest_fp_p, dest_vmx_p, dest_vsx_p;
17896 bool src_gpr_p, src_fp_p, src_vmx_p, src_vsx_p;
17900 dest_regno = REGNO (dest);
17901 dest_gpr_p = INT_REGNO_P (dest_regno);
17902 dest_fp_p = FP_REGNO_P (dest_regno);
17903 dest_vmx_p = ALTIVEC_REGNO_P (dest_regno);
17904 dest_vsx_p = dest_fp_p | dest_vmx_p;
17909 dest_gpr_p = dest_fp_p = dest_vmx_p = dest_vsx_p = false;
17914 src_regno = REGNO (src);
17915 src_gpr_p = INT_REGNO_P (src_regno);
17916 src_fp_p = FP_REGNO_P (src_regno);
17917 src_vmx_p = ALTIVEC_REGNO_P (src_regno);
17918 src_vsx_p = src_fp_p | src_vmx_p;
17923 src_gpr_p = src_fp_p = src_vmx_p = src_vsx_p = false;
17926 /* Register moves. */
17927 if (dest_regno >= 0 && src_regno >= 0)
17934 else if (TARGET_VSX && TARGET_DIRECT_MOVE && src_vsx_p)
17938 else if (TARGET_VSX && dest_vsx_p)
17941 return "xxlor %x0,%x1,%x1";
17943 else if (TARGET_DIRECT_MOVE && src_gpr_p)
17947 else if (TARGET_ALTIVEC && dest_vmx_p && src_vmx_p)
17948 return "vor %0,%1,%1";
17950 else if (dest_fp_p && src_fp_p)
17955 else if (dest_regno >= 0 && MEM_P (src))
17959 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
17965 else if (TARGET_ALTIVEC && dest_vmx_p
17966 && altivec_indexed_or_indirect_operand (src, mode))
17967 return "lvx %0,%y1";
17969 else if (TARGET_VSX && dest_vsx_p)
17971 if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
17972 return "lxvw4x %x0,%y1";
17974 return "lxvd2x %x0,%y1";
17977 else if (TARGET_ALTIVEC && dest_vmx_p)
17978 return "lvx %0,%y1";
17980 else if (dest_fp_p)
17985 else if (src_regno >= 0 && MEM_P (dest))
17989 if (TARGET_QUAD_MEMORY && quad_load_store_p (dest, src))
17990 return "stq %1,%0";
17995 else if (TARGET_ALTIVEC && src_vmx_p
17996 && altivec_indexed_or_indirect_operand (src, mode))
17997 return "stvx %1,%y0";
17999 else if (TARGET_VSX && src_vsx_p)
18001 if (mode == V16QImode || mode == V8HImode || mode == V4SImode)
18002 return "stxvw4x %x1,%y0";
18004 return "stxvd2x %x1,%y0";
18007 else if (TARGET_ALTIVEC && src_vmx_p)
18008 return "stvx %1,%y0";
18015 else if (dest_regno >= 0
18016 && (GET_CODE (src) == CONST_INT
18017 || GET_CODE (src) == CONST_WIDE_INT
18018 || GET_CODE (src) == CONST_DOUBLE
18019 || GET_CODE (src) == CONST_VECTOR))
18024 else if (TARGET_VSX && dest_vsx_p && zero_constant (src, mode))
18025 return "xxlxor %x0,%x0,%x0";
18027 else if (TARGET_ALTIVEC && dest_vmx_p)
18028 return output_vec_const_move (operands);
18031 if (TARGET_DEBUG_ADDR)
18033 fprintf (stderr, "\n===== Bad 128 bit move:\n");
18034 debug_rtx (gen_rtx_SET (VOIDmode, dest, src));
18037 gcc_unreachable ();
18040 /* Validate a 128-bit move. */
18042 rs6000_move_128bit_ok_p (rtx operands[])
18044 machine_mode mode = GET_MODE (operands[0]);
18045 return (gpc_reg_operand (operands[0], mode)
18046 || gpc_reg_operand (operands[1], mode));
18049 /* Return true if a 128-bit move needs to be split. */
18051 rs6000_split_128bit_ok_p (rtx operands[])
18053 if (!reload_completed)
18056 if (!gpr_or_gpr_p (operands[0], operands[1]))
18059 if (quad_load_store_p (operands[0], operands[1]))
18066 /* Given a comparison operation, return the bit number in CCR to test. We
18067 know this is a valid comparison.
18069 SCC_P is 1 if this is for an scc. That means that %D will have been
18070 used instead of %C, so the bits will be in different places.
18072 Return -1 if OP isn't a valid comparison for some reason. */
18075 ccr_bit (rtx op, int scc_p)
18077 enum rtx_code code = GET_CODE (op);
18078 machine_mode cc_mode;
18083 if (!COMPARISON_P (op))
18086 reg = XEXP (op, 0);
18088 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
18090 cc_mode = GET_MODE (reg);
18091 cc_regnum = REGNO (reg);
18092 base_bit = 4 * (cc_regnum - CR0_REGNO);
18094 validate_condition_mode (code, cc_mode);
18096 /* When generating a sCOND operation, only positive conditions are
18099 || code == EQ || code == GT || code == LT || code == UNORDERED
18100 || code == GTU || code == LTU);
18105 return scc_p ? base_bit + 3 : base_bit + 2;
18107 return base_bit + 2;
18108 case GT: case GTU: case UNLE:
18109 return base_bit + 1;
18110 case LT: case LTU: case UNGE:
18112 case ORDERED: case UNORDERED:
18113 return base_bit + 3;
18116 /* If scc, we will have done a cror to put the bit in the
18117 unordered position. So test that bit. For integer, this is ! LT
18118 unless this is an scc insn. */
18119 return scc_p ? base_bit + 3 : base_bit;
18122 return scc_p ? base_bit + 3 : base_bit + 1;
18125 gcc_unreachable ();
18129 /* Return the GOT register. */
18132 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
18134 /* The second flow pass currently (June 1999) can't update
18135 regs_ever_live without disturbing other parts of the compiler, so
18136 update it here to make the prolog/epilogue code happy. */
18137 if (!can_create_pseudo_p ()
18138 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
18139 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
18141 crtl->uses_pic_offset_table = 1;
18143 return pic_offset_table_rtx;
18146 static rs6000_stack_t stack_info;
18148 /* Function to init struct machine_function.
18149 This will be called, via a pointer variable,
18150 from push_function_context. */
18152 static struct machine_function *
18153 rs6000_init_machine_status (void)
18155 stack_info.reload_completed = 0;
18156 return ggc_cleared_alloc<machine_function> ();
18159 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
18162 extract_MB (rtx op)
18165 unsigned long val = INTVAL (op);
18167 /* If the high bit is zero, the value is the first 1 bit we find
18169 if ((val & 0x80000000) == 0)
18171 gcc_assert (val & 0xffffffff);
18174 while (((val <<= 1) & 0x80000000) == 0)
18179 /* If the high bit is set and the low bit is not, or the mask is all
18180 1's, the value is zero. */
18181 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
18184 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
18187 while (((val >>= 1) & 1) != 0)
18194 extract_ME (rtx op)
18197 unsigned long val = INTVAL (op);
18199 /* If the low bit is zero, the value is the first 1 bit we find from
18201 if ((val & 1) == 0)
18203 gcc_assert (val & 0xffffffff);
18206 while (((val >>= 1) & 1) == 0)
18212 /* If the low bit is set and the high bit is not, or the mask is all
18213 1's, the value is 31. */
18214 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
18217 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
18220 while (((val <<= 1) & 0x80000000) != 0)
18226 /* Write out a function code label. */
18229 rs6000_output_function_entry (FILE *file, const char *fname)
18231 if (fname[0] != '.')
18233 switch (DEFAULT_ABI)
18236 gcc_unreachable ();
18242 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
18252 RS6000_OUTPUT_BASENAME (file, fname);
18255 /* Print an operand. Recognize special options, documented below. */
18258 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
18259 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
18261 #define SMALL_DATA_RELOC "sda21"
18262 #define SMALL_DATA_REG 0
18266 print_operand (FILE *file, rtx x, int code)
18269 unsigned HOST_WIDE_INT uval;
18273 /* %a is output_address. */
18276 /* If constant, low-order 16 bits of constant, unsigned.
18277 Otherwise, write normally. */
18279 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff);
18281 print_operand (file, x, 0);
18285 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
18286 for 64-bit mask direction. */
18287 putc (((INTVAL (x) & 1) == 0 ? 'r' : 'l'), file);
18290 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
18294 /* Like 'J' but get to the GT bit only. */
18295 gcc_assert (REG_P (x));
18297 /* Bit 1 is GT bit. */
18298 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
18300 /* Add one for shift count in rlinm for scc. */
18301 fprintf (file, "%d", i + 1);
18305 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
18308 output_operand_lossage ("invalid %%e value");
18313 if ((uval & 0xffff) == 0 && uval != 0)
18318 /* X is a CR register. Print the number of the EQ bit of the CR */
18319 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
18320 output_operand_lossage ("invalid %%E value");
18322 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
18326 /* X is a CR register. Print the shift count needed to move it
18327 to the high-order four bits. */
18328 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
18329 output_operand_lossage ("invalid %%f value");
18331 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
18335 /* Similar, but print the count for the rotate in the opposite
18337 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
18338 output_operand_lossage ("invalid %%F value");
18340 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
18344 /* X is a constant integer. If it is negative, print "m",
18345 otherwise print "z". This is to make an aze or ame insn. */
18346 if (GET_CODE (x) != CONST_INT)
18347 output_operand_lossage ("invalid %%G value");
18348 else if (INTVAL (x) >= 0)
18355 /* If constant, output low-order five bits. Otherwise, write
18358 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 31);
18360 print_operand (file, x, 0);
18364 /* If constant, output low-order six bits. Otherwise, write
18367 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 63);
18369 print_operand (file, x, 0);
18373 /* Print `i' if this is a constant, else nothing. */
18379 /* Write the bit number in CCR for jump. */
18380 i = ccr_bit (x, 0);
18382 output_operand_lossage ("invalid %%j code");
18384 fprintf (file, "%d", i);
18388 /* Similar, but add one for shift count in rlinm for scc and pass
18389 scc flag to `ccr_bit'. */
18390 i = ccr_bit (x, 1);
18392 output_operand_lossage ("invalid %%J code");
18394 /* If we want bit 31, write a shift count of zero, not 32. */
18395 fprintf (file, "%d", i == 31 ? 0 : i + 1);
18399 /* X must be a constant. Write the 1's complement of the
18402 output_operand_lossage ("invalid %%k value");
18404 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INTVAL (x));
18408 /* X must be a symbolic constant on ELF. Write an
18409 expression suitable for an 'addi' that adds in the low 16
18410 bits of the MEM. */
18411 if (GET_CODE (x) == CONST)
18413 if (GET_CODE (XEXP (x, 0)) != PLUS
18414 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
18415 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
18416 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
18417 output_operand_lossage ("invalid %%K value");
18419 print_operand_address (file, x);
18420 fputs ("@l", file);
18423 /* %l is output_asm_label. */
18426 /* Write second word of DImode or DFmode reference. Works on register
18427 or non-indexed memory only. */
18429 fputs (reg_names[REGNO (x) + 1], file);
18430 else if (MEM_P (x))
18432 /* Handle possible auto-increment. Since it is pre-increment and
18433 we have already done it, we can just use an offset of word. */
18434 if (GET_CODE (XEXP (x, 0)) == PRE_INC
18435 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
18436 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
18438 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
18439 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0),
18442 output_address (XEXP (adjust_address_nv (x, SImode,
18446 if (small_data_operand (x, GET_MODE (x)))
18447 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
18448 reg_names[SMALL_DATA_REG]);
18453 /* MB value for a mask operand. */
18454 if (! mask_operand (x, SImode))
18455 output_operand_lossage ("invalid %%m value");
18457 fprintf (file, "%d", extract_MB (x));
18461 /* ME value for a mask operand. */
18462 if (! mask_operand (x, SImode))
18463 output_operand_lossage ("invalid %%M value");
18465 fprintf (file, "%d", extract_ME (x));
18468 /* %n outputs the negative of its operand. */
18471 /* Write the number of elements in the vector times 4. */
18472 if (GET_CODE (x) != PARALLEL)
18473 output_operand_lossage ("invalid %%N value");
18475 fprintf (file, "%d", XVECLEN (x, 0) * 4);
18479 /* Similar, but subtract 1 first. */
18480 if (GET_CODE (x) != PARALLEL)
18481 output_operand_lossage ("invalid %%O value");
18483 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
18487 /* X is a CONST_INT that is a power of two. Output the logarithm. */
18490 || (i = exact_log2 (INTVAL (x))) < 0)
18491 output_operand_lossage ("invalid %%p value");
18493 fprintf (file, "%d", i);
18497 /* The operand must be an indirect memory reference. The result
18498 is the register name. */
18499 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
18500 || REGNO (XEXP (x, 0)) >= 32)
18501 output_operand_lossage ("invalid %%P value");
18503 fputs (reg_names[REGNO (XEXP (x, 0))], file);
18507 /* This outputs the logical code corresponding to a boolean
18508 expression. The expression may have one or both operands
18509 negated (if one, only the first one). For condition register
18510 logical operations, it will also treat the negated
18511 CR codes as NOTs, but not handle NOTs of them. */
18513 const char *const *t = 0;
18515 enum rtx_code code = GET_CODE (x);
18516 static const char * const tbl[3][3] = {
18517 { "and", "andc", "nor" },
18518 { "or", "orc", "nand" },
18519 { "xor", "eqv", "xor" } };
18523 else if (code == IOR)
18525 else if (code == XOR)
18528 output_operand_lossage ("invalid %%q value");
18530 if (GET_CODE (XEXP (x, 0)) != NOT)
18534 if (GET_CODE (XEXP (x, 1)) == NOT)
18545 if (! TARGET_MFCRF)
18551 /* X is a CR register. Print the mask for `mtcrf'. */
18552 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
18553 output_operand_lossage ("invalid %%R value");
18555 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
18559 /* Low 5 bits of 32 - value */
18561 output_operand_lossage ("invalid %%s value");
18563 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 31);
18567 /* PowerPC64 mask position. All 0's is excluded.
18568 CONST_INT 32-bit mask is considered sign-extended so any
18569 transition must occur within the CONST_INT, not on the boundary. */
18570 if (! mask64_operand (x, DImode))
18571 output_operand_lossage ("invalid %%S value");
18575 if (uval & 1) /* Clear Left */
18577 #if HOST_BITS_PER_WIDE_INT > 64
18578 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
18582 else /* Clear Right */
18585 #if HOST_BITS_PER_WIDE_INT > 64
18586 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
18592 gcc_assert (i >= 0);
18593 fprintf (file, "%d", i);
18597 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
18598 gcc_assert (REG_P (x) && GET_MODE (x) == CCmode);
18600 /* Bit 3 is OV bit. */
18601 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
18603 /* If we want bit 31, write a shift count of zero, not 32. */
18604 fprintf (file, "%d", i == 31 ? 0 : i + 1);
18608 /* Print the symbolic name of a branch target register. */
18609 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
18610 && REGNO (x) != CTR_REGNO))
18611 output_operand_lossage ("invalid %%T value");
18612 else if (REGNO (x) == LR_REGNO)
18613 fputs ("lr", file);
18615 fputs ("ctr", file);
18619 /* High-order or low-order 16 bits of constant, whichever is non-zero,
18620 for use in unsigned operand. */
18623 output_operand_lossage ("invalid %%u value");
18628 if ((uval & 0xffff) == 0)
18631 fprintf (file, HOST_WIDE_INT_PRINT_HEX, uval & 0xffff);
18635 /* High-order 16 bits of constant for use in signed operand. */
18637 output_operand_lossage ("invalid %%v value");
18639 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
18640 (INTVAL (x) >> 16) & 0xffff);
18644 /* Print `u' if this has an auto-increment or auto-decrement. */
18646 && (GET_CODE (XEXP (x, 0)) == PRE_INC
18647 || GET_CODE (XEXP (x, 0)) == PRE_DEC
18648 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
18653 /* Print the trap code for this operand. */
18654 switch (GET_CODE (x))
18657 fputs ("eq", file); /* 4 */
18660 fputs ("ne", file); /* 24 */
18663 fputs ("lt", file); /* 16 */
18666 fputs ("le", file); /* 20 */
18669 fputs ("gt", file); /* 8 */
18672 fputs ("ge", file); /* 12 */
18675 fputs ("llt", file); /* 2 */
18678 fputs ("lle", file); /* 6 */
18681 fputs ("lgt", file); /* 1 */
18684 fputs ("lge", file); /* 5 */
18687 gcc_unreachable ();
18692 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
18695 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
18696 ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
18698 print_operand (file, x, 0);
18702 /* MB value for a PowerPC64 rldic operand. */
18703 i = clz_hwi (INTVAL (x));
18705 fprintf (file, "%d", i);
18709 /* X is a FPR or Altivec register used in a VSX context. */
18710 if (GET_CODE (x) != REG || !VSX_REGNO_P (REGNO (x)))
18711 output_operand_lossage ("invalid %%x value");
18714 int reg = REGNO (x);
18715 int vsx_reg = (FP_REGNO_P (reg)
18717 : reg - FIRST_ALTIVEC_REGNO + 32);
18719 #ifdef TARGET_REGNAMES
18720 if (TARGET_REGNAMES)
18721 fprintf (file, "%%vs%d", vsx_reg);
18724 fprintf (file, "%d", vsx_reg);
18730 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
18731 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
18732 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
18737 /* Like 'L', for third word of TImode/PTImode */
18739 fputs (reg_names[REGNO (x) + 2], file);
18740 else if (MEM_P (x))
18742 if (GET_CODE (XEXP (x, 0)) == PRE_INC
18743 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
18744 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 8));
18745 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
18746 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 8));
18748 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
18749 if (small_data_operand (x, GET_MODE (x)))
18750 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
18751 reg_names[SMALL_DATA_REG]);
18756 /* X is a SYMBOL_REF. Write out the name preceded by a
18757 period and without any trailing data in brackets. Used for function
18758 names. If we are configured for System V (or the embedded ABI) on
18759 the PowerPC, do not emit the period, since those systems do not use
18760 TOCs and the like. */
18761 gcc_assert (GET_CODE (x) == SYMBOL_REF);
18763 /* For macho, check to see if we need a stub. */
18766 const char *name = XSTR (x, 0);
18768 if (darwin_emit_branch_islands
18769 && MACHOPIC_INDIRECT
18770 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
18771 name = machopic_indirection_name (x, /*stub_p=*/true);
18773 assemble_name (file, name);
18775 else if (!DOT_SYMBOLS)
18776 assemble_name (file, XSTR (x, 0));
18778 rs6000_output_function_entry (file, XSTR (x, 0));
18782 /* Like 'L', for last word of TImode/PTImode. */
18784 fputs (reg_names[REGNO (x) + 3], file);
18785 else if (MEM_P (x))
18787 if (GET_CODE (XEXP (x, 0)) == PRE_INC
18788 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
18789 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 12));
18790 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
18791 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 12));
18793 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
18794 if (small_data_operand (x, GET_MODE (x)))
18795 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
18796 reg_names[SMALL_DATA_REG]);
18800 /* Print AltiVec or SPE memory operand. */
18805 gcc_assert (MEM_P (x));
18809 /* Ugly hack because %y is overloaded. */
18810 if ((TARGET_SPE || TARGET_E500_DOUBLE)
18811 && (GET_MODE_SIZE (GET_MODE (x)) == 8
18812 || GET_MODE (x) == TFmode
18813 || GET_MODE (x) == TImode
18814 || GET_MODE (x) == PTImode))
18816 /* Handle [reg]. */
18819 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
18822 /* Handle [reg+UIMM]. */
18823 else if (GET_CODE (tmp) == PLUS &&
18824 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
18828 gcc_assert (REG_P (XEXP (tmp, 0)));
18830 x = INTVAL (XEXP (tmp, 1));
18831 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
18835 /* Fall through. Must be [reg+reg]. */
18837 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x))
18838 && GET_CODE (tmp) == AND
18839 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
18840 && INTVAL (XEXP (tmp, 1)) == -16)
18841 tmp = XEXP (tmp, 0);
18842 else if (VECTOR_MEM_VSX_P (GET_MODE (x))
18843 && GET_CODE (tmp) == PRE_MODIFY)
18844 tmp = XEXP (tmp, 1);
18846 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
18849 if (GET_CODE (tmp) != PLUS
18850 || !REG_P (XEXP (tmp, 0))
18851 || !REG_P (XEXP (tmp, 1)))
18853 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
18857 if (REGNO (XEXP (tmp, 0)) == 0)
18858 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
18859 reg_names[ REGNO (XEXP (tmp, 0)) ]);
18861 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
18862 reg_names[ REGNO (XEXP (tmp, 1)) ]);
18869 fprintf (file, "%s", reg_names[REGNO (x)]);
18870 else if (MEM_P (x))
18872 /* We need to handle PRE_INC and PRE_DEC here, since we need to
18873 know the width from the mode. */
18874 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
18875 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
18876 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
18877 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
18878 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
18879 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
18880 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
18881 output_address (XEXP (XEXP (x, 0), 1));
18883 output_address (XEXP (x, 0));
18887 if (toc_relative_expr_p (x, false))
18888 /* This hack along with a corresponding hack in
18889 rs6000_output_addr_const_extra arranges to output addends
18890 where the assembler expects to find them. eg.
18891 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
18892 without this hack would be output as "x@toc+4". We
18894 output_addr_const (file, CONST_CAST_RTX (tocrel_base));
18896 output_addr_const (file, x);
18901 if (const char *name = get_some_local_dynamic_name ())
18902 assemble_name (file, name);
18904 output_operand_lossage ("'%%&' used without any "
18905 "local dynamic TLS references");
18909 output_operand_lossage ("invalid %%xn code");
18913 /* Print the address of an operand. */
18916 print_operand_address (FILE *file, rtx x)
18919 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
18920 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
18921 || GET_CODE (x) == LABEL_REF)
18923 output_addr_const (file, x);
18924 if (small_data_operand (x, GET_MODE (x)))
18925 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
18926 reg_names[SMALL_DATA_REG]);
18928 gcc_assert (!TARGET_TOC);
18930 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
18931 && REG_P (XEXP (x, 1)))
18933 if (REGNO (XEXP (x, 0)) == 0)
18934 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
18935 reg_names[ REGNO (XEXP (x, 0)) ]);
18937 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
18938 reg_names[ REGNO (XEXP (x, 1)) ]);
18940 else if (GET_CODE (x) == PLUS && REG_P (XEXP (x, 0))
18941 && GET_CODE (XEXP (x, 1)) == CONST_INT)
18942 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
18943 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
18945 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
18946 && CONSTANT_P (XEXP (x, 1)))
18948 fprintf (file, "lo16(");
18949 output_addr_const (file, XEXP (x, 1));
18950 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
18954 else if (GET_CODE (x) == LO_SUM && REG_P (XEXP (x, 0))
18955 && CONSTANT_P (XEXP (x, 1)))
18957 output_addr_const (file, XEXP (x, 1));
18958 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
18961 else if (toc_relative_expr_p (x, false))
18963 /* This hack along with a corresponding hack in
18964 rs6000_output_addr_const_extra arranges to output addends
18965 where the assembler expects to find them. eg.
18967 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
18968 without this hack would be output as "x@toc+8@l(9)". We
18969 want "x+8@toc@l(9)". */
18970 output_addr_const (file, CONST_CAST_RTX (tocrel_base));
18971 if (GET_CODE (x) == LO_SUM)
18972 fprintf (file, "@l(%s)", reg_names[REGNO (XEXP (x, 0))]);
18974 fprintf (file, "(%s)", reg_names[REGNO (XVECEXP (tocrel_base, 0, 1))]);
18977 gcc_unreachable ();
18980 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
18983 rs6000_output_addr_const_extra (FILE *file, rtx x)
18985 if (GET_CODE (x) == UNSPEC)
18986 switch (XINT (x, 1))
18988 case UNSPEC_TOCREL:
18989 gcc_checking_assert (GET_CODE (XVECEXP (x, 0, 0)) == SYMBOL_REF
18990 && REG_P (XVECEXP (x, 0, 1))
18991 && REGNO (XVECEXP (x, 0, 1)) == TOC_REGISTER);
18992 output_addr_const (file, XVECEXP (x, 0, 0));
18993 if (x == tocrel_base && tocrel_offset != const0_rtx)
18995 if (INTVAL (tocrel_offset) >= 0)
18996 fprintf (file, "+");
18997 output_addr_const (file, CONST_CAST_RTX (tocrel_offset));
18999 if (!TARGET_AIX || (TARGET_ELF && TARGET_MINIMAL_TOC))
19002 assemble_name (file, toc_label_name);
19004 else if (TARGET_ELF)
19005 fputs ("@toc", file);
19009 case UNSPEC_MACHOPIC_OFFSET:
19010 output_addr_const (file, XVECEXP (x, 0, 0));
19012 machopic_output_function_base_name (file);
19019 /* Target hook for assembling integer objects. The PowerPC version has
19020 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
19021 is defined. It also needs to handle DI-mode objects on 64-bit
19025 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
19027 #ifdef RELOCATABLE_NEEDS_FIXUP
19028 /* Special handling for SI values. */
19029 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
19031 static int recurse = 0;
19033 /* For -mrelocatable, we mark all addresses that need to be fixed up in
19034 the .fixup section. Since the TOC section is already relocated, we
19035 don't need to mark it here. We used to skip the text section, but it
19036 should never be valid for relocated addresses to be placed in the text
19038 if (TARGET_RELOCATABLE
19039 && in_section != toc_section
19041 && !CONST_SCALAR_INT_P (x)
19047 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
19049 ASM_OUTPUT_LABEL (asm_out_file, buf);
19050 fprintf (asm_out_file, "\t.long\t(");
19051 output_addr_const (asm_out_file, x);
19052 fprintf (asm_out_file, ")@fixup\n");
19053 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
19054 ASM_OUTPUT_ALIGN (asm_out_file, 2);
19055 fprintf (asm_out_file, "\t.long\t");
19056 assemble_name (asm_out_file, buf);
19057 fprintf (asm_out_file, "\n\t.previous\n");
19061 /* Remove initial .'s to turn a -mcall-aixdesc function
19062 address into the address of the descriptor, not the function
19064 else if (GET_CODE (x) == SYMBOL_REF
19065 && XSTR (x, 0)[0] == '.'
19066 && DEFAULT_ABI == ABI_AIX)
19068 const char *name = XSTR (x, 0);
19069 while (*name == '.')
19072 fprintf (asm_out_file, "\t.long\t%s\n", name);
19076 #endif /* RELOCATABLE_NEEDS_FIXUP */
19077 return default_assemble_integer (x, size, aligned_p);
19080 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
19081 /* Emit an assembler directive to set symbol visibility for DECL to
19082 VISIBILITY_TYPE. */
19085 rs6000_assemble_visibility (tree decl, int vis)
19090 /* Functions need to have their entry point symbol visibility set as
19091 well as their descriptor symbol visibility. */
19092 if (DEFAULT_ABI == ABI_AIX
19094 && TREE_CODE (decl) == FUNCTION_DECL)
19096 static const char * const visibility_types[] = {
19097 NULL, "internal", "hidden", "protected"
19100 const char *name, *type;
19102 name = ((* targetm.strip_name_encoding)
19103 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
19104 type = visibility_types[vis];
19106 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
19107 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
19110 default_assemble_visibility (decl, vis);
19115 rs6000_reverse_condition (machine_mode mode, enum rtx_code code)
19117 /* Reversal of FP compares takes care -- an ordered compare
19118 becomes an unordered compare and vice versa. */
19119 if (mode == CCFPmode
19120 && (!flag_finite_math_only
19121 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
19122 || code == UNEQ || code == LTGT))
19123 return reverse_condition_maybe_unordered (code);
19125 return reverse_condition (code);
19128 /* Generate a compare for CODE. Return a brand-new rtx that
19129 represents the result of the compare. */
19132 rs6000_generate_compare (rtx cmp, machine_mode mode)
19134 machine_mode comp_mode;
19135 rtx compare_result;
19136 enum rtx_code code = GET_CODE (cmp);
19137 rtx op0 = XEXP (cmp, 0);
19138 rtx op1 = XEXP (cmp, 1);
19140 if (FLOAT_MODE_P (mode))
19141 comp_mode = CCFPmode;
19142 else if (code == GTU || code == LTU
19143 || code == GEU || code == LEU)
19144 comp_mode = CCUNSmode;
19145 else if ((code == EQ || code == NE)
19146 && unsigned_reg_p (op0)
19147 && (unsigned_reg_p (op1)
19148 || (CONST_INT_P (op1) && INTVAL (op1) != 0)))
19149 /* These are unsigned values, perhaps there will be a later
19150 ordering compare that can be shared with this one. */
19151 comp_mode = CCUNSmode;
19153 comp_mode = CCmode;
19155 /* If we have an unsigned compare, make sure we don't have a signed value as
19157 if (comp_mode == CCUNSmode && GET_CODE (op1) == CONST_INT
19158 && INTVAL (op1) < 0)
19160 op0 = copy_rtx_if_shared (op0);
19161 op1 = force_reg (GET_MODE (op0), op1);
19162 cmp = gen_rtx_fmt_ee (code, GET_MODE (cmp), op0, op1);
19165 /* First, the compare. */
19166 compare_result = gen_reg_rtx (comp_mode);
19168 /* E500 FP compare instructions on the GPRs. Yuck! */
19169 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
19170 && FLOAT_MODE_P (mode))
19172 rtx cmp, or_result, compare_result2;
19173 machine_mode op_mode = GET_MODE (op0);
19176 if (op_mode == VOIDmode)
19177 op_mode = GET_MODE (op1);
19179 /* First reverse the condition codes that aren't directly supported. */
19187 code = reverse_condition_maybe_unordered (code);
19200 gcc_unreachable ();
19203 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
19204 This explains the following mess. */
19212 cmp = (flag_finite_math_only && !flag_trapping_math)
19213 ? gen_tstsfeq_gpr (compare_result, op0, op1)
19214 : gen_cmpsfeq_gpr (compare_result, op0, op1);
19218 cmp = (flag_finite_math_only && !flag_trapping_math)
19219 ? gen_tstdfeq_gpr (compare_result, op0, op1)
19220 : gen_cmpdfeq_gpr (compare_result, op0, op1);
19224 cmp = (flag_finite_math_only && !flag_trapping_math)
19225 ? gen_tsttfeq_gpr (compare_result, op0, op1)
19226 : gen_cmptfeq_gpr (compare_result, op0, op1);
19230 gcc_unreachable ();
19239 cmp = (flag_finite_math_only && !flag_trapping_math)
19240 ? gen_tstsfgt_gpr (compare_result, op0, op1)
19241 : gen_cmpsfgt_gpr (compare_result, op0, op1);
19245 cmp = (flag_finite_math_only && !flag_trapping_math)
19246 ? gen_tstdfgt_gpr (compare_result, op0, op1)
19247 : gen_cmpdfgt_gpr (compare_result, op0, op1);
19251 cmp = (flag_finite_math_only && !flag_trapping_math)
19252 ? gen_tsttfgt_gpr (compare_result, op0, op1)
19253 : gen_cmptfgt_gpr (compare_result, op0, op1);
19257 gcc_unreachable ();
19266 cmp = (flag_finite_math_only && !flag_trapping_math)
19267 ? gen_tstsflt_gpr (compare_result, op0, op1)
19268 : gen_cmpsflt_gpr (compare_result, op0, op1);
19272 cmp = (flag_finite_math_only && !flag_trapping_math)
19273 ? gen_tstdflt_gpr (compare_result, op0, op1)
19274 : gen_cmpdflt_gpr (compare_result, op0, op1);
19278 cmp = (flag_finite_math_only && !flag_trapping_math)
19279 ? gen_tsttflt_gpr (compare_result, op0, op1)
19280 : gen_cmptflt_gpr (compare_result, op0, op1);
19284 gcc_unreachable ();
19289 gcc_unreachable ();
19292 /* Synthesize LE and GE from LT/GT || EQ. */
19293 if (code == LE || code == GE)
19297 compare_result2 = gen_reg_rtx (CCFPmode);
19303 cmp = (flag_finite_math_only && !flag_trapping_math)
19304 ? gen_tstsfeq_gpr (compare_result2, op0, op1)
19305 : gen_cmpsfeq_gpr (compare_result2, op0, op1);
19309 cmp = (flag_finite_math_only && !flag_trapping_math)
19310 ? gen_tstdfeq_gpr (compare_result2, op0, op1)
19311 : gen_cmpdfeq_gpr (compare_result2, op0, op1);
19315 cmp = (flag_finite_math_only && !flag_trapping_math)
19316 ? gen_tsttfeq_gpr (compare_result2, op0, op1)
19317 : gen_cmptfeq_gpr (compare_result2, op0, op1);
19321 gcc_unreachable ();
19326 /* OR them together. */
19327 or_result = gen_reg_rtx (CCFPmode);
19328 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
19330 compare_result = or_result;
19333 code = reverse_p ? NE : EQ;
19339 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
19340 CLOBBERs to match cmptf_internal2 pattern. */
19341 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
19342 && GET_MODE (op0) == TFmode
19343 && !TARGET_IEEEQUAD
19344 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
19345 emit_insn (gen_rtx_PARALLEL (VOIDmode,
19347 gen_rtx_SET (VOIDmode,
19349 gen_rtx_COMPARE (comp_mode, op0, op1)),
19350 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
19351 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
19352 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
19353 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
19354 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
19355 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
19356 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
19357 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
19358 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (Pmode)))));
19359 else if (GET_CODE (op1) == UNSPEC
19360 && XINT (op1, 1) == UNSPEC_SP_TEST)
19362 rtx op1b = XVECEXP (op1, 0, 0);
19363 comp_mode = CCEQmode;
19364 compare_result = gen_reg_rtx (CCEQmode);
19366 emit_insn (gen_stack_protect_testdi (compare_result, op0, op1b));
19368 emit_insn (gen_stack_protect_testsi (compare_result, op0, op1b));
19371 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
19372 gen_rtx_COMPARE (comp_mode, op0, op1)));
19375 /* Some kinds of FP comparisons need an OR operation;
19376 under flag_finite_math_only we don't bother. */
19377 if (FLOAT_MODE_P (mode)
19378 && !flag_finite_math_only
19379 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
19380 && (code == LE || code == GE
19381 || code == UNEQ || code == LTGT
19382 || code == UNGT || code == UNLT))
19384 enum rtx_code or1, or2;
19385 rtx or1_rtx, or2_rtx, compare2_rtx;
19386 rtx or_result = gen_reg_rtx (CCEQmode);
19390 case LE: or1 = LT; or2 = EQ; break;
19391 case GE: or1 = GT; or2 = EQ; break;
19392 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
19393 case LTGT: or1 = LT; or2 = GT; break;
19394 case UNGT: or1 = UNORDERED; or2 = GT; break;
19395 case UNLT: or1 = UNORDERED; or2 = LT; break;
19396 default: gcc_unreachable ();
19398 validate_condition_mode (or1, comp_mode);
19399 validate_condition_mode (or2, comp_mode);
19400 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
19401 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
19402 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
19403 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
19405 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
19407 compare_result = or_result;
19411 validate_condition_mode (code, GET_MODE (compare_result));
19413 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
19417 /* Emit the RTL for an sISEL pattern. */
19420 rs6000_emit_sISEL (machine_mode mode ATTRIBUTE_UNUSED, rtx operands[])
19422 rs6000_emit_int_cmove (operands[0], operands[1], const1_rtx, const0_rtx);
19425 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
19426 can be used as that dest register. Return the dest register. */
19429 rs6000_emit_eqne (machine_mode mode, rtx op1, rtx op2, rtx scratch)
19431 if (op2 == const0_rtx)
19434 if (GET_CODE (scratch) == SCRATCH)
19435 scratch = gen_reg_rtx (mode);
19437 if (logical_operand (op2, mode))
19438 emit_insn (gen_rtx_SET (VOIDmode, scratch, gen_rtx_XOR (mode, op1, op2)));
19440 emit_insn (gen_rtx_SET (VOIDmode, scratch,
19441 gen_rtx_PLUS (mode, op1, negate_rtx (mode, op2))));
19447 rs6000_emit_sCOND (machine_mode mode, rtx operands[])
19450 machine_mode op_mode;
19451 enum rtx_code cond_code;
19452 rtx result = operands[0];
19454 condition_rtx = rs6000_generate_compare (operands[1], mode);
19455 cond_code = GET_CODE (condition_rtx);
19457 if (FLOAT_MODE_P (mode)
19458 && !TARGET_FPRS && TARGET_HARD_FLOAT)
19462 PUT_MODE (condition_rtx, SImode);
19463 t = XEXP (condition_rtx, 0);
19465 gcc_assert (cond_code == NE || cond_code == EQ);
19467 if (cond_code == NE)
19468 emit_insn (gen_e500_flip_gt_bit (t, t));
19470 emit_insn (gen_move_from_CR_gt_bit (result, t));
19474 if (cond_code == NE
19475 || cond_code == GE || cond_code == LE
19476 || cond_code == GEU || cond_code == LEU
19477 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
19479 rtx not_result = gen_reg_rtx (CCEQmode);
19480 rtx not_op, rev_cond_rtx;
19481 machine_mode cc_mode;
19483 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
19485 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
19486 SImode, XEXP (condition_rtx, 0), const0_rtx);
19487 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
19488 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
19489 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
19492 op_mode = GET_MODE (XEXP (operands[1], 0));
19493 if (op_mode == VOIDmode)
19494 op_mode = GET_MODE (XEXP (operands[1], 1));
19496 if (TARGET_POWERPC64 && (op_mode == DImode || FLOAT_MODE_P (mode)))
19498 PUT_MODE (condition_rtx, DImode);
19499 convert_move (result, condition_rtx, 0);
19503 PUT_MODE (condition_rtx, SImode);
19504 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
19508 /* Emit a branch of kind CODE to location LOC. */
19511 rs6000_emit_cbranch (machine_mode mode, rtx operands[])
19513 rtx condition_rtx, loc_ref;
19515 condition_rtx = rs6000_generate_compare (operands[0], mode);
19516 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
19517 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
19518 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
19519 loc_ref, pc_rtx)));
19522 /* Return the string to output a conditional branch to LABEL, which is
19523 the operand template of the label, or NULL if the branch is really a
19524 conditional return.
19526 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
19527 condition code register and its mode specifies what kind of
19528 comparison we made.
19530 REVERSED is nonzero if we should reverse the sense of the comparison.
19532 INSN is the insn. */
19535 output_cbranch (rtx op, const char *label, int reversed, rtx_insn *insn)
19537 static char string[64];
19538 enum rtx_code code = GET_CODE (op);
19539 rtx cc_reg = XEXP (op, 0);
19540 machine_mode mode = GET_MODE (cc_reg);
19541 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
19542 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
19543 int really_reversed = reversed ^ need_longbranch;
19549 validate_condition_mode (code, mode);
19551 /* Work out which way this really branches. We could use
19552 reverse_condition_maybe_unordered here always but this
19553 makes the resulting assembler clearer. */
19554 if (really_reversed)
19556 /* Reversal of FP compares takes care -- an ordered compare
19557 becomes an unordered compare and vice versa. */
19558 if (mode == CCFPmode)
19559 code = reverse_condition_maybe_unordered (code);
19561 code = reverse_condition (code);
19564 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
19566 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
19571 /* Opposite of GT. */
19580 gcc_unreachable ();
19586 /* Not all of these are actually distinct opcodes, but
19587 we distinguish them for clarity of the resulting assembler. */
19588 case NE: case LTGT:
19589 ccode = "ne"; break;
19590 case EQ: case UNEQ:
19591 ccode = "eq"; break;
19593 ccode = "ge"; break;
19594 case GT: case GTU: case UNGT:
19595 ccode = "gt"; break;
19597 ccode = "le"; break;
19598 case LT: case LTU: case UNLT:
19599 ccode = "lt"; break;
19600 case UNORDERED: ccode = "un"; break;
19601 case ORDERED: ccode = "nu"; break;
19602 case UNGE: ccode = "nl"; break;
19603 case UNLE: ccode = "ng"; break;
19605 gcc_unreachable ();
19608 /* Maybe we have a guess as to how likely the branch is. */
19610 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
19611 if (note != NULL_RTX)
19613 /* PROB is the difference from 50%. */
19614 int prob = XINT (note, 0) - REG_BR_PROB_BASE / 2;
19616 /* Only hint for highly probable/improbable branches on newer
19617 cpus as static prediction overrides processor dynamic
19618 prediction. For older cpus we may as well always hint, but
19619 assume not taken for branches that are very close to 50% as a
19620 mispredicted taken branch is more expensive than a
19621 mispredicted not-taken branch. */
19622 if (rs6000_always_hint
19623 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
19624 && br_prob_note_reliable_p (note)))
19626 if (abs (prob) > REG_BR_PROB_BASE / 20
19627 && ((prob > 0) ^ need_longbranch))
19635 s += sprintf (s, "b%slr%s ", ccode, pred);
19637 s += sprintf (s, "b%s%s ", ccode, pred);
19639 /* We need to escape any '%' characters in the reg_names string.
19640 Assume they'd only be the first character.... */
19641 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
19643 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
19647 /* If the branch distance was too far, we may have to use an
19648 unconditional branch to go the distance. */
19649 if (need_longbranch)
19650 s += sprintf (s, ",$+8\n\tb %s", label);
19652 s += sprintf (s, ",%s", label);
19658 /* Return the string to flip the GT bit on a CR. */
19660 output_e500_flip_gt_bit (rtx dst, rtx src)
19662 static char string[64];
19665 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
19666 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
19669 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
19670 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
19672 sprintf (string, "crnot %d,%d", a, b);
19676 /* Return insn for VSX or Altivec comparisons. */
19679 rs6000_emit_vector_compare_inner (enum rtx_code code, rtx op0, rtx op1)
19682 machine_mode mode = GET_MODE (op0);
19690 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT)
19700 mask = gen_reg_rtx (mode);
19701 emit_insn (gen_rtx_SET (VOIDmode,
19703 gen_rtx_fmt_ee (code, mode, op0, op1)));
19710 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
19711 DMODE is expected destination mode. This is a recursive function. */
19714 rs6000_emit_vector_compare (enum rtx_code rcode,
19716 machine_mode dmode)
19719 bool swap_operands = false;
19720 bool try_again = false;
19722 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode));
19723 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
19725 /* See if the comparison works as is. */
19726 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
19734 swap_operands = true;
19739 swap_operands = true;
19747 /* Invert condition and try again.
19748 e.g., A != B becomes ~(A==B). */
19750 enum rtx_code rev_code;
19751 enum insn_code nor_code;
19754 rev_code = reverse_condition_maybe_unordered (rcode);
19755 if (rev_code == UNKNOWN)
19758 nor_code = optab_handler (one_cmpl_optab, dmode);
19759 if (nor_code == CODE_FOR_nothing)
19762 mask2 = rs6000_emit_vector_compare (rev_code, op0, op1, dmode);
19766 mask = gen_reg_rtx (dmode);
19767 emit_insn (GEN_FCN (nor_code) (mask, mask2));
19775 /* Try GT/GTU/LT/LTU OR EQ */
19778 enum insn_code ior_code;
19779 enum rtx_code new_code;
19800 gcc_unreachable ();
19803 ior_code = optab_handler (ior_optab, dmode);
19804 if (ior_code == CODE_FOR_nothing)
19807 c_rtx = rs6000_emit_vector_compare (new_code, op0, op1, dmode);
19811 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1, dmode);
19815 mask = gen_reg_rtx (dmode);
19816 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
19827 std::swap (op0, op1);
19829 mask = rs6000_emit_vector_compare_inner (rcode, op0, op1);
19834 /* You only get two chances. */
19838 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
19839 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
19840 operands for the relation operation COND. */
19843 rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
19844 rtx cond, rtx cc_op0, rtx cc_op1)
19846 machine_mode dest_mode = GET_MODE (dest);
19847 machine_mode mask_mode = GET_MODE (cc_op0);
19848 enum rtx_code rcode = GET_CODE (cond);
19849 machine_mode cc_mode = CCmode;
19853 bool invert_move = false;
19855 if (VECTOR_UNIT_NONE_P (dest_mode))
19858 gcc_assert (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (mask_mode)
19859 && GET_MODE_NUNITS (dest_mode) == GET_MODE_NUNITS (mask_mode));
19863 /* Swap operands if we can, and fall back to doing the operation as
19864 specified, and doing a NOR to invert the test. */
19870 /* Invert condition and try again.
19871 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
19872 invert_move = true;
19873 rcode = reverse_condition_maybe_unordered (rcode);
19874 if (rcode == UNKNOWN)
19878 /* Mark unsigned tests with CCUNSmode. */
19883 cc_mode = CCUNSmode;
19890 /* Get the vector mask for the given relational operations. */
19891 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, mask_mode);
19899 op_true = op_false;
19903 cond2 = gen_rtx_fmt_ee (NE, cc_mode, gen_lowpart (dest_mode, mask),
19904 CONST0_RTX (dest_mode));
19905 emit_insn (gen_rtx_SET (VOIDmode,
19907 gen_rtx_IF_THEN_ELSE (dest_mode,
19914 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
19915 operands of the last comparison is nonzero/true, FALSE_COND if it
19916 is zero/false. Return 0 if the hardware has no such operation. */
19919 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
19921 enum rtx_code code = GET_CODE (op);
19922 rtx op0 = XEXP (op, 0);
19923 rtx op1 = XEXP (op, 1);
19924 REAL_VALUE_TYPE c1;
19925 machine_mode compare_mode = GET_MODE (op0);
19926 machine_mode result_mode = GET_MODE (dest);
19928 bool is_against_zero;
19930 /* These modes should always match. */
19931 if (GET_MODE (op1) != compare_mode
19932 /* In the isel case however, we can use a compare immediate, so
19933 op1 may be a small constant. */
19934 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
19936 if (GET_MODE (true_cond) != result_mode)
19938 if (GET_MODE (false_cond) != result_mode)
19941 /* Don't allow using floating point comparisons for integer results for
19943 if (FLOAT_MODE_P (compare_mode) && !FLOAT_MODE_P (result_mode))
19946 /* First, work out if the hardware can do this at all, or
19947 if it's too slow.... */
19948 if (!FLOAT_MODE_P (compare_mode))
19951 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
19954 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
19955 && SCALAR_FLOAT_MODE_P (compare_mode))
19958 is_against_zero = op1 == CONST0_RTX (compare_mode);
19960 /* A floating-point subtract might overflow, underflow, or produce
19961 an inexact result, thus changing the floating-point flags, so it
19962 can't be generated if we care about that. It's safe if one side
19963 of the construct is zero, since then no subtract will be
19965 if (SCALAR_FLOAT_MODE_P (compare_mode)
19966 && flag_trapping_math && ! is_against_zero)
19969 /* Eliminate half of the comparisons by switching operands, this
19970 makes the remaining code simpler. */
19971 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
19972 || code == LTGT || code == LT || code == UNLE)
19974 code = reverse_condition_maybe_unordered (code);
19976 true_cond = false_cond;
19980 /* UNEQ and LTGT take four instructions for a comparison with zero,
19981 it'll probably be faster to use a branch here too. */
19982 if (code == UNEQ && HONOR_NANS (compare_mode))
19985 if (GET_CODE (op1) == CONST_DOUBLE)
19986 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
19988 /* We're going to try to implement comparisons by performing
19989 a subtract, then comparing against zero. Unfortunately,
19990 Inf - Inf is NaN which is not zero, and so if we don't
19991 know that the operand is finite and the comparison
19992 would treat EQ different to UNORDERED, we can't do it. */
19993 if (HONOR_INFINITIES (compare_mode)
19994 && code != GT && code != UNGE
19995 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
19996 /* Constructs of the form (a OP b ? a : b) are safe. */
19997 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
19998 || (! rtx_equal_p (op0, true_cond)
19999 && ! rtx_equal_p (op1, true_cond))))
20002 /* At this point we know we can use fsel. */
20004 /* Reduce the comparison to a comparison against zero. */
20005 if (! is_against_zero)
20007 temp = gen_reg_rtx (compare_mode);
20008 emit_insn (gen_rtx_SET (VOIDmode, temp,
20009 gen_rtx_MINUS (compare_mode, op0, op1)));
20011 op1 = CONST0_RTX (compare_mode);
20014 /* If we don't care about NaNs we can reduce some of the comparisons
20015 down to faster ones. */
20016 if (! HONOR_NANS (compare_mode))
20022 true_cond = false_cond;
20035 /* Now, reduce everything down to a GE. */
20042 temp = gen_reg_rtx (compare_mode);
20043 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
20048 temp = gen_reg_rtx (compare_mode);
20049 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
20054 temp = gen_reg_rtx (compare_mode);
20055 emit_insn (gen_rtx_SET (VOIDmode, temp,
20056 gen_rtx_NEG (compare_mode,
20057 gen_rtx_ABS (compare_mode, op0))));
20062 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
20063 temp = gen_reg_rtx (result_mode);
20064 emit_insn (gen_rtx_SET (VOIDmode, temp,
20065 gen_rtx_IF_THEN_ELSE (result_mode,
20066 gen_rtx_GE (VOIDmode,
20068 true_cond, false_cond)));
20069 false_cond = true_cond;
20072 temp = gen_reg_rtx (compare_mode);
20073 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
20078 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
20079 temp = gen_reg_rtx (result_mode);
20080 emit_insn (gen_rtx_SET (VOIDmode, temp,
20081 gen_rtx_IF_THEN_ELSE (result_mode,
20082 gen_rtx_GE (VOIDmode,
20084 true_cond, false_cond)));
20085 true_cond = false_cond;
20088 temp = gen_reg_rtx (compare_mode);
20089 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
20094 gcc_unreachable ();
20097 emit_insn (gen_rtx_SET (VOIDmode, dest,
20098 gen_rtx_IF_THEN_ELSE (result_mode,
20099 gen_rtx_GE (VOIDmode,
20101 true_cond, false_cond)));
20105 /* Same as above, but for ints (isel). */
20108 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
20110 rtx condition_rtx, cr;
20111 machine_mode mode = GET_MODE (dest);
20112 enum rtx_code cond_code;
20113 rtx (*isel_func) (rtx, rtx, rtx, rtx, rtx);
20116 if (mode != SImode && (!TARGET_POWERPC64 || mode != DImode))
20119 /* We still have to do the compare, because isel doesn't do a
20120 compare, it just looks at the CRx bits set by a previous compare
20122 condition_rtx = rs6000_generate_compare (op, mode);
20123 cond_code = GET_CODE (condition_rtx);
20124 cr = XEXP (condition_rtx, 0);
20125 signedp = GET_MODE (cr) == CCmode;
20127 isel_func = (mode == SImode
20128 ? (signedp ? gen_isel_signed_si : gen_isel_unsigned_si)
20129 : (signedp ? gen_isel_signed_di : gen_isel_unsigned_di));
20133 case LT: case GT: case LTU: case GTU: case EQ:
20134 /* isel handles these directly. */
20138 /* We need to swap the sense of the comparison. */
20140 std::swap (false_cond, true_cond);
20141 PUT_CODE (condition_rtx, reverse_condition (cond_code));
20146 false_cond = force_reg (mode, false_cond);
20147 if (true_cond != const0_rtx)
20148 true_cond = force_reg (mode, true_cond);
20150 emit_insn (isel_func (dest, condition_rtx, true_cond, false_cond, cr));
20156 output_isel (rtx *operands)
20158 enum rtx_code code;
20160 code = GET_CODE (operands[1]);
20162 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
20164 gcc_assert (GET_CODE (operands[2]) == REG
20165 && GET_CODE (operands[3]) == REG);
20166 PUT_CODE (operands[1], reverse_condition (code));
20167 return "isel %0,%3,%2,%j1";
20170 return "isel %0,%2,%3,%j1";
20174 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
20176 machine_mode mode = GET_MODE (op0);
20180 /* VSX/altivec have direct min/max insns. */
20181 if ((code == SMAX || code == SMIN)
20182 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)
20183 || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode))))
20185 emit_insn (gen_rtx_SET (VOIDmode,
20187 gen_rtx_fmt_ee (code, mode, op0, op1)));
20191 if (code == SMAX || code == SMIN)
20196 if (code == SMAX || code == UMAX)
20197 target = emit_conditional_move (dest, c, op0, op1, mode,
20198 op0, op1, mode, 0);
20200 target = emit_conditional_move (dest, c, op0, op1, mode,
20201 op1, op0, mode, 0);
20202 gcc_assert (target);
20203 if (target != dest)
20204 emit_move_insn (dest, target);
20207 /* A subroutine of the atomic operation splitters. Jump to LABEL if
20208 COND is true. Mark the jump as unlikely to be taken. */
20211 emit_unlikely_jump (rtx cond, rtx label)
20213 int very_unlikely = REG_BR_PROB_BASE / 100 - 1;
20216 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
20217 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
20218 add_int_reg_note (x, REG_BR_PROB, very_unlikely);
20221 /* A subroutine of the atomic operation splitters. Emit a load-locked
20222 instruction in MODE. For QI/HImode, possibly use a pattern than includes
20223 the zero_extend operation. */
20226 emit_load_locked (machine_mode mode, rtx reg, rtx mem)
20228 rtx (*fn) (rtx, rtx) = NULL;
20233 fn = gen_load_lockedqi;
20236 fn = gen_load_lockedhi;
20239 if (GET_MODE (mem) == QImode)
20240 fn = gen_load_lockedqi_si;
20241 else if (GET_MODE (mem) == HImode)
20242 fn = gen_load_lockedhi_si;
20244 fn = gen_load_lockedsi;
20247 fn = gen_load_lockeddi;
20250 fn = gen_load_lockedti;
20253 gcc_unreachable ();
20255 emit_insn (fn (reg, mem));
20258 /* A subroutine of the atomic operation splitters. Emit a store-conditional
20259 instruction in MODE. */
20262 emit_store_conditional (machine_mode mode, rtx res, rtx mem, rtx val)
20264 rtx (*fn) (rtx, rtx, rtx) = NULL;
20269 fn = gen_store_conditionalqi;
20272 fn = gen_store_conditionalhi;
20275 fn = gen_store_conditionalsi;
20278 fn = gen_store_conditionaldi;
20281 fn = gen_store_conditionalti;
20284 gcc_unreachable ();
20287 /* Emit sync before stwcx. to address PPC405 Erratum. */
20288 if (PPC405_ERRATUM77)
20289 emit_insn (gen_hwsync ());
20291 emit_insn (fn (res, mem, val));
20294 /* Expand barriers before and after a load_locked/store_cond sequence. */
20297 rs6000_pre_atomic_barrier (rtx mem, enum memmodel model)
20299 rtx addr = XEXP (mem, 0);
20300 int strict_p = (reload_in_progress || reload_completed);
20302 if (!legitimate_indirect_address_p (addr, strict_p)
20303 && !legitimate_indexed_address_p (addr, strict_p))
20305 addr = force_reg (Pmode, addr);
20306 mem = replace_equiv_address_nv (mem, addr);
20311 case MEMMODEL_RELAXED:
20312 case MEMMODEL_CONSUME:
20313 case MEMMODEL_ACQUIRE:
20315 case MEMMODEL_RELEASE:
20316 case MEMMODEL_ACQ_REL:
20317 emit_insn (gen_lwsync ());
20319 case MEMMODEL_SEQ_CST:
20320 emit_insn (gen_hwsync ());
20323 gcc_unreachable ();
20329 rs6000_post_atomic_barrier (enum memmodel model)
20333 case MEMMODEL_RELAXED:
20334 case MEMMODEL_CONSUME:
20335 case MEMMODEL_RELEASE:
20337 case MEMMODEL_ACQUIRE:
20338 case MEMMODEL_ACQ_REL:
20339 case MEMMODEL_SEQ_CST:
20340 emit_insn (gen_isync ());
20343 gcc_unreachable ();
20347 /* A subroutine of the various atomic expanders. For sub-word operations,
20348 we must adjust things to operate on SImode. Given the original MEM,
20349 return a new aligned memory. Also build and return the quantities by
20350 which to shift and mask. */
20353 rs6000_adjust_atomic_subword (rtx orig_mem, rtx *pshift, rtx *pmask)
20355 rtx addr, align, shift, mask, mem;
20356 HOST_WIDE_INT shift_mask;
20357 machine_mode mode = GET_MODE (orig_mem);
20359 /* For smaller modes, we have to implement this via SImode. */
20360 shift_mask = (mode == QImode ? 0x18 : 0x10);
20362 addr = XEXP (orig_mem, 0);
20363 addr = force_reg (GET_MODE (addr), addr);
20365 /* Aligned memory containing subword. Generate a new memory. We
20366 do not want any of the existing MEM_ATTR data, as we're now
20367 accessing memory outside the original object. */
20368 align = expand_simple_binop (Pmode, AND, addr, GEN_INT (-4),
20369 NULL_RTX, 1, OPTAB_LIB_WIDEN);
20370 mem = gen_rtx_MEM (SImode, align);
20371 MEM_VOLATILE_P (mem) = MEM_VOLATILE_P (orig_mem);
20372 if (MEM_ALIAS_SET (orig_mem) == ALIAS_SET_MEMORY_BARRIER)
20373 set_mem_alias_set (mem, ALIAS_SET_MEMORY_BARRIER);
20375 /* Shift amount for subword relative to aligned word. */
20376 shift = gen_reg_rtx (SImode);
20377 addr = gen_lowpart (SImode, addr);
20378 emit_insn (gen_rlwinm (shift, addr, GEN_INT (3), GEN_INT (shift_mask)));
20379 if (BYTES_BIG_ENDIAN)
20380 shift = expand_simple_binop (SImode, XOR, shift, GEN_INT (shift_mask),
20381 shift, 1, OPTAB_LIB_WIDEN);
20384 /* Mask for insertion. */
20385 mask = expand_simple_binop (SImode, ASHIFT, GEN_INT (GET_MODE_MASK (mode)),
20386 shift, NULL_RTX, 1, OPTAB_LIB_WIDEN);
20392 /* A subroutine of the various atomic expanders. For sub-word operands,
20393 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
20396 rs6000_mask_atomic_subword (rtx oldval, rtx newval, rtx mask)
20400 x = gen_reg_rtx (SImode);
20401 emit_insn (gen_rtx_SET (VOIDmode, x,
20402 gen_rtx_AND (SImode,
20403 gen_rtx_NOT (SImode, mask),
20406 x = expand_simple_binop (SImode, IOR, newval, x, x, 1, OPTAB_LIB_WIDEN);
20411 /* A subroutine of the various atomic expanders. For sub-word operands,
20412 extract WIDE to NARROW via SHIFT. */
20415 rs6000_finish_atomic_subword (rtx narrow, rtx wide, rtx shift)
20417 wide = expand_simple_binop (SImode, LSHIFTRT, wide, shift,
20418 wide, 1, OPTAB_LIB_WIDEN);
20419 emit_move_insn (narrow, gen_lowpart (GET_MODE (narrow), wide));
20422 /* Expand an atomic compare and swap operation. */
20425 rs6000_expand_atomic_compare_and_swap (rtx operands[])
20427 rtx boolval, retval, mem, oldval, newval, cond;
20428 rtx label1, label2, x, mask, shift;
20429 machine_mode mode, orig_mode;
20430 enum memmodel mod_s, mod_f;
20433 boolval = operands[0];
20434 retval = operands[1];
20436 oldval = operands[3];
20437 newval = operands[4];
20438 is_weak = (INTVAL (operands[5]) != 0);
20439 mod_s = (enum memmodel) INTVAL (operands[6]);
20440 mod_f = (enum memmodel) INTVAL (operands[7]);
20441 orig_mode = mode = GET_MODE (mem);
20443 mask = shift = NULL_RTX;
20444 if (mode == QImode || mode == HImode)
20446 /* Before power8, we didn't have access to lbarx/lharx, so generate a
20447 lwarx and shift/mask operations. With power8, we need to do the
20448 comparison in SImode, but the store is still done in QI/HImode. */
20449 oldval = convert_modes (SImode, mode, oldval, 1);
20451 if (!TARGET_SYNC_HI_QI)
20453 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
20455 /* Shift and mask OLDVAL into position with the word. */
20456 oldval = expand_simple_binop (SImode, ASHIFT, oldval, shift,
20457 NULL_RTX, 1, OPTAB_LIB_WIDEN);
20459 /* Shift and mask NEWVAL into position within the word. */
20460 newval = convert_modes (SImode, mode, newval, 1);
20461 newval = expand_simple_binop (SImode, ASHIFT, newval, shift,
20462 NULL_RTX, 1, OPTAB_LIB_WIDEN);
20465 /* Prepare to adjust the return value. */
20466 retval = gen_reg_rtx (SImode);
20469 else if (reg_overlap_mentioned_p (retval, oldval))
20470 oldval = copy_to_reg (oldval);
20472 mem = rs6000_pre_atomic_barrier (mem, mod_s);
20477 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
20478 emit_label (XEXP (label1, 0));
20480 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
20482 emit_load_locked (mode, retval, mem);
20487 x = expand_simple_binop (SImode, AND, retval, mask,
20488 NULL_RTX, 1, OPTAB_LIB_WIDEN);
20491 cond = gen_reg_rtx (CCmode);
20492 /* If we have TImode, synthesize a comparison. */
20493 if (mode != TImode)
20494 x = gen_rtx_COMPARE (CCmode, x, oldval);
20497 rtx xor1_result = gen_reg_rtx (DImode);
20498 rtx xor2_result = gen_reg_rtx (DImode);
20499 rtx or_result = gen_reg_rtx (DImode);
20500 rtx new_word0 = simplify_gen_subreg (DImode, x, TImode, 0);
20501 rtx new_word1 = simplify_gen_subreg (DImode, x, TImode, 8);
20502 rtx old_word0 = simplify_gen_subreg (DImode, oldval, TImode, 0);
20503 rtx old_word1 = simplify_gen_subreg (DImode, oldval, TImode, 8);
20505 emit_insn (gen_xordi3 (xor1_result, new_word0, old_word0));
20506 emit_insn (gen_xordi3 (xor2_result, new_word1, old_word1));
20507 emit_insn (gen_iordi3 (or_result, xor1_result, xor2_result));
20508 x = gen_rtx_COMPARE (CCmode, or_result, const0_rtx);
20511 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
20513 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
20514 emit_unlikely_jump (x, label2);
20518 x = rs6000_mask_atomic_subword (retval, newval, mask);
20520 emit_store_conditional (orig_mode, cond, mem, x);
20524 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
20525 emit_unlikely_jump (x, label1);
20528 if (mod_f != MEMMODEL_RELAXED)
20529 emit_label (XEXP (label2, 0));
20531 rs6000_post_atomic_barrier (mod_s);
20533 if (mod_f == MEMMODEL_RELAXED)
20534 emit_label (XEXP (label2, 0));
20537 rs6000_finish_atomic_subword (operands[1], retval, shift);
20538 else if (mode != GET_MODE (operands[1]))
20539 convert_move (operands[1], retval, 1);
20541 /* In all cases, CR0 contains EQ on success, and NE on failure. */
20542 x = gen_rtx_EQ (SImode, cond, const0_rtx);
20543 emit_insn (gen_rtx_SET (VOIDmode, boolval, x));
20546 /* Expand an atomic exchange operation. */
20549 rs6000_expand_atomic_exchange (rtx operands[])
20551 rtx retval, mem, val, cond;
20553 enum memmodel model;
20554 rtx label, x, mask, shift;
20556 retval = operands[0];
20559 model = (enum memmodel) INTVAL (operands[3]);
20560 mode = GET_MODE (mem);
20562 mask = shift = NULL_RTX;
20563 if (!TARGET_SYNC_HI_QI && (mode == QImode || mode == HImode))
20565 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
20567 /* Shift and mask VAL into position with the word. */
20568 val = convert_modes (SImode, mode, val, 1);
20569 val = expand_simple_binop (SImode, ASHIFT, val, shift,
20570 NULL_RTX, 1, OPTAB_LIB_WIDEN);
20572 /* Prepare to adjust the return value. */
20573 retval = gen_reg_rtx (SImode);
20577 mem = rs6000_pre_atomic_barrier (mem, model);
20579 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
20580 emit_label (XEXP (label, 0));
20582 emit_load_locked (mode, retval, mem);
20586 x = rs6000_mask_atomic_subword (retval, val, mask);
20588 cond = gen_reg_rtx (CCmode);
20589 emit_store_conditional (mode, cond, mem, x);
20591 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
20592 emit_unlikely_jump (x, label);
20594 rs6000_post_atomic_barrier (model);
20597 rs6000_finish_atomic_subword (operands[0], retval, shift);
20600 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
20601 to perform. MEM is the memory on which to operate. VAL is the second
20602 operand of the binary operator. BEFORE and AFTER are optional locations to
20603 return the value of MEM either before of after the operation. MODEL_RTX
20604 is a CONST_INT containing the memory model to use. */
20607 rs6000_expand_atomic_op (enum rtx_code code, rtx mem, rtx val,
20608 rtx orig_before, rtx orig_after, rtx model_rtx)
20610 enum memmodel model = (enum memmodel) INTVAL (model_rtx);
20611 machine_mode mode = GET_MODE (mem);
20612 machine_mode store_mode = mode;
20613 rtx label, x, cond, mask, shift;
20614 rtx before = orig_before, after = orig_after;
20616 mask = shift = NULL_RTX;
20617 /* On power8, we want to use SImode for the operation. On previous systems,
20618 use the operation in a subword and shift/mask to get the proper byte or
20620 if (mode == QImode || mode == HImode)
20622 if (TARGET_SYNC_HI_QI)
20624 val = convert_modes (SImode, mode, val, 1);
20626 /* Prepare to adjust the return value. */
20627 before = gen_reg_rtx (SImode);
20629 after = gen_reg_rtx (SImode);
20634 mem = rs6000_adjust_atomic_subword (mem, &shift, &mask);
20636 /* Shift and mask VAL into position with the word. */
20637 val = convert_modes (SImode, mode, val, 1);
20638 val = expand_simple_binop (SImode, ASHIFT, val, shift,
20639 NULL_RTX, 1, OPTAB_LIB_WIDEN);
20645 /* We've already zero-extended VAL. That is sufficient to
20646 make certain that it does not affect other bits. */
20651 /* If we make certain that all of the other bits in VAL are
20652 set, that will be sufficient to not affect other bits. */
20653 x = gen_rtx_NOT (SImode, mask);
20654 x = gen_rtx_IOR (SImode, x, val);
20655 emit_insn (gen_rtx_SET (VOIDmode, val, x));
20662 /* These will all affect bits outside the field and need
20663 adjustment via MASK within the loop. */
20667 gcc_unreachable ();
20670 /* Prepare to adjust the return value. */
20671 before = gen_reg_rtx (SImode);
20673 after = gen_reg_rtx (SImode);
20674 store_mode = mode = SImode;
20678 mem = rs6000_pre_atomic_barrier (mem, model);
20680 label = gen_label_rtx ();
20681 emit_label (label);
20682 label = gen_rtx_LABEL_REF (VOIDmode, label);
20684 if (before == NULL_RTX)
20685 before = gen_reg_rtx (mode);
20687 emit_load_locked (mode, before, mem);
20691 x = expand_simple_binop (mode, AND, before, val,
20692 NULL_RTX, 1, OPTAB_LIB_WIDEN);
20693 after = expand_simple_unop (mode, NOT, x, after, 1);
20697 after = expand_simple_binop (mode, code, before, val,
20698 after, 1, OPTAB_LIB_WIDEN);
20704 x = expand_simple_binop (SImode, AND, after, mask,
20705 NULL_RTX, 1, OPTAB_LIB_WIDEN);
20706 x = rs6000_mask_atomic_subword (before, x, mask);
20708 else if (store_mode != mode)
20709 x = convert_modes (store_mode, mode, x, 1);
20711 cond = gen_reg_rtx (CCmode);
20712 emit_store_conditional (store_mode, cond, mem, x);
20714 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
20715 emit_unlikely_jump (x, label);
20717 rs6000_post_atomic_barrier (model);
20721 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
20722 then do the calcuations in a SImode register. */
20724 rs6000_finish_atomic_subword (orig_before, before, shift);
20726 rs6000_finish_atomic_subword (orig_after, after, shift);
20728 else if (store_mode != mode)
20730 /* QImode/HImode on machines with lbarx/lharx where we do the native
20731 operation and then do the calcuations in a SImode register. */
20733 convert_move (orig_before, before, 1);
20735 convert_move (orig_after, after, 1);
20737 else if (orig_after && after != orig_after)
20738 emit_move_insn (orig_after, after);
20741 /* Emit instructions to move SRC to DST. Called by splitters for
20742 multi-register moves. It will emit at most one instruction for
20743 each register that is accessed; that is, it won't emit li/lis pairs
20744 (or equivalent for 64-bit code). One of SRC or DST must be a hard
20748 rs6000_split_multireg_move (rtx dst, rtx src)
20750 /* The register number of the first register being moved. */
20752 /* The mode that is to be moved. */
20754 /* The mode that the move is being done in, and its size. */
20755 machine_mode reg_mode;
20757 /* The number of registers that will be moved. */
20760 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
20761 mode = GET_MODE (dst);
20762 nregs = hard_regno_nregs[reg][mode];
20763 if (FP_REGNO_P (reg))
20764 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode :
20765 ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT) ? DFmode : SFmode);
20766 else if (ALTIVEC_REGNO_P (reg))
20767 reg_mode = V16QImode;
20768 else if (TARGET_E500_DOUBLE && mode == TFmode)
20771 reg_mode = word_mode;
20772 reg_mode_size = GET_MODE_SIZE (reg_mode);
20774 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
20776 /* TDmode residing in FP registers is special, since the ISA requires that
20777 the lower-numbered word of a register pair is always the most significant
20778 word, even in little-endian mode. This does not match the usual subreg
20779 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
20780 the appropriate constituent registers "by hand" in little-endian mode.
20782 Note we do not need to check for destructive overlap here since TDmode
20783 can only reside in even/odd register pairs. */
20784 if (FP_REGNO_P (reg) && DECIMAL_FLOAT_MODE_P (mode) && !BYTES_BIG_ENDIAN)
20789 for (i = 0; i < nregs; i++)
20791 if (REG_P (src) && FP_REGNO_P (REGNO (src)))
20792 p_src = gen_rtx_REG (reg_mode, REGNO (src) + nregs - 1 - i);
20794 p_src = simplify_gen_subreg (reg_mode, src, mode,
20795 i * reg_mode_size);
20797 if (REG_P (dst) && FP_REGNO_P (REGNO (dst)))
20798 p_dst = gen_rtx_REG (reg_mode, REGNO (dst) + nregs - 1 - i);
20800 p_dst = simplify_gen_subreg (reg_mode, dst, mode,
20801 i * reg_mode_size);
20803 emit_insn (gen_rtx_SET (VOIDmode, p_dst, p_src));
20809 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
20811 /* Move register range backwards, if we might have destructive
20814 for (i = nregs - 1; i >= 0; i--)
20815 emit_insn (gen_rtx_SET (VOIDmode,
20816 simplify_gen_subreg (reg_mode, dst, mode,
20817 i * reg_mode_size),
20818 simplify_gen_subreg (reg_mode, src, mode,
20819 i * reg_mode_size)));
20825 bool used_update = false;
20826 rtx restore_basereg = NULL_RTX;
20828 if (MEM_P (src) && INT_REGNO_P (reg))
20832 if (GET_CODE (XEXP (src, 0)) == PRE_INC
20833 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
20836 breg = XEXP (XEXP (src, 0), 0);
20837 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
20838 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
20839 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
20840 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
20841 src = replace_equiv_address (src, breg);
20843 else if (! rs6000_offsettable_memref_p (src, reg_mode))
20845 if (GET_CODE (XEXP (src, 0)) == PRE_MODIFY)
20847 rtx basereg = XEXP (XEXP (src, 0), 0);
20850 rtx ndst = simplify_gen_subreg (reg_mode, dst, mode, 0);
20851 emit_insn (gen_rtx_SET (VOIDmode, ndst,
20852 gen_rtx_MEM (reg_mode, XEXP (src, 0))));
20853 used_update = true;
20856 emit_insn (gen_rtx_SET (VOIDmode, basereg,
20857 XEXP (XEXP (src, 0), 1)));
20858 src = replace_equiv_address (src, basereg);
20862 rtx basereg = gen_rtx_REG (Pmode, reg);
20863 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
20864 src = replace_equiv_address (src, basereg);
20868 breg = XEXP (src, 0);
20869 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
20870 breg = XEXP (breg, 0);
20872 /* If the base register we are using to address memory is
20873 also a destination reg, then change that register last. */
20875 && REGNO (breg) >= REGNO (dst)
20876 && REGNO (breg) < REGNO (dst) + nregs)
20877 j = REGNO (breg) - REGNO (dst);
20879 else if (MEM_P (dst) && INT_REGNO_P (reg))
20883 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
20884 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
20887 breg = XEXP (XEXP (dst, 0), 0);
20888 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
20889 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
20890 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
20892 /* We have to update the breg before doing the store.
20893 Use store with update, if available. */
20897 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
20898 emit_insn (TARGET_32BIT
20899 ? (TARGET_POWERPC64
20900 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
20901 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
20902 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
20903 used_update = true;
20906 emit_insn (gen_add3_insn (breg, breg, delta_rtx));
20907 dst = replace_equiv_address (dst, breg);
20909 else if (!rs6000_offsettable_memref_p (dst, reg_mode)
20910 && GET_CODE (XEXP (dst, 0)) != LO_SUM)
20912 if (GET_CODE (XEXP (dst, 0)) == PRE_MODIFY)
20914 rtx basereg = XEXP (XEXP (dst, 0), 0);
20917 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
20918 emit_insn (gen_rtx_SET (VOIDmode,
20919 gen_rtx_MEM (reg_mode, XEXP (dst, 0)), nsrc));
20920 used_update = true;
20923 emit_insn (gen_rtx_SET (VOIDmode, basereg,
20924 XEXP (XEXP (dst, 0), 1)));
20925 dst = replace_equiv_address (dst, basereg);
20929 rtx basereg = XEXP (XEXP (dst, 0), 0);
20930 rtx offsetreg = XEXP (XEXP (dst, 0), 1);
20931 gcc_assert (GET_CODE (XEXP (dst, 0)) == PLUS
20933 && REG_P (offsetreg)
20934 && REGNO (basereg) != REGNO (offsetreg));
20935 if (REGNO (basereg) == 0)
20937 rtx tmp = offsetreg;
20938 offsetreg = basereg;
20941 emit_insn (gen_add3_insn (basereg, basereg, offsetreg));
20942 restore_basereg = gen_sub3_insn (basereg, basereg, offsetreg);
20943 dst = replace_equiv_address (dst, basereg);
20946 else if (GET_CODE (XEXP (dst, 0)) != LO_SUM)
20947 gcc_assert (rs6000_offsettable_memref_p (dst, reg_mode));
20950 for (i = 0; i < nregs; i++)
20952 /* Calculate index to next subword. */
20957 /* If compiler already emitted move of first word by
20958 store with update, no need to do anything. */
20959 if (j == 0 && used_update)
20962 emit_insn (gen_rtx_SET (VOIDmode,
20963 simplify_gen_subreg (reg_mode, dst, mode,
20964 j * reg_mode_size),
20965 simplify_gen_subreg (reg_mode, src, mode,
20966 j * reg_mode_size)));
20968 if (restore_basereg != NULL_RTX)
20969 emit_insn (restore_basereg);
20974 /* This page contains routines that are used to determine what the
20975 function prologue and epilogue code will do and write them out. */
20980 return !call_used_regs[r] && df_regs_ever_live_p (r);
20983 /* Return the first fixed-point register that is required to be
20984 saved. 32 if none. */
20987 first_reg_to_save (void)
20991 /* Find lowest numbered live register. */
20992 for (first_reg = 13; first_reg <= 31; first_reg++)
20993 if (save_reg_p (first_reg))
20996 if (first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM
20997 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
20998 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
20999 || (TARGET_TOC && TARGET_MINIMAL_TOC))
21000 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
21001 first_reg = RS6000_PIC_OFFSET_TABLE_REGNUM;
21005 && crtl->uses_pic_offset_table
21006 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
21007 return RS6000_PIC_OFFSET_TABLE_REGNUM;
21013 /* Similar, for FP regs. */
21016 first_fp_reg_to_save (void)
21020 /* Find lowest numbered live register. */
21021 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
21022 if (save_reg_p (first_reg))
21028 /* Similar, for AltiVec regs. */
21031 first_altivec_reg_to_save (void)
21035 /* Stack frame remains as is unless we are in AltiVec ABI. */
21036 if (! TARGET_ALTIVEC_ABI)
21037 return LAST_ALTIVEC_REGNO + 1;
21039 /* On Darwin, the unwind routines are compiled without
21040 TARGET_ALTIVEC, and use save_world to save/restore the
21041 altivec registers when necessary. */
21042 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
21043 && ! TARGET_ALTIVEC)
21044 return FIRST_ALTIVEC_REGNO + 20;
21046 /* Find lowest numbered live register. */
21047 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
21048 if (save_reg_p (i))
21054 /* Return a 32-bit mask of the AltiVec registers we need to set in
21055 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
21056 the 32-bit word is 0. */
21058 static unsigned int
21059 compute_vrsave_mask (void)
21061 unsigned int i, mask = 0;
21063 /* On Darwin, the unwind routines are compiled without
21064 TARGET_ALTIVEC, and use save_world to save/restore the
21065 call-saved altivec registers when necessary. */
21066 if (DEFAULT_ABI == ABI_DARWIN && crtl->calls_eh_return
21067 && ! TARGET_ALTIVEC)
21070 /* First, find out if we use _any_ altivec registers. */
21071 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
21072 if (df_regs_ever_live_p (i))
21073 mask |= ALTIVEC_REG_BIT (i);
21078 /* Next, remove the argument registers from the set. These must
21079 be in the VRSAVE mask set by the caller, so we don't need to add
21080 them in again. More importantly, the mask we compute here is
21081 used to generate CLOBBERs in the set_vrsave insn, and we do not
21082 wish the argument registers to die. */
21083 for (i = crtl->args.info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
21084 mask &= ~ALTIVEC_REG_BIT (i);
21086 /* Similarly, remove the return value from the set. */
21089 diddle_return_value (is_altivec_return_reg, &yes);
21091 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
21097 /* For a very restricted set of circumstances, we can cut down the
21098 size of prologues/epilogues by calling our own save/restore-the-world
21102 compute_save_world_info (rs6000_stack_t *info_ptr)
21104 info_ptr->world_save_p = 1;
21105 info_ptr->world_save_p
21106 = (WORLD_SAVE_P (info_ptr)
21107 && DEFAULT_ABI == ABI_DARWIN
21108 && !cfun->has_nonlocal_label
21109 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
21110 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
21111 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
21112 && info_ptr->cr_save_p);
21114 /* This will not work in conjunction with sibcalls. Make sure there
21115 are none. (This check is expensive, but seldom executed.) */
21116 if (WORLD_SAVE_P (info_ptr))
21119 for (insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
21120 if (CALL_P (insn) && SIBLING_CALL_P (insn))
21122 info_ptr->world_save_p = 0;
21127 if (WORLD_SAVE_P (info_ptr))
21129 /* Even if we're not touching VRsave, make sure there's room on the
21130 stack for it, if it looks like we're calling SAVE_WORLD, which
21131 will attempt to save it. */
21132 info_ptr->vrsave_size = 4;
21134 /* If we are going to save the world, we need to save the link register too. */
21135 info_ptr->lr_save_p = 1;
21137 /* "Save" the VRsave register too if we're saving the world. */
21138 if (info_ptr->vrsave_mask == 0)
21139 info_ptr->vrsave_mask = compute_vrsave_mask ();
21141 /* Because the Darwin register save/restore routines only handle
21142 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
21144 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
21145 && (info_ptr->first_altivec_reg_save
21146 >= FIRST_SAVED_ALTIVEC_REGNO));
21153 is_altivec_return_reg (rtx reg, void *xyes)
21155 bool *yes = (bool *) xyes;
21156 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
21161 /* Look for user-defined global regs in the range FIRST to LAST-1.
21162 We should not restore these, and so cannot use lmw or out-of-line
21163 restore functions if there are any. We also can't save them
21164 (well, emit frame notes for them), because frame unwinding during
21165 exception handling will restore saved registers. */
21168 global_regs_p (unsigned first, unsigned last)
21170 while (first < last)
21171 if (global_regs[first++])
21176 /* Determine the strategy for savings/restoring registers. */
21179 SAVRES_MULTIPLE = 0x1,
21180 SAVE_INLINE_FPRS = 0x2,
21181 SAVE_INLINE_GPRS = 0x4,
21182 REST_INLINE_FPRS = 0x8,
21183 REST_INLINE_GPRS = 0x10,
21184 SAVE_NOINLINE_GPRS_SAVES_LR = 0x20,
21185 SAVE_NOINLINE_FPRS_SAVES_LR = 0x40,
21186 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR = 0x80,
21187 SAVE_INLINE_VRS = 0x100,
21188 REST_INLINE_VRS = 0x200
21192 rs6000_savres_strategy (rs6000_stack_t *info,
21193 bool using_static_chain_p)
21198 if (TARGET_MULTIPLE
21199 && !TARGET_POWERPC64
21200 && !(TARGET_SPE_ABI && info->spe_64bit_regs_used)
21201 && info->first_gp_reg_save < 31
21202 && !global_regs_p (info->first_gp_reg_save, 32))
21203 strategy |= SAVRES_MULTIPLE;
21205 if (crtl->calls_eh_return
21206 || cfun->machine->ra_need_lr)
21207 strategy |= (SAVE_INLINE_FPRS | REST_INLINE_FPRS
21208 | SAVE_INLINE_GPRS | REST_INLINE_GPRS
21209 | SAVE_INLINE_VRS | REST_INLINE_VRS);
21211 if (info->first_fp_reg_save == 64
21212 /* The out-of-line FP routines use double-precision stores;
21213 we can't use those routines if we don't have such stores. */
21214 || (TARGET_HARD_FLOAT && !TARGET_DOUBLE_FLOAT)
21215 || global_regs_p (info->first_fp_reg_save, 64))
21216 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
21218 if (info->first_gp_reg_save == 32
21219 || (!(strategy & SAVRES_MULTIPLE)
21220 && global_regs_p (info->first_gp_reg_save, 32)))
21221 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
21223 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
21224 || global_regs_p (info->first_altivec_reg_save, LAST_ALTIVEC_REGNO + 1))
21225 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
21227 /* Define cutoff for using out-of-line functions to save registers. */
21228 if (DEFAULT_ABI == ABI_V4 || TARGET_ELF)
21230 if (!optimize_size)
21232 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
21233 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
21234 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
21238 /* Prefer out-of-line restore if it will exit. */
21239 if (info->first_fp_reg_save > 61)
21240 strategy |= SAVE_INLINE_FPRS;
21241 if (info->first_gp_reg_save > 29)
21243 if (info->first_fp_reg_save == 64)
21244 strategy |= SAVE_INLINE_GPRS;
21246 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
21248 if (info->first_altivec_reg_save == LAST_ALTIVEC_REGNO)
21249 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
21252 else if (DEFAULT_ABI == ABI_DARWIN)
21254 if (info->first_fp_reg_save > 60)
21255 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
21256 if (info->first_gp_reg_save > 29)
21257 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
21258 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
21262 gcc_checking_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
21263 if (info->first_fp_reg_save > 61)
21264 strategy |= SAVE_INLINE_FPRS | REST_INLINE_FPRS;
21265 strategy |= SAVE_INLINE_GPRS | REST_INLINE_GPRS;
21266 strategy |= SAVE_INLINE_VRS | REST_INLINE_VRS;
21269 /* Don't bother to try to save things out-of-line if r11 is occupied
21270 by the static chain. It would require too much fiddling and the
21271 static chain is rarely used anyway. FPRs are saved w.r.t the stack
21272 pointer on Darwin, and AIX uses r1 or r12. */
21273 if (using_static_chain_p
21274 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN))
21275 strategy |= ((DEFAULT_ABI == ABI_DARWIN ? 0 : SAVE_INLINE_FPRS)
21277 | SAVE_INLINE_VRS | REST_INLINE_VRS);
21279 /* We can only use the out-of-line routines to restore if we've
21280 saved all the registers from first_fp_reg_save in the prologue.
21281 Otherwise, we risk loading garbage. */
21282 if ((strategy & (SAVE_INLINE_FPRS | REST_INLINE_FPRS)) == SAVE_INLINE_FPRS)
21286 for (i = info->first_fp_reg_save; i < 64; i++)
21287 if (!save_reg_p (i))
21289 strategy |= REST_INLINE_FPRS;
21294 /* If we are going to use store multiple, then don't even bother
21295 with the out-of-line routines, since the store-multiple
21296 instruction will always be smaller. */
21297 if ((strategy & SAVRES_MULTIPLE))
21298 strategy |= SAVE_INLINE_GPRS;
21300 /* info->lr_save_p isn't yet set if the only reason lr needs to be
21301 saved is an out-of-line save or restore. Set up the value for
21302 the next test (excluding out-of-line gpr restore). */
21303 lr_save_p = (info->lr_save_p
21304 || !(strategy & SAVE_INLINE_GPRS)
21305 || !(strategy & SAVE_INLINE_FPRS)
21306 || !(strategy & SAVE_INLINE_VRS)
21307 || !(strategy & REST_INLINE_FPRS)
21308 || !(strategy & REST_INLINE_VRS));
21310 /* The situation is more complicated with load multiple. We'd
21311 prefer to use the out-of-line routines for restores, since the
21312 "exit" out-of-line routines can handle the restore of LR and the
21313 frame teardown. However if doesn't make sense to use the
21314 out-of-line routine if that is the only reason we'd need to save
21315 LR, and we can't use the "exit" out-of-line gpr restore if we
21316 have saved some fprs; In those cases it is advantageous to use
21317 load multiple when available. */
21318 if ((strategy & SAVRES_MULTIPLE)
21320 || info->first_fp_reg_save != 64))
21321 strategy |= REST_INLINE_GPRS;
21323 /* Saving CR interferes with the exit routines used on the SPE, so
21326 && info->spe_64bit_regs_used
21327 && info->cr_save_p)
21328 strategy |= REST_INLINE_GPRS;
21330 /* We can only use load multiple or the out-of-line routines to
21331 restore if we've used store multiple or out-of-line routines
21332 in the prologue, i.e. if we've saved all the registers from
21333 first_gp_reg_save. Otherwise, we risk loading garbage. */
21334 if ((strategy & (SAVE_INLINE_GPRS | REST_INLINE_GPRS | SAVRES_MULTIPLE))
21335 == SAVE_INLINE_GPRS)
21339 for (i = info->first_gp_reg_save; i < 32; i++)
21340 if (!save_reg_p (i))
21342 strategy |= REST_INLINE_GPRS;
21347 if (TARGET_ELF && TARGET_64BIT)
21349 if (!(strategy & SAVE_INLINE_FPRS))
21350 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
21351 else if (!(strategy & SAVE_INLINE_GPRS)
21352 && info->first_fp_reg_save == 64)
21353 strategy |= SAVE_NOINLINE_GPRS_SAVES_LR;
21355 else if (TARGET_AIX && !(strategy & REST_INLINE_FPRS))
21356 strategy |= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR;
21358 if (TARGET_MACHO && !(strategy & SAVE_INLINE_FPRS))
21359 strategy |= SAVE_NOINLINE_FPRS_SAVES_LR;
21364 /* Calculate the stack information for the current function. This is
21365 complicated by having two separate calling sequences, the AIX calling
21366 sequence and the V.4 calling sequence.
21368 AIX (and Darwin/Mac OS X) stack frames look like:
21370 SP----> +---------------------------------------+
21371 | back chain to caller | 0 0
21372 +---------------------------------------+
21373 | saved CR | 4 8 (8-11)
21374 +---------------------------------------+
21376 +---------------------------------------+
21377 | reserved for compilers | 12 24
21378 +---------------------------------------+
21379 | reserved for binders | 16 32
21380 +---------------------------------------+
21381 | saved TOC pointer | 20 40
21382 +---------------------------------------+
21383 | Parameter save area (P) | 24 48
21384 +---------------------------------------+
21385 | Alloca space (A) | 24+P etc.
21386 +---------------------------------------+
21387 | Local variable space (L) | 24+P+A
21388 +---------------------------------------+
21389 | Float/int conversion temporary (X) | 24+P+A+L
21390 +---------------------------------------+
21391 | Save area for AltiVec registers (W) | 24+P+A+L+X
21392 +---------------------------------------+
21393 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
21394 +---------------------------------------+
21395 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
21396 +---------------------------------------+
21397 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
21398 +---------------------------------------+
21399 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
21400 +---------------------------------------+
21401 old SP->| back chain to caller's caller |
21402 +---------------------------------------+
21404 The required alignment for AIX configurations is two words (i.e., 8
21407 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
21409 SP----> +---------------------------------------+
21410 | Back chain to caller | 0
21411 +---------------------------------------+
21412 | Save area for CR | 8
21413 +---------------------------------------+
21415 +---------------------------------------+
21416 | Saved TOC pointer | 24
21417 +---------------------------------------+
21418 | Parameter save area (P) | 32
21419 +---------------------------------------+
21420 | Alloca space (A) | 32+P
21421 +---------------------------------------+
21422 | Local variable space (L) | 32+P+A
21423 +---------------------------------------+
21424 | Save area for AltiVec registers (W) | 32+P+A+L
21425 +---------------------------------------+
21426 | AltiVec alignment padding (Y) | 32+P+A+L+W
21427 +---------------------------------------+
21428 | Save area for GP registers (G) | 32+P+A+L+W+Y
21429 +---------------------------------------+
21430 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
21431 +---------------------------------------+
21432 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
21433 +---------------------------------------+
21436 V.4 stack frames look like:
21438 SP----> +---------------------------------------+
21439 | back chain to caller | 0
21440 +---------------------------------------+
21441 | caller's saved LR | 4
21442 +---------------------------------------+
21443 | Parameter save area (P) | 8
21444 +---------------------------------------+
21445 | Alloca space (A) | 8+P
21446 +---------------------------------------+
21447 | Varargs save area (V) | 8+P+A
21448 +---------------------------------------+
21449 | Local variable space (L) | 8+P+A+V
21450 +---------------------------------------+
21451 | Float/int conversion temporary (X) | 8+P+A+V+L
21452 +---------------------------------------+
21453 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
21454 +---------------------------------------+
21455 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
21456 +---------------------------------------+
21457 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
21458 +---------------------------------------+
21459 | SPE: area for 64-bit GP registers |
21460 +---------------------------------------+
21461 | SPE alignment padding |
21462 +---------------------------------------+
21463 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
21464 +---------------------------------------+
21465 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
21466 +---------------------------------------+
21467 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
21468 +---------------------------------------+
21469 old SP->| back chain to caller's caller |
21470 +---------------------------------------+
21472 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
21473 given. (But note below and in sysv4.h that we require only 8 and
21474 may round up the size of our stack frame anyways. The historical
21475 reason is early versions of powerpc-linux which didn't properly
21476 align the stack at program startup. A happy side-effect is that
21477 -mno-eabi libraries can be used with -meabi programs.)
21479 The EABI configuration defaults to the V.4 layout. However,
21480 the stack alignment requirements may differ. If -mno-eabi is not
21481 given, the required stack alignment is 8 bytes; if -mno-eabi is
21482 given, the required alignment is 16 bytes. (But see V.4 comment
21485 #ifndef ABI_STACK_BOUNDARY
21486 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
21489 static rs6000_stack_t *
21490 rs6000_stack_info (void)
21492 rs6000_stack_t *info_ptr = &stack_info;
21493 int reg_size = TARGET_32BIT ? 4 : 8;
21498 HOST_WIDE_INT non_fixed_size;
21499 bool using_static_chain_p;
21501 if (reload_completed && info_ptr->reload_completed)
21504 memset (info_ptr, 0, sizeof (*info_ptr));
21505 info_ptr->reload_completed = reload_completed;
21509 /* Cache value so we don't rescan instruction chain over and over. */
21510 if (cfun->machine->insn_chain_scanned_p == 0)
21511 cfun->machine->insn_chain_scanned_p
21512 = spe_func_has_64bit_regs_p () + 1;
21513 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
21516 /* Select which calling sequence. */
21517 info_ptr->abi = DEFAULT_ABI;
21519 /* Calculate which registers need to be saved & save area size. */
21520 info_ptr->first_gp_reg_save = first_reg_to_save ();
21521 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
21522 even if it currently looks like we won't. Reload may need it to
21523 get at a constant; if so, it will have already created a constant
21524 pool entry for it. */
21525 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
21526 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
21527 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
21528 && crtl->uses_const_pool
21529 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
21530 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
21532 first_gp = info_ptr->first_gp_reg_save;
21534 info_ptr->gp_size = reg_size * (32 - first_gp);
21536 /* For the SPE, we have an additional upper 32-bits on each GPR.
21537 Ideally we should save the entire 64-bits only when the upper
21538 half is used in SIMD instructions. Since we only record
21539 registers live (not the size they are used in), this proves
21540 difficult because we'd have to traverse the instruction chain at
21541 the right time, taking reload into account. This is a real pain,
21542 so we opt to save the GPRs in 64-bits always if but one register
21543 gets used in 64-bits. Otherwise, all the registers in the frame
21544 get saved in 32-bits.
21546 So... since when we save all GPRs (except the SP) in 64-bits, the
21547 traditional GP save area will be empty. */
21548 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
21549 info_ptr->gp_size = 0;
21551 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
21552 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
21554 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
21555 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
21556 - info_ptr->first_altivec_reg_save);
21558 /* Does this function call anything? */
21559 info_ptr->calls_p = (! crtl->is_leaf
21560 || cfun->machine->ra_needs_full_frame);
21562 /* Determine if we need to save the condition code registers. */
21563 if (df_regs_ever_live_p (CR2_REGNO)
21564 || df_regs_ever_live_p (CR3_REGNO)
21565 || df_regs_ever_live_p (CR4_REGNO))
21567 info_ptr->cr_save_p = 1;
21568 if (DEFAULT_ABI == ABI_V4)
21569 info_ptr->cr_size = reg_size;
21572 /* If the current function calls __builtin_eh_return, then we need
21573 to allocate stack space for registers that will hold data for
21574 the exception handler. */
21575 if (crtl->calls_eh_return)
21578 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
21581 /* SPE saves EH registers in 64-bits. */
21582 ehrd_size = i * (TARGET_SPE_ABI
21583 && info_ptr->spe_64bit_regs_used != 0
21584 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
21589 /* In the ELFv2 ABI, we also need to allocate space for separate
21590 CR field save areas if the function calls __builtin_eh_return. */
21591 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
21593 /* This hard-codes that we have three call-saved CR fields. */
21594 ehcr_size = 3 * reg_size;
21595 /* We do *not* use the regular CR save mechanism. */
21596 info_ptr->cr_save_p = 0;
21601 /* Determine various sizes. */
21602 info_ptr->reg_size = reg_size;
21603 info_ptr->fixed_size = RS6000_SAVE_AREA;
21604 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
21605 info_ptr->parm_size = RS6000_ALIGN (crtl->outgoing_args_size,
21606 TARGET_ALTIVEC ? 16 : 8);
21607 if (FRAME_GROWS_DOWNWARD)
21608 info_ptr->vars_size
21609 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
21610 + info_ptr->parm_size,
21611 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
21612 - (info_ptr->fixed_size + info_ptr->vars_size
21613 + info_ptr->parm_size);
21615 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
21616 info_ptr->spe_gp_size = 8 * (32 - first_gp);
21618 info_ptr->spe_gp_size = 0;
21620 if (TARGET_ALTIVEC_ABI)
21621 info_ptr->vrsave_mask = compute_vrsave_mask ();
21623 info_ptr->vrsave_mask = 0;
21625 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
21626 info_ptr->vrsave_size = 4;
21628 info_ptr->vrsave_size = 0;
21630 compute_save_world_info (info_ptr);
21632 /* Calculate the offsets. */
21633 switch (DEFAULT_ABI)
21637 gcc_unreachable ();
21642 info_ptr->fp_save_offset = - info_ptr->fp_size;
21643 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
21645 if (TARGET_ALTIVEC_ABI)
21647 info_ptr->vrsave_save_offset
21648 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
21650 /* Align stack so vector save area is on a quadword boundary.
21651 The padding goes above the vectors. */
21652 if (info_ptr->altivec_size != 0)
21653 info_ptr->altivec_padding_size
21654 = info_ptr->vrsave_save_offset & 0xF;
21656 info_ptr->altivec_padding_size = 0;
21658 info_ptr->altivec_save_offset
21659 = info_ptr->vrsave_save_offset
21660 - info_ptr->altivec_padding_size
21661 - info_ptr->altivec_size;
21662 gcc_assert (info_ptr->altivec_size == 0
21663 || info_ptr->altivec_save_offset % 16 == 0);
21665 /* Adjust for AltiVec case. */
21666 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
21669 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
21671 info_ptr->ehcr_offset = info_ptr->ehrd_offset - ehcr_size;
21672 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
21673 info_ptr->lr_save_offset = 2*reg_size;
21677 info_ptr->fp_save_offset = - info_ptr->fp_size;
21678 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
21679 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
21681 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
21683 /* Align stack so SPE GPR save area is aligned on a
21684 double-word boundary. */
21685 if (info_ptr->spe_gp_size != 0 && info_ptr->cr_save_offset != 0)
21686 info_ptr->spe_padding_size
21687 = 8 - (-info_ptr->cr_save_offset % 8);
21689 info_ptr->spe_padding_size = 0;
21691 info_ptr->spe_gp_save_offset
21692 = info_ptr->cr_save_offset
21693 - info_ptr->spe_padding_size
21694 - info_ptr->spe_gp_size;
21696 /* Adjust for SPE case. */
21697 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
21699 else if (TARGET_ALTIVEC_ABI)
21701 info_ptr->vrsave_save_offset
21702 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
21704 /* Align stack so vector save area is on a quadword boundary. */
21705 if (info_ptr->altivec_size != 0)
21706 info_ptr->altivec_padding_size
21707 = 16 - (-info_ptr->vrsave_save_offset % 16);
21709 info_ptr->altivec_padding_size = 0;
21711 info_ptr->altivec_save_offset
21712 = info_ptr->vrsave_save_offset
21713 - info_ptr->altivec_padding_size
21714 - info_ptr->altivec_size;
21716 /* Adjust for AltiVec case. */
21717 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
21720 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
21721 info_ptr->ehrd_offset -= ehrd_size;
21722 info_ptr->lr_save_offset = reg_size;
21726 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
21727 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
21728 + info_ptr->gp_size
21729 + info_ptr->altivec_size
21730 + info_ptr->altivec_padding_size
21731 + info_ptr->spe_gp_size
21732 + info_ptr->spe_padding_size
21735 + info_ptr->cr_size
21736 + info_ptr->vrsave_size,
21739 non_fixed_size = (info_ptr->vars_size
21740 + info_ptr->parm_size
21741 + info_ptr->save_size);
21743 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
21744 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
21746 /* Determine if we need to save the link register. */
21747 if (info_ptr->calls_p
21748 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
21750 && !TARGET_PROFILE_KERNEL)
21751 || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca)
21752 #ifdef TARGET_RELOCATABLE
21753 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
21755 || rs6000_ra_ever_killed ())
21756 info_ptr->lr_save_p = 1;
21758 using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
21759 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
21760 && call_used_regs[STATIC_CHAIN_REGNUM]);
21761 info_ptr->savres_strategy = rs6000_savres_strategy (info_ptr,
21762 using_static_chain_p);
21764 if (!(info_ptr->savres_strategy & SAVE_INLINE_GPRS)
21765 || !(info_ptr->savres_strategy & SAVE_INLINE_FPRS)
21766 || !(info_ptr->savres_strategy & SAVE_INLINE_VRS)
21767 || !(info_ptr->savres_strategy & REST_INLINE_GPRS)
21768 || !(info_ptr->savres_strategy & REST_INLINE_FPRS)
21769 || !(info_ptr->savres_strategy & REST_INLINE_VRS))
21770 info_ptr->lr_save_p = 1;
21772 if (info_ptr->lr_save_p)
21773 df_set_regs_ever_live (LR_REGNO, true);
21775 /* Determine if we need to allocate any stack frame:
21777 For AIX we need to push the stack if a frame pointer is needed
21778 (because the stack might be dynamically adjusted), if we are
21779 debugging, if we make calls, or if the sum of fp_save, gp_save,
21780 and local variables are more than the space needed to save all
21781 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
21782 + 18*8 = 288 (GPR13 reserved).
21784 For V.4 we don't have the stack cushion that AIX uses, but assume
21785 that the debugger can handle stackless frames. */
21787 if (info_ptr->calls_p)
21788 info_ptr->push_p = 1;
21790 else if (DEFAULT_ABI == ABI_V4)
21791 info_ptr->push_p = non_fixed_size != 0;
21793 else if (frame_pointer_needed)
21794 info_ptr->push_p = 1;
21796 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
21797 info_ptr->push_p = 1;
21800 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
21802 /* Zero offsets if we're not saving those registers. */
21803 if (info_ptr->fp_size == 0)
21804 info_ptr->fp_save_offset = 0;
21806 if (info_ptr->gp_size == 0)
21807 info_ptr->gp_save_offset = 0;
21809 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
21810 info_ptr->altivec_save_offset = 0;
21812 /* Zero VRSAVE offset if not saved and restored. */
21813 if (! TARGET_ALTIVEC_VRSAVE || info_ptr->vrsave_mask == 0)
21814 info_ptr->vrsave_save_offset = 0;
21816 if (! TARGET_SPE_ABI
21817 || info_ptr->spe_64bit_regs_used == 0
21818 || info_ptr->spe_gp_size == 0)
21819 info_ptr->spe_gp_save_offset = 0;
21821 if (! info_ptr->lr_save_p)
21822 info_ptr->lr_save_offset = 0;
21824 if (! info_ptr->cr_save_p)
21825 info_ptr->cr_save_offset = 0;
21830 /* Return true if the current function uses any GPRs in 64-bit SIMD
21834 spe_func_has_64bit_regs_p (void)
21836 rtx_insn *insns, *insn;
21838 /* Functions that save and restore all the call-saved registers will
21839 need to save/restore the registers in 64-bits. */
21840 if (crtl->calls_eh_return
21841 || cfun->calls_setjmp
21842 || crtl->has_nonlocal_goto)
21845 insns = get_insns ();
21847 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
21853 /* FIXME: This should be implemented with attributes...
21855 (set_attr "spe64" "true")....then,
21856 if (get_spe64(insn)) return true;
21858 It's the only reliable way to do the stuff below. */
21860 i = PATTERN (insn);
21861 if (GET_CODE (i) == SET)
21863 machine_mode mode = GET_MODE (SET_SRC (i));
21865 if (SPE_VECTOR_MODE (mode))
21867 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
21877 debug_stack_info (rs6000_stack_t *info)
21879 const char *abi_string;
21882 info = rs6000_stack_info ();
21884 fprintf (stderr, "\nStack information for function %s:\n",
21885 ((current_function_decl && DECL_NAME (current_function_decl))
21886 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
21891 default: abi_string = "Unknown"; break;
21892 case ABI_NONE: abi_string = "NONE"; break;
21893 case ABI_AIX: abi_string = "AIX"; break;
21894 case ABI_ELFv2: abi_string = "ELFv2"; break;
21895 case ABI_DARWIN: abi_string = "Darwin"; break;
21896 case ABI_V4: abi_string = "V.4"; break;
21899 fprintf (stderr, "\tABI = %5s\n", abi_string);
21901 if (TARGET_ALTIVEC_ABI)
21902 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
21904 if (TARGET_SPE_ABI)
21905 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
21907 if (info->first_gp_reg_save != 32)
21908 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
21910 if (info->first_fp_reg_save != 64)
21911 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
21913 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
21914 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
21915 info->first_altivec_reg_save);
21917 if (info->lr_save_p)
21918 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
21920 if (info->cr_save_p)
21921 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
21923 if (info->vrsave_mask)
21924 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
21927 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
21930 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
21932 if (info->gp_save_offset)
21933 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
21935 if (info->fp_save_offset)
21936 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
21938 if (info->altivec_save_offset)
21939 fprintf (stderr, "\taltivec_save_offset = %5d\n",
21940 info->altivec_save_offset);
21942 if (info->spe_gp_save_offset)
21943 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
21944 info->spe_gp_save_offset);
21946 if (info->vrsave_save_offset)
21947 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
21948 info->vrsave_save_offset);
21950 if (info->lr_save_offset)
21951 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
21953 if (info->cr_save_offset)
21954 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
21956 if (info->varargs_save_offset)
21957 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
21959 if (info->total_size)
21960 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
21963 if (info->vars_size)
21964 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
21967 if (info->parm_size)
21968 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
21970 if (info->fixed_size)
21971 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
21974 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
21976 if (info->spe_gp_size)
21977 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
21980 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
21982 if (info->altivec_size)
21983 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
21985 if (info->vrsave_size)
21986 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
21988 if (info->altivec_padding_size)
21989 fprintf (stderr, "\taltivec_padding_size= %5d\n",
21990 info->altivec_padding_size);
21992 if (info->spe_padding_size)
21993 fprintf (stderr, "\tspe_padding_size = %5d\n",
21994 info->spe_padding_size);
21997 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
21999 if (info->save_size)
22000 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
22002 if (info->reg_size != 4)
22003 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
22005 fprintf (stderr, "\tsave-strategy = %04x\n", info->savres_strategy);
22007 fprintf (stderr, "\n");
22011 rs6000_return_addr (int count, rtx frame)
22013 /* Currently we don't optimize very well between prolog and body
22014 code and for PIC code the code can be actually quite bad, so
22015 don't try to be too clever here. */
22017 || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic))
22019 cfun->machine->ra_needs_full_frame = 1;
22026 plus_constant (Pmode,
22028 (gen_rtx_MEM (Pmode,
22029 memory_address (Pmode, frame))),
22030 RETURN_ADDRESS_OFFSET)));
22033 cfun->machine->ra_need_lr = 1;
22034 return get_hard_reg_initial_val (Pmode, LR_REGNO);
22037 /* Say whether a function is a candidate for sibcall handling or not. */
22040 rs6000_function_ok_for_sibcall (tree decl, tree exp)
22045 fntype = TREE_TYPE (decl);
22047 fntype = TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp)));
22049 /* We can't do it if the called function has more vector parameters
22050 than the current function; there's nowhere to put the VRsave code. */
22051 if (TARGET_ALTIVEC_ABI
22052 && TARGET_ALTIVEC_VRSAVE
22053 && !(decl && decl == current_function_decl))
22055 function_args_iterator args_iter;
22059 /* Functions with vector parameters are required to have a
22060 prototype, so the argument type info must be available
22062 FOREACH_FUNCTION_ARGS(fntype, type, args_iter)
22063 if (TREE_CODE (type) == VECTOR_TYPE
22064 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
22067 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl), type, args_iter)
22068 if (TREE_CODE (type) == VECTOR_TYPE
22069 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type)))
22076 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
22077 functions, because the callee may have a different TOC pointer to
22078 the caller and there's no way to ensure we restore the TOC when
22079 we return. With the secure-plt SYSV ABI we can't make non-local
22080 calls when -fpic/PIC because the plt call stubs use r30. */
22081 if (DEFAULT_ABI == ABI_DARWIN
22082 || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
22084 && !DECL_EXTERNAL (decl)
22085 && (*targetm.binds_local_p) (decl))
22086 || (DEFAULT_ABI == ABI_V4
22087 && (!TARGET_SECURE_PLT
22090 && (*targetm.binds_local_p) (decl)))))
22092 tree attr_list = TYPE_ATTRIBUTES (fntype);
22094 if (!lookup_attribute ("longcall", attr_list)
22095 || lookup_attribute ("shortcall", attr_list))
22103 rs6000_ra_ever_killed (void)
22109 if (cfun->is_thunk)
22112 if (cfun->machine->lr_save_state)
22113 return cfun->machine->lr_save_state - 1;
22115 /* regs_ever_live has LR marked as used if any sibcalls are present,
22116 but this should not force saving and restoring in the
22117 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
22118 clobbers LR, so that is inappropriate. */
22120 /* Also, the prologue can generate a store into LR that
22121 doesn't really count, like this:
22124 bcl to set PIC register
22128 When we're called from the epilogue, we need to avoid counting
22129 this as a store. */
22131 push_topmost_sequence ();
22132 top = get_insns ();
22133 pop_topmost_sequence ();
22134 reg = gen_rtx_REG (Pmode, LR_REGNO);
22136 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
22142 if (!SIBLING_CALL_P (insn))
22145 else if (find_regno_note (insn, REG_INC, LR_REGNO))
22147 else if (set_of (reg, insn) != NULL_RTX
22148 && !prologue_epilogue_contains (insn))
22155 /* Emit instructions needed to load the TOC register.
22156 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
22157 a constant pool; or for SVR4 -fpic. */
22160 rs6000_emit_load_toc_table (int fromprolog)
22163 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
22165 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic)
22168 rtx lab, tmp1, tmp2, got;
22170 lab = gen_label_rtx ();
22171 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (lab));
22172 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
22174 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
22176 got = rs6000_got_sym ();
22177 tmp1 = tmp2 = dest;
22180 tmp1 = gen_reg_rtx (Pmode);
22181 tmp2 = gen_reg_rtx (Pmode);
22183 emit_insn (gen_load_toc_v4_PIC_1 (lab));
22184 emit_move_insn (tmp1, gen_rtx_REG (Pmode, LR_REGNO));
22185 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
22186 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
22188 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
22190 emit_insn (gen_load_toc_v4_pic_si ());
22191 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
22193 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2)
22196 rtx temp0 = (fromprolog
22197 ? gen_rtx_REG (Pmode, 0)
22198 : gen_reg_rtx (Pmode));
22204 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
22205 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
22207 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
22208 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
22210 emit_insn (gen_load_toc_v4_PIC_1 (symF));
22211 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
22212 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
22218 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
22219 lab = gen_label_rtx ();
22220 emit_insn (gen_load_toc_v4_PIC_1b (tocsym, lab));
22221 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
22222 if (TARGET_LINK_STACK)
22223 emit_insn (gen_addsi3 (dest, dest, GEN_INT (4)));
22224 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
22226 emit_insn (gen_addsi3 (dest, temp0, dest));
22228 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
22230 /* This is for AIX code running in non-PIC ELF32. */
22233 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
22234 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
22236 emit_insn (gen_elf_high (dest, realsym));
22237 emit_insn (gen_elf_low (dest, dest, realsym));
22241 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
22244 emit_insn (gen_load_toc_aix_si (dest));
22246 emit_insn (gen_load_toc_aix_di (dest));
22250 /* Emit instructions to restore the link register after determining where
22251 its value has been stored. */
22254 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
22256 rs6000_stack_t *info = rs6000_stack_info ();
22259 operands[0] = source;
22260 operands[1] = scratch;
22262 if (info->lr_save_p)
22264 rtx frame_rtx = stack_pointer_rtx;
22265 HOST_WIDE_INT sp_offset = 0;
22268 if (frame_pointer_needed
22269 || cfun->calls_alloca
22270 || info->total_size > 32767)
22272 tmp = gen_frame_mem (Pmode, frame_rtx);
22273 emit_move_insn (operands[1], tmp);
22274 frame_rtx = operands[1];
22276 else if (info->push_p)
22277 sp_offset = info->total_size;
22279 tmp = plus_constant (Pmode, frame_rtx,
22280 info->lr_save_offset + sp_offset);
22281 tmp = gen_frame_mem (Pmode, tmp);
22282 emit_move_insn (tmp, operands[0]);
22285 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
22287 /* Freeze lr_save_p. We've just emitted rtl that depends on the
22288 state of lr_save_p so any change from here on would be a bug. In
22289 particular, stop rs6000_ra_ever_killed from considering the SET
22290 of lr we may have added just above. */
22291 cfun->machine->lr_save_state = info->lr_save_p + 1;
22294 static GTY(()) alias_set_type set = -1;
22297 get_TOC_alias_set (void)
22300 set = new_alias_set ();
22304 /* This returns nonzero if the current function uses the TOC. This is
22305 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
22306 is generated by the ABI_V4 load_toc_* patterns. */
22313 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
22316 rtx pat = PATTERN (insn);
22319 if (GET_CODE (pat) == PARALLEL)
22320 for (i = 0; i < XVECLEN (pat, 0); i++)
22322 rtx sub = XVECEXP (pat, 0, i);
22323 if (GET_CODE (sub) == USE)
22325 sub = XEXP (sub, 0);
22326 if (GET_CODE (sub) == UNSPEC
22327 && XINT (sub, 1) == UNSPEC_TOC)
22337 create_TOC_reference (rtx symbol, rtx largetoc_reg)
22339 rtx tocrel, tocreg, hi;
22341 if (TARGET_DEBUG_ADDR)
22343 if (GET_CODE (symbol) == SYMBOL_REF)
22344 fprintf (stderr, "\ncreate_TOC_reference, (symbol_ref %s)\n",
22348 fprintf (stderr, "\ncreate_TOC_reference, code %s:\n",
22349 GET_RTX_NAME (GET_CODE (symbol)));
22350 debug_rtx (symbol);
22354 if (!can_create_pseudo_p ())
22355 df_set_regs_ever_live (TOC_REGISTER, true);
22357 tocreg = gen_rtx_REG (Pmode, TOC_REGISTER);
22358 tocrel = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, symbol, tocreg), UNSPEC_TOCREL);
22359 if (TARGET_CMODEL == CMODEL_SMALL || can_create_pseudo_p ())
22362 hi = gen_rtx_HIGH (Pmode, copy_rtx (tocrel));
22363 if (largetoc_reg != NULL)
22365 emit_move_insn (largetoc_reg, hi);
22368 return gen_rtx_LO_SUM (Pmode, hi, tocrel);
22371 /* Issue assembly directives that create a reference to the given DWARF
22372 FRAME_TABLE_LABEL from the current function section. */
22374 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label)
22376 fprintf (asm_out_file, "\t.ref %s\n",
22377 (* targetm.strip_name_encoding) (frame_table_label));
22380 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
22381 and the change to the stack pointer. */
22384 rs6000_emit_stack_tie (rtx fp, bool hard_frame_needed)
22391 regs[i++] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
22392 if (hard_frame_needed)
22393 regs[i++] = gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM);
22394 if (!(REGNO (fp) == STACK_POINTER_REGNUM
22395 || (hard_frame_needed
22396 && REGNO (fp) == HARD_FRAME_POINTER_REGNUM)))
22399 p = rtvec_alloc (i);
22402 rtx mem = gen_frame_mem (BLKmode, regs[i]);
22403 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, const0_rtx);
22406 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode, p)));
22409 /* Emit the correct code for allocating stack space, as insns.
22410 If COPY_REG, make sure a copy of the old frame is left there.
22411 The generated code may use hard register 0 as a temporary. */
22414 rs6000_emit_allocate_stack (HOST_WIDE_INT size, rtx copy_reg, int copy_off)
22417 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
22418 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
22419 rtx todec = gen_int_mode (-size, Pmode);
22422 if (INTVAL (todec) != -size)
22424 warning (0, "stack frame too large");
22425 emit_insn (gen_trap ());
22429 if (crtl->limit_stack)
22431 if (REG_P (stack_limit_rtx)
22432 && REGNO (stack_limit_rtx) > 1
22433 && REGNO (stack_limit_rtx) <= 31)
22435 emit_insn (gen_add3_insn (tmp_reg, stack_limit_rtx, GEN_INT (size)));
22436 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
22439 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
22441 && DEFAULT_ABI == ABI_V4)
22443 rtx toload = gen_rtx_CONST (VOIDmode,
22444 gen_rtx_PLUS (Pmode,
22448 emit_insn (gen_elf_high (tmp_reg, toload));
22449 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
22450 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
22454 warning (0, "stack limit expression is not supported");
22460 emit_insn (gen_add3_insn (copy_reg, stack_reg, GEN_INT (copy_off)));
22462 emit_move_insn (copy_reg, stack_reg);
22467 /* Need a note here so that try_split doesn't get confused. */
22468 if (get_last_insn () == NULL_RTX)
22469 emit_note (NOTE_INSN_DELETED);
22470 insn = emit_move_insn (tmp_reg, todec);
22471 try_split (PATTERN (insn), insn, 0);
22475 insn = emit_insn (TARGET_32BIT
22476 ? gen_movsi_update_stack (stack_reg, stack_reg,
22478 : gen_movdi_di_update_stack (stack_reg, stack_reg,
22479 todec, stack_reg));
22480 /* Since we didn't use gen_frame_mem to generate the MEM, grab
22481 it now and set the alias set/attributes. The above gen_*_update
22482 calls will generate a PARALLEL with the MEM set being the first
22484 par = PATTERN (insn);
22485 gcc_assert (GET_CODE (par) == PARALLEL);
22486 set = XVECEXP (par, 0, 0);
22487 gcc_assert (GET_CODE (set) == SET);
22488 mem = SET_DEST (set);
22489 gcc_assert (MEM_P (mem));
22490 MEM_NOTRAP_P (mem) = 1;
22491 set_mem_alias_set (mem, get_frame_alias_set ());
22493 RTX_FRAME_RELATED_P (insn) = 1;
22494 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
22495 gen_rtx_SET (VOIDmode, stack_reg,
22496 gen_rtx_PLUS (Pmode, stack_reg,
22497 GEN_INT (-size))));
22500 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
22502 #if PROBE_INTERVAL > 32768
22503 #error Cannot use indexed addressing mode for stack probing
22506 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
22507 inclusive. These are offsets from the current stack pointer. */
22510 rs6000_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
22512 /* See if we have a constant small number of probes to generate. If so,
22513 that's the easy case. */
22514 if (first + size <= 32768)
22518 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
22519 it exceeds SIZE. If only one probe is needed, this will not
22520 generate any code. Then probe at FIRST + SIZE. */
22521 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
22522 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
22525 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
22529 /* Otherwise, do the same as above, but in a loop. Note that we must be
22530 extra careful with variables wrapping around because we might be at
22531 the very top (or the very bottom) of the address space and we have
22532 to be able to handle this case properly; in particular, we use an
22533 equality test for the loop condition. */
22536 HOST_WIDE_INT rounded_size;
22537 rtx r12 = gen_rtx_REG (Pmode, 12);
22538 rtx r0 = gen_rtx_REG (Pmode, 0);
22540 /* Sanity check for the addressing mode we're going to use. */
22541 gcc_assert (first <= 32768);
22543 /* Step 1: round SIZE to the previous multiple of the interval. */
22545 rounded_size = size & -PROBE_INTERVAL;
22548 /* Step 2: compute initial and final value of the loop counter. */
22550 /* TEST_ADDR = SP + FIRST. */
22551 emit_insn (gen_rtx_SET (VOIDmode, r12,
22552 plus_constant (Pmode, stack_pointer_rtx,
22555 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
22556 if (rounded_size > 32768)
22558 emit_move_insn (r0, GEN_INT (-rounded_size));
22559 emit_insn (gen_rtx_SET (VOIDmode, r0,
22560 gen_rtx_PLUS (Pmode, r12, r0)));
22563 emit_insn (gen_rtx_SET (VOIDmode, r0,
22564 plus_constant (Pmode, r12, -rounded_size)));
22567 /* Step 3: the loop
22569 while (TEST_ADDR != LAST_ADDR)
22571 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
22575 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
22576 until it is equal to ROUNDED_SIZE. */
22579 emit_insn (gen_probe_stack_rangedi (r12, r12, r0));
22581 emit_insn (gen_probe_stack_rangesi (r12, r12, r0));
22584 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
22585 that SIZE is equal to ROUNDED_SIZE. */
22587 if (size != rounded_size)
22588 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
22592 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
22593 absolute addresses. */
22596 output_probe_stack_range (rtx reg1, rtx reg2)
22598 static int labelno = 0;
22599 char loop_lab[32], end_lab[32];
22602 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
22603 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
22605 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
22607 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
22611 output_asm_insn ("cmpd 0,%0,%1", xops);
22613 output_asm_insn ("cmpw 0,%0,%1", xops);
22615 fputs ("\tbeq 0,", asm_out_file);
22616 assemble_name_raw (asm_out_file, end_lab);
22617 fputc ('\n', asm_out_file);
22619 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
22620 xops[1] = GEN_INT (-PROBE_INTERVAL);
22621 output_asm_insn ("addi %0,%0,%1", xops);
22623 /* Probe at TEST_ADDR and branch. */
22624 xops[1] = gen_rtx_REG (Pmode, 0);
22625 output_asm_insn ("stw %1,0(%0)", xops);
22626 fprintf (asm_out_file, "\tb ");
22627 assemble_name_raw (asm_out_file, loop_lab);
22628 fputc ('\n', asm_out_file);
22630 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
22635 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
22636 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
22637 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
22638 deduce these equivalences by itself so it wasn't necessary to hold
22639 its hand so much. Don't be tempted to always supply d2_f_d_e with
22640 the actual cfa register, ie. r31 when we are using a hard frame
22641 pointer. That fails when saving regs off r1, and sched moves the
22642 r31 setup past the reg saves. */
22645 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
22646 rtx reg2, rtx rreg, rtx split_reg)
22650 if (REGNO (reg) == STACK_POINTER_REGNUM && reg2 == NULL_RTX)
22652 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
22655 gcc_checking_assert (val == 0);
22656 real = PATTERN (insn);
22657 if (GET_CODE (real) == PARALLEL)
22658 for (i = 0; i < XVECLEN (real, 0); i++)
22659 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
22661 rtx set = XVECEXP (real, 0, i);
22663 RTX_FRAME_RELATED_P (set) = 1;
22665 RTX_FRAME_RELATED_P (insn) = 1;
22669 /* copy_rtx will not make unique copies of registers, so we need to
22670 ensure we don't have unwanted sharing here. */
22672 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
22675 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
22677 real = copy_rtx (PATTERN (insn));
22679 if (reg2 != NULL_RTX)
22680 real = replace_rtx (real, reg2, rreg);
22682 if (REGNO (reg) == STACK_POINTER_REGNUM)
22683 gcc_checking_assert (val == 0);
22685 real = replace_rtx (real, reg,
22686 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
22687 STACK_POINTER_REGNUM),
22690 /* We expect that 'real' is either a SET or a PARALLEL containing
22691 SETs (and possibly other stuff). In a PARALLEL, all the SETs
22692 are important so they all have to be marked RTX_FRAME_RELATED_P. */
22694 if (GET_CODE (real) == SET)
22698 temp = simplify_rtx (SET_SRC (set));
22700 SET_SRC (set) = temp;
22701 temp = simplify_rtx (SET_DEST (set));
22703 SET_DEST (set) = temp;
22704 if (GET_CODE (SET_DEST (set)) == MEM)
22706 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
22708 XEXP (SET_DEST (set), 0) = temp;
22715 gcc_assert (GET_CODE (real) == PARALLEL);
22716 for (i = 0; i < XVECLEN (real, 0); i++)
22717 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
22719 rtx set = XVECEXP (real, 0, i);
22721 temp = simplify_rtx (SET_SRC (set));
22723 SET_SRC (set) = temp;
22724 temp = simplify_rtx (SET_DEST (set));
22726 SET_DEST (set) = temp;
22727 if (GET_CODE (SET_DEST (set)) == MEM)
22729 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
22731 XEXP (SET_DEST (set), 0) = temp;
22733 RTX_FRAME_RELATED_P (set) = 1;
22737 /* If a store insn has been split into multiple insns, the
22738 true source register is given by split_reg. */
22739 if (split_reg != NULL_RTX)
22740 real = gen_rtx_SET (VOIDmode, SET_DEST (real), split_reg);
22742 RTX_FRAME_RELATED_P (insn) = 1;
22743 add_reg_note (insn, REG_FRAME_RELATED_EXPR, real);
22748 /* Returns an insn that has a vrsave set operation with the
22749 appropriate CLOBBERs. */
22752 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
22755 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
22756 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
22759 = gen_rtx_SET (VOIDmode,
22761 gen_rtx_UNSPEC_VOLATILE (SImode,
22762 gen_rtvec (2, reg, vrsave),
22763 UNSPECV_SET_VRSAVE));
22767 /* We need to clobber the registers in the mask so the scheduler
22768 does not move sets to VRSAVE before sets of AltiVec registers.
22770 However, if the function receives nonlocal gotos, reload will set
22771 all call saved registers live. We will end up with:
22773 (set (reg 999) (mem))
22774 (parallel [ (set (reg vrsave) (unspec blah))
22775 (clobber (reg 999))])
22777 The clobber will cause the store into reg 999 to be dead, and
22778 flow will attempt to delete an epilogue insn. In this case, we
22779 need an unspec use/set of the register. */
22781 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
22782 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
22784 if (!epiloguep || call_used_regs [i])
22785 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
22786 gen_rtx_REG (V4SImode, i));
22789 rtx reg = gen_rtx_REG (V4SImode, i);
22792 = gen_rtx_SET (VOIDmode,
22794 gen_rtx_UNSPEC (V4SImode,
22795 gen_rtvec (1, reg), 27));
22799 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
22801 for (i = 0; i < nclobs; ++i)
22802 XVECEXP (insn, 0, i) = clobs[i];
22808 gen_frame_set (rtx reg, rtx frame_reg, int offset, bool store)
22812 addr = gen_rtx_PLUS (Pmode, frame_reg, GEN_INT (offset));
22813 mem = gen_frame_mem (GET_MODE (reg), addr);
22814 return gen_rtx_SET (VOIDmode, store ? mem : reg, store ? reg : mem);
22818 gen_frame_load (rtx reg, rtx frame_reg, int offset)
22820 return gen_frame_set (reg, frame_reg, offset, false);
22824 gen_frame_store (rtx reg, rtx frame_reg, int offset)
22826 return gen_frame_set (reg, frame_reg, offset, true);
22829 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
22830 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
22833 emit_frame_save (rtx frame_reg, machine_mode mode,
22834 unsigned int regno, int offset, HOST_WIDE_INT frame_reg_to_sp)
22838 /* Some cases that need register indexed addressing. */
22839 gcc_checking_assert (!((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
22840 || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
22841 || (TARGET_E500_DOUBLE && mode == DFmode)
22843 && SPE_VECTOR_MODE (mode)
22844 && !SPE_CONST_OFFSET_OK (offset))));
22846 reg = gen_rtx_REG (mode, regno);
22847 insn = emit_insn (gen_frame_store (reg, frame_reg, offset));
22848 return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp,
22849 NULL_RTX, NULL_RTX, NULL_RTX);
22852 /* Emit an offset memory reference suitable for a frame store, while
22853 converting to a valid addressing mode. */
22856 gen_frame_mem_offset (machine_mode mode, rtx reg, int offset)
22858 rtx int_rtx, offset_rtx;
22860 int_rtx = GEN_INT (offset);
22862 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode) && !SPE_CONST_OFFSET_OK (offset))
22863 || (TARGET_E500_DOUBLE && mode == DFmode))
22865 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
22866 emit_move_insn (offset_rtx, int_rtx);
22869 offset_rtx = int_rtx;
22871 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
22874 #ifndef TARGET_FIX_AND_CONTINUE
22875 #define TARGET_FIX_AND_CONTINUE 0
22878 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
22879 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
22880 #define LAST_SAVRES_REGISTER 31
22881 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
22892 static GTY(()) rtx savres_routine_syms[N_SAVRES_REGISTERS][12];
22894 /* Temporary holding space for an out-of-line register save/restore
22896 static char savres_routine_name[30];
22898 /* Return the name for an out-of-line register save/restore routine.
22899 We are saving/restoring GPRs if GPR is true. */
22902 rs6000_savres_routine_name (rs6000_stack_t *info, int regno, int sel)
22904 const char *prefix = "";
22905 const char *suffix = "";
22907 /* Different targets are supposed to define
22908 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
22909 routine name could be defined with:
22911 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
22913 This is a nice idea in practice, but in reality, things are
22914 complicated in several ways:
22916 - ELF targets have save/restore routines for GPRs.
22918 - SPE targets use different prefixes for 32/64-bit registers, and
22919 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
22921 - PPC64 ELF targets have routines for save/restore of GPRs that
22922 differ in what they do with the link register, so having a set
22923 prefix doesn't work. (We only use one of the save routines at
22924 the moment, though.)
22926 - PPC32 elf targets have "exit" versions of the restore routines
22927 that restore the link register and can save some extra space.
22928 These require an extra suffix. (There are also "tail" versions
22929 of the restore routines and "GOT" versions of the save routines,
22930 but we don't generate those at present. Same problems apply,
22933 We deal with all this by synthesizing our own prefix/suffix and
22934 using that for the simple sprintf call shown above. */
22937 /* No floating point saves on the SPE. */
22938 gcc_assert ((sel & SAVRES_REG) == SAVRES_GPR);
22940 if ((sel & SAVRES_SAVE))
22941 prefix = info->spe_64bit_regs_used ? "_save64gpr_" : "_save32gpr_";
22943 prefix = info->spe_64bit_regs_used ? "_rest64gpr_" : "_rest32gpr_";
22945 if ((sel & SAVRES_LR))
22948 else if (DEFAULT_ABI == ABI_V4)
22953 if ((sel & SAVRES_REG) == SAVRES_GPR)
22954 prefix = (sel & SAVRES_SAVE) ? "_savegpr_" : "_restgpr_";
22955 else if ((sel & SAVRES_REG) == SAVRES_FPR)
22956 prefix = (sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_";
22957 else if ((sel & SAVRES_REG) == SAVRES_VR)
22958 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
22962 if ((sel & SAVRES_LR))
22965 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
22967 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
22968 /* No out-of-line save/restore routines for GPRs on AIX. */
22969 gcc_assert (!TARGET_AIX || (sel & SAVRES_REG) != SAVRES_GPR);
22973 if ((sel & SAVRES_REG) == SAVRES_GPR)
22974 prefix = ((sel & SAVRES_SAVE)
22975 ? ((sel & SAVRES_LR) ? "_savegpr0_" : "_savegpr1_")
22976 : ((sel & SAVRES_LR) ? "_restgpr0_" : "_restgpr1_"));
22977 else if ((sel & SAVRES_REG) == SAVRES_FPR)
22979 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
22980 if ((sel & SAVRES_LR))
22981 prefix = ((sel & SAVRES_SAVE) ? "_savefpr_" : "_restfpr_");
22985 prefix = (sel & SAVRES_SAVE) ? SAVE_FP_PREFIX : RESTORE_FP_PREFIX;
22986 suffix = (sel & SAVRES_SAVE) ? SAVE_FP_SUFFIX : RESTORE_FP_SUFFIX;
22989 else if ((sel & SAVRES_REG) == SAVRES_VR)
22990 prefix = (sel & SAVRES_SAVE) ? "_savevr_" : "_restvr_";
22995 if (DEFAULT_ABI == ABI_DARWIN)
22997 /* The Darwin approach is (slightly) different, in order to be
22998 compatible with code generated by the system toolchain. There is a
22999 single symbol for the start of save sequence, and the code here
23000 embeds an offset into that code on the basis of the first register
23002 prefix = (sel & SAVRES_SAVE) ? "save" : "rest" ;
23003 if ((sel & SAVRES_REG) == SAVRES_GPR)
23004 sprintf (savres_routine_name, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix,
23005 ((sel & SAVRES_LR) ? "x" : ""), (regno == 13 ? "" : "+"),
23006 (regno - 13) * 4, prefix, regno);
23007 else if ((sel & SAVRES_REG) == SAVRES_FPR)
23008 sprintf (savres_routine_name, "*%sFP%s%.0d ; %s f%d-f31", prefix,
23009 (regno == 14 ? "" : "+"), (regno - 14) * 4, prefix, regno);
23010 else if ((sel & SAVRES_REG) == SAVRES_VR)
23011 sprintf (savres_routine_name, "*%sVEC%s%.0d ; %s v%d-v31", prefix,
23012 (regno == 20 ? "" : "+"), (regno - 20) * 8, prefix, regno);
23017 sprintf (savres_routine_name, "%s%d%s", prefix, regno, suffix);
23019 return savres_routine_name;
23022 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
23023 We are saving/restoring GPRs if GPR is true. */
23026 rs6000_savres_routine_sym (rs6000_stack_t *info, int sel)
23028 int regno = ((sel & SAVRES_REG) == SAVRES_GPR
23029 ? info->first_gp_reg_save
23030 : (sel & SAVRES_REG) == SAVRES_FPR
23031 ? info->first_fp_reg_save - 32
23032 : (sel & SAVRES_REG) == SAVRES_VR
23033 ? info->first_altivec_reg_save - FIRST_ALTIVEC_REGNO
23038 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
23039 versions of the gpr routines. */
23040 if (TARGET_SPE_ABI && (sel & SAVRES_REG) == SAVRES_GPR
23041 && info->spe_64bit_regs_used)
23042 select ^= SAVRES_FPR ^ SAVRES_GPR;
23044 /* Don't generate bogus routine names. */
23045 gcc_assert (FIRST_SAVRES_REGISTER <= regno
23046 && regno <= LAST_SAVRES_REGISTER
23047 && select >= 0 && select <= 12);
23049 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select];
23055 name = rs6000_savres_routine_name (info, regno, sel);
23057 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
23058 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
23059 SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
23065 /* Emit a sequence of insns, including a stack tie if needed, for
23066 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
23067 reset the stack pointer, but move the base of the frame into
23068 reg UPDT_REGNO for use by out-of-line register restore routines. */
23071 rs6000_emit_stack_reset (rs6000_stack_t *info,
23072 rtx frame_reg_rtx, HOST_WIDE_INT frame_off,
23073 unsigned updt_regno)
23077 /* This blockage is needed so that sched doesn't decide to move
23078 the sp change before the register restores. */
23079 if (DEFAULT_ABI == ABI_V4
23081 && info->spe_64bit_regs_used != 0
23082 && info->first_gp_reg_save != 32))
23083 rs6000_emit_stack_tie (frame_reg_rtx, frame_pointer_needed);
23085 /* If we are restoring registers out-of-line, we will be using the
23086 "exit" variants of the restore routines, which will reset the
23087 stack for us. But we do need to point updt_reg into the
23088 right place for those routines. */
23089 updt_reg_rtx = gen_rtx_REG (Pmode, updt_regno);
23091 if (frame_off != 0)
23092 return emit_insn (gen_add3_insn (updt_reg_rtx,
23093 frame_reg_rtx, GEN_INT (frame_off)));
23094 else if (REGNO (frame_reg_rtx) != updt_regno)
23095 return emit_move_insn (updt_reg_rtx, frame_reg_rtx);
23100 /* Return the register number used as a pointer by out-of-line
23101 save/restore functions. */
23103 static inline unsigned
23104 ptr_regno_for_savres (int sel)
23106 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
23107 return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12;
23108 return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11;
23111 /* Construct a parallel rtx describing the effect of a call to an
23112 out-of-line register save/restore routine, and emit the insn
23113 or jump_insn as appropriate. */
23116 rs6000_emit_savres_rtx (rs6000_stack_t *info,
23117 rtx frame_reg_rtx, int save_area_offset, int lr_offset,
23118 machine_mode reg_mode, int sel)
23121 int offset, start_reg, end_reg, n_regs, use_reg;
23122 int reg_size = GET_MODE_SIZE (reg_mode);
23128 start_reg = ((sel & SAVRES_REG) == SAVRES_GPR
23129 ? info->first_gp_reg_save
23130 : (sel & SAVRES_REG) == SAVRES_FPR
23131 ? info->first_fp_reg_save
23132 : (sel & SAVRES_REG) == SAVRES_VR
23133 ? info->first_altivec_reg_save
23135 end_reg = ((sel & SAVRES_REG) == SAVRES_GPR
23137 : (sel & SAVRES_REG) == SAVRES_FPR
23139 : (sel & SAVRES_REG) == SAVRES_VR
23140 ? LAST_ALTIVEC_REGNO + 1
23142 n_regs = end_reg - start_reg;
23143 p = rtvec_alloc (3 + ((sel & SAVRES_LR) ? 1 : 0)
23144 + ((sel & SAVRES_REG) == SAVRES_VR ? 1 : 0)
23147 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
23148 RTVEC_ELT (p, offset++) = ret_rtx;
23150 RTVEC_ELT (p, offset++)
23151 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
23153 sym = rs6000_savres_routine_sym (info, sel);
23154 RTVEC_ELT (p, offset++) = gen_rtx_USE (VOIDmode, sym);
23156 use_reg = ptr_regno_for_savres (sel);
23157 if ((sel & SAVRES_REG) == SAVRES_VR)
23159 /* Vector regs are saved/restored using [reg+reg] addressing. */
23160 RTVEC_ELT (p, offset++)
23161 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, use_reg));
23162 RTVEC_ELT (p, offset++)
23163 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
23166 RTVEC_ELT (p, offset++)
23167 = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, use_reg));
23169 for (i = 0; i < end_reg - start_reg; i++)
23170 RTVEC_ELT (p, i + offset)
23171 = gen_frame_set (gen_rtx_REG (reg_mode, start_reg + i),
23172 frame_reg_rtx, save_area_offset + reg_size * i,
23173 (sel & SAVRES_SAVE) != 0);
23175 if ((sel & SAVRES_SAVE) && (sel & SAVRES_LR))
23176 RTVEC_ELT (p, i + offset)
23177 = gen_frame_store (gen_rtx_REG (Pmode, 0), frame_reg_rtx, lr_offset);
23179 par = gen_rtx_PARALLEL (VOIDmode, p);
23181 if (!(sel & SAVRES_SAVE) && (sel & SAVRES_LR))
23183 insn = emit_jump_insn (par);
23184 JUMP_LABEL (insn) = ret_rtx;
23187 insn = emit_insn (par);
23191 /* Emit code to store CR fields that need to be saved into REG. */
23194 rs6000_emit_move_from_cr (rtx reg)
23196 /* Only the ELFv2 ABI allows storing only selected fields. */
23197 if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF)
23199 int i, cr_reg[8], count = 0;
23201 /* Collect CR fields that must be saved. */
23202 for (i = 0; i < 8; i++)
23203 if (save_reg_p (CR0_REGNO + i))
23204 cr_reg[count++] = i;
23206 /* If it's just a single one, use mfcrf. */
23209 rtvec p = rtvec_alloc (1);
23210 rtvec r = rtvec_alloc (2);
23211 RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]);
23212 RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0]));
23214 = gen_rtx_SET (VOIDmode, reg,
23215 gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR));
23217 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
23221 /* ??? It might be better to handle count == 2 / 3 cases here
23222 as well, using logical operations to combine the values. */
23225 emit_insn (gen_movesi_from_cr (reg));
23228 /* Determine whether the gp REG is really used. */
23231 rs6000_reg_live_or_pic_offset_p (int reg)
23233 /* If the function calls eh_return, claim used all the registers that would
23234 be checked for liveness otherwise. This is required for the PIC offset
23235 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
23236 register allocation purposes in this case. */
23238 return (((crtl->calls_eh_return || df_regs_ever_live_p (reg))
23239 && (!call_used_regs[reg]
23240 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
23241 && !TARGET_SINGLE_PIC_BASE
23242 && TARGET_TOC && TARGET_MINIMAL_TOC)))
23243 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
23244 && !TARGET_SINGLE_PIC_BASE
23245 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
23246 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
23249 /* Emit function prologue as insns. */
23252 rs6000_emit_prologue (void)
23254 rs6000_stack_t *info = rs6000_stack_info ();
23255 machine_mode reg_mode = Pmode;
23256 int reg_size = TARGET_32BIT ? 4 : 8;
23257 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
23258 rtx frame_reg_rtx = sp_reg_rtx;
23259 unsigned int cr_save_regno;
23260 rtx cr_save_rtx = NULL_RTX;
23263 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
23264 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
23265 && call_used_regs[STATIC_CHAIN_REGNUM]);
23266 /* Offset to top of frame for frame_reg and sp respectively. */
23267 HOST_WIDE_INT frame_off = 0;
23268 HOST_WIDE_INT sp_off = 0;
23270 #ifdef ENABLE_CHECKING
23271 /* Track and check usage of r0, r11, r12. */
23272 int reg_inuse = using_static_chain_p ? 1 << 11 : 0;
23273 #define START_USE(R) do \
23275 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
23276 reg_inuse |= 1 << (R); \
23278 #define END_USE(R) do \
23280 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
23281 reg_inuse &= ~(1 << (R)); \
23283 #define NOT_INUSE(R) do \
23285 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
23288 #define START_USE(R) do {} while (0)
23289 #define END_USE(R) do {} while (0)
23290 #define NOT_INUSE(R) do {} while (0)
23293 if (DEFAULT_ABI == ABI_ELFv2)
23295 cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM);
23297 /* With -mminimal-toc we may generate an extra use of r2 below. */
23298 if (!TARGET_SINGLE_PIC_BASE
23299 && TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
23300 cfun->machine->r2_setup_needed = true;
23304 if (flag_stack_usage_info)
23305 current_function_static_stack_size = info->total_size;
23307 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
23309 HOST_WIDE_INT size = info->total_size;
23311 if (crtl->is_leaf && !cfun->calls_alloca)
23313 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
23314 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT,
23315 size - STACK_CHECK_PROTECT);
23318 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
23321 if (TARGET_FIX_AND_CONTINUE)
23323 /* gdb on darwin arranges to forward a function from the old
23324 address by modifying the first 5 instructions of the function
23325 to branch to the overriding function. This is necessary to
23326 permit function pointers that point to the old function to
23327 actually forward to the new function. */
23328 emit_insn (gen_nop ());
23329 emit_insn (gen_nop ());
23330 emit_insn (gen_nop ());
23331 emit_insn (gen_nop ());
23332 emit_insn (gen_nop ());
23335 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
23337 reg_mode = V2SImode;
23341 /* Handle world saves specially here. */
23342 if (WORLD_SAVE_P (info))
23349 /* save_world expects lr in r0. */
23350 reg0 = gen_rtx_REG (Pmode, 0);
23351 if (info->lr_save_p)
23353 insn = emit_move_insn (reg0,
23354 gen_rtx_REG (Pmode, LR_REGNO));
23355 RTX_FRAME_RELATED_P (insn) = 1;
23358 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
23359 assumptions about the offsets of various bits of the stack
23361 gcc_assert (info->gp_save_offset == -220
23362 && info->fp_save_offset == -144
23363 && info->lr_save_offset == 8
23364 && info->cr_save_offset == 4
23367 && (!crtl->calls_eh_return
23368 || info->ehrd_offset == -432)
23369 && info->vrsave_save_offset == -224
23370 && info->altivec_save_offset == -416);
23372 treg = gen_rtx_REG (SImode, 11);
23373 emit_move_insn (treg, GEN_INT (-info->total_size));
23375 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
23376 in R11. It also clobbers R12, so beware! */
23378 /* Preserve CR2 for save_world prologues */
23380 sz += 32 - info->first_gp_reg_save;
23381 sz += 64 - info->first_fp_reg_save;
23382 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
23383 p = rtvec_alloc (sz);
23385 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
23386 gen_rtx_REG (SImode,
23388 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
23389 gen_rtx_SYMBOL_REF (Pmode,
23391 /* We do floats first so that the instruction pattern matches
23393 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
23395 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
23397 info->first_fp_reg_save + i),
23399 info->fp_save_offset + frame_off + 8 * i);
23400 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
23402 = gen_frame_store (gen_rtx_REG (V4SImode,
23403 info->first_altivec_reg_save + i),
23405 info->altivec_save_offset + frame_off + 16 * i);
23406 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
23408 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
23410 info->gp_save_offset + frame_off + reg_size * i);
23412 /* CR register traditionally saved as CR2. */
23414 = gen_frame_store (gen_rtx_REG (SImode, CR2_REGNO),
23415 frame_reg_rtx, info->cr_save_offset + frame_off);
23416 /* Explain about use of R0. */
23417 if (info->lr_save_p)
23419 = gen_frame_store (reg0,
23420 frame_reg_rtx, info->lr_save_offset + frame_off);
23421 /* Explain what happens to the stack pointer. */
23423 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
23424 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
23427 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
23428 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
23429 treg, GEN_INT (-info->total_size), NULL_RTX);
23430 sp_off = frame_off = info->total_size;
23433 strategy = info->savres_strategy;
23435 /* For V.4, update stack before we do any saving and set back pointer. */
23436 if (! WORLD_SAVE_P (info)
23438 && (DEFAULT_ABI == ABI_V4
23439 || crtl->calls_eh_return))
23441 bool need_r11 = (TARGET_SPE
23442 ? (!(strategy & SAVE_INLINE_GPRS)
23443 && info->spe_64bit_regs_used == 0)
23444 : (!(strategy & SAVE_INLINE_FPRS)
23445 || !(strategy & SAVE_INLINE_GPRS)
23446 || !(strategy & SAVE_INLINE_VRS)));
23447 int ptr_regno = -1;
23448 rtx ptr_reg = NULL_RTX;
23451 if (info->total_size < 32767)
23452 frame_off = info->total_size;
23455 else if (info->cr_save_p
23457 || info->first_fp_reg_save < 64
23458 || info->first_gp_reg_save < 32
23459 || info->altivec_size != 0
23460 || info->vrsave_mask != 0
23461 || crtl->calls_eh_return)
23465 /* The prologue won't be saving any regs so there is no need
23466 to set up a frame register to access any frame save area.
23467 We also won't be using frame_off anywhere below, but set
23468 the correct value anyway to protect against future
23469 changes to this function. */
23470 frame_off = info->total_size;
23472 if (ptr_regno != -1)
23474 /* Set up the frame offset to that needed by the first
23475 out-of-line save function. */
23476 START_USE (ptr_regno);
23477 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
23478 frame_reg_rtx = ptr_reg;
23479 if (!(strategy & SAVE_INLINE_FPRS) && info->fp_size != 0)
23480 gcc_checking_assert (info->fp_save_offset + info->fp_size == 0);
23481 else if (!(strategy & SAVE_INLINE_GPRS) && info->first_gp_reg_save < 32)
23482 ptr_off = info->gp_save_offset + info->gp_size;
23483 else if (!(strategy & SAVE_INLINE_VRS) && info->altivec_size != 0)
23484 ptr_off = info->altivec_save_offset + info->altivec_size;
23485 frame_off = -ptr_off;
23487 rs6000_emit_allocate_stack (info->total_size, ptr_reg, ptr_off);
23488 sp_off = info->total_size;
23489 if (frame_reg_rtx != sp_reg_rtx)
23490 rs6000_emit_stack_tie (frame_reg_rtx, false);
23493 /* If we use the link register, get it into r0. */
23494 if (!WORLD_SAVE_P (info) && info->lr_save_p)
23496 rtx addr, reg, mem;
23498 reg = gen_rtx_REG (Pmode, 0);
23500 insn = emit_move_insn (reg, gen_rtx_REG (Pmode, LR_REGNO));
23501 RTX_FRAME_RELATED_P (insn) = 1;
23503 if (!(strategy & (SAVE_NOINLINE_GPRS_SAVES_LR
23504 | SAVE_NOINLINE_FPRS_SAVES_LR)))
23506 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
23507 GEN_INT (info->lr_save_offset + frame_off));
23508 mem = gen_rtx_MEM (Pmode, addr);
23509 /* This should not be of rs6000_sr_alias_set, because of
23510 __builtin_return_address. */
23512 insn = emit_move_insn (mem, reg);
23513 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
23514 NULL_RTX, NULL_RTX, NULL_RTX);
23519 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
23520 r12 will be needed by out-of-line gpr restore. */
23521 cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
23522 && !(strategy & (SAVE_INLINE_GPRS
23523 | SAVE_NOINLINE_GPRS_SAVES_LR))
23525 if (!WORLD_SAVE_P (info)
23527 && REGNO (frame_reg_rtx) != cr_save_regno
23528 && !(using_static_chain_p && cr_save_regno == 11))
23530 cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno);
23531 START_USE (cr_save_regno);
23532 rs6000_emit_move_from_cr (cr_save_rtx);
23535 /* Do any required saving of fpr's. If only one or two to save, do
23536 it ourselves. Otherwise, call function. */
23537 if (!WORLD_SAVE_P (info) && (strategy & SAVE_INLINE_FPRS))
23540 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
23541 if (save_reg_p (info->first_fp_reg_save + i))
23542 emit_frame_save (frame_reg_rtx,
23543 (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
23544 ? DFmode : SFmode),
23545 info->first_fp_reg_save + i,
23546 info->fp_save_offset + frame_off + 8 * i,
23547 sp_off - frame_off);
23549 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
23551 bool lr = (strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
23552 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
23553 unsigned ptr_regno = ptr_regno_for_savres (sel);
23554 rtx ptr_reg = frame_reg_rtx;
23556 if (REGNO (frame_reg_rtx) == ptr_regno)
23557 gcc_checking_assert (frame_off == 0);
23560 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
23561 NOT_INUSE (ptr_regno);
23562 emit_insn (gen_add3_insn (ptr_reg,
23563 frame_reg_rtx, GEN_INT (frame_off)));
23565 insn = rs6000_emit_savres_rtx (info, ptr_reg,
23566 info->fp_save_offset,
23567 info->lr_save_offset,
23569 rs6000_frame_related (insn, ptr_reg, sp_off,
23570 NULL_RTX, NULL_RTX, NULL_RTX);
23575 /* Save GPRs. This is done as a PARALLEL if we are using
23576 the store-multiple instructions. */
23577 if (!WORLD_SAVE_P (info)
23579 && info->spe_64bit_regs_used != 0
23580 && info->first_gp_reg_save != 32)
23583 rtx spe_save_area_ptr;
23584 HOST_WIDE_INT save_off;
23585 int ool_adjust = 0;
23587 /* Determine whether we can address all of the registers that need
23588 to be saved with an offset from frame_reg_rtx that fits in
23589 the small const field for SPE memory instructions. */
23590 int spe_regs_addressable
23591 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off
23592 + reg_size * (32 - info->first_gp_reg_save - 1))
23593 && (strategy & SAVE_INLINE_GPRS));
23595 if (spe_regs_addressable)
23597 spe_save_area_ptr = frame_reg_rtx;
23598 save_off = frame_off;
23602 /* Make r11 point to the start of the SPE save area. We need
23603 to be careful here if r11 is holding the static chain. If
23604 it is, then temporarily save it in r0. */
23605 HOST_WIDE_INT offset;
23607 if (!(strategy & SAVE_INLINE_GPRS))
23608 ool_adjust = 8 * (info->first_gp_reg_save - FIRST_SAVED_GP_REGNO);
23609 offset = info->spe_gp_save_offset + frame_off - ool_adjust;
23610 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
23611 save_off = frame_off - offset;
23613 if (using_static_chain_p)
23615 rtx r0 = gen_rtx_REG (Pmode, 0);
23618 gcc_assert (info->first_gp_reg_save > 11);
23620 emit_move_insn (r0, spe_save_area_ptr);
23622 else if (REGNO (frame_reg_rtx) != 11)
23625 emit_insn (gen_addsi3 (spe_save_area_ptr,
23626 frame_reg_rtx, GEN_INT (offset)));
23627 if (!using_static_chain_p && REGNO (frame_reg_rtx) == 11)
23628 frame_off = -info->spe_gp_save_offset + ool_adjust;
23631 if ((strategy & SAVE_INLINE_GPRS))
23633 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
23634 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
23635 emit_frame_save (spe_save_area_ptr, reg_mode,
23636 info->first_gp_reg_save + i,
23637 (info->spe_gp_save_offset + save_off
23639 sp_off - save_off);
23643 insn = rs6000_emit_savres_rtx (info, spe_save_area_ptr,
23644 info->spe_gp_save_offset + save_off,
23646 SAVRES_SAVE | SAVRES_GPR);
23648 rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off,
23649 NULL_RTX, NULL_RTX, NULL_RTX);
23652 /* Move the static chain pointer back. */
23653 if (!spe_regs_addressable)
23655 if (using_static_chain_p)
23657 emit_move_insn (spe_save_area_ptr, gen_rtx_REG (Pmode, 0));
23660 else if (REGNO (frame_reg_rtx) != 11)
23664 else if (!WORLD_SAVE_P (info) && !(strategy & SAVE_INLINE_GPRS))
23666 bool lr = (strategy & SAVE_NOINLINE_GPRS_SAVES_LR) != 0;
23667 int sel = SAVRES_SAVE | SAVRES_GPR | (lr ? SAVRES_LR : 0);
23668 unsigned ptr_regno = ptr_regno_for_savres (sel);
23669 rtx ptr_reg = frame_reg_rtx;
23670 bool ptr_set_up = REGNO (ptr_reg) == ptr_regno;
23671 int end_save = info->gp_save_offset + info->gp_size;
23675 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
23677 /* Need to adjust r11 (r12) if we saved any FPRs. */
23678 if (end_save + frame_off != 0)
23680 rtx offset = GEN_INT (end_save + frame_off);
23683 frame_off = -end_save;
23685 NOT_INUSE (ptr_regno);
23686 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
23688 else if (!ptr_set_up)
23690 NOT_INUSE (ptr_regno);
23691 emit_move_insn (ptr_reg, frame_reg_rtx);
23693 ptr_off = -end_save;
23694 insn = rs6000_emit_savres_rtx (info, ptr_reg,
23695 info->gp_save_offset + ptr_off,
23696 info->lr_save_offset + ptr_off,
23698 rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off,
23699 NULL_RTX, NULL_RTX, NULL_RTX);
23703 else if (!WORLD_SAVE_P (info) && (strategy & SAVRES_MULTIPLE))
23707 p = rtvec_alloc (32 - info->first_gp_reg_save);
23708 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
23710 = gen_frame_store (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
23712 info->gp_save_offset + frame_off + reg_size * i);
23713 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
23714 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
23715 NULL_RTX, NULL_RTX, NULL_RTX);
23717 else if (!WORLD_SAVE_P (info))
23720 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
23721 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
23722 emit_frame_save (frame_reg_rtx, reg_mode,
23723 info->first_gp_reg_save + i,
23724 info->gp_save_offset + frame_off + reg_size * i,
23725 sp_off - frame_off);
23728 if (crtl->calls_eh_return)
23735 unsigned int regno = EH_RETURN_DATA_REGNO (i);
23736 if (regno == INVALID_REGNUM)
23740 p = rtvec_alloc (i);
23744 unsigned int regno = EH_RETURN_DATA_REGNO (i);
23745 if (regno == INVALID_REGNUM)
23749 = gen_frame_store (gen_rtx_REG (reg_mode, regno),
23751 info->ehrd_offset + sp_off + reg_size * (int) i);
23752 RTVEC_ELT (p, i) = insn;
23753 RTX_FRAME_RELATED_P (insn) = 1;
23756 insn = emit_insn (gen_blockage ());
23757 RTX_FRAME_RELATED_P (insn) = 1;
23758 add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_PARALLEL (VOIDmode, p));
23761 /* In AIX ABI we need to make sure r2 is really saved. */
23762 if (TARGET_AIX && crtl->calls_eh_return)
23764 rtx tmp_reg, tmp_reg_si, hi, lo, compare_result, toc_save_done, jump;
23765 rtx save_insn, join_insn, note;
23766 long toc_restore_insn;
23768 tmp_reg = gen_rtx_REG (Pmode, 11);
23769 tmp_reg_si = gen_rtx_REG (SImode, 11);
23770 if (using_static_chain_p)
23773 emit_move_insn (gen_rtx_REG (Pmode, 0), tmp_reg);
23777 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, LR_REGNO));
23778 /* Peek at instruction to which this function returns. If it's
23779 restoring r2, then we know we've already saved r2. We can't
23780 unconditionally save r2 because the value we have will already
23781 be updated if we arrived at this function via a plt call or
23782 toc adjusting stub. */
23783 emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg));
23784 toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000)
23785 + RS6000_TOC_SAVE_SLOT);
23786 hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode);
23787 emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi));
23788 compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO);
23789 validate_condition_mode (EQ, CCUNSmode);
23790 lo = gen_int_mode (toc_restore_insn & 0xffff, SImode);
23791 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
23792 gen_rtx_COMPARE (CCUNSmode, tmp_reg_si, lo)));
23793 toc_save_done = gen_label_rtx ();
23794 jump = gen_rtx_IF_THEN_ELSE (VOIDmode,
23795 gen_rtx_EQ (VOIDmode, compare_result,
23797 gen_rtx_LABEL_REF (VOIDmode, toc_save_done),
23799 jump = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, jump));
23800 JUMP_LABEL (jump) = toc_save_done;
23801 LABEL_NUSES (toc_save_done) += 1;
23803 save_insn = emit_frame_save (frame_reg_rtx, reg_mode,
23804 TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT,
23805 sp_off - frame_off);
23807 emit_label (toc_save_done);
23809 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
23810 have a CFG that has different saves along different paths.
23811 Move the note to a dummy blockage insn, which describes that
23812 R2 is unconditionally saved after the label. */
23813 /* ??? An alternate representation might be a special insn pattern
23814 containing both the branch and the store. That might let the
23815 code that minimizes the number of DW_CFA_advance opcodes better
23816 freedom in placing the annotations. */
23817 note = find_reg_note (save_insn, REG_FRAME_RELATED_EXPR, NULL);
23819 remove_note (save_insn, note);
23821 note = alloc_reg_note (REG_FRAME_RELATED_EXPR,
23822 copy_rtx (PATTERN (save_insn)), NULL_RTX);
23823 RTX_FRAME_RELATED_P (save_insn) = 0;
23825 join_insn = emit_insn (gen_blockage ());
23826 REG_NOTES (join_insn) = note;
23827 RTX_FRAME_RELATED_P (join_insn) = 1;
23829 if (using_static_chain_p)
23831 emit_move_insn (tmp_reg, gen_rtx_REG (Pmode, 0));
23838 /* Save CR if we use any that must be preserved. */
23839 if (!WORLD_SAVE_P (info) && info->cr_save_p)
23841 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
23842 GEN_INT (info->cr_save_offset + frame_off));
23843 rtx mem = gen_frame_mem (SImode, addr);
23845 /* If we didn't copy cr before, do so now using r0. */
23846 if (cr_save_rtx == NULL_RTX)
23849 cr_save_rtx = gen_rtx_REG (SImode, 0);
23850 rs6000_emit_move_from_cr (cr_save_rtx);
23853 /* Saving CR requires a two-instruction sequence: one instruction
23854 to move the CR to a general-purpose register, and a second
23855 instruction that stores the GPR to memory.
23857 We do not emit any DWARF CFI records for the first of these,
23858 because we cannot properly represent the fact that CR is saved in
23859 a register. One reason is that we cannot express that multiple
23860 CR fields are saved; another reason is that on 64-bit, the size
23861 of the CR register in DWARF (4 bytes) differs from the size of
23862 a general-purpose register.
23864 This means if any intervening instruction were to clobber one of
23865 the call-saved CR fields, we'd have incorrect CFI. To prevent
23866 this from happening, we mark the store to memory as a use of
23867 those CR fields, which prevents any such instruction from being
23868 scheduled in between the two instructions. */
23873 crsave_v[n_crsave++] = gen_rtx_SET (VOIDmode, mem, cr_save_rtx);
23874 for (i = 0; i < 8; i++)
23875 if (save_reg_p (CR0_REGNO + i))
23876 crsave_v[n_crsave++]
23877 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
23879 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode,
23880 gen_rtvec_v (n_crsave, crsave_v)));
23881 END_USE (REGNO (cr_save_rtx));
23883 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
23884 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
23885 so we need to construct a frame expression manually. */
23886 RTX_FRAME_RELATED_P (insn) = 1;
23888 /* Update address to be stack-pointer relative, like
23889 rs6000_frame_related would do. */
23890 addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM),
23891 GEN_INT (info->cr_save_offset + sp_off));
23892 mem = gen_frame_mem (SImode, addr);
23894 if (DEFAULT_ABI == ABI_ELFv2)
23896 /* In the ELFv2 ABI we generate separate CFI records for each
23897 CR field that was actually saved. They all point to the
23898 same 32-bit stack slot. */
23902 for (i = 0; i < 8; i++)
23903 if (save_reg_p (CR0_REGNO + i))
23906 = gen_rtx_SET (VOIDmode, mem,
23907 gen_rtx_REG (SImode, CR0_REGNO + i));
23909 RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1;
23913 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
23914 gen_rtx_PARALLEL (VOIDmode,
23915 gen_rtvec_v (n_crframe, crframe)));
23919 /* In other ABIs, by convention, we use a single CR regnum to
23920 represent the fact that all call-saved CR fields are saved.
23921 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
23922 rtx set = gen_rtx_SET (VOIDmode, mem,
23923 gen_rtx_REG (SImode, CR2_REGNO));
23924 add_reg_note (insn, REG_FRAME_RELATED_EXPR, set);
23928 /* In the ELFv2 ABI we need to save all call-saved CR fields into
23929 *separate* slots if the routine calls __builtin_eh_return, so
23930 that they can be independently restored by the unwinder. */
23931 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
23933 int i, cr_off = info->ehcr_offset;
23936 /* ??? We might get better performance by using multiple mfocrf
23938 crsave = gen_rtx_REG (SImode, 0);
23939 emit_insn (gen_movesi_from_cr (crsave));
23941 for (i = 0; i < 8; i++)
23942 if (!call_used_regs[CR0_REGNO + i])
23944 rtvec p = rtvec_alloc (2);
23946 = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off);
23948 = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i));
23950 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
23952 RTX_FRAME_RELATED_P (insn) = 1;
23953 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
23954 gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i),
23955 sp_reg_rtx, cr_off + sp_off));
23957 cr_off += reg_size;
23961 /* Update stack and set back pointer unless this is V.4,
23962 for which it was done previously. */
23963 if (!WORLD_SAVE_P (info) && info->push_p
23964 && !(DEFAULT_ABI == ABI_V4 || crtl->calls_eh_return))
23966 rtx ptr_reg = NULL;
23969 /* If saving altivec regs we need to be able to address all save
23970 locations using a 16-bit offset. */
23971 if ((strategy & SAVE_INLINE_VRS) == 0
23972 || (info->altivec_size != 0
23973 && (info->altivec_save_offset + info->altivec_size - 16
23974 + info->total_size - frame_off) > 32767)
23975 || (info->vrsave_size != 0
23976 && (info->vrsave_save_offset
23977 + info->total_size - frame_off) > 32767))
23979 int sel = SAVRES_SAVE | SAVRES_VR;
23980 unsigned ptr_regno = ptr_regno_for_savres (sel);
23982 if (using_static_chain_p
23983 && ptr_regno == STATIC_CHAIN_REGNUM)
23985 if (REGNO (frame_reg_rtx) != ptr_regno)
23986 START_USE (ptr_regno);
23987 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
23988 frame_reg_rtx = ptr_reg;
23989 ptr_off = info->altivec_save_offset + info->altivec_size;
23990 frame_off = -ptr_off;
23992 else if (REGNO (frame_reg_rtx) == 1)
23993 frame_off = info->total_size;
23994 rs6000_emit_allocate_stack (info->total_size, ptr_reg, ptr_off);
23995 sp_off = info->total_size;
23996 if (frame_reg_rtx != sp_reg_rtx)
23997 rs6000_emit_stack_tie (frame_reg_rtx, false);
24000 /* Set frame pointer, if needed. */
24001 if (frame_pointer_needed)
24003 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
24005 RTX_FRAME_RELATED_P (insn) = 1;
24008 /* Save AltiVec registers if needed. Save here because the red zone does
24009 not always include AltiVec registers. */
24010 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI
24011 && info->altivec_size != 0 && (strategy & SAVE_INLINE_VRS) == 0)
24013 int end_save = info->altivec_save_offset + info->altivec_size;
24015 /* Oddly, the vector save/restore functions point r0 at the end
24016 of the save area, then use r11 or r12 to load offsets for
24017 [reg+reg] addressing. */
24018 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
24019 int scratch_regno = ptr_regno_for_savres (SAVRES_SAVE | SAVRES_VR);
24020 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
24022 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
24024 if (end_save + frame_off != 0)
24026 rtx offset = GEN_INT (end_save + frame_off);
24028 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
24031 emit_move_insn (ptr_reg, frame_reg_rtx);
24033 ptr_off = -end_save;
24034 insn = rs6000_emit_savres_rtx (info, scratch_reg,
24035 info->altivec_save_offset + ptr_off,
24036 0, V4SImode, SAVRES_SAVE | SAVRES_VR);
24037 rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off,
24038 NULL_RTX, NULL_RTX, NULL_RTX);
24039 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
24041 /* The oddity mentioned above clobbered our frame reg. */
24042 emit_move_insn (frame_reg_rtx, ptr_reg);
24043 frame_off = ptr_off;
24046 else if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI
24047 && info->altivec_size != 0)
24051 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
24052 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
24054 rtx areg, savereg, mem, split_reg;
24057 offset = (info->altivec_save_offset + frame_off
24058 + 16 * (i - info->first_altivec_reg_save));
24060 savereg = gen_rtx_REG (V4SImode, i);
24063 areg = gen_rtx_REG (Pmode, 0);
24064 emit_move_insn (areg, GEN_INT (offset));
24066 /* AltiVec addressing mode is [reg+reg]. */
24067 mem = gen_frame_mem (V4SImode,
24068 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
24070 insn = emit_move_insn (mem, savereg);
24072 /* When we split a VSX store into two insns, we need to make
24073 sure the DWARF info knows which register we are storing.
24074 Pass it in to be used on the appropriate note. */
24075 if (!BYTES_BIG_ENDIAN
24076 && GET_CODE (PATTERN (insn)) == SET
24077 && GET_CODE (SET_SRC (PATTERN (insn))) == VEC_SELECT)
24078 split_reg = savereg;
24080 split_reg = NULL_RTX;
24082 rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off,
24083 areg, GEN_INT (offset), split_reg);
24087 /* VRSAVE is a bit vector representing which AltiVec registers
24088 are used. The OS uses this to determine which vector
24089 registers to save on a context switch. We need to save
24090 VRSAVE on the stack frame, add whatever AltiVec registers we
24091 used in this function, and do the corresponding magic in the
24094 if (!WORLD_SAVE_P (info)
24096 && TARGET_ALTIVEC_VRSAVE
24097 && info->vrsave_mask != 0)
24103 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
24104 be using r12 as frame_reg_rtx and r11 as the static chain
24105 pointer for nested functions. */
24107 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
24108 && !using_static_chain_p)
24110 else if (REGNO (frame_reg_rtx) == 12)
24113 if (using_static_chain_p)
24117 NOT_INUSE (save_regno);
24118 reg = gen_rtx_REG (SImode, save_regno);
24119 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
24121 emit_insn (gen_get_vrsave_internal (reg));
24123 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
24126 offset = info->vrsave_save_offset + frame_off;
24127 insn = emit_insn (gen_frame_store (reg, frame_reg_rtx, offset));
24129 /* Include the registers in the mask. */
24130 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
24132 insn = emit_insn (generate_set_vrsave (reg, info, 0));
24135 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
24136 if (!TARGET_SINGLE_PIC_BASE
24137 && ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
24138 || (DEFAULT_ABI == ABI_V4
24139 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
24140 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))))
24142 /* If emit_load_toc_table will use the link register, we need to save
24143 it. We use R12 for this purpose because emit_load_toc_table
24144 can use register 0. This allows us to use a plain 'blr' to return
24145 from the procedure more often. */
24146 int save_LR_around_toc_setup = (TARGET_ELF
24147 && DEFAULT_ABI == ABI_V4
24149 && ! info->lr_save_p
24150 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) > 0);
24151 if (save_LR_around_toc_setup)
24153 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
24154 rtx tmp = gen_rtx_REG (Pmode, 12);
24156 insn = emit_move_insn (tmp, lr);
24157 RTX_FRAME_RELATED_P (insn) = 1;
24159 rs6000_emit_load_toc_table (TRUE);
24161 insn = emit_move_insn (lr, tmp);
24162 add_reg_note (insn, REG_CFA_RESTORE, lr);
24163 RTX_FRAME_RELATED_P (insn) = 1;
24166 rs6000_emit_load_toc_table (TRUE);
24170 if (!TARGET_SINGLE_PIC_BASE
24171 && DEFAULT_ABI == ABI_DARWIN
24172 && flag_pic && crtl->uses_pic_offset_table)
24174 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
24175 rtx src = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
24177 /* Save and restore LR locally around this call (in R0). */
24178 if (!info->lr_save_p)
24179 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
24181 emit_insn (gen_load_macho_picbase (src));
24183 emit_move_insn (gen_rtx_REG (Pmode,
24184 RS6000_PIC_OFFSET_TABLE_REGNUM),
24187 if (!info->lr_save_p)
24188 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
24192 /* If we need to, save the TOC register after doing the stack setup.
24193 Do not emit eh frame info for this save. The unwinder wants info,
24194 conceptually attached to instructions in this function, about
24195 register values in the caller of this function. This R2 may have
24196 already been changed from the value in the caller.
24197 We don't attempt to write accurate DWARF EH frame info for R2
24198 because code emitted by gcc for a (non-pointer) function call
24199 doesn't save and restore R2. Instead, R2 is managed out-of-line
24200 by a linker generated plt call stub when the function resides in
24201 a shared library. This behaviour is costly to describe in DWARF,
24202 both in terms of the size of DWARF info and the time taken in the
24203 unwinder to interpret it. R2 changes, apart from the
24204 calls_eh_return case earlier in this function, are handled by
24205 linux-unwind.h frob_update_context. */
24206 if (rs6000_save_toc_in_prologue_p ())
24208 rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM);
24209 emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT));
24213 /* Write function prologue. */
24216 rs6000_output_function_prologue (FILE *file,
24217 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
24219 rs6000_stack_t *info = rs6000_stack_info ();
24221 if (TARGET_DEBUG_STACK)
24222 debug_stack_info (info);
24224 /* Write .extern for any function we will call to save and restore
24226 if (info->first_fp_reg_save < 64
24231 int regno = info->first_fp_reg_save - 32;
24233 if ((info->savres_strategy & SAVE_INLINE_FPRS) == 0)
24235 bool lr = (info->savres_strategy & SAVE_NOINLINE_FPRS_SAVES_LR) != 0;
24236 int sel = SAVRES_SAVE | SAVRES_FPR | (lr ? SAVRES_LR : 0);
24237 name = rs6000_savres_routine_name (info, regno, sel);
24238 fprintf (file, "\t.extern %s\n", name);
24240 if ((info->savres_strategy & REST_INLINE_FPRS) == 0)
24242 bool lr = (info->savres_strategy
24243 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
24244 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
24245 name = rs6000_savres_routine_name (info, regno, sel);
24246 fprintf (file, "\t.extern %s\n", name);
24250 /* ELFv2 ABI r2 setup code and local entry point. This must follow
24251 immediately after the global entry point label. */
24252 if (DEFAULT_ABI == ABI_ELFv2 && cfun->machine->r2_setup_needed)
24254 const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
24256 fprintf (file, "0:\taddis 2,12,.TOC.-0b@ha\n");
24257 fprintf (file, "\taddi 2,2,.TOC.-0b@l\n");
24259 fputs ("\t.localentry\t", file);
24260 assemble_name (file, name);
24261 fputs (",.-", file);
24262 assemble_name (file, name);
24263 fputs ("\n", file);
24266 /* Output -mprofile-kernel code. This needs to be done here instead of
24267 in output_function_profile since it must go after the ELFv2 ABI
24268 local entry point. */
24269 if (TARGET_PROFILE_KERNEL && crtl->profile)
24271 gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2);
24272 gcc_assert (!TARGET_32BIT);
24274 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
24275 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
24277 /* In the ELFv2 ABI we have no compiler stack word. It must be
24278 the resposibility of _mcount to preserve the static chain
24279 register if required. */
24280 if (DEFAULT_ABI != ABI_ELFv2
24281 && cfun->static_chain_decl != NULL)
24283 asm_fprintf (file, "\tstd %s,24(%s)\n",
24284 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
24285 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
24286 asm_fprintf (file, "\tld %s,24(%s)\n",
24287 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
24290 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
24293 rs6000_pic_labelno++;
24296 /* Non-zero if vmx regs are restored before the frame pop, zero if
24297 we restore after the pop when possible. */
24298 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
24300 /* Restoring cr is a two step process: loading a reg from the frame
24301 save, then moving the reg to cr. For ABI_V4 we must let the
24302 unwinder know that the stack location is no longer valid at or
24303 before the stack deallocation, but we can't emit a cfa_restore for
24304 cr at the stack deallocation like we do for other registers.
24305 The trouble is that it is possible for the move to cr to be
24306 scheduled after the stack deallocation. So say exactly where cr
24307 is located on each of the two insns. */
24310 load_cr_save (int regno, rtx frame_reg_rtx, int offset, bool exit_func)
24312 rtx mem = gen_frame_mem_offset (SImode, frame_reg_rtx, offset);
24313 rtx reg = gen_rtx_REG (SImode, regno);
24314 rtx_insn *insn = emit_move_insn (reg, mem);
24316 if (!exit_func && DEFAULT_ABI == ABI_V4)
24318 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
24319 rtx set = gen_rtx_SET (VOIDmode, reg, cr);
24321 add_reg_note (insn, REG_CFA_REGISTER, set);
24322 RTX_FRAME_RELATED_P (insn) = 1;
24327 /* Reload CR from REG. */
24330 restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func)
24335 if (using_mfcr_multiple)
24337 for (i = 0; i < 8; i++)
24338 if (save_reg_p (CR0_REGNO + i))
24340 gcc_assert (count);
24343 if (using_mfcr_multiple && count > 1)
24349 p = rtvec_alloc (count);
24352 for (i = 0; i < 8; i++)
24353 if (save_reg_p (CR0_REGNO + i))
24355 rtvec r = rtvec_alloc (2);
24356 RTVEC_ELT (r, 0) = reg;
24357 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
24358 RTVEC_ELT (p, ndx) =
24359 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i),
24360 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
24363 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
24364 gcc_assert (ndx == count);
24366 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
24367 CR field separately. */
24368 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
24370 for (i = 0; i < 8; i++)
24371 if (save_reg_p (CR0_REGNO + i))
24372 add_reg_note (insn, REG_CFA_RESTORE,
24373 gen_rtx_REG (SImode, CR0_REGNO + i));
24375 RTX_FRAME_RELATED_P (insn) = 1;
24379 for (i = 0; i < 8; i++)
24380 if (save_reg_p (CR0_REGNO + i))
24382 rtx insn = emit_insn (gen_movsi_to_cr_one
24383 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
24385 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
24386 CR field separately, attached to the insn that in fact
24387 restores this particular CR field. */
24388 if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap)
24390 add_reg_note (insn, REG_CFA_RESTORE,
24391 gen_rtx_REG (SImode, CR0_REGNO + i));
24393 RTX_FRAME_RELATED_P (insn) = 1;
24397 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
24398 if (!exit_func && DEFAULT_ABI != ABI_ELFv2
24399 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
24401 rtx_insn *insn = get_last_insn ();
24402 rtx cr = gen_rtx_REG (SImode, CR2_REGNO);
24404 add_reg_note (insn, REG_CFA_RESTORE, cr);
24405 RTX_FRAME_RELATED_P (insn) = 1;
24409 /* Like cr, the move to lr instruction can be scheduled after the
24410 stack deallocation, but unlike cr, its stack frame save is still
24411 valid. So we only need to emit the cfa_restore on the correct
24415 load_lr_save (int regno, rtx frame_reg_rtx, int offset)
24417 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, offset);
24418 rtx reg = gen_rtx_REG (Pmode, regno);
24420 emit_move_insn (reg, mem);
24424 restore_saved_lr (int regno, bool exit_func)
24426 rtx reg = gen_rtx_REG (Pmode, regno);
24427 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
24428 rtx_insn *insn = emit_move_insn (lr, reg);
24430 if (!exit_func && flag_shrink_wrap)
24432 add_reg_note (insn, REG_CFA_RESTORE, lr);
24433 RTX_FRAME_RELATED_P (insn) = 1;
24438 add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores)
24440 if (DEFAULT_ABI == ABI_ELFv2)
24443 for (i = 0; i < 8; i++)
24444 if (save_reg_p (CR0_REGNO + i))
24446 rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i);
24447 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr,
24451 else if (info->cr_save_p)
24452 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
24453 gen_rtx_REG (SImode, CR2_REGNO),
24456 if (info->lr_save_p)
24457 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
24458 gen_rtx_REG (Pmode, LR_REGNO),
24460 return cfa_restores;
24463 /* Return true if OFFSET from stack pointer can be clobbered by signals.
24464 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
24465 below stack pointer not cloberred by signals. */
24468 offset_below_red_zone_p (HOST_WIDE_INT offset)
24470 return offset < (DEFAULT_ABI == ABI_V4
24472 : TARGET_32BIT ? -220 : -288);
24475 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
24478 emit_cfa_restores (rtx cfa_restores)
24480 rtx_insn *insn = get_last_insn ();
24481 rtx *loc = ®_NOTES (insn);
24484 loc = &XEXP (*loc, 1);
24485 *loc = cfa_restores;
24486 RTX_FRAME_RELATED_P (insn) = 1;
24489 /* Emit function epilogue as insns. */
24492 rs6000_emit_epilogue (int sibcall)
24494 rs6000_stack_t *info;
24495 int restoring_GPRs_inline;
24496 int restoring_FPRs_inline;
24497 int using_load_multiple;
24498 int using_mtcr_multiple;
24499 int use_backchain_to_restore_sp;
24502 HOST_WIDE_INT frame_off = 0;
24503 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
24504 rtx frame_reg_rtx = sp_reg_rtx;
24505 rtx cfa_restores = NULL_RTX;
24507 rtx cr_save_reg = NULL_RTX;
24508 machine_mode reg_mode = Pmode;
24509 int reg_size = TARGET_32BIT ? 4 : 8;
24512 unsigned ptr_regno;
24514 info = rs6000_stack_info ();
24516 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
24518 reg_mode = V2SImode;
24522 strategy = info->savres_strategy;
24523 using_load_multiple = strategy & SAVRES_MULTIPLE;
24524 restoring_FPRs_inline = sibcall || (strategy & REST_INLINE_FPRS);
24525 restoring_GPRs_inline = sibcall || (strategy & REST_INLINE_GPRS);
24526 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
24527 || rs6000_cpu == PROCESSOR_PPC603
24528 || rs6000_cpu == PROCESSOR_PPC750
24530 /* Restore via the backchain when we have a large frame, since this
24531 is more efficient than an addis, addi pair. The second condition
24532 here will not trigger at the moment; We don't actually need a
24533 frame pointer for alloca, but the generic parts of the compiler
24534 give us one anyway. */
24535 use_backchain_to_restore_sp = (info->total_size > 32767 - info->lr_save_offset
24536 || (cfun->calls_alloca
24537 && !frame_pointer_needed));
24538 restore_lr = (info->lr_save_p
24539 && (restoring_FPRs_inline
24540 || (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR))
24541 && (restoring_GPRs_inline
24542 || info->first_fp_reg_save < 64));
24544 if (WORLD_SAVE_P (info))
24548 const char *alloc_rname;
24551 /* eh_rest_world_r10 will return to the location saved in the LR
24552 stack slot (which is not likely to be our caller.)
24553 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
24554 rest_world is similar, except any R10 parameter is ignored.
24555 The exception-handling stuff that was here in 2.95 is no
24556 longer necessary. */
24560 + 32 - info->first_gp_reg_save
24561 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
24562 + 63 + 1 - info->first_fp_reg_save);
24564 strcpy (rname, ((crtl->calls_eh_return) ?
24565 "*eh_rest_world_r10" : "*rest_world"));
24566 alloc_rname = ggc_strdup (rname);
24569 RTVEC_ELT (p, j++) = ret_rtx;
24570 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
24571 gen_rtx_REG (Pmode,
24574 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
24575 /* The instruction pattern requires a clobber here;
24576 it is shared with the restVEC helper. */
24578 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
24581 /* CR register traditionally saved as CR2. */
24582 rtx reg = gen_rtx_REG (SImode, CR2_REGNO);
24584 = gen_frame_load (reg, frame_reg_rtx, info->cr_save_offset);
24585 if (flag_shrink_wrap)
24587 cfa_restores = alloc_reg_note (REG_CFA_RESTORE,
24588 gen_rtx_REG (Pmode, LR_REGNO),
24590 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
24594 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
24596 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
24598 = gen_frame_load (reg,
24599 frame_reg_rtx, info->gp_save_offset + reg_size * i);
24600 if (flag_shrink_wrap)
24601 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
24603 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
24605 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
24607 = gen_frame_load (reg,
24608 frame_reg_rtx, info->altivec_save_offset + 16 * i);
24609 if (flag_shrink_wrap)
24610 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
24612 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
24614 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
24615 ? DFmode : SFmode),
24616 info->first_fp_reg_save + i);
24618 = gen_frame_load (reg, frame_reg_rtx, info->fp_save_offset + 8 * i);
24619 if (flag_shrink_wrap)
24620 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
24623 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
24625 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
24627 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
24629 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
24631 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
24632 insn = emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
24634 if (flag_shrink_wrap)
24636 REG_NOTES (insn) = cfa_restores;
24637 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
24638 RTX_FRAME_RELATED_P (insn) = 1;
24643 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
24645 frame_off = info->total_size;
24647 /* Restore AltiVec registers if we must do so before adjusting the
24649 if (TARGET_ALTIVEC_ABI
24650 && info->altivec_size != 0
24651 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24652 || (DEFAULT_ABI != ABI_V4
24653 && offset_below_red_zone_p (info->altivec_save_offset))))
24656 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
24658 gcc_checking_assert (scratch_regno == 11 || scratch_regno == 12);
24659 if (use_backchain_to_restore_sp)
24661 int frame_regno = 11;
24663 if ((strategy & REST_INLINE_VRS) == 0)
24665 /* Of r11 and r12, select the one not clobbered by an
24666 out-of-line restore function for the frame register. */
24667 frame_regno = 11 + 12 - scratch_regno;
24669 frame_reg_rtx = gen_rtx_REG (Pmode, frame_regno);
24670 emit_move_insn (frame_reg_rtx,
24671 gen_rtx_MEM (Pmode, sp_reg_rtx));
24674 else if (frame_pointer_needed)
24675 frame_reg_rtx = hard_frame_pointer_rtx;
24677 if ((strategy & REST_INLINE_VRS) == 0)
24679 int end_save = info->altivec_save_offset + info->altivec_size;
24681 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
24682 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
24684 if (end_save + frame_off != 0)
24686 rtx offset = GEN_INT (end_save + frame_off);
24688 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
24691 emit_move_insn (ptr_reg, frame_reg_rtx);
24693 ptr_off = -end_save;
24694 insn = rs6000_emit_savres_rtx (info, scratch_reg,
24695 info->altivec_save_offset + ptr_off,
24696 0, V4SImode, SAVRES_VR);
24700 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
24701 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
24703 rtx addr, areg, mem, reg;
24705 areg = gen_rtx_REG (Pmode, 0);
24707 (areg, GEN_INT (info->altivec_save_offset
24709 + 16 * (i - info->first_altivec_reg_save)));
24711 /* AltiVec addressing mode is [reg+reg]. */
24712 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
24713 mem = gen_frame_mem (V4SImode, addr);
24715 reg = gen_rtx_REG (V4SImode, i);
24716 emit_move_insn (reg, mem);
24720 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
24721 if (((strategy & REST_INLINE_VRS) == 0
24722 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
24723 && (flag_shrink_wrap
24724 || (offset_below_red_zone_p
24725 (info->altivec_save_offset
24726 + 16 * (i - info->first_altivec_reg_save)))))
24728 rtx reg = gen_rtx_REG (V4SImode, i);
24729 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
24733 /* Restore VRSAVE if we must do so before adjusting the stack. */
24735 && TARGET_ALTIVEC_VRSAVE
24736 && info->vrsave_mask != 0
24737 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24738 || (DEFAULT_ABI != ABI_V4
24739 && offset_below_red_zone_p (info->vrsave_save_offset))))
24743 if (frame_reg_rtx == sp_reg_rtx)
24745 if (use_backchain_to_restore_sp)
24747 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
24748 emit_move_insn (frame_reg_rtx,
24749 gen_rtx_MEM (Pmode, sp_reg_rtx));
24752 else if (frame_pointer_needed)
24753 frame_reg_rtx = hard_frame_pointer_rtx;
24756 reg = gen_rtx_REG (SImode, 12);
24757 emit_insn (gen_frame_load (reg, frame_reg_rtx,
24758 info->vrsave_save_offset + frame_off));
24760 emit_insn (generate_set_vrsave (reg, info, 1));
24764 /* If we have a large stack frame, restore the old stack pointer
24765 using the backchain. */
24766 if (use_backchain_to_restore_sp)
24768 if (frame_reg_rtx == sp_reg_rtx)
24770 /* Under V.4, don't reset the stack pointer until after we're done
24771 loading the saved registers. */
24772 if (DEFAULT_ABI == ABI_V4)
24773 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
24775 insn = emit_move_insn (frame_reg_rtx,
24776 gen_rtx_MEM (Pmode, sp_reg_rtx));
24779 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24780 && DEFAULT_ABI == ABI_V4)
24781 /* frame_reg_rtx has been set up by the altivec restore. */
24785 insn = emit_move_insn (sp_reg_rtx, frame_reg_rtx);
24786 frame_reg_rtx = sp_reg_rtx;
24789 /* If we have a frame pointer, we can restore the old stack pointer
24791 else if (frame_pointer_needed)
24793 frame_reg_rtx = sp_reg_rtx;
24794 if (DEFAULT_ABI == ABI_V4)
24795 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
24796 /* Prevent reordering memory accesses against stack pointer restore. */
24797 else if (cfun->calls_alloca
24798 || offset_below_red_zone_p (-info->total_size))
24799 rs6000_emit_stack_tie (frame_reg_rtx, true);
24801 insn = emit_insn (gen_add3_insn (frame_reg_rtx, hard_frame_pointer_rtx,
24802 GEN_INT (info->total_size)));
24805 else if (info->push_p
24806 && DEFAULT_ABI != ABI_V4
24807 && !crtl->calls_eh_return)
24809 /* Prevent reordering memory accesses against stack pointer restore. */
24810 if (cfun->calls_alloca
24811 || offset_below_red_zone_p (-info->total_size))
24812 rs6000_emit_stack_tie (frame_reg_rtx, false);
24813 insn = emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx,
24814 GEN_INT (info->total_size)));
24817 if (insn && frame_reg_rtx == sp_reg_rtx)
24821 REG_NOTES (insn) = cfa_restores;
24822 cfa_restores = NULL_RTX;
24824 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
24825 RTX_FRAME_RELATED_P (insn) = 1;
24828 /* Restore AltiVec registers if we have not done so already. */
24829 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24830 && TARGET_ALTIVEC_ABI
24831 && info->altivec_size != 0
24832 && (DEFAULT_ABI == ABI_V4
24833 || !offset_below_red_zone_p (info->altivec_save_offset)))
24837 if ((strategy & REST_INLINE_VRS) == 0)
24839 int end_save = info->altivec_save_offset + info->altivec_size;
24841 rtx ptr_reg = gen_rtx_REG (Pmode, 0);
24842 int scratch_regno = ptr_regno_for_savres (SAVRES_VR);
24843 rtx scratch_reg = gen_rtx_REG (Pmode, scratch_regno);
24845 if (end_save + frame_off != 0)
24847 rtx offset = GEN_INT (end_save + frame_off);
24849 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx, offset));
24852 emit_move_insn (ptr_reg, frame_reg_rtx);
24854 ptr_off = -end_save;
24855 insn = rs6000_emit_savres_rtx (info, scratch_reg,
24856 info->altivec_save_offset + ptr_off,
24857 0, V4SImode, SAVRES_VR);
24858 if (REGNO (frame_reg_rtx) == REGNO (scratch_reg))
24860 /* Frame reg was clobbered by out-of-line save. Restore it
24861 from ptr_reg, and if we are calling out-of-line gpr or
24862 fpr restore set up the correct pointer and offset. */
24863 unsigned newptr_regno = 1;
24864 if (!restoring_GPRs_inline)
24866 bool lr = info->gp_save_offset + info->gp_size == 0;
24867 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
24868 newptr_regno = ptr_regno_for_savres (sel);
24869 end_save = info->gp_save_offset + info->gp_size;
24871 else if (!restoring_FPRs_inline)
24873 bool lr = !(strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR);
24874 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
24875 newptr_regno = ptr_regno_for_savres (sel);
24876 end_save = info->gp_save_offset + info->gp_size;
24879 if (newptr_regno != 1 && REGNO (frame_reg_rtx) != newptr_regno)
24880 frame_reg_rtx = gen_rtx_REG (Pmode, newptr_regno);
24882 if (end_save + ptr_off != 0)
24884 rtx offset = GEN_INT (end_save + ptr_off);
24886 frame_off = -end_save;
24887 emit_insn (gen_add3_insn (frame_reg_rtx, ptr_reg, offset));
24891 frame_off = ptr_off;
24892 emit_move_insn (frame_reg_rtx, ptr_reg);
24898 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
24899 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
24901 rtx addr, areg, mem, reg;
24903 areg = gen_rtx_REG (Pmode, 0);
24905 (areg, GEN_INT (info->altivec_save_offset
24907 + 16 * (i - info->first_altivec_reg_save)));
24909 /* AltiVec addressing mode is [reg+reg]. */
24910 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
24911 mem = gen_frame_mem (V4SImode, addr);
24913 reg = gen_rtx_REG (V4SImode, i);
24914 emit_move_insn (reg, mem);
24918 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
24919 if (((strategy & REST_INLINE_VRS) == 0
24920 || (info->vrsave_mask & ALTIVEC_REG_BIT (i)) != 0)
24921 && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap))
24923 rtx reg = gen_rtx_REG (V4SImode, i);
24924 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
24928 /* Restore VRSAVE if we have not done so already. */
24929 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
24931 && TARGET_ALTIVEC_VRSAVE
24932 && info->vrsave_mask != 0
24933 && (DEFAULT_ABI == ABI_V4
24934 || !offset_below_red_zone_p (info->vrsave_save_offset)))
24938 reg = gen_rtx_REG (SImode, 12);
24939 emit_insn (gen_frame_load (reg, frame_reg_rtx,
24940 info->vrsave_save_offset + frame_off));
24942 emit_insn (generate_set_vrsave (reg, info, 1));
24945 /* If we exit by an out-of-line restore function on ABI_V4 then that
24946 function will deallocate the stack, so we don't need to worry
24947 about the unwinder restoring cr from an invalid stack frame
24949 exit_func = (!restoring_FPRs_inline
24950 || (!restoring_GPRs_inline
24951 && info->first_fp_reg_save == 64));
24953 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
24954 *separate* slots if the routine calls __builtin_eh_return, so
24955 that they can be independently restored by the unwinder. */
24956 if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return)
24958 int i, cr_off = info->ehcr_offset;
24960 for (i = 0; i < 8; i++)
24961 if (!call_used_regs[CR0_REGNO + i])
24963 rtx reg = gen_rtx_REG (SImode, 0);
24964 emit_insn (gen_frame_load (reg, frame_reg_rtx,
24965 cr_off + frame_off));
24967 insn = emit_insn (gen_movsi_to_cr_one
24968 (gen_rtx_REG (CCmode, CR0_REGNO + i), reg));
24970 if (!exit_func && flag_shrink_wrap)
24972 add_reg_note (insn, REG_CFA_RESTORE,
24973 gen_rtx_REG (SImode, CR0_REGNO + i));
24975 RTX_FRAME_RELATED_P (insn) = 1;
24978 cr_off += reg_size;
24982 /* Get the old lr if we saved it. If we are restoring registers
24983 out-of-line, then the out-of-line routines can do this for us. */
24984 if (restore_lr && restoring_GPRs_inline)
24985 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
24987 /* Get the old cr if we saved it. */
24988 if (info->cr_save_p)
24990 unsigned cr_save_regno = 12;
24992 if (!restoring_GPRs_inline)
24994 /* Ensure we don't use the register used by the out-of-line
24995 gpr register restore below. */
24996 bool lr = info->gp_save_offset + info->gp_size == 0;
24997 int sel = SAVRES_GPR | (lr ? SAVRES_LR : 0);
24998 int gpr_ptr_regno = ptr_regno_for_savres (sel);
25000 if (gpr_ptr_regno == 12)
25001 cr_save_regno = 11;
25002 gcc_checking_assert (REGNO (frame_reg_rtx) != cr_save_regno);
25004 else if (REGNO (frame_reg_rtx) == 12)
25005 cr_save_regno = 11;
25007 cr_save_reg = load_cr_save (cr_save_regno, frame_reg_rtx,
25008 info->cr_save_offset + frame_off,
25012 /* Set LR here to try to overlap restores below. */
25013 if (restore_lr && restoring_GPRs_inline)
25014 restore_saved_lr (0, exit_func);
25016 /* Load exception handler data registers, if needed. */
25017 if (crtl->calls_eh_return)
25019 unsigned int i, regno;
25023 rtx reg = gen_rtx_REG (reg_mode, 2);
25024 emit_insn (gen_frame_load (reg, frame_reg_rtx,
25025 frame_off + RS6000_TOC_SAVE_SLOT));
25032 regno = EH_RETURN_DATA_REGNO (i);
25033 if (regno == INVALID_REGNUM)
25036 /* Note: possible use of r0 here to address SPE regs. */
25037 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
25038 info->ehrd_offset + frame_off
25039 + reg_size * (int) i);
25041 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
25045 /* Restore GPRs. This is done as a PARALLEL if we are using
25046 the load-multiple instructions. */
25048 && info->spe_64bit_regs_used
25049 && info->first_gp_reg_save != 32)
25051 /* Determine whether we can address all of the registers that need
25052 to be saved with an offset from frame_reg_rtx that fits in
25053 the small const field for SPE memory instructions. */
25054 int spe_regs_addressable
25055 = (SPE_CONST_OFFSET_OK (info->spe_gp_save_offset + frame_off
25056 + reg_size * (32 - info->first_gp_reg_save - 1))
25057 && restoring_GPRs_inline);
25059 if (!spe_regs_addressable)
25061 int ool_adjust = 0;
25062 rtx old_frame_reg_rtx = frame_reg_rtx;
25063 /* Make r11 point to the start of the SPE save area. We worried about
25064 not clobbering it when we were saving registers in the prologue.
25065 There's no need to worry here because the static chain is passed
25066 anew to every function. */
25068 if (!restoring_GPRs_inline)
25069 ool_adjust = 8 * (info->first_gp_reg_save - FIRST_SAVED_GP_REGNO);
25070 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
25071 emit_insn (gen_addsi3 (frame_reg_rtx, old_frame_reg_rtx,
25072 GEN_INT (info->spe_gp_save_offset
25075 /* Keep the invariant that frame_reg_rtx + frame_off points
25076 at the top of the stack frame. */
25077 frame_off = -info->spe_gp_save_offset + ool_adjust;
25080 if (restoring_GPRs_inline)
25082 HOST_WIDE_INT spe_offset = info->spe_gp_save_offset + frame_off;
25084 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
25085 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
25087 rtx offset, addr, mem, reg;
25089 /* We're doing all this to ensure that the immediate offset
25090 fits into the immediate field of 'evldd'. */
25091 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
25093 offset = GEN_INT (spe_offset + reg_size * i);
25094 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, offset);
25095 mem = gen_rtx_MEM (V2SImode, addr);
25096 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
25098 emit_move_insn (reg, mem);
25102 rs6000_emit_savres_rtx (info, frame_reg_rtx,
25103 info->spe_gp_save_offset + frame_off,
25104 info->lr_save_offset + frame_off,
25106 SAVRES_GPR | SAVRES_LR);
25108 else if (!restoring_GPRs_inline)
25110 /* We are jumping to an out-of-line function. */
25112 int end_save = info->gp_save_offset + info->gp_size;
25113 bool can_use_exit = end_save == 0;
25114 int sel = SAVRES_GPR | (can_use_exit ? SAVRES_LR : 0);
25117 /* Emit stack reset code if we need it. */
25118 ptr_regno = ptr_regno_for_savres (sel);
25119 ptr_reg = gen_rtx_REG (Pmode, ptr_regno);
25121 rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno);
25122 else if (end_save + frame_off != 0)
25123 emit_insn (gen_add3_insn (ptr_reg, frame_reg_rtx,
25124 GEN_INT (end_save + frame_off)));
25125 else if (REGNO (frame_reg_rtx) != ptr_regno)
25126 emit_move_insn (ptr_reg, frame_reg_rtx);
25127 if (REGNO (frame_reg_rtx) == ptr_regno)
25128 frame_off = -end_save;
25130 if (can_use_exit && info->cr_save_p)
25131 restore_saved_cr (cr_save_reg, using_mtcr_multiple, true);
25133 ptr_off = -end_save;
25134 rs6000_emit_savres_rtx (info, ptr_reg,
25135 info->gp_save_offset + ptr_off,
25136 info->lr_save_offset + ptr_off,
25139 else if (using_load_multiple)
25142 p = rtvec_alloc (32 - info->first_gp_reg_save);
25143 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
25145 = gen_frame_load (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
25147 info->gp_save_offset + frame_off + reg_size * i);
25148 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
25152 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
25153 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
25154 emit_insn (gen_frame_load
25155 (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
25157 info->gp_save_offset + frame_off + reg_size * i));
25160 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
25162 /* If the frame pointer was used then we can't delay emitting
25163 a REG_CFA_DEF_CFA note. This must happen on the insn that
25164 restores the frame pointer, r31. We may have already emitted
25165 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
25166 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
25167 be harmless if emitted. */
25168 if (frame_pointer_needed)
25170 insn = get_last_insn ();
25171 add_reg_note (insn, REG_CFA_DEF_CFA,
25172 plus_constant (Pmode, frame_reg_rtx, frame_off));
25173 RTX_FRAME_RELATED_P (insn) = 1;
25176 /* Set up cfa_restores. We always need these when
25177 shrink-wrapping. If not shrink-wrapping then we only need
25178 the cfa_restore when the stack location is no longer valid.
25179 The cfa_restores must be emitted on or before the insn that
25180 invalidates the stack, and of course must not be emitted
25181 before the insn that actually does the restore. The latter
25182 is why it is a bad idea to emit the cfa_restores as a group
25183 on the last instruction here that actually does a restore:
25184 That insn may be reordered with respect to others doing
25186 if (flag_shrink_wrap
25187 && !restoring_GPRs_inline
25188 && info->first_fp_reg_save == 64)
25189 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
25191 for (i = info->first_gp_reg_save; i < 32; i++)
25192 if (!restoring_GPRs_inline
25193 || using_load_multiple
25194 || rs6000_reg_live_or_pic_offset_p (i))
25196 rtx reg = gen_rtx_REG (reg_mode, i);
25198 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
25202 if (!restoring_GPRs_inline
25203 && info->first_fp_reg_save == 64)
25205 /* We are jumping to an out-of-line function. */
25207 emit_cfa_restores (cfa_restores);
25211 if (restore_lr && !restoring_GPRs_inline)
25213 load_lr_save (0, frame_reg_rtx, info->lr_save_offset + frame_off);
25214 restore_saved_lr (0, exit_func);
25217 /* Restore fpr's if we need to do it without calling a function. */
25218 if (restoring_FPRs_inline)
25219 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
25220 if (save_reg_p (info->first_fp_reg_save + i))
25222 rtx reg = gen_rtx_REG ((TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
25223 ? DFmode : SFmode),
25224 info->first_fp_reg_save + i);
25225 emit_insn (gen_frame_load (reg, frame_reg_rtx,
25226 info->fp_save_offset + frame_off + 8 * i));
25227 if (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)
25228 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg, cfa_restores);
25231 /* If we saved cr, restore it here. Just those that were used. */
25232 if (info->cr_save_p)
25233 restore_saved_cr (cr_save_reg, using_mtcr_multiple, exit_func);
25235 /* If this is V.4, unwind the stack pointer after all of the loads
25236 have been done, or set up r11 if we are restoring fp out of line. */
25238 if (!restoring_FPRs_inline)
25240 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
25241 int sel = SAVRES_FPR | (lr ? SAVRES_LR : 0);
25242 ptr_regno = ptr_regno_for_savres (sel);
25245 insn = rs6000_emit_stack_reset (info, frame_reg_rtx, frame_off, ptr_regno);
25246 if (REGNO (frame_reg_rtx) == ptr_regno)
25249 if (insn && restoring_FPRs_inline)
25253 REG_NOTES (insn) = cfa_restores;
25254 cfa_restores = NULL_RTX;
25256 add_reg_note (insn, REG_CFA_DEF_CFA, sp_reg_rtx);
25257 RTX_FRAME_RELATED_P (insn) = 1;
25260 if (crtl->calls_eh_return)
25262 rtx sa = EH_RETURN_STACKADJ_RTX;
25263 emit_insn (gen_add3_insn (sp_reg_rtx, sp_reg_rtx, sa));
25269 bool lr = (strategy & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR) == 0;
25270 if (! restoring_FPRs_inline)
25272 p = rtvec_alloc (4 + 64 - info->first_fp_reg_save);
25273 RTVEC_ELT (p, 0) = ret_rtx;
25279 /* We can't hang the cfa_restores off a simple return,
25280 since the shrink-wrap code sometimes uses an existing
25281 return. This means there might be a path from
25282 pre-prologue code to this return, and dwarf2cfi code
25283 wants the eh_frame unwinder state to be the same on
25284 all paths to any point. So we need to emit the
25285 cfa_restores before the return. For -m64 we really
25286 don't need epilogue cfa_restores at all, except for
25287 this irritating dwarf2cfi with shrink-wrap
25288 requirement; The stack red-zone means eh_frame info
25289 from the prologue telling the unwinder to restore
25290 from the stack is perfectly good right to the end of
25292 emit_insn (gen_blockage ());
25293 emit_cfa_restores (cfa_restores);
25294 cfa_restores = NULL_RTX;
25296 p = rtvec_alloc (2);
25297 RTVEC_ELT (p, 0) = simple_return_rtx;
25300 RTVEC_ELT (p, 1) = ((restoring_FPRs_inline || !lr)
25301 ? gen_rtx_USE (VOIDmode,
25302 gen_rtx_REG (Pmode, LR_REGNO))
25303 : gen_rtx_CLOBBER (VOIDmode,
25304 gen_rtx_REG (Pmode, LR_REGNO)));
25306 /* If we have to restore more than two FP registers, branch to the
25307 restore function. It will return to our caller. */
25308 if (! restoring_FPRs_inline)
25314 if (flag_shrink_wrap)
25315 cfa_restores = add_crlr_cfa_restore (info, cfa_restores);
25317 sym = rs6000_savres_routine_sym (info,
25318 SAVRES_FPR | (lr ? SAVRES_LR : 0));
25319 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym);
25320 reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11;
25321 RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg));
25323 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
25325 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
25327 RTVEC_ELT (p, i + 4)
25328 = gen_frame_load (reg, sp_reg_rtx, info->fp_save_offset + 8 * i);
25329 if (flag_shrink_wrap)
25330 cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
25335 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
25341 /* Ensure the cfa_restores are hung off an insn that won't
25342 be reordered above other restores. */
25343 emit_insn (gen_blockage ());
25345 emit_cfa_restores (cfa_restores);
25349 /* Write function epilogue. */
25352 rs6000_output_function_epilogue (FILE *file,
25353 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
25356 macho_branch_islands ();
25357 /* Mach-O doesn't support labels at the end of objects, so if
25358 it looks like we might want one, insert a NOP. */
25360 rtx_insn *insn = get_last_insn ();
25361 rtx_insn *deleted_debug_label = NULL;
25364 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
25366 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
25367 notes only, instead set their CODE_LABEL_NUMBER to -1,
25368 otherwise there would be code generation differences
25369 in between -g and -g0. */
25370 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
25371 deleted_debug_label = insn;
25372 insn = PREV_INSN (insn);
25377 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
25378 fputs ("\tnop\n", file);
25379 else if (deleted_debug_label)
25380 for (insn = deleted_debug_label; insn; insn = NEXT_INSN (insn))
25381 if (NOTE_KIND (insn) == NOTE_INSN_DELETED_DEBUG_LABEL)
25382 CODE_LABEL_NUMBER (insn) = -1;
25386 /* Output a traceback table here. See /usr/include/sys/debug.h for info
25389 We don't output a traceback table if -finhibit-size-directive was
25390 used. The documentation for -finhibit-size-directive reads
25391 ``don't output a @code{.size} assembler directive, or anything
25392 else that would cause trouble if the function is split in the
25393 middle, and the two halves are placed at locations far apart in
25394 memory.'' The traceback table has this property, since it
25395 includes the offset from the start of the function to the
25396 traceback table itself.
25398 System V.4 Powerpc's (and the embedded ABI derived from it) use a
25399 different traceback table. */
25400 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
25401 && ! flag_inhibit_size_directive
25402 && rs6000_traceback != traceback_none && !cfun->is_thunk)
25404 const char *fname = NULL;
25405 const char *language_string = lang_hooks.name;
25406 int fixed_parms = 0, float_parms = 0, parm_info = 0;
25408 int optional_tbtab;
25409 rs6000_stack_t *info = rs6000_stack_info ();
25411 if (rs6000_traceback == traceback_full)
25412 optional_tbtab = 1;
25413 else if (rs6000_traceback == traceback_part)
25414 optional_tbtab = 0;
25416 optional_tbtab = !optimize_size && !TARGET_ELF;
25418 if (optional_tbtab)
25420 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
25421 while (*fname == '.') /* V.4 encodes . in the name */
25424 /* Need label immediately before tbtab, so we can compute
25425 its offset from the function start. */
25426 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
25427 ASM_OUTPUT_LABEL (file, fname);
25430 /* The .tbtab pseudo-op can only be used for the first eight
25431 expressions, since it can't handle the possibly variable
25432 length fields that follow. However, if you omit the optional
25433 fields, the assembler outputs zeros for all optional fields
25434 anyways, giving each variable length field is minimum length
25435 (as defined in sys/debug.h). Thus we can not use the .tbtab
25436 pseudo-op at all. */
25438 /* An all-zero word flags the start of the tbtab, for debuggers
25439 that have to find it by searching forward from the entry
25440 point or from the current pc. */
25441 fputs ("\t.long 0\n", file);
25443 /* Tbtab format type. Use format type 0. */
25444 fputs ("\t.byte 0,", file);
25446 /* Language type. Unfortunately, there does not seem to be any
25447 official way to discover the language being compiled, so we
25448 use language_string.
25449 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
25450 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
25451 a number, so for now use 9. LTO and Go aren't assigned numbers
25452 either, so for now use 0. */
25454 || ! strcmp (language_string, "GNU GIMPLE")
25455 || ! strcmp (language_string, "GNU Go"))
25457 else if (! strcmp (language_string, "GNU F77")
25458 || ! strcmp (language_string, "GNU Fortran"))
25460 else if (! strcmp (language_string, "GNU Pascal"))
25462 else if (! strcmp (language_string, "GNU Ada"))
25464 else if (lang_GNU_CXX ()
25465 || ! strcmp (language_string, "GNU Objective-C++"))
25467 else if (! strcmp (language_string, "GNU Java"))
25469 else if (! strcmp (language_string, "GNU Objective-C"))
25472 gcc_unreachable ();
25473 fprintf (file, "%d,", i);
25475 /* 8 single bit fields: global linkage (not set for C extern linkage,
25476 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
25477 from start of procedure stored in tbtab, internal function, function
25478 has controlled storage, function has no toc, function uses fp,
25479 function logs/aborts fp operations. */
25480 /* Assume that fp operations are used if any fp reg must be saved. */
25481 fprintf (file, "%d,",
25482 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
25484 /* 6 bitfields: function is interrupt handler, name present in
25485 proc table, function calls alloca, on condition directives
25486 (controls stack walks, 3 bits), saves condition reg, saves
25488 /* The `function calls alloca' bit seems to be set whenever reg 31 is
25489 set up as a frame pointer, even when there is no alloca call. */
25490 fprintf (file, "%d,",
25491 ((optional_tbtab << 6)
25492 | ((optional_tbtab & frame_pointer_needed) << 5)
25493 | (info->cr_save_p << 1)
25494 | (info->lr_save_p)));
25496 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
25498 fprintf (file, "%d,",
25499 (info->push_p << 7) | (64 - info->first_fp_reg_save));
25501 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
25502 fprintf (file, "%d,", (32 - first_reg_to_save ()));
25504 if (optional_tbtab)
25506 /* Compute the parameter info from the function decl argument
25509 int next_parm_info_bit = 31;
25511 for (decl = DECL_ARGUMENTS (current_function_decl);
25512 decl; decl = DECL_CHAIN (decl))
25514 rtx parameter = DECL_INCOMING_RTL (decl);
25515 machine_mode mode = GET_MODE (parameter);
25517 if (GET_CODE (parameter) == REG)
25519 if (SCALAR_FLOAT_MODE_P (mode))
25540 gcc_unreachable ();
25543 /* If only one bit will fit, don't or in this entry. */
25544 if (next_parm_info_bit > 0)
25545 parm_info |= (bits << (next_parm_info_bit - 1));
25546 next_parm_info_bit -= 2;
25550 fixed_parms += ((GET_MODE_SIZE (mode)
25551 + (UNITS_PER_WORD - 1))
25553 next_parm_info_bit -= 1;
25559 /* Number of fixed point parameters. */
25560 /* This is actually the number of words of fixed point parameters; thus
25561 an 8 byte struct counts as 2; and thus the maximum value is 8. */
25562 fprintf (file, "%d,", fixed_parms);
25564 /* 2 bitfields: number of floating point parameters (7 bits), parameters
25566 /* This is actually the number of fp registers that hold parameters;
25567 and thus the maximum value is 13. */
25568 /* Set parameters on stack bit if parameters are not in their original
25569 registers, regardless of whether they are on the stack? Xlc
25570 seems to set the bit when not optimizing. */
25571 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
25573 if (! optional_tbtab)
25576 /* Optional fields follow. Some are variable length. */
25578 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
25579 11 double float. */
25580 /* There is an entry for each parameter in a register, in the order that
25581 they occur in the parameter list. Any intervening arguments on the
25582 stack are ignored. If the list overflows a long (max possible length
25583 34 bits) then completely leave off all elements that don't fit. */
25584 /* Only emit this long if there was at least one parameter. */
25585 if (fixed_parms || float_parms)
25586 fprintf (file, "\t.long %d\n", parm_info);
25588 /* Offset from start of code to tb table. */
25589 fputs ("\t.long ", file);
25590 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
25591 RS6000_OUTPUT_BASENAME (file, fname);
25593 rs6000_output_function_entry (file, fname);
25596 /* Interrupt handler mask. */
25597 /* Omit this long, since we never set the interrupt handler bit
25600 /* Number of CTL (controlled storage) anchors. */
25601 /* Omit this long, since the has_ctl bit is never set above. */
25603 /* Displacement into stack of each CTL anchor. */
25604 /* Omit this list of longs, because there are no CTL anchors. */
25606 /* Length of function name. */
25609 fprintf (file, "\t.short %d\n", (int) strlen (fname));
25611 /* Function name. */
25612 assemble_string (fname, strlen (fname));
25614 /* Register for alloca automatic storage; this is always reg 31.
25615 Only emit this if the alloca bit was set above. */
25616 if (frame_pointer_needed)
25617 fputs ("\t.byte 31\n", file);
25619 fputs ("\t.align 2\n", file);
25623 /* A C compound statement that outputs the assembler code for a thunk
25624 function, used to implement C++ virtual function calls with
25625 multiple inheritance. The thunk acts as a wrapper around a virtual
25626 function, adjusting the implicit object parameter before handing
25627 control off to the real function.
25629 First, emit code to add the integer DELTA to the location that
25630 contains the incoming first argument. Assume that this argument
25631 contains a pointer, and is the one used to pass the `this' pointer
25632 in C++. This is the incoming argument *before* the function
25633 prologue, e.g. `%o0' on a sparc. The addition must preserve the
25634 values of all other incoming arguments.
25636 After the addition, emit code to jump to FUNCTION, which is a
25637 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
25638 not touch the return address. Hence returning from FUNCTION will
25639 return to whoever called the current `thunk'.
25641 The effect must be as if FUNCTION had been called directly with the
25642 adjusted first argument. This macro is responsible for emitting
25643 all of the code for a thunk function; output_function_prologue()
25644 and output_function_epilogue() are not invoked.
25646 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
25647 been extracted from it.) It might possibly be useful on some
25648 targets, but probably not.
25650 If you do not define this macro, the target-independent code in the
25651 C++ frontend will generate a less efficient heavyweight thunk that
25652 calls FUNCTION instead of jumping to it. The generic approach does
25653 not support varargs. */
25656 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
25657 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
25660 rtx this_rtx, funexp;
25663 reload_completed = 1;
25664 epilogue_completed = 1;
25666 /* Mark the end of the (empty) prologue. */
25667 emit_note (NOTE_INSN_PROLOGUE_END);
25669 /* Find the "this" pointer. If the function returns a structure,
25670 the structure return pointer is in r3. */
25671 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
25672 this_rtx = gen_rtx_REG (Pmode, 4);
25674 this_rtx = gen_rtx_REG (Pmode, 3);
25676 /* Apply the constant offset, if required. */
25678 emit_insn (gen_add3_insn (this_rtx, this_rtx, GEN_INT (delta)));
25680 /* Apply the offset from the vtable, if required. */
25683 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
25684 rtx tmp = gen_rtx_REG (Pmode, 12);
25686 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this_rtx));
25687 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
25689 emit_insn (gen_add3_insn (tmp, tmp, vcall_offset_rtx));
25690 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
25694 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
25696 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
25698 emit_insn (gen_add3_insn (this_rtx, this_rtx, tmp));
25701 /* Generate a tail call to the target function. */
25702 if (!TREE_USED (function))
25704 assemble_external (function);
25705 TREE_USED (function) = 1;
25707 funexp = XEXP (DECL_RTL (function), 0);
25708 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
25711 if (MACHOPIC_INDIRECT)
25712 funexp = machopic_indirect_call_target (funexp);
25715 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
25716 generate sibcall RTL explicitly. */
25717 insn = emit_call_insn (
25718 gen_rtx_PARALLEL (VOIDmode,
25720 gen_rtx_CALL (VOIDmode,
25721 funexp, const0_rtx),
25722 gen_rtx_USE (VOIDmode, const0_rtx),
25723 gen_rtx_USE (VOIDmode,
25724 gen_rtx_REG (SImode,
25726 simple_return_rtx)));
25727 SIBLING_CALL_P (insn) = 1;
25730 /* Ensure we have a global entry point for the thunk. ??? We could
25731 avoid that if the target routine doesn't need a global entry point,
25732 but we do not know whether this is the case at this point. */
25733 if (DEFAULT_ABI == ABI_ELFv2)
25734 cfun->machine->r2_setup_needed = true;
25736 /* Run just enough of rest_of_compilation to get the insns emitted.
25737 There's not really enough bulk here to make other passes such as
25738 instruction scheduling worth while. Note that use_thunk calls
25739 assemble_start_function and assemble_end_function. */
25740 insn = get_insns ();
25741 shorten_branches (insn);
25742 final_start_function (insn, file, 1);
25743 final (insn, file, 1);
25744 final_end_function ();
25746 reload_completed = 0;
25747 epilogue_completed = 0;
25750 /* A quick summary of the various types of 'constant-pool tables'
25753 Target Flags Name One table per
25754 AIX (none) AIX TOC object file
25755 AIX -mfull-toc AIX TOC object file
25756 AIX -mminimal-toc AIX minimal TOC translation unit
25757 SVR4/EABI (none) SVR4 SDATA object file
25758 SVR4/EABI -fpic SVR4 pic object file
25759 SVR4/EABI -fPIC SVR4 PIC translation unit
25760 SVR4/EABI -mrelocatable EABI TOC function
25761 SVR4/EABI -maix AIX TOC object file
25762 SVR4/EABI -maix -mminimal-toc
25763 AIX minimal TOC translation unit
25765 Name Reg. Set by entries contains:
25766 made by addrs? fp? sum?
25768 AIX TOC 2 crt0 as Y option option
25769 AIX minimal TOC 30 prolog gcc Y Y option
25770 SVR4 SDATA 13 crt0 gcc N Y N
25771 SVR4 pic 30 prolog ld Y not yet N
25772 SVR4 PIC 30 prolog gcc Y option option
25773 EABI TOC 30 prolog gcc Y option option
25777 /* Hash functions for the hash table. */
25780 rs6000_hash_constant (rtx k)
25782 enum rtx_code code = GET_CODE (k);
25783 machine_mode mode = GET_MODE (k);
25784 unsigned result = (code << 3) ^ mode;
25785 const char *format;
25788 format = GET_RTX_FORMAT (code);
25789 flen = strlen (format);
25795 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
25797 case CONST_WIDE_INT:
25800 flen = CONST_WIDE_INT_NUNITS (k);
25801 for (i = 0; i < flen; i++)
25802 result = result * 613 + CONST_WIDE_INT_ELT (k, i);
25807 if (mode != VOIDmode)
25808 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
25820 for (; fidx < flen; fidx++)
25821 switch (format[fidx])
25826 const char *str = XSTR (k, fidx);
25827 len = strlen (str);
25828 result = result * 613 + len;
25829 for (i = 0; i < len; i++)
25830 result = result * 613 + (unsigned) str[i];
25835 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
25839 result = result * 613 + (unsigned) XINT (k, fidx);
25842 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
25843 result = result * 613 + (unsigned) XWINT (k, fidx);
25847 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
25848 result = result * 613 + (unsigned) (XWINT (k, fidx)
25855 gcc_unreachable ();
25862 toc_hasher::hash (toc_hash_struct *thc)
25864 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
25867 /* Compare H1 and H2 for equivalence. */
25870 toc_hasher::equal (toc_hash_struct *h1, toc_hash_struct *h2)
25875 if (h1->key_mode != h2->key_mode)
25878 return rtx_equal_p (r1, r2);
25881 /* These are the names given by the C++ front-end to vtables, and
25882 vtable-like objects. Ideally, this logic should not be here;
25883 instead, there should be some programmatic way of inquiring as
25884 to whether or not an object is a vtable. */
25886 #define VTABLE_NAME_P(NAME) \
25887 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
25888 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
25889 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
25890 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
25891 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
25893 #ifdef NO_DOLLAR_IN_LABEL
25894 /* Return a GGC-allocated character string translating dollar signs in
25895 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
25898 rs6000_xcoff_strip_dollar (const char *name)
25904 q = (const char *) strchr (name, '$');
25906 if (q == 0 || q == name)
25909 len = strlen (name);
25910 strip = XALLOCAVEC (char, len + 1);
25911 strcpy (strip, name);
25912 p = strip + (q - name);
25916 p = strchr (p + 1, '$');
25919 return ggc_alloc_string (strip, len);
25924 rs6000_output_symbol_ref (FILE *file, rtx x)
25926 /* Currently C++ toc references to vtables can be emitted before it
25927 is decided whether the vtable is public or private. If this is
25928 the case, then the linker will eventually complain that there is
25929 a reference to an unknown section. Thus, for vtables only,
25930 we emit the TOC reference to reference the symbol and not the
25932 const char *name = XSTR (x, 0);
25934 if (VTABLE_NAME_P (name))
25936 RS6000_OUTPUT_BASENAME (file, name);
25939 assemble_name (file, name);
25942 /* Output a TOC entry. We derive the entry name from what is being
25946 output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
25949 const char *name = buf;
25951 HOST_WIDE_INT offset = 0;
25953 gcc_assert (!TARGET_NO_TOC);
25955 /* When the linker won't eliminate them, don't output duplicate
25956 TOC entries (this happens on AIX if there is any kind of TOC,
25957 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
25959 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
25961 struct toc_hash_struct *h;
25963 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
25964 time because GGC is not initialized at that point. */
25965 if (toc_hash_table == NULL)
25966 toc_hash_table = hash_table<toc_hasher>::create_ggc (1021);
25968 h = ggc_alloc<toc_hash_struct> ();
25970 h->key_mode = mode;
25971 h->labelno = labelno;
25973 toc_hash_struct **found = toc_hash_table->find_slot (h, INSERT);
25974 if (*found == NULL)
25976 else /* This is indeed a duplicate.
25977 Set this label equal to that label. */
25979 fputs ("\t.set ", file);
25980 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
25981 fprintf (file, "%d,", labelno);
25982 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
25983 fprintf (file, "%d\n", ((*found)->labelno));
25986 if (TARGET_XCOFF && GET_CODE (x) == SYMBOL_REF
25987 && (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_GLOBAL_DYNAMIC
25988 || SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC))
25990 fputs ("\t.set ", file);
25991 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
25992 fprintf (file, "%d,", labelno);
25993 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LCM");
25994 fprintf (file, "%d\n", ((*found)->labelno));
26001 /* If we're going to put a double constant in the TOC, make sure it's
26002 aligned properly when strict alignment is on. */
26003 if ((CONST_DOUBLE_P (x) || CONST_WIDE_INT_P (x))
26004 && STRICT_ALIGNMENT
26005 && GET_MODE_BITSIZE (mode) >= 64
26006 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
26007 ASM_OUTPUT_ALIGN (file, 3);
26010 (*targetm.asm_out.internal_label) (file, "LC", labelno);
26012 /* Handle FP constants specially. Note that if we have a minimal
26013 TOC, things we put here aren't actually in the TOC, so we can allow
26015 if (GET_CODE (x) == CONST_DOUBLE &&
26016 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
26018 REAL_VALUE_TYPE rv;
26021 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
26022 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
26023 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
26025 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
26029 if (TARGET_ELF || TARGET_MINIMAL_TOC)
26030 fputs (DOUBLE_INT_ASM_OP, file);
26032 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
26033 k[0] & 0xffffffff, k[1] & 0xffffffff,
26034 k[2] & 0xffffffff, k[3] & 0xffffffff);
26035 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
26036 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
26037 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff,
26038 k[WORDS_BIG_ENDIAN ? 2 : 3] & 0xffffffff,
26039 k[WORDS_BIG_ENDIAN ? 3 : 2] & 0xffffffff);
26044 if (TARGET_ELF || TARGET_MINIMAL_TOC)
26045 fputs ("\t.long ", file);
26047 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
26048 k[0] & 0xffffffff, k[1] & 0xffffffff,
26049 k[2] & 0xffffffff, k[3] & 0xffffffff);
26050 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
26051 k[0] & 0xffffffff, k[1] & 0xffffffff,
26052 k[2] & 0xffffffff, k[3] & 0xffffffff);
26056 else if (GET_CODE (x) == CONST_DOUBLE &&
26057 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
26059 REAL_VALUE_TYPE rv;
26062 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
26064 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
26065 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
26067 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
26071 if (TARGET_ELF || TARGET_MINIMAL_TOC)
26072 fputs (DOUBLE_INT_ASM_OP, file);
26074 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
26075 k[0] & 0xffffffff, k[1] & 0xffffffff);
26076 fprintf (file, "0x%lx%08lx\n",
26077 k[WORDS_BIG_ENDIAN ? 0 : 1] & 0xffffffff,
26078 k[WORDS_BIG_ENDIAN ? 1 : 0] & 0xffffffff);
26083 if (TARGET_ELF || TARGET_MINIMAL_TOC)
26084 fputs ("\t.long ", file);
26086 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
26087 k[0] & 0xffffffff, k[1] & 0xffffffff);
26088 fprintf (file, "0x%lx,0x%lx\n",
26089 k[0] & 0xffffffff, k[1] & 0xffffffff);
26093 else if (GET_CODE (x) == CONST_DOUBLE &&
26094 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
26096 REAL_VALUE_TYPE rv;
26099 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
26100 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
26101 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
26103 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
26107 if (TARGET_ELF || TARGET_MINIMAL_TOC)
26108 fputs (DOUBLE_INT_ASM_OP, file);
26110 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
26111 if (WORDS_BIG_ENDIAN)
26112 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
26114 fprintf (file, "0x%lx\n", l & 0xffffffff);
26119 if (TARGET_ELF || TARGET_MINIMAL_TOC)
26120 fputs ("\t.long ", file);
26122 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
26123 fprintf (file, "0x%lx\n", l & 0xffffffff);
26127 else if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT)
26129 unsigned HOST_WIDE_INT low;
26130 HOST_WIDE_INT high;
26132 low = INTVAL (x) & 0xffffffff;
26133 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
26135 /* TOC entries are always Pmode-sized, so when big-endian
26136 smaller integer constants in the TOC need to be padded.
26137 (This is still a win over putting the constants in
26138 a separate constant pool, because then we'd have
26139 to have both a TOC entry _and_ the actual constant.)
26141 For a 32-bit target, CONST_INT values are loaded and shifted
26142 entirely within `low' and can be stored in one TOC entry. */
26144 /* It would be easy to make this work, but it doesn't now. */
26145 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
26147 if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode))
26150 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
26151 high = (HOST_WIDE_INT) low >> 32;
26157 if (TARGET_ELF || TARGET_MINIMAL_TOC)
26158 fputs (DOUBLE_INT_ASM_OP, file);
26160 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
26161 (long) high & 0xffffffff, (long) low & 0xffffffff);
26162 fprintf (file, "0x%lx%08lx\n",
26163 (long) high & 0xffffffff, (long) low & 0xffffffff);
26168 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
26170 if (TARGET_ELF || TARGET_MINIMAL_TOC)
26171 fputs ("\t.long ", file);
26173 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
26174 (long) high & 0xffffffff, (long) low & 0xffffffff);
26175 fprintf (file, "0x%lx,0x%lx\n",
26176 (long) high & 0xffffffff, (long) low & 0xffffffff);
26180 if (TARGET_ELF || TARGET_MINIMAL_TOC)
26181 fputs ("\t.long ", file);
26183 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
26184 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
26190 if (GET_CODE (x) == CONST)
26192 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS
26193 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
26195 base = XEXP (XEXP (x, 0), 0);
26196 offset = INTVAL (XEXP (XEXP (x, 0), 1));
26199 switch (GET_CODE (base))
26202 name = XSTR (base, 0);
26206 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
26207 CODE_LABEL_NUMBER (XEXP (base, 0)));
26211 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
26215 gcc_unreachable ();
26218 if (TARGET_ELF || TARGET_MINIMAL_TOC)
26219 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
26222 fputs ("\t.tc ", file);
26223 RS6000_OUTPUT_BASENAME (file, name);
26226 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
26228 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
26230 /* Mark large TOC symbols on AIX with [TE] so they are mapped
26231 after other TOC symbols, reducing overflow of small TOC access
26232 to [TC] symbols. */
26233 fputs (TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL
26234 ? "[TE]," : "[TC],", file);
26237 /* Currently C++ toc references to vtables can be emitted before it
26238 is decided whether the vtable is public or private. If this is
26239 the case, then the linker will eventually complain that there is
26240 a TOC reference to an unknown section. Thus, for vtables only,
26241 we emit the TOC reference to reference the symbol and not the
26243 if (VTABLE_NAME_P (name))
26245 RS6000_OUTPUT_BASENAME (file, name);
26247 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
26248 else if (offset > 0)
26249 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
26252 output_addr_const (file, x);
26255 if (TARGET_XCOFF && GET_CODE (base) == SYMBOL_REF
26256 && SYMBOL_REF_TLS_MODEL (base) != 0)
26258 if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_LOCAL_EXEC)
26259 fputs ("@le", file);
26260 else if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_INITIAL_EXEC)
26261 fputs ("@ie", file);
26262 /* Use global-dynamic for local-dynamic. */
26263 else if (SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_GLOBAL_DYNAMIC
26264 || SYMBOL_REF_TLS_MODEL (base) == TLS_MODEL_LOCAL_DYNAMIC)
26267 (*targetm.asm_out.internal_label) (file, "LCM", labelno);
26268 fputs ("\t.tc .", file);
26269 RS6000_OUTPUT_BASENAME (file, name);
26270 fputs ("[TC],", file);
26271 output_addr_const (file, x);
26272 fputs ("@m", file);
26280 /* Output an assembler pseudo-op to write an ASCII string of N characters
26281 starting at P to FILE.
26283 On the RS/6000, we have to do this using the .byte operation and
26284 write out special characters outside the quoted string.
26285 Also, the assembler is broken; very long strings are truncated,
26286 so we must artificially break them up early. */
26289 output_ascii (FILE *file, const char *p, int n)
26292 int i, count_string;
26293 const char *for_string = "\t.byte \"";
26294 const char *for_decimal = "\t.byte ";
26295 const char *to_close = NULL;
26298 for (i = 0; i < n; i++)
26301 if (c >= ' ' && c < 0177)
26304 fputs (for_string, file);
26307 /* Write two quotes to get one. */
26315 for_decimal = "\"\n\t.byte ";
26319 if (count_string >= 512)
26321 fputs (to_close, file);
26323 for_string = "\t.byte \"";
26324 for_decimal = "\t.byte ";
26332 fputs (for_decimal, file);
26333 fprintf (file, "%d", c);
26335 for_string = "\n\t.byte \"";
26336 for_decimal = ", ";
26342 /* Now close the string if we have written one. Then end the line. */
26344 fputs (to_close, file);
26347 /* Generate a unique section name for FILENAME for a section type
26348 represented by SECTION_DESC. Output goes into BUF.
26350 SECTION_DESC can be any string, as long as it is different for each
26351 possible section type.
26353 We name the section in the same manner as xlc. The name begins with an
26354 underscore followed by the filename (after stripping any leading directory
26355 names) with the last period replaced by the string SECTION_DESC. If
26356 FILENAME does not contain a period, SECTION_DESC is appended to the end of
26360 rs6000_gen_section_name (char **buf, const char *filename,
26361 const char *section_desc)
26363 const char *q, *after_last_slash, *last_period = 0;
26367 after_last_slash = filename;
26368 for (q = filename; *q; q++)
26371 after_last_slash = q + 1;
26372 else if (*q == '.')
26376 len = strlen (after_last_slash) + strlen (section_desc) + 2;
26377 *buf = (char *) xmalloc (len);
26382 for (q = after_last_slash; *q; q++)
26384 if (q == last_period)
26386 strcpy (p, section_desc);
26387 p += strlen (section_desc);
26391 else if (ISALNUM (*q))
26395 if (last_period == 0)
26396 strcpy (p, section_desc);
26401 /* Emit profile function. */
26404 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
26406 /* Non-standard profiling for kernels, which just saves LR then calls
26407 _mcount without worrying about arg saves. The idea is to change
26408 the function prologue as little as possible as it isn't easy to
26409 account for arg save/restore code added just for _mcount. */
26410 if (TARGET_PROFILE_KERNEL)
26413 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
26415 #ifndef NO_PROFILE_COUNTERS
26416 # define NO_PROFILE_COUNTERS 0
26418 if (NO_PROFILE_COUNTERS)
26419 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
26420 LCT_NORMAL, VOIDmode, 0);
26424 const char *label_name;
26427 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
26428 label_name = ggc_strdup ((*targetm.strip_name_encoding) (buf));
26429 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
26431 emit_library_call (init_one_libfunc (RS6000_MCOUNT),
26432 LCT_NORMAL, VOIDmode, 1, fun, Pmode);
26435 else if (DEFAULT_ABI == ABI_DARWIN)
26437 const char *mcount_name = RS6000_MCOUNT;
26438 int caller_addr_regno = LR_REGNO;
26440 /* Be conservative and always set this, at least for now. */
26441 crtl->uses_pic_offset_table = 1;
26444 /* For PIC code, set up a stub and collect the caller's address
26445 from r0, which is where the prologue puts it. */
26446 if (MACHOPIC_INDIRECT
26447 && crtl->uses_pic_offset_table)
26448 caller_addr_regno = 0;
26450 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
26451 LCT_NORMAL, VOIDmode, 1,
26452 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
26456 /* Write function profiler code. */
26459 output_function_profiler (FILE *file, int labelno)
26463 switch (DEFAULT_ABI)
26466 gcc_unreachable ();
26471 warning (0, "no profiling of 64-bit code for this ABI");
26474 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
26475 fprintf (file, "\tmflr %s\n", reg_names[0]);
26476 if (NO_PROFILE_COUNTERS)
26478 asm_fprintf (file, "\tstw %s,4(%s)\n",
26479 reg_names[0], reg_names[1]);
26481 else if (TARGET_SECURE_PLT && flag_pic)
26483 if (TARGET_LINK_STACK)
26486 get_ppc476_thunk_name (name);
26487 asm_fprintf (file, "\tbl %s\n", name);
26490 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n");
26491 asm_fprintf (file, "\tstw %s,4(%s)\n",
26492 reg_names[0], reg_names[1]);
26493 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
26494 asm_fprintf (file, "\taddis %s,%s,",
26495 reg_names[12], reg_names[12]);
26496 assemble_name (file, buf);
26497 asm_fprintf (file, "-1b@ha\n\tla %s,", reg_names[0]);
26498 assemble_name (file, buf);
26499 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
26501 else if (flag_pic == 1)
26503 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
26504 asm_fprintf (file, "\tstw %s,4(%s)\n",
26505 reg_names[0], reg_names[1]);
26506 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
26507 asm_fprintf (file, "\tlwz %s,", reg_names[0]);
26508 assemble_name (file, buf);
26509 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
26511 else if (flag_pic > 1)
26513 asm_fprintf (file, "\tstw %s,4(%s)\n",
26514 reg_names[0], reg_names[1]);
26515 /* Now, we need to get the address of the label. */
26516 if (TARGET_LINK_STACK)
26519 get_ppc476_thunk_name (name);
26520 asm_fprintf (file, "\tbl %s\n\tb 1f\n\t.long ", name);
26521 assemble_name (file, buf);
26522 fputs ("-.\n1:", file);
26523 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
26524 asm_fprintf (file, "\taddi %s,%s,4\n",
26525 reg_names[11], reg_names[11]);
26529 fputs ("\tbcl 20,31,1f\n\t.long ", file);
26530 assemble_name (file, buf);
26531 fputs ("-.\n1:", file);
26532 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
26534 asm_fprintf (file, "\tlwz %s,0(%s)\n",
26535 reg_names[0], reg_names[11]);
26536 asm_fprintf (file, "\tadd %s,%s,%s\n",
26537 reg_names[0], reg_names[0], reg_names[11]);
26541 asm_fprintf (file, "\tlis %s,", reg_names[12]);
26542 assemble_name (file, buf);
26543 fputs ("@ha\n", file);
26544 asm_fprintf (file, "\tstw %s,4(%s)\n",
26545 reg_names[0], reg_names[1]);
26546 asm_fprintf (file, "\tla %s,", reg_names[0]);
26547 assemble_name (file, buf);
26548 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
26551 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
26552 fprintf (file, "\tbl %s%s\n",
26553 RS6000_MCOUNT, flag_pic ? "@plt" : "");
26559 /* Don't do anything, done in output_profile_hook (). */
26566 /* The following variable value is the last issued insn. */
26568 static rtx last_scheduled_insn;
26570 /* The following variable helps to balance issuing of load and
26571 store instructions */
26573 static int load_store_pendulum;
26575 /* Power4 load update and store update instructions are cracked into a
26576 load or store and an integer insn which are executed in the same cycle.
26577 Branches have their own dispatch slot which does not count against the
26578 GCC issue rate, but it changes the program flow so there are no other
26579 instructions to issue in this cycle. */
26582 rs6000_variable_issue_1 (rtx_insn *insn, int more)
26584 last_scheduled_insn = insn;
26585 if (GET_CODE (PATTERN (insn)) == USE
26586 || GET_CODE (PATTERN (insn)) == CLOBBER)
26588 cached_can_issue_more = more;
26589 return cached_can_issue_more;
26592 if (insn_terminates_group_p (insn, current_group))
26594 cached_can_issue_more = 0;
26595 return cached_can_issue_more;
26598 /* If no reservation, but reach here */
26599 if (recog_memoized (insn) < 0)
26602 if (rs6000_sched_groups)
26604 if (is_microcoded_insn (insn))
26605 cached_can_issue_more = 0;
26606 else if (is_cracked_insn (insn))
26607 cached_can_issue_more = more > 2 ? more - 2 : 0;
26609 cached_can_issue_more = more - 1;
26611 return cached_can_issue_more;
26614 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
26617 cached_can_issue_more = more - 1;
26618 return cached_can_issue_more;
26622 rs6000_variable_issue (FILE *stream, int verbose, rtx_insn *insn, int more)
26624 int r = rs6000_variable_issue_1 (insn, more);
26626 fprintf (stream, "// rs6000_variable_issue (more = %d) = %d\n", more, r);
26630 /* Adjust the cost of a scheduling dependency. Return the new cost of
26631 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
26634 rs6000_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost)
26636 enum attr_type attr_type;
26638 if (! recog_memoized (insn))
26641 switch (REG_NOTE_KIND (link))
26645 /* Data dependency; DEP_INSN writes a register that INSN reads
26646 some cycles later. */
26648 /* Separate a load from a narrower, dependent store. */
26649 if (rs6000_sched_groups
26650 && GET_CODE (PATTERN (insn)) == SET
26651 && GET_CODE (PATTERN (dep_insn)) == SET
26652 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
26653 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
26654 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
26655 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
26658 attr_type = get_attr_type (insn);
26663 /* Tell the first scheduling pass about the latency between
26664 a mtctr and bctr (and mtlr and br/blr). The first
26665 scheduling pass will not know about this latency since
26666 the mtctr instruction, which has the latency associated
26667 to it, will be generated by reload. */
26670 /* Leave some extra cycles between a compare and its
26671 dependent branch, to inhibit expensive mispredicts. */
26672 if ((rs6000_cpu_attr == CPU_PPC603
26673 || rs6000_cpu_attr == CPU_PPC604
26674 || rs6000_cpu_attr == CPU_PPC604E
26675 || rs6000_cpu_attr == CPU_PPC620
26676 || rs6000_cpu_attr == CPU_PPC630
26677 || rs6000_cpu_attr == CPU_PPC750
26678 || rs6000_cpu_attr == CPU_PPC7400
26679 || rs6000_cpu_attr == CPU_PPC7450
26680 || rs6000_cpu_attr == CPU_PPCE5500
26681 || rs6000_cpu_attr == CPU_PPCE6500
26682 || rs6000_cpu_attr == CPU_POWER4
26683 || rs6000_cpu_attr == CPU_POWER5
26684 || rs6000_cpu_attr == CPU_POWER7
26685 || rs6000_cpu_attr == CPU_POWER8
26686 || rs6000_cpu_attr == CPU_CELL)
26687 && recog_memoized (dep_insn)
26688 && (INSN_CODE (dep_insn) >= 0))
26690 switch (get_attr_type (dep_insn))
26693 case TYPE_FPCOMPARE:
26694 case TYPE_CR_LOGICAL:
26695 case TYPE_DELAYED_CR:
26699 if (get_attr_dot (dep_insn) == DOT_YES)
26704 if (get_attr_dot (dep_insn) == DOT_YES
26705 && get_attr_var_shift (dep_insn) == VAR_SHIFT_NO)
26716 if ((rs6000_cpu == PROCESSOR_POWER6)
26717 && recog_memoized (dep_insn)
26718 && (INSN_CODE (dep_insn) >= 0))
26721 if (GET_CODE (PATTERN (insn)) != SET)
26722 /* If this happens, we have to extend this to schedule
26723 optimally. Return default for now. */
26726 /* Adjust the cost for the case where the value written
26727 by a fixed point operation is used as the address
26728 gen value on a store. */
26729 switch (get_attr_type (dep_insn))
26734 if (! store_data_bypass_p (dep_insn, insn))
26735 return get_attr_sign_extend (dep_insn)
26736 == SIGN_EXTEND_YES ? 6 : 4;
26741 if (! store_data_bypass_p (dep_insn, insn))
26742 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
26752 if (! store_data_bypass_p (dep_insn, insn))
26760 if (get_attr_update (dep_insn) == UPDATE_YES
26761 && ! store_data_bypass_p (dep_insn, insn))
26767 if (! store_data_bypass_p (dep_insn, insn))
26773 if (! store_data_bypass_p (dep_insn, insn))
26774 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
26784 if ((rs6000_cpu == PROCESSOR_POWER6)
26785 && recog_memoized (dep_insn)
26786 && (INSN_CODE (dep_insn) >= 0))
26789 /* Adjust the cost for the case where the value written
26790 by a fixed point instruction is used within the address
26791 gen portion of a subsequent load(u)(x) */
26792 switch (get_attr_type (dep_insn))
26797 if (set_to_load_agen (dep_insn, insn))
26798 return get_attr_sign_extend (dep_insn)
26799 == SIGN_EXTEND_YES ? 6 : 4;
26804 if (set_to_load_agen (dep_insn, insn))
26805 return get_attr_var_shift (dep_insn) == VAR_SHIFT_YES ?
26815 if (set_to_load_agen (dep_insn, insn))
26823 if (get_attr_update (dep_insn) == UPDATE_YES
26824 && set_to_load_agen (dep_insn, insn))
26830 if (set_to_load_agen (dep_insn, insn))
26836 if (set_to_load_agen (dep_insn, insn))
26837 return get_attr_size (dep_insn) == SIZE_32 ? 45 : 57;
26847 if ((rs6000_cpu == PROCESSOR_POWER6)
26848 && get_attr_update (insn) == UPDATE_NO
26849 && recog_memoized (dep_insn)
26850 && (INSN_CODE (dep_insn) >= 0)
26851 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
26858 /* Fall out to return default cost. */
26862 case REG_DEP_OUTPUT:
26863 /* Output dependency; DEP_INSN writes a register that INSN writes some
26865 if ((rs6000_cpu == PROCESSOR_POWER6)
26866 && recog_memoized (dep_insn)
26867 && (INSN_CODE (dep_insn) >= 0))
26869 attr_type = get_attr_type (insn);
26874 if (get_attr_type (dep_insn) == TYPE_FP)
26878 if (get_attr_update (insn) == UPDATE_NO
26879 && get_attr_type (dep_insn) == TYPE_MFFGPR)
26887 /* Anti dependency; DEP_INSN reads a register that INSN writes some
26892 gcc_unreachable ();
26898 /* Debug version of rs6000_adjust_cost. */
26901 rs6000_debug_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn,
26904 int ret = rs6000_adjust_cost (insn, link, dep_insn, cost);
26910 switch (REG_NOTE_KIND (link))
26912 default: dep = "unknown depencency"; break;
26913 case REG_DEP_TRUE: dep = "data dependency"; break;
26914 case REG_DEP_OUTPUT: dep = "output dependency"; break;
26915 case REG_DEP_ANTI: dep = "anti depencency"; break;
26919 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
26920 "%s, insn:\n", ret, cost, dep);
26928 /* The function returns a true if INSN is microcoded.
26929 Return false otherwise. */
26932 is_microcoded_insn (rtx_insn *insn)
26934 if (!insn || !NONDEBUG_INSN_P (insn)
26935 || GET_CODE (PATTERN (insn)) == USE
26936 || GET_CODE (PATTERN (insn)) == CLOBBER)
26939 if (rs6000_cpu_attr == CPU_CELL)
26940 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
26942 if (rs6000_sched_groups
26943 && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))
26945 enum attr_type type = get_attr_type (insn);
26946 if ((type == TYPE_LOAD
26947 && get_attr_update (insn) == UPDATE_YES
26948 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES)
26949 || ((type == TYPE_LOAD || type == TYPE_STORE)
26950 && get_attr_update (insn) == UPDATE_YES
26951 && get_attr_indexed (insn) == INDEXED_YES)
26952 || type == TYPE_MFCR)
26959 /* The function returns true if INSN is cracked into 2 instructions
26960 by the processor (and therefore occupies 2 issue slots). */
26963 is_cracked_insn (rtx_insn *insn)
26965 if (!insn || !NONDEBUG_INSN_P (insn)
26966 || GET_CODE (PATTERN (insn)) == USE
26967 || GET_CODE (PATTERN (insn)) == CLOBBER)
26970 if (rs6000_sched_groups
26971 && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5))
26973 enum attr_type type = get_attr_type (insn);
26974 if ((type == TYPE_LOAD
26975 && get_attr_sign_extend (insn) == SIGN_EXTEND_YES
26976 && get_attr_update (insn) == UPDATE_NO)
26977 || (type == TYPE_LOAD
26978 && get_attr_sign_extend (insn) == SIGN_EXTEND_NO
26979 && get_attr_update (insn) == UPDATE_YES
26980 && get_attr_indexed (insn) == INDEXED_NO)
26981 || (type == TYPE_STORE
26982 && get_attr_update (insn) == UPDATE_YES
26983 && get_attr_indexed (insn) == INDEXED_NO)
26984 || ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
26985 && get_attr_update (insn) == UPDATE_YES)
26986 || type == TYPE_DELAYED_CR
26987 || (type == TYPE_EXTS
26988 && get_attr_dot (insn) == DOT_YES)
26989 || (type == TYPE_SHIFT
26990 && get_attr_dot (insn) == DOT_YES
26991 && get_attr_var_shift (insn) == VAR_SHIFT_NO)
26992 || (type == TYPE_MUL
26993 && get_attr_dot (insn) == DOT_YES)
26994 || type == TYPE_DIV
26995 || (type == TYPE_INSERT
26996 && get_attr_size (insn) == SIZE_32))
27003 /* The function returns true if INSN can be issued only from
27004 the branch slot. */
27007 is_branch_slot_insn (rtx_insn *insn)
27009 if (!insn || !NONDEBUG_INSN_P (insn)
27010 || GET_CODE (PATTERN (insn)) == USE
27011 || GET_CODE (PATTERN (insn)) == CLOBBER)
27014 if (rs6000_sched_groups)
27016 enum attr_type type = get_attr_type (insn);
27017 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
27025 /* The function returns true if out_inst sets a value that is
27026 used in the address generation computation of in_insn */
27028 set_to_load_agen (rtx_insn *out_insn, rtx_insn *in_insn)
27030 rtx out_set, in_set;
27032 /* For performance reasons, only handle the simple case where
27033 both loads are a single_set. */
27034 out_set = single_set (out_insn);
27037 in_set = single_set (in_insn);
27039 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
27045 /* Try to determine base/offset/size parts of the given MEM.
27046 Return true if successful, false if all the values couldn't
27049 This function only looks for REG or REG+CONST address forms.
27050 REG+REG address form will return false. */
27053 get_memref_parts (rtx mem, rtx *base, HOST_WIDE_INT *offset,
27054 HOST_WIDE_INT *size)
27057 if MEM_SIZE_KNOWN_P (mem)
27058 *size = MEM_SIZE (mem);
27062 if (GET_CODE (XEXP (mem, 0)) == PRE_MODIFY)
27063 addr_rtx = XEXP (XEXP (mem, 0), 1);
27065 addr_rtx = (XEXP (mem, 0));
27067 if (GET_CODE (addr_rtx) == REG)
27072 else if (GET_CODE (addr_rtx) == PLUS
27073 && CONST_INT_P (XEXP (addr_rtx, 1)))
27075 *base = XEXP (addr_rtx, 0);
27076 *offset = INTVAL (XEXP (addr_rtx, 1));
27084 /* The function returns true if the target storage location of
27085 mem1 is adjacent to the target storage location of mem2 */
27086 /* Return 1 if memory locations are adjacent. */
27089 adjacent_mem_locations (rtx mem1, rtx mem2)
27092 HOST_WIDE_INT off1, size1, off2, size2;
27094 if (get_memref_parts (mem1, ®1, &off1, &size1)
27095 && get_memref_parts (mem2, ®2, &off2, &size2))
27096 return ((REGNO (reg1) == REGNO (reg2))
27097 && ((off1 + size1 == off2)
27098 || (off2 + size2 == off1)));
27103 /* This function returns true if it can be determined that the two MEM
27104 locations overlap by at least 1 byte based on base reg/offset/size. */
27107 mem_locations_overlap (rtx mem1, rtx mem2)
27110 HOST_WIDE_INT off1, size1, off2, size2;
27112 if (get_memref_parts (mem1, ®1, &off1, &size1)
27113 && get_memref_parts (mem2, ®2, &off2, &size2))
27114 return ((REGNO (reg1) == REGNO (reg2))
27115 && (((off1 <= off2) && (off1 + size1 > off2))
27116 || ((off2 <= off1) && (off2 + size2 > off1))));
27121 /* A C statement (sans semicolon) to update the integer scheduling
27122 priority INSN_PRIORITY (INSN). Increase the priority to execute the
27123 INSN earlier, reduce the priority to execute INSN later. Do not
27124 define this macro if you do not need to adjust the scheduling
27125 priorities of insns. */
27128 rs6000_adjust_priority (rtx_insn *insn ATTRIBUTE_UNUSED, int priority)
27130 rtx load_mem, str_mem;
27131 /* On machines (like the 750) which have asymmetric integer units,
27132 where one integer unit can do multiply and divides and the other
27133 can't, reduce the priority of multiply/divide so it is scheduled
27134 before other integer operations. */
27137 if (! INSN_P (insn))
27140 if (GET_CODE (PATTERN (insn)) == USE)
27143 switch (rs6000_cpu_attr) {
27145 switch (get_attr_type (insn))
27152 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
27153 priority, priority);
27154 if (priority >= 0 && priority < 0x01000000)
27161 if (insn_must_be_first_in_group (insn)
27162 && reload_completed
27163 && current_sched_info->sched_max_insns_priority
27164 && rs6000_sched_restricted_insns_priority)
27167 /* Prioritize insns that can be dispatched only in the first
27169 if (rs6000_sched_restricted_insns_priority == 1)
27170 /* Attach highest priority to insn. This means that in
27171 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
27172 precede 'priority' (critical path) considerations. */
27173 return current_sched_info->sched_max_insns_priority;
27174 else if (rs6000_sched_restricted_insns_priority == 2)
27175 /* Increase priority of insn by a minimal amount. This means that in
27176 haifa-sched.c:ready_sort(), only 'priority' (critical path)
27177 considerations precede dispatch-slot restriction considerations. */
27178 return (priority + 1);
27181 if (rs6000_cpu == PROCESSOR_POWER6
27182 && ((load_store_pendulum == -2 && is_load_insn (insn, &load_mem))
27183 || (load_store_pendulum == 2 && is_store_insn (insn, &str_mem))))
27184 /* Attach highest priority to insn if the scheduler has just issued two
27185 stores and this instruction is a load, or two loads and this instruction
27186 is a store. Power6 wants loads and stores scheduled alternately
27188 return current_sched_info->sched_max_insns_priority;
27193 /* Return true if the instruction is nonpipelined on the Cell. */
27195 is_nonpipeline_insn (rtx_insn *insn)
27197 enum attr_type type;
27198 if (!insn || !NONDEBUG_INSN_P (insn)
27199 || GET_CODE (PATTERN (insn)) == USE
27200 || GET_CODE (PATTERN (insn)) == CLOBBER)
27203 type = get_attr_type (insn);
27204 if (type == TYPE_MUL
27205 || type == TYPE_DIV
27206 || type == TYPE_SDIV
27207 || type == TYPE_DDIV
27208 || type == TYPE_SSQRT
27209 || type == TYPE_DSQRT
27210 || type == TYPE_MFCR
27211 || type == TYPE_MFCRF
27212 || type == TYPE_MFJMPR)
27220 /* Return how many instructions the machine can issue per cycle. */
27223 rs6000_issue_rate (void)
27225 /* Unless scheduling for register pressure, use issue rate of 1 for
27226 first scheduling pass to decrease degradation. */
27227 if (!reload_completed && !flag_sched_pressure)
27230 switch (rs6000_cpu_attr) {
27232 case CPU_PPC601: /* ? */
27242 case CPU_PPCE300C2:
27243 case CPU_PPCE300C3:
27244 case CPU_PPCE500MC:
27245 case CPU_PPCE500MC64:
27268 /* Return how many instructions to look ahead for better insn
27272 rs6000_use_sched_lookahead (void)
27274 switch (rs6000_cpu_attr)
27281 return (reload_completed ? 8 : 0);
27288 /* We are choosing insn from the ready queue. Return zero if INSN can be
27291 rs6000_use_sched_lookahead_guard (rtx_insn *insn, int ready_index)
27293 if (ready_index == 0)
27296 if (rs6000_cpu_attr != CPU_CELL)
27299 gcc_assert (insn != NULL_RTX && INSN_P (insn));
27301 if (!reload_completed
27302 || is_nonpipeline_insn (insn)
27303 || is_microcoded_insn (insn))
27309 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
27310 and return true. */
27313 find_mem_ref (rtx pat, rtx *mem_ref)
27318 /* stack_tie does not produce any real memory traffic. */
27319 if (tie_operand (pat, VOIDmode))
27322 if (GET_CODE (pat) == MEM)
27328 /* Recursively process the pattern. */
27329 fmt = GET_RTX_FORMAT (GET_CODE (pat));
27331 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0; i--)
27335 if (find_mem_ref (XEXP (pat, i), mem_ref))
27338 else if (fmt[i] == 'E')
27339 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
27341 if (find_mem_ref (XVECEXP (pat, i, j), mem_ref))
27349 /* Determine if PAT is a PATTERN of a load insn. */
27352 is_load_insn1 (rtx pat, rtx *load_mem)
27354 if (!pat || pat == NULL_RTX)
27357 if (GET_CODE (pat) == SET)
27358 return find_mem_ref (SET_SRC (pat), load_mem);
27360 if (GET_CODE (pat) == PARALLEL)
27364 for (i = 0; i < XVECLEN (pat, 0); i++)
27365 if (is_load_insn1 (XVECEXP (pat, 0, i), load_mem))
27372 /* Determine if INSN loads from memory. */
27375 is_load_insn (rtx insn, rtx *load_mem)
27377 if (!insn || !INSN_P (insn))
27383 return is_load_insn1 (PATTERN (insn), load_mem);
27386 /* Determine if PAT is a PATTERN of a store insn. */
27389 is_store_insn1 (rtx pat, rtx *str_mem)
27391 if (!pat || pat == NULL_RTX)
27394 if (GET_CODE (pat) == SET)
27395 return find_mem_ref (SET_DEST (pat), str_mem);
27397 if (GET_CODE (pat) == PARALLEL)
27401 for (i = 0; i < XVECLEN (pat, 0); i++)
27402 if (is_store_insn1 (XVECEXP (pat, 0, i), str_mem))
27409 /* Determine if INSN stores to memory. */
27412 is_store_insn (rtx insn, rtx *str_mem)
27414 if (!insn || !INSN_P (insn))
27417 return is_store_insn1 (PATTERN (insn), str_mem);
27420 /* Returns whether the dependence between INSN and NEXT is considered
27421 costly by the given target. */
27424 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
27428 rtx load_mem, str_mem;
27430 /* If the flag is not enabled - no dependence is considered costly;
27431 allow all dependent insns in the same group.
27432 This is the most aggressive option. */
27433 if (rs6000_sched_costly_dep == no_dep_costly)
27436 /* If the flag is set to 1 - a dependence is always considered costly;
27437 do not allow dependent instructions in the same group.
27438 This is the most conservative option. */
27439 if (rs6000_sched_costly_dep == all_deps_costly)
27442 insn = DEP_PRO (dep);
27443 next = DEP_CON (dep);
27445 if (rs6000_sched_costly_dep == store_to_load_dep_costly
27446 && is_load_insn (next, &load_mem)
27447 && is_store_insn (insn, &str_mem))
27448 /* Prevent load after store in the same group. */
27451 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
27452 && is_load_insn (next, &load_mem)
27453 && is_store_insn (insn, &str_mem)
27454 && DEP_TYPE (dep) == REG_DEP_TRUE
27455 && mem_locations_overlap(str_mem, load_mem))
27456 /* Prevent load after store in the same group if it is a true
27460 /* The flag is set to X; dependences with latency >= X are considered costly,
27461 and will not be scheduled in the same group. */
27462 if (rs6000_sched_costly_dep <= max_dep_latency
27463 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
27469 /* Return the next insn after INSN that is found before TAIL is reached,
27470 skipping any "non-active" insns - insns that will not actually occupy
27471 an issue slot. Return NULL_RTX if such an insn is not found. */
27474 get_next_active_insn (rtx_insn *insn, rtx_insn *tail)
27476 if (insn == NULL_RTX || insn == tail)
27481 insn = NEXT_INSN (insn);
27482 if (insn == NULL_RTX || insn == tail)
27486 || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
27487 || (NONJUMP_INSN_P (insn)
27488 && GET_CODE (PATTERN (insn)) != USE
27489 && GET_CODE (PATTERN (insn)) != CLOBBER
27490 && INSN_CODE (insn) != CODE_FOR_stack_tie))
27496 /* We are about to begin issuing insns for this clock cycle. */
27499 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
27500 rtx_insn **ready ATTRIBUTE_UNUSED,
27501 int *pn_ready ATTRIBUTE_UNUSED,
27502 int clock_var ATTRIBUTE_UNUSED)
27504 int n_ready = *pn_ready;
27507 fprintf (dump, "// rs6000_sched_reorder :\n");
27509 /* Reorder the ready list, if the second to last ready insn
27510 is a nonepipeline insn. */
27511 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
27513 if (is_nonpipeline_insn (ready[n_ready - 1])
27514 && (recog_memoized (ready[n_ready - 2]) > 0))
27515 /* Simply swap first two insns. */
27516 std::swap (ready[n_ready - 1], ready[n_ready - 2]);
27519 if (rs6000_cpu == PROCESSOR_POWER6)
27520 load_store_pendulum = 0;
27522 return rs6000_issue_rate ();
27525 /* Like rs6000_sched_reorder, but called after issuing each insn. */
27528 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx_insn **ready,
27529 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
27532 fprintf (dump, "// rs6000_sched_reorder2 :\n");
27534 /* For Power6, we need to handle some special cases to try and keep the
27535 store queue from overflowing and triggering expensive flushes.
27537 This code monitors how load and store instructions are being issued
27538 and skews the ready list one way or the other to increase the likelihood
27539 that a desired instruction is issued at the proper time.
27541 A couple of things are done. First, we maintain a "load_store_pendulum"
27542 to track the current state of load/store issue.
27544 - If the pendulum is at zero, then no loads or stores have been
27545 issued in the current cycle so we do nothing.
27547 - If the pendulum is 1, then a single load has been issued in this
27548 cycle and we attempt to locate another load in the ready list to
27551 - If the pendulum is -2, then two stores have already been
27552 issued in this cycle, so we increase the priority of the first load
27553 in the ready list to increase it's likelihood of being chosen first
27556 - If the pendulum is -1, then a single store has been issued in this
27557 cycle and we attempt to locate another store in the ready list to
27558 issue with it, preferring a store to an adjacent memory location to
27559 facilitate store pairing in the store queue.
27561 - If the pendulum is 2, then two loads have already been
27562 issued in this cycle, so we increase the priority of the first store
27563 in the ready list to increase it's likelihood of being chosen first
27566 - If the pendulum < -2 or > 2, then do nothing.
27568 Note: This code covers the most common scenarios. There exist non
27569 load/store instructions which make use of the LSU and which
27570 would need to be accounted for to strictly model the behavior
27571 of the machine. Those instructions are currently unaccounted
27572 for to help minimize compile time overhead of this code.
27574 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
27579 rtx load_mem, str_mem;
27581 if (is_store_insn (last_scheduled_insn, &str_mem))
27582 /* Issuing a store, swing the load_store_pendulum to the left */
27583 load_store_pendulum--;
27584 else if (is_load_insn (last_scheduled_insn, &load_mem))
27585 /* Issuing a load, swing the load_store_pendulum to the right */
27586 load_store_pendulum++;
27588 return cached_can_issue_more;
27590 /* If the pendulum is balanced, or there is only one instruction on
27591 the ready list, then all is well, so return. */
27592 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
27593 return cached_can_issue_more;
27595 if (load_store_pendulum == 1)
27597 /* A load has been issued in this cycle. Scan the ready list
27598 for another load to issue with it */
27603 if (is_load_insn (ready[pos], &load_mem))
27605 /* Found a load. Move it to the head of the ready list,
27606 and adjust it's priority so that it is more likely to
27609 for (i=pos; i<*pn_ready-1; i++)
27610 ready[i] = ready[i + 1];
27611 ready[*pn_ready-1] = tmp;
27613 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
27614 INSN_PRIORITY (tmp)++;
27620 else if (load_store_pendulum == -2)
27622 /* Two stores have been issued in this cycle. Increase the
27623 priority of the first load in the ready list to favor it for
27624 issuing in the next cycle. */
27629 if (is_load_insn (ready[pos], &load_mem)
27631 && INSN_PRIORITY_KNOWN (ready[pos]))
27633 INSN_PRIORITY (ready[pos])++;
27635 /* Adjust the pendulum to account for the fact that a load
27636 was found and increased in priority. This is to prevent
27637 increasing the priority of multiple loads */
27638 load_store_pendulum--;
27645 else if (load_store_pendulum == -1)
27647 /* A store has been issued in this cycle. Scan the ready list for
27648 another store to issue with it, preferring a store to an adjacent
27650 int first_store_pos = -1;
27656 if (is_store_insn (ready[pos], &str_mem))
27659 /* Maintain the index of the first store found on the
27661 if (first_store_pos == -1)
27662 first_store_pos = pos;
27664 if (is_store_insn (last_scheduled_insn, &str_mem2)
27665 && adjacent_mem_locations (str_mem, str_mem2))
27667 /* Found an adjacent store. Move it to the head of the
27668 ready list, and adjust it's priority so that it is
27669 more likely to stay there */
27671 for (i=pos; i<*pn_ready-1; i++)
27672 ready[i] = ready[i + 1];
27673 ready[*pn_ready-1] = tmp;
27675 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
27676 INSN_PRIORITY (tmp)++;
27678 first_store_pos = -1;
27686 if (first_store_pos >= 0)
27688 /* An adjacent store wasn't found, but a non-adjacent store was,
27689 so move the non-adjacent store to the front of the ready
27690 list, and adjust its priority so that it is more likely to
27692 tmp = ready[first_store_pos];
27693 for (i=first_store_pos; i<*pn_ready-1; i++)
27694 ready[i] = ready[i + 1];
27695 ready[*pn_ready-1] = tmp;
27696 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp))
27697 INSN_PRIORITY (tmp)++;
27700 else if (load_store_pendulum == 2)
27702 /* Two loads have been issued in this cycle. Increase the priority
27703 of the first store in the ready list to favor it for issuing in
27709 if (is_store_insn (ready[pos], &str_mem)
27711 && INSN_PRIORITY_KNOWN (ready[pos]))
27713 INSN_PRIORITY (ready[pos])++;
27715 /* Adjust the pendulum to account for the fact that a store
27716 was found and increased in priority. This is to prevent
27717 increasing the priority of multiple stores */
27718 load_store_pendulum++;
27727 return cached_can_issue_more;
27730 /* Return whether the presence of INSN causes a dispatch group termination
27731 of group WHICH_GROUP.
27733 If WHICH_GROUP == current_group, this function will return true if INSN
27734 causes the termination of the current group (i.e, the dispatch group to
27735 which INSN belongs). This means that INSN will be the last insn in the
27736 group it belongs to.
27738 If WHICH_GROUP == previous_group, this function will return true if INSN
27739 causes the termination of the previous group (i.e, the dispatch group that
27740 precedes the group to which INSN belongs). This means that INSN will be
27741 the first insn in the group it belongs to). */
27744 insn_terminates_group_p (rtx_insn *insn, enum group_termination which_group)
27751 first = insn_must_be_first_in_group (insn);
27752 last = insn_must_be_last_in_group (insn);
27757 if (which_group == current_group)
27759 else if (which_group == previous_group)
27767 insn_must_be_first_in_group (rtx_insn *insn)
27769 enum attr_type type;
27773 || DEBUG_INSN_P (insn)
27774 || GET_CODE (PATTERN (insn)) == USE
27775 || GET_CODE (PATTERN (insn)) == CLOBBER)
27778 switch (rs6000_cpu)
27780 case PROCESSOR_POWER5:
27781 if (is_cracked_insn (insn))
27783 case PROCESSOR_POWER4:
27784 if (is_microcoded_insn (insn))
27787 if (!rs6000_sched_groups)
27790 type = get_attr_type (insn);
27797 case TYPE_DELAYED_CR:
27798 case TYPE_CR_LOGICAL:
27811 case PROCESSOR_POWER6:
27812 type = get_attr_type (insn);
27821 case TYPE_FPCOMPARE:
27832 if (get_attr_dot (insn) == DOT_NO
27833 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
27838 if (get_attr_size (insn) == SIZE_32)
27846 if (get_attr_update (insn) == UPDATE_YES)
27854 case PROCESSOR_POWER7:
27855 type = get_attr_type (insn);
27859 case TYPE_CR_LOGICAL:
27873 if (get_attr_dot (insn) == DOT_YES)
27878 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
27879 || get_attr_update (insn) == UPDATE_YES)
27886 if (get_attr_update (insn) == UPDATE_YES)
27894 case PROCESSOR_POWER8:
27895 type = get_attr_type (insn);
27899 case TYPE_CR_LOGICAL:
27900 case TYPE_DELAYED_CR:
27908 case TYPE_VECSTORE:
27915 if (get_attr_dot (insn) == DOT_YES)
27920 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
27921 || get_attr_update (insn) == UPDATE_YES)
27926 if (get_attr_update (insn) == UPDATE_YES
27927 && get_attr_indexed (insn) == INDEXED_YES)
27943 insn_must_be_last_in_group (rtx_insn *insn)
27945 enum attr_type type;
27949 || DEBUG_INSN_P (insn)
27950 || GET_CODE (PATTERN (insn)) == USE
27951 || GET_CODE (PATTERN (insn)) == CLOBBER)
27954 switch (rs6000_cpu) {
27955 case PROCESSOR_POWER4:
27956 case PROCESSOR_POWER5:
27957 if (is_microcoded_insn (insn))
27960 if (is_branch_slot_insn (insn))
27964 case PROCESSOR_POWER6:
27965 type = get_attr_type (insn);
27973 case TYPE_FPCOMPARE:
27984 if (get_attr_dot (insn) == DOT_NO
27985 || get_attr_var_shift (insn) == VAR_SHIFT_NO)
27990 if (get_attr_size (insn) == SIZE_32)
27998 case PROCESSOR_POWER7:
27999 type = get_attr_type (insn);
28009 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
28010 && get_attr_update (insn) == UPDATE_YES)
28015 if (get_attr_update (insn) == UPDATE_YES
28016 && get_attr_indexed (insn) == INDEXED_YES)
28024 case PROCESSOR_POWER8:
28025 type = get_attr_type (insn);
28037 if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
28038 && get_attr_update (insn) == UPDATE_YES)
28043 if (get_attr_update (insn) == UPDATE_YES
28044 && get_attr_indexed (insn) == INDEXED_YES)
28059 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
28060 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
28063 is_costly_group (rtx *group_insns, rtx next_insn)
28066 int issue_rate = rs6000_issue_rate ();
28068 for (i = 0; i < issue_rate; i++)
28070 sd_iterator_def sd_it;
28072 rtx insn = group_insns[i];
28077 FOR_EACH_DEP (insn, SD_LIST_RES_FORW, sd_it, dep)
28079 rtx next = DEP_CON (dep);
28081 if (next == next_insn
28082 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
28090 /* Utility of the function redefine_groups.
28091 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
28092 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
28093 to keep it "far" (in a separate group) from GROUP_INSNS, following
28094 one of the following schemes, depending on the value of the flag
28095 -minsert_sched_nops = X:
28096 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
28097 in order to force NEXT_INSN into a separate group.
28098 (2) X < sched_finish_regroup_exact: insert exactly X nops.
28099 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
28100 insertion (has a group just ended, how many vacant issue slots remain in the
28101 last group, and how many dispatch groups were encountered so far). */
28104 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
28105 rtx_insn *next_insn, bool *group_end, int can_issue_more,
28110 int issue_rate = rs6000_issue_rate ();
28111 bool end = *group_end;
28114 if (next_insn == NULL_RTX || DEBUG_INSN_P (next_insn))
28115 return can_issue_more;
28117 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
28118 return can_issue_more;
28120 force = is_costly_group (group_insns, next_insn);
28122 return can_issue_more;
28124 if (sched_verbose > 6)
28125 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
28126 *group_count ,can_issue_more);
28128 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
28131 can_issue_more = 0;
28133 /* Since only a branch can be issued in the last issue_slot, it is
28134 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
28135 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
28136 in this case the last nop will start a new group and the branch
28137 will be forced to the new group. */
28138 if (can_issue_more && !is_branch_slot_insn (next_insn))
28141 /* Do we have a special group ending nop? */
28142 if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7
28143 || rs6000_cpu_attr == CPU_POWER8)
28145 nop = gen_group_ending_nop ();
28146 emit_insn_before (nop, next_insn);
28147 can_issue_more = 0;
28150 while (can_issue_more > 0)
28153 emit_insn_before (nop, next_insn);
28161 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
28163 int n_nops = rs6000_sched_insert_nops;
28165 /* Nops can't be issued from the branch slot, so the effective
28166 issue_rate for nops is 'issue_rate - 1'. */
28167 if (can_issue_more == 0)
28168 can_issue_more = issue_rate;
28170 if (can_issue_more == 0)
28172 can_issue_more = issue_rate - 1;
28175 for (i = 0; i < issue_rate; i++)
28177 group_insns[i] = 0;
28184 emit_insn_before (nop, next_insn);
28185 if (can_issue_more == issue_rate - 1) /* new group begins */
28188 if (can_issue_more == 0)
28190 can_issue_more = issue_rate - 1;
28193 for (i = 0; i < issue_rate; i++)
28195 group_insns[i] = 0;
28201 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
28204 /* Is next_insn going to start a new group? */
28207 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
28208 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
28209 || (can_issue_more < issue_rate &&
28210 insn_terminates_group_p (next_insn, previous_group)));
28211 if (*group_end && end)
28214 if (sched_verbose > 6)
28215 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
28216 *group_count, can_issue_more);
28217 return can_issue_more;
28220 return can_issue_more;
28223 /* This function tries to synch the dispatch groups that the compiler "sees"
28224 with the dispatch groups that the processor dispatcher is expected to
28225 form in practice. It tries to achieve this synchronization by forcing the
28226 estimated processor grouping on the compiler (as opposed to the function
28227 'pad_goups' which tries to force the scheduler's grouping on the processor).
28229 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
28230 examines the (estimated) dispatch groups that will be formed by the processor
28231 dispatcher. It marks these group boundaries to reflect the estimated
28232 processor grouping, overriding the grouping that the scheduler had marked.
28233 Depending on the value of the flag '-minsert-sched-nops' this function can
28234 force certain insns into separate groups or force a certain distance between
28235 them by inserting nops, for example, if there exists a "costly dependence"
28238 The function estimates the group boundaries that the processor will form as
28239 follows: It keeps track of how many vacant issue slots are available after
28240 each insn. A subsequent insn will start a new group if one of the following
28242 - no more vacant issue slots remain in the current dispatch group.
28243 - only the last issue slot, which is the branch slot, is vacant, but the next
28244 insn is not a branch.
28245 - only the last 2 or less issue slots, including the branch slot, are vacant,
28246 which means that a cracked insn (which occupies two issue slots) can't be
28247 issued in this group.
28248 - less than 'issue_rate' slots are vacant, and the next insn always needs to
28249 start a new group. */
28252 redefine_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
28255 rtx_insn *insn, *next_insn;
28257 int can_issue_more;
28260 int group_count = 0;
28264 issue_rate = rs6000_issue_rate ();
28265 group_insns = XALLOCAVEC (rtx, issue_rate);
28266 for (i = 0; i < issue_rate; i++)
28268 group_insns[i] = 0;
28270 can_issue_more = issue_rate;
28272 insn = get_next_active_insn (prev_head_insn, tail);
28275 while (insn != NULL_RTX)
28277 slot = (issue_rate - can_issue_more);
28278 group_insns[slot] = insn;
28280 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
28281 if (insn_terminates_group_p (insn, current_group))
28282 can_issue_more = 0;
28284 next_insn = get_next_active_insn (insn, tail);
28285 if (next_insn == NULL_RTX)
28286 return group_count + 1;
28288 /* Is next_insn going to start a new group? */
28290 = (can_issue_more == 0
28291 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
28292 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
28293 || (can_issue_more < issue_rate &&
28294 insn_terminates_group_p (next_insn, previous_group)));
28296 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
28297 next_insn, &group_end, can_issue_more,
28303 can_issue_more = 0;
28304 for (i = 0; i < issue_rate; i++)
28306 group_insns[i] = 0;
28310 if (GET_MODE (next_insn) == TImode && can_issue_more)
28311 PUT_MODE (next_insn, VOIDmode);
28312 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
28313 PUT_MODE (next_insn, TImode);
28316 if (can_issue_more == 0)
28317 can_issue_more = issue_rate;
28320 return group_count;
28323 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
28324 dispatch group boundaries that the scheduler had marked. Pad with nops
28325 any dispatch groups which have vacant issue slots, in order to force the
28326 scheduler's grouping on the processor dispatcher. The function
28327 returns the number of dispatch groups found. */
28330 pad_groups (FILE *dump, int sched_verbose, rtx_insn *prev_head_insn,
28333 rtx_insn *insn, *next_insn;
28336 int can_issue_more;
28338 int group_count = 0;
28340 /* Initialize issue_rate. */
28341 issue_rate = rs6000_issue_rate ();
28342 can_issue_more = issue_rate;
28344 insn = get_next_active_insn (prev_head_insn, tail);
28345 next_insn = get_next_active_insn (insn, tail);
28347 while (insn != NULL_RTX)
28350 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
28352 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
28354 if (next_insn == NULL_RTX)
28359 /* If the scheduler had marked group termination at this location
28360 (between insn and next_insn), and neither insn nor next_insn will
28361 force group termination, pad the group with nops to force group
28364 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
28365 && !insn_terminates_group_p (insn, current_group)
28366 && !insn_terminates_group_p (next_insn, previous_group))
28368 if (!is_branch_slot_insn (next_insn))
28371 while (can_issue_more)
28374 emit_insn_before (nop, next_insn);
28379 can_issue_more = issue_rate;
28384 next_insn = get_next_active_insn (insn, tail);
28387 return group_count;
28390 /* We're beginning a new block. Initialize data structures as necessary. */
28393 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
28394 int sched_verbose ATTRIBUTE_UNUSED,
28395 int max_ready ATTRIBUTE_UNUSED)
28397 last_scheduled_insn = NULL_RTX;
28398 load_store_pendulum = 0;
28401 /* The following function is called at the end of scheduling BB.
28402 After reload, it inserts nops at insn group bundling. */
28405 rs6000_sched_finish (FILE *dump, int sched_verbose)
28410 fprintf (dump, "=== Finishing schedule.\n");
28412 if (reload_completed && rs6000_sched_groups)
28414 /* Do not run sched_finish hook when selective scheduling enabled. */
28415 if (sel_sched_p ())
28418 if (rs6000_sched_insert_nops == sched_finish_none)
28421 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
28422 n_groups = pad_groups (dump, sched_verbose,
28423 current_sched_info->prev_head,
28424 current_sched_info->next_tail);
28426 n_groups = redefine_groups (dump, sched_verbose,
28427 current_sched_info->prev_head,
28428 current_sched_info->next_tail);
28430 if (sched_verbose >= 6)
28432 fprintf (dump, "ngroups = %d\n", n_groups);
28433 print_rtl (dump, current_sched_info->prev_head);
28434 fprintf (dump, "Done finish_sched\n");
28439 struct _rs6000_sched_context
28441 short cached_can_issue_more;
28442 rtx last_scheduled_insn;
28443 int load_store_pendulum;
28446 typedef struct _rs6000_sched_context rs6000_sched_context_def;
28447 typedef rs6000_sched_context_def *rs6000_sched_context_t;
28449 /* Allocate store for new scheduling context. */
28451 rs6000_alloc_sched_context (void)
28453 return xmalloc (sizeof (rs6000_sched_context_def));
28456 /* If CLEAN_P is true then initializes _SC with clean data,
28457 and from the global context otherwise. */
28459 rs6000_init_sched_context (void *_sc, bool clean_p)
28461 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
28465 sc->cached_can_issue_more = 0;
28466 sc->last_scheduled_insn = NULL_RTX;
28467 sc->load_store_pendulum = 0;
28471 sc->cached_can_issue_more = cached_can_issue_more;
28472 sc->last_scheduled_insn = last_scheduled_insn;
28473 sc->load_store_pendulum = load_store_pendulum;
28477 /* Sets the global scheduling context to the one pointed to by _SC. */
28479 rs6000_set_sched_context (void *_sc)
28481 rs6000_sched_context_t sc = (rs6000_sched_context_t) _sc;
28483 gcc_assert (sc != NULL);
28485 cached_can_issue_more = sc->cached_can_issue_more;
28486 last_scheduled_insn = sc->last_scheduled_insn;
28487 load_store_pendulum = sc->load_store_pendulum;
28492 rs6000_free_sched_context (void *_sc)
28494 gcc_assert (_sc != NULL);
28500 /* Length in units of the trampoline for entering a nested function. */
28503 rs6000_trampoline_size (void)
28507 switch (DEFAULT_ABI)
28510 gcc_unreachable ();
28513 ret = (TARGET_32BIT) ? 12 : 24;
28517 gcc_assert (!TARGET_32BIT);
28523 ret = (TARGET_32BIT) ? 40 : 48;
28530 /* Emit RTL insns to initialize the variable parts of a trampoline.
28531 FNADDR is an RTX for the address of the function's pure code.
28532 CXT is an RTX for the static chain value for the function. */
28535 rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
28537 int regsize = (TARGET_32BIT) ? 4 : 8;
28538 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
28539 rtx ctx_reg = force_reg (Pmode, cxt);
28540 rtx addr = force_reg (Pmode, XEXP (m_tramp, 0));
28542 switch (DEFAULT_ABI)
28545 gcc_unreachable ();
28547 /* Under AIX, just build the 3 word function descriptor */
28550 rtx fnmem, fn_reg, toc_reg;
28552 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS)
28553 error ("You cannot take the address of a nested function if you use "
28554 "the -mno-pointers-to-nested-functions option.");
28556 fnmem = gen_const_mem (Pmode, force_reg (Pmode, fnaddr));
28557 fn_reg = gen_reg_rtx (Pmode);
28558 toc_reg = gen_reg_rtx (Pmode);
28560 /* Macro to shorten the code expansions below. */
28561 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
28563 m_tramp = replace_equiv_address (m_tramp, addr);
28565 emit_move_insn (fn_reg, MEM_PLUS (fnmem, 0));
28566 emit_move_insn (toc_reg, MEM_PLUS (fnmem, regsize));
28567 emit_move_insn (MEM_PLUS (m_tramp, 0), fn_reg);
28568 emit_move_insn (MEM_PLUS (m_tramp, regsize), toc_reg);
28569 emit_move_insn (MEM_PLUS (m_tramp, 2*regsize), ctx_reg);
28575 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
28579 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
28580 LCT_NORMAL, VOIDmode, 4,
28582 GEN_INT (rs6000_trampoline_size ()), SImode,
28590 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
28591 identifier as an argument, so the front end shouldn't look it up. */
28594 rs6000_attribute_takes_identifier_p (const_tree attr_id)
28596 return is_attribute_p ("altivec", attr_id);
28599 /* Handle the "altivec" attribute. The attribute may have
28600 arguments as follows:
28602 __attribute__((altivec(vector__)))
28603 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
28604 __attribute__((altivec(bool__))) (always followed by 'unsigned')
28606 and may appear more than once (e.g., 'vector bool char') in a
28607 given declaration. */
28610 rs6000_handle_altivec_attribute (tree *node,
28611 tree name ATTRIBUTE_UNUSED,
28613 int flags ATTRIBUTE_UNUSED,
28614 bool *no_add_attrs)
28616 tree type = *node, result = NULL_TREE;
28620 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
28621 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
28622 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
28625 while (POINTER_TYPE_P (type)
28626 || TREE_CODE (type) == FUNCTION_TYPE
28627 || TREE_CODE (type) == METHOD_TYPE
28628 || TREE_CODE (type) == ARRAY_TYPE)
28629 type = TREE_TYPE (type);
28631 mode = TYPE_MODE (type);
28633 /* Check for invalid AltiVec type qualifiers. */
28634 if (type == long_double_type_node)
28635 error ("use of %<long double%> in AltiVec types is invalid");
28636 else if (type == boolean_type_node)
28637 error ("use of boolean types in AltiVec types is invalid");
28638 else if (TREE_CODE (type) == COMPLEX_TYPE)
28639 error ("use of %<complex%> in AltiVec types is invalid");
28640 else if (DECIMAL_FLOAT_MODE_P (mode))
28641 error ("use of decimal floating point types in AltiVec types is invalid");
28642 else if (!TARGET_VSX)
28644 if (type == long_unsigned_type_node || type == long_integer_type_node)
28647 error ("use of %<long%> in AltiVec types is invalid for "
28648 "64-bit code without -mvsx");
28649 else if (rs6000_warn_altivec_long)
28650 warning (0, "use of %<long%> in AltiVec types is deprecated; "
28653 else if (type == long_long_unsigned_type_node
28654 || type == long_long_integer_type_node)
28655 error ("use of %<long long%> in AltiVec types is invalid without "
28657 else if (type == double_type_node)
28658 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
28661 switch (altivec_type)
28664 unsigned_p = TYPE_UNSIGNED (type);
28668 result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node);
28671 result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node);
28674 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
28677 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
28680 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
28682 case SFmode: result = V4SF_type_node; break;
28683 case DFmode: result = V2DF_type_node; break;
28684 /* If the user says 'vector int bool', we may be handed the 'bool'
28685 attribute _before_ the 'vector' attribute, and so select the
28686 proper type in the 'b' case below. */
28687 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
28688 case V2DImode: case V2DFmode:
28696 case DImode: case V2DImode: result = bool_V2DI_type_node; break;
28697 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
28698 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
28699 case QImode: case V16QImode: result = bool_V16QI_type_node;
28706 case V8HImode: result = pixel_V8HI_type_node;
28712 /* Propagate qualifiers attached to the element type
28713 onto the vector type. */
28714 if (result && result != type && TYPE_QUALS (type))
28715 result = build_qualified_type (result, TYPE_QUALS (type));
28717 *no_add_attrs = true; /* No need to hang on to the attribute. */
28720 *node = lang_hooks.types.reconstruct_complex_type (*node, result);
28725 /* AltiVec defines four built-in scalar types that serve as vector
28726 elements; we must teach the compiler how to mangle them. */
28728 static const char *
28729 rs6000_mangle_type (const_tree type)
28731 type = TYPE_MAIN_VARIANT (type);
28733 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
28734 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
28737 if (type == bool_char_type_node) return "U6__boolc";
28738 if (type == bool_short_type_node) return "U6__bools";
28739 if (type == pixel_type_node) return "u7__pixel";
28740 if (type == bool_int_type_node) return "U6__booli";
28741 if (type == bool_long_type_node) return "U6__booll";
28743 /* Mangle IBM extended float long double as `g' (__float128) on
28744 powerpc*-linux where long-double-64 previously was the default. */
28745 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
28747 && TARGET_LONG_DOUBLE_128
28748 && !TARGET_IEEEQUAD)
28751 /* For all other types, use normal C++ mangling. */
28755 /* Handle a "longcall" or "shortcall" attribute; arguments as in
28756 struct attribute_spec.handler. */
28759 rs6000_handle_longcall_attribute (tree *node, tree name,
28760 tree args ATTRIBUTE_UNUSED,
28761 int flags ATTRIBUTE_UNUSED,
28762 bool *no_add_attrs)
28764 if (TREE_CODE (*node) != FUNCTION_TYPE
28765 && TREE_CODE (*node) != FIELD_DECL
28766 && TREE_CODE (*node) != TYPE_DECL)
28768 warning (OPT_Wattributes, "%qE attribute only applies to functions",
28770 *no_add_attrs = true;
28776 /* Set longcall attributes on all functions declared when
28777 rs6000_default_long_calls is true. */
28779 rs6000_set_default_type_attributes (tree type)
28781 if (rs6000_default_long_calls
28782 && (TREE_CODE (type) == FUNCTION_TYPE
28783 || TREE_CODE (type) == METHOD_TYPE))
28784 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
28786 TYPE_ATTRIBUTES (type));
28789 darwin_set_default_type_attributes (type);
28793 /* Return a reference suitable for calling a function with the
28794 longcall attribute. */
28797 rs6000_longcall_ref (rtx call_ref)
28799 const char *call_name;
28802 if (GET_CODE (call_ref) != SYMBOL_REF)
28805 /* System V adds '.' to the internal name, so skip them. */
28806 call_name = XSTR (call_ref, 0);
28807 if (*call_name == '.')
28809 while (*call_name == '.')
28812 node = get_identifier (call_name);
28813 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
28816 return force_reg (Pmode, call_ref);
28819 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
28820 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
28823 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
28824 struct attribute_spec.handler. */
28826 rs6000_handle_struct_attribute (tree *node, tree name,
28827 tree args ATTRIBUTE_UNUSED,
28828 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
28831 if (DECL_P (*node))
28833 if (TREE_CODE (*node) == TYPE_DECL)
28834 type = &TREE_TYPE (*node);
28839 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
28840 || TREE_CODE (*type) == UNION_TYPE)))
28842 warning (OPT_Wattributes, "%qE attribute ignored", name);
28843 *no_add_attrs = true;
28846 else if ((is_attribute_p ("ms_struct", name)
28847 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
28848 || ((is_attribute_p ("gcc_struct", name)
28849 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
28851 warning (OPT_Wattributes, "%qE incompatible attribute ignored",
28853 *no_add_attrs = true;
28860 rs6000_ms_bitfield_layout_p (const_tree record_type)
28862 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
28863 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
28864 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
28867 #ifdef USING_ELFOS_H
28869 /* A get_unnamed_section callback, used for switching to toc_section. */
28872 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
28874 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
28875 && TARGET_MINIMAL_TOC
28876 && !TARGET_RELOCATABLE)
28878 if (!toc_initialized)
28880 toc_initialized = 1;
28881 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
28882 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
28883 fprintf (asm_out_file, "\t.tc ");
28884 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
28885 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
28886 fprintf (asm_out_file, "\n");
28888 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
28889 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
28890 fprintf (asm_out_file, " = .+32768\n");
28893 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
28895 else if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
28896 && !TARGET_RELOCATABLE)
28897 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
28900 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
28901 if (!toc_initialized)
28903 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
28904 fprintf (asm_out_file, " = .+32768\n");
28905 toc_initialized = 1;
28910 /* Implement TARGET_ASM_INIT_SECTIONS. */
28913 rs6000_elf_asm_init_sections (void)
28916 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
28919 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
28920 SDATA2_SECTION_ASM_OP);
28923 /* Implement TARGET_SELECT_RTX_SECTION. */
28926 rs6000_elf_select_rtx_section (machine_mode mode, rtx x,
28927 unsigned HOST_WIDE_INT align)
28929 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
28930 return toc_section;
28932 return default_elf_select_rtx_section (mode, x, align);
28935 /* For a SYMBOL_REF, set generic flags and then perform some
28936 target-specific processing.
28938 When the AIX ABI is requested on a non-AIX system, replace the
28939 function name with the real name (with a leading .) rather than the
28940 function descriptor name. This saves a lot of overriding code to
28941 read the prefixes. */
28943 static void rs6000_elf_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED;
28945 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
28947 default_encode_section_info (decl, rtl, first);
28950 && TREE_CODE (decl) == FUNCTION_DECL
28952 && DEFAULT_ABI == ABI_AIX)
28954 rtx sym_ref = XEXP (rtl, 0);
28955 size_t len = strlen (XSTR (sym_ref, 0));
28956 char *str = XALLOCAVEC (char, len + 2);
28958 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
28959 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
28964 compare_section_name (const char *section, const char *templ)
28968 len = strlen (templ);
28969 return (strncmp (section, templ, len) == 0
28970 && (section[len] == 0 || section[len] == '.'));
28974 rs6000_elf_in_small_data_p (const_tree decl)
28976 if (rs6000_sdata == SDATA_NONE)
28979 /* We want to merge strings, so we never consider them small data. */
28980 if (TREE_CODE (decl) == STRING_CST)
28983 /* Functions are never in the small data area. */
28984 if (TREE_CODE (decl) == FUNCTION_DECL)
28987 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
28989 const char *section = DECL_SECTION_NAME (decl);
28990 if (compare_section_name (section, ".sdata")
28991 || compare_section_name (section, ".sdata2")
28992 || compare_section_name (section, ".gnu.linkonce.s")
28993 || compare_section_name (section, ".sbss")
28994 || compare_section_name (section, ".sbss2")
28995 || compare_section_name (section, ".gnu.linkonce.sb")
28996 || strcmp (section, ".PPC.EMB.sdata0") == 0
28997 || strcmp (section, ".PPC.EMB.sbss0") == 0)
29002 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
29005 && size <= g_switch_value
29006 /* If it's not public, and we're not going to reference it there,
29007 there's no need to put it in the small data section. */
29008 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
29015 #endif /* USING_ELFOS_H */
29017 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
29020 rs6000_use_blocks_for_constant_p (machine_mode mode, const_rtx x)
29022 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
29025 /* Do not place thread-local symbols refs in the object blocks. */
29028 rs6000_use_blocks_for_decl_p (const_tree decl)
29030 return !DECL_THREAD_LOCAL_P (decl);
29033 /* Return a REG that occurs in ADDR with coefficient 1.
29034 ADDR can be effectively incremented by incrementing REG.
29036 r0 is special and we must not select it as an address
29037 register by this routine since our caller will try to
29038 increment the returned register via an "la" instruction. */
29041 find_addr_reg (rtx addr)
29043 while (GET_CODE (addr) == PLUS)
29045 if (GET_CODE (XEXP (addr, 0)) == REG
29046 && REGNO (XEXP (addr, 0)) != 0)
29047 addr = XEXP (addr, 0);
29048 else if (GET_CODE (XEXP (addr, 1)) == REG
29049 && REGNO (XEXP (addr, 1)) != 0)
29050 addr = XEXP (addr, 1);
29051 else if (CONSTANT_P (XEXP (addr, 0)))
29052 addr = XEXP (addr, 1);
29053 else if (CONSTANT_P (XEXP (addr, 1)))
29054 addr = XEXP (addr, 0);
29056 gcc_unreachable ();
29058 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
29063 rs6000_fatal_bad_address (rtx op)
29065 fatal_insn ("bad address", op);
29070 typedef struct branch_island_d {
29071 tree function_name;
29077 static vec<branch_island, va_gc> *branch_islands;
29079 /* Remember to generate a branch island for far calls to the given
29083 add_compiler_branch_island (tree label_name, tree function_name,
29086 branch_island bi = {function_name, label_name, line_number};
29087 vec_safe_push (branch_islands, bi);
29090 /* Generate far-jump branch islands for everything recorded in
29091 branch_islands. Invoked immediately after the last instruction of
29092 the epilogue has been emitted; the branch islands must be appended
29093 to, and contiguous with, the function body. Mach-O stubs are
29094 generated in machopic_output_stub(). */
29097 macho_branch_islands (void)
29101 while (!vec_safe_is_empty (branch_islands))
29103 branch_island *bi = &branch_islands->last ();
29104 const char *label = IDENTIFIER_POINTER (bi->label_name);
29105 const char *name = IDENTIFIER_POINTER (bi->function_name);
29106 char name_buf[512];
29107 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
29108 if (name[0] == '*' || name[0] == '&')
29109 strcpy (name_buf, name+1);
29113 strcpy (name_buf+1, name);
29115 strcpy (tmp_buf, "\n");
29116 strcat (tmp_buf, label);
29117 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
29118 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
29119 dbxout_stabd (N_SLINE, bi->line_number);
29120 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
29123 if (TARGET_LINK_STACK)
29126 get_ppc476_thunk_name (name);
29127 strcat (tmp_buf, ":\n\tmflr r0\n\tbl ");
29128 strcat (tmp_buf, name);
29129 strcat (tmp_buf, "\n");
29130 strcat (tmp_buf, label);
29131 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
29135 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
29136 strcat (tmp_buf, label);
29137 strcat (tmp_buf, "_pic\n");
29138 strcat (tmp_buf, label);
29139 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
29142 strcat (tmp_buf, "\taddis r11,r11,ha16(");
29143 strcat (tmp_buf, name_buf);
29144 strcat (tmp_buf, " - ");
29145 strcat (tmp_buf, label);
29146 strcat (tmp_buf, "_pic)\n");
29148 strcat (tmp_buf, "\tmtlr r0\n");
29150 strcat (tmp_buf, "\taddi r12,r11,lo16(");
29151 strcat (tmp_buf, name_buf);
29152 strcat (tmp_buf, " - ");
29153 strcat (tmp_buf, label);
29154 strcat (tmp_buf, "_pic)\n");
29156 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
29160 strcat (tmp_buf, ":\nlis r12,hi16(");
29161 strcat (tmp_buf, name_buf);
29162 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
29163 strcat (tmp_buf, name_buf);
29164 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
29166 output_asm_insn (tmp_buf, 0);
29167 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
29168 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
29169 dbxout_stabd (N_SLINE, bi->line_number);
29170 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
29171 branch_islands->pop ();
29175 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
29176 already there or not. */
29179 no_previous_def (tree function_name)
29184 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
29185 if (function_name == bi->function_name)
29190 /* GET_PREV_LABEL gets the label name from the previous definition of
29194 get_prev_label (tree function_name)
29199 FOR_EACH_VEC_SAFE_ELT (branch_islands, ix, bi)
29200 if (function_name == bi->function_name)
29201 return bi->label_name;
29205 /* INSN is either a function call or a millicode call. It may have an
29206 unconditional jump in its delay slot.
29208 CALL_DEST is the routine we are calling. */
29211 output_call (rtx_insn *insn, rtx *operands, int dest_operand_number,
29212 int cookie_operand_number)
29214 static char buf[256];
29215 if (darwin_emit_branch_islands
29216 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
29217 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
29220 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
29222 if (no_previous_def (funname))
29224 rtx label_rtx = gen_label_rtx ();
29225 char *label_buf, temp_buf[256];
29226 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
29227 CODE_LABEL_NUMBER (label_rtx));
29228 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
29229 labelname = get_identifier (label_buf);
29230 add_compiler_branch_island (labelname, funname, insn_line (insn));
29233 labelname = get_prev_label (funname);
29235 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
29236 instruction will reach 'foo', otherwise link as 'bl L42'".
29237 "L42" should be a 'branch island', that will do a far jump to
29238 'foo'. Branch islands are generated in
29239 macho_branch_islands(). */
29240 sprintf (buf, "jbsr %%z%d,%.246s",
29241 dest_operand_number, IDENTIFIER_POINTER (labelname));
29244 sprintf (buf, "bl %%z%d", dest_operand_number);
29248 /* Generate PIC and indirect symbol stubs. */
29251 machopic_output_stub (FILE *file, const char *symb, const char *stub)
29253 unsigned int length;
29254 char *symbol_name, *lazy_ptr_name;
29255 char *local_label_0;
29256 static int label = 0;
29258 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
29259 symb = (*targetm.strip_name_encoding) (symb);
29262 length = strlen (symb);
29263 symbol_name = XALLOCAVEC (char, length + 32);
29264 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
29266 lazy_ptr_name = XALLOCAVEC (char, length + 32);
29267 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
29270 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
29272 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
29276 fprintf (file, "\t.align 5\n");
29278 fprintf (file, "%s:\n", stub);
29279 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
29282 local_label_0 = XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
29283 sprintf (local_label_0, "\"L%011d$spb\"", label);
29285 fprintf (file, "\tmflr r0\n");
29286 if (TARGET_LINK_STACK)
29289 get_ppc476_thunk_name (name);
29290 fprintf (file, "\tbl %s\n", name);
29291 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
29295 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
29296 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
29298 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
29299 lazy_ptr_name, local_label_0);
29300 fprintf (file, "\tmtlr r0\n");
29301 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
29302 (TARGET_64BIT ? "ldu" : "lwzu"),
29303 lazy_ptr_name, local_label_0);
29304 fprintf (file, "\tmtctr r12\n");
29305 fprintf (file, "\tbctr\n");
29309 fprintf (file, "\t.align 4\n");
29311 fprintf (file, "%s:\n", stub);
29312 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
29314 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
29315 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
29316 (TARGET_64BIT ? "ldu" : "lwzu"),
29318 fprintf (file, "\tmtctr r12\n");
29319 fprintf (file, "\tbctr\n");
29322 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
29323 fprintf (file, "%s:\n", lazy_ptr_name);
29324 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
29325 fprintf (file, "%sdyld_stub_binding_helper\n",
29326 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
29329 /* Legitimize PIC addresses. If the address is already
29330 position-independent, we return ORIG. Newly generated
29331 position-independent addresses go into a reg. This is REG if non
29332 zero, otherwise we allocate register(s) as necessary. */
29334 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
29337 rs6000_machopic_legitimize_pic_address (rtx orig, machine_mode mode,
29342 if (reg == NULL && ! reload_in_progress && ! reload_completed)
29343 reg = gen_reg_rtx (Pmode);
29345 if (GET_CODE (orig) == CONST)
29349 if (GET_CODE (XEXP (orig, 0)) == PLUS
29350 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
29353 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
29355 /* Use a different reg for the intermediate value, as
29356 it will be marked UNCHANGING. */
29357 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
29358 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
29361 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
29364 if (GET_CODE (offset) == CONST_INT)
29366 if (SMALL_INT (offset))
29367 return plus_constant (Pmode, base, INTVAL (offset));
29368 else if (! reload_in_progress && ! reload_completed)
29369 offset = force_reg (Pmode, offset);
29372 rtx mem = force_const_mem (Pmode, orig);
29373 return machopic_legitimize_pic_address (mem, Pmode, reg);
29376 return gen_rtx_PLUS (Pmode, base, offset);
29379 /* Fall back on generic machopic code. */
29380 return machopic_legitimize_pic_address (orig, mode, reg);
29383 /* Output a .machine directive for the Darwin assembler, and call
29384 the generic start_file routine. */
29387 rs6000_darwin_file_start (void)
29389 static const struct
29393 HOST_WIDE_INT if_set;
29395 { "ppc64", "ppc64", MASK_64BIT },
29396 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
29397 { "power4", "ppc970", 0 },
29398 { "G5", "ppc970", 0 },
29399 { "7450", "ppc7450", 0 },
29400 { "7400", "ppc7400", MASK_ALTIVEC },
29401 { "G4", "ppc7400", 0 },
29402 { "750", "ppc750", 0 },
29403 { "740", "ppc750", 0 },
29404 { "G3", "ppc750", 0 },
29405 { "604e", "ppc604e", 0 },
29406 { "604", "ppc604", 0 },
29407 { "603e", "ppc603", 0 },
29408 { "603", "ppc603", 0 },
29409 { "601", "ppc601", 0 },
29410 { NULL, "ppc", 0 } };
29411 const char *cpu_id = "";
29414 rs6000_file_start ();
29415 darwin_file_start ();
29417 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
29419 if (rs6000_default_cpu != 0 && rs6000_default_cpu[0] != '\0')
29420 cpu_id = rs6000_default_cpu;
29422 if (global_options_set.x_rs6000_cpu_index)
29423 cpu_id = processor_target_table[rs6000_cpu_index].name;
29425 /* Look through the mapping array. Pick the first name that either
29426 matches the argument, has a bit set in IF_SET that is also set
29427 in the target flags, or has a NULL name. */
29430 while (mapping[i].arg != NULL
29431 && strcmp (mapping[i].arg, cpu_id) != 0
29432 && (mapping[i].if_set & rs6000_isa_flags) == 0)
29435 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
29438 #endif /* TARGET_MACHO */
29442 rs6000_elf_reloc_rw_mask (void)
29446 else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
29452 /* Record an element in the table of global constructors. SYMBOL is
29453 a SYMBOL_REF of the function to be called; PRIORITY is a number
29454 between 0 and MAX_INIT_PRIORITY.
29456 This differs from default_named_section_asm_out_constructor in
29457 that we have special handling for -mrelocatable. */
29459 static void rs6000_elf_asm_out_constructor (rtx, int) ATTRIBUTE_UNUSED;
29461 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
29463 const char *section = ".ctors";
29466 if (priority != DEFAULT_INIT_PRIORITY)
29468 sprintf (buf, ".ctors.%.5u",
29469 /* Invert the numbering so the linker puts us in the proper
29470 order; constructors are run from right to left, and the
29471 linker sorts in increasing order. */
29472 MAX_INIT_PRIORITY - priority);
29476 switch_to_section (get_section (section, SECTION_WRITE, NULL));
29477 assemble_align (POINTER_SIZE);
29479 if (TARGET_RELOCATABLE)
29481 fputs ("\t.long (", asm_out_file);
29482 output_addr_const (asm_out_file, symbol);
29483 fputs (")@fixup\n", asm_out_file);
29486 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
29489 static void rs6000_elf_asm_out_destructor (rtx, int) ATTRIBUTE_UNUSED;
29491 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
29493 const char *section = ".dtors";
29496 if (priority != DEFAULT_INIT_PRIORITY)
29498 sprintf (buf, ".dtors.%.5u",
29499 /* Invert the numbering so the linker puts us in the proper
29500 order; constructors are run from right to left, and the
29501 linker sorts in increasing order. */
29502 MAX_INIT_PRIORITY - priority);
29506 switch_to_section (get_section (section, SECTION_WRITE, NULL));
29507 assemble_align (POINTER_SIZE);
29509 if (TARGET_RELOCATABLE)
29511 fputs ("\t.long (", asm_out_file);
29512 output_addr_const (asm_out_file, symbol);
29513 fputs (")@fixup\n", asm_out_file);
29516 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
29520 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
29522 if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2)
29524 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
29525 ASM_OUTPUT_LABEL (file, name);
29526 fputs (DOUBLE_INT_ASM_OP, file);
29527 rs6000_output_function_entry (file, name);
29528 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
29531 fputs ("\t.size\t", file);
29532 assemble_name (file, name);
29533 fputs (",24\n\t.type\t.", file);
29534 assemble_name (file, name);
29535 fputs (",@function\n", file);
29536 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
29538 fputs ("\t.globl\t.", file);
29539 assemble_name (file, name);
29544 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
29545 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
29546 rs6000_output_function_entry (file, name);
29547 fputs (":\n", file);
29551 if (TARGET_RELOCATABLE
29552 && !TARGET_SECURE_PLT
29553 && (get_pool_size () != 0 || crtl->profile)
29558 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
29560 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
29561 fprintf (file, "\t.long ");
29562 assemble_name (file, buf);
29564 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
29565 assemble_name (file, buf);
29569 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
29570 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
29572 if (DEFAULT_ABI == ABI_AIX)
29574 const char *desc_name, *orig_name;
29576 orig_name = (*targetm.strip_name_encoding) (name);
29577 desc_name = orig_name;
29578 while (*desc_name == '.')
29581 if (TREE_PUBLIC (decl))
29582 fprintf (file, "\t.globl %s\n", desc_name);
29584 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
29585 fprintf (file, "%s:\n", desc_name);
29586 fprintf (file, "\t.long %s\n", orig_name);
29587 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
29588 fputs ("\t.long 0\n", file);
29589 fprintf (file, "\t.previous\n");
29591 ASM_OUTPUT_LABEL (file, name);
29594 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED;
29596 rs6000_elf_file_end (void)
29598 #ifdef HAVE_AS_GNU_ATTRIBUTE
29599 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
29601 if (rs6000_passes_float)
29602 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
29603 ((TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) ? 1
29604 : (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT) ? 3
29606 if (rs6000_passes_vector)
29607 fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n",
29608 (TARGET_ALTIVEC_ABI ? 2
29609 : TARGET_SPE_ABI ? 3
29611 if (rs6000_returns_struct)
29612 fprintf (asm_out_file, "\t.gnu_attribute 12, %d\n",
29613 aix_struct_return ? 2 : 1);
29616 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
29617 if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2)
29618 file_end_indicate_exec_stack ();
29625 rs6000_xcoff_asm_output_anchor (rtx symbol)
29629 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
29630 SYMBOL_REF_BLOCK_OFFSET (symbol));
29631 fprintf (asm_out_file, "%s", SET_ASM_OP);
29632 RS6000_OUTPUT_BASENAME (asm_out_file, XSTR (symbol, 0));
29633 fprintf (asm_out_file, ",");
29634 RS6000_OUTPUT_BASENAME (asm_out_file, buffer);
29635 fprintf (asm_out_file, "\n");
29639 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
29641 fputs (GLOBAL_ASM_OP, stream);
29642 RS6000_OUTPUT_BASENAME (stream, name);
29643 putc ('\n', stream);
29646 /* A get_unnamed_decl callback, used for read-only sections. PTR
29647 points to the section string variable. */
29650 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
29652 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
29653 *(const char *const *) directive,
29654 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
29657 /* Likewise for read-write sections. */
29660 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
29662 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
29663 *(const char *const *) directive,
29664 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
29668 rs6000_xcoff_output_tls_section_asm_op (const void *directive)
29670 fprintf (asm_out_file, "\t.csect %s[TL],%s\n",
29671 *(const char *const *) directive,
29672 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
29675 /* A get_unnamed_section callback, used for switching to toc_section. */
29678 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
29680 if (TARGET_MINIMAL_TOC)
29682 /* toc_section is always selected at least once from
29683 rs6000_xcoff_file_start, so this is guaranteed to
29684 always be defined once and only once in each file. */
29685 if (!toc_initialized)
29687 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
29688 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
29689 toc_initialized = 1;
29691 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
29692 (TARGET_32BIT ? "" : ",3"));
29695 fputs ("\t.toc\n", asm_out_file);
29698 /* Implement TARGET_ASM_INIT_SECTIONS. */
29701 rs6000_xcoff_asm_init_sections (void)
29703 read_only_data_section
29704 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
29705 &xcoff_read_only_section_name);
29707 private_data_section
29708 = get_unnamed_section (SECTION_WRITE,
29709 rs6000_xcoff_output_readwrite_section_asm_op,
29710 &xcoff_private_data_section_name);
29713 = get_unnamed_section (SECTION_TLS,
29714 rs6000_xcoff_output_tls_section_asm_op,
29715 &xcoff_tls_data_section_name);
29717 tls_private_data_section
29718 = get_unnamed_section (SECTION_TLS,
29719 rs6000_xcoff_output_tls_section_asm_op,
29720 &xcoff_private_data_section_name);
29722 read_only_private_data_section
29723 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
29724 &xcoff_private_data_section_name);
29727 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
29729 readonly_data_section = read_only_data_section;
29730 exception_section = data_section;
29734 rs6000_xcoff_reloc_rw_mask (void)
29740 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
29741 tree decl ATTRIBUTE_UNUSED)
29744 static const char * const suffix[4] = { "PR", "RO", "RW", "TL" };
29746 if (flags & SECTION_CODE)
29748 else if (flags & SECTION_TLS)
29750 else if (flags & SECTION_WRITE)
29755 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
29756 (flags & SECTION_CODE) ? "." : "",
29757 name, suffix[smclass], flags & SECTION_ENTSIZE);
29760 #define IN_NAMED_SECTION(DECL) \
29761 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
29762 && DECL_SECTION_NAME (DECL) != NULL)
29765 rs6000_xcoff_select_section (tree decl, int reloc,
29766 unsigned HOST_WIDE_INT align)
29768 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
29770 if (align > BIGGEST_ALIGNMENT)
29772 resolve_unique_section (decl, reloc, true);
29773 if (IN_NAMED_SECTION (decl))
29774 return get_named_section (decl, NULL, reloc);
29777 if (decl_readonly_section (decl, reloc))
29779 if (TREE_PUBLIC (decl))
29780 return read_only_data_section;
29782 return read_only_private_data_section;
29787 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
29789 if (TREE_PUBLIC (decl))
29790 return tls_data_section;
29791 else if (bss_initializer_p (decl))
29793 /* Convert to COMMON to emit in BSS. */
29794 DECL_COMMON (decl) = 1;
29795 return tls_comm_section;
29798 return tls_private_data_section;
29802 if (TREE_PUBLIC (decl))
29803 return data_section;
29805 return private_data_section;
29810 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
29814 /* Use select_section for private data and uninitialized data with
29815 alignment <= BIGGEST_ALIGNMENT. */
29816 if (!TREE_PUBLIC (decl)
29817 || DECL_COMMON (decl)
29818 || (DECL_INITIAL (decl) == NULL_TREE
29819 && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT)
29820 || DECL_INITIAL (decl) == error_mark_node
29821 || (flag_zero_initialized_in_bss
29822 && initializer_zerop (DECL_INITIAL (decl))))
29825 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
29826 name = (*targetm.strip_name_encoding) (name);
29827 set_decl_section_name (decl, name);
29830 /* Select section for constant in constant pool.
29832 On RS/6000, all constants are in the private read-only data area.
29833 However, if this is being placed in the TOC it must be output as a
29837 rs6000_xcoff_select_rtx_section (machine_mode mode, rtx x,
29838 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
29840 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
29841 return toc_section;
29843 return read_only_private_data_section;
29846 /* Remove any trailing [DS] or the like from the symbol name. */
29848 static const char *
29849 rs6000_xcoff_strip_name_encoding (const char *name)
29854 len = strlen (name);
29855 if (name[len - 1] == ']')
29856 return ggc_alloc_string (name, len - 4);
29861 /* Section attributes. AIX is always PIC. */
29863 static unsigned int
29864 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
29866 unsigned int align;
29867 unsigned int flags = default_section_type_flags (decl, name, reloc);
29869 /* Align to at least UNIT size. */
29870 if ((flags & SECTION_CODE) != 0 || !decl || !DECL_P (decl))
29871 align = MIN_UNITS_PER_WORD;
29873 /* Increase alignment of large objects if not already stricter. */
29874 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
29875 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
29876 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
29878 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
29881 /* Output at beginning of assembler file.
29883 Initialize the section names for the RS/6000 at this point.
29885 Specify filename, including full path, to assembler.
29887 We want to go into the TOC section so at least one .toc will be emitted.
29888 Also, in order to output proper .bs/.es pairs, we need at least one static
29889 [RW] section emitted.
29891 Finally, declare mcount when profiling to make the assembler happy. */
29894 rs6000_xcoff_file_start (void)
29896 rs6000_gen_section_name (&xcoff_bss_section_name,
29897 main_input_filename, ".bss_");
29898 rs6000_gen_section_name (&xcoff_private_data_section_name,
29899 main_input_filename, ".rw_");
29900 rs6000_gen_section_name (&xcoff_read_only_section_name,
29901 main_input_filename, ".ro_");
29902 rs6000_gen_section_name (&xcoff_tls_data_section_name,
29903 main_input_filename, ".tls_");
29904 rs6000_gen_section_name (&xcoff_tbss_section_name,
29905 main_input_filename, ".tbss_[UL]");
29907 fputs ("\t.file\t", asm_out_file);
29908 output_quoted_string (asm_out_file, main_input_filename);
29909 fputc ('\n', asm_out_file);
29910 if (write_symbols != NO_DEBUG)
29911 switch_to_section (private_data_section);
29912 switch_to_section (text_section);
29914 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
29915 rs6000_file_start ();
29918 /* Output at end of assembler file.
29919 On the RS/6000, referencing data should automatically pull in text. */
29922 rs6000_xcoff_file_end (void)
29924 switch_to_section (text_section);
29925 fputs ("_section_.text:\n", asm_out_file);
29926 switch_to_section (data_section);
29927 fputs (TARGET_32BIT
29928 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
29932 struct declare_alias_data
29935 bool function_descriptor;
29938 /* Declare alias N. A helper function for for_node_and_aliases. */
29941 rs6000_declare_alias (struct symtab_node *n, void *d)
29943 struct declare_alias_data *data = (struct declare_alias_data *)d;
29944 /* Main symbol is output specially, because varasm machinery does part of
29945 the job for us - we do not need to declare .globl/lglobs and such. */
29946 if (!n->alias || n->weakref)
29949 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n->decl)))
29952 /* Prevent assemble_alias from trying to use .set pseudo operation
29953 that does not behave as expected by the middle-end. */
29954 TREE_ASM_WRITTEN (n->decl) = true;
29956 const char *name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n->decl));
29957 char *buffer = (char *) alloca (strlen (name) + 2);
29959 int dollar_inside = 0;
29961 strcpy (buffer, name);
29962 p = strchr (buffer, '$');
29966 p = strchr (p + 1, '$');
29968 if (TREE_PUBLIC (n->decl))
29970 if (!RS6000_WEAK || !DECL_WEAK (n->decl))
29972 if (dollar_inside) {
29973 if (data->function_descriptor)
29974 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
29976 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
29978 if (data->function_descriptor)
29979 fputs ("\t.globl .", data->file);
29981 fputs ("\t.globl ", data->file);
29982 RS6000_OUTPUT_BASENAME (data->file, buffer);
29983 putc ('\n', data->file);
29985 else if (DECL_WEAK (n->decl) && !data->function_descriptor)
29986 ASM_WEAKEN_DECL (data->file, n->decl, name, NULL);
29992 if (data->function_descriptor)
29993 fprintf(data->file, "\t.rename %s,\"%s\"\n", buffer, name);
29995 fprintf(data->file, "\t.rename .%s,\".%s\"\n", buffer, name);
29997 if (data->function_descriptor)
29998 fputs ("\t.lglobl .", data->file);
30000 fputs ("\t.lglobl ", data->file);
30001 RS6000_OUTPUT_BASENAME (data->file, buffer);
30002 putc ('\n', data->file);
30004 if (data->function_descriptor)
30005 fputs (".", data->file);
30006 RS6000_OUTPUT_BASENAME (data->file, buffer);
30007 fputs (":\n", data->file);
30011 /* This macro produces the initial definition of a function name.
30012 On the RS/6000, we need to place an extra '.' in the function name and
30013 output the function descriptor.
30014 Dollar signs are converted to underscores.
30016 The csect for the function will have already been created when
30017 text_section was selected. We do have to go back to that csect, however.
30019 The third and fourth parameters to the .function pseudo-op (16 and 044)
30020 are placeholders which no longer have any use.
30022 Because AIX assembler's .set command has unexpected semantics, we output
30023 all aliases as alternative labels in front of the definition. */
30026 rs6000_xcoff_declare_function_name (FILE *file, const char *name, tree decl)
30028 char *buffer = (char *) alloca (strlen (name) + 1);
30030 int dollar_inside = 0;
30031 struct declare_alias_data data = {file, false};
30033 strcpy (buffer, name);
30034 p = strchr (buffer, '$');
30038 p = strchr (p + 1, '$');
30040 if (TREE_PUBLIC (decl))
30042 if (!RS6000_WEAK || !DECL_WEAK (decl))
30044 if (dollar_inside) {
30045 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
30046 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
30048 fputs ("\t.globl .", file);
30049 RS6000_OUTPUT_BASENAME (file, buffer);
30055 if (dollar_inside) {
30056 fprintf(file, "\t.rename .%s,\".%s\"\n", buffer, name);
30057 fprintf(file, "\t.rename %s,\"%s\"\n", buffer, name);
30059 fputs ("\t.lglobl .", file);
30060 RS6000_OUTPUT_BASENAME (file, buffer);
30063 fputs ("\t.csect ", file);
30064 RS6000_OUTPUT_BASENAME (file, buffer);
30065 fputs (TARGET_32BIT ? "[DS]\n" : "[DS],3\n", file);
30066 RS6000_OUTPUT_BASENAME (file, buffer);
30067 fputs (":\n", file);
30068 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias, &data, true);
30069 fputs (TARGET_32BIT ? "\t.long ." : "\t.llong .", file);
30070 RS6000_OUTPUT_BASENAME (file, buffer);
30071 fputs (", TOC[tc0], 0\n", file);
30073 switch_to_section (function_section (decl));
30075 RS6000_OUTPUT_BASENAME (file, buffer);
30076 fputs (":\n", file);
30077 data.function_descriptor = true;
30078 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias, &data, true);
30079 if (write_symbols != NO_DEBUG && !DECL_IGNORED_P (decl))
30080 xcoffout_declare_function (file, decl, buffer);
30084 /* This macro produces the initial definition of a object (variable) name.
30085 Because AIX assembler's .set command has unexpected semantics, we output
30086 all aliases as alternative labels in front of the definition. */
30089 rs6000_xcoff_declare_object_name (FILE *file, const char *name, tree decl)
30091 struct declare_alias_data data = {file, false};
30092 RS6000_OUTPUT_BASENAME (file, name);
30093 fputs (":\n", file);
30094 symtab_node::get (decl)->call_for_symbol_and_aliases (rs6000_declare_alias, &data, true);
30099 rs6000_xcoff_encode_section_info (tree decl, rtx rtl, int first)
30104 default_encode_section_info (decl, rtl, first);
30106 /* Careful not to prod global register variables. */
30109 symbol = XEXP (rtl, 0);
30110 if (GET_CODE (symbol) != SYMBOL_REF)
30113 flags = SYMBOL_REF_FLAGS (symbol);
30115 if (TREE_CODE (decl) == VAR_DECL && DECL_THREAD_LOCAL_P (decl))
30116 flags &= ~SYMBOL_FLAG_HAS_BLOCK_INFO;
30118 SYMBOL_REF_FLAGS (symbol) = flags;
30120 #endif /* HAVE_AS_TLS */
30121 #endif /* TARGET_XCOFF */
30123 /* Compute a (partial) cost for rtx X. Return true if the complete
30124 cost has been computed, and false if subexpressions should be
30125 scanned. In either case, *TOTAL contains the cost result. */
30128 rs6000_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
30129 int *total, bool speed)
30131 machine_mode mode = GET_MODE (x);
30135 /* On the RS/6000, if it is valid in the insn, it is free. */
30137 if (((outer_code == SET
30138 || outer_code == PLUS
30139 || outer_code == MINUS)
30140 && (satisfies_constraint_I (x)
30141 || satisfies_constraint_L (x)))
30142 || (outer_code == AND
30143 && (satisfies_constraint_K (x)
30145 ? satisfies_constraint_L (x)
30146 : satisfies_constraint_J (x))
30147 || mask_operand (x, mode)
30149 && mask64_operand (x, DImode))))
30150 || ((outer_code == IOR || outer_code == XOR)
30151 && (satisfies_constraint_K (x)
30153 ? satisfies_constraint_L (x)
30154 : satisfies_constraint_J (x))))
30155 || outer_code == ASHIFT
30156 || outer_code == ASHIFTRT
30157 || outer_code == LSHIFTRT
30158 || outer_code == ROTATE
30159 || outer_code == ROTATERT
30160 || outer_code == ZERO_EXTRACT
30161 || (outer_code == MULT
30162 && satisfies_constraint_I (x))
30163 || ((outer_code == DIV || outer_code == UDIV
30164 || outer_code == MOD || outer_code == UMOD)
30165 && exact_log2 (INTVAL (x)) >= 0)
30166 || (outer_code == COMPARE
30167 && (satisfies_constraint_I (x)
30168 || satisfies_constraint_K (x)))
30169 || ((outer_code == EQ || outer_code == NE)
30170 && (satisfies_constraint_I (x)
30171 || satisfies_constraint_K (x)
30173 ? satisfies_constraint_L (x)
30174 : satisfies_constraint_J (x))))
30175 || (outer_code == GTU
30176 && satisfies_constraint_I (x))
30177 || (outer_code == LTU
30178 && satisfies_constraint_P (x)))
30183 else if ((outer_code == PLUS
30184 && reg_or_add_cint_operand (x, VOIDmode))
30185 || (outer_code == MINUS
30186 && reg_or_sub_cint_operand (x, VOIDmode))
30187 || ((outer_code == SET
30188 || outer_code == IOR
30189 || outer_code == XOR)
30191 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
30193 *total = COSTS_N_INSNS (1);
30199 case CONST_WIDE_INT:
30204 /* When optimizing for size, MEM should be slightly more expensive
30205 than generating address, e.g., (plus (reg) (const)).
30206 L1 cache latency is about two instructions. */
30207 *total = !speed ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
30216 if (FLOAT_MODE_P (mode))
30217 *total = rs6000_cost->fp;
30219 *total = COSTS_N_INSNS (1);
30223 if (GET_CODE (XEXP (x, 1)) == CONST_INT
30224 && satisfies_constraint_I (XEXP (x, 1)))
30226 if (INTVAL (XEXP (x, 1)) >= -256
30227 && INTVAL (XEXP (x, 1)) <= 255)
30228 *total = rs6000_cost->mulsi_const9;
30230 *total = rs6000_cost->mulsi_const;
30232 else if (mode == SFmode)
30233 *total = rs6000_cost->fp;
30234 else if (FLOAT_MODE_P (mode))
30235 *total = rs6000_cost->dmul;
30236 else if (mode == DImode)
30237 *total = rs6000_cost->muldi;
30239 *total = rs6000_cost->mulsi;
30243 if (mode == SFmode)
30244 *total = rs6000_cost->fp;
30246 *total = rs6000_cost->dmul;
30251 if (FLOAT_MODE_P (mode))
30253 *total = mode == DFmode ? rs6000_cost->ddiv
30254 : rs6000_cost->sdiv;
30261 if (GET_CODE (XEXP (x, 1)) == CONST_INT
30262 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
30264 if (code == DIV || code == MOD)
30266 *total = COSTS_N_INSNS (2);
30269 *total = COSTS_N_INSNS (1);
30273 if (GET_MODE (XEXP (x, 1)) == DImode)
30274 *total = rs6000_cost->divdi;
30276 *total = rs6000_cost->divsi;
30278 /* Add in shift and subtract for MOD. */
30279 if (code == MOD || code == UMOD)
30280 *total += COSTS_N_INSNS (2);
30285 *total = COSTS_N_INSNS (4);
30289 *total = COSTS_N_INSNS (TARGET_POPCNTD ? 1 : 6);
30293 *total = COSTS_N_INSNS (TARGET_CMPB ? 2 : 6);
30297 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
30309 *total = COSTS_N_INSNS (1);
30317 /* Handle mul_highpart. */
30318 if (outer_code == TRUNCATE
30319 && GET_CODE (XEXP (x, 0)) == MULT)
30321 if (mode == DImode)
30322 *total = rs6000_cost->muldi;
30324 *total = rs6000_cost->mulsi;
30327 else if (outer_code == AND)
30330 *total = COSTS_N_INSNS (1);
30335 if (GET_CODE (XEXP (x, 0)) == MEM)
30338 *total = COSTS_N_INSNS (1);
30344 if (!FLOAT_MODE_P (mode))
30346 *total = COSTS_N_INSNS (1);
30352 case UNSIGNED_FLOAT:
30355 case FLOAT_TRUNCATE:
30356 *total = rs6000_cost->fp;
30360 if (mode == DFmode)
30363 *total = rs6000_cost->fp;
30367 switch (XINT (x, 1))
30370 *total = rs6000_cost->fp;
30382 *total = COSTS_N_INSNS (1);
30385 else if (FLOAT_MODE_P (mode)
30386 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
30388 *total = rs6000_cost->fp;
30397 /* Carry bit requires mode == Pmode.
30398 NEG or PLUS already counted so only add one. */
30400 && (outer_code == NEG || outer_code == PLUS))
30402 *total = COSTS_N_INSNS (1);
30405 if (outer_code == SET)
30407 if (XEXP (x, 1) == const0_rtx)
30409 if (TARGET_ISEL && !TARGET_MFCRF)
30410 *total = COSTS_N_INSNS (8);
30412 *total = COSTS_N_INSNS (2);
30415 else if (mode == Pmode)
30417 *total = COSTS_N_INSNS (3);
30426 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
30428 if (TARGET_ISEL && !TARGET_MFCRF)
30429 *total = COSTS_N_INSNS (8);
30431 *total = COSTS_N_INSNS (2);
30435 if (outer_code == COMPARE)
30449 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
30452 rs6000_debug_rtx_costs (rtx x, int code, int outer_code, int opno, int *total,
30455 bool ret = rs6000_rtx_costs (x, code, outer_code, opno, total, speed);
30458 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
30459 "opno = %d, total = %d, speed = %s, x:\n",
30460 ret ? "complete" : "scan inner",
30461 GET_RTX_NAME (code),
30462 GET_RTX_NAME (outer_code),
30465 speed ? "true" : "false");
30472 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
30475 rs6000_debug_address_cost (rtx x, machine_mode mode,
30476 addr_space_t as, bool speed)
30478 int ret = TARGET_ADDRESS_COST (x, mode, as, speed);
30480 fprintf (stderr, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
30481 ret, speed ? "true" : "false");
30488 /* A C expression returning the cost of moving data from a register of class
30489 CLASS1 to one of CLASS2. */
30492 rs6000_register_move_cost (machine_mode mode,
30493 reg_class_t from, reg_class_t to)
30497 if (TARGET_DEBUG_COST)
30500 /* Moves from/to GENERAL_REGS. */
30501 if (reg_classes_intersect_p (to, GENERAL_REGS)
30502 || reg_classes_intersect_p (from, GENERAL_REGS))
30504 reg_class_t rclass = from;
30506 if (! reg_classes_intersect_p (to, GENERAL_REGS))
30509 if (rclass == FLOAT_REGS || rclass == ALTIVEC_REGS || rclass == VSX_REGS)
30510 ret = (rs6000_memory_move_cost (mode, rclass, false)
30511 + rs6000_memory_move_cost (mode, GENERAL_REGS, false));
30513 /* It's more expensive to move CR_REGS than CR0_REGS because of the
30515 else if (rclass == CR_REGS)
30518 /* For those processors that have slow LR/CTR moves, make them more
30519 expensive than memory in order to bias spills to memory .*/
30520 else if ((rs6000_cpu == PROCESSOR_POWER6
30521 || rs6000_cpu == PROCESSOR_POWER7
30522 || rs6000_cpu == PROCESSOR_POWER8)
30523 && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS))
30524 ret = 6 * hard_regno_nregs[0][mode];
30527 /* A move will cost one instruction per GPR moved. */
30528 ret = 2 * hard_regno_nregs[0][mode];
30531 /* If we have VSX, we can easily move between FPR or Altivec registers. */
30532 else if (VECTOR_MEM_VSX_P (mode)
30533 && reg_classes_intersect_p (to, VSX_REGS)
30534 && reg_classes_intersect_p (from, VSX_REGS))
30535 ret = 2 * hard_regno_nregs[32][mode];
30537 /* Moving between two similar registers is just one instruction. */
30538 else if (reg_classes_intersect_p (to, from))
30539 ret = (mode == TFmode || mode == TDmode) ? 4 : 2;
30541 /* Everything else has to go through GENERAL_REGS. */
30543 ret = (rs6000_register_move_cost (mode, GENERAL_REGS, to)
30544 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
30546 if (TARGET_DEBUG_COST)
30548 if (dbg_cost_ctrl == 1)
30550 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
30551 ret, GET_MODE_NAME (mode), reg_class_names[from],
30552 reg_class_names[to]);
30559 /* A C expressions returning the cost of moving data of MODE from a register to
30563 rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass,
30564 bool in ATTRIBUTE_UNUSED)
30568 if (TARGET_DEBUG_COST)
30571 if (reg_classes_intersect_p (rclass, GENERAL_REGS))
30572 ret = 4 * hard_regno_nregs[0][mode];
30573 else if ((reg_classes_intersect_p (rclass, FLOAT_REGS)
30574 || reg_classes_intersect_p (rclass, VSX_REGS)))
30575 ret = 4 * hard_regno_nregs[32][mode];
30576 else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS))
30577 ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
30579 ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
30581 if (TARGET_DEBUG_COST)
30583 if (dbg_cost_ctrl == 1)
30585 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
30586 ret, GET_MODE_NAME (mode), reg_class_names[rclass], in);
30593 /* Returns a code for a target-specific builtin that implements
30594 reciprocal of the function, or NULL_TREE if not available. */
30597 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
30598 bool sqrt ATTRIBUTE_UNUSED)
30600 if (optimize_insn_for_size_p ())
30606 case VSX_BUILTIN_XVSQRTDP:
30607 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode))
30610 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_2DF];
30612 case VSX_BUILTIN_XVSQRTSP:
30613 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode))
30616 return rs6000_builtin_decls[VSX_BUILTIN_RSQRT_4SF];
30625 case BUILT_IN_SQRT:
30626 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode))
30629 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRT];
30631 case BUILT_IN_SQRTF:
30632 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode))
30635 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
30642 /* Load up a constant. If the mode is a vector mode, splat the value across
30643 all of the vector elements. */
30646 rs6000_load_constant_and_splat (machine_mode mode, REAL_VALUE_TYPE dconst)
30650 if (mode == SFmode || mode == DFmode)
30652 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, mode);
30653 reg = force_reg (mode, d);
30655 else if (mode == V4SFmode)
30657 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, SFmode);
30658 rtvec v = gen_rtvec (4, d, d, d, d);
30659 reg = gen_reg_rtx (mode);
30660 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
30662 else if (mode == V2DFmode)
30664 rtx d = CONST_DOUBLE_FROM_REAL_VALUE (dconst, DFmode);
30665 rtvec v = gen_rtvec (2, d, d);
30666 reg = gen_reg_rtx (mode);
30667 rs6000_expand_vector_init (reg, gen_rtx_PARALLEL (mode, v));
30670 gcc_unreachable ();
30675 /* Generate an FMA instruction. */
30678 rs6000_emit_madd (rtx target, rtx m1, rtx m2, rtx a)
30680 machine_mode mode = GET_MODE (target);
30683 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
30684 gcc_assert (dst != NULL);
30687 emit_move_insn (target, dst);
30690 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
30693 rs6000_emit_msub (rtx target, rtx m1, rtx m2, rtx a)
30695 machine_mode mode = GET_MODE (target);
30698 /* Altivec does not support fms directly;
30699 generate in terms of fma in that case. */
30700 if (optab_handler (fms_optab, mode) != CODE_FOR_nothing)
30701 dst = expand_ternary_op (mode, fms_optab, m1, m2, a, target, 0);
30704 a = expand_unop (mode, neg_optab, a, NULL_RTX, 0);
30705 dst = expand_ternary_op (mode, fma_optab, m1, m2, a, target, 0);
30707 gcc_assert (dst != NULL);
30710 emit_move_insn (target, dst);
30713 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
30716 rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a)
30718 machine_mode mode = GET_MODE (dst);
30721 /* This is a tad more complicated, since the fnma_optab is for
30722 a different expression: fma(-m1, m2, a), which is the same
30723 thing except in the case of signed zeros.
30725 Fortunately we know that if FMA is supported that FNMSUB is
30726 also supported in the ISA. Just expand it directly. */
30728 gcc_assert (optab_handler (fma_optab, mode) != CODE_FOR_nothing);
30730 r = gen_rtx_NEG (mode, a);
30731 r = gen_rtx_FMA (mode, m1, m2, r);
30732 r = gen_rtx_NEG (mode, r);
30733 emit_insn (gen_rtx_SET (VOIDmode, dst, r));
30736 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
30737 add a reg_note saying that this was a division. Support both scalar and
30738 vector divide. Assumes no trapping math and finite arguments. */
30741 rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p)
30743 machine_mode mode = GET_MODE (dst);
30744 rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v;
30747 /* Low precision estimates guarantee 5 bits of accuracy. High
30748 precision estimates guarantee 14 bits of accuracy. SFmode
30749 requires 23 bits of accuracy. DFmode requires 52 bits of
30750 accuracy. Each pass at least doubles the accuracy, leading
30751 to the following. */
30752 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
30753 if (mode == DFmode || mode == V2DFmode)
30756 enum insn_code code = optab_handler (smul_optab, mode);
30757 insn_gen_fn gen_mul = GEN_FCN (code);
30759 gcc_assert (code != CODE_FOR_nothing);
30761 one = rs6000_load_constant_and_splat (mode, dconst1);
30763 /* x0 = 1./d estimate */
30764 x0 = gen_reg_rtx (mode);
30765 emit_insn (gen_rtx_SET (VOIDmode, x0,
30766 gen_rtx_UNSPEC (mode, gen_rtvec (1, d),
30769 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
30772 /* e0 = 1. - d * x0 */
30773 e0 = gen_reg_rtx (mode);
30774 rs6000_emit_nmsub (e0, d, x0, one);
30776 /* x1 = x0 + e0 * x0 */
30777 x1 = gen_reg_rtx (mode);
30778 rs6000_emit_madd (x1, e0, x0, x0);
30780 for (i = 0, xprev = x1, eprev = e0; i < passes - 2;
30781 ++i, xprev = xnext, eprev = enext) {
30783 /* enext = eprev * eprev */
30784 enext = gen_reg_rtx (mode);
30785 emit_insn (gen_mul (enext, eprev, eprev));
30787 /* xnext = xprev + enext * xprev */
30788 xnext = gen_reg_rtx (mode);
30789 rs6000_emit_madd (xnext, enext, xprev, xprev);
30795 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
30797 /* u = n * xprev */
30798 u = gen_reg_rtx (mode);
30799 emit_insn (gen_mul (u, n, xprev));
30801 /* v = n - (d * u) */
30802 v = gen_reg_rtx (mode);
30803 rs6000_emit_nmsub (v, d, u, n);
30805 /* dst = (v * xprev) + u */
30806 rs6000_emit_madd (dst, v, xprev, u);
30809 add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d));
30812 /* Newton-Raphson approximation of single/double-precision floating point
30813 rsqrt. Assumes no trapping math and finite arguments. */
30816 rs6000_emit_swrsqrt (rtx dst, rtx src)
30818 machine_mode mode = GET_MODE (src);
30819 rtx x0 = gen_reg_rtx (mode);
30820 rtx y = gen_reg_rtx (mode);
30822 /* Low precision estimates guarantee 5 bits of accuracy. High
30823 precision estimates guarantee 14 bits of accuracy. SFmode
30824 requires 23 bits of accuracy. DFmode requires 52 bits of
30825 accuracy. Each pass at least doubles the accuracy, leading
30826 to the following. */
30827 int passes = (TARGET_RECIP_PRECISION) ? 1 : 3;
30828 if (mode == DFmode || mode == V2DFmode)
30831 REAL_VALUE_TYPE dconst3_2;
30834 enum insn_code code = optab_handler (smul_optab, mode);
30835 insn_gen_fn gen_mul = GEN_FCN (code);
30837 gcc_assert (code != CODE_FOR_nothing);
30839 /* Load up the constant 1.5 either as a scalar, or as a vector. */
30840 real_from_integer (&dconst3_2, VOIDmode, 3, SIGNED);
30841 SET_REAL_EXP (&dconst3_2, REAL_EXP (&dconst3_2) - 1);
30843 halfthree = rs6000_load_constant_and_splat (mode, dconst3_2);
30845 /* x0 = rsqrt estimate */
30846 emit_insn (gen_rtx_SET (VOIDmode, x0,
30847 gen_rtx_UNSPEC (mode, gen_rtvec (1, src),
30850 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
30851 rs6000_emit_msub (y, src, halfthree, src);
30853 for (i = 0; i < passes; i++)
30855 rtx x1 = gen_reg_rtx (mode);
30856 rtx u = gen_reg_rtx (mode);
30857 rtx v = gen_reg_rtx (mode);
30859 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
30860 emit_insn (gen_mul (u, x0, x0));
30861 rs6000_emit_nmsub (v, y, u, halfthree);
30862 emit_insn (gen_mul (x1, x0, v));
30866 emit_move_insn (dst, x0);
30870 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
30871 (Power7) targets. DST is the target, and SRC is the argument operand. */
30874 rs6000_emit_popcount (rtx dst, rtx src)
30876 machine_mode mode = GET_MODE (dst);
30879 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
30880 if (TARGET_POPCNTD)
30882 if (mode == SImode)
30883 emit_insn (gen_popcntdsi2 (dst, src));
30885 emit_insn (gen_popcntddi2 (dst, src));
30889 tmp1 = gen_reg_rtx (mode);
30891 if (mode == SImode)
30893 emit_insn (gen_popcntbsi2 (tmp1, src));
30894 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
30896 tmp2 = force_reg (SImode, tmp2);
30897 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
30901 emit_insn (gen_popcntbdi2 (tmp1, src));
30902 tmp2 = expand_mult (DImode, tmp1,
30903 GEN_INT ((HOST_WIDE_INT)
30904 0x01010101 << 32 | 0x01010101),
30906 tmp2 = force_reg (DImode, tmp2);
30907 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
30912 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
30913 target, and SRC is the argument operand. */
30916 rs6000_emit_parity (rtx dst, rtx src)
30918 machine_mode mode = GET_MODE (dst);
30921 tmp = gen_reg_rtx (mode);
30923 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
30926 if (mode == SImode)
30928 emit_insn (gen_popcntbsi2 (tmp, src));
30929 emit_insn (gen_paritysi2_cmpb (dst, tmp));
30933 emit_insn (gen_popcntbdi2 (tmp, src));
30934 emit_insn (gen_paritydi2_cmpb (dst, tmp));
30939 if (mode == SImode)
30941 /* Is mult+shift >= shift+xor+shift+xor? */
30942 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
30944 rtx tmp1, tmp2, tmp3, tmp4;
30946 tmp1 = gen_reg_rtx (SImode);
30947 emit_insn (gen_popcntbsi2 (tmp1, src));
30949 tmp2 = gen_reg_rtx (SImode);
30950 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
30951 tmp3 = gen_reg_rtx (SImode);
30952 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
30954 tmp4 = gen_reg_rtx (SImode);
30955 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
30956 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
30959 rs6000_emit_popcount (tmp, src);
30960 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
30964 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
30965 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
30967 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
30969 tmp1 = gen_reg_rtx (DImode);
30970 emit_insn (gen_popcntbdi2 (tmp1, src));
30972 tmp2 = gen_reg_rtx (DImode);
30973 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
30974 tmp3 = gen_reg_rtx (DImode);
30975 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
30977 tmp4 = gen_reg_rtx (DImode);
30978 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
30979 tmp5 = gen_reg_rtx (DImode);
30980 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
30982 tmp6 = gen_reg_rtx (DImode);
30983 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
30984 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
30987 rs6000_emit_popcount (tmp, src);
30988 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
30992 /* Expand an Altivec constant permutation for little endian mode.
30993 There are two issues: First, the two input operands must be
30994 swapped so that together they form a double-wide array in LE
30995 order. Second, the vperm instruction has surprising behavior
30996 in LE mode: it interprets the elements of the source vectors
30997 in BE mode ("left to right") and interprets the elements of
30998 the destination vector in LE mode ("right to left"). To
30999 correct for this, we must subtract each element of the permute
31000 control vector from 31.
31002 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
31003 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
31004 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
31005 serve as the permute control vector. Then, in BE mode,
31009 places the desired result in vr9. However, in LE mode the
31010 vector contents will be
31012 vr10 = 00000003 00000002 00000001 00000000
31013 vr11 = 00000007 00000006 00000005 00000004
31015 The result of the vperm using the same permute control vector is
31017 vr9 = 05000000 07000000 01000000 03000000
31019 That is, the leftmost 4 bytes of vr10 are interpreted as the
31020 source for the rightmost 4 bytes of vr9, and so on.
31022 If we change the permute control vector to
31024 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
31032 vr9 = 00000006 00000004 00000002 00000000. */
31035 altivec_expand_vec_perm_const_le (rtx operands[4])
31039 rtx constv, unspec;
31040 rtx target = operands[0];
31041 rtx op0 = operands[1];
31042 rtx op1 = operands[2];
31043 rtx sel = operands[3];
31045 /* Unpack and adjust the constant selector. */
31046 for (i = 0; i < 16; ++i)
31048 rtx e = XVECEXP (sel, 0, i);
31049 unsigned int elt = 31 - (INTVAL (e) & 31);
31050 perm[i] = GEN_INT (elt);
31053 /* Expand to a permute, swapping the inputs and using the
31054 adjusted selector. */
31056 op0 = force_reg (V16QImode, op0);
31058 op1 = force_reg (V16QImode, op1);
31060 constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm));
31061 constv = force_reg (V16QImode, constv);
31062 unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv),
31064 if (!REG_P (target))
31066 rtx tmp = gen_reg_rtx (V16QImode);
31067 emit_move_insn (tmp, unspec);
31071 emit_move_insn (target, unspec);
31074 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
31075 permute control vector. But here it's not a constant, so we must
31076 generate a vector NAND or NOR to do the adjustment. */
31079 altivec_expand_vec_perm_le (rtx operands[4])
31081 rtx notx, iorx, unspec;
31082 rtx target = operands[0];
31083 rtx op0 = operands[1];
31084 rtx op1 = operands[2];
31085 rtx sel = operands[3];
31087 rtx norreg = gen_reg_rtx (V16QImode);
31088 machine_mode mode = GET_MODE (target);
31090 /* Get everything in regs so the pattern matches. */
31092 op0 = force_reg (mode, op0);
31094 op1 = force_reg (mode, op1);
31096 sel = force_reg (V16QImode, sel);
31097 if (!REG_P (target))
31098 tmp = gen_reg_rtx (mode);
31100 /* Invert the selector with a VNAND if available, else a VNOR.
31101 The VNAND is preferred for future fusion opportunities. */
31102 notx = gen_rtx_NOT (V16QImode, sel);
31103 iorx = (TARGET_P8_VECTOR
31104 ? gen_rtx_IOR (V16QImode, notx, notx)
31105 : gen_rtx_AND (V16QImode, notx, notx));
31106 emit_insn (gen_rtx_SET (VOIDmode, norreg, iorx));
31108 /* Permute with operands reversed and adjusted selector. */
31109 unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg),
31112 /* Copy into target, possibly by way of a register. */
31113 if (!REG_P (target))
31115 emit_move_insn (tmp, unspec);
31119 emit_move_insn (target, unspec);
31122 /* Expand an Altivec constant permutation. Return true if we match
31123 an efficient implementation; false to fall back to VPERM. */
31126 altivec_expand_vec_perm_const (rtx operands[4])
31128 struct altivec_perm_insn {
31129 HOST_WIDE_INT mask;
31130 enum insn_code impl;
31131 unsigned char perm[16];
31133 static const struct altivec_perm_insn patterns[] = {
31134 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct,
31135 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
31136 { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct,
31137 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
31138 { OPTION_MASK_ALTIVEC,
31139 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct
31140 : CODE_FOR_altivec_vmrglb_direct),
31141 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
31142 { OPTION_MASK_ALTIVEC,
31143 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct
31144 : CODE_FOR_altivec_vmrglh_direct),
31145 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
31146 { OPTION_MASK_ALTIVEC,
31147 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct
31148 : CODE_FOR_altivec_vmrglw_direct),
31149 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
31150 { OPTION_MASK_ALTIVEC,
31151 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct
31152 : CODE_FOR_altivec_vmrghb_direct),
31153 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
31154 { OPTION_MASK_ALTIVEC,
31155 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct
31156 : CODE_FOR_altivec_vmrghh_direct),
31157 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
31158 { OPTION_MASK_ALTIVEC,
31159 (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct
31160 : CODE_FOR_altivec_vmrghw_direct),
31161 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
31162 { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgew,
31163 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
31164 { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgow,
31165 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
31168 unsigned int i, j, elt, which;
31169 unsigned char perm[16];
31170 rtx target, op0, op1, sel, x;
31173 target = operands[0];
31178 /* Unpack the constant selector. */
31179 for (i = which = 0; i < 16; ++i)
31181 rtx e = XVECEXP (sel, 0, i);
31182 elt = INTVAL (e) & 31;
31183 which |= (elt < 16 ? 1 : 2);
31187 /* Simplify the constant selector based on operands. */
31191 gcc_unreachable ();
31195 if (!rtx_equal_p (op0, op1))
31200 for (i = 0; i < 16; ++i)
31212 /* Look for splat patterns. */
31217 for (i = 0; i < 16; ++i)
31218 if (perm[i] != elt)
31222 if (!BYTES_BIG_ENDIAN)
31224 emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt)));
31230 for (i = 0; i < 16; i += 2)
31231 if (perm[i] != elt || perm[i + 1] != elt + 1)
31235 int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2;
31236 x = gen_reg_rtx (V8HImode);
31237 emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0),
31239 emit_move_insn (target, gen_lowpart (V16QImode, x));
31246 for (i = 0; i < 16; i += 4)
31248 || perm[i + 1] != elt + 1
31249 || perm[i + 2] != elt + 2
31250 || perm[i + 3] != elt + 3)
31254 int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4;
31255 x = gen_reg_rtx (V4SImode);
31256 emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0),
31258 emit_move_insn (target, gen_lowpart (V16QImode, x));
31264 /* Look for merge and pack patterns. */
31265 for (j = 0; j < ARRAY_SIZE (patterns); ++j)
31269 if ((patterns[j].mask & rs6000_isa_flags) == 0)
31272 elt = patterns[j].perm[0];
31273 if (perm[0] == elt)
31275 else if (perm[0] == elt + 16)
31279 for (i = 1; i < 16; ++i)
31281 elt = patterns[j].perm[i];
31283 elt = (elt >= 16 ? elt - 16 : elt + 16);
31284 else if (one_vec && elt >= 16)
31286 if (perm[i] != elt)
31291 enum insn_code icode = patterns[j].impl;
31292 machine_mode omode = insn_data[icode].operand[0].mode;
31293 machine_mode imode = insn_data[icode].operand[1].mode;
31295 /* For little-endian, don't use vpkuwum and vpkuhum if the
31296 underlying vector type is not V4SI and V8HI, respectively.
31297 For example, using vpkuwum with a V8HI picks up the even
31298 halfwords (BE numbering) when the even halfwords (LE
31299 numbering) are what we need. */
31300 if (!BYTES_BIG_ENDIAN
31301 && icode == CODE_FOR_altivec_vpkuwum_direct
31302 && ((GET_CODE (op0) == REG
31303 && GET_MODE (op0) != V4SImode)
31304 || (GET_CODE (op0) == SUBREG
31305 && GET_MODE (XEXP (op0, 0)) != V4SImode)))
31307 if (!BYTES_BIG_ENDIAN
31308 && icode == CODE_FOR_altivec_vpkuhum_direct
31309 && ((GET_CODE (op0) == REG
31310 && GET_MODE (op0) != V8HImode)
31311 || (GET_CODE (op0) == SUBREG
31312 && GET_MODE (XEXP (op0, 0)) != V8HImode)))
31315 /* For little-endian, the two input operands must be swapped
31316 (or swapped back) to ensure proper right-to-left numbering
31318 if (swapped ^ !BYTES_BIG_ENDIAN)
31319 std::swap (op0, op1);
31320 if (imode != V16QImode)
31322 op0 = gen_lowpart (imode, op0);
31323 op1 = gen_lowpart (imode, op1);
31325 if (omode == V16QImode)
31328 x = gen_reg_rtx (omode);
31329 emit_insn (GEN_FCN (icode) (x, op0, op1));
31330 if (omode != V16QImode)
31331 emit_move_insn (target, gen_lowpart (V16QImode, x));
31336 if (!BYTES_BIG_ENDIAN)
31338 altivec_expand_vec_perm_const_le (operands);
31345 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
31346 Return true if we match an efficient implementation. */
31349 rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1,
31350 unsigned char perm0, unsigned char perm1)
31354 /* If both selectors come from the same operand, fold to single op. */
31355 if ((perm0 & 2) == (perm1 & 2))
31362 /* If both operands are equal, fold to simpler permutation. */
31363 if (rtx_equal_p (op0, op1))
31366 perm1 = (perm1 & 1) + 2;
31368 /* If the first selector comes from the second operand, swap. */
31369 else if (perm0 & 2)
31375 std::swap (op0, op1);
31377 /* If the second selector does not come from the second operand, fail. */
31378 else if ((perm1 & 2) == 0)
31382 if (target != NULL)
31384 machine_mode vmode, dmode;
31387 vmode = GET_MODE (target);
31388 gcc_assert (GET_MODE_NUNITS (vmode) == 2);
31389 dmode = mode_for_vector (GET_MODE_INNER (vmode), 4);
31390 x = gen_rtx_VEC_CONCAT (dmode, op0, op1);
31391 v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1));
31392 x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v));
31393 emit_insn (gen_rtx_SET (VOIDmode, target, x));
31399 rs6000_expand_vec_perm_const (rtx operands[4])
31401 rtx target, op0, op1, sel;
31402 unsigned char perm0, perm1;
31404 target = operands[0];
31409 /* Unpack the constant selector. */
31410 perm0 = INTVAL (XVECEXP (sel, 0, 0)) & 3;
31411 perm1 = INTVAL (XVECEXP (sel, 0, 1)) & 3;
31413 return rs6000_expand_vec_perm_const_1 (target, op0, op1, perm0, perm1);
31416 /* Test whether a constant permutation is supported. */
31419 rs6000_vectorize_vec_perm_const_ok (machine_mode vmode,
31420 const unsigned char *sel)
31422 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
31423 if (TARGET_ALTIVEC)
31426 /* Check for ps_merge* or evmerge* insns. */
31427 if ((TARGET_PAIRED_FLOAT && vmode == V2SFmode)
31428 || (TARGET_SPE && vmode == V2SImode))
31430 rtx op0 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 1);
31431 rtx op1 = gen_raw_REG (vmode, LAST_VIRTUAL_REGISTER + 2);
31432 return rs6000_expand_vec_perm_const_1 (NULL, op0, op1, sel[0], sel[1]);
31438 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
31441 rs6000_do_expand_vec_perm (rtx target, rtx op0, rtx op1,
31442 machine_mode vmode, unsigned nelt, rtx perm[])
31444 machine_mode imode;
31448 if (GET_MODE_CLASS (vmode) != MODE_VECTOR_INT)
31450 imode = GET_MODE_INNER (vmode);
31451 imode = mode_for_size (GET_MODE_BITSIZE (imode), MODE_INT, 0);
31452 imode = mode_for_vector (imode, nelt);
31455 x = gen_rtx_CONST_VECTOR (imode, gen_rtvec_v (nelt, perm));
31456 x = expand_vec_perm (vmode, op0, op1, x, target);
31458 emit_move_insn (target, x);
31461 /* Expand an extract even operation. */
31464 rs6000_expand_extract_even (rtx target, rtx op0, rtx op1)
31466 machine_mode vmode = GET_MODE (target);
31467 unsigned i, nelt = GET_MODE_NUNITS (vmode);
31470 for (i = 0; i < nelt; i++)
31471 perm[i] = GEN_INT (i * 2);
31473 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
31476 /* Expand a vector interleave operation. */
31479 rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp)
31481 machine_mode vmode = GET_MODE (target);
31482 unsigned i, high, nelt = GET_MODE_NUNITS (vmode);
31485 high = (highp ? 0 : nelt / 2);
31486 for (i = 0; i < nelt / 2; i++)
31488 perm[i * 2] = GEN_INT (i + high);
31489 perm[i * 2 + 1] = GEN_INT (i + nelt + high);
31492 rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm);
31495 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
31497 rs6000_scale_v2df (rtx tgt, rtx src, int scale)
31499 HOST_WIDE_INT hwi_scale (scale);
31500 REAL_VALUE_TYPE r_pow;
31501 rtvec v = rtvec_alloc (2);
31503 rtx scale_vec = gen_reg_rtx (V2DFmode);
31504 (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale);
31505 elt = CONST_DOUBLE_FROM_REAL_VALUE (r_pow, DFmode);
31506 RTVEC_ELT (v, 0) = elt;
31507 RTVEC_ELT (v, 1) = elt;
31508 rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v));
31509 emit_insn (gen_mulv2df3 (tgt, src, scale_vec));
31512 /* Return an RTX representing where to find the function value of a
31513 function returning MODE. */
31515 rs6000_complex_function_value (machine_mode mode)
31517 unsigned int regno;
31519 machine_mode inner = GET_MODE_INNER (mode);
31520 unsigned int inner_bytes = GET_MODE_SIZE (inner);
31522 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
31523 regno = FP_ARG_RETURN;
31526 regno = GP_ARG_RETURN;
31528 /* 32-bit is OK since it'll go in r3/r4. */
31529 if (TARGET_32BIT && inner_bytes >= 4)
31530 return gen_rtx_REG (mode, regno);
31533 if (inner_bytes >= 8)
31534 return gen_rtx_REG (mode, regno);
31536 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
31538 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
31539 GEN_INT (inner_bytes));
31540 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
31543 /* Target hook for TARGET_FUNCTION_VALUE.
31545 On the SPE, both FPs and vectors are returned in r3.
31547 On RS/6000 an integer value is in r3 and a floating-point value is in
31548 fp1, unless -msoft-float. */
31551 rs6000_function_value (const_tree valtype,
31552 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
31553 bool outgoing ATTRIBUTE_UNUSED)
31556 unsigned int regno;
31557 machine_mode elt_mode;
31560 /* Special handling for structs in darwin64. */
31562 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype), valtype))
31564 CUMULATIVE_ARGS valcum;
31568 valcum.fregno = FP_ARG_MIN_REG;
31569 valcum.vregno = ALTIVEC_ARG_MIN_REG;
31570 /* Do a trial code generation as if this were going to be passed as
31571 an argument; if any part goes in memory, we return NULL. */
31572 valret = rs6000_darwin64_record_arg (&valcum, valtype, true, /* retval= */ true);
31575 /* Otherwise fall through to standard ABI rules. */
31578 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
31579 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (valtype), valtype,
31580 &elt_mode, &n_elts))
31582 int first_reg, n_regs, i;
31585 if (SCALAR_FLOAT_MODE_P (elt_mode))
31587 /* _Decimal128 must use even/odd register pairs. */
31588 first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
31589 n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3;
31593 first_reg = ALTIVEC_ARG_RETURN;
31597 par = gen_rtx_PARALLEL (TYPE_MODE (valtype), rtvec_alloc (n_elts));
31598 for (i = 0; i < n_elts; i++)
31600 rtx r = gen_rtx_REG (elt_mode, first_reg + i * n_regs);
31601 rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode));
31602 XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off);
31608 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
31610 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
31611 return gen_rtx_PARALLEL (DImode,
31613 gen_rtx_EXPR_LIST (VOIDmode,
31614 gen_rtx_REG (SImode, GP_ARG_RETURN),
31616 gen_rtx_EXPR_LIST (VOIDmode,
31617 gen_rtx_REG (SImode,
31618 GP_ARG_RETURN + 1),
31621 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
31623 return gen_rtx_PARALLEL (DCmode,
31625 gen_rtx_EXPR_LIST (VOIDmode,
31626 gen_rtx_REG (SImode, GP_ARG_RETURN),
31628 gen_rtx_EXPR_LIST (VOIDmode,
31629 gen_rtx_REG (SImode,
31630 GP_ARG_RETURN + 1),
31632 gen_rtx_EXPR_LIST (VOIDmode,
31633 gen_rtx_REG (SImode,
31634 GP_ARG_RETURN + 2),
31636 gen_rtx_EXPR_LIST (VOIDmode,
31637 gen_rtx_REG (SImode,
31638 GP_ARG_RETURN + 3),
31642 mode = TYPE_MODE (valtype);
31643 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
31644 || POINTER_TYPE_P (valtype))
31645 mode = TARGET_32BIT ? SImode : DImode;
31647 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
31648 /* _Decimal128 must use an even/odd register pair. */
31649 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
31650 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS
31651 && ((TARGET_SINGLE_FLOAT && (mode == SFmode)) || TARGET_DOUBLE_FLOAT))
31652 regno = FP_ARG_RETURN;
31653 else if (TREE_CODE (valtype) == COMPLEX_TYPE
31654 && targetm.calls.split_complex_arg)
31655 return rs6000_complex_function_value (mode);
31656 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
31657 return register is used in both cases, and we won't see V2DImode/V2DFmode
31658 for pure altivec, combine the two cases. */
31659 else if (TREE_CODE (valtype) == VECTOR_TYPE
31660 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
31661 && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
31662 regno = ALTIVEC_ARG_RETURN;
31663 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
31664 && (mode == DFmode || mode == DCmode
31665 || mode == TFmode || mode == TCmode))
31666 return spe_build_register_parallel (mode, GP_ARG_RETURN);
31668 regno = GP_ARG_RETURN;
31670 return gen_rtx_REG (mode, regno);
31673 /* Define how to find the value returned by a library function
31674 assuming the value has mode MODE. */
31676 rs6000_libcall_value (machine_mode mode)
31678 unsigned int regno;
31680 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
31682 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
31683 return gen_rtx_PARALLEL (DImode,
31685 gen_rtx_EXPR_LIST (VOIDmode,
31686 gen_rtx_REG (SImode, GP_ARG_RETURN),
31688 gen_rtx_EXPR_LIST (VOIDmode,
31689 gen_rtx_REG (SImode,
31690 GP_ARG_RETURN + 1),
31694 if (DECIMAL_FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
31695 /* _Decimal128 must use an even/odd register pair. */
31696 regno = (mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN;
31697 else if (SCALAR_FLOAT_MODE_P (mode)
31698 && TARGET_HARD_FLOAT && TARGET_FPRS
31699 && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
31700 regno = FP_ARG_RETURN;
31701 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
31702 return register is used in both cases, and we won't see V2DImode/V2DFmode
31703 for pure altivec, combine the two cases. */
31704 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
31705 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
31706 regno = ALTIVEC_ARG_RETURN;
31707 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
31708 return rs6000_complex_function_value (mode);
31709 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
31710 && (mode == DFmode || mode == DCmode
31711 || mode == TFmode || mode == TCmode))
31712 return spe_build_register_parallel (mode, GP_ARG_RETURN);
31714 regno = GP_ARG_RETURN;
31716 return gen_rtx_REG (mode, regno);
31720 /* Return true if we use LRA instead of reload pass. */
31722 rs6000_lra_p (void)
31724 return rs6000_lra_flag;
31727 /* Given FROM and TO register numbers, say whether this elimination is allowed.
31728 Frame pointer elimination is automatically handled.
31730 For the RS/6000, if frame pointer elimination is being done, we would like
31731 to convert ap into fp, not sp.
31733 We need r30 if -mminimal-toc was specified, and there are constant pool
31737 rs6000_can_eliminate (const int from, const int to)
31739 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM
31740 ? ! frame_pointer_needed
31741 : from == RS6000_PIC_OFFSET_TABLE_REGNUM
31742 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0
31746 /* Define the offset between two registers, FROM to be eliminated and its
31747 replacement TO, at the start of a routine. */
31749 rs6000_initial_elimination_offset (int from, int to)
31751 rs6000_stack_t *info = rs6000_stack_info ();
31752 HOST_WIDE_INT offset;
31754 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
31755 offset = info->push_p ? 0 : -info->total_size;
31756 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
31758 offset = info->push_p ? 0 : -info->total_size;
31759 if (FRAME_GROWS_DOWNWARD)
31760 offset += info->fixed_size + info->vars_size + info->parm_size;
31762 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
31763 offset = FRAME_GROWS_DOWNWARD
31764 ? info->fixed_size + info->vars_size + info->parm_size
31766 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
31767 offset = info->total_size;
31768 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
31769 offset = info->push_p ? info->total_size : 0;
31770 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
31773 gcc_unreachable ();
31779 rs6000_dwarf_register_span (rtx reg)
31783 unsigned regno = REGNO (reg);
31784 machine_mode mode = GET_MODE (reg);
31788 && (SPE_VECTOR_MODE (GET_MODE (reg))
31789 || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
31790 && mode != SFmode && mode != SDmode && mode != SCmode)))
31795 regno = REGNO (reg);
31797 /* The duality of the SPE register size wreaks all kinds of havoc.
31798 This is a way of distinguishing r0 in 32-bits from r0 in
31800 words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
31801 gcc_assert (words <= 4);
31802 for (i = 0; i < words; i++, regno++)
31804 if (BYTES_BIG_ENDIAN)
31806 parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
31807 parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
31811 parts[2 * i] = gen_rtx_REG (SImode, regno);
31812 parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO);
31816 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
31819 /* Fill in sizes for SPE register high parts in table used by unwinder. */
31822 rs6000_init_dwarf_reg_sizes_extra (tree address)
31827 machine_mode mode = TYPE_MODE (char_type_node);
31828 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
31829 rtx mem = gen_rtx_MEM (BLKmode, addr);
31830 rtx value = gen_int_mode (4, mode);
31832 for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++)
31834 int column = DWARF_REG_TO_UNWIND_COLUMN
31835 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
31836 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
31838 emit_move_insn (adjust_address (mem, mode, offset), value);
31842 if (TARGET_MACHO && ! TARGET_ALTIVEC)
31845 machine_mode mode = TYPE_MODE (char_type_node);
31846 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, EXPAND_NORMAL);
31847 rtx mem = gen_rtx_MEM (BLKmode, addr);
31848 rtx value = gen_int_mode (16, mode);
31850 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
31851 The unwinder still needs to know the size of Altivec registers. */
31853 for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++)
31855 int column = DWARF_REG_TO_UNWIND_COLUMN
31856 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true));
31857 HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode);
31859 emit_move_insn (adjust_address (mem, mode, offset), value);
31864 /* Map internal gcc register numbers to debug format register numbers.
31865 FORMAT specifies the type of debug register number to use:
31866 0 -- debug information, except for frame-related sections
31867 1 -- DWARF .debug_frame section
31868 2 -- DWARF .eh_frame section */
31871 rs6000_dbx_register_number (unsigned int regno, unsigned int format)
31873 /* We never use the GCC internal number for SPE high registers.
31874 Those are mapped to the 1200..1231 range for all debug formats. */
31875 if (SPE_HIGH_REGNO_P (regno))
31876 return regno - FIRST_SPE_HIGH_REGNO + 1200;
31878 /* Except for the above, we use the internal number for non-DWARF
31879 debug information, and also for .eh_frame. */
31880 if ((format == 0 && write_symbols != DWARF2_DEBUG) || format == 2)
31883 /* On some platforms, we use the standard DWARF register
31884 numbering for .debug_info and .debug_frame. */
31885 #ifdef RS6000_USE_DWARF_NUMBERING
31888 if (regno == LR_REGNO)
31890 if (regno == CTR_REGNO)
31892 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
31893 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
31894 The actual code emitted saves the whole of CR, so we map CR2_REGNO
31895 to the DWARF reg for CR. */
31896 if (format == 1 && regno == CR2_REGNO)
31898 if (CR_REGNO_P (regno))
31899 return regno - CR0_REGNO + 86;
31900 if (regno == CA_REGNO)
31901 return 101; /* XER */
31902 if (ALTIVEC_REGNO_P (regno))
31903 return regno - FIRST_ALTIVEC_REGNO + 1124;
31904 if (regno == VRSAVE_REGNO)
31906 if (regno == VSCR_REGNO)
31908 if (regno == SPE_ACC_REGNO)
31910 if (regno == SPEFSCR_REGNO)
31916 /* target hook eh_return_filter_mode */
31917 static machine_mode
31918 rs6000_eh_return_filter_mode (void)
31920 return TARGET_32BIT ? SImode : word_mode;
31923 /* Target hook for scalar_mode_supported_p. */
31925 rs6000_scalar_mode_supported_p (machine_mode mode)
31927 if (DECIMAL_FLOAT_MODE_P (mode))
31928 return default_decimal_float_supported_p ();
31930 return default_scalar_mode_supported_p (mode);
31933 /* Target hook for vector_mode_supported_p. */
31935 rs6000_vector_mode_supported_p (machine_mode mode)
31938 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
31941 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
31944 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
31951 /* Target hook for invalid_arg_for_unprototyped_fn. */
31952 static const char *
31953 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
31955 return (!rs6000_darwin64_abi
31957 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
31958 && (funcdecl == NULL_TREE
31959 || (TREE_CODE (funcdecl) == FUNCTION_DECL
31960 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
31961 ? N_("AltiVec argument passed to unprototyped function")
31965 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
31966 setup by using __stack_chk_fail_local hidden function instead of
31967 calling __stack_chk_fail directly. Otherwise it is better to call
31968 __stack_chk_fail directly. */
31970 static tree ATTRIBUTE_UNUSED
31971 rs6000_stack_protect_fail (void)
31973 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
31974 ? default_hidden_stack_protect_fail ()
31975 : default_external_stack_protect_fail ();
31979 rs6000_final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
31980 int num_operands ATTRIBUTE_UNUSED)
31982 if (rs6000_warn_cell_microcode)
31985 int insn_code_number = recog_memoized (insn);
31986 location_t location = INSN_LOCATION (insn);
31988 /* Punt on insns we cannot recognize. */
31989 if (insn_code_number < 0)
31992 temp = get_insn_template (insn_code_number, insn);
31994 if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
31995 warning_at (location, OPT_mwarn_cell_microcode,
31996 "emitting microcode insn %s\t[%s] #%d",
31997 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
31998 else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
31999 warning_at (location, OPT_mwarn_cell_microcode,
32000 "emitting conditional microcode insn %s\t[%s] #%d",
32001 temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
32005 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
32008 static unsigned HOST_WIDE_INT
32009 rs6000_asan_shadow_offset (void)
32011 return (unsigned HOST_WIDE_INT) 1 << (TARGET_64BIT ? 41 : 29);
32015 /* Mask options that we want to support inside of attribute((target)) and
32016 #pragma GCC target operations. Note, we do not include things like
32017 64/32-bit, endianess, hard/soft floating point, etc. that would have
32018 different calling sequences. */
32020 struct rs6000_opt_mask {
32021 const char *name; /* option name */
32022 HOST_WIDE_INT mask; /* mask to set */
32023 bool invert; /* invert sense of mask */
32024 bool valid_target; /* option is a target option */
32027 static struct rs6000_opt_mask const rs6000_opt_masks[] =
32029 { "altivec", OPTION_MASK_ALTIVEC, false, true },
32030 { "cmpb", OPTION_MASK_CMPB, false, true },
32031 { "crypto", OPTION_MASK_CRYPTO, false, true },
32032 { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true },
32033 { "dlmzb", OPTION_MASK_DLMZB, false, true },
32034 { "fprnd", OPTION_MASK_FPRND, false, true },
32035 { "hard-dfp", OPTION_MASK_DFP, false, true },
32036 { "htm", OPTION_MASK_HTM, false, true },
32037 { "isel", OPTION_MASK_ISEL, false, true },
32038 { "mfcrf", OPTION_MASK_MFCRF, false, true },
32039 { "mfpgpr", OPTION_MASK_MFPGPR, false, true },
32040 { "mulhw", OPTION_MASK_MULHW, false, true },
32041 { "multiple", OPTION_MASK_MULTIPLE, false, true },
32042 { "popcntb", OPTION_MASK_POPCNTB, false, true },
32043 { "popcntd", OPTION_MASK_POPCNTD, false, true },
32044 { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
32045 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
32046 { "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
32047 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true },
32048 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true },
32049 { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true },
32050 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true },
32051 { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
32052 { "string", OPTION_MASK_STRING, false, true },
32053 { "update", OPTION_MASK_NO_UPDATE, true , true },
32054 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF, false, false },
32055 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF, false, false },
32056 { "vsx", OPTION_MASK_VSX, false, true },
32057 { "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true },
32058 #ifdef OPTION_MASK_64BIT
32060 { "aix64", OPTION_MASK_64BIT, false, false },
32061 { "aix32", OPTION_MASK_64BIT, true, false },
32063 { "64", OPTION_MASK_64BIT, false, false },
32064 { "32", OPTION_MASK_64BIT, true, false },
32067 #ifdef OPTION_MASK_EABI
32068 { "eabi", OPTION_MASK_EABI, false, false },
32070 #ifdef OPTION_MASK_LITTLE_ENDIAN
32071 { "little", OPTION_MASK_LITTLE_ENDIAN, false, false },
32072 { "big", OPTION_MASK_LITTLE_ENDIAN, true, false },
32074 #ifdef OPTION_MASK_RELOCATABLE
32075 { "relocatable", OPTION_MASK_RELOCATABLE, false, false },
32077 #ifdef OPTION_MASK_STRICT_ALIGN
32078 { "strict-align", OPTION_MASK_STRICT_ALIGN, false, false },
32080 { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
32081 { "string", OPTION_MASK_STRING, false, false },
32084 /* Builtin mask mapping for printing the flags. */
32085 static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
32087 { "altivec", RS6000_BTM_ALTIVEC, false, false },
32088 { "vsx", RS6000_BTM_VSX, false, false },
32089 { "spe", RS6000_BTM_SPE, false, false },
32090 { "paired", RS6000_BTM_PAIRED, false, false },
32091 { "fre", RS6000_BTM_FRE, false, false },
32092 { "fres", RS6000_BTM_FRES, false, false },
32093 { "frsqrte", RS6000_BTM_FRSQRTE, false, false },
32094 { "frsqrtes", RS6000_BTM_FRSQRTES, false, false },
32095 { "popcntd", RS6000_BTM_POPCNTD, false, false },
32096 { "cell", RS6000_BTM_CELL, false, false },
32097 { "power8-vector", RS6000_BTM_P8_VECTOR, false, false },
32098 { "crypto", RS6000_BTM_CRYPTO, false, false },
32099 { "htm", RS6000_BTM_HTM, false, false },
32100 { "hard-dfp", RS6000_BTM_DFP, false, false },
32101 { "hard-float", RS6000_BTM_HARD_FLOAT, false, false },
32102 { "long-double-128", RS6000_BTM_LDBL128, false, false },
32105 /* Option variables that we want to support inside attribute((target)) and
32106 #pragma GCC target operations. */
32108 struct rs6000_opt_var {
32109 const char *name; /* option name */
32110 size_t global_offset; /* offset of the option in global_options. */
32111 size_t target_offset; /* offset of the option in target optiosn. */
32114 static struct rs6000_opt_var const rs6000_opt_vars[] =
32117 offsetof (struct gcc_options, x_TARGET_FRIZ),
32118 offsetof (struct cl_target_option, x_TARGET_FRIZ), },
32119 { "avoid-indexed-addresses",
32120 offsetof (struct gcc_options, x_TARGET_AVOID_XFORM),
32121 offsetof (struct cl_target_option, x_TARGET_AVOID_XFORM) },
32123 offsetof (struct gcc_options, x_rs6000_paired_float),
32124 offsetof (struct cl_target_option, x_rs6000_paired_float), },
32126 offsetof (struct gcc_options, x_rs6000_default_long_calls),
32127 offsetof (struct cl_target_option, x_rs6000_default_long_calls), },
32130 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
32131 parsing. Return true if there were no errors. */
32134 rs6000_inner_target_options (tree args, bool attr_p)
32138 if (args == NULL_TREE)
32141 else if (TREE_CODE (args) == STRING_CST)
32143 char *p = ASTRDUP (TREE_STRING_POINTER (args));
32146 while ((q = strtok (p, ",")) != NULL)
32148 bool error_p = false;
32149 bool not_valid_p = false;
32150 const char *cpu_opt = NULL;
32153 if (strncmp (q, "cpu=", 4) == 0)
32155 int cpu_index = rs6000_cpu_name_lookup (q+4);
32156 if (cpu_index >= 0)
32157 rs6000_cpu_index = cpu_index;
32164 else if (strncmp (q, "tune=", 5) == 0)
32166 int tune_index = rs6000_cpu_name_lookup (q+5);
32167 if (tune_index >= 0)
32168 rs6000_tune_index = tune_index;
32178 bool invert = false;
32182 if (strncmp (r, "no-", 3) == 0)
32188 for (i = 0; i < ARRAY_SIZE (rs6000_opt_masks); i++)
32189 if (strcmp (r, rs6000_opt_masks[i].name) == 0)
32191 HOST_WIDE_INT mask = rs6000_opt_masks[i].mask;
32193 if (!rs6000_opt_masks[i].valid_target)
32194 not_valid_p = true;
32198 rs6000_isa_flags_explicit |= mask;
32200 /* VSX needs altivec, so -mvsx automagically sets
32202 if (mask == OPTION_MASK_VSX && !invert)
32203 mask |= OPTION_MASK_ALTIVEC;
32205 if (rs6000_opt_masks[i].invert)
32209 rs6000_isa_flags &= ~mask;
32211 rs6000_isa_flags |= mask;
32216 if (error_p && !not_valid_p)
32218 for (i = 0; i < ARRAY_SIZE (rs6000_opt_vars); i++)
32219 if (strcmp (r, rs6000_opt_vars[i].name) == 0)
32221 size_t j = rs6000_opt_vars[i].global_offset;
32222 *((int *) ((char *)&global_options + j)) = !invert;
32231 const char *eprefix, *esuffix;
32236 eprefix = "__attribute__((__target__(";
32241 eprefix = "#pragma GCC target ";
32246 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt, eprefix,
32248 else if (not_valid_p)
32249 error ("%s\"%s\"%s is not allowed", eprefix, q, esuffix);
32251 error ("%s\"%s\"%s is invalid", eprefix, q, esuffix);
32256 else if (TREE_CODE (args) == TREE_LIST)
32260 tree value = TREE_VALUE (args);
32263 bool ret2 = rs6000_inner_target_options (value, attr_p);
32267 args = TREE_CHAIN (args);
32269 while (args != NULL_TREE);
32273 gcc_unreachable ();
32278 /* Print out the target options as a list for -mdebug=target. */
32281 rs6000_debug_target_options (tree args, const char *prefix)
32283 if (args == NULL_TREE)
32284 fprintf (stderr, "%s<NULL>", prefix);
32286 else if (TREE_CODE (args) == STRING_CST)
32288 char *p = ASTRDUP (TREE_STRING_POINTER (args));
32291 while ((q = strtok (p, ",")) != NULL)
32294 fprintf (stderr, "%s\"%s\"", prefix, q);
32299 else if (TREE_CODE (args) == TREE_LIST)
32303 tree value = TREE_VALUE (args);
32306 rs6000_debug_target_options (value, prefix);
32309 args = TREE_CHAIN (args);
32311 while (args != NULL_TREE);
32315 gcc_unreachable ();
32321 /* Hook to validate attribute((target("..."))). */
32324 rs6000_valid_attribute_p (tree fndecl,
32325 tree ARG_UNUSED (name),
32329 struct cl_target_option cur_target;
32331 tree old_optimize = build_optimization_node (&global_options);
32332 tree new_target, new_optimize;
32333 tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
32335 gcc_assert ((fndecl != NULL_TREE) && (args != NULL_TREE));
32337 if (TARGET_DEBUG_TARGET)
32339 tree tname = DECL_NAME (fndecl);
32340 fprintf (stderr, "\n==================== rs6000_valid_attribute_p:\n");
32342 fprintf (stderr, "function: %.*s\n",
32343 (int) IDENTIFIER_LENGTH (tname),
32344 IDENTIFIER_POINTER (tname));
32346 fprintf (stderr, "function: unknown\n");
32348 fprintf (stderr, "args:");
32349 rs6000_debug_target_options (args, " ");
32350 fprintf (stderr, "\n");
32353 fprintf (stderr, "flags: 0x%x\n", flags);
32355 fprintf (stderr, "--------------------\n");
32358 old_optimize = build_optimization_node (&global_options);
32359 func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl);
32361 /* If the function changed the optimization levels as well as setting target
32362 options, start with the optimizations specified. */
32363 if (func_optimize && func_optimize != old_optimize)
32364 cl_optimization_restore (&global_options,
32365 TREE_OPTIMIZATION (func_optimize));
32367 /* The target attributes may also change some optimization flags, so update
32368 the optimization options if necessary. */
32369 cl_target_option_save (&cur_target, &global_options);
32370 rs6000_cpu_index = rs6000_tune_index = -1;
32371 ret = rs6000_inner_target_options (args, true);
32373 /* Set up any additional state. */
32376 ret = rs6000_option_override_internal (false);
32377 new_target = build_target_option_node (&global_options);
32382 new_optimize = build_optimization_node (&global_options);
32389 DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target;
32391 if (old_optimize != new_optimize)
32392 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize;
32395 cl_target_option_restore (&global_options, &cur_target);
32397 if (old_optimize != new_optimize)
32398 cl_optimization_restore (&global_options,
32399 TREE_OPTIMIZATION (old_optimize));
32405 /* Hook to validate the current #pragma GCC target and set the state, and
32406 update the macros based on what was changed. If ARGS is NULL, then
32407 POP_TARGET is used to reset the options. */
32410 rs6000_pragma_target_parse (tree args, tree pop_target)
32412 tree prev_tree = build_target_option_node (&global_options);
32414 struct cl_target_option *prev_opt, *cur_opt;
32415 HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
32416 HOST_WIDE_INT prev_bumask, cur_bumask, diff_bumask;
32418 if (TARGET_DEBUG_TARGET)
32420 fprintf (stderr, "\n==================== rs6000_pragma_target_parse\n");
32421 fprintf (stderr, "args:");
32422 rs6000_debug_target_options (args, " ");
32423 fprintf (stderr, "\n");
32427 fprintf (stderr, "pop_target:\n");
32428 debug_tree (pop_target);
32431 fprintf (stderr, "pop_target: <NULL>\n");
32433 fprintf (stderr, "--------------------\n");
32438 cur_tree = ((pop_target)
32440 : target_option_default_node);
32441 cl_target_option_restore (&global_options,
32442 TREE_TARGET_OPTION (cur_tree));
32446 rs6000_cpu_index = rs6000_tune_index = -1;
32447 if (!rs6000_inner_target_options (args, false)
32448 || !rs6000_option_override_internal (false)
32449 || (cur_tree = build_target_option_node (&global_options))
32452 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
32453 fprintf (stderr, "invalid pragma\n");
32459 target_option_current_node = cur_tree;
32461 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
32462 change the macros that are defined. */
32463 if (rs6000_target_modify_macros_ptr)
32465 prev_opt = TREE_TARGET_OPTION (prev_tree);
32466 prev_bumask = prev_opt->x_rs6000_builtin_mask;
32467 prev_flags = prev_opt->x_rs6000_isa_flags;
32469 cur_opt = TREE_TARGET_OPTION (cur_tree);
32470 cur_flags = cur_opt->x_rs6000_isa_flags;
32471 cur_bumask = cur_opt->x_rs6000_builtin_mask;
32473 diff_bumask = (prev_bumask ^ cur_bumask);
32474 diff_flags = (prev_flags ^ cur_flags);
32476 if ((diff_flags != 0) || (diff_bumask != 0))
32478 /* Delete old macros. */
32479 rs6000_target_modify_macros_ptr (false,
32480 prev_flags & diff_flags,
32481 prev_bumask & diff_bumask);
32483 /* Define new macros. */
32484 rs6000_target_modify_macros_ptr (true,
32485 cur_flags & diff_flags,
32486 cur_bumask & diff_bumask);
32494 /* Remember the last target of rs6000_set_current_function. */
32495 static GTY(()) tree rs6000_previous_fndecl;
32497 /* Establish appropriate back-end context for processing the function
32498 FNDECL. The argument might be NULL to indicate processing at top
32499 level, outside of any function scope. */
32501 rs6000_set_current_function (tree fndecl)
32503 tree old_tree = (rs6000_previous_fndecl
32504 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl)
32507 tree new_tree = (fndecl
32508 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl)
32511 if (TARGET_DEBUG_TARGET)
32513 bool print_final = false;
32514 fprintf (stderr, "\n==================== rs6000_set_current_function");
32517 fprintf (stderr, ", fndecl %s (%p)",
32518 (DECL_NAME (fndecl)
32519 ? IDENTIFIER_POINTER (DECL_NAME (fndecl))
32520 : "<unknown>"), (void *)fndecl);
32522 if (rs6000_previous_fndecl)
32523 fprintf (stderr, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl);
32525 fprintf (stderr, "\n");
32528 fprintf (stderr, "\nnew fndecl target specific options:\n");
32529 debug_tree (new_tree);
32530 print_final = true;
32535 fprintf (stderr, "\nold fndecl target specific options:\n");
32536 debug_tree (old_tree);
32537 print_final = true;
32541 fprintf (stderr, "--------------------\n");
32544 /* Only change the context if the function changes. This hook is called
32545 several times in the course of compiling a function, and we don't want to
32546 slow things down too much or call target_reinit when it isn't safe. */
32547 if (fndecl && fndecl != rs6000_previous_fndecl)
32549 rs6000_previous_fndecl = fndecl;
32550 if (old_tree == new_tree)
32555 cl_target_option_restore (&global_options,
32556 TREE_TARGET_OPTION (new_tree));
32557 if (TREE_TARGET_GLOBALS (new_tree))
32558 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
32560 TREE_TARGET_GLOBALS (new_tree)
32561 = save_target_globals_default_opts ();
32566 new_tree = target_option_current_node;
32567 cl_target_option_restore (&global_options,
32568 TREE_TARGET_OPTION (new_tree));
32569 if (TREE_TARGET_GLOBALS (new_tree))
32570 restore_target_globals (TREE_TARGET_GLOBALS (new_tree));
32571 else if (new_tree == target_option_default_node)
32572 restore_target_globals (&default_target_globals);
32574 TREE_TARGET_GLOBALS (new_tree)
32575 = save_target_globals_default_opts ();
32581 /* Save the current options */
32584 rs6000_function_specific_save (struct cl_target_option *ptr,
32585 struct gcc_options *opts)
32587 ptr->x_rs6000_isa_flags = opts->x_rs6000_isa_flags;
32588 ptr->x_rs6000_isa_flags_explicit = opts->x_rs6000_isa_flags_explicit;
32591 /* Restore the current options */
32594 rs6000_function_specific_restore (struct gcc_options *opts,
32595 struct cl_target_option *ptr)
32598 opts->x_rs6000_isa_flags = ptr->x_rs6000_isa_flags;
32599 opts->x_rs6000_isa_flags_explicit = ptr->x_rs6000_isa_flags_explicit;
32600 (void) rs6000_option_override_internal (false);
32603 /* Print the current options */
32606 rs6000_function_specific_print (FILE *file, int indent,
32607 struct cl_target_option *ptr)
32609 rs6000_print_isa_options (file, indent, "Isa options set",
32610 ptr->x_rs6000_isa_flags);
32612 rs6000_print_isa_options (file, indent, "Isa options explicit",
32613 ptr->x_rs6000_isa_flags_explicit);
32616 /* Helper function to print the current isa or misc options on a line. */
32619 rs6000_print_options_internal (FILE *file,
32621 const char *string,
32622 HOST_WIDE_INT flags,
32623 const char *prefix,
32624 const struct rs6000_opt_mask *opts,
32625 size_t num_elements)
32628 size_t start_column = 0;
32630 size_t max_column = 76;
32631 const char *comma = "";
32634 start_column += fprintf (file, "%*s", indent, "");
32638 fprintf (stderr, DEBUG_FMT_S, string, "<none>");
32642 start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
32644 /* Print the various mask options. */
32645 cur_column = start_column;
32646 for (i = 0; i < num_elements; i++)
32648 if ((flags & opts[i].mask) != 0)
32650 const char *no_str = rs6000_opt_masks[i].invert ? "no-" : "";
32651 size_t len = (strlen (comma)
32654 + strlen (rs6000_opt_masks[i].name));
32657 if (cur_column > max_column)
32659 fprintf (stderr, ", \\\n%*s", (int)start_column, "");
32660 cur_column = start_column + len;
32664 fprintf (file, "%s%s%s%s", comma, prefix, no_str,
32665 rs6000_opt_masks[i].name);
32666 flags &= ~ opts[i].mask;
32671 fputs ("\n", file);
32674 /* Helper function to print the current isa options on a line. */
32677 rs6000_print_isa_options (FILE *file, int indent, const char *string,
32678 HOST_WIDE_INT flags)
32680 rs6000_print_options_internal (file, indent, string, flags, "-m",
32681 &rs6000_opt_masks[0],
32682 ARRAY_SIZE (rs6000_opt_masks));
32686 rs6000_print_builtin_options (FILE *file, int indent, const char *string,
32687 HOST_WIDE_INT flags)
32689 rs6000_print_options_internal (file, indent, string, flags, "",
32690 &rs6000_builtin_mask_names[0],
32691 ARRAY_SIZE (rs6000_builtin_mask_names));
32695 /* Hook to determine if one function can safely inline another. */
32698 rs6000_can_inline_p (tree caller, tree callee)
32701 tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
32702 tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
32704 /* If callee has no option attributes, then it is ok to inline. */
32708 /* If caller has no option attributes, but callee does then it is not ok to
32710 else if (!caller_tree)
32715 struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
32716 struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
32718 /* Callee's options should a subset of the caller's, i.e. a vsx function
32719 can inline an altivec function but a non-vsx function can't inline a
32721 if ((caller_opts->x_rs6000_isa_flags & callee_opts->x_rs6000_isa_flags)
32722 == callee_opts->x_rs6000_isa_flags)
32726 if (TARGET_DEBUG_TARGET)
32727 fprintf (stderr, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
32728 (DECL_NAME (caller)
32729 ? IDENTIFIER_POINTER (DECL_NAME (caller))
32731 (DECL_NAME (callee)
32732 ? IDENTIFIER_POINTER (DECL_NAME (callee))
32734 (ret ? "can" : "cannot"));
32739 /* Allocate a stack temp and fixup the address so it meets the particular
32740 memory requirements (either offetable or REG+REG addressing). */
32743 rs6000_allocate_stack_temp (machine_mode mode,
32744 bool offsettable_p,
32747 rtx stack = assign_stack_temp (mode, GET_MODE_SIZE (mode));
32748 rtx addr = XEXP (stack, 0);
32749 int strict_p = (reload_in_progress || reload_completed);
32751 if (!legitimate_indirect_address_p (addr, strict_p))
32754 && !rs6000_legitimate_offset_address_p (mode, addr, strict_p, true))
32755 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
32757 else if (reg_reg_p && !legitimate_indexed_address_p (addr, strict_p))
32758 stack = replace_equiv_address (stack, copy_addr_to_reg (addr));
32764 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
32765 to such a form to deal with memory reference instructions like STFIWX that
32766 only take reg+reg addressing. */
32769 rs6000_address_for_fpconvert (rtx x)
32771 int strict_p = (reload_in_progress || reload_completed);
32774 gcc_assert (MEM_P (x));
32775 addr = XEXP (x, 0);
32776 if (! legitimate_indirect_address_p (addr, strict_p)
32777 && ! legitimate_indexed_address_p (addr, strict_p))
32779 if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
32781 rtx reg = XEXP (addr, 0);
32782 HOST_WIDE_INT size = GET_MODE_SIZE (GET_MODE (x));
32783 rtx size_rtx = GEN_INT ((GET_CODE (addr) == PRE_DEC) ? -size : size);
32784 gcc_assert (REG_P (reg));
32785 emit_insn (gen_add3_insn (reg, reg, size_rtx));
32788 else if (GET_CODE (addr) == PRE_MODIFY)
32790 rtx reg = XEXP (addr, 0);
32791 rtx expr = XEXP (addr, 1);
32792 gcc_assert (REG_P (reg));
32793 gcc_assert (GET_CODE (expr) == PLUS);
32794 emit_insn (gen_add3_insn (reg, XEXP (expr, 0), XEXP (expr, 1)));
32798 x = replace_equiv_address (x, copy_addr_to_reg (addr));
32804 /* Given a memory reference, if it is not in the form for altivec memory
32805 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
32806 convert to the altivec format. */
32809 rs6000_address_for_altivec (rtx x)
32811 gcc_assert (MEM_P (x));
32812 if (!altivec_indexed_or_indirect_operand (x, GET_MODE (x)))
32814 rtx addr = XEXP (x, 0);
32815 int strict_p = (reload_in_progress || reload_completed);
32817 if (!legitimate_indexed_address_p (addr, strict_p)
32818 && !legitimate_indirect_address_p (addr, strict_p))
32819 addr = copy_to_mode_reg (Pmode, addr);
32821 addr = gen_rtx_AND (Pmode, addr, GEN_INT (-16));
32822 x = change_address (x, GET_MODE (x), addr);
32828 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
32830 On the RS/6000, all integer constants are acceptable, most won't be valid
32831 for particular insns, though. Only easy FP constants are acceptable. */
32834 rs6000_legitimate_constant_p (machine_mode mode, rtx x)
32836 if (TARGET_ELF && tls_referenced_p (x))
32839 return ((GET_CODE (x) != CONST_DOUBLE && GET_CODE (x) != CONST_VECTOR)
32840 || GET_MODE (x) == VOIDmode
32841 || (TARGET_POWERPC64 && mode == DImode)
32842 || easy_fp_constant (x, mode)
32843 || easy_vector_constant (x, mode));
32848 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
32851 rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
32853 const bool direct_call_p
32854 = GET_CODE (func_desc) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (func_desc);
32855 rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM);
32856 rtx toc_load = NULL_RTX;
32857 rtx toc_restore = NULL_RTX;
32859 rtx abi_reg = NULL_RTX;
32864 /* Handle longcall attributes. */
32865 if (INTVAL (cookie) & CALL_LONG)
32866 func_desc = rs6000_longcall_ref (func_desc);
32868 /* Handle indirect calls. */
32869 if (GET_CODE (func_desc) != SYMBOL_REF
32870 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc)))
32872 /* Save the TOC into its reserved slot before the call,
32873 and prepare to restore it after the call. */
32874 rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
32875 rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT);
32876 rtx stack_toc_mem = gen_frame_mem (Pmode,
32877 gen_rtx_PLUS (Pmode, stack_ptr,
32878 stack_toc_offset));
32879 toc_restore = gen_rtx_SET (VOIDmode, toc_reg, stack_toc_mem);
32881 /* Can we optimize saving the TOC in the prologue or
32882 do we need to do it at every call? */
32883 if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca)
32884 cfun->machine->save_toc_in_prologue = true;
32887 MEM_VOLATILE_P (stack_toc_mem) = 1;
32888 emit_move_insn (stack_toc_mem, toc_reg);
32891 if (DEFAULT_ABI == ABI_ELFv2)
32893 /* A function pointer in the ELFv2 ABI is just a plain address, but
32894 the ABI requires it to be loaded into r12 before the call. */
32895 func_addr = gen_rtx_REG (Pmode, 12);
32896 emit_move_insn (func_addr, func_desc);
32897 abi_reg = func_addr;
32901 /* A function pointer under AIX is a pointer to a data area whose
32902 first word contains the actual address of the function, whose
32903 second word contains a pointer to its TOC, and whose third word
32904 contains a value to place in the static chain register (r11).
32905 Note that if we load the static chain, our "trampoline" need
32906 not have any executable code. */
32908 /* Load up address of the actual function. */
32909 func_desc = force_reg (Pmode, func_desc);
32910 func_addr = gen_reg_rtx (Pmode);
32911 emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc));
32913 /* Prepare to load the TOC of the called function. Note that the
32914 TOC load must happen immediately before the actual call so
32915 that unwinding the TOC registers works correctly. See the
32916 comment in frob_update_context. */
32917 rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode));
32918 rtx func_toc_mem = gen_rtx_MEM (Pmode,
32919 gen_rtx_PLUS (Pmode, func_desc,
32921 toc_load = gen_rtx_USE (VOIDmode, func_toc_mem);
32923 /* If we have a static chain, load it up. But, if the call was
32924 originally direct, the 3rd word has not been written since no
32925 trampoline has been built, so we ought not to load it, lest we
32926 override a static chain value. */
32927 if (!direct_call_p && TARGET_POINTERS_TO_NESTED_FUNCTIONS)
32929 rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
32930 rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode));
32931 rtx func_sc_mem = gen_rtx_MEM (Pmode,
32932 gen_rtx_PLUS (Pmode, func_desc,
32934 emit_move_insn (sc_reg, func_sc_mem);
32941 /* Direct calls use the TOC: for local calls, the callee will
32942 assume the TOC register is set; for non-local calls, the
32943 PLT stub needs the TOC register. */
32945 func_addr = func_desc;
32948 /* Create the call. */
32949 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag);
32950 if (value != NULL_RTX)
32951 call[0] = gen_rtx_SET (VOIDmode, value, call[0]);
32955 call[n_call++] = toc_load;
32957 call[n_call++] = toc_restore;
32959 call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO));
32961 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call));
32962 insn = emit_call_insn (insn);
32964 /* Mention all registers defined by the ABI to hold information
32965 as uses in CALL_INSN_FUNCTION_USAGE. */
32967 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg);
32970 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
32973 rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie)
32978 gcc_assert (INTVAL (cookie) == 0);
32980 /* Create the call. */
32981 call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag);
32982 if (value != NULL_RTX)
32983 call[0] = gen_rtx_SET (VOIDmode, value, call[0]);
32985 call[1] = simple_return_rtx;
32987 insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call));
32988 insn = emit_call_insn (insn);
32990 /* Note use of the TOC register. */
32991 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM));
32992 /* We need to also mark a use of the link register since the function we
32993 sibling-call to will use it to return to our caller. */
32994 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, LR_REGNO));
32997 /* Return whether we need to always update the saved TOC pointer when we update
32998 the stack pointer. */
33001 rs6000_save_toc_in_prologue_p (void)
33003 return (cfun && cfun->machine && cfun->machine->save_toc_in_prologue);
33006 #ifdef HAVE_GAS_HIDDEN
33007 # define USE_HIDDEN_LINKONCE 1
33009 # define USE_HIDDEN_LINKONCE 0
33012 /* Fills in the label name that should be used for a 476 link stack thunk. */
33015 get_ppc476_thunk_name (char name[32])
33017 gcc_assert (TARGET_LINK_STACK);
33019 if (USE_HIDDEN_LINKONCE)
33020 sprintf (name, "__ppc476.get_thunk");
33022 ASM_GENERATE_INTERNAL_LABEL (name, "LPPC476_", 0);
33025 /* This function emits the simple thunk routine that is used to preserve
33026 the link stack on the 476 cpu. */
33028 static void rs6000_code_end (void) ATTRIBUTE_UNUSED;
33030 rs6000_code_end (void)
33035 if (!TARGET_LINK_STACK)
33038 get_ppc476_thunk_name (name);
33040 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, get_identifier (name),
33041 build_function_type_list (void_type_node, NULL_TREE));
33042 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
33043 NULL_TREE, void_type_node);
33044 TREE_PUBLIC (decl) = 1;
33045 TREE_STATIC (decl) = 1;
33048 if (USE_HIDDEN_LINKONCE)
33050 cgraph_node::create (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
33051 targetm.asm_out.unique_section (decl, 0);
33052 switch_to_section (get_named_section (decl, NULL, 0));
33053 DECL_WEAK (decl) = 1;
33054 ASM_WEAKEN_DECL (asm_out_file, decl, name, 0);
33055 targetm.asm_out.globalize_label (asm_out_file, name);
33056 targetm.asm_out.assemble_visibility (decl, VISIBILITY_HIDDEN);
33057 ASM_DECLARE_FUNCTION_NAME (asm_out_file, name, decl);
33062 switch_to_section (text_section);
33063 ASM_OUTPUT_LABEL (asm_out_file, name);
33066 DECL_INITIAL (decl) = make_node (BLOCK);
33067 current_function_decl = decl;
33068 init_function_start (decl);
33069 first_function_block_is_cold = false;
33070 /* Make sure unwind info is emitted for the thunk if needed. */
33071 final_start_function (emit_barrier (), asm_out_file, 1);
33073 fputs ("\tblr\n", asm_out_file);
33075 final_end_function ();
33076 init_insn_lengths ();
33077 free_after_compilation (cfun);
33079 current_function_decl = NULL;
33082 /* Add r30 to hard reg set if the prologue sets it up and it is not
33083 pic_offset_table_rtx. */
33086 rs6000_set_up_by_prologue (struct hard_reg_set_container *set)
33088 if (!TARGET_SINGLE_PIC_BASE
33090 && TARGET_MINIMAL_TOC
33091 && get_pool_size () != 0)
33092 add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
33096 /* Helper function for rs6000_split_logical to emit a logical instruction after
33097 spliting the operation to single GPR registers.
33099 DEST is the destination register.
33100 OP1 and OP2 are the input source registers.
33101 CODE is the base operation (AND, IOR, XOR, NOT).
33102 MODE is the machine mode.
33103 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
33104 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
33105 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
33108 rs6000_split_logical_inner (rtx dest,
33111 enum rtx_code code,
33113 bool complement_final_p,
33114 bool complement_op1_p,
33115 bool complement_op2_p)
33119 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
33120 if (op2 && GET_CODE (op2) == CONST_INT
33121 && (mode == SImode || (mode == DImode && TARGET_POWERPC64))
33122 && !complement_final_p && !complement_op1_p && !complement_op2_p)
33124 HOST_WIDE_INT mask = GET_MODE_MASK (mode);
33125 HOST_WIDE_INT value = INTVAL (op2) & mask;
33127 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
33132 emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx));
33136 else if (value == mask)
33138 if (!rtx_equal_p (dest, op1))
33139 emit_insn (gen_rtx_SET (VOIDmode, dest, op1));
33144 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
33145 into separate ORI/ORIS or XORI/XORIS instrucitons. */
33146 else if (code == IOR || code == XOR)
33150 if (!rtx_equal_p (dest, op1))
33151 emit_insn (gen_rtx_SET (VOIDmode, dest, op1));
33157 if (code == AND && mode == SImode
33158 && !complement_final_p && !complement_op1_p && !complement_op2_p)
33160 emit_insn (gen_andsi3 (dest, op1, op2));
33164 if (complement_op1_p)
33165 op1 = gen_rtx_NOT (mode, op1);
33167 if (complement_op2_p)
33168 op2 = gen_rtx_NOT (mode, op2);
33170 bool_rtx = ((code == NOT)
33171 ? gen_rtx_NOT (mode, op1)
33172 : gen_rtx_fmt_ee (code, mode, op1, op2));
33174 if (complement_final_p)
33175 bool_rtx = gen_rtx_NOT (mode, bool_rtx);
33177 emit_insn (gen_rtx_SET (VOIDmode, dest, bool_rtx));
33180 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
33181 operations are split immediately during RTL generation to allow for more
33182 optimizations of the AND/IOR/XOR.
33184 OPERANDS is an array containing the destination and two input operands.
33185 CODE is the base operation (AND, IOR, XOR, NOT).
33186 MODE is the machine mode.
33187 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
33188 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
33189 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
33190 CLOBBER_REG is either NULL or a scratch register of type CC to allow
33191 formation of the AND instructions. */
33194 rs6000_split_logical_di (rtx operands[3],
33195 enum rtx_code code,
33196 bool complement_final_p,
33197 bool complement_op1_p,
33198 bool complement_op2_p)
33200 const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff);
33201 const HOST_WIDE_INT upper_32bits = ~ lower_32bits;
33202 const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000);
33203 enum hi_lo { hi = 0, lo = 1 };
33204 rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2];
33207 op0_hi_lo[hi] = gen_highpart (SImode, operands[0]);
33208 op1_hi_lo[hi] = gen_highpart (SImode, operands[1]);
33209 op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]);
33210 op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]);
33213 op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX;
33216 if (GET_CODE (operands[2]) != CONST_INT)
33218 op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]);
33219 op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]);
33223 HOST_WIDE_INT value = INTVAL (operands[2]);
33224 HOST_WIDE_INT value_hi_lo[2];
33226 gcc_assert (!complement_final_p);
33227 gcc_assert (!complement_op1_p);
33228 gcc_assert (!complement_op2_p);
33230 value_hi_lo[hi] = value >> 32;
33231 value_hi_lo[lo] = value & lower_32bits;
33233 for (i = 0; i < 2; i++)
33235 HOST_WIDE_INT sub_value = value_hi_lo[i];
33237 if (sub_value & sign_bit)
33238 sub_value |= upper_32bits;
33240 op2_hi_lo[i] = GEN_INT (sub_value);
33242 /* If this is an AND instruction, check to see if we need to load
33243 the value in a register. */
33244 if (code == AND && sub_value != -1 && sub_value != 0
33245 && !and_operand (op2_hi_lo[i], SImode))
33246 op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]);
33251 for (i = 0; i < 2; i++)
33253 /* Split large IOR/XOR operations. */
33254 if ((code == IOR || code == XOR)
33255 && GET_CODE (op2_hi_lo[i]) == CONST_INT
33256 && !complement_final_p
33257 && !complement_op1_p
33258 && !complement_op2_p
33259 && !logical_const_operand (op2_hi_lo[i], SImode))
33261 HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]);
33262 HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000);
33263 HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff);
33264 rtx tmp = gen_reg_rtx (SImode);
33266 /* Make sure the constant is sign extended. */
33267 if ((hi_16bits & sign_bit) != 0)
33268 hi_16bits |= upper_32bits;
33270 rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits),
33271 code, SImode, false, false, false);
33273 rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits),
33274 code, SImode, false, false, false);
33277 rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i],
33278 code, SImode, complement_final_p,
33279 complement_op1_p, complement_op2_p);
33285 /* Split the insns that make up boolean operations operating on multiple GPR
33286 registers. The boolean MD patterns ensure that the inputs either are
33287 exactly the same as the output registers, or there is no overlap.
33289 OPERANDS is an array containing the destination and two input operands.
33290 CODE is the base operation (AND, IOR, XOR, NOT).
33291 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
33292 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
33293 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
33296 rs6000_split_logical (rtx operands[3],
33297 enum rtx_code code,
33298 bool complement_final_p,
33299 bool complement_op1_p,
33300 bool complement_op2_p)
33302 machine_mode mode = GET_MODE (operands[0]);
33303 machine_mode sub_mode;
33305 int sub_size, regno0, regno1, nregs, i;
33307 /* If this is DImode, use the specialized version that can run before
33308 register allocation. */
33309 if (mode == DImode && !TARGET_POWERPC64)
33311 rs6000_split_logical_di (operands, code, complement_final_p,
33312 complement_op1_p, complement_op2_p);
33318 op2 = (code == NOT) ? NULL_RTX : operands[2];
33319 sub_mode = (TARGET_POWERPC64) ? DImode : SImode;
33320 sub_size = GET_MODE_SIZE (sub_mode);
33321 regno0 = REGNO (op0);
33322 regno1 = REGNO (op1);
33324 gcc_assert (reload_completed);
33325 gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO));
33326 gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO));
33328 nregs = rs6000_hard_regno_nregs[(int)mode][regno0];
33329 gcc_assert (nregs > 1);
33331 if (op2 && REG_P (op2))
33332 gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO));
33334 for (i = 0; i < nregs; i++)
33336 int offset = i * sub_size;
33337 rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset);
33338 rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset);
33339 rtx sub_op2 = ((code == NOT)
33341 : simplify_subreg (sub_mode, op2, mode, offset));
33343 rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode,
33344 complement_final_p, complement_op1_p,
33352 /* Return true if the peephole2 can combine a load involving a combination of
33353 an addis instruction and a load with an offset that can be fused together on
33357 fusion_gpr_load_p (rtx addis_reg, /* register set via addis. */
33358 rtx addis_value, /* addis value. */
33359 rtx target, /* target register that is loaded. */
33360 rtx mem) /* bottom part of the memory addr. */
33365 /* Validate arguments. */
33366 if (!base_reg_operand (addis_reg, GET_MODE (addis_reg)))
33369 if (!base_reg_operand (target, GET_MODE (target)))
33372 if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value)))
33375 /* Allow sign/zero extension. */
33376 if (GET_CODE (mem) == ZERO_EXTEND
33377 || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN))
33378 mem = XEXP (mem, 0);
33383 if (!fusion_gpr_mem_load (mem, GET_MODE (mem)))
33386 addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */
33387 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
33390 /* Validate that the register used to load the high value is either the
33391 register being loaded, or we can safely replace its use.
33393 This function is only called from the peephole2 pass and we assume that
33394 there are 2 instructions in the peephole (addis and load), so we want to
33395 check if the target register was not used in the memory address and the
33396 register to hold the addis result is dead after the peephole. */
33397 if (REGNO (addis_reg) != REGNO (target))
33399 if (reg_mentioned_p (target, mem))
33402 if (!peep2_reg_dead_p (2, addis_reg))
33405 /* If the target register being loaded is the stack pointer, we must
33406 avoid loading any other value into it, even temporarily. */
33407 if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM)
33411 base_reg = XEXP (addr, 0);
33412 return REGNO (addis_reg) == REGNO (base_reg);
33415 /* During the peephole2 pass, adjust and expand the insns for a load fusion
33416 sequence. We adjust the addis register to use the target register. If the
33417 load sign extends, we adjust the code to do the zero extending load, and an
33418 explicit sign extension later since the fusion only covers zero extending
33422 operands[0] register set with addis (to be replaced with target)
33423 operands[1] value set via addis
33424 operands[2] target register being loaded
33425 operands[3] D-form memory reference using operands[0]. */
33428 expand_fusion_gpr_load (rtx *operands)
33430 rtx addis_value = operands[1];
33431 rtx target = operands[2];
33432 rtx orig_mem = operands[3];
33433 rtx new_addr, new_mem, orig_addr, offset;
33434 enum rtx_code plus_or_lo_sum;
33435 machine_mode target_mode = GET_MODE (target);
33436 machine_mode extend_mode = target_mode;
33437 machine_mode ptr_mode = Pmode;
33438 enum rtx_code extend = UNKNOWN;
33440 if (GET_CODE (orig_mem) == ZERO_EXTEND
33441 || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND))
33443 extend = GET_CODE (orig_mem);
33444 orig_mem = XEXP (orig_mem, 0);
33445 target_mode = GET_MODE (orig_mem);
33448 gcc_assert (MEM_P (orig_mem));
33450 orig_addr = XEXP (orig_mem, 0);
33451 plus_or_lo_sum = GET_CODE (orig_addr);
33452 gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM);
33454 offset = XEXP (orig_addr, 1);
33455 new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_value, offset);
33456 new_mem = replace_equiv_address_nv (orig_mem, new_addr, false);
33458 if (extend != UNKNOWN)
33459 new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem);
33461 new_mem = gen_rtx_UNSPEC (extend_mode, gen_rtvec (1, new_mem),
33462 UNSPEC_FUSION_GPR);
33463 emit_insn (gen_rtx_SET (VOIDmode, target, new_mem));
33465 if (extend == SIGN_EXTEND)
33467 int sub_off = ((BYTES_BIG_ENDIAN)
33468 ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode)
33471 = simplify_subreg (target_mode, target, extend_mode, sub_off);
33473 emit_insn (gen_rtx_SET (VOIDmode, target,
33474 gen_rtx_SIGN_EXTEND (extend_mode, sign_reg)));
33480 /* Return a string to fuse an addis instruction with a gpr load to the same
33481 register that we loaded up the addis instruction. The address that is used
33482 is the logical address that was formed during peephole2:
33483 (lo_sum (high) (low-part))
33485 The code is complicated, so we call output_asm_insn directly, and just
33489 emit_fusion_gpr_load (rtx target, rtx mem)
33495 const char *addis_str = NULL;
33496 const char *load_str = NULL;
33497 const char *mode_name = NULL;
33498 char insn_template[80];
33500 const char *comment_str = ASM_COMMENT_START;
33502 if (GET_CODE (mem) == ZERO_EXTEND)
33503 mem = XEXP (mem, 0);
33505 gcc_assert (REG_P (target) && MEM_P (mem));
33507 if (*comment_str == ' ')
33510 addr = XEXP (mem, 0);
33511 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
33512 gcc_unreachable ();
33514 addis_value = XEXP (addr, 0);
33515 load_offset = XEXP (addr, 1);
33517 /* Now emit the load instruction to the same register. */
33518 mode = GET_MODE (mem);
33522 mode_name = "char";
33527 mode_name = "short";
33537 gcc_assert (TARGET_POWERPC64);
33538 mode_name = "long";
33543 gcc_unreachable ();
33546 /* Emit the addis instruction. */
33547 fuse_ops[0] = target;
33548 if (satisfies_constraint_L (addis_value))
33550 fuse_ops[1] = addis_value;
33551 addis_str = "lis %0,%v1";
33554 else if (GET_CODE (addis_value) == PLUS)
33556 rtx op0 = XEXP (addis_value, 0);
33557 rtx op1 = XEXP (addis_value, 1);
33559 if (REG_P (op0) && CONST_INT_P (op1)
33560 && satisfies_constraint_L (op1))
33564 addis_str = "addis %0,%1,%v2";
33568 else if (GET_CODE (addis_value) == HIGH)
33570 rtx value = XEXP (addis_value, 0);
33571 if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL)
33573 fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */
33574 fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */
33576 addis_str = "addis %0,%2,%1@toc@ha";
33578 else if (TARGET_XCOFF)
33579 addis_str = "addis %0,%1@u(%2)";
33582 gcc_unreachable ();
33585 else if (GET_CODE (value) == PLUS)
33587 rtx op0 = XEXP (value, 0);
33588 rtx op1 = XEXP (value, 1);
33590 if (GET_CODE (op0) == UNSPEC
33591 && XINT (op0, 1) == UNSPEC_TOCREL
33592 && CONST_INT_P (op1))
33594 fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */
33595 fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */
33598 addis_str = "addis %0,%2,%1+%3@toc@ha";
33600 else if (TARGET_XCOFF)
33601 addis_str = "addis %0,%1+%3@u(%2)";
33604 gcc_unreachable ();
33608 else if (satisfies_constraint_L (value))
33610 fuse_ops[1] = value;
33611 addis_str = "lis %0,%v1";
33614 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value))
33616 fuse_ops[1] = value;
33617 addis_str = "lis %0,%1@ha";
33622 fatal_insn ("Could not generate addis value for fusion", addis_value);
33624 sprintf (insn_template, "%s\t\t%s gpr load fusion, type %s", addis_str,
33625 comment_str, mode_name);
33626 output_asm_insn (insn_template, fuse_ops);
33628 /* Emit the D-form load instruction. */
33629 if (CONST_INT_P (load_offset) && satisfies_constraint_I (load_offset))
33631 sprintf (insn_template, "%s %%0,%%1(%%0)", load_str);
33632 fuse_ops[1] = load_offset;
33633 output_asm_insn (insn_template, fuse_ops);
33636 else if (GET_CODE (load_offset) == UNSPEC
33637 && XINT (load_offset, 1) == UNSPEC_TOCREL)
33640 sprintf (insn_template, "%s %%0,%%1@toc@l(%%0)", load_str);
33642 else if (TARGET_XCOFF)
33643 sprintf (insn_template, "%s %%0,%%1@l(%%0)", load_str);
33646 gcc_unreachable ();
33648 fuse_ops[1] = XVECEXP (load_offset, 0, 0);
33649 output_asm_insn (insn_template, fuse_ops);
33652 else if (GET_CODE (load_offset) == PLUS
33653 && GET_CODE (XEXP (load_offset, 0)) == UNSPEC
33654 && XINT (XEXP (load_offset, 0), 1) == UNSPEC_TOCREL
33655 && CONST_INT_P (XEXP (load_offset, 1)))
33657 rtx tocrel_unspec = XEXP (load_offset, 0);
33659 sprintf (insn_template, "%s %%0,%%1+%%2@toc@l(%%0)", load_str);
33661 else if (TARGET_XCOFF)
33662 sprintf (insn_template, "%s %%0,%%1+%%2@l(%%0)", load_str);
33665 gcc_unreachable ();
33667 fuse_ops[1] = XVECEXP (tocrel_unspec, 0, 0);
33668 fuse_ops[2] = XEXP (load_offset, 1);
33669 output_asm_insn (insn_template, fuse_ops);
33672 else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (load_offset))
33674 sprintf (insn_template, "%s %%0,%%1@l(%%0)", load_str);
33676 fuse_ops[1] = load_offset;
33677 output_asm_insn (insn_template, fuse_ops);
33681 fatal_insn ("Unable to generate load offset for fusion", load_offset);
33686 /* Analyze vector computations and remove unnecessary doubleword
33687 swaps (xxswapdi instructions). This pass is performed only
33688 for little-endian VSX code generation.
33690 For this specific case, loads and stores of 4x32 and 2x64 vectors
33691 are inefficient. These are implemented using the lvx2dx and
33692 stvx2dx instructions, which invert the order of doublewords in
33693 a vector register. Thus the code generation inserts an xxswapdi
33694 after each such load, and prior to each such store. (For spill
33695 code after register assignment, an additional xxswapdi is inserted
33696 following each store in order to return a hard register to its
33699 The extra xxswapdi instructions reduce performance. This can be
33700 particularly bad for vectorized code. The purpose of this pass
33701 is to reduce the number of xxswapdi instructions required for
33704 The primary insight is that much code that operates on vectors
33705 does not care about the relative order of elements in a register,
33706 so long as the correct memory order is preserved. If we have
33707 a computation where all input values are provided by lvxd2x/xxswapdi
33708 sequences, all outputs are stored using xxswapdi/stvxd2x sequences,
33709 and all intermediate computations are pure SIMD (independent of
33710 element order), then all the xxswapdi's associated with the loads
33711 and stores may be removed.
33713 This pass uses some of the infrastructure and logical ideas from
33714 the "web" pass in web.c. We create maximal webs of computations
33715 fitting the description above using union-find. Each such web is
33716 then optimized by removing its unnecessary xxswapdi instructions.
33718 The pass is placed prior to global optimization so that we can
33719 perform the optimization in the safest and simplest way possible;
33720 that is, by replacing each xxswapdi insn with a register copy insn.
33721 Subsequent forward propagation will remove copies where possible.
33723 There are some operations sensitive to element order for which we
33724 can still allow the operation, provided we modify those operations.
33725 These include CONST_VECTORs, for which we must swap the first and
33726 second halves of the constant vector; and SUBREGs, for which we
33727 must adjust the byte offset to account for the swapped doublewords.
33728 A remaining opportunity would be non-immediate-form splats, for
33729 which we should adjust the selected lane of the input. We should
33730 also make code generation adjustments for sum-across operations,
33731 since this is a common vectorizer reduction.
33733 Because we run prior to the first split, we can see loads and stores
33734 here that match *vsx_le_perm_{load,store}_<mode>. These are vanilla
33735 vector loads and stores that have not yet been split into a permuting
33736 load/store and a swap. (One way this can happen is with a builtin
33737 call to vec_vsx_{ld,st}.) We can handle these as well, but rather
33738 than deleting a swap, we convert the load/store into a permuting
33739 load/store (which effectively removes the swap). */
33741 /* Notes on Permutes
33743 We do not currently handle computations that contain permutes. There
33744 is a general transformation that can be performed correctly, but it
33745 may introduce more expensive code than it replaces. To handle these
33746 would require a cost model to determine when to perform the optimization.
33747 This commentary records how this could be done if desired.
33749 The most general permute is something like this (example for V16QI):
33751 (vec_select:V16QI (vec_concat:V32QI (op1:V16QI) (op2:V16QI))
33752 (parallel [(const_int a0) (const_int a1)
33754 (const_int a14) (const_int a15)]))
33756 where a0,...,a15 are in [0,31] and select elements from op1 and op2
33757 to produce in the result.
33759 Regardless of mode, we can convert the PARALLEL to a mask of 16
33760 byte-element selectors. Let's call this M, with M[i] representing
33761 the ith byte-element selector value. Then if we swap doublewords
33762 throughout the computation, we can get correct behavior by replacing
33763 M with M' as follows:
33765 { M[i+8]+8 : i < 8, M[i+8] in [0,7] U [16,23]
33766 M'[i] = { M[i+8]-8 : i < 8, M[i+8] in [8,15] U [24,31]
33767 { M[i-8]+8 : i >= 8, M[i-8] in [0,7] U [16,23]
33768 { M[i-8]-8 : i >= 8, M[i-8] in [8,15] U [24,31]
33770 This seems promising at first, since we are just replacing one mask
33771 with another. But certain masks are preferable to others. If M
33772 is a mask that matches a vmrghh pattern, for example, M' certainly
33773 will not. Instead of a single vmrghh, we would generate a load of
33774 M' and a vperm. So we would need to know how many xxswapd's we can
33775 remove as a result of this transformation to determine if it's
33776 profitable; and preferably the logic would need to be aware of all
33777 the special preferable masks.
33779 Another form of permute is an UNSPEC_VPERM, in which the mask is
33780 already in a register. In some cases, this mask may be a constant
33781 that we can discover with ud-chains, in which case the above
33782 transformation is ok. However, the common usage here is for the
33783 mask to be produced by an UNSPEC_LVSL, in which case the mask
33784 cannot be known at compile time. In such a case we would have to
33785 generate several instructions to compute M' as above at run time,
33786 and a cost model is needed again. */
33788 /* This is based on the union-find logic in web.c. web_entry_base is
33789 defined in df.h. */
33790 class swap_web_entry : public web_entry_base
33793 /* Pointer to the insn. */
33795 /* Set if insn contains a mention of a vector register. All other
33796 fields are undefined if this field is unset. */
33797 unsigned int is_relevant : 1;
33798 /* Set if insn is a load. */
33799 unsigned int is_load : 1;
33800 /* Set if insn is a store. */
33801 unsigned int is_store : 1;
33802 /* Set if insn is a doubleword swap. This can either be a register swap
33803 or a permuting load or store (test is_load and is_store for this). */
33804 unsigned int is_swap : 1;
33805 /* Set if the insn has a live-in use of a parameter register. */
33806 unsigned int is_live_in : 1;
33807 /* Set if the insn has a live-out def of a return register. */
33808 unsigned int is_live_out : 1;
33809 /* Set if the insn contains a subreg reference of a vector register. */
33810 unsigned int contains_subreg : 1;
33811 /* Set if the insn contains a 128-bit integer operand. */
33812 unsigned int is_128_int : 1;
33813 /* Set if this is a call-insn. */
33814 unsigned int is_call : 1;
33815 /* Set if this insn does not perform a vector operation for which
33816 element order matters, or if we know how to fix it up if it does.
33817 Undefined if is_swap is set. */
33818 unsigned int is_swappable : 1;
33819 /* A nonzero value indicates what kind of special handling for this
33820 insn is required if doublewords are swapped. Undefined if
33821 is_swappable is not set. */
33822 unsigned int special_handling : 3;
33823 /* Set if the web represented by this entry cannot be optimized. */
33824 unsigned int web_not_optimizable : 1;
33825 /* Set if this insn should be deleted. */
33826 unsigned int will_delete : 1;
33829 enum special_handling_values {
33839 /* Union INSN with all insns containing definitions that reach USE.
33840 Detect whether USE is live-in to the current function. */
33842 union_defs (swap_web_entry *insn_entry, rtx insn, df_ref use)
33844 struct df_link *link = DF_REF_CHAIN (use);
33847 insn_entry[INSN_UID (insn)].is_live_in = 1;
33851 if (DF_REF_IS_ARTIFICIAL (link->ref))
33852 insn_entry[INSN_UID (insn)].is_live_in = 1;
33854 if (DF_REF_INSN_INFO (link->ref))
33856 rtx def_insn = DF_REF_INSN (link->ref);
33857 (void)unionfind_union (insn_entry + INSN_UID (insn),
33858 insn_entry + INSN_UID (def_insn));
33865 /* Union INSN with all insns containing uses reached from DEF.
33866 Detect whether DEF is live-out from the current function. */
33868 union_uses (swap_web_entry *insn_entry, rtx insn, df_ref def)
33870 struct df_link *link = DF_REF_CHAIN (def);
33873 insn_entry[INSN_UID (insn)].is_live_out = 1;
33877 /* This could be an eh use or some other artificial use;
33878 we treat these all the same (killing the optimization). */
33879 if (DF_REF_IS_ARTIFICIAL (link->ref))
33880 insn_entry[INSN_UID (insn)].is_live_out = 1;
33882 if (DF_REF_INSN_INFO (link->ref))
33884 rtx use_insn = DF_REF_INSN (link->ref);
33885 (void)unionfind_union (insn_entry + INSN_UID (insn),
33886 insn_entry + INSN_UID (use_insn));
33893 /* Return 1 iff INSN is a load insn, including permuting loads that
33894 represent an lvxd2x instruction; else return 0. */
33895 static unsigned int
33896 insn_is_load_p (rtx insn)
33898 rtx body = PATTERN (insn);
33900 if (GET_CODE (body) == SET)
33902 if (GET_CODE (SET_SRC (body)) == MEM)
33905 if (GET_CODE (SET_SRC (body)) == VEC_SELECT
33906 && GET_CODE (XEXP (SET_SRC (body), 0)) == MEM)
33912 if (GET_CODE (body) != PARALLEL)
33915 rtx set = XVECEXP (body, 0, 0);
33917 if (GET_CODE (set) == SET && GET_CODE (SET_SRC (set)) == MEM)
33923 /* Return 1 iff INSN is a store insn, including permuting stores that
33924 represent an stvxd2x instruction; else return 0. */
33925 static unsigned int
33926 insn_is_store_p (rtx insn)
33928 rtx body = PATTERN (insn);
33929 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == MEM)
33931 if (GET_CODE (body) != PARALLEL)
33933 rtx set = XVECEXP (body, 0, 0);
33934 if (GET_CODE (set) == SET && GET_CODE (SET_DEST (set)) == MEM)
33939 /* Return 1 iff INSN swaps doublewords. This may be a reg-reg swap,
33940 a permuting load, or a permuting store. */
33941 static unsigned int
33942 insn_is_swap_p (rtx insn)
33944 rtx body = PATTERN (insn);
33945 if (GET_CODE (body) != SET)
33947 rtx rhs = SET_SRC (body);
33948 if (GET_CODE (rhs) != VEC_SELECT)
33950 rtx parallel = XEXP (rhs, 1);
33951 if (GET_CODE (parallel) != PARALLEL)
33953 unsigned int len = XVECLEN (parallel, 0);
33954 if (len != 2 && len != 4 && len != 8 && len != 16)
33956 for (unsigned int i = 0; i < len / 2; ++i)
33958 rtx op = XVECEXP (parallel, 0, i);
33959 if (GET_CODE (op) != CONST_INT || INTVAL (op) != len / 2 + i)
33962 for (unsigned int i = len / 2; i < len; ++i)
33964 rtx op = XVECEXP (parallel, 0, i);
33965 if (GET_CODE (op) != CONST_INT || INTVAL (op) != i - len / 2)
33971 /* Return 1 iff OP is an operand that will not be affected by having
33972 vector doublewords swapped in memory. */
33973 static unsigned int
33974 rtx_is_swappable_p (rtx op, unsigned int *special)
33976 enum rtx_code code = GET_CODE (op);
33995 *special = SH_CONST_VECTOR;
33999 case VEC_DUPLICATE:
34000 /* Opportunity: If XEXP (op, 0) has the same mode as the result,
34001 and XEXP (op, 1) is a PARALLEL with a single QImode const int,
34002 it represents a vector splat for which we can do special
34004 if (GET_CODE (XEXP (op, 0)) == CONST_INT)
34006 else if (GET_CODE (XEXP (op, 0)) == REG
34007 && GET_MODE_INNER (GET_MODE (op)) == GET_MODE (XEXP (op, 0)))
34008 /* This catches V2DF and V2DI splat, at a minimum. */
34010 else if (GET_CODE (XEXP (op, 0)) == VEC_SELECT)
34011 /* If the duplicated item is from a select, defer to the select
34012 processing to see if we can change the lane for the splat. */
34013 return rtx_is_swappable_p (XEXP (op, 0), special);
34018 /* A vec_extract operation is ok if we change the lane. */
34019 if (GET_CODE (XEXP (op, 0)) == REG
34020 && GET_MODE_INNER (GET_MODE (XEXP (op, 0))) == GET_MODE (op)
34021 && GET_CODE ((parallel = XEXP (op, 1))) == PARALLEL
34022 && XVECLEN (parallel, 0) == 1
34023 && GET_CODE (XVECEXP (parallel, 0, 0)) == CONST_INT)
34025 *special = SH_EXTRACT;
34033 /* Various operations are unsafe for this optimization, at least
34034 without significant additional work. Permutes are obviously
34035 problematic, as both the permute control vector and the ordering
34036 of the target values are invalidated by doubleword swapping.
34037 Vector pack and unpack modify the number of vector lanes.
34038 Merge-high/low will not operate correctly on swapped operands.
34039 Vector shifts across element boundaries are clearly uncool,
34040 as are vector select and concatenate operations. Vector
34041 sum-across instructions define one operand with a specific
34042 order-dependent element, so additional fixup code would be
34043 needed to make those work. Vector set and non-immediate-form
34044 vector splat are element-order sensitive. A few of these
34045 cases might be workable with special handling if required. */
34046 int val = XINT (op, 1);
34051 case UNSPEC_VMRGH_DIRECT:
34052 case UNSPEC_VMRGL_DIRECT:
34053 case UNSPEC_VPACK_SIGN_SIGN_SAT:
34054 case UNSPEC_VPACK_SIGN_UNS_SAT:
34055 case UNSPEC_VPACK_UNS_UNS_MOD:
34056 case UNSPEC_VPACK_UNS_UNS_MOD_DIRECT:
34057 case UNSPEC_VPACK_UNS_UNS_SAT:
34059 case UNSPEC_VPERM_UNS:
34060 case UNSPEC_VPERMHI:
34061 case UNSPEC_VPERMSI:
34063 case UNSPEC_VSLDOI:
34066 case UNSPEC_VSUM2SWS:
34067 case UNSPEC_VSUM4S:
34068 case UNSPEC_VSUM4UBS:
34069 case UNSPEC_VSUMSWS:
34070 case UNSPEC_VSUMSWS_DIRECT:
34071 case UNSPEC_VSX_CONCAT:
34072 case UNSPEC_VSX_SET:
34073 case UNSPEC_VSX_SLDWI:
34074 case UNSPEC_VUNPACK_HI_SIGN:
34075 case UNSPEC_VUNPACK_HI_SIGN_DIRECT:
34076 case UNSPEC_VUNPACK_LO_SIGN:
34077 case UNSPEC_VUNPACK_LO_SIGN_DIRECT:
34078 case UNSPEC_VUPKHPX:
34079 case UNSPEC_VUPKHS_V4SF:
34080 case UNSPEC_VUPKHU_V4SF:
34081 case UNSPEC_VUPKLPX:
34082 case UNSPEC_VUPKLS_V4SF:
34083 case UNSPEC_VUPKLU_V4SF:
34084 /* The following could be handled as an idiom with XXSPLTW.
34085 These place a scalar in BE element zero, but the XXSPLTW
34086 will currently expect it in BE element 2 in a swapped
34087 region. When one of these feeds an XXSPLTW with no other
34088 defs/uses either way, we can avoid the lane change for
34089 XXSPLTW and things will be correct. TBD. */
34090 case UNSPEC_VSX_CVDPSPN:
34091 case UNSPEC_VSX_CVSPDP:
34092 case UNSPEC_VSX_CVSPDPN:
34094 case UNSPEC_VSPLT_DIRECT:
34095 *special = SH_SPLAT;
34104 const char *fmt = GET_RTX_FORMAT (code);
34107 for (i = 0; i < GET_RTX_LENGTH (code); ++i)
34108 if (fmt[i] == 'e' || fmt[i] == 'u')
34110 unsigned int special_op = SH_NONE;
34111 ok &= rtx_is_swappable_p (XEXP (op, i), &special_op);
34112 /* Ensure we never have two kinds of special handling
34113 for the same insn. */
34114 if (*special != SH_NONE && special_op != SH_NONE
34115 && *special != special_op)
34117 *special = special_op;
34119 else if (fmt[i] == 'E')
34120 for (j = 0; j < XVECLEN (op, i); ++j)
34122 unsigned int special_op = SH_NONE;
34123 ok &= rtx_is_swappable_p (XVECEXP (op, i, j), &special_op);
34124 /* Ensure we never have two kinds of special handling
34125 for the same insn. */
34126 if (*special != SH_NONE && special_op != SH_NONE
34127 && *special != special_op)
34129 *special = special_op;
34135 /* Return 1 iff INSN is an operand that will not be affected by
34136 having vector doublewords swapped in memory (in which case
34137 *SPECIAL is unchanged), or that can be modified to be correct
34138 if vector doublewords are swapped in memory (in which case
34139 *SPECIAL is changed to a value indicating how). */
34140 static unsigned int
34141 insn_is_swappable_p (swap_web_entry *insn_entry, rtx insn,
34142 unsigned int *special)
34144 /* Calls are always bad. */
34145 if (GET_CODE (insn) == CALL_INSN)
34148 /* Loads and stores seen here are not permuting, but we can still
34149 fix them up by converting them to permuting ones. Exceptions:
34150 UNSPEC_LVE, UNSPEC_LVX, and UNSPEC_STVX, which have a PARALLEL
34151 body instead of a SET; and UNSPEC_STVE, which has an UNSPEC
34152 for the SET source. */
34153 rtx body = PATTERN (insn);
34154 int i = INSN_UID (insn);
34156 if (insn_entry[i].is_load)
34158 if (GET_CODE (body) == SET)
34160 *special = SH_NOSWAP_LD;
34167 if (insn_entry[i].is_store)
34169 if (GET_CODE (body) == SET && GET_CODE (SET_SRC (body)) != UNSPEC)
34171 *special = SH_NOSWAP_ST;
34178 /* Otherwise check the operands for vector lane violations. */
34179 return rtx_is_swappable_p (body, special);
34182 enum chain_purpose { FOR_LOADS, FOR_STORES };
34184 /* Return true if the UD or DU chain headed by LINK is non-empty,
34185 and every entry on the chain references an insn that is a
34186 register swap. Furthermore, if PURPOSE is FOR_LOADS, each such
34187 register swap must have only permuting loads as reaching defs.
34188 If PURPOSE is FOR_STORES, each such register swap must have only
34189 register swaps or permuting stores as reached uses. */
34191 chain_contains_only_swaps (swap_web_entry *insn_entry, struct df_link *link,
34192 enum chain_purpose purpose)
34197 for (; link; link = link->next)
34199 if (!VECTOR_MODE_P (GET_MODE (DF_REF_REG (link->ref))))
34202 if (DF_REF_IS_ARTIFICIAL (link->ref))
34205 rtx reached_insn = DF_REF_INSN (link->ref);
34206 unsigned uid = INSN_UID (reached_insn);
34207 struct df_insn_info *insn_info = DF_INSN_INFO_GET (reached_insn);
34209 if (!insn_entry[uid].is_swap || insn_entry[uid].is_load
34210 || insn_entry[uid].is_store)
34213 if (purpose == FOR_LOADS)
34216 FOR_EACH_INSN_INFO_USE (use, insn_info)
34218 struct df_link *swap_link = DF_REF_CHAIN (use);
34222 if (DF_REF_IS_ARTIFICIAL (link->ref))
34225 rtx swap_def_insn = DF_REF_INSN (swap_link->ref);
34226 unsigned uid2 = INSN_UID (swap_def_insn);
34228 /* Only permuting loads are allowed. */
34229 if (!insn_entry[uid2].is_swap || !insn_entry[uid2].is_load)
34232 swap_link = swap_link->next;
34236 else if (purpose == FOR_STORES)
34239 FOR_EACH_INSN_INFO_DEF (def, insn_info)
34241 struct df_link *swap_link = DF_REF_CHAIN (def);
34245 if (DF_REF_IS_ARTIFICIAL (link->ref))
34248 rtx swap_use_insn = DF_REF_INSN (swap_link->ref);
34249 unsigned uid2 = INSN_UID (swap_use_insn);
34251 /* Permuting stores or register swaps are allowed. */
34252 if (!insn_entry[uid2].is_swap || insn_entry[uid2].is_load)
34255 swap_link = swap_link->next;
34264 /* Mark the xxswapdi instructions associated with permuting loads and
34265 stores for removal. Note that we only flag them for deletion here,
34266 as there is a possibility of a swap being reached from multiple
34269 mark_swaps_for_removal (swap_web_entry *insn_entry, unsigned int i)
34271 rtx insn = insn_entry[i].insn;
34272 struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
34274 if (insn_entry[i].is_load)
34277 FOR_EACH_INSN_INFO_DEF (def, insn_info)
34279 struct df_link *link = DF_REF_CHAIN (def);
34281 /* We know by now that these are swaps, so we can delete
34282 them confidently. */
34285 rtx use_insn = DF_REF_INSN (link->ref);
34286 insn_entry[INSN_UID (use_insn)].will_delete = 1;
34291 else if (insn_entry[i].is_store)
34294 FOR_EACH_INSN_INFO_USE (use, insn_info)
34296 /* Ignore uses for addressability. */
34297 machine_mode mode = GET_MODE (DF_REF_REG (use));
34298 if (!VECTOR_MODE_P (mode))
34301 struct df_link *link = DF_REF_CHAIN (use);
34303 /* We know by now that these are swaps, so we can delete
34304 them confidently. */
34307 rtx def_insn = DF_REF_INSN (link->ref);
34308 insn_entry[INSN_UID (def_insn)].will_delete = 1;
34315 /* OP is either a CONST_VECTOR or an expression containing one.
34316 Swap the first half of the vector with the second in the first
34317 case. Recurse to find it in the second. */
34319 swap_const_vector_halves (rtx op)
34322 enum rtx_code code = GET_CODE (op);
34323 if (GET_CODE (op) == CONST_VECTOR)
34325 int half_units = GET_MODE_NUNITS (GET_MODE (op)) / 2;
34326 for (i = 0; i < half_units; ++i)
34328 rtx temp = CONST_VECTOR_ELT (op, i);
34329 CONST_VECTOR_ELT (op, i) = CONST_VECTOR_ELT (op, i + half_units);
34330 CONST_VECTOR_ELT (op, i + half_units) = temp;
34336 const char *fmt = GET_RTX_FORMAT (code);
34337 for (i = 0; i < GET_RTX_LENGTH (code); ++i)
34338 if (fmt[i] == 'e' || fmt[i] == 'u')
34339 swap_const_vector_halves (XEXP (op, i));
34340 else if (fmt[i] == 'E')
34341 for (j = 0; j < XVECLEN (op, i); ++j)
34342 swap_const_vector_halves (XVECEXP (op, i, j));
34346 /* Find all subregs of a vector expression that perform a narrowing,
34347 and adjust the subreg index to account for doubleword swapping. */
34349 adjust_subreg_index (rtx op)
34351 enum rtx_code code = GET_CODE (op);
34353 && (GET_MODE_SIZE (GET_MODE (op))
34354 < GET_MODE_SIZE (GET_MODE (XEXP (op, 0)))))
34356 unsigned int index = SUBREG_BYTE (op);
34361 SUBREG_BYTE (op) = index;
34364 const char *fmt = GET_RTX_FORMAT (code);
34366 for (i = 0; i < GET_RTX_LENGTH (code); ++i)
34367 if (fmt[i] == 'e' || fmt[i] == 'u')
34368 adjust_subreg_index (XEXP (op, i));
34369 else if (fmt[i] == 'E')
34370 for (j = 0; j < XVECLEN (op, i); ++j)
34371 adjust_subreg_index (XVECEXP (op, i, j));
34374 /* Convert the non-permuting load INSN to a permuting one. */
34376 permute_load (rtx_insn *insn)
34378 rtx body = PATTERN (insn);
34379 rtx mem_op = SET_SRC (body);
34380 rtx tgt_reg = SET_DEST (body);
34381 machine_mode mode = GET_MODE (tgt_reg);
34382 int n_elts = GET_MODE_NUNITS (mode);
34383 int half_elts = n_elts / 2;
34384 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
34386 for (i = 0, j = half_elts; i < half_elts; ++i, ++j)
34387 XVECEXP (par, 0, i) = GEN_INT (j);
34388 for (i = half_elts, j = 0; j < half_elts; ++i, ++j)
34389 XVECEXP (par, 0, i) = GEN_INT (j);
34390 rtx sel = gen_rtx_VEC_SELECT (mode, mem_op, par);
34391 SET_SRC (body) = sel;
34392 INSN_CODE (insn) = -1; /* Force re-recognition. */
34393 df_insn_rescan (insn);
34396 fprintf (dump_file, "Replacing load %d with permuted load\n",
34400 /* Convert the non-permuting store INSN to a permuting one. */
34402 permute_store (rtx_insn *insn)
34404 rtx body = PATTERN (insn);
34405 rtx src_reg = SET_SRC (body);
34406 machine_mode mode = GET_MODE (src_reg);
34407 int n_elts = GET_MODE_NUNITS (mode);
34408 int half_elts = n_elts / 2;
34409 rtx par = gen_rtx_PARALLEL (mode, rtvec_alloc (n_elts));
34411 for (i = 0, j = half_elts; i < half_elts; ++i, ++j)
34412 XVECEXP (par, 0, i) = GEN_INT (j);
34413 for (i = half_elts, j = 0; j < half_elts; ++i, ++j)
34414 XVECEXP (par, 0, i) = GEN_INT (j);
34415 rtx sel = gen_rtx_VEC_SELECT (mode, src_reg, par);
34416 SET_SRC (body) = sel;
34417 INSN_CODE (insn) = -1; /* Force re-recognition. */
34418 df_insn_rescan (insn);
34421 fprintf (dump_file, "Replacing store %d with permuted store\n",
34425 /* Given OP that contains a vector extract operation, adjust the index
34426 of the extracted lane to account for the doubleword swap. */
34428 adjust_extract (rtx_insn *insn)
34430 rtx src = SET_SRC (PATTERN (insn));
34431 /* The vec_select may be wrapped in a vec_duplicate for a splat, so
34432 account for that. */
34433 rtx sel = GET_CODE (src) == VEC_DUPLICATE ? XEXP (src, 0) : src;
34434 rtx par = XEXP (sel, 1);
34435 int half_elts = GET_MODE_NUNITS (GET_MODE (XEXP (sel, 0))) >> 1;
34436 int lane = INTVAL (XVECEXP (par, 0, 0));
34437 lane = lane >= half_elts ? lane - half_elts : lane + half_elts;
34438 XVECEXP (par, 0, 0) = GEN_INT (lane);
34439 INSN_CODE (insn) = -1; /* Force re-recognition. */
34440 df_insn_rescan (insn);
34443 fprintf (dump_file, "Changing lane for extract %d\n", INSN_UID (insn));
34446 /* Given OP that contains a vector direct-splat operation, adjust the index
34447 of the source lane to account for the doubleword swap. */
34449 adjust_splat (rtx_insn *insn)
34451 rtx body = PATTERN (insn);
34452 rtx unspec = XEXP (body, 1);
34453 int half_elts = GET_MODE_NUNITS (GET_MODE (unspec)) >> 1;
34454 int lane = INTVAL (XVECEXP (unspec, 0, 1));
34455 lane = lane >= half_elts ? lane - half_elts : lane + half_elts;
34456 XVECEXP (unspec, 0, 1) = GEN_INT (lane);
34457 INSN_CODE (insn) = -1; /* Force re-recognition. */
34458 df_insn_rescan (insn);
34461 fprintf (dump_file, "Changing lane for splat %d\n", INSN_UID (insn));
34464 /* The insn described by INSN_ENTRY[I] can be swapped, but only
34465 with special handling. Take care of that here. */
34467 handle_special_swappables (swap_web_entry *insn_entry, unsigned i)
34469 rtx_insn *insn = insn_entry[i].insn;
34470 rtx body = PATTERN (insn);
34472 switch (insn_entry[i].special_handling)
34475 gcc_unreachable ();
34476 case SH_CONST_VECTOR:
34478 /* A CONST_VECTOR will only show up somewhere in the RHS of a SET. */
34479 gcc_assert (GET_CODE (body) == SET);
34480 rtx rhs = SET_SRC (body);
34481 swap_const_vector_halves (rhs);
34483 fprintf (dump_file, "Swapping constant halves in insn %d\n", i);
34487 /* A subreg of the same size is already safe. For subregs that
34488 select a smaller portion of a reg, adjust the index for
34489 swapped doublewords. */
34490 adjust_subreg_index (body);
34492 fprintf (dump_file, "Adjusting subreg in insn %d\n", i);
34495 /* Convert a non-permuting load to a permuting one. */
34496 permute_load (insn);
34499 /* Convert a non-permuting store to a permuting one. */
34500 permute_store (insn);
34503 /* Change the lane on an extract operation. */
34504 adjust_extract (insn);
34507 /* Change the lane on a direct-splat operation. */
34508 adjust_splat (insn);
34513 /* Find the insn from the Ith table entry, which is known to be a
34514 register swap Y = SWAP(X). Replace it with a copy Y = X. */
34516 replace_swap_with_copy (swap_web_entry *insn_entry, unsigned i)
34518 rtx_insn *insn = insn_entry[i].insn;
34519 rtx body = PATTERN (insn);
34520 rtx src_reg = XEXP (SET_SRC (body), 0);
34521 rtx copy = gen_rtx_SET (VOIDmode, SET_DEST (body), src_reg);
34522 rtx_insn *new_insn = emit_insn_before (copy, insn);
34523 set_block_for_insn (new_insn, BLOCK_FOR_INSN (insn));
34524 df_insn_rescan (new_insn);
34528 unsigned int new_uid = INSN_UID (new_insn);
34529 fprintf (dump_file, "Replacing swap %d with copy %d\n", i, new_uid);
34532 df_insn_delete (insn);
34533 remove_insn (insn);
34534 insn->set_deleted ();
34537 /* Dump the swap table to DUMP_FILE. */
34539 dump_swap_insn_table (swap_web_entry *insn_entry)
34541 int e = get_max_uid ();
34542 fprintf (dump_file, "\nRelevant insns with their flag settings\n\n");
34544 for (int i = 0; i < e; ++i)
34545 if (insn_entry[i].is_relevant)
34547 swap_web_entry *pred_entry = (swap_web_entry *)insn_entry[i].pred ();
34548 fprintf (dump_file, "%6d %6d ", i,
34549 pred_entry && pred_entry->insn
34550 ? INSN_UID (pred_entry->insn) : 0);
34551 if (insn_entry[i].is_load)
34552 fputs ("load ", dump_file);
34553 if (insn_entry[i].is_store)
34554 fputs ("store ", dump_file);
34555 if (insn_entry[i].is_swap)
34556 fputs ("swap ", dump_file);
34557 if (insn_entry[i].is_live_in)
34558 fputs ("live-in ", dump_file);
34559 if (insn_entry[i].is_live_out)
34560 fputs ("live-out ", dump_file);
34561 if (insn_entry[i].contains_subreg)
34562 fputs ("subreg ", dump_file);
34563 if (insn_entry[i].is_128_int)
34564 fputs ("int128 ", dump_file);
34565 if (insn_entry[i].is_call)
34566 fputs ("call ", dump_file);
34567 if (insn_entry[i].is_swappable)
34569 fputs ("swappable ", dump_file);
34570 if (insn_entry[i].special_handling == SH_CONST_VECTOR)
34571 fputs ("special:constvec ", dump_file);
34572 else if (insn_entry[i].special_handling == SH_SUBREG)
34573 fputs ("special:subreg ", dump_file);
34574 else if (insn_entry[i].special_handling == SH_NOSWAP_LD)
34575 fputs ("special:load ", dump_file);
34576 else if (insn_entry[i].special_handling == SH_NOSWAP_ST)
34577 fputs ("special:store ", dump_file);
34578 else if (insn_entry[i].special_handling == SH_EXTRACT)
34579 fputs ("special:extract ", dump_file);
34580 else if (insn_entry[i].special_handling == SH_SPLAT)
34581 fputs ("special:splat ", dump_file);
34583 if (insn_entry[i].web_not_optimizable)
34584 fputs ("unoptimizable ", dump_file);
34585 if (insn_entry[i].will_delete)
34586 fputs ("delete ", dump_file);
34587 fputs ("\n", dump_file);
34589 fputs ("\n", dump_file);
34592 /* Main entry point for this pass. */
34594 rs6000_analyze_swaps (function *fun)
34596 swap_web_entry *insn_entry;
34600 /* Dataflow analysis for use-def chains. */
34601 df_set_flags (DF_RD_PRUNE_DEAD_DEFS);
34602 df_chain_add_problem (DF_DU_CHAIN | DF_UD_CHAIN);
34604 df_set_flags (DF_DEFER_INSN_RESCAN);
34606 /* Allocate structure to represent webs of insns. */
34607 insn_entry = XCNEWVEC (swap_web_entry, get_max_uid ());
34609 /* Walk the insns to gather basic data. */
34610 FOR_ALL_BB_FN (bb, fun)
34611 FOR_BB_INSNS (bb, insn)
34613 unsigned int uid = INSN_UID (insn);
34614 if (NONDEBUG_INSN_P (insn))
34616 insn_entry[uid].insn = insn;
34618 if (GET_CODE (insn) == CALL_INSN)
34619 insn_entry[uid].is_call = 1;
34621 /* Walk the uses and defs to see if we mention vector regs.
34622 Record any constraints on optimization of such mentions. */
34623 struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
34625 FOR_EACH_INSN_INFO_USE (mention, insn_info)
34627 /* We use DF_REF_REAL_REG here to get inside any subregs. */
34628 machine_mode mode = GET_MODE (DF_REF_REAL_REG (mention));
34630 /* If a use gets its value from a call insn, it will be
34631 a hard register and will look like (reg:V4SI 3 3).
34632 The df analysis creates two mentions for GPR3 and GPR4,
34633 both DImode. We must recognize this and treat it as a
34634 vector mention to ensure the call is unioned with this
34636 if (mode == DImode && DF_REF_INSN_INFO (mention))
34638 rtx feeder = DF_REF_INSN (mention);
34639 /* FIXME: It is pretty hard to get from the df mention
34640 to the mode of the use in the insn. We arbitrarily
34641 pick a vector mode here, even though the use might
34642 be a real DImode. We can be too conservative
34643 (create a web larger than necessary) because of
34644 this, so consider eventually fixing this. */
34645 if (GET_CODE (feeder) == CALL_INSN)
34649 if (VECTOR_MODE_P (mode))
34651 insn_entry[uid].is_relevant = 1;
34652 if (mode == TImode || mode == V1TImode)
34653 insn_entry[uid].is_128_int = 1;
34654 if (DF_REF_INSN_INFO (mention))
34655 insn_entry[uid].contains_subreg
34656 = !rtx_equal_p (DF_REF_REG (mention),
34657 DF_REF_REAL_REG (mention));
34658 union_defs (insn_entry, insn, mention);
34661 FOR_EACH_INSN_INFO_DEF (mention, insn_info)
34663 /* We use DF_REF_REAL_REG here to get inside any subregs. */
34664 machine_mode mode = GET_MODE (DF_REF_REAL_REG (mention));
34666 /* If we're loading up a hard vector register for a call,
34667 it looks like (set (reg:V4SI 9 9) (...)). The df
34668 analysis creates two mentions for GPR9 and GPR10, both
34669 DImode. So relying on the mode from the mentions
34670 isn't sufficient to ensure we union the call into the
34671 web with the parameter setup code. */
34672 if (mode == DImode && GET_CODE (insn) == SET
34673 && VECTOR_MODE_P (GET_MODE (SET_DEST (insn))))
34674 mode = GET_MODE (SET_DEST (insn));
34676 if (VECTOR_MODE_P (mode))
34678 insn_entry[uid].is_relevant = 1;
34679 if (mode == TImode || mode == V1TImode)
34680 insn_entry[uid].is_128_int = 1;
34681 if (DF_REF_INSN_INFO (mention))
34682 insn_entry[uid].contains_subreg
34683 = !rtx_equal_p (DF_REF_REG (mention),
34684 DF_REF_REAL_REG (mention));
34685 /* REG_FUNCTION_VALUE_P is not valid for subregs. */
34686 else if (REG_FUNCTION_VALUE_P (DF_REF_REG (mention)))
34687 insn_entry[uid].is_live_out = 1;
34688 union_uses (insn_entry, insn, mention);
34692 if (insn_entry[uid].is_relevant)
34694 /* Determine if this is a load or store. */
34695 insn_entry[uid].is_load = insn_is_load_p (insn);
34696 insn_entry[uid].is_store = insn_is_store_p (insn);
34698 /* Determine if this is a doubleword swap. If not,
34699 determine whether it can legally be swapped. */
34700 if (insn_is_swap_p (insn))
34701 insn_entry[uid].is_swap = 1;
34704 unsigned int special = SH_NONE;
34705 insn_entry[uid].is_swappable
34706 = insn_is_swappable_p (insn_entry, insn, &special);
34707 if (special != SH_NONE && insn_entry[uid].contains_subreg)
34708 insn_entry[uid].is_swappable = 0;
34709 else if (special != SH_NONE)
34710 insn_entry[uid].special_handling = special;
34711 else if (insn_entry[uid].contains_subreg)
34712 insn_entry[uid].special_handling = SH_SUBREG;
34720 fprintf (dump_file, "\nSwap insn entry table when first built\n");
34721 dump_swap_insn_table (insn_entry);
34724 /* Record unoptimizable webs. */
34725 unsigned e = get_max_uid (), i;
34726 for (i = 0; i < e; ++i)
34728 if (!insn_entry[i].is_relevant)
34731 swap_web_entry *root
34732 = (swap_web_entry*)(&insn_entry[i])->unionfind_root ();
34734 if (insn_entry[i].is_live_in || insn_entry[i].is_live_out
34735 || (insn_entry[i].contains_subreg
34736 && insn_entry[i].special_handling != SH_SUBREG)
34737 || insn_entry[i].is_128_int || insn_entry[i].is_call
34738 || !(insn_entry[i].is_swappable || insn_entry[i].is_swap))
34739 root->web_not_optimizable = 1;
34741 /* If we have loads or stores that aren't permuting then the
34742 optimization isn't appropriate. */
34743 else if ((insn_entry[i].is_load || insn_entry[i].is_store)
34744 && !insn_entry[i].is_swap && !insn_entry[i].is_swappable)
34745 root->web_not_optimizable = 1;
34747 /* If we have permuting loads or stores that are not accompanied
34748 by a register swap, the optimization isn't appropriate. */
34749 else if (insn_entry[i].is_load && insn_entry[i].is_swap)
34751 rtx insn = insn_entry[i].insn;
34752 struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
34755 FOR_EACH_INSN_INFO_DEF (def, insn_info)
34757 struct df_link *link = DF_REF_CHAIN (def);
34759 if (!chain_contains_only_swaps (insn_entry, link, FOR_LOADS))
34761 root->web_not_optimizable = 1;
34766 else if (insn_entry[i].is_store && insn_entry[i].is_swap)
34768 rtx insn = insn_entry[i].insn;
34769 struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn);
34772 FOR_EACH_INSN_INFO_USE (use, insn_info)
34774 struct df_link *link = DF_REF_CHAIN (use);
34776 if (!chain_contains_only_swaps (insn_entry, link, FOR_STORES))
34778 root->web_not_optimizable = 1;
34787 fprintf (dump_file, "\nSwap insn entry table after web analysis\n");
34788 dump_swap_insn_table (insn_entry);
34791 /* For each load and store in an optimizable web (which implies
34792 the loads and stores are permuting), find the associated
34793 register swaps and mark them for removal. Due to various
34794 optimizations we may mark the same swap more than once. Also
34795 perform special handling for swappable insns that require it. */
34796 for (i = 0; i < e; ++i)
34797 if ((insn_entry[i].is_load || insn_entry[i].is_store)
34798 && insn_entry[i].is_swap)
34800 swap_web_entry* root_entry
34801 = (swap_web_entry*)((&insn_entry[i])->unionfind_root ());
34802 if (!root_entry->web_not_optimizable)
34803 mark_swaps_for_removal (insn_entry, i);
34805 else if (insn_entry[i].is_swappable && insn_entry[i].special_handling)
34807 swap_web_entry* root_entry
34808 = (swap_web_entry*)((&insn_entry[i])->unionfind_root ());
34809 if (!root_entry->web_not_optimizable)
34810 handle_special_swappables (insn_entry, i);
34813 /* Now delete the swaps marked for removal. */
34814 for (i = 0; i < e; ++i)
34815 if (insn_entry[i].will_delete)
34816 replace_swap_with_copy (insn_entry, i);
34823 const pass_data pass_data_analyze_swaps =
34825 RTL_PASS, /* type */
34826 "swaps", /* name */
34827 OPTGROUP_NONE, /* optinfo_flags */
34828 TV_NONE, /* tv_id */
34829 0, /* properties_required */
34830 0, /* properties_provided */
34831 0, /* properties_destroyed */
34832 0, /* todo_flags_start */
34833 TODO_df_finish, /* todo_flags_finish */
34836 class pass_analyze_swaps : public rtl_opt_pass
34839 pass_analyze_swaps(gcc::context *ctxt)
34840 : rtl_opt_pass(pass_data_analyze_swaps, ctxt)
34843 /* opt_pass methods: */
34844 virtual bool gate (function *)
34846 return (optimize > 0 && !BYTES_BIG_ENDIAN && TARGET_VSX
34847 && rs6000_optimize_swaps);
34850 virtual unsigned int execute (function *fun)
34852 return rs6000_analyze_swaps (fun);
34855 }; // class pass_analyze_swaps
34858 make_pass_analyze_swaps (gcc::context *ctxt)
34860 return new pass_analyze_swaps (ctxt);
34863 #ifdef RS6000_GLIBC_ATOMIC_FENV
34864 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
34865 static tree atomic_hold_decl, atomic_clear_decl, atomic_update_decl;
34868 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
34871 rs6000_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
34873 if (!TARGET_HARD_FLOAT || !TARGET_FPRS)
34875 #ifdef RS6000_GLIBC_ATOMIC_FENV
34876 if (atomic_hold_decl == NULL_TREE)
34879 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
34880 get_identifier ("__atomic_feholdexcept"),
34881 build_function_type_list (void_type_node,
34882 double_ptr_type_node,
34884 TREE_PUBLIC (atomic_hold_decl) = 1;
34885 DECL_EXTERNAL (atomic_hold_decl) = 1;
34888 if (atomic_clear_decl == NULL_TREE)
34891 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
34892 get_identifier ("__atomic_feclearexcept"),
34893 build_function_type_list (void_type_node,
34895 TREE_PUBLIC (atomic_clear_decl) = 1;
34896 DECL_EXTERNAL (atomic_clear_decl) = 1;
34899 tree const_double = build_qualified_type (double_type_node,
34901 tree const_double_ptr = build_pointer_type (const_double);
34902 if (atomic_update_decl == NULL_TREE)
34905 = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
34906 get_identifier ("__atomic_feupdateenv"),
34907 build_function_type_list (void_type_node,
34910 TREE_PUBLIC (atomic_update_decl) = 1;
34911 DECL_EXTERNAL (atomic_update_decl) = 1;
34914 tree fenv_var = create_tmp_var (double_type_node);
34915 mark_addressable (fenv_var);
34916 tree fenv_addr = build1 (ADDR_EXPR, double_ptr_type_node, fenv_var);
34918 *hold = build_call_expr (atomic_hold_decl, 1, fenv_addr);
34919 *clear = build_call_expr (atomic_clear_decl, 0);
34920 *update = build_call_expr (atomic_update_decl, 1,
34921 fold_convert (const_double_ptr, fenv_addr));
34926 tree mffs = rs6000_builtin_decls[RS6000_BUILTIN_MFFS];
34927 tree mtfsf = rs6000_builtin_decls[RS6000_BUILTIN_MTFSF];
34928 tree call_mffs = build_call_expr (mffs, 0);
34930 /* Generates the equivalent of feholdexcept (&fenv_var)
34932 *fenv_var = __builtin_mffs ();
34934 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
34935 __builtin_mtfsf (0xff, fenv_hold); */
34937 /* Mask to clear everything except for the rounding modes and non-IEEE
34938 arithmetic flag. */
34939 const unsigned HOST_WIDE_INT hold_exception_mask =
34940 HOST_WIDE_INT_C (0xffffffff00000007);
34942 tree fenv_var = create_tmp_var (double_type_node);
34944 tree hold_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_var, call_mffs);
34946 tree fenv_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_var);
34947 tree fenv_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
34948 build_int_cst (uint64_type_node,
34949 hold_exception_mask));
34951 tree fenv_hold_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
34954 tree hold_mtfsf = build_call_expr (mtfsf, 2,
34955 build_int_cst (unsigned_type_node, 0xff),
34958 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_mffs, hold_mtfsf);
34960 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
34962 double fenv_clear = __builtin_mffs ();
34963 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
34964 __builtin_mtfsf (0xff, fenv_clear); */
34966 /* Mask to clear everything except for the rounding modes and non-IEEE
34967 arithmetic flag. */
34968 const unsigned HOST_WIDE_INT clear_exception_mask =
34969 HOST_WIDE_INT_C (0xffffffff00000000);
34971 tree fenv_clear = create_tmp_var (double_type_node);
34973 tree clear_mffs = build2 (MODIFY_EXPR, void_type_node, fenv_clear, call_mffs);
34975 tree fenv_clean_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, fenv_clear);
34976 tree fenv_clear_llu_and = build2 (BIT_AND_EXPR, uint64_type_node,
34978 build_int_cst (uint64_type_node,
34979 clear_exception_mask));
34981 tree fenv_clear_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
34982 fenv_clear_llu_and);
34984 tree clear_mtfsf = build_call_expr (mtfsf, 2,
34985 build_int_cst (unsigned_type_node, 0xff),
34988 *clear = build2 (COMPOUND_EXPR, void_type_node, clear_mffs, clear_mtfsf);
34990 /* Generates the equivalent of feupdateenv (&fenv_var)
34992 double old_fenv = __builtin_mffs ();
34993 double fenv_update;
34994 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
34995 (*(uint64_t*)fenv_var 0x1ff80fff);
34996 __builtin_mtfsf (0xff, fenv_update); */
34998 const unsigned HOST_WIDE_INT update_exception_mask =
34999 HOST_WIDE_INT_C (0xffffffff1fffff00);
35000 const unsigned HOST_WIDE_INT new_exception_mask =
35001 HOST_WIDE_INT_C (0x1ff80fff);
35003 tree old_fenv = create_tmp_var (double_type_node);
35004 tree update_mffs = build2 (MODIFY_EXPR, void_type_node, old_fenv, call_mffs);
35006 tree old_llu = build1 (VIEW_CONVERT_EXPR, uint64_type_node, old_fenv);
35007 tree old_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, old_llu,
35008 build_int_cst (uint64_type_node,
35009 update_exception_mask));
35011 tree new_llu_and = build2 (BIT_AND_EXPR, uint64_type_node, fenv_llu,
35012 build_int_cst (uint64_type_node,
35013 new_exception_mask));
35015 tree new_llu_mask = build2 (BIT_IOR_EXPR, uint64_type_node,
35016 old_llu_and, new_llu_and);
35018 tree fenv_update_mtfsf = build1 (VIEW_CONVERT_EXPR, double_type_node,
35021 tree update_mtfsf = build_call_expr (mtfsf, 2,
35022 build_int_cst (unsigned_type_node, 0xff),
35023 fenv_update_mtfsf);
35025 *update = build2 (COMPOUND_EXPR, void_type_node, update_mffs, update_mtfsf);
35029 struct gcc_target targetm = TARGET_INITIALIZER;
35031 #include "gt-rs6000.h"