2 ;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
31 (UNSPEC_VMHRADDSHS 72)
68 (UNSPEC_VPERM_UNS 145)
98 (UNSPEC_GET_VRSAVE 214)
100 (UNSPEC_REDUC_PLUS 217)
102 (UNSPEC_EXTEVEN_V4SI 220)
103 (UNSPEC_EXTEVEN_V8HI 221)
104 (UNSPEC_EXTEVEN_V16QI 222)
105 (UNSPEC_EXTEVEN_V4SF 223)
106 (UNSPEC_EXTODD_V4SI 224)
107 (UNSPEC_EXTODD_V8HI 225)
108 (UNSPEC_EXTODD_V16QI 226)
109 (UNSPEC_EXTODD_V4SF 227)
110 (UNSPEC_INTERHI_V4SI 228)
111 (UNSPEC_INTERHI_V8HI 229)
112 (UNSPEC_INTERHI_V16QI 230)
114 (UNSPEC_INTERLO_V4SI 232)
115 (UNSPEC_INTERLO_V8HI 233)
116 (UNSPEC_INTERLO_V16QI 234)
126 (UNSPEC_VMULWHUB 308)
127 (UNSPEC_VMULWLUB 309)
128 (UNSPEC_VMULWHSB 310)
129 (UNSPEC_VMULWLSB 311)
130 (UNSPEC_VMULWHUH 312)
131 (UNSPEC_VMULWLUH 313)
132 (UNSPEC_VMULWHSH 314)
133 (UNSPEC_VMULWLSH 315)
142 (UNSPEC_VUPKHS_V4SF 324)
143 (UNSPEC_VUPKLS_V4SF 325)
144 (UNSPEC_VUPKHU_V4SF 326)
145 (UNSPEC_VUPKLU_V4SF 327)
149 [(UNSPECV_SET_VRSAVE 30)
157 (define_mode_iterator VI [V4SI V8HI V16QI])
158 ;; Short vec in modes
159 (define_mode_iterator VIshort [V8HI V16QI])
161 (define_mode_iterator VF [V4SF])
162 ;; Vec modes, pity mode iterators are not composable
163 (define_mode_iterator V [V4SI V8HI V16QI V4SF])
164 ;; Vec modes for move/logical/permute ops, include vector types for move not
165 ;; otherwise handled by altivec (v2df, v2di, ti)
166 (define_mode_iterator VM [V4SI V8HI V16QI V4SF V2DF V2DI TI])
168 ;; Like VM, except don't do TImode
169 (define_mode_iterator VM2 [V4SI V8HI V16QI V4SF V2DF V2DI])
171 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
172 (define_mode_attr VI_scalar [(V4SI "SI") (V8HI "HI") (V16QI "QI")])
174 ;; Vector move instructions.
175 (define_insn "*altivec_mov<mode>"
176 [(set (match_operand:VM2 0 "nonimmediate_operand" "=Z,v,v,*o,*r,*r,v,v")
177 (match_operand:VM2 1 "input_operand" "v,Z,v,r,o,r,j,W"))]
178 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)
179 && (register_operand (operands[0], <MODE>mode)
180 || register_operand (operands[1], <MODE>mode))"
182 switch (which_alternative)
184 case 0: return "stvx %1,%y0";
185 case 1: return "lvx %0,%y1";
186 case 2: return "vor %0,%1,%1";
190 case 6: return "vxor %0,%0,%0";
191 case 7: return output_vec_const_move (operands);
192 default: gcc_unreachable ();
195 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")])
197 ;; Unlike other altivec moves, allow the GPRs, since a normal use of TImode
198 ;; is for unions. However for plain data movement, slightly favor the vector
200 (define_insn "*altivec_movti"
201 [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,v,v,?o,?r,?r,v,v")
202 (match_operand:TI 1 "input_operand" "v,Z,v,r,o,r,j,W"))]
203 "VECTOR_MEM_ALTIVEC_P (TImode)
204 && (register_operand (operands[0], TImode)
205 || register_operand (operands[1], TImode))"
207 switch (which_alternative)
209 case 0: return "stvx %1,%y0";
210 case 1: return "lvx %0,%y1";
211 case 2: return "vor %0,%1,%1";
215 case 6: return "vxor %0,%0,%0";
216 case 7: return output_vec_const_move (operands);
217 default: gcc_unreachable ();
220 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,vecsimple,*")])
222 ;; Load up a vector with the most significant bit set by loading up -1 and
223 ;; doing a shift left
225 [(set (match_operand:VM 0 "altivec_register_operand" "")
226 (match_operand:VM 1 "easy_vector_constant_msb" ""))]
227 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed"
230 rtx dest = operands[0];
231 enum machine_mode mode = GET_MODE (operands[0]);
235 if (mode == V4SFmode)
238 dest = gen_lowpart (V4SImode, dest);
241 num_elements = GET_MODE_NUNITS (mode);
242 v = rtvec_alloc (num_elements);
243 for (i = 0; i < num_elements; i++)
244 RTVEC_ELT (v, i) = constm1_rtx;
246 emit_insn (gen_vec_initv4si (dest, gen_rtx_PARALLEL (mode, v)));
247 emit_insn (gen_rtx_SET (VOIDmode, dest, gen_rtx_ASHIFT (mode, dest, dest)));
252 [(set (match_operand:VM 0 "altivec_register_operand" "")
253 (match_operand:VM 1 "easy_vector_constant_add_self" ""))]
254 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed"
255 [(set (match_dup 0) (match_dup 3))
256 (set (match_dup 0) (match_dup 4))]
258 rtx dup = gen_easy_altivec_constant (operands[1]);
260 enum machine_mode op_mode = <MODE>mode;
262 /* Divide the operand of the resulting VEC_DUPLICATE, and use
263 simplify_rtx to make a CONST_VECTOR. */
264 XEXP (dup, 0) = simplify_const_binary_operation (ASHIFTRT, QImode,
265 XEXP (dup, 0), const1_rtx);
266 const_vec = simplify_rtx (dup);
268 if (op_mode == V4SFmode)
271 operands[0] = gen_lowpart (op_mode, operands[0]);
273 if (GET_MODE (const_vec) == op_mode)
274 operands[3] = const_vec;
276 operands[3] = gen_lowpart (op_mode, const_vec);
277 operands[4] = gen_rtx_PLUS (op_mode, operands[0], operands[0]);
280 (define_insn "get_vrsave_internal"
281 [(set (match_operand:SI 0 "register_operand" "=r")
282 (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
286 return "mfspr %0,256";
288 return "mfvrsave %0";
290 [(set_attr "type" "*")])
292 (define_insn "*set_vrsave_internal"
293 [(match_parallel 0 "vrsave_operation"
295 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
296 (reg:SI 109)] UNSPECV_SET_VRSAVE))])]
300 return "mtspr 256,%1";
302 return "mtvrsave %1";
304 [(set_attr "type" "*")])
306 (define_insn "*save_world"
307 [(match_parallel 0 "save_world_operation"
308 [(clobber (reg:SI 65))
309 (use (match_operand:SI 1 "call_operand" "s"))])]
310 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
312 [(set_attr "type" "branch")
313 (set_attr "length" "4")])
315 (define_insn "*restore_world"
316 [(match_parallel 0 "restore_world_operation"
319 (use (match_operand:SI 1 "call_operand" "s"))
320 (clobber (match_operand:SI 2 "gpc_reg_operand" "=r"))])]
321 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
324 ;; Simple binary operations.
327 (define_insn "add<mode>3"
328 [(set (match_operand:VI 0 "register_operand" "=v")
329 (plus:VI (match_operand:VI 1 "register_operand" "v")
330 (match_operand:VI 2 "register_operand" "v")))]
332 "vaddu<VI_char>m %0,%1,%2"
333 [(set_attr "type" "vecsimple")])
335 (define_insn "*altivec_addv4sf3"
336 [(set (match_operand:V4SF 0 "register_operand" "=v")
337 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
338 (match_operand:V4SF 2 "register_operand" "v")))]
339 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
341 [(set_attr "type" "vecfloat")])
343 (define_insn "altivec_vaddcuw"
344 [(set (match_operand:V4SI 0 "register_operand" "=v")
345 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
346 (match_operand:V4SI 2 "register_operand" "v")]
350 [(set_attr "type" "vecsimple")])
352 (define_insn "altivec_vaddu<VI_char>s"
353 [(set (match_operand:VI 0 "register_operand" "=v")
354 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
355 (match_operand:VI 2 "register_operand" "v")]
357 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
359 "vaddu<VI_char>s %0,%1,%2"
360 [(set_attr "type" "vecsimple")])
362 (define_insn "altivec_vadds<VI_char>s"
363 [(set (match_operand:VI 0 "register_operand" "=v")
364 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
365 (match_operand:VI 2 "register_operand" "v")]
367 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
369 "vadds<VI_char>s %0,%1,%2"
370 [(set_attr "type" "vecsimple")])
373 (define_insn "sub<mode>3"
374 [(set (match_operand:VI 0 "register_operand" "=v")
375 (minus:VI (match_operand:VI 1 "register_operand" "v")
376 (match_operand:VI 2 "register_operand" "v")))]
378 "vsubu<VI_char>m %0,%1,%2"
379 [(set_attr "type" "vecsimple")])
381 (define_insn "*altivec_subv4sf3"
382 [(set (match_operand:V4SF 0 "register_operand" "=v")
383 (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
384 (match_operand:V4SF 2 "register_operand" "v")))]
385 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
387 [(set_attr "type" "vecfloat")])
389 (define_insn "altivec_vsubcuw"
390 [(set (match_operand:V4SI 0 "register_operand" "=v")
391 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
392 (match_operand:V4SI 2 "register_operand" "v")]
396 [(set_attr "type" "vecsimple")])
398 (define_insn "altivec_vsubu<VI_char>s"
399 [(set (match_operand:VI 0 "register_operand" "=v")
400 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
401 (match_operand:VI 2 "register_operand" "v")]
403 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
405 "vsubu<VI_char>s %0,%1,%2"
406 [(set_attr "type" "vecsimple")])
408 (define_insn "altivec_vsubs<VI_char>s"
409 [(set (match_operand:VI 0 "register_operand" "=v")
410 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
411 (match_operand:VI 2 "register_operand" "v")]
413 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
415 "vsubs<VI_char>s %0,%1,%2"
416 [(set_attr "type" "vecsimple")])
419 (define_insn "altivec_vavgu<VI_char>"
420 [(set (match_operand:VI 0 "register_operand" "=v")
421 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
422 (match_operand:VI 2 "register_operand" "v")]
425 "vavgu<VI_char> %0,%1,%2"
426 [(set_attr "type" "vecsimple")])
428 (define_insn "altivec_vavgs<VI_char>"
429 [(set (match_operand:VI 0 "register_operand" "=v")
430 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
431 (match_operand:VI 2 "register_operand" "v")]
434 "vavgs<VI_char> %0,%1,%2"
435 [(set_attr "type" "vecsimple")])
437 (define_insn "altivec_vcmpbfp"
438 [(set (match_operand:V4SI 0 "register_operand" "=v")
439 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
440 (match_operand:V4SF 2 "register_operand" "v")]
444 [(set_attr "type" "veccmp")])
446 (define_insn "*altivec_eq<mode>"
447 [(set (match_operand:VI 0 "altivec_register_operand" "=v")
448 (eq:VI (match_operand:VI 1 "altivec_register_operand" "v")
449 (match_operand:VI 2 "altivec_register_operand" "v")))]
451 "vcmpequ<VI_char> %0,%1,%2"
452 [(set_attr "type" "veccmp")])
454 (define_insn "*altivec_gt<mode>"
455 [(set (match_operand:VI 0 "altivec_register_operand" "=v")
456 (gt:VI (match_operand:VI 1 "altivec_register_operand" "v")
457 (match_operand:VI 2 "altivec_register_operand" "v")))]
459 "vcmpgts<VI_char> %0,%1,%2"
460 [(set_attr "type" "veccmp")])
462 (define_insn "*altivec_gtu<mode>"
463 [(set (match_operand:VI 0 "altivec_register_operand" "=v")
464 (gtu:VI (match_operand:VI 1 "altivec_register_operand" "v")
465 (match_operand:VI 2 "altivec_register_operand" "v")))]
467 "vcmpgtu<VI_char> %0,%1,%2"
468 [(set_attr "type" "veccmp")])
470 (define_insn "*altivec_eqv4sf"
471 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
472 (eq:V4SF (match_operand:V4SF 1 "altivec_register_operand" "v")
473 (match_operand:V4SF 2 "altivec_register_operand" "v")))]
474 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
476 [(set_attr "type" "veccmp")])
478 (define_insn "*altivec_gtv4sf"
479 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
480 (gt:V4SF (match_operand:V4SF 1 "altivec_register_operand" "v")
481 (match_operand:V4SF 2 "altivec_register_operand" "v")))]
482 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
484 [(set_attr "type" "veccmp")])
486 (define_insn "*altivec_gev4sf"
487 [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
488 (ge:V4SF (match_operand:V4SF 1 "altivec_register_operand" "v")
489 (match_operand:V4SF 2 "altivec_register_operand" "v")))]
490 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
492 [(set_attr "type" "veccmp")])
494 (define_insn "*altivec_vsel<mode>"
495 [(set (match_operand:VM 0 "altivec_register_operand" "=v")
497 (ne:CC (match_operand:VM 1 "altivec_register_operand" "v")
499 (match_operand:VM 2 "altivec_register_operand" "v")
500 (match_operand:VM 3 "altivec_register_operand" "v")))]
501 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
503 [(set_attr "type" "vecperm")])
505 (define_insn "*altivec_vsel<mode>_uns"
506 [(set (match_operand:VM 0 "altivec_register_operand" "=v")
508 (ne:CCUNS (match_operand:VM 1 "altivec_register_operand" "v")
510 (match_operand:VM 2 "altivec_register_operand" "v")
511 (match_operand:VM 3 "altivec_register_operand" "v")))]
512 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
514 [(set_attr "type" "vecperm")])
516 ;; Fused multiply add.
518 (define_insn "*altivec_fmav4sf4"
519 [(set (match_operand:V4SF 0 "register_operand" "=v")
520 (fma:V4SF (match_operand:V4SF 1 "register_operand" "v")
521 (match_operand:V4SF 2 "register_operand" "v")
522 (match_operand:V4SF 3 "register_operand" "v")))]
523 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
524 "vmaddfp %0,%1,%2,%3"
525 [(set_attr "type" "vecfloat")])
527 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
529 (define_expand "altivec_mulv4sf3"
530 [(set (match_operand:V4SF 0 "register_operand" "")
531 (fma:V4SF (match_operand:V4SF 1 "register_operand" "")
532 (match_operand:V4SF 2 "register_operand" "")
534 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
538 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
539 neg0 = gen_reg_rtx (V4SImode);
540 emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
541 emit_insn (gen_vashlv4si3 (neg0, neg0, neg0));
543 operands[3] = gen_lowpart (V4SFmode, neg0);
546 ;; 32-bit integer multiplication
547 ;; A_high = Operand_0 & 0xFFFF0000 >> 16
548 ;; A_low = Operand_0 & 0xFFFF
549 ;; B_high = Operand_1 & 0xFFFF0000 >> 16
550 ;; B_low = Operand_1 & 0xFFFF
551 ;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
553 ;; (define_insn "mulv4si3"
554 ;; [(set (match_operand:V4SI 0 "register_operand" "=v")
555 ;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
556 ;; (match_operand:V4SI 2 "register_operand" "v")))]
557 (define_expand "mulv4si3"
558 [(use (match_operand:V4SI 0 "register_operand" ""))
559 (use (match_operand:V4SI 1 "register_operand" ""))
560 (use (match_operand:V4SI 2 "register_operand" ""))]
573 zero = gen_reg_rtx (V4SImode);
574 emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
576 sixteen = gen_reg_rtx (V4SImode);
577 emit_insn (gen_altivec_vspltisw (sixteen, gen_rtx_CONST_INT (V4SImode, -16)));
579 swap = gen_reg_rtx (V4SImode);
580 emit_insn (gen_vrotlv4si3 (swap, operands[2], sixteen));
582 one = gen_reg_rtx (V8HImode);
583 convert_move (one, operands[1], 0);
585 two = gen_reg_rtx (V8HImode);
586 convert_move (two, operands[2], 0);
588 small_swap = gen_reg_rtx (V8HImode);
589 convert_move (small_swap, swap, 0);
591 low_product = gen_reg_rtx (V4SImode);
592 emit_insn (gen_altivec_vmulouh (low_product, one, two));
594 high_product = gen_reg_rtx (V4SImode);
595 emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
597 emit_insn (gen_vashlv4si3 (high_product, high_product, sixteen));
599 emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
604 (define_expand "mulv8hi3"
605 [(use (match_operand:V8HI 0 "register_operand" ""))
606 (use (match_operand:V8HI 1 "register_operand" ""))
607 (use (match_operand:V8HI 2 "register_operand" ""))]
611 rtx odd = gen_reg_rtx (V4SImode);
612 rtx even = gen_reg_rtx (V4SImode);
613 rtx high = gen_reg_rtx (V4SImode);
614 rtx low = gen_reg_rtx (V4SImode);
616 emit_insn (gen_altivec_vmulesh (even, operands[1], operands[2]));
617 emit_insn (gen_altivec_vmulosh (odd, operands[1], operands[2]));
619 emit_insn (gen_altivec_vmrghw (high, even, odd));
620 emit_insn (gen_altivec_vmrglw (low, even, odd));
622 emit_insn (gen_altivec_vpkuwum (operands[0], high, low));
627 ;; Fused multiply subtract
628 (define_insn "*altivec_vnmsubfp"
629 [(set (match_operand:V4SF 0 "register_operand" "=v")
631 (fma:V4SF (match_operand:V4SF 1 "register_operand" "v")
632 (match_operand:V4SF 2 "register_operand" "v")
634 (match_operand:V4SF 3 "register_operand" "v")))))]
635 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
636 "vnmsubfp %0,%1,%2,%3"
637 [(set_attr "type" "vecfloat")])
639 (define_insn "altivec_vmsumu<VI_char>m"
640 [(set (match_operand:V4SI 0 "register_operand" "=v")
641 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
642 (match_operand:VIshort 2 "register_operand" "v")
643 (match_operand:V4SI 3 "register_operand" "v")]
646 "vmsumu<VI_char>m %0,%1,%2,%3"
647 [(set_attr "type" "veccomplex")])
649 (define_insn "altivec_vmsumm<VI_char>m"
650 [(set (match_operand:V4SI 0 "register_operand" "=v")
651 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
652 (match_operand:VIshort 2 "register_operand" "v")
653 (match_operand:V4SI 3 "register_operand" "v")]
656 "vmsumm<VI_char>m %0,%1,%2,%3"
657 [(set_attr "type" "veccomplex")])
659 (define_insn "altivec_vmsumshm"
660 [(set (match_operand:V4SI 0 "register_operand" "=v")
661 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
662 (match_operand:V8HI 2 "register_operand" "v")
663 (match_operand:V4SI 3 "register_operand" "v")]
666 "vmsumshm %0,%1,%2,%3"
667 [(set_attr "type" "veccomplex")])
669 (define_insn "altivec_vmsumuhs"
670 [(set (match_operand:V4SI 0 "register_operand" "=v")
671 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
672 (match_operand:V8HI 2 "register_operand" "v")
673 (match_operand:V4SI 3 "register_operand" "v")]
675 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
677 "vmsumuhs %0,%1,%2,%3"
678 [(set_attr "type" "veccomplex")])
680 (define_insn "altivec_vmsumshs"
681 [(set (match_operand:V4SI 0 "register_operand" "=v")
682 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
683 (match_operand:V8HI 2 "register_operand" "v")
684 (match_operand:V4SI 3 "register_operand" "v")]
686 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
688 "vmsumshs %0,%1,%2,%3"
689 [(set_attr "type" "veccomplex")])
693 (define_insn "umax<mode>3"
694 [(set (match_operand:VI 0 "register_operand" "=v")
695 (umax:VI (match_operand:VI 1 "register_operand" "v")
696 (match_operand:VI 2 "register_operand" "v")))]
698 "vmaxu<VI_char> %0,%1,%2"
699 [(set_attr "type" "vecsimple")])
701 (define_insn "smax<mode>3"
702 [(set (match_operand:VI 0 "register_operand" "=v")
703 (smax:VI (match_operand:VI 1 "register_operand" "v")
704 (match_operand:VI 2 "register_operand" "v")))]
706 "vmaxs<VI_char> %0,%1,%2"
707 [(set_attr "type" "vecsimple")])
709 (define_insn "*altivec_smaxv4sf3"
710 [(set (match_operand:V4SF 0 "register_operand" "=v")
711 (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
712 (match_operand:V4SF 2 "register_operand" "v")))]
713 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
715 [(set_attr "type" "veccmp")])
717 (define_insn "umin<mode>3"
718 [(set (match_operand:VI 0 "register_operand" "=v")
719 (umin:VI (match_operand:VI 1 "register_operand" "v")
720 (match_operand:VI 2 "register_operand" "v")))]
722 "vminu<VI_char> %0,%1,%2"
723 [(set_attr "type" "vecsimple")])
725 (define_insn "smin<mode>3"
726 [(set (match_operand:VI 0 "register_operand" "=v")
727 (smin:VI (match_operand:VI 1 "register_operand" "v")
728 (match_operand:VI 2 "register_operand" "v")))]
730 "vmins<VI_char> %0,%1,%2"
731 [(set_attr "type" "vecsimple")])
733 (define_insn "*altivec_sminv4sf3"
734 [(set (match_operand:V4SF 0 "register_operand" "=v")
735 (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
736 (match_operand:V4SF 2 "register_operand" "v")))]
737 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
739 [(set_attr "type" "veccmp")])
741 (define_insn "altivec_vmhaddshs"
742 [(set (match_operand:V8HI 0 "register_operand" "=v")
743 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
744 (match_operand:V8HI 2 "register_operand" "v")
745 (match_operand:V8HI 3 "register_operand" "v")]
747 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
749 "vmhaddshs %0,%1,%2,%3"
750 [(set_attr "type" "veccomplex")])
752 (define_insn "altivec_vmhraddshs"
753 [(set (match_operand:V8HI 0 "register_operand" "=v")
754 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
755 (match_operand:V8HI 2 "register_operand" "v")
756 (match_operand:V8HI 3 "register_operand" "v")]
758 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
760 "vmhraddshs %0,%1,%2,%3"
761 [(set_attr "type" "veccomplex")])
763 (define_insn "altivec_vmladduhm"
764 [(set (match_operand:V8HI 0 "register_operand" "=v")
765 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
766 (match_operand:V8HI 2 "register_operand" "v")
767 (match_operand:V8HI 3 "register_operand" "v")]
770 "vmladduhm %0,%1,%2,%3"
771 [(set_attr "type" "veccomplex")])
773 (define_insn "altivec_vmrghb"
774 [(set (match_operand:V16QI 0 "register_operand" "=v")
775 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
776 (parallel [(const_int 0)
792 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
793 (parallel [(const_int 8)
812 [(set_attr "type" "vecperm")])
814 (define_insn "altivec_vmrghh"
815 [(set (match_operand:V8HI 0 "register_operand" "=v")
816 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
817 (parallel [(const_int 0)
825 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
826 (parallel [(const_int 4)
837 [(set_attr "type" "vecperm")])
839 (define_insn "altivec_vmrghw"
840 [(set (match_operand:V4SI 0 "register_operand" "=v")
841 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
842 (parallel [(const_int 0)
846 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
847 (parallel [(const_int 2)
852 "VECTOR_MEM_ALTIVEC_P (V4SImode)"
854 [(set_attr "type" "vecperm")])
856 (define_insn "*altivec_vmrghsf"
857 [(set (match_operand:V4SF 0 "register_operand" "=v")
858 (vec_merge:V4SF (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "v")
859 (parallel [(const_int 0)
863 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "v")
864 (parallel [(const_int 2)
869 "VECTOR_MEM_ALTIVEC_P (V4SFmode)"
871 [(set_attr "type" "vecperm")])
873 (define_insn "altivec_vmrglb"
874 [(set (match_operand:V16QI 0 "register_operand" "=v")
875 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
876 (parallel [(const_int 8)
892 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
893 (parallel [(const_int 0)
912 [(set_attr "type" "vecperm")])
914 (define_insn "altivec_vmrglh"
915 [(set (match_operand:V8HI 0 "register_operand" "=v")
916 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
917 (parallel [(const_int 4)
925 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
926 (parallel [(const_int 0)
937 [(set_attr "type" "vecperm")])
939 (define_insn "altivec_vmrglw"
940 [(set (match_operand:V4SI 0 "register_operand" "=v")
942 (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
943 (parallel [(const_int 2)
947 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
948 (parallel [(const_int 0)
953 "VECTOR_MEM_ALTIVEC_P (V4SImode)"
955 [(set_attr "type" "vecperm")])
957 (define_insn "*altivec_vmrglsf"
958 [(set (match_operand:V4SF 0 "register_operand" "=v")
960 (vec_select:V4SF (match_operand:V4SF 1 "register_operand" "v")
961 (parallel [(const_int 2)
965 (vec_select:V4SF (match_operand:V4SF 2 "register_operand" "v")
966 (parallel [(const_int 0)
971 "VECTOR_MEM_ALTIVEC_P (V4SFmode)"
973 [(set_attr "type" "vecperm")])
975 (define_insn "altivec_vmuleub"
976 [(set (match_operand:V8HI 0 "register_operand" "=v")
977 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
978 (match_operand:V16QI 2 "register_operand" "v")]
982 [(set_attr "type" "veccomplex")])
984 (define_insn "altivec_vmulesb"
985 [(set (match_operand:V8HI 0 "register_operand" "=v")
986 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
987 (match_operand:V16QI 2 "register_operand" "v")]
991 [(set_attr "type" "veccomplex")])
993 (define_insn "altivec_vmuleuh"
994 [(set (match_operand:V4SI 0 "register_operand" "=v")
995 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
996 (match_operand:V8HI 2 "register_operand" "v")]
1000 [(set_attr "type" "veccomplex")])
1002 (define_insn "altivec_vmulesh"
1003 [(set (match_operand:V4SI 0 "register_operand" "=v")
1004 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1005 (match_operand:V8HI 2 "register_operand" "v")]
1009 [(set_attr "type" "veccomplex")])
1011 (define_insn "altivec_vmuloub"
1012 [(set (match_operand:V8HI 0 "register_operand" "=v")
1013 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1014 (match_operand:V16QI 2 "register_operand" "v")]
1018 [(set_attr "type" "veccomplex")])
1020 (define_insn "altivec_vmulosb"
1021 [(set (match_operand:V8HI 0 "register_operand" "=v")
1022 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
1023 (match_operand:V16QI 2 "register_operand" "v")]
1027 [(set_attr "type" "veccomplex")])
1029 (define_insn "altivec_vmulouh"
1030 [(set (match_operand:V4SI 0 "register_operand" "=v")
1031 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1032 (match_operand:V8HI 2 "register_operand" "v")]
1036 [(set_attr "type" "veccomplex")])
1038 (define_insn "altivec_vmulosh"
1039 [(set (match_operand:V4SI 0 "register_operand" "=v")
1040 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1041 (match_operand:V8HI 2 "register_operand" "v")]
1045 [(set_attr "type" "veccomplex")])
1048 ;; logical ops. Have the logical ops follow the memory ops in
1049 ;; terms of whether to prefer VSX or Altivec
1051 (define_insn "*altivec_and<mode>3"
1052 [(set (match_operand:VM 0 "register_operand" "=v")
1053 (and:VM (match_operand:VM 1 "register_operand" "v")
1054 (match_operand:VM 2 "register_operand" "v")))]
1055 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
1057 [(set_attr "type" "vecsimple")])
1059 (define_insn "*altivec_ior<mode>3"
1060 [(set (match_operand:VM 0 "register_operand" "=v")
1061 (ior:VM (match_operand:VM 1 "register_operand" "v")
1062 (match_operand:VM 2 "register_operand" "v")))]
1063 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
1065 [(set_attr "type" "vecsimple")])
1067 (define_insn "*altivec_xor<mode>3"
1068 [(set (match_operand:VM 0 "register_operand" "=v")
1069 (xor:VM (match_operand:VM 1 "register_operand" "v")
1070 (match_operand:VM 2 "register_operand" "v")))]
1071 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
1073 [(set_attr "type" "vecsimple")])
1075 (define_insn "*altivec_one_cmpl<mode>2"
1076 [(set (match_operand:VM 0 "register_operand" "=v")
1077 (not:VM (match_operand:VM 1 "register_operand" "v")))]
1078 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
1080 [(set_attr "type" "vecsimple")])
1082 (define_insn "*altivec_nor<mode>3"
1083 [(set (match_operand:VM 0 "register_operand" "=v")
1084 (not:VM (ior:VM (match_operand:VM 1 "register_operand" "v")
1085 (match_operand:VM 2 "register_operand" "v"))))]
1086 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
1088 [(set_attr "type" "vecsimple")])
1090 (define_insn "*altivec_andc<mode>3"
1091 [(set (match_operand:VM 0 "register_operand" "=v")
1092 (and:VM (not:VM (match_operand:VM 2 "register_operand" "v"))
1093 (match_operand:VM 1 "register_operand" "v")))]
1094 "VECTOR_MEM_ALTIVEC_P (<MODE>mode)"
1096 [(set_attr "type" "vecsimple")])
1098 (define_insn "altivec_vpkuhum"
1099 [(set (match_operand:V16QI 0 "register_operand" "=v")
1100 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1101 (match_operand:V8HI 2 "register_operand" "v")]
1105 [(set_attr "type" "vecperm")])
1107 (define_insn "altivec_vpkuwum"
1108 [(set (match_operand:V8HI 0 "register_operand" "=v")
1109 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1110 (match_operand:V4SI 2 "register_operand" "v")]
1114 [(set_attr "type" "vecperm")])
1116 (define_insn "altivec_vpkpx"
1117 [(set (match_operand:V8HI 0 "register_operand" "=v")
1118 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1119 (match_operand:V4SI 2 "register_operand" "v")]
1123 [(set_attr "type" "vecperm")])
1125 (define_insn "altivec_vpkshss"
1126 [(set (match_operand:V16QI 0 "register_operand" "=v")
1127 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1128 (match_operand:V8HI 2 "register_operand" "v")]
1130 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1133 [(set_attr "type" "vecperm")])
1135 (define_insn "altivec_vpkswss"
1136 [(set (match_operand:V8HI 0 "register_operand" "=v")
1137 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1138 (match_operand:V4SI 2 "register_operand" "v")]
1140 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1143 [(set_attr "type" "vecperm")])
1145 (define_insn "altivec_vpkuhus"
1146 [(set (match_operand:V16QI 0 "register_operand" "=v")
1147 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1148 (match_operand:V8HI 2 "register_operand" "v")]
1150 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1153 [(set_attr "type" "vecperm")])
1155 (define_insn "altivec_vpkshus"
1156 [(set (match_operand:V16QI 0 "register_operand" "=v")
1157 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1158 (match_operand:V8HI 2 "register_operand" "v")]
1160 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1163 [(set_attr "type" "vecperm")])
1165 (define_insn "altivec_vpkuwus"
1166 [(set (match_operand:V8HI 0 "register_operand" "=v")
1167 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1168 (match_operand:V4SI 2 "register_operand" "v")]
1170 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1173 [(set_attr "type" "vecperm")])
1175 (define_insn "altivec_vpkswus"
1176 [(set (match_operand:V8HI 0 "register_operand" "=v")
1177 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1178 (match_operand:V4SI 2 "register_operand" "v")]
1180 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1183 [(set_attr "type" "vecperm")])
1185 (define_insn "*altivec_vrl<VI_char>"
1186 [(set (match_operand:VI 0 "register_operand" "=v")
1187 (rotate:VI (match_operand:VI 1 "register_operand" "v")
1188 (match_operand:VI 2 "register_operand" "v")))]
1190 "vrl<VI_char> %0,%1,%2"
1191 [(set_attr "type" "vecsimple")])
1193 (define_insn "altivec_vsl"
1194 [(set (match_operand:V4SI 0 "register_operand" "=v")
1195 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1196 (match_operand:V4SI 2 "register_operand" "v")]
1200 [(set_attr "type" "vecperm")])
1202 (define_insn "altivec_vslo"
1203 [(set (match_operand:V4SI 0 "register_operand" "=v")
1204 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1205 (match_operand:V4SI 2 "register_operand" "v")]
1209 [(set_attr "type" "vecperm")])
1211 (define_insn "*altivec_vsl<VI_char>"
1212 [(set (match_operand:VI 0 "register_operand" "=v")
1213 (ashift:VI (match_operand:VI 1 "register_operand" "v")
1214 (match_operand:VI 2 "register_operand" "v")))]
1216 "vsl<VI_char> %0,%1,%2"
1217 [(set_attr "type" "vecsimple")])
1219 (define_insn "*altivec_vsr<VI_char>"
1220 [(set (match_operand:VI 0 "register_operand" "=v")
1221 (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
1222 (match_operand:VI 2 "register_operand" "v")))]
1224 "vsr<VI_char> %0,%1,%2"
1225 [(set_attr "type" "vecsimple")])
1227 (define_insn "*altivec_vsra<VI_char>"
1228 [(set (match_operand:VI 0 "register_operand" "=v")
1229 (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
1230 (match_operand:VI 2 "register_operand" "v")))]
1232 "vsra<VI_char> %0,%1,%2"
1233 [(set_attr "type" "vecsimple")])
1235 (define_insn "altivec_vsr"
1236 [(set (match_operand:V4SI 0 "register_operand" "=v")
1237 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1238 (match_operand:V4SI 2 "register_operand" "v")]
1242 [(set_attr "type" "vecperm")])
1244 (define_insn "altivec_vsro"
1245 [(set (match_operand:V4SI 0 "register_operand" "=v")
1246 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1247 (match_operand:V4SI 2 "register_operand" "v")]
1251 [(set_attr "type" "vecperm")])
1253 (define_insn "altivec_vsum4ubs"
1254 [(set (match_operand:V4SI 0 "register_operand" "=v")
1255 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1256 (match_operand:V4SI 2 "register_operand" "v")]
1258 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1261 [(set_attr "type" "veccomplex")])
1263 (define_insn "altivec_vsum4s<VI_char>s"
1264 [(set (match_operand:V4SI 0 "register_operand" "=v")
1265 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1266 (match_operand:V4SI 2 "register_operand" "v")]
1268 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1270 "vsum4s<VI_char>s %0,%1,%2"
1271 [(set_attr "type" "veccomplex")])
1273 (define_insn "altivec_vsum2sws"
1274 [(set (match_operand:V4SI 0 "register_operand" "=v")
1275 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1276 (match_operand:V4SI 2 "register_operand" "v")]
1278 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1281 [(set_attr "type" "veccomplex")])
1283 (define_insn "altivec_vsumsws"
1284 [(set (match_operand:V4SI 0 "register_operand" "=v")
1285 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1286 (match_operand:V4SI 2 "register_operand" "v")]
1288 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1291 [(set_attr "type" "veccomplex")])
1293 (define_insn "altivec_vspltb"
1294 [(set (match_operand:V16QI 0 "register_operand" "=v")
1295 (vec_duplicate:V16QI
1296 (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
1298 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1301 [(set_attr "type" "vecperm")])
1303 (define_insn "altivec_vsplth"
1304 [(set (match_operand:V8HI 0 "register_operand" "=v")
1306 (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
1308 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1311 [(set_attr "type" "vecperm")])
1313 (define_insn "altivec_vspltw"
1314 [(set (match_operand:V4SI 0 "register_operand" "=v")
1316 (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
1318 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1321 [(set_attr "type" "vecperm")])
1323 (define_insn "altivec_vspltsf"
1324 [(set (match_operand:V4SF 0 "register_operand" "=v")
1326 (vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
1328 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1329 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1331 [(set_attr "type" "vecperm")])
1333 (define_insn "altivec_vspltis<VI_char>"
1334 [(set (match_operand:VI 0 "register_operand" "=v")
1336 (match_operand:QI 1 "s5bit_cint_operand" "i")))]
1338 "vspltis<VI_char> %0,%1"
1339 [(set_attr "type" "vecperm")])
1341 (define_insn "*altivec_vrfiz"
1342 [(set (match_operand:V4SF 0 "register_operand" "=v")
1343 (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1344 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1346 [(set_attr "type" "vecfloat")])
1348 (define_insn "altivec_vperm_<mode>"
1349 [(set (match_operand:VM 0 "register_operand" "=v")
1350 (unspec:VM [(match_operand:VM 1 "register_operand" "v")
1351 (match_operand:VM 2 "register_operand" "v")
1352 (match_operand:V16QI 3 "register_operand" "v")]
1356 [(set_attr "type" "vecperm")])
1358 (define_insn "altivec_vperm_<mode>_uns"
1359 [(set (match_operand:VM 0 "register_operand" "=v")
1360 (unspec:VM [(match_operand:VM 1 "register_operand" "v")
1361 (match_operand:VM 2 "register_operand" "v")
1362 (match_operand:V16QI 3 "register_operand" "v")]
1366 [(set_attr "type" "vecperm")])
1368 (define_insn "altivec_vrfip" ; ceil
1369 [(set (match_operand:V4SF 0 "register_operand" "=v")
1370 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1374 [(set_attr "type" "vecfloat")])
1376 (define_insn "altivec_vrfin"
1377 [(set (match_operand:V4SF 0 "register_operand" "=v")
1378 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1382 [(set_attr "type" "vecfloat")])
1384 (define_insn "*altivec_vrfim" ; floor
1385 [(set (match_operand:V4SF 0 "register_operand" "=v")
1386 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1390 [(set_attr "type" "vecfloat")])
1392 (define_insn "altivec_vcfux"
1393 [(set (match_operand:V4SF 0 "register_operand" "=v")
1394 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1395 (match_operand:QI 2 "immediate_operand" "i")]
1399 [(set_attr "type" "vecfloat")])
1401 (define_insn "altivec_vcfsx"
1402 [(set (match_operand:V4SF 0 "register_operand" "=v")
1403 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1404 (match_operand:QI 2 "immediate_operand" "i")]
1408 [(set_attr "type" "vecfloat")])
1410 (define_insn "altivec_vctuxs"
1411 [(set (match_operand:V4SI 0 "register_operand" "=v")
1412 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1413 (match_operand:QI 2 "immediate_operand" "i")]
1415 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1418 [(set_attr "type" "vecfloat")])
1420 (define_insn "altivec_vctsxs"
1421 [(set (match_operand:V4SI 0 "register_operand" "=v")
1422 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1423 (match_operand:QI 2 "immediate_operand" "i")]
1425 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1428 [(set_attr "type" "vecfloat")])
1430 (define_insn "altivec_vlogefp"
1431 [(set (match_operand:V4SF 0 "register_operand" "=v")
1432 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1436 [(set_attr "type" "vecfloat")])
1438 (define_insn "altivec_vexptefp"
1439 [(set (match_operand:V4SF 0 "register_operand" "=v")
1440 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1444 [(set_attr "type" "vecfloat")])
1446 (define_insn "*altivec_vrsqrtefp"
1447 [(set (match_operand:V4SF 0 "register_operand" "=v")
1448 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1450 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1452 [(set_attr "type" "vecfloat")])
1454 (define_insn "altivec_vrefp"
1455 [(set (match_operand:V4SF 0 "register_operand" "=v")
1456 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1458 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1460 [(set_attr "type" "vecfloat")])
1462 (define_expand "altivec_copysign_v4sf3"
1463 [(use (match_operand:V4SF 0 "register_operand" ""))
1464 (use (match_operand:V4SF 1 "register_operand" ""))
1465 (use (match_operand:V4SF 2 "register_operand" ""))]
1466 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1469 rtx mask = gen_reg_rtx (V4SImode);
1470 rtvec v = rtvec_alloc (4);
1471 unsigned HOST_WIDE_INT mask_val = ((unsigned HOST_WIDE_INT)1) << 31;
1473 RTVEC_ELT (v, 0) = GEN_INT (mask_val);
1474 RTVEC_ELT (v, 1) = GEN_INT (mask_val);
1475 RTVEC_ELT (v, 2) = GEN_INT (mask_val);
1476 RTVEC_ELT (v, 3) = GEN_INT (mask_val);
1478 emit_insn (gen_vec_initv4si (mask, gen_rtx_PARALLEL (V4SImode, v)));
1479 emit_insn (gen_vector_select_v4sf (operands[0], operands[1], operands[2],
1480 gen_lowpart (V4SFmode, mask)));
1484 (define_insn "altivec_vsldoi_<mode>"
1485 [(set (match_operand:VM 0 "register_operand" "=v")
1486 (unspec:VM [(match_operand:VM 1 "register_operand" "v")
1487 (match_operand:VM 2 "register_operand" "v")
1488 (match_operand:QI 3 "immediate_operand" "i")]
1491 "vsldoi %0,%1,%2,%3"
1492 [(set_attr "type" "vecperm")])
1494 (define_insn "altivec_vupkhsb"
1495 [(set (match_operand:V8HI 0 "register_operand" "=v")
1496 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1500 [(set_attr "type" "vecperm")])
1502 (define_insn "altivec_vupkhpx"
1503 [(set (match_operand:V4SI 0 "register_operand" "=v")
1504 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1508 [(set_attr "type" "vecperm")])
1510 (define_insn "altivec_vupkhsh"
1511 [(set (match_operand:V4SI 0 "register_operand" "=v")
1512 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1516 [(set_attr "type" "vecperm")])
1518 (define_insn "altivec_vupklsb"
1519 [(set (match_operand:V8HI 0 "register_operand" "=v")
1520 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1524 [(set_attr "type" "vecperm")])
1526 (define_insn "altivec_vupklpx"
1527 [(set (match_operand:V4SI 0 "register_operand" "=v")
1528 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1532 [(set_attr "type" "vecperm")])
1534 (define_insn "altivec_vupklsh"
1535 [(set (match_operand:V4SI 0 "register_operand" "=v")
1536 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1540 [(set_attr "type" "vecperm")])
1542 ;; Compare vectors producing a vector result and a predicate, setting CR6 to
1543 ;; indicate a combined status
1544 (define_insn "*altivec_vcmpequ<VI_char>_p"
1546 (unspec:CC [(eq:CC (match_operand:VI 1 "register_operand" "v")
1547 (match_operand:VI 2 "register_operand" "v"))]
1549 (set (match_operand:VI 0 "register_operand" "=v")
1550 (eq:VI (match_dup 1)
1552 "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
1553 "vcmpequ<VI_char>. %0,%1,%2"
1554 [(set_attr "type" "veccmp")])
1556 (define_insn "*altivec_vcmpgts<VI_char>_p"
1558 (unspec:CC [(gt:CC (match_operand:VI 1 "register_operand" "v")
1559 (match_operand:VI 2 "register_operand" "v"))]
1561 (set (match_operand:VI 0 "register_operand" "=v")
1562 (gt:VI (match_dup 1)
1564 "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
1565 "vcmpgts<VI_char>. %0,%1,%2"
1566 [(set_attr "type" "veccmp")])
1568 (define_insn "*altivec_vcmpgtu<VI_char>_p"
1570 (unspec:CC [(gtu:CC (match_operand:VI 1 "register_operand" "v")
1571 (match_operand:VI 2 "register_operand" "v"))]
1573 (set (match_operand:VI 0 "register_operand" "=v")
1574 (gtu:VI (match_dup 1)
1576 "VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
1577 "vcmpgtu<VI_char>. %0,%1,%2"
1578 [(set_attr "type" "veccmp")])
1580 (define_insn "*altivec_vcmpeqfp_p"
1582 (unspec:CC [(eq:CC (match_operand:V4SF 1 "register_operand" "v")
1583 (match_operand:V4SF 2 "register_operand" "v"))]
1585 (set (match_operand:V4SF 0 "register_operand" "=v")
1586 (eq:V4SF (match_dup 1)
1588 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1589 "vcmpeqfp. %0,%1,%2"
1590 [(set_attr "type" "veccmp")])
1592 (define_insn "*altivec_vcmpgtfp_p"
1594 (unspec:CC [(gt:CC (match_operand:V4SF 1 "register_operand" "v")
1595 (match_operand:V4SF 2 "register_operand" "v"))]
1597 (set (match_operand:V4SF 0 "register_operand" "=v")
1598 (gt:V4SF (match_dup 1)
1600 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1601 "vcmpgtfp. %0,%1,%2"
1602 [(set_attr "type" "veccmp")])
1604 (define_insn "*altivec_vcmpgefp_p"
1606 (unspec:CC [(ge:CC (match_operand:V4SF 1 "register_operand" "v")
1607 (match_operand:V4SF 2 "register_operand" "v"))]
1609 (set (match_operand:V4SF 0 "register_operand" "=v")
1610 (ge:V4SF (match_dup 1)
1612 "VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
1613 "vcmpgefp. %0,%1,%2"
1614 [(set_attr "type" "veccmp")])
1616 (define_insn "altivec_vcmpbfp_p"
1618 (unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
1619 (match_operand:V4SF 2 "register_operand" "v")]
1621 (set (match_operand:V4SF 0 "register_operand" "=v")
1622 (unspec:V4SF [(match_dup 1)
1625 "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
1627 [(set_attr "type" "veccmp")])
1629 (define_insn "altivec_mtvscr"
1632 [(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
1635 [(set_attr "type" "vecsimple")])
1637 (define_insn "altivec_mfvscr"
1638 [(set (match_operand:V8HI 0 "register_operand" "=v")
1639 (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
1642 [(set_attr "type" "vecsimple")])
1644 (define_insn "altivec_dssall"
1645 [(unspec_volatile [(const_int 0)] UNSPECV_DSSALL)]
1648 [(set_attr "type" "vecsimple")])
1650 (define_insn "altivec_dss"
1651 [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")]
1655 [(set_attr "type" "vecsimple")])
1657 (define_insn "altivec_dst"
1658 [(unspec [(match_operand 0 "register_operand" "b")
1659 (match_operand:SI 1 "register_operand" "r")
1660 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DST)]
1661 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1663 [(set_attr "type" "vecsimple")])
1665 (define_insn "altivec_dstt"
1666 [(unspec [(match_operand 0 "register_operand" "b")
1667 (match_operand:SI 1 "register_operand" "r")
1668 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTT)]
1669 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1671 [(set_attr "type" "vecsimple")])
1673 (define_insn "altivec_dstst"
1674 [(unspec [(match_operand 0 "register_operand" "b")
1675 (match_operand:SI 1 "register_operand" "r")
1676 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTST)]
1677 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1679 [(set_attr "type" "vecsimple")])
1681 (define_insn "altivec_dststt"
1682 [(unspec [(match_operand 0 "register_operand" "b")
1683 (match_operand:SI 1 "register_operand" "r")
1684 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTSTT)]
1685 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1687 [(set_attr "type" "vecsimple")])
1689 (define_insn "altivec_lvsl"
1690 [(set (match_operand:V16QI 0 "register_operand" "=v")
1691 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSL))]
1694 [(set_attr "type" "vecload")])
1696 (define_insn "altivec_lvsr"
1697 [(set (match_operand:V16QI 0 "register_operand" "=v")
1698 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSR))]
1701 [(set_attr "type" "vecload")])
1703 (define_expand "build_vector_mask_for_load"
1704 [(set (match_operand:V16QI 0 "register_operand" "")
1705 (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
1712 gcc_assert (GET_CODE (operands[1]) == MEM);
1714 addr = XEXP (operands[1], 0);
1715 temp = gen_reg_rtx (GET_MODE (addr));
1716 emit_insn (gen_rtx_SET (VOIDmode, temp,
1717 gen_rtx_NEG (GET_MODE (addr), addr)));
1718 emit_insn (gen_altivec_lvsr (operands[0],
1719 replace_equiv_address (operands[1], temp)));
1723 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1724 ;; identical rtl but different instructions-- and gcc gets confused.
1726 (define_insn "altivec_lve<VI_char>x"
1728 [(set (match_operand:VI 0 "register_operand" "=v")
1729 (match_operand:VI 1 "memory_operand" "Z"))
1730 (unspec [(const_int 0)] UNSPEC_LVE)])]
1732 "lve<VI_char>x %0,%y1"
1733 [(set_attr "type" "vecload")])
1735 (define_insn "*altivec_lvesfx"
1737 [(set (match_operand:V4SF 0 "register_operand" "=v")
1738 (match_operand:V4SF 1 "memory_operand" "Z"))
1739 (unspec [(const_int 0)] UNSPEC_LVE)])]
1742 [(set_attr "type" "vecload")])
1744 (define_insn "altivec_lvxl"
1746 [(set (match_operand:V4SI 0 "register_operand" "=v")
1747 (match_operand:V4SI 1 "memory_operand" "Z"))
1748 (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
1751 [(set_attr "type" "vecload")])
1753 (define_insn "altivec_lvx_<mode>"
1755 [(set (match_operand:VM2 0 "register_operand" "=v")
1756 (match_operand:VM2 1 "memory_operand" "Z"))
1757 (unspec [(const_int 0)] UNSPEC_LVX)])]
1760 [(set_attr "type" "vecload")])
1762 (define_insn "altivec_stvx_<mode>"
1764 [(set (match_operand:VM2 0 "memory_operand" "=Z")
1765 (match_operand:VM2 1 "register_operand" "v"))
1766 (unspec [(const_int 0)] UNSPEC_STVX)])]
1769 [(set_attr "type" "vecstore")])
1771 (define_insn "altivec_stvxl"
1773 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1774 (match_operand:V4SI 1 "register_operand" "v"))
1775 (unspec [(const_int 0)] UNSPEC_STVXL)])]
1778 [(set_attr "type" "vecstore")])
1780 (define_insn "altivec_stve<VI_char>x"
1781 [(set (match_operand:<VI_scalar> 0 "memory_operand" "=Z")
1782 (unspec:<VI_scalar> [(match_operand:VI 1 "register_operand" "v")] UNSPEC_STVE))]
1784 "stve<VI_char>x %1,%y0"
1785 [(set_attr "type" "vecstore")])
1787 (define_insn "*altivec_stvesfx"
1788 [(set (match_operand:SF 0 "memory_operand" "=Z")
1789 (unspec:SF [(match_operand:V4SF 1 "register_operand" "v")] UNSPEC_STVE))]
1792 [(set_attr "type" "vecstore")])
1795 ;; vspltis? SCRATCH0,0
1796 ;; vsubu?m SCRATCH2,SCRATCH1,%1
1797 ;; vmaxs? %0,%1,SCRATCH2"
1798 (define_expand "abs<mode>2"
1799 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
1801 (minus:VI (match_dup 2)
1802 (match_operand:VI 1 "register_operand" "v")))
1803 (set (match_operand:VI 0 "register_operand" "=v")
1804 (smax:VI (match_dup 1) (match_dup 3)))]
1807 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
1808 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
1812 ;; vspltisw SCRATCH1,-1
1813 ;; vslw SCRATCH2,SCRATCH1,SCRATCH1
1814 ;; vandc %0,%1,SCRATCH2
1815 (define_expand "altivec_absv4sf2"
1817 (vec_duplicate:V4SI (const_int -1)))
1819 (ashift:V4SI (match_dup 2) (match_dup 2)))
1820 (set (match_operand:V4SF 0 "register_operand" "=v")
1821 (and:V4SF (not:V4SF (subreg:V4SF (match_dup 3) 0))
1822 (match_operand:V4SF 1 "register_operand" "v")))]
1825 operands[2] = gen_reg_rtx (V4SImode);
1826 operands[3] = gen_reg_rtx (V4SImode);
1830 ;; vspltis? SCRATCH0,0
1831 ;; vsubs?s SCRATCH2,SCRATCH1,%1
1832 ;; vmaxs? %0,%1,SCRATCH2"
1833 (define_expand "altivec_abss_<mode>"
1834 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
1835 (parallel [(set (match_dup 3)
1836 (unspec:VI [(match_dup 2)
1837 (match_operand:VI 1 "register_operand" "v")]
1839 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
1840 (set (match_operand:VI 0 "register_operand" "=v")
1841 (smax:VI (match_dup 1) (match_dup 3)))]
1844 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
1845 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
1848 (define_insn "altivec_vsumsws_nomode"
1849 [(set (match_operand 0 "register_operand" "=v")
1850 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1851 (match_operand:V4SI 2 "register_operand" "v")]
1853 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1856 [(set_attr "type" "veccomplex")])
1858 (define_expand "reduc_splus_<mode>"
1859 [(set (match_operand:VIshort 0 "register_operand" "=v")
1860 (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
1861 UNSPEC_REDUC_PLUS))]
1865 rtx vzero = gen_reg_rtx (V4SImode);
1866 rtx vtmp1 = gen_reg_rtx (V4SImode);
1868 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
1869 emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
1870 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
1874 (define_expand "reduc_uplus_v16qi"
1875 [(set (match_operand:V16QI 0 "register_operand" "=v")
1876 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
1877 UNSPEC_REDUC_PLUS))]
1881 rtx vzero = gen_reg_rtx (V4SImode);
1882 rtx vtmp1 = gen_reg_rtx (V4SImode);
1884 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
1885 emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
1886 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
1890 (define_expand "neg<mode>2"
1891 [(use (match_operand:VI 0 "register_operand" ""))
1892 (use (match_operand:VI 1 "register_operand" ""))]
1898 vzero = gen_reg_rtx (GET_MODE (operands[0]));
1899 emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx));
1900 emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1]));
1905 (define_expand "udot_prod<mode>"
1906 [(set (match_operand:V4SI 0 "register_operand" "=v")
1907 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
1908 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1909 (match_operand:VIshort 2 "register_operand" "v")]
1914 emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3]));
1918 (define_expand "sdot_prodv8hi"
1919 [(set (match_operand:V4SI 0 "register_operand" "=v")
1920 (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
1921 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1922 (match_operand:V8HI 2 "register_operand" "v")]
1927 emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
1931 (define_expand "widen_usum<mode>3"
1932 [(set (match_operand:V4SI 0 "register_operand" "=v")
1933 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
1934 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
1939 rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
1941 emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx));
1942 emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2]));
1946 (define_expand "widen_ssumv16qi3"
1947 [(set (match_operand:V4SI 0 "register_operand" "=v")
1948 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
1949 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
1954 rtx vones = gen_reg_rtx (V16QImode);
1956 emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
1957 emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
1961 (define_expand "widen_ssumv8hi3"
1962 [(set (match_operand:V4SI 0 "register_operand" "=v")
1963 (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
1964 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1969 rtx vones = gen_reg_rtx (V8HImode);
1971 emit_insn (gen_altivec_vspltish (vones, const1_rtx));
1972 emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
1976 (define_expand "vec_unpacks_hi_v16qi"
1977 [(set (match_operand:V8HI 0 "register_operand" "=v")
1978 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1983 emit_insn (gen_altivec_vupkhsb (operands[0], operands[1]));
1987 (define_expand "vec_unpacks_hi_v8hi"
1988 [(set (match_operand:V4SI 0 "register_operand" "=v")
1989 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1994 emit_insn (gen_altivec_vupkhsh (operands[0], operands[1]));
1998 (define_expand "vec_unpacks_lo_v16qi"
1999 [(set (match_operand:V8HI 0 "register_operand" "=v")
2000 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2005 emit_insn (gen_altivec_vupklsb (operands[0], operands[1]));
2009 (define_expand "vec_unpacks_lo_v8hi"
2010 [(set (match_operand:V4SI 0 "register_operand" "=v")
2011 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2016 emit_insn (gen_altivec_vupklsh (operands[0], operands[1]));
2020 (define_insn "vperm_v8hiv4si"
2021 [(set (match_operand:V4SI 0 "register_operand" "=v")
2022 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2023 (match_operand:V4SI 2 "register_operand" "v")
2024 (match_operand:V16QI 3 "register_operand" "v")]
2028 [(set_attr "type" "vecperm")])
2030 (define_insn "vperm_v16qiv8hi"
2031 [(set (match_operand:V8HI 0 "register_operand" "=v")
2032 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2033 (match_operand:V8HI 2 "register_operand" "v")
2034 (match_operand:V16QI 3 "register_operand" "v")]
2038 [(set_attr "type" "vecperm")])
2041 (define_expand "vec_unpacku_hi_v16qi"
2042 [(set (match_operand:V8HI 0 "register_operand" "=v")
2043 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2048 rtx vzero = gen_reg_rtx (V8HImode);
2049 rtx mask = gen_reg_rtx (V16QImode);
2050 rtvec v = rtvec_alloc (16);
2052 emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2054 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2055 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 0);
2056 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2057 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2058 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2059 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 2);
2060 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2061 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2062 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2063 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 4);
2064 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2065 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2066 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2067 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 6);
2068 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2069 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2071 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2072 emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2076 (define_expand "vec_unpacku_hi_v8hi"
2077 [(set (match_operand:V4SI 0 "register_operand" "=v")
2078 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2083 rtx vzero = gen_reg_rtx (V4SImode);
2084 rtx mask = gen_reg_rtx (V16QImode);
2085 rtvec v = rtvec_alloc (16);
2087 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2089 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2090 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2091 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 0);
2092 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2093 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2094 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2095 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 2);
2096 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2097 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2098 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2099 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 4);
2100 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2101 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2102 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2103 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 6);
2104 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2106 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2107 emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2111 (define_expand "vec_unpacku_lo_v16qi"
2112 [(set (match_operand:V8HI 0 "register_operand" "=v")
2113 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2118 rtx vzero = gen_reg_rtx (V8HImode);
2119 rtx mask = gen_reg_rtx (V16QImode);
2120 rtvec v = rtvec_alloc (16);
2122 emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2124 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2125 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 8);
2126 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2127 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2128 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2129 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2130 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2131 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2132 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2133 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 12);
2134 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2135 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2136 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2137 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 14);
2138 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2139 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2141 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2142 emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2146 (define_expand "vec_unpacku_lo_v8hi"
2147 [(set (match_operand:V4SI 0 "register_operand" "=v")
2148 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2153 rtx vzero = gen_reg_rtx (V4SImode);
2154 rtx mask = gen_reg_rtx (V16QImode);
2155 rtvec v = rtvec_alloc (16);
2157 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2159 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2160 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2161 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 8);
2162 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2163 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2164 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2165 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2166 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2167 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2168 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2169 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 12);
2170 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2171 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2172 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2173 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 14);
2174 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2176 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2177 emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2181 (define_expand "vec_widen_umult_hi_v16qi"
2182 [(set (match_operand:V8HI 0 "register_operand" "=v")
2183 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2184 (match_operand:V16QI 2 "register_operand" "v")]
2189 rtx ve = gen_reg_rtx (V8HImode);
2190 rtx vo = gen_reg_rtx (V8HImode);
2192 emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2193 emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2194 emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2198 (define_expand "vec_widen_umult_lo_v16qi"
2199 [(set (match_operand:V8HI 0 "register_operand" "=v")
2200 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2201 (match_operand:V16QI 2 "register_operand" "v")]
2206 rtx ve = gen_reg_rtx (V8HImode);
2207 rtx vo = gen_reg_rtx (V8HImode);
2209 emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2210 emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2211 emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2215 (define_expand "vec_widen_smult_hi_v16qi"
2216 [(set (match_operand:V8HI 0 "register_operand" "=v")
2217 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2218 (match_operand:V16QI 2 "register_operand" "v")]
2223 rtx ve = gen_reg_rtx (V8HImode);
2224 rtx vo = gen_reg_rtx (V8HImode);
2226 emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2227 emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2228 emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2232 (define_expand "vec_widen_smult_lo_v16qi"
2233 [(set (match_operand:V8HI 0 "register_operand" "=v")
2234 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2235 (match_operand:V16QI 2 "register_operand" "v")]
2240 rtx ve = gen_reg_rtx (V8HImode);
2241 rtx vo = gen_reg_rtx (V8HImode);
2243 emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2244 emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2245 emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2249 (define_expand "vec_widen_umult_hi_v8hi"
2250 [(set (match_operand:V4SI 0 "register_operand" "=v")
2251 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2252 (match_operand:V8HI 2 "register_operand" "v")]
2257 rtx ve = gen_reg_rtx (V4SImode);
2258 rtx vo = gen_reg_rtx (V4SImode);
2260 emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2261 emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2262 emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2266 (define_expand "vec_widen_umult_lo_v8hi"
2267 [(set (match_operand:V4SI 0 "register_operand" "=v")
2268 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2269 (match_operand:V8HI 2 "register_operand" "v")]
2274 rtx ve = gen_reg_rtx (V4SImode);
2275 rtx vo = gen_reg_rtx (V4SImode);
2277 emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2278 emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2279 emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2283 (define_expand "vec_widen_smult_hi_v8hi"
2284 [(set (match_operand:V4SI 0 "register_operand" "=v")
2285 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2286 (match_operand:V8HI 2 "register_operand" "v")]
2291 rtx ve = gen_reg_rtx (V4SImode);
2292 rtx vo = gen_reg_rtx (V4SImode);
2294 emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2295 emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2296 emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2300 (define_expand "vec_widen_smult_lo_v8hi"
2301 [(set (match_operand:V4SI 0 "register_operand" "=v")
2302 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2303 (match_operand:V8HI 2 "register_operand" "v")]
2308 rtx ve = gen_reg_rtx (V4SImode);
2309 rtx vo = gen_reg_rtx (V4SImode);
2311 emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2312 emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2313 emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2317 (define_expand "vec_pack_trunc_v8hi"
2318 [(set (match_operand:V16QI 0 "register_operand" "=v")
2319 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
2320 (match_operand:V8HI 2 "register_operand" "v")]
2325 emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2]));
2329 (define_expand "vec_pack_trunc_v4si"
2330 [(set (match_operand:V8HI 0 "register_operand" "=v")
2331 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
2332 (match_operand:V4SI 2 "register_operand" "v")]
2337 emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2]));
2341 (define_expand "altivec_negv4sf2"
2342 [(use (match_operand:V4SF 0 "register_operand" ""))
2343 (use (match_operand:V4SF 1 "register_operand" ""))]
2349 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
2350 neg0 = gen_reg_rtx (V4SImode);
2351 emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
2352 emit_insn (gen_vashlv4si3 (neg0, neg0, neg0));
2355 emit_insn (gen_xorv4sf3 (operands[0],
2356 gen_lowpart (V4SFmode, neg0), operands[1]));
2361 ;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL,
2362 ;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell.
2363 (define_insn "altivec_lvlx"
2364 [(set (match_operand:V16QI 0 "register_operand" "=v")
2365 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
2367 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2369 [(set_attr "type" "vecload")])
2371 (define_insn "altivec_lvlxl"
2372 [(set (match_operand:V16QI 0 "register_operand" "=v")
2373 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
2375 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2377 [(set_attr "type" "vecload")])
2379 (define_insn "altivec_lvrx"
2380 [(set (match_operand:V16QI 0 "register_operand" "=v")
2381 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
2383 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2385 [(set_attr "type" "vecload")])
2387 (define_insn "altivec_lvrxl"
2388 [(set (match_operand:V16QI 0 "register_operand" "=v")
2389 (unspec:V16QI [(match_operand 1 "memory_operand" "Z")]
2391 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2393 [(set_attr "type" "vecload")])
2395 (define_insn "altivec_stvlx"
2397 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
2398 (match_operand:V4SI 1 "register_operand" "v"))
2399 (unspec [(const_int 0)] UNSPEC_STVLX)])]
2400 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2402 [(set_attr "type" "vecstore")])
2404 (define_insn "altivec_stvlxl"
2406 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
2407 (match_operand:V4SI 1 "register_operand" "v"))
2408 (unspec [(const_int 0)] UNSPEC_STVLXL)])]
2409 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2411 [(set_attr "type" "vecstore")])
2413 (define_insn "altivec_stvrx"
2415 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
2416 (match_operand:V4SI 1 "register_operand" "v"))
2417 (unspec [(const_int 0)] UNSPEC_STVRX)])]
2418 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2420 [(set_attr "type" "vecstore")])
2422 (define_insn "altivec_stvrxl"
2424 [(set (match_operand:V4SI 0 "memory_operand" "=Z")
2425 (match_operand:V4SI 1 "register_operand" "v"))
2426 (unspec [(const_int 0)] UNSPEC_STVRXL)])]
2427 "TARGET_ALTIVEC && rs6000_cpu == PROCESSOR_CELL"
2429 [(set_attr "type" "vecstore")])
2431 (define_expand "vec_extract_evenv4si"
2432 [(set (match_operand:V4SI 0 "register_operand" "")
2433 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
2434 (match_operand:V4SI 2 "register_operand" "")]
2435 UNSPEC_EXTEVEN_V4SI))]
2439 rtx mask = gen_reg_rtx (V16QImode);
2440 rtvec v = rtvec_alloc (16);
2442 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2443 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2444 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
2445 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
2446 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2447 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2448 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2449 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2450 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2451 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2452 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
2453 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
2454 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2455 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2456 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
2457 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
2458 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2459 emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
2464 (define_expand "vec_extract_evenv4sf"
2465 [(set (match_operand:V4SF 0 "register_operand" "")
2466 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
2467 (match_operand:V4SF 2 "register_operand" "")]
2468 UNSPEC_EXTEVEN_V4SF))]
2472 rtx mask = gen_reg_rtx (V16QImode);
2473 rtvec v = rtvec_alloc (16);
2475 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2476 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2477 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 2);
2478 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 3);
2479 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2480 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2481 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2482 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2483 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2484 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2485 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 18);
2486 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 19);
2487 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2488 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2489 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 26);
2490 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 27);
2491 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2492 emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
2497 (define_expand "vec_extract_evenv8hi"
2498 [(set (match_operand:V4SI 0 "register_operand" "")
2499 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
2500 (match_operand:V8HI 2 "register_operand" "")]
2501 UNSPEC_EXTEVEN_V8HI))]
2505 rtx mask = gen_reg_rtx (V16QImode);
2506 rtvec v = rtvec_alloc (16);
2508 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2509 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 1);
2510 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
2511 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 5);
2512 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2513 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 9);
2514 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
2515 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 13);
2516 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2517 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2518 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
2519 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 21);
2520 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2521 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 25);
2522 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
2523 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 29);
2524 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2525 emit_insn (gen_altivec_vperm_v8hi (operands[0], operands[1], operands[2], mask));
2530 (define_expand "vec_extract_evenv16qi"
2531 [(set (match_operand:V4SI 0 "register_operand" "")
2532 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "")
2533 (match_operand:V16QI 2 "register_operand" "")]
2534 UNSPEC_EXTEVEN_V16QI))]
2538 rtx mask = gen_reg_rtx (V16QImode);
2539 rtvec v = rtvec_alloc (16);
2541 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 0);
2542 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 2);
2543 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 4);
2544 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 6);
2545 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 8);
2546 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2547 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 12);
2548 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 14);
2549 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2550 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 18);
2551 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 20);
2552 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 22);
2553 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 24);
2554 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 26);
2555 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 28);
2556 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 30);
2557 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2558 emit_insn (gen_altivec_vperm_v16qi (operands[0], operands[1], operands[2], mask));
2563 (define_expand "vec_extract_oddv4si"
2564 [(set (match_operand:V4SI 0 "register_operand" "")
2565 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "")
2566 (match_operand:V4SI 2 "register_operand" "")]
2567 UNSPEC_EXTODD_V4SI))]
2571 rtx mask = gen_reg_rtx (V16QImode);
2572 rtvec v = rtvec_alloc (16);
2574 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
2575 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
2576 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
2577 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
2578 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
2579 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
2580 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
2581 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
2582 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
2583 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
2584 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
2585 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
2586 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
2587 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
2588 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
2589 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
2590 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2591 emit_insn (gen_altivec_vperm_v4si (operands[0], operands[1], operands[2], mask));
2596 (define_expand "vec_extract_oddv4sf"
2597 [(set (match_operand:V4SF 0 "register_operand" "")
2598 (unspec:V8HI [(match_operand:V4SF 1 "register_operand" "")
2599 (match_operand:V4SF 2 "register_operand" "")]
2600 UNSPEC_EXTODD_V4SF))]
2604 rtx mask = gen_reg_rtx (V16QImode);
2605 rtvec v = rtvec_alloc (16);
2607 RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 4);
2608 RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 5);
2609 RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 6);
2610 RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 7);
2611 RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 12);
2612 RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 13);
2613 RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 14);
2614 RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 15);
2615 RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 20);
2616 RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 21);
2617 RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 22);
2618 RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 23);
2619 RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 28);
2620 RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 29);
2621 RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 30);
2622 RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 31);
2623 emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2624 emit_insn (gen_altivec_vperm_v4sf (operands[0], operands[1], operands[2], mask));
2629 (define_insn "vpkuhum_nomode"
2630 [(set (match_operand:V16QI 0 "register_operand" "=v")
2631 (unspec:V16QI [(match_operand 1 "register_operand" "v")
2632 (match_operand 2 "register_operand" "v")]
2636 [(set_attr "type" "vecperm")])
2638 (define_insn "vpkuwum_nomode"
2639 [(set (match_operand:V8HI 0 "register_operand" "=v")
2640 (unspec:V8HI [(match_operand 1 "register_operand" "v")
2641 (match_operand 2 "register_operand" "v")]
2645 [(set_attr "type" "vecperm")])
2647 (define_expand "vec_extract_oddv8hi"
2648 [(set (match_operand:V8HI 0 "register_operand" "")
2649 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "")
2650 (match_operand:V8HI 2 "register_operand" "")]
2651 UNSPEC_EXTODD_V8HI))]
2655 emit_insn (gen_vpkuwum_nomode (operands[0], operands[1], operands[2]));
2659 (define_expand "vec_extract_oddv16qi"
2660 [(set (match_operand:V16QI 0 "register_operand" "")
2661 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
2662 (match_operand:V16QI 2 "register_operand" "")]
2663 UNSPEC_EXTODD_V16QI))]
2667 emit_insn (gen_vpkuhum_nomode (operands[0], operands[1], operands[2]));
2671 (define_expand "vec_interleave_high<mode>"
2672 [(set (match_operand:VI 0 "register_operand" "")
2673 (unspec:VI [(match_operand:VI 1 "register_operand" "")
2674 (match_operand:VI 2 "register_operand" "")]
2679 emit_insn (gen_altivec_vmrgh<VI_char> (operands[0], operands[1], operands[2]));
2683 (define_expand "vec_interleave_low<mode>"
2684 [(set (match_operand:VI 0 "register_operand" "")
2685 (unspec:VI [(match_operand:VI 1 "register_operand" "")
2686 (match_operand:VI 2 "register_operand" "")]
2691 emit_insn (gen_altivec_vmrgl<VI_char> (operands[0], operands[1], operands[2]));
2695 (define_expand "vec_unpacks_float_hi_v8hi"
2696 [(set (match_operand:V4SF 0 "register_operand" "")
2697 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
2698 UNSPEC_VUPKHS_V4SF))]
2702 rtx tmp = gen_reg_rtx (V4SImode);
2704 emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
2705 emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
2709 (define_expand "vec_unpacks_float_lo_v8hi"
2710 [(set (match_operand:V4SF 0 "register_operand" "")
2711 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
2712 UNSPEC_VUPKLS_V4SF))]
2716 rtx tmp = gen_reg_rtx (V4SImode);
2718 emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
2719 emit_insn (gen_altivec_vcfsx (operands[0], tmp, const0_rtx));
2723 (define_expand "vec_unpacku_float_hi_v8hi"
2724 [(set (match_operand:V4SF 0 "register_operand" "")
2725 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
2726 UNSPEC_VUPKHU_V4SF))]
2730 rtx tmp = gen_reg_rtx (V4SImode);
2732 emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
2733 emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));
2737 (define_expand "vec_unpacku_float_lo_v8hi"
2738 [(set (match_operand:V4SF 0 "register_operand" "")
2739 (unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
2740 UNSPEC_VUPKLU_V4SF))]
2744 rtx tmp = gen_reg_rtx (V4SImode);
2746 emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
2747 emit_insn (gen_altivec_vcfux (operands[0], tmp, const0_rtx));