1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; Millicode call delay slot description.
109 (define_delay (eq_attr "type" "milli")
110 [(eq_attr "in_call_delay" "true") (nil) (nil)])
112 ;; Return and other similar instructions.
113 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
114 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
116 ;; Floating point conditional branch delay slot description and
117 (define_delay (eq_attr "type" "fbranch")
118 [(eq_attr "in_branch_delay" "true")
119 (eq_attr "in_nullified_branch_delay" "true")
122 ;; Integer conditional branch delay slot description.
123 ;; Nullification of conditional branches on the PA is dependent on the
124 ;; direction of the branch. Forward branches nullify true and
125 ;; backward branches nullify false. If the direction is unknown
126 ;; then nullification is not allowed.
127 (define_delay (eq_attr "type" "cbranch")
128 [(eq_attr "in_branch_delay" "true")
129 (and (eq_attr "in_nullified_branch_delay" "true")
130 (attr_flag "forward"))
131 (and (eq_attr "in_nullified_branch_delay" "true")
132 (attr_flag "backward"))])
134 (define_delay (and (eq_attr "type" "uncond_branch")
135 (eq (symbol_ref "following_call (insn)")
137 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
139 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
140 ;; load: 2, fpload: 3
141 ;; store, fpstore: 3, no D-cache operations should be scheduled.
143 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
145 ;; Instruction Time Unit Minimum Distance (unit contention)
152 ;; fmpyadd 3 ALU,MPY 2
153 ;; fmpysub 3 ALU,MPY 2
154 ;; fmpycfxt 3 ALU,MPY 2
157 ;; fdiv,sgl 10 MPY 10
158 ;; fdiv,dbl 12 MPY 12
159 ;; fsqrt,sgl 14 MPY 14
160 ;; fsqrt,dbl 18 MPY 18
162 ;; We don't model fmpyadd/fmpysub properly as those instructions
163 ;; keep both the FP ALU and MPY units busy. Given that these
164 ;; processors are obsolete, I'm not going to spend the time to
165 ;; model those instructions correctly.
167 (define_automaton "pa700")
168 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
170 (define_insn_reservation "W0" 4
171 (and (eq_attr "type" "fpcc")
172 (eq_attr "cpu" "700"))
175 (define_insn_reservation "W1" 3
176 (and (eq_attr "type" "fpalu")
177 (eq_attr "cpu" "700"))
180 (define_insn_reservation "W2" 3
181 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
182 (eq_attr "cpu" "700"))
185 (define_insn_reservation "W3" 10
186 (and (eq_attr "type" "fpdivsgl")
187 (eq_attr "cpu" "700"))
190 (define_insn_reservation "W4" 12
191 (and (eq_attr "type" "fpdivdbl")
192 (eq_attr "cpu" "700"))
195 (define_insn_reservation "W5" 14
196 (and (eq_attr "type" "fpsqrtsgl")
197 (eq_attr "cpu" "700"))
200 (define_insn_reservation "W6" 18
201 (and (eq_attr "type" "fpsqrtdbl")
202 (eq_attr "cpu" "700"))
205 (define_insn_reservation "W7" 2
206 (and (eq_attr "type" "load")
207 (eq_attr "cpu" "700"))
210 (define_insn_reservation "W8" 2
211 (and (eq_attr "type" "fpload")
212 (eq_attr "cpu" "700"))
215 (define_insn_reservation "W9" 3
216 (and (eq_attr "type" "store")
217 (eq_attr "cpu" "700"))
220 (define_insn_reservation "W10" 3
221 (and (eq_attr "type" "fpstore")
222 (eq_attr "cpu" "700"))
225 (define_insn_reservation "W11" 1
226 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
227 (eq_attr "cpu" "700"))
230 ;; We have a bypass for all computations in the FP unit which feed an
231 ;; FP store as long as the sizes are the same.
232 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
233 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
234 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
235 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
236 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
238 ;; We have an "anti-bypass" for FP loads which feed an FP store.
239 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
241 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
242 ;; floating point computations with non-floating point computations (fp loads
243 ;; and stores are not fp computations).
245 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
246 ;; take two cycles, during which no Dcache operations should be scheduled.
247 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
248 ;; all have the same memory characteristics if one disregards cache misses.
250 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
251 ;; There's no value in modeling the ALU and MUL separately though
252 ;; since there can never be a functional unit conflict given the
253 ;; latency and issue rates for those units.
256 ;; Instruction Time Unit Minimum Distance (unit contention)
263 ;; fmpyadd 2 ALU,MPY 1
264 ;; fmpysub 2 ALU,MPY 1
265 ;; fmpycfxt 2 ALU,MPY 1
269 ;; fdiv,dbl 15 DIV 15
271 ;; fsqrt,dbl 15 DIV 15
273 (define_automaton "pa7100")
274 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
276 (define_insn_reservation "X0" 2
277 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
278 (eq_attr "cpu" "7100"))
281 (define_insn_reservation "X1" 8
282 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
283 (eq_attr "cpu" "7100"))
284 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
286 (define_insn_reservation "X2" 15
287 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
288 (eq_attr "cpu" "7100"))
289 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
291 (define_insn_reservation "X3" 2
292 (and (eq_attr "type" "load")
293 (eq_attr "cpu" "7100"))
296 (define_insn_reservation "X4" 2
297 (and (eq_attr "type" "fpload")
298 (eq_attr "cpu" "7100"))
301 (define_insn_reservation "X5" 2
302 (and (eq_attr "type" "store")
303 (eq_attr "cpu" "7100"))
304 "i_7100+mem_7100,mem_7100")
306 (define_insn_reservation "X6" 2
307 (and (eq_attr "type" "fpstore")
308 (eq_attr "cpu" "7100"))
309 "i_7100+mem_7100,mem_7100")
311 (define_insn_reservation "X7" 1
312 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
313 (eq_attr "cpu" "7100"))
316 ;; We have a bypass for all computations in the FP unit which feed an
317 ;; FP store as long as the sizes are the same.
318 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
319 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
320 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
322 ;; We have an "anti-bypass" for FP loads which feed an FP store.
323 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
325 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
326 ;; There's no value in modeling the ALU and MUL separately though
327 ;; since there can never be a functional unit conflict that
328 ;; can be avoided given the latency, issue rates and mandatory
329 ;; one cycle cpu-wide lock for a double precision fp multiply.
332 ;; Instruction Time Unit Minimum Distance (unit contention)
339 ;; fmpyadd,sgl 2 ALU,MPY 1
340 ;; fmpyadd,dbl 3 ALU,MPY 2
341 ;; fmpysub,sgl 2 ALU,MPY 1
342 ;; fmpysub,dbl 3 ALU,MPY 2
343 ;; fmpycfxt,sgl 2 ALU,MPY 1
344 ;; fmpycfxt,dbl 3 ALU,MPY 2
349 ;; fdiv,dbl 15 DIV 15
351 ;; fsqrt,dbl 15 DIV 15
353 ;; The PA7200 is just like the PA7100LC except that there is
354 ;; no store-store penalty.
356 ;; The PA7300 is just like the PA7200 except that there is
357 ;; no store-load penalty.
359 ;; Note there are some aspects of the 7100LC we are not modeling
360 ;; at the moment. I'll be reviewing the 7100LC scheduling info
361 ;; shortly and updating this description.
365 ;; other issue modeling
367 (define_automaton "pa7100lc")
368 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
369 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
370 (define_cpu_unit "mem_7100lc" "pa7100lc")
372 ;; Double precision multiplies lock the entire CPU for one
373 ;; cycle. There is no way to avoid this lock and trying to
374 ;; schedule around the lock is pointless and thus there is no
375 ;; value in trying to model this lock.
377 ;; Not modeling the lock allows us to treat fp multiplies just
378 ;; like any other FP alu instruction. It allows for a smaller
379 ;; DFA and may reduce register pressure.
380 (define_insn_reservation "Y0" 2
381 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
382 (eq_attr "cpu" "7100LC,7200,7300"))
383 "f_7100lc,fpmac_7100lc")
385 ;; fp division and sqrt instructions lock the entire CPU for
386 ;; 7 cycles (single precision) or 14 cycles (double precision).
387 ;; There is no way to avoid this lock and trying to schedule
388 ;; around the lock is pointless and thus there is no value in
389 ;; trying to model this lock. Not modeling the lock allows
390 ;; for a smaller DFA and may reduce register pressure.
391 (define_insn_reservation "Y1" 1
392 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
393 (eq_attr "cpu" "7100LC,7200,7300"))
396 (define_insn_reservation "Y2" 2
397 (and (eq_attr "type" "load")
398 (eq_attr "cpu" "7100LC,7200,7300"))
399 "i1_7100lc+mem_7100lc")
401 (define_insn_reservation "Y3" 2
402 (and (eq_attr "type" "fpload")
403 (eq_attr "cpu" "7100LC,7200,7300"))
404 "i1_7100lc+mem_7100lc")
406 (define_insn_reservation "Y4" 2
407 (and (eq_attr "type" "store")
408 (eq_attr "cpu" "7100LC"))
409 "i1_7100lc+mem_7100lc,mem_7100lc")
411 (define_insn_reservation "Y5" 2
412 (and (eq_attr "type" "fpstore")
413 (eq_attr "cpu" "7100LC"))
414 "i1_7100lc+mem_7100lc,mem_7100lc")
416 (define_insn_reservation "Y6" 1
417 (and (eq_attr "type" "shift,nullshift")
418 (eq_attr "cpu" "7100LC,7200,7300"))
421 (define_insn_reservation "Y7" 1
422 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
423 (eq_attr "cpu" "7100LC,7200,7300"))
424 "(i0_7100lc|i1_7100lc)")
426 ;; The 7200 has a store-load penalty
427 (define_insn_reservation "Y8" 2
428 (and (eq_attr "type" "store")
429 (eq_attr "cpu" "7200"))
430 "i1_7100lc,mem_7100lc")
432 (define_insn_reservation "Y9" 2
433 (and (eq_attr "type" "fpstore")
434 (eq_attr "cpu" "7200"))
435 "i1_7100lc,mem_7100lc")
437 ;; The 7300 has no penalty for store-store or store-load
438 (define_insn_reservation "Y10" 2
439 (and (eq_attr "type" "store")
440 (eq_attr "cpu" "7300"))
443 (define_insn_reservation "Y11" 2
444 (and (eq_attr "type" "fpstore")
445 (eq_attr "cpu" "7300"))
448 ;; We have an "anti-bypass" for FP loads which feed an FP store.
449 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
451 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
452 ;; traditional architecture.
454 ;; The PA8000 has a large (56) entry reorder buffer that is split between
455 ;; memory and non-memory operations.
457 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
458 ;; the function units, with the exception of branches and multi-output
459 ;; instructions. The PA8000 can retire two non-memory operations per cycle
460 ;; and two memory operations per cycle, only one of which may be a store.
462 ;; Given the large reorder buffer, the processor can hide most latencies.
463 ;; According to HP, they've got the best results by scheduling for retirement
464 ;; bandwidth with limited latency scheduling for floating point operations.
465 ;; Latency for integer operations and memory references is ignored.
468 ;; We claim floating point operations have a 2 cycle latency and are
469 ;; fully pipelined, except for div and sqrt which are not pipelined and
470 ;; take from 17 to 31 cycles to complete.
472 ;; It's worth noting that there is no way to saturate all the functional
473 ;; units on the PA8000 as there is not enough issue bandwidth.
475 (define_automaton "pa8000")
476 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
477 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
478 (define_cpu_unit "store_8000" "pa8000")
479 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
480 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
481 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
482 (define_reservation "im_8000" "im0_8000 | im1_8000")
483 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
484 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
485 (define_reservation "f_8000" "f0_8000 | f1_8000")
486 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
488 ;; We can issue any two memops per cycle, but we can only retire
489 ;; one memory store per cycle. We assume that the reorder buffer
490 ;; will hide any memory latencies per HP's recommendation.
491 (define_insn_reservation "Z0" 0
493 (eq_attr "type" "load,fpload")
494 (eq_attr "cpu" "8000"))
497 (define_insn_reservation "Z1" 0
499 (eq_attr "type" "store,fpstore")
500 (eq_attr "cpu" "8000"))
501 "im_8000,rm_8000+store_8000")
503 ;; We can issue and retire two non-memory operations per cycle with
504 ;; a few exceptions (branches). This group catches those we want
505 ;; to assume have zero latency.
506 (define_insn_reservation "Z2" 0
508 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
509 (eq_attr "cpu" "8000"))
512 ;; Branches use both slots in the non-memory issue and
514 (define_insn_reservation "Z3" 0
516 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
517 (eq_attr "cpu" "8000"))
518 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
520 ;; We partial latency schedule the floating point units.
521 ;; They can issue/retire two at a time in the non-memory
522 ;; units. We fix their latency at 2 cycles and they
523 ;; are fully pipelined.
524 (define_insn_reservation "Z4" 1
526 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
527 (eq_attr "cpu" "8000"))
528 "inm_8000,f_8000,rnm_8000")
530 ;; The fdivsqrt units are not pipelined and have a very long latency.
531 ;; To keep the DFA from exploding, we do not show all the
532 ;; reservations for the divsqrt unit.
533 (define_insn_reservation "Z5" 17
535 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
536 (eq_attr "cpu" "8000"))
537 "inm_8000,fdivsqrt_8000*6,rnm_8000")
539 (define_insn_reservation "Z6" 31
541 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
542 (eq_attr "cpu" "8000"))
543 "inm_8000,fdivsqrt_8000*6,rnm_8000")
547 ;; Compare instructions.
548 ;; This controls RTL generation and register allocation.
550 ;; We generate RTL for comparisons and branches by having the cmpxx
551 ;; patterns store away the operands. Then, the scc and bcc patterns
552 ;; emit RTL for both the compare and the branch.
555 (define_expand "cmpdi"
557 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
558 (match_operand:DI 1 "register_operand" "")))]
563 hppa_compare_op0 = operands[0];
564 hppa_compare_op1 = operands[1];
565 hppa_branch_type = CMP_SI;
569 (define_expand "cmpsi"
571 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
572 (match_operand:SI 1 "arith5_operand" "")))]
576 hppa_compare_op0 = operands[0];
577 hppa_compare_op1 = operands[1];
578 hppa_branch_type = CMP_SI;
582 (define_expand "cmpsf"
584 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
585 (match_operand:SF 1 "reg_or_0_operand" "")))]
586 "! TARGET_SOFT_FLOAT"
589 hppa_compare_op0 = operands[0];
590 hppa_compare_op1 = operands[1];
591 hppa_branch_type = CMP_SF;
595 (define_expand "cmpdf"
597 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
598 (match_operand:DF 1 "reg_or_0_operand" "")))]
599 "! TARGET_SOFT_FLOAT"
602 hppa_compare_op0 = operands[0];
603 hppa_compare_op1 = operands[1];
604 hppa_branch_type = CMP_DF;
610 (match_operator:CCFP 2 "comparison_operator"
611 [(match_operand:SF 0 "reg_or_0_operand" "fG")
612 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
613 "! TARGET_SOFT_FLOAT"
614 "fcmp,sgl,%Y2 %f0,%f1"
615 [(set_attr "length" "4")
616 (set_attr "type" "fpcc")])
620 (match_operator:CCFP 2 "comparison_operator"
621 [(match_operand:DF 0 "reg_or_0_operand" "fG")
622 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
623 "! TARGET_SOFT_FLOAT"
624 "fcmp,dbl,%Y2 %f0,%f1"
625 [(set_attr "length" "4")
626 (set_attr "type" "fpcc")])
628 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
629 ;; placeholders. This is necessary in rare situations when a
630 ;; placeholder is re-emitted (see PR 8705).
632 (define_expand "movccfp"
634 (match_operand 0 "const_int_operand" ""))]
635 "! TARGET_SOFT_FLOAT"
638 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
642 ;; The following patterns are optimization placeholders. In almost
643 ;; all cases, the user of the condition code will be simplified and the
644 ;; original condition code setting insn should be eliminated.
646 (define_insn "*movccfp0"
649 "! TARGET_SOFT_FLOAT"
650 "fcmp,dbl,= %%fr0,%%fr0"
651 [(set_attr "length" "4")
652 (set_attr "type" "fpcc")])
654 (define_insn "*movccfp1"
657 "! TARGET_SOFT_FLOAT"
658 "fcmp,dbl,!= %%fr0,%%fr0"
659 [(set_attr "length" "4")
660 (set_attr "type" "fpcc")])
665 [(set (match_operand:SI 0 "register_operand" "")
671 /* fp scc patterns rarely match, and are not a win on the PA. */
672 if (hppa_branch_type != CMP_SI)
674 /* set up operands from compare. */
675 operands[1] = hppa_compare_op0;
676 operands[2] = hppa_compare_op1;
677 /* fall through and generate default code */
681 [(set (match_operand:SI 0 "register_operand" "")
687 /* fp scc patterns rarely match, and are not a win on the PA. */
688 if (hppa_branch_type != CMP_SI)
690 operands[1] = hppa_compare_op0;
691 operands[2] = hppa_compare_op1;
695 [(set (match_operand:SI 0 "register_operand" "")
701 /* fp scc patterns rarely match, and are not a win on the PA. */
702 if (hppa_branch_type != CMP_SI)
704 operands[1] = hppa_compare_op0;
705 operands[2] = hppa_compare_op1;
709 [(set (match_operand:SI 0 "register_operand" "")
715 /* fp scc patterns rarely match, and are not a win on the PA. */
716 if (hppa_branch_type != CMP_SI)
718 operands[1] = hppa_compare_op0;
719 operands[2] = hppa_compare_op1;
723 [(set (match_operand:SI 0 "register_operand" "")
729 /* fp scc patterns rarely match, and are not a win on the PA. */
730 if (hppa_branch_type != CMP_SI)
732 operands[1] = hppa_compare_op0;
733 operands[2] = hppa_compare_op1;
737 [(set (match_operand:SI 0 "register_operand" "")
743 /* fp scc patterns rarely match, and are not a win on the PA. */
744 if (hppa_branch_type != CMP_SI)
746 operands[1] = hppa_compare_op0;
747 operands[2] = hppa_compare_op1;
750 (define_expand "sltu"
751 [(set (match_operand:SI 0 "register_operand" "")
752 (ltu:SI (match_dup 1)
757 if (hppa_branch_type != CMP_SI)
759 operands[1] = hppa_compare_op0;
760 operands[2] = hppa_compare_op1;
763 (define_expand "sgtu"
764 [(set (match_operand:SI 0 "register_operand" "")
765 (gtu:SI (match_dup 1)
770 if (hppa_branch_type != CMP_SI)
772 operands[1] = hppa_compare_op0;
773 operands[2] = hppa_compare_op1;
776 (define_expand "sleu"
777 [(set (match_operand:SI 0 "register_operand" "")
778 (leu:SI (match_dup 1)
783 if (hppa_branch_type != CMP_SI)
785 operands[1] = hppa_compare_op0;
786 operands[2] = hppa_compare_op1;
789 (define_expand "sgeu"
790 [(set (match_operand:SI 0 "register_operand" "")
791 (geu:SI (match_dup 1)
796 if (hppa_branch_type != CMP_SI)
798 operands[1] = hppa_compare_op0;
799 operands[2] = hppa_compare_op1;
802 ;; Instruction canonicalization puts immediate operands second, which
803 ;; is the reverse of what we want.
806 [(set (match_operand:SI 0 "register_operand" "=r")
807 (match_operator:SI 3 "comparison_operator"
808 [(match_operand:SI 1 "register_operand" "r")
809 (match_operand:SI 2 "arith11_operand" "rI")]))]
811 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
812 [(set_attr "type" "binary")
813 (set_attr "length" "8")])
816 [(set (match_operand:DI 0 "register_operand" "=r")
817 (match_operator:DI 3 "comparison_operator"
818 [(match_operand:DI 1 "register_operand" "r")
819 (match_operand:DI 2 "arith11_operand" "rI")]))]
821 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
822 [(set_attr "type" "binary")
823 (set_attr "length" "8")])
825 (define_insn "iorscc"
826 [(set (match_operand:SI 0 "register_operand" "=r")
827 (ior:SI (match_operator:SI 3 "comparison_operator"
828 [(match_operand:SI 1 "register_operand" "r")
829 (match_operand:SI 2 "arith11_operand" "rI")])
830 (match_operator:SI 6 "comparison_operator"
831 [(match_operand:SI 4 "register_operand" "r")
832 (match_operand:SI 5 "arith11_operand" "rI")])))]
834 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
835 [(set_attr "type" "binary")
836 (set_attr "length" "12")])
839 [(set (match_operand:DI 0 "register_operand" "=r")
840 (ior:DI (match_operator:DI 3 "comparison_operator"
841 [(match_operand:DI 1 "register_operand" "r")
842 (match_operand:DI 2 "arith11_operand" "rI")])
843 (match_operator:DI 6 "comparison_operator"
844 [(match_operand:DI 4 "register_operand" "r")
845 (match_operand:DI 5 "arith11_operand" "rI")])))]
847 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
848 [(set_attr "type" "binary")
849 (set_attr "length" "12")])
851 ;; Combiner patterns for common operations performed with the output
852 ;; from an scc insn (negscc and incscc).
853 (define_insn "negscc"
854 [(set (match_operand:SI 0 "register_operand" "=r")
855 (neg:SI (match_operator:SI 3 "comparison_operator"
856 [(match_operand:SI 1 "register_operand" "r")
857 (match_operand:SI 2 "arith11_operand" "rI")])))]
859 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
860 [(set_attr "type" "binary")
861 (set_attr "length" "8")])
864 [(set (match_operand:DI 0 "register_operand" "=r")
865 (neg:DI (match_operator:DI 3 "comparison_operator"
866 [(match_operand:DI 1 "register_operand" "r")
867 (match_operand:DI 2 "arith11_operand" "rI")])))]
869 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
870 [(set_attr "type" "binary")
871 (set_attr "length" "8")])
873 ;; Patterns for adding/subtracting the result of a boolean expression from
874 ;; a register. First we have special patterns that make use of the carry
875 ;; bit, and output only two instructions. For the cases we can't in
876 ;; general do in two instructions, the incscc pattern at the end outputs
877 ;; two or three instructions.
880 [(set (match_operand:SI 0 "register_operand" "=r")
881 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
882 (match_operand:SI 3 "arith11_operand" "rI"))
883 (match_operand:SI 1 "register_operand" "r")))]
885 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
886 [(set_attr "type" "binary")
887 (set_attr "length" "8")])
890 [(set (match_operand:DI 0 "register_operand" "=r")
891 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
892 (match_operand:DI 3 "arith11_operand" "rI"))
893 (match_operand:DI 1 "register_operand" "r")))]
895 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
899 ; This need only accept registers for op3, since canonicalization
900 ; replaces geu with gtu when op3 is an integer.
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
904 (match_operand:SI 3 "register_operand" "r"))
905 (match_operand:SI 1 "register_operand" "r")))]
907 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
908 [(set_attr "type" "binary")
909 (set_attr "length" "8")])
912 [(set (match_operand:DI 0 "register_operand" "=r")
913 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
914 (match_operand:DI 3 "register_operand" "r"))
915 (match_operand:DI 1 "register_operand" "r")))]
917 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
918 [(set_attr "type" "binary")
919 (set_attr "length" "8")])
921 ; Match only integers for op3 here. This is used as canonical form of the
922 ; geu pattern when op3 is an integer. Don't match registers since we can't
923 ; make better code than the general incscc pattern.
925 [(set (match_operand:SI 0 "register_operand" "=r")
926 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
927 (match_operand:SI 3 "int11_operand" "I"))
928 (match_operand:SI 1 "register_operand" "r")))]
930 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
931 [(set_attr "type" "binary")
932 (set_attr "length" "8")])
935 [(set (match_operand:DI 0 "register_operand" "=r")
936 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
937 (match_operand:DI 3 "int11_operand" "I"))
938 (match_operand:DI 1 "register_operand" "r")))]
940 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
941 [(set_attr "type" "binary")
942 (set_attr "length" "8")])
944 (define_insn "incscc"
945 [(set (match_operand:SI 0 "register_operand" "=r,r")
946 (plus:SI (match_operator:SI 4 "comparison_operator"
947 [(match_operand:SI 2 "register_operand" "r,r")
948 (match_operand:SI 3 "arith11_operand" "rI,rI")])
949 (match_operand:SI 1 "register_operand" "0,?r")))]
952 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
953 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
954 [(set_attr "type" "binary,binary")
955 (set_attr "length" "8,12")])
958 [(set (match_operand:DI 0 "register_operand" "=r,r")
959 (plus:DI (match_operator:DI 4 "comparison_operator"
960 [(match_operand:DI 2 "register_operand" "r,r")
961 (match_operand:DI 3 "arith11_operand" "rI,rI")])
962 (match_operand:DI 1 "register_operand" "0,?r")))]
965 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
966 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
967 [(set_attr "type" "binary,binary")
968 (set_attr "length" "8,12")])
971 [(set (match_operand:SI 0 "register_operand" "=r")
972 (minus:SI (match_operand:SI 1 "register_operand" "r")
973 (gtu:SI (match_operand:SI 2 "register_operand" "r")
974 (match_operand:SI 3 "arith11_operand" "rI"))))]
976 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
977 [(set_attr "type" "binary")
978 (set_attr "length" "8")])
981 [(set (match_operand:DI 0 "register_operand" "=r")
982 (minus:DI (match_operand:DI 1 "register_operand" "r")
983 (gtu:DI (match_operand:DI 2 "register_operand" "r")
984 (match_operand:DI 3 "arith11_operand" "rI"))))]
986 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
987 [(set_attr "type" "binary")
988 (set_attr "length" "8")])
991 [(set (match_operand:SI 0 "register_operand" "=r")
992 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
993 (gtu:SI (match_operand:SI 2 "register_operand" "r")
994 (match_operand:SI 3 "arith11_operand" "rI")))
995 (match_operand:SI 4 "register_operand" "r")))]
997 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
998 [(set_attr "type" "binary")
999 (set_attr "length" "8")])
1002 [(set (match_operand:DI 0 "register_operand" "=r")
1003 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1004 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1005 (match_operand:DI 3 "arith11_operand" "rI")))
1006 (match_operand:DI 4 "register_operand" "r")))]
1008 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1009 [(set_attr "type" "binary")
1010 (set_attr "length" "8")])
1012 ; This need only accept registers for op3, since canonicalization
1013 ; replaces ltu with leu when op3 is an integer.
1015 [(set (match_operand:SI 0 "register_operand" "=r")
1016 (minus:SI (match_operand:SI 1 "register_operand" "r")
1017 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1018 (match_operand:SI 3 "register_operand" "r"))))]
1020 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1021 [(set_attr "type" "binary")
1022 (set_attr "length" "8")])
1025 [(set (match_operand:DI 0 "register_operand" "=r")
1026 (minus:DI (match_operand:DI 1 "register_operand" "r")
1027 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1028 (match_operand:DI 3 "register_operand" "r"))))]
1030 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1031 [(set_attr "type" "binary")
1032 (set_attr "length" "8")])
1035 [(set (match_operand:SI 0 "register_operand" "=r")
1036 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1037 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1038 (match_operand:SI 3 "register_operand" "r")))
1039 (match_operand:SI 4 "register_operand" "r")))]
1041 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1042 [(set_attr "type" "binary")
1043 (set_attr "length" "8")])
1046 [(set (match_operand:DI 0 "register_operand" "=r")
1047 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1048 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1049 (match_operand:DI 3 "register_operand" "r")))
1050 (match_operand:DI 4 "register_operand" "r")))]
1052 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1053 [(set_attr "type" "binary")
1054 (set_attr "length" "8")])
1056 ; Match only integers for op3 here. This is used as canonical form of the
1057 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1058 ; make better code than the general incscc pattern.
1060 [(set (match_operand:SI 0 "register_operand" "=r")
1061 (minus:SI (match_operand:SI 1 "register_operand" "r")
1062 (leu:SI (match_operand:SI 2 "register_operand" "r")
1063 (match_operand:SI 3 "int11_operand" "I"))))]
1065 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1066 [(set_attr "type" "binary")
1067 (set_attr "length" "8")])
1070 [(set (match_operand:DI 0 "register_operand" "=r")
1071 (minus:DI (match_operand:DI 1 "register_operand" "r")
1072 (leu:DI (match_operand:DI 2 "register_operand" "r")
1073 (match_operand:DI 3 "int11_operand" "I"))))]
1075 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1076 [(set_attr "type" "binary")
1077 (set_attr "length" "8")])
1080 [(set (match_operand:SI 0 "register_operand" "=r")
1081 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1082 (leu:SI (match_operand:SI 2 "register_operand" "r")
1083 (match_operand:SI 3 "int11_operand" "I")))
1084 (match_operand:SI 4 "register_operand" "r")))]
1086 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1087 [(set_attr "type" "binary")
1088 (set_attr "length" "8")])
1091 [(set (match_operand:DI 0 "register_operand" "=r")
1092 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1093 (leu:DI (match_operand:DI 2 "register_operand" "r")
1094 (match_operand:DI 3 "int11_operand" "I")))
1095 (match_operand:DI 4 "register_operand" "r")))]
1097 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1098 [(set_attr "type" "binary")
1099 (set_attr "length" "8")])
1101 (define_insn "decscc"
1102 [(set (match_operand:SI 0 "register_operand" "=r,r")
1103 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1104 (match_operator:SI 4 "comparison_operator"
1105 [(match_operand:SI 2 "register_operand" "r,r")
1106 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1109 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1110 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1111 [(set_attr "type" "binary,binary")
1112 (set_attr "length" "8,12")])
1115 [(set (match_operand:DI 0 "register_operand" "=r,r")
1116 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1117 (match_operator:DI 4 "comparison_operator"
1118 [(match_operand:DI 2 "register_operand" "r,r")
1119 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1122 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1123 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1124 [(set_attr "type" "binary,binary")
1125 (set_attr "length" "8,12")])
1127 ; Patterns for max and min. (There is no need for an earlyclobber in the
1128 ; last alternative since the middle alternative will match if op0 == op1.)
1130 (define_insn "sminsi3"
1131 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1132 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1133 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1136 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1137 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1138 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1139 [(set_attr "type" "multi,multi,multi")
1140 (set_attr "length" "8,8,8")])
1142 (define_insn "smindi3"
1143 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1144 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1145 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1148 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1149 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1150 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1151 [(set_attr "type" "multi,multi,multi")
1152 (set_attr "length" "8,8,8")])
1154 (define_insn "uminsi3"
1155 [(set (match_operand:SI 0 "register_operand" "=r,r")
1156 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1157 (match_operand:SI 2 "arith11_operand" "r,I")))]
1160 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1161 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1162 [(set_attr "type" "multi,multi")
1163 (set_attr "length" "8,8")])
1165 (define_insn "umindi3"
1166 [(set (match_operand:DI 0 "register_operand" "=r,r")
1167 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1168 (match_operand:DI 2 "arith11_operand" "r,I")))]
1171 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1172 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1173 [(set_attr "type" "multi,multi")
1174 (set_attr "length" "8,8")])
1176 (define_insn "smaxsi3"
1177 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1178 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1179 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1182 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1183 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1184 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1185 [(set_attr "type" "multi,multi,multi")
1186 (set_attr "length" "8,8,8")])
1188 (define_insn "smaxdi3"
1189 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1190 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1191 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1194 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1195 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1196 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1197 [(set_attr "type" "multi,multi,multi")
1198 (set_attr "length" "8,8,8")])
1200 (define_insn "umaxsi3"
1201 [(set (match_operand:SI 0 "register_operand" "=r,r")
1202 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1203 (match_operand:SI 2 "arith11_operand" "r,I")))]
1206 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1207 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1208 [(set_attr "type" "multi,multi")
1209 (set_attr "length" "8,8")])
1211 (define_insn "umaxdi3"
1212 [(set (match_operand:DI 0 "register_operand" "=r,r")
1213 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1214 (match_operand:DI 2 "arith11_operand" "r,I")))]
1217 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1218 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1219 [(set_attr "type" "multi,multi")
1220 (set_attr "length" "8,8")])
1222 (define_insn "abssi2"
1223 [(set (match_operand:SI 0 "register_operand" "=r")
1224 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1226 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1227 [(set_attr "type" "multi")
1228 (set_attr "length" "8")])
1230 (define_insn "absdi2"
1231 [(set (match_operand:DI 0 "register_operand" "=r")
1232 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1234 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1235 [(set_attr "type" "multi")
1236 (set_attr "length" "8")])
1238 ;;; Experimental conditional move patterns
1240 (define_expand "movsicc"
1241 [(set (match_operand:SI 0 "register_operand" "")
1243 (match_operator 1 "comparison_operator"
1246 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1247 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1251 enum rtx_code code = GET_CODE (operands[1]);
1253 if (hppa_branch_type != CMP_SI)
1256 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1257 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1260 /* operands[1] is currently the result of compare_from_rtx. We want to
1261 emit a compare of the original operands. */
1262 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1263 operands[4] = hppa_compare_op0;
1264 operands[5] = hppa_compare_op1;
1267 ;; We used to accept any register for op1.
1269 ;; However, it loses sometimes because the compiler will end up using
1270 ;; different registers for op0 and op1 in some critical cases. local-alloc
1271 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1273 ;; If/when global register allocation supports tying we should allow any
1274 ;; register for op1 again.
1276 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1278 (match_operator 2 "comparison_operator"
1279 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1280 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1281 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1285 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1286 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1287 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1288 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1289 [(set_attr "type" "multi,multi,multi,nullshift")
1290 (set_attr "length" "8,8,8,8")])
1293 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1295 (match_operator 5 "comparison_operator"
1296 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1297 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1298 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1299 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1302 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1303 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1304 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1305 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1306 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1307 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1308 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1309 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1310 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1311 (set_attr "length" "8,8,8,8,8,8,8,8")])
1313 (define_expand "movdicc"
1314 [(set (match_operand:DI 0 "register_operand" "")
1316 (match_operator 1 "comparison_operator"
1319 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1320 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1324 enum rtx_code code = GET_CODE (operands[1]);
1326 if (hppa_branch_type != CMP_SI)
1329 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1330 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1333 /* operands[1] is currently the result of compare_from_rtx. We want to
1334 emit a compare of the original operands. */
1335 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1336 operands[4] = hppa_compare_op0;
1337 operands[5] = hppa_compare_op1;
1340 ; We need the first constraint alternative in order to avoid
1341 ; earlyclobbers on all other alternatives.
1343 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1345 (match_operator 2 "comparison_operator"
1346 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1347 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1348 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1352 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1353 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1354 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1355 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1356 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1357 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1358 (set_attr "length" "8,8,8,8,8")])
1361 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1363 (match_operator 5 "comparison_operator"
1364 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1365 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1366 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1367 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1370 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1371 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1372 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1373 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1374 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1375 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1376 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1377 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1378 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1379 (set_attr "length" "8,8,8,8,8,8,8,8")])
1381 ;; Conditional Branches
1383 (define_expand "beq"
1385 (if_then_else (eq (match_dup 1) (match_dup 2))
1386 (label_ref (match_operand 0 "" ""))
1391 if (hppa_branch_type != CMP_SI)
1393 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1394 emit_bcond_fp (NE, operands[0]);
1397 /* set up operands from compare. */
1398 operands[1] = hppa_compare_op0;
1399 operands[2] = hppa_compare_op1;
1400 /* fall through and generate default code */
1403 (define_expand "bne"
1405 (if_then_else (ne (match_dup 1) (match_dup 2))
1406 (label_ref (match_operand 0 "" ""))
1411 if (hppa_branch_type != CMP_SI)
1413 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1414 emit_bcond_fp (NE, operands[0]);
1417 operands[1] = hppa_compare_op0;
1418 operands[2] = hppa_compare_op1;
1421 (define_expand "bgt"
1423 (if_then_else (gt (match_dup 1) (match_dup 2))
1424 (label_ref (match_operand 0 "" ""))
1429 if (hppa_branch_type != CMP_SI)
1431 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1432 emit_bcond_fp (NE, operands[0]);
1435 operands[1] = hppa_compare_op0;
1436 operands[2] = hppa_compare_op1;
1439 (define_expand "blt"
1441 (if_then_else (lt (match_dup 1) (match_dup 2))
1442 (label_ref (match_operand 0 "" ""))
1447 if (hppa_branch_type != CMP_SI)
1449 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1450 emit_bcond_fp (NE, operands[0]);
1453 operands[1] = hppa_compare_op0;
1454 operands[2] = hppa_compare_op1;
1457 (define_expand "bge"
1459 (if_then_else (ge (match_dup 1) (match_dup 2))
1460 (label_ref (match_operand 0 "" ""))
1465 if (hppa_branch_type != CMP_SI)
1467 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1468 emit_bcond_fp (NE, operands[0]);
1471 operands[1] = hppa_compare_op0;
1472 operands[2] = hppa_compare_op1;
1475 (define_expand "ble"
1477 (if_then_else (le (match_dup 1) (match_dup 2))
1478 (label_ref (match_operand 0 "" ""))
1483 if (hppa_branch_type != CMP_SI)
1485 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1486 emit_bcond_fp (NE, operands[0]);
1489 operands[1] = hppa_compare_op0;
1490 operands[2] = hppa_compare_op1;
1493 (define_expand "bgtu"
1495 (if_then_else (gtu (match_dup 1) (match_dup 2))
1496 (label_ref (match_operand 0 "" ""))
1501 if (hppa_branch_type != CMP_SI)
1503 operands[1] = hppa_compare_op0;
1504 operands[2] = hppa_compare_op1;
1507 (define_expand "bltu"
1509 (if_then_else (ltu (match_dup 1) (match_dup 2))
1510 (label_ref (match_operand 0 "" ""))
1515 if (hppa_branch_type != CMP_SI)
1517 operands[1] = hppa_compare_op0;
1518 operands[2] = hppa_compare_op1;
1521 (define_expand "bgeu"
1523 (if_then_else (geu (match_dup 1) (match_dup 2))
1524 (label_ref (match_operand 0 "" ""))
1529 if (hppa_branch_type != CMP_SI)
1531 operands[1] = hppa_compare_op0;
1532 operands[2] = hppa_compare_op1;
1535 (define_expand "bleu"
1537 (if_then_else (leu (match_dup 1) (match_dup 2))
1538 (label_ref (match_operand 0 "" ""))
1543 if (hppa_branch_type != CMP_SI)
1545 operands[1] = hppa_compare_op0;
1546 operands[2] = hppa_compare_op1;
1549 (define_expand "bltgt"
1551 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1552 (label_ref (match_operand 0 "" ""))
1557 if (hppa_branch_type == CMP_SI)
1559 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1560 emit_bcond_fp (NE, operands[0]);
1564 (define_expand "bunle"
1566 (if_then_else (unle (match_dup 1) (match_dup 2))
1567 (label_ref (match_operand 0 "" ""))
1572 if (hppa_branch_type == CMP_SI)
1574 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1575 emit_bcond_fp (NE, operands[0]);
1579 (define_expand "bunlt"
1581 (if_then_else (unlt (match_dup 1) (match_dup 2))
1582 (label_ref (match_operand 0 "" ""))
1587 if (hppa_branch_type == CMP_SI)
1589 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1590 emit_bcond_fp (NE, operands[0]);
1594 (define_expand "bunge"
1596 (if_then_else (unge (match_dup 1) (match_dup 2))
1597 (label_ref (match_operand 0 "" ""))
1602 if (hppa_branch_type == CMP_SI)
1604 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1605 emit_bcond_fp (NE, operands[0]);
1609 (define_expand "bungt"
1611 (if_then_else (ungt (match_dup 1) (match_dup 2))
1612 (label_ref (match_operand 0 "" ""))
1617 if (hppa_branch_type == CMP_SI)
1619 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1620 emit_bcond_fp (NE, operands[0]);
1624 (define_expand "buneq"
1626 (if_then_else (uneq (match_dup 1) (match_dup 2))
1627 (label_ref (match_operand 0 "" ""))
1632 if (hppa_branch_type == CMP_SI)
1634 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1635 emit_bcond_fp (NE, operands[0]);
1639 (define_expand "bunordered"
1641 (if_then_else (unordered (match_dup 1) (match_dup 2))
1642 (label_ref (match_operand 0 "" ""))
1647 if (hppa_branch_type == CMP_SI)
1649 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1650 emit_bcond_fp (NE, operands[0]);
1654 (define_expand "bordered"
1656 (if_then_else (ordered (match_dup 1) (match_dup 2))
1657 (label_ref (match_operand 0 "" ""))
1662 if (hppa_branch_type == CMP_SI)
1664 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1665 emit_bcond_fp (NE, operands[0]);
1669 ;; Match the branch patterns.
1672 ;; Note a long backward conditional branch with an annulled delay slot
1673 ;; has a length of 12.
1677 (match_operator 3 "comparison_operator"
1678 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1679 (match_operand:SI 2 "arith5_operand" "rL")])
1680 (label_ref (match_operand 0 "" ""))
1685 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1686 get_attr_length (insn), 0, insn);
1688 [(set_attr "type" "cbranch")
1689 (set (attr "length")
1690 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1693 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1696 (eq (symbol_ref "flag_pic") (const_int 0))
1700 ;; Match the negated branch.
1705 (match_operator 3 "comparison_operator"
1706 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1707 (match_operand:SI 2 "arith5_operand" "rL")])
1709 (label_ref (match_operand 0 "" ""))))]
1713 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1714 get_attr_length (insn), 1, insn);
1716 [(set_attr "type" "cbranch")
1717 (set (attr "length")
1718 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1721 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1724 (eq (symbol_ref "flag_pic") (const_int 0))
1731 (match_operator 3 "comparison_operator"
1732 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1733 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1734 (label_ref (match_operand 0 "" ""))
1739 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1740 get_attr_length (insn), 0, insn);
1742 [(set_attr "type" "cbranch")
1743 (set (attr "length")
1744 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1747 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1750 (eq (symbol_ref "flag_pic") (const_int 0))
1754 ;; Match the negated branch.
1759 (match_operator 3 "comparison_operator"
1760 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1761 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1763 (label_ref (match_operand 0 "" ""))))]
1767 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1768 get_attr_length (insn), 1, insn);
1770 [(set_attr "type" "cbranch")
1771 (set (attr "length")
1772 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1775 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1778 (eq (symbol_ref "flag_pic") (const_int 0))
1784 (match_operator 3 "cmpib_comparison_operator"
1785 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1786 (match_operand:DI 2 "arith5_operand" "rL")])
1787 (label_ref (match_operand 0 "" ""))
1792 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1793 get_attr_length (insn), 0, insn);
1795 [(set_attr "type" "cbranch")
1796 (set (attr "length")
1797 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1800 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1803 (eq (symbol_ref "flag_pic") (const_int 0))
1807 ;; Match the negated branch.
1812 (match_operator 3 "cmpib_comparison_operator"
1813 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1814 (match_operand:DI 2 "arith5_operand" "rL")])
1816 (label_ref (match_operand 0 "" ""))))]
1820 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1821 get_attr_length (insn), 1, insn);
1823 [(set_attr "type" "cbranch")
1824 (set (attr "length")
1825 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1828 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1831 (eq (symbol_ref "flag_pic") (const_int 0))
1835 ;; Branch on Bit patterns.
1839 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1841 (match_operand:SI 1 "uint5_operand" ""))
1843 (label_ref (match_operand 2 "" ""))
1848 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1849 get_attr_length (insn), 0, insn, 0);
1851 [(set_attr "type" "cbranch")
1852 (set (attr "length")
1853 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1861 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1863 (match_operand:DI 1 "uint32_operand" ""))
1865 (label_ref (match_operand 2 "" ""))
1870 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1871 get_attr_length (insn), 0, insn, 0);
1873 [(set_attr "type" "cbranch")
1874 (set (attr "length")
1875 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1883 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1885 (match_operand:SI 1 "uint5_operand" ""))
1888 (label_ref (match_operand 2 "" ""))))]
1892 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1893 get_attr_length (insn), 1, insn, 0);
1895 [(set_attr "type" "cbranch")
1896 (set (attr "length")
1897 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1905 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1907 (match_operand:DI 1 "uint32_operand" ""))
1910 (label_ref (match_operand 2 "" ""))))]
1914 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1915 get_attr_length (insn), 1, insn, 0);
1917 [(set_attr "type" "cbranch")
1918 (set (attr "length")
1919 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1927 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1929 (match_operand:SI 1 "uint5_operand" ""))
1931 (label_ref (match_operand 2 "" ""))
1936 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1937 get_attr_length (insn), 0, insn, 1);
1939 [(set_attr "type" "cbranch")
1940 (set (attr "length")
1941 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1949 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1951 (match_operand:DI 1 "uint32_operand" ""))
1953 (label_ref (match_operand 2 "" ""))
1958 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1959 get_attr_length (insn), 0, insn, 1);
1961 [(set_attr "type" "cbranch")
1962 (set (attr "length")
1963 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1971 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1973 (match_operand:SI 1 "uint5_operand" ""))
1976 (label_ref (match_operand 2 "" ""))))]
1980 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1981 get_attr_length (insn), 1, insn, 1);
1983 [(set_attr "type" "cbranch")
1984 (set (attr "length")
1985 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1993 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1995 (match_operand:DI 1 "uint32_operand" ""))
1998 (label_ref (match_operand 2 "" ""))))]
2002 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
2003 get_attr_length (insn), 1, insn, 1);
2005 [(set_attr "type" "cbranch")
2006 (set (attr "length")
2007 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2012 ;; Branch on Variable Bit patterns.
2016 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2018 (match_operand:SI 1 "register_operand" "q"))
2020 (label_ref (match_operand 2 "" ""))
2025 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2026 get_attr_length (insn), 0, insn, 0);
2028 [(set_attr "type" "cbranch")
2029 (set (attr "length")
2030 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2038 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2040 (match_operand:DI 1 "register_operand" "q"))
2042 (label_ref (match_operand 2 "" ""))
2047 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2048 get_attr_length (insn), 0, insn, 0);
2050 [(set_attr "type" "cbranch")
2051 (set (attr "length")
2052 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2060 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2062 (match_operand:SI 1 "register_operand" "q"))
2065 (label_ref (match_operand 2 "" ""))))]
2069 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2070 get_attr_length (insn), 1, insn, 0);
2072 [(set_attr "type" "cbranch")
2073 (set (attr "length")
2074 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2082 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2084 (match_operand:DI 1 "register_operand" "q"))
2087 (label_ref (match_operand 2 "" ""))))]
2091 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2092 get_attr_length (insn), 1, insn, 0);
2094 [(set_attr "type" "cbranch")
2095 (set (attr "length")
2096 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2104 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2106 (match_operand:SI 1 "register_operand" "q"))
2108 (label_ref (match_operand 2 "" ""))
2113 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2114 get_attr_length (insn), 0, insn, 1);
2116 [(set_attr "type" "cbranch")
2117 (set (attr "length")
2118 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2126 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2128 (match_operand:DI 1 "register_operand" "q"))
2130 (label_ref (match_operand 2 "" ""))
2135 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2136 get_attr_length (insn), 0, insn, 1);
2138 [(set_attr "type" "cbranch")
2139 (set (attr "length")
2140 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2148 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2150 (match_operand:SI 1 "register_operand" "q"))
2153 (label_ref (match_operand 2 "" ""))))]
2157 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2158 get_attr_length (insn), 1, insn, 1);
2160 [(set_attr "type" "cbranch")
2161 (set (attr "length")
2162 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2170 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2172 (match_operand:DI 1 "register_operand" "q"))
2175 (label_ref (match_operand 2 "" ""))))]
2179 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2180 get_attr_length (insn), 1, insn, 1);
2182 [(set_attr "type" "cbranch")
2183 (set (attr "length")
2184 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2189 ;; Floating point branches
2191 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2192 (label_ref (match_operand 0 "" ""))
2194 "! TARGET_SOFT_FLOAT"
2197 if (INSN_ANNULLED_BRANCH_P (insn))
2198 return \"ftest\;b,n %0\";
2200 return \"ftest\;b%* %0\";
2202 [(set_attr "type" "fbranch")
2203 (set_attr "length" "8")])
2206 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2208 (label_ref (match_operand 0 "" ""))))]
2209 "! TARGET_SOFT_FLOAT"
2212 if (INSN_ANNULLED_BRANCH_P (insn))
2213 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
2215 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2217 [(set_attr "type" "fbranch")
2218 (set_attr "length" "12")])
2220 ;; Move instructions
2222 (define_expand "movsi"
2223 [(set (match_operand:SI 0 "general_operand" "")
2224 (match_operand:SI 1 "general_operand" ""))]
2228 if (emit_move_sequence (operands, SImode, 0))
2232 ;; Reloading an SImode or DImode value requires a scratch register if
2233 ;; going in to or out of float point registers.
2235 (define_expand "reload_insi"
2236 [(set (match_operand:SI 0 "register_operand" "=Z")
2237 (match_operand:SI 1 "non_hard_reg_operand" ""))
2238 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2242 if (emit_move_sequence (operands, SImode, operands[2]))
2245 /* We don't want the clobber emitted, so handle this ourselves. */
2246 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2250 (define_expand "reload_outsi"
2251 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2252 (match_operand:SI 1 "register_operand" "Z"))
2253 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2257 if (emit_move_sequence (operands, SImode, operands[2]))
2260 /* We don't want the clobber emitted, so handle this ourselves. */
2261 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2266 [(set (match_operand:SI 0 "move_dest_operand"
2267 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2268 (match_operand:SI 1 "move_src_operand"
2269 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2270 "(register_operand (operands[0], SImode)
2271 || reg_or_0_operand (operands[1], SImode))
2272 && !TARGET_SOFT_FLOAT"
2278 {zdepi|depwi,z} %Z1,%0
2282 {mfctl|mfctl,w} %%sar,%0
2286 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2287 (set_attr "pa_combine_type" "addmove")
2288 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2291 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2292 (match_operand:SI 1 "register_operand" "f"))]
2294 && !TARGET_DISABLE_INDEXING
2295 && reload_completed"
2297 [(set_attr "type" "fpstore")
2298 (set_attr "pa_combine_type" "addmove")
2299 (set_attr "length" "4")])
2301 ; Rewrite RTL using an indexed store. This will allow the insn that
2302 ; computes the address to be deleted if the register it sets is dead.
2304 [(set (match_operand:SI 0 "register_operand" "")
2305 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2307 (match_operand:SI 2 "register_operand" "")))
2308 (set (mem:SI (match_dup 0))
2309 (match_operand:SI 3 "register_operand" ""))]
2311 && !TARGET_DISABLE_INDEXING
2312 && REG_OK_FOR_BASE_P (operands[2])
2313 && FP_REGNO_P (REGNO (operands[3]))"
2314 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2316 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2321 [(set (match_operand:SI 0 "register_operand" "")
2322 (plus:SI (match_operand:SI 2 "register_operand" "")
2323 (mult:SI (match_operand:SI 1 "register_operand" "")
2325 (set (mem:SI (match_dup 0))
2326 (match_operand:SI 3 "register_operand" ""))]
2328 && !TARGET_DISABLE_INDEXING
2329 && REG_OK_FOR_BASE_P (operands[2])
2330 && FP_REGNO_P (REGNO (operands[3]))"
2331 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2333 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2338 [(set (match_operand:DI 0 "register_operand" "")
2339 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2341 (match_operand:DI 2 "register_operand" "")))
2342 (set (mem:SI (match_dup 0))
2343 (match_operand:SI 3 "register_operand" ""))]
2345 && !TARGET_DISABLE_INDEXING
2347 && REG_OK_FOR_BASE_P (operands[2])
2348 && FP_REGNO_P (REGNO (operands[3]))"
2349 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2351 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2356 [(set (match_operand:DI 0 "register_operand" "")
2357 (plus:DI (match_operand:DI 2 "register_operand" "")
2358 (mult:DI (match_operand:DI 1 "register_operand" "")
2360 (set (mem:SI (match_dup 0))
2361 (match_operand:SI 3 "register_operand" ""))]
2363 && !TARGET_DISABLE_INDEXING
2365 && REG_OK_FOR_BASE_P (operands[2])
2366 && FP_REGNO_P (REGNO (operands[3]))"
2367 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2369 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2374 [(set (match_operand:SI 0 "register_operand" "")
2375 (plus:SI (match_operand:SI 1 "register_operand" "")
2376 (match_operand:SI 2 "register_operand" "")))
2377 (set (mem:SI (match_dup 0))
2378 (match_operand:SI 3 "register_operand" ""))]
2380 && !TARGET_DISABLE_INDEXING
2381 && REG_OK_FOR_BASE_P (operands[1])
2382 && (TARGET_NO_SPACE_REGS
2383 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2384 && FP_REGNO_P (REGNO (operands[3]))"
2385 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2387 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2391 [(set (match_operand:SI 0 "register_operand" "")
2392 (plus:SI (match_operand:SI 1 "register_operand" "")
2393 (match_operand:SI 2 "register_operand" "")))
2394 (set (mem:SI (match_dup 0))
2395 (match_operand:SI 3 "register_operand" ""))]
2397 && !TARGET_DISABLE_INDEXING
2398 && REG_OK_FOR_BASE_P (operands[2])
2399 && (TARGET_NO_SPACE_REGS
2400 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2401 && FP_REGNO_P (REGNO (operands[3]))"
2402 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2404 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2408 [(set (match_operand:DI 0 "register_operand" "")
2409 (plus:DI (match_operand:DI 1 "register_operand" "")
2410 (match_operand:DI 2 "register_operand" "")))
2411 (set (mem:SI (match_dup 0))
2412 (match_operand:SI 3 "register_operand" ""))]
2414 && !TARGET_DISABLE_INDEXING
2416 && REG_OK_FOR_BASE_P (operands[1])
2417 && (TARGET_NO_SPACE_REGS
2418 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2419 && FP_REGNO_P (REGNO (operands[3]))"
2420 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2422 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2426 [(set (match_operand:DI 0 "register_operand" "")
2427 (plus:DI (match_operand:DI 1 "register_operand" "")
2428 (match_operand:DI 2 "register_operand" "")))
2429 (set (mem:SI (match_dup 0))
2430 (match_operand:SI 3 "register_operand" ""))]
2432 && !TARGET_DISABLE_INDEXING
2434 && REG_OK_FOR_BASE_P (operands[2])
2435 && (TARGET_NO_SPACE_REGS
2436 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2437 && FP_REGNO_P (REGNO (operands[3]))"
2438 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2440 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2444 [(set (match_operand:SI 0 "move_dest_operand"
2445 "=r,r,r,r,r,r,Q,!*q,!r")
2446 (match_operand:SI 1 "move_src_operand"
2447 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2448 "(register_operand (operands[0], SImode)
2449 || reg_or_0_operand (operands[1], SImode))
2450 && TARGET_SOFT_FLOAT"
2456 {zdepi|depwi,z} %Z1,%0
2460 {mfctl|mfctl,w} %%sar,%0"
2461 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2462 (set_attr "pa_combine_type" "addmove")
2463 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2465 ;; Load or store with base-register modification.
2467 [(set (match_operand:SI 0 "register_operand" "=r")
2468 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2469 (match_operand:DI 2 "int5_operand" "L"))))
2471 (plus:DI (match_dup 1) (match_dup 2)))]
2474 [(set_attr "type" "load")
2475 (set_attr "length" "4")])
2477 ; And a zero extended variant.
2479 [(set (match_operand:DI 0 "register_operand" "=r")
2480 (zero_extend:DI (mem:SI
2482 (match_operand:DI 1 "register_operand" "+r")
2483 (match_operand:DI 2 "int5_operand" "L")))))
2485 (plus:DI (match_dup 1) (match_dup 2)))]
2488 [(set_attr "type" "load")
2489 (set_attr "length" "4")])
2491 (define_expand "pre_load"
2492 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2493 (mem (plus (match_operand 1 "register_operand" "")
2494 (match_operand 2 "pre_cint_operand" ""))))
2496 (plus (match_dup 1) (match_dup 2)))])]
2502 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2505 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2509 (define_insn "pre_ldw"
2510 [(set (match_operand:SI 0 "register_operand" "=r")
2511 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2512 (match_operand:SI 2 "pre_cint_operand" ""))))
2514 (plus:SI (match_dup 1) (match_dup 2)))]
2518 if (INTVAL (operands[2]) < 0)
2519 return \"{ldwm|ldw,mb} %2(%1),%0\";
2520 return \"{ldws|ldw},mb %2(%1),%0\";
2522 [(set_attr "type" "load")
2523 (set_attr "length" "4")])
2525 (define_insn "pre_ldd"
2526 [(set (match_operand:DI 0 "register_operand" "=r")
2527 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2528 (match_operand:DI 2 "pre_cint_operand" ""))))
2530 (plus:DI (match_dup 1) (match_dup 2)))]
2533 [(set_attr "type" "load")
2534 (set_attr "length" "4")])
2537 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2538 (match_operand:SI 1 "pre_cint_operand" "")))
2539 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2541 (plus:SI (match_dup 0) (match_dup 1)))]
2545 if (INTVAL (operands[1]) < 0)
2546 return \"{stwm|stw,mb} %r2,%1(%0)\";
2547 return \"{stws|stw},mb %r2,%1(%0)\";
2549 [(set_attr "type" "store")
2550 (set_attr "length" "4")])
2553 [(set (match_operand:SI 0 "register_operand" "=r")
2554 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2556 (plus:SI (match_dup 1)
2557 (match_operand:SI 2 "post_cint_operand" "")))]
2561 if (INTVAL (operands[2]) > 0)
2562 return \"{ldwm|ldw,ma} %2(%1),%0\";
2563 return \"{ldws|ldw},ma %2(%1),%0\";
2565 [(set_attr "type" "load")
2566 (set_attr "length" "4")])
2568 (define_expand "post_store"
2569 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2570 (match_operand 1 "reg_or_0_operand" ""))
2573 (match_operand 2 "post_cint_operand" "")))])]
2579 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2582 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2586 (define_insn "post_stw"
2587 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2588 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2590 (plus:SI (match_dup 0)
2591 (match_operand:SI 2 "post_cint_operand" "")))]
2595 if (INTVAL (operands[2]) > 0)
2596 return \"{stwm|stw,ma} %r1,%2(%0)\";
2597 return \"{stws|stw},ma %r1,%2(%0)\";
2599 [(set_attr "type" "store")
2600 (set_attr "length" "4")])
2602 (define_insn "post_std"
2603 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2604 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2606 (plus:DI (match_dup 0)
2607 (match_operand:DI 2 "post_cint_operand" "")))]
2610 [(set_attr "type" "store")
2611 (set_attr "length" "4")])
2613 ;; For loading the address of a label while generating PIC code.
2614 ;; Note since this pattern can be created at reload time (via movsi), all
2615 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2617 [(set (match_operand 0 "pmode_register_operand" "=a")
2618 (match_operand 1 "pic_label_operand" ""))]
2624 xoperands[0] = operands[0];
2625 xoperands[1] = operands[1];
2626 xoperands[2] = gen_label_rtx ();
2628 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2629 CODE_LABEL_NUMBER (xoperands[2]));
2630 output_asm_insn (\"mfia %0\", xoperands);
2632 /* If we're trying to load the address of a label that happens to be
2633 close, then we can use a shorter sequence. */
2634 if (GET_CODE (operands[1]) == LABEL_REF
2635 && INSN_ADDRESSES_SET_P ()
2636 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2637 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2638 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2641 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2642 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2646 [(set_attr "type" "multi")
2647 (set_attr "length" "12")]) ; 8 or 12
2650 [(set (match_operand 0 "pmode_register_operand" "=a")
2651 (match_operand 1 "pic_label_operand" ""))]
2657 xoperands[0] = operands[0];
2658 xoperands[1] = operands[1];
2659 xoperands[2] = gen_label_rtx ();
2661 output_asm_insn (\"bl .+8,%0\", xoperands);
2662 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2663 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2664 CODE_LABEL_NUMBER (xoperands[2]));
2666 /* If we're trying to load the address of a label that happens to be
2667 close, then we can use a shorter sequence. */
2668 if (GET_CODE (operands[1]) == LABEL_REF
2669 && INSN_ADDRESSES_SET_P ()
2670 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2671 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2672 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2675 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2676 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2680 [(set_attr "type" "multi")
2681 (set_attr "length" "16")]) ; 12 or 16
2684 [(set (match_operand:SI 0 "register_operand" "=a")
2685 (plus:SI (match_operand:SI 1 "register_operand" "r")
2686 (high:SI (match_operand 2 "" ""))))]
2687 "symbolic_operand (operands[2], Pmode)
2688 && ! function_label_operand (operands[2], Pmode)
2691 [(set_attr "type" "binary")
2692 (set_attr "length" "4")])
2695 [(set (match_operand:DI 0 "register_operand" "=a")
2696 (plus:DI (match_operand:DI 1 "register_operand" "r")
2697 (high:DI (match_operand 2 "" ""))))]
2698 "symbolic_operand (operands[2], Pmode)
2699 && ! function_label_operand (operands[2], Pmode)
2703 [(set_attr "type" "binary")
2704 (set_attr "length" "4")])
2706 ;; Always use addil rather than ldil;add sequences. This allows the
2707 ;; HP linker to eliminate the dp relocation if the symbolic operand
2708 ;; lives in the TEXT space.
2710 [(set (match_operand:SI 0 "register_operand" "=a")
2711 (high:SI (match_operand 1 "" "")))]
2712 "symbolic_operand (operands[1], Pmode)
2713 && ! function_label_operand (operands[1], Pmode)
2714 && ! read_only_operand (operands[1], Pmode)
2718 if (TARGET_LONG_LOAD_STORE)
2719 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2721 return \"addil LR'%H1,%%r27\";
2723 [(set_attr "type" "binary")
2724 (set (attr "length")
2725 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2730 ;; This is for use in the prologue/epilogue code. We need it
2731 ;; to add large constants to a stack pointer or frame pointer.
2732 ;; Because of the additional %r1 pressure, we probably do not
2733 ;; want to use this in general code, so make it available
2734 ;; only after reload.
2736 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2737 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2738 (high:SI (match_operand 2 "const_int_operand" ""))))]
2742 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2743 [(set_attr "type" "binary,binary")
2744 (set_attr "length" "4,8")])
2747 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2748 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2749 (high:DI (match_operand 2 "const_int_operand" ""))))]
2750 "reload_completed && TARGET_64BIT"
2753 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2754 [(set_attr "type" "binary,binary")
2755 (set_attr "length" "4,8")])
2758 [(set (match_operand:SI 0 "register_operand" "=r")
2759 (high:SI (match_operand 1 "" "")))]
2760 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2761 && !is_function_label_plus_const (operands[1])"
2764 if (symbolic_operand (operands[1], Pmode))
2765 return \"ldil LR'%H1,%0\";
2767 return \"ldil L'%G1,%0\";
2769 [(set_attr "type" "move")
2770 (set_attr "length" "4")])
2773 [(set (match_operand:DI 0 "register_operand" "=r")
2774 (high:DI (match_operand 1 "const_int_operand" "")))]
2777 [(set_attr "type" "move")
2778 (set_attr "length" "4")])
2781 [(set (match_operand:DI 0 "register_operand" "=r")
2782 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2783 (match_operand:DI 2 "const_int_operand" "i")))]
2786 [(set_attr "type" "move")
2787 (set_attr "length" "4")])
2790 [(set (match_operand:SI 0 "register_operand" "=r")
2791 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2792 (match_operand:SI 2 "immediate_operand" "i")))]
2793 "!is_function_label_plus_const (operands[2])"
2796 if (flag_pic && symbolic_operand (operands[2], Pmode))
2798 else if (symbolic_operand (operands[2], Pmode))
2799 return \"ldo RR'%G2(%1),%0\";
2801 return \"ldo R'%G2(%1),%0\";
2803 [(set_attr "type" "move")
2804 (set_attr "length" "4")])
2806 ;; Now that a symbolic_address plus a constant is broken up early
2807 ;; in the compilation phase (for better CSE) we need a special
2808 ;; combiner pattern to load the symbolic address plus the constant
2809 ;; in only 2 instructions. (For cases where the symbolic address
2810 ;; was not a common subexpression.)
2812 [(set (match_operand:SI 0 "register_operand" "")
2813 (match_operand:SI 1 "symbolic_operand" ""))
2814 (clobber (match_operand:SI 2 "register_operand" ""))]
2815 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2816 [(set (match_dup 2) (high:SI (match_dup 1)))
2817 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2820 ;; hppa_legitimize_address goes to a great deal of trouble to
2821 ;; create addresses which use indexing. In some cases, this
2822 ;; is a lose because there isn't any store instructions which
2823 ;; allow indexed addresses (with integer register source).
2825 ;; These define_splits try to turn a 3 insn store into
2826 ;; a 2 insn store with some creative RTL rewriting.
2828 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2829 (match_operand:SI 1 "shadd_operand" ""))
2830 (plus:SI (match_operand:SI 2 "register_operand" "")
2831 (match_operand:SI 3 "const_int_operand" ""))))
2832 (match_operand:SI 4 "register_operand" ""))
2833 (clobber (match_operand:SI 5 "register_operand" ""))]
2835 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2837 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2841 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2842 (match_operand:SI 1 "shadd_operand" ""))
2843 (plus:SI (match_operand:SI 2 "register_operand" "")
2844 (match_operand:SI 3 "const_int_operand" ""))))
2845 (match_operand:HI 4 "register_operand" ""))
2846 (clobber (match_operand:SI 5 "register_operand" ""))]
2848 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2850 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2854 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2855 (match_operand:SI 1 "shadd_operand" ""))
2856 (plus:SI (match_operand:SI 2 "register_operand" "")
2857 (match_operand:SI 3 "const_int_operand" ""))))
2858 (match_operand:QI 4 "register_operand" ""))
2859 (clobber (match_operand:SI 5 "register_operand" ""))]
2861 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2863 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2866 (define_expand "movhi"
2867 [(set (match_operand:HI 0 "general_operand" "")
2868 (match_operand:HI 1 "general_operand" ""))]
2872 if (emit_move_sequence (operands, HImode, 0))
2877 [(set (match_operand:HI 0 "move_dest_operand"
2878 "=r,r,r,r,r,Q,!*q,!r,!*f")
2879 (match_operand:HI 1 "move_src_operand"
2880 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
2881 "register_operand (operands[0], HImode)
2882 || reg_or_0_operand (operands[1], HImode)"
2887 {zdepi|depwi,z} %Z1,%0
2891 {mfctl|mfctl,w} %sar,%0
2893 [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
2894 (set_attr "pa_combine_type" "addmove")
2895 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2898 [(set (match_operand:HI 0 "register_operand" "=r")
2899 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2900 (match_operand:SI 2 "int5_operand" "L"))))
2902 (plus:SI (match_dup 1) (match_dup 2)))]
2904 "{ldhs|ldh},mb %2(%1),%0"
2905 [(set_attr "type" "load")
2906 (set_attr "length" "4")])
2909 [(set (match_operand:HI 0 "register_operand" "=r")
2910 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2911 (match_operand:DI 2 "int5_operand" "L"))))
2913 (plus:DI (match_dup 1) (match_dup 2)))]
2916 [(set_attr "type" "load")
2917 (set_attr "length" "4")])
2919 ; And a zero extended variant.
2921 [(set (match_operand:DI 0 "register_operand" "=r")
2922 (zero_extend:DI (mem:HI
2924 (match_operand:DI 1 "register_operand" "+r")
2925 (match_operand:DI 2 "int5_operand" "L")))))
2927 (plus:DI (match_dup 1) (match_dup 2)))]
2930 [(set_attr "type" "load")
2931 (set_attr "length" "4")])
2934 [(set (match_operand:SI 0 "register_operand" "=r")
2935 (zero_extend:SI (mem:HI
2937 (match_operand:SI 1 "register_operand" "+r")
2938 (match_operand:SI 2 "int5_operand" "L")))))
2940 (plus:SI (match_dup 1) (match_dup 2)))]
2942 "{ldhs|ldh},mb %2(%1),%0"
2943 [(set_attr "type" "load")
2944 (set_attr "length" "4")])
2947 [(set (match_operand:SI 0 "register_operand" "=r")
2948 (zero_extend:SI (mem:HI
2950 (match_operand:DI 1 "register_operand" "+r")
2951 (match_operand:DI 2 "int5_operand" "L")))))
2953 (plus:DI (match_dup 1) (match_dup 2)))]
2956 [(set_attr "type" "load")
2957 (set_attr "length" "4")])
2960 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2961 (match_operand:SI 1 "int5_operand" "L")))
2962 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2964 (plus:SI (match_dup 0) (match_dup 1)))]
2966 "{sths|sth},mb %r2,%1(%0)"
2967 [(set_attr "type" "store")
2968 (set_attr "length" "4")])
2971 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2972 (match_operand:DI 1 "int5_operand" "L")))
2973 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2975 (plus:DI (match_dup 0) (match_dup 1)))]
2978 [(set_attr "type" "store")
2979 (set_attr "length" "4")])
2982 [(set (match_operand:HI 0 "register_operand" "=r")
2983 (plus:HI (match_operand:HI 1 "register_operand" "r")
2984 (match_operand 2 "const_int_operand" "J")))]
2987 [(set_attr "type" "binary")
2988 (set_attr "pa_combine_type" "addmove")
2989 (set_attr "length" "4")])
2991 (define_expand "movqi"
2992 [(set (match_operand:QI 0 "general_operand" "")
2993 (match_operand:QI 1 "general_operand" ""))]
2997 if (emit_move_sequence (operands, QImode, 0))
3002 [(set (match_operand:QI 0 "move_dest_operand"
3003 "=r,r,r,r,r,Q,!*q,!r,!*f")
3004 (match_operand:QI 1 "move_src_operand"
3005 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
3006 "register_operand (operands[0], QImode)
3007 || reg_or_0_operand (operands[1], QImode)"
3012 {zdepi|depwi,z} %Z1,%0
3016 {mfctl|mfctl,w} %%sar,%0
3018 [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
3019 (set_attr "pa_combine_type" "addmove")
3020 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3023 [(set (match_operand:QI 0 "register_operand" "=r")
3024 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3025 (match_operand:SI 2 "int5_operand" "L"))))
3026 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3028 "{ldbs|ldb},mb %2(%1),%0"
3029 [(set_attr "type" "load")
3030 (set_attr "length" "4")])
3033 [(set (match_operand:QI 0 "register_operand" "=r")
3034 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3035 (match_operand:DI 2 "int5_operand" "L"))))
3036 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3039 [(set_attr "type" "load")
3040 (set_attr "length" "4")])
3042 ; Now the same thing with zero extensions.
3044 [(set (match_operand:DI 0 "register_operand" "=r")
3045 (zero_extend:DI (mem:QI (plus:DI
3046 (match_operand:DI 1 "register_operand" "+r")
3047 (match_operand:DI 2 "int5_operand" "L")))))
3048 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3051 [(set_attr "type" "load")
3052 (set_attr "length" "4")])
3055 [(set (match_operand:SI 0 "register_operand" "=r")
3056 (zero_extend:SI (mem:QI (plus:SI
3057 (match_operand:SI 1 "register_operand" "+r")
3058 (match_operand:SI 2 "int5_operand" "L")))))
3059 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3061 "{ldbs|ldb},mb %2(%1),%0"
3062 [(set_attr "type" "load")
3063 (set_attr "length" "4")])
3066 [(set (match_operand:SI 0 "register_operand" "=r")
3067 (zero_extend:SI (mem:QI (plus:DI
3068 (match_operand:DI 1 "register_operand" "+r")
3069 (match_operand:DI 2 "int5_operand" "L")))))
3070 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3073 [(set_attr "type" "load")
3074 (set_attr "length" "4")])
3077 [(set (match_operand:HI 0 "register_operand" "=r")
3078 (zero_extend:HI (mem:QI (plus:SI
3079 (match_operand:SI 1 "register_operand" "+r")
3080 (match_operand:SI 2 "int5_operand" "L")))))
3081 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3083 "{ldbs|ldb},mb %2(%1),%0"
3084 [(set_attr "type" "load")
3085 (set_attr "length" "4")])
3088 [(set (match_operand:HI 0 "register_operand" "=r")
3089 (zero_extend:HI (mem:QI (plus:DI
3090 (match_operand:DI 1 "register_operand" "+r")
3091 (match_operand:DI 2 "int5_operand" "L")))))
3092 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3095 [(set_attr "type" "load")
3096 (set_attr "length" "4")])
3099 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3100 (match_operand:SI 1 "int5_operand" "L")))
3101 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3103 (plus:SI (match_dup 0) (match_dup 1)))]
3105 "{stbs|stb},mb %r2,%1(%0)"
3106 [(set_attr "type" "store")
3107 (set_attr "length" "4")])
3110 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3111 (match_operand:DI 1 "int5_operand" "L")))
3112 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3114 (plus:DI (match_dup 0) (match_dup 1)))]
3117 [(set_attr "type" "store")
3118 (set_attr "length" "4")])
3120 ;; The definition of this insn does not really explain what it does,
3121 ;; but it should suffice that anything generated as this insn will be
3122 ;; recognized as a movstrsi operation, and that it will not successfully
3123 ;; combine with anything.
3124 (define_expand "movstrsi"
3125 [(parallel [(set (match_operand:BLK 0 "" "")
3126 (match_operand:BLK 1 "" ""))
3127 (clobber (match_dup 4))
3128 (clobber (match_dup 5))
3129 (clobber (match_dup 6))
3130 (clobber (match_dup 7))
3131 (clobber (match_dup 8))
3132 (use (match_operand:SI 2 "arith_operand" ""))
3133 (use (match_operand:SI 3 "const_int_operand" ""))])]
3134 "!TARGET_64BIT && optimize > 0"
3139 /* HP provides very fast block move library routine for the PA;
3140 this routine includes:
3142 4x4 byte at a time block moves,
3143 1x4 byte at a time with alignment checked at runtime with
3144 attempts to align the source and destination as needed
3147 With that in mind, here's the heuristics to try and guess when
3148 the inlined block move will be better than the library block
3151 If the size isn't constant, then always use the library routines.
3153 If the size is large in respect to the known alignment, then use
3154 the library routines.
3156 If the size is small in respect to the known alignment, then open
3157 code the copy (since that will lead to better scheduling).
3159 Else use the block move pattern. */
3161 /* Undetermined size, use the library routine. */
3162 if (GET_CODE (operands[2]) != CONST_INT)
3165 size = INTVAL (operands[2]);
3166 align = INTVAL (operands[3]);
3167 align = align > 4 ? 4 : align;
3169 /* If size/alignment is large, then use the library routines. */
3170 if (size / align > 16)
3173 /* This does happen, but not often enough to worry much about. */
3174 if (size / align < MOVE_RATIO)
3177 /* Fall through means we're going to use our block move pattern. */
3179 = replace_equiv_address (operands[0],
3180 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3182 = replace_equiv_address (operands[1],
3183 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3184 operands[4] = gen_reg_rtx (SImode);
3185 operands[5] = gen_reg_rtx (SImode);
3186 operands[6] = gen_reg_rtx (SImode);
3187 operands[7] = gen_reg_rtx (SImode);
3188 operands[8] = gen_reg_rtx (SImode);
3191 ;; The operand constraints are written like this to support both compile-time
3192 ;; and run-time determined byte counts. The expander and output_block_move
3193 ;; only support compile-time determined counts at this time.
3195 ;; If the count is run-time determined, the register with the byte count
3196 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3198 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3199 ;; broke this semantic for pseudo registers. We can't use match_scratch
3200 ;; as this requires two registers in the class R1_REGS when the MEMs for
3201 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3202 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3203 ;; respectively. We then split or peephole optimize after reload.
3204 (define_insn "movstrsi_prereload"
3205 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3206 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3207 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3208 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3209 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3210 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3211 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3212 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3213 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3216 [(set_attr "type" "multi,multi")])
3219 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3220 (match_operand:BLK 1 "memory_operand" ""))
3221 (clobber (match_operand:SI 2 "register_operand" ""))
3222 (clobber (match_operand:SI 3 "register_operand" ""))
3223 (clobber (match_operand:SI 6 "register_operand" ""))
3224 (clobber (match_operand:SI 7 "register_operand" ""))
3225 (clobber (match_operand:SI 8 "register_operand" ""))
3226 (use (match_operand:SI 4 "arith_operand" ""))
3227 (use (match_operand:SI 5 "const_int_operand" ""))])]
3228 "!TARGET_64BIT && reload_completed && !flag_peephole2
3229 && GET_CODE (operands[0]) == MEM
3230 && register_operand (XEXP (operands[0], 0), SImode)
3231 && GET_CODE (operands[1]) == MEM
3232 && register_operand (XEXP (operands[1], 0), SImode)"
3233 [(set (match_dup 7) (match_dup 9))
3234 (set (match_dup 8) (match_dup 10))
3235 (parallel [(set (match_dup 0) (match_dup 1))
3236 (clobber (match_dup 2))
3237 (clobber (match_dup 3))
3238 (clobber (match_dup 6))
3239 (clobber (match_dup 7))
3240 (clobber (match_dup 8))
3246 operands[9] = XEXP (operands[0], 0);
3247 operands[10] = XEXP (operands[1], 0);
3248 operands[0] = replace_equiv_address (operands[0], operands[7]);
3249 operands[1] = replace_equiv_address (operands[1], operands[8]);
3253 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3254 (match_operand:BLK 1 "memory_operand" ""))
3255 (clobber (match_operand:SI 2 "register_operand" ""))
3256 (clobber (match_operand:SI 3 "register_operand" ""))
3257 (clobber (match_operand:SI 6 "register_operand" ""))
3258 (clobber (match_operand:SI 7 "register_operand" ""))
3259 (clobber (match_operand:SI 8 "register_operand" ""))
3260 (use (match_operand:SI 4 "arith_operand" ""))
3261 (use (match_operand:SI 5 "const_int_operand" ""))])]
3263 && GET_CODE (operands[0]) == MEM
3264 && register_operand (XEXP (operands[0], 0), SImode)
3265 && GET_CODE (operands[1]) == MEM
3266 && register_operand (XEXP (operands[1], 0), SImode)"
3267 [(parallel [(set (match_dup 0) (match_dup 1))
3268 (clobber (match_dup 2))
3269 (clobber (match_dup 3))
3270 (clobber (match_dup 6))
3271 (clobber (match_dup 7))
3272 (clobber (match_dup 8))
3278 rtx addr = XEXP (operands[0], 0);
3279 if (dead_or_set_p (curr_insn, addr))
3283 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3284 operands[0] = replace_equiv_address (operands[0], operands[7]);
3287 addr = XEXP (operands[1], 0);
3288 if (dead_or_set_p (curr_insn, addr))
3292 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3293 operands[1] = replace_equiv_address (operands[1], operands[8]);
3297 (define_insn "movstrsi_postreload"
3298 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3299 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3300 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3301 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3302 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3303 (clobber (match_dup 0))
3304 (clobber (match_dup 1))
3305 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3306 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3308 "!TARGET_64BIT && reload_completed"
3309 "* return output_block_move (operands, !which_alternative);"
3310 [(set_attr "type" "multi,multi")])
3312 (define_expand "movstrdi"
3313 [(parallel [(set (match_operand:BLK 0 "" "")
3314 (match_operand:BLK 1 "" ""))
3315 (clobber (match_dup 4))
3316 (clobber (match_dup 5))
3317 (clobber (match_dup 6))
3318 (clobber (match_dup 7))
3319 (clobber (match_dup 8))
3320 (use (match_operand:DI 2 "arith_operand" ""))
3321 (use (match_operand:DI 3 "const_int_operand" ""))])]
3322 "TARGET_64BIT && optimize > 0"
3327 /* HP provides very fast block move library routine for the PA;
3328 this routine includes:
3330 4x4 byte at a time block moves,
3331 1x4 byte at a time with alignment checked at runtime with
3332 attempts to align the source and destination as needed
3335 With that in mind, here's the heuristics to try and guess when
3336 the inlined block move will be better than the library block
3339 If the size isn't constant, then always use the library routines.
3341 If the size is large in respect to the known alignment, then use
3342 the library routines.
3344 If the size is small in respect to the known alignment, then open
3345 code the copy (since that will lead to better scheduling).
3347 Else use the block move pattern. */
3349 /* Undetermined size, use the library routine. */
3350 if (GET_CODE (operands[2]) != CONST_INT)
3353 size = INTVAL (operands[2]);
3354 align = INTVAL (operands[3]);
3355 align = align > 8 ? 8 : align;
3357 /* If size/alignment is large, then use the library routines. */
3358 if (size / align > 16)
3361 /* This does happen, but not often enough to worry much about. */
3362 if (size / align < MOVE_RATIO)
3365 /* Fall through means we're going to use our block move pattern. */
3367 = replace_equiv_address (operands[0],
3368 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3370 = replace_equiv_address (operands[1],
3371 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3372 operands[4] = gen_reg_rtx (DImode);
3373 operands[5] = gen_reg_rtx (DImode);
3374 operands[6] = gen_reg_rtx (DImode);
3375 operands[7] = gen_reg_rtx (DImode);
3376 operands[8] = gen_reg_rtx (DImode);
3379 ;; The operand constraints are written like this to support both compile-time
3380 ;; and run-time determined byte counts. The expander and output_block_move
3381 ;; only support compile-time determined counts at this time.
3383 ;; If the count is run-time determined, the register with the byte count
3384 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3386 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3387 ;; broke this semantic for pseudo registers. We can't use match_scratch
3388 ;; as this requires two registers in the class R1_REGS when the MEMs for
3389 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3390 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3391 ;; respectively. We then split or peephole optimize after reload.
3392 (define_insn "movstrdi_prereload"
3393 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3394 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3395 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3396 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3397 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3398 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3399 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3400 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3401 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3404 [(set_attr "type" "multi,multi")])
3407 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3408 (match_operand:BLK 1 "memory_operand" ""))
3409 (clobber (match_operand:DI 2 "register_operand" ""))
3410 (clobber (match_operand:DI 3 "register_operand" ""))
3411 (clobber (match_operand:DI 6 "register_operand" ""))
3412 (clobber (match_operand:DI 7 "register_operand" ""))
3413 (clobber (match_operand:DI 8 "register_operand" ""))
3414 (use (match_operand:DI 4 "arith_operand" ""))
3415 (use (match_operand:DI 5 "const_int_operand" ""))])]
3416 "TARGET_64BIT && reload_completed && !flag_peephole2
3417 && GET_CODE (operands[0]) == MEM
3418 && register_operand (XEXP (operands[0], 0), DImode)
3419 && GET_CODE (operands[1]) == MEM
3420 && register_operand (XEXP (operands[1], 0), DImode)"
3421 [(set (match_dup 7) (match_dup 9))
3422 (set (match_dup 8) (match_dup 10))
3423 (parallel [(set (match_dup 0) (match_dup 1))
3424 (clobber (match_dup 2))
3425 (clobber (match_dup 3))
3426 (clobber (match_dup 6))
3427 (clobber (match_dup 7))
3428 (clobber (match_dup 8))
3434 operands[9] = XEXP (operands[0], 0);
3435 operands[10] = XEXP (operands[1], 0);
3436 operands[0] = replace_equiv_address (operands[0], operands[7]);
3437 operands[1] = replace_equiv_address (operands[1], operands[8]);
3441 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3442 (match_operand:BLK 1 "memory_operand" ""))
3443 (clobber (match_operand:DI 2 "register_operand" ""))
3444 (clobber (match_operand:DI 3 "register_operand" ""))
3445 (clobber (match_operand:DI 6 "register_operand" ""))
3446 (clobber (match_operand:DI 7 "register_operand" ""))
3447 (clobber (match_operand:DI 8 "register_operand" ""))
3448 (use (match_operand:DI 4 "arith_operand" ""))
3449 (use (match_operand:DI 5 "const_int_operand" ""))])]
3451 && GET_CODE (operands[0]) == MEM
3452 && register_operand (XEXP (operands[0], 0), DImode)
3453 && GET_CODE (operands[1]) == MEM
3454 && register_operand (XEXP (operands[1], 0), DImode)"
3455 [(parallel [(set (match_dup 0) (match_dup 1))
3456 (clobber (match_dup 2))
3457 (clobber (match_dup 3))
3458 (clobber (match_dup 6))
3459 (clobber (match_dup 7))
3460 (clobber (match_dup 8))
3466 rtx addr = XEXP (operands[0], 0);
3467 if (dead_or_set_p (curr_insn, addr))
3471 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3472 operands[0] = replace_equiv_address (operands[0], operands[7]);
3475 addr = XEXP (operands[1], 0);
3476 if (dead_or_set_p (curr_insn, addr))
3480 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3481 operands[1] = replace_equiv_address (operands[1], operands[8]);
3485 (define_insn "movstrdi_postreload"
3486 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3487 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3488 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3489 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3490 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3491 (clobber (match_dup 0))
3492 (clobber (match_dup 1))
3493 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3494 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3496 "TARGET_64BIT && reload_completed"
3497 "* return output_block_move (operands, !which_alternative);"
3498 [(set_attr "type" "multi,multi")])
3500 (define_expand "clrstrsi"
3501 [(parallel [(set (match_operand:BLK 0 "" "")
3503 (clobber (match_dup 3))
3504 (clobber (match_dup 4))
3505 (use (match_operand:SI 1 "arith_operand" ""))
3506 (use (match_operand:SI 2 "const_int_operand" ""))])]
3507 "!TARGET_64BIT && optimize > 0"
3512 /* Undetermined size, use the library routine. */
3513 if (GET_CODE (operands[1]) != CONST_INT)
3516 size = INTVAL (operands[1]);
3517 align = INTVAL (operands[2]);
3518 align = align > 4 ? 4 : align;
3520 /* If size/alignment is large, then use the library routines. */
3521 if (size / align > 16)
3524 /* This does happen, but not often enough to worry much about. */
3525 if (size / align < MOVE_RATIO)
3528 /* Fall through means we're going to use our block clear pattern. */
3530 = replace_equiv_address (operands[0],
3531 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3532 operands[3] = gen_reg_rtx (SImode);
3533 operands[4] = gen_reg_rtx (SImode);
3536 (define_insn "clrstrsi_prereload"
3537 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3539 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3540 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3541 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3542 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3545 [(set_attr "type" "multi,multi")])
3548 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3550 (clobber (match_operand:SI 1 "register_operand" ""))
3551 (clobber (match_operand:SI 4 "register_operand" ""))
3552 (use (match_operand:SI 2 "arith_operand" ""))
3553 (use (match_operand:SI 3 "const_int_operand" ""))])]
3554 "!TARGET_64BIT && reload_completed && !flag_peephole2
3555 && GET_CODE (operands[0]) == MEM
3556 && register_operand (XEXP (operands[0], 0), SImode)"
3557 [(set (match_dup 4) (match_dup 5))
3558 (parallel [(set (match_dup 0) (const_int 0))
3559 (clobber (match_dup 1))
3560 (clobber (match_dup 4))
3566 operands[5] = XEXP (operands[0], 0);
3567 operands[0] = replace_equiv_address (operands[0], operands[4]);
3571 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3573 (clobber (match_operand:SI 1 "register_operand" ""))
3574 (clobber (match_operand:SI 4 "register_operand" ""))
3575 (use (match_operand:SI 2 "arith_operand" ""))
3576 (use (match_operand:SI 3 "const_int_operand" ""))])]
3578 && GET_CODE (operands[0]) == MEM
3579 && register_operand (XEXP (operands[0], 0), SImode)"
3580 [(parallel [(set (match_dup 0) (const_int 0))
3581 (clobber (match_dup 1))
3582 (clobber (match_dup 4))
3588 rtx addr = XEXP (operands[0], 0);
3589 if (dead_or_set_p (curr_insn, addr))
3593 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3594 operands[0] = replace_equiv_address (operands[0], operands[4]);
3598 (define_insn "clrstrsi_postreload"
3599 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3601 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3602 (clobber (match_dup 0))
3603 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3604 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3606 "!TARGET_64BIT && reload_completed"
3607 "* return output_block_clear (operands, !which_alternative);"
3608 [(set_attr "type" "multi,multi")])
3610 (define_expand "clrstrdi"
3611 [(parallel [(set (match_operand:BLK 0 "" "")
3613 (clobber (match_dup 3))
3614 (clobber (match_dup 4))
3615 (use (match_operand:DI 1 "arith_operand" ""))
3616 (use (match_operand:DI 2 "const_int_operand" ""))])]
3617 "TARGET_64BIT && optimize > 0"
3622 /* Undetermined size, use the library routine. */
3623 if (GET_CODE (operands[1]) != CONST_INT)
3626 size = INTVAL (operands[1]);
3627 align = INTVAL (operands[2]);
3628 align = align > 8 ? 8 : align;
3630 /* If size/alignment is large, then use the library routines. */
3631 if (size / align > 16)
3634 /* This does happen, but not often enough to worry much about. */
3635 if (size / align < MOVE_RATIO)
3638 /* Fall through means we're going to use our block clear pattern. */
3640 = replace_equiv_address (operands[0],
3641 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3642 operands[3] = gen_reg_rtx (DImode);
3643 operands[4] = gen_reg_rtx (DImode);
3646 (define_insn "clrstrdi_prereload"
3647 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3649 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3650 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3651 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3652 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3655 [(set_attr "type" "multi,multi")])
3658 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3660 (clobber (match_operand:DI 1 "register_operand" ""))
3661 (clobber (match_operand:DI 4 "register_operand" ""))
3662 (use (match_operand:DI 2 "arith_operand" ""))
3663 (use (match_operand:DI 3 "const_int_operand" ""))])]
3664 "TARGET_64BIT && reload_completed && !flag_peephole2
3665 && GET_CODE (operands[0]) == MEM
3666 && register_operand (XEXP (operands[0], 0), DImode)"
3667 [(set (match_dup 4) (match_dup 5))
3668 (parallel [(set (match_dup 0) (const_int 0))
3669 (clobber (match_dup 1))
3670 (clobber (match_dup 4))
3676 operands[5] = XEXP (operands[0], 0);
3677 operands[0] = replace_equiv_address (operands[0], operands[4]);
3681 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3683 (clobber (match_operand:DI 1 "register_operand" ""))
3684 (clobber (match_operand:DI 4 "register_operand" ""))
3685 (use (match_operand:DI 2 "arith_operand" ""))
3686 (use (match_operand:DI 3 "const_int_operand" ""))])]
3688 && GET_CODE (operands[0]) == MEM
3689 && register_operand (XEXP (operands[0], 0), DImode)"
3690 [(parallel [(set (match_dup 0) (const_int 0))
3691 (clobber (match_dup 1))
3692 (clobber (match_dup 4))
3698 rtx addr = XEXP (operands[0], 0);
3699 if (dead_or_set_p (curr_insn, addr))
3703 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3704 operands[0] = replace_equiv_address (operands[0], operands[4]);
3708 (define_insn "clrstrdi_postreload"
3709 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3711 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3712 (clobber (match_dup 0))
3713 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3714 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3716 "TARGET_64BIT && reload_completed"
3717 "* return output_block_clear (operands, !which_alternative);"
3718 [(set_attr "type" "multi,multi")])
3720 ;; Floating point move insns
3722 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3723 ;; to be reloaded by putting the constant into memory when
3724 ;; reg is a floating point register.
3726 ;; For integer registers we use ldil;ldo to set the appropriate
3729 ;; This must come before the movdf pattern, and it must be present
3730 ;; to handle obscure reloading cases.
3732 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3733 (match_operand:DF 1 "" "?F,m"))]
3734 "GET_CODE (operands[1]) == CONST_DOUBLE
3735 && operands[1] != CONST0_RTX (DFmode)
3737 && !TARGET_SOFT_FLOAT"
3738 "* return (which_alternative == 0 ? output_move_double (operands)
3739 : \"fldd%F1 %1,%0\");"
3740 [(set_attr "type" "move,fpload")
3741 (set_attr "length" "16,4")])
3743 (define_expand "movdf"
3744 [(set (match_operand:DF 0 "general_operand" "")
3745 (match_operand:DF 1 "general_operand" ""))]
3749 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3750 operands[1] = force_const_mem (DFmode, operands[1]);
3752 if (emit_move_sequence (operands, DFmode, 0))
3756 ;; Reloading an SImode or DImode value requires a scratch register if
3757 ;; going in to or out of float point registers.
3759 (define_expand "reload_indf"
3760 [(set (match_operand:DF 0 "register_operand" "=Z")
3761 (match_operand:DF 1 "non_hard_reg_operand" ""))
3762 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3766 if (emit_move_sequence (operands, DFmode, operands[2]))
3769 /* We don't want the clobber emitted, so handle this ourselves. */
3770 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3774 (define_expand "reload_outdf"
3775 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3776 (match_operand:DF 1 "register_operand" "Z"))
3777 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3781 if (emit_move_sequence (operands, DFmode, operands[2]))
3784 /* We don't want the clobber emitted, so handle this ourselves. */
3785 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3790 [(set (match_operand:DF 0 "move_dest_operand"
3791 "=f,*r,Q,?o,?Q,f,*r,*r")
3792 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3793 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
3794 "(register_operand (operands[0], DFmode)
3795 || reg_or_0_operand (operands[1], DFmode))
3796 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3797 && GET_CODE (operands[0]) == MEM)
3799 && !TARGET_SOFT_FLOAT"
3802 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3803 || operands[1] == CONST0_RTX (DFmode))
3804 return output_fp_move_double (operands);
3805 return output_move_double (operands);
3807 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
3808 (set_attr "length" "4,8,4,8,16,4,8,16")])
3811 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3812 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3814 && !TARGET_DISABLE_INDEXING
3815 && reload_completed"
3817 [(set_attr "type" "fpstore")
3818 (set_attr "pa_combine_type" "addmove")
3819 (set_attr "length" "4")])
3822 [(set (match_operand:SI 0 "register_operand" "")
3823 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3825 (match_operand:SI 2 "register_operand" "")))
3826 (set (mem:DF (match_dup 0))
3827 (match_operand:DF 3 "register_operand" ""))]
3829 && !TARGET_DISABLE_INDEXING
3830 && REG_OK_FOR_BASE_P (operands[2])
3831 && FP_REGNO_P (REGNO (operands[3]))"
3832 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3834 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3839 [(set (match_operand:SI 0 "register_operand" "")
3840 (plus:SI (match_operand:SI 2 "register_operand" "")
3841 (mult:SI (match_operand:SI 1 "register_operand" "")
3843 (set (mem:DF (match_dup 0))
3844 (match_operand:DF 3 "register_operand" ""))]
3846 && !TARGET_DISABLE_INDEXING
3847 && REG_OK_FOR_BASE_P (operands[2])
3848 && FP_REGNO_P (REGNO (operands[3]))"
3849 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3851 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3856 [(set (match_operand:DI 0 "register_operand" "")
3857 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3859 (match_operand:DI 2 "register_operand" "")))
3860 (set (mem:DF (match_dup 0))
3861 (match_operand:DF 3 "register_operand" ""))]
3863 && !TARGET_DISABLE_INDEXING
3865 && REG_OK_FOR_BASE_P (operands[2])
3866 && FP_REGNO_P (REGNO (operands[3]))"
3867 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3869 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3874 [(set (match_operand:DI 0 "register_operand" "")
3875 (plus:DI (match_operand:DI 2 "register_operand" "")
3876 (mult:DI (match_operand:DI 1 "register_operand" "")
3878 (set (mem:DF (match_dup 0))
3879 (match_operand:DF 3 "register_operand" ""))]
3881 && !TARGET_DISABLE_INDEXING
3883 && REG_OK_FOR_BASE_P (operands[2])
3884 && FP_REGNO_P (REGNO (operands[3]))"
3885 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3887 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3892 [(set (match_operand:SI 0 "register_operand" "")
3893 (plus:SI (match_operand:SI 1 "register_operand" "")
3894 (match_operand:SI 2 "register_operand" "")))
3895 (set (mem:DF (match_dup 0))
3896 (match_operand:DF 3 "register_operand" ""))]
3898 && !TARGET_DISABLE_INDEXING
3899 && REG_OK_FOR_BASE_P (operands[1])
3900 && (TARGET_NO_SPACE_REGS
3901 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3902 && FP_REGNO_P (REGNO (operands[3]))"
3903 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3905 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3909 [(set (match_operand:SI 0 "register_operand" "")
3910 (plus:SI (match_operand:SI 1 "register_operand" "")
3911 (match_operand:SI 2 "register_operand" "")))
3912 (set (mem:DF (match_dup 0))
3913 (match_operand:DF 3 "register_operand" ""))]
3915 && !TARGET_DISABLE_INDEXING
3916 && REG_OK_FOR_BASE_P (operands[2])
3917 && (TARGET_NO_SPACE_REGS
3918 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3919 && FP_REGNO_P (REGNO (operands[3]))"
3920 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3922 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3926 [(set (match_operand:DI 0 "register_operand" "")
3927 (plus:DI (match_operand:DI 1 "register_operand" "")
3928 (match_operand:DI 2 "register_operand" "")))
3929 (set (mem:DF (match_dup 0))
3930 (match_operand:DF 3 "register_operand" ""))]
3932 && !TARGET_DISABLE_INDEXING
3934 && REG_OK_FOR_BASE_P (operands[1])
3935 && (TARGET_NO_SPACE_REGS
3936 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3937 && FP_REGNO_P (REGNO (operands[3]))"
3938 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3940 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3944 [(set (match_operand:DI 0 "register_operand" "")
3945 (plus:DI (match_operand:DI 1 "register_operand" "")
3946 (match_operand:DI 2 "register_operand" "")))
3947 (set (mem:DF (match_dup 0))
3948 (match_operand:DF 3 "register_operand" ""))]
3950 && !TARGET_DISABLE_INDEXING
3952 && REG_OK_FOR_BASE_P (operands[2])
3953 && (TARGET_NO_SPACE_REGS
3954 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3955 && FP_REGNO_P (REGNO (operands[3]))"
3956 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3958 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3962 [(set (match_operand:DF 0 "move_dest_operand"
3964 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3966 "(register_operand (operands[0], DFmode)
3967 || reg_or_0_operand (operands[1], DFmode))
3969 && TARGET_SOFT_FLOAT"
3972 return output_move_double (operands);
3974 [(set_attr "type" "move,store,store,load,load")
3975 (set_attr "length" "8,8,16,8,16")])
3978 [(set (match_operand:DF 0 "move_dest_operand"
3979 "=!*r,*r,*r,*r,*r,Q,f,f,T")
3980 (match_operand:DF 1 "move_src_operand"
3981 "!*r,J,N,K,RQ,*rM,fM,RT,f"))]
3982 "(register_operand (operands[0], DFmode)
3983 || reg_or_0_operand (operands[1], DFmode))
3984 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
3995 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
3996 (set_attr "pa_combine_type" "addmove")
3997 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
4000 (define_expand "movdi"
4001 [(set (match_operand:DI 0 "general_operand" "")
4002 (match_operand:DI 1 "general_operand" ""))]
4006 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
4007 operands[1] = force_const_mem (DImode, operands[1]);
4009 if (emit_move_sequence (operands, DImode, 0))
4013 (define_expand "reload_indi"
4014 [(set (match_operand:DI 0 "register_operand" "=Z")
4015 (match_operand:DI 1 "non_hard_reg_operand" ""))
4016 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4020 if (emit_move_sequence (operands, DImode, operands[2]))
4023 /* We don't want the clobber emitted, so handle this ourselves. */
4024 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4028 (define_expand "reload_outdi"
4029 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4030 (match_operand:DI 1 "register_operand" "Z"))
4031 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4035 if (emit_move_sequence (operands, DImode, operands[2]))
4038 /* We don't want the clobber emitted, so handle this ourselves. */
4039 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4044 [(set (match_operand:DI 0 "register_operand" "=r")
4045 (high:DI (match_operand 1 "" "")))]
4049 rtx op0 = operands[0];
4050 rtx op1 = operands[1];
4052 if (GET_CODE (op1) == CONST_INT)
4054 operands[0] = operand_subword (op0, 1, 0, DImode);
4055 output_asm_insn (\"ldil L'%1,%0\", operands);
4057 operands[0] = operand_subword (op0, 0, 0, DImode);
4058 if (INTVAL (op1) < 0)
4059 output_asm_insn (\"ldi -1,%0\", operands);
4061 output_asm_insn (\"ldi 0,%0\", operands);
4064 else if (GET_CODE (op1) == CONST_DOUBLE)
4066 operands[0] = operand_subword (op0, 1, 0, DImode);
4067 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4068 output_asm_insn (\"ldil L'%1,%0\", operands);
4070 operands[0] = operand_subword (op0, 0, 0, DImode);
4071 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4072 output_asm_insn (singlemove_string (operands), operands);
4078 [(set_attr "type" "move")
4079 (set_attr "length" "8")])
4082 [(set (match_operand:DI 0 "move_dest_operand"
4083 "=r,o,Q,r,r,r,*f,*f,T")
4084 (match_operand:DI 1 "general_operand"
4085 "rM,r,r,o*R,Q,i,*fM,RT,*f"))]
4086 "(register_operand (operands[0], DImode)
4087 || reg_or_0_operand (operands[1], DImode))
4089 && !TARGET_SOFT_FLOAT"
4092 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4093 || (operands[1] == CONST0_RTX (DImode)))
4094 return output_fp_move_double (operands);
4095 return output_move_double (operands);
4097 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
4098 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
4101 [(set (match_operand:DI 0 "move_dest_operand"
4102 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4103 (match_operand:DI 1 "move_src_operand"
4104 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4105 "(register_operand (operands[0], DImode)
4106 || reg_or_0_operand (operands[1], DImode))
4107 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4117 {mfctl|mfctl,w} %%sar,%0
4121 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4122 (set_attr "pa_combine_type" "addmove")
4123 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4126 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4127 (match_operand:DI 1 "register_operand" "f"))]
4130 && !TARGET_DISABLE_INDEXING
4131 && reload_completed"
4133 [(set_attr "type" "fpstore")
4134 (set_attr "pa_combine_type" "addmove")
4135 (set_attr "length" "4")])
4138 [(set (match_operand:DI 0 "register_operand" "")
4139 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4141 (match_operand:DI 2 "register_operand" "")))
4142 (set (mem:DI (match_dup 0))
4143 (match_operand:DI 3 "register_operand" ""))]
4145 && !TARGET_DISABLE_INDEXING
4147 && REG_OK_FOR_BASE_P (operands[2])
4148 && FP_REGNO_P (REGNO (operands[3]))"
4149 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4151 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4156 [(set (match_operand:DI 0 "register_operand" "")
4157 (plus:DI (match_operand:DI 2 "register_operand" "")
4158 (mult:DI (match_operand:DI 1 "register_operand" "")
4160 (set (mem:DI (match_dup 0))
4161 (match_operand:DI 3 "register_operand" ""))]
4163 && !TARGET_DISABLE_INDEXING
4165 && REG_OK_FOR_BASE_P (operands[2])
4166 && FP_REGNO_P (REGNO (operands[3]))"
4167 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4169 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4174 [(set (match_operand:DI 0 "register_operand" "")
4175 (plus:DI (match_operand:DI 1 "register_operand" "")
4176 (match_operand:DI 2 "register_operand" "")))
4177 (set (mem:DI (match_dup 0))
4178 (match_operand:DI 3 "register_operand" ""))]
4180 && !TARGET_DISABLE_INDEXING
4182 && REG_OK_FOR_BASE_P (operands[1])
4183 && (TARGET_NO_SPACE_REGS
4184 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4185 && FP_REGNO_P (REGNO (operands[3]))"
4186 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4188 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4192 [(set (match_operand:DI 0 "register_operand" "")
4193 (plus:DI (match_operand:DI 1 "register_operand" "")
4194 (match_operand:DI 2 "register_operand" "")))
4195 (set (mem:DI (match_dup 0))
4196 (match_operand:DI 3 "register_operand" ""))]
4198 && !TARGET_DISABLE_INDEXING
4200 && REG_OK_FOR_BASE_P (operands[2])
4201 && (TARGET_NO_SPACE_REGS
4202 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4203 && FP_REGNO_P (REGNO (operands[3]))"
4204 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4206 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4210 [(set (match_operand:DI 0 "move_dest_operand"
4212 (match_operand:DI 1 "general_operand"
4214 "(register_operand (operands[0], DImode)
4215 || reg_or_0_operand (operands[1], DImode))
4217 && TARGET_SOFT_FLOAT"
4220 return output_move_double (operands);
4222 [(set_attr "type" "move,store,store,load,load,multi")
4223 (set_attr "length" "8,8,16,8,16,16")])
4226 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4227 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4228 (match_operand:DI 2 "immediate_operand" "i,i")))]
4232 /* Don't output a 64 bit constant, since we can't trust the assembler to
4233 handle it correctly. */
4234 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4235 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4236 if (which_alternative == 1)
4237 output_asm_insn (\"copy %1,%0\", operands);
4238 return \"ldo R'%G2(%R1),%R0\";
4240 [(set_attr "type" "move,move")
4241 (set_attr "length" "4,8")])
4243 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4244 ;; to be reloaded by putting the constant into memory when
4245 ;; reg is a floating point register.
4247 ;; For integer registers we use ldil;ldo to set the appropriate
4250 ;; This must come before the movsf pattern, and it must be present
4251 ;; to handle obscure reloading cases.
4253 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4254 (match_operand:SF 1 "" "?F,m"))]
4255 "GET_CODE (operands[1]) == CONST_DOUBLE
4256 && operands[1] != CONST0_RTX (SFmode)
4257 && ! TARGET_SOFT_FLOAT"
4258 "* return (which_alternative == 0 ? singlemove_string (operands)
4259 : \" fldw%F1 %1,%0\");"
4260 [(set_attr "type" "move,fpload")
4261 (set_attr "length" "8,4")])
4263 (define_expand "movsf"
4264 [(set (match_operand:SF 0 "general_operand" "")
4265 (match_operand:SF 1 "general_operand" ""))]
4269 if (emit_move_sequence (operands, SFmode, 0))
4273 ;; Reloading an SImode or DImode value requires a scratch register if
4274 ;; going in to or out of float point registers.
4276 (define_expand "reload_insf"
4277 [(set (match_operand:SF 0 "register_operand" "=Z")
4278 (match_operand:SF 1 "non_hard_reg_operand" ""))
4279 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4283 if (emit_move_sequence (operands, SFmode, operands[2]))
4286 /* We don't want the clobber emitted, so handle this ourselves. */
4287 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4291 (define_expand "reload_outsf"
4292 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4293 (match_operand:SF 1 "register_operand" "Z"))
4294 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4298 if (emit_move_sequence (operands, SFmode, operands[2]))
4301 /* We don't want the clobber emitted, so handle this ourselves. */
4302 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4307 [(set (match_operand:SF 0 "move_dest_operand"
4309 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4310 "fG,!*rG,RQ,RQ,f,*rG"))]
4311 "(register_operand (operands[0], SFmode)
4312 || reg_or_0_operand (operands[1], SFmode))
4313 && !TARGET_SOFT_FLOAT"
4321 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4322 (set_attr "pa_combine_type" "addmove")
4323 (set_attr "length" "4,4,4,4,4,4")])
4326 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4327 (match_operand:SF 1 "register_operand" "f"))]
4329 && !TARGET_DISABLE_INDEXING
4330 && reload_completed"
4332 [(set_attr "type" "fpstore")
4333 (set_attr "pa_combine_type" "addmove")
4334 (set_attr "length" "4")])
4337 [(set (match_operand:SI 0 "register_operand" "")
4338 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4340 (match_operand:SI 2 "register_operand" "")))
4341 (set (mem:SF (match_dup 0))
4342 (match_operand:SF 3 "register_operand" ""))]
4344 && !TARGET_DISABLE_INDEXING
4345 && REG_OK_FOR_BASE_P (operands[2])
4346 && FP_REGNO_P (REGNO (operands[3]))"
4347 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4349 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4354 [(set (match_operand:SI 0 "register_operand" "")
4355 (plus:SI (match_operand:SI 2 "register_operand" "")
4356 (mult:SI (match_operand:SI 1 "register_operand" "")
4358 (set (mem:SF (match_dup 0))
4359 (match_operand:SF 3 "register_operand" ""))]
4361 && !TARGET_DISABLE_INDEXING
4362 && REG_OK_FOR_BASE_P (operands[2])
4363 && FP_REGNO_P (REGNO (operands[3]))"
4364 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4366 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4371 [(set (match_operand:DI 0 "register_operand" "")
4372 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4374 (match_operand:DI 2 "register_operand" "")))
4375 (set (mem:SF (match_dup 0))
4376 (match_operand:SF 3 "register_operand" ""))]
4378 && !TARGET_DISABLE_INDEXING
4380 && REG_OK_FOR_BASE_P (operands[2])
4381 && FP_REGNO_P (REGNO (operands[3]))"
4382 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4384 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4389 [(set (match_operand:DI 0 "register_operand" "")
4390 (plus:DI (match_operand:DI 2 "register_operand" "")
4391 (mult:DI (match_operand:DI 1 "register_operand" "")
4393 (set (mem:SF (match_dup 0))
4394 (match_operand:SF 3 "register_operand" ""))]
4396 && !TARGET_DISABLE_INDEXING
4398 && REG_OK_FOR_BASE_P (operands[2])
4399 && FP_REGNO_P (REGNO (operands[3]))"
4400 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4402 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4407 [(set (match_operand:SI 0 "register_operand" "")
4408 (plus:SI (match_operand:SI 1 "register_operand" "")
4409 (match_operand:SI 2 "register_operand" "")))
4410 (set (mem:SF (match_dup 0))
4411 (match_operand:SF 3 "register_operand" ""))]
4413 && !TARGET_DISABLE_INDEXING
4414 && REG_OK_FOR_BASE_P (operands[1])
4415 && (TARGET_NO_SPACE_REGS
4416 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4417 && FP_REGNO_P (REGNO (operands[3]))"
4418 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4420 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4424 [(set (match_operand:SI 0 "register_operand" "")
4425 (plus:SI (match_operand:SI 1 "register_operand" "")
4426 (match_operand:SI 2 "register_operand" "")))
4427 (set (mem:SF (match_dup 0))
4428 (match_operand:SF 3 "register_operand" ""))]
4430 && !TARGET_DISABLE_INDEXING
4431 && REG_OK_FOR_BASE_P (operands[2])
4432 && (TARGET_NO_SPACE_REGS
4433 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4434 && FP_REGNO_P (REGNO (operands[3]))"
4435 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4437 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4441 [(set (match_operand:DI 0 "register_operand" "")
4442 (plus:DI (match_operand:DI 1 "register_operand" "")
4443 (match_operand:DI 2 "register_operand" "")))
4444 (set (mem:SF (match_dup 0))
4445 (match_operand:SF 3 "register_operand" ""))]
4447 && !TARGET_DISABLE_INDEXING
4449 && REG_OK_FOR_BASE_P (operands[1])
4450 && (TARGET_NO_SPACE_REGS
4451 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4452 && FP_REGNO_P (REGNO (operands[3]))"
4453 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4455 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4459 [(set (match_operand:DI 0 "register_operand" "")
4460 (plus:DI (match_operand:DI 1 "register_operand" "")
4461 (match_operand:DI 2 "register_operand" "")))
4462 (set (mem:SF (match_dup 0))
4463 (match_operand:SF 3 "register_operand" ""))]
4465 && !TARGET_DISABLE_INDEXING
4467 && REG_OK_FOR_BASE_P (operands[2])
4468 && (TARGET_NO_SPACE_REGS
4469 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4470 && FP_REGNO_P (REGNO (operands[3]))"
4471 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4473 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4477 [(set (match_operand:SF 0 "move_dest_operand"
4479 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4481 "(register_operand (operands[0], SFmode)
4482 || reg_or_0_operand (operands[1], SFmode))
4483 && TARGET_SOFT_FLOAT"
4488 [(set_attr "type" "move,load,store")
4489 (set_attr "pa_combine_type" "addmove")
4490 (set_attr "length" "4,4,4")])
4494 ;;- zero extension instructions
4495 ;; We have define_expand for zero extension patterns to make sure the
4496 ;; operands get loaded into registers. The define_insns accept
4497 ;; memory operands. This gives us better overall code than just
4498 ;; having a pattern that does or does not accept memory operands.
4500 (define_expand "zero_extendqihi2"
4501 [(set (match_operand:HI 0 "register_operand" "")
4503 (match_operand:QI 1 "register_operand" "")))]
4508 [(set (match_operand:HI 0 "register_operand" "=r,r")
4510 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4511 "GET_CODE (operands[1]) != CONST_INT"
4513 {extru|extrw,u} %1,31,8,%0
4515 [(set_attr "type" "shift,load")
4516 (set_attr "length" "4,4")])
4518 (define_expand "zero_extendqisi2"
4519 [(set (match_operand:SI 0 "register_operand" "")
4521 (match_operand:QI 1 "register_operand" "")))]
4526 [(set (match_operand:SI 0 "register_operand" "=r,r")
4528 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4529 "GET_CODE (operands[1]) != CONST_INT"
4531 {extru|extrw,u} %1,31,8,%0
4533 [(set_attr "type" "shift,load")
4534 (set_attr "length" "4,4")])
4536 (define_expand "zero_extendhisi2"
4537 [(set (match_operand:SI 0 "register_operand" "")
4539 (match_operand:HI 1 "register_operand" "")))]
4544 [(set (match_operand:SI 0 "register_operand" "=r,r")
4546 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4547 "GET_CODE (operands[1]) != CONST_INT"
4549 {extru|extrw,u} %1,31,16,%0
4551 [(set_attr "type" "shift,load")
4552 (set_attr "length" "4,4")])
4554 (define_expand "zero_extendqidi2"
4555 [(set (match_operand:DI 0 "register_operand" "")
4557 (match_operand:QI 1 "register_operand" "")))]
4562 [(set (match_operand:DI 0 "register_operand" "=r,r")
4564 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4565 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4569 [(set_attr "type" "shift,load")
4570 (set_attr "length" "4,4")])
4572 (define_expand "zero_extendhidi2"
4573 [(set (match_operand:DI 0 "register_operand" "")
4575 (match_operand:HI 1 "register_operand" "")))]
4580 [(set (match_operand:DI 0 "register_operand" "=r,r")
4582 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4583 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4587 [(set_attr "type" "shift,load")
4588 (set_attr "length" "4,4")])
4590 (define_expand "zero_extendsidi2"
4591 [(set (match_operand:DI 0 "register_operand" "")
4593 (match_operand:SI 1 "register_operand" "")))]
4598 [(set (match_operand:DI 0 "register_operand" "=r,r")
4600 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4601 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4605 [(set_attr "type" "shift,load")
4606 (set_attr "length" "4,4")])
4608 ;;- sign extension instructions
4610 (define_insn "extendhisi2"
4611 [(set (match_operand:SI 0 "register_operand" "=r")
4612 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4614 "{extrs|extrw,s} %1,31,16,%0"
4615 [(set_attr "type" "shift")
4616 (set_attr "length" "4")])
4618 (define_insn "extendqihi2"
4619 [(set (match_operand:HI 0 "register_operand" "=r")
4620 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4622 "{extrs|extrw,s} %1,31,8,%0"
4623 [(set_attr "type" "shift")
4624 (set_attr "length" "4")])
4626 (define_insn "extendqisi2"
4627 [(set (match_operand:SI 0 "register_operand" "=r")
4628 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4630 "{extrs|extrw,s} %1,31,8,%0"
4631 [(set_attr "type" "shift")
4632 (set_attr "length" "4")])
4634 (define_insn "extendqidi2"
4635 [(set (match_operand:DI 0 "register_operand" "=r")
4636 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4638 "extrd,s %1,63,8,%0"
4639 [(set_attr "type" "shift")
4640 (set_attr "length" "4")])
4642 (define_insn "extendhidi2"
4643 [(set (match_operand:DI 0 "register_operand" "=r")
4644 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4646 "extrd,s %1,63,16,%0"
4647 [(set_attr "type" "shift")
4648 (set_attr "length" "4")])
4650 (define_insn "extendsidi2"
4651 [(set (match_operand:DI 0 "register_operand" "=r")
4652 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4654 "extrd,s %1,63,32,%0"
4655 [(set_attr "type" "shift")
4656 (set_attr "length" "4")])
4659 ;; Conversions between float and double.
4661 (define_insn "extendsfdf2"
4662 [(set (match_operand:DF 0 "register_operand" "=f")
4664 (match_operand:SF 1 "register_operand" "f")))]
4665 "! TARGET_SOFT_FLOAT"
4666 "{fcnvff|fcnv},sgl,dbl %1,%0"
4667 [(set_attr "type" "fpalu")
4668 (set_attr "length" "4")])
4670 (define_insn "truncdfsf2"
4671 [(set (match_operand:SF 0 "register_operand" "=f")
4673 (match_operand:DF 1 "register_operand" "f")))]
4674 "! TARGET_SOFT_FLOAT"
4675 "{fcnvff|fcnv},dbl,sgl %1,%0"
4676 [(set_attr "type" "fpalu")
4677 (set_attr "length" "4")])
4679 ;; Conversion between fixed point and floating point.
4680 ;; Note that among the fix-to-float insns
4681 ;; the ones that start with SImode come first.
4682 ;; That is so that an operand that is a CONST_INT
4683 ;; (and therefore lacks a specific machine mode).
4684 ;; will be recognized as SImode (which is always valid)
4685 ;; rather than as QImode or HImode.
4687 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4688 ;; to be reloaded by putting the constant into memory.
4689 ;; It must come before the more general floatsisf2 pattern.
4691 [(set (match_operand:SF 0 "register_operand" "=f")
4692 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4693 "! TARGET_SOFT_FLOAT"
4694 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4695 [(set_attr "type" "fpalu")
4696 (set_attr "length" "8")])
4698 (define_insn "floatsisf2"
4699 [(set (match_operand:SF 0 "register_operand" "=f")
4700 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4701 "! TARGET_SOFT_FLOAT"
4702 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4703 [(set_attr "type" "fpalu")
4704 (set_attr "length" "4")])
4706 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4707 ;; to be reloaded by putting the constant into memory.
4708 ;; It must come before the more general floatsidf2 pattern.
4710 [(set (match_operand:DF 0 "register_operand" "=f")
4711 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4712 "! TARGET_SOFT_FLOAT"
4713 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4714 [(set_attr "type" "fpalu")
4715 (set_attr "length" "8")])
4717 (define_insn "floatsidf2"
4718 [(set (match_operand:DF 0 "register_operand" "=f")
4719 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4720 "! TARGET_SOFT_FLOAT"
4721 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4722 [(set_attr "type" "fpalu")
4723 (set_attr "length" "4")])
4725 (define_expand "floatunssisf2"
4726 [(set (subreg:SI (match_dup 2) 4)
4727 (match_operand:SI 1 "register_operand" ""))
4728 (set (subreg:SI (match_dup 2) 0)
4730 (set (match_operand:SF 0 "register_operand" "")
4731 (float:SF (match_dup 2)))]
4732 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4737 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4740 operands[2] = gen_reg_rtx (DImode);
4743 (define_expand "floatunssidf2"
4744 [(set (subreg:SI (match_dup 2) 4)
4745 (match_operand:SI 1 "register_operand" ""))
4746 (set (subreg:SI (match_dup 2) 0)
4748 (set (match_operand:DF 0 "register_operand" "")
4749 (float:DF (match_dup 2)))]
4750 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4755 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4758 operands[2] = gen_reg_rtx (DImode);
4761 (define_insn "floatdisf2"
4762 [(set (match_operand:SF 0 "register_operand" "=f")
4763 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4764 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4765 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4766 [(set_attr "type" "fpalu")
4767 (set_attr "length" "4")])
4769 (define_insn "floatdidf2"
4770 [(set (match_operand:DF 0 "register_operand" "=f")
4771 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4772 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4773 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4774 [(set_attr "type" "fpalu")
4775 (set_attr "length" "4")])
4777 ;; Convert a float to an actual integer.
4778 ;; Truncation is performed as part of the conversion.
4780 (define_insn "fix_truncsfsi2"
4781 [(set (match_operand:SI 0 "register_operand" "=f")
4782 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4783 "! TARGET_SOFT_FLOAT"
4784 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4785 [(set_attr "type" "fpalu")
4786 (set_attr "length" "4")])
4788 (define_insn "fix_truncdfsi2"
4789 [(set (match_operand:SI 0 "register_operand" "=f")
4790 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4791 "! TARGET_SOFT_FLOAT"
4792 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4793 [(set_attr "type" "fpalu")
4794 (set_attr "length" "4")])
4796 (define_insn "fix_truncsfdi2"
4797 [(set (match_operand:DI 0 "register_operand" "=f")
4798 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4799 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4800 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4801 [(set_attr "type" "fpalu")
4802 (set_attr "length" "4")])
4804 (define_insn "fix_truncdfdi2"
4805 [(set (match_operand:DI 0 "register_operand" "=f")
4806 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4807 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4808 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4809 [(set_attr "type" "fpalu")
4810 (set_attr "length" "4")])
4812 (define_insn "floatunssidf2_pa20"
4813 [(set (match_operand:DF 0 "register_operand" "=f")
4814 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4815 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4817 [(set_attr "type" "fpalu")
4818 (set_attr "length" "4")])
4820 (define_insn "floatunssisf2_pa20"
4821 [(set (match_operand:SF 0 "register_operand" "=f")
4822 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4823 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4825 [(set_attr "type" "fpalu")
4826 (set_attr "length" "4")])
4828 (define_insn "floatunsdisf2"
4829 [(set (match_operand:SF 0 "register_operand" "=f")
4830 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4831 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4832 "fcnv,udw,sgl %1,%0"
4833 [(set_attr "type" "fpalu")
4834 (set_attr "length" "4")])
4836 (define_insn "floatunsdidf2"
4837 [(set (match_operand:DF 0 "register_operand" "=f")
4838 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4839 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4840 "fcnv,udw,dbl %1,%0"
4841 [(set_attr "type" "fpalu")
4842 (set_attr "length" "4")])
4844 (define_insn "fixuns_truncsfsi2"
4845 [(set (match_operand:SI 0 "register_operand" "=f")
4846 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4847 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4848 "fcnv,t,sgl,uw %1,%0"
4849 [(set_attr "type" "fpalu")
4850 (set_attr "length" "4")])
4852 (define_insn "fixuns_truncdfsi2"
4853 [(set (match_operand:SI 0 "register_operand" "=f")
4854 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4855 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4856 "fcnv,t,dbl,uw %1,%0"
4857 [(set_attr "type" "fpalu")
4858 (set_attr "length" "4")])
4860 (define_insn "fixuns_truncsfdi2"
4861 [(set (match_operand:DI 0 "register_operand" "=f")
4862 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4863 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4864 "fcnv,t,sgl,udw %1,%0"
4865 [(set_attr "type" "fpalu")
4866 (set_attr "length" "4")])
4868 (define_insn "fixuns_truncdfdi2"
4869 [(set (match_operand:DI 0 "register_operand" "=f")
4870 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4871 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4872 "fcnv,t,dbl,udw %1,%0"
4873 [(set_attr "type" "fpalu")
4874 (set_attr "length" "4")])
4876 ;;- arithmetic instructions
4878 (define_expand "adddi3"
4879 [(set (match_operand:DI 0 "register_operand" "")
4880 (plus:DI (match_operand:DI 1 "register_operand" "")
4881 (match_operand:DI 2 "adddi3_operand" "")))]
4886 [(set (match_operand:DI 0 "register_operand" "=r")
4887 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4888 (match_operand:DI 2 "arith11_operand" "rI")))]
4892 if (GET_CODE (operands[2]) == CONST_INT)
4894 if (INTVAL (operands[2]) >= 0)
4895 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4897 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4900 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4902 [(set_attr "type" "binary")
4903 (set_attr "length" "8")])
4906 [(set (match_operand:DI 0 "register_operand" "=r,r")
4907 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4908 (match_operand:DI 2 "arith_operand" "r,J")))]
4913 [(set_attr "type" "binary,binary")
4914 (set_attr "pa_combine_type" "addmove")
4915 (set_attr "length" "4,4")])
4918 [(set (match_operand:DI 0 "register_operand" "=r")
4919 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4920 (match_operand:DI 2 "register_operand" "r")))]
4923 [(set_attr "type" "binary")
4924 (set_attr "length" "4")])
4927 [(set (match_operand:SI 0 "register_operand" "=r")
4928 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4929 (match_operand:SI 2 "register_operand" "r")))]
4932 [(set_attr "type" "binary")
4933 (set_attr "length" "4")])
4935 ;; define_splits to optimize cases of adding a constant integer
4936 ;; to a register when the constant does not fit in 14 bits. */
4938 [(set (match_operand:SI 0 "register_operand" "")
4939 (plus:SI (match_operand:SI 1 "register_operand" "")
4940 (match_operand:SI 2 "const_int_operand" "")))
4941 (clobber (match_operand:SI 4 "register_operand" ""))]
4942 "! cint_ok_for_move (INTVAL (operands[2]))
4943 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
4944 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
4945 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
4948 int val = INTVAL (operands[2]);
4949 int low = (val < 0) ? -0x2000 : 0x1fff;
4950 int rest = val - low;
4952 operands[2] = GEN_INT (rest);
4953 operands[3] = GEN_INT (low);
4957 [(set (match_operand:SI 0 "register_operand" "")
4958 (plus:SI (match_operand:SI 1 "register_operand" "")
4959 (match_operand:SI 2 "const_int_operand" "")))
4960 (clobber (match_operand:SI 4 "register_operand" ""))]
4961 "! cint_ok_for_move (INTVAL (operands[2]))"
4962 [(set (match_dup 4) (match_dup 2))
4963 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
4967 HOST_WIDE_INT intval = INTVAL (operands[2]);
4969 /* Try dividing the constant by 2, then 4, and finally 8 to see
4970 if we can get a constant which can be loaded into a register
4971 in a single instruction (cint_ok_for_move).
4973 If that fails, try to negate the constant and subtract it
4974 from our input operand. */
4975 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
4977 operands[2] = GEN_INT (intval / 2);
4978 operands[3] = const2_rtx;
4980 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
4982 operands[2] = GEN_INT (intval / 4);
4983 operands[3] = GEN_INT (4);
4985 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
4987 operands[2] = GEN_INT (intval / 8);
4988 operands[3] = GEN_INT (8);
4990 else if (cint_ok_for_move (-intval))
4992 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
4993 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5000 (define_insn "addsi3"
5001 [(set (match_operand:SI 0 "register_operand" "=r,r")
5002 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5003 (match_operand:SI 2 "arith_operand" "r,J")))]
5006 {addl|add,l} %1,%2,%0
5008 [(set_attr "type" "binary,binary")
5009 (set_attr "pa_combine_type" "addmove")
5010 (set_attr "length" "4,4")])
5012 (define_expand "subdi3"
5013 [(set (match_operand:DI 0 "register_operand" "")
5014 (minus:DI (match_operand:DI 1 "register_operand" "")
5015 (match_operand:DI 2 "register_operand" "")))]
5020 [(set (match_operand:DI 0 "register_operand" "=r")
5021 (minus:DI (match_operand:DI 1 "register_operand" "r")
5022 (match_operand:DI 2 "register_operand" "r")))]
5024 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
5025 [(set_attr "type" "binary")
5026 (set_attr "length" "8")])
5029 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5030 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5031 (match_operand:DI 2 "register_operand" "r,r,!r")))]
5037 [(set_attr "type" "binary,binary,move")
5038 (set_attr "length" "4,4,4")])
5040 (define_expand "subsi3"
5041 [(set (match_operand:SI 0 "register_operand" "")
5042 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5043 (match_operand:SI 2 "register_operand" "")))]
5048 [(set (match_operand:SI 0 "register_operand" "=r,r")
5049 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5050 (match_operand:SI 2 "register_operand" "r,r")))]
5055 [(set_attr "type" "binary,binary")
5056 (set_attr "length" "4,4")])
5059 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5060 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5061 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5067 [(set_attr "type" "binary,binary,move")
5068 (set_attr "length" "4,4,4")])
5070 ;; Clobbering a "register_operand" instead of a match_scratch
5071 ;; in operand3 of millicode calls avoids spilling %r1 and
5072 ;; produces better code.
5074 ;; The mulsi3 insns set up registers for the millicode call.
5075 (define_expand "mulsi3"
5076 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5077 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5078 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5079 (clobber (match_dup 3))
5080 (clobber (reg:SI 26))
5081 (clobber (reg:SI 25))
5082 (clobber (match_dup 4))])
5083 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5087 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5088 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5090 rtx scratch = gen_reg_rtx (DImode);
5091 operands[1] = force_reg (SImode, operands[1]);
5092 operands[2] = force_reg (SImode, operands[2]);
5093 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5094 emit_insn (gen_movsi (operands[0],
5095 gen_rtx_SUBREG (SImode, scratch,
5096 GET_MODE_SIZE (SImode))));
5099 operands[3] = gen_reg_rtx (SImode);
5102 (define_insn "umulsidi3"
5103 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5104 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5105 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5106 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5108 [(set_attr "type" "fpmuldbl")
5109 (set_attr "length" "4")])
5112 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5113 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5114 (match_operand:DI 2 "uint32_operand" "f")))]
5115 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5117 [(set_attr "type" "fpmuldbl")
5118 (set_attr "length" "4")])
5121 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5122 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5123 (match_operand:DI 2 "uint32_operand" "f")))]
5124 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5126 [(set_attr "type" "fpmuldbl")
5127 (set_attr "length" "4")])
5130 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5131 (clobber (match_operand:SI 0 "register_operand" "=a"))
5132 (clobber (reg:SI 26))
5133 (clobber (reg:SI 25))
5134 (clobber (reg:SI 31))]
5136 "* return output_mul_insn (0, insn);"
5137 [(set_attr "type" "milli")
5138 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5141 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5142 (clobber (match_operand:SI 0 "register_operand" "=a"))
5143 (clobber (reg:SI 26))
5144 (clobber (reg:SI 25))
5145 (clobber (reg:SI 2))]
5147 "* return output_mul_insn (0, insn);"
5148 [(set_attr "type" "milli")
5149 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5151 (define_expand "muldi3"
5152 [(set (match_operand:DI 0 "register_operand" "")
5153 (mult:DI (match_operand:DI 1 "register_operand" "")
5154 (match_operand:DI 2 "register_operand" "")))]
5155 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5158 rtx low_product = gen_reg_rtx (DImode);
5159 rtx cross_product1 = gen_reg_rtx (DImode);
5160 rtx cross_product2 = gen_reg_rtx (DImode);
5161 rtx cross_scratch = gen_reg_rtx (DImode);
5162 rtx cross_product = gen_reg_rtx (DImode);
5163 rtx op1l, op1r, op2l, op2r;
5164 rtx op1shifted, op2shifted;
5166 op1shifted = gen_reg_rtx (DImode);
5167 op2shifted = gen_reg_rtx (DImode);
5168 op1l = gen_reg_rtx (SImode);
5169 op1r = gen_reg_rtx (SImode);
5170 op2l = gen_reg_rtx (SImode);
5171 op2r = gen_reg_rtx (SImode);
5173 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5175 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5177 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
5178 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
5179 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
5180 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
5182 /* Emit multiplies for the cross products. */
5183 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5184 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5186 /* Emit a multiply for the low sub-word. */
5187 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5189 /* Sum the cross products and shift them into proper position. */
5190 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5191 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5193 /* Add the cross product to the low product and store the result
5194 into the output operand . */
5195 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5199 ;;; Division and mod.
5200 (define_expand "divsi3"
5201 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5202 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5203 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5204 (clobber (match_dup 3))
5205 (clobber (match_dup 4))
5206 (clobber (reg:SI 26))
5207 (clobber (reg:SI 25))
5208 (clobber (match_dup 5))])
5209 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5213 operands[3] = gen_reg_rtx (SImode);
5216 operands[5] = gen_rtx_REG (SImode, 2);
5217 operands[4] = operands[5];
5221 operands[5] = gen_rtx_REG (SImode, 31);
5222 operands[4] = gen_reg_rtx (SImode);
5224 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5230 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5231 (clobber (match_operand:SI 1 "register_operand" "=a"))
5232 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5233 (clobber (reg:SI 26))
5234 (clobber (reg:SI 25))
5235 (clobber (reg:SI 31))]
5238 return output_div_insn (operands, 0, insn);"
5239 [(set_attr "type" "milli")
5240 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5244 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5245 (clobber (match_operand:SI 1 "register_operand" "=a"))
5246 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5247 (clobber (reg:SI 26))
5248 (clobber (reg:SI 25))
5249 (clobber (reg:SI 2))]
5252 return output_div_insn (operands, 0, insn);"
5253 [(set_attr "type" "milli")
5254 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5256 (define_expand "udivsi3"
5257 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5258 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5259 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5260 (clobber (match_dup 3))
5261 (clobber (match_dup 4))
5262 (clobber (reg:SI 26))
5263 (clobber (reg:SI 25))
5264 (clobber (match_dup 5))])
5265 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5269 operands[3] = gen_reg_rtx (SImode);
5273 operands[5] = gen_rtx_REG (SImode, 2);
5274 operands[4] = operands[5];
5278 operands[5] = gen_rtx_REG (SImode, 31);
5279 operands[4] = gen_reg_rtx (SImode);
5281 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5287 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5288 (clobber (match_operand:SI 1 "register_operand" "=a"))
5289 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5290 (clobber (reg:SI 26))
5291 (clobber (reg:SI 25))
5292 (clobber (reg:SI 31))]
5295 return output_div_insn (operands, 1, insn);"
5296 [(set_attr "type" "milli")
5297 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5301 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5302 (clobber (match_operand:SI 1 "register_operand" "=a"))
5303 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5304 (clobber (reg:SI 26))
5305 (clobber (reg:SI 25))
5306 (clobber (reg:SI 2))]
5309 return output_div_insn (operands, 1, insn);"
5310 [(set_attr "type" "milli")
5311 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5313 (define_expand "modsi3"
5314 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5315 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5316 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5317 (clobber (match_dup 3))
5318 (clobber (match_dup 4))
5319 (clobber (reg:SI 26))
5320 (clobber (reg:SI 25))
5321 (clobber (match_dup 5))])
5322 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5328 operands[5] = gen_rtx_REG (SImode, 2);
5329 operands[4] = operands[5];
5333 operands[5] = gen_rtx_REG (SImode, 31);
5334 operands[4] = gen_reg_rtx (SImode);
5336 operands[3] = gen_reg_rtx (SImode);
5340 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5341 (clobber (match_operand:SI 0 "register_operand" "=a"))
5342 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5343 (clobber (reg:SI 26))
5344 (clobber (reg:SI 25))
5345 (clobber (reg:SI 31))]
5348 return output_mod_insn (0, insn);"
5349 [(set_attr "type" "milli")
5350 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5353 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5354 (clobber (match_operand:SI 0 "register_operand" "=a"))
5355 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5356 (clobber (reg:SI 26))
5357 (clobber (reg:SI 25))
5358 (clobber (reg:SI 2))]
5361 return output_mod_insn (0, insn);"
5362 [(set_attr "type" "milli")
5363 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5365 (define_expand "umodsi3"
5366 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5367 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5368 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5369 (clobber (match_dup 3))
5370 (clobber (match_dup 4))
5371 (clobber (reg:SI 26))
5372 (clobber (reg:SI 25))
5373 (clobber (match_dup 5))])
5374 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5380 operands[5] = gen_rtx_REG (SImode, 2);
5381 operands[4] = operands[5];
5385 operands[5] = gen_rtx_REG (SImode, 31);
5386 operands[4] = gen_reg_rtx (SImode);
5388 operands[3] = gen_reg_rtx (SImode);
5392 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5393 (clobber (match_operand:SI 0 "register_operand" "=a"))
5394 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5395 (clobber (reg:SI 26))
5396 (clobber (reg:SI 25))
5397 (clobber (reg:SI 31))]
5400 return output_mod_insn (1, insn);"
5401 [(set_attr "type" "milli")
5402 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5405 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5406 (clobber (match_operand:SI 0 "register_operand" "=a"))
5407 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5408 (clobber (reg:SI 26))
5409 (clobber (reg:SI 25))
5410 (clobber (reg:SI 2))]
5413 return output_mod_insn (1, insn);"
5414 [(set_attr "type" "milli")
5415 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5417 ;;- and instructions
5418 ;; We define DImode `and` so with DImode `not` we can get
5419 ;; DImode `andn`. Other combinations are possible.
5421 (define_expand "anddi3"
5422 [(set (match_operand:DI 0 "register_operand" "")
5423 (and:DI (match_operand:DI 1 "and_operand" "")
5424 (match_operand:DI 2 "and_operand" "")))]
5430 /* One operand must be a register operand. */
5431 if (!register_operand (operands[1], DImode)
5432 && !register_operand (operands[2], DImode))
5437 /* Both operands must be register operands. */
5438 if (!register_operand (operands[1], DImode)
5439 || !register_operand (operands[2], DImode))
5445 [(set (match_operand:DI 0 "register_operand" "=r")
5446 (and:DI (match_operand:DI 1 "register_operand" "%r")
5447 (match_operand:DI 2 "register_operand" "r")))]
5449 "and %1,%2,%0\;and %R1,%R2,%R0"
5450 [(set_attr "type" "binary")
5451 (set_attr "length" "8")])
5454 [(set (match_operand:DI 0 "register_operand" "=r,r")
5455 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5456 (match_operand:DI 2 "and_operand" "rO,P")))]
5458 "* return output_64bit_and (operands); "
5459 [(set_attr "type" "binary")
5460 (set_attr "length" "4")])
5462 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5463 ; constant with ldil;ldo.
5464 (define_insn "andsi3"
5465 [(set (match_operand:SI 0 "register_operand" "=r,r")
5466 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5467 (match_operand:SI 2 "and_operand" "rO,P")))]
5469 "* return output_and (operands); "
5470 [(set_attr "type" "binary,shift")
5471 (set_attr "length" "4,4")])
5474 [(set (match_operand:DI 0 "register_operand" "=r")
5475 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5476 (match_operand:DI 2 "register_operand" "r")))]
5478 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5479 [(set_attr "type" "binary")
5480 (set_attr "length" "8")])
5483 [(set (match_operand:DI 0 "register_operand" "=r")
5484 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5485 (match_operand:DI 2 "register_operand" "r")))]
5488 [(set_attr "type" "binary")
5489 (set_attr "length" "4")])
5492 [(set (match_operand:SI 0 "register_operand" "=r")
5493 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5494 (match_operand:SI 2 "register_operand" "r")))]
5497 [(set_attr "type" "binary")
5498 (set_attr "length" "4")])
5500 (define_expand "iordi3"
5501 [(set (match_operand:DI 0 "register_operand" "")
5502 (ior:DI (match_operand:DI 1 "ior_operand" "")
5503 (match_operand:DI 2 "ior_operand" "")))]
5509 /* One operand must be a register operand. */
5510 if (!register_operand (operands[1], DImode)
5511 && !register_operand (operands[2], DImode))
5516 /* Both operands must be register operands. */
5517 if (!register_operand (operands[1], DImode)
5518 || !register_operand (operands[2], DImode))
5524 [(set (match_operand:DI 0 "register_operand" "=r")
5525 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5526 (match_operand:DI 2 "register_operand" "r")))]
5528 "or %1,%2,%0\;or %R1,%R2,%R0"
5529 [(set_attr "type" "binary")
5530 (set_attr "length" "8")])
5533 [(set (match_operand:DI 0 "register_operand" "=r,r")
5534 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5535 (match_operand:DI 2 "ior_operand" "M,i")))]
5537 "* return output_64bit_ior (operands); "
5538 [(set_attr "type" "binary,shift")
5539 (set_attr "length" "4,4")])
5542 [(set (match_operand:DI 0 "register_operand" "=r")
5543 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5544 (match_operand:DI 2 "register_operand" "r")))]
5547 [(set_attr "type" "binary")
5548 (set_attr "length" "4")])
5550 ;; Need a define_expand because we've run out of CONST_OK... characters.
5551 (define_expand "iorsi3"
5552 [(set (match_operand:SI 0 "register_operand" "")
5553 (ior:SI (match_operand:SI 1 "register_operand" "")
5554 (match_operand:SI 2 "arith32_operand" "")))]
5558 if (! (ior_operand (operands[2], SImode)
5559 || register_operand (operands[2], SImode)))
5560 operands[2] = force_reg (SImode, operands[2]);
5564 [(set (match_operand:SI 0 "register_operand" "=r,r")
5565 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5566 (match_operand:SI 2 "ior_operand" "M,i")))]
5568 "* return output_ior (operands); "
5569 [(set_attr "type" "binary,shift")
5570 (set_attr "length" "4,4")])
5573 [(set (match_operand:SI 0 "register_operand" "=r")
5574 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5575 (match_operand:SI 2 "register_operand" "r")))]
5578 [(set_attr "type" "binary")
5579 (set_attr "length" "4")])
5581 (define_expand "xordi3"
5582 [(set (match_operand:DI 0 "register_operand" "")
5583 (xor:DI (match_operand:DI 1 "register_operand" "")
5584 (match_operand:DI 2 "register_operand" "")))]
5591 [(set (match_operand:DI 0 "register_operand" "=r")
5592 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5593 (match_operand:DI 2 "register_operand" "r")))]
5595 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5596 [(set_attr "type" "binary")
5597 (set_attr "length" "8")])
5600 [(set (match_operand:DI 0 "register_operand" "=r")
5601 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5602 (match_operand:DI 2 "register_operand" "r")))]
5605 [(set_attr "type" "binary")
5606 (set_attr "length" "4")])
5608 (define_insn "xorsi3"
5609 [(set (match_operand:SI 0 "register_operand" "=r")
5610 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5611 (match_operand:SI 2 "register_operand" "r")))]
5614 [(set_attr "type" "binary")
5615 (set_attr "length" "4")])
5617 (define_expand "negdi2"
5618 [(set (match_operand:DI 0 "register_operand" "")
5619 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5624 [(set (match_operand:DI 0 "register_operand" "=r")
5625 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5627 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5628 [(set_attr "type" "unary")
5629 (set_attr "length" "8")])
5632 [(set (match_operand:DI 0 "register_operand" "=r")
5633 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5636 [(set_attr "type" "unary")
5637 (set_attr "length" "4")])
5639 (define_insn "negsi2"
5640 [(set (match_operand:SI 0 "register_operand" "=r")
5641 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5644 [(set_attr "type" "unary")
5645 (set_attr "length" "4")])
5647 (define_expand "one_cmpldi2"
5648 [(set (match_operand:DI 0 "register_operand" "")
5649 (not:DI (match_operand:DI 1 "register_operand" "")))]
5656 [(set (match_operand:DI 0 "register_operand" "=r")
5657 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5659 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5660 [(set_attr "type" "unary")
5661 (set_attr "length" "8")])
5664 [(set (match_operand:DI 0 "register_operand" "=r")
5665 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5668 [(set_attr "type" "unary")
5669 (set_attr "length" "4")])
5671 (define_insn "one_cmplsi2"
5672 [(set (match_operand:SI 0 "register_operand" "=r")
5673 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5676 [(set_attr "type" "unary")
5677 (set_attr "length" "4")])
5679 ;; Floating point arithmetic instructions.
5681 (define_insn "adddf3"
5682 [(set (match_operand:DF 0 "register_operand" "=f")
5683 (plus:DF (match_operand:DF 1 "register_operand" "f")
5684 (match_operand:DF 2 "register_operand" "f")))]
5685 "! TARGET_SOFT_FLOAT"
5687 [(set_attr "type" "fpalu")
5688 (set_attr "pa_combine_type" "faddsub")
5689 (set_attr "length" "4")])
5691 (define_insn "addsf3"
5692 [(set (match_operand:SF 0 "register_operand" "=f")
5693 (plus:SF (match_operand:SF 1 "register_operand" "f")
5694 (match_operand:SF 2 "register_operand" "f")))]
5695 "! TARGET_SOFT_FLOAT"
5697 [(set_attr "type" "fpalu")
5698 (set_attr "pa_combine_type" "faddsub")
5699 (set_attr "length" "4")])
5701 (define_insn "subdf3"
5702 [(set (match_operand:DF 0 "register_operand" "=f")
5703 (minus:DF (match_operand:DF 1 "register_operand" "f")
5704 (match_operand:DF 2 "register_operand" "f")))]
5705 "! TARGET_SOFT_FLOAT"
5707 [(set_attr "type" "fpalu")
5708 (set_attr "pa_combine_type" "faddsub")
5709 (set_attr "length" "4")])
5711 (define_insn "subsf3"
5712 [(set (match_operand:SF 0 "register_operand" "=f")
5713 (minus:SF (match_operand:SF 1 "register_operand" "f")
5714 (match_operand:SF 2 "register_operand" "f")))]
5715 "! TARGET_SOFT_FLOAT"
5717 [(set_attr "type" "fpalu")
5718 (set_attr "pa_combine_type" "faddsub")
5719 (set_attr "length" "4")])
5721 (define_insn "muldf3"
5722 [(set (match_operand:DF 0 "register_operand" "=f")
5723 (mult:DF (match_operand:DF 1 "register_operand" "f")
5724 (match_operand:DF 2 "register_operand" "f")))]
5725 "! TARGET_SOFT_FLOAT"
5727 [(set_attr "type" "fpmuldbl")
5728 (set_attr "pa_combine_type" "fmpy")
5729 (set_attr "length" "4")])
5731 (define_insn "mulsf3"
5732 [(set (match_operand:SF 0 "register_operand" "=f")
5733 (mult:SF (match_operand:SF 1 "register_operand" "f")
5734 (match_operand:SF 2 "register_operand" "f")))]
5735 "! TARGET_SOFT_FLOAT"
5737 [(set_attr "type" "fpmulsgl")
5738 (set_attr "pa_combine_type" "fmpy")
5739 (set_attr "length" "4")])
5741 (define_insn "divdf3"
5742 [(set (match_operand:DF 0 "register_operand" "=f")
5743 (div:DF (match_operand:DF 1 "register_operand" "f")
5744 (match_operand:DF 2 "register_operand" "f")))]
5745 "! TARGET_SOFT_FLOAT"
5747 [(set_attr "type" "fpdivdbl")
5748 (set_attr "length" "4")])
5750 (define_insn "divsf3"
5751 [(set (match_operand:SF 0 "register_operand" "=f")
5752 (div:SF (match_operand:SF 1 "register_operand" "f")
5753 (match_operand:SF 2 "register_operand" "f")))]
5754 "! TARGET_SOFT_FLOAT"
5756 [(set_attr "type" "fpdivsgl")
5757 (set_attr "length" "4")])
5759 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5760 ;; negation can be done by subtracting from plus zero. However, this
5761 ;; violates the IEEE standard when negating plus and minus zero.
5762 (define_expand "negdf2"
5763 [(parallel [(set (match_operand:DF 0 "register_operand" "")
5764 (neg:DF (match_operand:DF 1 "register_operand" "")))
5765 (use (match_dup 2))])]
5766 "! TARGET_SOFT_FLOAT"
5768 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5769 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5772 operands[2] = force_reg (DFmode,
5773 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
5774 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
5779 (define_insn "negdf2_fast"
5780 [(set (match_operand:DF 0 "register_operand" "=f")
5781 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
5782 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5786 return \"fneg,dbl %1,%0\";
5788 return \"fsub,dbl %%fr0,%1,%0\";
5790 [(set_attr "type" "fpalu")
5791 (set_attr "length" "4")])
5793 (define_expand "negsf2"
5794 [(parallel [(set (match_operand:SF 0 "register_operand" "")
5795 (neg:SF (match_operand:SF 1 "register_operand" "")))
5796 (use (match_dup 2))])]
5797 "! TARGET_SOFT_FLOAT"
5799 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5800 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
5803 operands[2] = force_reg (SFmode,
5804 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
5805 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
5810 (define_insn "negsf2_fast"
5811 [(set (match_operand:SF 0 "register_operand" "=f")
5812 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
5813 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5817 return \"fneg,sgl %1,%0\";
5819 return \"fsub,sgl %%fr0,%1,%0\";
5821 [(set_attr "type" "fpalu")
5822 (set_attr "length" "4")])
5824 (define_insn "absdf2"
5825 [(set (match_operand:DF 0 "register_operand" "=f")
5826 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
5827 "! TARGET_SOFT_FLOAT"
5829 [(set_attr "type" "fpalu")
5830 (set_attr "length" "4")])
5832 (define_insn "abssf2"
5833 [(set (match_operand:SF 0 "register_operand" "=f")
5834 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
5835 "! TARGET_SOFT_FLOAT"
5837 [(set_attr "type" "fpalu")
5838 (set_attr "length" "4")])
5840 (define_insn "sqrtdf2"
5841 [(set (match_operand:DF 0 "register_operand" "=f")
5842 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
5843 "! TARGET_SOFT_FLOAT"
5845 [(set_attr "type" "fpsqrtdbl")
5846 (set_attr "length" "4")])
5848 (define_insn "sqrtsf2"
5849 [(set (match_operand:SF 0 "register_operand" "=f")
5850 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
5851 "! TARGET_SOFT_FLOAT"
5853 [(set_attr "type" "fpsqrtsgl")
5854 (set_attr "length" "4")])
5856 ;; PA 2.0 floating point instructions
5860 [(set (match_operand:DF 0 "register_operand" "=f")
5861 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5862 (match_operand:DF 2 "register_operand" "f"))
5863 (match_operand:DF 3 "register_operand" "f")))]
5864 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5865 "fmpyfadd,dbl %1,%2,%3,%0"
5866 [(set_attr "type" "fpmuldbl")
5867 (set_attr "length" "4")])
5870 [(set (match_operand:DF 0 "register_operand" "=f")
5871 (plus:DF (match_operand:DF 1 "register_operand" "f")
5872 (mult:DF (match_operand:DF 2 "register_operand" "f")
5873 (match_operand:DF 3 "register_operand" "f"))))]
5874 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5875 "fmpyfadd,dbl %2,%3,%1,%0"
5876 [(set_attr "type" "fpmuldbl")
5877 (set_attr "length" "4")])
5880 [(set (match_operand:SF 0 "register_operand" "=f")
5881 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5882 (match_operand:SF 2 "register_operand" "f"))
5883 (match_operand:SF 3 "register_operand" "f")))]
5884 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5885 "fmpyfadd,sgl %1,%2,%3,%0"
5886 [(set_attr "type" "fpmulsgl")
5887 (set_attr "length" "4")])
5890 [(set (match_operand:SF 0 "register_operand" "=f")
5891 (plus:SF (match_operand:SF 1 "register_operand" "f")
5892 (mult:SF (match_operand:SF 2 "register_operand" "f")
5893 (match_operand:SF 3 "register_operand" "f"))))]
5894 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5895 "fmpyfadd,sgl %2,%3,%1,%0"
5896 [(set_attr "type" "fpmulsgl")
5897 (set_attr "length" "4")])
5899 ; fmpynfadd patterns
5901 [(set (match_operand:DF 0 "register_operand" "=f")
5902 (minus:DF (match_operand:DF 1 "register_operand" "f")
5903 (mult:DF (match_operand:DF 2 "register_operand" "f")
5904 (match_operand:DF 3 "register_operand" "f"))))]
5905 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5906 "fmpynfadd,dbl %2,%3,%1,%0"
5907 [(set_attr "type" "fpmuldbl")
5908 (set_attr "length" "4")])
5911 [(set (match_operand:SF 0 "register_operand" "=f")
5912 (minus:SF (match_operand:SF 1 "register_operand" "f")
5913 (mult:SF (match_operand:SF 2 "register_operand" "f")
5914 (match_operand:SF 3 "register_operand" "f"))))]
5915 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5916 "fmpynfadd,sgl %2,%3,%1,%0"
5917 [(set_attr "type" "fpmulsgl")
5918 (set_attr "length" "4")])
5922 [(set (match_operand:DF 0 "register_operand" "=f")
5923 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
5924 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5926 [(set_attr "type" "fpalu")
5927 (set_attr "length" "4")])
5930 [(set (match_operand:SF 0 "register_operand" "=f")
5931 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
5932 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5934 [(set_attr "type" "fpalu")
5935 (set_attr "length" "4")])
5937 ;; Generating a fused multiply sequence is a win for this case as it will
5938 ;; reduce the latency for the fused case without impacting the plain
5941 ;; Similar possibilities exist for fnegabs, shadd and other insns which
5942 ;; perform two operations with the result of the first feeding the second.
5944 [(set (match_operand:DF 0 "register_operand" "=f")
5945 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5946 (match_operand:DF 2 "register_operand" "f"))
5947 (match_operand:DF 3 "register_operand" "f")))
5948 (set (match_operand:DF 4 "register_operand" "=&f")
5949 (mult:DF (match_dup 1) (match_dup 2)))]
5950 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5951 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5952 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5954 [(set_attr "type" "fpmuldbl")
5955 (set_attr "length" "8")])
5957 ;; We want to split this up during scheduling since we want both insns
5958 ;; to schedule independently.
5960 [(set (match_operand:DF 0 "register_operand" "")
5961 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5962 (match_operand:DF 2 "register_operand" ""))
5963 (match_operand:DF 3 "register_operand" "")))
5964 (set (match_operand:DF 4 "register_operand" "")
5965 (mult:DF (match_dup 1) (match_dup 2)))]
5966 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5967 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5968 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
5973 [(set (match_operand:SF 0 "register_operand" "=f")
5974 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5975 (match_operand:SF 2 "register_operand" "f"))
5976 (match_operand:SF 3 "register_operand" "f")))
5977 (set (match_operand:SF 4 "register_operand" "=&f")
5978 (mult:SF (match_dup 1) (match_dup 2)))]
5979 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5980 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5981 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5983 [(set_attr "type" "fpmuldbl")
5984 (set_attr "length" "8")])
5986 ;; We want to split this up during scheduling since we want both insns
5987 ;; to schedule independently.
5989 [(set (match_operand:SF 0 "register_operand" "")
5990 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5991 (match_operand:SF 2 "register_operand" ""))
5992 (match_operand:SF 3 "register_operand" "")))
5993 (set (match_operand:SF 4 "register_operand" "")
5994 (mult:SF (match_dup 1) (match_dup 2)))]
5995 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5996 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5997 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
6001 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6004 [(set (match_operand:DF 0 "register_operand" "=f")
6005 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6006 (match_operand:DF 2 "register_operand" "f"))))]
6007 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6008 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6009 [(set_attr "type" "fpmuldbl")
6010 (set_attr "length" "4")])
6013 [(set (match_operand:SF 0 "register_operand" "=f")
6014 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6015 (match_operand:SF 2 "register_operand" "f"))))]
6016 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6017 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6018 [(set_attr "type" "fpmuldbl")
6019 (set_attr "length" "4")])
6022 [(set (match_operand:DF 0 "register_operand" "=f")
6023 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6024 (match_operand:DF 2 "register_operand" "f"))))
6025 (set (match_operand:DF 3 "register_operand" "=&f")
6026 (mult:DF (match_dup 1) (match_dup 2)))]
6027 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6028 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6029 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6031 [(set_attr "type" "fpmuldbl")
6032 (set_attr "length" "8")])
6035 [(set (match_operand:DF 0 "register_operand" "")
6036 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6037 (match_operand:DF 2 "register_operand" ""))))
6038 (set (match_operand:DF 3 "register_operand" "")
6039 (mult:DF (match_dup 1) (match_dup 2)))]
6040 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6041 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6042 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6046 [(set (match_operand:SF 0 "register_operand" "=f")
6047 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6048 (match_operand:SF 2 "register_operand" "f"))))
6049 (set (match_operand:SF 3 "register_operand" "=&f")
6050 (mult:SF (match_dup 1) (match_dup 2)))]
6051 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6052 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6053 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6055 [(set_attr "type" "fpmuldbl")
6056 (set_attr "length" "8")])
6059 [(set (match_operand:SF 0 "register_operand" "")
6060 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6061 (match_operand:SF 2 "register_operand" ""))))
6062 (set (match_operand:SF 3 "register_operand" "")
6063 (mult:SF (match_dup 1) (match_dup 2)))]
6064 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6065 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6066 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6069 ;; Now fused multiplies with the result of the multiply negated.
6071 [(set (match_operand:DF 0 "register_operand" "=f")
6072 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6073 (match_operand:DF 2 "register_operand" "f")))
6074 (match_operand:DF 3 "register_operand" "f")))]
6075 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6076 "fmpynfadd,dbl %1,%2,%3,%0"
6077 [(set_attr "type" "fpmuldbl")
6078 (set_attr "length" "4")])
6081 [(set (match_operand:SF 0 "register_operand" "=f")
6082 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6083 (match_operand:SF 2 "register_operand" "f")))
6084 (match_operand:SF 3 "register_operand" "f")))]
6085 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6086 "fmpynfadd,sgl %1,%2,%3,%0"
6087 [(set_attr "type" "fpmuldbl")
6088 (set_attr "length" "4")])
6091 [(set (match_operand:DF 0 "register_operand" "=f")
6092 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6093 (match_operand:DF 2 "register_operand" "f")))
6094 (match_operand:DF 3 "register_operand" "f")))
6095 (set (match_operand:DF 4 "register_operand" "=&f")
6096 (mult:DF (match_dup 1) (match_dup 2)))]
6097 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6098 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6099 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6101 [(set_attr "type" "fpmuldbl")
6102 (set_attr "length" "8")])
6105 [(set (match_operand:DF 0 "register_operand" "")
6106 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6107 (match_operand:DF 2 "register_operand" "")))
6108 (match_operand:DF 3 "register_operand" "")))
6109 (set (match_operand:DF 4 "register_operand" "")
6110 (mult:DF (match_dup 1) (match_dup 2)))]
6111 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6112 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6113 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6118 [(set (match_operand:SF 0 "register_operand" "=f")
6119 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6120 (match_operand:SF 2 "register_operand" "f")))
6121 (match_operand:SF 3 "register_operand" "f")))
6122 (set (match_operand:SF 4 "register_operand" "=&f")
6123 (mult:SF (match_dup 1) (match_dup 2)))]
6124 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6125 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6126 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6128 [(set_attr "type" "fpmuldbl")
6129 (set_attr "length" "8")])
6132 [(set (match_operand:SF 0 "register_operand" "")
6133 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6134 (match_operand:SF 2 "register_operand" "")))
6135 (match_operand:SF 3 "register_operand" "")))
6136 (set (match_operand:SF 4 "register_operand" "")
6137 (mult:SF (match_dup 1) (match_dup 2)))]
6138 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6139 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6140 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6145 [(set (match_operand:DF 0 "register_operand" "=f")
6146 (minus:DF (match_operand:DF 3 "register_operand" "f")
6147 (mult:DF (match_operand:DF 1 "register_operand" "f")
6148 (match_operand:DF 2 "register_operand" "f"))))
6149 (set (match_operand:DF 4 "register_operand" "=&f")
6150 (mult:DF (match_dup 1) (match_dup 2)))]
6151 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6152 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6153 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6155 [(set_attr "type" "fpmuldbl")
6156 (set_attr "length" "8")])
6159 [(set (match_operand:DF 0 "register_operand" "")
6160 (minus:DF (match_operand:DF 3 "register_operand" "")
6161 (mult:DF (match_operand:DF 1 "register_operand" "")
6162 (match_operand:DF 2 "register_operand" ""))))
6163 (set (match_operand:DF 4 "register_operand" "")
6164 (mult:DF (match_dup 1) (match_dup 2)))]
6165 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6166 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6167 (set (match_dup 0) (minus:DF (match_dup 3)
6168 (mult:DF (match_dup 1) (match_dup 2))))]
6172 [(set (match_operand:SF 0 "register_operand" "=f")
6173 (minus:SF (match_operand:SF 3 "register_operand" "f")
6174 (mult:SF (match_operand:SF 1 "register_operand" "f")
6175 (match_operand:SF 2 "register_operand" "f"))))
6176 (set (match_operand:SF 4 "register_operand" "=&f")
6177 (mult:SF (match_dup 1) (match_dup 2)))]
6178 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6179 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6180 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6182 [(set_attr "type" "fpmuldbl")
6183 (set_attr "length" "8")])
6186 [(set (match_operand:SF 0 "register_operand" "")
6187 (minus:SF (match_operand:SF 3 "register_operand" "")
6188 (mult:SF (match_operand:SF 1 "register_operand" "")
6189 (match_operand:SF 2 "register_operand" ""))))
6190 (set (match_operand:SF 4 "register_operand" "")
6191 (mult:SF (match_dup 1) (match_dup 2)))]
6192 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6193 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6194 (set (match_dup 0) (minus:SF (match_dup 3)
6195 (mult:SF (match_dup 1) (match_dup 2))))]
6199 [(set (match_operand:DF 0 "register_operand" "=f")
6200 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6201 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6202 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6203 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6205 [(set_attr "type" "fpalu")
6206 (set_attr "length" "8")])
6209 [(set (match_operand:DF 0 "register_operand" "")
6210 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6211 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6212 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6213 [(set (match_dup 2) (abs:DF (match_dup 1)))
6214 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6218 [(set (match_operand:SF 0 "register_operand" "=f")
6219 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6220 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6221 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6222 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6224 [(set_attr "type" "fpalu")
6225 (set_attr "length" "8")])
6228 [(set (match_operand:SF 0 "register_operand" "")
6229 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6230 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6231 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6232 [(set (match_dup 2) (abs:SF (match_dup 1)))
6233 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6236 ;;- Shift instructions
6238 ;; Optimized special case of shifting.
6241 [(set (match_operand:SI 0 "register_operand" "=r")
6242 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6246 [(set_attr "type" "load")
6247 (set_attr "length" "4")])
6250 [(set (match_operand:SI 0 "register_operand" "=r")
6251 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6255 [(set_attr "type" "load")
6256 (set_attr "length" "4")])
6259 [(set (match_operand:SI 0 "register_operand" "=r")
6260 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6261 (match_operand:SI 3 "shadd_operand" ""))
6262 (match_operand:SI 1 "register_operand" "r")))]
6264 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6265 [(set_attr "type" "binary")
6266 (set_attr "length" "4")])
6269 [(set (match_operand:DI 0 "register_operand" "=r")
6270 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6271 (match_operand:DI 3 "shadd_operand" ""))
6272 (match_operand:DI 1 "register_operand" "r")))]
6274 "shladd,l %2,%O3,%1,%0"
6275 [(set_attr "type" "binary")
6276 (set_attr "length" "4")])
6278 (define_expand "ashlsi3"
6279 [(set (match_operand:SI 0 "register_operand" "")
6280 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6281 (match_operand:SI 2 "arith32_operand" "")))]
6285 if (GET_CODE (operands[2]) != CONST_INT)
6287 rtx temp = gen_reg_rtx (SImode);
6288 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6289 if (GET_CODE (operands[1]) == CONST_INT)
6290 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6292 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6295 /* Make sure both inputs are not constants,
6296 there are no patterns for that. */
6297 operands[1] = force_reg (SImode, operands[1]);
6301 [(set (match_operand:SI 0 "register_operand" "=r")
6302 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6303 (match_operand:SI 2 "const_int_operand" "n")))]
6305 "{zdep|depw,z} %1,%P2,%L2,%0"
6306 [(set_attr "type" "shift")
6307 (set_attr "length" "4")])
6309 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6310 ; Doing it like this makes slightly better code since reload can
6311 ; replace a register with a known value in range -16..15 with a
6312 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6313 ; but since we have no more CONST_OK... characters, that is not
6315 (define_insn "zvdep32"
6316 [(set (match_operand:SI 0 "register_operand" "=r,r")
6317 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6318 (minus:SI (const_int 31)
6319 (match_operand:SI 2 "register_operand" "q,q"))))]
6322 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6323 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6324 [(set_attr "type" "shift,shift")
6325 (set_attr "length" "4,4")])
6327 (define_insn "zvdep_imm32"
6328 [(set (match_operand:SI 0 "register_operand" "=r")
6329 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6330 (minus:SI (const_int 31)
6331 (match_operand:SI 2 "register_operand" "q"))))]
6335 int x = INTVAL (operands[1]);
6336 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6337 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6338 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6340 [(set_attr "type" "shift")
6341 (set_attr "length" "4")])
6343 (define_insn "vdepi_ior"
6344 [(set (match_operand:SI 0 "register_operand" "=r")
6345 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6346 (minus:SI (const_int 31)
6347 (match_operand:SI 2 "register_operand" "q")))
6348 (match_operand:SI 3 "register_operand" "0")))]
6349 ; accept ...0001...1, can this be generalized?
6350 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6353 int x = INTVAL (operands[1]);
6354 operands[2] = GEN_INT (exact_log2 (x + 1));
6355 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6357 [(set_attr "type" "shift")
6358 (set_attr "length" "4")])
6360 (define_insn "vdepi_and"
6361 [(set (match_operand:SI 0 "register_operand" "=r")
6362 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6363 (minus:SI (const_int 31)
6364 (match_operand:SI 2 "register_operand" "q")))
6365 (match_operand:SI 3 "register_operand" "0")))]
6366 ; this can be generalized...!
6367 "INTVAL (operands[1]) == -2"
6370 int x = INTVAL (operands[1]);
6371 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6372 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6374 [(set_attr "type" "shift")
6375 (set_attr "length" "4")])
6377 (define_expand "ashldi3"
6378 [(set (match_operand:DI 0 "register_operand" "")
6379 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6380 (match_operand:DI 2 "arith32_operand" "")))]
6384 if (GET_CODE (operands[2]) != CONST_INT)
6386 rtx temp = gen_reg_rtx (DImode);
6387 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6388 if (GET_CODE (operands[1]) == CONST_INT)
6389 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6391 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6394 /* Make sure both inputs are not constants,
6395 there are no patterns for that. */
6396 operands[1] = force_reg (DImode, operands[1]);
6400 [(set (match_operand:DI 0 "register_operand" "=r")
6401 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6402 (match_operand:DI 2 "const_int_operand" "n")))]
6404 "depd,z %1,%p2,%Q2,%0"
6405 [(set_attr "type" "shift")
6406 (set_attr "length" "4")])
6408 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6409 ; Doing it like this makes slightly better code since reload can
6410 ; replace a register with a known value in range -16..15 with a
6411 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6412 ; but since we have no more CONST_OK... characters, that is not
6414 (define_insn "zvdep64"
6415 [(set (match_operand:DI 0 "register_operand" "=r,r")
6416 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6417 (minus:DI (const_int 63)
6418 (match_operand:DI 2 "register_operand" "q,q"))))]
6421 depd,z %1,%%sar,64,%0
6422 depdi,z %1,%%sar,64,%0"
6423 [(set_attr "type" "shift,shift")
6424 (set_attr "length" "4,4")])
6426 (define_insn "zvdep_imm64"
6427 [(set (match_operand:DI 0 "register_operand" "=r")
6428 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6429 (minus:DI (const_int 63)
6430 (match_operand:DI 2 "register_operand" "q"))))]
6434 int x = INTVAL (operands[1]);
6435 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6436 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6437 return \"depdi,z %1,%%sar,%2,%0\";
6439 [(set_attr "type" "shift")
6440 (set_attr "length" "4")])
6443 [(set (match_operand:DI 0 "register_operand" "=r")
6444 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6445 (minus:DI (const_int 63)
6446 (match_operand:DI 2 "register_operand" "q")))
6447 (match_operand:DI 3 "register_operand" "0")))]
6448 ; accept ...0001...1, can this be generalized?
6449 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6452 int x = INTVAL (operands[1]);
6453 operands[2] = GEN_INT (exact_log2 (x + 1));
6454 return \"depdi -1,%%sar,%2,%0\";
6456 [(set_attr "type" "shift")
6457 (set_attr "length" "4")])
6460 [(set (match_operand:DI 0 "register_operand" "=r")
6461 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6462 (minus:DI (const_int 63)
6463 (match_operand:DI 2 "register_operand" "q")))
6464 (match_operand:DI 3 "register_operand" "0")))]
6465 ; this can be generalized...!
6466 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6469 int x = INTVAL (operands[1]);
6470 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6471 return \"depdi 0,%%sar,%2,%0\";
6473 [(set_attr "type" "shift")
6474 (set_attr "length" "4")])
6476 (define_expand "ashrsi3"
6477 [(set (match_operand:SI 0 "register_operand" "")
6478 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6479 (match_operand:SI 2 "arith32_operand" "")))]
6483 if (GET_CODE (operands[2]) != CONST_INT)
6485 rtx temp = gen_reg_rtx (SImode);
6486 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6487 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6493 [(set (match_operand:SI 0 "register_operand" "=r")
6494 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6495 (match_operand:SI 2 "const_int_operand" "n")))]
6497 "{extrs|extrw,s} %1,%P2,%L2,%0"
6498 [(set_attr "type" "shift")
6499 (set_attr "length" "4")])
6501 (define_insn "vextrs32"
6502 [(set (match_operand:SI 0 "register_operand" "=r")
6503 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6504 (minus:SI (const_int 31)
6505 (match_operand:SI 2 "register_operand" "q"))))]
6507 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6508 [(set_attr "type" "shift")
6509 (set_attr "length" "4")])
6511 (define_expand "ashrdi3"
6512 [(set (match_operand:DI 0 "register_operand" "")
6513 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6514 (match_operand:DI 2 "arith32_operand" "")))]
6518 if (GET_CODE (operands[2]) != CONST_INT)
6520 rtx temp = gen_reg_rtx (DImode);
6521 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6522 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6528 [(set (match_operand:DI 0 "register_operand" "=r")
6529 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6530 (match_operand:DI 2 "const_int_operand" "n")))]
6532 "extrd,s %1,%p2,%Q2,%0"
6533 [(set_attr "type" "shift")
6534 (set_attr "length" "4")])
6536 (define_insn "vextrs64"
6537 [(set (match_operand:DI 0 "register_operand" "=r")
6538 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6539 (minus:DI (const_int 63)
6540 (match_operand:DI 2 "register_operand" "q"))))]
6542 "extrd,s %1,%%sar,64,%0"
6543 [(set_attr "type" "shift")
6544 (set_attr "length" "4")])
6546 (define_insn "lshrsi3"
6547 [(set (match_operand:SI 0 "register_operand" "=r,r")
6548 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6549 (match_operand:SI 2 "arith32_operand" "q,n")))]
6552 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6553 {extru|extrw,u} %1,%P2,%L2,%0"
6554 [(set_attr "type" "shift")
6555 (set_attr "length" "4")])
6557 (define_insn "lshrdi3"
6558 [(set (match_operand:DI 0 "register_operand" "=r,r")
6559 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6560 (match_operand:DI 2 "arith32_operand" "q,n")))]
6563 shrpd %%r0,%1,%%sar,%0
6564 extrd,u %1,%p2,%Q2,%0"
6565 [(set_attr "type" "shift")
6566 (set_attr "length" "4")])
6568 (define_insn "rotrsi3"
6569 [(set (match_operand:SI 0 "register_operand" "=r,r")
6570 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6571 (match_operand:SI 2 "arith32_operand" "q,n")))]
6575 if (GET_CODE (operands[2]) == CONST_INT)
6577 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6578 return \"{shd|shrpw} %1,%1,%2,%0\";
6581 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6583 [(set_attr "type" "shift")
6584 (set_attr "length" "4")])
6586 (define_expand "rotlsi3"
6587 [(set (match_operand:SI 0 "register_operand" "")
6588 (rotate:SI (match_operand:SI 1 "register_operand" "")
6589 (match_operand:SI 2 "arith32_operand" "")))]
6593 if (GET_CODE (operands[2]) != CONST_INT)
6595 rtx temp = gen_reg_rtx (SImode);
6596 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6597 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6600 /* Else expand normally. */
6604 [(set (match_operand:SI 0 "register_operand" "=r")
6605 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6606 (match_operand:SI 2 "const_int_operand" "n")))]
6610 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6611 return \"{shd|shrpw} %1,%1,%2,%0\";
6613 [(set_attr "type" "shift")
6614 (set_attr "length" "4")])
6617 [(set (match_operand:SI 0 "register_operand" "=r")
6618 (match_operator:SI 5 "plus_xor_ior_operator"
6619 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6620 (match_operand:SI 3 "const_int_operand" "n"))
6621 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6622 (match_operand:SI 4 "const_int_operand" "n"))]))]
6623 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6624 "{shd|shrpw} %1,%2,%4,%0"
6625 [(set_attr "type" "shift")
6626 (set_attr "length" "4")])
6629 [(set (match_operand:SI 0 "register_operand" "=r")
6630 (match_operator:SI 5 "plus_xor_ior_operator"
6631 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6632 (match_operand:SI 4 "const_int_operand" "n"))
6633 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6634 (match_operand:SI 3 "const_int_operand" "n"))]))]
6635 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6636 "{shd|shrpw} %1,%2,%4,%0"
6637 [(set_attr "type" "shift")
6638 (set_attr "length" "4")])
6641 [(set (match_operand:SI 0 "register_operand" "=r")
6642 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6643 (match_operand:SI 2 "const_int_operand" ""))
6644 (match_operand:SI 3 "const_int_operand" "")))]
6645 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
6648 int cnt = INTVAL (operands[2]) & 31;
6649 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6650 operands[2] = GEN_INT (31 - cnt);
6651 return \"{zdep|depw,z} %1,%2,%3,%0\";
6653 [(set_attr "type" "shift")
6654 (set_attr "length" "4")])
6656 ;; Unconditional and other jump instructions.
6658 ;; This can only be used in a leaf function, so we do
6659 ;; not need to use the PIC register when generating PIC code.
6660 (define_insn "return"
6664 "hppa_can_use_return_insn_p ()"
6668 return \"bve%* (%%r2)\";
6669 return \"bv%* %%r0(%%r2)\";
6671 [(set_attr "type" "branch")
6672 (set_attr "length" "4")])
6674 ;; Emit a different pattern for functions which have non-trivial
6675 ;; epilogues so as not to confuse jump and reorg.
6676 (define_insn "return_internal"
6684 return \"bve%* (%%r2)\";
6685 return \"bv%* %%r0(%%r2)\";
6687 [(set_attr "type" "branch")
6688 (set_attr "length" "4")])
6690 ;; This is used for eh returns which bypass the return stub.
6691 (define_insn "return_external_pic"
6693 (clobber (reg:SI 1))
6695 "!TARGET_NO_SPACE_REGS
6697 && flag_pic && current_function_calls_eh_return"
6698 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6699 [(set_attr "type" "branch")
6700 (set_attr "length" "12")])
6702 (define_expand "prologue"
6705 "hppa_expand_prologue ();DONE;")
6707 (define_expand "sibcall_epilogue"
6712 hppa_expand_epilogue ();
6716 (define_expand "epilogue"
6721 /* Try to use the trivial return first. Else use the full
6723 if (hppa_can_use_return_insn_p ())
6724 emit_jump_insn (gen_return ());
6729 hppa_expand_epilogue ();
6731 /* EH returns bypass the normal return stub. Thus, we must do an
6732 interspace branch to return from functions that call eh_return.
6733 This is only a problem for returns from shared code on ports
6734 using space registers. */
6735 if (!TARGET_NO_SPACE_REGS
6737 && flag_pic && current_function_calls_eh_return)
6738 x = gen_return_external_pic ();
6740 x = gen_return_internal ();
6747 ; Used by hppa_profile_hook to load the starting address of the current
6748 ; function; operand 1 contains the address of the label in operand 3
6749 (define_insn "load_offset_label_address"
6750 [(set (match_operand:SI 0 "register_operand" "=r")
6751 (plus:SI (match_operand:SI 1 "register_operand" "r")
6752 (minus:SI (match_operand:SI 2 "" "")
6753 (label_ref:SI (match_operand 3 "" "")))))]
6756 [(set_attr "type" "multi")
6757 (set_attr "length" "4")])
6759 ; Output a code label and load its address.
6760 (define_insn "lcla1"
6761 [(set (match_operand:SI 0 "register_operand" "=r")
6762 (label_ref:SI (match_operand 1 "" "")))
6767 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6768 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6769 CODE_LABEL_NUMBER (operands[1]));
6772 [(set_attr "type" "multi")
6773 (set_attr "length" "8")])
6775 (define_insn "lcla2"
6776 [(set (match_operand:SI 0 "register_operand" "=r")
6777 (label_ref:SI (match_operand 1 "" "")))
6782 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6783 CODE_LABEL_NUMBER (operands[1]));
6786 [(set_attr "type" "move")
6787 (set_attr "length" "4")])
6789 (define_insn "blockage"
6790 [(unspec_volatile [(const_int 2)] 0)]
6793 [(set_attr "length" "0")])
6796 [(set (pc) (label_ref (match_operand 0 "" "")))]
6800 /* An unconditional branch which can reach its target. */
6801 if (get_attr_length (insn) != 24
6802 && get_attr_length (insn) != 16)
6805 return output_lbranch (operands[0], insn);
6807 [(set_attr "type" "uncond_branch")
6808 (set_attr "pa_combine_type" "uncond_branch")
6809 (set (attr "length")
6810 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
6811 (if_then_else (lt (abs (minus (match_dup 0)
6812 (plus (pc) (const_int 8))))
6816 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6818 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6823 ;;; Hope this is only within a function...
6824 (define_insn "indirect_jump"
6825 [(set (pc) (match_operand 0 "register_operand" "r"))]
6826 "GET_MODE (operands[0]) == word_mode"
6828 [(set_attr "type" "branch")
6829 (set_attr "length" "4")])
6831 ;;; This jump is used in branch tables where the insn length is fixed.
6832 ;;; The length of this insn is adjusted if the delay slot is not filled.
6833 (define_insn "short_jump"
6834 [(set (pc) (label_ref (match_operand 0 "" "")))
6838 [(set_attr "type" "btable_branch")
6839 (set_attr "length" "4")])
6841 ;; Subroutines of "casesi".
6842 ;; operand 0 is index
6843 ;; operand 1 is the minimum bound
6844 ;; operand 2 is the maximum bound - minimum bound + 1
6845 ;; operand 3 is CODE_LABEL for the table;
6846 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6848 (define_expand "casesi"
6849 [(match_operand:SI 0 "general_operand" "")
6850 (match_operand:SI 1 "const_int_operand" "")
6851 (match_operand:SI 2 "const_int_operand" "")
6852 (match_operand 3 "" "")
6853 (match_operand 4 "" "")]
6857 if (GET_CODE (operands[0]) != REG)
6858 operands[0] = force_reg (SImode, operands[0]);
6860 if (operands[1] != const0_rtx)
6862 rtx index = gen_reg_rtx (SImode);
6864 operands[1] = GEN_INT (-INTVAL (operands[1]));
6865 if (!INT_14_BITS (operands[1]))
6866 operands[1] = force_reg (SImode, operands[1]);
6867 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
6868 operands[0] = index;
6871 /* In 64bit mode we must make sure to wipe the upper bits of the register
6872 just in case the addition overflowed or we had random bits in the
6873 high part of the register. */
6876 rtx index = gen_reg_rtx (DImode);
6878 emit_insn (gen_extendsidi2 (index, operands[0]));
6879 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
6882 if (!INT_5_BITS (operands[2]))
6883 operands[2] = force_reg (SImode, operands[2]);
6885 /* This branch prevents us finding an insn for the delay slot of the
6886 following vectored branch. It might be possible to use the delay
6887 slot if an index value of -1 was used to transfer to the out-of-range
6888 label. In order to do this, we would have to output the -1 vector
6889 element after the delay insn. The casesi output code would have to
6890 check if the casesi insn is in a delay branch sequence and output
6891 the delay insn if one is found. If this was done, then it might
6892 then be worthwhile to split the casesi patterns to improve scheduling.
6893 However, it's not clear that all this extra complexity is worth
6895 emit_insn (gen_cmpsi (operands[0], operands[2]));
6896 emit_jump_insn (gen_bgtu (operands[4]));
6898 if (TARGET_BIG_SWITCH)
6902 rtx tmp1 = gen_reg_rtx (DImode);
6903 rtx tmp2 = gen_reg_rtx (DImode);
6905 emit_jump_insn (gen_casesi64p (operands[0], operands[3],
6910 rtx tmp1 = gen_reg_rtx (SImode);
6914 rtx tmp2 = gen_reg_rtx (SImode);
6916 emit_jump_insn (gen_casesi32p (operands[0], operands[3],
6920 emit_jump_insn (gen_casesi32 (operands[0], operands[3], tmp1));
6924 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
6928 ;;; The rtl for this pattern doesn't accurately describe what the insn
6929 ;;; actually does, particularly when case-vector elements are exploded
6930 ;;; in pa_reorg. However, the initial SET in these patterns must show
6931 ;;; the connection of the insn to the following jump table.
6932 (define_insn "casesi0"
6933 [(set (pc) (mem:SI (plus:SI
6934 (mult:SI (match_operand:SI 0 "register_operand" "r")
6936 (label_ref (match_operand 1 "" "")))))]
6938 "blr,n %0,%%r0\;nop"
6939 [(set_attr "type" "multi")
6940 (set_attr "length" "8")])
6942 ;;; 32-bit code, absolute branch table.
6943 (define_insn "casesi32"
6944 [(set (pc) (mem:SI (plus:SI
6945 (mult:SI (match_operand:SI 0 "register_operand" "r")
6947 (label_ref (match_operand 1 "" "")))))
6948 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
6949 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6950 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
6951 [(set_attr "type" "multi")
6952 (set_attr "length" "16")])
6954 ;;; 32-bit code, relative branch table.
6955 (define_insn "casesi32p"
6956 [(set (pc) (mem:SI (plus:SI
6957 (mult:SI (match_operand:SI 0 "register_operand" "r")
6959 (label_ref (match_operand 1 "" "")))))
6960 (clobber (match_operand:SI 2 "register_operand" "=&a"))
6961 (clobber (match_operand:SI 3 "register_operand" "=&r"))]
6962 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6963 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
6964 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
6965 [(set_attr "type" "multi")
6966 (set (attr "length")
6967 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
6971 ;;; 64-bit code, 32-bit relative branch table.
6972 (define_insn "casesi64p"
6973 [(set (pc) (mem:DI (plus:DI
6974 (mult:DI (sign_extend:DI
6975 (match_operand:SI 0 "register_operand" "r"))
6977 (label_ref (match_operand 1 "" "")))))
6978 (clobber (match_operand:DI 2 "register_operand" "=&r"))
6979 (clobber (match_operand:DI 3 "register_operand" "=&r"))]
6980 "TARGET_64BIT && TARGET_BIG_SWITCH"
6981 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
6982 add,l %2,%3,%3\;bv,n %%r0(%3)"
6983 [(set_attr "type" "multi")
6984 (set_attr "length" "24")])
6988 ;;- jump to subroutine
6990 (define_expand "call"
6991 [(parallel [(call (match_operand:SI 0 "" "")
6992 (match_operand 1 "" ""))
6993 (clobber (reg:SI 2))])]
6998 rtx nb = operands[1];
7000 if (TARGET_PORTABLE_RUNTIME)
7001 op = force_reg (SImode, XEXP (operands[0], 0));
7003 op = XEXP (operands[0], 0);
7007 if (!virtuals_instantiated)
7008 emit_move_insn (arg_pointer_rtx,
7009 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7013 /* The loop pass can generate new libcalls after the virtual
7014 registers are instantiated when fpregs are disabled because
7015 the only method that we have for doing DImode multiplication
7016 is with a libcall. This could be trouble if we haven't
7017 allocated enough space for the outgoing arguments. */
7018 if (INTVAL (nb) > current_function_outgoing_args_size)
7021 emit_move_insn (arg_pointer_rtx,
7022 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7023 GEN_INT (STACK_POINTER_OFFSET + 64)));
7027 /* Use two different patterns for calls to explicitly named functions
7028 and calls through function pointers. This is necessary as these two
7029 types of calls use different calling conventions, and CSE might try
7030 to change the named call into an indirect call in some cases (using
7031 two patterns keeps CSE from performing this optimization).
7033 We now use even more call patterns as there was a subtle bug in
7034 attempting to restore the pic register after a call using a simple
7035 move insn. During reload, a instruction involving a pseudo register
7036 with no explicit dependence on the PIC register can be converted
7037 to an equivalent load from memory using the PIC register. If we
7038 emit a simple move to restore the PIC register in the initial rtl
7039 generation, then it can potentially be repositioned during scheduling.
7040 and an instruction that eventually uses the PIC register may end up
7041 between the call and the PIC register restore.
7043 This only worked because there is a post call group of instructions
7044 that are scheduled with the call. These instructions are included
7045 in the same basic block as the call. However, calls can throw in
7046 C++ code and a basic block has to terminate at the call if the call
7047 can throw. This results in the PIC register restore being scheduled
7048 independently from the call. So, we now hide the save and restore
7049 of the PIC register in the call pattern until after reload. Then,
7050 we split the moves out. A small side benefit is that we now don't
7051 need to have a use of the PIC register in the return pattern and
7052 the final save/restore operation is not needed.
7054 I elected to just clobber %r4 in the PIC patterns and use it instead
7055 of trying to force hppa_pic_save_rtx () to a callee saved register.
7056 This might have required a new register class and constraint. It
7057 was also simpler to just handle the restore from a register than a
7061 if (GET_CODE (op) == SYMBOL_REF)
7062 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7065 op = force_reg (word_mode, op);
7066 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7071 if (GET_CODE (op) == SYMBOL_REF)
7074 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7076 call_insn = emit_call_insn (gen_call_symref (op, nb));
7080 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7082 emit_move_insn (tmpreg, force_reg (word_mode, op));
7084 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7086 call_insn = emit_call_insn (gen_call_reg (nb));
7093 ;; We use function calls to set the attribute length of calls and millicode
7094 ;; calls. This is necessary because of the large variety of call sequences.
7095 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7096 ;; we need the same calculation in several places, maintenance becomes a
7099 ;; However, this has a subtle impact on branch shortening. When the
7100 ;; expression used to set the length attribute of an instruction depends
7101 ;; on a relative address (e.g., pc or a branch address), genattrtab
7102 ;; notes that the insn's length is variable, and attempts to determine a
7103 ;; worst-case default length and code to compute an insn's current length.
7105 ;; The use of a function call hides the variable dependence of our calls
7106 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7107 ;; as variable and it only generates code for the default case using our
7108 ;; function call. Because of this, calls and millicode calls have a fixed
7109 ;; length in the branch shortening pass, and some branches will use a longer
7110 ;; code sequence than necessary. However, the length of any given call
7111 ;; will still reflect its final code location and it may be shorter than
7112 ;; the initial length estimate.
7114 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7115 ;; in the set. However, when genattrtab hits a function call in its attempt
7116 ;; to compute the default length, it marks the result as unknown and sets
7117 ;; the default result to MAX_INT ;-( One possible fix that would allow
7118 ;; calls to participate in branch shortening would be to make the call to
7119 ;; insn_default_length a target option. Then, we could massage unknown
7120 ;; results. Another fix might be to change genattrtab so that it just does
7121 ;; the call in the variable case as it already does for the fixed case.
7123 (define_insn "call_symref"
7124 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7125 (match_operand 1 "" "i"))
7126 (clobber (reg:SI 1))
7127 (clobber (reg:SI 2))
7128 (use (const_int 0))]
7129 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7132 output_arg_descriptor (insn);
7133 return output_call (insn, operands[0], 0);
7135 [(set_attr "type" "call")
7136 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7138 (define_insn "call_symref_pic"
7139 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7140 (match_operand 1 "" "i"))
7141 (clobber (reg:SI 1))
7142 (clobber (reg:SI 2))
7143 (clobber (reg:SI 4))
7145 (use (const_int 0))]
7146 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7149 output_arg_descriptor (insn);
7150 return output_call (insn, operands[0], 0);
7152 [(set_attr "type" "call")
7153 (set (attr "length")
7154 (plus (symbol_ref "attr_length_call (insn, 0)")
7155 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7157 ;; Split out the PIC register save and restore after reload. This is
7158 ;; done only if the function returns. As the split is done after reload,
7159 ;; there are some situations in which we unnecessarily save and restore
7160 ;; %r4. This happens when there is a single call and the PIC register
7161 ;; is "dead" after the call. This isn't easy to fix as the usage of
7162 ;; the PIC register isn't completely determined until the reload pass.
7164 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7165 (match_operand 1 "" ""))
7166 (clobber (reg:SI 1))
7167 (clobber (reg:SI 2))
7168 (clobber (reg:SI 4))
7170 (use (const_int 0))])]
7171 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7173 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7174 [(set (reg:SI 4) (reg:SI 19))
7175 (parallel [(call (mem:SI (match_dup 0))
7177 (clobber (reg:SI 1))
7178 (clobber (reg:SI 2))
7180 (use (const_int 0))])
7181 (set (reg:SI 19) (reg:SI 4))]
7184 ;; Remove the clobber of register 4 when optimizing. This has to be
7185 ;; done with a peephole optimization rather than a split because the
7186 ;; split sequence for a call must be longer than one instruction.
7188 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7189 (match_operand 1 "" ""))
7190 (clobber (reg:SI 1))
7191 (clobber (reg:SI 2))
7192 (clobber (reg:SI 4))
7194 (use (const_int 0))])]
7195 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7196 [(parallel [(call (mem:SI (match_dup 0))
7198 (clobber (reg:SI 1))
7199 (clobber (reg:SI 2))
7201 (use (const_int 0))])]
7204 (define_insn "*call_symref_pic_post_reload"
7205 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7206 (match_operand 1 "" "i"))
7207 (clobber (reg:SI 1))
7208 (clobber (reg:SI 2))
7210 (use (const_int 0))]
7211 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7214 output_arg_descriptor (insn);
7215 return output_call (insn, operands[0], 0);
7217 [(set_attr "type" "call")
7218 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7220 ;; This pattern is split if it is necessary to save and restore the
7222 (define_insn "call_symref_64bit"
7223 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7224 (match_operand 1 "" "i"))
7225 (clobber (reg:DI 1))
7226 (clobber (reg:DI 2))
7227 (clobber (reg:DI 4))
7230 (use (const_int 0))]
7234 output_arg_descriptor (insn);
7235 return output_call (insn, operands[0], 0);
7237 [(set_attr "type" "call")
7238 (set (attr "length")
7239 (plus (symbol_ref "attr_length_call (insn, 0)")
7240 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7242 ;; Split out the PIC register save and restore after reload. This is
7243 ;; done only if the function returns. As the split is done after reload,
7244 ;; there are some situations in which we unnecessarily save and restore
7245 ;; %r4. This happens when there is a single call and the PIC register
7246 ;; is "dead" after the call. This isn't easy to fix as the usage of
7247 ;; the PIC register isn't completely determined until the reload pass.
7249 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7250 (match_operand 1 "" ""))
7251 (clobber (reg:DI 1))
7252 (clobber (reg:DI 2))
7253 (clobber (reg:DI 4))
7256 (use (const_int 0))])]
7259 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7260 [(set (reg:DI 4) (reg:DI 27))
7261 (parallel [(call (mem:SI (match_dup 0))
7263 (clobber (reg:DI 1))
7264 (clobber (reg:DI 2))
7267 (use (const_int 0))])
7268 (set (reg:DI 27) (reg:DI 4))]
7271 ;; Remove the clobber of register 4 when optimizing. This has to be
7272 ;; done with a peephole optimization rather than a split because the
7273 ;; split sequence for a call must be longer than one instruction.
7275 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7276 (match_operand 1 "" ""))
7277 (clobber (reg:DI 1))
7278 (clobber (reg:DI 2))
7279 (clobber (reg:DI 4))
7282 (use (const_int 0))])]
7283 "TARGET_64BIT && reload_completed"
7284 [(parallel [(call (mem:SI (match_dup 0))
7286 (clobber (reg:DI 1))
7287 (clobber (reg:DI 2))
7290 (use (const_int 0))])]
7293 (define_insn "*call_symref_64bit_post_reload"
7294 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7295 (match_operand 1 "" "i"))
7296 (clobber (reg:DI 1))
7297 (clobber (reg:DI 2))
7300 (use (const_int 0))]
7304 output_arg_descriptor (insn);
7305 return output_call (insn, operands[0], 0);
7307 [(set_attr "type" "call")
7308 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7310 (define_insn "call_reg"
7311 [(call (mem:SI (reg:SI 22))
7312 (match_operand 0 "" "i"))
7313 (clobber (reg:SI 1))
7314 (clobber (reg:SI 2))
7315 (use (const_int 1))]
7319 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7321 [(set_attr "type" "dyncall")
7322 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7324 ;; This pattern is split if it is necessary to save and restore the
7326 (define_insn "call_reg_pic"
7327 [(call (mem:SI (reg:SI 22))
7328 (match_operand 0 "" "i"))
7329 (clobber (reg:SI 1))
7330 (clobber (reg:SI 2))
7331 (clobber (reg:SI 4))
7333 (use (const_int 1))]
7337 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7339 [(set_attr "type" "dyncall")
7340 (set (attr "length")
7341 (plus (symbol_ref "attr_length_indirect_call (insn)")
7342 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7344 ;; Split out the PIC register save and restore after reload. This is
7345 ;; done only if the function returns. As the split is done after reload,
7346 ;; there are some situations in which we unnecessarily save and restore
7347 ;; %r4. This happens when there is a single call and the PIC register
7348 ;; is "dead" after the call. This isn't easy to fix as the usage of
7349 ;; the PIC register isn't completely determined until the reload pass.
7351 [(parallel [(call (mem:SI (reg:SI 22))
7352 (match_operand 0 "" ""))
7353 (clobber (reg:SI 1))
7354 (clobber (reg:SI 2))
7355 (clobber (reg:SI 4))
7357 (use (const_int 1))])]
7360 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7361 [(set (reg:SI 4) (reg:SI 19))
7362 (parallel [(call (mem:SI (reg:SI 22))
7364 (clobber (reg:SI 1))
7365 (clobber (reg:SI 2))
7367 (use (const_int 1))])
7368 (set (reg:SI 19) (reg:SI 4))]
7371 ;; Remove the clobber of register 4 when optimizing. This has to be
7372 ;; done with a peephole optimization rather than a split because the
7373 ;; split sequence for a call must be longer than one instruction.
7375 [(parallel [(call (mem:SI (reg:SI 22))
7376 (match_operand 0 "" ""))
7377 (clobber (reg:SI 1))
7378 (clobber (reg:SI 2))
7379 (clobber (reg:SI 4))
7381 (use (const_int 1))])]
7382 "!TARGET_64BIT && reload_completed"
7383 [(parallel [(call (mem:SI (reg:SI 22))
7385 (clobber (reg:SI 1))
7386 (clobber (reg:SI 2))
7388 (use (const_int 1))])]
7391 (define_insn "*call_reg_pic_post_reload"
7392 [(call (mem:SI (reg:SI 22))
7393 (match_operand 0 "" "i"))
7394 (clobber (reg:SI 1))
7395 (clobber (reg:SI 2))
7397 (use (const_int 1))]
7401 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7403 [(set_attr "type" "dyncall")
7404 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7406 ;; This pattern is split if it is necessary to save and restore the
7408 (define_insn "call_reg_64bit"
7409 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7410 (match_operand 1 "" "i"))
7411 (clobber (reg:DI 2))
7412 (clobber (reg:DI 4))
7415 (use (const_int 1))]
7419 return output_indirect_call (insn, operands[0]);
7421 [(set_attr "type" "dyncall")
7422 (set (attr "length")
7423 (plus (symbol_ref "attr_length_indirect_call (insn)")
7424 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7426 ;; Split out the PIC register save and restore after reload. This is
7427 ;; done only if the function returns. As the split is done after reload,
7428 ;; there are some situations in which we unnecessarily save and restore
7429 ;; %r4. This happens when there is a single call and the PIC register
7430 ;; is "dead" after the call. This isn't easy to fix as the usage of
7431 ;; the PIC register isn't completely determined until the reload pass.
7433 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7434 (match_operand 1 "" ""))
7435 (clobber (reg:DI 2))
7436 (clobber (reg:DI 4))
7439 (use (const_int 1))])]
7442 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7443 [(set (reg:DI 4) (reg:DI 27))
7444 (parallel [(call (mem:SI (match_dup 0))
7446 (clobber (reg:DI 2))
7449 (use (const_int 1))])
7450 (set (reg:DI 27) (reg:DI 4))]
7453 ;; Remove the clobber of register 4 when optimizing. This has to be
7454 ;; done with a peephole optimization rather than a split because the
7455 ;; split sequence for a call must be longer than one instruction.
7457 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7458 (match_operand 1 "" ""))
7459 (clobber (reg:DI 2))
7460 (clobber (reg:DI 4))
7463 (use (const_int 1))])]
7464 "TARGET_64BIT && reload_completed"
7465 [(parallel [(call (mem:SI (match_dup 0))
7467 (clobber (reg:DI 2))
7470 (use (const_int 1))])]
7473 (define_insn "*call_reg_64bit_post_reload"
7474 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7475 (match_operand 1 "" "i"))
7476 (clobber (reg:DI 2))
7479 (use (const_int 1))]
7483 return output_indirect_call (insn, operands[0]);
7485 [(set_attr "type" "dyncall")
7486 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7488 (define_expand "call_value"
7489 [(parallel [(set (match_operand 0 "" "")
7490 (call (match_operand:SI 1 "" "")
7491 (match_operand 2 "" "")))
7492 (clobber (reg:SI 2))])]
7497 rtx dst = operands[0];
7498 rtx nb = operands[2];
7500 if (TARGET_PORTABLE_RUNTIME)
7501 op = force_reg (SImode, XEXP (operands[1], 0));
7503 op = XEXP (operands[1], 0);
7507 if (!virtuals_instantiated)
7508 emit_move_insn (arg_pointer_rtx,
7509 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7513 /* The loop pass can generate new libcalls after the virtual
7514 registers are instantiated when fpregs are disabled because
7515 the only method that we have for doing DImode multiplication
7516 is with a libcall. This could be trouble if we haven't
7517 allocated enough space for the outgoing arguments. */
7518 if (INTVAL (nb) > current_function_outgoing_args_size)
7521 emit_move_insn (arg_pointer_rtx,
7522 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7523 GEN_INT (STACK_POINTER_OFFSET + 64)));
7527 /* Use two different patterns for calls to explicitly named functions
7528 and calls through function pointers. This is necessary as these two
7529 types of calls use different calling conventions, and CSE might try
7530 to change the named call into an indirect call in some cases (using
7531 two patterns keeps CSE from performing this optimization).
7533 We now use even more call patterns as there was a subtle bug in
7534 attempting to restore the pic register after a call using a simple
7535 move insn. During reload, a instruction involving a pseudo register
7536 with no explicit dependence on the PIC register can be converted
7537 to an equivalent load from memory using the PIC register. If we
7538 emit a simple move to restore the PIC register in the initial rtl
7539 generation, then it can potentially be repositioned during scheduling.
7540 and an instruction that eventually uses the PIC register may end up
7541 between the call and the PIC register restore.
7543 This only worked because there is a post call group of instructions
7544 that are scheduled with the call. These instructions are included
7545 in the same basic block as the call. However, calls can throw in
7546 C++ code and a basic block has to terminate at the call if the call
7547 can throw. This results in the PIC register restore being scheduled
7548 independently from the call. So, we now hide the save and restore
7549 of the PIC register in the call pattern until after reload. Then,
7550 we split the moves out. A small side benefit is that we now don't
7551 need to have a use of the PIC register in the return pattern and
7552 the final save/restore operation is not needed.
7554 I elected to just clobber %r4 in the PIC patterns and use it instead
7555 of trying to force hppa_pic_save_rtx () to a callee saved register.
7556 This might have required a new register class and constraint. It
7557 was also simpler to just handle the restore from a register than a
7561 if (GET_CODE (op) == SYMBOL_REF)
7562 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
7565 op = force_reg (word_mode, op);
7566 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
7571 if (GET_CODE (op) == SYMBOL_REF)
7574 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
7576 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
7580 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7582 emit_move_insn (tmpreg, force_reg (word_mode, op));
7584 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
7586 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
7593 (define_insn "call_val_symref"
7594 [(set (match_operand 0 "" "")
7595 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7596 (match_operand 2 "" "i")))
7597 (clobber (reg:SI 1))
7598 (clobber (reg:SI 2))
7599 (use (const_int 0))]
7600 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7603 output_arg_descriptor (insn);
7604 return output_call (insn, operands[1], 0);
7606 [(set_attr "type" "call")
7607 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7609 (define_insn "call_val_symref_pic"
7610 [(set (match_operand 0 "" "")
7611 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7612 (match_operand 2 "" "i")))
7613 (clobber (reg:SI 1))
7614 (clobber (reg:SI 2))
7615 (clobber (reg:SI 4))
7617 (use (const_int 0))]
7618 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7621 output_arg_descriptor (insn);
7622 return output_call (insn, operands[1], 0);
7624 [(set_attr "type" "call")
7625 (set (attr "length")
7626 (plus (symbol_ref "attr_length_call (insn, 0)")
7627 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7629 ;; Split out the PIC register save and restore after reload. This is
7630 ;; done only if the function returns. As the split is done after reload,
7631 ;; there are some situations in which we unnecessarily save and restore
7632 ;; %r4. This happens when there is a single call and the PIC register
7633 ;; is "dead" after the call. This isn't easy to fix as the usage of
7634 ;; the PIC register isn't completely determined until the reload pass.
7636 [(parallel [(set (match_operand 0 "" "")
7637 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7638 (match_operand 2 "" "")))
7639 (clobber (reg:SI 1))
7640 (clobber (reg:SI 2))
7641 (clobber (reg:SI 4))
7643 (use (const_int 0))])]
7644 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7646 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7647 [(set (reg:SI 4) (reg:SI 19))
7648 (parallel [(set (match_dup 0)
7649 (call (mem:SI (match_dup 1))
7651 (clobber (reg:SI 1))
7652 (clobber (reg:SI 2))
7654 (use (const_int 0))])
7655 (set (reg:SI 19) (reg:SI 4))]
7658 ;; Remove the clobber of register 4 when optimizing. This has to be
7659 ;; done with a peephole optimization rather than a split because the
7660 ;; split sequence for a call must be longer than one instruction.
7662 [(parallel [(set (match_operand 0 "" "")
7663 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7664 (match_operand 2 "" "")))
7665 (clobber (reg:SI 1))
7666 (clobber (reg:SI 2))
7667 (clobber (reg:SI 4))
7669 (use (const_int 0))])]
7670 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7671 [(parallel [(set (match_dup 0)
7672 (call (mem:SI (match_dup 1))
7674 (clobber (reg:SI 1))
7675 (clobber (reg:SI 2))
7677 (use (const_int 0))])]
7680 (define_insn "*call_val_symref_pic_post_reload"
7681 [(set (match_operand 0 "" "")
7682 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7683 (match_operand 2 "" "i")))
7684 (clobber (reg:SI 1))
7685 (clobber (reg:SI 2))
7687 (use (const_int 0))]
7688 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7691 output_arg_descriptor (insn);
7692 return output_call (insn, operands[1], 0);
7694 [(set_attr "type" "call")
7695 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7697 ;; This pattern is split if it is necessary to save and restore the
7699 (define_insn "call_val_symref_64bit"
7700 [(set (match_operand 0 "" "")
7701 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7702 (match_operand 2 "" "i")))
7703 (clobber (reg:DI 1))
7704 (clobber (reg:DI 2))
7705 (clobber (reg:DI 4))
7708 (use (const_int 0))]
7712 output_arg_descriptor (insn);
7713 return output_call (insn, operands[1], 0);
7715 [(set_attr "type" "call")
7716 (set (attr "length")
7717 (plus (symbol_ref "attr_length_call (insn, 0)")
7718 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7720 ;; Split out the PIC register save and restore after reload. This is
7721 ;; done only if the function returns. As the split is done after reload,
7722 ;; there are some situations in which we unnecessarily save and restore
7723 ;; %r4. This happens when there is a single call and the PIC register
7724 ;; is "dead" after the call. This isn't easy to fix as the usage of
7725 ;; the PIC register isn't completely determined until the reload pass.
7727 [(parallel [(set (match_operand 0 "" "")
7728 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7729 (match_operand 2 "" "")))
7730 (clobber (reg:DI 1))
7731 (clobber (reg:DI 2))
7732 (clobber (reg:DI 4))
7735 (use (const_int 0))])]
7738 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7739 [(set (reg:DI 4) (reg:DI 27))
7740 (parallel [(set (match_dup 0)
7741 (call (mem:SI (match_dup 1))
7743 (clobber (reg:DI 1))
7744 (clobber (reg:DI 2))
7747 (use (const_int 0))])
7748 (set (reg:DI 27) (reg:DI 4))]
7751 ;; Remove the clobber of register 4 when optimizing. This has to be
7752 ;; done with a peephole optimization rather than a split because the
7753 ;; split sequence for a call must be longer than one instruction.
7755 [(parallel [(set (match_operand 0 "" "")
7756 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7757 (match_operand 2 "" "")))
7758 (clobber (reg:DI 1))
7759 (clobber (reg:DI 2))
7760 (clobber (reg:DI 4))
7763 (use (const_int 0))])]
7764 "TARGET_64BIT && reload_completed"
7765 [(parallel [(set (match_dup 0)
7766 (call (mem:SI (match_dup 1))
7768 (clobber (reg:DI 1))
7769 (clobber (reg:DI 2))
7772 (use (const_int 0))])]
7775 (define_insn "*call_val_symref_64bit_post_reload"
7776 [(set (match_operand 0 "" "")
7777 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7778 (match_operand 2 "" "i")))
7779 (clobber (reg:DI 1))
7780 (clobber (reg:DI 2))
7783 (use (const_int 0))]
7787 output_arg_descriptor (insn);
7788 return output_call (insn, operands[1], 0);
7790 [(set_attr "type" "call")
7791 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7793 (define_insn "call_val_reg"
7794 [(set (match_operand 0 "" "")
7795 (call (mem:SI (reg:SI 22))
7796 (match_operand 1 "" "i")))
7797 (clobber (reg:SI 1))
7798 (clobber (reg:SI 2))
7799 (use (const_int 1))]
7803 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7805 [(set_attr "type" "dyncall")
7806 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7808 ;; This pattern is split if it is necessary to save and restore the
7810 (define_insn "call_val_reg_pic"
7811 [(set (match_operand 0 "" "")
7812 (call (mem:SI (reg:SI 22))
7813 (match_operand 1 "" "i")))
7814 (clobber (reg:SI 1))
7815 (clobber (reg:SI 2))
7816 (clobber (reg:SI 4))
7818 (use (const_int 1))]
7822 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7824 [(set_attr "type" "dyncall")
7825 (set (attr "length")
7826 (plus (symbol_ref "attr_length_indirect_call (insn)")
7827 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7829 ;; Split out the PIC register save and restore after reload. This is
7830 ;; done only if the function returns. As the split is done after reload,
7831 ;; there are some situations in which we unnecessarily save and restore
7832 ;; %r4. This happens when there is a single call and the PIC register
7833 ;; is "dead" after the call. This isn't easy to fix as the usage of
7834 ;; the PIC register isn't completely determined until the reload pass.
7836 [(parallel [(set (match_operand 0 "" "")
7837 (call (mem:SI (reg:SI 22))
7838 (match_operand 1 "" "")))
7839 (clobber (reg:SI 1))
7840 (clobber (reg:SI 2))
7841 (clobber (reg:SI 4))
7843 (use (const_int 1))])]
7846 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7847 [(set (reg:SI 4) (reg:SI 19))
7848 (parallel [(set (match_dup 0)
7849 (call (mem:SI (reg:SI 22))
7851 (clobber (reg:SI 1))
7852 (clobber (reg:SI 2))
7854 (use (const_int 1))])
7855 (set (reg:SI 19) (reg:SI 4))]
7858 ;; Remove the clobber of register 4 when optimizing. This has to be
7859 ;; done with a peephole optimization rather than a split because the
7860 ;; split sequence for a call must be longer than one instruction.
7862 [(parallel [(set (match_operand 0 "" "")
7863 (call (mem:SI (reg:SI 22))
7864 (match_operand 1 "" "")))
7865 (clobber (reg:SI 1))
7866 (clobber (reg:SI 2))
7867 (clobber (reg:SI 4))
7869 (use (const_int 1))])]
7870 "!TARGET_64BIT && reload_completed"
7871 [(parallel [(set (match_dup 0)
7872 (call (mem:SI (reg:SI 22))
7874 (clobber (reg:SI 1))
7875 (clobber (reg:SI 2))
7877 (use (const_int 1))])]
7880 (define_insn "*call_val_reg_pic_post_reload"
7881 [(set (match_operand 0 "" "")
7882 (call (mem:SI (reg:SI 22))
7883 (match_operand 1 "" "i")))
7884 (clobber (reg:SI 1))
7885 (clobber (reg:SI 2))
7887 (use (const_int 1))]
7891 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7893 [(set_attr "type" "dyncall")
7894 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7896 ;; This pattern is split if it is necessary to save and restore the
7898 (define_insn "call_val_reg_64bit"
7899 [(set (match_operand 0 "" "")
7900 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7901 (match_operand 2 "" "i")))
7902 (clobber (reg:DI 2))
7903 (clobber (reg:DI 4))
7906 (use (const_int 1))]
7910 return output_indirect_call (insn, operands[1]);
7912 [(set_attr "type" "dyncall")
7913 (set (attr "length")
7914 (plus (symbol_ref "attr_length_indirect_call (insn)")
7915 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7917 ;; Split out the PIC register save and restore after reload. This is
7918 ;; done only if the function returns. As the split is done after reload,
7919 ;; there are some situations in which we unnecessarily save and restore
7920 ;; %r4. This happens when there is a single call and the PIC register
7921 ;; is "dead" after the call. This isn't easy to fix as the usage of
7922 ;; the PIC register isn't completely determined until the reload pass.
7924 [(parallel [(set (match_operand 0 "" "")
7925 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7926 (match_operand 2 "" "")))
7927 (clobber (reg:DI 2))
7928 (clobber (reg:DI 4))
7931 (use (const_int 1))])]
7934 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7935 [(set (reg:DI 4) (reg:DI 27))
7936 (parallel [(set (match_dup 0)
7937 (call (mem:SI (match_dup 1))
7939 (clobber (reg:DI 2))
7942 (use (const_int 1))])
7943 (set (reg:DI 27) (reg:DI 4))]
7946 ;; Remove the clobber of register 4 when optimizing. This has to be
7947 ;; done with a peephole optimization rather than a split because the
7948 ;; split sequence for a call must be longer than one instruction.
7950 [(parallel [(set (match_operand 0 "" "")
7951 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7952 (match_operand 2 "" "")))
7953 (clobber (reg:DI 2))
7954 (clobber (reg:DI 4))
7957 (use (const_int 1))])]
7958 "TARGET_64BIT && reload_completed"
7959 [(parallel [(set (match_dup 0)
7960 (call (mem:SI (match_dup 1))
7962 (clobber (reg:DI 2))
7965 (use (const_int 1))])]
7968 (define_insn "*call_val_reg_64bit_post_reload"
7969 [(set (match_operand 0 "" "")
7970 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7971 (match_operand 2 "" "i")))
7972 (clobber (reg:DI 2))
7975 (use (const_int 1))]
7979 return output_indirect_call (insn, operands[1]);
7981 [(set_attr "type" "dyncall")
7982 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7984 ;; Call subroutine returning any type.
7986 (define_expand "untyped_call"
7987 [(parallel [(call (match_operand 0 "" "")
7989 (match_operand 1 "" "")
7990 (match_operand 2 "" "")])]
7996 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7998 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8000 rtx set = XVECEXP (operands[2], 0, i);
8001 emit_move_insn (SET_DEST (set), SET_SRC (set));
8004 /* The optimizer does not know that the call sets the function value
8005 registers we stored in the result block. We avoid problems by
8006 claiming that all hard registers are used and clobbered at this
8008 emit_insn (gen_blockage ());
8013 (define_expand "sibcall"
8014 [(call (match_operand:SI 0 "" "")
8015 (match_operand 1 "" ""))]
8016 "!TARGET_PORTABLE_RUNTIME"
8020 rtx nb = operands[1];
8022 op = XEXP (operands[0], 0);
8026 if (!virtuals_instantiated)
8027 emit_move_insn (arg_pointer_rtx,
8028 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8032 /* The loop pass can generate new libcalls after the virtual
8033 registers are instantiated when fpregs are disabled because
8034 the only method that we have for doing DImode multiplication
8035 is with a libcall. This could be trouble if we haven't
8036 allocated enough space for the outgoing arguments. */
8037 if (INTVAL (nb) > current_function_outgoing_args_size)
8040 emit_move_insn (arg_pointer_rtx,
8041 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8042 GEN_INT (STACK_POINTER_OFFSET + 64)));
8046 /* Indirect sibling calls are not allowed. */
8048 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8050 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8052 call_insn = emit_call_insn (call_insn);
8055 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8057 /* We don't have to restore the PIC register. */
8059 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8064 (define_insn "sibcall_internal_symref"
8065 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8066 (match_operand 1 "" "i"))
8067 (clobber (reg:SI 1))
8069 (use (const_int 0))]
8070 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8073 output_arg_descriptor (insn);
8074 return output_call (insn, operands[0], 1);
8076 [(set_attr "type" "call")
8077 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8079 (define_insn "sibcall_internal_symref_64bit"
8080 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8081 (match_operand 1 "" "i"))
8082 (clobber (reg:DI 1))
8084 (use (const_int 0))]
8088 output_arg_descriptor (insn);
8089 return output_call (insn, operands[0], 1);
8091 [(set_attr "type" "call")
8092 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8094 (define_expand "sibcall_value"
8095 [(set (match_operand 0 "" "")
8096 (call (match_operand:SI 1 "" "")
8097 (match_operand 2 "" "")))]
8098 "!TARGET_PORTABLE_RUNTIME"
8102 rtx nb = operands[1];
8104 op = XEXP (operands[1], 0);
8108 if (!virtuals_instantiated)
8109 emit_move_insn (arg_pointer_rtx,
8110 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8114 /* The loop pass can generate new libcalls after the virtual
8115 registers are instantiated when fpregs are disabled because
8116 the only method that we have for doing DImode multiplication
8117 is with a libcall. This could be trouble if we haven't
8118 allocated enough space for the outgoing arguments. */
8119 if (INTVAL (nb) > current_function_outgoing_args_size)
8122 emit_move_insn (arg_pointer_rtx,
8123 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8124 GEN_INT (STACK_POINTER_OFFSET + 64)));
8128 /* Indirect sibling calls are not allowed. */
8131 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8134 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8136 call_insn = emit_call_insn (call_insn);
8139 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8141 /* We don't have to restore the PIC register. */
8143 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8148 (define_insn "sibcall_value_internal_symref"
8149 [(set (match_operand 0 "" "")
8150 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8151 (match_operand 2 "" "i")))
8152 (clobber (reg:SI 1))
8154 (use (const_int 0))]
8155 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8158 output_arg_descriptor (insn);
8159 return output_call (insn, operands[1], 1);
8161 [(set_attr "type" "call")
8162 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8164 (define_insn "sibcall_value_internal_symref_64bit"
8165 [(set (match_operand 0 "" "")
8166 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8167 (match_operand 2 "" "i")))
8168 (clobber (reg:DI 1))
8170 (use (const_int 0))]
8174 output_arg_descriptor (insn);
8175 return output_call (insn, operands[1], 1);
8177 [(set_attr "type" "call")
8178 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8184 [(set_attr "type" "move")
8185 (set_attr "length" "4")])
8187 ;; These are just placeholders so we know where branch tables
8189 (define_insn "begin_brtab"
8194 /* Only GAS actually supports this pseudo-op. */
8196 return \".begin_brtab\";
8200 [(set_attr "type" "move")
8201 (set_attr "length" "0")])
8203 (define_insn "end_brtab"
8208 /* Only GAS actually supports this pseudo-op. */
8210 return \".end_brtab\";
8214 [(set_attr "type" "move")
8215 (set_attr "length" "0")])
8217 ;;; EH does longjmp's from and within the data section. Thus,
8218 ;;; an interspace branch is required for the longjmp implementation.
8219 ;;; Registers r1 and r2 are used as scratch registers for the jump
8221 (define_expand "interspace_jump"
8223 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8224 (clobber (match_dup 1))])]
8228 operands[1] = gen_rtx_REG (word_mode, 2);
8232 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8233 (clobber (reg:SI 2))]
8234 "TARGET_PA_20 && !TARGET_64BIT"
8236 [(set_attr "type" "branch")
8237 (set_attr "length" "4")])
8240 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8241 (clobber (reg:SI 2))]
8242 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8244 [(set_attr "type" "branch")
8245 (set_attr "length" "4")])
8248 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8249 (clobber (reg:SI 2))]
8251 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
8252 [(set_attr "type" "branch")
8253 (set_attr "length" "12")])
8256 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8257 (clobber (reg:DI 2))]
8260 [(set_attr "type" "branch")
8261 (set_attr "length" "4")])
8263 (define_expand "builtin_longjmp"
8264 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
8268 /* The elements of the buffer are, in order: */
8269 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8270 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8271 POINTER_SIZE / BITS_PER_UNIT));
8272 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8273 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8274 rtx pv = gen_rtx_REG (Pmode, 1);
8276 /* This bit is the same as expand_builtin_longjmp. */
8277 emit_move_insn (hard_frame_pointer_rtx, fp);
8278 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8279 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8280 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8282 /* Load the label we are jumping through into r1 so that we know
8283 where to look for it when we get back to setjmp's function for
8284 restoring the gp. */
8285 emit_move_insn (pv, lab);
8287 /* Prevent the insns above from being scheduled into the delay slot
8288 of the interspace jump because the space register could change. */
8289 emit_insn (gen_blockage ());
8291 emit_jump_insn (gen_interspace_jump (pv));
8296 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8297 (define_expand "extzv"
8298 [(set (match_operand 0 "register_operand" "")
8299 (zero_extract (match_operand 1 "register_operand" "")
8300 (match_operand 2 "uint32_operand" "")
8301 (match_operand 3 "uint32_operand" "")))]
8305 HOST_WIDE_INT len = INTVAL (operands[2]);
8306 HOST_WIDE_INT pos = INTVAL (operands[3]);
8308 /* PA extraction insns don't support zero length bitfields or fields
8309 extending beyond the left or right-most bits. Also, we reject lengths
8310 equal to a word as they are better handled by the move patterns. */
8311 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8314 /* From mips.md: extract_bit_field doesn't verify that our source
8315 matches the predicate, so check it again here. */
8316 if (!register_operand (operands[1], VOIDmode))
8320 emit_insn (gen_extzv_64 (operands[0], operands[1],
8321 operands[2], operands[3]));
8323 emit_insn (gen_extzv_32 (operands[0], operands[1],
8324 operands[2], operands[3]));
8328 (define_insn "extzv_32"
8329 [(set (match_operand:SI 0 "register_operand" "=r")
8330 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8331 (match_operand:SI 2 "uint5_operand" "")
8332 (match_operand:SI 3 "uint5_operand" "")))]
8334 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8335 [(set_attr "type" "shift")
8336 (set_attr "length" "4")])
8339 [(set (match_operand:SI 0 "register_operand" "=r")
8340 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8342 (match_operand:SI 2 "register_operand" "q")))]
8344 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8345 [(set_attr "type" "shift")
8346 (set_attr "length" "4")])
8348 (define_insn "extzv_64"
8349 [(set (match_operand:DI 0 "register_operand" "=r")
8350 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8351 (match_operand:DI 2 "uint32_operand" "")
8352 (match_operand:DI 3 "uint32_operand" "")))]
8354 "extrd,u %1,%3+%2-1,%2,%0"
8355 [(set_attr "type" "shift")
8356 (set_attr "length" "4")])
8359 [(set (match_operand:DI 0 "register_operand" "=r")
8360 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8362 (match_operand:DI 2 "register_operand" "q")))]
8364 "extrd,u %1,%%sar,1,%0"
8365 [(set_attr "type" "shift")
8366 (set_attr "length" "4")])
8368 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8369 (define_expand "extv"
8370 [(set (match_operand 0 "register_operand" "")
8371 (sign_extract (match_operand 1 "register_operand" "")
8372 (match_operand 2 "uint32_operand" "")
8373 (match_operand 3 "uint32_operand" "")))]
8377 HOST_WIDE_INT len = INTVAL (operands[2]);
8378 HOST_WIDE_INT pos = INTVAL (operands[3]);
8380 /* PA extraction insns don't support zero length bitfields or fields
8381 extending beyond the left or right-most bits. Also, we reject lengths
8382 equal to a word as they are better handled by the move patterns. */
8383 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8386 /* From mips.md: extract_bit_field doesn't verify that our source
8387 matches the predicate, so check it again here. */
8388 if (!register_operand (operands[1], VOIDmode))
8392 emit_insn (gen_extv_64 (operands[0], operands[1],
8393 operands[2], operands[3]));
8395 emit_insn (gen_extv_32 (operands[0], operands[1],
8396 operands[2], operands[3]));
8400 (define_insn "extv_32"
8401 [(set (match_operand:SI 0 "register_operand" "=r")
8402 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8403 (match_operand:SI 2 "uint5_operand" "")
8404 (match_operand:SI 3 "uint5_operand" "")))]
8406 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8407 [(set_attr "type" "shift")
8408 (set_attr "length" "4")])
8411 [(set (match_operand:SI 0 "register_operand" "=r")
8412 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8414 (match_operand:SI 2 "register_operand" "q")))]
8416 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8417 [(set_attr "type" "shift")
8418 (set_attr "length" "4")])
8420 (define_insn "extv_64"
8421 [(set (match_operand:DI 0 "register_operand" "=r")
8422 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8423 (match_operand:DI 2 "uint32_operand" "")
8424 (match_operand:DI 3 "uint32_operand" "")))]
8426 "extrd,s %1,%3+%2-1,%2,%0"
8427 [(set_attr "type" "shift")
8428 (set_attr "length" "4")])
8431 [(set (match_operand:DI 0 "register_operand" "=r")
8432 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8434 (match_operand:DI 2 "register_operand" "q")))]
8436 "extrd,s %1,%%sar,1,%0"
8437 [(set_attr "type" "shift")
8438 (set_attr "length" "4")])
8440 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8441 (define_expand "insv"
8442 [(set (zero_extract (match_operand 0 "register_operand" "")
8443 (match_operand 1 "uint32_operand" "")
8444 (match_operand 2 "uint32_operand" ""))
8445 (match_operand 3 "arith5_operand" ""))]
8449 HOST_WIDE_INT len = INTVAL (operands[1]);
8450 HOST_WIDE_INT pos = INTVAL (operands[2]);
8452 /* PA insertion insns don't support zero length bitfields or fields
8453 extending beyond the left or right-most bits. Also, we reject lengths
8454 equal to a word as they are better handled by the move patterns. */
8455 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8458 /* From mips.md: insert_bit_field doesn't verify that our destination
8459 matches the predicate, so check it again here. */
8460 if (!register_operand (operands[0], VOIDmode))
8464 emit_insn (gen_insv_64 (operands[0], operands[1],
8465 operands[2], operands[3]));
8467 emit_insn (gen_insv_32 (operands[0], operands[1],
8468 operands[2], operands[3]));
8472 (define_insn "insv_32"
8473 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8474 (match_operand:SI 1 "uint5_operand" "")
8475 (match_operand:SI 2 "uint5_operand" ""))
8476 (match_operand:SI 3 "arith5_operand" "r,L"))]
8479 {dep|depw} %3,%2+%1-1,%1,%0
8480 {depi|depwi} %3,%2+%1-1,%1,%0"
8481 [(set_attr "type" "shift,shift")
8482 (set_attr "length" "4,4")])
8484 ;; Optimize insertion of const_int values of type 1...1xxxx.
8486 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8487 (match_operand:SI 1 "uint5_operand" "")
8488 (match_operand:SI 2 "uint5_operand" ""))
8489 (match_operand:SI 3 "const_int_operand" ""))]
8490 "(INTVAL (operands[3]) & 0x10) != 0 &&
8491 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8494 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8495 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8497 [(set_attr "type" "shift")
8498 (set_attr "length" "4")])
8500 (define_insn "insv_64"
8501 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8502 (match_operand:DI 1 "uint32_operand" "")
8503 (match_operand:DI 2 "uint32_operand" ""))
8504 (match_operand:DI 3 "arith32_operand" "r,L"))]
8507 depd %3,%2+%1-1,%1,%0
8508 depdi %3,%2+%1-1,%1,%0"
8509 [(set_attr "type" "shift,shift")
8510 (set_attr "length" "4,4")])
8512 ;; Optimize insertion of const_int values of type 1...1xxxx.
8514 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8515 (match_operand:DI 1 "uint32_operand" "")
8516 (match_operand:DI 2 "uint32_operand" ""))
8517 (match_operand:DI 3 "const_int_operand" ""))]
8518 "(INTVAL (operands[3]) & 0x10) != 0
8520 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8523 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8524 return \"depdi %3,%2+%1-1,%1,%0\";
8526 [(set_attr "type" "shift")
8527 (set_attr "length" "4")])
8530 [(set (match_operand:DI 0 "register_operand" "=r")
8531 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8534 "depd,z %1,31,32,%0"
8535 [(set_attr "type" "shift")
8536 (set_attr "length" "4")])
8538 ;; This insn is used for some loop tests, typically loops reversed when
8539 ;; strength reduction is used. It is actually created when the instruction
8540 ;; combination phase combines the special loop test. Since this insn
8541 ;; is both a jump insn and has an output, it must deal with its own
8542 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8543 ;; to not choose the register alternatives in the event a reload is needed.
8544 (define_insn "decrement_and_branch_until_zero"
8547 (match_operator 2 "comparison_operator"
8549 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8550 (match_operand:SI 1 "int5_operand" "L,L,L"))
8552 (label_ref (match_operand 3 "" ""))
8555 (plus:SI (match_dup 0) (match_dup 1)))
8556 (clobber (match_scratch:SI 4 "=X,r,r"))]
8558 "* return output_dbra (operands, insn, which_alternative); "
8559 ;; Do not expect to understand this the first time through.
8560 [(set_attr "type" "cbranch,multi,multi")
8561 (set (attr "length")
8562 (if_then_else (eq_attr "alternative" "0")
8563 ;; Loop counter in register case
8564 ;; Short branch has length of 4
8565 ;; Long branch has length of 8
8566 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8571 ;; Loop counter in FP reg case.
8572 ;; Extra goo to deal with additional reload insns.
8573 (if_then_else (eq_attr "alternative" "1")
8574 (if_then_else (lt (match_dup 3) (pc))
8576 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8581 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8585 ;; Loop counter in memory case.
8586 ;; Extra goo to deal with additional reload insns.
8587 (if_then_else (lt (match_dup 3) (pc))
8589 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8594 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8597 (const_int 16))))))])
8602 (match_operator 2 "movb_comparison_operator"
8603 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8604 (label_ref (match_operand 3 "" ""))
8606 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8609 "* return output_movb (operands, insn, which_alternative, 0); "
8610 ;; Do not expect to understand this the first time through.
8611 [(set_attr "type" "cbranch,multi,multi,multi")
8612 (set (attr "length")
8613 (if_then_else (eq_attr "alternative" "0")
8614 ;; Loop counter in register case
8615 ;; Short branch has length of 4
8616 ;; Long branch has length of 8
8617 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8622 ;; Loop counter in FP reg case.
8623 ;; Extra goo to deal with additional reload insns.
8624 (if_then_else (eq_attr "alternative" "1")
8625 (if_then_else (lt (match_dup 3) (pc))
8627 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8632 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8636 ;; Loop counter in memory or sar case.
8637 ;; Extra goo to deal with additional reload insns.
8639 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8642 (const_int 12)))))])
8644 ;; Handle negated branch.
8648 (match_operator 2 "movb_comparison_operator"
8649 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8651 (label_ref (match_operand 3 "" ""))))
8652 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8655 "* return output_movb (operands, insn, which_alternative, 1); "
8656 ;; Do not expect to understand this the first time through.
8657 [(set_attr "type" "cbranch,multi,multi,multi")
8658 (set (attr "length")
8659 (if_then_else (eq_attr "alternative" "0")
8660 ;; Loop counter in register case
8661 ;; Short branch has length of 4
8662 ;; Long branch has length of 8
8663 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8668 ;; Loop counter in FP reg case.
8669 ;; Extra goo to deal with additional reload insns.
8670 (if_then_else (eq_attr "alternative" "1")
8671 (if_then_else (lt (match_dup 3) (pc))
8673 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8678 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8682 ;; Loop counter in memory or SAR case.
8683 ;; Extra goo to deal with additional reload insns.
8685 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8688 (const_int 12)))))])
8691 [(set (pc) (label_ref (match_operand 3 "" "" )))
8692 (set (match_operand:SI 0 "ireg_operand" "=r")
8693 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
8694 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
8695 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
8698 return output_parallel_addb (operands, get_attr_length (insn));
8700 [(set_attr "type" "parallel_branch")
8701 (set (attr "length")
8702 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8708 [(set (pc) (label_ref (match_operand 2 "" "" )))
8709 (set (match_operand:SF 0 "ireg_operand" "=r")
8710 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
8714 return output_parallel_movb (operands, get_attr_length (insn));
8716 [(set_attr "type" "parallel_branch")
8717 (set (attr "length")
8718 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8724 [(set (pc) (label_ref (match_operand 2 "" "" )))
8725 (set (match_operand:SI 0 "ireg_operand" "=r")
8726 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
8730 return output_parallel_movb (operands, get_attr_length (insn));
8732 [(set_attr "type" "parallel_branch")
8733 (set (attr "length")
8734 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8740 [(set (pc) (label_ref (match_operand 2 "" "" )))
8741 (set (match_operand:HI 0 "ireg_operand" "=r")
8742 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
8746 return output_parallel_movb (operands, get_attr_length (insn));
8748 [(set_attr "type" "parallel_branch")
8749 (set (attr "length")
8750 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8756 [(set (pc) (label_ref (match_operand 2 "" "" )))
8757 (set (match_operand:QI 0 "ireg_operand" "=r")
8758 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
8762 return output_parallel_movb (operands, get_attr_length (insn));
8764 [(set_attr "type" "parallel_branch")
8765 (set (attr "length")
8766 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8772 [(set (match_operand 0 "register_operand" "=f")
8773 (mult (match_operand 1 "register_operand" "f")
8774 (match_operand 2 "register_operand" "f")))
8775 (set (match_operand 3 "register_operand" "+f")
8776 (plus (match_operand 4 "register_operand" "f")
8777 (match_operand 5 "register_operand" "f")))]
8778 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8779 && reload_completed && fmpyaddoperands (operands)"
8782 if (GET_MODE (operands[0]) == DFmode)
8784 if (rtx_equal_p (operands[3], operands[5]))
8785 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8787 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8791 if (rtx_equal_p (operands[3], operands[5]))
8792 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8794 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8797 [(set_attr "type" "fpalu")
8798 (set_attr "length" "4")])
8801 [(set (match_operand 3 "register_operand" "+f")
8802 (plus (match_operand 4 "register_operand" "f")
8803 (match_operand 5 "register_operand" "f")))
8804 (set (match_operand 0 "register_operand" "=f")
8805 (mult (match_operand 1 "register_operand" "f")
8806 (match_operand 2 "register_operand" "f")))]
8807 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8808 && reload_completed && fmpyaddoperands (operands)"
8811 if (GET_MODE (operands[0]) == DFmode)
8813 if (rtx_equal_p (operands[3], operands[5]))
8814 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8816 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8820 if (rtx_equal_p (operands[3], operands[5]))
8821 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8823 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8826 [(set_attr "type" "fpalu")
8827 (set_attr "length" "4")])
8830 [(set (match_operand 0 "register_operand" "=f")
8831 (mult (match_operand 1 "register_operand" "f")
8832 (match_operand 2 "register_operand" "f")))
8833 (set (match_operand 3 "register_operand" "+f")
8834 (minus (match_operand 4 "register_operand" "f")
8835 (match_operand 5 "register_operand" "f")))]
8836 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8837 && reload_completed && fmpysuboperands (operands)"
8840 if (GET_MODE (operands[0]) == DFmode)
8841 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8843 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8845 [(set_attr "type" "fpalu")
8846 (set_attr "length" "4")])
8849 [(set (match_operand 3 "register_operand" "+f")
8850 (minus (match_operand 4 "register_operand" "f")
8851 (match_operand 5 "register_operand" "f")))
8852 (set (match_operand 0 "register_operand" "=f")
8853 (mult (match_operand 1 "register_operand" "f")
8854 (match_operand 2 "register_operand" "f")))]
8855 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8856 && reload_completed && fmpysuboperands (operands)"
8859 if (GET_MODE (operands[0]) == DFmode)
8860 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8862 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8864 [(set_attr "type" "fpalu")
8865 (set_attr "length" "4")])
8867 ;; Clean up turds left by reload.
8869 [(set (match_operand 0 "move_dest_operand" "")
8870 (match_operand 1 "register_operand" "fr"))
8871 (set (match_operand 2 "register_operand" "fr")
8874 && GET_CODE (operands[0]) == MEM
8875 && ! MEM_VOLATILE_P (operands[0])
8876 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8877 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8878 && GET_MODE (operands[0]) == DFmode
8879 && GET_CODE (operands[1]) == REG
8880 && GET_CODE (operands[2]) == REG
8881 && ! side_effects_p (XEXP (operands[0], 0))
8882 && REGNO_REG_CLASS (REGNO (operands[1]))
8883 == REGNO_REG_CLASS (REGNO (operands[2]))"
8888 if (FP_REG_P (operands[1]))
8889 output_asm_insn (output_fp_move_double (operands), operands);
8891 output_asm_insn (output_move_double (operands), operands);
8893 if (rtx_equal_p (operands[1], operands[2]))
8896 xoperands[0] = operands[2];
8897 xoperands[1] = operands[1];
8899 if (FP_REG_P (xoperands[1]))
8900 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8902 output_asm_insn (output_move_double (xoperands), xoperands);
8908 [(set (match_operand 0 "register_operand" "fr")
8909 (match_operand 1 "move_src_operand" ""))
8910 (set (match_operand 2 "register_operand" "fr")
8913 && GET_CODE (operands[1]) == MEM
8914 && ! MEM_VOLATILE_P (operands[1])
8915 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8916 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8917 && GET_MODE (operands[0]) == DFmode
8918 && GET_CODE (operands[0]) == REG
8919 && GET_CODE (operands[2]) == REG
8920 && ! side_effects_p (XEXP (operands[1], 0))
8921 && REGNO_REG_CLASS (REGNO (operands[0]))
8922 == REGNO_REG_CLASS (REGNO (operands[2]))"
8927 if (FP_REG_P (operands[0]))
8928 output_asm_insn (output_fp_move_double (operands), operands);
8930 output_asm_insn (output_move_double (operands), operands);
8932 xoperands[0] = operands[2];
8933 xoperands[1] = operands[0];
8935 if (FP_REG_P (xoperands[1]))
8936 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8938 output_asm_insn (output_move_double (xoperands), xoperands);
8943 ;; Flush the I and D cache lines from the start address (operand0)
8944 ;; to the end address (operand1). No lines are flushed if the end
8945 ;; address is less than the start address (unsigned).
8947 ;; Because the range of memory flushed is variable and the size of
8948 ;; a MEM can only be a CONST_INT, the patterns specify that they
8949 ;; perform an unspecified volatile operation on all memory.
8951 ;; The address range for an icache flush must lie within a single
8952 ;; space on targets with non-equivalent space registers.
8954 ;; This is used by the trampoline code for nested functions.
8956 ;; Operand 0 contains the start address.
8957 ;; Operand 1 contains the end address.
8958 ;; Operand 2 contains the line length to use.
8959 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
8960 (define_insn "dcacheflush"
8962 (unspec_volatile [(mem:BLK (scratch))] 0)
8963 (use (match_operand 0 "pmode_register_operand" "r"))
8964 (use (match_operand 1 "pmode_register_operand" "r"))
8965 (use (match_operand 2 "pmode_register_operand" "r"))
8966 (clobber (match_scratch 3 "=&0"))]
8971 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8973 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8975 [(set_attr "type" "multi")
8976 (set_attr "length" "12")])
8978 (define_insn "icacheflush"
8980 (unspec_volatile [(mem:BLK (scratch))] 0)
8981 (use (match_operand 0 "pmode_register_operand" "r"))
8982 (use (match_operand 1 "pmode_register_operand" "r"))
8983 (use (match_operand 2 "pmode_register_operand" "r"))
8984 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
8985 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
8986 (clobber (match_scratch 5 "=&0"))]
8991 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
8993 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
8995 [(set_attr "type" "multi")
8996 (set_attr "length" "52")])
8998 ;; An out-of-line prologue.
8999 (define_insn "outline_prologue_call"
9000 [(unspec_volatile [(const_int 0)] 0)
9001 (clobber (reg:SI 31))
9002 (clobber (reg:SI 22))
9003 (clobber (reg:SI 21))
9004 (clobber (reg:SI 20))
9005 (clobber (reg:SI 19))
9006 (clobber (reg:SI 1))]
9010 extern int frame_pointer_needed;
9012 /* We need two different versions depending on whether or not we
9013 need a frame pointer. Also note that we return to the instruction
9014 immediately after the branch rather than two instructions after the
9015 break as normally is the case. */
9016 if (frame_pointer_needed)
9018 /* Must import the magic millicode routine(s). */
9019 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9021 if (TARGET_PORTABLE_RUNTIME)
9023 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9024 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9028 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9032 /* Must import the magic millicode routine(s). */
9033 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9035 if (TARGET_PORTABLE_RUNTIME)
9037 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9038 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9041 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9045 [(set_attr "type" "multi")
9046 (set_attr "length" "8")])
9048 ;; An out-of-line epilogue.
9049 (define_insn "outline_epilogue_call"
9050 [(unspec_volatile [(const_int 1)] 0)
9053 (clobber (reg:SI 31))
9054 (clobber (reg:SI 22))
9055 (clobber (reg:SI 21))
9056 (clobber (reg:SI 20))
9057 (clobber (reg:SI 19))
9058 (clobber (reg:SI 2))
9059 (clobber (reg:SI 1))]
9063 extern int frame_pointer_needed;
9065 /* We need two different versions depending on whether or not we
9066 need a frame pointer. Also note that we return to the instruction
9067 immediately after the branch rather than two instructions after the
9068 break as normally is the case. */
9069 if (frame_pointer_needed)
9071 /* Must import the magic millicode routine. */
9072 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9074 /* The out-of-line prologue will make sure we return to the right
9076 if (TARGET_PORTABLE_RUNTIME)
9078 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9079 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9083 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9087 /* Must import the magic millicode routine. */
9088 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9090 /* The out-of-line prologue will make sure we return to the right
9092 if (TARGET_PORTABLE_RUNTIME)
9094 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9095 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9098 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9102 [(set_attr "type" "multi")
9103 (set_attr "length" "8")])
9105 ;; Given a function pointer, canonicalize it so it can be
9106 ;; reliably compared to another function pointer. */
9107 (define_expand "canonicalize_funcptr_for_compare"
9108 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9109 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9110 (clobber (match_dup 2))
9111 (clobber (reg:SI 26))
9112 (clobber (reg:SI 22))
9113 (clobber (reg:SI 31))])
9114 (set (match_operand:SI 0 "register_operand" "")
9116 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9121 rtx canonicalize_funcptr_for_compare_libfunc
9122 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9124 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9125 operands[0], LCT_NORMAL, Pmode,
9126 1, operands[1], Pmode);
9130 operands[2] = gen_reg_rtx (SImode);
9131 if (GET_CODE (operands[1]) != REG)
9133 rtx tmp = gen_reg_rtx (Pmode);
9134 emit_move_insn (tmp, operands[1]);
9140 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9141 (clobber (match_operand:SI 0 "register_operand" "=a"))
9142 (clobber (reg:SI 26))
9143 (clobber (reg:SI 22))
9144 (clobber (reg:SI 31))]
9148 int length = get_attr_length (insn);
9151 xoperands[0] = GEN_INT (length - 8);
9152 xoperands[1] = GEN_INT (length - 16);
9154 /* Must import the magic millicode routine. */
9155 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9157 /* This is absolutely amazing.
9159 First, copy our input parameter into %r29 just in case we don't
9160 need to call $$sh_func_adrs. */
9161 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9162 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9164 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9165 we use %r26 unchanged. */
9166 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9167 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9169 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9170 4096, then again we use %r26 unchanged. */
9171 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9173 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9174 return output_millicode_call (insn,
9175 gen_rtx_SYMBOL_REF (SImode,
9176 \"$$sh_func_adrs\"));
9178 [(set_attr "type" "multi")
9179 (set (attr "length")
9180 (plus (symbol_ref "attr_length_millicode_call (insn)")
9183 ;; On the PA, the PIC register is call clobbered, so it must
9184 ;; be saved & restored around calls by the caller. If the call
9185 ;; doesn't return normally (nonlocal goto, or an exception is
9186 ;; thrown), then the code at the exception handler label must
9187 ;; restore the PIC register.
9188 (define_expand "exception_receiver"
9193 /* On the 64-bit port, we need a blockage because there is
9194 confusion regarding the dependence of the restore on the
9195 frame pointer. As a result, the frame pointer and pic
9196 register restores sometimes are interchanged erroneously. */
9198 emit_insn (gen_blockage ());
9199 /* Restore the PIC register using hppa_pic_save_rtx (). The
9200 PIC register is not saved in the frame in 64-bit ABI. */
9201 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9202 emit_insn (gen_blockage ());
9206 (define_expand "builtin_setjmp_receiver"
9207 [(label_ref (match_operand 0 "" ""))]
9212 emit_insn (gen_blockage ());
9213 /* Restore the PIC register. Hopefully, this will always be from
9214 a stack slot. The only registers that are valid after a
9215 builtin_longjmp are the stack and frame pointers. */
9216 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9217 emit_insn (gen_blockage ());
9221 ;; Allocate new stack space and update the saved stack pointer in the
9222 ;; frame marker. The HP C compilers also copy additional words in the
9223 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9224 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9225 ;; currently don't copy these values.
9227 ;; Since the copy of the frame marker can't be done atomically, I
9228 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9229 ;; The HP compilers appear to raise the stack and copy the frame
9230 ;; marker in a strict instruction sequence. This suggests that the
9231 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9232 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9233 ;; as GAS doesn't support it, or try to keep the instructions emitted
9234 ;; here in strict sequence.
9235 (define_expand "allocate_stack"
9236 [(match_operand 0 "" "")
9237 (match_operand 1 "" "")]
9243 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9244 in operand 0 before adjusting the stack. */
9245 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9246 anti_adjust_stack (operands[1]);
9247 if (TARGET_HPUX_UNWIND_LIBRARY)
9249 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9250 GEN_INT (TARGET_64BIT ? -8 : -4));
9251 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9253 if (!TARGET_64BIT && flag_pic)
9255 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9256 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);