1 ;;- Machine description for HP PA-RISC architecture for GNU C compiler
2 ;; Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 ;; Contributed by the Center for Software Science at the University
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;; This gcc Version 2 machine description is inspired by sparc.md and
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;; Insn type. Used to default other attribute values.
30 ;; type "unary" insns have one input operand (1) and one output operand (0)
31 ;; type "binary" insns have two input operands (1,2) and one output (0)
34 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
35 (const_string "binary"))
37 (define_attr "pa_combine_type"
38 "fmpy,faddsub,uncond_branch,addmove,none"
39 (const_string "none"))
41 ;; Processor type (for scheduling, not code generation) -- this attribute
42 ;; must exactly match the processor_type enumeration in pa.h.
44 ;; FIXME: Add 800 scheduling for completeness?
46 (define_attr "cpu" "700,7100,7100LC,7200,8000" (const (symbol_ref "pa_cpu_attr")))
48 ;; Length (in # of bytes).
49 (define_attr "length" ""
50 (cond [(eq_attr "type" "load,fpload")
51 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
52 (const_int 8) (const_int 4))
54 (eq_attr "type" "store,fpstore")
55 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
56 (const_int 8) (const_int 4))
58 (eq_attr "type" "binary,shift,nullshift")
59 (if_then_else (match_operand 2 "arith_operand" "")
60 (const_int 4) (const_int 12))
62 (eq_attr "type" "move,unary,shift,nullshift")
63 (if_then_else (match_operand 1 "arith_operand" "")
64 (const_int 4) (const_int 8))]
68 (define_asm_attributes
69 [(set_attr "length" "4")
70 (set_attr "type" "multi")])
72 ;; Attributes for instruction and branch scheduling
74 ;; For conditional branches.
75 (define_attr "in_branch_delay" "false,true"
76 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
77 (eq_attr "length" "4"))
79 (const_string "false")))
81 ;; Disallow instructions which use the FPU since they will tie up the FPU
82 ;; even if the instruction is nullified.
83 (define_attr "in_nullified_branch_delay" "false,true"
84 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
85 (eq_attr "length" "4"))
87 (const_string "false")))
89 ;; For calls and millicode calls. Allow unconditional branches in the
91 (define_attr "in_call_delay" "false,true"
92 (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
93 (eq_attr "length" "4"))
95 (eq_attr "type" "uncond_branch")
96 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
99 (const_string "false"))]
100 (const_string "false")))
103 ;; Call delay slot description.
104 (define_delay (eq_attr "type" "call")
105 [(eq_attr "in_call_delay" "true") (nil) (nil)])
107 ;; millicode call delay slot description. Note it disallows delay slot
108 ;; when TARGET_PORTABLE_RUNTIME is true.
109 (define_delay (eq_attr "type" "milli")
110 [(and (eq_attr "in_call_delay" "true")
111 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0)))
114 ;; Return and other similar instructions.
115 (define_delay (eq_attr "type" "branch,parallel_branch")
116 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
118 ;; Floating point conditional branch delay slot description and
119 (define_delay (eq_attr "type" "fbranch")
120 [(eq_attr "in_branch_delay" "true")
121 (eq_attr "in_nullified_branch_delay" "true")
124 ;; Integer conditional branch delay slot description.
125 ;; Nullification of conditional branches on the PA is dependent on the
126 ;; direction of the branch. Forward branches nullify true and
127 ;; backward branches nullify false. If the direction is unknown
128 ;; then nullification is not allowed.
129 (define_delay (eq_attr "type" "cbranch")
130 [(eq_attr "in_branch_delay" "true")
131 (and (eq_attr "in_nullified_branch_delay" "true")
132 (attr_flag "forward"))
133 (and (eq_attr "in_nullified_branch_delay" "true")
134 (attr_flag "backward"))])
136 (define_delay (and (eq_attr "type" "uncond_branch")
137 (eq (symbol_ref "following_call (insn)")
139 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
141 ;; Function units of the HPPA. The following data is for the 700 CPUs
142 ;; (Mustang CPU + Timex FPU aka PA-89) because that's what I have the docs for.
143 ;; Scheduling instructions for PA-83 machines according to the Snake
144 ;; constraints shouldn't hurt.
146 ;; (define_function_unit {name} {num-units} {n-users} {test}
147 ;; {ready-delay} {issue-delay} [{conflict-list}])
150 ;; (Noted only for documentation; units that take one cycle do not need to
153 ;; (define_function_unit "alu" 1 0
154 ;; (and (eq_attr "type" "unary,shift,nullshift,binary,move,address")
155 ;; (eq_attr "cpu" "700"))
159 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
160 ;; load: 2, fpload: 3
161 ;; store, fpstore: 3, no D-cache operations should be scheduled.
163 (define_function_unit "pa700memory" 1 0
164 (and (eq_attr "type" "load,fpload")
165 (eq_attr "cpu" "700")) 2 0)
166 (define_function_unit "pa700memory" 1 0
167 (and (eq_attr "type" "store,fpstore")
168 (eq_attr "cpu" "700")) 3 3)
170 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
172 ;; Instruction Time Unit Minimum Distance (unit contention)
179 ;; fmpyadd 3 ALU,MPY 2
180 ;; fmpysub 3 ALU,MPY 2
181 ;; fmpycfxt 3 ALU,MPY 2
184 ;; fdiv,sgl 10 MPY 10
185 ;; fdiv,dbl 12 MPY 12
186 ;; fsqrt,sgl 14 MPY 14
187 ;; fsqrt,dbl 18 MPY 18
189 (define_function_unit "pa700fp_alu" 1 0
190 (and (eq_attr "type" "fpcc")
191 (eq_attr "cpu" "700")) 4 2)
192 (define_function_unit "pa700fp_alu" 1 0
193 (and (eq_attr "type" "fpalu")
194 (eq_attr "cpu" "700")) 3 2)
195 (define_function_unit "pa700fp_mpy" 1 0
196 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
197 (eq_attr "cpu" "700")) 3 2)
198 (define_function_unit "pa700fp_mpy" 1 0
199 (and (eq_attr "type" "fpdivsgl")
200 (eq_attr "cpu" "700")) 10 10)
201 (define_function_unit "pa700fp_mpy" 1 0
202 (and (eq_attr "type" "fpdivdbl")
203 (eq_attr "cpu" "700")) 12 12)
204 (define_function_unit "pa700fp_mpy" 1 0
205 (and (eq_attr "type" "fpsqrtsgl")
206 (eq_attr "cpu" "700")) 14 14)
207 (define_function_unit "pa700fp_mpy" 1 0
208 (and (eq_attr "type" "fpsqrtdbl")
209 (eq_attr "cpu" "700")) 18 18)
211 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
212 ;; floating point computations with non-floating point computations (fp loads
213 ;; and stores are not fp computations).
216 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
217 ;; take two cycles, during which no Dcache operations should be scheduled.
218 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
219 ;; all have the same memory characteristics if one disregards cache misses.
220 (define_function_unit "pa7100memory" 1 0
221 (and (eq_attr "type" "load,fpload")
222 (eq_attr "cpu" "7100,7100LC")) 2 0)
223 (define_function_unit "pa7100memory" 1 0
224 (and (eq_attr "type" "store,fpstore")
225 (eq_attr "cpu" "7100,7100LC")) 2 2)
227 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
229 ;; Instruction Time Unit Minimum Distance (unit contention)
236 ;; fmpyadd 2 ALU,MPY 1
237 ;; fmpysub 2 ALU,MPY 1
238 ;; fmpycfxt 2 ALU,MPY 1
242 ;; fdiv,dbl 15 DIV 15
244 ;; fsqrt,dbl 15 DIV 15
246 (define_function_unit "pa7100fp_alu" 1 0
247 (and (eq_attr "type" "fpcc,fpalu")
248 (eq_attr "cpu" "7100")) 2 1)
249 (define_function_unit "pa7100fp_mpy" 1 0
250 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
251 (eq_attr "cpu" "7100")) 2 1)
252 (define_function_unit "pa7100fp_div" 1 0
253 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
254 (eq_attr "cpu" "7100")) 8 8)
255 (define_function_unit "pa7100fp_div" 1 0
256 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
257 (eq_attr "cpu" "7100")) 15 15)
259 ;; To encourage dual issue we define function units corresponding to
260 ;; the instructions which can be dual issued. This is a rather crude
261 ;; approximation, the "pa7100nonflop" test in particular could be refined.
262 (define_function_unit "pa7100flop" 1 1
264 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
265 (eq_attr "cpu" "7100")) 1 1)
267 (define_function_unit "pa7100nonflop" 1 1
269 (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
270 (eq_attr "cpu" "7100")) 1 1)
273 ;; Memory subsystem works just like 7100/7150 (except for cache miss times which
274 ;; we don't model here).
276 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
277 ;; Note divides and sqrt flops lock the cpu until the flop is
278 ;; finished. fmpy and xmpyu (fmpyi) lock the cpu for one cycle.
279 ;; There's no way to avoid the penalty.
281 ;; Instruction Time Unit Minimum Distance (unit contention)
288 ;; fmpyadd,sgl 2 ALU,MPY 1
289 ;; fmpyadd,dbl 3 ALU,MPY 2
290 ;; fmpysub,sgl 2 ALU,MPY 1
291 ;; fmpysub,dbl 3 ALU,MPY 2
292 ;; fmpycfxt,sgl 2 ALU,MPY 1
293 ;; fmpycfxt,dbl 3 ALU,MPY 2
298 ;; fdiv,dbl 15 DIV 15
300 ;; fsqrt,dbl 15 DIV 15
302 (define_function_unit "pa7100LCfp_alu" 1 0
303 (and (eq_attr "type" "fpcc,fpalu")
304 (eq_attr "cpu" "7100LC,7200")) 2 1)
305 (define_function_unit "pa7100LCfp_mpy" 1 0
306 (and (eq_attr "type" "fpmulsgl")
307 (eq_attr "cpu" "7100LC,7200")) 2 1)
308 (define_function_unit "pa7100LCfp_mpy" 1 0
309 (and (eq_attr "type" "fpmuldbl")
310 (eq_attr "cpu" "7100LC,7200")) 3 2)
311 (define_function_unit "pa7100LCfp_div" 1 0
312 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
313 (eq_attr "cpu" "7100LC,7200")) 8 8)
314 (define_function_unit "pa7100LCfp_div" 1 0
315 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
316 (eq_attr "cpu" "7100LC,7200")) 15 15)
318 ;; Define the various functional units for dual-issue.
320 ;; There's only one floating point unit.
321 (define_function_unit "pa7100LCflop" 1 1
323 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
324 (eq_attr "cpu" "7100LC,7200")) 1 1)
326 ;; Shifts and memory ops execute in only one of the integer ALUs
327 (define_function_unit "pa7100LCshiftmem" 1 1
329 (eq_attr "type" "shift,nullshift,load,fpload,store,fpstore")
330 (eq_attr "cpu" "7100LC,7200")) 1 1)
332 ;; We have two basic ALUs.
333 (define_function_unit "pa7100LCalu" 2 1
335 (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
336 (eq_attr "cpu" "7100LC,7200")) 1 1)
338 ;; I don't have complete information on the PA7200; however, most of
339 ;; what I've heard makes it look like a 7100LC without the store-store
340 ;; penalty. So that's how we'll model it.
342 ;; Memory. Disregarding Cache misses, memory loads and stores take
343 ;; two cycles. Any special cases are handled in pa_adjust_cost.
344 (define_function_unit "pa7200memory" 1 0
345 (and (eq_attr "type" "load,fpload,store,fpstore")
346 (eq_attr "cpu" "7200")) 2 0)
348 ;; I don't have detailed information on the PA7200 FP pipeline, so I
349 ;; treat it just like the 7100LC pipeline.
350 ;; Similarly for the multi-issue fake units.
353 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
354 ;; traditional architecture.
356 ;; The PA8000 has a large (56) entry reorder buffer that is split between
357 ;; memory and non-memory operations.
359 ;; The PA800 can issue two memory and two non-memory operations per cycle to
360 ;; the function units. Similarly, the PA8000 can retire two memory and two
361 ;; non-memory operations per cycle.
363 ;; Given the large reorder buffer, the processor can hide most latencies.
364 ;; According to HP, they've got the best results by scheduling for retirement
365 ;; bandwidth with limited latency scheduling for floating point operations.
366 ;; Latency for integer operations and memory references is ignored.
368 ;; We claim floating point operations have a 2 cycle latency and are
369 ;; fully pipelined, except for div and sqrt which are not pipelined.
371 ;; It is not necessary to define the shifter and integer alu units.
373 ;; These first two define_unit_unit descriptions model retirement from
374 ;; the reorder buffer.
375 (define_function_unit "pa8000lsu" 2 1
377 (eq_attr "type" "load,fpload,store,fpstore")
378 (eq_attr "cpu" "8000")) 1 1)
380 (define_function_unit "pa8000alu" 2 1
382 (eq_attr "type" "!load,fpload,store,fpstore")
383 (eq_attr "cpu" "8000")) 1 1)
385 ;; Claim floating point ops have a 2 cycle latency, excluding div and
386 ;; sqrt, which are not pipelined and issue to different units.
387 (define_function_unit "pa8000fmac" 2 0
389 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
390 (eq_attr "cpu" "8000")) 2 1)
392 (define_function_unit "pa8000fdiv" 2 1
394 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
395 (eq_attr "cpu" "8000")) 17 17)
397 (define_function_unit "pa8000fdiv" 2 1
399 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
400 (eq_attr "cpu" "8000")) 31 31)
403 ;; Compare instructions.
404 ;; This controls RTL generation and register allocation.
406 ;; We generate RTL for comparisons and branches by having the cmpxx
407 ;; patterns store away the operands. Then, the scc and bcc patterns
408 ;; emit RTL for both the compare and the branch.
411 (define_expand "cmpsi"
413 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
414 (match_operand:SI 1 "arith5_operand" "")))]
418 hppa_compare_op0 = operands[0];
419 hppa_compare_op1 = operands[1];
420 hppa_branch_type = CMP_SI;
424 (define_expand "cmpsf"
426 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
427 (match_operand:SF 1 "reg_or_0_operand" "")))]
428 "! TARGET_SOFT_FLOAT"
431 hppa_compare_op0 = operands[0];
432 hppa_compare_op1 = operands[1];
433 hppa_branch_type = CMP_SF;
437 (define_expand "cmpdf"
439 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
440 (match_operand:DF 1 "reg_or_0_operand" "")))]
441 "! TARGET_SOFT_FLOAT"
444 hppa_compare_op0 = operands[0];
445 hppa_compare_op1 = operands[1];
446 hppa_branch_type = CMP_DF;
452 (match_operator:CCFP 2 "comparison_operator"
453 [(match_operand:SF 0 "reg_or_0_operand" "fG")
454 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
455 "! TARGET_SOFT_FLOAT"
456 "fcmp,sgl,%Y2 %f0,%f1"
457 [(set_attr "length" "4")
458 (set_attr "type" "fpcc")])
462 (match_operator:CCFP 2 "comparison_operator"
463 [(match_operand:DF 0 "reg_or_0_operand" "fG")
464 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
465 "! TARGET_SOFT_FLOAT"
466 "fcmp,dbl,%Y2 %f0,%f1"
467 [(set_attr "length" "4")
468 (set_attr "type" "fpcc")])
473 [(set (match_operand:SI 0 "register_operand" "")
479 /* fp scc patterns rarely match, and are not a win on the PA. */
480 if (hppa_branch_type != CMP_SI)
482 /* set up operands from compare. */
483 operands[1] = hppa_compare_op0;
484 operands[2] = hppa_compare_op1;
485 /* fall through and generate default code */
489 [(set (match_operand:SI 0 "register_operand" "")
495 /* fp scc patterns rarely match, and are not a win on the PA. */
496 if (hppa_branch_type != CMP_SI)
498 operands[1] = hppa_compare_op0;
499 operands[2] = hppa_compare_op1;
503 [(set (match_operand:SI 0 "register_operand" "")
509 /* fp scc patterns rarely match, and are not a win on the PA. */
510 if (hppa_branch_type != CMP_SI)
512 operands[1] = hppa_compare_op0;
513 operands[2] = hppa_compare_op1;
517 [(set (match_operand:SI 0 "register_operand" "")
523 /* fp scc patterns rarely match, and are not a win on the PA. */
524 if (hppa_branch_type != CMP_SI)
526 operands[1] = hppa_compare_op0;
527 operands[2] = hppa_compare_op1;
531 [(set (match_operand:SI 0 "register_operand" "")
537 /* fp scc patterns rarely match, and are not a win on the PA. */
538 if (hppa_branch_type != CMP_SI)
540 operands[1] = hppa_compare_op0;
541 operands[2] = hppa_compare_op1;
545 [(set (match_operand:SI 0 "register_operand" "")
551 /* fp scc patterns rarely match, and are not a win on the PA. */
552 if (hppa_branch_type != CMP_SI)
554 operands[1] = hppa_compare_op0;
555 operands[2] = hppa_compare_op1;
558 (define_expand "sltu"
559 [(set (match_operand:SI 0 "register_operand" "")
560 (ltu:SI (match_dup 1)
565 if (hppa_branch_type != CMP_SI)
567 operands[1] = hppa_compare_op0;
568 operands[2] = hppa_compare_op1;
571 (define_expand "sgtu"
572 [(set (match_operand:SI 0 "register_operand" "")
573 (gtu:SI (match_dup 1)
578 if (hppa_branch_type != CMP_SI)
580 operands[1] = hppa_compare_op0;
581 operands[2] = hppa_compare_op1;
584 (define_expand "sleu"
585 [(set (match_operand:SI 0 "register_operand" "")
586 (leu:SI (match_dup 1)
591 if (hppa_branch_type != CMP_SI)
593 operands[1] = hppa_compare_op0;
594 operands[2] = hppa_compare_op1;
597 (define_expand "sgeu"
598 [(set (match_operand:SI 0 "register_operand" "")
599 (geu:SI (match_dup 1)
604 if (hppa_branch_type != CMP_SI)
606 operands[1] = hppa_compare_op0;
607 operands[2] = hppa_compare_op1;
610 ;; Instruction canonicalization puts immediate operands second, which
611 ;; is the reverse of what we want.
614 [(set (match_operand:SI 0 "register_operand" "=r")
615 (match_operator:SI 3 "comparison_operator"
616 [(match_operand:SI 1 "register_operand" "r")
617 (match_operand:SI 2 "arith11_operand" "rI")]))]
619 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
620 [(set_attr "type" "binary")
621 (set_attr "length" "8")])
623 (define_insn "iorscc"
624 [(set (match_operand:SI 0 "register_operand" "=r")
625 (ior:SI (match_operator:SI 3 "comparison_operator"
626 [(match_operand:SI 1 "register_operand" "r")
627 (match_operand:SI 2 "arith11_operand" "rI")])
628 (match_operator:SI 6 "comparison_operator"
629 [(match_operand:SI 4 "register_operand" "r")
630 (match_operand:SI 5 "arith11_operand" "rI")])))]
632 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
633 [(set_attr "type" "binary")
634 (set_attr "length" "12")])
636 ;; Combiner patterns for common operations performed with the output
637 ;; from an scc insn (negscc and incscc).
638 (define_insn "negscc"
639 [(set (match_operand:SI 0 "register_operand" "=r")
640 (neg:SI (match_operator:SI 3 "comparison_operator"
641 [(match_operand:SI 1 "register_operand" "r")
642 (match_operand:SI 2 "arith11_operand" "rI")])))]
644 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
645 [(set_attr "type" "binary")
646 (set_attr "length" "8")])
648 ;; Patterns for adding/subtracting the result of a boolean expression from
649 ;; a register. First we have special patterns that make use of the carry
650 ;; bit, and output only two instructions. For the cases we can't in
651 ;; general do in two instructions, the incscc pattern at the end outputs
652 ;; two or three instructions.
655 [(set (match_operand:SI 0 "register_operand" "=r")
656 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
657 (match_operand:SI 3 "arith11_operand" "rI"))
658 (match_operand:SI 1 "register_operand" "r")))]
660 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
661 [(set_attr "type" "binary")
662 (set_attr "length" "8")])
664 ; This need only accept registers for op3, since canonicalization
665 ; replaces geu with gtu when op3 is an integer.
667 [(set (match_operand:SI 0 "register_operand" "=r")
668 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
669 (match_operand:SI 3 "register_operand" "r"))
670 (match_operand:SI 1 "register_operand" "r")))]
672 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
673 [(set_attr "type" "binary")
674 (set_attr "length" "8")])
676 ; Match only integers for op3 here. This is used as canonical form of the
677 ; geu pattern when op3 is an integer. Don't match registers since we can't
678 ; make better code than the general incscc pattern.
680 [(set (match_operand:SI 0 "register_operand" "=r")
681 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
682 (match_operand:SI 3 "int11_operand" "I"))
683 (match_operand:SI 1 "register_operand" "r")))]
685 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
686 [(set_attr "type" "binary")
687 (set_attr "length" "8")])
689 (define_insn "incscc"
690 [(set (match_operand:SI 0 "register_operand" "=r,r")
691 (plus:SI (match_operator:SI 4 "comparison_operator"
692 [(match_operand:SI 2 "register_operand" "r,r")
693 (match_operand:SI 3 "arith11_operand" "rI,rI")])
694 (match_operand:SI 1 "register_operand" "0,?r")))]
697 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
698 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
699 [(set_attr "type" "binary,binary")
700 (set_attr "length" "8,12")])
703 [(set (match_operand:SI 0 "register_operand" "=r")
704 (minus:SI (match_operand:SI 1 "register_operand" "r")
705 (gtu:SI (match_operand:SI 2 "register_operand" "r")
706 (match_operand:SI 3 "arith11_operand" "rI"))))]
708 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
709 [(set_attr "type" "binary")
710 (set_attr "length" "8")])
713 [(set (match_operand:SI 0 "register_operand" "=r")
714 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
715 (gtu:SI (match_operand:SI 2 "register_operand" "r")
716 (match_operand:SI 3 "arith11_operand" "rI")))
717 (match_operand:SI 4 "register_operand" "r")))]
719 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
720 [(set_attr "type" "binary")
721 (set_attr "length" "8")])
723 ; This need only accept registers for op3, since canonicalization
724 ; replaces ltu with leu when op3 is an integer.
726 [(set (match_operand:SI 0 "register_operand" "=r")
727 (minus:SI (match_operand:SI 1 "register_operand" "r")
728 (ltu:SI (match_operand:SI 2 "register_operand" "r")
729 (match_operand:SI 3 "register_operand" "r"))))]
731 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
732 [(set_attr "type" "binary")
733 (set_attr "length" "8")])
736 [(set (match_operand:SI 0 "register_operand" "=r")
737 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
738 (ltu:SI (match_operand:SI 2 "register_operand" "r")
739 (match_operand:SI 3 "register_operand" "r")))
740 (match_operand:SI 4 "register_operand" "r")))]
742 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
743 [(set_attr "type" "binary")
744 (set_attr "length" "8")])
746 ; Match only integers for op3 here. This is used as canonical form of the
747 ; ltu pattern when op3 is an integer. Don't match registers since we can't
748 ; make better code than the general incscc pattern.
750 [(set (match_operand:SI 0 "register_operand" "=r")
751 (minus:SI (match_operand:SI 1 "register_operand" "r")
752 (leu:SI (match_operand:SI 2 "register_operand" "r")
753 (match_operand:SI 3 "int11_operand" "I"))))]
755 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
756 [(set_attr "type" "binary")
757 (set_attr "length" "8")])
760 [(set (match_operand:SI 0 "register_operand" "=r")
761 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
762 (leu:SI (match_operand:SI 2 "register_operand" "r")
763 (match_operand:SI 3 "int11_operand" "I")))
764 (match_operand:SI 4 "register_operand" "r")))]
766 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
767 [(set_attr "type" "binary")
768 (set_attr "length" "8")])
770 (define_insn "decscc"
771 [(set (match_operand:SI 0 "register_operand" "=r,r")
772 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
773 (match_operator:SI 4 "comparison_operator"
774 [(match_operand:SI 2 "register_operand" "r,r")
775 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
778 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
779 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
780 [(set_attr "type" "binary,binary")
781 (set_attr "length" "8,12")])
783 ; Patterns for max and min. (There is no need for an earlyclobber in the
784 ; last alternative since the middle alternative will match if op0 == op1.)
786 (define_insn "sminsi3"
787 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
788 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
789 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
792 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
793 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
794 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
795 [(set_attr "type" "multi,multi,multi")
796 (set_attr "length" "8,8,8")])
798 (define_insn "uminsi3"
799 [(set (match_operand:SI 0 "register_operand" "=r,r")
800 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
801 (match_operand:SI 2 "arith11_operand" "r,I")))]
804 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
805 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
806 [(set_attr "type" "multi,multi")
807 (set_attr "length" "8,8")])
809 (define_insn "smaxsi3"
810 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
811 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
812 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
815 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
816 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
817 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
818 [(set_attr "type" "multi,multi,multi")
819 (set_attr "length" "8,8,8")])
821 (define_insn "umaxsi3"
822 [(set (match_operand:SI 0 "register_operand" "=r,r")
823 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
824 (match_operand:SI 2 "arith11_operand" "r,I")))]
827 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
828 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
829 [(set_attr "type" "multi,multi")
830 (set_attr "length" "8,8")])
832 (define_insn "abssi2"
833 [(set (match_operand:SI 0 "register_operand" "=r")
834 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
836 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
837 [(set_attr "type" "multi")
838 (set_attr "length" "8")])
840 ;;; Experimental conditional move patterns
842 (define_expand "movsicc"
843 [(set (match_operand:SI 0 "register_operand" "")
845 (match_operator 1 "comparison_operator"
848 (match_operand:SI 2 "reg_or_cint_move_operand" "")
849 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
853 enum rtx_code code = GET_CODE (operands[1]);
855 if (hppa_branch_type != CMP_SI)
858 /* operands[1] is currently the result of compare_from_rtx. We want to
859 emit a compare of the original operands. */
860 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
861 operands[4] = hppa_compare_op0;
862 operands[5] = hppa_compare_op1;
865 ; We need the first constraint alternative in order to avoid
866 ; earlyclobbers on all other alternatives.
868 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
870 (match_operator 5 "comparison_operator"
871 [(match_operand:SI 3 "register_operand" "r,r,r,r,r")
872 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
873 (match_operand:SI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
877 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi 0,%0
878 {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;copy %1,%0
879 {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;ldi %1,%0
880 {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;ldil L'%1,%0
881 {com%I4clr|cmp%I4clr},%B5 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
882 [(set_attr "type" "multi,multi,multi,multi,nullshift")
883 (set_attr "length" "8,8,8,8,8")])
886 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
888 (match_operator 5 "comparison_operator"
889 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
890 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
891 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
892 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
895 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
896 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
897 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
898 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
899 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
900 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
901 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
902 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
903 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
904 (set_attr "length" "8,8,8,8,8,8,8,8")])
906 ;; Conditional Branches
910 (if_then_else (eq (match_dup 1) (match_dup 2))
911 (label_ref (match_operand 0 "" ""))
916 if (hppa_branch_type != CMP_SI)
918 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
919 emit_bcond_fp (NE, operands[0]);
922 /* set up operands from compare. */
923 operands[1] = hppa_compare_op0;
924 operands[2] = hppa_compare_op1;
925 /* fall through and generate default code */
930 (if_then_else (ne (match_dup 1) (match_dup 2))
931 (label_ref (match_operand 0 "" ""))
936 if (hppa_branch_type != CMP_SI)
938 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
939 emit_bcond_fp (NE, operands[0]);
942 operands[1] = hppa_compare_op0;
943 operands[2] = hppa_compare_op1;
948 (if_then_else (gt (match_dup 1) (match_dup 2))
949 (label_ref (match_operand 0 "" ""))
954 if (hppa_branch_type != CMP_SI)
956 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
957 emit_bcond_fp (NE, operands[0]);
960 operands[1] = hppa_compare_op0;
961 operands[2] = hppa_compare_op1;
966 (if_then_else (lt (match_dup 1) (match_dup 2))
967 (label_ref (match_operand 0 "" ""))
972 if (hppa_branch_type != CMP_SI)
974 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
975 emit_bcond_fp (NE, operands[0]);
978 operands[1] = hppa_compare_op0;
979 operands[2] = hppa_compare_op1;
984 (if_then_else (ge (match_dup 1) (match_dup 2))
985 (label_ref (match_operand 0 "" ""))
990 if (hppa_branch_type != CMP_SI)
992 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
993 emit_bcond_fp (NE, operands[0]);
996 operands[1] = hppa_compare_op0;
997 operands[2] = hppa_compare_op1;
1000 (define_expand "ble"
1002 (if_then_else (le (match_dup 1) (match_dup 2))
1003 (label_ref (match_operand 0 "" ""))
1008 if (hppa_branch_type != CMP_SI)
1010 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1011 emit_bcond_fp (NE, operands[0]);
1014 operands[1] = hppa_compare_op0;
1015 operands[2] = hppa_compare_op1;
1018 (define_expand "bgtu"
1020 (if_then_else (gtu (match_dup 1) (match_dup 2))
1021 (label_ref (match_operand 0 "" ""))
1026 if (hppa_branch_type != CMP_SI)
1028 operands[1] = hppa_compare_op0;
1029 operands[2] = hppa_compare_op1;
1032 (define_expand "bltu"
1034 (if_then_else (ltu (match_dup 1) (match_dup 2))
1035 (label_ref (match_operand 0 "" ""))
1040 if (hppa_branch_type != CMP_SI)
1042 operands[1] = hppa_compare_op0;
1043 operands[2] = hppa_compare_op1;
1046 (define_expand "bgeu"
1048 (if_then_else (geu (match_dup 1) (match_dup 2))
1049 (label_ref (match_operand 0 "" ""))
1054 if (hppa_branch_type != CMP_SI)
1056 operands[1] = hppa_compare_op0;
1057 operands[2] = hppa_compare_op1;
1060 (define_expand "bleu"
1062 (if_then_else (leu (match_dup 1) (match_dup 2))
1063 (label_ref (match_operand 0 "" ""))
1068 if (hppa_branch_type != CMP_SI)
1070 operands[1] = hppa_compare_op0;
1071 operands[2] = hppa_compare_op1;
1074 ;; Match the branch patterns.
1077 ;; Note a long backward conditional branch with an annulled delay slot
1078 ;; has a length of 12.
1082 (match_operator 3 "comparison_operator"
1083 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1084 (match_operand:SI 2 "arith5_operand" "rL")])
1085 (label_ref (match_operand 0 "" ""))
1090 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1091 get_attr_length (insn), 0, insn);
1093 [(set_attr "type" "cbranch")
1094 (set (attr "length")
1095 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1098 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1101 (eq (symbol_ref "flag_pic") (const_int 0))
1105 ;; Match the negated branch.
1110 (match_operator 3 "comparison_operator"
1111 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1112 (match_operand:SI 2 "arith5_operand" "rL")])
1114 (label_ref (match_operand 0 "" ""))))]
1118 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1119 get_attr_length (insn), 1, insn);
1121 [(set_attr "type" "cbranch")
1122 (set (attr "length")
1123 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1126 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1129 (eq (symbol_ref "flag_pic") (const_int 0))
1133 ;; Branch on Bit patterns.
1137 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1139 (match_operand:SI 1 "uint5_operand" ""))
1141 (label_ref (match_operand 2 "" ""))
1146 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1147 get_attr_length (insn), 0, insn, 0);
1149 [(set_attr "type" "cbranch")
1150 (set (attr "length")
1151 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1159 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1161 (match_operand:SI 1 "uint5_operand" ""))
1164 (label_ref (match_operand 2 "" ""))))]
1168 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1169 get_attr_length (insn), 1, insn, 0);
1171 [(set_attr "type" "cbranch")
1172 (set (attr "length")
1173 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1181 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1183 (match_operand:SI 1 "uint5_operand" ""))
1185 (label_ref (match_operand 2 "" ""))
1190 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1191 get_attr_length (insn), 0, insn, 1);
1193 [(set_attr "type" "cbranch")
1194 (set (attr "length")
1195 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1203 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1205 (match_operand:SI 1 "uint5_operand" ""))
1208 (label_ref (match_operand 2 "" ""))))]
1212 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1213 get_attr_length (insn), 1, insn, 1);
1215 [(set_attr "type" "cbranch")
1216 (set (attr "length")
1217 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1222 ;; Branch on Variable Bit patterns.
1226 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1228 (match_operand:SI 1 "register_operand" "q"))
1230 (label_ref (match_operand 2 "" ""))
1235 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1236 get_attr_length (insn), 0, insn, 0);
1238 [(set_attr "type" "cbranch")
1239 (set (attr "length")
1240 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1248 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1250 (match_operand:SI 1 "register_operand" "q"))
1253 (label_ref (match_operand 2 "" ""))))]
1257 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1258 get_attr_length (insn), 1, insn, 0);
1260 [(set_attr "type" "cbranch")
1261 (set (attr "length")
1262 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1270 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1272 (match_operand:SI 1 "register_operand" "q"))
1274 (label_ref (match_operand 2 "" ""))
1279 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1280 get_attr_length (insn), 0, insn, 1);
1282 [(set_attr "type" "cbranch")
1283 (set (attr "length")
1284 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1292 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1294 (match_operand:SI 1 "register_operand" "q"))
1297 (label_ref (match_operand 2 "" ""))))]
1301 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1302 get_attr_length (insn), 1, insn, 1);
1304 [(set_attr "type" "cbranch")
1305 (set (attr "length")
1306 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1311 ;; Floating point branches
1313 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1314 (label_ref (match_operand 0 "" ""))
1316 "! TARGET_SOFT_FLOAT"
1319 if (INSN_ANNULLED_BRANCH_P (insn))
1320 return \"ftest\;b,n %0\";
1322 return \"ftest\;b%* %0\";
1324 [(set_attr "type" "fbranch")
1325 (set_attr "length" "8")])
1328 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1330 (label_ref (match_operand 0 "" ""))))]
1331 "! TARGET_SOFT_FLOAT"
1334 if (INSN_ANNULLED_BRANCH_P (insn))
1335 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
1337 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
1339 [(set_attr "type" "fbranch")
1340 (set_attr "length" "12")])
1342 ;; Move instructions
1344 (define_expand "movsi"
1345 [(set (match_operand:SI 0 "general_operand" "")
1346 (match_operand:SI 1 "general_operand" ""))]
1350 if (emit_move_sequence (operands, SImode, 0))
1354 ;; Reloading an SImode or DImode value requires a scratch register if
1355 ;; going in to or out of float point registers.
1357 (define_expand "reload_insi"
1358 [(set (match_operand:SI 0 "register_operand" "=Z")
1359 (match_operand:SI 1 "non_hard_reg_operand" ""))
1360 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
1364 if (emit_move_sequence (operands, SImode, operands[2]))
1367 /* We don't want the clobber emitted, so handle this ourselves. */
1368 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1372 (define_expand "reload_outsi"
1373 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
1374 (match_operand:SI 1 "register_operand" "Z"))
1375 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
1379 if (emit_move_sequence (operands, SImode, operands[2]))
1382 /* We don't want the clobber emitted, so handle this ourselves. */
1383 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1387 ;;; pic symbol references
1390 [(set (match_operand:SI 0 "register_operand" "=r")
1391 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
1392 (match_operand:SI 2 "symbolic_operand" ""))))]
1393 "flag_pic && operands[1] == pic_offset_table_rtx"
1395 [(set_attr "type" "load")
1396 (set_attr "length" "4")])
1399 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
1400 "=r,r,r,r,r,Q,*q,!f,f,*TR")
1401 (match_operand:SI 1 "move_operand"
1402 "r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
1403 "(register_operand (operands[0], SImode)
1404 || reg_or_0_operand (operands[1], SImode))
1405 && ! TARGET_SOFT_FLOAT"
1410 {zdepi|depwi,z} %Z1,%0
1417 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
1418 (set_attr "pa_combine_type" "addmove")
1419 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
1422 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
1424 (match_operand:SI 1 "move_operand"
1425 "r,J,N,K,RQ,rM,rM"))]
1426 "(register_operand (operands[0], SImode)
1427 || reg_or_0_operand (operands[1], SImode))
1428 && TARGET_SOFT_FLOAT"
1433 {zdepi|depwi,z} %Z1,%0
1437 [(set_attr "type" "move,move,move,move,load,store,move")
1438 (set_attr "pa_combine_type" "addmove")
1439 (set_attr "length" "4,4,4,4,4,4,4")])
1442 [(set (match_operand:SI 0 "register_operand" "=r")
1443 (mem:SI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
1444 (match_operand:SI 2 "register_operand" "r"))))]
1445 "! TARGET_DISABLE_INDEXING"
1448 /* Reload can create backwards (relative to cse) unscaled index
1449 address modes when eliminating registers and possibly for
1450 pseudos that don't get hard registers. Deal with it. */
1451 if (operands[2] == hard_frame_pointer_rtx
1452 || operands[2] == stack_pointer_rtx)
1453 return \"{ldwx|ldw} %1(%2),%0\";
1455 return \"{ldwx|ldw} %2(%1),%0\";
1457 [(set_attr "type" "load")
1458 (set_attr "length" "4")])
1461 [(set (match_operand:SI 0 "register_operand" "=r")
1462 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
1463 (match_operand:SI 2 "basereg_operand" "r"))))]
1464 "! TARGET_DISABLE_INDEXING"
1467 /* Reload can create backwards (relative to cse) unscaled index
1468 address modes when eliminating registers and possibly for
1469 pseudos that don't get hard registers. Deal with it. */
1470 if (operands[1] == hard_frame_pointer_rtx
1471 || operands[1] == stack_pointer_rtx)
1472 return \"{ldwx|ldw} %2(%1),%0\";
1474 return \"{ldwx|ldw} %1(%2),%0\";
1476 [(set_attr "type" "load")
1477 (set_attr "length" "4")])
1479 ;; Load or store with base-register modification.
1481 (define_expand "pre_load"
1482 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1483 (mem (plus (match_operand 1 "register_operand" "")
1484 (match_operand 2 "pre_cint_operand" ""))))
1486 (plus (match_dup 1) (match_dup 2)))])]
1490 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
1494 (define_insn "pre_ldw"
1495 [(set (match_operand:SI 0 "register_operand" "=r")
1496 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
1497 (match_operand:SI 2 "pre_cint_operand" ""))))
1499 (plus:SI (match_dup 1) (match_dup 2)))]
1503 if (INTVAL (operands[2]) < 0)
1504 return \"{ldwm|ldw,mb} %2(%1),%0\";
1505 return \"{ldws|ldw},mb %2(%1),%0\";
1507 [(set_attr "type" "load")
1508 (set_attr "length" "4")])
1511 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
1512 (match_operand:SI 1 "pre_cint_operand" "")))
1513 (match_operand:SI 2 "reg_or_0_operand" "rM"))
1515 (plus:SI (match_dup 0) (match_dup 1)))]
1519 if (INTVAL (operands[1]) < 0)
1520 return \"{stwm|stw,mb} %r2,%1(%0)\";
1521 return \"{stws|stw},mb %r2,%1(%0)\";
1523 [(set_attr "type" "store")
1524 (set_attr "length" "4")])
1527 [(set (match_operand:SI 0 "register_operand" "=r")
1528 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
1530 (plus:SI (match_dup 1)
1531 (match_operand:SI 2 "post_cint_operand" "")))]
1535 if (INTVAL (operands[2]) > 0)
1536 return \"{ldwm|ldw,ma} %2(%1),%0\";
1537 return \"{ldws|ldw},ma %2(%1),%0\";
1539 [(set_attr "type" "load")
1540 (set_attr "length" "4")])
1542 (define_expand "post_store"
1543 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
1544 (match_operand 1 "reg_or_0_operand" ""))
1547 (match_operand 2 "post_cint_operand" "")))])]
1551 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
1555 (define_insn "post_stw"
1556 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
1557 (match_operand:SI 1 "reg_or_0_operand" "rM"))
1559 (plus:SI (match_dup 0)
1560 (match_operand:SI 2 "post_cint_operand" "")))]
1564 if (INTVAL (operands[2]) > 0)
1565 return \"{stwm|stw,ma} %r1,%2(%0)\";
1566 return \"{stws|stw},ma %r1,%2(%0)\";
1568 [(set_attr "type" "store")
1569 (set_attr "length" "4")])
1571 ;; For loading the address of a label while generating PIC code.
1572 ;; Note since this pattern can be created at reload time (via movsi), all
1573 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
1575 [(set (match_operand 0 "pmode_register_operand" "=a")
1576 (match_operand 1 "pic_label_operand" ""))]
1580 rtx label_rtx = gen_label_rtx ();
1582 extern FILE *asm_out_file;
1584 xoperands[0] = operands[0];
1585 xoperands[1] = operands[1];
1586 xoperands[2] = label_rtx;
1587 output_asm_insn (\"{bl|b,l} .+8,%0\", xoperands);
1588 output_asm_insn (\"{depi|depwi} 0,31,2,%0\", xoperands);
1589 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1590 CODE_LABEL_NUMBER (label_rtx));
1592 /* If we're trying to load the address of a label that happens to be
1593 close, then we can use a shorter sequence. */
1594 if (GET_CODE (operands[1]) == LABEL_REF
1596 && abs (insn_addresses[INSN_UID (XEXP (operands[1], 0))]
1597 - insn_addresses[INSN_UID (insn)]) < 8100)
1599 /* Prefixing with R% here is wrong, it extracts just 11 bits and is
1600 always non-negative. */
1601 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
1605 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
1606 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
1610 [(set_attr "type" "multi")
1611 (set_attr "length" "16")]) ; 12 or 16
1614 [(set (match_operand:SI 0 "register_operand" "=a")
1615 (plus:SI (match_operand:SI 1 "register_operand" "r")
1616 (high:SI (match_operand 2 "" ""))))]
1617 "symbolic_operand (operands[2], Pmode)
1618 && ! function_label_operand (operands[2])
1621 [(set_attr "type" "binary")
1622 (set_attr "length" "4")])
1624 ; We need this to make sure CSE doesn't simplify a memory load with a
1625 ; symbolic address, whose content it think it knows. For PIC, what CSE
1626 ; think is the real value will be the address of that value.
1628 [(set (match_operand:SI 0 "register_operand" "=r")
1630 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1632 [(match_operand:SI 2 "symbolic_operand" "")] 0))))]
1638 return \"ldw RT'%G2(%1),%0\";
1640 [(set_attr "type" "load")
1641 (set_attr "length" "4")])
1643 ;; Always use addil rather than ldil;add sequences. This allows the
1644 ;; HP linker to eliminate the dp relocation if the symbolic operand
1645 ;; lives in the TEXT space.
1647 [(set (match_operand:SI 0 "register_operand" "=a")
1648 (high:SI (match_operand 1 "" "")))]
1649 "symbolic_operand (operands[1], Pmode)
1650 && ! function_label_operand (operands[1])
1651 && ! read_only_operand (operands[1])
1655 if (TARGET_LONG_LOAD_STORE)
1656 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
1658 return \"addil LR'%H1,%%r27\";
1660 [(set_attr "type" "binary")
1661 (set (attr "length")
1662 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
1667 ;; This is for use in the prologue/epilogue code. We need it
1668 ;; to add large constants to a stack pointer or frame pointer.
1669 ;; Because of the additional %r1 pressure, we probably do not
1670 ;; want to use this in general code, so make it available
1671 ;; only after reload.
1673 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
1674 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
1675 (high:SI (match_operand 2 "const_int_operand" ""))))]
1679 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
1680 [(set_attr "type" "binary,binary")
1681 (set_attr "length" "4,8")])
1684 [(set (match_operand:SI 0 "register_operand" "=r")
1685 (high:SI (match_operand 1 "" "")))]
1686 "(!flag_pic || !symbolic_operand (operands[1]), Pmode)
1687 && !is_function_label_plus_const (operands[1])"
1690 if (symbolic_operand (operands[1], Pmode))
1691 return \"ldil LR'%H1,%0\";
1693 return \"ldil L'%G1,%0\";
1695 [(set_attr "type" "move")
1696 (set_attr "length" "4")])
1699 [(set (match_operand:SI 0 "register_operand" "=r")
1700 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1701 (match_operand:SI 2 "immediate_operand" "i")))]
1702 "!is_function_label_plus_const (operands[2])"
1705 if (flag_pic && symbolic_operand (operands[2], Pmode))
1707 else if (symbolic_operand (operands[2], Pmode))
1708 return \"ldo RR'%G2(%1),%0\";
1710 return \"ldo R'%G2(%1),%0\";
1712 [(set_attr "type" "move")
1713 (set_attr "length" "4")])
1715 ;; Now that a symbolic_address plus a constant is broken up early
1716 ;; in the compilation phase (for better CSE) we need a special
1717 ;; combiner pattern to load the symbolic address plus the constant
1718 ;; in only 2 instructions. (For cases where the symbolic address
1719 ;; was not a common subexpression.)
1721 [(set (match_operand:SI 0 "register_operand" "")
1722 (match_operand:SI 1 "symbolic_operand" ""))
1723 (clobber (match_operand:SI 2 "register_operand" ""))]
1724 "! (flag_pic && pic_label_operand (operands[1], SImode))"
1725 [(set (match_dup 2) (high:SI (match_dup 1)))
1726 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
1729 ;; hppa_legitimize_address goes to a great deal of trouble to
1730 ;; create addresses which use indexing. In some cases, this
1731 ;; is a lose because there isn't any store instructions which
1732 ;; allow indexed addresses (with integer register source).
1734 ;; These define_splits try to turn a 3 insn store into
1735 ;; a 2 insn store with some creative RTL rewriting.
1737 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
1738 (match_operand:SI 1 "shadd_operand" ""))
1739 (plus:SI (match_operand:SI 2 "register_operand" "")
1740 (match_operand:SI 3 "const_int_operand" ""))))
1741 (match_operand:SI 4 "register_operand" ""))
1742 (clobber (match_operand:SI 5 "register_operand" ""))]
1744 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
1746 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
1750 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
1751 (match_operand:SI 1 "shadd_operand" ""))
1752 (plus:SI (match_operand:SI 2 "register_operand" "")
1753 (match_operand:SI 3 "const_int_operand" ""))))
1754 (match_operand:HI 4 "register_operand" ""))
1755 (clobber (match_operand:SI 5 "register_operand" ""))]
1757 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
1759 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
1763 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
1764 (match_operand:SI 1 "shadd_operand" ""))
1765 (plus:SI (match_operand:SI 2 "register_operand" "")
1766 (match_operand:SI 3 "const_int_operand" ""))))
1767 (match_operand:QI 4 "register_operand" ""))
1768 (clobber (match_operand:SI 5 "register_operand" ""))]
1770 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
1772 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
1775 (define_expand "movhi"
1776 [(set (match_operand:HI 0 "general_operand" "")
1777 (match_operand:HI 1 "general_operand" ""))]
1781 if (emit_move_sequence (operands, HImode, 0))
1786 [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
1787 (match_operand:HI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
1788 "register_operand (operands[0], HImode)
1789 || reg_or_0_operand (operands[1], HImode)"
1794 {zdepi|depwi,z} %Z1,%0
1799 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
1800 (set_attr "pa_combine_type" "addmove")
1801 (set_attr "length" "4,4,4,4,4,4,4,4")])
1804 [(set (match_operand:HI 0 "register_operand" "=r")
1805 (mem:HI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
1806 (match_operand:SI 2 "register_operand" "r"))))]
1807 "! TARGET_DISABLE_INDEXING"
1810 /* Reload can create backwards (relative to cse) unscaled index
1811 address modes when eliminating registers and possibly for
1812 pseudos that don't get hard registers. Deal with it. */
1813 if (operands[2] == hard_frame_pointer_rtx
1814 || operands[2] == stack_pointer_rtx)
1815 return \"{ldhx|ldh} %1(%2),%0\";
1817 return \"{ldhx|ldh} %2(%1),%0\";
1819 [(set_attr "type" "load")
1820 (set_attr "length" "4")])
1823 [(set (match_operand:HI 0 "register_operand" "=r")
1824 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
1825 (match_operand:SI 2 "basereg_operand" "r"))))]
1826 "! TARGET_DISABLE_INDEXING"
1829 /* Reload can create backwards (relative to cse) unscaled index
1830 address modes when eliminating registers and possibly for
1831 pseudos that don't get hard registers. Deal with it. */
1832 if (operands[1] == hard_frame_pointer_rtx
1833 || operands[1] == stack_pointer_rtx)
1834 return \"{ldhx|ldh} %2(%1),%0\";
1836 return \"{ldhx|ldh} %1(%2),%0\";
1838 [(set_attr "type" "load")
1839 (set_attr "length" "4")])
1841 ; Now zero extended variants.
1843 [(set (match_operand:SI 0 "register_operand" "=r")
1844 (zero_extend:SI (mem:HI
1846 (match_operand:SI 1 "basereg_operand" "r")
1847 (match_operand:SI 2 "register_operand" "r")))))]
1848 "! TARGET_DISABLE_INDEXING"
1851 /* Reload can create backwards (relative to cse) unscaled index
1852 address modes when eliminating registers and possibly for
1853 pseudos that don't get hard registers. Deal with it. */
1854 if (operands[2] == hard_frame_pointer_rtx
1855 || operands[2] == stack_pointer_rtx)
1856 return \"{ldhx|ldh} %1(%2),%0\";
1858 return \"{ldhx|ldh} %2(%1),%0\";
1860 [(set_attr "type" "load")
1861 (set_attr "length" "4")])
1864 [(set (match_operand:SI 0 "register_operand" "=r")
1865 (zero_extend:SI (mem:HI
1867 (match_operand:SI 1 "register_operand" "r")
1868 (match_operand:SI 2 "basereg_operand" "r")))))]
1869 "! TARGET_DISABLE_INDEXING"
1872 /* Reload can create backwards (relative to cse) unscaled index
1873 address modes when eliminating registers and possibly for
1874 pseudos that don't get hard registers. Deal with it. */
1875 if (operands[1] == hard_frame_pointer_rtx
1876 || operands[1] == stack_pointer_rtx)
1877 return \"{ldhx|ldh} %2(%1),%0\";
1879 return \"{ldhx|ldh} %1(%2),%0\";
1881 [(set_attr "type" "load")
1882 (set_attr "length" "4")])
1885 [(set (match_operand:HI 0 "register_operand" "=r")
1886 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
1887 (match_operand:SI 2 "int5_operand" "L"))))
1889 (plus:SI (match_dup 1) (match_dup 2)))]
1891 "{ldhs|ldh},mb %2(%1),%0"
1892 [(set_attr "type" "load")
1893 (set_attr "length" "4")])
1895 ; And a zero extended variant.
1897 [(set (match_operand:SI 0 "register_operand" "=r")
1898 (zero_extend:SI (mem:HI
1900 (match_operand:SI 1 "register_operand" "+r")
1901 (match_operand:SI 2 "int5_operand" "L")))))
1903 (plus:SI (match_dup 1) (match_dup 2)))]
1905 "{ldhs|ldh},mb %2(%1),%0"
1906 [(set_attr "type" "load")
1907 (set_attr "length" "4")])
1910 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
1911 (match_operand:SI 1 "int5_operand" "L")))
1912 (match_operand:HI 2 "reg_or_0_operand" "rM"))
1914 (plus:SI (match_dup 0) (match_dup 1)))]
1916 "{sths|sth},mb %r2,%1(%0)"
1917 [(set_attr "type" "store")
1918 (set_attr "length" "4")])
1921 [(set (match_operand:HI 0 "register_operand" "=r")
1922 (high:HI (match_operand 1 "const_int_operand" "")))]
1925 [(set_attr "type" "move")
1926 (set_attr "length" "4")])
1929 [(set (match_operand:HI 0 "register_operand" "=r")
1930 (lo_sum:HI (match_operand:HI 1 "register_operand" "r")
1931 (match_operand 2 "const_int_operand" "")))]
1934 [(set_attr "type" "move")
1935 (set_attr "length" "4")])
1937 (define_expand "movqi"
1938 [(set (match_operand:QI 0 "general_operand" "")
1939 (match_operand:QI 1 "general_operand" ""))]
1943 if (emit_move_sequence (operands, QImode, 0))
1948 [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
1949 (match_operand:QI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
1950 "register_operand (operands[0], QImode)
1951 || reg_or_0_operand (operands[1], QImode)"
1956 {zdepi|depwi,z} %Z1,%0
1961 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
1962 (set_attr "pa_combine_type" "addmove")
1963 (set_attr "length" "4,4,4,4,4,4,4,4")])
1966 [(set (match_operand:QI 0 "register_operand" "=r")
1967 (mem:QI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
1968 (match_operand:SI 2 "register_operand" "r"))))]
1969 "! TARGET_DISABLE_INDEXING"
1972 /* Reload can create backwards (relative to cse) unscaled index
1973 address modes when eliminating registers and possibly for
1974 pseudos that don't get hard registers. Deal with it. */
1975 if (operands[2] == hard_frame_pointer_rtx
1976 || operands[2] == stack_pointer_rtx)
1977 return \"{ldbx|ldb} %1(%2),%0\";
1979 return \"{ldbx|ldb} %2(%1),%0\";
1981 [(set_attr "type" "load")
1982 (set_attr "length" "4")])
1985 [(set (match_operand:QI 0 "register_operand" "=r")
1986 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
1987 (match_operand:SI 2 "basereg_operand" "r"))))]
1988 "! TARGET_DISABLE_INDEXING"
1991 /* Reload can create backwards (relative to cse) unscaled index
1992 address modes when eliminating registers and possibly for
1993 pseudos that don't get hard registers. Deal with it. */
1994 if (operands[1] == hard_frame_pointer_rtx
1995 || operands[1] == stack_pointer_rtx)
1996 return \"{ldbx|ldb} %2(%1),%0\";
1998 return \"{ldbx|ldb} %1(%2),%0\";
2000 [(set_attr "type" "load")
2001 (set_attr "length" "4")])
2003 ; Indexed byte load with zero extension to SImode or HImode.
2005 [(set (match_operand:SI 0 "register_operand" "=r")
2006 (zero_extend:SI (mem:QI
2008 (match_operand:SI 1 "basereg_operand" "r")
2009 (match_operand:SI 2 "register_operand" "r")))))]
2010 "! TARGET_DISABLE_INDEXING"
2013 /* Reload can create backwards (relative to cse) unscaled index
2014 address modes when eliminating registers and possibly for
2015 pseudos that don't get hard registers. Deal with it. */
2016 if (operands[2] == hard_frame_pointer_rtx
2017 || operands[2] == stack_pointer_rtx)
2018 return \"{ldbx|ldb} %1(%2),%0\";
2020 return \"{ldbx|ldb} %2(%1),%0\";
2022 [(set_attr "type" "load")
2023 (set_attr "length" "4")])
2026 [(set (match_operand:SI 0 "register_operand" "=r")
2027 (zero_extend:SI (mem:QI
2029 (match_operand:SI 1 "register_operand" "r")
2030 (match_operand:SI 2 "basereg_operand" "r")))))]
2031 "! TARGET_DISABLE_INDEXING"
2034 /* Reload can create backwards (relative to cse) unscaled index
2035 address modes when eliminating registers and possibly for
2036 pseudos that don't get hard registers. Deal with it. */
2037 if (operands[1] == hard_frame_pointer_rtx
2038 || operands[1] == stack_pointer_rtx)
2039 return \"{ldbx|ldb} %2(%1),%0\";
2041 return \"{ldbx|ldb} %1(%2),%0\";
2043 [(set_attr "type" "load")
2044 (set_attr "length" "4")])
2047 [(set (match_operand:HI 0 "register_operand" "=r")
2048 (zero_extend:HI (mem:QI
2050 (match_operand:SI 1 "basereg_operand" "r")
2051 (match_operand:SI 2 "register_operand" "r")))))]
2052 "! TARGET_DISABLE_INDEXING"
2055 /* Reload can create backwards (relative to cse) unscaled index
2056 address modes when eliminating registers and possibly for
2057 pseudos that don't get hard registers. Deal with it. */
2058 if (operands[2] == hard_frame_pointer_rtx
2059 || operands[2] == stack_pointer_rtx)
2060 return \"{ldbx|ldb} %1(%2),%0\";
2062 return \"{ldbx|ldb} %2(%1),%0\";
2064 [(set_attr "type" "load")
2065 (set_attr "length" "4")])
2068 [(set (match_operand:HI 0 "register_operand" "=r")
2069 (zero_extend:HI (mem:QI
2071 (match_operand:SI 1 "register_operand" "r")
2072 (match_operand:SI 2 "basereg_operand" "r")))))]
2073 "! TARGET_DISABLE_INDEXING"
2076 /* Reload can create backwards (relative to cse) unscaled index
2077 address modes when eliminating registers and possibly for
2078 pseudos that don't get hard registers. Deal with it. */
2079 if (operands[1] == hard_frame_pointer_rtx
2080 || operands[1] == stack_pointer_rtx)
2081 return \"{ldbx|ldb} %2(%1),%0\";
2083 return \"{ldbx|ldb} %1(%2),%0\";
2085 [(set_attr "type" "load")
2086 (set_attr "length" "4")])
2089 [(set (match_operand:QI 0 "register_operand" "=r")
2090 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2091 (match_operand:SI 2 "int5_operand" "L"))))
2092 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2094 "{ldbs|ldb},mb %2(%1),%0"
2095 [(set_attr "type" "load")
2096 (set_attr "length" "4")])
2098 ; Now the same thing with zero extensions.
2100 [(set (match_operand:SI 0 "register_operand" "=r")
2101 (zero_extend:SI (mem:QI (plus:SI
2102 (match_operand:SI 1 "register_operand" "+r")
2103 (match_operand:SI 2 "int5_operand" "L")))))
2104 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2106 "{ldbs|ldb},mb %2(%1),%0"
2107 [(set_attr "type" "load")
2108 (set_attr "length" "4")])
2111 [(set (match_operand:HI 0 "register_operand" "=r")
2112 (zero_extend:HI (mem:QI (plus:SI
2113 (match_operand:SI 1 "register_operand" "+r")
2114 (match_operand:SI 2 "int5_operand" "L")))))
2115 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2117 "{ldbs|ldb},mb %2(%1),%0"
2118 [(set_attr "type" "load")
2119 (set_attr "length" "4")])
2122 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2123 (match_operand:SI 1 "int5_operand" "L")))
2124 (match_operand:QI 2 "reg_or_0_operand" "rM"))
2126 (plus:SI (match_dup 0) (match_dup 1)))]
2128 "{stbs|stb},mb %r2,%1(%0)"
2129 [(set_attr "type" "store")
2130 (set_attr "length" "4")])
2132 ;; The definition of this insn does not really explain what it does,
2133 ;; but it should suffice
2134 ;; that anything generated as this insn will be recognized as one
2135 ;; and that it will not successfully combine with anything.
2136 (define_expand "movstrsi"
2137 [(parallel [(set (match_operand:BLK 0 "" "")
2138 (match_operand:BLK 1 "" ""))
2139 (clobber (match_dup 7))
2140 (clobber (match_dup 8))
2141 (clobber (match_dup 4))
2142 (clobber (match_dup 5))
2143 (clobber (match_dup 6))
2144 (use (match_operand:SI 2 "arith_operand" ""))
2145 (use (match_operand:SI 3 "const_int_operand" ""))])]
2151 /* HP provides very fast block move library routine for the PA;
2152 this routine includes:
2154 4x4 byte at a time block moves,
2155 1x4 byte at a time with alignment checked at runtime with
2156 attempts to align the source and destination as needed
2159 With that in mind, here's the heuristics to try and guess when
2160 the inlined block move will be better than the library block
2163 If the size isn't constant, then always use the library routines.
2165 If the size is large in respect to the known alignment, then use
2166 the library routines.
2168 If the size is small in repsect to the known alignment, then open
2169 code the copy (since that will lead to better scheduling).
2171 Else use the block move pattern. */
2173 /* Undetermined size, use the library routine. */
2174 if (GET_CODE (operands[2]) != CONST_INT)
2177 size = INTVAL (operands[2]);
2178 align = INTVAL (operands[3]);
2179 align = align > 4 ? 4 : align;
2181 /* If size/alignment > 8 (eg size is large in respect to alignment),
2182 then use the library routines. */
2183 if (size / align > 16)
2186 /* This does happen, but not often enough to worry much about. */
2187 if (size / align < MOVE_RATIO)
2190 /* Fall through means we're going to use our block move pattern. */
2192 = change_address (operands[0], VOIDmode,
2193 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
2195 = change_address (operands[1], VOIDmode,
2196 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
2197 operands[4] = gen_reg_rtx (SImode);
2198 operands[5] = gen_reg_rtx (SImode);
2199 operands[6] = gen_reg_rtx (SImode);
2200 operands[7] = XEXP (operands[0], 0);
2201 operands[8] = XEXP (operands[1], 0);
2204 ;; The operand constraints are written like this to support both compile-time
2205 ;; and run-time determined byte count. If the count is run-time determined,
2206 ;; the register with the byte count is clobbered by the copying code, and
2207 ;; therefore it is forced to operand 2. If the count is compile-time
2208 ;; determined, we need two scratch registers for the unrolled code.
2209 (define_insn "movstrsi_internal"
2210 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
2211 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
2212 (clobber (match_dup 0))
2213 (clobber (match_dup 1))
2214 (clobber (match_operand:SI 2 "register_operand" "=r,r")) ;loop cnt/tmp
2215 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp
2216 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
2217 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
2218 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
2220 "* return output_block_move (operands, !which_alternative);"
2221 [(set_attr "type" "multi,multi")])
2223 ;; Floating point move insns
2225 ;; This pattern forces (set (reg:DF ...) (const_double ...))
2226 ;; to be reloaded by putting the constant into memory when
2227 ;; reg is a floating point register.
2229 ;; For integer registers we use ldil;ldo to set the appropriate
2232 ;; This must come before the movdf pattern, and it must be present
2233 ;; to handle obscure reloading cases.
2235 [(set (match_operand:DF 0 "register_operand" "=?r,f")
2236 (match_operand:DF 1 "" "?F,m"))]
2237 "GET_CODE (operands[1]) == CONST_DOUBLE
2238 && operands[1] != CONST0_RTX (DFmode)
2239 && ! TARGET_SOFT_FLOAT"
2240 "* return (which_alternative == 0 ? output_move_double (operands)
2241 : \"fldd%F1 %1,%0\");"
2242 [(set_attr "type" "move,fpload")
2243 (set_attr "length" "16,4")])
2245 (define_expand "movdf"
2246 [(set (match_operand:DF 0 "general_operand" "")
2247 (match_operand:DF 1 "general_operand" ""))]
2251 if (emit_move_sequence (operands, DFmode, 0))
2255 ;; Reloading an SImode or DImode value requires a scratch register if
2256 ;; going in to or out of float point registers.
2258 (define_expand "reload_indf"
2259 [(set (match_operand:DF 0 "register_operand" "=Z")
2260 (match_operand:DF 1 "non_hard_reg_operand" ""))
2261 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
2265 if (emit_move_sequence (operands, DFmode, operands[2]))
2268 /* We don't want the clobber emitted, so handle this ourselves. */
2269 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2273 (define_expand "reload_outdf"
2274 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
2275 (match_operand:DF 1 "register_operand" "Z"))
2276 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
2280 if (emit_move_sequence (operands, DFmode, operands[2]))
2283 /* We don't want the clobber emitted, so handle this ourselves. */
2284 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2289 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
2290 "=f,*r,RQ,?o,?Q,f,*r,*r")
2291 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
2292 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
2293 "(register_operand (operands[0], DFmode)
2294 || reg_or_0_operand (operands[1], DFmode))
2295 && ! (GET_CODE (operands[1]) == CONST_DOUBLE
2296 && GET_CODE (operands[0]) == MEM)
2297 && ! TARGET_SOFT_FLOAT"
2300 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
2301 || operands[1] == CONST0_RTX (DFmode))
2302 return output_fp_move_double (operands);
2303 return output_move_double (operands);
2305 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
2306 (set_attr "length" "4,8,4,8,16,4,8,16")])
2309 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
2311 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
2313 "(register_operand (operands[0], DFmode)
2314 || reg_or_0_operand (operands[1], DFmode))
2315 && TARGET_SOFT_FLOAT"
2318 return output_move_double (operands);
2320 [(set_attr "type" "move,store,store,load,load")
2321 (set_attr "length" "8,8,16,8,16")])
2324 [(set (match_operand:DF 0 "register_operand" "=fx")
2325 (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2326 (match_operand:SI 2 "register_operand" "r"))))]
2327 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
2330 /* Reload can create backwards (relative to cse) unscaled index
2331 address modes when eliminating registers and possibly for
2332 pseudos that don't get hard registers. Deal with it. */
2333 if (operands[2] == hard_frame_pointer_rtx
2334 || operands[2] == stack_pointer_rtx)
2335 return \"{flddx|fldd} %1(%2),%0\";
2337 return \"{flddx|fldd} %2(%1),%0\";
2339 [(set_attr "type" "fpload")
2340 (set_attr "length" "4")])
2343 [(set (match_operand:DF 0 "register_operand" "=fx")
2344 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
2345 (match_operand:SI 2 "basereg_operand" "r"))))]
2346 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
2349 /* Reload can create backwards (relative to cse) unscaled index
2350 address modes when eliminating registers and possibly for
2351 pseudos that don't get hard registers. Deal with it. */
2352 if (operands[1] == hard_frame_pointer_rtx
2353 || operands[1] == stack_pointer_rtx)
2354 return \"{flddx|fldd} %2(%1),%0\";
2356 return \"{flddx|fldd} %1(%2),%0\";
2358 [(set_attr "type" "fpload")
2359 (set_attr "length" "4")])
2362 [(set (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2363 (match_operand:SI 2 "register_operand" "r")))
2364 (match_operand:DF 0 "register_operand" "fx"))]
2365 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
2368 /* Reload can create backwards (relative to cse) unscaled index
2369 address modes when eliminating registers and possibly for
2370 pseudos that don't get hard registers. Deal with it. */
2371 if (operands[2] == hard_frame_pointer_rtx
2372 || operands[2] == stack_pointer_rtx)
2373 return \"{fstdx|fstd} %0,%1(%2)\";
2375 return \"{fstdx|fstd} %0,%2(%1)\";
2377 [(set_attr "type" "fpstore")
2378 (set_attr "length" "4")])
2381 [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
2382 (match_operand:SI 2 "basereg_operand" "r")))
2383 (match_operand:DF 0 "register_operand" "fx"))]
2384 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
2387 /* Reload can create backwards (relative to cse) unscaled index
2388 address modes when eliminating registers and possibly for
2389 pseudos that don't get hard registers. Deal with it. */
2390 if (operands[1] == hard_frame_pointer_rtx
2391 || operands[1] == stack_pointer_rtx)
2392 return \"{fstdx|fstd} %0,%2(%1)\";
2394 return \"{fstdx|fstd} %0,%1(%2)\";
2396 [(set_attr "type" "fpstore")
2397 (set_attr "length" "4")])
2399 (define_expand "movdi"
2400 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
2401 (match_operand:DI 1 "general_operand" ""))]
2405 if (emit_move_sequence (operands, DImode, 0))
2409 (define_expand "reload_indi"
2410 [(set (match_operand:DI 0 "register_operand" "=Z")
2411 (match_operand:DI 1 "non_hard_reg_operand" ""))
2412 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2416 if (emit_move_sequence (operands, DImode, operands[2]))
2419 /* We don't want the clobber emitted, so handle this ourselves. */
2420 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2424 (define_expand "reload_outdi"
2425 [(set (match_operand:DI 0 "general_operand" "")
2426 (match_operand:DI 1 "register_operand" "Z"))
2427 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2431 if (emit_move_sequence (operands, DImode, operands[2]))
2434 /* We don't want the clobber emitted, so handle this ourselves. */
2435 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2440 [(set (match_operand:DI 0 "register_operand" "=r")
2441 (high:DI (match_operand 1 "" "")))]
2445 rtx op0 = operands[0];
2446 rtx op1 = operands[1];
2448 if (GET_CODE (op1) == CONST_INT)
2450 operands[0] = operand_subword (op0, 1, 0, DImode);
2451 output_asm_insn (\"ldil L'%1,%0\", operands);
2453 operands[0] = operand_subword (op0, 0, 0, DImode);
2454 if (INTVAL (op1) < 0)
2455 output_asm_insn (\"ldi -1,%0\", operands);
2457 output_asm_insn (\"ldi 0,%0\", operands);
2460 else if (GET_CODE (op1) == CONST_DOUBLE)
2462 operands[0] = operand_subword (op0, 1, 0, DImode);
2463 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
2464 output_asm_insn (\"ldil L'%1,%0\", operands);
2466 operands[0] = operand_subword (op0, 0, 0, DImode);
2467 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
2468 output_asm_insn (singlemove_string (operands), operands);
2474 [(set_attr "type" "move")
2475 (set_attr "length" "8")])
2478 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
2479 "=r,o,Q,r,r,r,f,f,*TR")
2480 (match_operand:DI 1 "general_operand"
2481 "rM,r,r,o*R,Q,i,fM,*TR,f"))]
2482 "(register_operand (operands[0], DImode)
2483 || reg_or_0_operand (operands[1], DImode))
2484 && ! TARGET_SOFT_FLOAT"
2487 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
2488 || (operands[1] == CONST0_RTX (DImode)))
2489 return output_fp_move_double (operands);
2490 return output_move_double (operands);
2492 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
2493 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
2496 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
2498 (match_operand:DI 1 "general_operand"
2500 "(register_operand (operands[0], DImode)
2501 || reg_or_0_operand (operands[1], DImode))
2502 && TARGET_SOFT_FLOAT"
2505 return output_move_double (operands);
2507 [(set_attr "type" "move,store,store,load,load,multi")
2508 (set_attr "length" "8,8,16,8,16,16")])
2511 [(set (match_operand:DI 0 "register_operand" "=r,&r")
2512 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
2513 (match_operand:DI 2 "immediate_operand" "i,i")))]
2517 /* Don't output a 64 bit constant, since we can't trust the assembler to
2518 handle it correctly. */
2519 if (GET_CODE (operands[2]) == CONST_DOUBLE)
2520 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2521 if (which_alternative == 1)
2522 output_asm_insn (\"copy %1,%0\", operands);
2523 return \"ldo R'%G2(%R1),%R0\";
2525 [(set_attr "type" "move,move")
2526 (set_attr "length" "4,8")])
2528 ;; This pattern forces (set (reg:SF ...) (const_double ...))
2529 ;; to be reloaded by putting the constant into memory when
2530 ;; reg is a floating point register.
2532 ;; For integer registers we use ldil;ldo to set the appropriate
2535 ;; This must come before the movsf pattern, and it must be present
2536 ;; to handle obscure reloading cases.
2538 [(set (match_operand:SF 0 "register_operand" "=?r,f")
2539 (match_operand:SF 1 "" "?F,m"))]
2540 "GET_CODE (operands[1]) == CONST_DOUBLE
2541 && operands[1] != CONST0_RTX (SFmode)
2542 && ! TARGET_SOFT_FLOAT"
2543 "* return (which_alternative == 0 ? singlemove_string (operands)
2544 : \" fldw%F1 %1,%0\");"
2545 [(set_attr "type" "move,fpload")
2546 (set_attr "length" "8,4")])
2548 (define_expand "movsf"
2549 [(set (match_operand:SF 0 "general_operand" "")
2550 (match_operand:SF 1 "general_operand" ""))]
2554 if (emit_move_sequence (operands, SFmode, 0))
2558 ;; Reloading an SImode or DImode value requires a scratch register if
2559 ;; going in to or out of float point registers.
2561 (define_expand "reload_insf"
2562 [(set (match_operand:SF 0 "register_operand" "=Z")
2563 (match_operand:SF 1 "non_hard_reg_operand" ""))
2564 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
2568 if (emit_move_sequence (operands, SFmode, operands[2]))
2571 /* We don't want the clobber emitted, so handle this ourselves. */
2572 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2576 (define_expand "reload_outsf"
2577 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
2578 (match_operand:SF 1 "register_operand" "Z"))
2579 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
2583 if (emit_move_sequence (operands, SFmode, operands[2]))
2586 /* We don't want the clobber emitted, so handle this ourselves. */
2587 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2592 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
2594 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
2595 "fG,rG,RQ,RQ,f,rG"))]
2596 "(register_operand (operands[0], SFmode)
2597 || reg_or_0_operand (operands[1], SFmode))
2598 && ! TARGET_SOFT_FLOAT"
2606 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
2607 (set_attr "pa_combine_type" "addmove")
2608 (set_attr "length" "4,4,4,4,4,4")])
2611 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
2613 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
2615 "(register_operand (operands[0], SFmode)
2616 || reg_or_0_operand (operands[1], SFmode))
2617 && TARGET_SOFT_FLOAT"
2622 [(set_attr "type" "move,load,store")
2623 (set_attr "pa_combine_type" "addmove")
2624 (set_attr "length" "4,4,4")])
2627 [(set (match_operand:SF 0 "register_operand" "=fx")
2628 (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2629 (match_operand:SI 2 "register_operand" "r"))))]
2630 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
2633 /* Reload can create backwards (relative to cse) unscaled index
2634 address modes when eliminating registers and possibly for
2635 pseudos that don't get hard registers. Deal with it. */
2636 if (operands[2] == hard_frame_pointer_rtx
2637 || operands[2] == stack_pointer_rtx)
2638 return \"{fldwx|fldw} %1(%2),%0\";
2640 return \"{fldwx|fldw} %2(%1),%0\";
2642 [(set_attr "type" "fpload")
2643 (set_attr "length" "4")])
2646 [(set (match_operand:SF 0 "register_operand" "=fx")
2647 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
2648 (match_operand:SI 2 "basereg_operand" "r"))))]
2649 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
2652 /* Reload can create backwards (relative to cse) unscaled index
2653 address modes when eliminating registers and possibly for
2654 pseudos that don't get hard registers. Deal with it. */
2655 if (operands[1] == hard_frame_pointer_rtx
2656 || operands[1] == stack_pointer_rtx)
2657 return \"{fldwx|fldw} %2(%1),%0\";
2659 return \"{fldwx|fldw} %1(%2),%0\";
2661 [(set_attr "type" "fpload")
2662 (set_attr "length" "4")])
2665 [(set (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2666 (match_operand:SI 2 "register_operand" "r")))
2667 (match_operand:SF 0 "register_operand" "fx"))]
2668 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
2671 /* Reload can create backwards (relative to cse) unscaled index
2672 address modes when eliminating registers and possibly for
2673 pseudos that don't get hard registers. Deal with it. */
2674 if (operands[2] == hard_frame_pointer_rtx
2675 || operands[2] == stack_pointer_rtx)
2676 return \"{fstwx|fstw} %0,%1(%2)\";
2678 return \"{fstwx|fstw} %0,%2(%1)\";
2680 [(set_attr "type" "fpstore")
2681 (set_attr "length" "4")])
2684 [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
2685 (match_operand:SI 2 "basereg_operand" "r")))
2686 (match_operand:SF 0 "register_operand" "fx"))]
2687 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
2690 /* Reload can create backwards (relative to cse) unscaled index
2691 address modes when eliminating registers and possibly for
2692 pseudos that don't get hard registers. Deal with it. */
2693 if (operands[1] == hard_frame_pointer_rtx
2694 || operands[1] == stack_pointer_rtx)
2695 return \"{fstwx|fstw} %0,%2(%1)\";
2697 return \"{fstwx|fstw} %0,%1(%2)\";
2699 [(set_attr "type" "fpstore")
2700 (set_attr "length" "4")])
2703 ;;- zero extension instructions
2704 ;; We have define_expand for zero extension patterns to make sure the
2705 ;; operands get loaded into registers. The define_insns accept
2706 ;; memory operands. This gives us better overall code than just
2707 ;; having a pattern that does or does not accept memory operands.
2709 (define_expand "zero_extendhisi2"
2710 [(set (match_operand:SI 0 "register_operand" "")
2712 (match_operand:HI 1 "register_operand" "")))]
2717 [(set (match_operand:SI 0 "register_operand" "=r,r")
2719 (match_operand:HI 1 "move_operand" "r,RQ")))]
2720 "GET_CODE (operands[1]) != CONST_INT"
2722 {extru|extrw,u} %1,31,16,%0
2724 [(set_attr "type" "shift,load")
2725 (set_attr "length" "4,4")])
2727 (define_expand "zero_extendqihi2"
2728 [(set (match_operand:HI 0 "register_operand" "")
2730 (match_operand:QI 1 "register_operand" "")))]
2735 [(set (match_operand:HI 0 "register_operand" "=r,r")
2737 (match_operand:QI 1 "move_operand" "r,RQ")))]
2738 "GET_CODE (operands[1]) != CONST_INT"
2740 {extru|extrw,u} %1,31,8,%0
2742 [(set_attr "type" "shift,load")
2743 (set_attr "length" "4,4")])
2745 (define_expand "zero_extendqisi2"
2746 [(set (match_operand:SI 0 "register_operand" "")
2748 (match_operand:QI 1 "register_operand" "")))]
2753 [(set (match_operand:SI 0 "register_operand" "=r,r")
2755 (match_operand:QI 1 "move_operand" "r,RQ")))]
2756 "GET_CODE (operands[1]) != CONST_INT"
2758 {extru|extrw,u} %1,31,8,%0
2760 [(set_attr "type" "shift,load")
2761 (set_attr "length" "4,4")])
2763 ;;- sign extension instructions
2765 (define_insn "extendhisi2"
2766 [(set (match_operand:SI 0 "register_operand" "=r")
2767 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
2769 "{extrs|extrw,s} %1,31,16,%0"
2770 [(set_attr "type" "shift")
2771 (set_attr "length" "4")])
2773 (define_insn "extendqihi2"
2774 [(set (match_operand:HI 0 "register_operand" "=r")
2775 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
2777 "{extrs|extrw,s} %1,31,8,%0"
2778 [(set_attr "type" "shift")
2779 (set_attr "length" "4")])
2781 (define_insn "extendqisi2"
2782 [(set (match_operand:SI 0 "register_operand" "=r")
2783 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
2785 "{extrs|extrw,s} %1,31,8,%0"
2786 [(set_attr "type" "shift")
2787 (set_attr "length" "4")])
2789 ;; Conversions between float and double.
2791 (define_insn "extendsfdf2"
2792 [(set (match_operand:DF 0 "register_operand" "=f")
2794 (match_operand:SF 1 "register_operand" "f")))]
2795 "! TARGET_SOFT_FLOAT"
2796 "{fcnvff|fcnv},sgl,dbl %1,%0"
2797 [(set_attr "type" "fpalu")
2798 (set_attr "length" "4")])
2800 (define_insn "truncdfsf2"
2801 [(set (match_operand:SF 0 "register_operand" "=f")
2803 (match_operand:DF 1 "register_operand" "f")))]
2804 "! TARGET_SOFT_FLOAT"
2805 "{fcnvff|fcnv},dbl,sgl %1,%0"
2806 [(set_attr "type" "fpalu")
2807 (set_attr "length" "4")])
2809 ;; Conversion between fixed point and floating point.
2810 ;; Note that among the fix-to-float insns
2811 ;; the ones that start with SImode come first.
2812 ;; That is so that an operand that is a CONST_INT
2813 ;; (and therefore lacks a specific machine mode).
2814 ;; will be recognized as SImode (which is always valid)
2815 ;; rather than as QImode or HImode.
2817 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
2818 ;; to be reloaded by putting the constant into memory.
2819 ;; It must come before the more general floatsisf2 pattern.
2821 [(set (match_operand:SF 0 "register_operand" "=f")
2822 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
2823 "! TARGET_SOFT_FLOAT"
2824 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
2825 [(set_attr "type" "fpalu")
2826 (set_attr "length" "8")])
2828 (define_insn "floatsisf2"
2829 [(set (match_operand:SF 0 "register_operand" "=f")
2830 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2831 "! TARGET_SOFT_FLOAT"
2832 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
2833 [(set_attr "type" "fpalu")
2834 (set_attr "length" "4")])
2836 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
2837 ;; to be reloaded by putting the constant into memory.
2838 ;; It must come before the more general floatsidf2 pattern.
2840 [(set (match_operand:DF 0 "register_operand" "=f")
2841 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
2842 "! TARGET_SOFT_FLOAT"
2843 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
2844 [(set_attr "type" "fpalu")
2845 (set_attr "length" "8")])
2847 (define_insn "floatsidf2"
2848 [(set (match_operand:DF 0 "register_operand" "=f")
2849 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2850 "! TARGET_SOFT_FLOAT"
2851 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
2852 [(set_attr "type" "fpalu")
2853 (set_attr "length" "4")])
2855 (define_expand "floatunssisf2"
2856 [(set (subreg:SI (match_dup 2) 1)
2857 (match_operand:SI 1 "register_operand" ""))
2858 (set (subreg:SI (match_dup 2) 0)
2860 (set (match_operand:SF 0 "register_operand" "")
2861 (float:SF (match_dup 2)))]
2862 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
2867 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
2870 operands[2] = gen_reg_rtx (DImode);
2873 (define_expand "floatunssidf2"
2874 [(set (subreg:SI (match_dup 2) 1)
2875 (match_operand:SI 1 "register_operand" ""))
2876 (set (subreg:SI (match_dup 2) 0)
2878 (set (match_operand:DF 0 "register_operand" "")
2879 (float:DF (match_dup 2)))]
2880 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
2885 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
2888 operands[2] = gen_reg_rtx (DImode);
2891 (define_insn "floatdisf2"
2892 [(set (match_operand:SF 0 "register_operand" "=f")
2893 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2894 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
2895 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
2896 [(set_attr "type" "fpalu")
2897 (set_attr "length" "4")])
2899 (define_insn "floatdidf2"
2900 [(set (match_operand:DF 0 "register_operand" "=f")
2901 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2902 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
2903 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
2904 [(set_attr "type" "fpalu")
2905 (set_attr "length" "4")])
2907 ;; Convert a float to an actual integer.
2908 ;; Truncation is performed as part of the conversion.
2910 (define_insn "fix_truncsfsi2"
2911 [(set (match_operand:SI 0 "register_operand" "=f")
2912 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
2913 "! TARGET_SOFT_FLOAT"
2914 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
2915 [(set_attr "type" "fpalu")
2916 (set_attr "length" "4")])
2918 (define_insn "fix_truncdfsi2"
2919 [(set (match_operand:SI 0 "register_operand" "=f")
2920 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
2921 "! TARGET_SOFT_FLOAT"
2922 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
2923 [(set_attr "type" "fpalu")
2924 (set_attr "length" "4")])
2926 (define_insn "fix_truncsfdi2"
2927 [(set (match_operand:DI 0 "register_operand" "=f")
2928 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
2929 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
2930 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
2931 [(set_attr "type" "fpalu")
2932 (set_attr "length" "4")])
2934 (define_insn "fix_truncdfdi2"
2935 [(set (match_operand:DI 0 "register_operand" "=f")
2936 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
2937 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
2938 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
2939 [(set_attr "type" "fpalu")
2940 (set_attr "length" "4")])
2942 (define_insn "floatunssidf2_pa20"
2943 [(set (match_operand:DF 0 "register_operand" "=f")
2944 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
2945 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
2947 [(set_attr "type" "fpalu")
2948 (set_attr "length" "4")])
2950 (define_insn "floatunssisf2_pa20"
2951 [(set (match_operand:SF 0 "register_operand" "=f")
2952 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
2953 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
2955 [(set_attr "type" "fpalu")
2956 (set_attr "length" "4")])
2958 (define_insn "floatunsdisf2"
2959 [(set (match_operand:SF 0 "register_operand" "=f")
2960 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
2961 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
2962 "fcnv,udw,sgl %1,%0"
2963 [(set_attr "type" "fpalu")
2964 (set_attr "length" "4")])
2966 (define_insn "floatunsdidf2"
2967 [(set (match_operand:DF 0 "register_operand" "=f")
2968 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
2969 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
2970 "fcnv,udw,dbl %1,%0"
2971 [(set_attr "type" "fpalu")
2972 (set_attr "length" "4")])
2974 (define_insn "fixuns_truncsfsi2"
2975 [(set (match_operand:SI 0 "register_operand" "=f")
2976 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
2977 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
2978 "fcnv,t,sgl,uw %1,%0"
2979 [(set_attr "type" "fpalu")
2980 (set_attr "length" "4")])
2982 (define_insn "fixuns_truncdfsi2"
2983 [(set (match_operand:SI 0 "register_operand" "=f")
2984 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
2985 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
2986 "fcnv,t,dbl,uw %1,%0"
2987 [(set_attr "type" "fpalu")
2988 (set_attr "length" "4")])
2990 (define_insn "fixuns_truncsfdi2"
2991 [(set (match_operand:DI 0 "register_operand" "=f")
2992 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
2993 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
2994 "fcnv,t,sgl,udw %1,%0"
2995 [(set_attr "type" "fpalu")
2996 (set_attr "length" "4")])
2998 (define_insn "fixuns_truncdfdi2"
2999 [(set (match_operand:DI 0 "register_operand" "=f")
3000 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3001 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3002 "fcnv,t,dbl,udw %1,%0"
3003 [(set_attr "type" "fpalu")
3004 (set_attr "length" "4")])
3006 ;;- arithmetic instructions
3008 (define_expand "adddi3"
3009 [(set (match_operand:DI 0 "register_operand" "")
3010 (plus:DI (match_operand:DI 1 "register_operand" "")
3011 (match_operand:DI 2 "arith11_operand" "")))]
3016 [(set (match_operand:DI 0 "register_operand" "=r")
3017 (plus:DI (match_operand:DI 1 "register_operand" "%r")
3018 (match_operand:DI 2 "arith11_operand" "rI")))]
3022 if (GET_CODE (operands[2]) == CONST_INT)
3024 if (INTVAL (operands[2]) >= 0)
3025 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
3027 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
3030 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
3032 [(set_attr "type" "binary")
3033 (set_attr "length" "8")])
3036 [(set (match_operand:SI 0 "register_operand" "=r")
3037 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3038 (match_operand:SI 2 "register_operand" "r")))]
3041 [(set_attr "type" "binary")
3042 (set_attr "length" "4")])
3044 ;; define_splits to optimize cases of adding a constant integer
3045 ;; to a register when the constant does not fit in 14 bits. */
3047 [(set (match_operand:SI 0 "register_operand" "")
3048 (plus:SI (match_operand:SI 1 "register_operand" "")
3049 (match_operand:SI 2 "const_int_operand" "")))
3050 (clobber (match_operand:SI 4 "register_operand" ""))]
3051 "! cint_ok_for_move (INTVAL (operands[2]))
3052 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
3053 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
3054 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
3057 int val = INTVAL (operands[2]);
3058 int low = (val < 0) ? -0x2000 : 0x1fff;
3059 int rest = val - low;
3061 operands[2] = GEN_INT (rest);
3062 operands[3] = GEN_INT (low);
3066 [(set (match_operand:SI 0 "register_operand" "")
3067 (plus:SI (match_operand:SI 1 "register_operand" "")
3068 (match_operand:SI 2 "const_int_operand" "")))
3069 (clobber (match_operand:SI 4 "register_operand" ""))]
3070 "! cint_ok_for_move (INTVAL (operands[2]))"
3071 [(set (match_dup 4) (match_dup 2))
3072 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
3076 HOST_WIDE_INT intval = INTVAL (operands[2]);
3078 /* Try dividing the constant by 2, then 4, and finally 8 to see
3079 if we can get a constant which can be loaded into a register
3080 in a single instruction (cint_ok_for_move).
3082 If that fails, try to negate the constant and subtract it
3083 from our input operand. */
3084 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
3086 operands[2] = GEN_INT (intval / 2);
3087 operands[3] = GEN_INT (2);
3089 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
3091 operands[2] = GEN_INT (intval / 4);
3092 operands[3] = GEN_INT (4);
3094 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
3096 operands[2] = GEN_INT (intval / 8);
3097 operands[3] = GEN_INT (8);
3099 else if (cint_ok_for_move (-intval))
3101 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
3102 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
3109 (define_insn "addsi3"
3110 [(set (match_operand:SI 0 "register_operand" "=r,r")
3111 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
3112 (match_operand:SI 2 "arith_operand" "r,J")))]
3115 {addl|add,l} %1,%2,%0
3117 [(set_attr "type" "binary,binary")
3118 (set_attr "pa_combine_type" "addmove")
3119 (set_attr "length" "4,4")])
3121 (define_expand "subdi3"
3122 [(set (match_operand:DI 0 "register_operand" "")
3123 (minus:DI (match_operand:DI 1 "register_operand" "")
3124 (match_operand:DI 2 "register_operand" "")))]
3129 [(set (match_operand:DI 0 "register_operand" "=r")
3130 (minus:DI (match_operand:DI 1 "register_operand" "r")
3131 (match_operand:DI 2 "register_operand" "r")))]
3133 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
3134 [(set_attr "type" "binary")
3135 (set_attr "length" "8")])
3137 (define_expand "subsi3"
3138 [(set (match_operand:SI 0 "register_operand" "")
3139 (minus:SI (match_operand:SI 1 "arith11_operand" "")
3140 (match_operand:SI 2 "register_operand" "")))]
3145 [(set (match_operand:SI 0 "register_operand" "=r,r")
3146 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
3147 (match_operand:SI 2 "register_operand" "r,r")))]
3152 [(set_attr "type" "binary,binary")
3153 (set_attr "length" "4,4")])
3156 [(set (match_operand:SI 0 "register_operand" "=r,r,q")
3157 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,S")
3158 (match_operand:SI 2 "register_operand" "r,r,r")))]
3164 [(set_attr "type" "binary,binary,move")
3165 (set_attr "length" "4,4,4")])
3167 ;; Clobbering a "register_operand" instead of a match_scratch
3168 ;; in operand3 of millicode calls avoids spilling %r1 and
3169 ;; produces better code.
3171 ;; The mulsi3 insns set up registers for the millicode call.
3172 (define_expand "mulsi3"
3173 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
3174 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
3175 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
3176 (clobber (match_dup 3))
3177 (clobber (reg:SI 26))
3178 (clobber (reg:SI 25))
3179 (clobber (reg:SI 31))])
3180 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
3184 if (TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT)
3186 rtx scratch = gen_reg_rtx (DImode);
3187 operands[1] = force_reg (SImode, operands[1]);
3188 operands[2] = force_reg (SImode, operands[2]);
3189 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
3190 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3191 gen_rtx_SUBREG (SImode, scratch, 1)));
3194 operands[3] = gen_reg_rtx (SImode);
3197 (define_insn "umulsidi3"
3198 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
3199 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
3200 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
3201 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
3203 [(set_attr "type" "fpmuldbl")
3204 (set_attr "length" "4")])
3207 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
3208 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
3209 (match_operand:DI 2 "uint32_operand" "f")))]
3210 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
3212 [(set_attr "type" "fpmuldbl")
3213 (set_attr "length" "4")])
3216 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
3217 (clobber (match_operand:SI 0 "register_operand" "=a"))
3218 (clobber (reg:SI 26))
3219 (clobber (reg:SI 25))
3220 (clobber (reg:SI 31))]
3222 "* return output_mul_insn (0, insn);"
3223 [(set_attr "type" "milli")
3224 (set (attr "length")
3226 ;; Target (or stub) within reach
3227 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
3229 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3234 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
3238 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
3239 ;; same as NO_SPACE_REGS code
3240 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3242 (eq (symbol_ref "flag_pic")
3246 ;; Out of range and either PIC or PORTABLE_RUNTIME
3249 ;;; Division and mod.
3250 (define_expand "divsi3"
3251 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
3252 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
3253 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
3254 (clobber (match_dup 3))
3255 (clobber (match_dup 4))
3256 (clobber (reg:SI 26))
3257 (clobber (reg:SI 25))
3258 (clobber (reg:SI 31))])
3259 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
3263 operands[3] = gen_reg_rtx (SImode);
3264 operands[4] = gen_reg_rtx (SImode);
3265 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
3271 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
3272 (clobber (match_operand:SI 1 "register_operand" "=a"))
3273 (clobber (match_operand:SI 2 "register_operand" "=&r"))
3274 (clobber (reg:SI 26))
3275 (clobber (reg:SI 25))
3276 (clobber (reg:SI 31))]
3279 return output_div_insn (operands, 0, insn);"
3280 [(set_attr "type" "milli")
3281 (set (attr "length")
3283 ;; Target (or stub) within reach
3284 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
3286 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3291 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
3295 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
3296 ;; same as NO_SPACE_REGS code
3297 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3299 (eq (symbol_ref "flag_pic")
3303 ;; Out of range and either PIC or PORTABLE_RUNTIME
3306 (define_expand "udivsi3"
3307 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
3308 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
3309 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
3310 (clobber (match_dup 3))
3311 (clobber (match_dup 4))
3312 (clobber (reg:SI 26))
3313 (clobber (reg:SI 25))
3314 (clobber (reg:SI 31))])
3315 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
3319 operands[3] = gen_reg_rtx (SImode);
3320 operands[4] = gen_reg_rtx (SImode);
3321 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
3327 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
3328 (clobber (match_operand:SI 1 "register_operand" "=a"))
3329 (clobber (match_operand:SI 2 "register_operand" "=&r"))
3330 (clobber (reg:SI 26))
3331 (clobber (reg:SI 25))
3332 (clobber (reg:SI 31))]
3335 return output_div_insn (operands, 1, insn);"
3336 [(set_attr "type" "milli")
3337 (set (attr "length")
3339 ;; Target (or stub) within reach
3340 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
3342 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3347 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
3351 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
3352 ;; same as NO_SPACE_REGS code
3353 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3355 (eq (symbol_ref "flag_pic")
3359 ;; Out of range and either PIC or PORTABLE_RUNTIME
3362 (define_expand "modsi3"
3363 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
3364 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
3365 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
3366 (clobber (match_dup 3))
3367 (clobber (match_dup 4))
3368 (clobber (reg:SI 26))
3369 (clobber (reg:SI 25))
3370 (clobber (reg:SI 31))])
3371 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
3375 operands[4] = gen_reg_rtx (SImode);
3376 operands[3] = gen_reg_rtx (SImode);
3380 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
3381 (clobber (match_operand:SI 0 "register_operand" "=a"))
3382 (clobber (match_operand:SI 2 "register_operand" "=&r"))
3383 (clobber (reg:SI 26))
3384 (clobber (reg:SI 25))
3385 (clobber (reg:SI 31))]
3388 return output_mod_insn (0, insn);"
3389 [(set_attr "type" "milli")
3390 (set (attr "length")
3392 ;; Target (or stub) within reach
3393 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
3395 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3400 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
3404 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
3405 ;; same as NO_SPACE_REGS code
3406 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3408 (eq (symbol_ref "flag_pic")
3412 ;; Out of range and either PIC or PORTABLE_RUNTIME
3415 (define_expand "umodsi3"
3416 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
3417 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
3418 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
3419 (clobber (match_dup 3))
3420 (clobber (match_dup 4))
3421 (clobber (reg:SI 26))
3422 (clobber (reg:SI 25))
3423 (clobber (reg:SI 31))])
3424 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
3428 operands[4] = gen_reg_rtx (SImode);
3429 operands[3] = gen_reg_rtx (SImode);
3433 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
3434 (clobber (match_operand:SI 0 "register_operand" "=a"))
3435 (clobber (match_operand:SI 2 "register_operand" "=&r"))
3436 (clobber (reg:SI 26))
3437 (clobber (reg:SI 25))
3438 (clobber (reg:SI 31))]
3441 return output_mod_insn (1, insn);"
3442 [(set_attr "type" "milli")
3443 (set (attr "length")
3445 ;; Target (or stub) within reach
3446 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
3448 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3453 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
3457 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
3458 ;; same as NO_SPACE_REGS code
3459 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
3461 (eq (symbol_ref "flag_pic")
3465 ;; Out of range and either PIC or PORTABLE_RUNTIME
3468 ;;- and instructions
3469 ;; We define DImode `and` so with DImode `not` we can get
3470 ;; DImode `andn`. Other combinations are possible.
3472 (define_expand "anddi3"
3473 [(set (match_operand:DI 0 "register_operand" "")
3474 (and:DI (match_operand:DI 1 "arith_double_operand" "")
3475 (match_operand:DI 2 "arith_double_operand" "")))]
3479 if (! register_operand (operands[1], DImode)
3480 || ! register_operand (operands[2], DImode))
3481 /* Let GCC break this into word-at-a-time operations. */
3486 [(set (match_operand:DI 0 "register_operand" "=r")
3487 (and:DI (match_operand:DI 1 "register_operand" "%r")
3488 (match_operand:DI 2 "register_operand" "r")))]
3490 "and %1,%2,%0\;and %R1,%R2,%R0"
3491 [(set_attr "type" "binary")
3492 (set_attr "length" "8")])
3494 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
3495 ; constant with ldil;ldo.
3496 (define_insn "andsi3"
3497 [(set (match_operand:SI 0 "register_operand" "=r,r")
3498 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
3499 (match_operand:SI 2 "and_operand" "rO,P")))]
3501 "* return output_and (operands); "
3502 [(set_attr "type" "binary,shift")
3503 (set_attr "length" "4,4")])
3506 [(set (match_operand:DI 0 "register_operand" "=r")
3507 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
3508 (match_operand:DI 2 "register_operand" "r")))]
3510 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
3511 [(set_attr "type" "binary")
3512 (set_attr "length" "8")])
3515 [(set (match_operand:SI 0 "register_operand" "=r")
3516 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3517 (match_operand:SI 2 "register_operand" "r")))]
3520 [(set_attr "type" "binary")
3521 (set_attr "length" "4")])
3523 (define_expand "iordi3"
3524 [(set (match_operand:DI 0 "register_operand" "")
3525 (ior:DI (match_operand:DI 1 "arith_double_operand" "")
3526 (match_operand:DI 2 "arith_double_operand" "")))]
3530 if (! register_operand (operands[1], DImode)
3531 || ! register_operand (operands[2], DImode))
3532 /* Let GCC break this into word-at-a-time operations. */
3537 [(set (match_operand:DI 0 "register_operand" "=r")
3538 (ior:DI (match_operand:DI 1 "register_operand" "%r")
3539 (match_operand:DI 2 "register_operand" "r")))]
3541 "or %1,%2,%0\;or %R1,%R2,%R0"
3542 [(set_attr "type" "binary")
3543 (set_attr "length" "8")])
3545 ;; Need a define_expand because we've run out of CONST_OK... characters.
3546 (define_expand "iorsi3"
3547 [(set (match_operand:SI 0 "register_operand" "")
3548 (ior:SI (match_operand:SI 1 "register_operand" "")
3549 (match_operand:SI 2 "arith32_operand" "")))]
3553 if (! (ior_operand (operands[2], SImode)
3554 || register_operand (operands[2], SImode)))
3555 operands[2] = force_reg (SImode, operands[2]);
3559 [(set (match_operand:SI 0 "register_operand" "=r,r")
3560 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
3561 (match_operand:SI 2 "ior_operand" "M,i")))]
3563 "* return output_ior (operands); "
3564 [(set_attr "type" "binary,shift")
3565 (set_attr "length" "4,4")])
3568 [(set (match_operand:SI 0 "register_operand" "=r")
3569 (ior:SI (match_operand:SI 1 "register_operand" "%r")
3570 (match_operand:SI 2 "register_operand" "r")))]
3573 [(set_attr "type" "binary")
3574 (set_attr "length" "4")])
3576 (define_expand "xordi3"
3577 [(set (match_operand:DI 0 "register_operand" "")
3578 (xor:DI (match_operand:DI 1 "arith_double_operand" "")
3579 (match_operand:DI 2 "arith_double_operand" "")))]
3583 if (! register_operand (operands[1], DImode)
3584 || ! register_operand (operands[2], DImode))
3585 /* Let GCC break this into word-at-a-time operations. */
3590 [(set (match_operand:DI 0 "register_operand" "=r")
3591 (xor:DI (match_operand:DI 1 "register_operand" "%r")
3592 (match_operand:DI 2 "register_operand" "r")))]
3594 "xor %1,%2,%0\;xor %R1,%R2,%R0"
3595 [(set_attr "type" "binary")
3596 (set_attr "length" "8")])
3598 (define_insn "xorsi3"
3599 [(set (match_operand:SI 0 "register_operand" "=r")
3600 (xor:SI (match_operand:SI 1 "register_operand" "%r")
3601 (match_operand:SI 2 "register_operand" "r")))]
3604 [(set_attr "type" "binary")
3605 (set_attr "length" "4")])
3607 (define_expand "negdi2"
3608 [(set (match_operand:DI 0 "register_operand" "")
3609 (neg:DI (match_operand:DI 1 "register_operand" "")))]
3614 [(set (match_operand:DI 0 "register_operand" "=r")
3615 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
3617 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
3618 [(set_attr "type" "unary")
3619 (set_attr "length" "8")])
3621 (define_insn "negsi2"
3622 [(set (match_operand:SI 0 "register_operand" "=r")
3623 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
3626 [(set_attr "type" "unary")
3627 (set_attr "length" "4")])
3629 (define_expand "one_cmpldi2"
3630 [(set (match_operand:DI 0 "register_operand" "")
3631 (not:DI (match_operand:DI 1 "arith_double_operand" "")))]
3635 if (! register_operand (operands[1], DImode))
3640 [(set (match_operand:DI 0 "register_operand" "=r")
3641 (not:DI (match_operand:DI 1 "register_operand" "r")))]
3643 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
3644 [(set_attr "type" "unary")
3645 (set_attr "length" "8")])
3647 (define_insn "one_cmplsi2"
3648 [(set (match_operand:SI 0 "register_operand" "=r")
3649 (not:SI (match_operand:SI 1 "register_operand" "r")))]
3652 [(set_attr "type" "unary")
3653 (set_attr "length" "4")])
3655 ;; Floating point arithmetic instructions.
3657 (define_insn "adddf3"
3658 [(set (match_operand:DF 0 "register_operand" "=f")
3659 (plus:DF (match_operand:DF 1 "register_operand" "f")
3660 (match_operand:DF 2 "register_operand" "f")))]
3661 "! TARGET_SOFT_FLOAT"
3663 [(set_attr "type" "fpalu")
3664 (set_attr "pa_combine_type" "faddsub")
3665 (set_attr "length" "4")])
3667 (define_insn "addsf3"
3668 [(set (match_operand:SF 0 "register_operand" "=f")
3669 (plus:SF (match_operand:SF 1 "register_operand" "f")
3670 (match_operand:SF 2 "register_operand" "f")))]
3671 "! TARGET_SOFT_FLOAT"
3673 [(set_attr "type" "fpalu")
3674 (set_attr "pa_combine_type" "faddsub")
3675 (set_attr "length" "4")])
3677 (define_insn "subdf3"
3678 [(set (match_operand:DF 0 "register_operand" "=f")
3679 (minus:DF (match_operand:DF 1 "register_operand" "f")
3680 (match_operand:DF 2 "register_operand" "f")))]
3681 "! TARGET_SOFT_FLOAT"
3683 [(set_attr "type" "fpalu")
3684 (set_attr "pa_combine_type" "faddsub")
3685 (set_attr "length" "4")])
3687 (define_insn "subsf3"
3688 [(set (match_operand:SF 0 "register_operand" "=f")
3689 (minus:SF (match_operand:SF 1 "register_operand" "f")
3690 (match_operand:SF 2 "register_operand" "f")))]
3691 "! TARGET_SOFT_FLOAT"
3693 [(set_attr "type" "fpalu")
3694 (set_attr "pa_combine_type" "faddsub")
3695 (set_attr "length" "4")])
3697 (define_insn "muldf3"
3698 [(set (match_operand:DF 0 "register_operand" "=f")
3699 (mult:DF (match_operand:DF 1 "register_operand" "f")
3700 (match_operand:DF 2 "register_operand" "f")))]
3701 "! TARGET_SOFT_FLOAT"
3703 [(set_attr "type" "fpmuldbl")
3704 (set_attr "pa_combine_type" "fmpy")
3705 (set_attr "length" "4")])
3707 (define_insn "mulsf3"
3708 [(set (match_operand:SF 0 "register_operand" "=f")
3709 (mult:SF (match_operand:SF 1 "register_operand" "f")
3710 (match_operand:SF 2 "register_operand" "f")))]
3711 "! TARGET_SOFT_FLOAT"
3713 [(set_attr "type" "fpmulsgl")
3714 (set_attr "pa_combine_type" "fmpy")
3715 (set_attr "length" "4")])
3717 (define_insn "divdf3"
3718 [(set (match_operand:DF 0 "register_operand" "=f")
3719 (div:DF (match_operand:DF 1 "register_operand" "f")
3720 (match_operand:DF 2 "register_operand" "f")))]
3721 "! TARGET_SOFT_FLOAT"
3723 [(set_attr "type" "fpdivdbl")
3724 (set_attr "length" "4")])
3726 (define_insn "divsf3"
3727 [(set (match_operand:SF 0 "register_operand" "=f")
3728 (div:SF (match_operand:SF 1 "register_operand" "f")
3729 (match_operand:SF 2 "register_operand" "f")))]
3730 "! TARGET_SOFT_FLOAT"
3732 [(set_attr "type" "fpdivsgl")
3733 (set_attr "length" "4")])
3735 (define_insn "negdf2"
3736 [(set (match_operand:DF 0 "register_operand" "=f")
3737 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
3738 "! TARGET_SOFT_FLOAT"
3742 return \"fneg,dbl %1,%0\";
3744 return \"fsub,dbl %%fr0,%1,%0\";
3746 [(set_attr "type" "fpalu")
3747 (set_attr "length" "4")])
3749 (define_insn "negsf2"
3750 [(set (match_operand:SF 0 "register_operand" "=f")
3751 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
3752 "! TARGET_SOFT_FLOAT"
3756 return \"fneg,sgl %1,%0\";
3758 return \"fsub,sgl %%fr0,%1,%0\";
3760 [(set_attr "type" "fpalu")
3761 (set_attr "length" "4")])
3763 (define_insn "absdf2"
3764 [(set (match_operand:DF 0 "register_operand" "=f")
3765 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
3766 "! TARGET_SOFT_FLOAT"
3768 [(set_attr "type" "fpalu")
3769 (set_attr "length" "4")])
3771 (define_insn "abssf2"
3772 [(set (match_operand:SF 0 "register_operand" "=f")
3773 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
3774 "! TARGET_SOFT_FLOAT"
3776 [(set_attr "type" "fpalu")
3777 (set_attr "length" "4")])
3779 (define_insn "sqrtdf2"
3780 [(set (match_operand:DF 0 "register_operand" "=f")
3781 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
3782 "! TARGET_SOFT_FLOAT"
3784 [(set_attr "type" "fpsqrtdbl")
3785 (set_attr "length" "4")])
3787 (define_insn "sqrtsf2"
3788 [(set (match_operand:SF 0 "register_operand" "=f")
3789 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
3790 "! TARGET_SOFT_FLOAT"
3792 [(set_attr "type" "fpsqrtsgl")
3793 (set_attr "length" "4")])
3795 ;; PA 2.0 floating point instructions
3799 [(set (match_operand:DF 0 "register_operand" "=f")
3800 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
3801 (match_operand:DF 2 "register_operand" "f"))
3802 (match_operand:DF 3 "register_operand" "f")))]
3803 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
3804 "fmpyfadd,dbl %1,%2,%3,%0"
3805 [(set_attr "type" "fpmuldbl")
3806 (set_attr "length" "4")])
3809 [(set (match_operand:DF 0 "register_operand" "=f")
3810 (plus:DF (match_operand:DF 1 "register_operand" "f")
3811 (mult:DF (match_operand:DF 2 "register_operand" "f")
3812 (match_operand:DF 3 "register_operand" "f"))))]
3813 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
3814 "fmpyfadd,dbl %2,%3,%1,%0"
3815 [(set_attr "type" "fpmuldbl")
3816 (set_attr "length" "4")])
3819 [(set (match_operand:SF 0 "register_operand" "=f")
3820 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
3821 (match_operand:SF 2 "register_operand" "f"))
3822 (match_operand:SF 3 "register_operand" "f")))]
3823 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
3824 "fmpyfadd,sgl %1,%2,%3,%0"
3825 [(set_attr "type" "fpmulsgl")
3826 (set_attr "length" "4")])
3829 [(set (match_operand:SF 0 "register_operand" "=f")
3830 (plus:SF (match_operand:SF 1 "register_operand" "f")
3831 (mult:SF (match_operand:SF 2 "register_operand" "f")
3832 (match_operand:SF 3 "register_operand" "f"))))]
3833 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
3834 "fmpyfadd,sgl %2,%3,%1,%0"
3835 [(set_attr "type" "fpmulsgl")
3836 (set_attr "length" "4")])
3838 ; fmpynfadd patterns
3840 [(set (match_operand:DF 0 "register_operand" "=f")
3841 (minus:DF (match_operand:DF 1 "register_operand" "f")
3842 (mult:DF (match_operand:DF 2 "register_operand" "f")
3843 (match_operand:DF 3 "register_operand" "f"))))]
3844 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
3845 "fmpynfadd,dbl %2,%3,%1,%0"
3846 [(set_attr "type" "fpmuldbl")
3847 (set_attr "length" "4")])
3850 [(set (match_operand:SF 0 "register_operand" "=f")
3851 (minus:SF (match_operand:SF 1 "register_operand" "f")
3852 (mult:SF (match_operand:SF 2 "register_operand" "f")
3853 (match_operand:SF 3 "register_operand" "f"))))]
3854 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
3855 "fmpynfadd,sgl %2,%3,%1,%0"
3856 [(set_attr "type" "fpmulsgl")
3857 (set_attr "length" "4")])
3861 [(set (match_operand:DF 0 "register_operand" "=f")
3862 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
3863 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
3865 [(set_attr "type" "fpalu")
3866 (set_attr "length" "4")])
3869 [(set (match_operand:SF 0 "register_operand" "=f")
3870 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
3871 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
3873 [(set_attr "type" "fpalu")
3874 (set_attr "length" "4")])
3876 ;; Generating a fused multiply sequence is a win for this case as it will
3877 ;; reduce the latency for the fused case without impacting the plain
3880 ;; Similar possibilities exist for fnegabs, shadd and other insns which
3881 ;; perform two operations with the result of the first feeding the second.
3883 [(set (match_operand:DF 0 "register_operand" "=f")
3884 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
3885 (match_operand:DF 2 "register_operand" "f"))
3886 (match_operand:DF 3 "register_operand" "f")))
3887 (set (match_operand:DF 4 "register_operand" "=&f")
3888 (mult:DF (match_dup 1) (match_dup 2)))]
3889 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
3890 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
3891 || reg_overlap_mentioned_p (operands[4], operands[2])))"
3893 [(set_attr "type" "fpmuldbl")
3894 (set_attr "length" "8")])
3896 ;; We want to split this up during scheduling since we want both insns
3897 ;; to schedule independently.
3899 [(set (match_operand:DF 0 "register_operand" "=f")
3900 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
3901 (match_operand:DF 2 "register_operand" "f"))
3902 (match_operand:DF 3 "register_operand" "f")))
3903 (set (match_operand:DF 4 "register_operand" "=&f")
3904 (mult:DF (match_dup 1) (match_dup 2)))]
3905 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3906 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
3907 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
3912 [(set (match_operand:SF 0 "register_operand" "=f")
3913 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
3914 (match_operand:SF 2 "register_operand" "f"))
3915 (match_operand:SF 3 "register_operand" "f")))
3916 (set (match_operand:SF 4 "register_operand" "=&f")
3917 (mult:SF (match_dup 1) (match_dup 2)))]
3918 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
3919 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
3920 || reg_overlap_mentioned_p (operands[4], operands[2])))"
3922 [(set_attr "type" "fpmuldbl")
3923 (set_attr "length" "8")])
3925 ;; We want to split this up during scheduling since we want both insns
3926 ;; to schedule independently.
3928 [(set (match_operand:SF 0 "register_operand" "=f")
3929 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
3930 (match_operand:SF 2 "register_operand" "f"))
3931 (match_operand:SF 3 "register_operand" "f")))
3932 (set (match_operand:SF 4 "register_operand" "=&f")
3933 (mult:SF (match_dup 1) (match_dup 2)))]
3934 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3935 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
3936 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
3940 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
3943 [(set (match_operand:DF 0 "register_operand" "=f")
3944 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
3945 (match_operand:DF 2 "register_operand" "f"))))]
3946 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3947 "fmpynfadd,dbl %1,%2,%%fr0,%0"
3948 [(set_attr "type" "fpmuldbl")
3949 (set_attr "length" "4")])
3952 [(set (match_operand:SF 0 "register_operand" "=f")
3953 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
3954 (match_operand:SF 2 "register_operand" "f"))))]
3955 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3956 "fmpynfadd,sgl %1,%2,%%fr0,%0"
3957 [(set_attr "type" "fpmuldbl")
3958 (set_attr "length" "4")])
3961 [(set (match_operand:DF 0 "register_operand" "=f")
3962 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
3963 (match_operand:DF 2 "register_operand" "f"))))
3964 (set (match_operand:DF 3 "register_operand" "=&f")
3965 (mult:DF (match_dup 1) (match_dup 2)))]
3966 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
3967 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
3968 || reg_overlap_mentioned_p (operands[3], operands[2])))"
3970 [(set_attr "type" "fpmuldbl")
3971 (set_attr "length" "8")])
3974 [(set (match_operand:DF 0 "register_operand" "=f")
3975 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
3976 (match_operand:DF 2 "register_operand" "f"))))
3977 (set (match_operand:DF 3 "register_operand" "=&f")
3978 (mult:DF (match_dup 1) (match_dup 2)))]
3979 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3980 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
3981 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
3985 [(set (match_operand:SF 0 "register_operand" "=f")
3986 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
3987 (match_operand:SF 2 "register_operand" "f"))))
3988 (set (match_operand:SF 3 "register_operand" "=&f")
3989 (mult:SF (match_dup 1) (match_dup 2)))]
3990 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
3991 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
3992 || reg_overlap_mentioned_p (operands[3], operands[2])))"
3994 [(set_attr "type" "fpmuldbl")
3995 (set_attr "length" "8")])
3998 [(set (match_operand:SF 0 "register_operand" "=f")
3999 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4000 (match_operand:SF 2 "register_operand" "f"))))
4001 (set (match_operand:SF 3 "register_operand" "=&f")
4002 (mult:SF (match_dup 1) (match_dup 2)))]
4003 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4004 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
4005 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
4008 ;; Now fused multiplies with the result of the multiply negated.
4010 [(set (match_operand:DF 0 "register_operand" "=f")
4011 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4012 (match_operand:DF 2 "register_operand" "f")))
4013 (match_operand:DF 3 "register_operand" "f")))]
4014 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4015 "fmpynfadd,dbl %1,%2,%3,%0"
4016 [(set_attr "type" "fpmuldbl")
4017 (set_attr "length" "4")])
4020 [(set (match_operand:SF 0 "register_operand" "=f")
4021 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4022 (match_operand:SF 2 "register_operand" "f")))
4023 (match_operand:SF 3 "register_operand" "f")))]
4024 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4025 "fmpynfadd,sgl %1,%2,%3,%0"
4026 [(set_attr "type" "fpmuldbl")
4027 (set_attr "length" "4")])
4030 [(set (match_operand:DF 0 "register_operand" "=f")
4031 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4032 (match_operand:DF 2 "register_operand" "f")))
4033 (match_operand:DF 3 "register_operand" "f")))
4034 (set (match_operand:DF 4 "register_operand" "=&f")
4035 (mult:DF (match_dup 1) (match_dup 2)))]
4036 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4037 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4038 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4040 [(set_attr "type" "fpmuldbl")
4041 (set_attr "length" "8")])
4044 [(set (match_operand:DF 0 "register_operand" "=f")
4045 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4046 (match_operand:DF 2 "register_operand" "f")))
4047 (match_operand:DF 3 "register_operand" "f")))
4048 (set (match_operand:DF 4 "register_operand" "=&f")
4049 (mult:DF (match_dup 1) (match_dup 2)))]
4050 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4051 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
4052 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
4057 [(set (match_operand:SF 0 "register_operand" "=f")
4058 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4059 (match_operand:SF 2 "register_operand" "f")))
4060 (match_operand:SF 3 "register_operand" "f")))
4061 (set (match_operand:SF 4 "register_operand" "=&f")
4062 (mult:SF (match_dup 1) (match_dup 2)))]
4063 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4064 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4065 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4067 [(set_attr "type" "fpmuldbl")
4068 (set_attr "length" "8")])
4071 [(set (match_operand:SF 0 "register_operand" "=f")
4072 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4073 (match_operand:SF 2 "register_operand" "f")))
4074 (match_operand:SF 3 "register_operand" "f")))
4075 (set (match_operand:SF 4 "register_operand" "=&f")
4076 (mult:SF (match_dup 1) (match_dup 2)))]
4077 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4078 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
4079 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
4084 [(set (match_operand:DF 0 "register_operand" "=f")
4085 (minus:DF (match_operand:DF 3 "register_operand" "f")
4086 (mult:DF (match_operand:DF 1 "register_operand" "f")
4087 (match_operand:DF 2 "register_operand" "f"))))
4088 (set (match_operand:DF 4 "register_operand" "=&f")
4089 (mult:DF (match_dup 1) (match_dup 2)))]
4090 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4091 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4092 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4094 [(set_attr "type" "fpmuldbl")
4095 (set_attr "length" "8")])
4098 [(set (match_operand:DF 0 "register_operand" "=f")
4099 (minus:DF (match_operand:DF 3 "register_operand" "f")
4100 (mult:DF (match_operand:DF 1 "register_operand" "f")
4101 (match_operand:DF 2 "register_operand" "f"))))
4102 (set (match_operand:DF 4 "register_operand" "=&f")
4103 (mult:DF (match_dup 1) (match_dup 2)))]
4104 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4105 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
4106 (set (match_dup 0) (minus:DF (match_dup 3)
4107 (mult:DF (match_dup 1) (match_dup 2))))]
4111 [(set (match_operand:SF 0 "register_operand" "=f")
4112 (minus:SF (match_operand:SF 3 "register_operand" "f")
4113 (mult:SF (match_operand:SF 1 "register_operand" "f")
4114 (match_operand:SF 2 "register_operand" "f"))))
4115 (set (match_operand:SF 4 "register_operand" "=&f")
4116 (mult:SF (match_dup 1) (match_dup 2)))]
4117 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4118 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4119 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4121 [(set_attr "type" "fpmuldbl")
4122 (set_attr "length" "8")])
4125 [(set (match_operand:SF 0 "register_operand" "=f")
4126 (minus:SF (match_operand:SF 3 "register_operand" "f")
4127 (mult:SF (match_operand:SF 1 "register_operand" "f")
4128 (match_operand:SF 2 "register_operand" "f"))))
4129 (set (match_operand:SF 4 "register_operand" "=&f")
4130 (mult:SF (match_dup 1) (match_dup 2)))]
4131 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4132 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
4133 (set (match_dup 0) (minus:SF (match_dup 3)
4134 (mult:SF (match_dup 1) (match_dup 2))))]
4138 [(set (match_operand:DF 0 "register_operand" "=f")
4139 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
4140 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
4141 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4142 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
4144 [(set_attr "type" "fpalu")
4145 (set_attr "length" "8")])
4148 [(set (match_operand:DF 0 "register_operand" "=f")
4149 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
4150 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
4151 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4152 [(set (match_dup 2) (abs:DF (match_dup 1)))
4153 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
4157 [(set (match_operand:SF 0 "register_operand" "=f")
4158 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
4159 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
4160 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4161 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
4163 [(set_attr "type" "fpalu")
4164 (set_attr "length" "8")])
4167 [(set (match_operand:SF 0 "register_operand" "=f")
4168 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
4169 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
4170 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4171 [(set (match_dup 2) (abs:SF (match_dup 1)))
4172 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
4175 ;;- Shift instructions
4177 ;; Optimized special case of shifting.
4180 [(set (match_operand:SI 0 "register_operand" "=r")
4181 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4185 [(set_attr "type" "load")
4186 (set_attr "length" "4")])
4189 [(set (match_operand:SI 0 "register_operand" "=r")
4190 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4194 [(set_attr "type" "load")
4195 (set_attr "length" "4")])
4198 [(set (match_operand:SI 0 "register_operand" "=r")
4199 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
4200 (match_operand:SI 3 "shadd_operand" ""))
4201 (match_operand:SI 1 "register_operand" "r")))]
4203 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
4204 [(set_attr "type" "binary")
4205 (set_attr "length" "4")])
4207 ;; This anonymous pattern and splitter wins because it reduces the latency
4208 ;; of the shadd sequence without increasing the latency of the shift.
4210 ;; We want to make sure and split up the operations for the scheduler since
4211 ;; these instructions can (and should) schedule independently.
4213 ;; It would be clearer if combine used the same operator for both expressions,
4214 ;; it's somewhat confusing to have a mult in ine operation and an ashift
4217 ;; If this pattern is not split before register allocation, then we must expose
4218 ;; the fact that operand 4 is set before operands 1, 2 and 3 have been read.
4220 [(set (match_operand:SI 0 "register_operand" "=r")
4221 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
4222 (match_operand:SI 3 "shadd_operand" ""))
4223 (match_operand:SI 1 "register_operand" "r")))
4224 (set (match_operand:SI 4 "register_operand" "=&r")
4225 (ashift:SI (match_dup 2)
4226 (match_operand:SI 5 "const_int_operand" "i")))]
4227 "(INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))
4228 && ! (reg_overlap_mentioned_p (operands[4], operands[2])))"
4230 [(set_attr "type" "binary")
4231 (set_attr "length" "8")])
4234 [(set (match_operand:SI 0 "register_operand" "=r")
4235 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
4236 (match_operand:SI 3 "shadd_operand" ""))
4237 (match_operand:SI 1 "register_operand" "r")))
4238 (set (match_operand:SI 4 "register_operand" "=&r")
4239 (ashift:SI (match_dup 2)
4240 (match_operand:SI 5 "const_int_operand" "i")))]
4241 "INTVAL (operands[5]) == exact_log2 (INTVAL (operands[3]))"
4242 [(set (match_dup 4) (ashift:SI (match_dup 2) (match_dup 5)))
4243 (set (match_dup 0) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4247 (define_expand "ashlsi3"
4248 [(set (match_operand:SI 0 "register_operand" "")
4249 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
4250 (match_operand:SI 2 "arith32_operand" "")))]
4254 if (GET_CODE (operands[2]) != CONST_INT)
4256 rtx temp = gen_reg_rtx (SImode);
4257 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
4258 if (GET_CODE (operands[1]) == CONST_INT)
4259 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
4261 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
4264 /* Make sure both inputs are not constants,
4265 there are no patterns for that. */
4266 operands[1] = force_reg (SImode, operands[1]);
4270 [(set (match_operand:SI 0 "register_operand" "=r")
4271 (ashift:SI (match_operand:SI 1 "register_operand" "r")
4272 (match_operand:SI 2 "const_int_operand" "n")))]
4274 "{zdep|depw,z} %1,%P2,%L2,%0"
4275 [(set_attr "type" "shift")
4276 (set_attr "length" "4")])
4278 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
4279 ; Doing it like this makes slightly better code since reload can
4280 ; replace a register with a known value in range -16..15 with a
4281 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
4282 ; but since we have no more CONST_OK... characters, that is not
4284 (define_insn "zvdep32"
4285 [(set (match_operand:SI 0 "register_operand" "=r,r")
4286 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
4287 (minus:SI (const_int 31)
4288 (match_operand:SI 2 "register_operand" "q,q"))))]
4291 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
4292 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
4293 [(set_attr "type" "shift,shift")
4294 (set_attr "length" "4,4")])
4296 (define_insn "zvdep_imm32"
4297 [(set (match_operand:SI 0 "register_operand" "=r")
4298 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
4299 (minus:SI (const_int 31)
4300 (match_operand:SI 2 "register_operand" "q"))))]
4304 int x = INTVAL (operands[1]);
4305 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
4306 operands[1] = GEN_INT ((x & 0xf) - 0x10);
4307 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
4309 [(set_attr "type" "shift")
4310 (set_attr "length" "4")])
4312 (define_insn "vdepi_ior"
4313 [(set (match_operand:SI 0 "register_operand" "=r")
4314 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
4315 (minus:SI (const_int 31)
4316 (match_operand:SI 2 "register_operand" "q")))
4317 (match_operand:SI 3 "register_operand" "0")))]
4318 ; accept ...0001...1, can this be generalized?
4319 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
4322 int x = INTVAL (operands[1]);
4323 operands[2] = GEN_INT (exact_log2 (x + 1));
4324 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
4326 [(set_attr "type" "shift")
4327 (set_attr "length" "4")])
4329 (define_insn "vdepi_and"
4330 [(set (match_operand:SI 0 "register_operand" "=r")
4331 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
4332 (minus:SI (const_int 31)
4333 (match_operand:SI 2 "register_operand" "q")))
4334 (match_operand:SI 3 "register_operand" "0")))]
4335 ; this can be generalized...!
4336 "INTVAL (operands[1]) == -2"
4339 int x = INTVAL (operands[1]);
4340 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
4341 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
4343 [(set_attr "type" "shift")
4344 (set_attr "length" "4")])
4346 (define_expand "ashrsi3"
4347 [(set (match_operand:SI 0 "register_operand" "")
4348 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
4349 (match_operand:SI 2 "arith32_operand" "")))]
4353 if (GET_CODE (operands[2]) != CONST_INT)
4355 rtx temp = gen_reg_rtx (SImode);
4356 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
4357 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
4363 [(set (match_operand:SI 0 "register_operand" "=r")
4364 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
4365 (match_operand:SI 2 "const_int_operand" "n")))]
4367 "{extrs|extrw,s} %1,%P2,%L2,%0"
4368 [(set_attr "type" "shift")
4369 (set_attr "length" "4")])
4371 (define_insn "vextrs32"
4372 [(set (match_operand:SI 0 "register_operand" "=r")
4373 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
4374 (minus:SI (const_int 31)
4375 (match_operand:SI 2 "register_operand" "q"))))]
4377 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
4378 [(set_attr "type" "shift")
4379 (set_attr "length" "4")])
4381 (define_insn "lshrsi3"
4382 [(set (match_operand:SI 0 "register_operand" "=r,r")
4383 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
4384 (match_operand:SI 2 "arith32_operand" "q,n")))]
4387 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
4388 {extru|extrw,u} %1,%P2,%L2,%0"
4389 [(set_attr "type" "shift")
4390 (set_attr "length" "4")])
4392 (define_insn "rotrsi3"
4393 [(set (match_operand:SI 0 "register_operand" "=r,r")
4394 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
4395 (match_operand:SI 2 "arith32_operand" "q,n")))]
4399 if (GET_CODE (operands[2]) == CONST_INT)
4401 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
4402 return \"{shd|shrpw} %1,%1,%2,%0\";
4405 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
4407 [(set_attr "type" "shift")
4408 (set_attr "length" "4")])
4410 (define_expand "rotlsi3"
4411 [(set (match_operand:SI 0 "register_operand" "")
4412 (rotate:SI (match_operand:SI 1 "register_operand" "")
4413 (match_operand:SI 2 "arith32_operand" "")))]
4417 if (GET_CODE (operands[2]) != CONST_INT)
4419 rtx temp = gen_reg_rtx (SImode);
4420 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
4421 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
4424 /* Else expand normally. */
4428 [(set (match_operand:SI 0 "register_operand" "=r")
4429 (rotate:SI (match_operand:SI 1 "register_operand" "r")
4430 (match_operand:SI 2 "const_int_operand" "n")))]
4434 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
4435 return \"{shd|shrpw} %1,%1,%2,%0\";
4437 [(set_attr "type" "shift")
4438 (set_attr "length" "4")])
4441 [(set (match_operand:SI 0 "register_operand" "=r")
4442 (match_operator:SI 5 "plus_xor_ior_operator"
4443 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
4444 (match_operand:SI 3 "const_int_operand" "n"))
4445 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4446 (match_operand:SI 4 "const_int_operand" "n"))]))]
4447 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
4448 "{shd|shrpw} %1,%2,%4,%0"
4449 [(set_attr "type" "shift")
4450 (set_attr "length" "4")])
4453 [(set (match_operand:SI 0 "register_operand" "=r")
4454 (match_operator:SI 5 "plus_xor_ior_operator"
4455 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
4456 (match_operand:SI 4 "const_int_operand" "n"))
4457 (ashift:SI (match_operand:SI 1 "register_operand" "r")
4458 (match_operand:SI 3 "const_int_operand" "n"))]))]
4459 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
4460 "{shd|shrpw} %1,%2,%4,%0"
4461 [(set_attr "type" "shift")
4462 (set_attr "length" "4")])
4465 [(set (match_operand:SI 0 "register_operand" "=r")
4466 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4467 (match_operand:SI 2 "const_int_operand" ""))
4468 (match_operand:SI 3 "const_int_operand" "")))]
4469 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
4472 int cnt = INTVAL (operands[2]) & 31;
4473 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
4474 operands[2] = GEN_INT (31 - cnt);
4475 return \"{zdep|depw,z} %1,%2,%3,%0\";
4477 [(set_attr "type" "shift")
4478 (set_attr "length" "4")])
4480 ;; Unconditional and other jump instructions.
4482 (define_insn "return"
4484 "hppa_can_use_return_insn_p ()"
4488 return \"bve%* (%%r2)\";
4489 return \"bv%* %%r0(%%r2)\";
4491 [(set_attr "type" "branch")
4492 (set_attr "length" "4")])
4494 ;; Use a different pattern for functions which have non-trivial
4495 ;; epilogues so as not to confuse jump and reorg.
4496 (define_insn "return_internal"
4503 return \"bve%* (%%r2)\";
4504 return \"bv%* %%r0(%%r2)\";
4506 [(set_attr "type" "branch")
4507 (set_attr "length" "4")])
4509 (define_expand "prologue"
4512 "hppa_expand_prologue ();DONE;")
4514 (define_expand "epilogue"
4519 /* Try to use the trivial return first. Else use the full
4521 if (hppa_can_use_return_insn_p ())
4522 emit_jump_insn (gen_return ());
4525 hppa_expand_epilogue ();
4526 emit_jump_insn (gen_return_internal ());
4531 ;; Special because we use the value placed in %r2 by the bl instruction
4532 ;; from within its delay slot to set the value for the 2nd parameter to
4534 (define_insn "call_profiler"
4535 [(unspec_volatile [(const_int 0)] 0)
4536 (use (match_operand:SI 0 "const_int_operand" ""))]
4538 "{bl|b,l} _mcount,%%r2\;ldo %0(%%r2),%%r25"
4539 [(set_attr "type" "multi")
4540 (set_attr "length" "8")])
4542 (define_insn "blockage"
4543 [(unspec_volatile [(const_int 2)] 0)]
4546 [(set_attr "length" "0")])
4549 [(set (pc) (label_ref (match_operand 0 "" "")))]
4553 extern int optimize;
4555 if (GET_MODE (insn) == SImode)
4558 /* An unconditional branch which can reach its target. */
4559 if (get_attr_length (insn) != 24
4560 && get_attr_length (insn) != 16)
4563 /* An unconditional branch which can not reach its target.
4565 We need to be able to use %r1 as a scratch register; however,
4566 we can never be sure whether or not it's got a live value in
4567 it. Therefore, we must restore its original value after the
4570 To make matters worse, we don't have a stack slot which we
4571 can always clobber. sp-12/sp-16 shouldn't ever have a live
4572 value during a non-optimizing compilation, so we use those
4573 slots for now. We don't support very long branches when
4574 optimizing -- they should be quite rare when optimizing.
4576 Really the way to go long term is a register scavenger; goto
4577 the target of the jump and find a register which we can use
4578 as a scratch to hold the value in %r1. */
4580 /* We don't know how to register scavenge yet. */
4584 /* First store %r1 into the stack. */
4585 output_asm_insn (\"stw %%r1,-16(%%r30)\", operands);
4587 /* Now load the target address into %r1 and do an indirect jump
4588 to the value specified in %r1. Be careful to generate PIC
4593 xoperands[0] = operands[0];
4594 xoperands[1] = gen_label_rtx ();
4596 output_asm_insn (\"{bl|b,l} .+8,%%r1\\n\\taddil L'%l0-%l1,%%r1\",
4598 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
4599 CODE_LABEL_NUMBER (xoperands[1]));
4600 output_asm_insn (\"ldo R'%l0-%l1(%%r1),%%r1\\n\\tbv %%r0(%%r1)\",
4604 output_asm_insn (\"ldil L'%l0,%%r1\\n\\tbe R'%l0(%%sr4,%%r1)\", operands);;
4606 /* And restore the value of %r1 in the delay slot. We're not optimizing,
4607 so we know nothing else can be in the delay slot. */
4608 return \"ldw -16(%%r30),%%r1\";
4610 [(set_attr "type" "uncond_branch")
4611 (set_attr "pa_combine_type" "uncond_branch")
4612 (set (attr "length")
4613 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
4614 (if_then_else (lt (abs (minus (match_dup 0)
4615 (plus (pc) (const_int 8))))
4619 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
4621 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
4626 ;; Subroutines of "casesi".
4627 ;; operand 0 is index
4628 ;; operand 1 is the minimum bound
4629 ;; operand 2 is the maximum bound - minimum bound + 1
4630 ;; operand 3 is CODE_LABEL for the table;
4631 ;; operand 4 is the CODE_LABEL to go to if index out of range.
4633 (define_expand "casesi"
4634 [(match_operand:SI 0 "general_operand" "")
4635 (match_operand:SI 1 "const_int_operand" "")
4636 (match_operand:SI 2 "const_int_operand" "")
4637 (match_operand 3 "" "")
4638 (match_operand 4 "" "")]
4642 if (GET_CODE (operands[0]) != REG)
4643 operands[0] = force_reg (SImode, operands[0]);
4645 if (operands[1] != const0_rtx)
4647 rtx reg = gen_reg_rtx (SImode);
4649 operands[1] = GEN_INT (-INTVAL (operands[1]));
4650 if (!INT_14_BITS (operands[1]))
4651 operands[1] = force_reg (SImode, operands[1]);
4652 emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
4657 if (!INT_5_BITS (operands[2]))
4658 operands[2] = force_reg (SImode, operands[2]);
4660 emit_insn (gen_cmpsi (operands[0], operands[2]));
4661 emit_jump_insn (gen_bgtu (operands[4]));
4662 if (TARGET_BIG_SWITCH)
4664 rtx temp = gen_reg_rtx (SImode);
4665 emit_move_insn (temp, gen_rtx_PLUS (SImode, operands[0], operands[0]));
4668 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
4672 (define_insn "casesi0"
4674 (mem:SI (plus:SI (pc)
4675 (match_operand:SI 0 "register_operand" "r")))
4676 (label_ref (match_operand 1 "" ""))))]
4679 [(set_attr "type" "multi")
4680 (set_attr "length" "8")])
4682 ;; Need nops for the calls because execution is supposed to continue
4683 ;; past; we don't want to nullify an instruction that we need.
4684 ;;- jump to subroutine
4686 (define_expand "call"
4687 [(parallel [(call (match_operand:SI 0 "" "")
4688 (match_operand 1 "" ""))
4689 (clobber (reg:SI 2))])]
4696 if (TARGET_PORTABLE_RUNTIME)
4697 op = force_reg (SImode, XEXP (operands[0], 0));
4699 op = XEXP (operands[0], 0);
4701 /* Use two different patterns for calls to explicitly named functions
4702 and calls through function pointers. This is necessary as these two
4703 types of calls use different calling conventions, and CSE might try
4704 to change the named call into an indirect call in some cases (using
4705 two patterns keeps CSE from performing this optimization). */
4706 if (GET_CODE (op) == SYMBOL_REF)
4707 call_insn = emit_call_insn (gen_call_internal_symref (op, operands[1]));
4710 rtx tmpreg = gen_rtx_REG (word_mode, 22);
4711 emit_move_insn (tmpreg, force_reg (word_mode, op));
4712 call_insn = emit_call_insn (gen_call_internal_reg (operands[1]));
4717 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
4718 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
4719 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
4721 /* After each call we must restore the PIC register, even if it
4722 doesn't appear to be used.
4724 This will set regs_ever_live for the callee saved register we
4725 stored the PIC register in. */
4726 emit_move_insn (pic_offset_table_rtx,
4727 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
4732 (define_insn "call_internal_symref"
4733 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
4734 (match_operand 1 "" "i"))
4735 (clobber (reg:SI 2))
4736 (use (const_int 0))]
4737 "! TARGET_PORTABLE_RUNTIME"
4740 output_arg_descriptor (insn);
4741 return output_call (insn, operands[0]);
4743 [(set_attr "type" "call")
4744 (set (attr "length")
4745 ;; If we're sure that we can either reach the target or that the
4746 ;; linker can use a long-branch stub, then the length is 4 bytes.
4748 ;; For long-calls the length will be either 52 bytes (non-pic)
4749 ;; or 68 bytes (pic). */
4750 ;; Else we have to use a long-call;
4751 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
4754 (if_then_else (eq (symbol_ref "flag_pic")
4759 (define_insn "call_internal_reg"
4760 [(call (mem:SI (reg:SI 22))
4761 (match_operand 0 "" "i"))
4762 (clobber (reg:SI 2))
4763 (use (const_int 1))]
4769 /* First the special case for kernels, level 0 systems, etc. */
4770 if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS)
4771 return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\";
4773 /* Now the normal case -- we can reach $$dyncall directly or
4774 we're sure that we can get there via a long-branch stub.
4776 No need to check target flags as the length uniquely identifies
4777 the remaining cases. */
4778 if (get_attr_length (insn) == 8)
4779 return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\";
4781 /* Long millicode call, but we are not generating PIC or portable runtime
4783 if (get_attr_length (insn) == 12)
4784 return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\";
4786 /* Long millicode call for portable runtime. */
4787 if (get_attr_length (insn) == 20)
4788 return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr %%r0,%%r2\;bv,n %%r0(%%r31)\;nop\";
4790 /* If we're generating PIC code. */
4791 xoperands[0] = operands[0];
4792 xoperands[1] = gen_label_rtx ();
4793 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
4794 output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
4795 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
4796 CODE_LABEL_NUMBER (xoperands[1]));
4797 output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands);
4798 output_asm_insn (\"blr %%r0,%%r2\", xoperands);
4799 output_asm_insn (\"bv,n %%r0(%%r1)\\n\\tnop\", xoperands);
4802 [(set_attr "type" "dyncall")
4803 (set (attr "length")
4805 ;; First NO_SPACE_REGS
4806 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
4810 ;; Target (or stub) within reach
4811 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4813 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4817 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
4818 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4820 (eq (symbol_ref "flag_pic")
4824 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
4828 ;; Out of range PIC case
4831 (define_expand "call_value"
4832 [(parallel [(set (match_operand 0 "" "")
4833 (call (match_operand:SI 1 "" "")
4834 (match_operand 2 "" "")))
4835 (clobber (reg:SI 2))])]
4842 if (TARGET_PORTABLE_RUNTIME)
4843 op = force_reg (word_mode, XEXP (operands[1], 0));
4845 op = XEXP (operands[1], 0);
4847 /* Use two different patterns for calls to explicitly named functions
4848 and calls through function pointers. This is necessary as these two
4849 types of calls use different calling conventions, and CSE might try
4850 to change the named call into an indirect call in some cases (using
4851 two patterns keeps CSE from performing this optimization). */
4852 if (GET_CODE (op) == SYMBOL_REF)
4853 call_insn = emit_call_insn (gen_call_value_internal_symref (operands[0],
4858 rtx tmpreg = gen_rtx_REG (word_mode, 22);
4859 emit_move_insn (tmpreg, force_reg (word_mode, op));
4860 call_insn = emit_call_insn (gen_call_value_internal_reg (operands[0],
4865 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
4866 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn),
4867 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
4869 /* After each call we must restore the PIC register, even if it
4870 doesn't appear to be used.
4872 This will set regs_ever_live for the callee saved register we
4873 stored the PIC register in. */
4874 emit_move_insn (pic_offset_table_rtx,
4875 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED));
4880 (define_insn "call_value_internal_symref"
4881 [(set (match_operand 0 "" "=rf")
4882 (call (mem:SI (match_operand 1 "call_operand_address" ""))
4883 (match_operand 2 "" "i")))
4884 (clobber (reg:SI 2))
4885 (use (const_int 0))]
4886 ;;- Don't use operand 1 for most machines.
4887 "! TARGET_PORTABLE_RUNTIME"
4890 output_arg_descriptor (insn);
4891 return output_call (insn, operands[1]);
4893 [(set_attr "type" "call")
4894 (set (attr "length")
4895 ;; If we're sure that we can either reach the target or that the
4896 ;; linker can use a long-branch stub, then the length is 4 bytes.
4898 ;; For long-calls the length will be either 52 bytes (non-pic)
4899 ;; or 68 bytes (pic). */
4900 ;; Else we have to use a long-call;
4901 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
4904 (if_then_else (eq (symbol_ref "flag_pic")
4909 (define_insn "call_value_internal_reg"
4910 [(set (match_operand 0 "" "=rf")
4911 (call (mem:SI (reg:SI 22))
4912 (match_operand 1 "" "i")))
4913 (clobber (reg:SI 2))
4914 (use (const_int 1))]
4920 /* First the special case for kernels, level 0 systems, etc. */
4921 if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS)
4922 return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\";
4924 /* Now the normal case -- we can reach $$dyncall directly or
4925 we're sure that we can get there via a long-branch stub.
4927 No need to check target flags as the length uniquely identifies
4928 the remaining cases. */
4929 if (get_attr_length (insn) == 8)
4930 return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\";
4932 /* Long millicode call, but we are not generating PIC or portable runtime
4934 if (get_attr_length (insn) == 12)
4935 return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\";
4937 /* Long millicode call for portable runtime. */
4938 if (get_attr_length (insn) == 20)
4939 return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr %%r0,%%r2\;bv,n %%r0(%%r31)\;nop\";
4941 /* If we're generating PIC code. */
4942 xoperands[0] = operands[1];
4943 xoperands[1] = gen_label_rtx ();
4944 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
4945 output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
4946 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
4947 CODE_LABEL_NUMBER (xoperands[1]));
4948 output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands);
4949 output_asm_insn (\"blr %%r0,%%r2\", xoperands);
4950 output_asm_insn (\"bv,n %%r0(%%r1)\\n\\tnop\", xoperands);
4953 [(set_attr "type" "dyncall")
4954 (set (attr "length")
4956 ;; First NO_SPACE_REGS
4957 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
4961 ;; Target (or stub) within reach
4962 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4964 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4968 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
4969 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4971 (eq (symbol_ref "flag_pic")
4975 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
4979 ;; Out of range PIC case
4982 ;; Call subroutine returning any type.
4984 (define_expand "untyped_call"
4985 [(parallel [(call (match_operand 0 "" "")
4987 (match_operand 1 "" "")
4988 (match_operand 2 "" "")])]
4994 emit_call_insn (gen_call (operands[0], const0_rtx));
4996 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4998 rtx set = XVECEXP (operands[2], 0, i);
4999 emit_move_insn (SET_DEST (set), SET_SRC (set));
5002 /* The optimizer does not know that the call sets the function value
5003 registers we stored in the result block. We avoid problems by
5004 claiming that all hard registers are used and clobbered at this
5006 emit_insn (gen_blockage ());
5014 [(set_attr "type" "move")
5015 (set_attr "length" "4")])
5017 ;; These are just placeholders so we know where branch tables
5019 (define_insn "begin_brtab"
5024 /* Only GAS actually supports this pseudo-op. */
5026 return \".begin_brtab\";
5030 [(set_attr "type" "move")
5031 (set_attr "length" "0")])
5033 (define_insn "end_brtab"
5038 /* Only GAS actually supports this pseudo-op. */
5040 return \".end_brtab\";
5044 [(set_attr "type" "move")
5045 (set_attr "length" "0")])
5047 ;;; Hope this is only within a function...
5048 (define_insn "indirect_jump"
5049 [(set (pc) (match_operand 0 "register_operand" "r"))]
5050 "GET_MODE (operands[0]) == word_mode"
5052 [(set_attr "type" "branch")
5053 (set_attr "length" "4")])
5055 ;;; EH does longjmp's from and within the data section. Thus,
5056 ;;; an interspace branch is required for the longjmp implementation.
5057 ;;; Registers r1 and r2 are not saved in the jmpbuf environment.
5058 ;;; Thus, they can be used as scratch registers for the jump.
5059 (define_insn "interspace_jump"
5060 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
5061 (clobber (reg:SI 2))]
5063 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
5064 [(set_attr "type" "branch")
5065 (set_attr "length" "12")])
5067 (define_expand "builtin_longjmp"
5068 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
5072 /* The elements of the buffer are, in order: */
5073 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5074 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4));
5075 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
5076 rtx pv = gen_rtx_REG (Pmode, 1);
5078 /* This bit is the same as expand_builtin_longjmp. */
5079 emit_move_insn (hard_frame_pointer_rtx, fp);
5080 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5081 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5082 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5084 /* Load the label we are jumping through into r1 so that we know
5085 where to look for it when we get back to setjmp's function for
5086 restoring the gp. */
5087 emit_move_insn (pv, lab);
5088 emit_jump_insn (gen_interspace_jump (pv));
5093 (define_expand "extzv"
5094 [(set (match_operand:SI 0 "register_operand" "")
5095 (zero_extract:SI (match_operand:SI 1 "register_operand" "")
5096 (match_operand:SI 2 "uint5_operand" "")
5097 (match_operand:SI 3 "uint5_operand" "")))]
5101 if (! uint5_operand (operands[2], SImode)
5102 || ! uint5_operand (operands[3], SImode))
5107 [(set (match_operand:SI 0 "register_operand" "=r")
5108 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
5109 (match_operand:SI 2 "uint5_operand" "")
5110 (match_operand:SI 3 "uint5_operand" "")))]
5112 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
5113 [(set_attr "type" "shift")
5114 (set_attr "length" "4")])
5117 [(set (match_operand:SI 0 "register_operand" "=r")
5118 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
5120 (match_operand:SI 3 "register_operand" "q")))]
5122 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
5123 [(set_attr "type" "shift")
5124 (set_attr "length" "4")])
5126 (define_expand "extv"
5127 [(set (match_operand:SI 0 "register_operand" "")
5128 (sign_extract:SI (match_operand:SI 1 "register_operand" "")
5129 (match_operand:SI 2 "uint5_operand" "")
5130 (match_operand:SI 3 "uint5_operand" "")))]
5134 if (! uint5_operand (operands[2], SImode)
5135 || ! uint5_operand (operands[3], SImode))
5140 [(set (match_operand:SI 0 "register_operand" "=r")
5141 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
5142 (match_operand:SI 2 "uint5_operand" "")
5143 (match_operand:SI 3 "uint5_operand" "")))]
5145 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
5146 [(set_attr "type" "shift")
5147 (set_attr "length" "4")])
5150 [(set (match_operand:SI 0 "register_operand" "=r")
5151 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
5153 (match_operand:SI 3 "register_operand" "q")))]
5155 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
5156 [(set_attr "type" "shift")
5157 (set_attr "length" "4")])
5159 (define_expand "insv"
5160 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "")
5161 (match_operand:SI 1 "uint5_operand" "")
5162 (match_operand:SI 2 "uint5_operand" ""))
5163 (match_operand:SI 3 "arith5_operand" "r,L"))]
5167 if (! uint5_operand (operands[1], SImode)
5168 || ! uint5_operand (operands[2], SImode))
5173 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
5174 (match_operand:SI 1 "uint5_operand" "")
5175 (match_operand:SI 2 "uint5_operand" ""))
5176 (match_operand:SI 3 "arith5_operand" "r,L"))]
5179 {dep|depw} %3,%2+%1-1,%1,%0
5180 {depi|depwi} %3,%2+%1-1,%1,%0"
5181 [(set_attr "type" "shift,shift")
5182 (set_attr "length" "4,4")])
5184 ;; Optimize insertion of const_int values of type 1...1xxxx.
5186 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
5187 (match_operand:SI 1 "uint5_operand" "")
5188 (match_operand:SI 2 "uint5_operand" ""))
5189 (match_operand:SI 3 "const_int_operand" ""))]
5190 "(INTVAL (operands[3]) & 0x10) != 0 &&
5191 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
5194 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
5195 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
5197 [(set_attr "type" "shift")
5198 (set_attr "length" "4")])
5200 ;; This insn is used for some loop tests, typically loops reversed when
5201 ;; strength reduction is used. It is actually created when the instruction
5202 ;; combination phase combines the special loop test. Since this insn
5203 ;; is both a jump insn and has an output, it must deal with its own
5204 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
5205 ;; to not choose the register alternatives in the event a reload is needed.
5206 (define_insn "decrement_and_branch_until_zero"
5209 (match_operator 2 "comparison_operator"
5210 [(plus:SI (match_operand:SI 0 "register_operand" "+!r,!*f,!*m")
5211 (match_operand:SI 1 "int5_operand" "L,L,L"))
5213 (label_ref (match_operand 3 "" ""))
5216 (plus:SI (match_dup 0) (match_dup 1)))
5217 (clobber (match_scratch:SI 4 "=X,r,r"))]
5219 "* return output_dbra (operands, insn, which_alternative); "
5220 ;; Do not expect to understand this the first time through.
5221 [(set_attr "type" "cbranch,multi,multi")
5222 (set (attr "length")
5223 (if_then_else (eq_attr "alternative" "0")
5224 ;; Loop counter in register case
5225 ;; Short branch has length of 4
5226 ;; Long branch has length of 8
5227 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
5232 ;; Loop counter in FP reg case.
5233 ;; Extra goo to deal with additional reload insns.
5234 (if_then_else (eq_attr "alternative" "1")
5235 (if_then_else (lt (match_dup 3) (pc))
5237 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
5242 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
5246 ;; Loop counter in memory case.
5247 ;; Extra goo to deal with additional reload insns.
5248 (if_then_else (lt (match_dup 3) (pc))
5250 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
5255 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
5258 (const_int 16))))))])
5263 (match_operator 2 "movb_comparison_operator"
5264 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
5265 (label_ref (match_operand 3 "" ""))
5267 (set (match_operand:SI 0 "register_operand" "=!r,!*f,!*m,!*q")
5270 "* return output_movb (operands, insn, which_alternative, 0); "
5271 ;; Do not expect to understand this the first time through.
5272 [(set_attr "type" "cbranch,multi,multi,multi")
5273 (set (attr "length")
5274 (if_then_else (eq_attr "alternative" "0")
5275 ;; Loop counter in register case
5276 ;; Short branch has length of 4
5277 ;; Long branch has length of 8
5278 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
5283 ;; Loop counter in FP reg case.
5284 ;; Extra goo to deal with additional reload insns.
5285 (if_then_else (eq_attr "alternative" "1")
5286 (if_then_else (lt (match_dup 3) (pc))
5288 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
5293 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
5297 ;; Loop counter in memory or sar case.
5298 ;; Extra goo to deal with additional reload insns.
5300 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
5303 (const_int 12)))))])
5305 ;; Handle negated branch.
5309 (match_operator 2 "movb_comparison_operator"
5310 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
5312 (label_ref (match_operand 3 "" ""))))
5313 (set (match_operand:SI 0 "register_operand" "=!r,!*f,!*m,!*q")
5316 "* return output_movb (operands, insn, which_alternative, 1); "
5317 ;; Do not expect to understand this the first time through.
5318 [(set_attr "type" "cbranch,multi,multi,multi")
5319 (set (attr "length")
5320 (if_then_else (eq_attr "alternative" "0")
5321 ;; Loop counter in register case
5322 ;; Short branch has length of 4
5323 ;; Long branch has length of 8
5324 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
5329 ;; Loop counter in FP reg case.
5330 ;; Extra goo to deal with additional reload insns.
5331 (if_then_else (eq_attr "alternative" "1")
5332 (if_then_else (lt (match_dup 3) (pc))
5334 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
5339 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
5343 ;; Loop counter in memory or SAR case.
5344 ;; Extra goo to deal with additional reload insns.
5346 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
5349 (const_int 12)))))])
5352 [(set (pc) (label_ref (match_operand 3 "" "" )))
5353 (set (match_operand:SI 0 "ireg_operand" "=r")
5354 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
5355 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
5356 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
5359 return output_parallel_addb (operands, get_attr_length (insn));
5361 [(set_attr "type" "parallel_branch")
5362 (set (attr "length")
5363 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
5369 [(set (pc) (label_ref (match_operand 2 "" "" )))
5370 (set (match_operand:SF 0 "ireg_operand" "=r")
5371 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
5375 return output_parallel_movb (operands, get_attr_length (insn));
5377 [(set_attr "type" "parallel_branch")
5378 (set (attr "length")
5379 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
5385 [(set (pc) (label_ref (match_operand 2 "" "" )))
5386 (set (match_operand:SI 0 "ireg_operand" "=r")
5387 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
5391 return output_parallel_movb (operands, get_attr_length (insn));
5393 [(set_attr "type" "parallel_branch")
5394 (set (attr "length")
5395 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
5401 [(set (pc) (label_ref (match_operand 2 "" "" )))
5402 (set (match_operand:HI 0 "ireg_operand" "=r")
5403 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
5407 return output_parallel_movb (operands, get_attr_length (insn));
5409 [(set_attr "type" "parallel_branch")
5410 (set (attr "length")
5411 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
5417 [(set (pc) (label_ref (match_operand 2 "" "" )))
5418 (set (match_operand:QI 0 "ireg_operand" "=r")
5419 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
5423 return output_parallel_movb (operands, get_attr_length (insn));
5425 [(set_attr "type" "parallel_branch")
5426 (set (attr "length")
5427 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
5433 [(set (match_operand 0 "register_operand" "=f")
5434 (mult (match_operand 1 "register_operand" "f")
5435 (match_operand 2 "register_operand" "f")))
5436 (set (match_operand 3 "register_operand" "+f")
5437 (plus (match_operand 4 "register_operand" "f")
5438 (match_operand 5 "register_operand" "f")))]
5439 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
5440 && reload_completed && fmpyaddoperands (operands)"
5443 if (GET_MODE (operands[0]) == DFmode)
5445 if (rtx_equal_p (operands[3], operands[5]))
5446 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
5448 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
5452 if (rtx_equal_p (operands[3], operands[5]))
5453 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
5455 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
5458 [(set_attr "type" "fpalu")
5459 (set_attr "length" "4")])
5462 [(set (match_operand 3 "register_operand" "+f")
5463 (plus (match_operand 4 "register_operand" "f")
5464 (match_operand 5 "register_operand" "f")))
5465 (set (match_operand 0 "register_operand" "=f")
5466 (mult (match_operand 1 "register_operand" "f")
5467 (match_operand 2 "register_operand" "f")))]
5468 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
5469 && reload_completed && fmpyaddoperands (operands)"
5472 if (GET_MODE (operands[0]) == DFmode)
5474 if (rtx_equal_p (operands[3], operands[5]))
5475 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
5477 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
5481 if (rtx_equal_p (operands[3], operands[5]))
5482 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
5484 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
5487 [(set_attr "type" "fpalu")
5488 (set_attr "length" "4")])
5491 [(set (match_operand 0 "register_operand" "=f")
5492 (mult (match_operand 1 "register_operand" "f")
5493 (match_operand 2 "register_operand" "f")))
5494 (set (match_operand 3 "register_operand" "+f")
5495 (minus (match_operand 4 "register_operand" "f")
5496 (match_operand 5 "register_operand" "f")))]
5497 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
5498 && reload_completed && fmpysuboperands (operands)"
5501 if (GET_MODE (operands[0]) == DFmode)
5502 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
5504 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
5506 [(set_attr "type" "fpalu")
5507 (set_attr "length" "4")])
5510 [(set (match_operand 3 "register_operand" "+f")
5511 (minus (match_operand 4 "register_operand" "f")
5512 (match_operand 5 "register_operand" "f")))
5513 (set (match_operand 0 "register_operand" "=f")
5514 (mult (match_operand 1 "register_operand" "f")
5515 (match_operand 2 "register_operand" "f")))]
5516 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
5517 && reload_completed && fmpysuboperands (operands)"
5520 if (GET_MODE (operands[0]) == DFmode)
5521 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
5523 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
5525 [(set_attr "type" "fpalu")
5526 (set_attr "length" "4")])
5528 ;; Clean up turds left by reload.
5530 [(set (match_operand 0 "reg_or_nonsymb_mem_operand" "")
5531 (match_operand 1 "register_operand" "fr"))
5532 (set (match_operand 2 "register_operand" "fr")
5534 "! TARGET_SOFT_FLOAT
5535 && GET_CODE (operands[0]) == MEM
5536 && ! MEM_VOLATILE_P (operands[0])
5537 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5538 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5539 && GET_MODE (operands[0]) == DFmode
5540 && GET_CODE (operands[1]) == REG
5541 && GET_CODE (operands[2]) == REG
5542 && ! side_effects_p (XEXP (operands[0], 0))
5543 && REGNO_REG_CLASS (REGNO (operands[1]))
5544 == REGNO_REG_CLASS (REGNO (operands[2]))"
5549 if (FP_REG_P (operands[1]))
5550 output_asm_insn (output_fp_move_double (operands), operands);
5552 output_asm_insn (output_move_double (operands), operands);
5554 if (rtx_equal_p (operands[1], operands[2]))
5557 xoperands[0] = operands[2];
5558 xoperands[1] = operands[1];
5560 if (FP_REG_P (xoperands[1]))
5561 output_asm_insn (output_fp_move_double (xoperands), xoperands);
5563 output_asm_insn (output_move_double (xoperands), xoperands);
5569 [(set (match_operand 0 "register_operand" "fr")
5570 (match_operand 1 "reg_or_nonsymb_mem_operand" ""))
5571 (set (match_operand 2 "register_operand" "fr")
5573 "! TARGET_SOFT_FLOAT
5574 && GET_CODE (operands[1]) == MEM
5575 && ! MEM_VOLATILE_P (operands[1])
5576 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5577 && GET_MODE (operands[0]) == GET_MODE (operands[2])
5578 && GET_MODE (operands[0]) == DFmode
5579 && GET_CODE (operands[0]) == REG
5580 && GET_CODE (operands[2]) == REG
5581 && ! side_effects_p (XEXP (operands[1], 0))
5582 && REGNO_REG_CLASS (REGNO (operands[0]))
5583 == REGNO_REG_CLASS (REGNO (operands[2]))"
5588 if (FP_REG_P (operands[0]))
5589 output_asm_insn (output_fp_move_double (operands), operands);
5591 output_asm_insn (output_move_double (operands), operands);
5593 xoperands[0] = operands[2];
5594 xoperands[1] = operands[0];
5596 if (FP_REG_P (xoperands[1]))
5597 output_asm_insn (output_fp_move_double (xoperands), xoperands);
5599 output_asm_insn (output_move_double (xoperands), xoperands);
5604 ;; Flush the I and D cache line found at the address in operand 0.
5605 ;; This is used by the trampoline code for nested functions.
5606 ;; So long as the trampoline itself is less than 32 bytes this
5609 (define_insn "dcacheflush"
5610 [(unspec_volatile [(const_int 1)] 0)
5611 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
5612 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))]
5614 "fdc 0(%0)\;fdc 0(%1)\;sync"
5615 [(set_attr "type" "multi")
5616 (set_attr "length" "12")])
5618 (define_insn "icacheflush"
5619 [(unspec_volatile [(const_int 2)] 0)
5620 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
5621 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))
5622 (use (match_operand 2 "pmode_register_operand" "r"))
5623 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
5624 (clobber (match_operand 4 "pmode_register_operand" "=&r"))]
5626 "mfsp %%sr0,%4\;ldsid (%2),%3\;mtsp %3,%%sr0\;fic 0(%%sr0,%0)\;fic 0(%%sr0,%1)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
5627 [(set_attr "type" "multi")
5628 (set_attr "length" "52")])
5630 ;; An out-of-line prologue.
5631 (define_insn "outline_prologue_call"
5632 [(unspec_volatile [(const_int 0)] 0)
5633 (clobber (reg:SI 31))
5634 (clobber (reg:SI 22))
5635 (clobber (reg:SI 21))
5636 (clobber (reg:SI 20))
5637 (clobber (reg:SI 19))
5638 (clobber (reg:SI 1))]
5642 extern int frame_pointer_needed;
5644 /* We need two different versions depending on whether or not we
5645 need a frame pointer. Also note that we return to the instruction
5646 immediately after the branch rather than two instructions after the
5647 break as normally is the case. */
5648 if (frame_pointer_needed)
5650 /* Must import the magic millicode routine(s). */
5651 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
5653 if (TARGET_PORTABLE_RUNTIME)
5655 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
5656 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
5660 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
5664 /* Must import the magic millicode routine(s). */
5665 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
5667 if (TARGET_PORTABLE_RUNTIME)
5669 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
5670 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
5673 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
5677 [(set_attr "type" "multi")
5678 (set_attr "length" "8")])
5680 ;; An out-of-line epilogue.
5681 (define_insn "outline_epilogue_call"
5682 [(unspec_volatile [(const_int 1)] 0)
5685 (clobber (reg:SI 31))
5686 (clobber (reg:SI 22))
5687 (clobber (reg:SI 21))
5688 (clobber (reg:SI 20))
5689 (clobber (reg:SI 19))
5690 (clobber (reg:SI 2))
5691 (clobber (reg:SI 1))]
5695 extern int frame_pointer_needed;
5697 /* We need two different versions depending on whether or not we
5698 need a frame pointer. Also note that we return to the instruction
5699 immediately after the branch rather than two instructions after the
5700 break as normally is the case. */
5701 if (frame_pointer_needed)
5703 /* Must import the magic millicode routine. */
5704 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
5706 /* The out-of-line prologue will make sure we return to the right
5708 if (TARGET_PORTABLE_RUNTIME)
5710 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
5711 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
5715 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
5719 /* Must import the magic millicode routine. */
5720 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
5722 /* The out-of-line prologue will make sure we return to the right
5724 if (TARGET_PORTABLE_RUNTIME)
5726 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
5727 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
5730 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
5734 [(set_attr "type" "multi")
5735 (set_attr "length" "8")])
5737 ;; Given a function pointer, canonicalize it so it can be
5738 ;; reliably compared to another function pointer. */
5739 (define_expand "canonicalize_funcptr_for_compare"
5740 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
5741 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
5742 (clobber (match_dup 2))
5743 (clobber (reg:SI 26))
5744 (clobber (reg:SI 22))
5745 (clobber (reg:SI 31))])
5746 (set (match_operand:SI 0 "register_operand" "")
5748 "! TARGET_PORTABLE_RUNTIME"
5751 operands[2] = gen_reg_rtx (SImode);
5752 if (GET_CODE (operands[1]) != REG)
5754 rtx tmp = gen_reg_rtx (Pmode);
5755 emit_move_insn (tmp, operands[1]);
5761 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
5762 (clobber (match_operand:SI 0 "register_operand" "=a"))
5763 (clobber (reg:SI 26))
5764 (clobber (reg:SI 22))
5765 (clobber (reg:SI 31))]
5769 /* Must import the magic millicode routine. */
5770 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
5772 /* This is absolutely amazing.
5774 First, copy our input parameter into %r29 just in case we don't
5775 need to call $$sh_func_adrs. */
5776 output_asm_insn (\"copy %%r26,%%r29\", NULL);
5778 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
5779 we use %r26 unchanged. */
5780 if (get_attr_length (insn) == 32)
5781 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+24\", NULL);
5782 else if (get_attr_length (insn) == 40)
5783 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+32\", NULL);
5784 else if (get_attr_length (insn) == 44)
5785 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+36\", NULL);
5787 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+20\", NULL);
5789 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
5790 4096, then we use %r26 unchanged. */
5791 if (get_attr_length (insn) == 32)
5792 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+16\",
5794 else if (get_attr_length (insn) == 40)
5795 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+24\",
5797 else if (get_attr_length (insn) == 44)
5798 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+28\",
5801 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+12\",
5804 /* Else call $$sh_func_adrs to extract the function's real add24. */
5805 return output_millicode_call (insn,
5806 gen_rtx_SYMBOL_REF (SImode,
5807 \"$$sh_func_adrs\"));
5809 [(set_attr "type" "multi")
5810 (set (attr "length")
5812 ;; Target (or stub) within reach
5813 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
5815 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
5820 (ne (symbol_ref "TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS")
5824 ;; Out of reach, but not PIC or PORTABLE_RUNTIME
5825 ;; same as NO_SPACE_REGS code
5826 (and (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
5828 (eq (symbol_ref "flag_pic")
5833 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
5837 ;; Out of range and PIC
5840 ;; On the PA, the PIC register is call clobbered, so it must
5841 ;; be saved & restored around calls by the caller. If the call
5842 ;; doesn't return normally (nonlocal goto, or an exception is
5843 ;; thrown), then the code at the exception handler label must
5844 ;; restore the PIC register.
5845 (define_expand "exception_receiver"
5847 "!TARGET_PORTABLE_RUNTIME && flag_pic"
5850 /* Load the PIC register from the stack slot (in our caller's
5852 emit_move_insn (pic_offset_table_rtx,
5853 gen_rtx_MEM (SImode,
5854 plus_constant (stack_pointer_rtx, -32)));
5855 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
5856 emit_insn (gen_blockage ());