1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by the Center for Software Science at the University
8 ;; This file is part of GCC.
10 ;; GCC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 3, or (at your option)
15 ;; GCC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GCC; see the file COPYING3. If not see
22 ;; <http://www.gnu.org/licenses/>.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Uses of UNSPEC in this file:
32 [(UNSPEC_CFFC 0) ; canonicalize_funcptr_for_compare
33 (UNSPEC_GOTO 1) ; indirect_goto
34 (UNSPEC_DLTIND14R 2) ;
43 (UNSPEC_TLSLDM_PIC 11)
50 [(UNSPECV_BLOCKAGE 0) ; blockage
51 (UNSPECV_DCACHE 1) ; dcacheflush
52 (UNSPECV_ICACHE 2) ; icacheflush
53 (UNSPECV_OPC 3) ; outline_prologue_call
54 (UNSPECV_OEC 4) ; outline_epilogue_call
55 (UNSPECV_LONGJMP 5) ; builtin_longjmp
58 ;; Maximum pc-relative branch offsets.
60 ;; These numbers are a bit smaller than the maximum allowable offsets
61 ;; so that a few instructions may be inserted before the actual branch.
64 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
65 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
68 ;; Mode and code iterators
70 ;; This mode iterator allows :P to be used for patterns that operate on
71 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
72 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
74 ;; This attribute defines the condition prefix for word and double word
75 ;; add, compare, subtract and logical instructions.
76 (define_mode_attr dwc [(SI "") (DI "*")])
78 ;; Insn type. Used to default other attribute values.
80 ;; type "unary" insns have one input operand (1) and one output operand (0)
81 ;; type "binary" insns have two input operands (1,2) and one output (0)
84 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch,fpstore_load,store_fpload"
85 (const_string "binary"))
87 (define_attr "pa_combine_type"
88 "fmpy,faddsub,uncond_branch,addmove,none"
89 (const_string "none"))
91 ;; Processor type (for scheduling, not code generation) -- this attribute
92 ;; must exactly match the processor_type enumeration in pa.h.
94 ;; FIXME: Add 800 scheduling for completeness?
96 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
98 ;; Length (in # of bytes).
99 (define_attr "length" ""
100 (cond [(eq_attr "type" "load,fpload")
101 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
102 (const_int 8) (const_int 4))
104 (eq_attr "type" "store,fpstore")
105 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
106 (const_int 8) (const_int 4))
108 (eq_attr "type" "binary,shift,nullshift")
109 (if_then_else (match_operand 2 "arith14_operand" "")
110 (const_int 4) (const_int 12))
112 (eq_attr "type" "move,unary,shift,nullshift")
113 (if_then_else (match_operand 1 "arith14_operand" "")
114 (const_int 4) (const_int 8))]
118 (define_asm_attributes
119 [(set_attr "length" "4")
120 (set_attr "type" "multi")])
122 ;; Attributes for instruction and branch scheduling
124 ;; For conditional branches.
125 (define_attr "in_branch_delay" "false,true"
126 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
127 (eq_attr "length" "4"))
128 (const_string "true")
129 (const_string "false")))
131 ;; Disallow instructions which use the FPU since they will tie up the FPU
132 ;; even if the instruction is nullified.
133 (define_attr "in_nullified_branch_delay" "false,true"
134 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
135 (eq_attr "length" "4"))
136 (const_string "true")
137 (const_string "false")))
139 ;; For calls and millicode calls. Allow unconditional branches in the
141 (define_attr "in_call_delay" "false,true"
142 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
143 (eq_attr "length" "4"))
144 (const_string "true")
145 (eq_attr "type" "uncond_branch")
146 (if_then_else (match_test "TARGET_JUMP_IN_DELAY")
147 (const_string "true")
148 (const_string "false"))]
149 (const_string "false")))
152 ;; Call delay slot description.
153 (define_delay (eq_attr "type" "call")
154 [(eq_attr "in_call_delay" "true") (nil) (nil)])
156 ;; Millicode call delay slot description.
157 (define_delay (eq_attr "type" "milli")
158 [(eq_attr "in_call_delay" "true") (nil) (nil)])
160 ;; Return and other similar instructions.
161 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
162 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
164 ;; Floating point conditional branch delay slot description.
165 (define_delay (eq_attr "type" "fbranch")
166 [(eq_attr "in_branch_delay" "true")
167 (eq_attr "in_nullified_branch_delay" "true")
170 ;; Integer conditional branch delay slot description.
171 ;; Nullification of conditional branches on the PA is dependent on the
172 ;; direction of the branch. Forward branches nullify true and
173 ;; backward branches nullify false. If the direction is unknown
174 ;; then nullification is not allowed.
175 (define_delay (eq_attr "type" "cbranch")
176 [(eq_attr "in_branch_delay" "true")
177 (and (eq_attr "in_nullified_branch_delay" "true")
178 (attr_flag "forward"))
179 (and (eq_attr "in_nullified_branch_delay" "true")
180 (attr_flag "backward"))])
182 (define_delay (and (eq_attr "type" "uncond_branch")
183 (not (match_test "following_call (insn)")))
184 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
186 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
187 ;; load: 2, fpload: 3
188 ;; store, fpstore: 3, no D-cache operations should be scheduled.
190 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
192 ;; Instruction Time Unit Minimum Distance (unit contention)
199 ;; fmpyadd 3 ALU,MPY 2
200 ;; fmpysub 3 ALU,MPY 2
201 ;; fmpycfxt 3 ALU,MPY 2
204 ;; fdiv,sgl 10 MPY 10
205 ;; fdiv,dbl 12 MPY 12
206 ;; fsqrt,sgl 14 MPY 14
207 ;; fsqrt,dbl 18 MPY 18
209 ;; We don't model fmpyadd/fmpysub properly as those instructions
210 ;; keep both the FP ALU and MPY units busy. Given that these
211 ;; processors are obsolete, I'm not going to spend the time to
212 ;; model those instructions correctly.
214 (define_automaton "pa700")
215 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
217 (define_insn_reservation "W0" 4
218 (and (eq_attr "type" "fpcc")
219 (eq_attr "cpu" "700"))
222 (define_insn_reservation "W1" 3
223 (and (eq_attr "type" "fpalu")
224 (eq_attr "cpu" "700"))
227 (define_insn_reservation "W2" 3
228 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
229 (eq_attr "cpu" "700"))
232 (define_insn_reservation "W3" 10
233 (and (eq_attr "type" "fpdivsgl")
234 (eq_attr "cpu" "700"))
237 (define_insn_reservation "W4" 12
238 (and (eq_attr "type" "fpdivdbl")
239 (eq_attr "cpu" "700"))
242 (define_insn_reservation "W5" 14
243 (and (eq_attr "type" "fpsqrtsgl")
244 (eq_attr "cpu" "700"))
247 (define_insn_reservation "W6" 18
248 (and (eq_attr "type" "fpsqrtdbl")
249 (eq_attr "cpu" "700"))
252 (define_insn_reservation "W7" 2
253 (and (eq_attr "type" "load")
254 (eq_attr "cpu" "700"))
257 (define_insn_reservation "W8" 2
258 (and (eq_attr "type" "fpload")
259 (eq_attr "cpu" "700"))
262 (define_insn_reservation "W9" 3
263 (and (eq_attr "type" "store")
264 (eq_attr "cpu" "700"))
267 (define_insn_reservation "W10" 3
268 (and (eq_attr "type" "fpstore")
269 (eq_attr "cpu" "700"))
272 (define_insn_reservation "W11" 5
273 (and (eq_attr "type" "fpstore_load")
274 (eq_attr "cpu" "700"))
277 (define_insn_reservation "W12" 6
278 (and (eq_attr "type" "store_fpload")
279 (eq_attr "cpu" "700"))
282 (define_insn_reservation "W13" 1
283 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
284 (eq_attr "cpu" "700"))
287 ;; We have a bypass for all computations in the FP unit which feed an
288 ;; FP store as long as the sizes are the same.
289 (define_bypass 2 "W1,W2" "W10,W11" "hppa_fpstore_bypass_p")
290 (define_bypass 9 "W3" "W10,W11" "hppa_fpstore_bypass_p")
291 (define_bypass 11 "W4" "W10,W11" "hppa_fpstore_bypass_p")
292 (define_bypass 13 "W5" "W10,W11" "hppa_fpstore_bypass_p")
293 (define_bypass 17 "W6" "W10,W11" "hppa_fpstore_bypass_p")
295 ;; We have an "anti-bypass" for FP loads which feed an FP store.
296 (define_bypass 4 "W8,W12" "W10,W11" "hppa_fpstore_bypass_p")
298 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
299 ;; floating point computations with non-floating point computations (fp loads
300 ;; and stores are not fp computations).
302 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
303 ;; take two cycles, during which no Dcache operations should be scheduled.
304 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
305 ;; all have the same memory characteristics if one disregards cache misses.
307 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
308 ;; There's no value in modeling the ALU and MUL separately though
309 ;; since there can never be a functional unit conflict given the
310 ;; latency and issue rates for those units.
313 ;; Instruction Time Unit Minimum Distance (unit contention)
320 ;; fmpyadd 2 ALU,MPY 1
321 ;; fmpysub 2 ALU,MPY 1
322 ;; fmpycfxt 2 ALU,MPY 1
326 ;; fdiv,dbl 15 DIV 15
328 ;; fsqrt,dbl 15 DIV 15
330 (define_automaton "pa7100")
331 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
333 (define_insn_reservation "X0" 2
334 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
335 (eq_attr "cpu" "7100"))
338 (define_insn_reservation "X1" 8
339 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
340 (eq_attr "cpu" "7100"))
341 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
343 (define_insn_reservation "X2" 15
344 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
345 (eq_attr "cpu" "7100"))
346 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
348 (define_insn_reservation "X3" 2
349 (and (eq_attr "type" "load")
350 (eq_attr "cpu" "7100"))
353 (define_insn_reservation "X4" 2
354 (and (eq_attr "type" "fpload")
355 (eq_attr "cpu" "7100"))
358 (define_insn_reservation "X5" 2
359 (and (eq_attr "type" "store")
360 (eq_attr "cpu" "7100"))
361 "i_7100+mem_7100,mem_7100")
363 (define_insn_reservation "X6" 2
364 (and (eq_attr "type" "fpstore")
365 (eq_attr "cpu" "7100"))
366 "i_7100+mem_7100,mem_7100")
368 (define_insn_reservation "X7" 4
369 (and (eq_attr "type" "fpstore_load")
370 (eq_attr "cpu" "7100"))
371 "i_7100+mem_7100,mem_7100*3")
373 (define_insn_reservation "X8" 4
374 (and (eq_attr "type" "store_fpload")
375 (eq_attr "cpu" "7100"))
376 "i_7100+mem_7100,mem_7100*3")
378 (define_insn_reservation "X9" 1
379 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,fpstore_load,store_fpload")
380 (eq_attr "cpu" "7100"))
383 ;; We have a bypass for all computations in the FP unit which feed an
384 ;; FP store as long as the sizes are the same.
385 (define_bypass 1 "X0" "X6,X7" "hppa_fpstore_bypass_p")
386 (define_bypass 7 "X1" "X6,X7" "hppa_fpstore_bypass_p")
387 (define_bypass 14 "X2" "X6,X7" "hppa_fpstore_bypass_p")
389 ;; We have an "anti-bypass" for FP loads which feed an FP store.
390 (define_bypass 3 "X4,X8" "X6,X7" "hppa_fpstore_bypass_p")
392 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
393 ;; There's no value in modeling the ALU and MUL separately though
394 ;; since there can never be a functional unit conflict that
395 ;; can be avoided given the latency, issue rates and mandatory
396 ;; one cycle cpu-wide lock for a double precision fp multiply.
399 ;; Instruction Time Unit Minimum Distance (unit contention)
406 ;; fmpyadd,sgl 2 ALU,MPY 1
407 ;; fmpyadd,dbl 3 ALU,MPY 2
408 ;; fmpysub,sgl 2 ALU,MPY 1
409 ;; fmpysub,dbl 3 ALU,MPY 2
410 ;; fmpycfxt,sgl 2 ALU,MPY 1
411 ;; fmpycfxt,dbl 3 ALU,MPY 2
416 ;; fdiv,dbl 15 DIV 15
418 ;; fsqrt,dbl 15 DIV 15
420 ;; The PA7200 is just like the PA7100LC except that there is
421 ;; no store-store penalty.
423 ;; The PA7300 is just like the PA7200 except that there is
424 ;; no store-load penalty.
426 ;; Note there are some aspects of the 7100LC we are not modeling
427 ;; at the moment. I'll be reviewing the 7100LC scheduling info
428 ;; shortly and updating this description.
432 ;; other issue modeling
434 (define_automaton "pa7100lc")
435 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
436 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
437 (define_cpu_unit "mem_7100lc" "pa7100lc")
439 ;; Double precision multiplies lock the entire CPU for one
440 ;; cycle. There is no way to avoid this lock and trying to
441 ;; schedule around the lock is pointless and thus there is no
442 ;; value in trying to model this lock.
444 ;; Not modeling the lock allows us to treat fp multiplies just
445 ;; like any other FP alu instruction. It allows for a smaller
446 ;; DFA and may reduce register pressure.
447 (define_insn_reservation "Y0" 2
448 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
449 (eq_attr "cpu" "7100LC,7200,7300"))
450 "f_7100lc,fpmac_7100lc")
452 ;; fp division and sqrt instructions lock the entire CPU for
453 ;; 7 cycles (single precision) or 14 cycles (double precision).
454 ;; There is no way to avoid this lock and trying to schedule
455 ;; around the lock is pointless and thus there is no value in
456 ;; trying to model this lock. Not modeling the lock allows
457 ;; for a smaller DFA and may reduce register pressure.
458 (define_insn_reservation "Y1" 1
459 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
460 (eq_attr "cpu" "7100LC,7200,7300"))
463 (define_insn_reservation "Y2" 2
464 (and (eq_attr "type" "load")
465 (eq_attr "cpu" "7100LC,7200,7300"))
466 "i1_7100lc+mem_7100lc")
468 (define_insn_reservation "Y3" 2
469 (and (eq_attr "type" "fpload")
470 (eq_attr "cpu" "7100LC,7200,7300"))
471 "i1_7100lc+mem_7100lc")
473 (define_insn_reservation "Y4" 2
474 (and (eq_attr "type" "store")
475 (eq_attr "cpu" "7100LC"))
476 "i1_7100lc+mem_7100lc,mem_7100lc")
478 (define_insn_reservation "Y5" 2
479 (and (eq_attr "type" "fpstore")
480 (eq_attr "cpu" "7100LC"))
481 "i1_7100lc+mem_7100lc,mem_7100lc")
483 (define_insn_reservation "Y6" 4
484 (and (eq_attr "type" "fpstore_load")
485 (eq_attr "cpu" "7100LC"))
486 "i1_7100lc+mem_7100lc,mem_7100lc*3")
488 (define_insn_reservation "Y7" 4
489 (and (eq_attr "type" "store_fpload")
490 (eq_attr "cpu" "7100LC"))
491 "i1_7100lc+mem_7100lc,mem_7100lc*3")
493 (define_insn_reservation "Y8" 1
494 (and (eq_attr "type" "shift,nullshift")
495 (eq_attr "cpu" "7100LC,7200,7300"))
498 (define_insn_reservation "Y9" 1
499 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
500 (eq_attr "cpu" "7100LC,7200,7300"))
501 "(i0_7100lc|i1_7100lc)")
503 ;; The 7200 has a store-load penalty
504 (define_insn_reservation "Y10" 2
505 (and (eq_attr "type" "store")
506 (eq_attr "cpu" "7200"))
507 "i1_7100lc,mem_7100lc")
509 (define_insn_reservation "Y11" 2
510 (and (eq_attr "type" "fpstore")
511 (eq_attr "cpu" "7200"))
512 "i1_7100lc,mem_7100lc")
514 (define_insn_reservation "Y12" 4
515 (and (eq_attr "type" "fpstore_load")
516 (eq_attr "cpu" "7200"))
517 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
519 (define_insn_reservation "Y13" 4
520 (and (eq_attr "type" "store_fpload")
521 (eq_attr "cpu" "7200"))
522 "i1_7100lc,mem_7100lc,i1_7100lc+mem_7100lc")
524 ;; The 7300 has no penalty for store-store or store-load
525 (define_insn_reservation "Y14" 2
526 (and (eq_attr "type" "store")
527 (eq_attr "cpu" "7300"))
530 (define_insn_reservation "Y15" 2
531 (and (eq_attr "type" "fpstore")
532 (eq_attr "cpu" "7300"))
535 (define_insn_reservation "Y16" 4
536 (and (eq_attr "type" "fpstore_load")
537 (eq_attr "cpu" "7300"))
538 "i1_7100lc,i1_7100lc+mem_7100lc")
540 (define_insn_reservation "Y17" 4
541 (and (eq_attr "type" "store_fpload")
542 (eq_attr "cpu" "7300"))
543 "i1_7100lc,i1_7100lc+mem_7100lc")
545 ;; We have an "anti-bypass" for FP loads which feed an FP store.
546 (define_bypass 3 "Y3,Y7,Y13,Y17" "Y5,Y6,Y11,Y12,Y15,Y16" "hppa_fpstore_bypass_p")
548 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
549 ;; traditional architecture.
551 ;; The PA8000 has a large (56) entry reorder buffer that is split between
552 ;; memory and non-memory operations.
554 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
555 ;; the function units, with the exception of branches and multi-output
556 ;; instructions. The PA8000 can retire two non-memory operations per cycle
557 ;; and two memory operations per cycle, only one of which may be a store.
559 ;; Given the large reorder buffer, the processor can hide most latencies.
560 ;; According to HP, they've got the best results by scheduling for retirement
561 ;; bandwidth with limited latency scheduling for floating point operations.
562 ;; Latency for integer operations and memory references is ignored.
565 ;; We claim floating point operations have a 2 cycle latency and are
566 ;; fully pipelined, except for div and sqrt which are not pipelined and
567 ;; take from 17 to 31 cycles to complete.
569 ;; It's worth noting that there is no way to saturate all the functional
570 ;; units on the PA8000 as there is not enough issue bandwidth.
572 (define_automaton "pa8000")
573 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
574 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
575 (define_cpu_unit "store_8000" "pa8000")
576 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
577 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
578 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
579 (define_reservation "im_8000" "im0_8000 | im1_8000")
580 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
581 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
582 (define_reservation "f_8000" "f0_8000 | f1_8000")
583 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
585 ;; We can issue any two memops per cycle, but we can only retire
586 ;; one memory store per cycle. We assume that the reorder buffer
587 ;; will hide any memory latencies per HP's recommendation.
588 (define_insn_reservation "Z0" 0
590 (eq_attr "type" "load,fpload")
591 (eq_attr "cpu" "8000"))
594 (define_insn_reservation "Z1" 0
596 (eq_attr "type" "store,fpstore")
597 (eq_attr "cpu" "8000"))
598 "im_8000,rm_8000+store_8000")
600 (define_insn_reservation "Z2" 0
601 (and (eq_attr "type" "fpstore_load,store_fpload")
602 (eq_attr "cpu" "8000"))
603 "im_8000,rm_8000+store_8000,im_8000,rm_8000")
605 ;; We can issue and retire two non-memory operations per cycle with
606 ;; a few exceptions (branches). This group catches those we want
607 ;; to assume have zero latency.
608 (define_insn_reservation "Z3" 0
610 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl,fpstore_load,store_fpload")
611 (eq_attr "cpu" "8000"))
614 ;; Branches use both slots in the non-memory issue and
616 (define_insn_reservation "Z4" 0
618 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
619 (eq_attr "cpu" "8000"))
620 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
622 ;; We partial latency schedule the floating point units.
623 ;; They can issue/retire two at a time in the non-memory
624 ;; units. We fix their latency at 2 cycles and they
625 ;; are fully pipelined.
626 (define_insn_reservation "Z5" 1
628 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
629 (eq_attr "cpu" "8000"))
630 "inm_8000,f_8000,rnm_8000")
632 ;; The fdivsqrt units are not pipelined and have a very long latency.
633 ;; To keep the DFA from exploding, we do not show all the
634 ;; reservations for the divsqrt unit.
635 (define_insn_reservation "Z6" 17
637 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
638 (eq_attr "cpu" "8000"))
639 "inm_8000,fdivsqrt_8000*6,rnm_8000")
641 (define_insn_reservation "Z7" 31
643 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
644 (eq_attr "cpu" "8000"))
645 "inm_8000,fdivsqrt_8000*6,rnm_8000")
647 ;; Operand and operator predicates and constraints
649 (include "predicates.md")
650 (include "constraints.md")
652 ;; Compare instructions.
653 ;; This controls RTL generation and register allocation.
657 (match_operator:CCFP 2 "comparison_operator"
658 [(match_operand:SF 0 "reg_or_0_operand" "fG")
659 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
660 "! TARGET_SOFT_FLOAT"
661 "fcmp,sgl,%Y2 %f0,%f1"
662 [(set_attr "length" "4")
663 (set_attr "type" "fpcc")])
667 (match_operator:CCFP 2 "comparison_operator"
668 [(match_operand:DF 0 "reg_or_0_operand" "fG")
669 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
670 "! TARGET_SOFT_FLOAT"
671 "fcmp,dbl,%Y2 %f0,%f1"
672 [(set_attr "length" "4")
673 (set_attr "type" "fpcc")])
675 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
676 ;; placeholders. This is necessary in rare situations when a
677 ;; placeholder is re-emitted (see PR 8705).
679 (define_expand "movccfp"
681 (match_operand 0 "const_int_operand" ""))]
682 "! TARGET_SOFT_FLOAT"
685 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
689 ;; The following patterns are optimization placeholders. In almost
690 ;; all cases, the user of the condition code will be simplified and the
691 ;; original condition code setting insn should be eliminated.
693 (define_insn "*movccfp0"
696 "! TARGET_SOFT_FLOAT"
697 "fcmp,dbl,= %%fr0,%%fr0"
698 [(set_attr "length" "4")
699 (set_attr "type" "fpcc")])
701 (define_insn "*movccfp1"
704 "! TARGET_SOFT_FLOAT"
705 "fcmp,dbl,!= %%fr0,%%fr0"
706 [(set_attr "length" "4")
707 (set_attr "type" "fpcc")])
711 (define_expand "cstoresi4"
712 [(set (match_operand:SI 0 "register_operand")
713 (match_operator:SI 1 "ordered_comparison_operator"
714 [(match_operand:SI 2 "reg_or_0_operand" "")
715 (match_operand:SI 3 "arith5_operand" "")]))]
719 ;; Instruction canonicalization puts immediate operands second, which
720 ;; is the reverse of what we want.
723 [(set (match_operand:SI 0 "register_operand" "=r")
724 (match_operator:SI 3 "comparison_operator"
725 [(match_operand:SI 1 "register_operand" "r")
726 (match_operand:SI 2 "arith11_operand" "rI")]))]
728 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
729 [(set_attr "type" "binary")
730 (set_attr "length" "8")])
733 [(set (match_operand:DI 0 "register_operand" "=r")
734 (match_operator:DI 3 "comparison_operator"
735 [(match_operand:DI 1 "register_operand" "r")
736 (match_operand:DI 2 "arith11_operand" "rI")]))]
738 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
739 [(set_attr "type" "binary")
740 (set_attr "length" "8")])
742 (define_insn "iorscc"
743 [(set (match_operand:SI 0 "register_operand" "=r")
744 (ior:SI (match_operator:SI 3 "comparison_operator"
745 [(match_operand:SI 1 "register_operand" "r")
746 (match_operand:SI 2 "arith11_operand" "rI")])
747 (match_operator:SI 6 "comparison_operator"
748 [(match_operand:SI 4 "register_operand" "r")
749 (match_operand:SI 5 "arith11_operand" "rI")])))]
751 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
752 [(set_attr "type" "binary")
753 (set_attr "length" "12")])
756 [(set (match_operand:DI 0 "register_operand" "=r")
757 (ior:DI (match_operator:DI 3 "comparison_operator"
758 [(match_operand:DI 1 "register_operand" "r")
759 (match_operand:DI 2 "arith11_operand" "rI")])
760 (match_operator:DI 6 "comparison_operator"
761 [(match_operand:DI 4 "register_operand" "r")
762 (match_operand:DI 5 "arith11_operand" "rI")])))]
764 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
765 [(set_attr "type" "binary")
766 (set_attr "length" "12")])
768 ;; Combiner patterns for common operations performed with the output
769 ;; from an scc insn (negscc and incscc).
770 (define_insn "negscc"
771 [(set (match_operand:SI 0 "register_operand" "=r")
772 (neg:SI (match_operator:SI 3 "comparison_operator"
773 [(match_operand:SI 1 "register_operand" "r")
774 (match_operand:SI 2 "arith11_operand" "rI")])))]
776 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
777 [(set_attr "type" "binary")
778 (set_attr "length" "8")])
781 [(set (match_operand:DI 0 "register_operand" "=r")
782 (neg:DI (match_operator:DI 3 "comparison_operator"
783 [(match_operand:DI 1 "register_operand" "r")
784 (match_operand:DI 2 "arith11_operand" "rI")])))]
786 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
787 [(set_attr "type" "binary")
788 (set_attr "length" "8")])
790 ;; Patterns for adding/subtracting the result of a boolean expression from
791 ;; a register. First we have special patterns that make use of the carry
792 ;; bit, and output only two instructions. For the cases we can't in
793 ;; general do in two instructions, the incscc pattern at the end outputs
794 ;; two or three instructions.
797 [(set (match_operand:SI 0 "register_operand" "=r")
798 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
799 (match_operand:SI 3 "arith11_operand" "rI"))
800 (match_operand:SI 1 "register_operand" "r")))]
802 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
803 [(set_attr "type" "binary")
804 (set_attr "length" "8")])
807 [(set (match_operand:DI 0 "register_operand" "=r")
808 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
809 (match_operand:DI 3 "arith11_operand" "rI"))
810 (match_operand:DI 1 "register_operand" "r")))]
812 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
813 [(set_attr "type" "binary")
814 (set_attr "length" "8")])
816 ; This need only accept registers for op3, since canonicalization
817 ; replaces geu with gtu when op3 is an integer.
819 [(set (match_operand:SI 0 "register_operand" "=r")
820 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
821 (match_operand:SI 3 "register_operand" "r"))
822 (match_operand:SI 1 "register_operand" "r")))]
824 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
825 [(set_attr "type" "binary")
826 (set_attr "length" "8")])
829 [(set (match_operand:DI 0 "register_operand" "=r")
830 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
831 (match_operand:DI 3 "register_operand" "r"))
832 (match_operand:DI 1 "register_operand" "r")))]
834 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
835 [(set_attr "type" "binary")
836 (set_attr "length" "8")])
838 ; Match only integers for op3 here. This is used as canonical form of the
839 ; geu pattern when op3 is an integer. Don't match registers since we can't
840 ; make better code than the general incscc pattern.
842 [(set (match_operand:SI 0 "register_operand" "=r")
843 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
844 (match_operand:SI 3 "int11_operand" "I"))
845 (match_operand:SI 1 "register_operand" "r")))]
847 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
848 [(set_attr "type" "binary")
849 (set_attr "length" "8")])
852 [(set (match_operand:DI 0 "register_operand" "=r")
853 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
854 (match_operand:DI 3 "int11_operand" "I"))
855 (match_operand:DI 1 "register_operand" "r")))]
857 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
858 [(set_attr "type" "binary")
859 (set_attr "length" "8")])
861 (define_insn "incscc"
862 [(set (match_operand:SI 0 "register_operand" "=r,r")
863 (plus:SI (match_operator:SI 4 "comparison_operator"
864 [(match_operand:SI 2 "register_operand" "r,r")
865 (match_operand:SI 3 "arith11_operand" "rI,rI")])
866 (match_operand:SI 1 "register_operand" "0,?r")))]
869 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
870 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
871 [(set_attr "type" "binary,binary")
872 (set_attr "length" "8,12")])
875 [(set (match_operand:DI 0 "register_operand" "=r,r")
876 (plus:DI (match_operator:DI 4 "comparison_operator"
877 [(match_operand:DI 2 "register_operand" "r,r")
878 (match_operand:DI 3 "arith11_operand" "rI,rI")])
879 (match_operand:DI 1 "register_operand" "0,?r")))]
882 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
883 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
884 [(set_attr "type" "binary,binary")
885 (set_attr "length" "8,12")])
888 [(set (match_operand:SI 0 "register_operand" "=r")
889 (minus:SI (match_operand:SI 1 "register_operand" "r")
890 (gtu:SI (match_operand:SI 2 "register_operand" "r")
891 (match_operand:SI 3 "arith11_operand" "rI"))))]
893 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
894 [(set_attr "type" "binary")
895 (set_attr "length" "8")])
898 [(set (match_operand:DI 0 "register_operand" "=r")
899 (minus:DI (match_operand:DI 1 "register_operand" "r")
900 (gtu:DI (match_operand:DI 2 "register_operand" "r")
901 (match_operand:DI 3 "arith11_operand" "rI"))))]
903 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
904 [(set_attr "type" "binary")
905 (set_attr "length" "8")])
908 [(set (match_operand:SI 0 "register_operand" "=r")
909 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
910 (gtu:SI (match_operand:SI 2 "register_operand" "r")
911 (match_operand:SI 3 "arith11_operand" "rI")))
912 (match_operand:SI 4 "register_operand" "r")))]
914 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
915 [(set_attr "type" "binary")
916 (set_attr "length" "8")])
919 [(set (match_operand:DI 0 "register_operand" "=r")
920 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
921 (gtu:DI (match_operand:DI 2 "register_operand" "r")
922 (match_operand:DI 3 "arith11_operand" "rI")))
923 (match_operand:DI 4 "register_operand" "r")))]
925 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
926 [(set_attr "type" "binary")
927 (set_attr "length" "8")])
929 ; This need only accept registers for op3, since canonicalization
930 ; replaces ltu with leu when op3 is an integer.
932 [(set (match_operand:SI 0 "register_operand" "=r")
933 (minus:SI (match_operand:SI 1 "register_operand" "r")
934 (ltu:SI (match_operand:SI 2 "register_operand" "r")
935 (match_operand:SI 3 "register_operand" "r"))))]
937 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
938 [(set_attr "type" "binary")
939 (set_attr "length" "8")])
942 [(set (match_operand:DI 0 "register_operand" "=r")
943 (minus:DI (match_operand:DI 1 "register_operand" "r")
944 (ltu:DI (match_operand:DI 2 "register_operand" "r")
945 (match_operand:DI 3 "register_operand" "r"))))]
947 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
948 [(set_attr "type" "binary")
949 (set_attr "length" "8")])
952 [(set (match_operand:SI 0 "register_operand" "=r")
953 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
954 (ltu:SI (match_operand:SI 2 "register_operand" "r")
955 (match_operand:SI 3 "register_operand" "r")))
956 (match_operand:SI 4 "register_operand" "r")))]
958 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
959 [(set_attr "type" "binary")
960 (set_attr "length" "8")])
963 [(set (match_operand:DI 0 "register_operand" "=r")
964 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
965 (ltu:DI (match_operand:DI 2 "register_operand" "r")
966 (match_operand:DI 3 "register_operand" "r")))
967 (match_operand:DI 4 "register_operand" "r")))]
969 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
970 [(set_attr "type" "binary")
971 (set_attr "length" "8")])
973 ; Match only integers for op3 here. This is used as canonical form of the
974 ; ltu pattern when op3 is an integer. Don't match registers since we can't
975 ; make better code than the general incscc pattern.
977 [(set (match_operand:SI 0 "register_operand" "=r")
978 (minus:SI (match_operand:SI 1 "register_operand" "r")
979 (leu:SI (match_operand:SI 2 "register_operand" "r")
980 (match_operand:SI 3 "int11_operand" "I"))))]
982 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
983 [(set_attr "type" "binary")
984 (set_attr "length" "8")])
987 [(set (match_operand:DI 0 "register_operand" "=r")
988 (minus:DI (match_operand:DI 1 "register_operand" "r")
989 (leu:DI (match_operand:DI 2 "register_operand" "r")
990 (match_operand:DI 3 "int11_operand" "I"))))]
992 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
993 [(set_attr "type" "binary")
994 (set_attr "length" "8")])
997 [(set (match_operand:SI 0 "register_operand" "=r")
998 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
999 (leu:SI (match_operand:SI 2 "register_operand" "r")
1000 (match_operand:SI 3 "int11_operand" "I")))
1001 (match_operand:SI 4 "register_operand" "r")))]
1003 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1004 [(set_attr "type" "binary")
1005 (set_attr "length" "8")])
1008 [(set (match_operand:DI 0 "register_operand" "=r")
1009 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1010 (leu:DI (match_operand:DI 2 "register_operand" "r")
1011 (match_operand:DI 3 "int11_operand" "I")))
1012 (match_operand:DI 4 "register_operand" "r")))]
1014 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1015 [(set_attr "type" "binary")
1016 (set_attr "length" "8")])
1018 (define_insn "decscc"
1019 [(set (match_operand:SI 0 "register_operand" "=r,r")
1020 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1021 (match_operator:SI 4 "comparison_operator"
1022 [(match_operand:SI 2 "register_operand" "r,r")
1023 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1026 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1027 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1028 [(set_attr "type" "binary,binary")
1029 (set_attr "length" "8,12")])
1032 [(set (match_operand:DI 0 "register_operand" "=r,r")
1033 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1034 (match_operator:DI 4 "comparison_operator"
1035 [(match_operand:DI 2 "register_operand" "r,r")
1036 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1039 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1040 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1041 [(set_attr "type" "binary,binary")
1042 (set_attr "length" "8,12")])
1044 ; Patterns for max and min. (There is no need for an earlyclobber in the
1045 ; last alternative since the middle alternative will match if op0 == op1.)
1047 (define_insn "sminsi3"
1048 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1049 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1050 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1053 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1054 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1055 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1056 [(set_attr "type" "multi,multi,multi")
1057 (set_attr "length" "8,8,8")])
1059 (define_insn "smindi3"
1060 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1061 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1062 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1065 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1066 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1067 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1068 [(set_attr "type" "multi,multi,multi")
1069 (set_attr "length" "8,8,8")])
1071 (define_insn "uminsi3"
1072 [(set (match_operand:SI 0 "register_operand" "=r,r")
1073 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1074 (match_operand:SI 2 "arith11_operand" "r,I")))]
1077 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1078 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1079 [(set_attr "type" "multi,multi")
1080 (set_attr "length" "8,8")])
1082 (define_insn "umindi3"
1083 [(set (match_operand:DI 0 "register_operand" "=r,r")
1084 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1085 (match_operand:DI 2 "arith11_operand" "r,I")))]
1088 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1089 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1090 [(set_attr "type" "multi,multi")
1091 (set_attr "length" "8,8")])
1093 (define_insn "smaxsi3"
1094 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1095 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1096 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1099 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1100 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1101 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1102 [(set_attr "type" "multi,multi,multi")
1103 (set_attr "length" "8,8,8")])
1105 (define_insn "smaxdi3"
1106 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1107 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1108 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1111 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1112 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1113 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1114 [(set_attr "type" "multi,multi,multi")
1115 (set_attr "length" "8,8,8")])
1117 (define_insn "umaxsi3"
1118 [(set (match_operand:SI 0 "register_operand" "=r,r")
1119 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1120 (match_operand:SI 2 "arith11_operand" "r,I")))]
1123 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1124 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1125 [(set_attr "type" "multi,multi")
1126 (set_attr "length" "8,8")])
1128 (define_insn "umaxdi3"
1129 [(set (match_operand:DI 0 "register_operand" "=r,r")
1130 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1131 (match_operand:DI 2 "arith11_operand" "r,I")))]
1134 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1135 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1136 [(set_attr "type" "multi,multi")
1137 (set_attr "length" "8,8")])
1139 (define_insn "abssi2"
1140 [(set (match_operand:SI 0 "register_operand" "=r")
1141 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1143 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1144 [(set_attr "type" "multi")
1145 (set_attr "length" "8")])
1147 (define_insn "absdi2"
1148 [(set (match_operand:DI 0 "register_operand" "=r")
1149 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1151 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1152 [(set_attr "type" "multi")
1153 (set_attr "length" "8")])
1155 ;;; Experimental conditional move patterns
1157 (define_expand "movsicc"
1158 [(set (match_operand:SI 0 "register_operand" "")
1160 (match_operand 1 "comparison_operator" "")
1161 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1162 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1166 if (GET_MODE (XEXP (operands[1], 0)) != SImode
1167 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1171 ;; We used to accept any register for op1.
1173 ;; However, it loses sometimes because the compiler will end up using
1174 ;; different registers for op0 and op1 in some critical cases. local-alloc
1175 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1177 ;; If/when global register allocation supports tying we should allow any
1178 ;; register for op1 again.
1180 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1182 (match_operator 2 "comparison_operator"
1183 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1184 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1185 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1189 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1190 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1191 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1192 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1193 [(set_attr "type" "multi,multi,multi,nullshift")
1194 (set_attr "length" "8,8,8,8")])
1197 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1199 (match_operator 5 "comparison_operator"
1200 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1201 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1202 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1203 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1206 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1207 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1208 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1209 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1210 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1211 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1212 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1213 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1214 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1215 (set_attr "length" "8,8,8,8,8,8,8,8")])
1217 (define_expand "movdicc"
1218 [(set (match_operand:DI 0 "register_operand" "")
1220 (match_operand 1 "comparison_operator" "")
1221 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1222 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1226 if (GET_MODE (XEXP (operands[1], 0)) != DImode
1227 || GET_MODE (XEXP (operands[1], 0)) != GET_MODE (XEXP (operands[1], 1)))
1231 ; We need the first constraint alternative in order to avoid
1232 ; earlyclobbers on all other alternatives.
1234 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1236 (match_operator 2 "comparison_operator"
1237 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1238 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1239 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1243 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1244 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1245 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1246 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1247 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1248 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1249 (set_attr "length" "8,8,8,8,8")])
1252 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1254 (match_operator 5 "comparison_operator"
1255 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1256 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1257 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1258 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1261 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1262 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1263 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1264 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1265 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1266 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1267 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1268 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1269 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1270 (set_attr "length" "8,8,8,8,8,8,8,8")])
1272 ;; Conditional Branches
1274 (define_expand "cbranchdi4"
1276 (if_then_else (match_operator 0 "ordered_comparison_operator"
1277 [(match_operand:DI 1 "reg_or_0_operand" "")
1278 (match_operand:DI 2 "register_operand" "")])
1279 (label_ref (match_operand 3 "" ""))
1284 (define_expand "cbranchsi4"
1286 (if_then_else (match_operator 0 "ordered_comparison_operator"
1287 [(match_operand:SI 1 "reg_or_0_operand" "")
1288 (match_operand:SI 2 "arith5_operand" "")])
1289 (label_ref (match_operand 3 "" ""))
1294 (define_expand "cbranchsf4"
1296 (if_then_else (match_operator 0 "comparison_operator"
1297 [(match_operand:SF 1 "reg_or_0_operand" "")
1298 (match_operand:SF 2 "reg_or_0_operand" "")])
1299 (label_ref (match_operand 3 "" ""))
1304 emit_bcond_fp (operands);
1309 (define_expand "cbranchdf4"
1311 (if_then_else (match_operator 0 "comparison_operator"
1312 [(match_operand:DF 1 "reg_or_0_operand" "")
1313 (match_operand:DF 2 "reg_or_0_operand" "")])
1314 (label_ref (match_operand 3 "" ""))
1319 emit_bcond_fp (operands);
1323 ;; Match the branch patterns.
1326 ;; Note a long backward conditional branch with an annulled delay slot
1327 ;; has a length of 12.
1331 (match_operator 3 "comparison_operator"
1332 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1333 (match_operand:SI 2 "arith5_operand" "rL")])
1334 (label_ref (match_operand 0 "" ""))
1339 return output_cbranch (operands, 0, insn);
1341 [(set_attr "type" "cbranch")
1342 (set (attr "length")
1343 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1344 (const_int MAX_12BIT_OFFSET))
1346 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1347 (const_int MAX_17BIT_OFFSET))
1349 (match_test "TARGET_PORTABLE_RUNTIME")
1351 (not (match_test "flag_pic"))
1355 ;; Match the negated branch.
1360 (match_operator 3 "comparison_operator"
1361 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1362 (match_operand:SI 2 "arith5_operand" "rL")])
1364 (label_ref (match_operand 0 "" ""))))]
1368 return output_cbranch (operands, 1, insn);
1370 [(set_attr "type" "cbranch")
1371 (set (attr "length")
1372 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1373 (const_int MAX_12BIT_OFFSET))
1375 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1376 (const_int MAX_17BIT_OFFSET))
1378 (match_test "TARGET_PORTABLE_RUNTIME")
1380 (not (match_test "flag_pic"))
1387 (match_operator 3 "comparison_operator"
1388 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1389 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1390 (label_ref (match_operand 0 "" ""))
1395 return output_cbranch (operands, 0, insn);
1397 [(set_attr "type" "cbranch")
1398 (set (attr "length")
1399 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1400 (const_int MAX_12BIT_OFFSET))
1402 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1403 (const_int MAX_17BIT_OFFSET))
1405 (match_test "TARGET_PORTABLE_RUNTIME")
1407 (not (match_test "flag_pic"))
1411 ;; Match the negated branch.
1416 (match_operator 3 "comparison_operator"
1417 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1418 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1420 (label_ref (match_operand 0 "" ""))))]
1424 return output_cbranch (operands, 1, insn);
1426 [(set_attr "type" "cbranch")
1427 (set (attr "length")
1428 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1429 (const_int MAX_12BIT_OFFSET))
1431 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1432 (const_int MAX_17BIT_OFFSET))
1434 (match_test "TARGET_PORTABLE_RUNTIME")
1436 (not (match_test "flag_pic"))
1442 (match_operator 3 "cmpib_comparison_operator"
1443 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1444 (match_operand:DI 2 "arith5_operand" "rL")])
1445 (label_ref (match_operand 0 "" ""))
1450 return output_cbranch (operands, 0, insn);
1452 [(set_attr "type" "cbranch")
1453 (set (attr "length")
1454 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1455 (const_int MAX_12BIT_OFFSET))
1457 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1458 (const_int MAX_17BIT_OFFSET))
1460 (match_test "TARGET_PORTABLE_RUNTIME")
1462 (not (match_test "flag_pic"))
1466 ;; Match the negated branch.
1471 (match_operator 3 "cmpib_comparison_operator"
1472 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1473 (match_operand:DI 2 "arith5_operand" "rL")])
1475 (label_ref (match_operand 0 "" ""))))]
1479 return output_cbranch (operands, 1, insn);
1481 [(set_attr "type" "cbranch")
1482 (set (attr "length")
1483 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1484 (const_int MAX_12BIT_OFFSET))
1486 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1487 (const_int MAX_17BIT_OFFSET))
1489 (match_test "TARGET_PORTABLE_RUNTIME")
1491 (not (match_test "flag_pic"))
1495 ;; Branch on Bit patterns.
1499 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1501 (match_operand:SI 1 "uint5_operand" ""))
1503 (label_ref (match_operand 2 "" ""))
1508 return output_bb (operands, 0, insn, 0);
1510 [(set_attr "type" "cbranch")
1511 (set (attr "length")
1512 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1513 (const_int MAX_12BIT_OFFSET))
1515 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1516 (const_int MAX_17BIT_OFFSET))
1518 (match_test "TARGET_PORTABLE_RUNTIME")
1520 (not (match_test "flag_pic"))
1527 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1529 (match_operand:DI 1 "uint32_operand" ""))
1531 (label_ref (match_operand 2 "" ""))
1536 return output_bb (operands, 0, insn, 0);
1538 [(set_attr "type" "cbranch")
1539 (set (attr "length")
1540 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1541 (const_int MAX_12BIT_OFFSET))
1543 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1544 (const_int MAX_17BIT_OFFSET))
1546 (match_test "TARGET_PORTABLE_RUNTIME")
1548 (not (match_test "flag_pic"))
1555 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1557 (match_operand:SI 1 "uint5_operand" ""))
1560 (label_ref (match_operand 2 "" ""))))]
1564 return output_bb (operands, 1, insn, 0);
1566 [(set_attr "type" "cbranch")
1567 (set (attr "length")
1568 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1569 (const_int MAX_12BIT_OFFSET))
1571 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1572 (const_int MAX_17BIT_OFFSET))
1574 (match_test "TARGET_PORTABLE_RUNTIME")
1576 (not (match_test "flag_pic"))
1583 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1585 (match_operand:DI 1 "uint32_operand" ""))
1588 (label_ref (match_operand 2 "" ""))))]
1592 return output_bb (operands, 1, insn, 0);
1594 [(set_attr "type" "cbranch")
1595 (set (attr "length")
1596 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1597 (const_int MAX_12BIT_OFFSET))
1599 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1600 (const_int MAX_17BIT_OFFSET))
1602 (match_test "TARGET_PORTABLE_RUNTIME")
1604 (not (match_test "flag_pic"))
1611 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1613 (match_operand:SI 1 "uint5_operand" ""))
1615 (label_ref (match_operand 2 "" ""))
1620 return output_bb (operands, 0, insn, 1);
1622 [(set_attr "type" "cbranch")
1623 (set (attr "length")
1624 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1625 (const_int MAX_12BIT_OFFSET))
1627 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1628 (const_int MAX_17BIT_OFFSET))
1630 (match_test "TARGET_PORTABLE_RUNTIME")
1632 (not (match_test "flag_pic"))
1639 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1641 (match_operand:DI 1 "uint32_operand" ""))
1643 (label_ref (match_operand 2 "" ""))
1648 return output_bb (operands, 0, insn, 1);
1650 [(set_attr "type" "cbranch")
1651 (set (attr "length")
1652 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1653 (const_int MAX_12BIT_OFFSET))
1655 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1656 (const_int MAX_17BIT_OFFSET))
1658 (match_test "TARGET_PORTABLE_RUNTIME")
1660 (not (match_test "flag_pic"))
1667 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1669 (match_operand:SI 1 "uint5_operand" ""))
1672 (label_ref (match_operand 2 "" ""))))]
1676 return output_bb (operands, 1, insn, 1);
1678 [(set_attr "type" "cbranch")
1679 (set (attr "length")
1680 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1681 (const_int MAX_12BIT_OFFSET))
1683 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1684 (const_int MAX_17BIT_OFFSET))
1686 (match_test "TARGET_PORTABLE_RUNTIME")
1688 (not (match_test "flag_pic"))
1695 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1697 (match_operand:DI 1 "uint32_operand" ""))
1700 (label_ref (match_operand 2 "" ""))))]
1704 return output_bb (operands, 1, insn, 1);
1706 [(set_attr "type" "cbranch")
1707 (set (attr "length")
1708 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1709 (const_int MAX_12BIT_OFFSET))
1711 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1712 (const_int MAX_17BIT_OFFSET))
1714 (match_test "TARGET_PORTABLE_RUNTIME")
1716 (not (match_test "flag_pic"))
1720 ;; Branch on Variable Bit patterns.
1724 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1726 (match_operand:SI 1 "register_operand" "q"))
1728 (label_ref (match_operand 2 "" ""))
1733 return output_bvb (operands, 0, insn, 0);
1735 [(set_attr "type" "cbranch")
1736 (set (attr "length")
1737 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1738 (const_int MAX_12BIT_OFFSET))
1740 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1741 (const_int MAX_17BIT_OFFSET))
1743 (match_test "TARGET_PORTABLE_RUNTIME")
1745 (not (match_test "flag_pic"))
1752 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1754 (match_operand:DI 1 "register_operand" "q"))
1756 (label_ref (match_operand 2 "" ""))
1761 return output_bvb (operands, 0, insn, 0);
1763 [(set_attr "type" "cbranch")
1764 (set (attr "length")
1765 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1766 (const_int MAX_12BIT_OFFSET))
1768 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1769 (const_int MAX_17BIT_OFFSET))
1771 (match_test "TARGET_PORTABLE_RUNTIME")
1773 (not (match_test "flag_pic"))
1780 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1782 (match_operand:SI 1 "register_operand" "q"))
1785 (label_ref (match_operand 2 "" ""))))]
1789 return output_bvb (operands, 1, insn, 0);
1791 [(set_attr "type" "cbranch")
1792 (set (attr "length")
1793 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1794 (const_int MAX_12BIT_OFFSET))
1796 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1797 (const_int MAX_17BIT_OFFSET))
1799 (match_test "TARGET_PORTABLE_RUNTIME")
1801 (not (match_test "flag_pic"))
1808 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1810 (match_operand:DI 1 "register_operand" "q"))
1813 (label_ref (match_operand 2 "" ""))))]
1817 return output_bvb (operands, 1, insn, 0);
1819 [(set_attr "type" "cbranch")
1820 (set (attr "length")
1821 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1822 (const_int MAX_12BIT_OFFSET))
1824 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1825 (const_int MAX_17BIT_OFFSET))
1827 (match_test "TARGET_PORTABLE_RUNTIME")
1829 (not (match_test "flag_pic"))
1836 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1838 (match_operand:SI 1 "register_operand" "q"))
1840 (label_ref (match_operand 2 "" ""))
1845 return output_bvb (operands, 0, insn, 1);
1847 [(set_attr "type" "cbranch")
1848 (set (attr "length")
1849 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1850 (const_int MAX_12BIT_OFFSET))
1852 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1853 (const_int MAX_17BIT_OFFSET))
1855 (match_test "TARGET_PORTABLE_RUNTIME")
1857 (not (match_test "flag_pic"))
1864 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1866 (match_operand:DI 1 "register_operand" "q"))
1868 (label_ref (match_operand 2 "" ""))
1873 return output_bvb (operands, 0, insn, 1);
1875 [(set_attr "type" "cbranch")
1876 (set (attr "length")
1877 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1878 (const_int MAX_12BIT_OFFSET))
1880 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1881 (const_int MAX_17BIT_OFFSET))
1883 (match_test "TARGET_PORTABLE_RUNTIME")
1885 (not (match_test "flag_pic"))
1892 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1894 (match_operand:SI 1 "register_operand" "q"))
1897 (label_ref (match_operand 2 "" ""))))]
1901 return output_bvb (operands, 1, insn, 1);
1903 [(set_attr "type" "cbranch")
1904 (set (attr "length")
1905 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1906 (const_int MAX_12BIT_OFFSET))
1908 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1909 (const_int MAX_17BIT_OFFSET))
1911 (match_test "TARGET_PORTABLE_RUNTIME")
1913 (not (match_test "flag_pic"))
1920 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1922 (match_operand:DI 1 "register_operand" "q"))
1925 (label_ref (match_operand 2 "" ""))))]
1929 return output_bvb (operands, 1, insn, 1);
1931 [(set_attr "type" "cbranch")
1932 (set (attr "length")
1933 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1934 (const_int MAX_12BIT_OFFSET))
1936 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1937 (const_int MAX_17BIT_OFFSET))
1939 (match_test "TARGET_PORTABLE_RUNTIME")
1941 (not (match_test "flag_pic"))
1945 ;; Floating point branches
1947 ;; ??? Nullification is handled differently from other branches.
1948 ;; If nullification is specified, the delay slot is nullified on any
1949 ;; taken branch regardless of branch direction.
1951 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1952 (label_ref (match_operand 0 "" ""))
1954 "!TARGET_SOFT_FLOAT"
1957 int length = get_attr_length (insn);
1959 int nullify, xdelay;
1962 return \"ftest\;b%* %l0\";
1964 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
1968 xoperands[0] = GEN_INT (length - 8);
1974 xoperands[0] = GEN_INT (length - 4);
1978 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
1980 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
1981 return output_lbranch (operands[0], insn, xdelay);
1983 [(set_attr "type" "fbranch")
1984 (set (attr "length")
1985 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1986 (const_int MAX_17BIT_OFFSET))
1988 (match_test "TARGET_PORTABLE_RUNTIME")
1990 (not (match_test "flag_pic"))
1995 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
1997 (label_ref (match_operand 0 "" ""))))]
1998 "!TARGET_SOFT_FLOAT"
2001 int length = get_attr_length (insn);
2003 int nullify, xdelay;
2006 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2008 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2012 xoperands[0] = GEN_INT (length - 4);
2018 xoperands[0] = GEN_INT (length);
2022 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2024 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2025 return output_lbranch (operands[0], insn, xdelay);
2027 [(set_attr "type" "fbranch")
2028 (set (attr "length")
2029 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2030 (const_int MAX_17BIT_OFFSET))
2032 (match_test "TARGET_PORTABLE_RUNTIME")
2034 (not (match_test "flag_pic"))
2038 ;; Move instructions
2040 (define_expand "movsi"
2041 [(set (match_operand:SI 0 "general_operand" "")
2042 (match_operand:SI 1 "general_operand" ""))]
2046 if (emit_move_sequence (operands, SImode, 0))
2050 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2051 (define_expand "reload_insi_r1"
2052 [(set (match_operand:SI 0 "register_operand" "=Z")
2053 (match_operand:SI 1 "non_hard_reg_operand" ""))
2054 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2058 if (emit_move_sequence (operands, SImode, operands[2]))
2061 /* We don't want the clobber emitted, so handle this ourselves. */
2062 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2066 ;; Handle SImode input reloads requiring a general register as a
2067 ;; scratch register.
2068 (define_expand "reload_insi"
2069 [(set (match_operand:SI 0 "register_operand" "=Z")
2070 (match_operand:SI 1 "non_hard_reg_operand" ""))
2071 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2075 if (emit_move_sequence (operands, SImode, operands[2]))
2078 /* We don't want the clobber emitted, so handle this ourselves. */
2079 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2083 ;; Handle SImode output reloads requiring a general register as a
2084 ;; scratch register.
2085 (define_expand "reload_outsi"
2086 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2087 (match_operand:SI 1 "register_operand" "Z"))
2088 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2092 if (emit_move_sequence (operands, SImode, operands[2]))
2095 /* We don't want the clobber emitted, so handle this ourselves. */
2096 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2101 [(set (match_operand:SI 0 "move_dest_operand"
2102 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,?r,?*f")
2103 (match_operand:SI 1 "move_src_operand"
2104 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,*f,r"))]
2105 "(register_operand (operands[0], SImode)
2106 || reg_or_0_operand (operands[1], SImode))
2107 && !TARGET_SOFT_FLOAT
2114 {zdepi|depwi,z} %Z1,%0
2118 {mfctl|mfctl,w} %%sar,%0
2122 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2123 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2124 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,fpstore_load,store_fpload")
2125 (set_attr "pa_combine_type" "addmove")
2126 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2129 [(set (match_operand:SI 0 "move_dest_operand"
2130 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2131 (match_operand:SI 1 "move_src_operand"
2132 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2133 "(register_operand (operands[0], SImode)
2134 || reg_or_0_operand (operands[1], SImode))
2135 && !TARGET_SOFT_FLOAT
2142 {zdepi|depwi,z} %Z1,%0
2146 {mfctl|mfctl,w} %%sar,%0
2150 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2151 (set_attr "pa_combine_type" "addmove")
2152 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2155 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2156 (match_operand:SI 1 "register_operand" "f"))]
2158 && !TARGET_DISABLE_INDEXING
2159 && reload_completed"
2161 [(set_attr "type" "fpstore")
2162 (set_attr "pa_combine_type" "addmove")
2163 (set_attr "length" "4")])
2165 ; Rewrite RTL using an indexed store. This will allow the insn that
2166 ; computes the address to be deleted if the register it sets is dead.
2168 [(set (match_operand:SI 0 "register_operand" "")
2169 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2171 (match_operand:SI 2 "register_operand" "")))
2172 (set (mem:SI (match_dup 0))
2173 (match_operand:SI 3 "register_operand" ""))]
2175 && !TARGET_DISABLE_INDEXING
2176 && REG_OK_FOR_BASE_P (operands[2])
2177 && FP_REGNO_P (REGNO (operands[3]))"
2178 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2180 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2185 [(set (match_operand:SI 0 "register_operand" "")
2186 (plus:SI (match_operand:SI 2 "register_operand" "")
2187 (mult:SI (match_operand:SI 1 "register_operand" "")
2189 (set (mem:SI (match_dup 0))
2190 (match_operand:SI 3 "register_operand" ""))]
2192 && !TARGET_DISABLE_INDEXING
2193 && REG_OK_FOR_BASE_P (operands[2])
2194 && FP_REGNO_P (REGNO (operands[3]))"
2195 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2197 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2202 [(set (match_operand:DI 0 "register_operand" "")
2203 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2205 (match_operand:DI 2 "register_operand" "")))
2206 (set (mem:SI (match_dup 0))
2207 (match_operand:SI 3 "register_operand" ""))]
2209 && !TARGET_DISABLE_INDEXING
2211 && REG_OK_FOR_BASE_P (operands[2])
2212 && FP_REGNO_P (REGNO (operands[3]))"
2213 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2215 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2220 [(set (match_operand:DI 0 "register_operand" "")
2221 (plus:DI (match_operand:DI 2 "register_operand" "")
2222 (mult:DI (match_operand:DI 1 "register_operand" "")
2224 (set (mem:SI (match_dup 0))
2225 (match_operand:SI 3 "register_operand" ""))]
2227 && !TARGET_DISABLE_INDEXING
2229 && REG_OK_FOR_BASE_P (operands[2])
2230 && FP_REGNO_P (REGNO (operands[3]))"
2231 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2233 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2238 [(set (match_operand:SI 0 "register_operand" "")
2239 (plus:SI (match_operand:SI 1 "register_operand" "")
2240 (match_operand:SI 2 "register_operand" "")))
2241 (set (mem:SI (match_dup 0))
2242 (match_operand:SI 3 "register_operand" ""))]
2244 && !TARGET_DISABLE_INDEXING
2245 && TARGET_NO_SPACE_REGS
2246 && REG_OK_FOR_INDEX_P (operands[1])
2247 && REG_OK_FOR_BASE_P (operands[2])
2248 && FP_REGNO_P (REGNO (operands[3]))"
2249 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2251 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2255 [(set (match_operand:SI 0 "register_operand" "")
2256 (plus:SI (match_operand:SI 1 "register_operand" "")
2257 (match_operand:SI 2 "register_operand" "")))
2258 (set (mem:SI (match_dup 0))
2259 (match_operand:SI 3 "register_operand" ""))]
2261 && !TARGET_DISABLE_INDEXING
2262 && TARGET_NO_SPACE_REGS
2263 && REG_OK_FOR_BASE_P (operands[1])
2264 && REG_OK_FOR_INDEX_P (operands[2])
2265 && FP_REGNO_P (REGNO (operands[3]))"
2266 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2268 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2272 [(set (match_operand:DI 0 "register_operand" "")
2273 (plus:DI (match_operand:DI 1 "register_operand" "")
2274 (match_operand:DI 2 "register_operand" "")))
2275 (set (mem:SI (match_dup 0))
2276 (match_operand:SI 3 "register_operand" ""))]
2278 && !TARGET_DISABLE_INDEXING
2280 && TARGET_NO_SPACE_REGS
2281 && REG_OK_FOR_INDEX_P (operands[1])
2282 && REG_OK_FOR_BASE_P (operands[2])
2283 && FP_REGNO_P (REGNO (operands[3]))"
2284 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2286 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2290 [(set (match_operand:DI 0 "register_operand" "")
2291 (plus:DI (match_operand:DI 1 "register_operand" "")
2292 (match_operand:DI 2 "register_operand" "")))
2293 (set (mem:SI (match_dup 0))
2294 (match_operand:SI 3 "register_operand" ""))]
2296 && !TARGET_DISABLE_INDEXING
2298 && TARGET_NO_SPACE_REGS
2299 && REG_OK_FOR_BASE_P (operands[1])
2300 && REG_OK_FOR_INDEX_P (operands[2])
2301 && FP_REGNO_P (REGNO (operands[3]))"
2302 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2304 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2308 [(set (match_operand:SI 0 "move_dest_operand"
2309 "=r,r,r,r,r,r,Q,!*q,!r")
2310 (match_operand:SI 1 "move_src_operand"
2311 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2312 "(register_operand (operands[0], SImode)
2313 || reg_or_0_operand (operands[1], SImode))
2314 && TARGET_SOFT_FLOAT"
2320 {zdepi|depwi,z} %Z1,%0
2324 {mfctl|mfctl,w} %%sar,%0"
2325 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2326 (set_attr "pa_combine_type" "addmove")
2327 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2329 ;; Load or store with base-register modification.
2331 [(set (match_operand:SI 0 "register_operand" "=r")
2332 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2333 (match_operand:DI 2 "int5_operand" "L"))))
2335 (plus:DI (match_dup 1) (match_dup 2)))]
2338 [(set_attr "type" "load")
2339 (set_attr "length" "4")])
2341 ; And a zero extended variant.
2343 [(set (match_operand:DI 0 "register_operand" "=r")
2344 (zero_extend:DI (mem:SI
2346 (match_operand:DI 1 "register_operand" "+r")
2347 (match_operand:DI 2 "int5_operand" "L")))))
2349 (plus:DI (match_dup 1) (match_dup 2)))]
2352 [(set_attr "type" "load")
2353 (set_attr "length" "4")])
2355 (define_expand "pre_load"
2356 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2357 (mem (plus (match_operand 1 "register_operand" "")
2358 (match_operand 2 "pre_cint_operand" ""))))
2360 (plus (match_dup 1) (match_dup 2)))])]
2366 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2369 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2373 (define_insn "pre_ldw"
2374 [(set (match_operand:SI 0 "register_operand" "=r")
2375 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2376 (match_operand:SI 2 "pre_cint_operand" ""))))
2378 (plus:SI (match_dup 1) (match_dup 2)))]
2382 if (INTVAL (operands[2]) < 0)
2383 return \"{ldwm|ldw,mb} %2(%1),%0\";
2384 return \"{ldws|ldw},mb %2(%1),%0\";
2386 [(set_attr "type" "load")
2387 (set_attr "length" "4")])
2389 (define_insn "pre_ldd"
2390 [(set (match_operand:DI 0 "register_operand" "=r")
2391 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2392 (match_operand:DI 2 "pre_cint_operand" ""))))
2394 (plus:DI (match_dup 1) (match_dup 2)))]
2397 [(set_attr "type" "load")
2398 (set_attr "length" "4")])
2401 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2402 (match_operand:SI 1 "pre_cint_operand" "")))
2403 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2405 (plus:SI (match_dup 0) (match_dup 1)))]
2409 if (INTVAL (operands[1]) < 0)
2410 return \"{stwm|stw,mb} %r2,%1(%0)\";
2411 return \"{stws|stw},mb %r2,%1(%0)\";
2413 [(set_attr "type" "store")
2414 (set_attr "length" "4")])
2417 [(set (match_operand:SI 0 "register_operand" "=r")
2418 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2420 (plus:SI (match_dup 1)
2421 (match_operand:SI 2 "post_cint_operand" "")))]
2425 if (INTVAL (operands[2]) > 0)
2426 return \"{ldwm|ldw,ma} %2(%1),%0\";
2427 return \"{ldws|ldw},ma %2(%1),%0\";
2429 [(set_attr "type" "load")
2430 (set_attr "length" "4")])
2432 (define_expand "post_store"
2433 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2434 (match_operand 1 "reg_or_0_operand" ""))
2437 (match_operand 2 "post_cint_operand" "")))])]
2443 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2446 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2450 (define_insn "post_stw"
2451 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2452 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2454 (plus:SI (match_dup 0)
2455 (match_operand:SI 2 "post_cint_operand" "")))]
2459 if (INTVAL (operands[2]) > 0)
2460 return \"{stwm|stw,ma} %r1,%2(%0)\";
2461 return \"{stws|stw},ma %r1,%2(%0)\";
2463 [(set_attr "type" "store")
2464 (set_attr "length" "4")])
2466 (define_insn "post_std"
2467 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2468 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2470 (plus:DI (match_dup 0)
2471 (match_operand:DI 2 "post_cint_operand" "")))]
2474 [(set_attr "type" "store")
2475 (set_attr "length" "4")])
2477 ;; For loading the address of a label while generating PIC code.
2478 ;; Note since this pattern can be created at reload time (via movsi), all
2479 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2481 [(set (match_operand 0 "pmode_register_operand" "=a")
2482 (match_operand 1 "pic_label_operand" ""))]
2488 xoperands[0] = operands[0];
2489 xoperands[1] = operands[1];
2490 xoperands[2] = gen_label_rtx ();
2492 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2493 CODE_LABEL_NUMBER (xoperands[2]));
2494 output_asm_insn (\"mfia %0\", xoperands);
2496 /* If we're trying to load the address of a label that happens to be
2497 close, then we can use a shorter sequence. */
2498 if (GET_CODE (operands[1]) == LABEL_REF
2499 && !LABEL_REF_NONLOCAL_P (operands[1])
2500 && INSN_ADDRESSES_SET_P ()
2501 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2502 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2503 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2506 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2507 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2511 [(set_attr "type" "multi")
2512 (set_attr "length" "12")]) ; 8 or 12
2515 [(set (match_operand 0 "pmode_register_operand" "=a")
2516 (match_operand 1 "pic_label_operand" ""))]
2522 xoperands[0] = operands[0];
2523 xoperands[1] = operands[1];
2524 xoperands[2] = gen_label_rtx ();
2526 output_asm_insn (\"bl .+8,%0\", xoperands);
2527 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2528 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2529 CODE_LABEL_NUMBER (xoperands[2]));
2531 /* If we're trying to load the address of a label that happens to be
2532 close, then we can use a shorter sequence. */
2533 if (GET_CODE (operands[1]) == LABEL_REF
2534 && !LABEL_REF_NONLOCAL_P (operands[1])
2535 && INSN_ADDRESSES_SET_P ()
2536 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2537 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2538 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2541 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2542 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2546 [(set_attr "type" "multi")
2547 (set_attr "length" "16")]) ; 12 or 16
2550 [(set (match_operand:SI 0 "register_operand" "=a")
2551 (plus:SI (match_operand:SI 1 "register_operand" "r")
2552 (high:SI (match_operand 2 "" ""))))]
2553 "symbolic_operand (operands[2], Pmode)
2554 && ! function_label_operand (operands[2], Pmode)
2557 [(set_attr "type" "binary")
2558 (set_attr "length" "4")])
2561 [(set (match_operand:DI 0 "register_operand" "=a")
2562 (plus:DI (match_operand:DI 1 "register_operand" "r")
2563 (high:DI (match_operand 2 "" ""))))]
2564 "symbolic_operand (operands[2], Pmode)
2565 && ! function_label_operand (operands[2], Pmode)
2569 [(set_attr "type" "binary")
2570 (set_attr "length" "4")])
2572 ;; Always use addil rather than ldil;add sequences. This allows the
2573 ;; HP linker to eliminate the dp relocation if the symbolic operand
2574 ;; lives in the TEXT space.
2576 [(set (match_operand:SI 0 "register_operand" "=a")
2577 (high:SI (match_operand 1 "" "")))]
2578 "symbolic_operand (operands[1], Pmode)
2579 && ! function_label_operand (operands[1], Pmode)
2580 && ! read_only_operand (operands[1], Pmode)
2584 if (TARGET_LONG_LOAD_STORE)
2585 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2587 return \"addil LR'%H1,%%r27\";
2589 [(set_attr "type" "binary")
2590 (set (attr "length")
2591 (if_then_else (not (match_test "TARGET_LONG_LOAD_STORE"))
2596 ;; This is for use in the prologue/epilogue code. We need it
2597 ;; to add large constants to a stack pointer or frame pointer.
2598 ;; Because of the additional %r1 pressure, we probably do not
2599 ;; want to use this in general code, so make it available
2600 ;; only after reload.
2602 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2603 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2604 (high:SI (match_operand 2 "const_int_operand" ""))))]
2608 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2609 [(set_attr "type" "binary,binary")
2610 (set_attr "length" "4,8")])
2613 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2614 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2615 (high:DI (match_operand 2 "const_int_operand" ""))))]
2616 "reload_completed && TARGET_64BIT"
2619 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2620 [(set_attr "type" "binary,binary")
2621 (set_attr "length" "4,8")])
2624 [(set (match_operand:SI 0 "register_operand" "=r")
2625 (high:SI (match_operand 1 "" "")))]
2626 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2627 && !is_function_label_plus_const (operands[1])"
2630 if (symbolic_operand (operands[1], Pmode))
2631 return \"ldil LR'%H1,%0\";
2633 return \"ldil L'%G1,%0\";
2635 [(set_attr "type" "move")
2636 (set_attr "length" "4")])
2639 [(set (match_operand:DI 0 "register_operand" "=r")
2640 (high:DI (match_operand 1 "const_int_operand" "")))]
2643 [(set_attr "type" "move")
2644 (set_attr "length" "4")])
2647 [(set (match_operand:DI 0 "register_operand" "=r")
2648 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2649 (match_operand:DI 2 "const_int_operand" "i")))]
2652 [(set_attr "type" "move")
2653 (set_attr "length" "4")])
2656 [(set (match_operand:SI 0 "register_operand" "=r")
2657 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2658 (match_operand:SI 2 "immediate_operand" "i")))]
2659 "!is_function_label_plus_const (operands[2])"
2662 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
2664 if (symbolic_operand (operands[2], Pmode))
2665 return \"ldo RR'%G2(%1),%0\";
2667 return \"ldo R'%G2(%1),%0\";
2669 [(set_attr "type" "move")
2670 (set_attr "length" "4")])
2672 ;; Now that a symbolic_address plus a constant is broken up early
2673 ;; in the compilation phase (for better CSE) we need a special
2674 ;; combiner pattern to load the symbolic address plus the constant
2675 ;; in only 2 instructions. (For cases where the symbolic address
2676 ;; was not a common subexpression.)
2678 [(set (match_operand:SI 0 "register_operand" "")
2679 (match_operand:SI 1 "symbolic_operand" ""))
2680 (clobber (match_operand:SI 2 "register_operand" ""))]
2681 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2682 [(set (match_dup 2) (high:SI (match_dup 1)))
2683 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2686 ;; hppa_legitimize_address goes to a great deal of trouble to
2687 ;; create addresses which use indexing. In some cases, this
2688 ;; is a lose because there isn't any store instructions which
2689 ;; allow indexed addresses (with integer register source).
2691 ;; These define_splits try to turn a 3 insn store into
2692 ;; a 2 insn store with some creative RTL rewriting.
2694 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2695 (match_operand:SI 1 "shadd_operand" ""))
2696 (plus:SI (match_operand:SI 2 "register_operand" "")
2697 (match_operand:SI 3 "const_int_operand" ""))))
2698 (match_operand:SI 4 "register_operand" ""))
2699 (clobber (match_operand:SI 5 "register_operand" ""))]
2701 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2703 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2707 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2708 (match_operand:SI 1 "shadd_operand" ""))
2709 (plus:SI (match_operand:SI 2 "register_operand" "")
2710 (match_operand:SI 3 "const_int_operand" ""))))
2711 (match_operand:HI 4 "register_operand" ""))
2712 (clobber (match_operand:SI 5 "register_operand" ""))]
2714 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2716 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2720 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2721 (match_operand:SI 1 "shadd_operand" ""))
2722 (plus:SI (match_operand:SI 2 "register_operand" "")
2723 (match_operand:SI 3 "const_int_operand" ""))))
2724 (match_operand:QI 4 "register_operand" ""))
2725 (clobber (match_operand:SI 5 "register_operand" ""))]
2727 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2729 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2732 (define_expand "movhi"
2733 [(set (match_operand:HI 0 "general_operand" "")
2734 (match_operand:HI 1 "general_operand" ""))]
2738 if (emit_move_sequence (operands, HImode, 0))
2742 ;; Handle HImode input reloads requiring a general register as a
2743 ;; scratch register.
2744 (define_expand "reload_inhi"
2745 [(set (match_operand:HI 0 "register_operand" "=Z")
2746 (match_operand:HI 1 "non_hard_reg_operand" ""))
2747 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2751 if (emit_move_sequence (operands, HImode, operands[2]))
2754 /* We don't want the clobber emitted, so handle this ourselves. */
2755 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2759 ;; Handle HImode output reloads requiring a general register as a
2760 ;; scratch register.
2761 (define_expand "reload_outhi"
2762 [(set (match_operand:HI 0 "non_hard_reg_operand" "")
2763 (match_operand:HI 1 "register_operand" "Z"))
2764 (clobber (match_operand:HI 2 "register_operand" "=&r"))]
2768 if (emit_move_sequence (operands, HImode, operands[2]))
2771 /* We don't want the clobber emitted, so handle this ourselves. */
2772 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2777 [(set (match_operand:HI 0 "move_dest_operand"
2778 "=r,r,r,r,r,Q,!*q,!r")
2779 (match_operand:HI 1 "move_src_operand"
2780 "r,J,N,K,RQ,rM,!rM,!*q"))]
2781 "(register_operand (operands[0], HImode)
2782 || reg_or_0_operand (operands[1], HImode))"
2787 {zdepi|depwi,z} %Z1,%0
2791 {mfctl|mfctl,w} %sar,%0"
2792 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2793 (set_attr "pa_combine_type" "addmove")
2794 (set_attr "length" "4,4,4,4,4,4,4,4")])
2797 [(set (match_operand:HI 0 "register_operand" "=r")
2798 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2799 (match_operand:SI 2 "int5_operand" "L"))))
2801 (plus:SI (match_dup 1) (match_dup 2)))]
2803 "{ldhs|ldh},mb %2(%1),%0"
2804 [(set_attr "type" "load")
2805 (set_attr "length" "4")])
2808 [(set (match_operand:HI 0 "register_operand" "=r")
2809 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2810 (match_operand:DI 2 "int5_operand" "L"))))
2812 (plus:DI (match_dup 1) (match_dup 2)))]
2815 [(set_attr "type" "load")
2816 (set_attr "length" "4")])
2818 ; And a zero extended variant.
2820 [(set (match_operand:DI 0 "register_operand" "=r")
2821 (zero_extend:DI (mem:HI
2823 (match_operand:DI 1 "register_operand" "+r")
2824 (match_operand:DI 2 "int5_operand" "L")))))
2826 (plus:DI (match_dup 1) (match_dup 2)))]
2829 [(set_attr "type" "load")
2830 (set_attr "length" "4")])
2833 [(set (match_operand:SI 0 "register_operand" "=r")
2834 (zero_extend:SI (mem:HI
2836 (match_operand:SI 1 "register_operand" "+r")
2837 (match_operand:SI 2 "int5_operand" "L")))))
2839 (plus:SI (match_dup 1) (match_dup 2)))]
2841 "{ldhs|ldh},mb %2(%1),%0"
2842 [(set_attr "type" "load")
2843 (set_attr "length" "4")])
2846 [(set (match_operand:SI 0 "register_operand" "=r")
2847 (zero_extend:SI (mem:HI
2849 (match_operand:DI 1 "register_operand" "+r")
2850 (match_operand:DI 2 "int5_operand" "L")))))
2852 (plus:DI (match_dup 1) (match_dup 2)))]
2855 [(set_attr "type" "load")
2856 (set_attr "length" "4")])
2859 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2860 (match_operand:SI 1 "int5_operand" "L")))
2861 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2863 (plus:SI (match_dup 0) (match_dup 1)))]
2865 "{sths|sth},mb %r2,%1(%0)"
2866 [(set_attr "type" "store")
2867 (set_attr "length" "4")])
2870 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2871 (match_operand:DI 1 "int5_operand" "L")))
2872 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2874 (plus:DI (match_dup 0) (match_dup 1)))]
2877 [(set_attr "type" "store")
2878 (set_attr "length" "4")])
2881 [(set (match_operand:HI 0 "register_operand" "=r")
2882 (plus:HI (match_operand:HI 1 "register_operand" "r")
2883 (match_operand 2 "const_int_operand" "J")))]
2886 [(set_attr "type" "binary")
2887 (set_attr "pa_combine_type" "addmove")
2888 (set_attr "length" "4")])
2890 (define_expand "movqi"
2891 [(set (match_operand:QI 0 "general_operand" "")
2892 (match_operand:QI 1 "general_operand" ""))]
2896 if (emit_move_sequence (operands, QImode, 0))
2900 ;; Handle QImode input reloads requiring a general register as a
2901 ;; scratch register.
2902 (define_expand "reload_inqi"
2903 [(set (match_operand:QI 0 "register_operand" "=Z")
2904 (match_operand:QI 1 "non_hard_reg_operand" ""))
2905 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
2909 if (emit_move_sequence (operands, QImode, operands[2]))
2912 /* We don't want the clobber emitted, so handle this ourselves. */
2913 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2917 ;; Handle QImode output reloads requiring a general register as a
2918 ;; scratch register.
2919 (define_expand "reload_outqi"
2920 [(set (match_operand:QI 0 "non_hard_reg_operand" "")
2921 (match_operand:QI 1 "register_operand" "Z"))
2922 (clobber (match_operand:QI 2 "register_operand" "=&r"))]
2926 if (emit_move_sequence (operands, QImode, operands[2]))
2929 /* We don't want the clobber emitted, so handle this ourselves. */
2930 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2935 [(set (match_operand:QI 0 "move_dest_operand"
2936 "=r,r,r,r,r,Q,!*q,!r")
2937 (match_operand:QI 1 "move_src_operand"
2938 "r,J,N,K,RQ,rM,!rM,!*q"))]
2939 "(register_operand (operands[0], QImode)
2940 || reg_or_0_operand (operands[1], QImode))"
2945 {zdepi|depwi,z} %Z1,%0
2949 {mfctl|mfctl,w} %%sar,%0"
2950 [(set_attr "type" "move,move,move,shift,load,store,move,move")
2951 (set_attr "pa_combine_type" "addmove")
2952 (set_attr "length" "4,4,4,4,4,4,4,4")])
2955 [(set (match_operand:QI 0 "register_operand" "=r")
2956 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2957 (match_operand:SI 2 "int5_operand" "L"))))
2958 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2960 "{ldbs|ldb},mb %2(%1),%0"
2961 [(set_attr "type" "load")
2962 (set_attr "length" "4")])
2965 [(set (match_operand:QI 0 "register_operand" "=r")
2966 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2967 (match_operand:DI 2 "int5_operand" "L"))))
2968 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
2971 [(set_attr "type" "load")
2972 (set_attr "length" "4")])
2974 ; Now the same thing with zero extensions.
2976 [(set (match_operand:DI 0 "register_operand" "=r")
2977 (zero_extend:DI (mem:QI (plus:DI
2978 (match_operand:DI 1 "register_operand" "+r")
2979 (match_operand:DI 2 "int5_operand" "L")))))
2980 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
2983 [(set_attr "type" "load")
2984 (set_attr "length" "4")])
2987 [(set (match_operand:SI 0 "register_operand" "=r")
2988 (zero_extend:SI (mem:QI (plus:SI
2989 (match_operand:SI 1 "register_operand" "+r")
2990 (match_operand:SI 2 "int5_operand" "L")))))
2991 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2993 "{ldbs|ldb},mb %2(%1),%0"
2994 [(set_attr "type" "load")
2995 (set_attr "length" "4")])
2998 [(set (match_operand:SI 0 "register_operand" "=r")
2999 (zero_extend:SI (mem:QI (plus:DI
3000 (match_operand:DI 1 "register_operand" "+r")
3001 (match_operand:DI 2 "int5_operand" "L")))))
3002 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3005 [(set_attr "type" "load")
3006 (set_attr "length" "4")])
3009 [(set (match_operand:HI 0 "register_operand" "=r")
3010 (zero_extend:HI (mem:QI (plus:SI
3011 (match_operand:SI 1 "register_operand" "+r")
3012 (match_operand:SI 2 "int5_operand" "L")))))
3013 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3015 "{ldbs|ldb},mb %2(%1),%0"
3016 [(set_attr "type" "load")
3017 (set_attr "length" "4")])
3020 [(set (match_operand:HI 0 "register_operand" "=r")
3021 (zero_extend:HI (mem:QI (plus:DI
3022 (match_operand:DI 1 "register_operand" "+r")
3023 (match_operand:DI 2 "int5_operand" "L")))))
3024 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3027 [(set_attr "type" "load")
3028 (set_attr "length" "4")])
3031 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3032 (match_operand:SI 1 "int5_operand" "L")))
3033 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3035 (plus:SI (match_dup 0) (match_dup 1)))]
3037 "{stbs|stb},mb %r2,%1(%0)"
3038 [(set_attr "type" "store")
3039 (set_attr "length" "4")])
3042 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3043 (match_operand:DI 1 "int5_operand" "L")))
3044 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3046 (plus:DI (match_dup 0) (match_dup 1)))]
3049 [(set_attr "type" "store")
3050 (set_attr "length" "4")])
3052 ;; The definition of this insn does not really explain what it does,
3053 ;; but it should suffice that anything generated as this insn will be
3054 ;; recognized as a movmemsi operation, and that it will not successfully
3055 ;; combine with anything.
3056 (define_expand "movmemsi"
3057 [(parallel [(set (match_operand:BLK 0 "" "")
3058 (match_operand:BLK 1 "" ""))
3059 (clobber (match_dup 4))
3060 (clobber (match_dup 5))
3061 (clobber (match_dup 6))
3062 (clobber (match_dup 7))
3063 (clobber (match_dup 8))
3064 (use (match_operand:SI 2 "arith14_operand" ""))
3065 (use (match_operand:SI 3 "const_int_operand" ""))])]
3066 "!TARGET_64BIT && optimize > 0"
3071 /* HP provides very fast block move library routine for the PA;
3072 this routine includes:
3074 4x4 byte at a time block moves,
3075 1x4 byte at a time with alignment checked at runtime with
3076 attempts to align the source and destination as needed
3079 With that in mind, here's the heuristics to try and guess when
3080 the inlined block move will be better than the library block
3083 If the size isn't constant, then always use the library routines.
3085 If the size is large in respect to the known alignment, then use
3086 the library routines.
3088 If the size is small in respect to the known alignment, then open
3089 code the copy (since that will lead to better scheduling).
3091 Else use the block move pattern. */
3093 /* Undetermined size, use the library routine. */
3094 if (GET_CODE (operands[2]) != CONST_INT)
3097 size = INTVAL (operands[2]);
3098 align = INTVAL (operands[3]);
3099 align = align > 4 ? 4 : (align ? align : 1);
3101 /* If size/alignment is large, then use the library routines. */
3102 if (size / align > 16)
3105 /* This does happen, but not often enough to worry much about. */
3106 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3109 /* Fall through means we're going to use our block move pattern. */
3111 = replace_equiv_address (operands[0],
3112 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3114 = replace_equiv_address (operands[1],
3115 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3116 operands[4] = gen_reg_rtx (SImode);
3117 operands[5] = gen_reg_rtx (SImode);
3118 operands[6] = gen_reg_rtx (SImode);
3119 operands[7] = gen_reg_rtx (SImode);
3120 operands[8] = gen_reg_rtx (SImode);
3123 ;; The operand constraints are written like this to support both compile-time
3124 ;; and run-time determined byte counts. The expander and output_block_move
3125 ;; only support compile-time determined counts at this time.
3127 ;; If the count is run-time determined, the register with the byte count
3128 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3130 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3131 ;; broke this semantic for pseudo registers. We can't use match_scratch
3132 ;; as this requires two registers in the class R1_REGS when the MEMs for
3133 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3134 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3135 ;; respectively. We then split or peephole optimize after reload.
3136 (define_insn "movmemsi_prereload"
3137 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3138 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3139 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3140 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3141 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3142 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3143 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3144 (use (match_operand:SI 4 "arith14_operand" "J,2")) ;byte count
3145 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3148 [(set_attr "type" "multi,multi")])
3151 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3152 (match_operand:BLK 1 "memory_operand" ""))
3153 (clobber (match_operand:SI 2 "register_operand" ""))
3154 (clobber (match_operand:SI 3 "register_operand" ""))
3155 (clobber (match_operand:SI 6 "register_operand" ""))
3156 (clobber (match_operand:SI 7 "register_operand" ""))
3157 (clobber (match_operand:SI 8 "register_operand" ""))
3158 (use (match_operand:SI 4 "arith14_operand" ""))
3159 (use (match_operand:SI 5 "const_int_operand" ""))])]
3160 "!TARGET_64BIT && reload_completed && !flag_peephole2
3161 && GET_CODE (operands[0]) == MEM
3162 && register_operand (XEXP (operands[0], 0), SImode)
3163 && GET_CODE (operands[1]) == MEM
3164 && register_operand (XEXP (operands[1], 0), SImode)"
3165 [(set (match_dup 7) (match_dup 9))
3166 (set (match_dup 8) (match_dup 10))
3167 (parallel [(set (match_dup 0) (match_dup 1))
3168 (clobber (match_dup 2))
3169 (clobber (match_dup 3))
3170 (clobber (match_dup 6))
3171 (clobber (match_dup 7))
3172 (clobber (match_dup 8))
3178 operands[9] = XEXP (operands[0], 0);
3179 operands[10] = XEXP (operands[1], 0);
3180 operands[0] = replace_equiv_address (operands[0], operands[7]);
3181 operands[1] = replace_equiv_address (operands[1], operands[8]);
3185 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3186 (match_operand:BLK 1 "memory_operand" ""))
3187 (clobber (match_operand:SI 2 "register_operand" ""))
3188 (clobber (match_operand:SI 3 "register_operand" ""))
3189 (clobber (match_operand:SI 6 "register_operand" ""))
3190 (clobber (match_operand:SI 7 "register_operand" ""))
3191 (clobber (match_operand:SI 8 "register_operand" ""))
3192 (use (match_operand:SI 4 "arith14_operand" ""))
3193 (use (match_operand:SI 5 "const_int_operand" ""))])]
3195 && GET_CODE (operands[0]) == MEM
3196 && register_operand (XEXP (operands[0], 0), SImode)
3197 && GET_CODE (operands[1]) == MEM
3198 && register_operand (XEXP (operands[1], 0), SImode)"
3199 [(parallel [(set (match_dup 0) (match_dup 1))
3200 (clobber (match_dup 2))
3201 (clobber (match_dup 3))
3202 (clobber (match_dup 6))
3203 (clobber (match_dup 7))
3204 (clobber (match_dup 8))
3210 rtx addr = XEXP (operands[0], 0);
3211 if (dead_or_set_p (curr_insn, addr))
3215 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3216 operands[0] = replace_equiv_address (operands[0], operands[7]);
3219 addr = XEXP (operands[1], 0);
3220 if (dead_or_set_p (curr_insn, addr))
3224 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3225 operands[1] = replace_equiv_address (operands[1], operands[8]);
3229 (define_insn "movmemsi_postreload"
3230 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3231 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3232 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3233 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3234 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3235 (clobber (match_dup 0))
3236 (clobber (match_dup 1))
3237 (use (match_operand:SI 4 "arith14_operand" "J,2")) ;byte count
3238 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3240 "!TARGET_64BIT && reload_completed"
3241 "* return output_block_move (operands, !which_alternative);"
3242 [(set_attr "type" "multi,multi")])
3244 (define_expand "movmemdi"
3245 [(parallel [(set (match_operand:BLK 0 "" "")
3246 (match_operand:BLK 1 "" ""))
3247 (clobber (match_dup 4))
3248 (clobber (match_dup 5))
3249 (clobber (match_dup 6))
3250 (clobber (match_dup 7))
3251 (clobber (match_dup 8))
3252 (use (match_operand:DI 2 "arith14_operand" ""))
3253 (use (match_operand:DI 3 "const_int_operand" ""))])]
3254 "TARGET_64BIT && optimize > 0"
3259 /* HP provides very fast block move library routine for the PA;
3260 this routine includes:
3262 4x4 byte at a time block moves,
3263 1x4 byte at a time with alignment checked at runtime with
3264 attempts to align the source and destination as needed
3267 With that in mind, here's the heuristics to try and guess when
3268 the inlined block move will be better than the library block
3271 If the size isn't constant, then always use the library routines.
3273 If the size is large in respect to the known alignment, then use
3274 the library routines.
3276 If the size is small in respect to the known alignment, then open
3277 code the copy (since that will lead to better scheduling).
3279 Else use the block move pattern. */
3281 /* Undetermined size, use the library routine. */
3282 if (GET_CODE (operands[2]) != CONST_INT)
3285 size = INTVAL (operands[2]);
3286 align = INTVAL (operands[3]);
3287 align = align > 8 ? 8 : (align ? align : 1);
3289 /* If size/alignment is large, then use the library routines. */
3290 if (size / align > 16)
3293 /* This does happen, but not often enough to worry much about. */
3294 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3297 /* Fall through means we're going to use our block move pattern. */
3299 = replace_equiv_address (operands[0],
3300 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3302 = replace_equiv_address (operands[1],
3303 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3304 operands[4] = gen_reg_rtx (DImode);
3305 operands[5] = gen_reg_rtx (DImode);
3306 operands[6] = gen_reg_rtx (DImode);
3307 operands[7] = gen_reg_rtx (DImode);
3308 operands[8] = gen_reg_rtx (DImode);
3311 ;; The operand constraints are written like this to support both compile-time
3312 ;; and run-time determined byte counts. The expander and output_block_move
3313 ;; only support compile-time determined counts at this time.
3315 ;; If the count is run-time determined, the register with the byte count
3316 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3318 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3319 ;; broke this semantic for pseudo registers. We can't use match_scratch
3320 ;; as this requires two registers in the class R1_REGS when the MEMs for
3321 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3322 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3323 ;; respectively. We then split or peephole optimize after reload.
3324 (define_insn "movmemdi_prereload"
3325 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3326 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3327 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3328 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3329 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3330 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3331 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3332 (use (match_operand:DI 4 "arith14_operand" "J,2")) ;byte count
3333 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3336 [(set_attr "type" "multi,multi")])
3339 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3340 (match_operand:BLK 1 "memory_operand" ""))
3341 (clobber (match_operand:DI 2 "register_operand" ""))
3342 (clobber (match_operand:DI 3 "register_operand" ""))
3343 (clobber (match_operand:DI 6 "register_operand" ""))
3344 (clobber (match_operand:DI 7 "register_operand" ""))
3345 (clobber (match_operand:DI 8 "register_operand" ""))
3346 (use (match_operand:DI 4 "arith14_operand" ""))
3347 (use (match_operand:DI 5 "const_int_operand" ""))])]
3348 "TARGET_64BIT && reload_completed && !flag_peephole2
3349 && GET_CODE (operands[0]) == MEM
3350 && register_operand (XEXP (operands[0], 0), DImode)
3351 && GET_CODE (operands[1]) == MEM
3352 && register_operand (XEXP (operands[1], 0), DImode)"
3353 [(set (match_dup 7) (match_dup 9))
3354 (set (match_dup 8) (match_dup 10))
3355 (parallel [(set (match_dup 0) (match_dup 1))
3356 (clobber (match_dup 2))
3357 (clobber (match_dup 3))
3358 (clobber (match_dup 6))
3359 (clobber (match_dup 7))
3360 (clobber (match_dup 8))
3366 operands[9] = XEXP (operands[0], 0);
3367 operands[10] = XEXP (operands[1], 0);
3368 operands[0] = replace_equiv_address (operands[0], operands[7]);
3369 operands[1] = replace_equiv_address (operands[1], operands[8]);
3373 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3374 (match_operand:BLK 1 "memory_operand" ""))
3375 (clobber (match_operand:DI 2 "register_operand" ""))
3376 (clobber (match_operand:DI 3 "register_operand" ""))
3377 (clobber (match_operand:DI 6 "register_operand" ""))
3378 (clobber (match_operand:DI 7 "register_operand" ""))
3379 (clobber (match_operand:DI 8 "register_operand" ""))
3380 (use (match_operand:DI 4 "arith14_operand" ""))
3381 (use (match_operand:DI 5 "const_int_operand" ""))])]
3383 && GET_CODE (operands[0]) == MEM
3384 && register_operand (XEXP (operands[0], 0), DImode)
3385 && GET_CODE (operands[1]) == MEM
3386 && register_operand (XEXP (operands[1], 0), DImode)"
3387 [(parallel [(set (match_dup 0) (match_dup 1))
3388 (clobber (match_dup 2))
3389 (clobber (match_dup 3))
3390 (clobber (match_dup 6))
3391 (clobber (match_dup 7))
3392 (clobber (match_dup 8))
3398 rtx addr = XEXP (operands[0], 0);
3399 if (dead_or_set_p (curr_insn, addr))
3403 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3404 operands[0] = replace_equiv_address (operands[0], operands[7]);
3407 addr = XEXP (operands[1], 0);
3408 if (dead_or_set_p (curr_insn, addr))
3412 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3413 operands[1] = replace_equiv_address (operands[1], operands[8]);
3417 (define_insn "movmemdi_postreload"
3418 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3419 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3420 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3421 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3422 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3423 (clobber (match_dup 0))
3424 (clobber (match_dup 1))
3425 (use (match_operand:DI 4 "arith14_operand" "J,2")) ;byte count
3426 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3428 "TARGET_64BIT && reload_completed"
3429 "* return output_block_move (operands, !which_alternative);"
3430 [(set_attr "type" "multi,multi")])
3432 (define_expand "setmemsi"
3433 [(parallel [(set (match_operand:BLK 0 "" "")
3434 (match_operand 2 "const_int_operand" ""))
3435 (clobber (match_dup 4))
3436 (clobber (match_dup 5))
3437 (use (match_operand:SI 1 "arith14_operand" ""))
3438 (use (match_operand:SI 3 "const_int_operand" ""))])]
3439 "!TARGET_64BIT && optimize > 0"
3444 /* If value to set is not zero, use the library routine. */
3445 if (operands[2] != const0_rtx)
3448 /* Undetermined size, use the library routine. */
3449 if (GET_CODE (operands[1]) != CONST_INT)
3452 size = INTVAL (operands[1]);
3453 align = INTVAL (operands[3]);
3454 align = align > 4 ? 4 : align;
3456 /* If size/alignment is large, then use the library routines. */
3457 if (size / align > 16)
3460 /* This does happen, but not often enough to worry much about. */
3461 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3464 /* Fall through means we're going to use our block clear pattern. */
3466 = replace_equiv_address (operands[0],
3467 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3468 operands[4] = gen_reg_rtx (SImode);
3469 operands[5] = gen_reg_rtx (SImode);
3472 (define_insn "clrmemsi_prereload"
3473 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3475 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3476 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3477 (use (match_operand:SI 2 "arith14_operand" "J,1")) ;byte count
3478 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3481 [(set_attr "type" "multi,multi")])
3484 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3486 (clobber (match_operand:SI 1 "register_operand" ""))
3487 (clobber (match_operand:SI 4 "register_operand" ""))
3488 (use (match_operand:SI 2 "arith14_operand" ""))
3489 (use (match_operand:SI 3 "const_int_operand" ""))])]
3490 "!TARGET_64BIT && reload_completed && !flag_peephole2
3491 && GET_CODE (operands[0]) == MEM
3492 && register_operand (XEXP (operands[0], 0), SImode)"
3493 [(set (match_dup 4) (match_dup 5))
3494 (parallel [(set (match_dup 0) (const_int 0))
3495 (clobber (match_dup 1))
3496 (clobber (match_dup 4))
3502 operands[5] = XEXP (operands[0], 0);
3503 operands[0] = replace_equiv_address (operands[0], operands[4]);
3507 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3509 (clobber (match_operand:SI 1 "register_operand" ""))
3510 (clobber (match_operand:SI 4 "register_operand" ""))
3511 (use (match_operand:SI 2 "arith14_operand" ""))
3512 (use (match_operand:SI 3 "const_int_operand" ""))])]
3514 && GET_CODE (operands[0]) == MEM
3515 && register_operand (XEXP (operands[0], 0), SImode)"
3516 [(parallel [(set (match_dup 0) (const_int 0))
3517 (clobber (match_dup 1))
3518 (clobber (match_dup 4))
3524 rtx addr = XEXP (operands[0], 0);
3525 if (dead_or_set_p (curr_insn, addr))
3529 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3530 operands[0] = replace_equiv_address (operands[0], operands[4]);
3534 (define_insn "clrmemsi_postreload"
3535 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3537 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3538 (clobber (match_dup 0))
3539 (use (match_operand:SI 2 "arith14_operand" "J,1")) ;byte count
3540 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3542 "!TARGET_64BIT && reload_completed"
3543 "* return output_block_clear (operands, !which_alternative);"
3544 [(set_attr "type" "multi,multi")])
3546 (define_expand "setmemdi"
3547 [(parallel [(set (match_operand:BLK 0 "" "")
3548 (match_operand 2 "const_int_operand" ""))
3549 (clobber (match_dup 4))
3550 (clobber (match_dup 5))
3551 (use (match_operand:DI 1 "arith14_operand" ""))
3552 (use (match_operand:DI 3 "const_int_operand" ""))])]
3553 "TARGET_64BIT && optimize > 0"
3558 /* If value to set is not zero, use the library routine. */
3559 if (operands[2] != const0_rtx)
3562 /* Undetermined size, use the library routine. */
3563 if (GET_CODE (operands[1]) != CONST_INT)
3566 size = INTVAL (operands[1]);
3567 align = INTVAL (operands[3]);
3568 align = align > 8 ? 8 : align;
3570 /* If size/alignment is large, then use the library routines. */
3571 if (size / align > 16)
3574 /* This does happen, but not often enough to worry much about. */
3575 if (size / align < MOVE_RATIO (optimize_insn_for_speed_p ()))
3578 /* Fall through means we're going to use our block clear pattern. */
3580 = replace_equiv_address (operands[0],
3581 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3582 operands[4] = gen_reg_rtx (DImode);
3583 operands[5] = gen_reg_rtx (DImode);
3586 (define_insn "clrmemdi_prereload"
3587 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3589 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3590 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3591 (use (match_operand:DI 2 "arith14_operand" "J,1")) ;byte count
3592 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3595 [(set_attr "type" "multi,multi")])
3598 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3600 (clobber (match_operand:DI 1 "register_operand" ""))
3601 (clobber (match_operand:DI 4 "register_operand" ""))
3602 (use (match_operand:DI 2 "arith14_operand" ""))
3603 (use (match_operand:DI 3 "const_int_operand" ""))])]
3604 "TARGET_64BIT && reload_completed && !flag_peephole2
3605 && GET_CODE (operands[0]) == MEM
3606 && register_operand (XEXP (operands[0], 0), DImode)"
3607 [(set (match_dup 4) (match_dup 5))
3608 (parallel [(set (match_dup 0) (const_int 0))
3609 (clobber (match_dup 1))
3610 (clobber (match_dup 4))
3616 operands[5] = XEXP (operands[0], 0);
3617 operands[0] = replace_equiv_address (operands[0], operands[4]);
3621 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3623 (clobber (match_operand:DI 1 "register_operand" ""))
3624 (clobber (match_operand:DI 4 "register_operand" ""))
3625 (use (match_operand:DI 2 "arith14_operand" ""))
3626 (use (match_operand:DI 3 "const_int_operand" ""))])]
3628 && GET_CODE (operands[0]) == MEM
3629 && register_operand (XEXP (operands[0], 0), DImode)"
3630 [(parallel [(set (match_dup 0) (const_int 0))
3631 (clobber (match_dup 1))
3632 (clobber (match_dup 4))
3638 rtx addr = XEXP (operands[0], 0);
3639 if (dead_or_set_p (curr_insn, addr))
3643 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3644 operands[0] = replace_equiv_address (operands[0], operands[4]);
3648 (define_insn "clrmemdi_postreload"
3649 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3651 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3652 (clobber (match_dup 0))
3653 (use (match_operand:DI 2 "arith14_operand" "J,1")) ;byte count
3654 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3656 "TARGET_64BIT && reload_completed"
3657 "* return output_block_clear (operands, !which_alternative);"
3658 [(set_attr "type" "multi,multi")])
3660 ;; Floating point move insns
3662 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3663 ;; to be reloaded by putting the constant into memory when
3664 ;; reg is a floating point register.
3666 ;; For integer registers we use ldil;ldo to set the appropriate
3669 ;; This must come before the movdf pattern, and it must be present
3670 ;; to handle obscure reloading cases.
3672 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3673 (match_operand:DF 1 "" "?F,m"))]
3674 "GET_CODE (operands[1]) == CONST_DOUBLE
3675 && operands[1] != CONST0_RTX (DFmode)
3677 && !TARGET_SOFT_FLOAT"
3678 "* return (which_alternative == 0 ? output_move_double (operands)
3679 : \"fldd%F1 %1,%0\");"
3680 [(set_attr "type" "move,fpload")
3681 (set_attr "length" "16,4")])
3683 (define_expand "movdf"
3684 [(set (match_operand:DF 0 "general_operand" "")
3685 (match_operand:DF 1 "general_operand" ""))]
3689 if (GET_CODE (operands[1]) == CONST_DOUBLE
3690 && operands[1] != CONST0_RTX (DFmode))
3692 /* Reject CONST_DOUBLE loads to all hard registers when
3693 generating 64-bit code and to floating point registers
3694 when generating 32-bit code. */
3695 if (REG_P (operands[0])
3696 && HARD_REGISTER_P (operands[0])
3697 && (TARGET_64BIT || REGNO (operands[0]) >= 32))
3701 operands[1] = force_const_mem (DFmode, operands[1]);
3704 if (emit_move_sequence (operands, DFmode, 0))
3708 ;; Handle DFmode input reloads requiring a general register as a
3709 ;; scratch register.
3710 (define_expand "reload_indf"
3711 [(set (match_operand:DF 0 "register_operand" "=Z")
3712 (match_operand:DF 1 "non_hard_reg_operand" ""))
3713 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3717 if (emit_move_sequence (operands, DFmode, operands[2]))
3720 /* We don't want the clobber emitted, so handle this ourselves. */
3721 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3725 ;; Handle DFmode output reloads requiring a general register as a
3726 ;; scratch register.
3727 (define_expand "reload_outdf"
3728 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3729 (match_operand:DF 1 "register_operand" "Z"))
3730 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3734 if (emit_move_sequence (operands, DFmode, operands[2]))
3737 /* We don't want the clobber emitted, so handle this ourselves. */
3738 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3743 [(set (match_operand:DF 0 "move_dest_operand"
3744 "=f,*r,Q,?o,?Q,f,*r,*r,?*r,?f")
3745 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3746 "fG,*rG,f,*r,*r,RQ,o,RQ,f,*r"))]
3747 "(register_operand (operands[0], DFmode)
3748 || reg_or_0_operand (operands[1], DFmode))
3749 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3750 && GET_CODE (operands[0]) == MEM)
3752 && !TARGET_SOFT_FLOAT"
3755 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3756 || operands[1] == CONST0_RTX (DFmode))
3757 && !(REG_P (operands[0]) && REG_P (operands[1])
3758 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
3759 return output_fp_move_double (operands);
3760 return output_move_double (operands);
3762 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,fpstore_load,store_fpload")
3763 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
3766 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3767 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3769 && !TARGET_DISABLE_INDEXING
3770 && reload_completed"
3772 [(set_attr "type" "fpstore")
3773 (set_attr "pa_combine_type" "addmove")
3774 (set_attr "length" "4")])
3777 [(set (match_operand:SI 0 "register_operand" "")
3778 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3780 (match_operand:SI 2 "register_operand" "")))
3781 (set (mem:DF (match_dup 0))
3782 (match_operand:DF 3 "register_operand" ""))]
3784 && !TARGET_DISABLE_INDEXING
3785 && REG_OK_FOR_BASE_P (operands[2])
3786 && FP_REGNO_P (REGNO (operands[3]))"
3787 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3789 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3794 [(set (match_operand:SI 0 "register_operand" "")
3795 (plus:SI (match_operand:SI 2 "register_operand" "")
3796 (mult:SI (match_operand:SI 1 "register_operand" "")
3798 (set (mem:DF (match_dup 0))
3799 (match_operand:DF 3 "register_operand" ""))]
3801 && !TARGET_DISABLE_INDEXING
3802 && REG_OK_FOR_BASE_P (operands[2])
3803 && FP_REGNO_P (REGNO (operands[3]))"
3804 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3806 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3811 [(set (match_operand:DI 0 "register_operand" "")
3812 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3814 (match_operand:DI 2 "register_operand" "")))
3815 (set (mem:DF (match_dup 0))
3816 (match_operand:DF 3 "register_operand" ""))]
3818 && !TARGET_DISABLE_INDEXING
3820 && REG_OK_FOR_BASE_P (operands[2])
3821 && FP_REGNO_P (REGNO (operands[3]))"
3822 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3824 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3829 [(set (match_operand:DI 0 "register_operand" "")
3830 (plus:DI (match_operand:DI 2 "register_operand" "")
3831 (mult:DI (match_operand:DI 1 "register_operand" "")
3833 (set (mem:DF (match_dup 0))
3834 (match_operand:DF 3 "register_operand" ""))]
3836 && !TARGET_DISABLE_INDEXING
3838 && REG_OK_FOR_BASE_P (operands[2])
3839 && FP_REGNO_P (REGNO (operands[3]))"
3840 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3842 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3847 [(set (match_operand:SI 0 "register_operand" "")
3848 (plus:SI (match_operand:SI 1 "register_operand" "")
3849 (match_operand:SI 2 "register_operand" "")))
3850 (set (mem:DF (match_dup 0))
3851 (match_operand:DF 3 "register_operand" ""))]
3853 && !TARGET_DISABLE_INDEXING
3854 && TARGET_NO_SPACE_REGS
3855 && REG_OK_FOR_INDEX_P (operands[1])
3856 && REG_OK_FOR_BASE_P (operands[2])
3857 && FP_REGNO_P (REGNO (operands[3]))"
3858 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3860 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3864 [(set (match_operand:SI 0 "register_operand" "")
3865 (plus:SI (match_operand:SI 1 "register_operand" "")
3866 (match_operand:SI 2 "register_operand" "")))
3867 (set (mem:DF (match_dup 0))
3868 (match_operand:DF 3 "register_operand" ""))]
3870 && !TARGET_DISABLE_INDEXING
3871 && TARGET_NO_SPACE_REGS
3872 && REG_OK_FOR_BASE_P (operands[1])
3873 && REG_OK_FOR_INDEX_P (operands[2])
3874 && FP_REGNO_P (REGNO (operands[3]))"
3875 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3877 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3881 [(set (match_operand:DI 0 "register_operand" "")
3882 (plus:DI (match_operand:DI 1 "register_operand" "")
3883 (match_operand:DI 2 "register_operand" "")))
3884 (set (mem:DF (match_dup 0))
3885 (match_operand:DF 3 "register_operand" ""))]
3887 && !TARGET_DISABLE_INDEXING
3889 && TARGET_NO_SPACE_REGS
3890 && REG_OK_FOR_INDEX_P (operands[1])
3891 && REG_OK_FOR_BASE_P (operands[2])
3892 && FP_REGNO_P (REGNO (operands[3]))"
3893 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3895 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3899 [(set (match_operand:DI 0 "register_operand" "")
3900 (plus:DI (match_operand:DI 1 "register_operand" "")
3901 (match_operand:DI 2 "register_operand" "")))
3902 (set (mem:DF (match_dup 0))
3903 (match_operand:DF 3 "register_operand" ""))]
3905 && !TARGET_DISABLE_INDEXING
3907 && TARGET_NO_SPACE_REGS
3908 && REG_OK_FOR_BASE_P (operands[1])
3909 && REG_OK_FOR_INDEX_P (operands[2])
3910 && FP_REGNO_P (REGNO (operands[3]))"
3911 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3913 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3917 [(set (match_operand:DF 0 "move_dest_operand"
3919 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3921 "(register_operand (operands[0], DFmode)
3922 || reg_or_0_operand (operands[1], DFmode))
3924 && TARGET_SOFT_FLOAT"
3927 return output_move_double (operands);
3929 [(set_attr "type" "move,store,store,load,load")
3930 (set_attr "length" "8,8,16,8,16")])
3933 [(set (match_operand:DF 0 "move_dest_operand"
3934 "=!*r,*r,*r,*r,*r,Q,f,f,T")
3935 (match_operand:DF 1 "move_src_operand"
3936 "!*r,J,N,K,RQ,*rG,fG,RT,f"))]
3937 "(register_operand (operands[0], DFmode)
3938 || reg_or_0_operand (operands[1], DFmode))
3939 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
3950 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
3951 (set_attr "pa_combine_type" "addmove")
3952 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3955 (define_expand "movdi"
3956 [(set (match_operand:DI 0 "general_operand" "")
3957 (match_operand:DI 1 "general_operand" ""))]
3961 /* Except for zero, we don't support loading a CONST_INT directly
3962 to a hard floating-point register since a scratch register is
3963 needed for the operation. While the operation could be handled
3964 before register allocation, the simplest solution is to fail. */
3966 && GET_CODE (operands[1]) == CONST_INT
3967 && operands[1] != CONST0_RTX (DImode)
3968 && REG_P (operands[0])
3969 && HARD_REGISTER_P (operands[0])
3970 && REGNO (operands[0]) >= 32)
3973 if (emit_move_sequence (operands, DImode, 0))
3977 ;; Handle DImode input reloads requiring %r1 as a scratch register.
3978 (define_expand "reload_indi_r1"
3979 [(set (match_operand:DI 0 "register_operand" "=Z")
3980 (match_operand:DI 1 "non_hard_reg_operand" ""))
3981 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
3985 if (emit_move_sequence (operands, DImode, operands[2]))
3988 /* We don't want the clobber emitted, so handle this ourselves. */
3989 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3993 ;; Handle DImode input reloads requiring a general register as a
3994 ;; scratch register.
3995 (define_expand "reload_indi"
3996 [(set (match_operand:DI 0 "register_operand" "=Z")
3997 (match_operand:DI 1 "non_hard_reg_operand" ""))
3998 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4002 if (emit_move_sequence (operands, DImode, operands[2]))
4005 /* We don't want the clobber emitted, so handle this ourselves. */
4006 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4010 ;; Handle DImode output reloads requiring a general register as a
4011 ;; scratch register.
4012 (define_expand "reload_outdi"
4013 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4014 (match_operand:DI 1 "register_operand" "Z"))
4015 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4019 if (emit_move_sequence (operands, DImode, operands[2]))
4022 /* We don't want the clobber emitted, so handle this ourselves. */
4023 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4028 [(set (match_operand:DI 0 "register_operand" "=r")
4029 (high:DI (match_operand 1 "" "")))]
4033 rtx op0 = operands[0];
4034 rtx op1 = operands[1];
4036 switch (GET_CODE (op1))
4039 #if HOST_BITS_PER_WIDE_INT <= 32
4040 operands[0] = operand_subword (op0, 1, 0, DImode);
4041 output_asm_insn (\"ldil L'%1,%0\", operands);
4043 operands[0] = operand_subword (op0, 0, 0, DImode);
4044 if (INTVAL (op1) < 0)
4045 output_asm_insn (\"ldi -1,%0\", operands);
4047 output_asm_insn (\"ldi 0,%0\", operands);
4049 operands[0] = operand_subword (op0, 1, 0, DImode);
4050 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4051 output_asm_insn (\"ldil L'%1,%0\", operands);
4053 operands[0] = operand_subword (op0, 0, 0, DImode);
4054 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4055 output_asm_insn (singlemove_string (operands), operands);
4060 operands[0] = operand_subword (op0, 1, 0, DImode);
4061 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4062 output_asm_insn (\"ldil L'%1,%0\", operands);
4064 operands[0] = operand_subword (op0, 0, 0, DImode);
4065 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4066 output_asm_insn (singlemove_string (operands), operands);
4074 [(set_attr "type" "move")
4075 (set_attr "length" "12")])
4078 [(set (match_operand:DI 0 "move_dest_operand"
4079 "=r,o,Q,r,r,r,*f,*f,T,?r,?*f")
4080 (match_operand:DI 1 "general_operand"
4081 "rM,r,r,o*R,Q,i,*fM,RT,*f,*f,r"))]
4082 "(register_operand (operands[0], DImode)
4083 || reg_or_0_operand (operands[1], DImode))
4085 && !TARGET_SOFT_FLOAT"
4088 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4089 || operands[1] == CONST0_RTX (DFmode))
4090 && !(REG_P (operands[0]) && REG_P (operands[1])
4091 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4092 return output_fp_move_double (operands);
4093 return output_move_double (operands);
4096 "move,store,store,load,load,multi,fpalu,fpload,fpstore,fpstore_load,store_fpload")
4097 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4100 [(set (match_operand:DI 0 "move_dest_operand"
4101 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4102 (match_operand:DI 1 "move_src_operand"
4103 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4104 "(register_operand (operands[0], DImode)
4105 || reg_or_0_operand (operands[1], DImode))
4106 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4116 {mfctl|mfctl,w} %%sar,%0
4120 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4121 (set_attr "pa_combine_type" "addmove")
4122 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4125 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4126 (match_operand:DI 1 "register_operand" "f"))]
4129 && !TARGET_DISABLE_INDEXING
4130 && reload_completed"
4132 [(set_attr "type" "fpstore")
4133 (set_attr "pa_combine_type" "addmove")
4134 (set_attr "length" "4")])
4137 [(set (match_operand:DI 0 "register_operand" "")
4138 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4140 (match_operand:DI 2 "register_operand" "")))
4141 (set (mem:DI (match_dup 0))
4142 (match_operand:DI 3 "register_operand" ""))]
4144 && !TARGET_DISABLE_INDEXING
4146 && REG_OK_FOR_BASE_P (operands[2])
4147 && FP_REGNO_P (REGNO (operands[3]))"
4148 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4150 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4155 [(set (match_operand:DI 0 "register_operand" "")
4156 (plus:DI (match_operand:DI 2 "register_operand" "")
4157 (mult:DI (match_operand:DI 1 "register_operand" "")
4159 (set (mem:DI (match_dup 0))
4160 (match_operand:DI 3 "register_operand" ""))]
4162 && !TARGET_DISABLE_INDEXING
4164 && REG_OK_FOR_BASE_P (operands[2])
4165 && FP_REGNO_P (REGNO (operands[3]))"
4166 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4168 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4173 [(set (match_operand:DI 0 "register_operand" "")
4174 (plus:DI (match_operand:DI 1 "register_operand" "")
4175 (match_operand:DI 2 "register_operand" "")))
4176 (set (mem:DI (match_dup 0))
4177 (match_operand:DI 3 "register_operand" ""))]
4179 && !TARGET_DISABLE_INDEXING
4181 && TARGET_NO_SPACE_REGS
4182 && REG_OK_FOR_INDEX_P (operands[1])
4183 && REG_OK_FOR_BASE_P (operands[2])
4184 && FP_REGNO_P (REGNO (operands[3]))"
4185 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4187 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4191 [(set (match_operand:DI 0 "register_operand" "")
4192 (plus:DI (match_operand:DI 1 "register_operand" "")
4193 (match_operand:DI 2 "register_operand" "")))
4194 (set (mem:DI (match_dup 0))
4195 (match_operand:DI 3 "register_operand" ""))]
4197 && !TARGET_DISABLE_INDEXING
4199 && TARGET_NO_SPACE_REGS
4200 && REG_OK_FOR_BASE_P (operands[1])
4201 && REG_OK_FOR_INDEX_P (operands[2])
4202 && FP_REGNO_P (REGNO (operands[3]))"
4203 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4205 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4209 [(set (match_operand:DI 0 "move_dest_operand"
4211 (match_operand:DI 1 "general_operand"
4213 "(register_operand (operands[0], DImode)
4214 || reg_or_0_operand (operands[1], DImode))
4216 && TARGET_SOFT_FLOAT"
4219 return output_move_double (operands);
4221 [(set_attr "type" "move,store,store,load,load,multi")
4222 (set_attr "length" "8,8,16,8,16,16")])
4225 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4226 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4227 (match_operand:DI 2 "immediate_operand" "i,i")))]
4231 /* Don't output a 64-bit constant, since we can't trust the assembler to
4232 handle it correctly. */
4233 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4234 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4235 else if (HOST_BITS_PER_WIDE_INT > 32
4236 && GET_CODE (operands[2]) == CONST_INT)
4237 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4238 if (which_alternative == 1)
4239 output_asm_insn (\"copy %1,%0\", operands);
4240 return \"ldo R'%G2(%R1),%R0\";
4242 [(set_attr "type" "move,move")
4243 (set_attr "length" "4,8")])
4245 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4246 ;; to be reloaded by putting the constant into memory when
4247 ;; reg is a floating point register.
4249 ;; For integer registers we use ldil;ldo to set the appropriate
4252 ;; This must come before the movsf pattern, and it must be present
4253 ;; to handle obscure reloading cases.
4255 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4256 (match_operand:SF 1 "" "?F,m"))]
4257 "GET_CODE (operands[1]) == CONST_DOUBLE
4258 && operands[1] != CONST0_RTX (SFmode)
4259 && ! TARGET_SOFT_FLOAT"
4260 "* return (which_alternative == 0 ? singlemove_string (operands)
4261 : \" fldw%F1 %1,%0\");"
4262 [(set_attr "type" "move,fpload")
4263 (set_attr "length" "8,4")])
4265 (define_expand "movsf"
4266 [(set (match_operand:SF 0 "general_operand" "")
4267 (match_operand:SF 1 "general_operand" ""))]
4271 /* Reject CONST_DOUBLE loads to floating point registers. */
4272 if (GET_CODE (operands[1]) == CONST_DOUBLE
4273 && operands[1] != CONST0_RTX (SFmode)
4274 && REG_P (operands[0])
4275 && HARD_REGISTER_P (operands[0])
4276 && REGNO (operands[0]) >= 32)
4279 if (emit_move_sequence (operands, SFmode, 0))
4283 ;; Handle SFmode input reloads requiring a general register as a
4284 ;; scratch register.
4285 (define_expand "reload_insf"
4286 [(set (match_operand:SF 0 "register_operand" "=Z")
4287 (match_operand:SF 1 "non_hard_reg_operand" ""))
4288 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4292 if (emit_move_sequence (operands, SFmode, operands[2]))
4295 /* We don't want the clobber emitted, so handle this ourselves. */
4296 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4300 ;; Handle SFmode output reloads requiring a general register as a
4301 ;; scratch register.
4302 (define_expand "reload_outsf"
4303 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4304 (match_operand:SF 1 "register_operand" "Z"))
4305 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4309 if (emit_move_sequence (operands, SFmode, operands[2]))
4312 /* We don't want the clobber emitted, so handle this ourselves. */
4313 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4318 [(set (match_operand:SF 0 "move_dest_operand"
4319 "=f,!*r,f,*r,Q,Q,?*r,?f")
4320 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4321 "fG,!*rG,RQ,RQ,f,*rG,f,*r"))]
4322 "(register_operand (operands[0], SFmode)
4323 || reg_or_0_operand (operands[1], SFmode))
4324 && !TARGET_SOFT_FLOAT
4333 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4334 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4335 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,fpstore_load,store_fpload")
4336 (set_attr "pa_combine_type" "addmove")
4337 (set_attr "length" "4,4,4,4,4,4,8,8")])
4340 [(set (match_operand:SF 0 "move_dest_operand"
4342 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4343 "fG,!*rG,RQ,RQ,f,*rG"))]
4344 "(register_operand (operands[0], SFmode)
4345 || reg_or_0_operand (operands[1], SFmode))
4346 && !TARGET_SOFT_FLOAT
4355 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4356 (set_attr "pa_combine_type" "addmove")
4357 (set_attr "length" "4,4,4,4,4,4")])
4360 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4361 (match_operand:SF 1 "register_operand" "f"))]
4363 && !TARGET_DISABLE_INDEXING
4364 && reload_completed"
4366 [(set_attr "type" "fpstore")
4367 (set_attr "pa_combine_type" "addmove")
4368 (set_attr "length" "4")])
4371 [(set (match_operand:SI 0 "register_operand" "")
4372 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4374 (match_operand:SI 2 "register_operand" "")))
4375 (set (mem:SF (match_dup 0))
4376 (match_operand:SF 3 "register_operand" ""))]
4378 && !TARGET_DISABLE_INDEXING
4379 && REG_OK_FOR_BASE_P (operands[2])
4380 && FP_REGNO_P (REGNO (operands[3]))"
4381 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4383 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4388 [(set (match_operand:SI 0 "register_operand" "")
4389 (plus:SI (match_operand:SI 2 "register_operand" "")
4390 (mult:SI (match_operand:SI 1 "register_operand" "")
4392 (set (mem:SF (match_dup 0))
4393 (match_operand:SF 3 "register_operand" ""))]
4395 && !TARGET_DISABLE_INDEXING
4396 && REG_OK_FOR_BASE_P (operands[2])
4397 && FP_REGNO_P (REGNO (operands[3]))"
4398 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4400 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4405 [(set (match_operand:DI 0 "register_operand" "")
4406 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4408 (match_operand:DI 2 "register_operand" "")))
4409 (set (mem:SF (match_dup 0))
4410 (match_operand:SF 3 "register_operand" ""))]
4412 && !TARGET_DISABLE_INDEXING
4414 && REG_OK_FOR_BASE_P (operands[2])
4415 && FP_REGNO_P (REGNO (operands[3]))"
4416 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4418 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4423 [(set (match_operand:DI 0 "register_operand" "")
4424 (plus:DI (match_operand:DI 2 "register_operand" "")
4425 (mult:DI (match_operand:DI 1 "register_operand" "")
4427 (set (mem:SF (match_dup 0))
4428 (match_operand:SF 3 "register_operand" ""))]
4430 && !TARGET_DISABLE_INDEXING
4432 && REG_OK_FOR_BASE_P (operands[2])
4433 && FP_REGNO_P (REGNO (operands[3]))"
4434 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4436 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4441 [(set (match_operand:SI 0 "register_operand" "")
4442 (plus:SI (match_operand:SI 1 "register_operand" "")
4443 (match_operand:SI 2 "register_operand" "")))
4444 (set (mem:SF (match_dup 0))
4445 (match_operand:SF 3 "register_operand" ""))]
4447 && !TARGET_DISABLE_INDEXING
4448 && TARGET_NO_SPACE_REGS
4449 && REG_OK_FOR_INDEX_P (operands[1])
4450 && REG_OK_FOR_BASE_P (operands[2])
4451 && FP_REGNO_P (REGNO (operands[3]))"
4452 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4454 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4458 [(set (match_operand:SI 0 "register_operand" "")
4459 (plus:SI (match_operand:SI 1 "register_operand" "")
4460 (match_operand:SI 2 "register_operand" "")))
4461 (set (mem:SF (match_dup 0))
4462 (match_operand:SF 3 "register_operand" ""))]
4464 && !TARGET_DISABLE_INDEXING
4465 && TARGET_NO_SPACE_REGS
4466 && REG_OK_FOR_BASE_P (operands[1])
4467 && REG_OK_FOR_INDEX_P (operands[2])
4468 && FP_REGNO_P (REGNO (operands[3]))"
4469 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4471 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4475 [(set (match_operand:DI 0 "register_operand" "")
4476 (plus:DI (match_operand:DI 1 "register_operand" "")
4477 (match_operand:DI 2 "register_operand" "")))
4478 (set (mem:SF (match_dup 0))
4479 (match_operand:SF 3 "register_operand" ""))]
4481 && !TARGET_DISABLE_INDEXING
4483 && TARGET_NO_SPACE_REGS
4484 && REG_OK_FOR_INDEX_P (operands[1])
4485 && REG_OK_FOR_BASE_P (operands[2])
4486 && FP_REGNO_P (REGNO (operands[3]))"
4487 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4489 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4493 [(set (match_operand:DI 0 "register_operand" "")
4494 (plus:DI (match_operand:DI 1 "register_operand" "")
4495 (match_operand:DI 2 "register_operand" "")))
4496 (set (mem:SF (match_dup 0))
4497 (match_operand:SF 3 "register_operand" ""))]
4499 && !TARGET_DISABLE_INDEXING
4501 && TARGET_NO_SPACE_REGS
4502 && REG_OK_FOR_BASE_P (operands[1])
4503 && REG_OK_FOR_INDEX_P (operands[2])
4504 && FP_REGNO_P (REGNO (operands[3]))"
4505 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4507 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4511 [(set (match_operand:SF 0 "move_dest_operand"
4513 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4515 "(register_operand (operands[0], SFmode)
4516 || reg_or_0_operand (operands[1], SFmode))
4517 && TARGET_SOFT_FLOAT"
4522 [(set_attr "type" "move,load,store")
4523 (set_attr "pa_combine_type" "addmove")
4524 (set_attr "length" "4,4,4")])
4528 ;;- zero extension instructions
4529 ;; We have define_expand for zero extension patterns to make sure the
4530 ;; operands get loaded into registers. The define_insns accept
4531 ;; memory operands. This gives us better overall code than just
4532 ;; having a pattern that does or does not accept memory operands.
4534 (define_expand "zero_extendqihi2"
4535 [(set (match_operand:HI 0 "register_operand" "")
4537 (match_operand:QI 1 "register_operand" "")))]
4542 [(set (match_operand:HI 0 "register_operand" "=r,r")
4544 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4545 "GET_CODE (operands[1]) != CONST_INT"
4547 {extru|extrw,u} %1,31,8,%0
4549 [(set_attr "type" "shift,load")
4550 (set_attr "length" "4,4")])
4552 (define_expand "zero_extendqisi2"
4553 [(set (match_operand:SI 0 "register_operand" "")
4555 (match_operand:QI 1 "register_operand" "")))]
4560 [(set (match_operand:SI 0 "register_operand" "=r,r")
4562 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4563 "GET_CODE (operands[1]) != CONST_INT"
4565 {extru|extrw,u} %1,31,8,%0
4567 [(set_attr "type" "shift,load")
4568 (set_attr "length" "4,4")])
4570 (define_expand "zero_extendhisi2"
4571 [(set (match_operand:SI 0 "register_operand" "")
4573 (match_operand:HI 1 "register_operand" "")))]
4578 [(set (match_operand:SI 0 "register_operand" "=r,r")
4580 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4581 "GET_CODE (operands[1]) != CONST_INT"
4583 {extru|extrw,u} %1,31,16,%0
4585 [(set_attr "type" "shift,load")
4586 (set_attr "length" "4,4")])
4588 (define_expand "zero_extendqidi2"
4589 [(set (match_operand:DI 0 "register_operand" "")
4591 (match_operand:QI 1 "register_operand" "")))]
4596 [(set (match_operand:DI 0 "register_operand" "=r,r")
4598 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4599 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4603 [(set_attr "type" "shift,load")
4604 (set_attr "length" "4,4")])
4606 (define_expand "zero_extendhidi2"
4607 [(set (match_operand:DI 0 "register_operand" "")
4609 (match_operand:HI 1 "register_operand" "")))]
4614 [(set (match_operand:DI 0 "register_operand" "=r,r")
4616 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4617 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4621 [(set_attr "type" "shift,load")
4622 (set_attr "length" "4,4")])
4624 (define_expand "zero_extendsidi2"
4625 [(set (match_operand:DI 0 "register_operand" "")
4627 (match_operand:SI 1 "register_operand" "")))]
4632 [(set (match_operand:DI 0 "register_operand" "=r,r")
4634 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4635 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4639 [(set_attr "type" "shift,load")
4640 (set_attr "length" "4,4")])
4642 ;;- sign extension instructions
4644 (define_insn "extendhisi2"
4645 [(set (match_operand:SI 0 "register_operand" "=r")
4646 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4648 "{extrs|extrw,s} %1,31,16,%0"
4649 [(set_attr "type" "shift")
4650 (set_attr "length" "4")])
4652 (define_insn "extendqihi2"
4653 [(set (match_operand:HI 0 "register_operand" "=r")
4654 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4656 "{extrs|extrw,s} %1,31,8,%0"
4657 [(set_attr "type" "shift")
4658 (set_attr "length" "4")])
4660 (define_insn "extendqisi2"
4661 [(set (match_operand:SI 0 "register_operand" "=r")
4662 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4664 "{extrs|extrw,s} %1,31,8,%0"
4665 [(set_attr "type" "shift")
4666 (set_attr "length" "4")])
4668 (define_insn "extendqidi2"
4669 [(set (match_operand:DI 0 "register_operand" "=r")
4670 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4672 "extrd,s %1,63,8,%0"
4673 [(set_attr "type" "shift")
4674 (set_attr "length" "4")])
4676 (define_insn "extendhidi2"
4677 [(set (match_operand:DI 0 "register_operand" "=r")
4678 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4680 "extrd,s %1,63,16,%0"
4681 [(set_attr "type" "shift")
4682 (set_attr "length" "4")])
4684 (define_insn "extendsidi2"
4685 [(set (match_operand:DI 0 "register_operand" "=r")
4686 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4688 "extrd,s %1,63,32,%0"
4689 [(set_attr "type" "shift")
4690 (set_attr "length" "4")])
4693 ;; Conversions between float and double.
4695 (define_insn "extendsfdf2"
4696 [(set (match_operand:DF 0 "register_operand" "=f")
4698 (match_operand:SF 1 "register_operand" "f")))]
4699 "! TARGET_SOFT_FLOAT"
4700 "{fcnvff|fcnv},sgl,dbl %1,%0"
4701 [(set_attr "type" "fpalu")
4702 (set_attr "length" "4")])
4704 (define_insn "truncdfsf2"
4705 [(set (match_operand:SF 0 "register_operand" "=f")
4707 (match_operand:DF 1 "register_operand" "f")))]
4708 "! TARGET_SOFT_FLOAT"
4709 "{fcnvff|fcnv},dbl,sgl %1,%0"
4710 [(set_attr "type" "fpalu")
4711 (set_attr "length" "4")])
4713 ;; Conversion between fixed point and floating point.
4714 ;; Note that among the fix-to-float insns
4715 ;; the ones that start with SImode come first.
4716 ;; That is so that an operand that is a CONST_INT
4717 ;; (and therefore lacks a specific machine mode).
4718 ;; will be recognized as SImode (which is always valid)
4719 ;; rather than as QImode or HImode.
4721 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4722 ;; to be reloaded by putting the constant into memory.
4723 ;; It must come before the more general floatsisf2 pattern.
4725 [(set (match_operand:SF 0 "register_operand" "=f")
4726 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4727 "! TARGET_SOFT_FLOAT"
4728 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4729 [(set_attr "type" "fpalu")
4730 (set_attr "length" "8")])
4732 (define_insn "floatsisf2"
4733 [(set (match_operand:SF 0 "register_operand" "=f")
4734 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4735 "! TARGET_SOFT_FLOAT"
4736 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4737 [(set_attr "type" "fpalu")
4738 (set_attr "length" "4")])
4740 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4741 ;; to be reloaded by putting the constant into memory.
4742 ;; It must come before the more general floatsidf2 pattern.
4744 [(set (match_operand:DF 0 "register_operand" "=f")
4745 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4746 "! TARGET_SOFT_FLOAT"
4747 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4748 [(set_attr "type" "fpalu")
4749 (set_attr "length" "8")])
4751 (define_insn "floatsidf2"
4752 [(set (match_operand:DF 0 "register_operand" "=f")
4753 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4754 "! TARGET_SOFT_FLOAT"
4755 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4756 [(set_attr "type" "fpalu")
4757 (set_attr "length" "4")])
4759 (define_expand "floatunssisf2"
4760 [(set (subreg:SI (match_dup 2) 4)
4761 (match_operand:SI 1 "register_operand" ""))
4762 (set (subreg:SI (match_dup 2) 0)
4764 (set (match_operand:SF 0 "register_operand" "")
4765 (float:SF (match_dup 2)))]
4766 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4771 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4774 operands[2] = gen_reg_rtx (DImode);
4777 (define_expand "floatunssidf2"
4778 [(set (subreg:SI (match_dup 2) 4)
4779 (match_operand:SI 1 "register_operand" ""))
4780 (set (subreg:SI (match_dup 2) 0)
4782 (set (match_operand:DF 0 "register_operand" "")
4783 (float:DF (match_dup 2)))]
4784 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4789 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4792 operands[2] = gen_reg_rtx (DImode);
4795 (define_insn "floatdisf2"
4796 [(set (match_operand:SF 0 "register_operand" "=f")
4797 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4798 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4799 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4800 [(set_attr "type" "fpalu")
4801 (set_attr "length" "4")])
4803 (define_insn "floatdidf2"
4804 [(set (match_operand:DF 0 "register_operand" "=f")
4805 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4806 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4807 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4808 [(set_attr "type" "fpalu")
4809 (set_attr "length" "4")])
4811 ;; Convert a float to an actual integer.
4812 ;; Truncation is performed as part of the conversion.
4814 (define_insn "fix_truncsfsi2"
4815 [(set (match_operand:SI 0 "register_operand" "=f")
4816 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4817 "! TARGET_SOFT_FLOAT"
4818 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4819 [(set_attr "type" "fpalu")
4820 (set_attr "length" "4")])
4822 (define_insn "fix_truncdfsi2"
4823 [(set (match_operand:SI 0 "register_operand" "=f")
4824 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4825 "! TARGET_SOFT_FLOAT"
4826 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4827 [(set_attr "type" "fpalu")
4828 (set_attr "length" "4")])
4830 (define_insn "fix_truncsfdi2"
4831 [(set (match_operand:DI 0 "register_operand" "=f")
4832 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4833 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4834 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4835 [(set_attr "type" "fpalu")
4836 (set_attr "length" "4")])
4838 (define_insn "fix_truncdfdi2"
4839 [(set (match_operand:DI 0 "register_operand" "=f")
4840 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4841 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4842 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4843 [(set_attr "type" "fpalu")
4844 (set_attr "length" "4")])
4846 (define_insn "floatunssidf2_pa20"
4847 [(set (match_operand:DF 0 "register_operand" "=f")
4848 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4849 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4851 [(set_attr "type" "fpalu")
4852 (set_attr "length" "4")])
4854 (define_insn "floatunssisf2_pa20"
4855 [(set (match_operand:SF 0 "register_operand" "=f")
4856 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4857 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4859 [(set_attr "type" "fpalu")
4860 (set_attr "length" "4")])
4862 (define_insn "floatunsdisf2"
4863 [(set (match_operand:SF 0 "register_operand" "=f")
4864 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4865 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4866 "fcnv,udw,sgl %1,%0"
4867 [(set_attr "type" "fpalu")
4868 (set_attr "length" "4")])
4870 (define_insn "floatunsdidf2"
4871 [(set (match_operand:DF 0 "register_operand" "=f")
4872 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4873 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4874 "fcnv,udw,dbl %1,%0"
4875 [(set_attr "type" "fpalu")
4876 (set_attr "length" "4")])
4878 (define_insn "fixuns_truncsfsi2"
4879 [(set (match_operand:SI 0 "register_operand" "=f")
4880 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4881 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4882 "fcnv,t,sgl,uw %1,%0"
4883 [(set_attr "type" "fpalu")
4884 (set_attr "length" "4")])
4886 (define_insn "fixuns_truncdfsi2"
4887 [(set (match_operand:SI 0 "register_operand" "=f")
4888 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4889 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4890 "fcnv,t,dbl,uw %1,%0"
4891 [(set_attr "type" "fpalu")
4892 (set_attr "length" "4")])
4894 (define_insn "fixuns_truncsfdi2"
4895 [(set (match_operand:DI 0 "register_operand" "=f")
4896 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4897 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4898 "fcnv,t,sgl,udw %1,%0"
4899 [(set_attr "type" "fpalu")
4900 (set_attr "length" "4")])
4902 (define_insn "fixuns_truncdfdi2"
4903 [(set (match_operand:DI 0 "register_operand" "=f")
4904 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4905 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4906 "fcnv,t,dbl,udw %1,%0"
4907 [(set_attr "type" "fpalu")
4908 (set_attr "length" "4")])
4910 ;;- arithmetic instructions
4912 (define_expand "adddi3"
4913 [(set (match_operand:DI 0 "register_operand" "")
4914 (plus:DI (match_operand:DI 1 "register_operand" "")
4915 (match_operand:DI 2 "adddi3_operand" "")))]
4920 [(set (match_operand:DI 0 "register_operand" "=r")
4921 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4922 (match_operand:DI 2 "arith11_operand" "rI")))]
4926 if (GET_CODE (operands[2]) == CONST_INT)
4928 if (INTVAL (operands[2]) >= 0)
4929 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4931 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4934 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4936 [(set_attr "type" "binary")
4937 (set_attr "length" "8")])
4940 [(set (match_operand:DI 0 "register_operand" "=r,r")
4941 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4942 (match_operand:DI 2 "arith14_operand" "r,J")))]
4947 [(set_attr "type" "binary,binary")
4948 (set_attr "pa_combine_type" "addmove")
4949 (set_attr "length" "4,4")])
4952 [(set (match_operand:DI 0 "register_operand" "=r")
4953 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4954 (match_operand:DI 2 "register_operand" "r")))]
4957 [(set_attr "type" "binary")
4958 (set_attr "length" "4")])
4961 [(set (match_operand:SI 0 "register_operand" "=r")
4962 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4963 (match_operand:SI 2 "register_operand" "r")))]
4966 [(set_attr "type" "binary")
4967 (set_attr "length" "4")])
4969 (define_expand "addvdi3"
4970 [(parallel [(set (match_operand:DI 0 "register_operand" "")
4971 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
4972 (match_operand:DI 2 "arith11_operand" "")))
4973 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4974 (sign_extend:TI (match_dup 2)))
4975 (sign_extend:TI (plus:DI (match_dup 1)
4982 [(set (match_operand:DI 0 "register_operand" "=r,r")
4983 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
4984 (match_operand:DI 2 "arith11_operand" "r,I")))
4985 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
4986 (sign_extend:TI (match_dup 2)))
4987 (sign_extend:TI (plus:DI (match_dup 1)
4993 addi,tsv,* %2,%1,%0"
4994 [(set_attr "type" "binary,binary")
4995 (set_attr "length" "4,4")])
4998 [(set (match_operand:DI 0 "register_operand" "=r")
4999 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
5000 (match_operand:DI 2 "arith11_operand" "rI")))
5001 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5002 (sign_extend:TI (match_dup 2)))
5003 (sign_extend:TI (plus:DI (match_dup 1)
5009 if (GET_CODE (operands[2]) == CONST_INT)
5011 if (INTVAL (operands[2]) >= 0)
5012 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5014 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5017 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5019 [(set_attr "type" "binary")
5020 (set_attr "length" "8")])
5022 ;; define_splits to optimize cases of adding a constant integer
5023 ;; to a register when the constant does not fit in 14 bits. */
5025 [(set (match_operand:SI 0 "register_operand" "")
5026 (plus:SI (match_operand:SI 1 "register_operand" "")
5027 (match_operand:SI 2 "const_int_operand" "")))
5028 (clobber (match_operand:SI 4 "register_operand" ""))]
5029 "! cint_ok_for_move (INTVAL (operands[2]))
5030 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5031 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5032 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5035 int val = INTVAL (operands[2]);
5036 int low = (val < 0) ? -0x2000 : 0x1fff;
5037 int rest = val - low;
5039 operands[2] = GEN_INT (rest);
5040 operands[3] = GEN_INT (low);
5044 [(set (match_operand:SI 0 "register_operand" "")
5045 (plus:SI (match_operand:SI 1 "register_operand" "")
5046 (match_operand:SI 2 "const_int_operand" "")))
5047 (clobber (match_operand:SI 4 "register_operand" ""))]
5048 "! cint_ok_for_move (INTVAL (operands[2]))"
5049 [(set (match_dup 4) (match_dup 2))
5050 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
5054 HOST_WIDE_INT intval = INTVAL (operands[2]);
5056 /* Try dividing the constant by 2, then 4, and finally 8 to see
5057 if we can get a constant which can be loaded into a register
5058 in a single instruction (cint_ok_for_move).
5060 If that fails, try to negate the constant and subtract it
5061 from our input operand. */
5062 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
5064 operands[2] = GEN_INT (intval / 2);
5065 operands[3] = const2_rtx;
5067 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
5069 operands[2] = GEN_INT (intval / 4);
5070 operands[3] = GEN_INT (4);
5072 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
5074 operands[2] = GEN_INT (intval / 8);
5075 operands[3] = GEN_INT (8);
5077 else if (cint_ok_for_move (-intval))
5079 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5080 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5087 (define_insn "addsi3"
5088 [(set (match_operand:SI 0 "register_operand" "=r,r")
5089 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5090 (match_operand:SI 2 "arith14_operand" "r,J")))]
5093 {addl|add,l} %1,%2,%0
5095 [(set_attr "type" "binary,binary")
5096 (set_attr "pa_combine_type" "addmove")
5097 (set_attr "length" "4,4")])
5099 (define_insn "addvsi3"
5100 [(set (match_operand:SI 0 "register_operand" "=r,r")
5101 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5102 (match_operand:SI 2 "arith11_operand" "r,I")))
5103 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5104 (sign_extend:DI (match_dup 2)))
5105 (sign_extend:DI (plus:SI (match_dup 1)
5110 {addo|add,tsv} %2,%1,%0
5111 {addio|addi,tsv} %2,%1,%0"
5112 [(set_attr "type" "binary,binary")
5113 (set_attr "length" "4,4")])
5115 (define_expand "subdi3"
5116 [(set (match_operand:DI 0 "register_operand" "")
5117 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5118 (match_operand:DI 2 "reg_or_0_operand" "")))]
5123 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5124 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5125 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5131 [(set_attr "type" "binary,binary,move")
5132 (set_attr "length" "4,4,4")])
5135 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5136 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5137 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5141 if (GET_CODE (operands[1]) == CONST_INT)
5143 if (INTVAL (operands[1]) >= 0)
5144 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5146 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5149 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5151 [(set_attr "type" "binary")
5152 (set (attr "length")
5153 (if_then_else (eq_attr "alternative" "0")
5155 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5160 (define_expand "subvdi3"
5161 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5162 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5163 (match_operand:DI 2 "reg_or_0_operand" "")))
5164 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5165 (sign_extend:TI (match_dup 2)))
5166 (sign_extend:TI (minus:DI (match_dup 1)
5173 [(set (match_operand:DI 0 "register_operand" "=r,r")
5174 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5175 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5176 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5177 (sign_extend:TI (match_dup 2)))
5178 (sign_extend:TI (minus:DI (match_dup 1)
5183 {subo|sub,tsv} %1,%2,%0
5184 {subio|subi,tsv} %1,%2,%0"
5185 [(set_attr "type" "binary,binary")
5186 (set_attr "length" "4,4")])
5189 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5190 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5191 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5192 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5193 (sign_extend:TI (match_dup 2)))
5194 (sign_extend:TI (minus:DI (match_dup 1)
5200 if (GET_CODE (operands[1]) == CONST_INT)
5202 if (INTVAL (operands[1]) >= 0)
5203 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5205 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5208 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5210 [(set_attr "type" "binary,binary")
5211 (set (attr "length")
5212 (if_then_else (eq_attr "alternative" "0")
5214 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5219 (define_expand "subsi3"
5220 [(set (match_operand:SI 0 "register_operand" "")
5221 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5222 (match_operand:SI 2 "register_operand" "")))]
5227 [(set (match_operand:SI 0 "register_operand" "=r,r")
5228 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5229 (match_operand:SI 2 "register_operand" "r,r")))]
5234 [(set_attr "type" "binary,binary")
5235 (set_attr "length" "4,4")])
5238 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5239 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5240 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5246 [(set_attr "type" "binary,binary,move")
5247 (set_attr "length" "4,4,4")])
5249 (define_insn "subvsi3"
5250 [(set (match_operand:SI 0 "register_operand" "=r,r")
5251 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5252 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5253 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5254 (sign_extend:DI (match_dup 2)))
5255 (sign_extend:DI (minus:SI (match_dup 1)
5260 {subo|sub,tsv} %1,%2,%0
5261 {subio|subi,tsv} %1,%2,%0"
5262 [(set_attr "type" "binary,binary")
5263 (set_attr "length" "4,4")])
5265 ;; Clobbering a "register_operand" instead of a match_scratch
5266 ;; in operand3 of millicode calls avoids spilling %r1 and
5267 ;; produces better code.
5269 ;; The mulsi3 insns set up registers for the millicode call.
5270 (define_expand "mulsi3"
5271 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5272 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5273 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5274 (clobber (match_dup 3))
5275 (clobber (reg:SI 26))
5276 (clobber (reg:SI 25))
5277 (clobber (match_dup 4))])
5278 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5282 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5283 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5285 rtx scratch = gen_reg_rtx (DImode);
5286 operands[1] = force_reg (SImode, operands[1]);
5287 operands[2] = force_reg (SImode, operands[2]);
5288 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5289 emit_insn (gen_movsi (operands[0],
5290 gen_rtx_SUBREG (SImode, scratch,
5291 GET_MODE_SIZE (SImode))));
5294 operands[3] = gen_reg_rtx (SImode);
5297 (define_insn "umulsidi3"
5298 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5299 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5300 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5301 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5303 [(set_attr "type" "fpmuldbl")
5304 (set_attr "length" "4")])
5307 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5308 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5309 (match_operand:DI 2 "uint32_operand" "f")))]
5310 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5312 [(set_attr "type" "fpmuldbl")
5313 (set_attr "length" "4")])
5316 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5317 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5318 (match_operand:DI 2 "uint32_operand" "f")))]
5319 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5321 [(set_attr "type" "fpmuldbl")
5322 (set_attr "length" "4")])
5325 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5326 (clobber (match_operand:SI 0 "register_operand" "=a"))
5327 (clobber (reg:SI 26))
5328 (clobber (reg:SI 25))
5329 (clobber (reg:SI 31))]
5331 "* return output_mul_insn (0, insn);"
5332 [(set_attr "type" "milli")
5333 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5336 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5337 (clobber (match_operand:SI 0 "register_operand" "=a"))
5338 (clobber (reg:SI 26))
5339 (clobber (reg:SI 25))
5340 (clobber (reg:SI 2))]
5342 "* return output_mul_insn (0, insn);"
5343 [(set_attr "type" "milli")
5344 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5346 (define_expand "muldi3"
5347 [(set (match_operand:DI 0 "register_operand" "")
5348 (mult:DI (match_operand:DI 1 "register_operand" "")
5349 (match_operand:DI 2 "register_operand" "")))]
5350 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5353 rtx low_product = gen_reg_rtx (DImode);
5354 rtx cross_product1 = gen_reg_rtx (DImode);
5355 rtx cross_product2 = gen_reg_rtx (DImode);
5356 rtx cross_scratch = gen_reg_rtx (DImode);
5357 rtx cross_product = gen_reg_rtx (DImode);
5358 rtx op1l, op1r, op2l, op2r;
5359 rtx op1shifted, op2shifted;
5361 op1shifted = gen_reg_rtx (DImode);
5362 op2shifted = gen_reg_rtx (DImode);
5363 op1l = gen_reg_rtx (SImode);
5364 op1r = gen_reg_rtx (SImode);
5365 op2l = gen_reg_rtx (SImode);
5366 op2r = gen_reg_rtx (SImode);
5368 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5370 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5372 op1r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[1], 4));
5373 op2r = force_reg (SImode, gen_rtx_SUBREG (SImode, operands[2], 4));
5374 op1l = force_reg (SImode, gen_rtx_SUBREG (SImode, op1shifted, 4));
5375 op2l = force_reg (SImode, gen_rtx_SUBREG (SImode, op2shifted, 4));
5377 /* Emit multiplies for the cross products. */
5378 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5379 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5381 /* Emit a multiply for the low sub-word. */
5382 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5384 /* Sum the cross products and shift them into proper position. */
5385 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5386 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5388 /* Add the cross product to the low product and store the result
5389 into the output operand . */
5390 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5394 ;;; Division and mod.
5395 (define_expand "divsi3"
5396 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5397 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5398 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5399 (clobber (match_dup 3))
5400 (clobber (match_dup 4))
5401 (clobber (reg:SI 26))
5402 (clobber (reg:SI 25))
5403 (clobber (match_dup 5))])
5404 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5408 operands[3] = gen_reg_rtx (SImode);
5411 operands[5] = gen_rtx_REG (SImode, 2);
5412 operands[4] = operands[5];
5416 operands[5] = gen_rtx_REG (SImode, 31);
5417 operands[4] = gen_reg_rtx (SImode);
5419 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5425 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5426 (clobber (match_operand:SI 1 "register_operand" "=a"))
5427 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5428 (clobber (reg:SI 26))
5429 (clobber (reg:SI 25))
5430 (clobber (reg:SI 31))]
5433 return output_div_insn (operands, 0, insn);"
5434 [(set_attr "type" "milli")
5435 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5439 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5440 (clobber (match_operand:SI 1 "register_operand" "=a"))
5441 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5442 (clobber (reg:SI 26))
5443 (clobber (reg:SI 25))
5444 (clobber (reg:SI 2))]
5447 return output_div_insn (operands, 0, insn);"
5448 [(set_attr "type" "milli")
5449 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5451 (define_expand "udivsi3"
5452 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5453 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5454 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5455 (clobber (match_dup 3))
5456 (clobber (match_dup 4))
5457 (clobber (reg:SI 26))
5458 (clobber (reg:SI 25))
5459 (clobber (match_dup 5))])
5460 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5464 operands[3] = gen_reg_rtx (SImode);
5468 operands[5] = gen_rtx_REG (SImode, 2);
5469 operands[4] = operands[5];
5473 operands[5] = gen_rtx_REG (SImode, 31);
5474 operands[4] = gen_reg_rtx (SImode);
5476 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5482 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5483 (clobber (match_operand:SI 1 "register_operand" "=a"))
5484 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5485 (clobber (reg:SI 26))
5486 (clobber (reg:SI 25))
5487 (clobber (reg:SI 31))]
5490 return output_div_insn (operands, 1, insn);"
5491 [(set_attr "type" "milli")
5492 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5496 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5497 (clobber (match_operand:SI 1 "register_operand" "=a"))
5498 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5499 (clobber (reg:SI 26))
5500 (clobber (reg:SI 25))
5501 (clobber (reg:SI 2))]
5504 return output_div_insn (operands, 1, insn);"
5505 [(set_attr "type" "milli")
5506 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5508 (define_expand "modsi3"
5509 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5510 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5511 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5512 (clobber (match_dup 3))
5513 (clobber (match_dup 4))
5514 (clobber (reg:SI 26))
5515 (clobber (reg:SI 25))
5516 (clobber (match_dup 5))])
5517 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5523 operands[5] = gen_rtx_REG (SImode, 2);
5524 operands[4] = operands[5];
5528 operands[5] = gen_rtx_REG (SImode, 31);
5529 operands[4] = gen_reg_rtx (SImode);
5531 operands[3] = gen_reg_rtx (SImode);
5535 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5536 (clobber (match_operand:SI 0 "register_operand" "=a"))
5537 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5538 (clobber (reg:SI 26))
5539 (clobber (reg:SI 25))
5540 (clobber (reg:SI 31))]
5543 return output_mod_insn (0, insn);"
5544 [(set_attr "type" "milli")
5545 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5548 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5549 (clobber (match_operand:SI 0 "register_operand" "=a"))
5550 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5551 (clobber (reg:SI 26))
5552 (clobber (reg:SI 25))
5553 (clobber (reg:SI 2))]
5556 return output_mod_insn (0, insn);"
5557 [(set_attr "type" "milli")
5558 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5560 (define_expand "umodsi3"
5561 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5562 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5563 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5564 (clobber (match_dup 3))
5565 (clobber (match_dup 4))
5566 (clobber (reg:SI 26))
5567 (clobber (reg:SI 25))
5568 (clobber (match_dup 5))])
5569 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5575 operands[5] = gen_rtx_REG (SImode, 2);
5576 operands[4] = operands[5];
5580 operands[5] = gen_rtx_REG (SImode, 31);
5581 operands[4] = gen_reg_rtx (SImode);
5583 operands[3] = gen_reg_rtx (SImode);
5587 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5588 (clobber (match_operand:SI 0 "register_operand" "=a"))
5589 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5590 (clobber (reg:SI 26))
5591 (clobber (reg:SI 25))
5592 (clobber (reg:SI 31))]
5595 return output_mod_insn (1, insn);"
5596 [(set_attr "type" "milli")
5597 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5600 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5601 (clobber (match_operand:SI 0 "register_operand" "=a"))
5602 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5603 (clobber (reg:SI 26))
5604 (clobber (reg:SI 25))
5605 (clobber (reg:SI 2))]
5608 return output_mod_insn (1, insn);"
5609 [(set_attr "type" "milli")
5610 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5612 ;;- and instructions
5613 ;; We define DImode `and` so with DImode `not` we can get
5614 ;; DImode `andn`. Other combinations are possible.
5616 (define_expand "anddi3"
5617 [(set (match_operand:DI 0 "register_operand" "")
5618 (and:DI (match_operand:DI 1 "register_operand" "")
5619 (match_operand:DI 2 "and_operand" "")))]
5623 /* Both operands must be register operands. */
5624 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
5629 [(set (match_operand:DI 0 "register_operand" "=r")
5630 (and:DI (match_operand:DI 1 "register_operand" "%r")
5631 (match_operand:DI 2 "register_operand" "r")))]
5633 "and %1,%2,%0\;and %R1,%R2,%R0"
5634 [(set_attr "type" "binary")
5635 (set_attr "length" "8")])
5638 [(set (match_operand:DI 0 "register_operand" "=r,r")
5639 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5640 (match_operand:DI 2 "and_operand" "rO,P")))]
5642 "* return output_64bit_and (operands); "
5643 [(set_attr "type" "binary")
5644 (set_attr "length" "4")])
5646 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5647 ; constant with ldil;ldo.
5648 (define_insn "andsi3"
5649 [(set (match_operand:SI 0 "register_operand" "=r,r")
5650 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5651 (match_operand:SI 2 "and_operand" "rO,P")))]
5653 "* return output_and (operands); "
5654 [(set_attr "type" "binary,shift")
5655 (set_attr "length" "4,4")])
5658 [(set (match_operand:DI 0 "register_operand" "=r")
5659 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5660 (match_operand:DI 2 "register_operand" "r")))]
5662 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5663 [(set_attr "type" "binary")
5664 (set_attr "length" "8")])
5667 [(set (match_operand:DI 0 "register_operand" "=r")
5668 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5669 (match_operand:DI 2 "register_operand" "r")))]
5672 [(set_attr "type" "binary")
5673 (set_attr "length" "4")])
5676 [(set (match_operand:SI 0 "register_operand" "=r")
5677 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5678 (match_operand:SI 2 "register_operand" "r")))]
5681 [(set_attr "type" "binary")
5682 (set_attr "length" "4")])
5684 (define_expand "iordi3"
5685 [(set (match_operand:DI 0 "register_operand" "")
5686 (ior:DI (match_operand:DI 1 "register_operand" "")
5687 (match_operand:DI 2 "reg_or_cint_ior_operand" "")))]
5691 /* Both operands must be register operands. */
5692 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
5697 [(set (match_operand:DI 0 "register_operand" "=r")
5698 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5699 (match_operand:DI 2 "register_operand" "r")))]
5701 "or %1,%2,%0\;or %R1,%R2,%R0"
5702 [(set_attr "type" "binary")
5703 (set_attr "length" "8")])
5706 [(set (match_operand:DI 0 "register_operand" "=r,r")
5707 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5708 (match_operand:DI 2 "cint_ior_operand" "M,i")))]
5710 "* return output_64bit_ior (operands); "
5711 [(set_attr "type" "binary,shift")
5712 (set_attr "length" "4,4")])
5715 [(set (match_operand:DI 0 "register_operand" "=r")
5716 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5717 (match_operand:DI 2 "register_operand" "r")))]
5720 [(set_attr "type" "binary")
5721 (set_attr "length" "4")])
5723 ;; Need a define_expand because we've run out of CONST_OK... characters.
5724 (define_expand "iorsi3"
5725 [(set (match_operand:SI 0 "register_operand" "")
5726 (ior:SI (match_operand:SI 1 "register_operand" "")
5727 (match_operand:SI 2 "reg_or_cint_ior_operand" "")))]
5732 [(set (match_operand:SI 0 "register_operand" "=r,r")
5733 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5734 (match_operand:SI 2 "cint_ior_operand" "M,i")))]
5736 "* return output_ior (operands); "
5737 [(set_attr "type" "binary,shift")
5738 (set_attr "length" "4,4")])
5741 [(set (match_operand:SI 0 "register_operand" "=r")
5742 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5743 (match_operand:SI 2 "register_operand" "r")))]
5746 [(set_attr "type" "binary")
5747 (set_attr "length" "4")])
5749 (define_expand "xordi3"
5750 [(set (match_operand:DI 0 "register_operand" "")
5751 (xor:DI (match_operand:DI 1 "register_operand" "")
5752 (match_operand:DI 2 "register_operand" "")))]
5759 [(set (match_operand:DI 0 "register_operand" "=r")
5760 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5761 (match_operand:DI 2 "register_operand" "r")))]
5763 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5764 [(set_attr "type" "binary")
5765 (set_attr "length" "8")])
5768 [(set (match_operand:DI 0 "register_operand" "=r")
5769 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5770 (match_operand:DI 2 "register_operand" "r")))]
5773 [(set_attr "type" "binary")
5774 (set_attr "length" "4")])
5776 (define_insn "xorsi3"
5777 [(set (match_operand:SI 0 "register_operand" "=r")
5778 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5779 (match_operand:SI 2 "register_operand" "r")))]
5782 [(set_attr "type" "binary")
5783 (set_attr "length" "4")])
5785 (define_expand "negdi2"
5786 [(set (match_operand:DI 0 "register_operand" "")
5787 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5792 [(set (match_operand:DI 0 "register_operand" "=r")
5793 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5795 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5796 [(set_attr "type" "unary")
5797 (set_attr "length" "8")])
5800 [(set (match_operand:DI 0 "register_operand" "=r")
5801 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5804 [(set_attr "type" "unary")
5805 (set_attr "length" "4")])
5807 (define_expand "negvdi2"
5808 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5809 (neg:DI (match_operand:DI 1 "register_operand" "")))
5810 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5811 (sign_extend:TI (neg:DI (match_dup 1))))
5817 [(set (match_operand:DI 0 "register_operand" "=r")
5818 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5819 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5820 (sign_extend:TI (neg:DI (match_dup 1))))
5823 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
5824 [(set_attr "type" "unary")
5825 (set_attr "length" "8")])
5828 [(set (match_operand:DI 0 "register_operand" "=r")
5829 (neg:DI (match_operand:DI 1 "register_operand" "r")))
5830 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
5831 (sign_extend:TI (neg:DI (match_dup 1))))
5834 "sub,tsv %%r0,%1,%0"
5835 [(set_attr "type" "unary")
5836 (set_attr "length" "4")])
5838 (define_insn "negsi2"
5839 [(set (match_operand:SI 0 "register_operand" "=r")
5840 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5843 [(set_attr "type" "unary")
5844 (set_attr "length" "4")])
5846 (define_insn "negvsi2"
5847 [(set (match_operand:SI 0 "register_operand" "=r")
5848 (neg:SI (match_operand:SI 1 "register_operand" "r")))
5849 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
5850 (sign_extend:DI (neg:SI (match_dup 1))))
5853 "{subo|sub,tsv} %%r0,%1,%0"
5854 [(set_attr "type" "unary")
5855 (set_attr "length" "4")])
5857 (define_expand "one_cmpldi2"
5858 [(set (match_operand:DI 0 "register_operand" "")
5859 (not:DI (match_operand:DI 1 "register_operand" "")))]
5866 [(set (match_operand:DI 0 "register_operand" "=r")
5867 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5869 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5870 [(set_attr "type" "unary")
5871 (set_attr "length" "8")])
5874 [(set (match_operand:DI 0 "register_operand" "=r")
5875 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5878 [(set_attr "type" "unary")
5879 (set_attr "length" "4")])
5881 (define_insn "one_cmplsi2"
5882 [(set (match_operand:SI 0 "register_operand" "=r")
5883 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5886 [(set_attr "type" "unary")
5887 (set_attr "length" "4")])
5889 ;; Floating point arithmetic instructions.
5891 (define_insn "adddf3"
5892 [(set (match_operand:DF 0 "register_operand" "=f")
5893 (plus:DF (match_operand:DF 1 "register_operand" "f")
5894 (match_operand:DF 2 "register_operand" "f")))]
5895 "! TARGET_SOFT_FLOAT"
5897 [(set_attr "type" "fpalu")
5898 (set_attr "pa_combine_type" "faddsub")
5899 (set_attr "length" "4")])
5901 (define_insn "addsf3"
5902 [(set (match_operand:SF 0 "register_operand" "=f")
5903 (plus:SF (match_operand:SF 1 "register_operand" "f")
5904 (match_operand:SF 2 "register_operand" "f")))]
5905 "! TARGET_SOFT_FLOAT"
5907 [(set_attr "type" "fpalu")
5908 (set_attr "pa_combine_type" "faddsub")
5909 (set_attr "length" "4")])
5911 (define_insn "subdf3"
5912 [(set (match_operand:DF 0 "register_operand" "=f")
5913 (minus:DF (match_operand:DF 1 "register_operand" "f")
5914 (match_operand:DF 2 "register_operand" "f")))]
5915 "! TARGET_SOFT_FLOAT"
5917 [(set_attr "type" "fpalu")
5918 (set_attr "pa_combine_type" "faddsub")
5919 (set_attr "length" "4")])
5921 (define_insn "subsf3"
5922 [(set (match_operand:SF 0 "register_operand" "=f")
5923 (minus:SF (match_operand:SF 1 "register_operand" "f")
5924 (match_operand:SF 2 "register_operand" "f")))]
5925 "! TARGET_SOFT_FLOAT"
5927 [(set_attr "type" "fpalu")
5928 (set_attr "pa_combine_type" "faddsub")
5929 (set_attr "length" "4")])
5931 (define_insn "muldf3"
5932 [(set (match_operand:DF 0 "register_operand" "=f")
5933 (mult:DF (match_operand:DF 1 "register_operand" "f")
5934 (match_operand:DF 2 "register_operand" "f")))]
5935 "! TARGET_SOFT_FLOAT"
5937 [(set_attr "type" "fpmuldbl")
5938 (set_attr "pa_combine_type" "fmpy")
5939 (set_attr "length" "4")])
5941 (define_insn "mulsf3"
5942 [(set (match_operand:SF 0 "register_operand" "=f")
5943 (mult:SF (match_operand:SF 1 "register_operand" "f")
5944 (match_operand:SF 2 "register_operand" "f")))]
5945 "! TARGET_SOFT_FLOAT"
5947 [(set_attr "type" "fpmulsgl")
5948 (set_attr "pa_combine_type" "fmpy")
5949 (set_attr "length" "4")])
5951 (define_insn "divdf3"
5952 [(set (match_operand:DF 0 "register_operand" "=f")
5953 (div:DF (match_operand:DF 1 "register_operand" "f")
5954 (match_operand:DF 2 "register_operand" "f")))]
5955 "! TARGET_SOFT_FLOAT"
5957 [(set_attr "type" "fpdivdbl")
5958 (set_attr "length" "4")])
5960 (define_insn "divsf3"
5961 [(set (match_operand:SF 0 "register_operand" "=f")
5962 (div:SF (match_operand:SF 1 "register_operand" "f")
5963 (match_operand:SF 2 "register_operand" "f")))]
5964 "! TARGET_SOFT_FLOAT"
5966 [(set_attr "type" "fpdivsgl")
5967 (set_attr "length" "4")])
5969 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5970 ;; negation can be done by subtracting from plus zero. However, this
5971 ;; violates the IEEE standard when negating plus and minus zero.
5972 ;; The slow path toggles the sign bit in the general registers.
5973 (define_expand "negdf2"
5974 [(set (match_operand:DF 0 "register_operand" "")
5975 (neg:DF (match_operand:DF 1 "register_operand" "")))]
5976 "!TARGET_SOFT_FLOAT"
5978 if (TARGET_PA_20 || !flag_signed_zeros)
5979 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5981 emit_insn (gen_negdf2_slow (operands[0], operands[1]));
5985 (define_insn "negdf2_slow"
5986 [(set (match_operand:DF 0 "register_operand" "=r")
5987 (neg:DF (match_operand:DF 1 "register_operand" "r")))]
5988 "!TARGET_SOFT_FLOAT && !TARGET_PA_20"
5991 if (rtx_equal_p (operands[0], operands[1]))
5992 return \"and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0\";
5994 return \"and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0\;copy %R1,%R0\";
5996 [(set_attr "type" "multi")
5997 (set (attr "length")
5998 (if_then_else (match_test "rtx_equal_p (operands[0], operands[1])")
6002 (define_insn "negdf2_fast"
6003 [(set (match_operand:DF 0 "register_operand" "=f")
6004 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
6005 "!TARGET_SOFT_FLOAT"
6009 return \"fneg,dbl %1,%0\";
6011 return \"fsub,dbl %%fr0,%1,%0\";
6013 [(set_attr "type" "fpalu")
6014 (set_attr "length" "4")])
6016 (define_expand "negsf2"
6017 [(set (match_operand:SF 0 "register_operand" "")
6018 (neg:SF (match_operand:SF 1 "register_operand" "")))]
6019 "!TARGET_SOFT_FLOAT"
6021 if (TARGET_PA_20 || !flag_signed_zeros)
6022 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
6024 emit_insn (gen_negsf2_slow (operands[0], operands[1]));
6028 (define_insn "negsf2_slow"
6029 [(set (match_operand:SF 0 "register_operand" "=r")
6030 (neg:SF (match_operand:SF 1 "register_operand" "r")))]
6031 "!TARGET_SOFT_FLOAT && !TARGET_PA_20"
6032 "and,< %1,%1,%0\;depi,tr 1,0,1,%0\;depi 0,0,1,%0"
6033 [(set_attr "type" "multi")
6034 (set_attr "length" "12")])
6036 (define_insn "negsf2_fast"
6037 [(set (match_operand:SF 0 "register_operand" "=f")
6038 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6039 "!TARGET_SOFT_FLOAT"
6043 return \"fneg,sgl %1,%0\";
6045 return \"fsub,sgl %%fr0,%1,%0\";
6047 [(set_attr "type" "fpalu")
6048 (set_attr "length" "4")])
6050 (define_insn "absdf2"
6051 [(set (match_operand:DF 0 "register_operand" "=f")
6052 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6053 "! TARGET_SOFT_FLOAT"
6055 [(set_attr "type" "fpalu")
6056 (set_attr "length" "4")])
6058 (define_insn "abssf2"
6059 [(set (match_operand:SF 0 "register_operand" "=f")
6060 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6061 "! TARGET_SOFT_FLOAT"
6063 [(set_attr "type" "fpalu")
6064 (set_attr "length" "4")])
6066 (define_insn "sqrtdf2"
6067 [(set (match_operand:DF 0 "register_operand" "=f")
6068 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6069 "! TARGET_SOFT_FLOAT"
6071 [(set_attr "type" "fpsqrtdbl")
6072 (set_attr "length" "4")])
6074 (define_insn "sqrtsf2"
6075 [(set (match_operand:SF 0 "register_operand" "=f")
6076 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6077 "! TARGET_SOFT_FLOAT"
6079 [(set_attr "type" "fpsqrtsgl")
6080 (set_attr "length" "4")])
6082 ;; PA 2.0 floating point instructions
6085 (define_insn "fmadf4"
6086 [(set (match_operand:DF 0 "register_operand" "=f")
6087 (fma:DF (match_operand:DF 1 "register_operand" "f")
6088 (match_operand:DF 2 "register_operand" "f")
6089 (match_operand:DF 3 "register_operand" "f")))]
6090 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6091 "fmpyfadd,dbl %1,%2,%3,%0"
6092 [(set_attr "type" "fpmuldbl")
6093 (set_attr "length" "4")])
6095 (define_insn "fmasf4"
6096 [(set (match_operand:SF 0 "register_operand" "=f")
6097 (fma:SF (match_operand:SF 1 "register_operand" "f")
6098 (match_operand:SF 2 "register_operand" "f")
6099 (match_operand:SF 3 "register_operand" "f")))]
6100 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6101 "fmpyfadd,sgl %1,%2,%3,%0"
6102 [(set_attr "type" "fpmulsgl")
6103 (set_attr "length" "4")])
6105 ; fmpynfadd patterns
6106 (define_insn "fnmadf4"
6107 [(set (match_operand:DF 0 "register_operand" "=f")
6108 (fma:DF (neg:DF (match_operand:DF 1 "register_operand" "f"))
6109 (match_operand:DF 2 "register_operand" "f")
6110 (match_operand:DF 3 "register_operand" "f")))]
6111 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6112 "fmpynfadd,dbl %1,%2,%3,%0"
6113 [(set_attr "type" "fpmuldbl")
6114 (set_attr "length" "4")])
6116 (define_insn "fnmasf4"
6117 [(set (match_operand:SF 0 "register_operand" "=f")
6118 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
6119 (match_operand:SF 2 "register_operand" "f")
6120 (match_operand:SF 3 "register_operand" "f")))]
6121 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6122 "fmpynfadd,sgl %1,%2,%3,%0"
6123 [(set_attr "type" "fpmulsgl")
6124 (set_attr "length" "4")])
6128 [(set (match_operand:DF 0 "register_operand" "=f")
6129 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6130 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6132 [(set_attr "type" "fpalu")
6133 (set_attr "length" "4")])
6136 [(set (match_operand:SF 0 "register_operand" "=f")
6137 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6138 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6140 [(set_attr "type" "fpalu")
6141 (set_attr "length" "4")])
6144 [(set (match_operand:DF 0 "register_operand" "=f")
6145 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6146 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6147 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6148 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6150 [(set_attr "type" "fpalu")
6151 (set_attr "length" "8")])
6154 [(set (match_operand:DF 0 "register_operand" "")
6155 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6156 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6157 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6158 [(set (match_dup 2) (abs:DF (match_dup 1)))
6159 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6163 [(set (match_operand:SF 0 "register_operand" "=f")
6164 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6165 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6166 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6167 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6169 [(set_attr "type" "fpalu")
6170 (set_attr "length" "8")])
6173 [(set (match_operand:SF 0 "register_operand" "")
6174 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6175 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6176 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6177 [(set (match_dup 2) (abs:SF (match_dup 1)))
6178 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6181 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6182 ;; instruction if we can ignore the sign of zero.
6184 [(set (match_operand:DF 0 "register_operand" "=f")
6185 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6186 (match_operand:DF 2 "register_operand" "f"))))]
6187 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6188 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6189 [(set_attr "type" "fpmuldbl")
6190 (set_attr "length" "4")])
6193 [(set (match_operand:SF 0 "register_operand" "=f")
6194 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6195 (match_operand:SF 2 "register_operand" "f"))))]
6196 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6197 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6198 [(set_attr "type" "fpmuldbl")
6199 (set_attr "length" "4")])
6202 [(set (match_operand:DF 0 "register_operand" "=f")
6203 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6204 (match_operand:DF 2 "register_operand" "f"))))
6205 (set (match_operand:DF 3 "register_operand" "=&f")
6206 (mult:DF (match_dup 1) (match_dup 2)))]
6207 "(!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros
6208 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6209 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6211 [(set_attr "type" "fpmuldbl")
6212 (set_attr "length" "8")])
6215 [(set (match_operand:DF 0 "register_operand" "")
6216 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6217 (match_operand:DF 2 "register_operand" ""))))
6218 (set (match_operand:DF 3 "register_operand" "")
6219 (mult:DF (match_dup 1) (match_dup 2)))]
6220 "!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros"
6221 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6222 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6226 [(set (match_operand:SF 0 "register_operand" "=f")
6227 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6228 (match_operand:SF 2 "register_operand" "f"))))
6229 (set (match_operand:SF 3 "register_operand" "=&f")
6230 (mult:SF (match_dup 1) (match_dup 2)))]
6231 "(!TARGET_SOFT_FLOAT && TARGET_PA_20 && !flag_signed_zeros
6232 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6233 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6235 [(set_attr "type" "fpmuldbl")
6236 (set_attr "length" "8")])
6239 [(set (match_operand:SF 0 "register_operand" "")
6240 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6241 (match_operand:SF 2 "register_operand" ""))))
6242 (set (match_operand:SF 3 "register_operand" "")
6243 (mult:SF (match_dup 1) (match_dup 2)))]
6244 "!TARGET_SOFT_FLOAT && TARGET_PA_20&& !flag_signed_zeros"
6245 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6246 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6249 ;;- Shift instructions
6251 ;; Optimized special case of shifting.
6254 [(set (match_operand:SI 0 "register_operand" "=r")
6255 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6259 [(set_attr "type" "load")
6260 (set_attr "length" "4")])
6263 [(set (match_operand:SI 0 "register_operand" "=r")
6264 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6268 [(set_attr "type" "load")
6269 (set_attr "length" "4")])
6272 [(set (match_operand:SI 0 "register_operand" "=r")
6273 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6274 (match_operand:SI 3 "shadd_operand" ""))
6275 (match_operand:SI 1 "register_operand" "r")))]
6277 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6278 [(set_attr "type" "binary")
6279 (set_attr "length" "4")])
6282 [(set (match_operand:DI 0 "register_operand" "=r")
6283 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6284 (match_operand:DI 3 "shadd_operand" ""))
6285 (match_operand:DI 1 "register_operand" "r")))]
6287 "shladd,l %2,%O3,%1,%0"
6288 [(set_attr "type" "binary")
6289 (set_attr "length" "4")])
6291 (define_expand "ashlsi3"
6292 [(set (match_operand:SI 0 "register_operand" "")
6293 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6294 (match_operand:SI 2 "arith32_operand" "")))]
6298 if (GET_CODE (operands[2]) != CONST_INT)
6300 rtx temp = gen_reg_rtx (SImode);
6301 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6302 if (GET_CODE (operands[1]) == CONST_INT)
6303 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6305 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6308 /* Make sure both inputs are not constants,
6309 there are no patterns for that. */
6310 operands[1] = force_reg (SImode, operands[1]);
6314 [(set (match_operand:SI 0 "register_operand" "=r")
6315 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6316 (match_operand:SI 2 "const_int_operand" "n")))]
6318 "{zdep|depw,z} %1,%P2,%L2,%0"
6319 [(set_attr "type" "shift")
6320 (set_attr "length" "4")])
6322 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6323 ; Doing it like this makes slightly better code since reload can
6324 ; replace a register with a known value in range -16..15 with a
6325 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6326 ; but since we have no more CONST_OK... characters, that is not
6328 (define_insn "zvdep32"
6329 [(set (match_operand:SI 0 "register_operand" "=r,r")
6330 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6331 (minus:SI (const_int 31)
6332 (match_operand:SI 2 "register_operand" "q,q"))))]
6335 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6336 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6337 [(set_attr "type" "shift,shift")
6338 (set_attr "length" "4,4")])
6340 (define_insn "zvdep_imm32"
6341 [(set (match_operand:SI 0 "register_operand" "=r")
6342 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6343 (minus:SI (const_int 31)
6344 (match_operand:SI 2 "register_operand" "q"))))]
6348 int x = INTVAL (operands[1]);
6349 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6350 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6351 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6353 [(set_attr "type" "shift")
6354 (set_attr "length" "4")])
6356 (define_insn "vdepi_ior"
6357 [(set (match_operand:SI 0 "register_operand" "=r")
6358 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6359 (minus:SI (const_int 31)
6360 (match_operand:SI 2 "register_operand" "q")))
6361 (match_operand:SI 3 "register_operand" "0")))]
6362 ; accept ...0001...1, can this be generalized?
6363 "exact_log2 (INTVAL (operands[1]) + 1) > 0"
6366 int x = INTVAL (operands[1]);
6367 operands[2] = GEN_INT (exact_log2 (x + 1));
6368 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6370 [(set_attr "type" "shift")
6371 (set_attr "length" "4")])
6373 (define_insn "vdepi_and"
6374 [(set (match_operand:SI 0 "register_operand" "=r")
6375 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6376 (minus:SI (const_int 31)
6377 (match_operand:SI 2 "register_operand" "q")))
6378 (match_operand:SI 3 "register_operand" "0")))]
6379 ; this can be generalized...!
6380 "INTVAL (operands[1]) == -2"
6383 int x = INTVAL (operands[1]);
6384 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6385 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6387 [(set_attr "type" "shift")
6388 (set_attr "length" "4")])
6390 (define_expand "ashldi3"
6391 [(set (match_operand:DI 0 "register_operand" "")
6392 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6393 (match_operand:DI 2 "arith32_operand" "")))]
6397 if (GET_CODE (operands[2]) != CONST_INT)
6399 rtx temp = gen_reg_rtx (DImode);
6400 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6401 if (GET_CODE (operands[1]) == CONST_INT)
6402 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6404 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6407 /* Make sure both inputs are not constants,
6408 there are no patterns for that. */
6409 operands[1] = force_reg (DImode, operands[1]);
6413 [(set (match_operand:DI 0 "register_operand" "=r")
6414 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6415 (match_operand:DI 2 "const_int_operand" "n")))]
6417 "depd,z %1,%p2,%Q2,%0"
6418 [(set_attr "type" "shift")
6419 (set_attr "length" "4")])
6421 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6422 ; Doing it like this makes slightly better code since reload can
6423 ; replace a register with a known value in range -16..15 with a
6424 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6425 ; but since we have no more CONST_OK... characters, that is not
6427 (define_insn "zvdep64"
6428 [(set (match_operand:DI 0 "register_operand" "=r,r")
6429 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6430 (minus:DI (const_int 63)
6431 (match_operand:DI 2 "register_operand" "q,q"))))]
6434 depd,z %1,%%sar,64,%0
6435 depdi,z %1,%%sar,64,%0"
6436 [(set_attr "type" "shift,shift")
6437 (set_attr "length" "4,4")])
6439 (define_insn "zvdep_imm64"
6440 [(set (match_operand:DI 0 "register_operand" "=r")
6441 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6442 (minus:DI (const_int 63)
6443 (match_operand:DI 2 "register_operand" "q"))))]
6447 int x = INTVAL (operands[1]);
6448 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6449 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6450 return \"depdi,z %1,%%sar,%2,%0\";
6452 [(set_attr "type" "shift")
6453 (set_attr "length" "4")])
6456 [(set (match_operand:DI 0 "register_operand" "=r")
6457 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6458 (minus:DI (const_int 63)
6459 (match_operand:DI 2 "register_operand" "q")))
6460 (match_operand:DI 3 "register_operand" "0")))]
6461 ; accept ...0001...1, can this be generalized?
6462 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) > 0"
6465 int x = INTVAL (operands[1]);
6466 operands[2] = GEN_INT (exact_log2 (x + 1));
6467 return \"depdi -1,%%sar,%2,%0\";
6469 [(set_attr "type" "shift")
6470 (set_attr "length" "4")])
6473 [(set (match_operand:DI 0 "register_operand" "=r")
6474 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6475 (minus:DI (const_int 63)
6476 (match_operand:DI 2 "register_operand" "q")))
6477 (match_operand:DI 3 "register_operand" "0")))]
6478 ; this can be generalized...!
6479 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6482 int x = INTVAL (operands[1]);
6483 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6484 return \"depdi 0,%%sar,%2,%0\";
6486 [(set_attr "type" "shift")
6487 (set_attr "length" "4")])
6489 (define_expand "ashrsi3"
6490 [(set (match_operand:SI 0 "register_operand" "")
6491 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6492 (match_operand:SI 2 "arith32_operand" "")))]
6496 if (GET_CODE (operands[2]) != CONST_INT)
6498 rtx temp = gen_reg_rtx (SImode);
6499 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6500 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6506 [(set (match_operand:SI 0 "register_operand" "=r")
6507 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6508 (match_operand:SI 2 "const_int_operand" "n")))]
6510 "{extrs|extrw,s} %1,%P2,%L2,%0"
6511 [(set_attr "type" "shift")
6512 (set_attr "length" "4")])
6514 (define_insn "vextrs32"
6515 [(set (match_operand:SI 0 "register_operand" "=r")
6516 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6517 (minus:SI (const_int 31)
6518 (match_operand:SI 2 "register_operand" "q"))))]
6520 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6521 [(set_attr "type" "shift")
6522 (set_attr "length" "4")])
6524 (define_expand "ashrdi3"
6525 [(set (match_operand:DI 0 "register_operand" "")
6526 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6527 (match_operand:DI 2 "arith32_operand" "")))]
6531 if (GET_CODE (operands[2]) != CONST_INT)
6533 rtx temp = gen_reg_rtx (DImode);
6534 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6535 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6541 [(set (match_operand:DI 0 "register_operand" "=r")
6542 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6543 (match_operand:DI 2 "const_int_operand" "n")))]
6545 "extrd,s %1,%p2,%Q2,%0"
6546 [(set_attr "type" "shift")
6547 (set_attr "length" "4")])
6549 (define_insn "vextrs64"
6550 [(set (match_operand:DI 0 "register_operand" "=r")
6551 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6552 (minus:DI (const_int 63)
6553 (match_operand:DI 2 "register_operand" "q"))))]
6555 "extrd,s %1,%%sar,64,%0"
6556 [(set_attr "type" "shift")
6557 (set_attr "length" "4")])
6559 (define_insn "lshrsi3"
6560 [(set (match_operand:SI 0 "register_operand" "=r,r")
6561 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6562 (match_operand:SI 2 "arith32_operand" "q,n")))]
6565 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6566 {extru|extrw,u} %1,%P2,%L2,%0"
6567 [(set_attr "type" "shift")
6568 (set_attr "length" "4")])
6570 (define_insn "lshrdi3"
6571 [(set (match_operand:DI 0 "register_operand" "=r,r")
6572 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6573 (match_operand:DI 2 "arith32_operand" "q,n")))]
6576 shrpd %%r0,%1,%%sar,%0
6577 extrd,u %1,%p2,%Q2,%0"
6578 [(set_attr "type" "shift")
6579 (set_attr "length" "4")])
6581 (define_insn "rotrsi3"
6582 [(set (match_operand:SI 0 "register_operand" "=r,r")
6583 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6584 (match_operand:SI 2 "arith32_operand" "q,n")))]
6588 if (GET_CODE (operands[2]) == CONST_INT)
6590 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6591 return \"{shd|shrpw} %1,%1,%2,%0\";
6594 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6596 [(set_attr "type" "shift")
6597 (set_attr "length" "4")])
6599 (define_expand "rotlsi3"
6600 [(set (match_operand:SI 0 "register_operand" "")
6601 (rotate:SI (match_operand:SI 1 "register_operand" "")
6602 (match_operand:SI 2 "arith32_operand" "")))]
6606 if (GET_CODE (operands[2]) != CONST_INT)
6608 rtx temp = gen_reg_rtx (SImode);
6609 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6610 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6613 /* Else expand normally. */
6617 [(set (match_operand:SI 0 "register_operand" "=r")
6618 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6619 (match_operand:SI 2 "const_int_operand" "n")))]
6623 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6624 return \"{shd|shrpw} %1,%1,%2,%0\";
6626 [(set_attr "type" "shift")
6627 (set_attr "length" "4")])
6630 [(set (match_operand:SI 0 "register_operand" "=r")
6631 (match_operator:SI 5 "plus_xor_ior_operator"
6632 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6633 (match_operand:SI 3 "const_int_operand" "n"))
6634 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6635 (match_operand:SI 4 "const_int_operand" "n"))]))]
6636 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6637 "{shd|shrpw} %1,%2,%4,%0"
6638 [(set_attr "type" "shift")
6639 (set_attr "length" "4")])
6642 [(set (match_operand:SI 0 "register_operand" "=r")
6643 (match_operator:SI 5 "plus_xor_ior_operator"
6644 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6645 (match_operand:SI 4 "const_int_operand" "n"))
6646 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6647 (match_operand:SI 3 "const_int_operand" "n"))]))]
6648 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6649 "{shd|shrpw} %1,%2,%4,%0"
6650 [(set_attr "type" "shift")
6651 (set_attr "length" "4")])
6654 [(set (match_operand:SI 0 "register_operand" "=r")
6655 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6656 (match_operand:SI 2 "const_int_operand" ""))
6657 (match_operand:SI 3 "const_int_operand" "")))]
6658 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) > 0"
6661 int cnt = INTVAL (operands[2]) & 31;
6662 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6663 operands[2] = GEN_INT (31 - cnt);
6664 return \"{zdep|depw,z} %1,%2,%3,%0\";
6666 [(set_attr "type" "shift")
6667 (set_attr "length" "4")])
6669 ;; Unconditional and other jump instructions.
6671 ;; Trivial return used when no epilogue is needed.
6672 (define_insn "return"
6675 "pa_can_use_return_insn ()"
6679 return \"bve%* (%%r2)\";
6680 return \"bv%* %%r0(%%r2)\";
6682 [(set_attr "type" "branch")
6683 (set_attr "length" "4")])
6685 ;; This is used for most returns.
6686 (define_insn "return_internal"
6693 return \"bve%* (%%r2)\";
6694 return \"bv%* %%r0(%%r2)\";
6696 [(set_attr "type" "branch")
6697 (set_attr "length" "4")])
6699 ;; This is used for eh returns which bypass the return stub.
6700 (define_insn "return_external_pic"
6702 (clobber (reg:SI 1))
6704 "!TARGET_NO_SPACE_REGS
6706 && flag_pic && crtl->calls_eh_return"
6707 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6708 [(set_attr "type" "branch")
6709 (set_attr "length" "12")])
6711 (define_expand "prologue"
6714 "hppa_expand_prologue ();DONE;")
6716 (define_expand "sibcall_epilogue"
6721 hppa_expand_epilogue ();
6725 (define_expand "epilogue"
6732 /* Try to use the trivial return first. Else use the full epilogue. */
6733 if (pa_can_use_return_insn ())
6737 hppa_expand_epilogue ();
6739 /* EH returns bypass the normal return stub. Thus, we must do an
6740 interspace branch to return from functions that call eh_return.
6741 This is only a problem for returns from shared code on ports
6742 using space registers. */
6743 if (!TARGET_NO_SPACE_REGS
6745 && flag_pic && crtl->calls_eh_return)
6746 x = gen_return_external_pic ();
6748 x = gen_return_internal ();
6754 ; Used by hppa_profile_hook to load the starting address of the current
6755 ; function; operand 1 contains the address of the label in operand 3
6756 (define_insn "load_offset_label_address"
6757 [(set (match_operand:SI 0 "register_operand" "=r")
6758 (plus:SI (match_operand:SI 1 "register_operand" "r")
6759 (minus:SI (match_operand:SI 2 "" "")
6760 (label_ref:SI (match_operand 3 "" "")))))]
6763 [(set_attr "type" "multi")
6764 (set_attr "length" "4")])
6766 ; Output a code label and load its address.
6767 (define_insn "lcla1"
6768 [(set (match_operand:SI 0 "register_operand" "=r")
6769 (label_ref:SI (match_operand 1 "" "")))
6774 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6775 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6776 CODE_LABEL_NUMBER (operands[1]));
6779 [(set_attr "type" "multi")
6780 (set_attr "length" "8")])
6782 (define_insn "lcla2"
6783 [(set (match_operand:SI 0 "register_operand" "=r")
6784 (label_ref:SI (match_operand 1 "" "")))
6789 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6790 CODE_LABEL_NUMBER (operands[1]));
6793 [(set_attr "type" "move")
6794 (set_attr "length" "4")])
6796 (define_insn "blockage"
6797 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
6800 [(set_attr "length" "0")])
6803 [(set (pc) (label_ref (match_operand 0 "" "")))]
6807 /* An unconditional branch which can reach its target. */
6808 if (get_attr_length (insn) < 16)
6811 return output_lbranch (operands[0], insn, 1);
6813 [(set_attr "type" "uncond_branch")
6814 (set_attr "pa_combine_type" "uncond_branch")
6815 (set (attr "length")
6816 (cond [(match_test "jump_in_call_delay (insn)")
6817 (if_then_else (lt (abs (minus (match_dup 0)
6818 (plus (pc) (const_int 8))))
6819 (const_int MAX_12BIT_OFFSET))
6822 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6823 (const_int MAX_17BIT_OFFSET))
6825 (match_test "TARGET_PORTABLE_RUNTIME")
6827 (not (match_test "flag_pic"))
6831 ;;; Hope this is only within a function...
6832 (define_insn "indirect_jump"
6833 [(set (pc) (match_operand 0 "register_operand" "r"))]
6834 "GET_MODE (operands[0]) == word_mode"
6836 [(set_attr "type" "branch")
6837 (set_attr "length" "4")])
6839 ;;; An indirect jump can be optimized to a direct jump. GAS for the
6840 ;;; SOM target doesn't allow branching to a label inside a function.
6841 ;;; We also don't correctly compute branch distances for labels
6842 ;;; outside the current function. Thus, we use an indirect jump can't
6843 ;;; be optimized to a direct jump for all targets. We assume that
6844 ;;; the branch target is in the same space (i.e., nested function
6845 ;;; jumping to a label in an outer function in the same translation
6847 (define_expand "nonlocal_goto"
6848 [(use (match_operand 0 "general_operand" ""))
6849 (use (match_operand 1 "general_operand" ""))
6850 (use (match_operand 2 "general_operand" ""))
6851 (use (match_operand 3 "general_operand" ""))]
6854 rtx lab = operands[1];
6855 rtx stack = operands[2];
6856 rtx fp = operands[3];
6858 lab = copy_to_reg (lab);
6860 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
6861 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
6863 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
6864 instead of the hard_frame_pointer_rtx in the save area. As a
6865 result, an extra instruction is needed to adjust for the offset
6866 of the virtual stack variables and the hard frame pointer. */
6867 if (GET_CODE (fp) != REG)
6868 fp = force_reg (Pmode, fp);
6869 emit_move_insn (hard_frame_pointer_rtx, plus_constant (fp, -8));
6871 emit_stack_restore (SAVE_NONLOCAL, stack);
6873 emit_use (hard_frame_pointer_rtx);
6874 emit_use (stack_pointer_rtx);
6876 /* Nonlocal goto jumps are only used between functions in the same
6877 translation unit. Thus, we can avoid the extra overhead of an
6879 emit_jump_insn (gen_indirect_goto (lab));
6884 (define_insn "indirect_goto"
6885 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
6886 "GET_MODE (operands[0]) == word_mode"
6888 [(set_attr "type" "branch")
6889 (set_attr "length" "4")])
6891 ;;; This jump is used in branch tables where the insn length is fixed.
6892 ;;; The length of this insn is adjusted if the delay slot is not filled.
6893 (define_insn "short_jump"
6894 [(set (pc) (label_ref (match_operand 0 "" "")))
6898 [(set_attr "type" "btable_branch")
6899 (set_attr "length" "4")])
6901 ;; Subroutines of "casesi".
6902 ;; operand 0 is index
6903 ;; operand 1 is the minimum bound
6904 ;; operand 2 is the maximum bound - minimum bound + 1
6905 ;; operand 3 is CODE_LABEL for the table;
6906 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6908 (define_expand "casesi"
6909 [(match_operand:SI 0 "general_operand" "")
6910 (match_operand:SI 1 "const_int_operand" "")
6911 (match_operand:SI 2 "const_int_operand" "")
6912 (match_operand 3 "" "")
6913 (match_operand 4 "" "")]
6917 if (GET_CODE (operands[0]) != REG)
6918 operands[0] = force_reg (SImode, operands[0]);
6920 if (operands[1] != const0_rtx)
6922 rtx index = gen_reg_rtx (SImode);
6924 operands[1] = gen_int_mode (-INTVAL (operands[1]), SImode);
6925 if (!INT_14_BITS (operands[1]))
6926 operands[1] = force_reg (SImode, operands[1]);
6927 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
6928 operands[0] = index;
6931 if (!INT_5_BITS (operands[2]))
6932 operands[2] = force_reg (SImode, operands[2]);
6934 /* This branch prevents us finding an insn for the delay slot of the
6935 following vectored branch. It might be possible to use the delay
6936 slot if an index value of -1 was used to transfer to the out-of-range
6937 label. In order to do this, we would have to output the -1 vector
6938 element after the delay insn. The casesi output code would have to
6939 check if the casesi insn is in a delay branch sequence and output
6940 the delay insn if one is found. If this was done, then it might
6941 then be worthwhile to split the casesi patterns to improve scheduling.
6942 However, it's not clear that all this extra complexity is worth
6945 rtx test = gen_rtx_GTU (VOIDmode, operands[0], operands[2]);
6946 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
6949 /* In 64bit mode we must make sure to wipe the upper bits of the register
6950 just in case the addition overflowed or we had random bits in the
6951 high part of the register. */
6954 rtx index = gen_reg_rtx (DImode);
6956 emit_insn (gen_extendsidi2 (index, operands[0]));
6957 operands[0] = index;
6960 if (TARGET_BIG_SWITCH)
6963 emit_jump_insn (gen_casesi64p (operands[0], operands[3]));
6965 emit_jump_insn (gen_casesi32p (operands[0], operands[3]));
6967 emit_jump_insn (gen_casesi32 (operands[0], operands[3]));
6970 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
6974 ;;; The rtl for this pattern doesn't accurately describe what the insn
6975 ;;; actually does, particularly when case-vector elements are exploded
6976 ;;; in pa_reorg. However, the initial SET in these patterns must show
6977 ;;; the connection of the insn to the following jump table.
6978 (define_insn "casesi0"
6979 [(set (pc) (mem:SI (plus:SI
6980 (mult:SI (match_operand:SI 0 "register_operand" "r")
6982 (label_ref (match_operand 1 "" "")))))]
6984 "blr,n %0,%%r0\;nop"
6985 [(set_attr "type" "multi")
6986 (set_attr "length" "8")])
6988 ;;; 32-bit code, absolute branch table.
6989 (define_insn "casesi32"
6990 [(set (pc) (mem:SI (plus:SI
6991 (mult:SI (match_operand:SI 0 "register_operand" "r")
6993 (label_ref (match_operand 1 "" "")))))
6994 (clobber (match_scratch:SI 2 "=&r"))]
6996 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
6997 [(set_attr "type" "multi")
6998 (set_attr "length" "16")])
7000 ;;; 32-bit code, relative branch table.
7001 (define_insn "casesi32p"
7002 [(set (pc) (mem:SI (plus:SI
7003 (mult:SI (match_operand:SI 0 "register_operand" "r")
7005 (label_ref (match_operand 1 "" "")))))
7006 (clobber (match_scratch:SI 2 "=&r"))
7007 (clobber (match_scratch:SI 3 "=&r"))]
7009 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {%l1-.|%l1+4-.}(%2),%2\;\
7010 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7011 [(set_attr "type" "multi")
7012 (set (attr "length")
7013 (if_then_else (match_test "TARGET_PA_20")
7017 ;;; 64-bit code, 32-bit relative branch table.
7018 (define_insn "casesi64p"
7019 [(set (pc) (mem:DI (plus:DI
7020 (mult:DI (match_operand:DI 0 "register_operand" "r")
7022 (label_ref (match_operand 1 "" "")))))
7023 (clobber (match_scratch:DI 2 "=&r"))
7024 (clobber (match_scratch:DI 3 "=&r"))]
7026 "mfia %2\;ldo %l1+4-.(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7027 add,l %2,%3,%3\;bv,n %%r0(%3)"
7028 [(set_attr "type" "multi")
7029 (set_attr "length" "24")])
7033 ;;- jump to subroutine
7035 (define_expand "call"
7036 [(parallel [(call (match_operand:SI 0 "" "")
7037 (match_operand 1 "" ""))
7038 (clobber (reg:SI 2))])]
7043 rtx nb = operands[1];
7045 if (TARGET_PORTABLE_RUNTIME)
7046 op = force_reg (SImode, XEXP (operands[0], 0));
7048 op = XEXP (operands[0], 0);
7052 if (!virtuals_instantiated)
7053 emit_move_insn (arg_pointer_rtx,
7054 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7058 /* The loop pass can generate new libcalls after the virtual
7059 registers are instantiated when fpregs are disabled because
7060 the only method that we have for doing DImode multiplication
7061 is with a libcall. This could be trouble if we haven't
7062 allocated enough space for the outgoing arguments. */
7063 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7065 emit_move_insn (arg_pointer_rtx,
7066 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7067 GEN_INT (STACK_POINTER_OFFSET + 64)));
7071 /* Use two different patterns for calls to explicitly named functions
7072 and calls through function pointers. This is necessary as these two
7073 types of calls use different calling conventions, and CSE might try
7074 to change the named call into an indirect call in some cases (using
7075 two patterns keeps CSE from performing this optimization).
7077 We now use even more call patterns as there was a subtle bug in
7078 attempting to restore the pic register after a call using a simple
7079 move insn. During reload, a instruction involving a pseudo register
7080 with no explicit dependence on the PIC register can be converted
7081 to an equivalent load from memory using the PIC register. If we
7082 emit a simple move to restore the PIC register in the initial rtl
7083 generation, then it can potentially be repositioned during scheduling.
7084 and an instruction that eventually uses the PIC register may end up
7085 between the call and the PIC register restore.
7087 This only worked because there is a post call group of instructions
7088 that are scheduled with the call. These instructions are included
7089 in the same basic block as the call. However, calls can throw in
7090 C++ code and a basic block has to terminate at the call if the call
7091 can throw. This results in the PIC register restore being scheduled
7092 independently from the call. So, we now hide the save and restore
7093 of the PIC register in the call pattern until after reload. Then,
7094 we split the moves out. A small side benefit is that we now don't
7095 need to have a use of the PIC register in the return pattern and
7096 the final save/restore operation is not needed.
7098 I elected to just use register %r4 in the PIC patterns instead
7099 of trying to force hppa_pic_save_rtx () to a callee saved register.
7100 This might have required a new register class and constraint. It
7101 was also simpler to just handle the restore from a register than a
7105 rtx r4 = gen_rtx_REG (word_mode, 4);
7106 if (GET_CODE (op) == SYMBOL_REF)
7107 emit_call_insn (gen_call_symref_64bit (op, nb, r4));
7110 op = force_reg (word_mode, op);
7111 emit_call_insn (gen_call_reg_64bit (op, nb, r4));
7116 if (GET_CODE (op) == SYMBOL_REF)
7120 rtx r4 = gen_rtx_REG (word_mode, 4);
7121 emit_call_insn (gen_call_symref_pic (op, nb, r4));
7124 emit_call_insn (gen_call_symref (op, nb));
7128 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7129 emit_move_insn (tmpreg, force_reg (word_mode, op));
7132 rtx r4 = gen_rtx_REG (word_mode, 4);
7133 emit_call_insn (gen_call_reg_pic (nb, r4));
7136 emit_call_insn (gen_call_reg (nb));
7143 ;; We use function calls to set the attribute length of calls and millicode
7144 ;; calls. This is necessary because of the large variety of call sequences.
7145 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7146 ;; we need the same calculation in several places, maintenance becomes a
7149 ;; However, this has a subtle impact on branch shortening. When the
7150 ;; expression used to set the length attribute of an instruction depends
7151 ;; on a relative address (e.g., pc or a branch address), genattrtab
7152 ;; notes that the insn's length is variable, and attempts to determine a
7153 ;; worst-case default length and code to compute an insn's current length.
7155 ;; The use of a function call hides the variable dependence of our calls
7156 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7157 ;; as variable and it only generates code for the default case using our
7158 ;; function call. Because of this, calls and millicode calls have a fixed
7159 ;; length in the branch shortening pass, and some branches will use a longer
7160 ;; code sequence than necessary. However, the length of any given call
7161 ;; will still reflect its final code location and it may be shorter than
7162 ;; the initial length estimate.
7164 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7165 ;; in the set. However, when genattrtab hits a function call in its attempt
7166 ;; to compute the default length, it marks the result as unknown and sets
7167 ;; the default result to MAX_INT ;-( One possible fix that would allow
7168 ;; calls to participate in branch shortening would be to make the call to
7169 ;; insn_default_length a target option. Then, we could massage unknown
7170 ;; results. Another fix might be to change genattrtab so that it just does
7171 ;; the call in the variable case as it already does for the fixed case.
7173 (define_insn "call_symref"
7174 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7175 (match_operand 1 "" "i"))
7176 (clobber (reg:SI 1))
7177 (clobber (reg:SI 2))
7178 (use (const_int 0))]
7179 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7182 output_arg_descriptor (insn);
7183 return output_call (insn, operands[0], 0);
7185 [(set_attr "type" "call")
7186 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7188 (define_insn "call_symref_pic"
7189 [(set (match_operand:SI 2 "register_operand" "=&r") (reg:SI 19))
7190 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7191 (match_operand 1 "" "i"))
7192 (clobber (reg:SI 1))
7193 (clobber (reg:SI 2))
7196 (use (const_int 0))]
7197 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7200 ;; Split out the PIC register save and restore after reload. As the
7201 ;; split is done after reload, there are some situations in which we
7202 ;; unnecessarily save and restore %r4. This happens when there is a
7203 ;; single call and the PIC register is not used after the call.
7205 ;; The split has to be done since call_from_call_insn () can't handle
7206 ;; the pattern as is. Noreturn calls are special because they have to
7207 ;; terminate the basic block. The split has to contain more than one
7210 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7211 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7212 (match_operand 1 "" ""))
7213 (clobber (reg:SI 1))
7214 (clobber (reg:SI 2))
7217 (use (const_int 0))])]
7218 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7219 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7220 [(set (match_dup 2) (reg:SI 19))
7221 (parallel [(call (mem:SI (match_dup 0))
7223 (clobber (reg:SI 1))
7224 (clobber (reg:SI 2))
7226 (use (const_int 0))])]
7230 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7231 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7232 (match_operand 1 "" ""))
7233 (clobber (reg:SI 1))
7234 (clobber (reg:SI 2))
7237 (use (const_int 0))])]
7238 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7239 [(set (match_dup 2) (reg:SI 19))
7240 (parallel [(call (mem:SI (match_dup 0))
7242 (clobber (reg:SI 1))
7243 (clobber (reg:SI 2))
7245 (use (const_int 0))])
7246 (set (reg:SI 19) (match_dup 2))]
7249 (define_insn "*call_symref_pic_post_reload"
7250 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7251 (match_operand 1 "" "i"))
7252 (clobber (reg:SI 1))
7253 (clobber (reg:SI 2))
7255 (use (const_int 0))]
7256 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7259 output_arg_descriptor (insn);
7260 return output_call (insn, operands[0], 0);
7262 [(set_attr "type" "call")
7263 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7265 ;; This pattern is split if it is necessary to save and restore the
7267 (define_insn "call_symref_64bit"
7268 [(set (match_operand:DI 2 "register_operand" "=&r") (reg:DI 27))
7269 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7270 (match_operand 1 "" "i"))
7271 (clobber (reg:DI 1))
7272 (clobber (reg:DI 2))
7276 (use (const_int 0))]
7280 ;; Split out the PIC register save and restore after reload. As the
7281 ;; split is done after reload, there are some situations in which we
7282 ;; unnecessarily save and restore %r4. This happens when there is a
7283 ;; single call and the PIC register is not used after the call.
7285 ;; The split has to be done since call_from_call_insn () can't handle
7286 ;; the pattern as is. Noreturn calls are special because they have to
7287 ;; terminate the basic block. The split has to contain more than one
7290 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7291 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7292 (match_operand 1 "" ""))
7293 (clobber (reg:DI 1))
7294 (clobber (reg:DI 2))
7298 (use (const_int 0))])]
7299 "TARGET_64BIT && reload_completed
7300 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7301 [(set (match_dup 2) (reg:DI 27))
7302 (parallel [(call (mem:SI (match_dup 0))
7304 (clobber (reg:DI 1))
7305 (clobber (reg:DI 2))
7308 (use (const_int 0))])]
7312 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7313 (call (mem:SI (match_operand 0 "call_operand_address" ""))
7314 (match_operand 1 "" ""))
7315 (clobber (reg:DI 1))
7316 (clobber (reg:DI 2))
7320 (use (const_int 0))])]
7321 "TARGET_64BIT && reload_completed"
7322 [(set (match_dup 2) (reg:DI 27))
7323 (parallel [(call (mem:SI (match_dup 0))
7325 (clobber (reg:DI 1))
7326 (clobber (reg:DI 2))
7329 (use (const_int 0))])
7330 (set (reg:DI 27) (match_dup 2))]
7333 (define_insn "*call_symref_64bit_post_reload"
7334 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7335 (match_operand 1 "" "i"))
7336 (clobber (reg:DI 1))
7337 (clobber (reg:DI 2))
7340 (use (const_int 0))]
7344 output_arg_descriptor (insn);
7345 return output_call (insn, operands[0], 0);
7347 [(set_attr "type" "call")
7348 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7350 (define_insn "call_reg"
7351 [(call (mem:SI (reg:SI 22))
7352 (match_operand 0 "" "i"))
7353 (clobber (reg:SI 1))
7354 (clobber (reg:SI 2))
7355 (use (const_int 1))]
7359 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7361 [(set_attr "type" "dyncall")
7362 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7364 ;; This pattern is split if it is necessary to save and restore the
7366 (define_insn "call_reg_pic"
7367 [(set (match_operand:SI 1 "register_operand" "=&r") (reg:SI 19))
7368 (call (mem:SI (reg:SI 22))
7369 (match_operand 0 "" "i"))
7370 (clobber (reg:SI 1))
7371 (clobber (reg:SI 2))
7374 (use (const_int 1))]
7378 ;; Split out the PIC register save and restore after reload. As the
7379 ;; split is done after reload, there are some situations in which we
7380 ;; unnecessarily save and restore %r4. This happens when there is a
7381 ;; single call and the PIC register is not used after the call.
7383 ;; The split has to be done since call_from_call_insn () can't handle
7384 ;; the pattern as is. Noreturn calls are special because they have to
7385 ;; terminate the basic block. The split has to contain more than one
7388 [(parallel [(set (match_operand:SI 1 "register_operand" "") (reg:SI 19))
7389 (call (mem:SI (reg:SI 22))
7390 (match_operand 0 "" ""))
7391 (clobber (reg:SI 1))
7392 (clobber (reg:SI 2))
7395 (use (const_int 1))])]
7396 "!TARGET_64BIT && reload_completed
7397 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7398 [(set (match_dup 1) (reg:SI 19))
7399 (parallel [(call (mem:SI (reg:SI 22))
7401 (clobber (reg:SI 1))
7402 (clobber (reg:SI 2))
7404 (use (const_int 1))])]
7408 [(parallel [(set (match_operand:SI 1 "register_operand" "") (reg:SI 19))
7409 (call (mem:SI (reg:SI 22))
7410 (match_operand 0 "" ""))
7411 (clobber (reg:SI 1))
7412 (clobber (reg:SI 2))
7415 (use (const_int 1))])]
7416 "!TARGET_64BIT && reload_completed"
7417 [(set (match_dup 1) (reg:SI 19))
7418 (parallel [(call (mem:SI (reg:SI 22))
7420 (clobber (reg:SI 1))
7421 (clobber (reg:SI 2))
7423 (use (const_int 1))])
7424 (set (reg:SI 19) (match_dup 1))]
7427 (define_insn "*call_reg_pic_post_reload"
7428 [(call (mem:SI (reg:SI 22))
7429 (match_operand 0 "" "i"))
7430 (clobber (reg:SI 1))
7431 (clobber (reg:SI 2))
7433 (use (const_int 1))]
7437 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7439 [(set_attr "type" "dyncall")
7440 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7442 ;; This pattern is split if it is necessary to save and restore the
7444 (define_insn "call_reg_64bit"
7445 [(set (match_operand:DI 2 "register_operand" "=&r") (reg:DI 27))
7446 (call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7447 (match_operand 1 "" "i"))
7448 (clobber (reg:DI 1))
7449 (clobber (reg:DI 2))
7453 (use (const_int 1))]
7457 ;; Split out the PIC register save and restore after reload. As the
7458 ;; split is done after reload, there are some situations in which we
7459 ;; unnecessarily save and restore %r4. This happens when there is a
7460 ;; single call and the PIC register is not used after the call.
7462 ;; The split has to be done since call_from_call_insn () can't handle
7463 ;; the pattern as is. Noreturn calls are special because they have to
7464 ;; terminate the basic block. The split has to contain more than one
7467 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7468 (call (mem:SI (match_operand 0 "register_operand" ""))
7469 (match_operand 1 "" ""))
7470 (clobber (reg:DI 1))
7471 (clobber (reg:DI 2))
7475 (use (const_int 1))])]
7476 "TARGET_64BIT && reload_completed
7477 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7478 [(set (match_dup 2) (reg:DI 27))
7479 (parallel [(call (mem:SI (match_dup 0))
7481 (clobber (reg:DI 1))
7482 (clobber (reg:DI 2))
7485 (use (const_int 1))])]
7489 [(parallel [(set (match_operand:DI 2 "register_operand" "") (reg:DI 27))
7490 (call (mem:SI (match_operand 0 "register_operand" ""))
7491 (match_operand 1 "" ""))
7492 (clobber (reg:DI 1))
7493 (clobber (reg:DI 2))
7497 (use (const_int 1))])]
7498 "TARGET_64BIT && reload_completed"
7499 [(set (match_dup 2) (reg:DI 27))
7500 (parallel [(call (mem:SI (match_dup 0))
7502 (clobber (reg:DI 1))
7503 (clobber (reg:DI 2))
7506 (use (const_int 1))])
7507 (set (reg:DI 27) (match_dup 2))]
7510 (define_insn "*call_reg_64bit_post_reload"
7511 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7512 (match_operand 1 "" "i"))
7513 (clobber (reg:DI 1))
7514 (clobber (reg:DI 2))
7517 (use (const_int 1))]
7521 return output_indirect_call (insn, operands[0]);
7523 [(set_attr "type" "dyncall")
7524 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7526 (define_expand "call_value"
7527 [(parallel [(set (match_operand 0 "" "")
7528 (call (match_operand:SI 1 "" "")
7529 (match_operand 2 "" "")))
7530 (clobber (reg:SI 2))])]
7535 rtx dst = operands[0];
7536 rtx nb = operands[2];
7538 if (TARGET_PORTABLE_RUNTIME)
7539 op = force_reg (SImode, XEXP (operands[1], 0));
7541 op = XEXP (operands[1], 0);
7545 if (!virtuals_instantiated)
7546 emit_move_insn (arg_pointer_rtx,
7547 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7551 /* The loop pass can generate new libcalls after the virtual
7552 registers are instantiated when fpregs are disabled because
7553 the only method that we have for doing DImode multiplication
7554 is with a libcall. This could be trouble if we haven't
7555 allocated enough space for the outgoing arguments. */
7556 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
7558 emit_move_insn (arg_pointer_rtx,
7559 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7560 GEN_INT (STACK_POINTER_OFFSET + 64)));
7564 /* Use two different patterns for calls to explicitly named functions
7565 and calls through function pointers. This is necessary as these two
7566 types of calls use different calling conventions, and CSE might try
7567 to change the named call into an indirect call in some cases (using
7568 two patterns keeps CSE from performing this optimization).
7570 We now use even more call patterns as there was a subtle bug in
7571 attempting to restore the pic register after a call using a simple
7572 move insn. During reload, a instruction involving a pseudo register
7573 with no explicit dependence on the PIC register can be converted
7574 to an equivalent load from memory using the PIC register. If we
7575 emit a simple move to restore the PIC register in the initial rtl
7576 generation, then it can potentially be repositioned during scheduling.
7577 and an instruction that eventually uses the PIC register may end up
7578 between the call and the PIC register restore.
7580 This only worked because there is a post call group of instructions
7581 that are scheduled with the call. These instructions are included
7582 in the same basic block as the call. However, calls can throw in
7583 C++ code and a basic block has to terminate at the call if the call
7584 can throw. This results in the PIC register restore being scheduled
7585 independently from the call. So, we now hide the save and restore
7586 of the PIC register in the call pattern until after reload. Then,
7587 we split the moves out. A small side benefit is that we now don't
7588 need to have a use of the PIC register in the return pattern and
7589 the final save/restore operation is not needed.
7591 I elected to just use register %r4 in the PIC patterns instead
7592 of trying to force hppa_pic_save_rtx () to a callee saved register.
7593 This might have required a new register class and constraint. It
7594 was also simpler to just handle the restore from a register than a
7598 rtx r4 = gen_rtx_REG (word_mode, 4);
7599 if (GET_CODE (op) == SYMBOL_REF)
7600 emit_call_insn (gen_call_val_symref_64bit (dst, op, nb, r4));
7603 op = force_reg (word_mode, op);
7604 emit_call_insn (gen_call_val_reg_64bit (dst, op, nb, r4));
7609 if (GET_CODE (op) == SYMBOL_REF)
7613 rtx r4 = gen_rtx_REG (word_mode, 4);
7614 emit_call_insn (gen_call_val_symref_pic (dst, op, nb, r4));
7617 emit_call_insn (gen_call_val_symref (dst, op, nb));
7621 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7622 emit_move_insn (tmpreg, force_reg (word_mode, op));
7625 rtx r4 = gen_rtx_REG (word_mode, 4);
7626 emit_call_insn (gen_call_val_reg_pic (dst, nb, r4));
7629 emit_call_insn (gen_call_val_reg (dst, nb));
7636 (define_insn "call_val_symref"
7637 [(set (match_operand 0 "" "")
7638 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7639 (match_operand 2 "" "i")))
7640 (clobber (reg:SI 1))
7641 (clobber (reg:SI 2))
7642 (use (const_int 0))]
7643 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7646 output_arg_descriptor (insn);
7647 return output_call (insn, operands[1], 0);
7649 [(set_attr "type" "call")
7650 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7652 (define_insn "call_val_symref_pic"
7653 [(set (match_operand:SI 3 "register_operand" "=&r") (reg:SI 19))
7654 (set (match_operand 0 "" "")
7655 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7656 (match_operand 2 "" "i")))
7657 (clobber (reg:SI 1))
7658 (clobber (reg:SI 2))
7661 (use (const_int 0))]
7662 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7665 ;; Split out the PIC register save and restore after reload. As the
7666 ;; split is done after reload, there are some situations in which we
7667 ;; unnecessarily save and restore %r4. This happens when there is a
7668 ;; single call and the PIC register is not used after the call.
7670 ;; The split has to be done since call_from_call_insn () can't handle
7671 ;; the pattern as is. Noreturn calls are special because they have to
7672 ;; terminate the basic block. The split has to contain more than one
7675 [(parallel [(set (match_operand:SI 3 "register_operand" "") (reg:SI 19))
7676 (set (match_operand 0 "" "")
7677 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7678 (match_operand 2 "" "")))
7679 (clobber (reg:SI 1))
7680 (clobber (reg:SI 2))
7683 (use (const_int 0))])]
7684 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed
7685 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7686 [(set (match_dup 3) (reg:SI 19))
7687 (parallel [(set (match_dup 0)
7688 (call (mem:SI (match_dup 1))
7690 (clobber (reg:SI 1))
7691 (clobber (reg:SI 2))
7693 (use (const_int 0))])]
7697 [(parallel [(set (match_operand:SI 3 "register_operand" "") (reg:SI 19))
7698 (set (match_operand 0 "" "")
7699 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7700 (match_operand 2 "" "")))
7701 (clobber (reg:SI 1))
7702 (clobber (reg:SI 2))
7705 (use (const_int 0))])]
7706 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7707 [(set (match_dup 3) (reg:SI 19))
7708 (parallel [(set (match_dup 0)
7709 (call (mem:SI (match_dup 1))
7711 (clobber (reg:SI 1))
7712 (clobber (reg:SI 2))
7714 (use (const_int 0))])
7715 (set (reg:SI 19) (match_dup 3))]
7718 (define_insn "*call_val_symref_pic_post_reload"
7719 [(set (match_operand 0 "" "")
7720 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7721 (match_operand 2 "" "i")))
7722 (clobber (reg:SI 1))
7723 (clobber (reg:SI 2))
7725 (use (const_int 0))]
7726 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7729 output_arg_descriptor (insn);
7730 return output_call (insn, operands[1], 0);
7732 [(set_attr "type" "call")
7733 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7735 ;; This pattern is split if it is necessary to save and restore the
7737 (define_insn "call_val_symref_64bit"
7738 [(set (match_operand:DI 3 "register_operand" "=&r") (reg:DI 27))
7739 (set (match_operand 0 "" "")
7740 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7741 (match_operand 2 "" "i")))
7742 (clobber (reg:DI 1))
7743 (clobber (reg:DI 2))
7747 (use (const_int 0))]
7751 ;; Split out the PIC register save and restore after reload. As the
7752 ;; split is done after reload, there are some situations in which we
7753 ;; unnecessarily save and restore %r4. This happens when there is a
7754 ;; single call and the PIC register is not used after the call.
7756 ;; The split has to be done since call_from_call_insn () can't handle
7757 ;; the pattern as is. Noreturn calls are special because they have to
7758 ;; terminate the basic block. The split has to contain more than one
7761 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
7762 (set (match_operand 0 "" "")
7763 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7764 (match_operand 2 "" "")))
7765 (clobber (reg:DI 1))
7766 (clobber (reg:DI 2))
7770 (use (const_int 0))])]
7771 "TARGET_64BIT && reload_completed
7772 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7773 [(set (match_dup 3) (reg:DI 27))
7774 (parallel [(set (match_dup 0)
7775 (call (mem:SI (match_dup 1))
7777 (clobber (reg:DI 1))
7778 (clobber (reg:DI 2))
7781 (use (const_int 0))])]
7785 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
7786 (set (match_operand 0 "" "")
7787 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7788 (match_operand 2 "" "")))
7789 (clobber (reg:DI 1))
7790 (clobber (reg:DI 2))
7794 (use (const_int 0))])]
7795 "TARGET_64BIT && reload_completed"
7796 [(set (match_dup 3) (reg:DI 27))
7797 (parallel [(set (match_dup 0)
7798 (call (mem:SI (match_dup 1))
7800 (clobber (reg:DI 1))
7801 (clobber (reg:DI 2))
7804 (use (const_int 0))])
7805 (set (reg:DI 27) (match_dup 3))]
7808 (define_insn "*call_val_symref_64bit_post_reload"
7809 [(set (match_operand 0 "" "")
7810 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7811 (match_operand 2 "" "i")))
7812 (clobber (reg:DI 1))
7813 (clobber (reg:DI 2))
7816 (use (const_int 0))]
7820 output_arg_descriptor (insn);
7821 return output_call (insn, operands[1], 0);
7823 [(set_attr "type" "call")
7824 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7826 (define_insn "call_val_reg"
7827 [(set (match_operand 0 "" "")
7828 (call (mem:SI (reg:SI 22))
7829 (match_operand 1 "" "i")))
7830 (clobber (reg:SI 1))
7831 (clobber (reg:SI 2))
7832 (use (const_int 1))]
7836 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7838 [(set_attr "type" "dyncall")
7839 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7841 ;; This pattern is split if it is necessary to save and restore the
7843 (define_insn "call_val_reg_pic"
7844 [(set (match_operand:SI 2 "register_operand" "=&r") (reg:SI 19))
7845 (set (match_operand 0 "" "")
7846 (call (mem:SI (reg:SI 22))
7847 (match_operand 1 "" "i")))
7848 (clobber (reg:SI 1))
7849 (clobber (reg:SI 2))
7852 (use (const_int 1))]
7856 ;; Split out the PIC register save and restore after reload. As the
7857 ;; split is done after reload, there are some situations in which we
7858 ;; unnecessarily save and restore %r4. This happens when there is a
7859 ;; single call and the PIC register is not used after the call.
7861 ;; The split has to be done since call_from_call_insn () can't handle
7862 ;; the pattern as is. Noreturn calls are special because they have to
7863 ;; terminate the basic block. The split has to contain more than one
7866 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7867 (set (match_operand 0 "" "")
7868 (call (mem:SI (reg:SI 22))
7869 (match_operand 1 "" "")))
7870 (clobber (reg:SI 1))
7871 (clobber (reg:SI 2))
7874 (use (const_int 1))])]
7875 "!TARGET_64BIT && reload_completed
7876 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7877 [(set (match_dup 2) (reg:SI 19))
7878 (parallel [(set (match_dup 0)
7879 (call (mem:SI (reg:SI 22))
7881 (clobber (reg:SI 1))
7882 (clobber (reg:SI 2))
7884 (use (const_int 1))])]
7888 [(parallel [(set (match_operand:SI 2 "register_operand" "") (reg:SI 19))
7889 (set (match_operand 0 "" "")
7890 (call (mem:SI (reg:SI 22))
7891 (match_operand 1 "" "")))
7892 (clobber (reg:SI 1))
7893 (clobber (reg:SI 2))
7896 (use (const_int 1))])]
7897 "!TARGET_64BIT && reload_completed"
7898 [(set (match_dup 2) (reg:SI 19))
7899 (parallel [(set (match_dup 0)
7900 (call (mem:SI (reg:SI 22))
7902 (clobber (reg:SI 1))
7903 (clobber (reg:SI 2))
7905 (use (const_int 1))])
7906 (set (reg:SI 19) (match_dup 2))]
7909 (define_insn "*call_val_reg_pic_post_reload"
7910 [(set (match_operand 0 "" "")
7911 (call (mem:SI (reg:SI 22))
7912 (match_operand 1 "" "i")))
7913 (clobber (reg:SI 1))
7914 (clobber (reg:SI 2))
7916 (use (const_int 1))]
7920 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7922 [(set_attr "type" "dyncall")
7923 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7925 ;; This pattern is split if it is necessary to save and restore the
7927 (define_insn "call_val_reg_64bit"
7928 [(set (match_operand:DI 3 "register_operand" "=&r") (reg:DI 27))
7929 (set (match_operand 0 "" "")
7930 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7931 (match_operand 2 "" "i")))
7932 (clobber (reg:DI 1))
7933 (clobber (reg:DI 2))
7937 (use (const_int 1))]
7941 ;; Split out the PIC register save and restore after reload. As the
7942 ;; split is done after reload, there are some situations in which we
7943 ;; unnecessarily save and restore %r4. This happens when there is a
7944 ;; single call and the PIC register is not used after the call.
7946 ;; The split has to be done since call_from_call_insn () can't handle
7947 ;; the pattern as is. Noreturn calls are special because they have to
7948 ;; terminate the basic block. The split has to contain more than one
7951 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
7952 (set (match_operand 0 "" "")
7953 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7954 (match_operand 2 "" "")))
7955 (clobber (reg:DI 1))
7956 (clobber (reg:DI 2))
7960 (use (const_int 1))])]
7961 "TARGET_64BIT && reload_completed
7962 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7963 [(set (match_dup 3) (reg:DI 27))
7964 (parallel [(set (match_dup 0)
7965 (call (mem:SI (match_dup 1))
7967 (clobber (reg:DI 1))
7968 (clobber (reg:DI 2))
7971 (use (const_int 1))])]
7975 [(parallel [(set (match_operand:DI 3 "register_operand" "") (reg:DI 27))
7976 (set (match_operand 0 "" "")
7977 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7978 (match_operand 2 "" "")))
7979 (clobber (reg:DI 1))
7980 (clobber (reg:DI 2))
7984 (use (const_int 1))])]
7985 "TARGET_64BIT && reload_completed"
7986 [(set (match_dup 3) (reg:DI 27))
7987 (parallel [(set (match_dup 0)
7988 (call (mem:SI (match_dup 1))
7990 (clobber (reg:DI 1))
7991 (clobber (reg:DI 2))
7994 (use (const_int 1))])
7995 (set (reg:DI 27) (match_dup 3))]
7998 (define_insn "*call_val_reg_64bit_post_reload"
7999 [(set (match_operand 0 "" "")
8000 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8001 (match_operand 2 "" "i")))
8002 (clobber (reg:DI 1))
8003 (clobber (reg:DI 2))
8006 (use (const_int 1))]
8010 return output_indirect_call (insn, operands[1]);
8012 [(set_attr "type" "dyncall")
8013 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8015 ;; Call subroutine returning any type.
8017 (define_expand "untyped_call"
8018 [(parallel [(call (match_operand 0 "" "")
8020 (match_operand 1 "" "")
8021 (match_operand 2 "" "")])]
8027 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8029 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8031 rtx set = XVECEXP (operands[2], 0, i);
8032 emit_move_insn (SET_DEST (set), SET_SRC (set));
8035 /* The optimizer does not know that the call sets the function value
8036 registers we stored in the result block. We avoid problems by
8037 claiming that all hard registers are used and clobbered at this
8039 emit_insn (gen_blockage ());
8044 (define_expand "sibcall"
8045 [(call (match_operand:SI 0 "" "")
8046 (match_operand 1 "" ""))]
8047 "!TARGET_PORTABLE_RUNTIME"
8051 rtx nb = operands[1];
8053 op = XEXP (operands[0], 0);
8057 if (!virtuals_instantiated)
8058 emit_move_insn (arg_pointer_rtx,
8059 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8063 /* The loop pass can generate new libcalls after the virtual
8064 registers are instantiated when fpregs are disabled because
8065 the only method that we have for doing DImode multiplication
8066 is with a libcall. This could be trouble if we haven't
8067 allocated enough space for the outgoing arguments. */
8068 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8070 emit_move_insn (arg_pointer_rtx,
8071 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8072 GEN_INT (STACK_POINTER_OFFSET + 64)));
8076 /* Indirect sibling calls are not allowed. */
8078 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8080 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8082 call_insn = emit_call_insn (call_insn);
8085 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8087 /* We don't have to restore the PIC register. */
8089 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8094 (define_insn "sibcall_internal_symref"
8095 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8096 (match_operand 1 "" "i"))
8097 (clobber (reg:SI 1))
8099 (use (const_int 0))]
8100 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8103 output_arg_descriptor (insn);
8104 return output_call (insn, operands[0], 1);
8106 [(set_attr "type" "call")
8107 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8109 (define_insn "sibcall_internal_symref_64bit"
8110 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8111 (match_operand 1 "" "i"))
8112 (clobber (reg:DI 1))
8114 (use (const_int 0))]
8118 output_arg_descriptor (insn);
8119 return output_call (insn, operands[0], 1);
8121 [(set_attr "type" "call")
8122 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8124 (define_expand "sibcall_value"
8125 [(set (match_operand 0 "" "")
8126 (call (match_operand:SI 1 "" "")
8127 (match_operand 2 "" "")))]
8128 "!TARGET_PORTABLE_RUNTIME"
8132 rtx nb = operands[1];
8134 op = XEXP (operands[1], 0);
8138 if (!virtuals_instantiated)
8139 emit_move_insn (arg_pointer_rtx,
8140 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8144 /* The loop pass can generate new libcalls after the virtual
8145 registers are instantiated when fpregs are disabled because
8146 the only method that we have for doing DImode multiplication
8147 is with a libcall. This could be trouble if we haven't
8148 allocated enough space for the outgoing arguments. */
8149 gcc_assert (INTVAL (nb) <= crtl->outgoing_args_size);
8151 emit_move_insn (arg_pointer_rtx,
8152 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8153 GEN_INT (STACK_POINTER_OFFSET + 64)));
8157 /* Indirect sibling calls are not allowed. */
8160 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8163 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8165 call_insn = emit_call_insn (call_insn);
8168 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8170 /* We don't have to restore the PIC register. */
8172 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8177 (define_insn "sibcall_value_internal_symref"
8178 [(set (match_operand 0 "" "")
8179 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8180 (match_operand 2 "" "i")))
8181 (clobber (reg:SI 1))
8183 (use (const_int 0))]
8184 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8187 output_arg_descriptor (insn);
8188 return output_call (insn, operands[1], 1);
8190 [(set_attr "type" "call")
8191 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8193 (define_insn "sibcall_value_internal_symref_64bit"
8194 [(set (match_operand 0 "" "")
8195 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8196 (match_operand 2 "" "i")))
8197 (clobber (reg:DI 1))
8199 (use (const_int 0))]
8203 output_arg_descriptor (insn);
8204 return output_call (insn, operands[1], 1);
8206 [(set_attr "type" "call")
8207 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8213 [(set_attr "type" "move")
8214 (set_attr "length" "4")])
8216 ;; These are just placeholders so we know where branch tables
8218 (define_insn "begin_brtab"
8223 /* Only GAS actually supports this pseudo-op. */
8225 return \".begin_brtab\";
8229 [(set_attr "type" "move")
8230 (set_attr "length" "0")])
8232 (define_insn "end_brtab"
8237 /* Only GAS actually supports this pseudo-op. */
8239 return \".end_brtab\";
8243 [(set_attr "type" "move")
8244 (set_attr "length" "0")])
8246 ;;; EH does longjmp's from and within the data section. Thus,
8247 ;;; an interspace branch is required for the longjmp implementation.
8248 ;;; Registers r1 and r2 are used as scratch registers for the jump
8250 (define_expand "interspace_jump"
8252 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8253 (clobber (match_dup 1))])]
8257 operands[1] = gen_rtx_REG (word_mode, 2);
8261 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8262 (clobber (reg:SI 2))]
8263 "TARGET_PA_20 && !TARGET_64BIT"
8265 [(set_attr "type" "branch")
8266 (set_attr "length" "4")])
8269 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8270 (clobber (reg:SI 2))]
8271 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8273 [(set_attr "type" "branch")
8274 (set_attr "length" "4")])
8277 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8278 (clobber (reg:SI 2))]
8280 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8281 [(set_attr "type" "branch")
8282 (set_attr "length" "12")])
8285 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8286 (clobber (reg:DI 2))]
8289 [(set_attr "type" "branch")
8290 (set_attr "length" "4")])
8292 (define_expand "builtin_longjmp"
8293 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8297 /* The elements of the buffer are, in order: */
8298 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8299 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8300 POINTER_SIZE / BITS_PER_UNIT));
8301 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8302 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8303 rtx pv = gen_rtx_REG (Pmode, 1);
8305 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
8306 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
8308 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8309 instead of the hard_frame_pointer_rtx in the save area. We need
8310 to adjust for the offset between these two values. */
8311 if (GET_CODE (fp) != REG)
8312 fp = force_reg (Pmode, fp);
8313 emit_move_insn (hard_frame_pointer_rtx, plus_constant (fp, -8));
8315 /* This bit is the same as expand_builtin_longjmp. */
8316 emit_stack_restore (SAVE_NONLOCAL, stack);
8317 emit_use (hard_frame_pointer_rtx);
8318 emit_use (stack_pointer_rtx);
8320 /* Load the label we are jumping through into r1 so that we know
8321 where to look for it when we get back to setjmp's function for
8322 restoring the gp. */
8323 emit_move_insn (pv, lab);
8325 /* Prevent the insns above from being scheduled into the delay slot
8326 of the interspace jump because the space register could change. */
8327 emit_insn (gen_blockage ());
8329 emit_jump_insn (gen_interspace_jump (pv));
8334 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8335 (define_expand "extzv"
8336 [(set (match_operand 0 "register_operand" "")
8337 (zero_extract (match_operand 1 "register_operand" "")
8338 (match_operand 2 "uint32_operand" "")
8339 (match_operand 3 "uint32_operand" "")))]
8343 HOST_WIDE_INT len = INTVAL (operands[2]);
8344 HOST_WIDE_INT pos = INTVAL (operands[3]);
8346 /* PA extraction insns don't support zero length bitfields or fields
8347 extending beyond the left or right-most bits. Also, we reject lengths
8348 equal to a word as they are better handled by the move patterns. */
8349 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8352 /* From mips.md: extract_bit_field doesn't verify that our source
8353 matches the predicate, so check it again here. */
8354 if (!register_operand (operands[1], VOIDmode))
8358 emit_insn (gen_extzv_64 (operands[0], operands[1],
8359 operands[2], operands[3]));
8361 emit_insn (gen_extzv_32 (operands[0], operands[1],
8362 operands[2], operands[3]));
8366 (define_insn "extzv_32"
8367 [(set (match_operand:SI 0 "register_operand" "=r")
8368 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8369 (match_operand:SI 2 "uint5_operand" "")
8370 (match_operand:SI 3 "uint5_operand" "")))]
8372 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8373 [(set_attr "type" "shift")
8374 (set_attr "length" "4")])
8377 [(set (match_operand:SI 0 "register_operand" "=r")
8378 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8380 (match_operand:SI 2 "register_operand" "q")))]
8382 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8383 [(set_attr "type" "shift")
8384 (set_attr "length" "4")])
8386 (define_insn "extzv_64"
8387 [(set (match_operand:DI 0 "register_operand" "=r")
8388 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8389 (match_operand:DI 2 "uint32_operand" "")
8390 (match_operand:DI 3 "uint32_operand" "")))]
8392 "extrd,u %1,%3+%2-1,%2,%0"
8393 [(set_attr "type" "shift")
8394 (set_attr "length" "4")])
8397 [(set (match_operand:DI 0 "register_operand" "=r")
8398 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8400 (match_operand:DI 2 "register_operand" "q")))]
8402 "extrd,u %1,%%sar,1,%0"
8403 [(set_attr "type" "shift")
8404 (set_attr "length" "4")])
8406 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8407 (define_expand "extv"
8408 [(set (match_operand 0 "register_operand" "")
8409 (sign_extract (match_operand 1 "register_operand" "")
8410 (match_operand 2 "uint32_operand" "")
8411 (match_operand 3 "uint32_operand" "")))]
8415 HOST_WIDE_INT len = INTVAL (operands[2]);
8416 HOST_WIDE_INT pos = INTVAL (operands[3]);
8418 /* PA extraction insns don't support zero length bitfields or fields
8419 extending beyond the left or right-most bits. Also, we reject lengths
8420 equal to a word as they are better handled by the move patterns. */
8421 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8424 /* From mips.md: extract_bit_field doesn't verify that our source
8425 matches the predicate, so check it again here. */
8426 if (!register_operand (operands[1], VOIDmode))
8430 emit_insn (gen_extv_64 (operands[0], operands[1],
8431 operands[2], operands[3]));
8433 emit_insn (gen_extv_32 (operands[0], operands[1],
8434 operands[2], operands[3]));
8438 (define_insn "extv_32"
8439 [(set (match_operand:SI 0 "register_operand" "=r")
8440 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8441 (match_operand:SI 2 "uint5_operand" "")
8442 (match_operand:SI 3 "uint5_operand" "")))]
8444 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8445 [(set_attr "type" "shift")
8446 (set_attr "length" "4")])
8449 [(set (match_operand:SI 0 "register_operand" "=r")
8450 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8452 (match_operand:SI 2 "register_operand" "q")))]
8454 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8455 [(set_attr "type" "shift")
8456 (set_attr "length" "4")])
8458 (define_insn "extv_64"
8459 [(set (match_operand:DI 0 "register_operand" "=r")
8460 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8461 (match_operand:DI 2 "uint32_operand" "")
8462 (match_operand:DI 3 "uint32_operand" "")))]
8464 "extrd,s %1,%3+%2-1,%2,%0"
8465 [(set_attr "type" "shift")
8466 (set_attr "length" "4")])
8469 [(set (match_operand:DI 0 "register_operand" "=r")
8470 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8472 (match_operand:DI 2 "register_operand" "q")))]
8474 "extrd,s %1,%%sar,1,%0"
8475 [(set_attr "type" "shift")
8476 (set_attr "length" "4")])
8478 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8479 (define_expand "insv"
8480 [(set (zero_extract (match_operand 0 "register_operand" "")
8481 (match_operand 1 "uint32_operand" "")
8482 (match_operand 2 "uint32_operand" ""))
8483 (match_operand 3 "arith5_operand" ""))]
8487 HOST_WIDE_INT len = INTVAL (operands[1]);
8488 HOST_WIDE_INT pos = INTVAL (operands[2]);
8490 /* PA insertion insns don't support zero length bitfields or fields
8491 extending beyond the left or right-most bits. Also, we reject lengths
8492 equal to a word as they are better handled by the move patterns. */
8493 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8496 /* From mips.md: insert_bit_field doesn't verify that our destination
8497 matches the predicate, so check it again here. */
8498 if (!register_operand (operands[0], VOIDmode))
8502 emit_insn (gen_insv_64 (operands[0], operands[1],
8503 operands[2], operands[3]));
8505 emit_insn (gen_insv_32 (operands[0], operands[1],
8506 operands[2], operands[3]));
8510 (define_insn "insv_32"
8511 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8512 (match_operand:SI 1 "uint5_operand" "")
8513 (match_operand:SI 2 "uint5_operand" ""))
8514 (match_operand:SI 3 "arith5_operand" "r,L"))]
8517 {dep|depw} %3,%2+%1-1,%1,%0
8518 {depi|depwi} %3,%2+%1-1,%1,%0"
8519 [(set_attr "type" "shift,shift")
8520 (set_attr "length" "4,4")])
8522 ;; Optimize insertion of const_int values of type 1...1xxxx.
8524 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8525 (match_operand:SI 1 "uint5_operand" "")
8526 (match_operand:SI 2 "uint5_operand" ""))
8527 (match_operand:SI 3 "const_int_operand" ""))]
8528 "(INTVAL (operands[3]) & 0x10) != 0 &&
8529 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8532 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8533 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8535 [(set_attr "type" "shift")
8536 (set_attr "length" "4")])
8538 (define_insn "insv_64"
8539 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8540 (match_operand:DI 1 "uint32_operand" "")
8541 (match_operand:DI 2 "uint32_operand" ""))
8542 (match_operand:DI 3 "arith32_operand" "r,L"))]
8545 depd %3,%2+%1-1,%1,%0
8546 depdi %3,%2+%1-1,%1,%0"
8547 [(set_attr "type" "shift,shift")
8548 (set_attr "length" "4,4")])
8550 ;; Optimize insertion of const_int values of type 1...1xxxx.
8552 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8553 (match_operand:DI 1 "uint32_operand" "")
8554 (match_operand:DI 2 "uint32_operand" ""))
8555 (match_operand:DI 3 "const_int_operand" ""))]
8556 "(INTVAL (operands[3]) & 0x10) != 0
8558 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8561 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8562 return \"depdi %3,%2+%1-1,%1,%0\";
8564 [(set_attr "type" "shift")
8565 (set_attr "length" "4")])
8568 [(set (match_operand:DI 0 "register_operand" "=r")
8569 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8572 "depd,z %1,31,32,%0"
8573 [(set_attr "type" "shift")
8574 (set_attr "length" "4")])
8576 ;; This insn is used for some loop tests, typically loops reversed when
8577 ;; strength reduction is used. It is actually created when the instruction
8578 ;; combination phase combines the special loop test. Since this insn
8579 ;; is both a jump insn and has an output, it must deal with its own
8580 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8581 ;; to not choose the register alternatives in the event a reload is needed.
8582 (define_insn "decrement_and_branch_until_zero"
8585 (match_operator 2 "comparison_operator"
8587 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8588 (match_operand:SI 1 "int5_operand" "L,L,L"))
8590 (label_ref (match_operand 3 "" ""))
8593 (plus:SI (match_dup 0) (match_dup 1)))
8594 (clobber (match_scratch:SI 4 "=X,r,r"))]
8596 "* return output_dbra (operands, insn, which_alternative); "
8597 ;; Do not expect to understand this the first time through.
8598 [(set_attr "type" "cbranch,multi,multi")
8599 (set (attr "length")
8600 (if_then_else (eq_attr "alternative" "0")
8601 ;; Loop counter in register case
8602 ;; Short branch has length of 4
8603 ;; Long branch has length of 8, 20, 24 or 28
8604 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8605 (const_int MAX_12BIT_OFFSET))
8607 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8608 (const_int MAX_17BIT_OFFSET))
8610 (match_test "TARGET_PORTABLE_RUNTIME")
8612 (not (match_test "flag_pic"))
8616 ;; Loop counter in FP reg case.
8617 ;; Extra goo to deal with additional reload insns.
8618 (if_then_else (eq_attr "alternative" "1")
8619 (if_then_else (lt (match_dup 3) (pc))
8620 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8621 (const_int MAX_12BIT_OFFSET))
8623 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8624 (const_int MAX_17BIT_OFFSET))
8626 (match_test "TARGET_PORTABLE_RUNTIME")
8628 (not (match_test "flag_pic"))
8631 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8632 (const_int MAX_12BIT_OFFSET))
8634 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8635 (const_int MAX_17BIT_OFFSET))
8637 (match_test "TARGET_PORTABLE_RUNTIME")
8639 (not (match_test "flag_pic"))
8643 ;; Loop counter in memory case.
8644 ;; Extra goo to deal with additional reload insns.
8645 (if_then_else (lt (match_dup 3) (pc))
8646 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8647 (const_int MAX_12BIT_OFFSET))
8649 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8650 (const_int MAX_17BIT_OFFSET))
8652 (match_test "TARGET_PORTABLE_RUNTIME")
8654 (not (match_test "flag_pic"))
8657 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8658 (const_int MAX_12BIT_OFFSET))
8660 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8661 (const_int MAX_17BIT_OFFSET))
8663 (match_test "TARGET_PORTABLE_RUNTIME")
8665 (not (match_test "flag_pic"))
8667 (const_int 36))))))])
8672 (match_operator 2 "movb_comparison_operator"
8673 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8674 (label_ref (match_operand 3 "" ""))
8676 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8679 "* return output_movb (operands, insn, which_alternative, 0); "
8680 ;; Do not expect to understand this the first time through.
8681 [(set_attr "type" "cbranch,multi,multi,multi")
8682 (set (attr "length")
8683 (if_then_else (eq_attr "alternative" "0")
8684 ;; Loop counter in register case
8685 ;; Short branch has length of 4
8686 ;; Long branch has length of 8, 20, 24 or 28
8687 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8688 (const_int MAX_12BIT_OFFSET))
8690 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8691 (const_int MAX_17BIT_OFFSET))
8693 (match_test "TARGET_PORTABLE_RUNTIME")
8695 (not (match_test "flag_pic"))
8699 ;; Loop counter in FP reg case.
8700 ;; Extra goo to deal with additional reload insns.
8701 (if_then_else (eq_attr "alternative" "1")
8702 (if_then_else (lt (match_dup 3) (pc))
8703 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8704 (const_int MAX_12BIT_OFFSET))
8706 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8707 (const_int MAX_17BIT_OFFSET))
8709 (match_test "TARGET_PORTABLE_RUNTIME")
8711 (not (match_test "flag_pic"))
8714 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8715 (const_int MAX_12BIT_OFFSET))
8717 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8718 (const_int MAX_17BIT_OFFSET))
8720 (match_test "TARGET_PORTABLE_RUNTIME")
8722 (not (match_test "flag_pic"))
8726 ;; Loop counter in memory or sar case.
8727 ;; Extra goo to deal with additional reload insns.
8728 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8729 (const_int MAX_12BIT_OFFSET))
8731 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8732 (const_int MAX_17BIT_OFFSET))
8734 (match_test "TARGET_PORTABLE_RUNTIME")
8736 (not (match_test "flag_pic"))
8738 (const_int 32)))))])
8740 ;; Handle negated branch.
8744 (match_operator 2 "movb_comparison_operator"
8745 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8747 (label_ref (match_operand 3 "" ""))))
8748 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8751 "* return output_movb (operands, insn, which_alternative, 1); "
8752 ;; Do not expect to understand this the first time through.
8753 [(set_attr "type" "cbranch,multi,multi,multi")
8754 (set (attr "length")
8755 (if_then_else (eq_attr "alternative" "0")
8756 ;; Loop counter in register case
8757 ;; Short branch has length of 4
8758 ;; Long branch has length of 8
8759 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8760 (const_int MAX_12BIT_OFFSET))
8762 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8763 (const_int MAX_17BIT_OFFSET))
8765 (match_test "TARGET_PORTABLE_RUNTIME")
8767 (not (match_test "flag_pic"))
8771 ;; Loop counter in FP reg case.
8772 ;; Extra goo to deal with additional reload insns.
8773 (if_then_else (eq_attr "alternative" "1")
8774 (if_then_else (lt (match_dup 3) (pc))
8775 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8776 (const_int MAX_12BIT_OFFSET))
8778 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8779 (const_int MAX_17BIT_OFFSET))
8781 (match_test "TARGET_PORTABLE_RUNTIME")
8783 (not (match_test "flag_pic"))
8786 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8787 (const_int MAX_12BIT_OFFSET))
8789 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8790 (const_int MAX_17BIT_OFFSET))
8792 (match_test "TARGET_PORTABLE_RUNTIME")
8794 (not (match_test "flag_pic"))
8798 ;; Loop counter in memory or SAR case.
8799 ;; Extra goo to deal with additional reload insns.
8800 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8801 (const_int MAX_12BIT_OFFSET))
8803 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8804 (const_int MAX_17BIT_OFFSET))
8806 (match_test "TARGET_PORTABLE_RUNTIME")
8808 (not (match_test "flag_pic"))
8810 (const_int 32)))))])
8813 [(set (pc) (label_ref (match_operand 3 "" "" )))
8814 (set (match_operand:SI 0 "ireg_operand" "=r")
8815 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
8816 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
8817 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
8820 return output_parallel_addb (operands, insn);
8822 [(set_attr "type" "parallel_branch")
8823 (set (attr "length")
8824 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8825 (const_int MAX_12BIT_OFFSET))
8827 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8828 (const_int MAX_17BIT_OFFSET))
8830 (match_test "TARGET_PORTABLE_RUNTIME")
8832 (not (match_test "flag_pic"))
8837 [(set (pc) (label_ref (match_operand 2 "" "" )))
8838 (set (match_operand:SF 0 "ireg_operand" "=r")
8839 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
8843 return output_parallel_movb (operands, insn);
8845 [(set_attr "type" "parallel_branch")
8846 (set (attr "length")
8847 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8848 (const_int MAX_12BIT_OFFSET))
8850 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8851 (const_int MAX_17BIT_OFFSET))
8853 (match_test "TARGET_PORTABLE_RUNTIME")
8855 (not (match_test "flag_pic"))
8860 [(set (pc) (label_ref (match_operand 2 "" "" )))
8861 (set (match_operand:SI 0 "ireg_operand" "=r")
8862 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
8866 return output_parallel_movb (operands, insn);
8868 [(set_attr "type" "parallel_branch")
8869 (set (attr "length")
8870 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8871 (const_int MAX_12BIT_OFFSET))
8873 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8874 (const_int MAX_17BIT_OFFSET))
8876 (match_test "TARGET_PORTABLE_RUNTIME")
8878 (not (match_test "flag_pic"))
8883 [(set (pc) (label_ref (match_operand 2 "" "" )))
8884 (set (match_operand:HI 0 "ireg_operand" "=r")
8885 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
8889 return output_parallel_movb (operands, insn);
8891 [(set_attr "type" "parallel_branch")
8892 (set (attr "length")
8893 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8894 (const_int MAX_12BIT_OFFSET))
8896 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8897 (const_int MAX_17BIT_OFFSET))
8899 (match_test "TARGET_PORTABLE_RUNTIME")
8901 (not (match_test "flag_pic"))
8906 [(set (pc) (label_ref (match_operand 2 "" "" )))
8907 (set (match_operand:QI 0 "ireg_operand" "=r")
8908 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
8912 return output_parallel_movb (operands, insn);
8914 [(set_attr "type" "parallel_branch")
8915 (set (attr "length")
8916 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8917 (const_int MAX_12BIT_OFFSET))
8919 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8920 (const_int MAX_17BIT_OFFSET))
8922 (match_test "TARGET_PORTABLE_RUNTIME")
8924 (not (match_test "flag_pic"))
8929 [(set (match_operand 0 "register_operand" "=f")
8930 (mult (match_operand 1 "register_operand" "f")
8931 (match_operand 2 "register_operand" "f")))
8932 (set (match_operand 3 "register_operand" "+f")
8933 (plus (match_operand 4 "register_operand" "f")
8934 (match_operand 5 "register_operand" "f")))]
8935 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8936 && reload_completed && fmpyaddoperands (operands)"
8939 if (GET_MODE (operands[0]) == DFmode)
8941 if (rtx_equal_p (operands[3], operands[5]))
8942 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8944 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8948 if (rtx_equal_p (operands[3], operands[5]))
8949 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8951 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8954 [(set_attr "type" "fpalu")
8955 (set_attr "length" "4")])
8958 [(set (match_operand 3 "register_operand" "+f")
8959 (plus (match_operand 4 "register_operand" "f")
8960 (match_operand 5 "register_operand" "f")))
8961 (set (match_operand 0 "register_operand" "=f")
8962 (mult (match_operand 1 "register_operand" "f")
8963 (match_operand 2 "register_operand" "f")))]
8964 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8965 && reload_completed && fmpyaddoperands (operands)"
8968 if (GET_MODE (operands[0]) == DFmode)
8970 if (rtx_equal_p (operands[3], operands[5]))
8971 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8973 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8977 if (rtx_equal_p (operands[3], operands[5]))
8978 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8980 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8983 [(set_attr "type" "fpalu")
8984 (set_attr "length" "4")])
8987 [(set (match_operand 0 "register_operand" "=f")
8988 (mult (match_operand 1 "register_operand" "f")
8989 (match_operand 2 "register_operand" "f")))
8990 (set (match_operand 3 "register_operand" "+f")
8991 (minus (match_operand 4 "register_operand" "f")
8992 (match_operand 5 "register_operand" "f")))]
8993 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8994 && reload_completed && fmpysuboperands (operands)"
8997 if (GET_MODE (operands[0]) == DFmode)
8998 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9000 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9002 [(set_attr "type" "fpalu")
9003 (set_attr "length" "4")])
9006 [(set (match_operand 3 "register_operand" "+f")
9007 (minus (match_operand 4 "register_operand" "f")
9008 (match_operand 5 "register_operand" "f")))
9009 (set (match_operand 0 "register_operand" "=f")
9010 (mult (match_operand 1 "register_operand" "f")
9011 (match_operand 2 "register_operand" "f")))]
9012 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9013 && reload_completed && fmpysuboperands (operands)"
9016 if (GET_MODE (operands[0]) == DFmode)
9017 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9019 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9021 [(set_attr "type" "fpalu")
9022 (set_attr "length" "4")])
9024 ;; The following two patterns are used by the trampoline code for nested
9025 ;; functions. They flush the I and D cache lines from the start address
9026 ;; (operand0) to the end address (operand1). No lines are flushed if the
9027 ;; end address is less than the start address (unsigned).
9029 ;; Because the range of memory flushed is variable and the size of a MEM
9030 ;; can only be a CONST_INT, the patterns specify that they perform an
9031 ;; unspecified volatile operation on all memory.
9033 ;; The address range for an icache flush must lie within a single
9034 ;; space on targets with non-equivalent space registers.
9036 ;; Operand 0 contains the start address.
9037 ;; Operand 1 contains the end address.
9038 ;; Operand 2 contains the line length to use.
9039 (define_insn "dcacheflush<P:mode>"
9041 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9042 (use (match_operand 0 "pmode_register_operand" "r"))
9043 (use (match_operand 1 "pmode_register_operand" "r"))
9044 (use (match_operand 2 "pmode_register_operand" "r"))
9045 (clobber (match_scratch:P 3 "=&0"))]
9047 "cmpb,<dwc><<=,n %3,%1,.\;fdc,m %2(%3)\;sync"
9048 [(set_attr "type" "multi")
9049 (set_attr "length" "12")])
9051 (define_insn "icacheflush<P:mode>"
9053 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9054 (use (match_operand 0 "pmode_register_operand" "r"))
9055 (use (match_operand 1 "pmode_register_operand" "r"))
9056 (use (match_operand 2 "pmode_register_operand" "r"))
9057 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9058 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9059 (clobber (match_scratch:P 5 "=&0"))]
9061 "mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<dwc><<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
9062 [(set_attr "type" "multi")
9063 (set_attr "length" "52")])
9065 ;; An out-of-line prologue.
9066 (define_insn "outline_prologue_call"
9067 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9068 (clobber (reg:SI 31))
9069 (clobber (reg:SI 22))
9070 (clobber (reg:SI 21))
9071 (clobber (reg:SI 20))
9072 (clobber (reg:SI 19))
9073 (clobber (reg:SI 1))]
9078 /* We need two different versions depending on whether or not we
9079 need a frame pointer. Also note that we return to the instruction
9080 immediately after the branch rather than two instructions after the
9081 break as normally is the case. */
9082 if (frame_pointer_needed)
9084 /* Must import the magic millicode routine(s). */
9085 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9087 if (TARGET_PORTABLE_RUNTIME)
9089 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9090 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9094 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9098 /* Must import the magic millicode routine(s). */
9099 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9101 if (TARGET_PORTABLE_RUNTIME)
9103 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9104 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9107 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9111 [(set_attr "type" "multi")
9112 (set_attr "length" "8")])
9114 ;; An out-of-line epilogue.
9115 (define_insn "outline_epilogue_call"
9116 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9119 (clobber (reg:SI 31))
9120 (clobber (reg:SI 22))
9121 (clobber (reg:SI 21))
9122 (clobber (reg:SI 20))
9123 (clobber (reg:SI 19))
9124 (clobber (reg:SI 2))
9125 (clobber (reg:SI 1))]
9130 /* We need two different versions depending on whether or not we
9131 need a frame pointer. Also note that we return to the instruction
9132 immediately after the branch rather than two instructions after the
9133 break as normally is the case. */
9134 if (frame_pointer_needed)
9136 /* Must import the magic millicode routine. */
9137 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9139 /* The out-of-line prologue will make sure we return to the right
9141 if (TARGET_PORTABLE_RUNTIME)
9143 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9144 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9148 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9152 /* Must import the magic millicode routine. */
9153 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9155 /* The out-of-line prologue will make sure we return to the right
9157 if (TARGET_PORTABLE_RUNTIME)
9159 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9160 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9163 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9167 [(set_attr "type" "multi")
9168 (set_attr "length" "8")])
9170 ;; Given a function pointer, canonicalize it so it can be
9171 ;; reliably compared to another function pointer. */
9172 (define_expand "canonicalize_funcptr_for_compare"
9173 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9174 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9175 (clobber (match_dup 2))
9176 (clobber (reg:SI 26))
9177 (clobber (reg:SI 22))
9178 (clobber (reg:SI 31))])
9179 (set (match_operand:SI 0 "register_operand" "")
9181 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9186 rtx canonicalize_funcptr_for_compare_libfunc
9187 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9189 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9190 operands[0], LCT_NORMAL, Pmode,
9191 1, operands[1], Pmode);
9195 operands[2] = gen_reg_rtx (SImode);
9196 if (GET_CODE (operands[1]) != REG)
9198 rtx tmp = gen_reg_rtx (Pmode);
9199 emit_move_insn (tmp, operands[1]);
9204 (define_insn "*$$sh_func_adrs"
9205 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9206 (clobber (match_operand:SI 0 "register_operand" "=a"))
9207 (clobber (reg:SI 26))
9208 (clobber (reg:SI 22))
9209 (clobber (reg:SI 31))]
9213 int length = get_attr_length (insn);
9216 xoperands[0] = GEN_INT (length - 8);
9217 xoperands[1] = GEN_INT (length - 16);
9219 /* Must import the magic millicode routine. */
9220 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9222 /* This is absolutely amazing.
9224 First, copy our input parameter into %r29 just in case we don't
9225 need to call $$sh_func_adrs. */
9226 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9227 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9229 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9230 we use %r26 unchanged. */
9231 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9232 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9234 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9235 4096, then again we use %r26 unchanged. */
9236 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9238 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9239 return output_millicode_call (insn,
9240 gen_rtx_SYMBOL_REF (SImode,
9241 \"$$sh_func_adrs\"));
9243 [(set_attr "type" "multi")
9244 (set (attr "length")
9245 (plus (symbol_ref "attr_length_millicode_call (insn)")
9248 ;; On the PA, the PIC register is call clobbered, so it must
9249 ;; be saved & restored around calls by the caller. If the call
9250 ;; doesn't return normally (nonlocal goto, or an exception is
9251 ;; thrown), then the code at the exception handler label must
9252 ;; restore the PIC register.
9253 (define_expand "exception_receiver"
9258 /* On the 64-bit port, we need a blockage because there is
9259 confusion regarding the dependence of the restore on the
9260 frame pointer. As a result, the frame pointer and pic
9261 register restores sometimes are interchanged erroneously. */
9263 emit_insn (gen_blockage ());
9264 /* Restore the PIC register using hppa_pic_save_rtx (). The
9265 PIC register is not saved in the frame in 64-bit ABI. */
9266 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9267 emit_insn (gen_blockage ());
9271 (define_expand "builtin_setjmp_receiver"
9272 [(label_ref (match_operand 0 "" ""))]
9277 emit_insn (gen_blockage ());
9278 /* Restore the PIC register. Hopefully, this will always be from
9279 a stack slot. The only registers that are valid after a
9280 builtin_longjmp are the stack and frame pointers. */
9281 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9282 emit_insn (gen_blockage ());
9286 ;; Allocate new stack space and update the saved stack pointer in the
9287 ;; frame marker. The HP C compilers also copy additional words in the
9288 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9289 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9290 ;; currently don't copy these values.
9292 ;; Since the copy of the frame marker can't be done atomically, I
9293 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9294 ;; The HP compilers appear to raise the stack and copy the frame
9295 ;; marker in a strict instruction sequence. This suggests that the
9296 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9297 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9298 ;; as GAS doesn't support it, or try to keep the instructions emitted
9299 ;; here in strict sequence.
9300 (define_expand "allocate_stack"
9301 [(match_operand 0 "" "")
9302 (match_operand 1 "" "")]
9308 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9309 in operand 0 before adjusting the stack. */
9310 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9311 anti_adjust_stack (operands[1]);
9312 if (TARGET_HPUX_UNWIND_LIBRARY)
9314 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9315 GEN_INT (TARGET_64BIT ? -8 : -4));
9316 emit_move_insn (gen_rtx_MEM (word_mode, addr), hard_frame_pointer_rtx);
9318 if (!TARGET_64BIT && flag_pic)
9320 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9321 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9326 (define_expand "prefetch"
9327 [(match_operand 0 "address_operand" "")
9328 (match_operand 1 "const_int_operand" "")
9329 (match_operand 2 "const_int_operand" "")]
9332 operands[0] = copy_addr_to_reg (operands[0]);
9333 emit_insn (gen_prefetch_20 (operands[0], operands[1], operands[2]));
9337 (define_insn "prefetch_20"
9338 [(prefetch (match_operand 0 "pmode_register_operand" "r")
9339 (match_operand:SI 1 "const_int_operand" "n")
9340 (match_operand:SI 2 "const_int_operand" "n"))]
9343 /* The SL cache-control completer indicates good spatial locality but
9344 poor temporal locality. The ldw instruction with a target of general
9345 register 0 prefetches a cache line for a read. The ldd instruction
9346 prefetches a cache line for a write. */
9347 static const char * const instr[2][2] = {
9349 "ldw,sl 0(%0),%%r0",
9357 int read_or_write = INTVAL (operands[1]) == 0 ? 0 : 1;
9358 int locality = INTVAL (operands[2]) == 0 ? 0 : 1;
9360 return instr [locality][read_or_write];
9362 [(set_attr "type" "load")
9363 (set_attr "length" "4")])
9366 (define_insn "tgd_load"
9367 [(set (match_operand:SI 0 "register_operand" "=r")
9368 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
9369 (clobber (reg:SI 1))
9374 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
9376 [(set_attr "type" "multi")
9377 (set_attr "length" "8")])
9379 (define_insn "tgd_load_pic"
9380 [(set (match_operand:SI 0 "register_operand" "=r")
9381 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD_PIC))
9382 (clobber (reg:SI 1))
9387 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
9389 [(set_attr "type" "multi")
9390 (set_attr "length" "8")])
9392 (define_insn "tld_load"
9393 [(set (match_operand:SI 0 "register_operand" "=r")
9394 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
9395 (clobber (reg:SI 1))
9400 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
9402 [(set_attr "type" "multi")
9403 (set_attr "length" "8")])
9405 (define_insn "tld_load_pic"
9406 [(set (match_operand:SI 0 "register_operand" "=r")
9407 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM_PIC))
9408 (clobber (reg:SI 1))
9413 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
9415 [(set_attr "type" "multi")
9416 (set_attr "length" "8")])
9418 (define_insn "tld_offset_load"
9419 [(set (match_operand:SI 0 "register_operand" "=r")
9420 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
9422 (match_operand:SI 2 "register_operand" "r")))
9423 (clobber (reg:SI 1))]
9427 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
9429 [(set_attr "type" "multi")
9430 (set_attr "length" "8")])
9432 (define_insn "tp_load"
9433 [(set (match_operand:SI 0 "register_operand" "=r")
9434 (unspec:SI [(const_int 0)] UNSPEC_TP))]
9437 [(set_attr "type" "multi")
9438 (set_attr "length" "4")])
9440 (define_insn "tie_load"
9441 [(set (match_operand:SI 0 "register_operand" "=r")
9442 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
9443 (clobber (reg:SI 1))
9448 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
9450 [(set_attr "type" "multi")
9451 (set_attr "length" "8")])
9453 (define_insn "tie_load_pic"
9454 [(set (match_operand:SI 0 "register_operand" "=r")
9455 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE_PIC))
9456 (clobber (reg:SI 1))
9461 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
9463 [(set_attr "type" "multi")
9464 (set_attr "length" "8")])
9466 (define_insn "tle_load"
9467 [(set (match_operand:SI 0 "register_operand" "=r")
9468 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
9470 (match_operand:SI 2 "register_operand" "r")))
9471 (clobber (reg:SI 1))]
9473 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
9474 [(set_attr "type" "multi")
9475 (set_attr "length" "8")])