1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 93-98, 1999 Free Software Foundation, Inc.
3 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-flags.h"
33 #include "insn-attr.h"
42 static void restore_unscaled_index_insn_codes PROTO((rtx));
43 static void record_unscaled_index_insn_codes PROTO((rtx));
44 static void pa_combine_instructions PROTO((rtx));
45 static int pa_can_combine_p PROTO((rtx, rtx, rtx, int, rtx, rtx, rtx));
46 static int forward_branch_p PROTO((rtx));
47 static int shadd_constant_p PROTO((int));
49 /* Save the operands last given to a compare for use when we
50 generate a scc or bcc insn. */
52 rtx hppa_compare_op0, hppa_compare_op1;
53 enum cmp_type hppa_branch_type;
55 /* Which cpu we are scheduling for. */
56 enum processor_type pa_cpu;
58 /* String to hold which cpu we are scheduling for. */
61 /* Which architecture we are generating code for. */
62 enum architecture_type pa_arch;
64 /* String to hold which architecture we are generating code for. */
67 /* Set by the FUNCTION_PROFILER macro. */
68 int hp_profile_labelno;
70 /* Counts for the number of callee-saved general and floating point
71 registers which were saved by the current function's prologue. */
72 static int gr_saved, fr_saved;
74 static rtx find_addr_reg ();
76 /* Keep track of the number of bytes we have output in the CODE subspaces
77 during this compilation so we'll know when to emit inline long-calls. */
79 unsigned int total_code_bytes;
81 /* Variables to handle plabels that we discover are necessary at assembly
82 output time. They are output after the current function. */
84 struct deferred_plabel
88 } *deferred_plabels = 0;
89 int n_deferred_plabels = 0;
91 /* Array indexed by INSN_UIDs holding the INSN_CODE of an insn which
92 uses an unscaled indexed address before delay slot scheduling. */
93 static int *unscaled_index_insn_codes;
95 /* Upper bound for the array. */
96 static int max_unscaled_index_insn_codes_uid;
101 /* Default to 7100LC scheduling. */
102 if (pa_cpu_string && ! strcmp (pa_cpu_string, "7100"))
104 pa_cpu_string = "7100";
105 pa_cpu = PROCESSOR_7100;
107 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "700"))
109 pa_cpu_string = "700";
110 pa_cpu = PROCESSOR_700;
112 else if (pa_cpu_string == NULL
113 || ! strcmp (pa_cpu_string, "7100LC"))
115 pa_cpu_string = "7100LC";
116 pa_cpu = PROCESSOR_7100LC;
118 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "7200"))
120 pa_cpu_string = "7200";
121 pa_cpu = PROCESSOR_7200;
123 else if (pa_cpu_string && ! strcmp (pa_cpu_string, "8000"))
125 pa_cpu_string = "8000";
126 pa_cpu = PROCESSOR_8000;
130 warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n", pa_cpu_string);
133 /* Set the instruction set architecture. */
134 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
136 pa_arch_string = "1.0";
137 pa_arch = ARCHITECTURE_10;
138 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
140 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
142 pa_arch_string = "1.1";
143 pa_arch = ARCHITECTURE_11;
144 target_flags &= ~MASK_PA_20;
145 target_flags |= MASK_PA_11;
147 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
149 pa_arch_string = "2.0";
150 pa_arch = ARCHITECTURE_20;
151 target_flags |= MASK_PA_11 | MASK_PA_20;
153 else if (pa_arch_string)
155 warning ("Unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
158 if (flag_pic && TARGET_PORTABLE_RUNTIME)
160 warning ("PIC code generation is not supported in the portable runtime model\n");
163 if (flag_pic && (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS))
165 warning ("PIC code generation is not compatible with fast indirect calls\n");
168 if (flag_pic && profile_flag)
170 warning ("PIC code generation is not compatible with profiling\n");
173 if (! TARGET_GAS && write_symbols != NO_DEBUG)
175 warning ("-g is only supported when using GAS on this processor,");
176 warning ("-g option disabled.");
177 write_symbols = NO_DEBUG;
182 /* Return non-zero only if OP is a register of mode MODE,
185 reg_or_0_operand (op, mode)
187 enum machine_mode mode;
189 return (op == CONST0_RTX (mode) || register_operand (op, mode));
192 /* Return non-zero if OP is suitable for use in a call to a named
195 (???) For 2.5 try to eliminate either call_operand_address or
196 function_label_operand, they perform very similar functions. */
198 call_operand_address (op, mode)
200 enum machine_mode mode ATTRIBUTE_UNUSED;
202 return (CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
205 /* Return 1 if X contains a symbolic expression. We know these
206 expressions will have one of a few well defined forms, so
207 we need only check those forms. */
209 symbolic_expression_p (x)
213 /* Strip off any HIGH. */
214 if (GET_CODE (x) == HIGH)
217 return (symbolic_operand (x, VOIDmode));
221 symbolic_operand (op, mode)
223 enum machine_mode mode ATTRIBUTE_UNUSED;
225 switch (GET_CODE (op))
232 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
233 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
234 && GET_CODE (XEXP (op, 1)) == CONST_INT);
240 /* Return truth value of statement that OP is a symbolic memory
241 operand of mode MODE. */
244 symbolic_memory_operand (op, mode)
246 enum machine_mode mode ATTRIBUTE_UNUSED;
248 if (GET_CODE (op) == SUBREG)
249 op = SUBREG_REG (op);
250 if (GET_CODE (op) != MEM)
253 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
254 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
257 /* Return 1 if the operand is either a register or a memory operand that is
261 reg_or_nonsymb_mem_operand (op, mode)
263 enum machine_mode mode;
265 if (register_operand (op, mode))
268 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
274 /* Return 1 if the operand is either a register, zero, or a memory operand
275 that is not symbolic. */
278 reg_or_0_or_nonsymb_mem_operand (op, mode)
280 enum machine_mode mode;
282 if (register_operand (op, mode))
285 if (op == CONST0_RTX (mode))
288 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
294 /* Accept any constant that can be moved in one instructions into a
297 cint_ok_for_move (intval)
298 HOST_WIDE_INT intval;
300 /* OK if ldo, ldil, or zdepi, can be used. */
301 return (VAL_14_BITS_P (intval) || (intval & 0x7ff) == 0
302 || zdepi_cint_p (intval));
305 /* Accept anything that can be moved in one instruction into a general
308 move_operand (op, mode)
310 enum machine_mode mode;
312 if (register_operand (op, mode))
315 if (GET_CODE (op) == CONSTANT_P_RTX)
318 if (GET_CODE (op) == CONST_INT)
319 return cint_ok_for_move (INTVAL (op));
321 if (GET_CODE (op) == SUBREG)
322 op = SUBREG_REG (op);
323 if (GET_CODE (op) != MEM)
327 if (GET_CODE (op) == LO_SUM)
328 return (register_operand (XEXP (op, 0), Pmode)
329 && CONSTANT_P (XEXP (op, 1)));
331 /* Since move_operand is only used for source operands, we can always
332 allow scaled indexing! */
333 if (! TARGET_DISABLE_INDEXING
334 && GET_CODE (op) == PLUS
335 && ((GET_CODE (XEXP (op, 0)) == MULT
336 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
337 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
338 && INTVAL (XEXP (XEXP (op, 0), 1)) == GET_MODE_SIZE (mode)
339 && GET_CODE (XEXP (op, 1)) == REG)
340 || (GET_CODE (XEXP (op, 1)) == MULT
341 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
342 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
343 && INTVAL (XEXP (XEXP (op, 1), 1)) == GET_MODE_SIZE (mode)
344 && GET_CODE (XEXP (op, 0)) == REG)))
347 return memory_address_p (mode, op);
350 /* Accept REG and any CONST_INT that can be moved in one instruction into a
353 reg_or_cint_move_operand (op, mode)
355 enum machine_mode mode;
357 if (register_operand (op, mode))
360 if (GET_CODE (op) == CONST_INT)
361 return cint_ok_for_move (INTVAL (op));
367 pic_label_operand (op, mode)
369 enum machine_mode mode ATTRIBUTE_UNUSED;
374 switch (GET_CODE (op))
380 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
381 && GET_CODE (XEXP (op, 1)) == CONST_INT);
388 fp_reg_operand (op, mode)
390 enum machine_mode mode ATTRIBUTE_UNUSED;
392 return reg_renumber && FP_REG_P (op);
397 /* Return truth value of whether OP can be used as an operand in a
398 three operand arithmetic insn that accepts registers of mode MODE
399 or 14-bit signed integers. */
401 arith_operand (op, mode)
403 enum machine_mode mode;
405 return (register_operand (op, mode)
406 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
409 /* Return truth value of whether OP can be used as an operand in a
410 three operand arithmetic insn that accepts registers of mode MODE
411 or 11-bit signed integers. */
413 arith11_operand (op, mode)
415 enum machine_mode mode;
417 return (register_operand (op, mode)
418 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
421 /* A constant integer suitable for use in a PRE_MODIFY memory
424 pre_cint_operand (op, mode)
426 enum machine_mode mode ATTRIBUTE_UNUSED;
428 return (GET_CODE (op) == CONST_INT
429 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
432 /* A constant integer suitable for use in a POST_MODIFY memory
435 post_cint_operand (op, mode)
437 enum machine_mode mode ATTRIBUTE_UNUSED;
439 return (GET_CODE (op) == CONST_INT
440 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
444 arith_double_operand (op, mode)
446 enum machine_mode mode;
448 return (register_operand (op, mode)
449 || (GET_CODE (op) == CONST_DOUBLE
450 && GET_MODE (op) == mode
451 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
452 && ((CONST_DOUBLE_HIGH (op) >= 0)
453 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
456 /* Return truth value of whether OP is a integer which fits the
457 range constraining immediate operands in three-address insns, or
458 is an integer register. */
461 ireg_or_int5_operand (op, mode)
463 enum machine_mode mode ATTRIBUTE_UNUSED;
465 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
466 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
469 /* Return truth value of whether OP is a integer which fits the
470 range constraining immediate operands in three-address insns. */
473 int5_operand (op, mode)
475 enum machine_mode mode ATTRIBUTE_UNUSED;
477 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
481 uint5_operand (op, mode)
483 enum machine_mode mode ATTRIBUTE_UNUSED;
485 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
489 int11_operand (op, mode)
491 enum machine_mode mode ATTRIBUTE_UNUSED;
493 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
497 uint32_operand (op, mode)
499 enum machine_mode mode ATTRIBUTE_UNUSED;
501 #if HOST_BITS_PER_WIDE_INT > 32
502 /* All allowed constants will fit a CONST_INT. */
503 return (GET_CODE (op) == CONST_INT
504 && (INTVAL (op) >= 0 && INTVAL (op) < 0x100000000L));
506 return (GET_CODE (op) == CONST_INT
507 || (GET_CODE (op) == CONST_DOUBLE
508 && CONST_DOUBLE_HIGH (op) == 0));
513 arith5_operand (op, mode)
515 enum machine_mode mode;
517 return register_operand (op, mode) || int5_operand (op, mode);
520 /* True iff zdepi can be used to generate this CONST_INT. */
523 unsigned HOST_WIDE_INT x;
525 unsigned HOST_WIDE_INT lsb_mask, t;
527 /* This might not be obvious, but it's at least fast.
528 This function is critical; we don't have the time loops would take. */
530 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
531 /* Return true iff t is a power of two. */
532 return ((t & (t - 1)) == 0);
535 /* True iff depi or extru can be used to compute (reg & mask).
536 Accept bit pattern like these:
542 unsigned HOST_WIDE_INT mask;
545 mask += mask & -mask;
546 return (mask & (mask - 1)) == 0;
549 /* True iff depi or extru can be used to compute (reg & OP). */
551 and_operand (op, mode)
553 enum machine_mode mode;
555 return (register_operand (op, mode)
556 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
559 /* True iff depi can be used to compute (reg | MASK). */
562 unsigned HOST_WIDE_INT mask;
564 mask += mask & -mask;
565 return (mask & (mask - 1)) == 0;
568 /* True iff depi can be used to compute (reg | OP). */
570 ior_operand (op, mode)
572 enum machine_mode mode ATTRIBUTE_UNUSED;
574 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
578 lhs_lshift_operand (op, mode)
580 enum machine_mode mode;
582 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
585 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
586 Such values can be the left hand side x in (x << r), using the zvdepi
589 lhs_lshift_cint_operand (op, mode)
591 enum machine_mode mode ATTRIBUTE_UNUSED;
593 unsigned HOST_WIDE_INT x;
594 if (GET_CODE (op) != CONST_INT)
596 x = INTVAL (op) >> 4;
597 return (x & (x + 1)) == 0;
601 arith32_operand (op, mode)
603 enum machine_mode mode;
605 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
609 pc_or_label_operand (op, mode)
611 enum machine_mode mode ATTRIBUTE_UNUSED;
613 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
616 /* Legitimize PIC addresses. If the address is already
617 position-independent, we return ORIG. Newly generated
618 position-independent addresses go to REG. If we need more
619 than one register, we lose. */
622 legitimize_pic_address (orig, mode, reg)
624 enum machine_mode mode ATTRIBUTE_UNUSED;
628 /* Labels need special handling. */
629 if (pic_label_operand (orig))
631 emit_insn (gen_pic_load_label (reg, orig));
632 current_function_uses_pic_offset_table = 1;
635 if (GET_CODE (orig) == SYMBOL_REF)
643 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
644 gen_rtx_HIGH (word_mode, orig)));
646 = gen_rtx_MEM (Pmode,
647 gen_rtx_LO_SUM (Pmode, reg,
648 gen_rtx_UNSPEC (Pmode,
653 pic_ref = gen_rtx_MEM (Pmode,
655 pic_offset_table_rtx, orig));
656 current_function_uses_pic_offset_table = 1;
657 RTX_UNCHANGING_P (pic_ref) = 1;
658 emit_move_insn (reg, pic_ref);
661 else if (GET_CODE (orig) == CONST)
665 if (GET_CODE (XEXP (orig, 0)) == PLUS
666 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
672 if (GET_CODE (XEXP (orig, 0)) == PLUS)
674 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
675 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
676 base == reg ? 0 : reg);
679 if (GET_CODE (orig) == CONST_INT)
681 if (INT_14_BITS (orig))
682 return plus_constant_for_output (base, INTVAL (orig));
683 orig = force_reg (Pmode, orig);
685 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
686 /* Likewise, should we set special REG_NOTEs here? */
691 /* Try machine-dependent ways of modifying an illegitimate address
692 to be legitimate. If we find one, return the new, valid address.
693 This macro is used in only one place: `memory_address' in explow.c.
695 OLDX is the address as it was before break_out_memory_refs was called.
696 In some cases it is useful to look at this to decide what needs to be done.
698 MODE and WIN are passed so that this macro can use
699 GO_IF_LEGITIMATE_ADDRESS.
701 It is always safe for this macro to do nothing. It exists to recognize
702 opportunities to optimize the output.
704 For the PA, transform:
706 memory(X + <large int>)
710 if (<large int> & mask) >= 16
711 Y = (<large int> & ~mask) + mask + 1 Round up.
713 Y = (<large int> & ~mask) Round down.
715 memory (Z + (<large int> - Y));
717 This is for CSE to find several similar references, and only use one Z.
719 X can either be a SYMBOL_REF or REG, but because combine can not
720 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
721 D will not fit in 14 bits.
723 MODE_FLOAT references allow displacements which fit in 5 bits, so use
726 MODE_INT references allow displacements which fit in 14 bits, so use
729 This relies on the fact that most mode MODE_FLOAT references will use FP
730 registers and most mode MODE_INT references will use integer registers.
731 (In the rare case of an FP register used in an integer MODE, we depend
732 on secondary reloads to clean things up.)
735 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
736 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
737 addressing modes to be used).
739 Put X and Z into registers. Then put the entire expression into
743 hppa_legitimize_address (x, oldx, mode)
744 rtx x, oldx ATTRIBUTE_UNUSED;
745 enum machine_mode mode;
750 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
752 /* Strip off CONST. */
753 if (GET_CODE (x) == CONST)
756 /* Special case. Get the SYMBOL_REF into a register and use indexing.
757 That should always be safe. */
758 if (GET_CODE (x) == PLUS
759 && GET_CODE (XEXP (x, 0)) == REG
760 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
762 rtx reg = force_reg (Pmode, XEXP (x, 1));
763 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
766 /* Note we must reject symbols which represent function addresses
767 since the assembler/linker can't handle arithmetic on plabels. */
768 if (GET_CODE (x) == PLUS
769 && GET_CODE (XEXP (x, 1)) == CONST_INT
770 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
771 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
772 || GET_CODE (XEXP (x, 0)) == REG))
774 rtx int_part, ptr_reg;
776 int offset = INTVAL (XEXP (x, 1));
777 int mask = GET_MODE_CLASS (mode) == MODE_FLOAT ? 0x1f : 0x3fff;
779 /* Choose which way to round the offset. Round up if we
780 are >= halfway to the next boundary. */
781 if ((offset & mask) >= ((mask + 1) / 2))
782 newoffset = (offset & ~ mask) + mask + 1;
784 newoffset = (offset & ~ mask);
786 /* If the newoffset will not fit in 14 bits (ldo), then
787 handling this would take 4 or 5 instructions (2 to load
788 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
789 add the new offset and the SYMBOL_REF.) Combine can
790 not handle 4->2 or 5->2 combinations, so do not create
792 if (! VAL_14_BITS_P (newoffset)
793 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
796 = gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (Pmode,
798 GEN_INT (newoffset)));
801 gen_rtx_HIGH (Pmode, const_part));
804 gen_rtx_LO_SUM (Pmode, tmp_reg, const_part));
808 if (! VAL_14_BITS_P (newoffset))
809 int_part = force_reg (Pmode, GEN_INT (newoffset));
811 int_part = GEN_INT (newoffset);
813 ptr_reg = force_reg (Pmode,
815 force_reg (Pmode, XEXP (x, 0)),
818 return plus_constant (ptr_reg, offset - newoffset);
821 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
823 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
824 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
825 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
826 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
827 || GET_CODE (XEXP (x, 1)) == SUBREG)
828 && GET_CODE (XEXP (x, 1)) != CONST)
830 int val = INTVAL (XEXP (XEXP (x, 0), 1));
834 if (GET_CODE (reg1) != REG)
835 reg1 = force_reg (Pmode, force_operand (reg1, 0));
837 reg2 = XEXP (XEXP (x, 0), 0);
838 if (GET_CODE (reg2) != REG)
839 reg2 = force_reg (Pmode, force_operand (reg2, 0));
841 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
842 gen_rtx_MULT (Pmode, reg2,
847 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
849 Only do so for floating point modes since this is more speculative
850 and we lose if it's an integer store. */
851 if (GET_CODE (x) == PLUS
852 && GET_CODE (XEXP (x, 0)) == PLUS
853 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
854 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
855 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
856 && (mode == SFmode || mode == DFmode))
859 /* First, try and figure out what to use as a base register. */
860 rtx reg1, reg2, base, idx, orig_base;
862 reg1 = XEXP (XEXP (x, 0), 1);
867 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
868 then emit_move_sequence will turn on REGNO_POINTER_FLAG so we'll
869 know it's a base register below. */
870 if (GET_CODE (reg1) != REG)
871 reg1 = force_reg (Pmode, force_operand (reg1, 0));
873 if (GET_CODE (reg2) != REG)
874 reg2 = force_reg (Pmode, force_operand (reg2, 0));
876 /* Figure out what the base and index are. */
878 if (GET_CODE (reg1) == REG
879 && REGNO_POINTER_FLAG (REGNO (reg1)))
882 orig_base = XEXP (XEXP (x, 0), 1);
883 idx = gen_rtx_PLUS (Pmode,
885 XEXP (XEXP (XEXP (x, 0), 0), 0),
886 XEXP (XEXP (XEXP (x, 0), 0), 1)),
889 else if (GET_CODE (reg2) == REG
890 && REGNO_POINTER_FLAG (REGNO (reg2)))
893 orig_base = XEXP (x, 1);
900 /* If the index adds a large constant, try to scale the
901 constant so that it can be loaded with only one insn. */
902 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
903 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
904 / INTVAL (XEXP (XEXP (idx, 0), 1)))
905 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
907 /* Divide the CONST_INT by the scale factor, then add it to A. */
908 int val = INTVAL (XEXP (idx, 1));
910 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
911 reg1 = XEXP (XEXP (idx, 0), 0);
912 if (GET_CODE (reg1) != REG)
913 reg1 = force_reg (Pmode, force_operand (reg1, 0));
915 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
917 /* We can now generate a simple scaled indexed address. */
918 return force_reg (Pmode,
920 gen_rtx_MULT (Pmode, reg1,
921 XEXP (XEXP (idx, 0), 1)),
925 /* If B + C is still a valid base register, then add them. */
926 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
927 && INTVAL (XEXP (idx, 1)) <= 4096
928 && INTVAL (XEXP (idx, 1)) >= -4096)
930 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
933 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
935 reg2 = XEXP (XEXP (idx, 0), 0);
936 if (GET_CODE (reg2) != CONST_INT)
937 reg2 = force_reg (Pmode, force_operand (reg2, 0));
939 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
940 gen_rtx_MULT (Pmode, reg2,
945 /* Get the index into a register, then add the base + index and
946 return a register holding the result. */
948 /* First get A into a register. */
949 reg1 = XEXP (XEXP (idx, 0), 0);
950 if (GET_CODE (reg1) != REG)
951 reg1 = force_reg (Pmode, force_operand (reg1, 0));
953 /* And get B into a register. */
954 reg2 = XEXP (idx, 1);
955 if (GET_CODE (reg2) != REG)
956 reg2 = force_reg (Pmode, force_operand (reg2, 0));
958 reg1 = force_reg (Pmode,
960 gen_rtx_MULT (Pmode, reg1,
961 XEXP (XEXP (idx, 0), 1)),
964 /* Add the result to our base register and return. */
965 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
969 /* Uh-oh. We might have an address for x[n-100000]. This needs
970 special handling to avoid creating an indexed memory address
971 with x-100000 as the base.
973 If the constant part is small enough, then it's still safe because
974 there is a guard page at the beginning and end of the data segment.
976 Scaled references are common enough that we want to try and rearrange the
977 terms so that we can use indexing for these addresses too. Only
978 do the optimization for floatint point modes. */
980 if (GET_CODE (x) == PLUS
981 && symbolic_expression_p (XEXP (x, 1)))
983 /* Ugly. We modify things here so that the address offset specified
984 by the index expression is computed first, then added to x to form
985 the entire address. */
987 rtx regx1, regx2, regy1, regy2, y;
989 /* Strip off any CONST. */
991 if (GET_CODE (y) == CONST)
994 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
996 /* See if this looks like
997 (plus (mult (reg) (shadd_const))
998 (const (plus (symbol_ref) (const_int))))
1000 Where const_int is small. In that case the const
1001 expression is a valid pointer for indexing.
1003 If const_int is big, but can be divided evenly by shadd_const
1004 and added to (reg). This allows more scaled indexed addresses. */
1005 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1006 && GET_CODE (XEXP (x, 0)) == MULT
1007 && GET_CODE (XEXP (y, 1)) == CONST_INT
1008 && INTVAL (XEXP (y, 1)) >= -4096
1009 && INTVAL (XEXP (y, 1)) <= 4095
1010 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1011 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1013 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1017 if (GET_CODE (reg1) != REG)
1018 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1020 reg2 = XEXP (XEXP (x, 0), 0);
1021 if (GET_CODE (reg2) != REG)
1022 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1024 return force_reg (Pmode,
1025 gen_rtx_PLUS (Pmode,
1026 gen_rtx_MULT (Pmode, reg2,
1030 else if ((mode == DFmode || mode == SFmode)
1031 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1032 && GET_CODE (XEXP (x, 0)) == MULT
1033 && GET_CODE (XEXP (y, 1)) == CONST_INT
1034 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1035 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1036 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1039 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1040 / INTVAL (XEXP (XEXP (x, 0), 1))));
1041 regx2 = XEXP (XEXP (x, 0), 0);
1042 if (GET_CODE (regx2) != REG)
1043 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1044 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1046 return force_reg (Pmode,
1047 gen_rtx_PLUS (Pmode,
1048 gen_rtx_MULT (Pmode, regx2,
1051 force_reg (Pmode, XEXP (y, 0))));
1053 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1054 && INTVAL (XEXP (y, 1)) >= -4096
1055 && INTVAL (XEXP (y, 1)) <= 4095)
1057 /* This is safe because of the guard page at the
1058 beginning and end of the data space. Just
1059 return the original address. */
1064 /* Doesn't look like one we can optimize. */
1065 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1066 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1067 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1068 regx1 = force_reg (Pmode,
1069 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1071 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1079 /* For the HPPA, REG and REG+CONST is cost 0
1080 and addresses involving symbolic constants are cost 2.
1082 PIC addresses are very expensive.
1084 It is no coincidence that this has the same structure
1085 as GO_IF_LEGITIMATE_ADDRESS. */
1087 hppa_address_cost (X)
1090 if (GET_CODE (X) == PLUS)
1092 else if (GET_CODE (X) == LO_SUM)
1094 else if (GET_CODE (X) == HIGH)
1099 /* Emit insns to move operands[1] into operands[0].
1101 Return 1 if we have written out everything that needs to be done to
1102 do the move. Otherwise, return 0 and the caller will emit the move
1106 emit_move_sequence (operands, mode, scratch_reg)
1108 enum machine_mode mode;
1111 register rtx operand0 = operands[0];
1112 register rtx operand1 = operands[1];
1116 && reload_in_progress && GET_CODE (operand0) == REG
1117 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1118 operand0 = reg_equiv_mem[REGNO (operand0)];
1119 else if (scratch_reg
1120 && reload_in_progress && GET_CODE (operand0) == SUBREG
1121 && GET_CODE (SUBREG_REG (operand0)) == REG
1122 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1124 SUBREG_REG (operand0) = reg_equiv_mem[REGNO (SUBREG_REG (operand0))];
1125 operand0 = alter_subreg (operand0);
1129 && reload_in_progress && GET_CODE (operand1) == REG
1130 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1131 operand1 = reg_equiv_mem[REGNO (operand1)];
1132 else if (scratch_reg
1133 && reload_in_progress && GET_CODE (operand1) == SUBREG
1134 && GET_CODE (SUBREG_REG (operand1)) == REG
1135 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1137 SUBREG_REG (operand1) = reg_equiv_mem[REGNO (SUBREG_REG (operand1))];
1138 operand1 = alter_subreg (operand1);
1141 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1142 && ((tem = find_replacement (&XEXP (operand0, 0)))
1143 != XEXP (operand0, 0)))
1144 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1145 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1146 && ((tem = find_replacement (&XEXP (operand1, 0)))
1147 != XEXP (operand1, 0)))
1148 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1150 /* Handle secondary reloads for loads/stores of FP registers from
1151 REG+D addresses where D does not fit in 5 bits, including
1152 (subreg (mem (addr))) cases. */
1153 if (fp_reg_operand (operand0, mode)
1154 && ((GET_CODE (operand1) == MEM
1155 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1156 || ((GET_CODE (operand1) == SUBREG
1157 && GET_CODE (XEXP (operand1, 0)) == MEM
1158 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1161 if (GET_CODE (operand1) == SUBREG)
1162 operand1 = XEXP (operand1, 0);
1164 scratch_reg = gen_rtx_REG (word_mode, REGNO (scratch_reg));
1166 /* D might not fit in 14 bits either; for such cases load D into
1168 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1170 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1171 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1173 XEXP (XEXP (operand1, 0), 0),
1177 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1178 emit_insn (gen_rtx_SET (VOIDmode, operand0, gen_rtx_MEM (mode,
1182 else if (fp_reg_operand (operand1, mode)
1183 && ((GET_CODE (operand0) == MEM
1184 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1185 || ((GET_CODE (operand0) == SUBREG)
1186 && GET_CODE (XEXP (operand0, 0)) == MEM
1187 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1190 if (GET_CODE (operand0) == SUBREG)
1191 operand0 = XEXP (operand0, 0);
1193 scratch_reg = gen_rtx_REG (word_mode, REGNO (scratch_reg));
1194 /* D might not fit in 14 bits either; for such cases load D into
1196 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1198 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1199 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1202 XEXP (XEXP (operand0, 0),
1207 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1208 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1212 /* Handle secondary reloads for loads of FP registers from constant
1213 expressions by forcing the constant into memory.
1215 use scratch_reg to hold the address of the memory location.
1217 ??? The proper fix is to change PREFERRED_RELOAD_CLASS to return
1218 NO_REGS when presented with a const_int and an register class
1219 containing only FP registers. Doing so unfortunately creates
1220 more problems than it solves. Fix this for 2.5. */
1221 else if (fp_reg_operand (operand0, mode)
1222 && CONSTANT_P (operand1)
1227 /* Force the constant into memory and put the address of the
1228 memory location into scratch_reg. */
1229 xoperands[0] = scratch_reg;
1230 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1231 emit_move_sequence (xoperands, Pmode, 0);
1233 /* Now load the destination register. */
1234 emit_insn (gen_rtx_SET (mode, operand0, gen_rtx_MEM (mode, scratch_reg)));
1237 /* Handle secondary reloads for SAR. These occur when trying to load
1238 the SAR from memory a FP register, or with a constant. */
1239 else if (GET_CODE (operand0) == REG
1240 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1241 && (GET_CODE (operand1) == MEM
1242 || GET_CODE (operand1) == CONST_INT
1243 || (GET_CODE (operand1) == REG
1244 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1247 /* D might not fit in 14 bits either; for such cases load D into
1249 if (GET_CODE (operand1) == MEM
1250 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1252 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1253 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1256 XEXP (XEXP (operand1, 0),
1259 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand1),
1263 emit_move_insn (scratch_reg, operand1);
1264 emit_move_insn (operand0, scratch_reg);
1267 /* Handle most common case: storing into a register. */
1268 else if (register_operand (operand0, mode))
1270 if (register_operand (operand1, mode)
1271 || (GET_CODE (operand1) == CONST_INT && INT_14_BITS (operand1))
1272 || (operand1 == CONST0_RTX (mode))
1273 || (GET_CODE (operand1) == HIGH
1274 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1275 /* Only `general_operands' can come here, so MEM is ok. */
1276 || GET_CODE (operand1) == MEM)
1278 /* Run this case quickly. */
1279 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1283 else if (GET_CODE (operand0) == MEM)
1285 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1286 && !(reload_in_progress || reload_completed))
1288 rtx temp = gen_reg_rtx (DFmode);
1290 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1291 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1294 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1296 /* Run this case quickly. */
1297 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1300 if (! (reload_in_progress || reload_completed))
1302 operands[0] = validize_mem (operand0);
1303 operands[1] = operand1 = force_reg (mode, operand1);
1307 /* Simplify the source if we need to.
1308 Note we do have to handle function labels here, even though we do
1309 not consider them legitimate constants. Loop optimizations can
1310 call the emit_move_xxx with one as a source. */
1311 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1312 || function_label_operand (operand1, mode)
1313 || (GET_CODE (operand1) == HIGH
1314 && symbolic_operand (XEXP (operand1, 0), mode)))
1318 if (GET_CODE (operand1) == HIGH)
1321 operand1 = XEXP (operand1, 0);
1323 if (symbolic_operand (operand1, mode))
1325 /* Argh. The assembler and linker can't handle arithmetic
1328 So we force the plabel into memory, load operand0 from
1329 the memory location, then add in the constant part. */
1330 if ((GET_CODE (operand1) == CONST
1331 && GET_CODE (XEXP (operand1, 0)) == PLUS
1332 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1333 || function_label_operand (operand1, mode))
1335 rtx temp, const_part;
1337 /* Figure out what (if any) scratch register to use. */
1338 if (reload_in_progress || reload_completed)
1339 scratch_reg = scratch_reg ? scratch_reg : operand0;
1341 scratch_reg = gen_reg_rtx (Pmode);
1343 if (GET_CODE (operand1) == CONST)
1345 /* Save away the constant part of the expression. */
1346 const_part = XEXP (XEXP (operand1, 0), 1);
1347 if (GET_CODE (const_part) != CONST_INT)
1350 /* Force the function label into memory. */
1351 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1355 /* No constant part. */
1356 const_part = NULL_RTX;
1358 /* Force the function label into memory. */
1359 temp = force_const_mem (mode, operand1);
1363 /* Get the address of the memory location. PIC-ify it if
1365 temp = XEXP (temp, 0);
1367 temp = legitimize_pic_address (temp, mode, scratch_reg);
1369 /* Put the address of the memory location into our destination
1372 emit_move_sequence (operands, mode, scratch_reg);
1374 /* Now load from the memory location into our destination
1376 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1377 emit_move_sequence (operands, mode, scratch_reg);
1379 /* And add back in the constant part. */
1380 if (const_part != NULL_RTX)
1381 expand_inc (operand0, const_part);
1390 if (reload_in_progress || reload_completed)
1391 temp = scratch_reg ? scratch_reg : operand0;
1393 temp = gen_reg_rtx (Pmode);
1395 /* (const (plus (symbol) (const_int))) must be forced to
1396 memory during/after reload if the const_int will not fit
1398 if (GET_CODE (operand1) == CONST
1399 && GET_CODE (XEXP (operand1, 0)) == PLUS
1400 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1401 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1402 && (reload_completed || reload_in_progress)
1405 operands[1] = force_const_mem (mode, operand1);
1406 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1408 emit_move_sequence (operands, mode, temp);
1412 operands[1] = legitimize_pic_address (operand1, mode, temp);
1413 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1416 /* On the HPPA, references to data space are supposed to use dp,
1417 register 27, but showing it in the RTL inhibits various cse
1418 and loop optimizations. */
1423 if (reload_in_progress || reload_completed)
1424 temp = scratch_reg ? scratch_reg : operand0;
1426 temp = gen_reg_rtx (mode);
1428 /* Loading a SYMBOL_REF into a register makes that register
1429 safe to be used as the base in an indexed address.
1431 Don't mark hard registers though. That loses. */
1432 if (GET_CODE (operand0) == REG
1433 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1434 REGNO_POINTER_FLAG (REGNO (operand0)) = 1;
1435 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1436 REGNO_POINTER_FLAG (REGNO (temp)) = 1;
1438 set = gen_rtx_SET (mode, operand0, temp);
1440 set = gen_rtx_SET (VOIDmode, operand0,
1441 gen_rtx_LO_SUM (mode, temp, operand1));
1443 emit_insn (gen_rtx_SET (VOIDmode,
1445 gen_rtx_HIGH (mode, operand1)));
1451 else if (GET_CODE (operand1) != CONST_INT
1452 || ! cint_ok_for_move (INTVAL (operand1)))
1456 if (reload_in_progress || reload_completed)
1459 temp = gen_reg_rtx (mode);
1461 emit_insn (gen_rtx_SET (VOIDmode, temp,
1462 gen_rtx_HIGH (mode, operand1)));
1463 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1466 /* Now have insn-emit do whatever it normally does. */
1470 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1471 it will need a link/runtime reloc). */
1479 switch (TREE_CODE (exp))
1486 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1487 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1492 case NON_LVALUE_EXPR:
1493 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1499 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1500 if (TREE_VALUE (link) != 0)
1501 reloc |= reloc_needed (TREE_VALUE (link));
1514 /* Does operand (which is a symbolic_operand) live in text space? If
1515 so SYMBOL_REF_FLAG, which is set by ENCODE_SECTION_INFO, will be true. */
1518 read_only_operand (operand)
1521 if (GET_CODE (operand) == CONST)
1522 operand = XEXP (XEXP (operand, 0), 0);
1525 if (GET_CODE (operand) == SYMBOL_REF)
1526 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1530 if (GET_CODE (operand) == SYMBOL_REF)
1531 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1537 /* Return the best assembler insn template
1538 for moving operands[1] into operands[0] as a fullword. */
1540 singlemove_string (operands)
1543 HOST_WIDE_INT intval;
1545 if (GET_CODE (operands[0]) == MEM)
1546 return "stw %r1,%0";
1547 if (GET_CODE (operands[1]) == MEM)
1549 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1554 if (GET_MODE (operands[1]) != SFmode)
1557 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1559 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1560 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1562 operands[1] = GEN_INT (i);
1563 /* Fall through to CONST_INT case. */
1565 if (GET_CODE (operands[1]) == CONST_INT)
1567 intval = INTVAL (operands[1]);
1569 if (VAL_14_BITS_P (intval))
1571 else if ((intval & 0x7ff) == 0)
1572 return "ldil L'%1,%0";
1573 else if (zdepi_cint_p (intval))
1574 return "zdepi %Z1,%0";
1576 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1578 return "copy %1,%0";
1582 /* Compute position (in OP[1]) and width (in OP[2])
1583 useful for copying IMM to a register using the zdepi
1584 instructions. Store the immediate value to insert in OP[0]. */
1586 compute_zdepi_operands (imm, op)
1587 unsigned HOST_WIDE_INT imm;
1592 /* Find the least significant set bit in IMM. */
1593 for (lsb = 0; lsb < 32; lsb++)
1600 /* Choose variants based on *sign* of the 5-bit field. */
1601 if ((imm & 0x10) == 0)
1602 len = (lsb <= 28) ? 4 : 32 - lsb;
1605 /* Find the width of the bitstring in IMM. */
1606 for (len = 5; len < 32; len++)
1608 if ((imm & (1 << len)) == 0)
1612 /* Sign extend IMM as a 5-bit value. */
1613 imm = (imm & 0xf) - 0x10;
1621 /* Output assembler code to perform a doubleword move insn
1622 with operands OPERANDS. */
1625 output_move_double (operands)
1628 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
1630 rtx addreg0 = 0, addreg1 = 0;
1632 /* First classify both operands. */
1634 if (REG_P (operands[0]))
1636 else if (offsettable_memref_p (operands[0]))
1638 else if (GET_CODE (operands[0]) == MEM)
1643 if (REG_P (operands[1]))
1645 else if (CONSTANT_P (operands[1]))
1647 else if (offsettable_memref_p (operands[1]))
1649 else if (GET_CODE (operands[1]) == MEM)
1654 /* Check for the cases that the operand constraints are not
1655 supposed to allow to happen. Abort if we get one,
1656 because generating code for these cases is painful. */
1658 if (optype0 != REGOP && optype1 != REGOP)
1661 /* Handle auto decrementing and incrementing loads and stores
1662 specifically, since the structure of the function doesn't work
1663 for them without major modification. Do it better when we learn
1664 this port about the general inc/dec addressing of PA.
1665 (This was written by tege. Chide him if it doesn't work.) */
1667 if (optype0 == MEMOP)
1669 /* We have to output the address syntax ourselves, since print_operand
1670 doesn't deal with the addresses we want to use. Fix this later. */
1672 rtx addr = XEXP (operands[0], 0);
1673 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1675 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1677 operands[0] = XEXP (addr, 0);
1678 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1681 if (!reg_overlap_mentioned_p (high_reg, addr))
1683 /* No overlap between high target register and address
1684 register. (We do this in a non-obvious way to
1685 save a register file writeback) */
1686 if (GET_CODE (addr) == POST_INC)
1687 return "stws,ma %1,8(%0)\n\tstw %R1,-4(%0)";
1688 return "stws,ma %1,-8(%0)\n\tstw %R1,12(%0)";
1693 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1695 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
1697 operands[0] = XEXP (addr, 0);
1698 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
1701 if (!reg_overlap_mentioned_p (high_reg, addr))
1703 /* No overlap between high target register and address
1704 register. (We do this in a non-obvious way to
1705 save a register file writeback) */
1706 if (GET_CODE (addr) == PRE_INC)
1707 return "stws,mb %1,8(%0)\n\tstw %R1,4(%0)";
1708 return "stws,mb %1,-8(%0)\n\tstw %R1,4(%0)";
1714 if (optype1 == MEMOP)
1716 /* We have to output the address syntax ourselves, since print_operand
1717 doesn't deal with the addresses we want to use. Fix this later. */
1719 rtx addr = XEXP (operands[1], 0);
1720 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
1722 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1724 operands[1] = XEXP (addr, 0);
1725 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1728 if (!reg_overlap_mentioned_p (high_reg, addr))
1730 /* No overlap between high target register and address
1731 register. (We do this in a non-obvious way to
1732 save a register file writeback) */
1733 if (GET_CODE (addr) == POST_INC)
1734 return "ldws,ma 8(%1),%0\n\tldw -4(%1),%R0";
1735 return "ldws,ma -8(%1),%0\n\tldw 12(%1),%R0";
1739 /* This is an undefined situation. We should load into the
1740 address register *and* update that register. Probably
1741 we don't need to handle this at all. */
1742 if (GET_CODE (addr) == POST_INC)
1743 return "ldw 4(%1),%R0\n\tldws,ma 8(%1),%0";
1744 return "ldw 4(%1),%R0\n\tldws,ma -8(%1),%0";
1747 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
1749 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1751 operands[1] = XEXP (addr, 0);
1752 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
1755 if (!reg_overlap_mentioned_p (high_reg, addr))
1757 /* No overlap between high target register and address
1758 register. (We do this in a non-obvious way to
1759 save a register file writeback) */
1760 if (GET_CODE (addr) == PRE_INC)
1761 return "ldws,mb 8(%1),%0\n\tldw 4(%1),%R0";
1762 return "ldws,mb -8(%1),%0\n\tldw 4(%1),%R0";
1766 /* This is an undefined situation. We should load into the
1767 address register *and* update that register. Probably
1768 we don't need to handle this at all. */
1769 if (GET_CODE (addr) == PRE_INC)
1770 return "ldw 12(%1),%R0\n\tldws,mb 8(%1),%0";
1771 return "ldw -4(%1),%R0\n\tldws,mb -8(%1),%0";
1774 else if (GET_CODE (addr) == PLUS
1775 && GET_CODE (XEXP (addr, 0)) == MULT)
1777 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
1779 if (!reg_overlap_mentioned_p (high_reg, addr))
1783 xoperands[0] = high_reg;
1784 xoperands[1] = XEXP (addr, 1);
1785 xoperands[2] = XEXP (XEXP (addr, 0), 0);
1786 xoperands[3] = XEXP (XEXP (addr, 0), 1);
1787 output_asm_insn ("sh%O3addl %2,%1,%0", xoperands);
1788 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
1794 xoperands[0] = high_reg;
1795 xoperands[1] = XEXP (addr, 1);
1796 xoperands[2] = XEXP (XEXP (addr, 0), 0);
1797 xoperands[3] = XEXP (XEXP (addr, 0), 1);
1798 output_asm_insn ("sh%O3addl %2,%1,%R0", xoperands);
1799 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
1805 /* If an operand is an unoffsettable memory ref, find a register
1806 we can increment temporarily to make it refer to the second word. */
1808 if (optype0 == MEMOP)
1809 addreg0 = find_addr_reg (XEXP (operands[0], 0));
1811 if (optype1 == MEMOP)
1812 addreg1 = find_addr_reg (XEXP (operands[1], 0));
1814 /* Ok, we can do one word at a time.
1815 Normally we do the low-numbered word first.
1817 In either case, set up in LATEHALF the operands to use
1818 for the high-numbered word and in some cases alter the
1819 operands in OPERANDS to be suitable for the low-numbered word. */
1821 if (optype0 == REGOP)
1822 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1823 else if (optype0 == OFFSOP)
1824 latehalf[0] = adj_offsettable_operand (operands[0], 4);
1826 latehalf[0] = operands[0];
1828 if (optype1 == REGOP)
1829 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1830 else if (optype1 == OFFSOP)
1831 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1832 else if (optype1 == CNSTOP)
1833 split_double (operands[1], &operands[1], &latehalf[1]);
1835 latehalf[1] = operands[1];
1837 /* If the first move would clobber the source of the second one,
1838 do them in the other order.
1840 This can happen in two cases:
1842 mem -> register where the first half of the destination register
1843 is the same register used in the memory's address. Reload
1844 can create such insns.
1846 mem in this case will be either register indirect or register
1847 indirect plus a valid offset.
1849 register -> register move where REGNO(dst) == REGNO(src + 1)
1850 someone (Tim/Tege?) claimed this can happen for parameter loads.
1852 Handle mem -> register case first. */
1853 if (optype0 == REGOP
1854 && (optype1 == MEMOP || optype1 == OFFSOP)
1855 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
1858 /* Do the late half first. */
1860 output_asm_insn ("ldo 4(%0),%0", &addreg1);
1861 output_asm_insn (singlemove_string (latehalf), latehalf);
1865 output_asm_insn ("ldo -4(%0),%0", &addreg1);
1866 return singlemove_string (operands);
1869 /* Now handle register -> register case. */
1870 if (optype0 == REGOP && optype1 == REGOP
1871 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
1873 output_asm_insn (singlemove_string (latehalf), latehalf);
1874 return singlemove_string (operands);
1877 /* Normal case: do the two words, low-numbered first. */
1879 output_asm_insn (singlemove_string (operands), operands);
1881 /* Make any unoffsettable addresses point at high-numbered word. */
1883 output_asm_insn ("ldo 4(%0),%0", &addreg0);
1885 output_asm_insn ("ldo 4(%0),%0", &addreg1);
1888 output_asm_insn (singlemove_string (latehalf), latehalf);
1890 /* Undo the adds we just did. */
1892 output_asm_insn ("ldo -4(%0),%0", &addreg0);
1894 output_asm_insn ("ldo -4(%0),%0", &addreg1);
1900 output_fp_move_double (operands)
1903 if (FP_REG_P (operands[0]))
1905 if (FP_REG_P (operands[1])
1906 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
1907 output_asm_insn ("fcpy,dbl %f1,%0", operands);
1909 output_asm_insn ("fldd%F1 %1,%0", operands);
1911 else if (FP_REG_P (operands[1]))
1913 output_asm_insn ("fstd%F0 %1,%0", operands);
1915 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
1917 if (GET_CODE (operands[0]) == REG)
1920 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1921 xoperands[0] = operands[0];
1922 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
1924 /* This is a pain. You have to be prepared to deal with an
1925 arbitrary address here including pre/post increment/decrement.
1927 so avoid this in the MD. */
1935 /* Return a REG that occurs in ADDR with coefficient 1.
1936 ADDR can be effectively incremented by incrementing REG. */
1939 find_addr_reg (addr)
1942 while (GET_CODE (addr) == PLUS)
1944 if (GET_CODE (XEXP (addr, 0)) == REG)
1945 addr = XEXP (addr, 0);
1946 else if (GET_CODE (XEXP (addr, 1)) == REG)
1947 addr = XEXP (addr, 1);
1948 else if (CONSTANT_P (XEXP (addr, 0)))
1949 addr = XEXP (addr, 1);
1950 else if (CONSTANT_P (XEXP (addr, 1)))
1951 addr = XEXP (addr, 0);
1955 if (GET_CODE (addr) == REG)
1960 /* Emit code to perform a block move.
1962 OPERANDS[0] is the destination pointer as a REG, clobbered.
1963 OPERANDS[1] is the source pointer as a REG, clobbered.
1964 OPERANDS[2] is a register for temporary storage.
1965 OPERANDS[4] is the size as a CONST_INT
1966 OPERANDS[3] is a register for temporary storage.
1967 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
1968 OPERANDS[6] is another temporary register. */
1971 output_block_move (operands, size_is_constant)
1973 int size_is_constant ATTRIBUTE_UNUSED;
1975 int align = INTVAL (operands[5]);
1976 unsigned long n_bytes = INTVAL (operands[4]);
1978 /* We can't move more than four bytes at a time because the PA
1979 has no longer integer move insns. (Could use fp mem ops?) */
1983 /* Note that we know each loop below will execute at least twice
1984 (else we would have open-coded the copy). */
1988 /* Pre-adjust the loop counter. */
1989 operands[4] = GEN_INT (n_bytes - 8);
1990 output_asm_insn ("ldi %4,%2", operands);
1993 output_asm_insn ("ldws,ma 4(%1),%3", operands);
1994 output_asm_insn ("ldws,ma 4(%1),%6", operands);
1995 output_asm_insn ("stws,ma %3,4(%0)", operands);
1996 output_asm_insn ("addib,>= -8,%2,.-12", operands);
1997 output_asm_insn ("stws,ma %6,4(%0)", operands);
1999 /* Handle the residual. There could be up to 7 bytes of
2000 residual to copy! */
2001 if (n_bytes % 8 != 0)
2003 operands[4] = GEN_INT (n_bytes % 4);
2004 if (n_bytes % 8 >= 4)
2005 output_asm_insn ("ldws,ma 4(%1),%3", operands);
2006 if (n_bytes % 4 != 0)
2007 output_asm_insn ("ldw 0(%1),%6", operands);
2008 if (n_bytes % 8 >= 4)
2009 output_asm_insn ("stws,ma %3,4(%0)", operands);
2010 if (n_bytes % 4 != 0)
2011 output_asm_insn ("stbys,e %6,%4(%0)", operands);
2016 /* Pre-adjust the loop counter. */
2017 operands[4] = GEN_INT (n_bytes - 4);
2018 output_asm_insn ("ldi %4,%2", operands);
2021 output_asm_insn ("ldhs,ma 2(%1),%3", operands);
2022 output_asm_insn ("ldhs,ma 2(%1),%6", operands);
2023 output_asm_insn ("sths,ma %3,2(%0)", operands);
2024 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2025 output_asm_insn ("sths,ma %6,2(%0)", operands);
2027 /* Handle the residual. */
2028 if (n_bytes % 4 != 0)
2030 if (n_bytes % 4 >= 2)
2031 output_asm_insn ("ldhs,ma 2(%1),%3", operands);
2032 if (n_bytes % 2 != 0)
2033 output_asm_insn ("ldb 0(%1),%6", operands);
2034 if (n_bytes % 4 >= 2)
2035 output_asm_insn ("sths,ma %3,2(%0)", operands);
2036 if (n_bytes % 2 != 0)
2037 output_asm_insn ("stb %6,0(%0)", operands);
2042 /* Pre-adjust the loop counter. */
2043 operands[4] = GEN_INT (n_bytes - 2);
2044 output_asm_insn ("ldi %4,%2", operands);
2047 output_asm_insn ("ldbs,ma 1(%1),%3", operands);
2048 output_asm_insn ("ldbs,ma 1(%1),%6", operands);
2049 output_asm_insn ("stbs,ma %3,1(%0)", operands);
2050 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2051 output_asm_insn ("stbs,ma %6,1(%0)", operands);
2053 /* Handle the residual. */
2054 if (n_bytes % 2 != 0)
2056 output_asm_insn ("ldb 0(%1),%3", operands);
2057 output_asm_insn ("stb %3,0(%0)", operands);
2066 /* Count the number of insns necessary to handle this block move.
2068 Basic structure is the same as emit_block_move, except that we
2069 count insns rather than emit them. */
2072 compute_movstrsi_length (insn)
2075 rtx pat = PATTERN (insn);
2076 int align = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2077 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 5), 0));
2078 unsigned int n_insns = 0;
2080 /* We can't move more than four bytes at a time because the PA
2081 has no longer integer move insns. (Could use fp mem ops?) */
2085 /* The basic copying loop. */
2089 if (n_bytes % (2 * align) != 0)
2091 if ((n_bytes % (2 * align)) >= align)
2094 if ((n_bytes % align) != 0)
2098 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2104 output_and (operands)
2107 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2109 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2110 int ls0, ls1, ms0, p, len;
2112 for (ls0 = 0; ls0 < 32; ls0++)
2113 if ((mask & (1 << ls0)) == 0)
2116 for (ls1 = ls0; ls1 < 32; ls1++)
2117 if ((mask & (1 << ls1)) != 0)
2120 for (ms0 = ls1; ms0 < 32; ms0++)
2121 if ((mask & (1 << ms0)) == 0)
2134 operands[2] = GEN_INT (len);
2135 return "extru %1,31,%2,%0";
2139 /* We could use this `depi' for the case above as well, but `depi'
2140 requires one more register file access than an `extru'. */
2145 operands[2] = GEN_INT (p);
2146 operands[3] = GEN_INT (len);
2147 return "depi 0,%2,%3,%0";
2151 return "and %1,%2,%0";
2155 output_ior (operands)
2158 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2159 int bs0, bs1, p, len;
2161 if (INTVAL (operands[2]) == 0)
2162 return "copy %1,%0";
2164 for (bs0 = 0; bs0 < 32; bs0++)
2165 if ((mask & (1 << bs0)) != 0)
2168 for (bs1 = bs0; bs1 < 32; bs1++)
2169 if ((mask & (1 << bs1)) == 0)
2172 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2178 operands[2] = GEN_INT (p);
2179 operands[3] = GEN_INT (len);
2180 return "depi -1,%2,%3,%0";
2183 /* Output an ascii string. */
2185 output_ascii (file, p, size)
2192 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2194 /* The HP assembler can only take strings of 256 characters at one
2195 time. This is a limitation on input line length, *not* the
2196 length of the string. Sigh. Even worse, it seems that the
2197 restriction is in number of input characters (see \xnn &
2198 \whatever). So we have to do this very carefully. */
2200 fputs ("\t.STRING \"", file);
2203 for (i = 0; i < size; i += 4)
2207 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2209 register unsigned int c = p[i + io];
2211 if (c == '\"' || c == '\\')
2212 partial_output[co++] = '\\';
2213 if (c >= ' ' && c < 0177)
2214 partial_output[co++] = c;
2218 partial_output[co++] = '\\';
2219 partial_output[co++] = 'x';
2220 hexd = c / 16 - 0 + '0';
2222 hexd -= '9' - 'a' + 1;
2223 partial_output[co++] = hexd;
2224 hexd = c % 16 - 0 + '0';
2226 hexd -= '9' - 'a' + 1;
2227 partial_output[co++] = hexd;
2230 if (chars_output + co > 243)
2232 fputs ("\"\n\t.STRING \"", file);
2235 fwrite (partial_output, 1, co, file);
2239 fputs ("\"\n", file);
2242 /* Try to rewrite floating point comparisons & branches to avoid
2243 useless add,tr insns.
2245 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2246 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2247 first attempt to remove useless add,tr insns. It is zero
2248 for the second pass as reorg sometimes leaves bogus REG_DEAD
2251 When CHECK_NOTES is zero we can only eliminate add,tr insns
2252 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2255 remove_useless_addtr_insns (insns, check_notes)
2260 static int pass = 0;
2262 /* This is fairly cheap, so always run it when optimizing. */
2266 int fbranch_count = 0;
2268 /* Walk all the insns in this function looking for fcmp & fbranch
2269 instructions. Keep track of how many of each we find. */
2270 insns = get_insns ();
2271 for (insn = insns; insn; insn = next_insn (insn))
2275 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2276 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2279 tmp = PATTERN (insn);
2281 /* It must be a set. */
2282 if (GET_CODE (tmp) != SET)
2285 /* If the destination is CCFP, then we've found an fcmp insn. */
2286 tmp = SET_DEST (tmp);
2287 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2293 tmp = PATTERN (insn);
2294 /* If this is an fbranch instruction, bump the fbranch counter. */
2295 if (GET_CODE (tmp) == SET
2296 && SET_DEST (tmp) == pc_rtx
2297 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2298 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2299 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2300 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2308 /* Find all floating point compare + branch insns. If possible,
2309 reverse the comparison & the branch to avoid add,tr insns. */
2310 for (insn = insns; insn; insn = next_insn (insn))
2314 /* Ignore anything that isn't an INSN. */
2315 if (GET_CODE (insn) != INSN)
2318 tmp = PATTERN (insn);
2320 /* It must be a set. */
2321 if (GET_CODE (tmp) != SET)
2324 /* The destination must be CCFP, which is register zero. */
2325 tmp = SET_DEST (tmp);
2326 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2329 /* INSN should be a set of CCFP.
2331 See if the result of this insn is used in a reversed FP
2332 conditional branch. If so, reverse our condition and
2333 the branch. Doing so avoids useless add,tr insns. */
2334 next = next_insn (insn);
2337 /* Jumps, calls and labels stop our search. */
2338 if (GET_CODE (next) == JUMP_INSN
2339 || GET_CODE (next) == CALL_INSN
2340 || GET_CODE (next) == CODE_LABEL)
2343 /* As does another fcmp insn. */
2344 if (GET_CODE (next) == INSN
2345 && GET_CODE (PATTERN (next)) == SET
2346 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2347 && REGNO (SET_DEST (PATTERN (next))) == 0)
2350 next = next_insn (next);
2353 /* Is NEXT_INSN a branch? */
2355 && GET_CODE (next) == JUMP_INSN)
2357 rtx pattern = PATTERN (next);
2359 /* If it a reversed fp conditional branch (eg uses add,tr)
2360 and CCFP dies, then reverse our conditional and the branch
2361 to avoid the add,tr. */
2362 if (GET_CODE (pattern) == SET
2363 && SET_DEST (pattern) == pc_rtx
2364 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2365 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2366 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2367 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2368 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2369 && (fcmp_count == fbranch_count
2371 && find_regno_note (next, REG_DEAD, 0))))
2373 /* Reverse the branch. */
2374 tmp = XEXP (SET_SRC (pattern), 1);
2375 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2376 XEXP (SET_SRC (pattern), 2) = tmp;
2377 INSN_CODE (next) = -1;
2379 /* Reverse our condition. */
2380 tmp = PATTERN (insn);
2381 PUT_CODE (XEXP (tmp, 1),
2382 reverse_condition (GET_CODE (XEXP (tmp, 1))));
2392 /* You may have trouble believing this, but this is the HP-PA stack
2397 Variable arguments (optional; any number may be allocated)
2399 SP-(4*(N+9)) arg word N
2404 Fixed arguments (must be allocated; may remain unused)
2413 SP-32 External Data Pointer (DP)
2415 SP-24 External/stub RP (RP')
2419 SP-8 Calling Stub RP (RP'')
2424 SP-0 Stack Pointer (points to next available address)
2428 /* This function saves registers as follows. Registers marked with ' are
2429 this function's registers (as opposed to the previous function's).
2430 If a frame_pointer isn't needed, r4 is saved as a general register;
2431 the space for the frame pointer is still allocated, though, to keep
2437 SP (FP') Previous FP
2438 SP + 4 Alignment filler (sigh)
2439 SP + 8 Space for locals reserved here.
2443 SP + n All call saved register used.
2447 SP + o All call saved fp registers used.
2451 SP + p (SP') points to next available address.
2455 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2456 Handle case where DISP > 8k by using the add_high_const patterns.
2458 Note in DISP > 8k case, we will leave the high part of the address
2459 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2461 store_reg (reg, disp, base)
2462 int reg, disp, base;
2464 if (VAL_14_BITS_P (disp))
2466 emit_move_insn (gen_rtx_MEM (word_mode,
2467 gen_rtx_PLUS (Pmode,
2468 gen_rtx_REG (Pmode, base),
2470 gen_rtx_REG (word_mode, reg));
2474 emit_move_insn (gen_rtx_REG (Pmode, 1),
2475 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, base),
2476 gen_rtx_HIGH (Pmode, GEN_INT (disp))));
2477 emit_move_insn (gen_rtx_MEM (word_mode,
2478 gen_rtx_LO_SUM (Pmode,
2479 gen_rtx_REG (Pmode, 1),
2481 gen_rtx_REG (word_mode, reg));
2485 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
2486 Handle case where DISP > 8k by using the add_high_const patterns.
2488 Note in DISP > 8k case, we will leave the high part of the address
2489 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2491 load_reg (reg, disp, base)
2492 int reg, disp, base;
2494 if (VAL_14_BITS_P (disp))
2496 emit_move_insn (gen_rtx_REG (word_mode, reg),
2497 gen_rtx_MEM (word_mode,
2498 gen_rtx_PLUS (Pmode,
2499 gen_rtx_REG (Pmode, base),
2504 emit_move_insn (gen_rtx_REG (Pmode, 1),
2505 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, base),
2506 gen_rtx_HIGH (Pmode, GEN_INT (disp))));
2507 emit_move_insn (gen_rtx_REG (word_mode, reg),
2508 gen_rtx_MEM (word_mode,
2509 gen_rtx_LO_SUM (Pmode,
2510 gen_rtx_REG (Pmode, 1),
2515 /* Emit RTL to set REG to the value specified by BASE+DISP.
2516 Handle case where DISP > 8k by using the add_high_const patterns.
2518 Note in DISP > 8k case, we will leave the high part of the address
2519 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2521 set_reg_plus_d(reg, base, disp)
2522 int reg, base, disp;
2524 if (VAL_14_BITS_P (disp))
2526 emit_move_insn (gen_rtx_REG (Pmode, reg),
2527 gen_rtx_PLUS (Pmode,
2528 gen_rtx_REG (Pmode, base),
2533 emit_move_insn (gen_rtx_REG (Pmode, 1),
2534 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, base),
2535 gen_rtx_HIGH (Pmode, GEN_INT (disp))));
2536 emit_move_insn (gen_rtx_REG (Pmode, reg),
2537 gen_rtx_LO_SUM (Pmode,
2538 gen_rtx_REG (Pmode, 1),
2543 /* Global variables set by FUNCTION_PROLOGUE. */
2544 /* Size of frame. Need to know this to emit return insns from
2546 static int actual_fsize;
2547 static int local_fsize, save_fregs;
2550 compute_frame_size (size, fregs_live)
2554 extern int current_function_outgoing_args_size;
2557 /* 8 is space for frame pointer + filler. If any frame is allocated
2558 we need to add this in because of STARTING_FRAME_OFFSET. */
2559 fsize = size + (size || frame_pointer_needed ? 8 : 0);
2561 for (i = 18; i >= 3; i--)
2562 if (regs_ever_live[i])
2563 fsize += UNITS_PER_WORD;
2565 /* Round the stack. */
2566 fsize = (fsize + 7) & ~7;
2568 for (i = 66; i >= 48; i -= 2)
2569 if (regs_ever_live[i] || regs_ever_live[i + 1])
2577 fsize += current_function_outgoing_args_size;
2578 if (! leaf_function_p () || fsize)
2580 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
2583 rtx hp_profile_label_rtx;
2584 static char hp_profile_label_name[8];
2586 output_function_prologue (file, size)
2588 int size ATTRIBUTE_UNUSED;
2590 /* The function's label and associated .PROC must never be
2591 separated and must be output *after* any profiling declarations
2592 to avoid changing spaces/subspaces within a procedure. */
2594 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
2596 fputs ("\t.PROC\n", file);
2598 /* hppa_expand_prologue does the dirty work now. We just need
2599 to output the assembler directives which denote the start
2601 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
2602 if (regs_ever_live[2] || profile_flag)
2603 fputs (",CALLS,SAVE_RP", file);
2605 fputs (",NO_CALLS", file);
2607 if (frame_pointer_needed)
2608 fputs (",SAVE_SP", file);
2610 /* Pass on information about the number of callee register saves
2611 performed in the prologue.
2613 The compiler is supposed to pass the highest register number
2614 saved, the assembler then has to adjust that number before
2615 entering it into the unwind descriptor (to account for any
2616 caller saved registers with lower register numbers than the
2617 first callee saved register). */
2619 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
2622 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
2624 fputs ("\n\t.ENTRY\n", file);
2626 /* Horrid hack. emit_function_prologue will modify this RTL in
2627 place to get the expected results. */
2629 ASM_GENERATE_INTERNAL_LABEL (hp_profile_label_name, "LP",
2630 hp_profile_labelno);
2632 /* If we're using GAS and not using the portable runtime model, then
2633 we don't need to accumulate the total number of code bytes. */
2634 if (TARGET_GAS && ! TARGET_PORTABLE_RUNTIME)
2635 total_code_bytes = 0;
2636 else if (insn_addresses)
2638 unsigned int old_total = total_code_bytes;
2640 total_code_bytes += insn_addresses[INSN_UID (get_last_insn())];
2641 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
2643 /* Be prepared to handle overflows. */
2644 total_code_bytes = old_total > total_code_bytes ? -1 : total_code_bytes;
2647 total_code_bytes = -1;
2649 remove_useless_addtr_insns (get_insns (), 0);
2651 /* Restore INSN_CODEs for insn which use unscaled indexed addresses. */
2652 restore_unscaled_index_insn_codes (get_insns ());
2656 hppa_expand_prologue()
2658 extern char call_used_regs[];
2659 int size = get_frame_size ();
2660 int merge_sp_adjust_with_store = 0;
2662 rtx tmpreg, size_rtx;
2667 local_fsize = size + (size || frame_pointer_needed ? 8 : 0);
2668 actual_fsize = compute_frame_size (size, &save_fregs);
2670 /* Compute a few things we will use often. */
2671 tmpreg = gen_rtx_REG (word_mode, 1);
2672 size_rtx = GEN_INT (actual_fsize);
2674 /* Save RP first. The calling conventions manual states RP will
2675 always be stored into the caller's frame at sp-20. */
2676 if (regs_ever_live[2] || profile_flag)
2677 store_reg (2, -20, STACK_POINTER_REGNUM);
2679 /* Allocate the local frame and set up the frame pointer if needed. */
2682 if (frame_pointer_needed)
2684 /* Copy the old frame pointer temporarily into %r1. Set up the
2685 new stack pointer, then store away the saved old frame pointer
2686 into the stack at sp+actual_fsize and at the same time update
2687 the stack pointer by actual_fsize bytes. Two versions, first
2688 handles small (<8k) frames. The second handles large (>8k)
2690 emit_move_insn (tmpreg, frame_pointer_rtx);
2691 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
2692 if (VAL_14_BITS_P (actual_fsize))
2693 emit_insn (gen_post_store (stack_pointer_rtx, tmpreg, size_rtx));
2696 /* It is incorrect to store the saved frame pointer at *sp,
2697 then increment sp (writes beyond the current stack boundary).
2699 So instead use stwm to store at *sp and post-increment the
2700 stack pointer as an atomic operation. Then increment sp to
2701 finish allocating the new frame. */
2702 emit_insn (gen_post_store (stack_pointer_rtx, tmpreg,
2704 set_reg_plus_d (STACK_POINTER_REGNUM,
2705 STACK_POINTER_REGNUM,
2709 /* no frame pointer needed. */
2712 /* In some cases we can perform the first callee register save
2713 and allocating the stack frame at the same time. If so, just
2714 make a note of it and defer allocating the frame until saving
2715 the callee registers. */
2716 if (VAL_14_BITS_P (-actual_fsize)
2720 merge_sp_adjust_with_store = 1;
2721 /* Can not optimize. Adjust the stack frame by actual_fsize bytes. */
2722 else if (actual_fsize != 0)
2723 set_reg_plus_d (STACK_POINTER_REGNUM,
2724 STACK_POINTER_REGNUM,
2729 /* The hppa calling conventions say that %r19, the pic offset
2730 register, is saved at sp - 32 (in this function's frame) when
2731 generating PIC code. FIXME: What is the correct thing to do
2732 for functions which make no calls and allocate no frame? Do
2733 we need to allocate a frame, or can we just omit the save? For
2734 now we'll just omit the save. */
2735 if (actual_fsize != 0 && flag_pic)
2736 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
2740 Instead of taking one argument, the counter label, as most normal
2741 mcounts do, _mcount appears to behave differently on the HPPA. It
2742 takes the return address of the caller, the address of this routine,
2743 and the address of the label. Also, it isn't magic, so
2744 argument registers have to be preserved. */
2747 int pc_offset, i, arg_offset, basereg, offsetadj;
2749 pc_offset = 4 + (frame_pointer_needed
2750 ? (VAL_14_BITS_P (actual_fsize) ? 12 : 20)
2751 : (VAL_14_BITS_P (actual_fsize) ? 4 : 8));
2753 /* When the function has a frame pointer, use it as the base
2754 register for saving/restore registers. Else use the stack
2755 pointer. Adjust the offset according to the frame size if
2756 this function does not have a frame pointer. */
2758 basereg = frame_pointer_needed ? FRAME_POINTER_REGNUM
2759 : STACK_POINTER_REGNUM;
2760 offsetadj = frame_pointer_needed ? 0 : actual_fsize;
2762 /* Horrid hack. emit_function_prologue will modify this RTL in
2763 place to get the expected results. sprintf here is just to
2764 put something in the name. */
2765 sprintf(hp_profile_label_name, "LP$%04d", -1);
2766 hp_profile_label_rtx = gen_rtx_SYMBOL_REF (Pmode, hp_profile_label_name);
2767 if (current_function_returns_struct)
2768 store_reg (STRUCT_VALUE_REGNUM, - 12 - offsetadj, basereg);
2769 if (current_function_needs_context)
2770 store_reg (STATIC_CHAIN_REGNUM, - 16 - offsetadj, basereg);
2772 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
2773 if (regs_ever_live [i])
2775 store_reg (i, arg_offset, basereg);
2776 /* Deal with arg_offset not fitting in 14 bits. */
2777 pc_offset += VAL_14_BITS_P (arg_offset) ? 4 : 8;
2780 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
2781 emit_move_insn (tmpreg, gen_rtx_HIGH (Pmode, hp_profile_label_rtx));
2782 emit_move_insn (gen_rtx_REG (Pmode, 24),
2783 gen_rtx_LO_SUM (Pmode, tmpreg, hp_profile_label_rtx));
2784 /* %r25 is set from within the output pattern. */
2785 emit_insn (gen_call_profiler (GEN_INT (- pc_offset - 20)));
2787 /* Restore argument registers. */
2788 for (i = 26, arg_offset = -36 - offsetadj; i >= 23; i--, arg_offset -= 4)
2789 if (regs_ever_live [i])
2790 load_reg (i, arg_offset, basereg);
2792 if (current_function_returns_struct)
2793 load_reg (STRUCT_VALUE_REGNUM, -12 - offsetadj, basereg);
2795 if (current_function_needs_context)
2796 load_reg (STATIC_CHAIN_REGNUM, -16 - offsetadj, basereg);
2799 /* Normal register save.
2801 Do not save the frame pointer in the frame_pointer_needed case. It
2802 was done earlier. */
2803 if (frame_pointer_needed)
2805 for (i = 18, offset = local_fsize; i >= 4; i--)
2806 if (regs_ever_live[i] && ! call_used_regs[i])
2808 store_reg (i, offset, FRAME_POINTER_REGNUM);
2809 offset += UNITS_PER_WORD;
2812 /* Account for %r3 which is saved in a special place. */
2815 /* No frame pointer needed. */
2818 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
2819 if (regs_ever_live[i] && ! call_used_regs[i])
2821 /* If merge_sp_adjust_with_store is nonzero, then we can
2822 optimize the first GR save. */
2823 if (merge_sp_adjust_with_store)
2825 merge_sp_adjust_with_store = 0;
2826 emit_insn (gen_post_store (stack_pointer_rtx,
2827 gen_rtx_REG (word_mode, i),
2828 GEN_INT (-offset)));
2831 store_reg (i, offset, STACK_POINTER_REGNUM);
2832 offset += UNITS_PER_WORD;
2836 /* If we wanted to merge the SP adjustment with a GR save, but we never
2837 did any GR saves, then just emit the adjustment here. */
2838 if (merge_sp_adjust_with_store)
2839 set_reg_plus_d (STACK_POINTER_REGNUM,
2840 STACK_POINTER_REGNUM,
2844 /* Align pointer properly (doubleword boundary). */
2845 offset = (offset + 7) & ~7;
2847 /* Floating point register store. */
2850 /* First get the frame or stack pointer to the start of the FP register
2852 if (frame_pointer_needed)
2853 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
2855 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
2857 /* Now actually save the FP registers. */
2858 for (i = 66; i >= 48; i -= 2)
2860 if (regs_ever_live[i] || regs_ever_live[i + 1])
2862 emit_move_insn (gen_rtx_MEM (DFmode,
2863 gen_rtx_POST_INC (DFmode, tmpreg)),
2864 gen_rtx_REG (DFmode, i));
2870 /* When generating PIC code it is necessary to save/restore the
2871 PIC register around each function call. We used to do this
2872 in the call patterns themselves, but that implementation
2873 made incorrect assumptions about using global variables to hold
2874 per-function rtl code generated in the backend.
2876 So instead, we copy the PIC register into a reserved callee saved
2877 register in the prologue. Then after each call we reload the PIC
2878 register from the callee saved register. We also reload the PIC
2879 register from the callee saved register in the epilogue ensure the
2880 PIC register is valid at function exit.
2882 This may (depending on the exact characteristics of the function)
2883 even be more efficient.
2885 Avoid this if the callee saved register wasn't used (these are
2887 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM_SAVED])
2888 emit_move_insn (gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM_SAVED),
2889 gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM));
2894 output_function_epilogue (file, size)
2896 int size ATTRIBUTE_UNUSED;
2898 rtx insn = get_last_insn ();
2900 /* hppa_expand_epilogue does the dirty work now. We just need
2901 to output the assembler directives which denote the end
2904 To make debuggers happy, emit a nop if the epilogue was completely
2905 eliminated due to a volatile call as the last insn in the
2906 current function. That way the return address (in %r2) will
2907 always point to a valid instruction in the current function. */
2909 /* Get the last real insn. */
2910 if (GET_CODE (insn) == NOTE)
2911 insn = prev_real_insn (insn);
2913 /* If it is a sequence, then look inside. */
2914 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
2915 insn = XVECEXP (PATTERN (insn), 0, 0);
2917 /* If insn is a CALL_INSN, then it must be a call to a volatile
2918 function (otherwise there would be epilogue insns). */
2919 if (insn && GET_CODE (insn) == CALL_INSN)
2920 fputs ("\tnop\n", file);
2922 fputs ("\t.EXIT\n\t.PROCEND\n", file);
2924 /* Free up stuff we don't need anymore. */
2925 if (unscaled_index_insn_codes)
2926 free (unscaled_index_insn_codes);
2927 max_unscaled_index_insn_codes_uid = 0;
2931 hppa_expand_epilogue ()
2935 int merge_sp_adjust_with_load = 0;
2937 /* We will use this often. */
2938 tmpreg = gen_rtx_REG (word_mode, 1);
2940 /* Try to restore RP early to avoid load/use interlocks when
2941 RP gets used in the return (bv) instruction. This appears to still
2942 be necessary even when we schedule the prologue and epilogue. */
2943 if (frame_pointer_needed
2944 && (regs_ever_live [2] || profile_flag))
2945 load_reg (2, -20, FRAME_POINTER_REGNUM);
2947 /* No frame pointer, and stack is smaller than 8k. */
2948 else if (! frame_pointer_needed
2949 && VAL_14_BITS_P (actual_fsize + 20)
2950 && (regs_ever_live[2] || profile_flag))
2951 load_reg (2, - (actual_fsize + 20), STACK_POINTER_REGNUM);
2953 /* General register restores. */
2954 if (frame_pointer_needed)
2956 for (i = 18, offset = local_fsize; i >= 4; i--)
2957 if (regs_ever_live[i] && ! call_used_regs[i])
2959 load_reg (i, offset, FRAME_POINTER_REGNUM);
2960 offset += UNITS_PER_WORD;
2965 for (i = 18, offset = local_fsize - actual_fsize; i >= 3; i--)
2967 if (regs_ever_live[i] && ! call_used_regs[i])
2969 /* Only for the first load.
2970 merge_sp_adjust_with_load holds the register load
2971 with which we will merge the sp adjustment. */
2972 if (VAL_14_BITS_P (actual_fsize + 20)
2974 && ! merge_sp_adjust_with_load)
2975 merge_sp_adjust_with_load = i;
2977 load_reg (i, offset, STACK_POINTER_REGNUM);
2978 offset += UNITS_PER_WORD;
2983 /* Align pointer properly (doubleword boundary). */
2984 offset = (offset + 7) & ~7;
2986 /* FP register restores. */
2989 /* Adjust the register to index off of. */
2990 if (frame_pointer_needed)
2991 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset);
2993 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset);
2995 /* Actually do the restores now. */
2996 for (i = 66; i >= 48; i -= 2)
2998 if (regs_ever_live[i] || regs_ever_live[i + 1])
3000 emit_move_insn (gen_rtx_REG (DFmode, i),
3001 gen_rtx_MEM (DFmode,
3002 gen_rtx_POST_INC (DFmode, tmpreg)));
3007 /* Emit a blockage insn here to keep these insns from being moved to
3008 an earlier spot in the epilogue, or into the main instruction stream.
3010 This is necessary as we must not cut the stack back before all the
3011 restores are finished. */
3012 emit_insn (gen_blockage ());
3013 /* No frame pointer, but we have a stack greater than 8k. We restore
3014 %r2 very late in this case. (All other cases are restored as early
3016 if (! frame_pointer_needed
3017 && ! VAL_14_BITS_P (actual_fsize + 20)
3018 && (regs_ever_live[2] || profile_flag))
3020 set_reg_plus_d (STACK_POINTER_REGNUM,
3021 STACK_POINTER_REGNUM,
3024 /* This used to try and be clever by not depending on the value in
3025 %r30 and instead use the value held in %r1 (so that the 2nd insn
3026 which sets %r30 could be put in the delay slot of the return insn).
3028 That won't work since if the stack is exactly 8k set_reg_plus_d
3029 doesn't set %r1, just %r30. */
3030 load_reg (2, - 20, STACK_POINTER_REGNUM);
3033 /* Reset stack pointer (and possibly frame pointer). The stack
3034 pointer is initially set to fp + 64 to avoid a race condition. */
3035 else if (frame_pointer_needed)
3037 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64);
3038 emit_insn (gen_pre_load (frame_pointer_rtx,
3042 /* If we were deferring a callee register restore, do it now. */
3043 else if (! frame_pointer_needed && merge_sp_adjust_with_load)
3044 emit_insn (gen_pre_load (gen_rtx_REG (word_mode, merge_sp_adjust_with_load),
3046 GEN_INT (- actual_fsize)));
3047 else if (actual_fsize != 0)
3048 set_reg_plus_d (STACK_POINTER_REGNUM,
3049 STACK_POINTER_REGNUM,
3053 /* Fetch the return address for the frame COUNT steps up from
3054 the current frame, after the prologue. FRAMEADDR is the
3055 frame pointer of the COUNT frame.
3057 We want to ignore any export stub remnants here.
3059 The value returned is used in two different ways:
3061 1. To find a function's caller.
3063 2. To change the return address for a function.
3065 This function handles most instances of case 1; however, it will
3066 fail if there are two levels of stubs to execute on the return
3067 path. The only way I believe that can happen is if the return value
3068 needs a parameter relocation, which never happens for C code.
3070 This function handles most instances of case 2; however, it will
3071 fail if we did not originally have stub code on the return path
3072 but will need code on the new return path. This can happen if
3073 the caller & callee are both in the main program, but the new
3074 return location is in a shared library.
3076 To handle this correctly we need to set the return pointer at
3077 frame-20 to point to a return stub frame-24 to point to the
3078 location we wish to return to. */
3081 return_addr_rtx (count, frameaddr)
3082 int count ATTRIBUTE_UNUSED;
3089 saved_rp = gen_reg_rtx (Pmode);
3091 /* First, we start off with the normal return address pointer from
3094 emit_move_insn (saved_rp, plus_constant (frameaddr, -5 * UNITS_PER_WORD));
3096 /* Get pointer to the instruction stream. We have to mask out the
3097 privilege level from the two low order bits of the return address
3098 pointer here so that ins will point to the start of the first
3099 instruction that would have been executed if we returned. */
3100 ins = copy_to_reg (gen_rtx_AND (Pmode,
3101 copy_to_reg (gen_rtx_MEM (Pmode, saved_rp)),
3103 label = gen_label_rtx ();
3105 /* Check the instruction stream at the normal return address for the
3108 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3109 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3110 0x00011820 | stub+16: mtsp r1,sr0
3111 0xe0400002 | stub+20: be,n 0(sr0,rp)
3113 If it is an export stub, than our return address is really in
3116 emit_cmp_insn (gen_rtx_MEM (SImode, ins),
3117 GEN_INT (0x4bc23fd1),
3118 NE, NULL_RTX, SImode, 1, 0);
3119 emit_jump_insn (gen_bne (label));
3121 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3122 GEN_INT (0x004010a1),
3123 NE, NULL_RTX, SImode, 1, 0);
3124 emit_jump_insn (gen_bne (label));
3126 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3127 GEN_INT (0x00011820),
3128 NE, NULL_RTX, SImode, 1, 0);
3129 emit_jump_insn (gen_bne (label));
3131 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3132 GEN_INT (0xe0400002),
3133 NE, NULL_RTX, SImode, 1, 0);
3135 /* If there is no export stub then just use our initial guess of
3138 emit_jump_insn (gen_bne (label));
3140 /* Here we know that our return address pointer points to an export
3141 stub. We don't want to return the address of the export stub,
3142 but rather the return address that leads back into user code.
3143 That return address is stored at -24[frameaddr]. */
3145 emit_move_insn (saved_rp, plus_constant (frameaddr, -6 * UNITS_PER_WORD));
3148 return gen_rtx_MEM (Pmode, memory_address (Pmode, saved_rp));
3151 /* This is only valid once reload has completed because it depends on
3152 knowing exactly how much (if any) frame there is and...
3154 It's only valid if there is no frame marker to de-allocate and...
3156 It's only valid if %r2 hasn't been saved into the caller's frame
3157 (we're not profiling and %r2 isn't live anywhere). */
3159 hppa_can_use_return_insn_p ()
3161 return (reload_completed
3162 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3164 && ! regs_ever_live[2]
3165 && ! frame_pointer_needed);
3169 emit_bcond_fp (code, operand0)
3173 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3174 gen_rtx_IF_THEN_ELSE (VOIDmode,
3175 gen_rtx_fmt_ee (code,
3177 gen_rtx_REG (CCFPmode, 0),
3179 gen_rtx_LABEL_REF (VOIDmode, operand0),
3185 gen_cmp_fp (code, operand0, operand1)
3187 rtx operand0, operand1;
3189 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3190 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3193 /* Adjust the cost of a scheduling dependency. Return the new cost of
3194 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3197 pa_adjust_cost (insn, link, dep_insn, cost)
3203 enum attr_type attr_type;
3205 /* Don't adjust costs for a pa8000 chip. */
3206 if (pa_cpu >= PROCESSOR_8000)
3209 if (! recog_memoized (insn))
3212 attr_type = get_attr_type (insn);
3214 if (REG_NOTE_KIND (link) == 0)
3216 /* Data dependency; DEP_INSN writes a register that INSN reads some
3219 if (attr_type == TYPE_FPSTORE)
3221 rtx pat = PATTERN (insn);
3222 rtx dep_pat = PATTERN (dep_insn);
3223 if (GET_CODE (pat) == PARALLEL)
3225 /* This happens for the fstXs,mb patterns. */
3226 pat = XVECEXP (pat, 0, 0);
3228 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3229 /* If this happens, we have to extend this to schedule
3230 optimally. Return 0 for now. */
3233 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
3235 if (! recog_memoized (dep_insn))
3237 /* DEP_INSN is writing its result to the register
3238 being stored in the fpstore INSN. */
3239 switch (get_attr_type (dep_insn))
3242 /* This cost 3 cycles, not 2 as the md says for the
3251 case TYPE_FPSQRTSGL:
3252 case TYPE_FPSQRTDBL:
3253 /* In these important cases, we save one cycle compared to
3254 when flop instruction feed each other. */
3263 /* For other data dependencies, the default cost specified in the
3267 else if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3269 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3272 if (attr_type == TYPE_FPLOAD)
3274 rtx pat = PATTERN (insn);
3275 rtx dep_pat = PATTERN (dep_insn);
3276 if (GET_CODE (pat) == PARALLEL)
3278 /* This happens for the fldXs,mb patterns. */
3279 pat = XVECEXP (pat, 0, 0);
3281 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3282 /* If this happens, we have to extend this to schedule
3283 optimally. Return 0 for now. */
3286 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3288 if (! recog_memoized (dep_insn))
3290 switch (get_attr_type (dep_insn))
3297 case TYPE_FPSQRTSGL:
3298 case TYPE_FPSQRTDBL:
3299 /* A fpload can't be issued until one cycle before a
3300 preceding arithmetic operation has finished if
3301 the target of the fpload is any of the sources
3302 (or destination) of the arithmetic operation. */
3310 else if (attr_type == TYPE_FPALU)
3312 rtx pat = PATTERN (insn);
3313 rtx dep_pat = PATTERN (dep_insn);
3314 if (GET_CODE (pat) == PARALLEL)
3316 /* This happens for the fldXs,mb patterns. */
3317 pat = XVECEXP (pat, 0, 0);
3319 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3320 /* If this happens, we have to extend this to schedule
3321 optimally. Return 0 for now. */
3324 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3326 if (! recog_memoized (dep_insn))
3328 switch (get_attr_type (dep_insn))
3332 case TYPE_FPSQRTSGL:
3333 case TYPE_FPSQRTDBL:
3334 /* An ALU flop can't be issued until two cycles before a
3335 preceding divide or sqrt operation has finished if
3336 the target of the ALU flop is any of the sources
3337 (or destination) of the divide or sqrt operation. */
3346 /* For other anti dependencies, the cost is 0. */
3349 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
3351 /* Output dependency; DEP_INSN writes a register that INSN writes some
3353 if (attr_type == TYPE_FPLOAD)
3355 rtx pat = PATTERN (insn);
3356 rtx dep_pat = PATTERN (dep_insn);
3357 if (GET_CODE (pat) == PARALLEL)
3359 /* This happens for the fldXs,mb patterns. */
3360 pat = XVECEXP (pat, 0, 0);
3362 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3363 /* If this happens, we have to extend this to schedule
3364 optimally. Return 0 for now. */
3367 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3369 if (! recog_memoized (dep_insn))
3371 switch (get_attr_type (dep_insn))
3378 case TYPE_FPSQRTSGL:
3379 case TYPE_FPSQRTDBL:
3380 /* A fpload can't be issued until one cycle before a
3381 preceding arithmetic operation has finished if
3382 the target of the fpload is the destination of the
3383 arithmetic operation. */
3391 else if (attr_type == TYPE_FPALU)
3393 rtx pat = PATTERN (insn);
3394 rtx dep_pat = PATTERN (dep_insn);
3395 if (GET_CODE (pat) == PARALLEL)
3397 /* This happens for the fldXs,mb patterns. */
3398 pat = XVECEXP (pat, 0, 0);
3400 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3401 /* If this happens, we have to extend this to schedule
3402 optimally. Return 0 for now. */
3405 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
3407 if (! recog_memoized (dep_insn))
3409 switch (get_attr_type (dep_insn))
3413 case TYPE_FPSQRTSGL:
3414 case TYPE_FPSQRTDBL:
3415 /* An ALU flop can't be issued until two cycles before a
3416 preceding divide or sqrt operation has finished if
3417 the target of the ALU flop is also the target of
3418 the divide or sqrt operation. */
3427 /* For other output dependencies, the cost is 0. */
3434 /* Return any length adjustment needed by INSN which already has its length
3435 computed as LENGTH. Return zero if no adjustment is necessary.
3437 For the PA: function calls, millicode calls, and backwards short
3438 conditional branches with unfilled delay slots need an adjustment by +1
3439 (to account for the NOP which will be inserted into the instruction stream).
3441 Also compute the length of an inline block move here as it is too
3442 complicated to express as a length attribute in pa.md. */
3444 pa_adjust_insn_length (insn, length)
3448 rtx pat = PATTERN (insn);
3450 /* Call insns which are *not* indirect and have unfilled delay slots. */
3451 if (GET_CODE (insn) == CALL_INSN)
3454 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
3455 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
3457 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
3458 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
3464 /* Jumps inside switch tables which have unfilled delay slots
3465 also need adjustment. */
3466 else if (GET_CODE (insn) == JUMP_INSN
3467 && simplejump_p (insn)
3468 && GET_MODE (insn) == SImode)
3470 /* Millicode insn with an unfilled delay slot. */
3471 else if (GET_CODE (insn) == INSN
3472 && GET_CODE (pat) != SEQUENCE
3473 && GET_CODE (pat) != USE
3474 && GET_CODE (pat) != CLOBBER
3475 && get_attr_type (insn) == TYPE_MILLI)
3477 /* Block move pattern. */
3478 else if (GET_CODE (insn) == INSN
3479 && GET_CODE (pat) == PARALLEL
3480 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
3481 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
3482 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
3483 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
3484 return compute_movstrsi_length (insn) - 4;
3485 /* Conditional branch with an unfilled delay slot. */
3486 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
3488 /* Adjust a short backwards conditional with an unfilled delay slot. */
3489 if (GET_CODE (pat) == SET
3491 && ! forward_branch_p (insn))
3493 else if (GET_CODE (pat) == PARALLEL
3494 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
3497 /* Adjust dbra insn with short backwards conditional branch with
3498 unfilled delay slot -- only for case where counter is in a
3499 general register register. */
3500 else if (GET_CODE (pat) == PARALLEL
3501 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
3502 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
3503 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
3505 && ! forward_branch_p (insn))
3513 /* Print operand X (an rtx) in assembler syntax to file FILE.
3514 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3515 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3518 print_operand (file, x, code)
3526 /* Output a 'nop' if there's nothing for the delay slot. */
3527 if (dbr_sequence_length () == 0)
3528 fputs ("\n\tnop", file);
3531 /* Output an nullification completer if there's nothing for the */
3532 /* delay slot or nullification is requested. */
3533 if (dbr_sequence_length () == 0 ||
3535 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
3539 /* Print out the second register name of a register pair.
3540 I.e., R (6) => 7. */
3541 fputs (reg_names[REGNO (x)+1], file);
3544 /* A register or zero. */
3546 || (x == CONST0_RTX (DFmode))
3547 || (x == CONST0_RTX (SFmode)))
3549 fputs ("%r0", file);
3555 /* A register or zero (floating point). */
3557 || (x == CONST0_RTX (DFmode))
3558 || (x == CONST0_RTX (SFmode)))
3560 fputs ("%fr0", file);
3565 case 'C': /* Plain (C)ondition */
3567 switch (GET_CODE (x))
3570 fputs ("=", file); break;
3572 fputs ("<>", file); break;
3574 fputs (">", file); break;
3576 fputs (">=", file); break;
3578 fputs (">>=", file); break;
3580 fputs (">>", file); break;
3582 fputs ("<", file); break;
3584 fputs ("<=", file); break;
3586 fputs ("<<=", file); break;
3588 fputs ("<<", file); break;
3593 case 'N': /* Condition, (N)egated */
3594 switch (GET_CODE (x))
3597 fputs ("<>", file); break;
3599 fputs ("=", file); break;
3601 fputs ("<=", file); break;
3603 fputs ("<", file); break;
3605 fputs ("<<", file); break;
3607 fputs ("<<=", file); break;
3609 fputs (">=", file); break;
3611 fputs (">", file); break;
3613 fputs (">>", file); break;
3615 fputs (">>=", file); break;
3620 /* For floating point comparisons. Need special conditions to deal
3621 with NaNs properly. */
3623 switch (GET_CODE (x))
3626 fputs ("!=", file); break;
3628 fputs ("=", file); break;
3630 fputs ("<=", file); break;
3632 fputs ("<", file); break;
3634 fputs (">=", file); break;
3636 fputs (">", file); break;
3641 case 'S': /* Condition, operands are (S)wapped. */
3642 switch (GET_CODE (x))
3645 fputs ("=", file); break;
3647 fputs ("<>", file); break;
3649 fputs ("<", file); break;
3651 fputs ("<=", file); break;
3653 fputs ("<<=", file); break;
3655 fputs ("<<", file); break;
3657 fputs (">", file); break;
3659 fputs (">=", file); break;
3661 fputs (">>=", file); break;
3663 fputs (">>", file); break;
3668 case 'B': /* Condition, (B)oth swapped and negate. */
3669 switch (GET_CODE (x))
3672 fputs ("<>", file); break;
3674 fputs ("=", file); break;
3676 fputs (">=", file); break;
3678 fputs (">", file); break;
3680 fputs (">>", file); break;
3682 fputs (">>=", file); break;
3684 fputs ("<=", file); break;
3686 fputs ("<", file); break;
3688 fputs ("<<", file); break;
3690 fputs ("<<=", file); break;
3696 if (GET_CODE (x) == CONST_INT)
3698 fprintf (file, "%d", ~INTVAL (x));
3703 if (GET_CODE (x) == CONST_INT)
3705 fprintf (file, "%d", 32 - (INTVAL (x) & 31));
3710 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
3712 fprintf (file, "%d", exact_log2 (INTVAL (x)));
3717 if (GET_CODE (x) == CONST_INT)
3719 fprintf (file, "%d", 31 - (INTVAL (x) & 31));
3724 if (GET_CODE (x) == CONST_INT)
3729 switch (GET_CODE (XEXP (x, 0)))
3733 fputs ("s,mb", file);
3737 fputs ("s,ma", file);
3740 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
3741 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
3742 fputs ("x,s", file);
3743 else if (code == 'F')
3753 output_global_address (file, x, 0);
3756 output_global_address (file, x, 1);
3758 case 0: /* Don't do anything special */
3763 compute_zdepi_operands (INTVAL (x), op);
3764 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
3770 if (GET_CODE (x) == REG)
3772 fputs (reg_names [REGNO (x)], file);
3773 if (FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4 && (REGNO (x) & 1) == 0)
3776 else if (GET_CODE (x) == MEM)
3778 int size = GET_MODE_SIZE (GET_MODE (x));
3779 rtx base = XEXP (XEXP (x, 0), 0);
3780 switch (GET_CODE (XEXP (x, 0)))
3784 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
3788 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
3791 if (GET_CODE (XEXP (x, 0)) == PLUS
3792 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
3793 fprintf (file, "%s(%s)",
3794 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
3795 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
3796 else if (GET_CODE (XEXP (x, 0)) == PLUS
3797 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
3798 fprintf (file, "%s(%s)",
3799 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
3800 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
3802 output_address (XEXP (x, 0));
3807 output_addr_const (file, x);
3810 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
3813 output_global_address (file, x, round_constant)
3819 /* Imagine (high (const (plus ...))). */
3820 if (GET_CODE (x) == HIGH)
3823 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x))
3824 assemble_name (file, XSTR (x, 0));
3825 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
3827 assemble_name (file, XSTR (x, 0));
3828 fputs ("-$global$", file);
3830 else if (GET_CODE (x) == CONST)
3833 int offset = 0; /* assembler wants -$global$ at end */
3834 rtx base = NULL_RTX;
3836 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
3838 base = XEXP (XEXP (x, 0), 0);
3839 output_addr_const (file, base);
3841 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
3842 offset = INTVAL (XEXP (XEXP (x, 0), 0));
3845 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
3847 base = XEXP (XEXP (x, 0), 1);
3848 output_addr_const (file, base);
3850 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
3851 offset = INTVAL (XEXP (XEXP (x, 0),1));
3854 /* How bogus. The compiler is apparently responsible for
3855 rounding the constant if it uses an LR field selector.
3857 The linker and/or assembler seem a better place since
3858 they have to do this kind of thing already.
3860 If we fail to do this, HP's optimizing linker may eliminate
3861 an addil, but not update the ldw/stw/ldo instruction that
3862 uses the result of the addil. */
3864 offset = ((offset + 0x1000) & ~0x1fff);
3866 if (GET_CODE (XEXP (x, 0)) == PLUS)
3876 else if (GET_CODE (XEXP (x, 0)) == MINUS
3877 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
3881 if (!read_only_operand (base) && !flag_pic)
3882 fputs ("-$global$", file);
3884 fprintf (file,"%s%d", sep, offset);
3887 output_addr_const (file, x);
3891 output_deferred_plabels (file)
3895 /* If we have deferred plabels, then we need to switch into the data
3896 section and align it to a 4 byte boundary before we output the
3897 deferred plabels. */
3898 if (n_deferred_plabels)
3901 ASM_OUTPUT_ALIGN (file, 2);
3904 /* Now output the deferred plabels. */
3905 for (i = 0; i < n_deferred_plabels; i++)
3907 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
3908 assemble_integer (gen_rtx_SYMBOL_REF (VOIDmode,
3909 deferred_plabels[i].name), 4, 1);
3913 /* HP's millicode routines mean something special to the assembler.
3914 Keep track of which ones we have used. */
3916 enum millicodes { remI, remU, divI, divU, mulI, mulU, end1000 };
3917 static char imported[(int)end1000];
3918 static char *milli_names[] = {"remI", "remU", "divI", "divU", "mulI", "mulU"};
3919 static char import_string[] = ".IMPORT $$....,MILLICODE";
3920 #define MILLI_START 10
3924 enum millicodes code;
3926 char str[sizeof (import_string)];
3928 if (!imported[(int)code])
3930 imported[(int)code] = 1;
3931 strcpy (str, import_string);
3932 strncpy (str + MILLI_START, milli_names[(int)code], 4);
3933 output_asm_insn (str, 0);
3937 /* The register constraints have put the operands and return value in
3938 the proper registers. */
3941 output_mul_insn (unsignedp, insn)
3942 int unsignedp ATTRIBUTE_UNUSED;
3945 import_milli (mulI);
3946 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
3949 /* Emit the rtl for doing a division by a constant. */
3951 /* Do magic division millicodes exist for this value? */
3952 static int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
3955 /* We'll use an array to keep track of the magic millicodes and
3956 whether or not we've used them already. [n][0] is signed, [n][1] is
3959 static int div_milli[16][2];
3962 div_operand (op, mode)
3964 enum machine_mode mode;
3966 return (mode == SImode
3967 && ((GET_CODE (op) == REG && REGNO (op) == 25)
3968 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
3969 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
3973 emit_hpdiv_const (operands, unsignedp)
3977 if (GET_CODE (operands[2]) == CONST_INT
3978 && INTVAL (operands[2]) > 0
3979 && INTVAL (operands[2]) < 16
3980 && magic_milli[INTVAL (operands[2])])
3982 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
3985 (PARALLEL, VOIDmode,
3986 gen_rtvec (5, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
3987 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
3989 gen_rtx_REG (SImode, 26),
3991 gen_rtx_CLOBBER (VOIDmode, operands[3]),
3992 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
3993 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
3994 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 31)))));
3995 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4002 output_div_insn (operands, unsignedp, insn)
4009 /* If the divisor is a constant, try to use one of the special
4011 if (GET_CODE (operands[0]) == CONST_INT)
4013 static char buf[100];
4014 divisor = INTVAL (operands[0]);
4015 if (!div_milli[divisor][unsignedp])
4017 div_milli[divisor][unsignedp] = 1;
4019 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4021 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4025 sprintf (buf, "$$divU_%d", INTVAL (operands[0]));
4026 return output_millicode_call (insn,
4027 gen_rtx_SYMBOL_REF (SImode, buf));
4031 sprintf (buf, "$$divI_%d", INTVAL (operands[0]));
4032 return output_millicode_call (insn,
4033 gen_rtx_SYMBOL_REF (SImode, buf));
4036 /* Divisor isn't a special constant. */
4041 import_milli (divU);
4042 return output_millicode_call (insn,
4043 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4047 import_milli (divI);
4048 return output_millicode_call (insn,
4049 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4054 /* Output a $$rem millicode to do mod. */
4057 output_mod_insn (unsignedp, insn)
4063 import_milli (remU);
4064 return output_millicode_call (insn,
4065 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4069 import_milli (remI);
4070 return output_millicode_call (insn,
4071 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4076 output_arg_descriptor (call_insn)
4080 enum machine_mode arg_mode;
4082 int i, output_flag = 0;
4085 for (i = 0; i < 4; i++)
4088 /* Specify explicitly that no argument relocations should take place
4089 if using the portable runtime calling conventions. */
4090 if (TARGET_PORTABLE_RUNTIME)
4092 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4097 if (GET_CODE (call_insn) != CALL_INSN)
4099 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4101 rtx use = XEXP (link, 0);
4103 if (! (GET_CODE (use) == USE
4104 && GET_CODE (XEXP (use, 0)) == REG
4105 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4108 arg_mode = GET_MODE (XEXP (use, 0));
4109 regno = REGNO (XEXP (use, 0));
4110 if (regno >= 23 && regno <= 26)
4112 arg_regs[26 - regno] = "GR";
4113 if (arg_mode == DImode)
4114 arg_regs[25 - regno] = "GR";
4116 else if (regno >= 32 && regno <= 39)
4118 if (arg_mode == SFmode)
4119 arg_regs[(regno - 32) / 2] = "FR";
4122 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4123 arg_regs[(regno - 34) / 2] = "FR";
4124 arg_regs[(regno - 34) / 2 + 1] = "FU";
4126 arg_regs[(regno - 34) / 2] = "FU";
4127 arg_regs[(regno - 34) / 2 + 1] = "FR";
4132 fputs ("\t.CALL ", asm_out_file);
4133 for (i = 0; i < 4; i++)
4138 fputc (',', asm_out_file);
4139 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4142 fputc ('\n', asm_out_file);
4145 /* Return the class of any secondary reload register that is needed to
4146 move IN into a register in class CLASS using mode MODE.
4148 Profiling has showed this routine and its descendants account for
4149 a significant amount of compile time (~7%). So it has been
4150 optimized to reduce redundant computations and eliminate useless
4153 It might be worthwhile to try and make this a leaf function too. */
4156 secondary_reload_class (class, mode, in)
4157 enum reg_class class;
4158 enum machine_mode mode;
4161 int regno, is_symbolic;
4163 /* Trying to load a constant into a FP register during PIC code
4164 generation will require %r1 as a scratch register. */
4166 && GET_MODE_CLASS (mode) == MODE_INT
4167 && FP_REG_CLASS_P (class)
4168 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
4171 /* Profiling showed the PA port spends about 1.3% of its compilation
4172 time in true_regnum from calls inside secondary_reload_class. */
4174 if (GET_CODE (in) == REG)
4177 if (regno >= FIRST_PSEUDO_REGISTER)
4178 regno = true_regnum (in);
4180 else if (GET_CODE (in) == SUBREG)
4181 regno = true_regnum (in);
4185 /* If we have something like (mem (mem (...)), we can safely assume the
4186 inner MEM will end up in a general register after reloading, so there's
4187 no need for a secondary reload. */
4188 if (GET_CODE (in) == MEM
4189 && GET_CODE (XEXP (in, 0)) == MEM)
4192 /* Handle out of range displacement for integer mode loads/stores of
4194 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
4195 && GET_MODE_CLASS (mode) == MODE_INT
4196 && FP_REG_CLASS_P (class))
4197 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
4198 return GENERAL_REGS;
4200 if (GET_CODE (in) == HIGH)
4203 /* Profiling has showed GCC spends about 2.6% of its compilation
4204 time in symbolic_operand from calls inside secondary_reload_class.
4206 We use an inline copy and only compute its return value once to avoid
4208 switch (GET_CODE (in))
4218 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
4219 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
4220 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
4230 && read_only_operand (in))
4233 if (class != R1_REGS && is_symbolic)
4240 function_arg_padding (mode, type)
4241 enum machine_mode mode;
4246 if (mode == BLKmode)
4248 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4249 size = int_size_in_bytes (type) * BITS_PER_UNIT;
4251 return upward; /* Don't know if this is right, but */
4252 /* same as old definition. */
4255 size = GET_MODE_BITSIZE (mode);
4256 if (size < PARM_BOUNDARY)
4258 else if (size % PARM_BOUNDARY)
4265 /* Do what is necessary for `va_start'. We look at the current function
4266 to determine if stdargs or varargs is used and fill in an initial
4267 va_list. A pointer to this constructor is returned. */
4270 hppa_builtin_saveregs ()
4273 tree fntype = TREE_TYPE (current_function_decl);
4274 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
4275 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4276 != void_type_node)))
4277 ? UNITS_PER_WORD : 0);
4280 offset = plus_constant (current_function_arg_offset_rtx, argadj);
4282 offset = current_function_arg_offset_rtx;
4284 /* Store general registers on the stack. */
4285 dest = gen_rtx_MEM (BLKmode,
4286 plus_constant (current_function_internal_arg_pointer,
4288 MEM_ALIAS_SET (dest) = get_varargs_alias_set ();
4289 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
4291 /* move_block_from_reg will emit code to store the argument registers
4292 individually as scalar stores.
4294 However, other insns may later load from the same addresses for
4295 a structure load (passing a struct to a varargs routine).
4297 The alias code assumes that such aliasing can never happen, so we
4298 have to keep memory referencing insns from moving up beyond the
4299 last argument register store. So we emit a blockage insn here. */
4300 emit_insn (gen_blockage ());
4302 if (current_function_check_memory_usage)
4303 emit_library_call (chkr_set_right_libfunc, 1, VOIDmode, 3,
4305 GEN_INT (4 * UNITS_PER_WORD), TYPE_MODE (sizetype),
4306 GEN_INT (MEMORY_USE_RW),
4307 TYPE_MODE (integer_type_node));
4309 return copy_to_reg (expand_binop (Pmode, add_optab,
4310 current_function_internal_arg_pointer,
4311 offset, 0, 0, OPTAB_LIB_WIDEN));
4315 hppa_va_start (stdarg_p, valist, nextarg)
4320 nextarg = expand_builtin_saveregs ();
4321 std_expand_builtin_va_start (1, valist, nextarg);
4325 hppa_va_arg (valist, type)
4328 HOST_WIDE_INT align, size, ofs;
4331 /* Compute the rounded size of the type. */
4332 align = PARM_BOUNDARY / BITS_PER_UNIT;
4333 size = int_size_in_bytes (type);
4335 ptr = build_pointer_type (type);
4337 /* "Large" types are passed by reference. */
4340 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
4341 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
4342 TREE_SIDE_EFFECTS (t) = 1;
4344 pptr = build_pointer_type (ptr);
4345 t = build1 (NOP_EXPR, pptr, t);
4346 TREE_SIDE_EFFECTS (t) = 1;
4348 t = build1 (INDIRECT_REF, ptr, t);
4349 TREE_SIDE_EFFECTS (t) = 1;
4353 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
4354 build_int_2 (-size, -1));
4356 /* ??? Copied from va-pa.h, but we probably don't need to align
4357 to word size, since we generate and preserve that invariant. */
4358 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
4359 build_int_2 ((size > 4 ? -8 : -4), -1));
4361 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
4362 TREE_SIDE_EFFECTS (t) = 1;
4364 ofs = (8 - size) % 4;
4367 t = build (PLUS_EXPR, TREE_TYPE (valist), t, build_int_2 (ofs, 0));
4368 TREE_SIDE_EFFECTS (t) = 1;
4371 t = build1 (NOP_EXPR, ptr, t);
4372 TREE_SIDE_EFFECTS (t) = 1;
4376 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
4381 /* This routine handles all the normal conditional branch sequences we
4382 might need to generate. It handles compare immediate vs compare
4383 register, nullification of delay slots, varying length branches,
4384 negated branches, and all combinations of the above. It returns the
4385 output appropriate to emit the branch corresponding to all given
4389 output_cbranch (operands, nullify, length, negated, insn)
4391 int nullify, length, negated;
4394 static char buf[100];
4397 /* A conditional branch to the following instruction (eg the delay slot) is
4398 asking for a disaster. This can happen when not optimizing.
4400 In such cases it is safe to emit nothing. */
4402 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4405 /* If this is a long branch with its delay slot unfilled, set `nullify'
4406 as it can nullify the delay slot and save a nop. */
4407 if (length == 8 && dbr_sequence_length () == 0)
4410 /* If this is a short forward conditional branch which did not get
4411 its delay slot filled, the delay slot can still be nullified. */
4412 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4413 nullify = forward_branch_p (insn);
4415 /* A forward branch over a single nullified insn can be done with a
4416 comclr instruction. This avoids a single cycle penalty due to
4417 mis-predicted branch if we fall through (branch not taken). */
4419 && next_real_insn (insn) != 0
4420 && get_attr_length (next_real_insn (insn)) == 4
4421 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4427 /* All short conditional branches except backwards with an unfilled
4431 strcpy (buf, "com%I2clr,");
4433 strcpy (buf, "com%I2b,");
4435 strcat (buf, "%B3");
4437 strcat (buf, "%S3");
4439 strcat (buf, " %2,%r1,%%r0");
4441 strcat (buf, ",n %2,%r1,%0");
4443 strcat (buf, " %2,%r1,%0");
4446 /* All long conditionals. Note an short backward branch with an
4447 unfilled delay slot is treated just like a long backward branch
4448 with an unfilled delay slot. */
4450 /* Handle weird backwards branch with a filled delay slot
4451 with is nullified. */
4452 if (dbr_sequence_length () != 0
4453 && ! forward_branch_p (insn)
4456 strcpy (buf, "com%I2b,");
4458 strcat (buf, "%S3");
4460 strcat (buf, "%B3");
4461 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
4463 /* Handle short backwards branch with an unfilled delay slot.
4464 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
4465 taken and untaken branches. */
4466 else if (dbr_sequence_length () == 0
4467 && ! forward_branch_p (insn)
4469 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4470 - insn_addresses[INSN_UID (insn)] - 8))
4472 strcpy (buf, "com%I2b,");
4474 strcat (buf, "%B3 %2,%r1,%0%#");
4476 strcat (buf, "%S3 %2,%r1,%0%#");
4480 strcpy (buf, "com%I2clr,");
4482 strcat (buf, "%S3");
4484 strcat (buf, "%B3");
4486 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
4488 strcat (buf, " %2,%r1,%%r0\n\tb %0");
4493 /* Very long branch. Right now we only handle these when not
4494 optimizing. See "jump" pattern in pa.md for details. */
4498 /* Create a reversed conditional branch which branches around
4499 the following insns. */
4501 strcpy (buf, "com%I2b,%S3,n %2,%r1,.+20");
4503 strcpy (buf, "com%I2b,%B3,n %2,%r1,.+20");
4504 output_asm_insn (buf, operands);
4506 /* Output an insn to save %r1. */
4507 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
4509 /* Now output a very long branch to the original target. */
4510 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
4512 /* Now restore the value of %r1 in the delay slot. We're not
4513 optimizing so we know nothing else can be in the delay slot. */
4514 return "ldw -16(%%r30),%%r1";
4517 /* Very long branch when generating PIC code. Right now we only
4518 handle these when not optimizing. See "jump" pattern in pa.md
4523 /* Create a reversed conditional branch which branches around
4524 the following insns. */
4526 strcpy (buf, "com%I2b,%S3,n %2,%r1,.+28");
4528 strcpy (buf, "com%I2b,%B3,n %2,%r1,.+28");
4529 output_asm_insn (buf, operands);
4531 /* Output an insn to save %r1. */
4532 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
4534 /* Now output a very long PIC branch to the original target. */
4538 xoperands[0] = operands[0];
4539 xoperands[1] = operands[1];
4540 xoperands[2] = operands[2];
4541 xoperands[3] = operands[3];
4542 xoperands[4] = gen_label_rtx ();
4544 output_asm_insn ("bl .+8,%%r1\n\taddil L'%l0-%l4,%%r1", xoperands);
4545 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
4546 CODE_LABEL_NUMBER (xoperands[4]));
4547 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1\n\tbv %%r0(%%r1)",
4551 /* Now restore the value of %r1 in the delay slot. We're not
4552 optimizing so we know nothing else can be in the delay slot. */
4553 return "ldw -16(%%r30),%%r1";
4561 /* This routine handles all the branch-on-bit conditional branch sequences we
4562 might need to generate. It handles nullification of delay slots,
4563 varying length branches, negated branches and all combinations of the
4564 above. it returns the appropriate output template to emit the branch. */
4567 output_bb (operands, nullify, length, negated, insn, which)
4568 rtx *operands ATTRIBUTE_UNUSED;
4569 int nullify, length, negated;
4573 static char buf[100];
4576 /* A conditional branch to the following instruction (eg the delay slot) is
4577 asking for a disaster. I do not think this can happen as this pattern
4578 is only used when optimizing; jump optimization should eliminate the
4579 jump. But be prepared just in case. */
4581 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4584 /* If this is a long branch with its delay slot unfilled, set `nullify'
4585 as it can nullify the delay slot and save a nop. */
4586 if (length == 8 && dbr_sequence_length () == 0)
4589 /* If this is a short forward conditional branch which did not get
4590 its delay slot filled, the delay slot can still be nullified. */
4591 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4592 nullify = forward_branch_p (insn);
4594 /* A forward branch over a single nullified insn can be done with a
4595 extrs instruction. This avoids a single cycle penalty due to
4596 mis-predicted branch if we fall through (branch not taken). */
4599 && next_real_insn (insn) != 0
4600 && get_attr_length (next_real_insn (insn)) == 4
4601 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4608 /* All short conditional branches except backwards with an unfilled
4612 strcpy (buf, "extrs,");
4614 strcpy (buf, "bb,");
4615 if ((which == 0 && negated)
4616 || (which == 1 && ! negated))
4621 strcat (buf, " %0,%1,1,%%r0");
4622 else if (nullify && negated)
4623 strcat (buf, ",n %0,%1,%3");
4624 else if (nullify && ! negated)
4625 strcat (buf, ",n %0,%1,%2");
4626 else if (! nullify && negated)
4627 strcat (buf, "%0,%1,%3");
4628 else if (! nullify && ! negated)
4629 strcat (buf, " %0,%1,%2");
4632 /* All long conditionals. Note an short backward branch with an
4633 unfilled delay slot is treated just like a long backward branch
4634 with an unfilled delay slot. */
4636 /* Handle weird backwards branch with a filled delay slot
4637 with is nullified. */
4638 if (dbr_sequence_length () != 0
4639 && ! forward_branch_p (insn)
4642 strcpy (buf, "bb,");
4643 if ((which == 0 && negated)
4644 || (which == 1 && ! negated))
4649 strcat (buf, ",n %0,%1,.+12\n\tb %3");
4651 strcat (buf, ",n %0,%1,.+12\n\tb %2");
4653 /* Handle short backwards branch with an unfilled delay slot.
4654 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4655 taken and untaken branches. */
4656 else if (dbr_sequence_length () == 0
4657 && ! forward_branch_p (insn)
4659 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4660 - insn_addresses[INSN_UID (insn)] - 8))
4662 strcpy (buf, "bb,");
4663 if ((which == 0 && negated)
4664 || (which == 1 && ! negated))
4669 strcat (buf, " %0,%1,%3%#");
4671 strcat (buf, " %0,%1,%2%#");
4675 strcpy (buf, "extrs,");
4676 if ((which == 0 && negated)
4677 || (which == 1 && ! negated))
4681 if (nullify && negated)
4682 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
4683 else if (nullify && ! negated)
4684 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
4686 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
4688 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
4698 /* This routine handles all the branch-on-variable-bit conditional branch
4699 sequences we might need to generate. It handles nullification of delay
4700 slots, varying length branches, negated branches and all combinations
4701 of the above. it returns the appropriate output template to emit the
4705 output_bvb (operands, nullify, length, negated, insn, which)
4706 rtx *operands ATTRIBUTE_UNUSED;
4707 int nullify, length, negated;
4711 static char buf[100];
4714 /* A conditional branch to the following instruction (eg the delay slot) is
4715 asking for a disaster. I do not think this can happen as this pattern
4716 is only used when optimizing; jump optimization should eliminate the
4717 jump. But be prepared just in case. */
4719 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4722 /* If this is a long branch with its delay slot unfilled, set `nullify'
4723 as it can nullify the delay slot and save a nop. */
4724 if (length == 8 && dbr_sequence_length () == 0)
4727 /* If this is a short forward conditional branch which did not get
4728 its delay slot filled, the delay slot can still be nullified. */
4729 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4730 nullify = forward_branch_p (insn);
4732 /* A forward branch over a single nullified insn can be done with a
4733 extrs instruction. This avoids a single cycle penalty due to
4734 mis-predicted branch if we fall through (branch not taken). */
4737 && next_real_insn (insn) != 0
4738 && get_attr_length (next_real_insn (insn)) == 4
4739 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
4746 /* All short conditional branches except backwards with an unfilled
4750 strcpy (buf, "vextrs,");
4752 strcpy (buf, "bvb,");
4753 if ((which == 0 && negated)
4754 || (which == 1 && ! negated))
4759 strcat (buf, " %0,1,%%r0");
4760 else if (nullify && negated)
4761 strcat (buf, ",n %0,%3");
4762 else if (nullify && ! negated)
4763 strcat (buf, ",n %0,%2");
4764 else if (! nullify && negated)
4765 strcat (buf, "%0,%3");
4766 else if (! nullify && ! negated)
4767 strcat (buf, " %0,%2");
4770 /* All long conditionals. Note an short backward branch with an
4771 unfilled delay slot is treated just like a long backward branch
4772 with an unfilled delay slot. */
4774 /* Handle weird backwards branch with a filled delay slot
4775 with is nullified. */
4776 if (dbr_sequence_length () != 0
4777 && ! forward_branch_p (insn)
4780 strcpy (buf, "bvb,");
4781 if ((which == 0 && negated)
4782 || (which == 1 && ! negated))
4787 strcat (buf, ",n %0,.+12\n\tb %3");
4789 strcat (buf, ",n %0,.+12\n\tb %2");
4791 /* Handle short backwards branch with an unfilled delay slot.
4792 Using a bb;nop rather than extrs;bl saves 1 cycle for both
4793 taken and untaken branches. */
4794 else if (dbr_sequence_length () == 0
4795 && ! forward_branch_p (insn)
4797 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4798 - insn_addresses[INSN_UID (insn)] - 8))
4800 strcpy (buf, "bvb,");
4801 if ((which == 0 && negated)
4802 || (which == 1 && ! negated))
4807 strcat (buf, " %0,%3%#");
4809 strcat (buf, " %0,%2%#");
4813 strcpy (buf, "vextrs,");
4814 if ((which == 0 && negated)
4815 || (which == 1 && ! negated))
4819 if (nullify && negated)
4820 strcat (buf, " %0,1,%%r0\n\tb,n %3");
4821 else if (nullify && ! negated)
4822 strcat (buf, " %0,1,%%r0\n\tb,n %2");
4824 strcat (buf, " %0,1,%%r0\n\tb %3");
4826 strcat (buf, " %0,1,%%r0\n\tb %2");
4836 /* Return the output template for emitting a dbra type insn.
4838 Note it may perform some output operations on its own before
4839 returning the final output string. */
4841 output_dbra (operands, insn, which_alternative)
4844 int which_alternative;
4847 /* A conditional branch to the following instruction (eg the delay slot) is
4848 asking for a disaster. Be prepared! */
4850 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4852 if (which_alternative == 0)
4853 return "ldo %1(%0),%0";
4854 else if (which_alternative == 1)
4856 output_asm_insn ("fstws %0,-16(%%r30)",operands);
4857 output_asm_insn ("ldw -16(%%r30),%4",operands);
4858 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
4859 return "fldws -16(%%r30),%0";
4863 output_asm_insn ("ldw %0,%4", operands);
4864 return "ldo %1(%4),%4\n\tstw %4,%0";
4868 if (which_alternative == 0)
4870 int nullify = INSN_ANNULLED_BRANCH_P (insn);
4871 int length = get_attr_length (insn);
4873 /* If this is a long branch with its delay slot unfilled, set `nullify'
4874 as it can nullify the delay slot and save a nop. */
4875 if (length == 8 && dbr_sequence_length () == 0)
4878 /* If this is a short forward conditional branch which did not get
4879 its delay slot filled, the delay slot can still be nullified. */
4880 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4881 nullify = forward_branch_p (insn);
4883 /* Handle short versions first. */
4884 if (length == 4 && nullify)
4885 return "addib,%C2,n %1,%0,%3";
4886 else if (length == 4 && ! nullify)
4887 return "addib,%C2 %1,%0,%3";
4888 else if (length == 8)
4890 /* Handle weird backwards branch with a fulled delay slot
4891 which is nullified. */
4892 if (dbr_sequence_length () != 0
4893 && ! forward_branch_p (insn)
4895 return "addib,%N2,n %1,%0,.+12\n\tb %3";
4896 /* Handle short backwards branch with an unfilled delay slot.
4897 Using a addb;nop rather than addi;bl saves 1 cycle for both
4898 taken and untaken branches. */
4899 else if (dbr_sequence_length () == 0
4900 && ! forward_branch_p (insn)
4902 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
4903 - insn_addresses[INSN_UID (insn)] - 8))
4904 return "addib,%C2 %1,%0,%3%#";
4906 /* Handle normal cases. */
4908 return "addi,%N2 %1,%0,%0\n\tb,n %3";
4910 return "addi,%N2 %1,%0,%0\n\tb %3";
4915 /* Deal with gross reload from FP register case. */
4916 else if (which_alternative == 1)
4918 /* Move loop counter from FP register to MEM then into a GR,
4919 increment the GR, store the GR into MEM, and finally reload
4920 the FP register from MEM from within the branch's delay slot. */
4921 output_asm_insn ("fstws %0,-16(%%r30)\n\tldw -16(%%r30),%4",operands);
4922 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
4923 if (get_attr_length (insn) == 24)
4924 return "comb,%S2 %%r0,%4,%3\n\tfldws -16(%%r30),%0";
4926 return "comclr,%B2 %%r0,%4,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
4928 /* Deal with gross reload from memory case. */
4931 /* Reload loop counter from memory, the store back to memory
4932 happens in the branch's delay slot. */
4933 output_asm_insn ("ldw %0,%4", operands);
4934 if (get_attr_length (insn) == 12)
4935 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
4937 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
4941 /* Return the output template for emitting a dbra type insn.
4943 Note it may perform some output operations on its own before
4944 returning the final output string. */
4946 output_movb (operands, insn, which_alternative, reverse_comparison)
4949 int which_alternative;
4950 int reverse_comparison;
4953 /* A conditional branch to the following instruction (eg the delay slot) is
4954 asking for a disaster. Be prepared! */
4956 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
4958 if (which_alternative == 0)
4959 return "copy %1,%0";
4960 else if (which_alternative == 1)
4962 output_asm_insn ("stw %1,-16(%%r30)",operands);
4963 return "fldws -16(%%r30),%0";
4965 else if (which_alternative == 2)
4971 /* Support the second variant. */
4972 if (reverse_comparison)
4973 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
4975 if (which_alternative == 0)
4977 int nullify = INSN_ANNULLED_BRANCH_P (insn);
4978 int length = get_attr_length (insn);
4980 /* If this is a long branch with its delay slot unfilled, set `nullify'
4981 as it can nullify the delay slot and save a nop. */
4982 if (length == 8 && dbr_sequence_length () == 0)
4985 /* If this is a short forward conditional branch which did not get
4986 its delay slot filled, the delay slot can still be nullified. */
4987 if (! nullify && length == 4 && dbr_sequence_length () == 0)
4988 nullify = forward_branch_p (insn);
4990 /* Handle short versions first. */
4991 if (length == 4 && nullify)
4992 return "movb,%C2,n %1,%0,%3";
4993 else if (length == 4 && ! nullify)
4994 return "movb,%C2 %1,%0,%3";
4995 else if (length == 8)
4997 /* Handle weird backwards branch with a filled delay slot
4998 which is nullified. */
4999 if (dbr_sequence_length () != 0
5000 && ! forward_branch_p (insn)
5002 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5004 /* Handle short backwards branch with an unfilled delay slot.
5005 Using a movb;nop rather than or;bl saves 1 cycle for both
5006 taken and untaken branches. */
5007 else if (dbr_sequence_length () == 0
5008 && ! forward_branch_p (insn)
5010 && VAL_14_BITS_P (insn_addresses[INSN_UID (JUMP_LABEL (insn))]
5011 - insn_addresses[INSN_UID (insn)] - 8))
5012 return "movb,%C2 %1,%0,%3%#";
5013 /* Handle normal cases. */
5015 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5017 return "or,%N2 %1,%%r0,%0\n\tb %3";
5022 /* Deal with gross reload from FP register case. */
5023 else if (which_alternative == 1)
5025 /* Move loop counter from FP register to MEM then into a GR,
5026 increment the GR, store the GR into MEM, and finally reload
5027 the FP register from MEM from within the branch's delay slot. */
5028 output_asm_insn ("stw %1,-16(%%r30)",operands);
5029 if (get_attr_length (insn) == 12)
5030 return "comb,%S2 %%r0,%1,%3\n\tfldws -16(%%r30),%0";
5032 return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tfldws -16(%%r30),%0";
5034 /* Deal with gross reload from memory case. */
5035 else if (which_alternative == 2)
5037 /* Reload loop counter from memory, the store back to memory
5038 happens in the branch's delay slot. */
5039 if (get_attr_length (insn) == 8)
5040 return "comb,%S2 %%r0,%1,%3\n\tstw %1,%0";
5042 return "comclr,%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5044 /* Handle SAR as a destination. */
5047 if (get_attr_length (insn) == 8)
5048 return "comb,%S2 %%r0,%1,%3\n\tmtsar %r1";
5050 return "comclr,%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5055 /* INSN is a millicode call. It may have an unconditional jump in its delay
5058 CALL_DEST is the routine we are calling. */
5061 output_millicode_call (insn, call_dest)
5069 /* Handle common case -- empty delay slot or no jump in the delay slot,
5070 and we're sure that the branch will reach the beginning of the $CODE$
5072 if ((dbr_sequence_length () == 0
5073 && (get_attr_length (insn) == 8 || get_attr_length (insn) == 28))
5074 || (dbr_sequence_length () != 0
5075 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5076 && get_attr_length (insn) == 4))
5078 xoperands[0] = call_dest;
5079 output_asm_insn ("bl %0,%%r31%#", xoperands);
5083 /* This call may not reach the beginning of the $CODE$ subspace. */
5084 if (get_attr_length (insn) > 4)
5086 int delay_insn_deleted = 0;
5089 /* We need to emit an inline long-call branch. */
5090 if (dbr_sequence_length () != 0
5091 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5093 /* A non-jump insn in the delay slot. By definition we can
5094 emit this insn before the call. */
5095 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5097 /* Now delete the delay insn. */
5098 PUT_CODE (NEXT_INSN (insn), NOTE);
5099 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5100 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5101 delay_insn_deleted = 1;
5104 /* If we're allowed to use be/ble instructions, then this is the
5105 best sequence to use for a long millicode call. */
5106 if (TARGET_NO_SPACE_REGS || TARGET_FAST_INDIRECT_CALLS
5107 || ! (flag_pic || TARGET_PORTABLE_RUNTIME))
5109 xoperands[0] = call_dest;
5110 output_asm_insn ("ldil L%%%0,%%r31", xoperands);
5111 output_asm_insn ("ble R%%%0(%%sr4,%%r31)", xoperands);
5112 output_asm_insn ("nop", xoperands);
5114 /* Pure portable runtime doesn't allow be/ble; we also don't have
5115 PIC support int he assembler/linker, so this sequence is needed. */
5116 else if (TARGET_PORTABLE_RUNTIME)
5118 xoperands[0] = call_dest;
5119 /* Get the address of our target into %r29. */
5120 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
5121 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
5123 /* Get our return address into %r31. */
5124 output_asm_insn ("blr %%r0,%%r31", xoperands);
5126 /* Jump to our target address in %r29. */
5127 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
5129 /* Empty delay slot. Note this insn gets fetched twice and
5130 executed once. To be safe we use a nop. */
5131 output_asm_insn ("nop", xoperands);
5134 /* PIC long millicode call sequence. */
5137 xoperands[0] = call_dest;
5138 xoperands[1] = gen_label_rtx ();
5139 /* Get our address + 8 into %r1. */
5140 output_asm_insn ("bl .+8,%%r1", xoperands);
5142 /* Add %r1 to the offset of our target from the next insn. */
5143 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
5144 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5145 CODE_LABEL_NUMBER (xoperands[1]));
5146 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
5148 /* Get the return address into %r31. */
5149 output_asm_insn ("blr 0,%%r31", xoperands);
5151 /* Branch to our target which is in %r1. */
5152 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
5154 /* Empty delay slot. Note this insn gets fetched twice and
5155 executed once. To be safe we use a nop. */
5156 output_asm_insn ("nop", xoperands);
5159 /* If we had a jump in the call's delay slot, output it now. */
5160 if (dbr_sequence_length () != 0
5161 && !delay_insn_deleted)
5163 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5164 output_asm_insn ("b,n %0", xoperands);
5166 /* Now delete the delay insn. */
5167 PUT_CODE (NEXT_INSN (insn), NOTE);
5168 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5169 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5174 /* This call has an unconditional jump in its delay slot and the
5175 call is known to reach its target or the beginning of the current
5178 /* Use the containing sequence insn's address. */
5179 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5181 distance = insn_addresses[INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))]
5182 - insn_addresses[INSN_UID (seq_insn)] - 8;
5184 /* If the branch was too far away, emit a normal call followed
5185 by a nop, followed by the unconditional branch.
5187 If the branch is close, then adjust %r2 from within the
5188 call's delay slot. */
5190 xoperands[0] = call_dest;
5191 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5192 if (! VAL_14_BITS_P (distance))
5193 output_asm_insn ("bl %0,%%r31\n\tnop\n\tb,n %1", xoperands);
5196 xoperands[3] = gen_label_rtx ();
5197 output_asm_insn ("\n\tbl %0,%%r31\n\tldo %1-%3(%%r31),%%r31", xoperands);
5198 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5199 CODE_LABEL_NUMBER (xoperands[3]));
5202 /* Delete the jump. */
5203 PUT_CODE (NEXT_INSN (insn), NOTE);
5204 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5205 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5209 extern struct obstack permanent_obstack;
5210 extern struct obstack *saveable_obstack;
5211 extern struct obstack *rtl_obstack;
5212 extern struct obstack *current_obstack;
5214 /* INSN is either a function call. It may have an unconditional jump
5217 CALL_DEST is the routine we are calling. */
5220 output_call (insn, call_dest)
5228 /* Handle common case -- empty delay slot or no jump in the delay slot,
5229 and we're sure that the branch will reach the beginning of the $CODE$
5231 if ((dbr_sequence_length () == 0
5232 && get_attr_length (insn) == 8)
5233 || (dbr_sequence_length () != 0
5234 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
5235 && get_attr_length (insn) == 4))
5237 xoperands[0] = call_dest;
5238 output_asm_insn ("bl %0,%%r2%#", xoperands);
5242 /* This call may not reach the beginning of the $CODE$ subspace. */
5243 if (get_attr_length (insn) > 8)
5245 int delay_insn_deleted = 0;
5249 /* We need to emit an inline long-call branch. Furthermore,
5250 because we're changing a named function call into an indirect
5251 function call well after the parameters have been set up, we
5252 need to make sure any FP args appear in both the integer
5253 and FP registers. Also, we need move any delay slot insn
5254 out of the delay slot. And finally, we can't rely on the linker
5255 being able to fix the call to $$dyncall! -- Yuk!. */
5256 if (dbr_sequence_length () != 0
5257 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
5259 /* A non-jump insn in the delay slot. By definition we can
5260 emit this insn before the call (and in fact before argument
5262 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
5264 /* Now delete the delay insn. */
5265 PUT_CODE (NEXT_INSN (insn), NOTE);
5266 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5267 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5268 delay_insn_deleted = 1;
5271 /* Now copy any FP arguments into integer registers. */
5272 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
5274 int arg_mode, regno;
5275 rtx use = XEXP (link, 0);
5276 if (! (GET_CODE (use) == USE
5277 && GET_CODE (XEXP (use, 0)) == REG
5278 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5281 arg_mode = GET_MODE (XEXP (use, 0));
5282 regno = REGNO (XEXP (use, 0));
5283 /* Is it a floating point register? */
5284 if (regno >= 32 && regno <= 39)
5286 /* Copy from the FP register into an integer register
5288 if (arg_mode == SFmode)
5290 xoperands[0] = XEXP (use, 0);
5291 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
5292 output_asm_insn ("fstws %0,-16(%%sr0,%%r30)", xoperands);
5293 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5297 xoperands[0] = XEXP (use, 0);
5298 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
5299 output_asm_insn ("fstds %0,-16(%%sr0,%%r30)", xoperands);
5300 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
5301 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
5306 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
5307 we don't have any direct calls in that case. */
5310 char *name = XSTR (call_dest, 0);
5312 /* See if we have already put this function on the list
5313 of deferred plabels. This list is generally small,
5314 so a liner search is not too ugly. If it proves too
5315 slow replace it with something faster. */
5316 for (i = 0; i < n_deferred_plabels; i++)
5317 if (strcmp (name, deferred_plabels[i].name) == 0)
5320 /* If the deferred plabel list is empty, or this entry was
5321 not found on the list, create a new entry on the list. */
5322 if (deferred_plabels == NULL || i == n_deferred_plabels)
5324 struct obstack *ambient_obstack = current_obstack;
5325 struct obstack *ambient_rtl_obstack = rtl_obstack;
5328 /* Any RTL we create here needs to live until the end of
5329 the compilation unit and therefore must live on the
5330 permanent obstack. */
5331 current_obstack = &permanent_obstack;
5332 rtl_obstack = &permanent_obstack;
5334 if (deferred_plabels == 0)
5335 deferred_plabels = (struct deferred_plabel *)
5336 xmalloc (1 * sizeof (struct deferred_plabel));
5338 deferred_plabels = (struct deferred_plabel *)
5339 xrealloc (deferred_plabels,
5340 ((n_deferred_plabels + 1)
5341 * sizeof (struct deferred_plabel)));
5343 i = n_deferred_plabels++;
5344 deferred_plabels[i].internal_label = gen_label_rtx ();
5345 deferred_plabels[i].name = obstack_alloc (&permanent_obstack,
5347 strcpy (deferred_plabels[i].name, name);
5349 /* Switch back to normal obstack allocation. */
5350 current_obstack = ambient_obstack;
5351 rtl_obstack = ambient_rtl_obstack;
5353 /* Gross. We have just implicitly taken the address of this
5354 function, mark it as such. */
5355 STRIP_NAME_ENCODING (real_name, name);
5356 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5359 /* We have to load the address of the function using a procedure
5360 label (plabel). Inline plabels can lose for PIC and other
5361 cases, so avoid them by creating a 32bit plabel in the data
5365 xoperands[0] = deferred_plabels[i].internal_label;
5366 xoperands[1] = gen_label_rtx ();
5368 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
5369 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
5370 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
5372 /* Get our address + 8 into %r1. */
5373 output_asm_insn ("bl .+8,%%r1", xoperands);
5375 /* Add %r1 to the offset of dyncall from the next insn. */
5376 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
5377 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5378 CODE_LABEL_NUMBER (xoperands[1]));
5379 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
5381 /* Get the return address into %r31. */
5382 output_asm_insn ("blr %%r0,%%r31", xoperands);
5384 /* Branch to our target which is in %r1. */
5385 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5387 /* Copy the return address into %r2 also. */
5388 output_asm_insn ("copy %%r31,%%r2", xoperands);
5392 xoperands[0] = deferred_plabels[i].internal_label;
5394 /* Get the address of our target into %r22. */
5395 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
5396 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
5398 /* Get the high part of the address of $dyncall into %r2, then
5399 add in the low part in the branch instruction. */
5400 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
5401 output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands);
5403 /* Copy the return pointer into both %r31 and %r2. */
5404 output_asm_insn ("copy %%r31,%%r2", xoperands);
5408 /* If we had a jump in the call's delay slot, output it now. */
5409 if (dbr_sequence_length () != 0
5410 && !delay_insn_deleted)
5412 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5413 output_asm_insn ("b,n %0", xoperands);
5415 /* Now delete the delay insn. */
5416 PUT_CODE (NEXT_INSN (insn), NOTE);
5417 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5418 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5423 /* This call has an unconditional jump in its delay slot and the
5424 call is known to reach its target or the beginning of the current
5427 /* Use the containing sequence insn's address. */
5428 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
5430 distance = insn_addresses[INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))]
5431 - insn_addresses[INSN_UID (seq_insn)] - 8;
5433 /* If the branch was too far away, emit a normal call followed
5434 by a nop, followed by the unconditional branch.
5436 If the branch is close, then adjust %r2 from within the
5437 call's delay slot. */
5439 xoperands[0] = call_dest;
5440 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
5441 if (! VAL_14_BITS_P (distance))
5442 output_asm_insn ("bl %0,%%r2\n\tnop\n\tb,n %1", xoperands);
5445 xoperands[3] = gen_label_rtx ();
5446 output_asm_insn ("\n\tbl %0,%%r2\n\tldo %1-%3(%%r2),%%r2", xoperands);
5447 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5448 CODE_LABEL_NUMBER (xoperands[3]));
5451 /* Delete the jump. */
5452 PUT_CODE (NEXT_INSN (insn), NOTE);
5453 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5454 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5458 /* In HPUX 8.0's shared library scheme, special relocations are needed
5459 for function labels if they might be passed to a function
5460 in a shared library (because shared libraries don't live in code
5461 space), and special magic is needed to construct their address.
5463 For reasons too disgusting to describe storage for the new name
5464 is allocated either on the saveable_obstack (released at function
5465 exit) or on the permanent_obstack for things that can never change
5466 (libcall names for example). */
5469 hppa_encode_label (sym, permanent)
5473 char *str = XSTR (sym, 0);
5474 int len = strlen (str);
5477 newstr = obstack_alloc ((permanent ? &permanent_obstack : saveable_obstack),
5482 strcpy (newstr + 1, str);
5484 XSTR (sym,0) = newstr;
5488 function_label_operand (op, mode)
5490 enum machine_mode mode ATTRIBUTE_UNUSED;
5492 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
5495 /* Returns 1 if OP is a function label involved in a simple addition
5496 with a constant. Used to keep certain patterns from matching
5497 during instruction combination. */
5499 is_function_label_plus_const (op)
5502 /* Strip off any CONST. */
5503 if (GET_CODE (op) == CONST)
5506 return (GET_CODE (op) == PLUS
5507 && function_label_operand (XEXP (op, 0), Pmode)
5508 && GET_CODE (XEXP (op, 1)) == CONST_INT);
5511 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5512 use in fmpyadd instructions. */
5514 fmpyaddoperands (operands)
5517 enum machine_mode mode = GET_MODE (operands[0]);
5519 /* Must be a floating point mode. */
5520 if (mode != SFmode && mode != DFmode)
5523 /* All modes must be the same. */
5524 if (! (mode == GET_MODE (operands[1])
5525 && mode == GET_MODE (operands[2])
5526 && mode == GET_MODE (operands[3])
5527 && mode == GET_MODE (operands[4])
5528 && mode == GET_MODE (operands[5])))
5531 /* All operands must be registers. */
5532 if (! (GET_CODE (operands[1]) == REG
5533 && GET_CODE (operands[2]) == REG
5534 && GET_CODE (operands[3]) == REG
5535 && GET_CODE (operands[4]) == REG
5536 && GET_CODE (operands[5]) == REG))
5539 /* Only 2 real operands to the addition. One of the input operands must
5540 be the same as the output operand. */
5541 if (! rtx_equal_p (operands[3], operands[4])
5542 && ! rtx_equal_p (operands[3], operands[5]))
5545 /* Inout operand of add can not conflict with any operands from multiply. */
5546 if (rtx_equal_p (operands[3], operands[0])
5547 || rtx_equal_p (operands[3], operands[1])
5548 || rtx_equal_p (operands[3], operands[2]))
5551 /* multiply can not feed into addition operands. */
5552 if (rtx_equal_p (operands[4], operands[0])
5553 || rtx_equal_p (operands[5], operands[0]))
5556 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5558 && (REGNO (operands[0]) < 57
5559 || REGNO (operands[1]) < 57
5560 || REGNO (operands[2]) < 57
5561 || REGNO (operands[3]) < 57
5562 || REGNO (operands[4]) < 57
5563 || REGNO (operands[5]) < 57))
5566 /* Passed. Operands are suitable for fmpyadd. */
5570 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
5571 use in fmpysub instructions. */
5573 fmpysuboperands (operands)
5576 enum machine_mode mode = GET_MODE (operands[0]);
5578 /* Must be a floating point mode. */
5579 if (mode != SFmode && mode != DFmode)
5582 /* All modes must be the same. */
5583 if (! (mode == GET_MODE (operands[1])
5584 && mode == GET_MODE (operands[2])
5585 && mode == GET_MODE (operands[3])
5586 && mode == GET_MODE (operands[4])
5587 && mode == GET_MODE (operands[5])))
5590 /* All operands must be registers. */
5591 if (! (GET_CODE (operands[1]) == REG
5592 && GET_CODE (operands[2]) == REG
5593 && GET_CODE (operands[3]) == REG
5594 && GET_CODE (operands[4]) == REG
5595 && GET_CODE (operands[5]) == REG))
5598 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
5599 operation, so operands[4] must be the same as operand[3]. */
5600 if (! rtx_equal_p (operands[3], operands[4]))
5603 /* multiply can not feed into subtraction. */
5604 if (rtx_equal_p (operands[5], operands[0]))
5607 /* Inout operand of sub can not conflict with any operands from multiply. */
5608 if (rtx_equal_p (operands[3], operands[0])
5609 || rtx_equal_p (operands[3], operands[1])
5610 || rtx_equal_p (operands[3], operands[2]))
5613 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
5615 && (REGNO (operands[0]) < 57
5616 || REGNO (operands[1]) < 57
5617 || REGNO (operands[2]) < 57
5618 || REGNO (operands[3]) < 57
5619 || REGNO (operands[4]) < 57
5620 || REGNO (operands[5]) < 57))
5623 /* Passed. Operands are suitable for fmpysub. */
5628 plus_xor_ior_operator (op, mode)
5630 enum machine_mode mode ATTRIBUTE_UNUSED;
5632 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
5633 || GET_CODE (op) == IOR);
5636 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
5637 constants for shadd instructions. */
5639 shadd_constant_p (val)
5642 if (val == 2 || val == 4 || val == 8)
5648 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
5649 the valid constant for shadd instructions. */
5651 shadd_operand (op, mode)
5653 enum machine_mode mode ATTRIBUTE_UNUSED;
5655 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
5658 /* Return 1 if OP is valid as a base register in a reg + reg address. */
5661 basereg_operand (op, mode)
5663 enum machine_mode mode;
5665 /* cse will create some unscaled indexed addresses, however; it
5666 generally isn't a win on the PA, so avoid creating unscaled
5667 indexed addresses until after cse is finished. */
5668 if (!cse_not_expected)
5671 /* Once reload has started everything is considered valid. Reload should
5672 only create indexed addresses using the stack/frame pointer, and any
5673 others were checked for validity when created by the combine pass.
5675 Also allow any register when TARGET_NO_SPACE_REGS is in effect since
5676 we don't have to worry about the braindamaged implicit space register
5677 selection using the basereg only (rather than effective address)
5678 screwing us over. */
5679 if (TARGET_NO_SPACE_REGS || reload_in_progress || reload_completed)
5680 return (GET_CODE (op) == REG);
5682 /* Stack is always OK for indexing. */
5683 if (op == stack_pointer_rtx)
5686 /* While it's always safe to index off the frame pointer, it's not
5687 always profitable, particularly when the frame pointer is being
5689 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
5692 /* The only other valid OPs are pseudo registers with
5693 REGNO_POINTER_FLAG set. */
5694 if (GET_CODE (op) != REG
5695 || REGNO (op) < FIRST_PSEUDO_REGISTER
5696 || ! register_operand (op, mode))
5699 return REGNO_POINTER_FLAG (REGNO (op));
5702 /* Return 1 if this operand is anything other than a hard register. */
5705 non_hard_reg_operand (op, mode)
5707 enum machine_mode mode ATTRIBUTE_UNUSED;
5709 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
5712 /* Return 1 if INSN branches forward. Should be using insn_addresses
5713 to avoid walking through all the insns... */
5715 forward_branch_p (insn)
5718 rtx label = JUMP_LABEL (insn);
5725 insn = NEXT_INSN (insn);
5728 return (insn == label);
5731 /* Return 1 if OP is an equality comparison, else return 0. */
5733 eq_neq_comparison_operator (op, mode)
5735 enum machine_mode mode ATTRIBUTE_UNUSED;
5737 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
5740 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
5742 movb_comparison_operator (op, mode)
5744 enum machine_mode mode ATTRIBUTE_UNUSED;
5746 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
5747 || GET_CODE (op) == LT || GET_CODE (op) == GE);
5750 /* Return 1 if INSN is in the delay slot of a call instruction. */
5752 jump_in_call_delay (insn)
5756 if (GET_CODE (insn) != JUMP_INSN)
5759 if (PREV_INSN (insn)
5760 && PREV_INSN (PREV_INSN (insn))
5761 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
5763 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
5765 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
5766 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
5773 /* Output an unconditional move and branch insn. */
5776 output_parallel_movb (operands, length)
5780 /* These are the cases in which we win. */
5782 return "mov%I1b,tr %1,%0,%2";
5784 /* None of these cases wins, but they don't lose either. */
5785 if (dbr_sequence_length () == 0)
5787 /* Nothing in the delay slot, fake it by putting the combined
5788 insn (the copy or add) in the delay slot of a bl. */
5789 if (GET_CODE (operands[1]) == CONST_INT)
5790 return "b %2\n\tldi %1,%0";
5792 return "b %2\n\tcopy %1,%0";
5796 /* Something in the delay slot, but we've got a long branch. */
5797 if (GET_CODE (operands[1]) == CONST_INT)
5798 return "ldi %1,%0\n\tb %2";
5800 return "copy %1,%0\n\tb %2";
5804 /* Output an unconditional add and branch insn. */
5807 output_parallel_addb (operands, length)
5811 /* To make life easy we want operand0 to be the shared input/output
5812 operand and operand1 to be the readonly operand. */
5813 if (operands[0] == operands[1])
5814 operands[1] = operands[2];
5816 /* These are the cases in which we win. */
5818 return "add%I1b,tr %1,%0,%3";
5820 /* None of these cases win, but they don't lose either. */
5821 if (dbr_sequence_length () == 0)
5823 /* Nothing in the delay slot, fake it by putting the combined
5824 insn (the copy or add) in the delay slot of a bl. */
5825 return "b %3\n\tadd%I1 %1,%0,%0";
5829 /* Something in the delay slot, but we've got a long branch. */
5830 return "add%I1 %1,%0,%0\n\tb %3";
5834 /* Return nonzero if INSN (a jump insn) immediately follows a call to
5835 a named function. This is used to discourage creating parallel movb/addb
5836 insns since a jump which immediately follows a call can execute in the
5837 delay slot of the call.
5839 It is also used to avoid filling the delay slot of a jump which
5840 immediately follows a call since the jump can usually be eliminated
5841 completely by modifying RP in the delay slot of the call. */
5844 following_call (insn)
5847 /* Find the previous real insn, skipping NOTEs. */
5848 insn = PREV_INSN (insn);
5849 while (insn && GET_CODE (insn) == NOTE)
5850 insn = PREV_INSN (insn);
5852 /* Check for CALL_INSNs and millicode calls. */
5854 && ((GET_CODE (insn) == CALL_INSN
5855 && get_attr_type (insn) != TYPE_DYNCALL)
5856 || (GET_CODE (insn) == INSN
5857 && GET_CODE (PATTERN (insn)) != SEQUENCE
5858 && GET_CODE (PATTERN (insn)) != USE
5859 && GET_CODE (PATTERN (insn)) != CLOBBER
5860 && get_attr_type (insn) == TYPE_MILLI)))
5866 /* Restore any INSN_CODEs for insns with unscaled indexed addresses since
5867 the INSN_CODE might be clobberd by rerecognition triggered by reorg. */
5870 restore_unscaled_index_insn_codes (insns)
5875 for (insn = insns; insn; insn = NEXT_INSN (insn))
5877 if (INSN_UID (insn) < max_unscaled_index_insn_codes_uid
5878 && unscaled_index_insn_codes[INSN_UID (insn)] != -1)
5879 INSN_CODE (insn) = unscaled_index_insn_codes[INSN_UID (insn)];
5883 /* Severe braindamage:
5885 On the PA, address computations within MEM expressions are not
5886 commutative because of the implicit space register selection
5887 from the base register (instead of the entire effective address).
5889 Because of this mis-feature we have to know which register in a reg+reg
5890 address is the base and which is the index.
5892 Before reload, the base can be identified by REGNO_POINTER_FLAG. We use
5893 this to force base + index addresses to match a different insn than
5894 index + base addresses.
5896 We assume that no pass during or after reload creates new unscaled indexed
5897 addresses, so any unscaled indexed address we find after reload must have
5898 at one time been recognized a base + index or index + base and we accept
5899 any register as a base register.
5901 This scheme assumes that no pass during/after reload will rerecognize an
5902 insn with an unscaled indexed address. This failed due to a reorg call
5903 to rerecognize certain insns.
5905 So, we record if an insn uses an unscaled indexed address and which
5906 register is the base (via recording of the INSN_CODE for such insns).
5908 Just before we output code for the function, we make sure all the insns
5909 using unscaled indexed addresses have the same INSN_CODE as they did
5910 immediately before delay slot scheduling.
5912 This is extremely gross. Long term, I'd like to be able to look at
5913 REG_POINTER_FLAG to handle these kinds of problems. */
5916 record_unscaled_index_insn_codes (insns)
5921 max_unscaled_index_insn_codes_uid = get_max_uid ();
5922 unscaled_index_insn_codes
5923 = (int *)xmalloc (max_unscaled_index_insn_codes_uid * sizeof (int));
5924 memset (unscaled_index_insn_codes, -1,
5925 max_unscaled_index_insn_codes_uid * sizeof (int));
5927 for (insn = insns; insn; insn = NEXT_INSN (insn))
5929 rtx set = single_set (insn);
5932 /* Ignore anything that isn't a normal SET. */
5933 if (set == NULL_RTX)
5936 /* No insns can have more than one MEM. */
5937 if (GET_CODE (SET_SRC (set)) == MEM)
5938 mem = SET_SRC (set);
5940 if (GET_CODE (SET_DEST (set)) == MEM)
5941 mem = SET_DEST (set);
5943 /* If neither operand is a mem, then there's nothing to do. */
5944 if (mem == NULL_RTX)
5947 if (GET_CODE (XEXP (mem, 0)) != PLUS)
5950 /* If both are REGs (or SUBREGs), then record the insn code for
5952 if (REG_P (XEXP (XEXP (mem, 0), 0)) && REG_P (XEXP (XEXP (mem, 0), 1)))
5953 unscaled_index_insn_codes[INSN_UID (insn)] = INSN_CODE (insn);
5957 /* We use this hook to perform a PA specific optimization which is difficult
5958 to do in earlier passes.
5960 We want the delay slots of branches within jump tables to be filled.
5961 None of the compiler passes at the moment even has the notion that a
5962 PA jump table doesn't contain addresses, but instead contains actual
5965 Because we actually jump into the table, the addresses of each entry
5966 must stay constant in relation to the beginning of the table (which
5967 itself must stay constant relative to the instruction to jump into
5968 it). I don't believe we can guarantee earlier passes of the compiler
5969 will adhere to those rules.
5971 So, late in the compilation process we find all the jump tables, and
5972 expand them into real code -- eg each entry in the jump table vector
5973 will get an appropriate label followed by a jump to the final target.
5975 Reorg and the final jump pass can then optimize these branches and
5976 fill their delay slots. We end up with smaller, more efficient code.
5978 The jump instructions within the table are special; we must be able
5979 to identify them during assembly output (if the jumps don't get filled
5980 we need to emit a nop rather than nullifying the delay slot)). We
5981 identify jumps in switch tables by marking the SET with DImode.
5983 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
5984 insns. This serves two purposes, first it prevents jump.c from
5985 noticing that the last N entries in the table jump to the instruction
5986 immediately after the table and deleting the jumps. Second, those
5987 insns mark where we should emit .begin_brtab and .end_brtab directives
5988 when using GAS (allows for better link time optimizations). */
5996 /* Keep track of which insns have unscaled indexed addresses, and which
5997 register is the base address in such insns. */
5998 record_unscaled_index_insn_codes (insns);
6000 remove_useless_addtr_insns (insns, 1);
6002 if (pa_cpu < PROCESSOR_8000)
6003 pa_combine_instructions (get_insns ());
6006 /* This is fairly cheap, so always run it if optimizing. */
6007 if (optimize > 0 && !TARGET_BIG_SWITCH)
6009 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6010 insns = get_insns ();
6011 for (insn = insns; insn; insn = NEXT_INSN (insn))
6013 rtx pattern, tmp, location;
6014 unsigned int length, i;
6016 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6017 if (GET_CODE (insn) != JUMP_INSN
6018 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6019 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6022 /* Emit marker for the beginning of the branch table. */
6023 emit_insn_before (gen_begin_brtab (), insn);
6025 pattern = PATTERN (insn);
6026 location = PREV_INSN (insn);
6027 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
6029 for (i = 0; i < length; i++)
6031 /* Emit a label before each jump to keep jump.c from
6032 removing this code. */
6033 tmp = gen_label_rtx ();
6034 LABEL_NUSES (tmp) = 1;
6035 emit_label_after (tmp, location);
6036 location = NEXT_INSN (location);
6038 if (GET_CODE (pattern) == ADDR_VEC)
6040 /* Emit the jump itself. */
6041 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
6042 tmp = emit_jump_insn_after (tmp, location);
6043 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
6044 /* It is easy to rely on the branch table markers
6045 during assembly output to trigger the correct code
6046 for a switch table jump with an unfilled delay slot,
6048 However, that requires state and assumes that we look
6051 We can't make such assumptions when computing the length
6052 of instructions. Ugh. We could walk the insn chain to
6053 determine if this instruction is in a branch table, but
6054 that can get rather expensive, particularly during the
6055 branch shortening phase of the compiler.
6057 So instead we mark this jump as being special. This is
6058 far from ideal and knows that no code after this will
6059 muck around with the mode of the JUMP_INSN itself. */
6060 PUT_MODE (tmp, SImode);
6061 LABEL_NUSES (JUMP_LABEL (tmp))++;
6062 location = NEXT_INSN (location);
6066 /* Emit the jump itself. */
6067 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
6068 tmp = emit_jump_insn_after (tmp, location);
6069 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
6070 /* It is easy to rely on the branch table markers
6071 during assembly output to trigger the correct code
6072 for a switch table jump with an unfilled delay slot,
6074 However, that requires state and assumes that we look
6077 We can't make such assumptions when computing the length
6078 of instructions. Ugh. We could walk the insn chain to
6079 determine if this instruction is in a branch table, but
6080 that can get rather expensive, particularly during the
6081 branch shortening phase of the compiler.
6083 So instead we mark this jump as being special. This is
6084 far from ideal and knows that no code after this will
6085 muck around with the mode of the JUMP_INSN itself. */
6086 PUT_MODE (tmp, SImode);
6087 LABEL_NUSES (JUMP_LABEL (tmp))++;
6088 location = NEXT_INSN (location);
6091 /* Emit a BARRIER after the jump. */
6092 emit_barrier_after (location);
6093 location = NEXT_INSN (location);
6096 /* Emit marker for the end of the branch table. */
6097 emit_insn_before (gen_end_brtab (), location);
6098 location = NEXT_INSN (location);
6099 emit_barrier_after (location);
6101 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
6107 /* Sill need an end_brtab insn. */
6108 insns = get_insns ();
6109 for (insn = insns; insn; insn = NEXT_INSN (insn))
6111 /* Find an ADDR_VEC insn. */
6112 if (GET_CODE (insn) != JUMP_INSN
6113 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6114 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6117 /* Now generate markers for the beginning and end of the
6119 emit_insn_before (gen_begin_brtab (), insn);
6120 emit_insn_after (gen_end_brtab (), insn);
6125 /* The PA has a number of odd instructions which can perform multiple
6126 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
6127 it may be profitable to combine two instructions into one instruction
6128 with two outputs. It's not profitable PA2.0 machines because the
6129 two outputs would take two slots in the reorder buffers.
6131 This routine finds instructions which can be combined and combines
6132 them. We only support some of the potential combinations, and we
6133 only try common ways to find suitable instructions.
6135 * addb can add two registers or a register and a small integer
6136 and jump to a nearby (+-8k) location. Normally the jump to the
6137 nearby location is conditional on the result of the add, but by
6138 using the "true" condition we can make the jump unconditional.
6139 Thus addb can perform two independent operations in one insn.
6141 * movb is similar to addb in that it can perform a reg->reg
6142 or small immediate->reg copy and jump to a nearby (+-8k location).
6144 * fmpyadd and fmpysub can perform a FP multiply and either an
6145 FP add or FP sub if the operands of the multiply and add/sub are
6146 independent (there are other minor restrictions). Note both
6147 the fmpy and fadd/fsub can in theory move to better spots according
6148 to data dependencies, but for now we require the fmpy stay at a
6151 * Many of the memory operations can perform pre & post updates
6152 of index registers. GCC's pre/post increment/decrement addressing
6153 is far too simple to take advantage of all the possibilities. This
6154 pass may not be suitable since those insns may not be independent.
6156 * comclr can compare two ints or an int and a register, nullify
6157 the following instruction and zero some other register. This
6158 is more difficult to use as it's harder to find an insn which
6159 will generate a comclr than finding something like an unconditional
6160 branch. (conditional moves & long branches create comclr insns).
6162 * Most arithmetic operations can conditionally skip the next
6163 instruction. They can be viewed as "perform this operation
6164 and conditionally jump to this nearby location" (where nearby
6165 is an insns away). These are difficult to use due to the
6166 branch length restrictions. */
6169 pa_combine_instructions (insns)
6170 rtx insns ATTRIBUTE_UNUSED;
6174 /* This can get expensive since the basic algorithm is on the
6175 order of O(n^2) (or worse). Only do it for -O2 or higher
6176 levels of optimization. */
6180 /* Walk down the list of insns looking for "anchor" insns which
6181 may be combined with "floating" insns. As the name implies,
6182 "anchor" instructions don't move, while "floating" insns may
6184 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
6185 new = make_insn_raw (new);
6187 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
6189 enum attr_pa_combine_type anchor_attr;
6190 enum attr_pa_combine_type floater_attr;
6192 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
6193 Also ignore any special USE insns. */
6194 if ((GET_CODE (anchor) != INSN
6195 && GET_CODE (anchor) != JUMP_INSN
6196 && GET_CODE (anchor) != CALL_INSN)
6197 || GET_CODE (PATTERN (anchor)) == USE
6198 || GET_CODE (PATTERN (anchor)) == CLOBBER
6199 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
6200 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
6203 anchor_attr = get_attr_pa_combine_type (anchor);
6204 /* See if anchor is an insn suitable for combination. */
6205 if (anchor_attr == PA_COMBINE_TYPE_FMPY
6206 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
6207 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6208 && ! forward_branch_p (anchor)))
6212 for (floater = PREV_INSN (anchor);
6214 floater = PREV_INSN (floater))
6216 if (GET_CODE (floater) == NOTE
6217 || (GET_CODE (floater) == INSN
6218 && (GET_CODE (PATTERN (floater)) == USE
6219 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6222 /* Anything except a regular INSN will stop our search. */
6223 if (GET_CODE (floater) != INSN
6224 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6225 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6231 /* See if FLOATER is suitable for combination with the
6233 floater_attr = get_attr_pa_combine_type (floater);
6234 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6235 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6236 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6237 && floater_attr == PA_COMBINE_TYPE_FMPY))
6239 /* If ANCHOR and FLOATER can be combined, then we're
6240 done with this pass. */
6241 if (pa_can_combine_p (new, anchor, floater, 0,
6242 SET_DEST (PATTERN (floater)),
6243 XEXP (SET_SRC (PATTERN (floater)), 0),
6244 XEXP (SET_SRC (PATTERN (floater)), 1)))
6248 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
6249 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
6251 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
6253 if (pa_can_combine_p (new, anchor, floater, 0,
6254 SET_DEST (PATTERN (floater)),
6255 XEXP (SET_SRC (PATTERN (floater)), 0),
6256 XEXP (SET_SRC (PATTERN (floater)), 1)))
6261 if (pa_can_combine_p (new, anchor, floater, 0,
6262 SET_DEST (PATTERN (floater)),
6263 SET_SRC (PATTERN (floater)),
6264 SET_SRC (PATTERN (floater))))
6270 /* If we didn't find anything on the backwards scan try forwards. */
6272 && (anchor_attr == PA_COMBINE_TYPE_FMPY
6273 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
6275 for (floater = anchor; floater; floater = NEXT_INSN (floater))
6277 if (GET_CODE (floater) == NOTE
6278 || (GET_CODE (floater) == INSN
6279 && (GET_CODE (PATTERN (floater)) == USE
6280 || GET_CODE (PATTERN (floater)) == CLOBBER)))
6284 /* Anything except a regular INSN will stop our search. */
6285 if (GET_CODE (floater) != INSN
6286 || GET_CODE (PATTERN (floater)) == ADDR_VEC
6287 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
6293 /* See if FLOATER is suitable for combination with the
6295 floater_attr = get_attr_pa_combine_type (floater);
6296 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
6297 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
6298 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6299 && floater_attr == PA_COMBINE_TYPE_FMPY))
6301 /* If ANCHOR and FLOATER can be combined, then we're
6302 done with this pass. */
6303 if (pa_can_combine_p (new, anchor, floater, 1,
6304 SET_DEST (PATTERN (floater)),
6305 XEXP (SET_SRC (PATTERN(floater)),0),
6306 XEXP(SET_SRC(PATTERN(floater)),1)))
6312 /* FLOATER will be nonzero if we found a suitable floating
6313 insn for combination with ANCHOR. */
6315 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
6316 || anchor_attr == PA_COMBINE_TYPE_FMPY))
6318 /* Emit the new instruction and delete the old anchor. */
6319 emit_insn_before (gen_rtx_PARALLEL (VOIDmode,
6322 PATTERN (floater))),
6324 PUT_CODE (anchor, NOTE);
6325 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6326 NOTE_SOURCE_FILE (anchor) = 0;
6328 /* Emit a special USE insn for FLOATER, then delete
6329 the floating insn. */
6330 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6331 delete_insn (floater);
6336 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
6339 /* Emit the new_jump instruction and delete the old anchor. */
6340 temp = emit_jump_insn_before (gen_rtx_PARALLEL (VOIDmode,
6341 gen_rtvec (2, PATTERN (anchor),
6342 PATTERN (floater))),
6344 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
6345 PUT_CODE (anchor, NOTE);
6346 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
6347 NOTE_SOURCE_FILE (anchor) = 0;
6349 /* Emit a special USE insn for FLOATER, then delete
6350 the floating insn. */
6351 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
6352 delete_insn (floater);
6360 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
6361 rtx new, anchor, floater;
6363 rtx dest, src1, src2;
6365 int insn_code_number;
6368 /* Create a PARALLEL with the patterns of ANCHOR and
6369 FLOATER, try to recognize it, then test constraints
6370 for the resulting pattern.
6372 If the pattern doesn't match or the constraints
6373 aren't met keep searching for a suitable floater
6375 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
6376 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
6377 INSN_CODE (new) = -1;
6378 insn_code_number = recog_memoized (new);
6379 if (insn_code_number < 0
6380 || !constrain_operands (insn_code_number, 1))
6394 /* There's up to three operands to consider. One
6395 output and two inputs.
6397 The output must not be used between FLOATER & ANCHOR
6398 exclusive. The inputs must not be set between
6399 FLOATER and ANCHOR exclusive. */
6401 if (reg_used_between_p (dest, start, end))
6404 if (reg_set_between_p (src1, start, end))
6407 if (reg_set_between_p (src2, start, end))
6410 /* If we get here, then everything is good. */
6414 /* Return nonzero if sets and references for INSN are delayed.
6416 Millicode insns are actually function calls with some special
6417 constraints on arguments and register usage.
6419 Millicode calls always expect their arguments in the integer argument
6420 registers, and always return their result in %r29 (ret1). They
6421 are expected to clobber their arguments, %r1, %r29, and %r31 and
6424 By considering this effects delayed reorg reorg can put insns
6425 which set the argument registers into the delay slot of the millicode
6426 call -- thus they act more like traditional CALL_INSNs.
6428 get_attr_type will try to recognize the given insn, so make sure to
6429 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
6432 insn_sets_and_refs_are_delayed (insn)
6435 return ((GET_CODE (insn) == INSN
6436 && GET_CODE (PATTERN (insn)) != SEQUENCE
6437 && GET_CODE (PATTERN (insn)) != USE
6438 && GET_CODE (PATTERN (insn)) != CLOBBER
6439 && get_attr_type (insn) == TYPE_MILLI));