1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "diagnostic-core.h"
43 #include "tm-constrs.h"
45 #include "target-def.h"
51 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
52 names are not prefixed by underscores, to tell whether to prefix a
53 label with a plus sign or not, so that the assembler can tell
54 symbol names from register names. */
55 int mn10300_protect_label;
57 /* Selected processor type for tuning. */
58 enum processor_type mn10300_tune_cpu = PROCESSOR_DEFAULT;
65 static int cc_flags_for_mode(enum machine_mode);
66 static int cc_flags_for_code(enum rtx_code);
68 /* Implement TARGET_OPTION_OVERRIDE. */
71 mn10300_option_override (void)
74 target_flags &= ~MASK_MULT_BUG;
77 /* Disable scheduling for the MN10300 as we do
78 not have timing information available for it. */
79 flag_schedule_insns = 0;
80 flag_schedule_insns_after_reload = 0;
82 /* Force enable splitting of wide types, as otherwise it is trivial
83 to run out of registers. Indeed, this works so well that register
84 allocation problems are now more common *without* optimization,
85 when this flag is not enabled by default. */
86 flag_split_wide_types = 1;
89 if (mn10300_tune_string)
91 if (strcasecmp (mn10300_tune_string, "mn10300") == 0)
92 mn10300_tune_cpu = PROCESSOR_MN10300;
93 else if (strcasecmp (mn10300_tune_string, "am33") == 0)
94 mn10300_tune_cpu = PROCESSOR_AM33;
95 else if (strcasecmp (mn10300_tune_string, "am33-2") == 0)
96 mn10300_tune_cpu = PROCESSOR_AM33_2;
97 else if (strcasecmp (mn10300_tune_string, "am34") == 0)
98 mn10300_tune_cpu = PROCESSOR_AM34;
100 error ("-mtune= expects mn10300, am33, am33-2, or am34");
105 mn10300_file_start (void)
107 default_file_start ();
110 fprintf (asm_out_file, "\t.am33_2\n");
111 else if (TARGET_AM33)
112 fprintf (asm_out_file, "\t.am33\n");
115 /* Note: This list must match the liw_op attribute in mn10300.md. */
117 static const char *liw_op_names[] =
119 "add", "cmp", "sub", "mov",
125 /* Print operand X using operand code CODE to assembly language output file
129 mn10300_print_operand (FILE *file, rtx x, int code)
135 unsigned int liw_op = UINTVAL (x);
137 gcc_assert (TARGET_ALLOW_LIW);
138 gcc_assert (liw_op < LIW_OP_MAX);
139 fputs (liw_op_names[liw_op], file);
146 enum rtx_code cmp = GET_CODE (x);
147 enum machine_mode mode = GET_MODE (XEXP (x, 0));
152 cmp = reverse_condition (cmp);
153 have_flags = cc_flags_for_mode (mode);
164 /* bge is smaller than bnc. */
165 str = (have_flags & CC_FLAG_V ? "ge" : "nc");
168 str = (have_flags & CC_FLAG_V ? "lt" : "ns");
216 gcc_checking_assert ((cc_flags_for_code (cmp) & ~have_flags) == 0);
222 /* This is used for the operand to a call instruction;
223 if it's a REG, enclose it in parens, else output
224 the operand normally. */
228 mn10300_print_operand (file, x, 0);
232 mn10300_print_operand (file, x, 0);
236 switch (GET_CODE (x))
240 output_address (XEXP (x, 0));
245 fprintf (file, "fd%d", REGNO (x) - 18);
253 /* These are the least significant word in a 64bit value. */
255 switch (GET_CODE (x))
259 output_address (XEXP (x, 0));
264 fprintf (file, "%s", reg_names[REGNO (x)]);
268 fprintf (file, "%s", reg_names[subreg_regno (x)]);
276 switch (GET_MODE (x))
279 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
280 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
281 fprintf (file, "0x%lx", val[0]);
284 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
285 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
286 fprintf (file, "0x%lx", val[0]);
290 mn10300_print_operand_address (file,
291 GEN_INT (CONST_DOUBLE_LOW (x)));
302 split_double (x, &low, &high);
303 fprintf (file, "%ld", (long)INTVAL (low));
312 /* Similarly, but for the most significant word. */
314 switch (GET_CODE (x))
318 x = adjust_address (x, SImode, 4);
319 output_address (XEXP (x, 0));
324 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
328 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
336 switch (GET_MODE (x))
339 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
340 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
341 fprintf (file, "0x%lx", val[1]);
347 mn10300_print_operand_address (file,
348 GEN_INT (CONST_DOUBLE_HIGH (x)));
359 split_double (x, &low, &high);
360 fprintf (file, "%ld", (long)INTVAL (high));
371 if (REG_P (XEXP (x, 0)))
372 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx));
374 output_address (XEXP (x, 0));
379 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
380 fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
384 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
385 fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
388 /* For shift counts. The hardware ignores the upper bits of
389 any immediate, but the assembler will flag an out of range
390 shift count as an error. So we mask off the high bits
391 of the immediate here. */
395 fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
401 switch (GET_CODE (x))
405 output_address (XEXP (x, 0));
414 fprintf (file, "%s", reg_names[REGNO (x)]);
418 fprintf (file, "%s", reg_names[subreg_regno (x)]);
421 /* This will only be single precision.... */
427 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
428 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
429 fprintf (file, "0x%lx", val);
439 mn10300_print_operand_address (file, x);
448 /* Output assembly language output for the address ADDR to FILE. */
451 mn10300_print_operand_address (FILE *file, rtx addr)
453 switch (GET_CODE (addr))
456 mn10300_print_operand (file, XEXP (addr, 0), 0);
461 mn10300_print_operand (file, XEXP (addr, 0), 0);
464 mn10300_print_operand (file, XEXP (addr, 1), 0);
468 mn10300_print_operand (file, addr, 0);
472 rtx base = XEXP (addr, 0);
473 rtx index = XEXP (addr, 1);
475 if (REG_P (index) && !REG_OK_FOR_INDEX_P (index))
481 gcc_assert (REG_P (index) && REG_OK_FOR_INDEX_P (index));
483 gcc_assert (REG_OK_FOR_BASE_P (base));
485 mn10300_print_operand (file, index, 0);
487 mn10300_print_operand (file, base, 0);
491 output_addr_const (file, addr);
494 output_addr_const (file, addr);
499 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA.
501 Used for PIC-specific UNSPECs. */
504 mn10300_asm_output_addr_const_extra (FILE *file, rtx x)
506 if (GET_CODE (x) == UNSPEC)
511 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
512 output_addr_const (file, XVECEXP (x, 0, 0));
515 output_addr_const (file, XVECEXP (x, 0, 0));
516 fputs ("@GOT", file);
519 output_addr_const (file, XVECEXP (x, 0, 0));
520 fputs ("@GOTOFF", file);
523 output_addr_const (file, XVECEXP (x, 0, 0));
524 fputs ("@PLT", file);
526 case UNSPEC_GOTSYM_OFF:
527 assemble_name (file, GOT_SYMBOL_NAME);
529 output_addr_const (file, XVECEXP (x, 0, 0));
541 /* Count the number of FP registers that have to be saved. */
543 fp_regs_to_save (void)
550 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
551 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
557 /* Print a set of registers in the format required by "movm" and "ret".
558 Register K is saved if bit K of MASK is set. The data and address
559 registers can be stored individually, but the extended registers cannot.
560 We assume that the mask already takes that into account. For instance,
561 bits 14 to 17 must have the same value. */
564 mn10300_print_reg_list (FILE *file, int mask)
572 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
573 if ((mask & (1 << i)) != 0)
577 fputs (reg_names [i], file);
581 if ((mask & 0x3c000) != 0)
583 gcc_assert ((mask & 0x3c000) == 0x3c000);
586 fputs ("exreg1", file);
593 /* If the MDR register is never clobbered, we can use the RETF instruction
594 which takes the address from the MDR register. This is 3 cycles faster
595 than having to load the address from the stack. */
598 mn10300_can_use_retf_insn (void)
600 /* Don't bother if we're not optimizing. In this case we won't
601 have proper access to df_regs_ever_live_p. */
605 /* EH returns alter the saved return address; MDR is not current. */
606 if (crtl->calls_eh_return)
609 /* Obviously not if MDR is ever clobbered. */
610 if (df_regs_ever_live_p (MDR_REG))
613 /* ??? Careful not to use this during expand_epilogue etc. */
614 gcc_assert (!in_sequence_p ());
615 return leaf_function_p ();
619 mn10300_can_use_rets_insn (void)
621 return !mn10300_initial_offset (ARG_POINTER_REGNUM, STACK_POINTER_REGNUM);
624 /* Returns the set of live, callee-saved registers as a bitmask. The
625 callee-saved extended registers cannot be stored individually, so
626 Also returns the number of bytes in the registers in the mask if
627 BYTES_SAVED is not NULL. */
630 mn10300_get_live_callee_saved_regs (unsigned int * bytes_saved)
637 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
638 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
644 if ((mask & 0x3c000) != 0)
646 for (i = 0x04000; i < 0x40000; i <<= 1)
654 * bytes_saved = count * UNITS_PER_WORD;
662 RTX_FRAME_RELATED_P (r) = 1;
666 /* Generate an instruction that pushes several registers onto the stack.
667 Register K will be saved if bit K in MASK is set. The function does
668 nothing if MASK is zero.
670 To be compatible with the "movm" instruction, the lowest-numbered
671 register must be stored in the lowest slot. If MASK is the set
672 { R1,...,RN }, where R1...RN are ordered least first, the generated
673 instruction will have the form:
676 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
677 (set (mem:SI (plus:SI (reg:SI 9)
681 (set (mem:SI (plus:SI (reg:SI 9)
686 mn10300_gen_multiple_store (unsigned int mask)
688 /* The order in which registers are stored, from SP-4 through SP-N*4. */
689 static const unsigned int store_order[8] = {
690 /* e2, e3: never saved */
691 FIRST_EXTENDED_REGNUM + 4,
692 FIRST_EXTENDED_REGNUM + 5,
693 FIRST_EXTENDED_REGNUM + 6,
694 FIRST_EXTENDED_REGNUM + 7,
695 /* e0, e1, mdrq, mcrh, mcrl, mcvf: never saved. */
696 FIRST_DATA_REGNUM + 2,
697 FIRST_DATA_REGNUM + 3,
698 FIRST_ADDRESS_REGNUM + 2,
699 FIRST_ADDRESS_REGNUM + 3,
700 /* d0, d1, a0, a1, mdr, lir, lar: never saved. */
710 for (i = count = 0; i < ARRAY_SIZE(store_order); ++i)
712 unsigned regno = store_order[i];
714 if (((mask >> regno) & 1) == 0)
718 x = plus_constant (Pmode, stack_pointer_rtx, count * -4);
719 x = gen_frame_mem (SImode, x);
720 x = gen_rtx_SET (VOIDmode, x, gen_rtx_REG (SImode, regno));
723 /* Remove the register from the mask so that... */
724 mask &= ~(1u << regno);
727 /* ... we can make sure that we didn't try to use a register
728 not listed in the store order. */
729 gcc_assert (mask == 0);
731 /* Create the instruction that updates the stack pointer. */
732 x = plus_constant (Pmode, stack_pointer_rtx, count * -4);
733 x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x);
736 /* We need one PARALLEL element to update the stack pointer and
737 an additional element for each register that is stored. */
738 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (count + 1, elts));
743 mn10300_expand_prologue (void)
745 HOST_WIDE_INT size = mn10300_frame_size ();
747 if (flag_stack_usage_info)
748 current_function_static_stack_size = size;
750 /* If we use any of the callee-saved registers, save them now. */
751 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs (NULL));
753 if (TARGET_AM33_2 && fp_regs_to_save ())
755 int num_regs_to_save = fp_regs_to_save (), i;
761 save_sp_partial_merge,
765 unsigned int strategy_size = (unsigned)-1, this_strategy_size;
768 /* We have several different strategies to save FP registers.
769 We can store them using SP offsets, which is beneficial if
770 there are just a few registers to save, or we can use `a0' in
771 post-increment mode (`a0' is the only call-clobbered address
772 register that is never used to pass information to a
773 function). Furthermore, if we don't need a frame pointer, we
774 can merge the two SP adds into a single one, but this isn't
775 always beneficial; sometimes we can just split the two adds
776 so that we don't exceed a 16-bit constant size. The code
777 below will select which strategy to use, so as to generate
778 smallest code. Ties are broken in favor or shorter sequences
779 (in terms of number of instructions). */
781 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
782 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
783 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
784 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
786 /* We add 0 * (S) in two places to promote to the type of S,
787 so that all arms of the conditional have the same type. */
788 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
789 (((S) >= (L)) ? 0 * (S) + (SIZE1) * (N) \
790 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
791 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
793 #define SIZE_FMOV_SP_(S,N) \
794 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
795 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
796 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
797 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
799 /* Consider alternative save_sp_merge only if we don't need the
800 frame pointer and size is nonzero. */
801 if (! frame_pointer_needed && size)
803 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
804 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
805 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
806 this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
808 if (this_strategy_size < strategy_size)
810 strategy = save_sp_merge;
811 strategy_size = this_strategy_size;
815 /* Consider alternative save_sp_no_merge unconditionally. */
816 /* Insn: add -4 * num_regs_to_save, sp. */
817 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
818 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
819 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
822 /* Insn: add -size, sp. */
823 this_strategy_size += SIZE_ADD_SP (-size);
826 if (this_strategy_size < strategy_size)
828 strategy = save_sp_no_merge;
829 strategy_size = this_strategy_size;
832 /* Consider alternative save_sp_partial_merge only if we don't
833 need a frame pointer and size is reasonably large. */
834 if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
836 /* Insn: add -128, sp. */
837 this_strategy_size = SIZE_ADD_SP (-128);
838 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
839 this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
843 /* Insn: add 128-size, sp. */
844 this_strategy_size += SIZE_ADD_SP (128 - size);
847 if (this_strategy_size < strategy_size)
849 strategy = save_sp_partial_merge;
850 strategy_size = this_strategy_size;
854 /* Consider alternative save_a0_merge only if we don't need a
855 frame pointer, size is nonzero and the user hasn't
856 changed the calling conventions of a0. */
857 if (! frame_pointer_needed && size
858 && call_really_used_regs [FIRST_ADDRESS_REGNUM]
859 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
861 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
862 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
863 /* Insn: mov sp, a0. */
864 this_strategy_size++;
867 /* Insn: add size, a0. */
868 this_strategy_size += SIZE_ADD_AX (size);
870 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
871 this_strategy_size += 3 * num_regs_to_save;
873 if (this_strategy_size < strategy_size)
875 strategy = save_a0_merge;
876 strategy_size = this_strategy_size;
880 /* Consider alternative save_a0_no_merge if the user hasn't
881 changed the calling conventions of a0. */
882 if (call_really_used_regs [FIRST_ADDRESS_REGNUM]
883 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
885 /* Insn: add -4 * num_regs_to_save, sp. */
886 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
887 /* Insn: mov sp, a0. */
888 this_strategy_size++;
889 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
890 this_strategy_size += 3 * num_regs_to_save;
893 /* Insn: add -size, sp. */
894 this_strategy_size += SIZE_ADD_SP (-size);
897 if (this_strategy_size < strategy_size)
899 strategy = save_a0_no_merge;
900 strategy_size = this_strategy_size;
904 /* Emit the initial SP add, common to all strategies. */
907 case save_sp_no_merge:
908 case save_a0_no_merge:
909 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
911 GEN_INT (-4 * num_regs_to_save))));
915 case save_sp_partial_merge:
916 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
919 xsize = 128 - 4 * num_regs_to_save;
925 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
927 GEN_INT (-(size + 4 * num_regs_to_save)))));
928 /* We'll have to adjust FP register saves according to the
931 /* Since we've already created the stack frame, don't do it
932 again at the end of the function. */
940 /* Now prepare register a0, if we have decided to use it. */
944 case save_sp_no_merge:
945 case save_sp_partial_merge:
950 case save_a0_no_merge:
951 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
952 F (emit_insn (gen_movsi (reg, stack_pointer_rtx)));
954 F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))));
955 reg = gen_rtx_POST_INC (SImode, reg);
962 /* Now actually save the FP registers. */
963 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
964 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
972 /* If we aren't using `a0', use an SP offset. */
975 addr = gen_rtx_PLUS (SImode,
980 addr = stack_pointer_rtx;
985 F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr),
986 gen_rtx_REG (SFmode, i))));
990 /* Now put the frame pointer into the frame pointer register. */
991 if (frame_pointer_needed)
992 F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx));
994 /* Allocate stack for this frame. */
996 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
1000 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
1001 emit_insn (gen_load_pic ());
1005 mn10300_expand_epilogue (void)
1007 HOST_WIDE_INT size = mn10300_frame_size ();
1008 unsigned int reg_save_bytes;
1010 mn10300_get_live_callee_saved_regs (& reg_save_bytes);
1012 if (TARGET_AM33_2 && fp_regs_to_save ())
1014 int num_regs_to_save = fp_regs_to_save (), i;
1017 /* We have several options to restore FP registers. We could
1018 load them from SP offsets, but, if there are enough FP
1019 registers to restore, we win if we use a post-increment
1022 /* If we have a frame pointer, it's the best option, because we
1023 already know it has the value we want. */
1024 if (frame_pointer_needed)
1025 reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
1026 /* Otherwise, we may use `a1', since it's call-clobbered and
1027 it's never used for return values. But only do so if it's
1028 smaller than using SP offsets. */
1031 enum { restore_sp_post_adjust,
1032 restore_sp_pre_adjust,
1033 restore_sp_partial_adjust,
1034 restore_a1 } strategy;
1035 unsigned int this_strategy_size, strategy_size = (unsigned)-1;
1037 /* Consider using sp offsets before adjusting sp. */
1038 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1039 this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
1040 /* If size is too large, we'll have to adjust SP with an
1042 if (size + 4 * num_regs_to_save + reg_save_bytes > 255)
1044 /* Insn: add size + 4 * num_regs_to_save, sp. */
1045 this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
1047 /* If we don't have to restore any non-FP registers,
1048 we'll be able to save one byte by using rets. */
1049 if (! reg_save_bytes)
1050 this_strategy_size--;
1052 if (this_strategy_size < strategy_size)
1054 strategy = restore_sp_post_adjust;
1055 strategy_size = this_strategy_size;
1058 /* Consider using sp offsets after adjusting sp. */
1059 /* Insn: add size, sp. */
1060 this_strategy_size = SIZE_ADD_SP (size);
1061 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1062 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
1063 /* We're going to use ret to release the FP registers
1064 save area, so, no savings. */
1066 if (this_strategy_size < strategy_size)
1068 strategy = restore_sp_pre_adjust;
1069 strategy_size = this_strategy_size;
1072 /* Consider using sp offsets after partially adjusting sp.
1073 When size is close to 32Kb, we may be able to adjust SP
1074 with an imm16 add instruction while still using fmov
1076 if (size + 4 * num_regs_to_save + reg_save_bytes > 255)
1078 /* Insn: add size + 4 * num_regs_to_save
1079 + reg_save_bytes - 252,sp. */
1080 this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
1081 + reg_save_bytes - 252);
1082 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
1083 this_strategy_size += SIZE_FMOV_SP (252 - reg_save_bytes
1084 - 4 * num_regs_to_save,
1086 /* We're going to use ret to release the FP registers
1087 save area, so, no savings. */
1089 if (this_strategy_size < strategy_size)
1091 strategy = restore_sp_partial_adjust;
1092 strategy_size = this_strategy_size;
1096 /* Consider using a1 in post-increment mode, as long as the
1097 user hasn't changed the calling conventions of a1. */
1098 if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1]
1099 && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
1101 /* Insn: mov sp,a1. */
1102 this_strategy_size = 1;
1105 /* Insn: add size,a1. */
1106 this_strategy_size += SIZE_ADD_AX (size);
1108 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1109 this_strategy_size += 3 * num_regs_to_save;
1110 /* If size is large enough, we may be able to save a
1112 if (size + 4 * num_regs_to_save + reg_save_bytes > 255)
1114 /* Insn: mov a1,sp. */
1115 this_strategy_size += 2;
1117 /* If we don't have to restore any non-FP registers,
1118 we'll be able to save one byte by using rets. */
1119 if (! reg_save_bytes)
1120 this_strategy_size--;
1122 if (this_strategy_size < strategy_size)
1124 strategy = restore_a1;
1125 strategy_size = this_strategy_size;
1131 case restore_sp_post_adjust:
1134 case restore_sp_pre_adjust:
1135 emit_insn (gen_addsi3 (stack_pointer_rtx,
1141 case restore_sp_partial_adjust:
1142 emit_insn (gen_addsi3 (stack_pointer_rtx,
1144 GEN_INT (size + 4 * num_regs_to_save
1145 + reg_save_bytes - 252)));
1146 size = 252 - reg_save_bytes - 4 * num_regs_to_save;
1150 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
1151 emit_insn (gen_movsi (reg, stack_pointer_rtx));
1153 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
1161 /* Adjust the selected register, if any, for post-increment. */
1163 reg = gen_rtx_POST_INC (SImode, reg);
1165 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
1166 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
1174 /* If we aren't using a post-increment register, use an
1176 addr = gen_rtx_PLUS (SImode,
1181 addr = stack_pointer_rtx;
1185 emit_insn (gen_movsf (gen_rtx_REG (SFmode, i),
1186 gen_rtx_MEM (SFmode, addr)));
1189 /* If we were using the restore_a1 strategy and the number of
1190 bytes to be released won't fit in the `ret' byte, copy `a1'
1191 to `sp', to avoid having to use `add' to adjust it. */
1192 if (! frame_pointer_needed && reg && size + reg_save_bytes > 255)
1194 emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
1199 /* Maybe cut back the stack, except for the register save area.
1201 If the frame pointer exists, then use the frame pointer to
1204 If the stack size + register save area is more than 255 bytes,
1205 then the stack must be cut back here since the size + register
1206 save size is too big for a ret/retf instruction.
1208 Else leave it alone, it will be cut back as part of the
1209 ret/retf instruction, or there wasn't any stack to begin with.
1211 Under no circumstances should the register save area be
1212 deallocated here, that would leave a window where an interrupt
1213 could occur and trash the register save area. */
1214 if (frame_pointer_needed)
1216 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1219 else if (size + reg_save_bytes > 255)
1221 emit_insn (gen_addsi3 (stack_pointer_rtx,
1227 /* Adjust the stack and restore callee-saved registers, if any. */
1228 if (mn10300_can_use_rets_insn ())
1229 emit_jump_insn (ret_rtx);
1231 emit_jump_insn (gen_return_ret (GEN_INT (size + reg_save_bytes)));
1234 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1235 This function is for MATCH_PARALLEL and so assumes OP is known to be
1236 parallel. If OP is a multiple store, return a mask indicating which
1237 registers it saves. Return 0 otherwise. */
1240 mn10300_store_multiple_operation (rtx op,
1241 enum machine_mode mode ATTRIBUTE_UNUSED)
1249 count = XVECLEN (op, 0);
1253 /* Check that first instruction has the form (set (sp) (plus A B)) */
1254 elt = XVECEXP (op, 0, 0);
1255 if (GET_CODE (elt) != SET
1256 || (! REG_P (SET_DEST (elt)))
1257 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
1258 || GET_CODE (SET_SRC (elt)) != PLUS)
1261 /* Check that A is the stack pointer and B is the expected stack size.
1262 For OP to match, each subsequent instruction should push a word onto
1263 the stack. We therefore expect the first instruction to create
1264 COUNT-1 stack slots. */
1265 elt = SET_SRC (elt);
1266 if ((! REG_P (XEXP (elt, 0)))
1267 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1268 || (! CONST_INT_P (XEXP (elt, 1)))
1269 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
1273 for (i = 1; i < count; i++)
1275 /* Check that element i is a (set (mem M) R). */
1276 /* ??? Validate the register order a-la mn10300_gen_multiple_store.
1277 Remember: the ordering is *not* monotonic. */
1278 elt = XVECEXP (op, 0, i);
1279 if (GET_CODE (elt) != SET
1280 || (! MEM_P (SET_DEST (elt)))
1281 || (! REG_P (SET_SRC (elt))))
1284 /* Remember which registers are to be saved. */
1285 last = REGNO (SET_SRC (elt));
1286 mask |= (1 << last);
1288 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1289 elt = XEXP (SET_DEST (elt), 0);
1290 if (GET_CODE (elt) != PLUS
1291 || (! REG_P (XEXP (elt, 0)))
1292 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1293 || (! CONST_INT_P (XEXP (elt, 1)))
1294 || INTVAL (XEXP (elt, 1)) != -i * 4)
1298 /* All or none of the callee-saved extended registers must be in the set. */
1299 if ((mask & 0x3c000) != 0
1300 && (mask & 0x3c000) != 0x3c000)
1306 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
1309 mn10300_preferred_reload_class (rtx x, reg_class_t rclass)
1311 if (x == stack_pointer_rtx && rclass != SP_REGS)
1312 return (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
1315 && !HARD_REGISTER_P (x))
1316 || (GET_CODE (x) == SUBREG
1317 && REG_P (SUBREG_REG (x))
1318 && !HARD_REGISTER_P (SUBREG_REG (x))))
1319 return LIMIT_RELOAD_CLASS (GET_MODE (x), rclass);
1324 /* Implement TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
1327 mn10300_preferred_output_reload_class (rtx x, reg_class_t rclass)
1329 if (x == stack_pointer_rtx && rclass != SP_REGS)
1330 return (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
1334 /* Implement TARGET_SECONDARY_RELOAD. */
1337 mn10300_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
1338 enum machine_mode mode, secondary_reload_info *sri)
1340 enum reg_class rclass = (enum reg_class) rclass_i;
1341 enum reg_class xclass = NO_REGS;
1342 unsigned int xregno = INVALID_REGNUM;
1347 if (xregno >= FIRST_PSEUDO_REGISTER)
1348 xregno = true_regnum (x);
1349 if (xregno != INVALID_REGNUM)
1350 xclass = REGNO_REG_CLASS (xregno);
1355 /* Memory load/stores less than a full word wide can't have an
1356 address or stack pointer destination. They must use a data
1357 register as an intermediate register. */
1358 if (rclass != DATA_REGS
1359 && (mode == QImode || mode == HImode)
1360 && xclass == NO_REGS)
1363 /* We can only move SP to/from an address register. */
1365 && rclass == SP_REGS
1366 && xclass != ADDRESS_REGS)
1367 return ADDRESS_REGS;
1369 && xclass == SP_REGS
1370 && rclass != ADDRESS_REGS
1371 && rclass != SP_OR_ADDRESS_REGS)
1372 return ADDRESS_REGS;
1375 /* We can't directly load sp + const_int into a register;
1376 we must use an address register as an scratch. */
1378 && rclass != SP_REGS
1379 && rclass != SP_OR_ADDRESS_REGS
1380 && rclass != SP_OR_GENERAL_REGS
1381 && GET_CODE (x) == PLUS
1382 && (XEXP (x, 0) == stack_pointer_rtx
1383 || XEXP (x, 1) == stack_pointer_rtx))
1385 sri->icode = CODE_FOR_reload_plus_sp_const;
1389 /* We can only move MDR to/from a data register. */
1390 if (rclass == MDR_REGS && xclass != DATA_REGS)
1392 if (xclass == MDR_REGS && rclass != DATA_REGS)
1395 /* We can't load/store an FP register from a constant address. */
1397 && (rclass == FP_REGS || xclass == FP_REGS)
1398 && (xclass == NO_REGS || rclass == NO_REGS))
1402 if (xregno >= FIRST_PSEUDO_REGISTER && xregno != INVALID_REGNUM)
1404 addr = reg_equiv_mem (xregno);
1406 addr = XEXP (addr, 0);
1411 if (addr && CONSTANT_ADDRESS_P (addr))
1412 return GENERAL_REGS;
1415 /* Otherwise assume no secondary reloads are needed. */
1420 mn10300_frame_size (void)
1422 /* size includes the fixed stack space needed for function calls. */
1423 int size = get_frame_size () + crtl->outgoing_args_size;
1425 /* And space for the return pointer. */
1426 size += crtl->outgoing_args_size ? 4 : 0;
1432 mn10300_initial_offset (int from, int to)
1436 gcc_assert (from == ARG_POINTER_REGNUM || from == FRAME_POINTER_REGNUM);
1437 gcc_assert (to == FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
1439 if (to == STACK_POINTER_REGNUM)
1440 diff = mn10300_frame_size ();
1442 /* The difference between the argument pointer and the frame pointer
1443 is the size of the callee register save area. */
1444 if (from == ARG_POINTER_REGNUM)
1446 unsigned int reg_save_bytes;
1448 mn10300_get_live_callee_saved_regs (& reg_save_bytes);
1449 diff += reg_save_bytes;
1450 diff += 4 * fp_regs_to_save ();
1456 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1459 mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1461 /* Return values > 8 bytes in length in memory. */
1462 return (int_size_in_bytes (type) > 8
1463 || int_size_in_bytes (type) == 0
1464 || TYPE_MODE (type) == BLKmode);
1467 /* Flush the argument registers to the stack for a stdarg function;
1468 return the new argument pointer. */
1470 mn10300_builtin_saveregs (void)
1473 tree fntype = TREE_TYPE (current_function_decl);
1474 int argadj = ((!stdarg_p (fntype))
1475 ? UNITS_PER_WORD : 0);
1476 alias_set_type set = get_varargs_alias_set ();
1479 offset = plus_constant (Pmode, crtl->args.arg_offset_rtx, argadj);
1481 offset = crtl->args.arg_offset_rtx;
1483 mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer);
1484 set_mem_alias_set (mem, set);
1485 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
1487 mem = gen_rtx_MEM (SImode,
1488 plus_constant (Pmode,
1489 crtl->args.internal_arg_pointer, 4));
1490 set_mem_alias_set (mem, set);
1491 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
1493 return copy_to_reg (expand_binop (Pmode, add_optab,
1494 crtl->args.internal_arg_pointer,
1495 offset, 0, 0, OPTAB_LIB_WIDEN));
1499 mn10300_va_start (tree valist, rtx nextarg)
1501 nextarg = expand_builtin_saveregs ();
1502 std_expand_builtin_va_start (valist, nextarg);
1505 /* Return true when a parameter should be passed by reference. */
1508 mn10300_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
1509 enum machine_mode mode, const_tree type,
1510 bool named ATTRIBUTE_UNUSED)
1512 unsigned HOST_WIDE_INT size;
1515 size = int_size_in_bytes (type);
1517 size = GET_MODE_SIZE (mode);
1519 return (size > 8 || size == 0);
1522 /* Return an RTX to represent where a value with mode MODE will be returned
1523 from a function. If the result is NULL_RTX, the argument is pushed. */
1526 mn10300_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
1527 const_tree type, bool named ATTRIBUTE_UNUSED)
1529 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1530 rtx result = NULL_RTX;
1533 /* We only support using 2 data registers as argument registers. */
1536 /* Figure out the size of the object to be passed. */
1537 if (mode == BLKmode)
1538 size = int_size_in_bytes (type);
1540 size = GET_MODE_SIZE (mode);
1542 cum->nbytes = (cum->nbytes + 3) & ~3;
1544 /* Don't pass this arg via a register if all the argument registers
1546 if (cum->nbytes > nregs * UNITS_PER_WORD)
1549 /* Don't pass this arg via a register if it would be split between
1550 registers and memory. */
1551 if (type == NULL_TREE
1552 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1555 switch (cum->nbytes / UNITS_PER_WORD)
1558 result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM);
1561 result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1);
1570 /* Update the data in CUM to advance over an argument
1571 of mode MODE and data type TYPE.
1572 (TYPE is null for libcalls where that information may not be available.) */
1575 mn10300_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
1576 const_tree type, bool named ATTRIBUTE_UNUSED)
1578 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1580 cum->nbytes += (mode != BLKmode
1581 ? (GET_MODE_SIZE (mode) + 3) & ~3
1582 : (int_size_in_bytes (type) + 3) & ~3);
1585 /* Return the number of bytes of registers to use for an argument passed
1586 partially in registers and partially in memory. */
1589 mn10300_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
1590 tree type, bool named ATTRIBUTE_UNUSED)
1592 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1595 /* We only support using 2 data registers as argument registers. */
1598 /* Figure out the size of the object to be passed. */
1599 if (mode == BLKmode)
1600 size = int_size_in_bytes (type);
1602 size = GET_MODE_SIZE (mode);
1604 cum->nbytes = (cum->nbytes + 3) & ~3;
1606 /* Don't pass this arg via a register if all the argument registers
1608 if (cum->nbytes > nregs * UNITS_PER_WORD)
1611 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1614 /* Don't pass this arg via a register if it would be split between
1615 registers and memory. */
1616 if (type == NULL_TREE
1617 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1620 return nregs * UNITS_PER_WORD - cum->nbytes;
1623 /* Return the location of the function's value. This will be either
1624 $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
1625 $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that
1626 we only return the PARALLEL for outgoing values; we do not want
1627 callers relying on this extra copy. */
1630 mn10300_function_value (const_tree valtype,
1631 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1635 enum machine_mode mode = TYPE_MODE (valtype);
1637 if (! POINTER_TYPE_P (valtype))
1638 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1639 else if (! TARGET_PTR_A0D0 || ! outgoing
1640 || cfun->returns_struct)
1641 return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM);
1643 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
1645 = gen_rtx_EXPR_LIST (VOIDmode,
1646 gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM),
1650 = gen_rtx_EXPR_LIST (VOIDmode,
1651 gen_rtx_REG (mode, FIRST_DATA_REGNUM),
1656 /* Implements TARGET_LIBCALL_VALUE. */
1659 mn10300_libcall_value (enum machine_mode mode,
1660 const_rtx fun ATTRIBUTE_UNUSED)
1662 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1665 /* Implements FUNCTION_VALUE_REGNO_P. */
1668 mn10300_function_value_regno_p (const unsigned int regno)
1670 return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM);
1673 /* Output an addition operation. */
1676 mn10300_output_add (rtx operands[3], bool need_flags)
1678 rtx dest, src1, src2;
1679 unsigned int dest_regnum, src1_regnum, src2_regnum;
1680 enum reg_class src1_class, src2_class, dest_class;
1686 dest_regnum = true_regnum (dest);
1687 src1_regnum = true_regnum (src1);
1689 dest_class = REGNO_REG_CLASS (dest_regnum);
1690 src1_class = REGNO_REG_CLASS (src1_regnum);
1692 if (CONST_INT_P (src2))
1694 gcc_assert (dest_regnum == src1_regnum);
1696 if (src2 == const1_rtx && !need_flags)
1698 if (INTVAL (src2) == 4 && !need_flags && dest_class != DATA_REGS)
1701 gcc_assert (!need_flags || dest_class != SP_REGS);
1704 else if (CONSTANT_P (src2))
1707 src2_regnum = true_regnum (src2);
1708 src2_class = REGNO_REG_CLASS (src2_regnum);
1710 if (dest_regnum == src1_regnum)
1712 if (dest_regnum == src2_regnum)
1715 /* The rest of the cases are reg = reg+reg. For AM33, we can implement
1716 this directly, as below, but when optimizing for space we can sometimes
1717 do better by using a mov+add. For MN103, we claimed that we could
1718 implement a three-operand add because the various move and add insns
1719 change sizes across register classes, and we can often do better than
1720 reload in choosing which operand to move. */
1721 if (TARGET_AM33 && optimize_insn_for_speed_p ())
1722 return "add %2,%1,%0";
1724 /* Catch cases where no extended register was used. */
1725 if (src1_class != EXTENDED_REGS
1726 && src2_class != EXTENDED_REGS
1727 && dest_class != EXTENDED_REGS)
1729 /* We have to copy one of the sources into the destination, then
1730 add the other source to the destination.
1732 Carefully select which source to copy to the destination; a
1733 naive implementation will waste a byte when the source classes
1734 are different and the destination is an address register.
1735 Selecting the lowest cost register copy will optimize this
1737 if (src1_class == dest_class)
1738 return "mov %1,%0\n\tadd %2,%0";
1740 return "mov %2,%0\n\tadd %1,%0";
1743 /* At least one register is an extended register. */
1745 /* The three operand add instruction on the am33 is a win iff the
1746 output register is an extended register, or if both source
1747 registers are extended registers. */
1748 if (dest_class == EXTENDED_REGS || src1_class == src2_class)
1749 return "add %2,%1,%0";
1751 /* It is better to copy one of the sources to the destination, then
1752 perform a 2 address add. The destination in this case must be
1753 an address or data register and one of the sources must be an
1754 extended register and the remaining source must not be an extended
1757 The best code for this case is to copy the extended reg to the
1758 destination, then emit a two address add. */
1759 if (src1_class == EXTENDED_REGS)
1760 return "mov %1,%0\n\tadd %2,%0";
1762 return "mov %2,%0\n\tadd %1,%0";
1765 /* Return 1 if X contains a symbolic expression. We know these
1766 expressions will have one of a few well defined forms, so
1767 we need only check those forms. */
1770 mn10300_symbolic_operand (rtx op,
1771 enum machine_mode mode ATTRIBUTE_UNUSED)
1773 switch (GET_CODE (op))
1780 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1781 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1782 && CONST_INT_P (XEXP (op, 1)));
1788 /* Try machine dependent ways of modifying an illegitimate address
1789 to be legitimate. If we find one, return the new valid address.
1790 This macro is used in only one place: `memory_address' in explow.c.
1792 OLDX is the address as it was before break_out_memory_refs was called.
1793 In some cases it is useful to look at this to decide what needs to be done.
1795 Normally it is always safe for this macro to do nothing. It exists to
1796 recognize opportunities to optimize the output.
1798 But on a few ports with segmented architectures and indexed addressing
1799 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1802 mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1803 enum machine_mode mode ATTRIBUTE_UNUSED)
1805 if (flag_pic && ! mn10300_legitimate_pic_operand_p (x))
1806 x = mn10300_legitimize_pic_address (oldx, NULL_RTX);
1808 /* Uh-oh. We might have an address for x[n-100000]. This needs
1809 special handling to avoid creating an indexed memory address
1810 with x-100000 as the base. */
1811 if (GET_CODE (x) == PLUS
1812 && mn10300_symbolic_operand (XEXP (x, 1), VOIDmode))
1814 /* Ugly. We modify things here so that the address offset specified
1815 by the index expression is computed first, then added to x to form
1816 the entire address. */
1818 rtx regx1, regy1, regy2, y;
1820 /* Strip off any CONST. */
1822 if (GET_CODE (y) == CONST)
1825 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1827 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1828 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1829 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1830 regx1 = force_reg (Pmode,
1831 gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1,
1833 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1839 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1840 @GOTOFF in `reg'. */
1843 mn10300_legitimize_pic_address (rtx orig, rtx reg)
1847 if (GET_CODE (orig) == LABEL_REF
1848 || (GET_CODE (orig) == SYMBOL_REF
1849 && (CONSTANT_POOL_ADDRESS_P (orig)
1850 || ! MN10300_GLOBAL_P (orig))))
1853 reg = gen_reg_rtx (Pmode);
1855 x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOTOFF);
1856 x = gen_rtx_CONST (SImode, x);
1857 emit_move_insn (reg, x);
1859 x = emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1861 else if (GET_CODE (orig) == SYMBOL_REF)
1864 reg = gen_reg_rtx (Pmode);
1866 x = gen_rtx_UNSPEC (SImode, gen_rtvec (1, orig), UNSPEC_GOT);
1867 x = gen_rtx_CONST (SImode, x);
1868 x = gen_rtx_PLUS (SImode, pic_offset_table_rtx, x);
1869 x = gen_const_mem (SImode, x);
1871 x = emit_move_insn (reg, x);
1876 set_unique_reg_note (x, REG_EQUAL, orig);
1880 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1881 isn't protected by a PIC unspec; nonzero otherwise. */
1884 mn10300_legitimate_pic_operand_p (rtx x)
1889 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1892 if (GET_CODE (x) == UNSPEC
1893 && (XINT (x, 1) == UNSPEC_PIC
1894 || XINT (x, 1) == UNSPEC_GOT
1895 || XINT (x, 1) == UNSPEC_GOTOFF
1896 || XINT (x, 1) == UNSPEC_PLT
1897 || XINT (x, 1) == UNSPEC_GOTSYM_OFF))
1900 fmt = GET_RTX_FORMAT (GET_CODE (x));
1901 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1907 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1908 if (! mn10300_legitimate_pic_operand_p (XVECEXP (x, i, j)))
1911 else if (fmt[i] == 'e'
1912 && ! mn10300_legitimate_pic_operand_p (XEXP (x, i)))
1919 /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1920 legitimate, and FALSE otherwise.
1922 On the mn10300, the value in the address register must be
1923 in the same memory space/segment as the effective address.
1925 This is problematical for reload since it does not understand
1926 that base+index != index+base in a memory reference.
1928 Note it is still possible to use reg+reg addressing modes,
1929 it's just much more difficult. For a discussion of a possible
1930 workaround and solution, see the comments in pa.c before the
1931 function record_unscaled_index_insn_codes. */
1934 mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
1938 if (CONSTANT_ADDRESS_P (x))
1939 return !flag_pic || mn10300_legitimate_pic_operand_p (x);
1941 if (RTX_OK_FOR_BASE_P (x, strict))
1944 if (TARGET_AM33 && (mode == SImode || mode == SFmode || mode == HImode))
1946 if (GET_CODE (x) == POST_INC)
1947 return RTX_OK_FOR_BASE_P (XEXP (x, 0), strict);
1948 if (GET_CODE (x) == POST_MODIFY)
1949 return (RTX_OK_FOR_BASE_P (XEXP (x, 0), strict)
1950 && CONSTANT_ADDRESS_P (XEXP (x, 1)));
1953 if (GET_CODE (x) != PLUS)
1957 index = XEXP (x, 1);
1963 /* ??? Without AM33 generalized (Ri,Rn) addressing, reg+reg
1964 addressing is hard to satisfy. */
1968 return (REGNO_GENERAL_P (REGNO (base), strict)
1969 && REGNO_GENERAL_P (REGNO (index), strict));
1972 if (!REGNO_STRICT_OK_FOR_BASE_P (REGNO (base), strict))
1975 if (CONST_INT_P (index))
1976 return IN_RANGE (INTVAL (index), -1 - 0x7fffffff, 0x7fffffff);
1978 if (CONSTANT_ADDRESS_P (index))
1979 return !flag_pic || mn10300_legitimate_pic_operand_p (index);
1985 mn10300_regno_in_class_p (unsigned regno, int rclass, bool strict)
1987 if (regno >= FIRST_PSEUDO_REGISTER)
1993 regno = reg_renumber[regno];
1994 if (regno == INVALID_REGNUM)
1997 return TEST_HARD_REG_BIT (reg_class_contents[rclass], regno);
2001 mn10300_legitimize_reload_address (rtx x,
2002 enum machine_mode mode ATTRIBUTE_UNUSED,
2003 int opnum, int type,
2004 int ind_levels ATTRIBUTE_UNUSED)
2006 bool any_change = false;
2008 /* See above re disabling reg+reg addressing for MN103. */
2012 if (GET_CODE (x) != PLUS)
2015 if (XEXP (x, 0) == stack_pointer_rtx)
2017 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2018 GENERAL_REGS, GET_MODE (x), VOIDmode, 0, 0,
2019 opnum, (enum reload_type) type);
2022 if (XEXP (x, 1) == stack_pointer_rtx)
2024 push_reload (XEXP (x, 1), NULL_RTX, &XEXP (x, 1), NULL,
2025 GENERAL_REGS, GET_MODE (x), VOIDmode, 0, 0,
2026 opnum, (enum reload_type) type);
2030 return any_change ? x : NULL_RTX;
2033 /* Implement TARGET_LEGITIMATE_CONSTANT_P. Returns TRUE if X is a valid
2034 constant. Note that some "constants" aren't valid, such as TLS
2035 symbols and unconverted GOT-based references, so we eliminate
2039 mn10300_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
2041 switch (GET_CODE (x))
2046 if (GET_CODE (x) == PLUS)
2048 if (! CONST_INT_P (XEXP (x, 1)))
2053 /* Only some unspecs are valid as "constants". */
2054 if (GET_CODE (x) == UNSPEC)
2056 switch (XINT (x, 1))
2068 /* We must have drilled down to a symbol. */
2069 if (! mn10300_symbolic_operand (x, Pmode))
2080 /* Undo pic address legitimization for the benefit of debug info. */
2083 mn10300_delegitimize_address (rtx orig_x)
2085 rtx x = orig_x, ret, addend = NULL;
2090 if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode)
2093 if (XEXP (x, 0) == pic_offset_table_rtx)
2095 /* With the REG+REG addressing of AM33, var-tracking can re-assemble
2096 some odd-looking "addresses" that were never valid in the first place.
2097 We need to look harder to avoid warnings being emitted. */
2098 else if (GET_CODE (XEXP (x, 0)) == PLUS)
2100 rtx x0 = XEXP (x, 0);
2101 rtx x00 = XEXP (x0, 0);
2102 rtx x01 = XEXP (x0, 1);
2104 if (x00 == pic_offset_table_rtx)
2106 else if (x01 == pic_offset_table_rtx)
2116 if (GET_CODE (x) != CONST)
2119 if (GET_CODE (x) != UNSPEC)
2122 ret = XVECEXP (x, 0, 0);
2123 if (XINT (x, 1) == UNSPEC_GOTOFF)
2125 else if (XINT (x, 1) == UNSPEC_GOT)
2130 gcc_assert (GET_CODE (ret) == SYMBOL_REF);
2131 if (need_mem != MEM_P (orig_x))
2133 if (need_mem && addend)
2136 ret = gen_rtx_PLUS (Pmode, addend, ret);
2140 /* For addresses, costs are relative to "MOV (Rm),Rn". For AM33 this is
2141 the 3-byte fully general instruction; for MN103 this is the 2-byte form
2142 with an address register. */
2145 mn10300_address_cost (rtx x, bool speed)
2150 switch (GET_CODE (x))
2155 /* We assume all of these require a 32-bit constant, even though
2156 some symbol and label references can be relaxed. */
2157 return speed ? 1 : 4;
2165 /* Assume any symbolic offset is a 32-bit constant. */
2166 i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678);
2167 if (IN_RANGE (i, -128, 127))
2168 return speed ? 0 : 1;
2171 if (IN_RANGE (i, -0x800000, 0x7fffff))
2177 index = XEXP (x, 1);
2178 if (register_operand (index, SImode))
2180 /* Attempt to minimize the number of registers in the address.
2181 This is similar to what other ports do. */
2182 if (register_operand (base, SImode))
2186 index = XEXP (x, 0);
2189 /* Assume any symbolic offset is a 32-bit constant. */
2190 i = (CONST_INT_P (XEXP (x, 1)) ? INTVAL (XEXP (x, 1)) : 0x12345678);
2191 if (IN_RANGE (i, -128, 127))
2192 return speed ? 0 : 1;
2193 if (IN_RANGE (i, -32768, 32767))
2194 return speed ? 0 : 2;
2195 return speed ? 2 : 6;
2198 return rtx_cost (x, MEM, 0, speed);
2202 /* Implement the TARGET_REGISTER_MOVE_COST hook.
2204 Recall that the base value of 2 is required by assumptions elsewhere
2205 in the body of the compiler, and that cost 2 is special-cased as an
2206 early exit from reload meaning no work is required. */
2209 mn10300_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2210 reg_class_t ifrom, reg_class_t ito)
2212 enum reg_class from = (enum reg_class) ifrom;
2213 enum reg_class to = (enum reg_class) ito;
2214 enum reg_class scratch, test;
2216 /* Simplify the following code by unifying the fp register classes. */
2217 if (to == FP_ACC_REGS)
2219 if (from == FP_ACC_REGS)
2222 /* Diagnose invalid moves by costing them as two moves. */
2227 scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
2228 else if (to == MDR_REGS)
2229 scratch = DATA_REGS;
2230 else if (to == FP_REGS && to != from)
2231 scratch = GENERAL_REGS;
2235 if (from == SP_REGS)
2236 scratch = (TARGET_AM33 ? GENERAL_REGS : ADDRESS_REGS);
2237 else if (from == MDR_REGS)
2238 scratch = DATA_REGS;
2239 else if (from == FP_REGS && to != from)
2240 scratch = GENERAL_REGS;
2242 if (scratch != NO_REGS && !reg_class_subset_p (test, scratch))
2243 return (mn10300_register_move_cost (VOIDmode, from, scratch)
2244 + mn10300_register_move_cost (VOIDmode, scratch, to));
2246 /* From here on, all we need consider are legal combinations. */
2250 /* The scale here is bytes * 2. */
2252 if (from == to && (to == ADDRESS_REGS || to == DATA_REGS))
2255 if (from == SP_REGS)
2256 return (to == ADDRESS_REGS ? 2 : 6);
2258 /* For MN103, all remaining legal moves are two bytes. */
2263 return (from == ADDRESS_REGS ? 4 : 6);
2265 if ((from == ADDRESS_REGS || from == DATA_REGS)
2266 && (to == ADDRESS_REGS || to == DATA_REGS))
2269 if (to == EXTENDED_REGS)
2270 return (to == from ? 6 : 4);
2272 /* What's left are SP_REGS, FP_REGS, or combinations of the above. */
2277 /* The scale here is cycles * 2. */
2281 if (from == FP_REGS)
2284 /* All legal moves between integral registers are single cycle. */
2289 /* Implement the TARGET_MEMORY_MOVE_COST hook.
2291 Given lack of the form of the address, this must be speed-relative,
2292 though we should never be less expensive than a size-relative register
2293 move cost above. This is not a problem. */
2296 mn10300_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2297 reg_class_t iclass, bool in ATTRIBUTE_UNUSED)
2299 enum reg_class rclass = (enum reg_class) iclass;
2301 if (rclass == FP_REGS)
2306 /* Implement the TARGET_RTX_COSTS hook.
2308 Speed-relative costs are relative to COSTS_N_INSNS, which is intended
2309 to represent cycles. Size-relative costs are in bytes. */
2312 mn10300_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2313 int *ptotal, bool speed)
2315 /* This value is used for SYMBOL_REF etc where we want to pretend
2316 we have a full 32-bit constant. */
2317 HOST_WIDE_INT i = 0x12345678;
2327 if (outer_code == SET)
2329 /* 16-bit integer loads have latency 1, 32-bit loads 2. */
2330 if (IN_RANGE (i, -32768, 32767))
2331 total = COSTS_N_INSNS (1);
2333 total = COSTS_N_INSNS (2);
2337 /* 16-bit integer operands don't affect latency;
2338 24-bit and 32-bit operands add a cycle. */
2339 if (IN_RANGE (i, -32768, 32767))
2342 total = COSTS_N_INSNS (1);
2347 if (outer_code == SET)
2351 else if (IN_RANGE (i, -128, 127))
2353 else if (IN_RANGE (i, -32768, 32767))
2360 /* Reference here is ADD An,Dn, vs ADD imm,Dn. */
2361 if (IN_RANGE (i, -128, 127))
2363 else if (IN_RANGE (i, -32768, 32767))
2365 else if (TARGET_AM33 && IN_RANGE (i, -0x01000000, 0x00ffffff))
2377 /* We assume all of these require a 32-bit constant, even though
2378 some symbol and label references can be relaxed. */
2382 switch (XINT (x, 1))
2388 case UNSPEC_GOTSYM_OFF:
2389 /* The PIC unspecs also resolve to a 32-bit constant. */
2393 /* Assume any non-listed unspec is some sort of arithmetic. */
2394 goto do_arith_costs;
2398 /* Notice the size difference of INC and INC4. */
2399 if (!speed && outer_code == SET && CONST_INT_P (XEXP (x, 1)))
2401 i = INTVAL (XEXP (x, 1));
2402 if (i == 1 || i == 4)
2404 total = 1 + rtx_cost (XEXP (x, 0), PLUS, 0, speed);
2408 goto do_arith_costs;
2422 total = (speed ? COSTS_N_INSNS (1) : 2);
2426 /* Notice the size difference of ASL2 and variants. */
2427 if (!speed && CONST_INT_P (XEXP (x, 1)))
2428 switch (INTVAL (XEXP (x, 1)))
2443 total = (speed ? COSTS_N_INSNS (1) : 3);
2447 total = (speed ? COSTS_N_INSNS (3) : 2);
2454 total = (speed ? COSTS_N_INSNS (39)
2455 /* Include space to load+retrieve MDR. */
2456 : code == MOD || code == UMOD ? 6 : 4);
2460 total = mn10300_address_cost (XEXP (x, 0), speed);
2462 total = COSTS_N_INSNS (2 + total);
2466 /* Probably not implemented. Assume external call. */
2467 total = (speed ? COSTS_N_INSNS (10) : 7);
2479 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2480 may access it using GOTOFF instead of GOT. */
2483 mn10300_encode_section_info (tree decl, rtx rtl, int first)
2487 default_encode_section_info (decl, rtl, first);
2492 symbol = XEXP (rtl, 0);
2493 if (GET_CODE (symbol) != SYMBOL_REF)
2497 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
2500 /* Dispatch tables on the mn10300 are extremely expensive in terms of code
2501 and readonly data size. So we crank up the case threshold value to
2502 encourage a series of if/else comparisons to implement many small switch
2503 statements. In theory, this value could be increased much more if we
2504 were solely optimizing for space, but we keep it "reasonable" to avoid
2505 serious code efficiency lossage. */
2508 mn10300_case_values_threshold (void)
2513 /* Worker function for TARGET_TRAMPOLINE_INIT. */
2516 mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2518 rtx mem, disp, fnaddr = XEXP (DECL_RTL (fndecl), 0);
2520 /* This is a strict alignment target, which means that we play
2521 some games to make sure that the locations at which we need
2522 to store <chain> and <disp> wind up at aligned addresses.
2525 0xfc 0xdd mov chain,a1
2527 0xf8 0xed 0x00 btst 0,d1
2531 Note that the two extra insns are effectively nops; they
2532 clobber the flags but do not affect the contents of D0 or D1. */
2534 disp = expand_binop (SImode, sub_optab, fnaddr,
2535 plus_constant (Pmode, XEXP (m_tramp, 0), 11),
2536 NULL_RTX, 1, OPTAB_DIRECT);
2538 mem = adjust_address (m_tramp, SImode, 0);
2539 emit_move_insn (mem, gen_int_mode (0xddfc0028, SImode));
2540 mem = adjust_address (m_tramp, SImode, 4);
2541 emit_move_insn (mem, chain_value);
2542 mem = adjust_address (m_tramp, SImode, 8);
2543 emit_move_insn (mem, gen_int_mode (0xdc00edf8, SImode));
2544 mem = adjust_address (m_tramp, SImode, 12);
2545 emit_move_insn (mem, disp);
2548 /* Output the assembler code for a C++ thunk function.
2549 THUNK_DECL is the declaration for the thunk function itself, FUNCTION
2550 is the decl for the target function. DELTA is an immediate constant
2551 offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero
2552 the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be
2553 additionally added to THIS. Finally jump to the entry point of
2557 mn10300_asm_output_mi_thunk (FILE * file,
2558 tree thunk_fndecl ATTRIBUTE_UNUSED,
2559 HOST_WIDE_INT delta,
2560 HOST_WIDE_INT vcall_offset,
2565 /* Get the register holding the THIS parameter. Handle the case
2566 where there is a hidden first argument for a returned structure. */
2567 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
2568 _this = reg_names [FIRST_ARGUMENT_REGNUM + 1];
2570 _this = reg_names [FIRST_ARGUMENT_REGNUM];
2572 fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START);
2575 fprintf (file, "\tadd %d, %s\n", (int) delta, _this);
2579 const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1];
2581 fprintf (file, "\tmov %s, %s\n", _this, scratch);
2582 fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2583 fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch);
2584 fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2585 fprintf (file, "\tadd %s, %s\n", scratch, _this);
2588 fputs ("\tjmp ", file);
2589 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
2593 /* Return true if mn10300_output_mi_thunk would be able to output the
2594 assembler code for the thunk function specified by the arguments
2595 it is passed, and false otherwise. */
2598 mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
2599 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
2600 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2601 const_tree function ATTRIBUTE_UNUSED)
2607 mn10300_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
2609 if (REGNO_REG_CLASS (regno) == FP_REGS
2610 || REGNO_REG_CLASS (regno) == FP_ACC_REGS)
2611 /* Do not store integer values in FP registers. */
2612 return GET_MODE_CLASS (mode) == MODE_FLOAT && ((regno & 1) == 0);
2614 if (((regno) & 1) == 0 || GET_MODE_SIZE (mode) == 4)
2617 if (REGNO_REG_CLASS (regno) == DATA_REGS
2618 || (TARGET_AM33 && REGNO_REG_CLASS (regno) == ADDRESS_REGS)
2619 || REGNO_REG_CLASS (regno) == EXTENDED_REGS)
2620 return GET_MODE_SIZE (mode) <= 4;
2626 mn10300_modes_tieable (enum machine_mode mode1, enum machine_mode mode2)
2628 if (GET_MODE_CLASS (mode1) == MODE_FLOAT
2629 && GET_MODE_CLASS (mode2) != MODE_FLOAT)
2632 if (GET_MODE_CLASS (mode2) == MODE_FLOAT
2633 && GET_MODE_CLASS (mode1) != MODE_FLOAT)
2638 || (GET_MODE_SIZE (mode1) <= 4 && GET_MODE_SIZE (mode2) <= 4))
2645 cc_flags_for_mode (enum machine_mode mode)
2650 return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C | CC_FLAG_V;
2652 return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_C;
2654 return CC_FLAG_Z | CC_FLAG_N;
2663 cc_flags_for_code (enum rtx_code code)
2676 case GT: /* ~(Z|(N^V)) */
2677 case LE: /* Z|(N^V) */
2678 return CC_FLAG_Z | CC_FLAG_N | CC_FLAG_V;
2684 case GTU: /* ~(C | Z) */
2685 case LEU: /* C | Z */
2686 return CC_FLAG_Z | CC_FLAG_C;
2704 mn10300_select_cc_mode (enum rtx_code code, rtx x, rtx y ATTRIBUTE_UNUSED)
2708 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2709 return CC_FLOATmode;
2711 req = cc_flags_for_code (code);
2713 if (req & CC_FLAG_V)
2715 if (req & CC_FLAG_C)
2721 is_load_insn (rtx insn)
2723 if (GET_CODE (PATTERN (insn)) != SET)
2726 return MEM_P (SET_SRC (PATTERN (insn)));
2730 is_store_insn (rtx insn)
2732 if (GET_CODE (PATTERN (insn)) != SET)
2735 return MEM_P (SET_DEST (PATTERN (insn)));
2738 /* Update scheduling costs for situations that cannot be
2739 described using the attributes and DFA machinery.
2740 DEP is the insn being scheduled.
2741 INSN is the previous insn.
2742 COST is the current cycle cost for DEP. */
2745 mn10300_adjust_sched_cost (rtx insn, rtx link, rtx dep, int cost)
2747 int timings = get_attr_timings (insn);
2752 if (GET_CODE (insn) == PARALLEL)
2753 insn = XVECEXP (insn, 0, 0);
2755 if (GET_CODE (dep) == PARALLEL)
2756 dep = XVECEXP (dep, 0, 0);
2758 /* For the AM34 a load instruction that follows a
2759 store instruction incurs an extra cycle of delay. */
2760 if (mn10300_tune_cpu == PROCESSOR_AM34
2761 && is_load_insn (dep)
2762 && is_store_insn (insn))
2765 /* For the AM34 a non-store, non-branch FPU insn that follows
2766 another FPU insn incurs a one cycle throughput increase. */
2767 else if (mn10300_tune_cpu == PROCESSOR_AM34
2768 && ! is_store_insn (insn)
2770 && GET_CODE (PATTERN (dep)) == SET
2771 && GET_CODE (PATTERN (insn)) == SET
2772 && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) == MODE_FLOAT
2773 && GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) == MODE_FLOAT)
2776 /* Resolve the conflict described in section 1-7-4 of
2777 Chapter 3 of the MN103E Series Instruction Manual
2780 "When the preceding instruction is a CPU load or
2781 store instruction, a following FPU instruction
2782 cannot be executed until the CPU completes the
2783 latency period even though there are no register
2784 or flag dependencies between them." */
2786 /* Only the AM33-2 (and later) CPUs have FPU instructions. */
2787 if (! TARGET_AM33_2)
2790 /* If a data dependence already exists then the cost is correct. */
2791 if (REG_NOTE_KIND (link) == 0)
2794 /* Check that the instruction about to scheduled is an FPU instruction. */
2795 if (GET_CODE (PATTERN (dep)) != SET)
2798 if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (dep)))) != MODE_FLOAT)
2801 /* Now check to see if the previous instruction is a load or store. */
2802 if (! is_load_insn (insn) && ! is_store_insn (insn))
2805 /* XXX: Verify: The text of 1-7-4 implies that the restriction
2806 only applies when an INTEGER load/store precedes an FPU
2807 instruction, but is this true ? For now we assume that it is. */
2808 if (GET_MODE_CLASS (GET_MODE (SET_SRC (PATTERN (insn)))) != MODE_INT)
2811 /* Extract the latency value from the timings attribute. */
2812 return timings < 100 ? (timings % 10) : (timings % 100);
2816 mn10300_conditional_register_usage (void)
2822 for (i = FIRST_EXTENDED_REGNUM;
2823 i <= LAST_EXTENDED_REGNUM; i++)
2824 fixed_regs[i] = call_used_regs[i] = 1;
2828 for (i = FIRST_FP_REGNUM;
2829 i <= LAST_FP_REGNUM; i++)
2830 fixed_regs[i] = call_used_regs[i] = 1;
2833 fixed_regs[PIC_OFFSET_TABLE_REGNUM] =
2834 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
2837 /* Worker function for TARGET_MD_ASM_CLOBBERS.
2838 We do this in the mn10300 backend to maintain source compatibility
2839 with the old cc0-based compiler. */
2842 mn10300_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED,
2843 tree inputs ATTRIBUTE_UNUSED,
2846 clobbers = tree_cons (NULL_TREE, build_string (5, "EPSW"),
2851 /* A helper function for splitting cbranch patterns after reload. */
2854 mn10300_split_cbranch (enum machine_mode cmp_mode, rtx cmp_op, rtx label_ref)
2858 flags = gen_rtx_REG (cmp_mode, CC_REG);
2859 x = gen_rtx_COMPARE (cmp_mode, XEXP (cmp_op, 0), XEXP (cmp_op, 1));
2860 x = gen_rtx_SET (VOIDmode, flags, x);
2863 x = gen_rtx_fmt_ee (GET_CODE (cmp_op), VOIDmode, flags, const0_rtx);
2864 x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label_ref, pc_rtx);
2865 x = gen_rtx_SET (VOIDmode, pc_rtx, x);
2869 /* A helper function for matching parallels that set the flags. */
2872 mn10300_match_ccmode (rtx insn, enum machine_mode cc_mode)
2875 enum machine_mode flags_mode;
2877 gcc_checking_assert (XVECLEN (PATTERN (insn), 0) == 2);
2879 op1 = XVECEXP (PATTERN (insn), 0, 1);
2880 gcc_checking_assert (GET_CODE (SET_SRC (op1)) == COMPARE);
2882 flags = SET_DEST (op1);
2883 flags_mode = GET_MODE (flags);
2885 if (GET_MODE (SET_SRC (op1)) != flags_mode)
2887 if (GET_MODE_CLASS (flags_mode) != MODE_CC)
2890 /* Ensure that the mode of FLAGS is compatible with CC_MODE. */
2891 if (cc_flags_for_mode (flags_mode) & ~cc_flags_for_mode (cc_mode))
2897 /* This function is used to help split:
2899 (set (reg) (and (reg) (int)))
2903 (set (reg) (shift (reg) (int))
2904 (set (reg) (shift (reg) (int))
2906 where the shitfs will be shorter than the "and" insn.
2908 It returns the number of bits that should be shifted. A positive
2909 values means that the low bits are to be cleared (and hence the
2910 shifts should be right followed by left) whereas a negative value
2911 means that the high bits are to be cleared (left followed by right).
2912 Zero is returned when it would not be economical to split the AND. */
2915 mn10300_split_and_operand_count (rtx op)
2917 HOST_WIDE_INT val = INTVAL (op);
2922 /* High bit is set, look for bits clear at the bottom. */
2923 count = exact_log2 (-val);
2926 /* This is only size win if we can use the asl2 insn. Otherwise we
2927 would be replacing 1 6-byte insn with 2 3-byte insns. */
2928 if (count > (optimize_insn_for_speed_p () ? 2 : 4))
2934 /* High bit is clear, look for bits set at the bottom. */
2935 count = exact_log2 (val + 1);
2937 /* Again, this is only a size win with asl2. */
2938 if (count > (optimize_insn_for_speed_p () ? 2 : 4))
2947 enum attr_liw_op op;
2952 /* Decide if the given insn is a candidate for LIW bundling. If it is then
2953 extract the operands and LIW attributes from the insn and use them to fill
2954 in the liw_data structure. Return true upon success or false if the insn
2955 cannot be bundled. */
2958 extract_bundle (rtx insn, struct liw_data * pdata)
2960 bool allow_consts = true;
2963 gcc_assert (pdata != NULL);
2965 if (insn == NULL_RTX)
2967 /* Make sure that we are dealing with a simple SET insn. */
2968 p = single_set (insn);
2972 /* Make sure that it could go into one of the LIW pipelines. */
2973 pdata->slot = get_attr_liw (insn);
2974 if (pdata->slot == LIW_BOTH)
2977 pdata->op = get_attr_liw_op (insn);
2982 pdata->dest = SET_DEST (p);
2983 pdata->src = SET_SRC (p);
2986 pdata->dest = XEXP (SET_SRC (p), 0);
2987 pdata->src = XEXP (SET_SRC (p), 1);
2994 /* The AND, OR and XOR long instruction words only accept register arguments. */
2995 allow_consts = false;
2998 pdata->dest = SET_DEST (p);
2999 pdata->src = XEXP (SET_SRC (p), 1);
3003 if (! REG_P (pdata->dest))
3006 if (REG_P (pdata->src))
3009 return allow_consts && satisfies_constraint_O (pdata->src);
3012 /* Make sure that it is OK to execute LIW1 and LIW2 in parallel. GCC generated
3013 the instructions with the assumption that LIW1 would be executed before LIW2
3014 so we must check for overlaps between their sources and destinations. */
3017 check_liw_constraints (struct liw_data * pliw1, struct liw_data * pliw2)
3019 /* Check for slot conflicts. */
3020 if (pliw2->slot == pliw1->slot && pliw1->slot != LIW_EITHER)
3023 /* If either operation is a compare, then "dest" is really an input; the real
3024 destination is CC_REG. So these instructions need different checks. */
3026 /* Changing "CMP ; OP" into "CMP | OP" is OK because the comparison will
3027 check its values prior to any changes made by OP. */
3028 if (pliw1->op == LIW_OP_CMP)
3030 /* Two sequential comparisons means dead code, which ought to
3031 have been eliminated given that bundling only happens with
3032 optimization. We cannot bundle them in any case. */
3033 gcc_assert (pliw1->op != pliw2->op);
3037 /* Changing "OP ; CMP" into "OP | CMP" does not work if the value being compared
3038 is the destination of OP, as the CMP will look at the old value, not the new
3040 if (pliw2->op == LIW_OP_CMP)
3042 if (REGNO (pliw2->dest) == REGNO (pliw1->dest))
3045 if (REG_P (pliw2->src))
3046 return REGNO (pliw2->src) != REGNO (pliw1->dest);
3051 /* Changing "OP1 ; OP2" into "OP1 | OP2" does not work if they both write to the
3052 same destination register. */
3053 if (REGNO (pliw2->dest) == REGNO (pliw1->dest))
3056 /* Changing "OP1 ; OP2" into "OP1 | OP2" generally does not work if the destination
3057 of OP1 is the source of OP2. The exception is when OP1 is a MOVE instruction when
3058 we can replace the source in OP2 with the source of OP1. */
3059 if (REG_P (pliw2->src) && REGNO (pliw2->src) == REGNO (pliw1->dest))
3061 if (pliw1->op == LIW_OP_MOV && REG_P (pliw1->src))
3063 if (! REG_P (pliw1->src)
3064 && (pliw2->op == LIW_OP_AND
3065 || pliw2->op == LIW_OP_OR
3066 || pliw2->op == LIW_OP_XOR))
3069 pliw2->src = pliw1->src;
3075 /* Everything else is OK. */
3079 /* Combine pairs of insns into LIW bundles. */
3082 mn10300_bundle_liw (void)
3086 for (r = get_insns (); r != NULL_RTX; r = next_nonnote_nondebug_insn (r))
3089 struct liw_data liw1, liw2;
3092 if (! extract_bundle (insn1, & liw1))
3095 insn2 = next_nonnote_nondebug_insn (insn1);
3096 if (! extract_bundle (insn2, & liw2))
3099 /* Check for source/destination overlap. */
3100 if (! check_liw_constraints (& liw1, & liw2))
3103 if (liw1.slot == LIW_OP2 || liw2.slot == LIW_OP1)
3105 struct liw_data temp;
3112 delete_insn (insn2);
3114 if (liw1.op == LIW_OP_CMP)
3115 insn2 = gen_cmp_liw (liw2.dest, liw2.src, liw1.dest, liw1.src,
3117 else if (liw2.op == LIW_OP_CMP)
3118 insn2 = gen_liw_cmp (liw1.dest, liw1.src, liw2.dest, liw2.src,
3121 insn2 = gen_liw (liw1.dest, liw2.dest, liw1.src, liw2.src,
3122 GEN_INT (liw1.op), GEN_INT (liw2.op));
3124 insn2 = emit_insn_after (insn2, insn1);
3125 delete_insn (insn1);
3130 #define DUMP(reason, insn) \
3135 fprintf (dump_file, reason "\n"); \
3136 if (insn != NULL_RTX) \
3137 print_rtl_single (dump_file, insn); \
3138 fprintf(dump_file, "\n"); \
3143 /* Replace the BRANCH insn with a Lcc insn that goes to LABEL.
3144 Insert a SETLB insn just before LABEL. */
3147 mn10300_insert_setlb_lcc (rtx label, rtx branch)
3149 rtx lcc, comparison, cmp_reg;
3151 if (LABEL_NUSES (label) > 1)
3155 /* This label is used both as an entry point to the loop
3156 and as a loop-back point for the loop. We need to separate
3157 these two functions so that the SETLB happens upon entry,
3158 but the loop-back does not go to the SETLB instruction. */
3159 DUMP ("Inserting SETLB insn after:", label);
3160 insn = emit_insn_after (gen_setlb (), label);
3161 label = gen_label_rtx ();
3162 emit_label_after (label, insn);
3163 DUMP ("Created new loop-back label:", label);
3167 DUMP ("Inserting SETLB insn before:", label);
3168 emit_insn_before (gen_setlb (), label);
3171 comparison = XEXP (SET_SRC (PATTERN (branch)), 0);
3172 cmp_reg = XEXP (comparison, 0);
3173 gcc_assert (REG_P (cmp_reg));
3175 /* If the comparison has not already been split out of the branch
3177 gcc_assert (REGNO (cmp_reg) == CC_REG);
3179 if (GET_MODE (cmp_reg) == CC_FLOATmode)
3180 lcc = gen_FLcc (comparison, label);
3182 lcc = gen_Lcc (comparison, label);
3184 lcc = emit_jump_insn_before (lcc, branch);
3185 mark_jump_label (XVECEXP (PATTERN (lcc), 0, 0), lcc, 0);
3186 JUMP_LABEL (lcc) = label;
3187 DUMP ("Replacing branch insn...", branch);
3188 DUMP ("... with Lcc insn:", lcc);
3189 delete_insn (branch);
3193 mn10300_block_contains_call (basic_block block)
3197 FOR_BB_INSNS (block, insn)
3205 mn10300_loop_contains_call_insn (loop_p loop)
3208 bool result = false;
3211 bbs = get_loop_body (loop);
3213 for (i = 0; i < loop->num_nodes; i++)
3214 if (mn10300_block_contains_call (bbs[i]))
3225 mn10300_scan_for_setlb_lcc (void)
3228 loop_iterator liter;
3231 DUMP ("Looking for loops that can use the SETLB insn", NULL_RTX);
3234 compute_bb_for_insn ();
3236 /* Find the loops. */
3237 if (flow_loops_find (& loops) < 1)
3238 DUMP ("No loops found", NULL_RTX);
3239 current_loops = & loops;
3241 /* FIXME: For now we only investigate innermost loops. In practice however
3242 if an inner loop is not suitable for use with the SETLB/Lcc insns, it may
3243 be the case that its parent loop is suitable. Thus we should check all
3244 loops, but work from the innermost outwards. */
3245 FOR_EACH_LOOP (liter, loop, LI_ONLY_INNERMOST)
3247 const char * reason = NULL;
3249 /* Check to see if we can modify this loop. If we cannot
3250 then set 'reason' to describe why it could not be done. */
3251 if (loop->latch == NULL)
3252 reason = "it contains multiple latches";
3253 else if (loop->header != loop->latch)
3254 /* FIXME: We could handle loops that span multiple blocks,
3255 but this requires a lot more work tracking down the branches
3256 that need altering, so for now keep things simple. */
3257 reason = "the loop spans multiple blocks";
3258 else if (mn10300_loop_contains_call_insn (loop))
3259 reason = "it contains CALL insns";
3262 rtx branch = BB_END (loop->latch);
3264 gcc_assert (JUMP_P (branch));
3265 if (single_set (branch) == NULL_RTX || ! any_condjump_p (branch))
3266 /* We cannot optimize tablejumps and the like. */
3267 /* FIXME: We could handle unconditional jumps. */
3268 reason = "it is not a simple loop";
3274 flow_loop_dump (loop, dump_file, NULL, 0);
3276 label = BB_HEAD (loop->header);
3277 gcc_assert (LABEL_P (label));
3279 mn10300_insert_setlb_lcc (label, branch);
3283 if (dump_file && reason != NULL)
3284 fprintf (dump_file, "Loop starting with insn %d is not suitable because %s\n",
3285 INSN_UID (BB_HEAD (loop->header)),
3289 #if 0 /* FIXME: We should free the storage we allocated, but
3290 for some unknown reason this leads to seg-faults. */
3291 FOR_EACH_LOOP (liter, loop, 0)
3292 free_simple_loop_desc (loop);
3294 flow_loops_free (current_loops);
3297 current_loops = NULL;
3299 df_finish_pass (false);
3301 DUMP ("SETLB scan complete", NULL_RTX);
3305 mn10300_reorg (void)
3307 /* These are optimizations, so only run them if optimizing. */
3308 if (TARGET_AM33 && (optimize > 0 || optimize_size))
3310 if (TARGET_ALLOW_SETLB)
3311 mn10300_scan_for_setlb_lcc ();
3313 if (TARGET_ALLOW_LIW)
3314 mn10300_bundle_liw ();
3318 /* Initialize the GCC target structure. */
3320 #undef TARGET_MACHINE_DEPENDENT_REORG
3321 #define TARGET_MACHINE_DEPENDENT_REORG mn10300_reorg
3323 #undef TARGET_ASM_ALIGNED_HI_OP
3324 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
3326 #undef TARGET_LEGITIMIZE_ADDRESS
3327 #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
3329 #undef TARGET_ADDRESS_COST
3330 #define TARGET_ADDRESS_COST mn10300_address_cost
3331 #undef TARGET_REGISTER_MOVE_COST
3332 #define TARGET_REGISTER_MOVE_COST mn10300_register_move_cost
3333 #undef TARGET_MEMORY_MOVE_COST
3334 #define TARGET_MEMORY_MOVE_COST mn10300_memory_move_cost
3335 #undef TARGET_RTX_COSTS
3336 #define TARGET_RTX_COSTS mn10300_rtx_costs
3338 #undef TARGET_ASM_FILE_START
3339 #define TARGET_ASM_FILE_START mn10300_file_start
3340 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
3341 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
3343 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
3344 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA mn10300_asm_output_addr_const_extra
3346 #undef TARGET_OPTION_OVERRIDE
3347 #define TARGET_OPTION_OVERRIDE mn10300_option_override
3349 #undef TARGET_ENCODE_SECTION_INFO
3350 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
3352 #undef TARGET_PROMOTE_PROTOTYPES
3353 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
3354 #undef TARGET_RETURN_IN_MEMORY
3355 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
3356 #undef TARGET_PASS_BY_REFERENCE
3357 #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
3358 #undef TARGET_CALLEE_COPIES
3359 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
3360 #undef TARGET_ARG_PARTIAL_BYTES
3361 #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
3362 #undef TARGET_FUNCTION_ARG
3363 #define TARGET_FUNCTION_ARG mn10300_function_arg
3364 #undef TARGET_FUNCTION_ARG_ADVANCE
3365 #define TARGET_FUNCTION_ARG_ADVANCE mn10300_function_arg_advance
3367 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
3368 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
3369 #undef TARGET_EXPAND_BUILTIN_VA_START
3370 #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
3372 #undef TARGET_CASE_VALUES_THRESHOLD
3373 #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
3375 #undef TARGET_LEGITIMATE_ADDRESS_P
3376 #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
3377 #undef TARGET_DELEGITIMIZE_ADDRESS
3378 #define TARGET_DELEGITIMIZE_ADDRESS mn10300_delegitimize_address
3379 #undef TARGET_LEGITIMATE_CONSTANT_P
3380 #define TARGET_LEGITIMATE_CONSTANT_P mn10300_legitimate_constant_p
3382 #undef TARGET_PREFERRED_RELOAD_CLASS
3383 #define TARGET_PREFERRED_RELOAD_CLASS mn10300_preferred_reload_class
3384 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
3385 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS \
3386 mn10300_preferred_output_reload_class
3387 #undef TARGET_SECONDARY_RELOAD
3388 #define TARGET_SECONDARY_RELOAD mn10300_secondary_reload
3390 #undef TARGET_TRAMPOLINE_INIT
3391 #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
3393 #undef TARGET_FUNCTION_VALUE
3394 #define TARGET_FUNCTION_VALUE mn10300_function_value
3395 #undef TARGET_LIBCALL_VALUE
3396 #define TARGET_LIBCALL_VALUE mn10300_libcall_value
3398 #undef TARGET_ASM_OUTPUT_MI_THUNK
3399 #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk
3400 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
3401 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
3403 #undef TARGET_SCHED_ADJUST_COST
3404 #define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost
3406 #undef TARGET_CONDITIONAL_REGISTER_USAGE
3407 #define TARGET_CONDITIONAL_REGISTER_USAGE mn10300_conditional_register_usage
3409 #undef TARGET_MD_ASM_CLOBBERS
3410 #define TARGET_MD_ASM_CLOBBERS mn10300_md_asm_clobbers
3412 #undef TARGET_FLAGS_REGNUM
3413 #define TARGET_FLAGS_REGNUM CC_REG
3415 struct gcc_target targetm = TARGET_INITIALIZER;