1 ;; GCC machine description for Matsushita MN10200
2 ;; Copyright (C) 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
3 ;; Contributed by Jeff Law (law@cygnus.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
27 ;; Condition code settings.
28 ;; none - insn does not affect cc
29 ;; none_0hit - insn does not affect cc but it does modify operand 0
30 ;; This attribute is used to keep track of when operand 0 changes.
31 ;; See the description of NOTICE_UPDATE_CC for more info.
32 ;; set_znv - sets z,n,v to usable values; c is unknown.
33 ;; set_zn - sets z,n to usable values; v,c is unknown.
34 ;; compare - compare instruction
35 ;; clobber - value of cc is unknown
36 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber"
37 (const_string "clobber"))
39 ;; ----------------------------------------------------------------------
41 ;; ----------------------------------------------------------------------
43 ;; Some general notes on move instructions.
45 ;; The hardware can't encode nop moves involving data registers, so
46 ;; we catch them and emit a nop instead.
48 ;; Loads/stores to/from address registers must be 16bit aligned,
49 ;; thus we avoid them for QImode.
51 ;; Stores from address registers always store 24bits, so avoid
52 ;; stores from address registers in HImode, SImode, and SFmode.
54 ;; As a result of the various problems using address registers in
55 ;; QImode, HImode, SImode, and SFmode, we discourage their use via
56 ;; '*' in their constraints. They're still allowed, but they're never
57 ;; the preferred class for insns with those modes.
61 (define_expand "movqi"
62 [(set (match_operand:QI 0 "general_operand" "")
63 (match_operand:QI 1 "general_operand" ""))]
67 /* One of the ops has to be in a register */
68 if (!register_operand (operand0, QImode)
69 && !register_operand (operand1, QImode))
70 operands[1] = copy_to_mode_reg (QImode, operand1);
73 ;; We avoid memory operations involving address registers because we
74 ;; can't be sure they'll be suitably aligned.
76 ;; We also discourage holding QImode values in address registers.
78 [(set (match_operand:QI 0 "general_operand" "=d,d,*a,d,d,m,d,*a,*a")
79 (match_operand:QI 1 "general_operand" "0,I,I,di,m,d,*a,d,i*a"))]
80 "register_operand (operands[0], QImode)
81 || register_operand (operands[1], QImode)"
92 [(set_attr "cc" "none,clobber,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
96 (define_expand "movhi"
97 [(set (match_operand:HI 0 "general_operand" "")
98 (match_operand:HI 1 "general_operand" ""))]
102 /* One of the ops has to be in a register */
103 if (!register_operand (operand1, HImode)
104 && !register_operand (operand0, HImode))
105 operands[1] = copy_to_mode_reg (HImode, operand1);
109 [(set (match_operand:HI 0 "general_operand" "=d,d,*a,d,d,m,d,*a,*a,*a")
110 (match_operand:HI 1 "general_operand" "0,I,I,di,m,d,*a,d,i*a,m"))]
111 "register_operand (operands[0], HImode)
112 || register_operand (operands[1], HImode)"
124 [(set_attr "cc" "none,clobber,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
126 ;; movpsi and helpers
128 (define_expand "movpsi"
129 [(set (match_operand:PSI 0 "general_operand" "")
130 (match_operand:PSI 1 "general_operand" ""))]
134 /* One of the ops has to be in a register */
135 if (!register_operand (operand1, PSImode)
136 && !register_operand (operand0, PSImode))
137 operands[1] = copy_to_mode_reg (PSImode, operand1);
141 ;; Constant and indexed addresses are not valid addresses for PSImode,
142 ;; therefore they won't be matched by the general movpsi pattern below.
143 ;; ??? We had patterns to handle indexed addresses, but they kept making
144 ;; us run out of regs, so they were eliminated.
147 [(set (match_operand:PSI 0 "register_operand" "=a")
148 (match_operand:PSI 1 "constant_memory_operand" ""))]
151 [(set_attr "cc" "none_0hit")])
154 [(set (match_operand:PSI 0 "constant_memory_operand" "=X")
155 (match_operand:PSI 1 "register_operand" "a"))]
158 [(set_attr "cc" "none_0hit")])
160 ;; We want to prefer address registers here because 24bit moves to/from
161 ;; memory are shorter and faster when done via address registers.
163 [(set (match_operand:PSI 0 "general_operand" "=d,a?d,?da,a,m,?d,m")
164 (match_operand:PSI 1 "general_operand" "0,I,?dai,m,a,m,?d"))]
165 "register_operand (operands[0], PSImode)
166 || register_operand (operands[1], PSImode)"
175 [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
177 (define_expand "movsi"
178 [(set (match_operand:SI 0 "general_operand" "")
179 (match_operand:SI 1 "general_operand" ""))]
183 /* One of the ops has to be in a register */
184 if (!register_operand (operand1, SImode)
185 && !register_operand (operand0, SImode))
186 operands[1] = copy_to_mode_reg (SImode, operand1);
190 [(set (match_operand:SI 0 "general_operand" "=d,d,*a,dm,d,d,*a,*a,*a")
191 (match_operand:SI 1 "general_operand" "0,I,I,d,dim,*a,d,*a,i"))]
192 "register_operand (operands[0], SImode)
193 || register_operand (operands[1], SImode)"
196 switch (which_alternative)
202 return \"sub %H0,%H0\;sub %L0,%L0\";
207 return \"mov %H1,%H0\;mov %L1,%L0\";
209 /* The next two cases try to optimize cases where one half
210 of the constant is all zeros, or when the two halves are
214 if (REG_P (operands[0])
215 && GET_CODE (operands[1]) == CONST_INT
216 && (INTVAL (operands[1]) & 0xffff0000) == 0)
217 output_asm_insn (\"sub %H0,%H0\", operands);
219 output_asm_insn (\"mov %h1,%H0\", operands);
221 if (GET_CODE (operands[1]) == CONST_INT
222 && ((INTVAL (operands[1]) & 0xffff)
223 == ((INTVAL (operands[1]) >> 16) & 0xffff)))
224 output_asm_insn (\"mov %H0,%L0\", operands);
225 else if (GET_CODE (operands[1]) == CONST_INT
226 && (INTVAL (operands[1]) & 0xffff) == 0)
227 output_asm_insn (\"sub %L0,%L0\", operands);
229 output_asm_insn (\"mov %o1,%L0\", operands);
235 [(set_attr "cc" "none,clobber,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
237 (define_expand "movsf"
238 [(set (match_operand:SF 0 "general_operand" "")
239 (match_operand:SF 1 "general_operand" ""))]
243 /* One of the ops has to be in a register */
244 if (!register_operand (operand1, SFmode)
245 && !register_operand (operand0, SFmode))
246 operands[1] = copy_to_mode_reg (SFmode, operand1);
250 [(set (match_operand:SF 0 "general_operand" "=d,d,*a,dm,d,d,*a,*a,*a")
251 (match_operand:SF 1 "general_operand" "0,G,G,d,dim,*a,d,*a,i"))]
252 "register_operand (operands[0], SFmode)
253 || register_operand (operands[1], SFmode)"
256 switch (which_alternative)
263 return \"sub %H0,%H0\;sub %L0,%L0\";
270 if (GET_CODE (operands[1]) == CONST_DOUBLE)
272 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
273 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
276 if (GET_CODE (operands[1]) == CONST_INT)
277 val = INTVAL (operands[1]);
279 if ((GET_CODE (operands[1]) == CONST_INT
280 || GET_CODE (operands[1]) == CONST_DOUBLE)
281 && (val & 0xffff0000) == 0)
282 output_asm_insn (\"sub %H0,%H0\", operands);
284 output_asm_insn (\"mov %h1,%H0\", operands);
286 if (GET_CODE (operands[1]) == CONST_INT
287 && ((INTVAL (operands[1]) & 0xffff)
288 == ((INTVAL (operands[1]) >> 16) & 0xffff)))
289 output_asm_insn (\"mov %H0,%L0\", operands);
290 else if ((GET_CODE (operands[1]) == CONST_INT
291 || GET_CODE (operands[1]) == CONST_DOUBLE)
292 && (val & 0x0000ffff) == 0)
293 output_asm_insn (\"sub %L0,%L0\", operands);
295 output_asm_insn (\"mov %o1,%L0\", operands);
300 [(set_attr "cc" "none,clobber,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
303 ;; ----------------------------------------------------------------------
305 ;; ----------------------------------------------------------------------
307 ;; Go ahead and define tsthi and tstpsi so we can eliminate redundant tst insns
308 ;; when we start trying to optimize this port.
310 [(set (cc0) (match_operand:HI 0 "nonimmediate_operand" "da"))]
312 "* return output_tst (operands[0], insn);"
313 [(set_attr "cc" "set_znv")])
315 (define_insn "tstpsi"
316 [(set (cc0) (match_operand:PSI 0 "nonimmediate_operand" "da"))]
318 "* return output_tst (operands[0], insn);"
319 [(set_attr "cc" "set_znv")])
322 [(set (cc0) (zero_extend:HI (match_operand:QI 0 "memory_operand" "d")))]
324 "* return output_tst (operands[0], insn);"
325 [(set_attr "cc" "set_znv")])
328 [(set (cc0) (zero_extend:PSI (match_operand:QI 0 "memory_operand" "d")))]
330 "* return output_tst (operands[0], insn);"
331 [(set_attr "cc" "set_znv")])
335 (compare:HI (match_operand:HI 0 "nonimmediate_operand" "da")
336 (match_operand:HI 1 "general_operand" "dai")))]
339 [(set_attr "cc" "compare")])
341 (define_insn "cmppsi"
343 (compare:PSI (match_operand:PSI 0 "nonimmediate_operand" "da")
344 (match_operand:PSI 1 "general_operand" "dai")))]
347 [(set_attr "cc" "compare")])
349 ;; ----------------------------------------------------------------------
351 ;; ----------------------------------------------------------------------
353 (define_insn "addhi3"
354 [(set (match_operand:HI 0 "general_operand" "=d")
355 (plus:HI (match_operand:HI 1 "general_operand" "%0")
356 (match_operand:HI 2 "general_operand" "dai")))]
359 [(set_attr "cc" "set_zn")])
361 (define_insn "addpsi3"
362 [(set (match_operand:PSI 0 "general_operand" "=da")
363 (plus:PSI (match_operand:PSI 1 "general_operand" "%0")
364 (match_operand:PSI 2 "general_operand" "dai")))]
367 [(set_attr "cc" "set_zn")])
369 ;; We want to avoid using explicit registers; reload won't tell us
370 ;; if it has to spill them and may generate incorrect code in such
373 ;; So we call out to a library routine to perform 32bit add or
374 ;; subtract operations.
376 ;; operand2 must be nonmemory_operand so that we will accept CONST_INTs
377 ;; during initial code generation.
378 (define_expand "addsi3"
379 [(set (match_operand:SI 0 "register_operand" "")
380 (plus:SI (match_operand:SI 1 "register_operand" "")
381 (match_operand:SI 2 "nonmemory_operand" "")))]
385 /* If adding a CONST_INT, we are better off generating code ourselves.
387 During RTL generation we call out to library routines.
389 After RTL generation we can not call the library routines as
390 they need to push arguments via virtual_outgoing_args_rtx which
391 has already been instantiated. So, after RTL generation we just
392 FAIL and open code the operation. */
393 if (GET_CODE (operands[2]) == CONST_INT)
395 if (!rtx_equal_p (operands[0], operands[1]))
396 emit_move_insn (operands[0], operands[1]);
397 emit_insn (gen_addsi3_const (operands[0], operands[0], operands[2]));
400 else if (rtx_equal_function_value_matters)
405 ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__addsi3\"),
406 NULL_RTX, 1, SImode, 2, operands[1],
407 SImode, operands[2], SImode);
408 insns = get_insns ();
410 emit_libcall_block (insns, operands[0], ret,
411 gen_rtx_PLUS (SImode, operands[1], operands[2]));
418 (define_insn "addsi3_const"
419 [(set (match_operand:SI 0 "register_operand" "=d")
420 (plus:SI (match_operand:SI 1 "register_operand" "0")
421 (match_operand:SI 2 "const_int_operand" "i")))
422 (clobber (match_scratch:SI 3 "=&d"))]
426 unsigned long value = INTVAL (operands[2]);
428 /* If only the high bits are set in the constant, then we only
429 need a single add operation. It might be better to catch this
430 at RTL expansion time. */
431 if ((value & 0xffff) == 0)
432 return \"add %h2,%H0\";
438 return \"sub %3,%3\;add %o2,%L0\;addc %3,%H0\";
440 return \"mov %h2,%3\;add %o2,%L0\;addc %3,%H0\";
442 [(set_attr "cc" "clobber")])
444 ;; ----------------------------------------------------------------------
445 ;; SUBTRACT INSTRUCTIONS
446 ;; ----------------------------------------------------------------------
448 (define_insn "subhi3"
449 [(set (match_operand:HI 0 "general_operand" "=d")
450 (minus:HI (match_operand:HI 1 "general_operand" "0")
451 (match_operand:HI 2 "general_operand" "dai")))]
454 [(set_attr "cc" "set_zn")])
456 (define_insn "subpsi3"
457 [(set (match_operand:PSI 0 "general_operand" "=da")
458 (minus:PSI (match_operand:PSI 1 "general_operand" "0")
459 (match_operand:PSI 2 "general_operand" "dai")))]
462 [(set_attr "cc" "set_zn")])
464 (define_expand "subsi3"
465 [(set (match_operand:SI 0 "register_operand" "")
466 (minus:SI (match_operand:SI 1 "register_operand" "")
467 (match_operand:SI 2 "register_operand" "")))]
471 /* During RTL generation we call out to library routines.
473 After RTL generation we can not call the library routines as
474 they need to push arguments via virtual_outgoing_args_rtx which
475 has already been instantiated. So, after RTL generation we just
476 FAIL and open code the operation. */
477 if (rtx_equal_function_value_matters)
482 ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__subsi3\"),
483 NULL_RTX, 1, SImode, 2, operands[1],
484 SImode, operands[2], SImode);
485 insns = get_insns ();
487 emit_libcall_block (insns, operands[0], ret,
488 gen_rtx_MINUS (SImode, operands[1], operands[2]));
495 ;; There isn't a negate instruction, so we fake it.
497 ;; We used to expand this into patterns, but a single pattern
498 ;; actually generates better overall code.
500 ;; We could do HImode negations with a "not;add" sequence, but
501 ;; generally it's generated slightly worse code.
503 ;; The second alternative is not strictly necesasry, but helps
504 ;; when the register allocators start running short of registers.
505 (define_insn "neghi2"
506 [(set (match_operand:HI 0 "general_operand" "=&d,d")
507 (neg:HI (match_operand:HI 1 "general_operand" "d,0")))]
512 [(set_attr "cc" "set_zn")])
514 ;; The not/and sequence won't work here. It's not clear if we'll
515 ;; ever need to provide an alternate sequence since this should
516 ;; be used much less frequently than neghi2.
517 (define_insn "negpsi2"
518 [(set (match_operand:PSI 0 "general_operand" "=&d")
519 (neg:PSI (match_operand:PSI 1 "general_operand" "d")))]
521 "sub %0,%0\;sub %1,%0"
522 [(set_attr "cc" "set_zn")])
524 ;; Using a magic libcall that accepts its arguments in any
525 ;; data register pair has proven to be the most efficient
526 ;; and most compact way to represent negsi2.
527 (define_insn "negsi2"
528 [(set (match_operand:SI 0 "register_operand" "=d")
529 (neg:SI (match_operand:SI 1 "register_operand" "0")))]
532 [(set_attr "cc" "clobber")])
534 ;; ----------------------------------------------------------------------
535 ;; MULTIPLY INSTRUCTIONS
536 ;; ----------------------------------------------------------------------
538 ;; The mn10200 has HIxHI->SI widening multiply, but we get _severe_
539 ;; code density regressions if we enable such a pattern.
541 (define_insn "mulhi3"
542 [(set (match_operand:HI 0 "general_operand" "=d")
543 (mult:HI (match_operand:HI 1 "general_operand" "%0")
544 (match_operand:HI 2 "general_operand" "d")))]
547 [(set_attr "cc" "set_zn")])
549 (define_insn "udivmodhi4"
550 [(set (match_operand:HI 0 "general_operand" "=d")
551 (udiv:HI (match_operand:HI 1 "general_operand" "0")
552 (match_operand:HI 2 "general_operand" "d")))
553 (set (match_operand:HI 3 "general_operand" "=&d")
554 (umod:HI (match_dup 1) (match_dup 2)))]
559 output_asm_insn (\"mov %0,mdr\", &zero_dreg);
561 output_asm_insn (\"sub %3,%3\;mov %3,mdr\", operands);
563 if (find_reg_note (insn, REG_UNUSED, operands[3]))
564 return \"divu %2,%0\";
566 return \"divu %2,%0\;mov mdr,%3\";
568 [(set_attr "cc" "set_zn")])
571 ;; ----------------------------------------------------------------------
573 ;; ----------------------------------------------------------------------
575 (define_insn "andhi3"
576 [(set (match_operand:HI 0 "general_operand" "=d,d")
577 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
578 (match_operand:HI 2 "general_operand" "M,di")))]
582 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
583 return \"extxbu %0\";
584 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x7fff)
585 return \"add %0,%0\;lsr %0\";
586 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xfffe)
587 return \"lsr %0\;add %0,%0\";
588 return \"and %2,%0\";
590 [(set_attr "cc" "none_0hit,set_znv")])
592 ;; This expander + pattern exist only to allow trampolines to be aligned
594 (define_expand "andpsi3"
595 [(set (match_operand:PSI 0 "general_operand" "")
596 (and:PSI (match_operand:PSI 1 "general_operand" "")
597 (match_operand:PSI 2 "const_int_operand" "")))]
601 if (GET_CODE (operands[2]) != CONST_INT
602 || (INTVAL (operands[2]) & 0xff0000) != 0xff0000)
607 [(set (match_operand:PSI 0 "general_operand" "=d")
608 (and:PSI (match_operand:PSI 1 "general_operand" "%0")
609 (match_operand:PSI 2 "const_int_operand" "i")))]
610 "GET_CODE (operands[2]) == CONST_INT
611 && (INTVAL (operands[2]) & 0xff0000) == 0xff0000"
613 [(set_attr "cc" "clobber")])
615 ;; ----------------------------------------------------------------------
617 ;; ----------------------------------------------------------------------
619 (define_insn "iorhi3"
620 [(set (match_operand:HI 0 "general_operand" "=d")
621 (ior:HI (match_operand:HI 1 "general_operand" "%0")
622 (match_operand:HI 2 "general_operand" "di")))]
625 [(set_attr "cc" "set_znv")])
627 ;; ----------------------------------------------------------------------
629 ;; ----------------------------------------------------------------------
631 (define_insn "xorhi3"
632 [(set (match_operand:HI 0 "general_operand" "=d")
633 (xor:HI (match_operand:HI 1 "general_operand" "%0")
634 (match_operand:HI 2 "general_operand" "di")))]
637 [(set_attr "cc" "set_znv")])
639 ;; ----------------------------------------------------------------------
641 ;; ----------------------------------------------------------------------
643 (define_insn "one_cmplhi2"
644 [(set (match_operand:HI 0 "general_operand" "=d")
645 (not:HI (match_operand:HI 1 "general_operand" "0")))]
648 [(set_attr "cc" "set_znv")])
651 ;; -----------------------------------------------------------------
653 ;; -----------------------------------------------------------------
655 ;; These clears a constant set of bits in memory or in a register.
656 ;; We must support register destinations to make reload happy.
658 [(set (match_operand:QI 0 "general_operand" "+R,d")
660 (and:HI (subreg:HI (match_dup 0) 0)
661 (match_operand 1 "const_int_operand" "")) 0))
662 (clobber (match_scratch:HI 2 "=&d,X"))]
665 mov %N1,%2\;bclr %2,%0
667 [(set_attr "cc" "clobber")])
669 ;; This clears a variable set of bits in memory or in a register.
671 [(set (match_operand:QI 0 "general_operand" "+R,d")
673 (and:HI (subreg:HI (match_dup 0) 0)
674 (not:HI (match_operand:HI 1 "general_operand" "d,d"))) 0))
675 (clobber (match_scratch:HI 2 "=X,&d"))]
679 mov %1,%2\;not %2\;and %2,%0"
680 [(set_attr "cc" "clobber")])
683 [(set (match_operand:QI 0 "general_operand" "+R,d")
685 (and:HI (not:HI (match_operand:HI 1 "general_operand" "d,d"))
686 (subreg:HI (match_dup 0) 0)) 0))
687 (clobber (match_scratch:HI 2 "=X,&d"))]
691 mov %1,%2\;not %2\;and %2,%0"
692 [(set_attr "cc" "clobber")])
694 ;; These set bits in memory.
696 [(set (match_operand:QI 0 "general_operand" "+R,d")
698 (ior:HI (subreg:HI (match_dup 0) 0)
699 (match_operand:HI 1 "general_operand" "d,d")) 0))]
704 [(set_attr "cc" "clobber")])
707 [(set (match_operand:QI 0 "general_operand" "+R,d")
709 (ior:HI (match_operand:HI 1 "general_operand" "d,d")
710 (subreg:HI (match_dup 0) 0)) 0))]
715 [(set_attr "cc" "clobber")])
717 ;; Not any shorter/faster than using cmp, but it might save a
718 ;; register if the result of the AND isn't ever used.
722 (zero_extract:HI (match_operand:HI 0 "general_operand" "d")
723 (match_operand 1 "const_int_operand" "")
724 (match_operand 2 "const_int_operand" "")))]
728 int len = INTVAL (operands[1]);
729 int bit = INTVAL (operands[2]);
740 xoperands[0] = operands[0];
741 xoperands[1] = GEN_INT (mask);
742 output_asm_insn (\"btst %1,%0\", xoperands);
745 [(set_attr "cc" "clobber")])
748 [(set (cc0) (and:HI (match_operand:HI 0 "general_operand" "d")
749 (match_operand:HI 1 "const_int_operand" "i")))]
752 [(set_attr "cc" "clobber")])
755 ;; ----------------------------------------------------------------------
757 ;; ----------------------------------------------------------------------
759 ;; Conditional jump instructions
763 (if_then_else (le (cc0)
765 (label_ref (match_operand 0 "" ""))
770 (define_expand "bleu"
772 (if_then_else (leu (cc0)
774 (label_ref (match_operand 0 "" ""))
781 (if_then_else (ge (cc0)
783 (label_ref (match_operand 0 "" ""))
788 (define_expand "bgeu"
790 (if_then_else (geu (cc0)
792 (label_ref (match_operand 0 "" ""))
799 (if_then_else (lt (cc0)
801 (label_ref (match_operand 0 "" ""))
806 (define_expand "bltu"
808 (if_then_else (ltu (cc0)
810 (label_ref (match_operand 0 "" ""))
817 (if_then_else (gt (cc0)
819 (label_ref (match_operand 0 "" ""))
824 (define_expand "bgtu"
826 (if_then_else (gtu (cc0)
828 (label_ref (match_operand 0 "" ""))
835 (if_then_else (eq (cc0)
837 (label_ref (match_operand 0 "" ""))
844 (if_then_else (ne (cc0)
846 (label_ref (match_operand 0 "" ""))
853 (if_then_else (match_operator 1 "comparison_operator"
854 [(cc0) (const_int 0)])
855 (label_ref (match_operand 0 "" ""))
860 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
861 && (GET_CODE (operands[1]) == GT
862 || GET_CODE (operands[1]) == GE
863 || GET_CODE (operands[1]) == LE
864 || GET_CODE (operands[1]) == LT))
867 if (GET_MODE (SET_SRC (PATTERN (PREV_INSN (insn)))) == PSImode)
872 [(set_attr "cc" "none")])
876 (if_then_else (match_operator 1 "comparison_operator"
877 [(cc0) (const_int 0)])
879 (label_ref (match_operand 0 "" ""))))]
883 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
884 && (GET_CODE (operands[1]) == GT
885 || GET_CODE (operands[1]) == GE
886 || GET_CODE (operands[1]) == LE
887 || GET_CODE (operands[1]) == LT))
890 if (GET_MODE (SET_SRC (PATTERN (PREV_INSN (insn)))) == PSImode)
895 [(set_attr "cc" "none")])
899 (label_ref (match_operand 0 "" "")))]
902 [(set_attr "cc" "none")])
904 (define_insn "indirect_jump"
905 [(set (pc) (match_operand:PSI 0 "register_operand" "a"))]
908 [(set_attr "cc" "none")])
910 (define_insn "tablejump"
911 [(set (pc) (match_operand:PSI 0 "register_operand" "a"))
912 (use (label_ref (match_operand 1 "" "")))]
915 [(set_attr "cc" "none")])
917 ;; Call subroutine with no return value.
919 (define_expand "call"
920 [(call (match_operand:QI 0 "general_operand" "")
921 (match_operand:HI 1 "general_operand" ""))]
925 if (! call_address_operand (XEXP (operands[0], 0), VOIDmode))
926 XEXP (operands[0], 0) = force_reg (PSImode, XEXP (operands[0], 0));
927 emit_call_insn (gen_call_internal (XEXP (operands[0], 0), operands[1]));
931 (define_insn "call_internal"
932 [(call (mem:QI (match_operand:PSI 0 "call_address_operand" "aS"))
933 (match_operand:HI 1 "general_operand" "g"))]
936 [(set_attr "cc" "clobber")])
938 ;; Call subroutine, returning value in operand 0
939 ;; (which must be a hard register).
941 (define_expand "call_value"
942 [(set (match_operand 0 "" "")
943 (call (match_operand:QI 1 "general_operand" "")
944 (match_operand:HI 2 "general_operand" "")))]
948 if (! call_address_operand (XEXP (operands[1], 0), VOIDmode))
949 XEXP (operands[1], 0) = force_reg (PSImode, XEXP (operands[1], 0));
950 emit_call_insn (gen_call_value_internal (operands[0],
951 XEXP (operands[1], 0),
956 (define_insn "call_value_internal"
957 [(set (match_operand 0 "" "=da")
958 (call (mem:QI (match_operand:PSI 1 "call_address_operand" "aS"))
959 (match_operand:HI 2 "general_operand" "g")))]
962 [(set_attr "cc" "clobber")])
964 (define_expand "untyped_call"
965 [(parallel [(call (match_operand 0 "" "")
967 (match_operand 1 "" "")
968 (match_operand 2 "" "")])]
974 emit_call_insn (gen_call (operands[0], const0_rtx));
976 for (i = 0; i < XVECLEN (operands[2], 0); i++)
978 rtx set = XVECEXP (operands[2], 0, i);
979 emit_move_insn (SET_DEST (set), SET_SRC (set));
988 [(set_attr "cc" "none")])
990 ;; ----------------------------------------------------------------------
991 ;; EXTEND INSTRUCTIONS
992 ;; ----------------------------------------------------------------------
994 (define_insn "zero_extendqihi2"
995 [(set (match_operand:HI 0 "general_operand" "=d,d,d")
997 (match_operand:QI 1 "general_operand" "0,di,m")))]
1001 mov %1,%0\;extxbu %0
1003 [(set_attr "cc" "none_0hit")])
1005 (define_insn "zero_extendqipsi2"
1006 [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
1008 (match_operand:QI 1 "general_operand" "0,di,m")))]
1012 mov %1,%0\;extxbu %0
1014 [(set_attr "cc" "none_0hit")])
1016 (define_insn "zero_extendqisi2"
1017 [(set (match_operand:SI 0 "general_operand" "=d,d,d")
1019 (match_operand:QI 1 "general_operand" "0,di,m")))]
1022 extxbu %L0\;sub %H0,%H0
1023 mov %1,%L0\;extxbu %L0\;sub %H0,%H0
1024 movbu %1,%L0\;sub %H0,%H0"
1025 [(set_attr "cc" "clobber")])
1027 (define_insn "zero_extendhipsi2"
1028 [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
1030 (match_operand:HI 1 "general_operand" "0,di,m")))]
1035 mov %1,%0\;extxu %0"
1036 [(set_attr "cc" "none_0hit")])
1038 (define_insn "zero_extendhisi2"
1039 [(set (match_operand:SI 0 "general_operand" "=d,d")
1041 (match_operand:HI 1 "general_operand" "0,dim")))]
1045 mov %1,%L0\;sub %H0,%H0"
1046 [(set_attr "cc" "clobber,clobber")])
1048 ;; The last alternative is necessary because the second operand might
1049 ;; have been the frame pointer. The frame pointer would get replaced
1050 ;; by (plus (stack_pointer) (const_int)).
1052 ;; Reload would think that it only needed a PSImode register in
1053 ;; push_reload and at the start of allocate_reload_regs. However,
1054 ;; at the end of allocate_reload_reg it would realize that the
1055 ;; reload register must also be valid for SImode, and if it was
1056 ;; not valid reload would abort.
1057 (define_insn "zero_extendpsisi2"
1058 [(set (match_operand:SI 0 "register_operand" "=d,?d,?*d,?*d")
1059 (zero_extend:SI (match_operand:PSI 1 "extendpsi_operand"
1063 mov %L1,%L0\;movbu %H1,%H0
1064 jsr ___zero_extendpsisi2_%0
1065 mov %1,%L0\;jsr ___zero_extendpsisi2_%0
1066 mov a3,%L0\;add %Z1,%L0\;jsr ___zero_extendpsisi2_%0"
1067 [(set_attr "cc" "clobber")])
1069 ;;- sign extension instructions
1071 (define_insn "extendqihi2"
1072 [(set (match_operand:HI 0 "general_operand" "=d,d,d")
1074 (match_operand:QI 1 "general_operand" "0,di,m")))]
1078 if (which_alternative == 0)
1079 return \"extxb %0\";
1080 else if (which_alternative == 1)
1081 return \"mov %1,%0\;extxb %0\";
1082 else if (GET_CODE (XEXP (operands[1], 0)) == REG)
1083 return \"movbu %1,%0\;extxb %0\";
1085 return \"movb %1,%0\";
1087 [(set_attr "cc" "none_0hit")])
1089 (define_insn "extendqipsi2"
1090 [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
1092 (match_operand:QI 1 "general_operand" "0,di,m")))]
1096 if (which_alternative == 0)
1097 return \"extxb %0\";
1098 else if (which_alternative == 1)
1099 return \"mov %1,%0\;extxb %0\";
1100 else if (GET_CODE (XEXP (operands[1], 0)) == REG)
1101 return \"movbu %1,%0\;extxb %0\";
1103 return \"movb %1,%0\";
1105 [(set_attr "cc" "none_0hit")])
1107 (define_insn "extendqisi2"
1108 [(set (match_operand:SI 0 "general_operand" "=d,d,d")
1110 (match_operand:QI 1 "general_operand" "0,di,m")))]
1114 if (which_alternative == 0)
1115 return \"extxb %L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\";
1116 else if (which_alternative == 1)
1117 return \"mov %1,%L0\;extxb %L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\";
1118 else if (GET_CODE (XEXP (operands[1], 0)) == REG)
1119 return \"movbu %1,%L0\;extxb %L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\";
1121 return \"movb %1,%L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0\";
1123 [(set_attr "cc" "clobber")])
1125 (define_insn "extendhipsi2"
1126 [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
1128 (match_operand:HI 1 "general_operand" "0,di,m")))]
1134 [(set_attr "cc" "none_0hit")])
1136 (define_insn "extendhisi2"
1137 [(set (match_operand:SI 0 "general_operand" "=d,d,d")
1139 (match_operand:HI 1 "general_operand" "0,di,m")))]
1142 mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0
1143 mov %1,%L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0
1144 mov %1,%L0\;mov %L0,%H0\;add %H0,%H0\;subc %H0,%H0"
1145 [(set_attr "cc" "clobber")])
1147 ;; The last alternative is necessary because the second operand might
1148 ;; have been the frame pointer. The frame pointer would get replaced
1149 ;; by (plus (stack_pointer) (const_int)).
1151 ;; Reload would think that it only needed a PSImode register in
1152 ;; push_reload and at the start of allocate_reload_regs. However,
1153 ;; at the end of allocate_reload_reg it would realize that the
1154 ;; reload register must also be valid for SImode, and if it was
1155 ;; not valid reload would abort.
1156 (define_insn "extendpsisi2"
1157 [(set (match_operand:SI 0 "general_operand" "=d,?d,?*d,?*d")
1158 (sign_extend:SI (match_operand:PSI 1 "extendpsi_operand"
1162 mov %L1,%L0\;movb %H1,%H0
1163 jsr ___sign_extendpsisi2_%0
1164 mov %1,%L0\;jsr ___sign_extendpsisi2_%0
1165 mov a3,%L0\;add %Z1,%L0\;jsr ___sign_extendpsisi2_%0"
1166 [(set_attr "cc" "clobber")])
1168 (define_insn "truncsipsi2"
1169 [(set (match_operand:PSI 0 "general_operand" "=a,?d,?*d,da")
1170 (truncate:PSI (match_operand:SI 1 "psimode_truncation_operand" "m,?m,?*d,i")))]
1175 jsr ___truncsipsi2_%1_%0
1177 [(set_attr "cc" "clobber")])
1180 ;; Combine should be simplifying this stuff, but isn't.
1183 [(set (match_operand:SI 0 "general_operand" "=d,d,d")
1185 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,di,m"))))]
1188 extxbu %L0\;sub %H0,%H0
1189 mov %1,%L0\;extxbu %L0\;sub %H0,%H0
1190 movbu %1,%L0\;sub %H0,%H0"
1191 [(set_attr "cc" "clobber")])
1194 [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
1196 (sign_extend:SI (match_operand:QI 1 "general_operand" "0,di,m"))))]
1200 if (which_alternative == 0)
1201 return \"extxb %0\";
1202 else if (which_alternative == 1)
1203 return \"mov %1,%0\;extxb %0\";
1204 else if (GET_CODE (XEXP (operands[1], 0)) == REG)
1205 return \"movbu %1,%0\;extxb %0\";
1207 return \"movb %1,%0\";
1209 [(set_attr "cc" "none_0hit")])
1212 [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
1214 (sign_extend:SI (match_operand:HI 1 "general_operand" "0,di,m"))))]
1220 [(set_attr "cc" "none_0hit")])
1223 [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
1226 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,di,m")))))]
1230 mov %1,%0\;extxbu %0
1232 [(set_attr "cc" "none_0hit")])
1235 [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
1237 (zero_extend:SI (match_operand:HI 1 "general_operand" "0,di,m"))))]
1242 mov %1,%0\;extxu %0"
1243 [(set_attr "cc" "none_0hit")])
1246 [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
1248 (zero_extend:SI (match_operand:QI 1 "general_operand" "0,di,m"))))]
1252 mov %1,%0\;extxbu %0
1254 [(set_attr "cc" "none_0hit")])
1256 ;; ----------------------------------------------------------------------
1258 ;; ----------------------------------------------------------------------
1260 ;; If the shift count is small, we expand it into several single bit
1261 ;; shift insns. Otherwise we expand into a generic shift insn which
1262 ;; handles larger shift counts, shift by variable amounts, etc.
1263 (define_expand "ashlhi3"
1264 [(set (match_operand:HI 0 "general_operand" "")
1265 (ashift:HI (match_operand:HI 1 "general_operand" "")
1266 (match_operand:HI 2 "general_operand" "")))]
1270 /* This is an experiment to see if exposing more of the underlying
1271 operations results in better code. */
1272 if (GET_CODE (operands[2]) == CONST_INT
1273 && INTVAL (operands[2]) <= 4)
1275 int count = INTVAL (operands[2]);
1276 emit_move_insn (operands[0], operands[1]);
1279 emit_insn (gen_rtx_SET (HImode, operands[0],
1280 gen_rtx_ASHIFT (HImode,
1281 operands[0], GEN_INT (1))));
1288 expand_a_shift (HImode, ASHIFT, operands);
1295 [(set (match_operand:HI 0 "general_operand" "=d")
1296 (ashift:HI (match_operand:HI 1 "general_operand" "0")
1300 [(set_attr "cc" "set_zn")])
1302 (define_expand "lshrhi3"
1303 [(set (match_operand:HI 0 "general_operand" "")
1304 (lshiftrt:HI (match_operand:HI 1 "general_operand" "")
1305 (match_operand:HI 2 "general_operand" "")))]
1309 /* This is an experiment to see if exposing more of the underlying
1310 operations results in better code. */
1311 if (GET_CODE (operands[2]) == CONST_INT
1312 && INTVAL (operands[2]) <= 4)
1314 int count = INTVAL (operands[2]);
1315 emit_move_insn (operands[0], operands[1]);
1318 emit_insn (gen_rtx_SET (HImode, operands[0],
1319 gen_rtx_LSHIFTRT (HImode,
1328 expand_a_shift (HImode, LSHIFTRT, operands);
1333 ;; LSHIFTRT one bit.
1335 [(set (match_operand:HI 0 "general_operand" "=d")
1336 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1340 [(set_attr "cc" "set_znv")])
1342 (define_expand "ashrhi3"
1343 [(set (match_operand:HI 0 "general_operand" "")
1344 (ashiftrt:HI (match_operand:HI 1 "general_operand" "")
1345 (match_operand:HI 2 "general_operand" "")))]
1349 /* This is an experiment to see if exposing more of the underlying
1350 operations results in better code. */
1351 if (GET_CODE (operands[2]) == CONST_INT
1352 && INTVAL (operands[2]) <= 4)
1354 int count = INTVAL (operands[2]);
1355 emit_move_insn (operands[0], operands[1]);
1358 emit_insn (gen_rtx_SET (HImode, operands[0],
1359 gen_rtx_ASHIFTRT (HImode, operands[0],
1367 expand_a_shift (HImode, ASHIFTRT, operands);
1372 ;; ASHIFTRT one bit.
1374 [(set (match_operand:HI 0 "general_operand" "=d")
1375 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1379 [(set_attr "cc" "set_znv")])
1381 ;; And the general HImode shift pattern. Handles both shift by constants
1382 ;; and shift by variable counts.
1384 [(set (match_operand:HI 0 "general_operand" "=d,d")
1385 (match_operator:HI 3 "nshift_operator"
1386 [ (match_operand:HI 1 "general_operand" "0,0")
1387 (match_operand:HI 2 "general_operand" "KL,dan")]))
1388 (clobber (match_scratch:HI 4 "=X,&d"))]
1390 "* return emit_a_shift (insn, operands);"
1391 [(set_attr "cc" "clobber")])
1393 ;; We expect only ASHIFT with constant shift counts to be common for
1394 ;; PSImode, so we optimize just that case. For all other cases we
1395 ;; extend the value to SImode and perform the shift in SImode.
1396 (define_expand "ashlpsi3"
1397 [(set (match_operand:PSI 0 "general_operand" "")
1398 (ashift:PSI (match_operand:PSI 1 "general_operand" "")
1399 (match_operand:HI 2 "general_operand" "")))]
1403 /* This is an experiment to see if exposing more of the underlying
1404 operations results in better code. */
1405 if (GET_CODE (operands[2]) == CONST_INT
1406 && INTVAL (operands[2]) <= 7)
1408 int count = INTVAL (operands[2]);
1409 emit_move_insn (operands[0], operands[1]);
1412 emit_insn (gen_rtx_SET (PSImode, operands[0],
1413 gen_rtx_ASHIFT (PSImode,
1414 operands[0], GEN_INT (1))));
1421 expand_a_shift (PSImode, ASHIFT, operands);
1428 [(set (match_operand:PSI 0 "general_operand" "=d")
1429 (ashift:PSI (match_operand:PSI 1 "general_operand" "0")
1433 [(set_attr "cc" "set_zn")])
1435 (define_expand "lshrpsi3"
1436 [(set (match_operand:PSI 0 "general_operand" "")
1437 (lshiftrt:PSI (match_operand:PSI 1 "general_operand" "")
1438 (match_operand:HI 2 "general_operand" "")))]
1442 rtx reg = gen_reg_rtx (SImode);
1444 emit_insn (gen_zero_extendpsisi2 (reg, operands[1]));
1445 reg = expand_binop (SImode, lshr_optab, reg,
1446 operands[2], reg, 1, OPTAB_WIDEN);
1447 emit_insn (gen_truncsipsi2 (operands[0], reg));
1451 (define_expand "ashrpsi3"
1452 [(set (match_operand:PSI 0 "general_operand" "")
1453 (ashiftrt:PSI (match_operand:PSI 1 "general_operand" "")
1454 (match_operand:HI 2 "general_operand" "")))]
1458 rtx reg = gen_reg_rtx (SImode);
1460 emit_insn (gen_extendpsisi2 (reg, operands[1]));
1461 reg = expand_binop (SImode, ashr_optab, reg,
1462 operands[2], reg, 0, OPTAB_WIDEN);
1463 emit_insn (gen_truncsipsi2 (operands[0], reg));
1467 (define_expand "ashlsi3"
1468 [(set (match_operand:SI 0 "register_operand" "")
1469 (ashift:SI (match_operand:SI 1 "nonmemory_operand" "")
1470 (match_operand:HI 2 "general_operand" "")))]
1474 /* For small shifts, just emit a series of single bit shifts inline.
1476 For other constant shift counts smaller than a word or non-constant
1477 shift counts we call out to a library call during RTL generation time;
1478 after RTL generation time we allow optabs.c to open code the operation.
1479 See comments in addsi3/subsi3 expanders.
1481 Otherwise we allow optabs.c to open code the operation. */
1482 if (GET_CODE (operands[2]) == CONST_INT
1483 && (INTVAL (operands[2]) <= 3))
1485 int count = INTVAL (operands[2]);
1486 emit_move_insn (operands[0], operands[1]);
1489 emit_insn (gen_rtx_SET (SImode, operands[0],
1490 gen_rtx_ASHIFT (SImode,
1491 operands[0], GEN_INT (1))));
1496 else if (rtx_equal_function_value_matters
1497 && (GET_CODE (operands[2]) != CONST_INT
1498 || INTVAL (operands[2]) <= 15))
1503 ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__ashlsi3\"),
1504 NULL_RTX, 1, SImode, 2, operands[1],
1505 SImode, operands[2], HImode);
1506 insns = get_insns ();
1508 emit_libcall_block (insns, operands[0], ret,
1509 gen_rtx_ASHIFT (SImode, operands[1], operands[2]));
1518 [(set (match_operand:SI 0 "general_operand" "=d")
1519 (ashift:SI (match_operand:SI 1 "general_operand" "0")
1522 "add %L0,%L0\;addc %H0,%H0"
1523 [(set_attr "cc" "clobber")])
1525 (define_expand "lshrsi3"
1526 [(set (match_operand:SI 0 "register_operand" "")
1527 (lshiftrt:SI (match_operand:SI 1 "general_operand" "")
1528 (match_operand:HI 2 "general_operand" "")))]
1532 /* For small shifts, just emit a series of single bit shifts inline.
1534 For other constant shift counts smaller than a word or non-constant
1535 shift counts we call out to a library call during RTL generation time;
1536 after RTL generation time we allow optabs.c to open code the operation.
1537 See comments in addsi3/subsi3 expanders.
1539 Otherwise we allow optabs.c to open code the operation. */
1540 if (GET_CODE (operands[2]) == CONST_INT
1541 && (INTVAL (operands[2]) <= 2))
1543 int count = INTVAL (operands[2]);
1544 emit_move_insn (operands[0], operands[1]);
1547 emit_insn (gen_rtx_SET (SImode, operands[0],
1548 gen_rtx_LSHIFTRT (SImode, operands[0],
1554 else if (rtx_equal_function_value_matters
1555 && (GET_CODE (operands[2]) != CONST_INT
1556 || INTVAL (operands[2]) <= 15))
1561 ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__lshrsi3\"),
1562 NULL_RTX, 1, SImode, 2, operands[1],
1563 SImode, operands[2], HImode);
1564 insns = get_insns ();
1566 emit_libcall_block (insns, operands[0], ret,
1567 gen_rtx_LSHIFTRT (SImode, operands[1], operands[2]));
1574 ;; LSHIFTRT one bit.
1576 [(set (match_operand:SI 0 "general_operand" "=d")
1577 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1581 [(set_attr "cc" "clobber")])
1583 (define_expand "ashrsi3"
1584 [(set (match_operand:SI 0 "register_operand" "")
1585 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1586 (match_operand:HI 2 "general_operand" "")))]
1590 /* For small shifts, just emit a series of single bit shifts inline.
1592 For other constant shift counts smaller than a word or non-constant
1593 shift counts we call out to a library call during RTL generation time;
1594 after RTL generation time we allow optabs.c to open code the operation.
1595 See comments in addsi3/subsi3 expanders.
1597 Otherwise we allow optabs.c to open code the operation. */
1598 if (GET_CODE (operands[2]) == CONST_INT
1599 && (INTVAL (operands[2]) <= 2))
1601 int count = INTVAL (operands[2]);
1602 emit_move_insn (operands[0], operands[1]);
1605 emit_insn (gen_rtx_SET (SImode, operands[0],
1606 gen_rtx_ASHIFTRT (SImode, operands[0],
1612 else if (rtx_equal_function_value_matters
1613 && (GET_CODE (operands[2]) != CONST_INT
1614 || INTVAL (operands[2]) <= 15))
1619 ret = emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__ashrsi3\"),
1620 NULL_RTX, 1, SImode, 2, operands[1],
1621 SImode, operands[2], HImode);
1622 insns = get_insns ();
1624 emit_libcall_block (insns, operands[0], ret,
1625 gen_rtx_ASHIFTRT (SImode, operands[1], operands[2]));
1632 ;; ASHIFTRT one bit.
1634 [(set (match_operand:SI 0 "general_operand" "=d")
1635 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1639 [(set_attr "cc" "clobber")])
1641 ;; ----------------------------------------------------------------------
1643 ;; ----------------------------------------------------------------------
1645 ;; The mn102 series does not have floating point instructions, but since
1646 ;; FP values are held in integer regs, we can clear the high bit easily
1647 ;; which gives us an efficient inline floating point absolute value.
1649 ;; Similarly for negation of a FP value.
1652 (define_expand "abssf2"
1653 [(set (match_operand:SF 0 "register_operand" "")
1654 (abs:SF (match_operand:SF 1 "register_operand" "")))]
1658 rtx target, result, insns;
1661 target = operand_subword (operands[0], 1, 1, SFmode);
1662 result = expand_binop (HImode, and_optab,
1663 operand_subword_force (operands[1], 1, SFmode),
1664 GEN_INT(0x7fff), target, 0, OPTAB_WIDEN);
1669 if (result != target)
1670 emit_move_insn (result, target);
1672 emit_move_insn (operand_subword (operands[0], 0, 1, SFmode),
1673 operand_subword_force (operands[1], 0, SFmode));
1675 insns = get_insns ();
1678 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
1682 (define_expand "negsf2"
1683 [(set (match_operand:SF 0 "register_operand" "")
1684 (neg:SF (match_operand:SF 1 "register_operand" "")))]
1688 rtx target, result, insns;
1691 target = operand_subword (operands[0], 1, 1, SFmode);
1692 result = expand_binop (HImode, xor_optab,
1693 operand_subword_force (operands[1], 1, SFmode),
1694 GEN_INT(-0x8000), target, 0, OPTAB_WIDEN);
1699 if (result != target)
1700 emit_move_insn (result, target);
1702 emit_move_insn (operand_subword (operands[0], 0, 1, SFmode),
1703 operand_subword_force (operands[1], 0, SFmode));
1705 insns = get_insns ();
1708 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
1712 ;; ----------------------------------------------------------------------
1713 ;; PROLOGUE/EPILOGUE
1714 ;; ----------------------------------------------------------------------
1715 (define_expand "prologue"
1718 "expand_prologue (); DONE;")
1720 (define_insn "outline_prologue_call"
1724 [(set_attr "cc" "clobber")])
1726 (define_expand "epilogue"
1735 (define_insn "outline_epilogue_call_a0"
1738 "jsr ___epilogue_a0"
1739 [(set_attr "cc" "clobber")])
1741 (define_insn "outline_epilogue_call_d0"
1744 "jsr ___epilogue_d0"
1745 [(set_attr "cc" "clobber")])
1747 (define_insn "outline_epilogue_jump"
1751 "jmp ___epilogue_noreturn"
1752 [(set_attr "cc" "clobber")])
1754 (define_insn "return"
1756 "reload_completed && total_frame_size () == 0
1757 && !current_function_needs_context"
1760 rtx next = next_active_insn (insn);
1763 && GET_CODE (next) == JUMP_INSN
1764 && GET_CODE (PATTERN (next)) == RETURN)
1768 [(set_attr "cc" "clobber")])
1770 (define_insn "return_internal"
1775 [(set_attr "cc" "clobber")])
1777 ;; These are special combiner patterns to improve array/pointer accesses.
1779 ;; A typical sequence involves extending an integer/char, shifting it left
1780 ;; a few times, then truncating the value to PSImode.
1782 ;; This first pattern combines the shifting & truncation operations, by
1783 ;; itself it is a win because the shifts end up occurring in PSImode instead
1784 ;; of SImode. However, it has the secondary effect of giving us the
1785 ;; opportunity to match patterns which allow us to remove the initial
1786 ;; extension completely, which is a big win.
1788 [(set (match_operand:PSI 0 "general_operand" "=d,d,a,da")
1790 (ashift:SI (match_operand:SI 1 "psimode_truncation_operand" "d,m,m,i")
1791 (match_operand:HI 2 "const_int_operand" "i,i,i,i"))))]
1795 int count = INTVAL (operands[2]);
1796 if (which_alternative == 0)
1797 output_asm_insn (\"jsr ___truncsipsi2_%1_%0\", operands);
1798 else if (which_alternative == 1)
1799 output_asm_insn (\"movx %A1,%0\", operands);
1801 output_asm_insn (\" mov %1,%0\", operands);
1805 output_asm_insn (\"add %0,%0\", operands);
1810 [(set_attr "cc" "clobber")])
1812 ;; Similarly, except that we also have zero/sign extension of the
1813 ;; original operand. */
1815 [(set (match_operand:PSI 0 "general_operand" "=d,d")
1818 (zero_extend:SI (match_operand:HI 1 "general_operand" "0,dim"))
1819 (match_operand:HI 2 "const_int_operand" "i,i"))))]
1823 int count = INTVAL (operands[2]);
1825 /* First extend operand 1 to PSImode. */
1826 if (which_alternative == 0)
1827 output_asm_insn (\"extxu %0\", operands);
1829 output_asm_insn (\"mov %1,%0\;extxu %0\", operands);
1831 /* Now do the shifting. */
1834 output_asm_insn (\"add %0,%0\", operands);
1839 [(set_attr "cc" "clobber")])
1842 [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
1845 (sign_extend:SI (match_operand:HI 1 "general_operand" "0,di,m"))
1846 (match_operand:HI 2 "const_int_operand" "i,i,i"))))]
1850 int count = INTVAL (operands[2]);
1852 /* First extend operand 1 to PSImode. */
1853 if (which_alternative == 0)
1854 output_asm_insn (\"extx %0\", operands);
1855 else if (which_alternative == 1)
1856 output_asm_insn (\"mov %1,%0\;extx %0\", operands);
1858 output_asm_insn (\"mov %1,%0\", operands);
1860 /* Now do the shifting. */
1863 output_asm_insn (\"add %0,%0\", operands);
1868 [(set_attr "cc" "clobber")])
1871 [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
1875 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,di,m")))
1876 (match_operand:HI 2 "const_int_operand" "i,i,i"))))]
1880 int count = INTVAL (operands[2]);
1882 /* First extend operand 1 to PSImode. */
1883 if (which_alternative == 0)
1884 output_asm_insn (\"extxbu %0\", operands);
1885 else if (which_alternative == 1)
1886 output_asm_insn (\"mov %1,%0\;extxbu %0\", operands);
1888 output_asm_insn (\"movbu %1,%0\", operands);
1890 /* Now do the shifting. */
1893 output_asm_insn (\"add %0,%0\", operands);
1898 [(set_attr "cc" "clobber")])
1901 [(set (match_operand:PSI 0 "general_operand" "=d,d,d")
1905 (match_operand:QI 1 "general_operand" "0,di,m"))
1906 (match_operand:HI 2 "const_int_operand" "i,i,i"))))]
1910 int count = INTVAL (operands[2]);
1912 /* First extend operand 1 to PSImode. */
1913 if (which_alternative == 0)
1914 output_asm_insn (\"extxb %0\", operands);
1915 else if (which_alternative == 1)
1916 output_asm_insn (\"mov %1,%0\;extxb %0\", operands);
1917 else if (GET_CODE (XEXP (operands[1], 0)) == REG)
1918 output_asm_insn (\"movbu %1,%0\;extxb %0\", operands);
1920 output_asm_insn (\"movb %1,%0\", operands);
1922 /* Now do the shifting. */
1925 output_asm_insn (\"add %0,%0\", operands);
1930 [(set_attr "cc" "clobber")])
1932 ;; Try to combine consecutive updates of the stack pointer (or any
1933 ;; other register for that matter).
1935 [(set (match_operand:PSI 0 "register_operand" "=da")
1936 (plus:PSI (match_dup 0)
1937 (match_operand 1 "const_int_operand" "")))
1939 (plus:PSI (match_dup 0)
1940 (match_operand 2 "const_int_operand" "")))]
1944 operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]));
1945 return \"add %1,%0\";
1947 [(set_attr "cc" "clobber")])
1950 ;; We had patterns to check eq/ne, but the they don't work because
1951 ;; 0x80000000 + 0x80000000 = 0x0 with a carry out.
1953 ;; The Z flag and C flag would be set, and we have no way to
1954 ;; check for the Z flag set and C flag clear.
1956 ;; This will work on the mn10200 because we can check the ZX flag
1957 ;; if the comparison is in HImode.
1959 [(set (cc0) (match_operand:HI 0 "register_operand" "d"))
1960 (set (pc) (if_then_else (ge (cc0) (const_int 0))
1961 (match_operand 1 "" "")
1963 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
1965 [(set_attr "cc" "clobber")])
1968 [(set (cc0) (match_operand:HI 0 "register_operand" "d"))
1969 (set (pc) (if_then_else (lt (cc0) (const_int 0))
1970 (match_operand 1 "" "")
1972 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
1974 [(set_attr "cc" "clobber")])
1977 [(set (cc0) (match_operand:HI 0 "register_operand" "d"))
1978 (set (pc) (if_then_else (ge (cc0) (const_int 0))
1980 (match_operand 1 "" "")))]
1981 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
1983 [(set_attr "cc" "clobber")])
1986 [(set (cc0) (match_operand:HI 0 "register_operand" "d"))
1987 (set (pc) (if_then_else (lt (cc0) (const_int 0))
1989 (match_operand 1 "" "")))]
1990 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
1992 [(set_attr "cc" "clobber")])
1995 [(set (cc0) (match_operand:PSI 0 "register_operand" "d"))
1996 (set (pc) (if_then_else (ge (cc0) (const_int 0))
1997 (match_operand 1 "" "")
1999 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2000 "add %0,%0\;bccx %1"
2001 [(set_attr "cc" "clobber")])
2004 [(set (cc0) (match_operand:PSI 0 "register_operand" "d"))
2005 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2006 (match_operand 1 "" "")
2008 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2009 "add %0,%0\;bcsx %1"
2010 [(set_attr "cc" "clobber")])
2013 [(set (cc0) (match_operand:PSI 0 "register_operand" "d"))
2014 (set (pc) (if_then_else (ge (cc0) (const_int 0))
2016 (match_operand 1 "" "")))]
2017 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2018 "add %0,%0\;bcsx %1"
2019 [(set_attr "cc" "clobber")])
2022 [(set (cc0) (match_operand:PSI 0 "register_operand" "d"))
2023 (set (pc) (if_then_else (lt (cc0) (const_int 0))
2025 (match_operand 1 "" "")))]
2026 "dead_or_set_p (ins1, operands[0]) && REG_OK_FOR_INDEX_P (operands[0])"
2027 "add %0,%0\;bccx %1"
2028 [(set_attr "cc" "clobber")])
2030 ;; We call out to library routines to perform 32bit addition and subtraction
2031 ;; operations (see addsi3/subsi3 expanders for why). These peepholes catch
2032 ;; the trivial case where the operation could be done with an add;addc or
2033 ;; sub;subc sequence.
2035 [(set (mem:SI (reg:PSI 7)) (reg:SI 2))
2036 (set (reg:SI 0) (call (match_operand:QI 1 "general_operand" "")
2037 (match_operand:HI 2 "general_operand" "")))]
2038 "GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2039 && strcmp (XSTR (XEXP (operands[1], 0), 0), \"__addsi3\") == 0"
2040 "add d2,d0\;addc d3,d1"
2041 [(set_attr "cc" "clobber")])
2044 [(set (mem:SI (reg:PSI 7)) (reg:SI 2))
2045 (set (reg:SI 0) (call (match_operand:QI 1 "general_operand" "")
2046 (match_operand:HI 2 "general_operand" "")))]
2047 "GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
2048 && strcmp (XSTR (XEXP (operands[1], 0), 0), \"__subsi3\") == 0"
2049 "sub d2,d0\;subc d3,d1"
2050 [(set_attr "cc" "clobber")])