1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
5 ;; Changes by Michael Meissner, meissner@osf.org
6 ;; 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 ;; Brendan Eich, brendan@microunity.com.
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 2, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING. If not, write to
23 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 ;; Boston, MA 02110-1301, USA.
27 [(UNSPEC_LOAD_DF_LOW 0)
28 (UNSPEC_LOAD_DF_HIGH 1)
29 (UNSPEC_STORE_DF_HIGH 2)
33 (UNSPEC_EH_RECEIVER 6)
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
53 (UNSPEC_ADDRESS_FIRST 100)
57 ;; For MIPS Paired-Singled Floating Point Instructions.
59 (UNSPEC_MOVE_TF_PS 200)
62 ;; MIPS64/MIPS32R2 alnv.ps
65 ;; MIPS-3D instructions
69 (UNSPEC_CVT_PW_PS 205)
70 (UNSPEC_CVT_PS_PW 206)
78 (UNSPEC_SINGLE_CC 213)
81 ;; MIPS DSP ASE Revision 0.98 3/24/2005
89 (UNSPEC_RADDU_W_QB 307)
91 (UNSPEC_PRECRQ_QB_PH 309)
92 (UNSPEC_PRECRQ_PH_W 310)
93 (UNSPEC_PRECRQ_RS_PH_W 311)
94 (UNSPEC_PRECRQU_S_QB_PH 312)
95 (UNSPEC_PRECEQ_W_PHL 313)
96 (UNSPEC_PRECEQ_W_PHR 314)
97 (UNSPEC_PRECEQU_PH_QBL 315)
98 (UNSPEC_PRECEQU_PH_QBR 316)
99 (UNSPEC_PRECEQU_PH_QBLA 317)
100 (UNSPEC_PRECEQU_PH_QBRA 318)
101 (UNSPEC_PRECEU_PH_QBL 319)
102 (UNSPEC_PRECEU_PH_QBR 320)
103 (UNSPEC_PRECEU_PH_QBLA 321)
104 (UNSPEC_PRECEU_PH_QBRA 322)
110 (UNSPEC_MULEU_S_PH_QBL 328)
111 (UNSPEC_MULEU_S_PH_QBR 329)
112 (UNSPEC_MULQ_RS_PH 330)
113 (UNSPEC_MULEQ_S_W_PHL 331)
114 (UNSPEC_MULEQ_S_W_PHR 332)
115 (UNSPEC_DPAU_H_QBL 333)
116 (UNSPEC_DPAU_H_QBR 334)
117 (UNSPEC_DPSU_H_QBL 335)
118 (UNSPEC_DPSU_H_QBR 336)
119 (UNSPEC_DPAQ_S_W_PH 337)
120 (UNSPEC_DPSQ_S_W_PH 338)
121 (UNSPEC_MULSAQ_S_W_PH 339)
122 (UNSPEC_DPAQ_SA_L_W 340)
123 (UNSPEC_DPSQ_SA_L_W 341)
124 (UNSPEC_MAQ_S_W_PHL 342)
125 (UNSPEC_MAQ_S_W_PHR 343)
126 (UNSPEC_MAQ_SA_W_PHL 344)
127 (UNSPEC_MAQ_SA_W_PHR 345)
135 (UNSPEC_CMPGU_EQ_QB 353)
136 (UNSPEC_CMPGU_LT_QB 354)
137 (UNSPEC_CMPGU_LE_QB 355)
139 (UNSPEC_PACKRL_PH 357)
141 (UNSPEC_EXTR_R_W 359)
142 (UNSPEC_EXTR_RS_W 360)
143 (UNSPEC_EXTR_S_H 361)
151 ;; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006
152 (UNSPEC_ABSQ_S_QB 400)
154 (UNSPEC_ADDU_S_PH 402)
155 (UNSPEC_ADDUH_QB 403)
156 (UNSPEC_ADDUH_R_QB 404)
159 (UNSPEC_CMPGDU_EQ_QB 407)
160 (UNSPEC_CMPGDU_LT_QB 408)
161 (UNSPEC_CMPGDU_LE_QB 409)
162 (UNSPEC_DPA_W_PH 410)
163 (UNSPEC_DPS_W_PH 411)
169 (UNSPEC_MUL_S_PH 417)
170 (UNSPEC_MULQ_RS_W 418)
171 (UNSPEC_MULQ_S_PH 419)
172 (UNSPEC_MULQ_S_W 420)
173 (UNSPEC_MULSA_W_PH 421)
176 (UNSPEC_PRECR_QB_PH 424)
177 (UNSPEC_PRECR_SRA_PH_W 425)
178 (UNSPEC_PRECR_SRA_R_PH_W 426)
181 (UNSPEC_SHRA_R_QB 429)
184 (UNSPEC_SUBU_S_PH 432)
185 (UNSPEC_SUBUH_QB 433)
186 (UNSPEC_SUBUH_R_QB 434)
187 (UNSPEC_ADDQH_PH 435)
188 (UNSPEC_ADDQH_R_PH 436)
190 (UNSPEC_ADDQH_R_W 438)
191 (UNSPEC_SUBQH_PH 439)
192 (UNSPEC_SUBQH_R_PH 440)
194 (UNSPEC_SUBQH_R_W 442)
195 (UNSPEC_DPAX_W_PH 443)
196 (UNSPEC_DPSX_W_PH 444)
197 (UNSPEC_DPAQX_S_W_PH 445)
198 (UNSPEC_DPAQX_SA_W_PH 446)
199 (UNSPEC_DPSQX_S_W_PH 447)
200 (UNSPEC_DPSQX_SA_W_PH 448)
204 (include "predicates.md")
205 (include "constraints.md")
207 ;; ....................
211 ;; ....................
213 (define_attr "got" "unset,xgot_high,load"
214 (const_string "unset"))
216 ;; For jal instructions, this attribute is DIRECT when the target address
217 ;; is symbolic and INDIRECT when it is a register.
218 (define_attr "jal" "unset,direct,indirect"
219 (const_string "unset"))
221 ;; This attribute is YES if the instruction is a jal macro (not a
222 ;; real jal instruction).
224 ;; jal is always a macro for TARGET_CALL_CLOBBERED_GP because it includes
225 ;; an instruction to restore $gp. Direct jals are also macros for
226 ;; flag_pic && !TARGET_ABSOLUTE_ABICALLS because they first load
227 ;; the target address into a register.
228 (define_attr "jal_macro" "no,yes"
229 (cond [(eq_attr "jal" "direct")
230 (symbol_ref "TARGET_CALL_CLOBBERED_GP
231 || (flag_pic && !TARGET_ABSOLUTE_ABICALLS)")
232 (eq_attr "jal" "indirect")
233 (symbol_ref "TARGET_CALL_CLOBBERED_GP")]
234 (const_string "no")))
236 ;; Classification of each insn.
237 ;; branch conditional branch
238 ;; jump unconditional jump
239 ;; call unconditional call
240 ;; load load instruction(s)
241 ;; fpload floating point load
242 ;; fpidxload floating point indexed load
243 ;; store store instruction(s)
244 ;; fpstore floating point store
245 ;; fpidxstore floating point indexed store
246 ;; prefetch memory prefetch (register + offset)
247 ;; prefetchx memory indexed prefetch (register + register)
248 ;; condmove conditional moves
249 ;; mfc transfer from coprocessor
250 ;; mtc transfer to coprocessor
251 ;; mthilo transfer to hi/lo registers
252 ;; mfhilo transfer from hi/lo registers
253 ;; const load constant
254 ;; arith integer arithmetic and logical instructions
255 ;; shift integer shift instructions
256 ;; slt set less than instructions
257 ;; clz the clz and clo instructions
258 ;; trap trap if instructions
259 ;; imul integer multiply 2 operands
260 ;; imul3 integer multiply 3 operands
261 ;; imadd integer multiply-add
262 ;; idiv integer divide
263 ;; fmove floating point register move
264 ;; fadd floating point add/subtract
265 ;; fmul floating point multiply
266 ;; fmadd floating point multiply-add
267 ;; fdiv floating point divide
268 ;; frdiv floating point reciprocal divide
269 ;; frdiv1 floating point reciprocal divide step 1
270 ;; frdiv2 floating point reciprocal divide step 2
271 ;; fabs floating point absolute value
272 ;; fneg floating point negation
273 ;; fcmp floating point compare
274 ;; fcvt floating point convert
275 ;; fsqrt floating point square root
276 ;; frsqrt floating point reciprocal square root
277 ;; frsqrt1 floating point reciprocal square root step1
278 ;; frsqrt2 floating point reciprocal square root step2
279 ;; multi multiword sequence (or user asm statements)
282 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,mfc,mtc,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
283 (cond [(eq_attr "jal" "!unset") (const_string "call")
284 (eq_attr "got" "load") (const_string "load")]
285 (const_string "unknown")))
287 ;; Main data type used by the insn
288 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
289 (const_string "unknown"))
291 ;; Mode for conversion types (fcvt)
292 ;; I2S integer to float single (SI/DI to SF)
293 ;; I2D integer to float double (SI/DI to DF)
294 ;; S2I float to integer (SF to SI/DI)
295 ;; D2I float to integer (DF to SI/DI)
296 ;; D2S double to float single
297 ;; S2D float single to double
299 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
300 (const_string "unknown"))
302 ;; Is this an extended instruction in mips16 mode?
303 (define_attr "extended_mips16" "no,yes"
306 ;; Length of instruction in bytes.
307 (define_attr "length" ""
308 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
309 ;; If a branch is outside this range, we have a choice of two
310 ;; sequences. For PIC, an out-of-range branch like:
315 ;; becomes the equivalent of:
324 ;; where the load address can be up to three instructions long
327 ;; The non-PIC case is similar except that we use a direct
328 ;; jump instead of an la/jr pair. Since the target of this
329 ;; jump is an absolute 28-bit bit address (the other bits
330 ;; coming from the address of the delay slot) this form cannot
331 ;; cross a 256MB boundary. We could provide the option of
332 ;; using la/jr in this case too, but we do not do so at
335 ;; Note that this value does not account for the delay slot
336 ;; instruction, whose length is added separately. If the RTL
337 ;; pattern has no explicit delay slot, mips_adjust_insn_length
338 ;; will add the length of the implicit nop. The values for
339 ;; forward and backward branches will be different as well.
340 (eq_attr "type" "branch")
341 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
342 (le (minus (pc) (match_dup 1)) (const_int 131068)))
344 (ne (symbol_ref "flag_pic") (const_int 0))
348 (eq_attr "got" "load")
350 (eq_attr "got" "xgot_high")
353 (eq_attr "type" "const")
354 (symbol_ref "mips_const_insns (operands[1]) * 4")
355 (eq_attr "type" "load,fpload")
356 (symbol_ref "mips_fetch_insns (operands[1]) * 4")
357 (eq_attr "type" "store,fpstore")
358 (symbol_ref "mips_fetch_insns (operands[0]) * 4")
360 ;; In the worst case, a call macro will take 8 instructions:
362 ;; lui $25,%call_hi(FOO)
364 ;; lw $25,%call_lo(FOO)($25)
370 (eq_attr "jal_macro" "yes")
373 (and (eq_attr "extended_mips16" "yes")
374 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
377 ;; Various VR4120 errata require a nop to be inserted after a macc
378 ;; instruction. The assembler does this for us, so account for
379 ;; the worst-case length here.
380 (and (eq_attr "type" "imadd")
381 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
384 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
385 ;; the result of the second one is missed. The assembler should work
386 ;; around this by inserting a nop after the first dmult.
387 (and (eq_attr "type" "imul,imul3")
388 (and (eq_attr "mode" "DI")
389 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
392 (eq_attr "type" "idiv")
393 (symbol_ref "mips_idiv_insns () * 4")
396 ;; Attribute describing the processor. This attribute must match exactly
397 ;; with the processor_type enumeration in mips.h.
399 "r3000,4kc,4kp,5kc,5kf,20kc,24kc,24kf,24kx,74kc,74kf,74kx,m4k,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sb1a,sr71000"
400 (const (symbol_ref "mips_tune")))
402 ;; The type of hardware hazard associated with this instruction.
403 ;; DELAY means that the next instruction cannot read the result
404 ;; of this one. HILO means that the next two instructions cannot
405 ;; write to HI or LO.
406 (define_attr "hazard" "none,delay,hilo"
407 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
408 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
409 (const_string "delay")
411 (and (eq_attr "type" "mfc,mtc")
412 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
413 (const_string "delay")
415 (and (eq_attr "type" "fcmp")
416 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
417 (const_string "delay")
419 ;; The r4000 multiplication patterns include an mflo instruction.
420 (and (eq_attr "type" "imul")
421 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
422 (const_string "hilo")
424 (and (eq_attr "type" "mfhilo")
425 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
426 (const_string "hilo")]
427 (const_string "none")))
429 ;; Is it a single instruction?
430 (define_attr "single_insn" "no,yes"
431 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
433 ;; Can the instruction be put into a delay slot?
434 (define_attr "can_delay" "no,yes"
435 (if_then_else (and (eq_attr "type" "!branch,call,jump")
436 (and (eq_attr "hazard" "none")
437 (eq_attr "single_insn" "yes")))
439 (const_string "no")))
441 ;; Attribute defining whether or not we can use the branch-likely instructions
442 (define_attr "branch_likely" "no,yes"
444 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
446 (const_string "no"))))
448 ;; True if an instruction might assign to hi or lo when reloaded.
449 ;; This is used by the TUNE_MACC_CHAINS code.
450 (define_attr "may_clobber_hilo" "no,yes"
451 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
453 (const_string "no")))
455 ;; Describe a user's asm statement.
456 (define_asm_attributes
457 [(set_attr "type" "multi")
458 (set_attr "can_delay" "no")])
460 ;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
461 ;; from the same template.
462 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
464 ;; This mode macro allows :P to be used for patterns that operate on
465 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
466 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
468 ;; This mode macro allows :MOVECC to be used anywhere that a
469 ;; conditional-move-type condition is needed.
470 (define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
472 ;; This mode macro allows the QI and HI extension patterns to be defined from
473 ;; the same template.
474 (define_mode_macro SHORT [QI HI])
476 ;; This mode macro allows :ANYF to be used wherever a scalar or vector
477 ;; floating-point mode is allowed.
478 (define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
479 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
480 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
482 ;; Like ANYF, but only applies to scalar modes.
483 (define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
484 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
486 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
487 ;; 32-bit version and "dsubu" in the 64-bit version.
488 (define_mode_attr d [(SI "") (DI "d")])
490 ;; This attribute gives the length suffix for a sign- or zero-extension
492 (define_mode_attr size [(QI "b") (HI "h")])
494 ;; This attributes gives the mode mask of a SHORT.
495 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
497 ;; Mode attributes for GPR loads and stores.
498 (define_mode_attr load [(SI "lw") (DI "ld")])
499 (define_mode_attr store [(SI "sw") (DI "sd")])
501 ;; Similarly for MIPS IV indexed FPR loads and stores.
502 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
503 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
505 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
506 ;; are different. Some forms of unextended addiu have an 8-bit immediate
507 ;; field but the equivalent daddiu has only a 5-bit field.
508 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
510 ;; This attribute gives the best constraint to use for registers of
512 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
514 ;; This attribute gives the format suffix for floating-point operations.
515 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
517 ;; This attribute gives the upper-case mode name for one unit of a
518 ;; floating-point mode.
519 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
521 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
523 ;; In certain cases, div.s and div.ps may have a rounding error
524 ;; and/or wrong inexact flag.
526 ;; Therefore, we only allow div.s if not working around SB-1 rev2
527 ;; errata or if a slight loss of precision is OK.
528 (define_mode_attr divide_condition
529 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
530 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
532 ; This attribute gives the condition for which sqrt instructions exist.
533 (define_mode_attr sqrt_condition
534 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
536 ; This attribute gives the condition for which recip and rsqrt instructions
538 (define_mode_attr recip_condition
539 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
541 ;; This code macro allows all branch instructions to be generated from
542 ;; a single define_expand template.
543 (define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
544 eq ne gt ge lt le gtu geu ltu leu])
546 ;; This code macro allows signed and unsigned widening multiplications
547 ;; to use the same template.
548 (define_code_macro any_extend [sign_extend zero_extend])
550 ;; This code macro allows the three shift instructions to be generated
551 ;; from the same template.
552 (define_code_macro any_shift [ashift ashiftrt lshiftrt])
554 ;; This code macro allows all native floating-point comparisons to be
555 ;; generated from the same template.
556 (define_code_macro fcond [unordered uneq unlt unle eq lt le])
558 ;; This code macro is used for comparisons that can be implemented
559 ;; by swapping the operands.
560 (define_code_macro swapped_fcond [ge gt unge ungt])
562 ;; <u> expands to an empty string when doing a signed operation and
563 ;; "u" when doing an unsigned operation.
564 (define_code_attr u [(sign_extend "") (zero_extend "u")])
566 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
567 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
569 ;; <optab> expands to the name of the optab for a particular code.
570 (define_code_attr optab [(ashift "ashl")
574 ;; <insn> expands to the name of the insn that implements a particular code.
575 (define_code_attr insn [(ashift "sll")
579 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
580 (define_code_attr fcond [(unordered "un")
588 ;; Similar, but for swapped conditions.
589 (define_code_attr swapped_fcond [(ge "le")
594 ;; .........................
596 ;; Branch, call and jump delay slots
598 ;; .........................
600 (define_delay (and (eq_attr "type" "branch")
601 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
602 [(eq_attr "can_delay" "yes")
604 (and (eq_attr "branch_likely" "yes")
605 (eq_attr "can_delay" "yes"))])
607 (define_delay (eq_attr "type" "jump")
608 [(eq_attr "can_delay" "yes")
612 (define_delay (and (eq_attr "type" "call")
613 (eq_attr "jal_macro" "no"))
614 [(eq_attr "can_delay" "yes")
618 ;; Pipeline descriptions.
620 ;; generic.md provides a fallback for processors without a specific
621 ;; pipeline description. It is derived from the old define_function_unit
622 ;; version and uses the "alu" and "imuldiv" units declared below.
624 ;; Some of the processor-specific files are also derived from old
625 ;; define_function_unit descriptions and simply override the parts of
626 ;; generic.md that don't apply. The other processor-specific files
627 ;; are self-contained.
628 (define_automaton "alu,imuldiv")
630 (define_cpu_unit "alu" "alu")
631 (define_cpu_unit "imuldiv" "imuldiv")
651 (include "generic.md")
654 ;; ....................
658 ;; ....................
662 [(trap_if (const_int 1) (const_int 0))]
665 if (ISA_HAS_COND_TRAP)
667 else if (TARGET_MIPS16)
672 [(set_attr "type" "trap")])
674 (define_expand "conditional_trap"
675 [(trap_if (match_operator 0 "comparison_operator"
676 [(match_dup 2) (match_dup 3)])
677 (match_operand 1 "const_int_operand"))]
680 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
681 && operands[1] == const0_rtx)
683 mips_gen_conditional_trap (operands);
690 (define_insn "*conditional_trap<mode>"
691 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
692 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
693 (match_operand:GPR 2 "arith_operand" "dI")])
697 [(set_attr "type" "trap")])
700 ;; ....................
704 ;; ....................
707 (define_insn "add<mode>3"
708 [(set (match_operand:ANYF 0 "register_operand" "=f")
709 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
710 (match_operand:ANYF 2 "register_operand" "f")))]
712 "add.<fmt>\t%0,%1,%2"
713 [(set_attr "type" "fadd")
714 (set_attr "mode" "<UNITMODE>")])
716 (define_expand "add<mode>3"
717 [(set (match_operand:GPR 0 "register_operand")
718 (plus:GPR (match_operand:GPR 1 "register_operand")
719 (match_operand:GPR 2 "arith_operand")))]
722 (define_insn "*add<mode>3"
723 [(set (match_operand:GPR 0 "register_operand" "=d,d")
724 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
725 (match_operand:GPR 2 "arith_operand" "d,Q")))]
730 [(set_attr "type" "arith")
731 (set_attr "mode" "<MODE>")])
733 ;; We need to recognize MIPS16 stack pointer additions explicitly, since
734 ;; we don't have a constraint for $sp. These insns will be generated by
735 ;; the save_restore_insns functions.
737 (define_insn "*add<mode>3_sp1"
739 (plus:GPR (reg:GPR 29)
740 (match_operand:GPR 0 "const_arith_operand" "")))]
743 [(set_attr "type" "arith")
744 (set_attr "mode" "<MODE>")
745 (set (attr "length") (if_then_else (match_operand 0 "m16_simm8_8")
749 (define_insn "*add<mode>3_sp2"
750 [(set (match_operand:GPR 0 "register_operand" "=d")
751 (plus:GPR (reg:GPR 29)
752 (match_operand:GPR 1 "const_arith_operand" "")))]
755 [(set_attr "type" "arith")
756 (set_attr "mode" "<MODE>")
757 (set (attr "length") (if_then_else (match_operand 1 "m16_uimm<si8_di5>_4")
761 (define_insn "*add<mode>3_mips16"
762 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
763 (plus:GPR (match_operand:GPR 1 "register_operand" "0,d,d")
764 (match_operand:GPR 2 "arith_operand" "Q,O,d")))]
770 [(set_attr "type" "arith")
771 (set_attr "mode" "<MODE>")
772 (set_attr_alternative "length"
773 [(if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
776 (if_then_else (match_operand 2 "m16_simm4_1")
782 ;; On the mips16, we can sometimes split an add of a constant which is
783 ;; a 4 byte instruction into two adds which are both 2 byte
784 ;; instructions. There are two cases: one where we are adding a
785 ;; constant plus a register to another register, and one where we are
786 ;; simply adding a constant to a register.
789 [(set (match_operand:SI 0 "register_operand")
790 (plus:SI (match_dup 0)
791 (match_operand:SI 1 "const_int_operand")))]
792 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
793 && REG_P (operands[0])
794 && M16_REG_P (REGNO (operands[0]))
795 && GET_CODE (operands[1]) == CONST_INT
796 && ((INTVAL (operands[1]) > 0x7f
797 && INTVAL (operands[1]) <= 0x7f + 0x7f)
798 || (INTVAL (operands[1]) < - 0x80
799 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
800 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
801 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
803 HOST_WIDE_INT val = INTVAL (operands[1]);
807 operands[1] = GEN_INT (0x7f);
808 operands[2] = GEN_INT (val - 0x7f);
812 operands[1] = GEN_INT (- 0x80);
813 operands[2] = GEN_INT (val + 0x80);
818 [(set (match_operand:SI 0 "register_operand")
819 (plus:SI (match_operand:SI 1 "register_operand")
820 (match_operand:SI 2 "const_int_operand")))]
821 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
822 && REG_P (operands[0])
823 && M16_REG_P (REGNO (operands[0]))
824 && REG_P (operands[1])
825 && M16_REG_P (REGNO (operands[1]))
826 && REGNO (operands[0]) != REGNO (operands[1])
827 && GET_CODE (operands[2]) == CONST_INT
828 && ((INTVAL (operands[2]) > 0x7
829 && INTVAL (operands[2]) <= 0x7 + 0x7f)
830 || (INTVAL (operands[2]) < - 0x8
831 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
832 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
833 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
835 HOST_WIDE_INT val = INTVAL (operands[2]);
839 operands[2] = GEN_INT (0x7);
840 operands[3] = GEN_INT (val - 0x7);
844 operands[2] = GEN_INT (- 0x8);
845 operands[3] = GEN_INT (val + 0x8);
850 [(set (match_operand:DI 0 "register_operand")
851 (plus:DI (match_dup 0)
852 (match_operand:DI 1 "const_int_operand")))]
853 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
854 && REG_P (operands[0])
855 && M16_REG_P (REGNO (operands[0]))
856 && GET_CODE (operands[1]) == CONST_INT
857 && ((INTVAL (operands[1]) > 0xf
858 && INTVAL (operands[1]) <= 0xf + 0xf)
859 || (INTVAL (operands[1]) < - 0x10
860 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
861 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
862 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
864 HOST_WIDE_INT val = INTVAL (operands[1]);
868 operands[1] = GEN_INT (0xf);
869 operands[2] = GEN_INT (val - 0xf);
873 operands[1] = GEN_INT (- 0x10);
874 operands[2] = GEN_INT (val + 0x10);
879 [(set (match_operand:DI 0 "register_operand")
880 (plus:DI (match_operand:DI 1 "register_operand")
881 (match_operand:DI 2 "const_int_operand")))]
882 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
883 && REG_P (operands[0])
884 && M16_REG_P (REGNO (operands[0]))
885 && REG_P (operands[1])
886 && M16_REG_P (REGNO (operands[1]))
887 && REGNO (operands[0]) != REGNO (operands[1])
888 && GET_CODE (operands[2]) == CONST_INT
889 && ((INTVAL (operands[2]) > 0x7
890 && INTVAL (operands[2]) <= 0x7 + 0xf)
891 || (INTVAL (operands[2]) < - 0x8
892 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
893 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
894 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
896 HOST_WIDE_INT val = INTVAL (operands[2]);
900 operands[2] = GEN_INT (0x7);
901 operands[3] = GEN_INT (val - 0x7);
905 operands[2] = GEN_INT (- 0x8);
906 operands[3] = GEN_INT (val + 0x8);
910 (define_insn "*addsi3_extended"
911 [(set (match_operand:DI 0 "register_operand" "=d,d")
913 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
914 (match_operand:SI 2 "arith_operand" "d,Q"))))]
915 "TARGET_64BIT && !TARGET_MIPS16"
919 [(set_attr "type" "arith")
920 (set_attr "mode" "SI")])
922 ;; Split this insn so that the addiu splitters can have a crack at it.
923 ;; Use a conservative length estimate until the split.
924 (define_insn_and_split "*addsi3_extended_mips16"
925 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
927 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
928 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
929 "TARGET_64BIT && TARGET_MIPS16"
931 "&& reload_completed"
932 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
933 { operands[3] = gen_lowpart (SImode, operands[0]); }
934 [(set_attr "type" "arith")
935 (set_attr "mode" "SI")
936 (set_attr "extended_mips16" "yes")])
939 ;; ....................
943 ;; ....................
946 (define_insn "sub<mode>3"
947 [(set (match_operand:ANYF 0 "register_operand" "=f")
948 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
949 (match_operand:ANYF 2 "register_operand" "f")))]
951 "sub.<fmt>\t%0,%1,%2"
952 [(set_attr "type" "fadd")
953 (set_attr "mode" "<UNITMODE>")])
955 (define_insn "sub<mode>3"
956 [(set (match_operand:GPR 0 "register_operand" "=d")
957 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
958 (match_operand:GPR 2 "register_operand" "d")))]
961 [(set_attr "type" "arith")
962 (set_attr "mode" "<MODE>")])
964 (define_insn "*subsi3_extended"
965 [(set (match_operand:DI 0 "register_operand" "=d")
967 (minus:SI (match_operand:SI 1 "register_operand" "d")
968 (match_operand:SI 2 "register_operand" "d"))))]
971 [(set_attr "type" "arith")
972 (set_attr "mode" "DI")])
975 ;; ....................
979 ;; ....................
982 (define_expand "mul<mode>3"
983 [(set (match_operand:SCALARF 0 "register_operand")
984 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
985 (match_operand:SCALARF 2 "register_operand")))]
989 (define_insn "*mul<mode>3"
990 [(set (match_operand:SCALARF 0 "register_operand" "=f")
991 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
992 (match_operand:SCALARF 2 "register_operand" "f")))]
993 "!TARGET_4300_MUL_FIX"
994 "mul.<fmt>\t%0,%1,%2"
995 [(set_attr "type" "fmul")
996 (set_attr "mode" "<MODE>")])
998 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
999 ;; operands may corrupt immediately following multiplies. This is a
1000 ;; simple fix to insert NOPs.
1002 (define_insn "*mul<mode>3_r4300"
1003 [(set (match_operand:SCALARF 0 "register_operand" "=f")
1004 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
1005 (match_operand:SCALARF 2 "register_operand" "f")))]
1006 "TARGET_4300_MUL_FIX"
1007 "mul.<fmt>\t%0,%1,%2\;nop"
1008 [(set_attr "type" "fmul")
1009 (set_attr "mode" "<MODE>")
1010 (set_attr "length" "8")])
1012 (define_insn "mulv2sf3"
1013 [(set (match_operand:V2SF 0 "register_operand" "=f")
1014 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
1015 (match_operand:V2SF 2 "register_operand" "f")))]
1016 "TARGET_PAIRED_SINGLE_FLOAT"
1018 [(set_attr "type" "fmul")
1019 (set_attr "mode" "SF")])
1021 ;; The original R4000 has a cpu bug. If a double-word or a variable
1022 ;; shift executes while an integer multiplication is in progress, the
1023 ;; shift may give an incorrect result. Avoid this by keeping the mflo
1024 ;; with the mult on the R4000.
1026 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
1027 ;; (also valid for MIPS R4000MC processors):
1029 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
1030 ;; this errata description.
1031 ;; The following code sequence causes the R4000 to incorrectly
1032 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
1033 ;; instruction. If the dsra32 instruction is executed during an
1034 ;; integer multiply, the dsra32 will only shift by the amount in
1035 ;; specified in the instruction rather than the amount plus 32
1037 ;; instruction 1: mult rs,rt integer multiply
1038 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
1039 ;; right arithmetic + 32
1040 ;; Workaround: A dsra32 instruction placed after an integer
1041 ;; multiply should not be one of the 11 instructions after the
1042 ;; multiply instruction."
1046 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
1047 ;; the following description.
1048 ;; All extended shifts (shift by n+32) and variable shifts (32 and
1049 ;; 64-bit versions) may produce incorrect results under the
1050 ;; following conditions:
1051 ;; 1) An integer multiply is currently executing
1052 ;; 2) These types of shift instructions are executed immediately
1053 ;; following an integer divide instruction.
1055 ;; 1) Make sure no integer multiply is running wihen these
1056 ;; instruction are executed. If this cannot be predicted at
1057 ;; compile time, then insert a "mfhi" to R0 instruction
1058 ;; immediately after the integer multiply instruction. This
1059 ;; will cause the integer multiply to complete before the shift
1061 ;; 2) Separate integer divide and these two classes of shift
1062 ;; instructions by another instruction or a noop."
1064 ;; These processors have PRId values of 0x00004220 and 0x00004300,
1067 (define_expand "mulsi3"
1068 [(set (match_operand:SI 0 "register_operand")
1069 (mult:SI (match_operand:SI 1 "register_operand")
1070 (match_operand:SI 2 "register_operand")))]
1074 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1075 else if (TARGET_FIX_R4000)
1076 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1078 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1082 (define_expand "muldi3"
1083 [(set (match_operand:DI 0 "register_operand")
1084 (mult:DI (match_operand:DI 1 "register_operand")
1085 (match_operand:DI 2 "register_operand")))]
1088 if (TARGET_FIX_R4000)
1089 emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
1091 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1095 (define_insn "mulsi3_mult3"
1096 [(set (match_operand:SI 0 "register_operand" "=d,l")
1097 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1098 (match_operand:SI 2 "register_operand" "d,d")))
1099 (clobber (match_scratch:SI 3 "=h,h"))
1100 (clobber (match_scratch:SI 4 "=l,X"))]
1103 if (which_alternative == 1)
1104 return "mult\t%1,%2";
1105 if (TARGET_MIPS3900)
1106 return "mult\t%0,%1,%2";
1107 return "mul\t%0,%1,%2";
1109 [(set_attr "type" "imul3,imul")
1110 (set_attr "mode" "SI")])
1112 ;; If a register gets allocated to LO, and we spill to memory, the reload
1113 ;; will include a move from LO to a GPR. Merge it into the multiplication
1114 ;; if it can set the GPR directly.
1117 ;; Operand 1: GPR (1st multiplication operand)
1118 ;; Operand 2: GPR (2nd multiplication operand)
1120 ;; Operand 4: GPR (destination)
1123 [(set (match_operand:SI 0 "register_operand")
1124 (mult:SI (match_operand:SI 1 "register_operand")
1125 (match_operand:SI 2 "register_operand")))
1126 (clobber (match_operand:SI 3 "register_operand"))
1127 (clobber (scratch:SI))])
1128 (set (match_operand:SI 4 "register_operand")
1129 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1130 "ISA_HAS_MUL3 && peep2_reg_dead_p (2, operands[0])"
1133 (mult:SI (match_dup 1)
1135 (clobber (match_dup 3))
1136 (clobber (match_dup 0))])])
1138 (define_insn "mul<mode>3_internal"
1139 [(set (match_operand:GPR 0 "register_operand" "=l")
1140 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1141 (match_operand:GPR 2 "register_operand" "d")))
1142 (clobber (match_scratch:GPR 3 "=h"))]
1145 [(set_attr "type" "imul")
1146 (set_attr "mode" "<MODE>")])
1148 (define_insn "mul<mode>3_r4000"
1149 [(set (match_operand:GPR 0 "register_operand" "=d")
1150 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1151 (match_operand:GPR 2 "register_operand" "d")))
1152 (clobber (match_scratch:GPR 3 "=h"))
1153 (clobber (match_scratch:GPR 4 "=l"))]
1155 "<d>mult\t%1,%2\;mflo\t%0"
1156 [(set_attr "type" "imul")
1157 (set_attr "mode" "<MODE>")
1158 (set_attr "length" "8")])
1160 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1161 ;; of "mult; mflo". They have the same latency, but the first form gives
1162 ;; us an extra cycle to compute the operands.
1165 ;; Operand 1: GPR (1st multiplication operand)
1166 ;; Operand 2: GPR (2nd multiplication operand)
1168 ;; Operand 4: GPR (destination)
1171 [(set (match_operand:SI 0 "register_operand")
1172 (mult:SI (match_operand:SI 1 "register_operand")
1173 (match_operand:SI 2 "register_operand")))
1174 (clobber (match_operand:SI 3 "register_operand"))])
1175 (set (match_operand:SI 4 "register_operand")
1176 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1177 "ISA_HAS_MACC && !ISA_HAS_MUL3"
1182 (plus:SI (mult:SI (match_dup 1)
1186 (plus:SI (mult:SI (match_dup 1)
1189 (clobber (match_dup 3))])])
1191 ;; Multiply-accumulate patterns
1193 ;; For processors that can copy the output to a general register:
1195 ;; The all-d alternative is needed because the combiner will find this
1196 ;; pattern and then register alloc/reload will move registers around to
1197 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1199 ;; The last alternative should be made slightly less desirable, but adding
1200 ;; "?" to the constraint is too strong, and causes values to be loaded into
1201 ;; LO even when that's more costly. For now, using "*d" mostly does the
1203 (define_insn "*mul_acc_si"
1204 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1205 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1206 (match_operand:SI 2 "register_operand" "d,d,d"))
1207 (match_operand:SI 3 "register_operand" "0,l,*d")))
1208 (clobber (match_scratch:SI 4 "=h,h,h"))
1209 (clobber (match_scratch:SI 5 "=X,3,l"))
1210 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1212 || GENERATE_MADD_MSUB)
1215 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1216 if (which_alternative == 2)
1218 if (GENERATE_MADD_MSUB && which_alternative != 0)
1220 return madd[which_alternative];
1222 [(set_attr "type" "imadd,imadd,multi")
1223 (set_attr "mode" "SI")
1224 (set_attr "length" "4,4,8")])
1226 ;; Split the above insn if we failed to get LO allocated.
1228 [(set (match_operand:SI 0 "register_operand")
1229 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1230 (match_operand:SI 2 "register_operand"))
1231 (match_operand:SI 3 "register_operand")))
1232 (clobber (match_scratch:SI 4))
1233 (clobber (match_scratch:SI 5))
1234 (clobber (match_scratch:SI 6))]
1235 "reload_completed && !TARGET_DEBUG_D_MODE
1236 && GP_REG_P (true_regnum (operands[0]))
1237 && GP_REG_P (true_regnum (operands[3]))"
1238 [(parallel [(set (match_dup 6)
1239 (mult:SI (match_dup 1) (match_dup 2)))
1240 (clobber (match_dup 4))
1241 (clobber (match_dup 5))])
1242 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1245 ;; Splitter to copy result of MADD to a general register
1247 [(set (match_operand:SI 0 "register_operand")
1248 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1249 (match_operand:SI 2 "register_operand"))
1250 (match_operand:SI 3 "register_operand")))
1251 (clobber (match_scratch:SI 4))
1252 (clobber (match_scratch:SI 5))
1253 (clobber (match_scratch:SI 6))]
1254 "reload_completed && !TARGET_DEBUG_D_MODE
1255 && GP_REG_P (true_regnum (operands[0]))
1256 && true_regnum (operands[3]) == LO_REGNUM"
1257 [(parallel [(set (match_dup 3)
1258 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1260 (clobber (match_dup 4))
1261 (clobber (match_dup 5))
1262 (clobber (match_dup 6))])
1263 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1266 (define_insn "*macc"
1267 [(set (match_operand:SI 0 "register_operand" "=l,d")
1268 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1269 (match_operand:SI 2 "register_operand" "d,d"))
1270 (match_operand:SI 3 "register_operand" "0,l")))
1271 (clobber (match_scratch:SI 4 "=h,h"))
1272 (clobber (match_scratch:SI 5 "=X,3"))]
1275 if (which_alternative == 1)
1276 return "macc\t%0,%1,%2";
1277 else if (TARGET_MIPS5500)
1278 return "madd\t%1,%2";
1280 /* The VR4130 assumes that there is a two-cycle latency between a macc
1281 that "writes" to $0 and an instruction that reads from it. We avoid
1282 this by assigning to $1 instead. */
1283 return "%[macc\t%@,%1,%2%]";
1285 [(set_attr "type" "imadd")
1286 (set_attr "mode" "SI")])
1288 (define_insn "*msac"
1289 [(set (match_operand:SI 0 "register_operand" "=l,d")
1290 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1291 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1292 (match_operand:SI 3 "register_operand" "d,d"))))
1293 (clobber (match_scratch:SI 4 "=h,h"))
1294 (clobber (match_scratch:SI 5 "=X,1"))]
1297 if (which_alternative == 1)
1298 return "msac\t%0,%2,%3";
1299 else if (TARGET_MIPS5500)
1300 return "msub\t%2,%3";
1302 return "msac\t$0,%2,%3";
1304 [(set_attr "type" "imadd")
1305 (set_attr "mode" "SI")])
1307 ;; An msac-like instruction implemented using negation and a macc.
1308 (define_insn_and_split "*msac_using_macc"
1309 [(set (match_operand:SI 0 "register_operand" "=l,d")
1310 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1311 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1312 (match_operand:SI 3 "register_operand" "d,d"))))
1313 (clobber (match_scratch:SI 4 "=h,h"))
1314 (clobber (match_scratch:SI 5 "=X,1"))
1315 (clobber (match_scratch:SI 6 "=d,d"))]
1316 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1318 "&& reload_completed"
1320 (neg:SI (match_dup 3)))
1323 (plus:SI (mult:SI (match_dup 2)
1326 (clobber (match_dup 4))
1327 (clobber (match_dup 5))])]
1329 [(set_attr "type" "imadd")
1330 (set_attr "length" "8")])
1332 ;; Patterns generated by the define_peephole2 below.
1334 (define_insn "*macc2"
1335 [(set (match_operand:SI 0 "register_operand" "=l")
1336 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1337 (match_operand:SI 2 "register_operand" "d"))
1339 (set (match_operand:SI 3 "register_operand" "=d")
1340 (plus:SI (mult:SI (match_dup 1)
1343 (clobber (match_scratch:SI 4 "=h"))]
1344 "ISA_HAS_MACC && reload_completed"
1346 [(set_attr "type" "imadd")
1347 (set_attr "mode" "SI")])
1349 (define_insn "*msac2"
1350 [(set (match_operand:SI 0 "register_operand" "=l")
1351 (minus:SI (match_dup 0)
1352 (mult:SI (match_operand:SI 1 "register_operand" "d")
1353 (match_operand:SI 2 "register_operand" "d"))))
1354 (set (match_operand:SI 3 "register_operand" "=d")
1355 (minus:SI (match_dup 0)
1356 (mult:SI (match_dup 1)
1358 (clobber (match_scratch:SI 4 "=h"))]
1359 "ISA_HAS_MSAC && reload_completed"
1361 [(set_attr "type" "imadd")
1362 (set_attr "mode" "SI")])
1364 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1368 ;; Operand 1: macc/msac
1370 ;; Operand 3: GPR (destination)
1373 [(set (match_operand:SI 0 "register_operand")
1374 (match_operand:SI 1 "macc_msac_operand"))
1375 (clobber (match_operand:SI 2 "register_operand"))
1376 (clobber (scratch:SI))])
1377 (set (match_operand:SI 3 "register_operand")
1378 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1380 [(parallel [(set (match_dup 0)
1384 (clobber (match_dup 2))])]
1387 ;; When we have a three-address multiplication instruction, it should
1388 ;; be faster to do a separate multiply and add, rather than moving
1389 ;; something into LO in order to use a macc instruction.
1391 ;; This peephole needs a scratch register to cater for the case when one
1392 ;; of the multiplication operands is the same as the destination.
1394 ;; Operand 0: GPR (scratch)
1396 ;; Operand 2: GPR (addend)
1397 ;; Operand 3: GPR (destination)
1398 ;; Operand 4: macc/msac
1400 ;; Operand 6: new multiplication
1401 ;; Operand 7: new addition/subtraction
1403 [(match_scratch:SI 0 "d")
1404 (set (match_operand:SI 1 "register_operand")
1405 (match_operand:SI 2 "register_operand"))
1408 [(set (match_operand:SI 3 "register_operand")
1409 (match_operand:SI 4 "macc_msac_operand"))
1410 (clobber (match_operand:SI 5 "register_operand"))
1411 (clobber (match_dup 1))])]
1413 && true_regnum (operands[1]) == LO_REGNUM
1414 && peep2_reg_dead_p (2, operands[1])
1415 && GP_REG_P (true_regnum (operands[3]))"
1416 [(parallel [(set (match_dup 0)
1418 (clobber (match_dup 5))
1419 (clobber (match_dup 1))])
1423 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1424 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1425 operands[2], operands[0]);
1428 ;; Same as above, except LO is the initial target of the macc.
1430 ;; Operand 0: GPR (scratch)
1432 ;; Operand 2: GPR (addend)
1433 ;; Operand 3: macc/msac
1435 ;; Operand 5: GPR (destination)
1436 ;; Operand 6: new multiplication
1437 ;; Operand 7: new addition/subtraction
1439 [(match_scratch:SI 0 "d")
1440 (set (match_operand:SI 1 "register_operand")
1441 (match_operand:SI 2 "register_operand"))
1445 (match_operand:SI 3 "macc_msac_operand"))
1446 (clobber (match_operand:SI 4 "register_operand"))
1447 (clobber (scratch:SI))])
1449 (set (match_operand:SI 5 "register_operand")
1450 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1451 "ISA_HAS_MUL3 && peep2_reg_dead_p (3, operands[1])"
1452 [(parallel [(set (match_dup 0)
1454 (clobber (match_dup 4))
1455 (clobber (match_dup 1))])
1459 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1460 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1461 operands[2], operands[0]);
1464 (define_insn "*mul_sub_si"
1465 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1466 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1467 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1468 (match_operand:SI 3 "register_operand" "d,d,d"))))
1469 (clobber (match_scratch:SI 4 "=h,h,h"))
1470 (clobber (match_scratch:SI 5 "=X,1,l"))
1471 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1472 "GENERATE_MADD_MSUB"
1477 [(set_attr "type" "imadd,multi,multi")
1478 (set_attr "mode" "SI")
1479 (set_attr "length" "4,8,8")])
1481 ;; Split the above insn if we failed to get LO allocated.
1483 [(set (match_operand:SI 0 "register_operand")
1484 (minus:SI (match_operand:SI 1 "register_operand")
1485 (mult:SI (match_operand:SI 2 "register_operand")
1486 (match_operand:SI 3 "register_operand"))))
1487 (clobber (match_scratch:SI 4))
1488 (clobber (match_scratch:SI 5))
1489 (clobber (match_scratch:SI 6))]
1490 "reload_completed && !TARGET_DEBUG_D_MODE
1491 && GP_REG_P (true_regnum (operands[0]))
1492 && GP_REG_P (true_regnum (operands[1]))"
1493 [(parallel [(set (match_dup 6)
1494 (mult:SI (match_dup 2) (match_dup 3)))
1495 (clobber (match_dup 4))
1496 (clobber (match_dup 5))])
1497 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1500 ;; Splitter to copy result of MSUB to a general register
1502 [(set (match_operand:SI 0 "register_operand")
1503 (minus:SI (match_operand:SI 1 "register_operand")
1504 (mult:SI (match_operand:SI 2 "register_operand")
1505 (match_operand:SI 3 "register_operand"))))
1506 (clobber (match_scratch:SI 4))
1507 (clobber (match_scratch:SI 5))
1508 (clobber (match_scratch:SI 6))]
1509 "reload_completed && !TARGET_DEBUG_D_MODE
1510 && GP_REG_P (true_regnum (operands[0]))
1511 && true_regnum (operands[1]) == LO_REGNUM"
1512 [(parallel [(set (match_dup 1)
1513 (minus:SI (match_dup 1)
1514 (mult:SI (match_dup 2) (match_dup 3))))
1515 (clobber (match_dup 4))
1516 (clobber (match_dup 5))
1517 (clobber (match_dup 6))])
1518 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1521 (define_insn "*muls"
1522 [(set (match_operand:SI 0 "register_operand" "=l,d")
1523 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1524 (match_operand:SI 2 "register_operand" "d,d"))))
1525 (clobber (match_scratch:SI 3 "=h,h"))
1526 (clobber (match_scratch:SI 4 "=X,l"))]
1531 [(set_attr "type" "imul,imul3")
1532 (set_attr "mode" "SI")])
1534 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1536 (define_expand "<u>mulsidi3"
1538 [(set (match_operand:DI 0 "register_operand")
1539 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1540 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1541 (clobber (scratch:DI))
1542 (clobber (scratch:DI))
1543 (clobber (scratch:DI))])]
1544 "!TARGET_64BIT || !TARGET_FIX_R4000"
1548 if (!TARGET_FIX_R4000)
1549 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1552 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1558 (define_insn "<u>mulsidi3_32bit_internal"
1559 [(set (match_operand:DI 0 "register_operand" "=x")
1560 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1561 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1562 "!TARGET_64BIT && !TARGET_FIX_R4000 && !TARGET_DSPR2"
1564 [(set_attr "type" "imul")
1565 (set_attr "mode" "SI")])
1567 (define_insn "<u>mulsidi3_32bit_r4000"
1568 [(set (match_operand:DI 0 "register_operand" "=d")
1569 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1570 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1571 (clobber (match_scratch:DI 3 "=x"))]
1572 "!TARGET_64BIT && TARGET_FIX_R4000"
1573 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1574 [(set_attr "type" "imul")
1575 (set_attr "mode" "SI")
1576 (set_attr "length" "12")])
1578 (define_insn_and_split "*<u>mulsidi3_64bit"
1579 [(set (match_operand:DI 0 "register_operand" "=d")
1580 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1581 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1582 (clobber (match_scratch:DI 3 "=l"))
1583 (clobber (match_scratch:DI 4 "=h"))
1584 (clobber (match_scratch:DI 5 "=d"))]
1585 "TARGET_64BIT && !TARGET_FIX_R4000"
1587 "&& reload_completed"
1591 (mult:SI (match_dup 1)
1595 (mult:DI (any_extend:DI (match_dup 1))
1596 (any_extend:DI (match_dup 2)))
1599 ;; OP5 <- LO, OP0 <- HI
1600 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1601 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1605 (ashift:DI (match_dup 5)
1608 (lshiftrt:DI (match_dup 5)
1611 ;; Shift OP0 into place.
1613 (ashift:DI (match_dup 0)
1616 ;; OR the two halves together
1618 (ior:DI (match_dup 0)
1621 [(set_attr "type" "imul")
1622 (set_attr "mode" "SI")
1623 (set_attr "length" "24")])
1625 (define_insn "*<u>mulsidi3_64bit_parts"
1626 [(set (match_operand:DI 0 "register_operand" "=l")
1628 (mult:SI (match_operand:SI 2 "register_operand" "d")
1629 (match_operand:SI 3 "register_operand" "d"))))
1630 (set (match_operand:DI 1 "register_operand" "=h")
1632 (mult:DI (any_extend:DI (match_dup 2))
1633 (any_extend:DI (match_dup 3)))
1635 "TARGET_64BIT && !TARGET_FIX_R4000"
1637 [(set_attr "type" "imul")
1638 (set_attr "mode" "SI")])
1640 ;; Widening multiply with negation.
1641 (define_insn "*muls<u>_di"
1642 [(set (match_operand:DI 0 "register_operand" "=x")
1645 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1646 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1647 "!TARGET_64BIT && ISA_HAS_MULS"
1649 [(set_attr "type" "imul")
1650 (set_attr "mode" "SI")])
1652 (define_insn "*msac<u>_di"
1653 [(set (match_operand:DI 0 "register_operand" "=x")
1655 (match_operand:DI 3 "register_operand" "0")
1657 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1658 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1659 "!TARGET_64BIT && ISA_HAS_MSAC"
1661 if (TARGET_MIPS5500)
1662 return "msub<u>\t%1,%2";
1664 return "msac<u>\t$0,%1,%2";
1666 [(set_attr "type" "imadd")
1667 (set_attr "mode" "SI")])
1669 ;; _highpart patterns
1671 (define_expand "<su>mulsi3_highpart"
1672 [(set (match_operand:SI 0 "register_operand")
1675 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1676 (any_extend:DI (match_operand:SI 2 "register_operand")))
1678 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1681 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1685 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1690 (define_insn "<su>mulsi3_highpart_internal"
1691 [(set (match_operand:SI 0 "register_operand" "=h")
1694 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1695 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1697 (clobber (match_scratch:SI 3 "=l"))]
1698 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1700 [(set_attr "type" "imul")
1701 (set_attr "mode" "SI")])
1703 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1704 [(set (match_operand:SI 0 "register_operand" "=h,d")
1708 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1709 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1711 (clobber (match_scratch:SI 3 "=l,l"))
1712 (clobber (match_scratch:SI 4 "=X,h"))]
1717 [(set_attr "type" "imul,imul3")
1718 (set_attr "mode" "SI")])
1720 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1721 [(set (match_operand:SI 0 "register_operand" "=h,d")
1726 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1727 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1729 (clobber (match_scratch:SI 3 "=l,l"))
1730 (clobber (match_scratch:SI 4 "=X,h"))]
1734 mulshi<u>\t%0,%1,%2"
1735 [(set_attr "type" "imul,imul3")
1736 (set_attr "mode" "SI")])
1738 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1739 ;; errata MD(0), which says that dmultu does not always produce the
1741 (define_insn "<su>muldi3_highpart"
1742 [(set (match_operand:DI 0 "register_operand" "=h")
1746 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1747 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1749 (clobber (match_scratch:DI 3 "=l"))]
1750 "TARGET_64BIT && !TARGET_FIX_R4000
1751 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1753 [(set_attr "type" "imul")
1754 (set_attr "mode" "DI")])
1756 ;; The R4650 supports a 32-bit multiply/ 64-bit accumulate
1757 ;; instruction. The HI/LO registers are used as a 64-bit accumulator.
1759 (define_insn "madsi"
1760 [(set (match_operand:SI 0 "register_operand" "+l")
1761 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1762 (match_operand:SI 2 "register_operand" "d"))
1764 (clobber (match_scratch:SI 3 "=h"))]
1767 [(set_attr "type" "imadd")
1768 (set_attr "mode" "SI")])
1770 (define_insn "*<su>mul_acc_di"
1771 [(set (match_operand:DI 0 "register_operand" "=x")
1773 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1774 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1775 (match_operand:DI 3 "register_operand" "0")))]
1776 "(TARGET_MAD || ISA_HAS_MACC)
1780 return "mad<u>\t%1,%2";
1781 else if (TARGET_MIPS5500)
1782 return "madd<u>\t%1,%2";
1784 /* See comment in *macc. */
1785 return "%[macc<u>\t%@,%1,%2%]";
1787 [(set_attr "type" "imadd")
1788 (set_attr "mode" "SI")])
1790 ;; Floating point multiply accumulate instructions.
1792 (define_insn "*madd<mode>"
1793 [(set (match_operand:ANYF 0 "register_operand" "=f")
1794 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1795 (match_operand:ANYF 2 "register_operand" "f"))
1796 (match_operand:ANYF 3 "register_operand" "f")))]
1797 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1798 "madd.<fmt>\t%0,%3,%1,%2"
1799 [(set_attr "type" "fmadd")
1800 (set_attr "mode" "<UNITMODE>")])
1802 (define_insn "*msub<mode>"
1803 [(set (match_operand:ANYF 0 "register_operand" "=f")
1804 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1805 (match_operand:ANYF 2 "register_operand" "f"))
1806 (match_operand:ANYF 3 "register_operand" "f")))]
1807 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1808 "msub.<fmt>\t%0,%3,%1,%2"
1809 [(set_attr "type" "fmadd")
1810 (set_attr "mode" "<UNITMODE>")])
1812 (define_insn "*nmadd<mode>"
1813 [(set (match_operand:ANYF 0 "register_operand" "=f")
1814 (neg:ANYF (plus:ANYF
1815 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1816 (match_operand:ANYF 2 "register_operand" "f"))
1817 (match_operand:ANYF 3 "register_operand" "f"))))]
1818 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1819 && HONOR_SIGNED_ZEROS (<MODE>mode)
1820 && !HONOR_NANS (<MODE>mode)"
1821 "nmadd.<fmt>\t%0,%3,%1,%2"
1822 [(set_attr "type" "fmadd")
1823 (set_attr "mode" "<UNITMODE>")])
1825 (define_insn "*nmadd<mode>_fastmath"
1826 [(set (match_operand:ANYF 0 "register_operand" "=f")
1828 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1829 (match_operand:ANYF 2 "register_operand" "f"))
1830 (match_operand:ANYF 3 "register_operand" "f")))]
1831 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1832 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1833 && !HONOR_NANS (<MODE>mode)"
1834 "nmadd.<fmt>\t%0,%3,%1,%2"
1835 [(set_attr "type" "fmadd")
1836 (set_attr "mode" "<UNITMODE>")])
1838 (define_insn "*nmsub<mode>"
1839 [(set (match_operand:ANYF 0 "register_operand" "=f")
1840 (neg:ANYF (minus:ANYF
1841 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1842 (match_operand:ANYF 3 "register_operand" "f"))
1843 (match_operand:ANYF 1 "register_operand" "f"))))]
1844 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1845 && HONOR_SIGNED_ZEROS (<MODE>mode)
1846 && !HONOR_NANS (<MODE>mode)"
1847 "nmsub.<fmt>\t%0,%1,%2,%3"
1848 [(set_attr "type" "fmadd")
1849 (set_attr "mode" "<UNITMODE>")])
1851 (define_insn "*nmsub<mode>_fastmath"
1852 [(set (match_operand:ANYF 0 "register_operand" "=f")
1854 (match_operand:ANYF 1 "register_operand" "f")
1855 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1856 (match_operand:ANYF 3 "register_operand" "f"))))]
1857 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1858 && !HONOR_SIGNED_ZEROS (<MODE>mode)
1859 && !HONOR_NANS (<MODE>mode)"
1860 "nmsub.<fmt>\t%0,%1,%2,%3"
1861 [(set_attr "type" "fmadd")
1862 (set_attr "mode" "<UNITMODE>")])
1865 ;; ....................
1867 ;; DIVISION and REMAINDER
1869 ;; ....................
1872 (define_expand "div<mode>3"
1873 [(set (match_operand:ANYF 0 "register_operand")
1874 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1875 (match_operand:ANYF 2 "register_operand")))]
1876 "<divide_condition>"
1878 if (const_1_operand (operands[1], <MODE>mode))
1879 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
1880 operands[1] = force_reg (<MODE>mode, operands[1]);
1883 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1885 ;; If an mfc1 or dmfc1 happens to access the floating point register
1886 ;; file at the same time a long latency operation (div, sqrt, recip,
1887 ;; sqrt) iterates an intermediate result back through the floating
1888 ;; point register file bypass, then instead returning the correct
1889 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1890 ;; result of the long latency operation.
1892 ;; The workaround is to insert an unconditional 'mov' from/to the
1893 ;; long latency op destination register.
1895 (define_insn "*div<mode>3"
1896 [(set (match_operand:ANYF 0 "register_operand" "=f")
1897 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1898 (match_operand:ANYF 2 "register_operand" "f")))]
1899 "<divide_condition>"
1902 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1904 return "div.<fmt>\t%0,%1,%2";
1906 [(set_attr "type" "fdiv")
1907 (set_attr "mode" "<UNITMODE>")
1908 (set (attr "length")
1909 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1913 (define_insn "*recip<mode>3"
1914 [(set (match_operand:ANYF 0 "register_operand" "=f")
1915 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1916 (match_operand:ANYF 2 "register_operand" "f")))]
1917 "<recip_condition> && flag_unsafe_math_optimizations"
1920 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1922 return "recip.<fmt>\t%0,%2";
1924 [(set_attr "type" "frdiv")
1925 (set_attr "mode" "<UNITMODE>")
1926 (set (attr "length")
1927 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1931 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1932 ;; with negative operands. We use special libgcc functions instead.
1933 (define_insn "divmod<mode>4"
1934 [(set (match_operand:GPR 0 "register_operand" "=l")
1935 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1936 (match_operand:GPR 2 "register_operand" "d")))
1937 (set (match_operand:GPR 3 "register_operand" "=h")
1938 (mod:GPR (match_dup 1)
1940 "!TARGET_FIX_VR4120"
1941 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
1942 [(set_attr "type" "idiv")
1943 (set_attr "mode" "<MODE>")])
1945 (define_insn "udivmod<mode>4"
1946 [(set (match_operand:GPR 0 "register_operand" "=l")
1947 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
1948 (match_operand:GPR 2 "register_operand" "d")))
1949 (set (match_operand:GPR 3 "register_operand" "=h")
1950 (umod:GPR (match_dup 1)
1953 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
1954 [(set_attr "type" "idiv")
1955 (set_attr "mode" "<MODE>")])
1958 ;; ....................
1962 ;; ....................
1964 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
1965 ;; "*div[sd]f3" comment for details).
1967 (define_insn "sqrt<mode>2"
1968 [(set (match_operand:ANYF 0 "register_operand" "=f")
1969 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1973 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
1975 return "sqrt.<fmt>\t%0,%1";
1977 [(set_attr "type" "fsqrt")
1978 (set_attr "mode" "<UNITMODE>")
1979 (set (attr "length")
1980 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1984 (define_insn "*rsqrt<mode>a"
1985 [(set (match_operand:ANYF 0 "register_operand" "=f")
1986 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1987 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
1988 "<recip_condition> && flag_unsafe_math_optimizations"
1991 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1993 return "rsqrt.<fmt>\t%0,%2";
1995 [(set_attr "type" "frsqrt")
1996 (set_attr "mode" "<UNITMODE>")
1997 (set (attr "length")
1998 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2002 (define_insn "*rsqrt<mode>b"
2003 [(set (match_operand:ANYF 0 "register_operand" "=f")
2004 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
2005 (match_operand:ANYF 2 "register_operand" "f"))))]
2006 "<recip_condition> && flag_unsafe_math_optimizations"
2009 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
2011 return "rsqrt.<fmt>\t%0,%2";
2013 [(set_attr "type" "frsqrt")
2014 (set_attr "mode" "<UNITMODE>")
2015 (set (attr "length")
2016 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
2021 ;; ....................
2025 ;; ....................
2027 ;; Do not use the integer abs macro instruction, since that signals an
2028 ;; exception on -2147483648 (sigh).
2030 ;; abs.fmt is an arithmetic instruction and treats all NaN inputs as
2031 ;; invalid; it does not clear their sign bits. We therefore can't use
2032 ;; abs.fmt if the signs of NaNs matter.
2034 (define_insn "abs<mode>2"
2035 [(set (match_operand:ANYF 0 "register_operand" "=f")
2036 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2037 "!HONOR_NANS (<MODE>mode)"
2039 [(set_attr "type" "fabs")
2040 (set_attr "mode" "<UNITMODE>")])
2043 ;; ...................
2045 ;; Count leading zeroes.
2047 ;; ...................
2050 (define_insn "clz<mode>2"
2051 [(set (match_operand:GPR 0 "register_operand" "=d")
2052 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
2055 [(set_attr "type" "clz")
2056 (set_attr "mode" "<MODE>")])
2059 ;; ....................
2061 ;; NEGATION and ONE'S COMPLEMENT
2063 ;; ....................
2065 (define_insn "negsi2"
2066 [(set (match_operand:SI 0 "register_operand" "=d")
2067 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
2071 return "neg\t%0,%1";
2073 return "subu\t%0,%.,%1";
2075 [(set_attr "type" "arith")
2076 (set_attr "mode" "SI")])
2078 (define_insn "negdi2"
2079 [(set (match_operand:DI 0 "register_operand" "=d")
2080 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2081 "TARGET_64BIT && !TARGET_MIPS16"
2083 [(set_attr "type" "arith")
2084 (set_attr "mode" "DI")])
2086 ;; neg.fmt is an arithmetic instruction and treats all NaN inputs as
2087 ;; invalid; it does not flip their sign bit. We therefore can't use
2088 ;; neg.fmt if the signs of NaNs matter.
2090 (define_insn "neg<mode>2"
2091 [(set (match_operand:ANYF 0 "register_operand" "=f")
2092 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2093 "!HONOR_NANS (<MODE>mode)"
2095 [(set_attr "type" "fneg")
2096 (set_attr "mode" "<UNITMODE>")])
2098 (define_insn "one_cmpl<mode>2"
2099 [(set (match_operand:GPR 0 "register_operand" "=d")
2100 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2104 return "not\t%0,%1";
2106 return "nor\t%0,%.,%1";
2108 [(set_attr "type" "arith")
2109 (set_attr "mode" "<MODE>")])
2112 ;; ....................
2116 ;; ....................
2119 ;; Many of these instructions use trivial define_expands, because we
2120 ;; want to use a different set of constraints when TARGET_MIPS16.
2122 (define_expand "and<mode>3"
2123 [(set (match_operand:GPR 0 "register_operand")
2124 (and:GPR (match_operand:GPR 1 "register_operand")
2125 (match_operand:GPR 2 "uns_arith_operand")))]
2129 operands[2] = force_reg (<MODE>mode, operands[2]);
2132 (define_insn "*and<mode>3"
2133 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2134 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2135 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2140 [(set_attr "type" "arith")
2141 (set_attr "mode" "<MODE>")])
2143 (define_insn "*and<mode>3_mips16"
2144 [(set (match_operand:GPR 0 "register_operand" "=d")
2145 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2146 (match_operand:GPR 2 "register_operand" "d")))]
2149 [(set_attr "type" "arith")
2150 (set_attr "mode" "<MODE>")])
2152 (define_expand "ior<mode>3"
2153 [(set (match_operand:GPR 0 "register_operand")
2154 (ior:GPR (match_operand:GPR 1 "register_operand")
2155 (match_operand:GPR 2 "uns_arith_operand")))]
2159 operands[2] = force_reg (<MODE>mode, operands[2]);
2162 (define_insn "*ior<mode>3"
2163 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2164 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2165 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2170 [(set_attr "type" "arith")
2171 (set_attr "mode" "<MODE>")])
2173 (define_insn "*ior<mode>3_mips16"
2174 [(set (match_operand:GPR 0 "register_operand" "=d")
2175 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2176 (match_operand:GPR 2 "register_operand" "d")))]
2179 [(set_attr "type" "arith")
2180 (set_attr "mode" "<MODE>")])
2182 (define_expand "xor<mode>3"
2183 [(set (match_operand:GPR 0 "register_operand")
2184 (xor:GPR (match_operand:GPR 1 "register_operand")
2185 (match_operand:GPR 2 "uns_arith_operand")))]
2190 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2191 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2192 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2197 [(set_attr "type" "arith")
2198 (set_attr "mode" "<MODE>")])
2201 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2202 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2203 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2209 [(set_attr "type" "arith")
2210 (set_attr "mode" "<MODE>")
2211 (set_attr_alternative "length"
2213 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2218 (define_insn "*nor<mode>3"
2219 [(set (match_operand:GPR 0 "register_operand" "=d")
2220 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2221 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2224 [(set_attr "type" "arith")
2225 (set_attr "mode" "<MODE>")])
2228 ;; ....................
2232 ;; ....................
2236 (define_insn "truncdfsf2"
2237 [(set (match_operand:SF 0 "register_operand" "=f")
2238 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2239 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2241 [(set_attr "type" "fcvt")
2242 (set_attr "cnv_mode" "D2S")
2243 (set_attr "mode" "SF")])
2245 ;; Integer truncation patterns. Truncating SImode values to smaller
2246 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2247 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2248 ;; need to make sure that the lower 32 bits are properly sign-extended
2249 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2250 ;; smaller than SImode is equivalent to two separate truncations:
2253 ;; DI ---> HI == DI ---> SI ---> HI
2254 ;; DI ---> QI == DI ---> SI ---> QI
2256 ;; Step A needs a real instruction but step B does not.
2258 (define_insn "truncdisi2"
2259 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2260 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2265 [(set_attr "type" "shift,store")
2266 (set_attr "mode" "SI")
2267 (set_attr "extended_mips16" "yes,*")])
2269 (define_insn "truncdihi2"
2270 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2271 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2276 [(set_attr "type" "shift,store")
2277 (set_attr "mode" "SI")
2278 (set_attr "extended_mips16" "yes,*")])
2280 (define_insn "truncdiqi2"
2281 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2282 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2287 [(set_attr "type" "shift,store")
2288 (set_attr "mode" "SI")
2289 (set_attr "extended_mips16" "yes,*")])
2291 ;; Combiner patterns to optimize shift/truncate combinations.
2294 [(set (match_operand:SI 0 "register_operand" "=d")
2296 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2297 (match_operand:DI 2 "const_arith_operand" ""))))]
2298 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2300 [(set_attr "type" "shift")
2301 (set_attr "mode" "SI")])
2304 [(set (match_operand:SI 0 "register_operand" "=d")
2305 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2307 "TARGET_64BIT && !TARGET_MIPS16"
2309 [(set_attr "type" "shift")
2310 (set_attr "mode" "SI")])
2313 ;; Combiner patterns for truncate/sign_extend combinations. They use
2314 ;; the shift/truncate patterns above.
2316 (define_insn_and_split ""
2317 [(set (match_operand:SI 0 "register_operand" "=d")
2319 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2320 "TARGET_64BIT && !TARGET_MIPS16"
2322 "&& reload_completed"
2324 (ashift:DI (match_dup 1)
2327 (truncate:SI (ashiftrt:DI (match_dup 2)
2329 { operands[2] = gen_lowpart (DImode, operands[0]); })
2331 (define_insn_and_split ""
2332 [(set (match_operand:SI 0 "register_operand" "=d")
2334 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2335 "TARGET_64BIT && !TARGET_MIPS16"
2337 "&& reload_completed"
2339 (ashift:DI (match_dup 1)
2342 (truncate:SI (ashiftrt:DI (match_dup 2)
2344 { operands[2] = gen_lowpart (DImode, operands[0]); })
2347 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2350 [(set (match_operand:SI 0 "register_operand" "=d")
2351 (zero_extend:SI (truncate:HI
2352 (match_operand:DI 1 "register_operand" "d"))))]
2353 "TARGET_64BIT && !TARGET_MIPS16"
2354 "andi\t%0,%1,0xffff"
2355 [(set_attr "type" "arith")
2356 (set_attr "mode" "SI")])
2359 [(set (match_operand:SI 0 "register_operand" "=d")
2360 (zero_extend:SI (truncate:QI
2361 (match_operand:DI 1 "register_operand" "d"))))]
2362 "TARGET_64BIT && !TARGET_MIPS16"
2364 [(set_attr "type" "arith")
2365 (set_attr "mode" "SI")])
2368 [(set (match_operand:HI 0 "register_operand" "=d")
2369 (zero_extend:HI (truncate:QI
2370 (match_operand:DI 1 "register_operand" "d"))))]
2371 "TARGET_64BIT && !TARGET_MIPS16"
2373 [(set_attr "type" "arith")
2374 (set_attr "mode" "HI")])
2377 ;; ....................
2381 ;; ....................
2385 (define_insn_and_split "zero_extendsidi2"
2386 [(set (match_operand:DI 0 "register_operand" "=d,d")
2387 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2392 "&& reload_completed && REG_P (operands[1])"
2394 (ashift:DI (match_dup 1) (const_int 32)))
2396 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2397 { operands[1] = gen_lowpart (DImode, operands[1]); }
2398 [(set_attr "type" "multi,load")
2399 (set_attr "mode" "DI")
2400 (set_attr "length" "8,*")])
2402 ;; Combine is not allowed to convert this insn into a zero_extendsidi2
2403 ;; because of TRULY_NOOP_TRUNCATION.
2405 (define_insn_and_split "*clear_upper32"
2406 [(set (match_operand:DI 0 "register_operand" "=d,d")
2407 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2408 (const_int 4294967295)))]
2411 if (which_alternative == 0)
2414 operands[1] = gen_lowpart (SImode, operands[1]);
2415 return "lwu\t%0,%1";
2417 "&& reload_completed && REG_P (operands[1])"
2419 (ashift:DI (match_dup 1) (const_int 32)))
2421 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2423 [(set_attr "type" "multi,load")
2424 (set_attr "mode" "DI")
2425 (set_attr "length" "8,*")])
2427 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2428 [(set (match_operand:GPR 0 "register_operand")
2429 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2432 if (TARGET_MIPS16 && !GENERATE_MIPS16E
2433 && !memory_operand (operands[1], <SHORT:MODE>mode))
2435 emit_insn (gen_and<GPR:mode>3 (operands[0],
2436 gen_lowpart (<GPR:MODE>mode, operands[1]),
2437 force_reg (<GPR:MODE>mode,
2438 GEN_INT (<SHORT:mask>))));
2443 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2444 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2446 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2449 andi\t%0,%1,<SHORT:mask>
2450 l<SHORT:size>u\t%0,%1"
2451 [(set_attr "type" "arith,load")
2452 (set_attr "mode" "<GPR:MODE>")])
2454 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
2455 [(set (match_operand:GPR 0 "register_operand" "=d")
2456 (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
2458 "ze<SHORT:size>\t%0"
2459 [(set_attr "type" "arith")
2460 (set_attr "mode" "<GPR:MODE>")])
2462 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2463 [(set (match_operand:GPR 0 "register_operand" "=d")
2464 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2466 "l<SHORT:size>u\t%0,%1"
2467 [(set_attr "type" "load")
2468 (set_attr "mode" "<GPR:MODE>")])
2470 (define_expand "zero_extendqihi2"
2471 [(set (match_operand:HI 0 "register_operand")
2472 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2475 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2477 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2483 (define_insn "*zero_extendqihi2"
2484 [(set (match_operand:HI 0 "register_operand" "=d,d")
2485 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2490 [(set_attr "type" "arith,load")
2491 (set_attr "mode" "HI")])
2493 (define_insn "*zero_extendqihi2_mips16"
2494 [(set (match_operand:HI 0 "register_operand" "=d")
2495 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2498 [(set_attr "type" "load")
2499 (set_attr "mode" "HI")])
2502 ;; ....................
2506 ;; ....................
2509 ;; Those for integer source operand are ordered widest source type first.
2511 ;; When TARGET_64BIT, all SImode integer registers should already be in
2512 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2513 ;; therefore get rid of register->register instructions if we constrain
2514 ;; the source to be in the same register as the destination.
2516 ;; The register alternative has type "arith" so that the pre-reload
2517 ;; scheduler will treat it as a move. This reflects what happens if
2518 ;; the register alternative needs a reload.
2519 (define_insn_and_split "extendsidi2"
2520 [(set (match_operand:DI 0 "register_operand" "=d,d")
2521 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2526 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2529 emit_note (NOTE_INSN_DELETED);
2532 [(set_attr "type" "arith,load")
2533 (set_attr "mode" "DI")])
2535 (define_expand "extend<SHORT:mode><GPR:mode>2"
2536 [(set (match_operand:GPR 0 "register_operand")
2537 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2540 (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
2541 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2542 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
2546 l<SHORT:size>\t%0,%1"
2547 [(set_attr "type" "arith,load")
2548 (set_attr "mode" "<GPR:MODE>")])
2550 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2551 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2553 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2554 "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
2557 l<SHORT:size>\t%0,%1"
2558 "&& reload_completed && REG_P (operands[1])"
2559 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2560 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2562 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2563 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2564 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2566 [(set_attr "type" "arith,load")
2567 (set_attr "mode" "<GPR:MODE>")
2568 (set_attr "length" "8,*")])
2570 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2571 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2573 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2576 se<SHORT:size>\t%0,%1
2577 l<SHORT:size>\t%0,%1"
2578 [(set_attr "type" "arith,load")
2579 (set_attr "mode" "<GPR:MODE>")])
2581 ;; This pattern generates the same code as extendqisi2; split it into
2582 ;; that form after reload.
2583 (define_insn_and_split "extendqihi2"
2584 [(set (match_operand:HI 0 "register_operand" "=d,d")
2585 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2589 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
2590 { operands[0] = gen_lowpart (SImode, operands[0]); }
2591 [(set_attr "type" "arith,load")
2592 (set_attr "mode" "SI")
2593 (set_attr "length" "8,*")])
2595 (define_insn "extendsfdf2"
2596 [(set (match_operand:DF 0 "register_operand" "=f")
2597 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2598 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2600 [(set_attr "type" "fcvt")
2601 (set_attr "cnv_mode" "S2D")
2602 (set_attr "mode" "DF")])
2605 ;; ....................
2609 ;; ....................
2611 (define_expand "fix_truncdfsi2"
2612 [(set (match_operand:SI 0 "register_operand")
2613 (fix:SI (match_operand:DF 1 "register_operand")))]
2614 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2616 if (!ISA_HAS_TRUNC_W)
2618 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2623 (define_insn "fix_truncdfsi2_insn"
2624 [(set (match_operand:SI 0 "register_operand" "=f")
2625 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2626 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2628 [(set_attr "type" "fcvt")
2629 (set_attr "mode" "DF")
2630 (set_attr "cnv_mode" "D2I")
2631 (set_attr "length" "4")])
2633 (define_insn "fix_truncdfsi2_macro"
2634 [(set (match_operand:SI 0 "register_operand" "=f")
2635 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2636 (clobber (match_scratch:DF 2 "=d"))]
2637 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2640 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2642 return "trunc.w.d %0,%1,%2";
2644 [(set_attr "type" "fcvt")
2645 (set_attr "mode" "DF")
2646 (set_attr "cnv_mode" "D2I")
2647 (set_attr "length" "36")])
2649 (define_expand "fix_truncsfsi2"
2650 [(set (match_operand:SI 0 "register_operand")
2651 (fix:SI (match_operand:SF 1 "register_operand")))]
2654 if (!ISA_HAS_TRUNC_W)
2656 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2661 (define_insn "fix_truncsfsi2_insn"
2662 [(set (match_operand:SI 0 "register_operand" "=f")
2663 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2664 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2666 [(set_attr "type" "fcvt")
2667 (set_attr "mode" "SF")
2668 (set_attr "cnv_mode" "S2I")
2669 (set_attr "length" "4")])
2671 (define_insn "fix_truncsfsi2_macro"
2672 [(set (match_operand:SI 0 "register_operand" "=f")
2673 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2674 (clobber (match_scratch:SF 2 "=d"))]
2675 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2678 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2680 return "trunc.w.s %0,%1,%2";
2682 [(set_attr "type" "fcvt")
2683 (set_attr "mode" "SF")
2684 (set_attr "cnv_mode" "S2I")
2685 (set_attr "length" "36")])
2688 (define_insn "fix_truncdfdi2"
2689 [(set (match_operand:DI 0 "register_operand" "=f")
2690 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2691 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2693 [(set_attr "type" "fcvt")
2694 (set_attr "mode" "DF")
2695 (set_attr "cnv_mode" "D2I")
2696 (set_attr "length" "4")])
2699 (define_insn "fix_truncsfdi2"
2700 [(set (match_operand:DI 0 "register_operand" "=f")
2701 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2702 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2704 [(set_attr "type" "fcvt")
2705 (set_attr "mode" "SF")
2706 (set_attr "cnv_mode" "S2I")
2707 (set_attr "length" "4")])
2710 (define_insn "floatsidf2"
2711 [(set (match_operand:DF 0 "register_operand" "=f")
2712 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2713 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2715 [(set_attr "type" "fcvt")
2716 (set_attr "mode" "DF")
2717 (set_attr "cnv_mode" "I2D")
2718 (set_attr "length" "4")])
2721 (define_insn "floatdidf2"
2722 [(set (match_operand:DF 0 "register_operand" "=f")
2723 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2724 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2726 [(set_attr "type" "fcvt")
2727 (set_attr "mode" "DF")
2728 (set_attr "cnv_mode" "I2D")
2729 (set_attr "length" "4")])
2732 (define_insn "floatsisf2"
2733 [(set (match_operand:SF 0 "register_operand" "=f")
2734 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2737 [(set_attr "type" "fcvt")
2738 (set_attr "mode" "SF")
2739 (set_attr "cnv_mode" "I2S")
2740 (set_attr "length" "4")])
2743 (define_insn "floatdisf2"
2744 [(set (match_operand:SF 0 "register_operand" "=f")
2745 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2746 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2748 [(set_attr "type" "fcvt")
2749 (set_attr "mode" "SF")
2750 (set_attr "cnv_mode" "I2S")
2751 (set_attr "length" "4")])
2754 (define_expand "fixuns_truncdfsi2"
2755 [(set (match_operand:SI 0 "register_operand")
2756 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2757 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2759 rtx reg1 = gen_reg_rtx (DFmode);
2760 rtx reg2 = gen_reg_rtx (DFmode);
2761 rtx reg3 = gen_reg_rtx (SImode);
2762 rtx label1 = gen_label_rtx ();
2763 rtx label2 = gen_label_rtx ();
2764 REAL_VALUE_TYPE offset;
2766 real_2expN (&offset, 31);
2768 if (reg1) /* Turn off complaints about unreached code. */
2770 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2771 do_pending_stack_adjust ();
2773 emit_insn (gen_cmpdf (operands[1], reg1));
2774 emit_jump_insn (gen_bge (label1));
2776 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2777 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2778 gen_rtx_LABEL_REF (VOIDmode, label2)));
2781 emit_label (label1);
2782 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2783 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2784 (BITMASK_HIGH, SImode)));
2786 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2787 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2789 emit_label (label2);
2791 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2792 fields, and can't be used for REG_NOTES anyway). */
2793 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2799 (define_expand "fixuns_truncdfdi2"
2800 [(set (match_operand:DI 0 "register_operand")
2801 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2802 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2804 rtx reg1 = gen_reg_rtx (DFmode);
2805 rtx reg2 = gen_reg_rtx (DFmode);
2806 rtx reg3 = gen_reg_rtx (DImode);
2807 rtx label1 = gen_label_rtx ();
2808 rtx label2 = gen_label_rtx ();
2809 REAL_VALUE_TYPE offset;
2811 real_2expN (&offset, 63);
2813 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2814 do_pending_stack_adjust ();
2816 emit_insn (gen_cmpdf (operands[1], reg1));
2817 emit_jump_insn (gen_bge (label1));
2819 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2820 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2821 gen_rtx_LABEL_REF (VOIDmode, label2)));
2824 emit_label (label1);
2825 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2826 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2827 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2829 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2830 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2832 emit_label (label2);
2834 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2835 fields, and can't be used for REG_NOTES anyway). */
2836 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2841 (define_expand "fixuns_truncsfsi2"
2842 [(set (match_operand:SI 0 "register_operand")
2843 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2846 rtx reg1 = gen_reg_rtx (SFmode);
2847 rtx reg2 = gen_reg_rtx (SFmode);
2848 rtx reg3 = gen_reg_rtx (SImode);
2849 rtx label1 = gen_label_rtx ();
2850 rtx label2 = gen_label_rtx ();
2851 REAL_VALUE_TYPE offset;
2853 real_2expN (&offset, 31);
2855 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2856 do_pending_stack_adjust ();
2858 emit_insn (gen_cmpsf (operands[1], reg1));
2859 emit_jump_insn (gen_bge (label1));
2861 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2862 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2863 gen_rtx_LABEL_REF (VOIDmode, label2)));
2866 emit_label (label1);
2867 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2868 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2869 (BITMASK_HIGH, SImode)));
2871 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2872 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2874 emit_label (label2);
2876 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2877 fields, and can't be used for REG_NOTES anyway). */
2878 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2883 (define_expand "fixuns_truncsfdi2"
2884 [(set (match_operand:DI 0 "register_operand")
2885 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2886 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2888 rtx reg1 = gen_reg_rtx (SFmode);
2889 rtx reg2 = gen_reg_rtx (SFmode);
2890 rtx reg3 = gen_reg_rtx (DImode);
2891 rtx label1 = gen_label_rtx ();
2892 rtx label2 = gen_label_rtx ();
2893 REAL_VALUE_TYPE offset;
2895 real_2expN (&offset, 63);
2897 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2898 do_pending_stack_adjust ();
2900 emit_insn (gen_cmpsf (operands[1], reg1));
2901 emit_jump_insn (gen_bge (label1));
2903 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2904 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2905 gen_rtx_LABEL_REF (VOIDmode, label2)));
2908 emit_label (label1);
2909 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2910 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2911 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2913 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
2914 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2916 emit_label (label2);
2918 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2919 fields, and can't be used for REG_NOTES anyway). */
2920 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2925 ;; ....................
2929 ;; ....................
2931 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
2933 (define_expand "extv"
2934 [(set (match_operand 0 "register_operand")
2935 (sign_extract (match_operand:QI 1 "memory_operand")
2936 (match_operand 2 "immediate_operand")
2937 (match_operand 3 "immediate_operand")))]
2940 if (mips_expand_unaligned_load (operands[0], operands[1],
2941 INTVAL (operands[2]),
2942 INTVAL (operands[3])))
2948 (define_expand "extzv"
2949 [(set (match_operand 0 "register_operand")
2950 (zero_extract (match_operand 1 "nonimmediate_operand")
2951 (match_operand 2 "immediate_operand")
2952 (match_operand 3 "immediate_operand")))]
2955 if (mips_expand_unaligned_load (operands[0], operands[1],
2956 INTVAL (operands[2]),
2957 INTVAL (operands[3])))
2959 else if (mips_use_ins_ext_p (operands[1], operands[2], operands[3]))
2961 if (GET_MODE (operands[0]) == DImode)
2962 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2],
2965 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2],
2973 (define_insn "extzv<mode>"
2974 [(set (match_operand:GPR 0 "register_operand" "=d")
2975 (zero_extract:GPR (match_operand:GPR 1 "register_operand" "d")
2976 (match_operand:SI 2 "immediate_operand" "I")
2977 (match_operand:SI 3 "immediate_operand" "I")))]
2978 "mips_use_ins_ext_p (operands[1], operands[2], operands[3])"
2979 "<d>ext\t%0,%1,%3,%2"
2980 [(set_attr "type" "arith")
2981 (set_attr "mode" "<MODE>")])
2984 (define_expand "insv"
2985 [(set (zero_extract (match_operand 0 "nonimmediate_operand")
2986 (match_operand 1 "immediate_operand")
2987 (match_operand 2 "immediate_operand"))
2988 (match_operand 3 "reg_or_0_operand"))]
2991 if (mips_expand_unaligned_store (operands[0], operands[3],
2992 INTVAL (operands[1]),
2993 INTVAL (operands[2])))
2995 else if (mips_use_ins_ext_p (operands[0], operands[1], operands[2]))
2997 if (GET_MODE (operands[0]) == DImode)
2998 emit_insn (gen_insvdi (operands[0], operands[1], operands[2],
3001 emit_insn (gen_insvsi (operands[0], operands[1], operands[2],
3009 (define_insn "insv<mode>"
3010 [(set (zero_extract:GPR (match_operand:GPR 0 "register_operand" "+d")
3011 (match_operand:SI 1 "immediate_operand" "I")
3012 (match_operand:SI 2 "immediate_operand" "I"))
3013 (match_operand:GPR 3 "reg_or_0_operand" "dJ"))]
3014 "mips_use_ins_ext_p (operands[0], operands[1], operands[2])"
3015 "<d>ins\t%0,%z3,%2,%1"
3016 [(set_attr "type" "arith")
3017 (set_attr "mode" "<MODE>")])
3019 ;; Unaligned word moves generated by the bit field patterns.
3021 ;; As far as the rtl is concerned, both the left-part and right-part
3022 ;; instructions can access the whole field. However, the real operand
3023 ;; refers to just the first or the last byte (depending on endianness).
3024 ;; We therefore use two memory operands to each instruction, one to
3025 ;; describe the rtl effect and one to use in the assembly output.
3027 ;; Operands 0 and 1 are the rtl-level target and source respectively.
3028 ;; This allows us to use the standard length calculations for the "load"
3029 ;; and "store" type attributes.
3031 (define_insn "mov_<load>l"
3032 [(set (match_operand:GPR 0 "register_operand" "=d")
3033 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3034 (match_operand:QI 2 "memory_operand" "m")]
3036 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3038 [(set_attr "type" "load")
3039 (set_attr "mode" "<MODE>")])
3041 (define_insn "mov_<load>r"
3042 [(set (match_operand:GPR 0 "register_operand" "=d")
3043 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
3044 (match_operand:QI 2 "memory_operand" "m")
3045 (match_operand:GPR 3 "register_operand" "0")]
3046 UNSPEC_LOAD_RIGHT))]
3047 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
3049 [(set_attr "type" "load")
3050 (set_attr "mode" "<MODE>")])
3052 (define_insn "mov_<store>l"
3053 [(set (match_operand:BLK 0 "memory_operand" "=m")
3054 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3055 (match_operand:QI 2 "memory_operand" "m")]
3056 UNSPEC_STORE_LEFT))]
3057 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3059 [(set_attr "type" "store")
3060 (set_attr "mode" "<MODE>")])
3062 (define_insn "mov_<store>r"
3063 [(set (match_operand:BLK 0 "memory_operand" "+m")
3064 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
3065 (match_operand:QI 2 "memory_operand" "m")
3067 UNSPEC_STORE_RIGHT))]
3068 "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
3070 [(set_attr "type" "store")
3071 (set_attr "mode" "<MODE>")])
3073 ;; An instruction to calculate the high part of a 64-bit SYMBOL_GENERAL.
3074 ;; The required value is:
3076 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
3078 ;; which translates to:
3080 ;; lui op0,%highest(op1)
3081 ;; daddiu op0,op0,%higher(op1)
3083 ;; daddiu op0,op0,%hi(op1)
3086 ;; The split is deferred until after flow2 to allow the peephole2 below
3088 (define_insn_and_split "*lea_high64"
3089 [(set (match_operand:DI 0 "register_operand" "=d")
3090 (high:DI (match_operand:DI 1 "general_symbolic_operand" "")))]
3091 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3093 "&& flow2_completed"
3094 [(set (match_dup 0) (high:DI (match_dup 2)))
3095 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
3096 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
3097 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3098 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
3100 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3101 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
3103 [(set_attr "length" "20")])
3105 ;; Use a scratch register to reduce the latency of the above pattern
3106 ;; on superscalar machines. The optimized sequence is:
3108 ;; lui op1,%highest(op2)
3110 ;; daddiu op1,op1,%higher(op2)
3112 ;; daddu op1,op1,op0
3114 [(set (match_operand:DI 1 "register_operand")
3115 (high:DI (match_operand:DI 2 "general_symbolic_operand")))
3116 (match_scratch:DI 0 "d")]
3117 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
3118 [(set (match_dup 1) (high:DI (match_dup 3)))
3119 (set (match_dup 0) (high:DI (match_dup 4)))
3120 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
3121 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
3122 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
3124 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
3125 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
3128 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
3129 ;; SYMBOL_GENERAL X will take 6 cycles. This next pattern allows combine
3130 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
3131 ;; used once. We can then use the sequence:
3133 ;; lui op0,%highest(op1)
3135 ;; daddiu op0,op0,%higher(op1)
3136 ;; daddiu op2,op2,%lo(op1)
3138 ;; daddu op0,op0,op2
3140 ;; which takes 4 cycles on most superscalar targets.
3141 (define_insn_and_split "*lea64"
3142 [(set (match_operand:DI 0 "register_operand" "=d")
3143 (match_operand:DI 1 "general_symbolic_operand" ""))
3144 (clobber (match_scratch:DI 2 "=&d"))]
3145 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
3147 "&& reload_completed"
3148 [(set (match_dup 0) (high:DI (match_dup 3)))
3149 (set (match_dup 2) (high:DI (match_dup 4)))
3150 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
3151 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
3152 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
3153 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
3155 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
3156 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
3158 [(set_attr "length" "24")])
3160 ;; Insns to fetch a symbol from a big GOT.
3162 (define_insn_and_split "*xgot_hi<mode>"
3163 [(set (match_operand:P 0 "register_operand" "=d")
3164 (high:P (match_operand:P 1 "got_disp_operand" "")))]
3165 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3167 "&& reload_completed"
3168 [(set (match_dup 0) (high:P (match_dup 2)))
3169 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3171 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3172 operands[3] = pic_offset_table_rtx;
3174 [(set_attr "got" "xgot_high")
3175 (set_attr "mode" "<MODE>")])
3177 (define_insn_and_split "*xgot_lo<mode>"
3178 [(set (match_operand:P 0 "register_operand" "=d")
3179 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3180 (match_operand:P 2 "got_disp_operand" "")))]
3181 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3183 "&& reload_completed"
3185 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3186 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_DISP); }
3187 [(set_attr "got" "load")
3188 (set_attr "mode" "<MODE>")])
3190 ;; Insns to fetch a symbol from a normal GOT.
3192 (define_insn_and_split "*got_disp<mode>"
3193 [(set (match_operand:P 0 "register_operand" "=d")
3194 (match_operand:P 1 "got_disp_operand" ""))]
3195 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3197 "&& reload_completed"
3199 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3201 operands[2] = pic_offset_table_rtx;
3202 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_DISP);
3204 [(set_attr "got" "load")
3205 (set_attr "mode" "<MODE>")])
3207 ;; Insns for loading the "page" part of a page/ofst address from the GOT.
3209 (define_insn_and_split "*got_page<mode>"
3210 [(set (match_operand:P 0 "register_operand" "=d")
3211 (high:P (match_operand:P 1 "got_page_ofst_operand" "")))]
3212 "TARGET_EXPLICIT_RELOCS"
3214 "&& reload_completed"
3216 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3218 operands[2] = pic_offset_table_rtx;
3219 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3221 [(set_attr "got" "load")
3222 (set_attr "mode" "<MODE>")])
3224 ;; Lower-level instructions for loading an address from the GOT.
3225 ;; We could use MEMs, but an unspec gives more optimization
3228 (define_insn "load_got<mode>"
3229 [(set (match_operand:P 0 "register_operand" "=d")
3230 (unspec:P [(match_operand:P 1 "register_operand" "d")
3231 (match_operand:P 2 "immediate_operand" "")]
3234 "<load>\t%0,%R2(%1)"
3235 [(set_attr "type" "load")
3236 (set_attr "mode" "<MODE>")
3237 (set_attr "length" "4")])
3239 ;; Instructions for adding the low 16 bits of an address to a register.
3240 ;; Operand 2 is the address: print_operand works out which relocation
3241 ;; should be applied.
3243 (define_insn "*low<mode>"
3244 [(set (match_operand:P 0 "register_operand" "=d")
3245 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3246 (match_operand:P 2 "immediate_operand" "")))]
3248 "<d>addiu\t%0,%1,%R2"
3249 [(set_attr "type" "arith")
3250 (set_attr "mode" "<MODE>")])
3252 (define_insn "*low<mode>_mips16"
3253 [(set (match_operand:P 0 "register_operand" "=d")
3254 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3255 (match_operand:P 2 "immediate_operand" "")))]
3258 [(set_attr "type" "arith")
3259 (set_attr "mode" "<MODE>")
3260 (set_attr "length" "8")])
3262 ;; Allow combine to split complex const_int load sequences, using operand 2
3263 ;; to store the intermediate results. See move_operand for details.
3265 [(set (match_operand:GPR 0 "register_operand")
3266 (match_operand:GPR 1 "splittable_const_int_operand"))
3267 (clobber (match_operand:GPR 2 "register_operand"))]
3271 mips_move_integer (operands[0], operands[2], INTVAL (operands[1]));
3275 ;; Likewise, for symbolic operands.
3277 [(set (match_operand:P 0 "register_operand")
3278 (match_operand:P 1 "splittable_symbolic_operand"))
3279 (clobber (match_operand:P 2 "register_operand"))]
3281 [(set (match_dup 0) (match_dup 1))]
3282 { operands[1] = mips_split_symbol (operands[2], operands[1]); })
3284 ;; 64-bit integer moves
3286 ;; Unlike most other insns, the move insns can't be split with
3287 ;; different predicates, because register spilling and other parts of
3288 ;; the compiler, have memoized the insn number already.
3290 (define_expand "movdi"
3291 [(set (match_operand:DI 0 "")
3292 (match_operand:DI 1 ""))]
3295 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3299 ;; For mips16, we need a special case to handle storing $31 into
3300 ;; memory, since we don't have a constraint to match $31. This
3301 ;; instruction can be generated by save_restore_insns.
3303 (define_insn "*mov<mode>_ra"
3304 [(set (match_operand:GPR 0 "stack_operand" "=m")
3308 [(set_attr "type" "store")
3309 (set_attr "mode" "<MODE>")])
3311 (define_insn "*movdi_32bit"
3312 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*B*C*D,*B*C*D,*d,*m")
3313 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))]
3314 "!TARGET_64BIT && !TARGET_FLOAT64 && !TARGET_MIPS16
3315 && (register_operand (operands[0], DImode)
3316 || reg_or_0_operand (operands[1], DImode))"
3317 { return mips_output_move (operands[0], operands[1]); }
3318 [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,mtc,load,mfc,store")
3319 (set_attr "mode" "DI")
3320 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3322 (define_insn "*movdi_gp32_fp64"
3323 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*a,*d,*f,*f,*f,*d,*m")
3324 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*a,*f,*J*d,*m,*f,*f"))]
3325 "!TARGET_64BIT && TARGET_FLOAT64 && !TARGET_MIPS16
3326 && (register_operand (operands[0], DImode)
3327 || reg_or_0_operand (operands[1], DImode))"
3328 { return mips_output_move (operands[0], operands[1]); }
3329 [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,fmove,mtc,fpload,mfc,fpstore")
3330 (set_attr "mode" "DI")
3331 (set_attr "length" "8,16,*,*,8,8,4,8,*,8,*")])
3333 (define_insn "*movdi_32bit_mips16"
3334 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3335 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3336 "!TARGET_64BIT && TARGET_MIPS16
3337 && (register_operand (operands[0], DImode)
3338 || register_operand (operands[1], DImode))"
3339 { return mips_output_move (operands[0], operands[1]); }
3340 [(set_attr "type" "arith,arith,arith,arith,arith,load,store,mfhilo")
3341 (set_attr "mode" "DI")
3342 (set_attr "length" "8,8,8,8,12,*,*,8")])
3344 (define_insn "*movdi_64bit"
3345 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3346 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3347 "TARGET_64BIT && !TARGET_MIPS16
3348 && (register_operand (operands[0], DImode)
3349 || reg_or_0_operand (operands[1], DImode))"
3350 { return mips_output_move (operands[0], operands[1]); }
3351 [(set_attr "type" "arith,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mthilo,mtc,load,mfc,store")
3352 (set_attr "mode" "DI")
3353 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
3355 (define_insn "*movdi_64bit_mips16"
3356 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3357 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3358 "TARGET_64BIT && TARGET_MIPS16
3359 && (register_operand (operands[0], DImode)
3360 || register_operand (operands[1], DImode))"
3361 { return mips_output_move (operands[0], operands[1]); }
3362 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3363 (set_attr "mode" "DI")
3364 (set_attr_alternative "length"
3368 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3371 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3376 (const_string "*")])])
3379 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3380 ;; when the original load is a 4 byte instruction but the add and the
3381 ;; load are 2 2 byte instructions.
3384 [(set (match_operand:DI 0 "register_operand")
3385 (mem:DI (plus:DI (match_dup 0)
3386 (match_operand:DI 1 "const_int_operand"))))]
3387 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3388 && !TARGET_DEBUG_D_MODE
3389 && REG_P (operands[0])
3390 && M16_REG_P (REGNO (operands[0]))
3391 && GET_CODE (operands[1]) == CONST_INT
3392 && ((INTVAL (operands[1]) < 0
3393 && INTVAL (operands[1]) >= -0x10)
3394 || (INTVAL (operands[1]) >= 32 * 8
3395 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3396 || (INTVAL (operands[1]) >= 0
3397 && INTVAL (operands[1]) < 32 * 8
3398 && (INTVAL (operands[1]) & 7) != 0))"
3399 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3400 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3402 HOST_WIDE_INT val = INTVAL (operands[1]);
3405 operands[2] = const0_rtx;
3406 else if (val >= 32 * 8)
3410 operands[1] = GEN_INT (0x8 + off);
3411 operands[2] = GEN_INT (val - off - 0x8);
3417 operands[1] = GEN_INT (off);
3418 operands[2] = GEN_INT (val - off);
3422 ;; 32-bit Integer moves
3424 ;; Unlike most other insns, the move insns can't be split with
3425 ;; different predicates, because register spilling and other parts of
3426 ;; the compiler, have memoized the insn number already.
3428 (define_expand "movsi"
3429 [(set (match_operand:SI 0 "")
3430 (match_operand:SI 1 ""))]
3433 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3437 ;; The difference between these two is whether or not ints are allowed
3438 ;; in FP registers (off by default, use -mdebugh to enable).
3440 (define_insn "*movsi_internal"
3441 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m")
3442 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*A,*d,*m,*B*C*D,*B*C*D"))]
3444 && (register_operand (operands[0], SImode)
3445 || reg_or_0_operand (operands[1], SImode))"
3446 { return mips_output_move (operands[0], operands[1]); }
3447 [(set_attr "type" "arith,const,const,load,store,fmove,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,load,mfc,store")
3448 (set_attr "mode" "SI")
3449 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,*,4,*")])
3451 (define_insn "*movsi_mips16"
3452 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3453 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3455 && (register_operand (operands[0], SImode)
3456 || register_operand (operands[1], SImode))"
3457 { return mips_output_move (operands[0], operands[1]); }
3458 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3459 (set_attr "mode" "SI")
3460 (set_attr_alternative "length"
3464 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3467 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3472 (const_string "*")])])
3474 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3475 ;; when the original load is a 4 byte instruction but the add and the
3476 ;; load are 2 2 byte instructions.
3479 [(set (match_operand:SI 0 "register_operand")
3480 (mem:SI (plus:SI (match_dup 0)
3481 (match_operand:SI 1 "const_int_operand"))))]
3482 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3483 && REG_P (operands[0])
3484 && M16_REG_P (REGNO (operands[0]))
3485 && GET_CODE (operands[1]) == CONST_INT
3486 && ((INTVAL (operands[1]) < 0
3487 && INTVAL (operands[1]) >= -0x80)
3488 || (INTVAL (operands[1]) >= 32 * 4
3489 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3490 || (INTVAL (operands[1]) >= 0
3491 && INTVAL (operands[1]) < 32 * 4
3492 && (INTVAL (operands[1]) & 3) != 0))"
3493 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3494 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3496 HOST_WIDE_INT val = INTVAL (operands[1]);
3499 operands[2] = const0_rtx;
3500 else if (val >= 32 * 4)
3504 operands[1] = GEN_INT (0x7c + off);
3505 operands[2] = GEN_INT (val - off - 0x7c);
3511 operands[1] = GEN_INT (off);
3512 operands[2] = GEN_INT (val - off);
3516 ;; On the mips16, we can split a load of certain constants into a load
3517 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3521 [(set (match_operand:SI 0 "register_operand")
3522 (match_operand:SI 1 "const_int_operand"))]
3523 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3524 && REG_P (operands[0])
3525 && M16_REG_P (REGNO (operands[0]))
3526 && GET_CODE (operands[1]) == CONST_INT
3527 && INTVAL (operands[1]) >= 0x100
3528 && INTVAL (operands[1]) <= 0xff + 0x7f"
3529 [(set (match_dup 0) (match_dup 1))
3530 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3532 int val = INTVAL (operands[1]);
3534 operands[1] = GEN_INT (0xff);
3535 operands[2] = GEN_INT (val - 0xff);
3538 ;; This insn handles moving CCmode values. It's really just a
3539 ;; slightly simplified copy of movsi_internal2, with additional cases
3540 ;; to move a condition register to a general register and to move
3541 ;; between the general registers and the floating point registers.
3543 (define_insn "movcc"
3544 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3545 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3546 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3547 { return mips_output_move (operands[0], operands[1]); }
3548 [(set_attr "type" "multi,arith,load,store,mfc,mtc,fmove,fpload,fpstore")
3549 (set_attr "mode" "SI")
3550 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3552 ;; Reload condition code registers. reload_incc and reload_outcc
3553 ;; both handle moves from arbitrary operands into condition code
3554 ;; registers. reload_incc handles the more common case in which
3555 ;; a source operand is constrained to be in a condition-code
3556 ;; register, but has not been allocated to one.
3558 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3559 ;; constraints do not include 'z'. reload_outcc handles the case
3560 ;; when such an operand is allocated to a condition-code register.
3562 ;; Note that reloads from a condition code register to some
3563 ;; other location can be done using ordinary moves. Moving
3564 ;; into a GPR takes a single movcc, moving elsewhere takes
3565 ;; two. We can leave these cases to the generic reload code.
3566 (define_expand "reload_incc"
3567 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3568 (match_operand:CC 1 "general_operand" ""))
3569 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3570 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3572 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3576 (define_expand "reload_outcc"
3577 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3578 (match_operand:CC 1 "register_operand" ""))
3579 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3580 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3582 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3586 ;; MIPS4 supports loading and storing a floating point register from
3587 ;; the sum of two general registers. We use two versions for each of
3588 ;; these four instructions: one where the two general registers are
3589 ;; SImode, and one where they are DImode. This is because general
3590 ;; registers will be in SImode when they hold 32-bit values, but,
3591 ;; since the 32-bit values are always sign extended, the [ls][wd]xc1
3592 ;; instructions will still work correctly.
3594 ;; ??? Perhaps it would be better to support these instructions by
3595 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3596 ;; these instructions can only be used to load and store floating
3597 ;; point registers, that would probably cause trouble in reload.
3599 (define_insn "*<ANYF:loadx>_<P:mode>"
3600 [(set (match_operand:ANYF 0 "register_operand" "=f")
3601 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3602 (match_operand:P 2 "register_operand" "d"))))]
3604 "<ANYF:loadx>\t%0,%1(%2)"
3605 [(set_attr "type" "fpidxload")
3606 (set_attr "mode" "<ANYF:UNITMODE>")])
3608 (define_insn "*<ANYF:storex>_<P:mode>"
3609 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3610 (match_operand:P 2 "register_operand" "d")))
3611 (match_operand:ANYF 0 "register_operand" "f"))]
3613 "<ANYF:storex>\t%0,%1(%2)"
3614 [(set_attr "type" "fpidxstore")
3615 (set_attr "mode" "<ANYF:UNITMODE>")])
3617 ;; 16-bit Integer moves
3619 ;; Unlike most other insns, the move insns can't be split with
3620 ;; different predicates, because register spilling and other parts of
3621 ;; the compiler, have memoized the insn number already.
3622 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3624 (define_expand "movhi"
3625 [(set (match_operand:HI 0 "")
3626 (match_operand:HI 1 ""))]
3629 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3633 (define_insn "*movhi_internal"
3634 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3635 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3637 && (register_operand (operands[0], HImode)
3638 || reg_or_0_operand (operands[1], HImode))"
3648 [(set_attr "type" "arith,arith,load,store,mfc,mtc,fmove,mthilo")
3649 (set_attr "mode" "HI")
3650 (set_attr "length" "4,4,*,*,4,4,4,4")])
3652 (define_insn "*movhi_mips16"
3653 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3654 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3656 && (register_operand (operands[0], HImode)
3657 || register_operand (operands[1], HImode))"
3666 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3667 (set_attr "mode" "HI")
3668 (set_attr_alternative "length"
3672 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3675 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3679 (const_string "*")])])
3682 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3683 ;; when the original load is a 4 byte instruction but the add and the
3684 ;; load are 2 2 byte instructions.
3687 [(set (match_operand:HI 0 "register_operand")
3688 (mem:HI (plus:SI (match_dup 0)
3689 (match_operand:SI 1 "const_int_operand"))))]
3690 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3691 && REG_P (operands[0])
3692 && M16_REG_P (REGNO (operands[0]))
3693 && GET_CODE (operands[1]) == CONST_INT
3694 && ((INTVAL (operands[1]) < 0
3695 && INTVAL (operands[1]) >= -0x80)
3696 || (INTVAL (operands[1]) >= 32 * 2
3697 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3698 || (INTVAL (operands[1]) >= 0
3699 && INTVAL (operands[1]) < 32 * 2
3700 && (INTVAL (operands[1]) & 1) != 0))"
3701 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3702 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3704 HOST_WIDE_INT val = INTVAL (operands[1]);
3707 operands[2] = const0_rtx;
3708 else if (val >= 32 * 2)
3712 operands[1] = GEN_INT (0x7e + off);
3713 operands[2] = GEN_INT (val - off - 0x7e);
3719 operands[1] = GEN_INT (off);
3720 operands[2] = GEN_INT (val - off);
3724 ;; 8-bit Integer moves
3726 ;; Unlike most other insns, the move insns can't be split with
3727 ;; different predicates, because register spilling and other parts of
3728 ;; the compiler, have memoized the insn number already.
3729 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3731 (define_expand "movqi"
3732 [(set (match_operand:QI 0 "")
3733 (match_operand:QI 1 ""))]
3736 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3740 (define_insn "*movqi_internal"
3741 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3742 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3744 && (register_operand (operands[0], QImode)
3745 || reg_or_0_operand (operands[1], QImode))"
3755 [(set_attr "type" "arith,arith,load,store,mfc,mtc,fmove,mthilo")
3756 (set_attr "mode" "QI")
3757 (set_attr "length" "4,4,*,*,4,4,4,4")])
3759 (define_insn "*movqi_mips16"
3760 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3761 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3763 && (register_operand (operands[0], QImode)
3764 || register_operand (operands[1], QImode))"
3773 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3774 (set_attr "mode" "QI")
3775 (set_attr "length" "4,4,4,4,8,*,*")])
3777 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3778 ;; when the original load is a 4 byte instruction but the add and the
3779 ;; load are 2 2 byte instructions.
3782 [(set (match_operand:QI 0 "register_operand")
3783 (mem:QI (plus:SI (match_dup 0)
3784 (match_operand:SI 1 "const_int_operand"))))]
3785 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3786 && REG_P (operands[0])
3787 && M16_REG_P (REGNO (operands[0]))
3788 && GET_CODE (operands[1]) == CONST_INT
3789 && ((INTVAL (operands[1]) < 0
3790 && INTVAL (operands[1]) >= -0x80)
3791 || (INTVAL (operands[1]) >= 32
3792 && INTVAL (operands[1]) <= 31 + 0x7f))"
3793 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3794 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3796 HOST_WIDE_INT val = INTVAL (operands[1]);
3799 operands[2] = const0_rtx;
3802 operands[1] = GEN_INT (0x7f);
3803 operands[2] = GEN_INT (val - 0x7f);
3807 ;; 32-bit floating point moves
3809 (define_expand "movsf"
3810 [(set (match_operand:SF 0 "")
3811 (match_operand:SF 1 ""))]
3814 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3818 (define_insn "*movsf_hardfloat"
3819 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3820 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3822 && (register_operand (operands[0], SFmode)
3823 || reg_or_0_operand (operands[1], SFmode))"
3824 { return mips_output_move (operands[0], operands[1]); }
3825 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
3826 (set_attr "mode" "SF")
3827 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3829 (define_insn "*movsf_softfloat"
3830 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3831 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3832 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3833 && (register_operand (operands[0], SFmode)
3834 || reg_or_0_operand (operands[1], SFmode))"
3835 { return mips_output_move (operands[0], operands[1]); }
3836 [(set_attr "type" "arith,load,store")
3837 (set_attr "mode" "SF")
3838 (set_attr "length" "4,*,*")])
3840 (define_insn "*movsf_mips16"
3841 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3842 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3844 && (register_operand (operands[0], SFmode)
3845 || register_operand (operands[1], SFmode))"
3846 { return mips_output_move (operands[0], operands[1]); }
3847 [(set_attr "type" "arith,arith,arith,load,store")
3848 (set_attr "mode" "SF")
3849 (set_attr "length" "4,4,4,*,*")])
3852 ;; 64-bit floating point moves
3854 (define_expand "movdf"
3855 [(set (match_operand:DF 0 "")
3856 (match_operand:DF 1 ""))]
3859 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3863 (define_insn "*movdf_hardfloat_64bit"
3864 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3865 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3866 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3867 && (register_operand (operands[0], DFmode)
3868 || reg_or_0_operand (operands[1], DFmode))"
3869 { return mips_output_move (operands[0], operands[1]); }
3870 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
3871 (set_attr "mode" "DF")
3872 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3874 ;; This pattern applies to both !TARGET_FLOAT64 and TARGET_FLOAT64.
3875 (define_insn "*movdf_hardfloat_32bit"
3876 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3877 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3878 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
3879 && (register_operand (operands[0], DFmode)
3880 || reg_or_0_operand (operands[1], DFmode))"
3881 { return mips_output_move (operands[0], operands[1]); }
3882 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
3883 (set_attr "mode" "DF")
3884 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
3886 (define_insn "*movdf_softfloat"
3887 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
3888 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
3889 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
3890 && (register_operand (operands[0], DFmode)
3891 || reg_or_0_operand (operands[1], DFmode))"
3892 { return mips_output_move (operands[0], operands[1]); }
3893 [(set_attr "type" "arith,load,store,mfc,mtc,fmove")
3894 (set_attr "mode" "DF")
3895 (set_attr "length" "8,*,*,4,4,4")])
3897 (define_insn "*movdf_mips16"
3898 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
3899 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
3901 && (register_operand (operands[0], DFmode)
3902 || register_operand (operands[1], DFmode))"
3903 { return mips_output_move (operands[0], operands[1]); }
3904 [(set_attr "type" "arith,arith,arith,load,store")
3905 (set_attr "mode" "DF")
3906 (set_attr "length" "8,8,8,*,*")])
3909 [(set (match_operand:DI 0 "nonimmediate_operand")
3910 (match_operand:DI 1 "move_operand"))]
3911 "reload_completed && !TARGET_64BIT
3912 && mips_split_64bit_move_p (operands[0], operands[1])"
3915 mips_split_64bit_move (operands[0], operands[1]);
3920 [(set (match_operand:DF 0 "nonimmediate_operand")
3921 (match_operand:DF 1 "move_operand"))]
3922 "reload_completed && !TARGET_64BIT
3923 && mips_split_64bit_move_p (operands[0], operands[1])"
3926 mips_split_64bit_move (operands[0], operands[1]);
3930 ;; When generating mips16 code, split moves of negative constants into
3931 ;; a positive "li" followed by a negation.
3933 [(set (match_operand 0 "register_operand")
3934 (match_operand 1 "const_int_operand"))]
3935 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
3939 (neg:SI (match_dup 2)))]
3941 operands[2] = gen_lowpart (SImode, operands[0]);
3942 operands[3] = GEN_INT (-INTVAL (operands[1]));
3945 ;; 64-bit paired-single floating point moves
3947 (define_expand "movv2sf"
3948 [(set (match_operand:V2SF 0)
3949 (match_operand:V2SF 1))]
3950 "TARGET_PAIRED_SINGLE_FLOAT"
3952 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
3956 (define_insn "movv2sf_hardfloat_64bit"
3957 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3958 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
3959 "TARGET_PAIRED_SINGLE_FLOAT
3961 && (register_operand (operands[0], V2SFmode)
3962 || reg_or_0_operand (operands[1], V2SFmode))"
3963 { return mips_output_move (operands[0], operands[1]); }
3964 [(set_attr "type" "fmove,mtc,fpload,fpstore,store,mtc,mfc,arith,load,store")
3965 (set_attr "mode" "SF")
3966 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3968 ;; The HI and LO registers are not truly independent. If we move an mthi
3969 ;; instruction before an mflo instruction, it will make the result of the
3970 ;; mflo unpredictable. The same goes for mtlo and mfhi.
3972 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
3973 ;; Operand 1 is the register we want, operand 2 is the other one.
3975 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
3976 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
3977 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
3979 (define_expand "mfhilo_<mode>"
3980 [(set (match_operand:GPR 0 "register_operand")
3981 (unspec:GPR [(match_operand:GPR 1 "register_operand")
3982 (match_operand:GPR 2 "register_operand")]
3985 (define_insn "*mfhilo_<mode>"
3986 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3987 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
3988 (match_operand:GPR 2 "register_operand" "l,h")]
3992 [(set_attr "type" "mfhilo")
3993 (set_attr "mode" "<MODE>")])
3995 (define_insn "*mfhilo_<mode>_macc"
3996 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3997 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
3998 (match_operand:GPR 2 "register_operand" "l,h")]
4002 if (REGNO (operands[1]) == HI_REGNUM)
4003 return "<d>macchi\t%0,%.,%.";
4005 return "<d>macc\t%0,%.,%.";
4007 [(set_attr "type" "mfhilo")
4008 (set_attr "mode" "<MODE>")])
4010 ;; Patterns for loading or storing part of a paired floating point
4011 ;; register. We need them because odd-numbered floating-point registers
4012 ;; are not fully independent: see mips_split_64bit_move.
4014 ;; Load the low word of operand 0 with operand 1.
4015 (define_insn "load_df_low"
4016 [(set (match_operand:DF 0 "register_operand" "=f,f")
4017 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
4018 UNSPEC_LOAD_DF_LOW))]
4019 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4021 operands[0] = mips_subword (operands[0], 0);
4022 return mips_output_move (operands[0], operands[1]);
4024 [(set_attr "type" "mtc,fpload")
4025 (set_attr "mode" "SF")])
4027 ;; Load the high word of operand 0 from operand 1, preserving the value
4029 (define_insn "load_df_high"
4030 [(set (match_operand:DF 0 "register_operand" "=f,f")
4031 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
4032 (match_operand:DF 2 "register_operand" "0,0")]
4033 UNSPEC_LOAD_DF_HIGH))]
4034 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4036 operands[0] = mips_subword (operands[0], 1);
4037 return mips_output_move (operands[0], operands[1]);
4039 [(set_attr "type" "mtc,fpload")
4040 (set_attr "mode" "SF")])
4042 ;; Store the high word of operand 1 in operand 0. The corresponding
4043 ;; low-word move is done in the normal way.
4044 (define_insn "store_df_high"
4045 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
4046 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
4047 UNSPEC_STORE_DF_HIGH))]
4048 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
4050 operands[1] = mips_subword (operands[1], 1);
4051 return mips_output_move (operands[0], operands[1]);
4053 [(set_attr "type" "mfc,fpstore")
4054 (set_attr "mode" "SF")])
4056 ;; Move operand 1 to the high word of operand 0 using mthc1, preserving the
4057 ;; value in the low word.
4058 (define_insn "mthc1"
4059 [(set (match_operand:DF 0 "register_operand" "=f")
4060 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ")
4061 (match_operand:DF 2 "register_operand" "0")]
4063 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4065 [(set_attr "type" "mtc")
4066 (set_attr "mode" "SF")])
4068 ;; Move high word of operand 1 to operand 0 using mfhc1. The corresponding
4069 ;; low-word move is done in the normal way.
4070 (define_insn "mfhc1"
4071 [(set (match_operand:SI 0 "register_operand" "=d")
4072 (unspec:SI [(match_operand:DF 1 "register_operand" "f")]
4074 "TARGET_HARD_FLOAT && !TARGET_64BIT && ISA_HAS_MXHC1"
4076 [(set_attr "type" "mfc")
4077 (set_attr "mode" "SF")])
4079 ;; Move a constant that satisfies CONST_GP_P into operand 0.
4080 (define_expand "load_const_gp"
4081 [(set (match_operand 0 "register_operand" "=d")
4082 (const (unspec [(const_int 0)] UNSPEC_GP)))])
4084 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
4085 ;; of _gp from the start of this function. Operand 1 is the incoming
4086 ;; function address.
4087 (define_insn_and_split "loadgp_newabi"
4088 [(unspec_volatile [(match_operand 0 "" "")
4089 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
4090 "mips_current_loadgp_style () == LOADGP_NEWABI"
4093 [(set (match_dup 2) (match_dup 3))
4094 (set (match_dup 2) (match_dup 4))
4095 (set (match_dup 2) (match_dup 5))]
4097 operands[2] = pic_offset_table_rtx;
4098 operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
4099 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
4100 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
4102 [(set_attr "length" "12")])
4104 ;; Likewise, for -mno-shared code. Operand 0 is the __gnu_local_gp symbol.
4105 (define_insn_and_split "loadgp_absolute"
4106 [(unspec_volatile [(match_operand 0 "" "")] UNSPEC_LOADGP)]
4107 "mips_current_loadgp_style () == LOADGP_ABSOLUTE"
4112 emit_move_insn (pic_offset_table_rtx, operands[0]);
4115 [(set_attr "length" "8")])
4117 ;; The use of gp is hidden when not using explicit relocations.
4118 ;; This blockage instruction prevents the gp load from being
4119 ;; scheduled after an implicit use of gp. It also prevents
4120 ;; the load from being deleted as dead.
4121 (define_insn "loadgp_blockage"
4122 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
4125 [(set_attr "type" "unknown")
4126 (set_attr "mode" "none")
4127 (set_attr "length" "0")])
4129 ;; Initialize $gp for RTP PIC. Operand 0 is the __GOTT_BASE__ symbol
4130 ;; and operand 1 is the __GOTT_INDEX__ symbol.
4131 (define_insn "loadgp_rtp"
4132 [(unspec_volatile [(match_operand 0 "symbol_ref_operand")
4133 (match_operand 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4134 "mips_current_loadgp_style () == LOADGP_RTP"
4136 [(set_attr "length" "12")])
4139 [(unspec_volatile [(match_operand:P 0 "symbol_ref_operand")
4140 (match_operand:P 1 "symbol_ref_operand")] UNSPEC_LOADGP)]
4141 "mips_current_loadgp_style () == LOADGP_RTP"
4142 [(set (match_dup 2) (high:P (match_dup 3)))
4143 (set (match_dup 2) (unspec:P [(match_dup 2)
4144 (match_dup 3)] UNSPEC_LOAD_GOT))
4145 (set (match_dup 2) (unspec:P [(match_dup 2)
4146 (match_dup 4)] UNSPEC_LOAD_GOT))]
4148 operands[2] = pic_offset_table_rtx;
4149 operands[3] = mips_unspec_address (operands[0], SYMBOL_GENERAL);
4150 operands[4] = mips_unspec_address (operands[1], SYMBOL_HALF);
4153 ;; Emit a .cprestore directive, which normally expands to a single store
4154 ;; instruction. Note that we continue to use .cprestore for explicit reloc
4155 ;; code so that jals inside inline asms will work correctly.
4156 (define_insn "cprestore"
4157 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")]
4161 if (set_nomacro && which_alternative == 1)
4162 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
4164 return ".cprestore\t%0";
4166 [(set_attr "type" "store")
4167 (set_attr "length" "4,12")])
4169 ;; Block moves, see mips.c for more details.
4170 ;; Argument 0 is the destination
4171 ;; Argument 1 is the source
4172 ;; Argument 2 is the length
4173 ;; Argument 3 is the alignment
4175 (define_expand "movmemsi"
4176 [(parallel [(set (match_operand:BLK 0 "general_operand")
4177 (match_operand:BLK 1 "general_operand"))
4178 (use (match_operand:SI 2 ""))
4179 (use (match_operand:SI 3 "const_int_operand"))])]
4180 "!TARGET_MIPS16 && !TARGET_MEMCPY"
4182 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
4189 ;; ....................
4193 ;; ....................
4195 (define_expand "<optab><mode>3"
4196 [(set (match_operand:GPR 0 "register_operand")
4197 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4198 (match_operand:SI 2 "arith_operand")))]
4201 /* On the mips16, a shift of more than 8 is a four byte instruction,
4202 so, for a shift between 8 and 16, it is just as fast to do two
4203 shifts of 8 or less. If there is a lot of shifting going on, we
4204 may win in CSE. Otherwise combine will put the shifts back
4205 together again. This can be called by function_arg, so we must
4206 be careful not to allocate a new register if we've reached the
4210 && GET_CODE (operands[2]) == CONST_INT
4211 && INTVAL (operands[2]) > 8
4212 && INTVAL (operands[2]) <= 16
4213 && !reload_in_progress
4214 && !reload_completed)
4216 rtx temp = gen_reg_rtx (<MODE>mode);
4218 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
4219 emit_insn (gen_<optab><mode>3 (operands[0], temp,
4220 GEN_INT (INTVAL (operands[2]) - 8)));
4225 (define_insn "*<optab><mode>3"
4226 [(set (match_operand:GPR 0 "register_operand" "=d")
4227 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
4228 (match_operand:SI 2 "arith_operand" "dI")))]
4231 if (GET_CODE (operands[2]) == CONST_INT)
4232 operands[2] = GEN_INT (INTVAL (operands[2])
4233 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
4235 return "<d><insn>\t%0,%1,%2";
4237 [(set_attr "type" "shift")
4238 (set_attr "mode" "<MODE>")])
4240 (define_insn "*<optab>si3_extend"
4241 [(set (match_operand:DI 0 "register_operand" "=d")
4243 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
4244 (match_operand:SI 2 "arith_operand" "dI"))))]
4245 "TARGET_64BIT && !TARGET_MIPS16"
4247 if (GET_CODE (operands[2]) == CONST_INT)
4248 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4250 return "<insn>\t%0,%1,%2";
4252 [(set_attr "type" "shift")
4253 (set_attr "mode" "SI")])
4255 (define_insn "*<optab>si3_mips16"
4256 [(set (match_operand:SI 0 "register_operand" "=d,d")
4257 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
4258 (match_operand:SI 2 "arith_operand" "d,I")))]
4261 if (which_alternative == 0)
4262 return "<insn>\t%0,%2";
4264 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
4265 return "<insn>\t%0,%1,%2";
4267 [(set_attr "type" "shift")
4268 (set_attr "mode" "SI")
4269 (set_attr_alternative "length"
4271 (if_then_else (match_operand 2 "m16_uimm3_b")
4275 ;; We need separate DImode MIPS16 patterns because of the irregularity
4277 (define_insn "*ashldi3_mips16"
4278 [(set (match_operand:DI 0 "register_operand" "=d,d")
4279 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4280 (match_operand:SI 2 "arith_operand" "d,I")))]
4281 "TARGET_64BIT && TARGET_MIPS16"
4283 if (which_alternative == 0)
4284 return "dsll\t%0,%2";
4286 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4287 return "dsll\t%0,%1,%2";
4289 [(set_attr "type" "shift")
4290 (set_attr "mode" "DI")
4291 (set_attr_alternative "length"
4293 (if_then_else (match_operand 2 "m16_uimm3_b")
4297 (define_insn "*ashrdi3_mips16"
4298 [(set (match_operand:DI 0 "register_operand" "=d,d")
4299 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4300 (match_operand:SI 2 "arith_operand" "d,I")))]
4301 "TARGET_64BIT && TARGET_MIPS16"
4303 if (GET_CODE (operands[2]) == CONST_INT)
4304 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4306 return "dsra\t%0,%2";
4308 [(set_attr "type" "shift")
4309 (set_attr "mode" "DI")
4310 (set_attr_alternative "length"
4312 (if_then_else (match_operand 2 "m16_uimm3_b")
4316 (define_insn "*lshrdi3_mips16"
4317 [(set (match_operand:DI 0 "register_operand" "=d,d")
4318 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4319 (match_operand:SI 2 "arith_operand" "d,I")))]
4320 "TARGET_64BIT && TARGET_MIPS16"
4322 if (GET_CODE (operands[2]) == CONST_INT)
4323 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4325 return "dsrl\t%0,%2";
4327 [(set_attr "type" "shift")
4328 (set_attr "mode" "DI")
4329 (set_attr_alternative "length"
4331 (if_then_else (match_operand 2 "m16_uimm3_b")
4335 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4338 [(set (match_operand:GPR 0 "register_operand")
4339 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4340 (match_operand:GPR 2 "const_int_operand")))]
4341 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4342 && GET_CODE (operands[2]) == CONST_INT
4343 && INTVAL (operands[2]) > 8
4344 && INTVAL (operands[2]) <= 16"
4345 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4346 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4347 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4349 ;; If we load a byte on the mips16 as a bitfield, the resulting
4350 ;; sequence of instructions is too complicated for combine, because it
4351 ;; involves four instructions: a load, a shift, a constant load into a
4352 ;; register, and an and (the key problem here is that the mips16 does
4353 ;; not have and immediate). We recognize a shift of a load in order
4354 ;; to make it simple enough for combine to understand.
4356 ;; The length here is the worst case: the length of the split version
4357 ;; will be more accurate.
4358 (define_insn_and_split ""
4359 [(set (match_operand:SI 0 "register_operand" "=d")
4360 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4361 (match_operand:SI 2 "immediate_operand" "I")))]
4365 [(set (match_dup 0) (match_dup 1))
4366 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4368 [(set_attr "type" "load")
4369 (set_attr "mode" "SI")
4370 (set_attr "length" "16")])
4372 (define_insn "rotr<mode>3"
4373 [(set (match_operand:GPR 0 "register_operand" "=d")
4374 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4375 (match_operand:SI 2 "arith_operand" "dI")))]
4378 if (GET_CODE (operands[2]) == CONST_INT)
4379 gcc_assert (INTVAL (operands[2]) >= 0
4380 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4382 return "<d>ror\t%0,%1,%2";
4384 [(set_attr "type" "shift")
4385 (set_attr "mode" "<MODE>")])
4388 ;; ....................
4392 ;; ....................
4394 ;; Flow here is rather complex:
4396 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4397 ;; into cmp_operands[] but generates no RTL.
4399 ;; 2) The appropriate branch define_expand is called, which then
4400 ;; creates the appropriate RTL for the comparison and branch.
4401 ;; Different CC modes are used, based on what type of branch is
4402 ;; done, so that we can constrain things appropriately. There
4403 ;; are assumptions in the rest of GCC that break if we fold the
4404 ;; operands into the branches for integer operations, and use cc0
4405 ;; for floating point, so we use the fp status register instead.
4406 ;; If needed, an appropriate temporary is created to hold the
4407 ;; of the integer compare.
4409 (define_expand "cmp<mode>"
4411 (compare:CC (match_operand:GPR 0 "register_operand")
4412 (match_operand:GPR 1 "nonmemory_operand")))]
4415 cmp_operands[0] = operands[0];
4416 cmp_operands[1] = operands[1];
4420 (define_expand "cmp<mode>"
4422 (compare:CC (match_operand:SCALARF 0 "register_operand")
4423 (match_operand:SCALARF 1 "register_operand")))]
4426 cmp_operands[0] = operands[0];
4427 cmp_operands[1] = operands[1];
4432 ;; ....................
4434 ;; CONDITIONAL BRANCHES
4436 ;; ....................
4438 ;; Conditional branches on floating-point equality tests.
4440 (define_insn "*branch_fp"
4443 (match_operator 0 "equality_operator"
4444 [(match_operand:CC 2 "register_operand" "z")
4446 (label_ref (match_operand 1 "" ""))
4450 return mips_output_conditional_branch (insn, operands,
4451 MIPS_BRANCH ("b%F0", "%Z2%1"),
4452 MIPS_BRANCH ("b%W0", "%Z2%1"));
4454 [(set_attr "type" "branch")
4455 (set_attr "mode" "none")])
4457 (define_insn "*branch_fp_inverted"
4460 (match_operator 0 "equality_operator"
4461 [(match_operand:CC 2 "register_operand" "z")
4464 (label_ref (match_operand 1 "" ""))))]
4467 return mips_output_conditional_branch (insn, operands,
4468 MIPS_BRANCH ("b%W0", "%Z2%1"),
4469 MIPS_BRANCH ("b%F0", "%Z2%1"));
4471 [(set_attr "type" "branch")
4472 (set_attr "mode" "none")])
4474 ;; Conditional branches on ordered comparisons with zero.
4476 (define_insn "*branch_order<mode>"
4479 (match_operator 0 "order_operator"
4480 [(match_operand:GPR 2 "register_operand" "d")
4482 (label_ref (match_operand 1 "" ""))
4485 { return mips_output_order_conditional_branch (insn, operands, false); }
4486 [(set_attr "type" "branch")
4487 (set_attr "mode" "none")])
4489 (define_insn "*branch_order<mode>_inverted"
4492 (match_operator 0 "order_operator"
4493 [(match_operand:GPR 2 "register_operand" "d")
4496 (label_ref (match_operand 1 "" ""))))]
4498 { return mips_output_order_conditional_branch (insn, operands, true); }
4499 [(set_attr "type" "branch")
4500 (set_attr "mode" "none")])
4502 ;; Conditional branch on equality comparison.
4504 (define_insn "*branch_equality<mode>"
4507 (match_operator 0 "equality_operator"
4508 [(match_operand:GPR 2 "register_operand" "d")
4509 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4510 (label_ref (match_operand 1 "" ""))
4514 return mips_output_conditional_branch (insn, operands,
4515 MIPS_BRANCH ("b%C0", "%2,%z3,%1"),
4516 MIPS_BRANCH ("b%N0", "%2,%z3,%1"));
4518 [(set_attr "type" "branch")
4519 (set_attr "mode" "none")])
4521 (define_insn "*branch_equality<mode>_inverted"
4524 (match_operator 0 "equality_operator"
4525 [(match_operand:GPR 2 "register_operand" "d")
4526 (match_operand:GPR 3 "reg_or_0_operand" "dJ")])
4528 (label_ref (match_operand 1 "" ""))))]
4531 return mips_output_conditional_branch (insn, operands,
4532 MIPS_BRANCH ("b%N0", "%2,%z3,%1"),
4533 MIPS_BRANCH ("b%C0", "%2,%z3,%1"));
4535 [(set_attr "type" "branch")
4536 (set_attr "mode" "none")])
4540 (define_insn "*branch_equality<mode>_mips16"
4543 (match_operator 0 "equality_operator"
4544 [(match_operand:GPR 1 "register_operand" "d,t")
4546 (match_operand 2 "pc_or_label_operand" "")
4547 (match_operand 3 "pc_or_label_operand" "")))]
4550 if (operands[2] != pc_rtx)
4552 if (which_alternative == 0)
4553 return "b%C0z\t%1,%2";
4555 return "bt%C0z\t%2";
4559 if (which_alternative == 0)
4560 return "b%N0z\t%1,%3";
4562 return "bt%N0z\t%3";
4565 [(set_attr "type" "branch")
4566 (set_attr "mode" "none")
4567 (set_attr "length" "8")])
4569 (define_expand "b<code>"
4571 (if_then_else (any_cond:CC (cc0)
4573 (label_ref (match_operand 0 ""))
4577 gen_conditional_branch (operands, <CODE>);
4581 ;; Used to implement built-in functions.
4582 (define_expand "condjump"
4584 (if_then_else (match_operand 0)
4585 (label_ref (match_operand 1))
4589 ;; ....................
4591 ;; SETTING A REGISTER FROM A COMPARISON
4593 ;; ....................
4595 (define_expand "seq"
4596 [(set (match_operand:SI 0 "register_operand")
4597 (eq:SI (match_dup 1)
4600 { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
4602 (define_insn "*seq_<mode>"
4603 [(set (match_operand:GPR 0 "register_operand" "=d")
4604 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4608 [(set_attr "type" "slt")
4609 (set_attr "mode" "<MODE>")])
4611 (define_insn "*seq_<mode>_mips16"
4612 [(set (match_operand:GPR 0 "register_operand" "=t")
4613 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4617 [(set_attr "type" "slt")
4618 (set_attr "mode" "<MODE>")])
4620 ;; "sne" uses sltu instructions in which the first operand is $0.
4621 ;; This isn't possible in mips16 code.
4623 (define_expand "sne"
4624 [(set (match_operand:SI 0 "register_operand")
4625 (ne:SI (match_dup 1)
4628 { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
4630 (define_insn "*sne_<mode>"
4631 [(set (match_operand:GPR 0 "register_operand" "=d")
4632 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
4636 [(set_attr "type" "slt")
4637 (set_attr "mode" "<MODE>")])
4639 (define_expand "sgt"
4640 [(set (match_operand:SI 0 "register_operand")
4641 (gt:SI (match_dup 1)
4644 { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
4646 (define_insn "*sgt_<mode>"
4647 [(set (match_operand:GPR 0 "register_operand" "=d")
4648 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4649 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4652 [(set_attr "type" "slt")
4653 (set_attr "mode" "<MODE>")])
4655 (define_insn "*sgt_<mode>_mips16"
4656 [(set (match_operand:GPR 0 "register_operand" "=t")
4657 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4658 (match_operand:GPR 2 "register_operand" "d")))]
4661 [(set_attr "type" "slt")
4662 (set_attr "mode" "<MODE>")])
4664 (define_expand "sge"
4665 [(set (match_operand:SI 0 "register_operand")
4666 (ge:SI (match_dup 1)
4669 { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
4671 (define_insn "*sge_<mode>"
4672 [(set (match_operand:GPR 0 "register_operand" "=d")
4673 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
4677 [(set_attr "type" "slt")
4678 (set_attr "mode" "<MODE>")])
4680 (define_expand "slt"
4681 [(set (match_operand:SI 0 "register_operand")
4682 (lt:SI (match_dup 1)
4685 { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
4687 (define_insn "*slt_<mode>"
4688 [(set (match_operand:GPR 0 "register_operand" "=d")
4689 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
4690 (match_operand:GPR 2 "arith_operand" "dI")))]
4693 [(set_attr "type" "slt")
4694 (set_attr "mode" "<MODE>")])
4696 (define_insn "*slt_<mode>_mips16"
4697 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4698 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
4699 (match_operand:GPR 2 "arith_operand" "d,I")))]
4702 [(set_attr "type" "slt")
4703 (set_attr "mode" "<MODE>")
4704 (set_attr_alternative "length"
4706 (if_then_else (match_operand 2 "m16_uimm8_1")
4710 (define_expand "sle"
4711 [(set (match_operand:SI 0 "register_operand")
4712 (le:SI (match_dup 1)
4715 { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
4717 (define_insn "*sle_<mode>"
4718 [(set (match_operand:GPR 0 "register_operand" "=d")
4719 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4720 (match_operand:GPR 2 "sle_operand" "")))]
4723 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4724 return "slt\t%0,%1,%2";
4726 [(set_attr "type" "slt")
4727 (set_attr "mode" "<MODE>")])
4729 (define_insn "*sle_<mode>_mips16"
4730 [(set (match_operand:GPR 0 "register_operand" "=t")
4731 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4732 (match_operand:GPR 2 "sle_operand" "")))]
4735 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4736 return "slt\t%1,%2";
4738 [(set_attr "type" "slt")
4739 (set_attr "mode" "<MODE>")
4740 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4744 (define_expand "sgtu"
4745 [(set (match_operand:SI 0 "register_operand")
4746 (gtu:SI (match_dup 1)
4749 { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
4751 (define_insn "*sgtu_<mode>"
4752 [(set (match_operand:GPR 0 "register_operand" "=d")
4753 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4754 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4757 [(set_attr "type" "slt")
4758 (set_attr "mode" "<MODE>")])
4760 (define_insn "*sgtu_<mode>_mips16"
4761 [(set (match_operand:GPR 0 "register_operand" "=t")
4762 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4763 (match_operand:GPR 2 "register_operand" "d")))]
4766 [(set_attr "type" "slt")
4767 (set_attr "mode" "<MODE>")])
4769 (define_expand "sgeu"
4770 [(set (match_operand:SI 0 "register_operand")
4771 (geu:SI (match_dup 1)
4774 { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
4776 (define_insn "*sge_<mode>"
4777 [(set (match_operand:GPR 0 "register_operand" "=d")
4778 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
4782 [(set_attr "type" "slt")
4783 (set_attr "mode" "<MODE>")])
4785 (define_expand "sltu"
4786 [(set (match_operand:SI 0 "register_operand")
4787 (ltu:SI (match_dup 1)
4790 { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
4792 (define_insn "*sltu_<mode>"
4793 [(set (match_operand:GPR 0 "register_operand" "=d")
4794 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
4795 (match_operand:GPR 2 "arith_operand" "dI")))]
4798 [(set_attr "type" "slt")
4799 (set_attr "mode" "<MODE>")])
4801 (define_insn "*sltu_<mode>_mips16"
4802 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4803 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
4804 (match_operand:GPR 2 "arith_operand" "d,I")))]
4807 [(set_attr "type" "slt")
4808 (set_attr "mode" "<MODE>")
4809 (set_attr_alternative "length"
4811 (if_then_else (match_operand 2 "m16_uimm8_1")
4815 (define_expand "sleu"
4816 [(set (match_operand:SI 0 "register_operand")
4817 (leu:SI (match_dup 1)
4820 { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
4822 (define_insn "*sleu_<mode>"
4823 [(set (match_operand:GPR 0 "register_operand" "=d")
4824 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4825 (match_operand:GPR 2 "sleu_operand" "")))]
4828 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4829 return "sltu\t%0,%1,%2";
4831 [(set_attr "type" "slt")
4832 (set_attr "mode" "<MODE>")])
4834 (define_insn "*sleu_<mode>_mips16"
4835 [(set (match_operand:GPR 0 "register_operand" "=t")
4836 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4837 (match_operand:GPR 2 "sleu_operand" "")))]
4840 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4841 return "sltu\t%1,%2";
4843 [(set_attr "type" "slt")
4844 (set_attr "mode" "<MODE>")
4845 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4850 ;; ....................
4852 ;; FLOATING POINT COMPARISONS
4854 ;; ....................
4856 (define_insn "s<code>_<mode>"
4857 [(set (match_operand:CC 0 "register_operand" "=z")
4858 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4859 (match_operand:SCALARF 2 "register_operand" "f")))]
4861 "c.<fcond>.<fmt>\t%Z0%1,%2"
4862 [(set_attr "type" "fcmp")
4863 (set_attr "mode" "FPSW")])
4865 (define_insn "s<code>_<mode>"
4866 [(set (match_operand:CC 0 "register_operand" "=z")
4867 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4868 (match_operand:SCALARF 2 "register_operand" "f")))]
4870 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
4871 [(set_attr "type" "fcmp")
4872 (set_attr "mode" "FPSW")])
4875 ;; ....................
4877 ;; UNCONDITIONAL BRANCHES
4879 ;; ....................
4881 ;; Unconditional branches.
4885 (label_ref (match_operand 0 "" "")))]
4890 if (get_attr_length (insn) <= 8)
4891 return "%*b\t%l0%/";
4894 output_asm_insn (mips_output_load_label (), operands);
4895 return "%*jr\t%@%/%]";
4899 return "%*j\t%l0%/";
4901 [(set_attr "type" "jump")
4902 (set_attr "mode" "none")
4903 (set (attr "length")
4904 ;; We can't use `j' when emitting PIC. Emit a branch if it's
4905 ;; in range, otherwise load the address of the branch target into
4906 ;; $at and then jump to it.
4908 (ior (eq (symbol_ref "flag_pic") (const_int 0))
4909 (lt (abs (minus (match_dup 0)
4910 (plus (pc) (const_int 4))))
4911 (const_int 131072)))
4912 (const_int 4) (const_int 16)))])
4914 ;; We need a different insn for the mips16, because a mips16 branch
4915 ;; does not have a delay slot.
4919 (label_ref (match_operand 0 "" "")))]
4922 [(set_attr "type" "branch")
4923 (set_attr "mode" "none")
4924 (set_attr "length" "8")])
4926 (define_expand "indirect_jump"
4927 [(set (pc) (match_operand 0 "register_operand"))]
4930 operands[0] = force_reg (Pmode, operands[0]);
4931 if (Pmode == SImode)
4932 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
4934 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
4938 (define_insn "indirect_jump<mode>"
4939 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
4942 [(set_attr "type" "jump")
4943 (set_attr "mode" "none")])
4945 (define_expand "tablejump"
4947 (match_operand 0 "register_operand"))
4948 (use (label_ref (match_operand 1 "")))]
4952 operands[0] = expand_binop (Pmode, add_optab,
4953 convert_to_mode (Pmode, operands[0], false),
4954 gen_rtx_LABEL_REF (Pmode, operands[1]),
4956 else if (TARGET_GPWORD)
4957 operands[0] = expand_binop (Pmode, add_optab, operands[0],
4958 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
4959 else if (TARGET_RTP_PIC)
4961 /* When generating RTP PIC, we use case table entries that are relative
4962 to the start of the function. Add the function's address to the
4964 rtx start = get_hard_reg_initial_val (Pmode, PIC_FUNCTION_ADDR_REGNUM);
4965 operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
4966 start, 0, 0, OPTAB_WIDEN);
4969 if (Pmode == SImode)
4970 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
4972 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
4976 (define_insn "tablejump<mode>"
4978 (match_operand:P 0 "register_operand" "d"))
4979 (use (label_ref (match_operand 1 "" "")))]
4982 [(set_attr "type" "jump")
4983 (set_attr "mode" "none")])
4985 ;; For TARGET_USE_GOT, we save the gp in the jmp_buf as well.
4986 ;; While it is possible to either pull it off the stack (in the
4987 ;; o32 case) or recalculate it given t9 and our target label,
4988 ;; it takes 3 or 4 insns to do so.
4990 (define_expand "builtin_setjmp_setup"
4991 [(use (match_operand 0 "register_operand"))]
4996 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
4997 emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
5001 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
5002 ;; that older code did recalculate the gp from $25. Continue to jump through
5003 ;; $25 for compatibility (we lose nothing by doing so).
5005 (define_expand "builtin_longjmp"
5006 [(use (match_operand 0 "register_operand"))]
5009 /* The elements of the buffer are, in order: */
5010 int W = GET_MODE_SIZE (Pmode);
5011 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5012 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
5013 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
5014 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
5015 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
5016 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
5017 The target is bound to be using $28 as the global pointer
5018 but the current function might not be. */
5019 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
5021 /* This bit is similar to expand_builtin_longjmp except that it
5022 restores $gp as well. */
5023 emit_move_insn (hard_frame_pointer_rtx, fp);
5024 emit_move_insn (pv, lab);
5025 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5026 emit_move_insn (gp, gpv);
5027 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5028 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5029 emit_insn (gen_rtx_USE (VOIDmode, gp));
5030 emit_indirect_jump (pv);
5035 ;; ....................
5037 ;; Function prologue/epilogue
5039 ;; ....................
5042 (define_expand "prologue"
5046 mips_expand_prologue ();
5050 ;; Block any insns from being moved before this point, since the
5051 ;; profiling call to mcount can use various registers that aren't
5052 ;; saved or used to pass arguments.
5054 (define_insn "blockage"
5055 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
5058 [(set_attr "type" "unknown")
5059 (set_attr "mode" "none")
5060 (set_attr "length" "0")])
5062 (define_expand "epilogue"
5066 mips_expand_epilogue (false);
5070 (define_expand "sibcall_epilogue"
5074 mips_expand_epilogue (true);
5078 ;; Trivial return. Make it look like a normal return insn as that
5079 ;; allows jump optimizations to work better.
5081 (define_insn "return"
5083 "mips_can_use_return_insn ()"
5085 [(set_attr "type" "jump")
5086 (set_attr "mode" "none")])
5090 (define_insn "return_internal"
5092 (use (match_operand 0 "pmode_register_operand" ""))]
5095 [(set_attr "type" "jump")
5096 (set_attr "mode" "none")])
5098 ;; This is used in compiling the unwind routines.
5099 (define_expand "eh_return"
5100 [(use (match_operand 0 "general_operand"))]
5103 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
5105 if (GET_MODE (operands[0]) != gpr_mode)
5106 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
5108 emit_insn (gen_eh_set_lr_di (operands[0]));
5110 emit_insn (gen_eh_set_lr_si (operands[0]));
5115 ;; Clobber the return address on the stack. We can't expand this
5116 ;; until we know where it will be put in the stack frame.
5118 (define_insn "eh_set_lr_si"
5119 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5120 (clobber (match_scratch:SI 1 "=&d"))]
5124 (define_insn "eh_set_lr_di"
5125 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
5126 (clobber (match_scratch:DI 1 "=&d"))]
5131 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
5132 (clobber (match_scratch 1))]
5133 "reload_completed && !TARGET_DEBUG_D_MODE"
5136 mips_set_return_address (operands[0], operands[1]);
5140 (define_insn_and_split "exception_receiver"
5142 (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
5143 "TARGET_CALL_CLOBBERED_GP"
5145 "&& reload_completed"
5151 [(set_attr "type" "load")
5152 (set_attr "length" "12")])
5155 ;; ....................
5159 ;; ....................
5161 ;; Instructions to load a call address from the GOT. The address might
5162 ;; point to a function or to a lazy binding stub. In the latter case,
5163 ;; the stub will use the dynamic linker to resolve the function, which
5164 ;; in turn will change the GOT entry to point to the function's real
5167 ;; This means that every call, even pure and constant ones, can
5168 ;; potentially modify the GOT entry. And once a stub has been called,
5169 ;; we must not call it again.
5171 ;; We represent this restriction using an imaginary fixed register that
5172 ;; acts like a GOT version number. By making the register call-clobbered,
5173 ;; we tell the target-independent code that the address could be changed
5174 ;; by any call insn.
5175 (define_insn "load_call<mode>"
5176 [(set (match_operand:P 0 "register_operand" "=d")
5177 (unspec:P [(match_operand:P 1 "register_operand" "r")
5178 (match_operand:P 2 "immediate_operand" "")
5179 (reg:P FAKE_CALL_REGNO)]
5182 "<load>\t%0,%R2(%1)"
5183 [(set_attr "type" "load")
5184 (set_attr "mode" "<MODE>")
5185 (set_attr "length" "4")])
5187 ;; Sibling calls. All these patterns use jump instructions.
5189 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
5190 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
5191 ;; is defined in terms of call_insn_operand, the same is true of the
5194 ;; When we use an indirect jump, we need a register that will be
5195 ;; preserved by the epilogue. Since TARGET_USE_PIC_FN_ADDR_REG forces
5196 ;; us to use $25 for this purpose -- and $25 is never clobbered by the
5197 ;; epilogue -- we might as well use it for !TARGET_USE_PIC_FN_ADDR_REG
5200 (define_expand "sibcall"
5201 [(parallel [(call (match_operand 0 "")
5202 (match_operand 1 ""))
5203 (use (match_operand 2 "")) ;; next_arg_reg
5204 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5207 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
5211 (define_insn "sibcall_internal"
5212 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
5213 (match_operand 1 "" ""))]
5214 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5215 { return MIPS_CALL ("j", operands, 0); }
5216 [(set_attr "type" "call")])
5218 (define_expand "sibcall_value"
5219 [(parallel [(set (match_operand 0 "")
5220 (call (match_operand 1 "")
5221 (match_operand 2 "")))
5222 (use (match_operand 3 ""))])] ;; next_arg_reg
5225 mips_expand_call (operands[0], XEXP (operands[1], 0),
5226 operands[2], operands[3], true);
5230 (define_insn "sibcall_value_internal"
5231 [(set (match_operand 0 "register_operand" "")
5232 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5233 (match_operand 2 "" "")))]
5234 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5235 { return MIPS_CALL ("j", operands, 1); }
5236 [(set_attr "type" "call")])
5238 (define_insn "sibcall_value_multiple_internal"
5239 [(set (match_operand 0 "register_operand" "")
5240 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
5241 (match_operand 2 "" "")))
5242 (set (match_operand 3 "register_operand" "")
5243 (call (mem:SI (match_dup 1))
5245 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
5246 { return MIPS_CALL ("j", operands, 1); }
5247 [(set_attr "type" "call")])
5249 (define_expand "call"
5250 [(parallel [(call (match_operand 0 "")
5251 (match_operand 1 ""))
5252 (use (match_operand 2 "")) ;; next_arg_reg
5253 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5256 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
5260 ;; This instruction directly corresponds to an assembly-language "jal".
5261 ;; There are four cases:
5264 ;; Both symbolic and register destinations are OK. The pattern
5265 ;; always expands to a single mips instruction.
5267 ;; - -mabicalls/-mno-explicit-relocs:
5268 ;; Again, both symbolic and register destinations are OK.
5269 ;; The call is treated as a multi-instruction black box.
5271 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5272 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5275 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5276 ;; Only "jal $25" is allowed. The call is actually two instructions:
5277 ;; "jalr $25" followed by an insn to reload $gp.
5279 ;; In the last case, we can generate the individual instructions with
5280 ;; a define_split. There are several things to be wary of:
5282 ;; - We can't expose the load of $gp before reload. If we did,
5283 ;; it might get removed as dead, but reload can introduce new
5284 ;; uses of $gp by rematerializing constants.
5286 ;; - We shouldn't restore $gp after calls that never return.
5287 ;; It isn't valid to insert instructions between a noreturn
5288 ;; call and the following barrier.
5290 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5291 ;; instruction preserves $gp and so have no effect on its liveness.
5292 ;; But once we generate the separate insns, it becomes obvious that
5293 ;; $gp is not live on entry to the call.
5295 ;; ??? The operands[2] = insn check is a hack to make the original insn
5296 ;; available to the splitter.
5297 (define_insn_and_split "call_internal"
5298 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5299 (match_operand 1 "" ""))
5300 (clobber (reg:SI 31))]
5302 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 0); }
5303 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5306 emit_call_insn (gen_call_split (operands[0], operands[1]));
5307 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5311 [(set_attr "jal" "indirect,direct")
5312 (set_attr "extended_mips16" "no,yes")])
5314 (define_insn "call_split"
5315 [(call (mem:SI (match_operand 0 "call_insn_operand" "cS"))
5316 (match_operand 1 "" ""))
5317 (clobber (reg:SI 31))
5318 (clobber (reg:SI 28))]
5319 "TARGET_SPLIT_CALLS"
5320 { return MIPS_CALL ("jal", operands, 0); }
5321 [(set_attr "type" "call")])
5323 (define_expand "call_value"
5324 [(parallel [(set (match_operand 0 "")
5325 (call (match_operand 1 "")
5326 (match_operand 2 "")))
5327 (use (match_operand 3 ""))])] ;; next_arg_reg
5330 mips_expand_call (operands[0], XEXP (operands[1], 0),
5331 operands[2], operands[3], false);
5335 ;; See comment for call_internal.
5336 (define_insn_and_split "call_value_internal"
5337 [(set (match_operand 0 "register_operand" "")
5338 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5339 (match_operand 2 "" "")))
5340 (clobber (reg:SI 31))]
5342 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5343 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5346 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5348 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5352 [(set_attr "jal" "indirect,direct")
5353 (set_attr "extended_mips16" "no,yes")])
5355 (define_insn "call_value_split"
5356 [(set (match_operand 0 "register_operand" "")
5357 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5358 (match_operand 2 "" "")))
5359 (clobber (reg:SI 31))
5360 (clobber (reg:SI 28))]
5361 "TARGET_SPLIT_CALLS"
5362 { return MIPS_CALL ("jal", operands, 1); }
5363 [(set_attr "type" "call")])
5365 ;; See comment for call_internal.
5366 (define_insn_and_split "call_value_multiple_internal"
5367 [(set (match_operand 0 "register_operand" "")
5368 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5369 (match_operand 2 "" "")))
5370 (set (match_operand 3 "register_operand" "")
5371 (call (mem:SI (match_dup 1))
5373 (clobber (reg:SI 31))]
5375 { return TARGET_SPLIT_CALLS ? "#" : MIPS_CALL ("jal", operands, 1); }
5376 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5379 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5380 operands[2], operands[3]));
5381 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5385 [(set_attr "jal" "indirect,direct")
5386 (set_attr "extended_mips16" "no,yes")])
5388 (define_insn "call_value_multiple_split"
5389 [(set (match_operand 0 "register_operand" "")
5390 (call (mem:SI (match_operand 1 "call_insn_operand" "cS"))
5391 (match_operand 2 "" "")))
5392 (set (match_operand 3 "register_operand" "")
5393 (call (mem:SI (match_dup 1))
5395 (clobber (reg:SI 31))
5396 (clobber (reg:SI 28))]
5397 "TARGET_SPLIT_CALLS"
5398 { return MIPS_CALL ("jal", operands, 1); }
5399 [(set_attr "type" "call")])
5401 ;; Call subroutine returning any type.
5403 (define_expand "untyped_call"
5404 [(parallel [(call (match_operand 0 "")
5406 (match_operand 1 "")
5407 (match_operand 2 "")])]
5412 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5414 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5416 rtx set = XVECEXP (operands[2], 0, i);
5417 emit_move_insn (SET_DEST (set), SET_SRC (set));
5420 emit_insn (gen_blockage ());
5425 ;; ....................
5429 ;; ....................
5433 (define_insn "prefetch"
5434 [(prefetch (match_operand:QI 0 "address_operand" "p")
5435 (match_operand 1 "const_int_operand" "n")
5436 (match_operand 2 "const_int_operand" "n"))]
5437 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5439 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5440 return "pref\t%1,%a0";
5442 [(set_attr "type" "prefetch")])
5444 (define_insn "*prefetch_indexed_<mode>"
5445 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5446 (match_operand:P 1 "register_operand" "d"))
5447 (match_operand 2 "const_int_operand" "n")
5448 (match_operand 3 "const_int_operand" "n"))]
5449 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5451 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
5452 return "prefx\t%2,%1(%0)";
5454 [(set_attr "type" "prefetchx")])
5460 [(set_attr "type" "nop")
5461 (set_attr "mode" "none")])
5463 ;; Like nop, but commented out when outside a .set noreorder block.
5464 (define_insn "hazard_nop"
5473 [(set_attr "type" "nop")])
5475 ;; MIPS4 Conditional move instructions.
5477 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
5478 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5480 (match_operator:MOVECC 4 "equality_operator"
5481 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5483 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
5484 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
5489 [(set_attr "type" "condmove")
5490 (set_attr "mode" "<GPR:MODE>")])
5492 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
5493 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
5494 (if_then_else:SCALARF
5495 (match_operator:MOVECC 4 "equality_operator"
5496 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5498 (match_operand:SCALARF 2 "register_operand" "f,0")
5499 (match_operand:SCALARF 3 "register_operand" "0,f")))]
5502 mov%T4.<fmt>\t%0,%2,%1
5503 mov%t4.<fmt>\t%0,%3,%1"
5504 [(set_attr "type" "condmove")
5505 (set_attr "mode" "<SCALARF:MODE>")])
5507 ;; These are the main define_expand's used to make conditional moves.
5509 (define_expand "mov<mode>cc"
5510 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5511 (set (match_operand:GPR 0 "register_operand")
5512 (if_then_else:GPR (match_dup 5)
5513 (match_operand:GPR 2 "reg_or_0_operand")
5514 (match_operand:GPR 3 "reg_or_0_operand")))]
5517 gen_conditional_move (operands);
5521 (define_expand "mov<mode>cc"
5522 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5523 (set (match_operand:SCALARF 0 "register_operand")
5524 (if_then_else:SCALARF (match_dup 5)
5525 (match_operand:SCALARF 2 "register_operand")
5526 (match_operand:SCALARF 3 "register_operand")))]
5529 gen_conditional_move (operands);
5534 ;; ....................
5536 ;; mips16 inline constant tables
5538 ;; ....................
5541 (define_insn "consttable_int"
5542 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
5543 (match_operand 1 "const_int_operand" "")]
5544 UNSPEC_CONSTTABLE_INT)]
5547 assemble_integer (operands[0], INTVAL (operands[1]),
5548 BITS_PER_UNIT * INTVAL (operands[1]), 1);
5551 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
5553 (define_insn "consttable_float"
5554 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
5555 UNSPEC_CONSTTABLE_FLOAT)]
5560 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
5561 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
5562 assemble_real (d, GET_MODE (operands[0]),
5563 GET_MODE_BITSIZE (GET_MODE (operands[0])));
5566 [(set (attr "length")
5567 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
5569 (define_insn "align"
5570 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
5573 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
5576 [(match_operand 0 "small_data_pattern")]
5579 { operands[0] = mips_rewrite_small_data (operands[0]); })
5581 ; Thread-Local Storage
5583 ; The TLS base pointer is accessed via "rdhwr $v1, $29". No current
5584 ; MIPS architecture defines this register, and no current
5585 ; implementation provides it; instead, any OS which supports TLS is
5586 ; expected to trap and emulate this instruction. rdhwr is part of the
5587 ; MIPS 32r2 specification, but we use it on any architecture because
5588 ; we expect it to be emulated. Use .set to force the assembler to
5591 (define_insn "tls_get_tp_<mode>"
5592 [(set (match_operand:P 0 "register_operand" "=v")
5593 (unspec:P [(const_int 0)]
5594 UNSPEC_TLS_GET_TP))]
5595 "HAVE_AS_TLS && !TARGET_MIPS16"
5596 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
5597 [(set_attr "type" "unknown")
5598 ; Since rdhwr always generates a trap for now, putting it in a delay
5599 ; slot would make the kernel's emulation of it much slower.
5600 (set_attr "can_delay" "no")
5601 (set_attr "mode" "<MODE>")])
5603 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
5605 (include "mips-ps-3d.md")
5607 ; The MIPS DSP Instructions.
5609 (include "mips-dsp.md")
5611 ; The MIPS DSP REV 2 Instructions.
5613 (include "mips-dspr2.md")