1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
5 ;; Changes by Michael Meissner, meissner@osf.org
6 ;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 ;; Brendan Eich, brendan@microunity.com.
9 ;; This file is part of GNU CC.
11 ;; GNU CC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 2, or (at your option)
16 ;; GNU CC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GNU CC; see the file COPYING. If not, write to
23 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
24 ;; Boston, MA 02111-1307, USA.
26 ;; ??? Currently does not have define_function_unit support for the R8000.
27 ;; Must include new entries for fmadd in addition to existing entries.
40 (UNSPEC_EH_RECEIVER 10)
42 (UNSPEC_CONSTTABLE_QI 12)
43 (UNSPEC_CONSTTABLE_HI 13)
44 (UNSPEC_CONSTTABLE_SI 14)
45 (UNSPEC_CONSTTABLE_DI 15)
46 (UNSPEC_CONSTTABLE_SF 16)
47 (UNSPEC_CONSTTABLE_DF 17)
53 ;; ....................
57 ;; ....................
59 ;; Classification of each insn.
60 ;; branch conditional branch
61 ;; jump unconditional jump
62 ;; call unconditional call
63 ;; load load instruction(s)
64 ;; store store instruction(s)
65 ;; move data movement within same register set
66 ;; xfer transfer to/from coprocessor
67 ;; hilo transfer of hi/lo registers
68 ;; arith integer arithmetic instruction
69 ;; darith double precision integer arithmetic instructions
70 ;; imul integer multiply
71 ;; imadd integer multiply-add
72 ;; idiv integer divide
73 ;; icmp integer compare
74 ;; fadd floating point add/subtract
75 ;; fmul floating point multiply
76 ;; fmadd floating point multiply-add
77 ;; fdiv floating point divide
78 ;; fabs floating point absolute value
79 ;; fneg floating point negation
80 ;; fcmp floating point compare
81 ;; fcvt floating point convert
82 ;; fsqrt floating point square root
83 ;; multi multiword sequence (or user asm statements)
87 "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
88 (const_string "unknown"))
90 ;; Main data type used by the insn
91 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
93 ;; Length (in # of bytes). A conditional branch is allowed only to a
94 ;; location within a signed 18-bit offset of the delay slot. If that
95 ;; provides too smal a range, we use the `j' instruction. This
96 ;; instruction takes a 28-bit value, but that value is not an offset.
97 ;; Instead, it's bitwise-ored with the high-order four bits of the
98 ;; instruction in the delay slot, which means it cannot be used to
99 ;; cross a 256MB boundary. We could fall back back on the jr,
100 ;; instruction which allows full access to the entire address space,
101 ;; but we do not do so at present.
103 (define_attr "length" ""
104 (cond [(eq_attr "type" "branch")
105 (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
111 ;; Attribute describing the processor. This attribute must match exactly
112 ;; with the processor_type enumeration in mips.h.
114 ;; Attribute describing the processor
115 ;; (define_attr "cpu" "default,r3000,r6000,r4000"
117 ;; (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000")
118 ;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000")
119 ;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")]
120 ;; (const_string "default"))))
122 ;; ??? Fix everything that tests this attribute.
124 "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000,r4kc,r5kc,r20kc"
125 (const (symbol_ref "mips_cpu_attr")))
127 ;; Does the instruction have a mandatory delay slot?
128 ;; The 3900, is (mostly) mips1, but does not have a mandatory load delay
130 (define_attr "dslot" "no,yes"
131 (if_then_else (ior (eq_attr "type" "branch,jump,call,xfer,hilo,fcmp")
132 (and (eq_attr "type" "load")
133 (and (eq (symbol_ref "mips_isa") (const_int 1))
134 (and (eq (symbol_ref "mips16") (const_int 0))
135 (eq_attr "cpu" "!r3900")))))
137 (const_string "no")))
139 ;; Can the instruction be put into a delay slot?
140 (define_attr "can_delay" "no,yes"
141 (if_then_else (and (eq_attr "dslot" "no")
142 ; ADJUST_INSN_LENGTH divides length by 2 on mips16,
143 ; so cope with it here.
144 (ior (and (eq (symbol_ref "mips16") (const_int 0))
145 (eq_attr "length" "4"))
146 (and (ne (symbol_ref "mips16") (const_int 0))
147 (eq_attr "length" "2"))))
149 (const_string "no")))
151 ;; Attribute defining whether or not we can use the branch-likely instructions
153 (define_attr "branch_likely" "no,yes"
155 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
157 (const_string "no"))))
160 ;; Describe a user's asm statement.
161 (define_asm_attributes
162 [(set_attr "type" "multi")])
164 ;; whether or not generating calls to position independent functions
165 (define_attr "abicalls" "no,yes"
166 (const (symbol_ref "mips_abicalls_attr")))
170 ;; .........................
172 ;; Delay slots, can't describe load/fcmp/xfer delay slots here
174 ;; .........................
176 (define_delay (and (eq_attr "type" "branch")
177 (eq (symbol_ref "mips16") (const_int 0)))
178 [(eq_attr "can_delay" "yes")
180 (and (eq_attr "branch_likely" "yes")
181 (and (eq_attr "dslot" "no")
182 (eq_attr "length" "4")))])
184 (define_delay (eq_attr "type" "jump")
185 [(eq_attr "can_delay" "yes")
189 (define_delay (and (eq_attr "type" "call") (eq_attr "abicalls" "no"))
190 [(eq_attr "can_delay" "yes")
196 ;; .........................
200 ;; .........................
202 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
203 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
205 ;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
207 (define_function_unit "memory" 1 0
208 (and (eq_attr "type" "load")
209 (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
212 (define_function_unit "memory" 1 0
213 (and (eq_attr "type" "load")
214 (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
217 (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
219 (define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
221 (define_function_unit "imuldiv" 1 0
222 (eq_attr "type" "hilo")
225 (define_function_unit "imuldiv" 1 0
226 (and (eq_attr "type" "imul,imadd")
227 (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
230 ;; On them mips16, we want to stronly discourage a mult from appearing
231 ;; after an mflo, since that requires explicit nop instructions. We
232 ;; do this by pretending that mflo ties up the function unit for long
233 ;; enough that the scheduler will ignore load stalls and the like when
234 ;; selecting instructions to between the two instructions.
236 (define_function_unit "imuldiv" 1 0
237 (and (eq_attr "type" "hilo") (ne (symbol_ref "mips16") (const_int 0)))
240 (define_function_unit "imuldiv" 1 0
241 (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r3000,r3900"))
244 (define_function_unit "imuldiv" 1 0
245 (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4000,r4600"))
248 (define_function_unit "imuldiv" 1 0
249 (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4650"))
252 (define_function_unit "imuldiv" 1 0
253 (and (eq_attr "type" "imul,imadd")
254 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
257 (define_function_unit "imuldiv" 1 0
258 (and (eq_attr "type" "imul,imadd")
259 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
262 (define_function_unit "imuldiv" 1 0
263 (and (eq_attr "type" "imul,imadd")
264 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000")))
267 (define_function_unit "imuldiv" 1 0
268 (and (eq_attr "type" "imul,imadd")
269 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
272 (define_function_unit "imuldiv" 1 0
273 (and (eq_attr "type" "imul,imadd")
274 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
277 (define_function_unit "imuldiv" 1 0
278 (and (eq_attr "type" "idiv")
279 (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
282 (define_function_unit "imuldiv" 1 0
283 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000,r3900"))
286 (define_function_unit "imuldiv" 1 0
287 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
290 (define_function_unit "imuldiv" 1 0
291 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650"))
294 (define_function_unit "imuldiv" 1 0
295 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
298 (define_function_unit "imuldiv" 1 0
299 (and (eq_attr "type" "idiv")
300 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
303 (define_function_unit "imuldiv" 1 0
304 (and (eq_attr "type" "idiv")
305 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
308 (define_function_unit "imuldiv" 1 0
309 (and (eq_attr "type" "idiv")
310 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300")))
313 (define_function_unit "imuldiv" 1 0
314 (and (eq_attr "type" "idiv")
315 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
318 (define_function_unit "imuldiv" 1 0
319 (and (eq_attr "type" "idiv")
320 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000")))
323 (define_function_unit "imuldiv" 1 0
324 (and (eq_attr "type" "idiv")
325 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
328 ;; The R4300 does *NOT* have a separate Floating Point Unit, instead
329 ;; the FP hardware is part of the normal ALU circuitry. This means FP
330 ;; instructions affect the pipe-line, and no functional unit
331 ;; parallelism can occur on R4300 processors. To force GCC into coding
332 ;; for only a single functional unit, we force the R4300 FP
333 ;; instructions to be processed in the "imuldiv" unit.
335 (define_function_unit "adder" 1 1
336 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))
339 (define_function_unit "adder" 1 1
340 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000"))
343 (define_function_unit "adder" 1 1
344 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000"))
347 (define_function_unit "adder" 1 1
348 (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300"))
351 (define_function_unit "adder" 1 1
352 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000,r3900"))
355 (define_function_unit "adder" 1 1
356 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
359 (define_function_unit "adder" 1 1
360 (and (eq_attr "type" "fabs,fneg")
361 (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
364 (define_function_unit "adder" 1 1
365 (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
368 (define_function_unit "mult" 1 1
369 (and (eq_attr "type" "fmul")
370 (and (eq_attr "mode" "SF")
371 (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
374 (define_function_unit "mult" 1 1
375 (and (eq_attr "type" "fmul")
376 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900,r5000")))
379 (define_function_unit "mult" 1 1
380 (and (eq_attr "type" "fmul")
381 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
384 (define_function_unit "mult" 1 1
385 (and (eq_attr "type" "fmul")
386 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
389 (define_function_unit "mult" 1 1
390 (and (eq_attr "type" "fmul")
391 (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")))
394 (define_function_unit "mult" 1 1
395 (and (eq_attr "type" "fmul")
396 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900,r5000")))
399 (define_function_unit "mult" 1 1
400 (and (eq_attr "type" "fmul")
401 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
404 (define_function_unit "divide" 1 1
405 (and (eq_attr "type" "fdiv")
406 (and (eq_attr "mode" "SF")
407 (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
410 (define_function_unit "divide" 1 1
411 (and (eq_attr "type" "fdiv")
412 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900")))
415 (define_function_unit "divide" 1 1
416 (and (eq_attr "type" "fdiv")
417 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
420 (define_function_unit "divide" 1 1
421 (and (eq_attr "type" "fdiv")
422 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
425 (define_function_unit "divide" 1 1
426 (and (eq_attr "type" "fdiv")
427 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
430 (define_function_unit "divide" 1 1
431 (and (eq_attr "type" "fdiv")
432 (and (eq_attr "mode" "DF")
433 (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300")))
436 (define_function_unit "divide" 1 1
437 (and (eq_attr "type" "fdiv")
438 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900")))
441 (define_function_unit "divide" 1 1
442 (and (eq_attr "type" "fdiv")
443 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
446 (define_function_unit "divide" 1 1
447 (and (eq_attr "type" "fdiv")
448 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
451 ;;; ??? Is this number right?
452 (define_function_unit "divide" 1 1
453 (and (eq_attr "type" "fsqrt")
454 (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
457 (define_function_unit "divide" 1 1
458 (and (eq_attr "type" "fsqrt")
459 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
462 (define_function_unit "divide" 1 1
463 (and (eq_attr "type" "fsqrt")
464 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
467 ;;; ??? Is this number right?
468 (define_function_unit "divide" 1 1
469 (and (eq_attr "type" "fsqrt")
470 (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
473 (define_function_unit "divide" 1 1
474 (and (eq_attr "type" "fsqrt")
475 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
478 (define_function_unit "divide" 1 1
479 (and (eq_attr "type" "fsqrt")
480 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
483 ;; R4300 FP instruction classes treated as part of the "imuldiv"
486 (define_function_unit "imuldiv" 1 0
487 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
490 (define_function_unit "imuldiv" 1 0
491 (and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300"))
494 (define_function_unit "imuldiv" 1 0
495 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
497 (define_function_unit "imuldiv" 1 0
498 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
501 (define_function_unit "imuldiv" 1 0
502 (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt"))
503 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
505 (define_function_unit "imuldiv" 1 0
506 (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt"))
507 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
510 ;; The following functional units do not use the cpu type, and use
511 ;; much less memory in genattrtab.c.
513 ;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0)
514 ;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
516 ;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0)
518 ;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0)
519 ;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0)
521 ;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0)
522 ;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0)
524 ;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0)
525 ;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0)
527 ;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0)
528 ;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0)
530 ;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0)
531 ;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0)
533 ;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0)
534 ;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
537 ;; ....................
541 ;; ....................
545 [(trap_if (const_int 1) (const_int 0))]
549 if (ISA_HAS_COND_TRAP)
550 return \"teq\\t$0,$0\";
551 else if (TARGET_MIPS16)
557 (define_expand "conditional_trap"
558 [(trap_if (match_operator 0 "cmp_op"
559 [(match_dup 2) (match_dup 3)])
560 (match_operand 1 "const_int_operand" ""))]
564 mips_gen_conditional_trap (operands);
568 ;; Match a TRAP_IF with 2nd arg of 0. The div_trap_* insns match a
569 ;; 2nd arg of any CONST_INT, so this insn must appear first.
570 ;; gen_div_trap always generates TRAP_IF with 2nd arg of 6 or 7.
573 [(trap_if (match_operator 0 "trap_cmp_op"
574 [(match_operand:SI 1 "reg_or_0_operand" "d")
575 (match_operand:SI 2 "nonmemory_operand" "dI")])
581 ;; ....................
585 ;; ....................
588 (define_insn "adddf3"
589 [(set (match_operand:DF 0 "register_operand" "=f")
590 (plus:DF (match_operand:DF 1 "register_operand" "f")
591 (match_operand:DF 2 "register_operand" "f")))]
592 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
594 [(set_attr "type" "fadd")
595 (set_attr "mode" "DF")])
597 (define_insn "addsf3"
598 [(set (match_operand:SF 0 "register_operand" "=f")
599 (plus:SF (match_operand:SF 1 "register_operand" "f")
600 (match_operand:SF 2 "register_operand" "f")))]
603 [(set_attr "type" "fadd")
604 (set_attr "mode" "SF")])
606 (define_expand "addsi3"
607 [(set (match_operand:SI 0 "register_operand" "=d")
608 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
609 (match_operand:SI 2 "arith_operand" "dI")))]
613 /* The mips16 assembler handles -32768 correctly, and so does gas,
614 but some other MIPS assemblers think that -32768 needs to be
615 loaded into a register before it can be added in. */
618 && GET_CODE (operands[2]) == CONST_INT
619 && INTVAL (operands[2]) == -32768)
620 operands[2] = force_reg (SImode, operands[2]);
622 /* If a large stack adjustment was forced into a register, we may be
623 asked to generate rtx such as:
625 (set (reg:SI sp) (plus:SI (reg:SI sp) (reg:SI pseudo)))
627 but no such instruction is available in mips16. Handle it by
628 using a temporary. */
630 && REGNO (operands[0]) == STACK_POINTER_REGNUM
631 && ((GET_CODE (operands[1]) == REG
632 && REGNO (operands[1]) != STACK_POINTER_REGNUM)
633 || GET_CODE (operands[2]) != CONST_INT))
635 rtx tmp = gen_reg_rtx (SImode);
637 emit_move_insn (tmp, operands[1]);
638 emit_insn (gen_addsi3 (tmp, tmp, operands[2]));
639 emit_move_insn (operands[0], tmp);
644 (define_insn "addsi3_internal"
645 [(set (match_operand:SI 0 "register_operand" "=d")
646 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
647 (match_operand:SI 2 "arith_operand" "dI")))]
650 || GET_CODE (operands[2]) != CONST_INT
651 || INTVAL (operands[2]) != -32768)"
653 [(set_attr "type" "arith")
654 (set_attr "mode" "SI")])
656 ;; For the mips16, we need to recognize stack pointer additions
657 ;; explicitly, since we don't have a constraint for $sp. These insns
658 ;; will be generated by the save_restore_insns functions.
663 (match_operand:SI 0 "small_int" "I")))]
666 [(set_attr "type" "arith")
667 (set_attr "mode" "SI")
668 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
673 [(set (match_operand:SI 0 "register_operand" "=d")
675 (match_operand:SI 1 "small_int" "I")))]
678 [(set_attr "type" "arith")
679 (set_attr "mode" "SI")
680 (set (attr "length") (if_then_else (match_operand:VOID 1 "m16_uimm8_4" "")
685 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
686 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
687 (match_operand:SI 2 "arith_operand" "IQ,O,d")))]
689 && (GET_CODE (operands[1]) != REG
690 || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
691 || M16_REG_P (REGNO (operands[1]))
692 || REGNO (operands[1]) == ARG_POINTER_REGNUM
693 || REGNO (operands[1]) == FRAME_POINTER_REGNUM
694 || REGNO (operands[1]) == STACK_POINTER_REGNUM)
695 && (GET_CODE (operands[2]) != REG
696 || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER
697 || M16_REG_P (REGNO (operands[2]))
698 || REGNO (operands[2]) == ARG_POINTER_REGNUM
699 || REGNO (operands[2]) == FRAME_POINTER_REGNUM
700 || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
703 if (REGNO (operands[0]) == REGNO (operands[1]))
704 return \"addu\\t%0,%2\";
705 return \"addu\\t%0,%1,%2\";
707 [(set_attr "type" "arith")
708 (set_attr "mode" "SI")
709 (set_attr_alternative "length"
710 [(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
713 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
719 ;; On the mips16, we can sometimes split an add of a constant which is
720 ;; a 4 byte instruction into two adds which are both 2 byte
721 ;; instructions. There are two cases: one where we are adding a
722 ;; constant plus a register to another register, and one where we are
723 ;; simply adding a constant to a register.
726 [(set (match_operand:SI 0 "register_operand" "")
727 (plus:SI (match_dup 0)
728 (match_operand:SI 1 "const_int_operand" "")))]
729 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
730 && GET_CODE (operands[0]) == REG
731 && M16_REG_P (REGNO (operands[0]))
732 && GET_CODE (operands[1]) == CONST_INT
733 && ((INTVAL (operands[1]) > 0x7f
734 && INTVAL (operands[1]) <= 0x7f + 0x7f)
735 || (INTVAL (operands[1]) < - 0x80
736 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
737 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
738 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
741 HOST_WIDE_INT val = INTVAL (operands[1]);
745 operands[1] = GEN_INT (0x7f);
746 operands[2] = GEN_INT (val - 0x7f);
750 operands[1] = GEN_INT (- 0x80);
751 operands[2] = GEN_INT (val + 0x80);
756 [(set (match_operand:SI 0 "register_operand" "")
757 (plus:SI (match_operand:SI 1 "register_operand" "")
758 (match_operand:SI 2 "const_int_operand" "")))]
759 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
760 && GET_CODE (operands[0]) == REG
761 && M16_REG_P (REGNO (operands[0]))
762 && GET_CODE (operands[1]) == REG
763 && M16_REG_P (REGNO (operands[1]))
764 && REGNO (operands[0]) != REGNO (operands[1])
765 && GET_CODE (operands[2]) == CONST_INT
766 && ((INTVAL (operands[2]) > 0x7
767 && INTVAL (operands[2]) <= 0x7 + 0x7f)
768 || (INTVAL (operands[2]) < - 0x8
769 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
770 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
771 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
774 HOST_WIDE_INT val = INTVAL (operands[2]);
778 operands[2] = GEN_INT (0x7);
779 operands[3] = GEN_INT (val - 0x7);
783 operands[2] = GEN_INT (- 0x8);
784 operands[3] = GEN_INT (val + 0x8);
788 (define_expand "adddi3"
789 [(parallel [(set (match_operand:DI 0 "register_operand" "")
790 (plus:DI (match_operand:DI 1 "se_register_operand" "")
791 (match_operand:DI 2 "se_arith_operand" "")))
792 (clobber (match_dup 3))])]
793 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
796 /* The mips16 assembler handles -32768 correctly, and so does gas,
797 but some other MIPS assemblers think that -32768 needs to be
798 loaded into a register before it can be added in. */
801 && GET_CODE (operands[2]) == CONST_INT
802 && INTVAL (operands[2]) == -32768)
803 operands[2] = force_reg (DImode, operands[2]);
805 /* If a large stack adjustment was forced into a register, we may be
806 asked to generate rtx such as:
808 (set (reg:DI sp) (plus:DI (reg:DI sp) (reg:DI pseudo)))
810 but no such instruction is available in mips16. Handle it by
811 using a temporary. */
813 && REGNO (operands[0]) == STACK_POINTER_REGNUM
814 && ((GET_CODE (operands[1]) == REG
815 && REGNO (operands[1]) != STACK_POINTER_REGNUM)
816 || GET_CODE (operands[2]) != CONST_INT))
818 rtx tmp = gen_reg_rtx (DImode);
820 emit_move_insn (tmp, operands[1]);
821 emit_insn (gen_addsi3 (tmp, tmp, operands[2]));
822 emit_move_insn (operands[0], tmp);
828 emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],
833 operands[3] = gen_reg_rtx (SImode);
836 (define_insn "adddi3_internal_1"
837 [(set (match_operand:DI 0 "register_operand" "=d,&d")
838 (plus:DI (match_operand:DI 1 "register_operand" "0,d")
839 (match_operand:DI 2 "register_operand" "d,d")))
840 (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
841 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
844 return (REGNO (operands[0]) == REGNO (operands[1])
845 && REGNO (operands[0]) == REGNO (operands[2]))
846 ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\"
847 : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\";
849 [(set_attr "type" "darith")
850 (set_attr "mode" "DI")
851 (set_attr "length" "16")])
854 [(set (match_operand:DI 0 "register_operand" "")
855 (plus:DI (match_operand:DI 1 "register_operand" "")
856 (match_operand:DI 2 "register_operand" "")))
857 (clobber (match_operand:SI 3 "register_operand" ""))]
858 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
859 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
860 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
861 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
862 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
863 && (REGNO (operands[0]) != REGNO (operands[1])
864 || REGNO (operands[0]) != REGNO (operands[2]))"
866 [(set (subreg:SI (match_dup 0) 0)
867 (plus:SI (subreg:SI (match_dup 1) 0)
868 (subreg:SI (match_dup 2) 0)))
871 (ltu:SI (subreg:SI (match_dup 0) 0)
872 (subreg:SI (match_dup 2) 0)))
874 (set (subreg:SI (match_dup 0) 4)
875 (plus:SI (subreg:SI (match_dup 1) 4)
876 (subreg:SI (match_dup 2) 4)))
878 (set (subreg:SI (match_dup 0) 4)
879 (plus:SI (subreg:SI (match_dup 0) 4)
884 [(set (match_operand:DI 0 "register_operand" "")
885 (plus:DI (match_operand:DI 1 "register_operand" "")
886 (match_operand:DI 2 "register_operand" "")))
887 (clobber (match_operand:SI 3 "register_operand" ""))]
888 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
889 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
890 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
891 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
892 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
893 && (REGNO (operands[0]) != REGNO (operands[1])
894 || REGNO (operands[0]) != REGNO (operands[2]))"
896 [(set (subreg:SI (match_dup 0) 4)
897 (plus:SI (subreg:SI (match_dup 1) 4)
898 (subreg:SI (match_dup 2) 4)))
901 (ltu:SI (subreg:SI (match_dup 0) 4)
902 (subreg:SI (match_dup 2) 4)))
904 (set (subreg:SI (match_dup 0) 0)
905 (plus:SI (subreg:SI (match_dup 1) 0)
906 (subreg:SI (match_dup 2) 0)))
908 (set (subreg:SI (match_dup 0) 0)
909 (plus:SI (subreg:SI (match_dup 0) 0)
913 (define_insn "adddi3_internal_2"
914 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
915 (plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
916 (match_operand:DI 2 "small_int" "P,J,N")))
917 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
918 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
920 || GET_CODE (operands[2]) != CONST_INT
921 || INTVAL (operands[2]) != -32768)"
923 addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
924 move\\t%L0,%L1\;move\\t%M0,%M1
925 subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3"
926 [(set_attr "type" "darith")
927 (set_attr "mode" "DI")
928 (set_attr "length" "12,8,16")])
931 [(set (match_operand:DI 0 "register_operand" "")
932 (plus:DI (match_operand:DI 1 "register_operand" "")
933 (match_operand:DI 2 "small_int" "")))
934 (clobber (match_operand:SI 3 "register_operand" ""))]
935 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
936 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
937 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
938 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
939 && INTVAL (operands[2]) > 0"
941 [(set (subreg:SI (match_dup 0) 0)
942 (plus:SI (subreg:SI (match_dup 1) 0)
946 (ltu:SI (subreg:SI (match_dup 0) 0)
949 (set (subreg:SI (match_dup 0) 4)
950 (plus:SI (subreg:SI (match_dup 1) 4)
955 [(set (match_operand:DI 0 "register_operand" "")
956 (plus:DI (match_operand:DI 1 "register_operand" "")
957 (match_operand:DI 2 "small_int" "")))
958 (clobber (match_operand:SI 3 "register_operand" ""))]
959 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
960 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
961 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
962 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
963 && INTVAL (operands[2]) > 0"
965 [(set (subreg:SI (match_dup 0) 4)
966 (plus:SI (subreg:SI (match_dup 1) 4)
970 (ltu:SI (subreg:SI (match_dup 0) 4)
973 (set (subreg:SI (match_dup 0) 0)
974 (plus:SI (subreg:SI (match_dup 1) 0)
978 (define_insn "adddi3_internal_3"
979 [(set (match_operand:DI 0 "register_operand" "=d")
980 (plus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ")
981 (match_operand:DI 2 "se_arith_operand" "dI")))]
985 || GET_CODE (operands[2]) != CONST_INT
986 || INTVAL (operands[2]) != -32768)"
989 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
990 ? \"dsubu\\t%0,%z1,%n2\"
991 : \"daddu\\t%0,%z1,%2\";
993 [(set_attr "type" "darith")
994 (set_attr "mode" "DI")])
996 ;; For the mips16, we need to recognize stack pointer additions
997 ;; explicitly, since we don't have a constraint for $sp. These insns
998 ;; will be generated by the save_restore_insns functions.
1002 (plus:DI (reg:DI 29)
1003 (match_operand:DI 0 "small_int" "I")))]
1004 "TARGET_MIPS16 && TARGET_64BIT"
1006 [(set_attr "type" "arith")
1007 (set_attr "mode" "DI")
1008 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
1013 [(set (match_operand:DI 0 "register_operand" "=d")
1014 (plus:DI (reg:DI 29)
1015 (match_operand:DI 1 "small_int" "I")))]
1016 "TARGET_MIPS16 && TARGET_64BIT"
1018 [(set_attr "type" "arith")
1019 (set_attr "mode" "DI")
1020 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_uimm5_4" "")
1025 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1026 (plus:DI (match_operand:DI 1 "register_operand" "0,d,d")
1027 (match_operand:DI 2 "arith_operand" "IQ,O,d")))]
1028 "TARGET_MIPS16 && TARGET_64BIT
1029 && (GET_CODE (operands[1]) != REG
1030 || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER
1031 || M16_REG_P (REGNO (operands[1]))
1032 || REGNO (operands[1]) == ARG_POINTER_REGNUM
1033 || REGNO (operands[1]) == FRAME_POINTER_REGNUM
1034 || REGNO (operands[1]) == STACK_POINTER_REGNUM)
1035 && (GET_CODE (operands[2]) != REG
1036 || REGNO (operands[2]) >= FIRST_PSEUDO_REGISTER
1037 || M16_REG_P (REGNO (operands[2]))
1038 || REGNO (operands[2]) == ARG_POINTER_REGNUM
1039 || REGNO (operands[2]) == FRAME_POINTER_REGNUM
1040 || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
1043 if (REGNO (operands[0]) == REGNO (operands[1]))
1044 return \"daddu\\t%0,%2\";
1045 return \"daddu\\t%0,%1,%2\";
1047 [(set_attr "type" "arith")
1048 (set_attr "mode" "DI")
1049 (set_attr_alternative "length"
1050 [(if_then_else (match_operand:VOID 2 "m16_simm5_1" "")
1053 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
1059 ;; On the mips16, we can sometimes split an add of a constant which is
1060 ;; a 4 byte instruction into two adds which are both 2 byte
1061 ;; instructions. There are two cases: one where we are adding a
1062 ;; constant plus a register to another register, and one where we are
1063 ;; simply adding a constant to a register.
1066 [(set (match_operand:DI 0 "register_operand" "")
1067 (plus:DI (match_dup 0)
1068 (match_operand:DI 1 "const_int_operand" "")))]
1069 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1070 && GET_CODE (operands[0]) == REG
1071 && M16_REG_P (REGNO (operands[0]))
1072 && GET_CODE (operands[1]) == CONST_INT
1073 && ((INTVAL (operands[1]) > 0xf
1074 && INTVAL (operands[1]) <= 0xf + 0xf)
1075 || (INTVAL (operands[1]) < - 0x10
1076 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
1077 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
1078 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
1081 HOST_WIDE_INT val = INTVAL (operands[1]);
1085 operands[1] = GEN_INT (0xf);
1086 operands[2] = GEN_INT (val - 0xf);
1090 operands[1] = GEN_INT (- 0x10);
1091 operands[2] = GEN_INT (val + 0x10);
1096 [(set (match_operand:DI 0 "register_operand" "")
1097 (plus:DI (match_operand:DI 1 "register_operand" "")
1098 (match_operand:DI 2 "const_int_operand" "")))]
1099 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1100 && GET_CODE (operands[0]) == REG
1101 && M16_REG_P (REGNO (operands[0]))
1102 && GET_CODE (operands[1]) == REG
1103 && M16_REG_P (REGNO (operands[1]))
1104 && REGNO (operands[0]) != REGNO (operands[1])
1105 && GET_CODE (operands[2]) == CONST_INT
1106 && ((INTVAL (operands[2]) > 0x7
1107 && INTVAL (operands[2]) <= 0x7 + 0xf)
1108 || (INTVAL (operands[2]) < - 0x8
1109 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
1110 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
1111 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
1114 HOST_WIDE_INT val = INTVAL (operands[2]);
1118 operands[2] = GEN_INT (0x7);
1119 operands[3] = GEN_INT (val - 0x7);
1123 operands[2] = GEN_INT (- 0x8);
1124 operands[3] = GEN_INT (val + 0x8);
1128 (define_insn "addsi3_internal_2"
1129 [(set (match_operand:DI 0 "register_operand" "=d")
1130 (sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
1131 (match_operand:SI 2 "arith_operand" "dI"))))]
1135 || GET_CODE (operands[2]) != CONST_INT
1136 || INTVAL (operands[2]) != -32768)"
1139 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1140 ? \"subu\\t%0,%z1,%n2\"
1141 : \"addu\\t%0,%z1,%2\";
1143 [(set_attr "type" "arith")
1144 (set_attr "mode" "SI")])
1147 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1148 (sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1149 (match_operand:SI 2 "arith_operand" "I,O,d"))))]
1150 "TARGET_MIPS16 && TARGET_64BIT"
1153 if (REGNO (operands[0]) == REGNO (operands[1]))
1154 return \"addu\\t%0,%2\";
1155 return \"addu\\t%0,%1,%2\";
1157 [(set_attr "type" "arith")
1158 (set_attr "mode" "SI")
1159 (set_attr_alternative "length"
1160 [(if_then_else (match_operand:VOID 2 "m16_simm8_1" "")
1163 (if_then_else (match_operand:VOID 2 "m16_simm4_1" "")
1170 ;; ....................
1174 ;; ....................
1177 (define_insn "subdf3"
1178 [(set (match_operand:DF 0 "register_operand" "=f")
1179 (minus:DF (match_operand:DF 1 "register_operand" "f")
1180 (match_operand:DF 2 "register_operand" "f")))]
1181 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
1183 [(set_attr "type" "fadd")
1184 (set_attr "mode" "DF")])
1186 (define_insn "subsf3"
1187 [(set (match_operand:SF 0 "register_operand" "=f")
1188 (minus:SF (match_operand:SF 1 "register_operand" "f")
1189 (match_operand:SF 2 "register_operand" "f")))]
1192 [(set_attr "type" "fadd")
1193 (set_attr "mode" "SF")])
1195 (define_expand "subsi3"
1196 [(set (match_operand:SI 0 "register_operand" "=d")
1197 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
1198 (match_operand:SI 2 "arith_operand" "dI")))]
1202 if (GET_CODE (operands[2]) == CONST_INT
1203 && (INTVAL (operands[2]) == -32768
1205 && INTVAL (operands[2]) == -0x4000)))
1206 operands[2] = force_reg (SImode, operands[2]);
1209 (define_insn "subsi3_internal"
1210 [(set (match_operand:SI 0 "register_operand" "=d")
1211 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
1212 (match_operand:SI 2 "arith_operand" "dI")))]
1214 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1216 [(set_attr "type" "arith")
1217 (set_attr "mode" "SI")])
1219 ;; For the mips16, we need to recognize stack pointer subtractions
1220 ;; explicitly, since we don't have a constraint for $sp. These insns
1221 ;; will be generated by the save_restore_insns functions.
1225 (minus:SI (reg:SI 29)
1226 (match_operand:SI 0 "small_int" "I")))]
1228 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1230 [(set_attr "type" "arith")
1231 (set_attr "mode" "SI")
1232 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
1237 [(set (match_operand:SI 0 "register_operand" "=d")
1238 (minus:SI (reg:SI 29)
1239 (match_operand:SI 1 "small_int" "I")))]
1241 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1243 [(set_attr "type" "arith")
1244 (set_attr "mode" "SI")
1245 (set (attr "length") (if_then_else (match_operand:VOID 1 "m16_nuimm8_4" "")
1251 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
1252 (minus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1253 (match_operand:SI 2 "arith_operand" "I,O,d")))]
1255 && (GET_CODE (operands[2]) != CONST_INT
1256 || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
1259 if (REGNO (operands[0]) == REGNO (operands[1]))
1260 return \"subu\\t%0,%2\";
1261 return \"subu\\t%0,%1,%2\";
1263 [(set_attr "type" "arith")
1264 (set_attr "mode" "SI")
1265 (set_attr_alternative "length"
1266 [(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
1269 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
1274 ;; On the mips16, we can sometimes split an subtract of a constant
1275 ;; which is a 4 byte instruction into two adds which are both 2 byte
1276 ;; instructions. There are two cases: one where we are setting a
1277 ;; register to a register minus a constant, and one where we are
1278 ;; simply subtracting a constant from a register.
1281 [(set (match_operand:SI 0 "register_operand" "")
1282 (minus:SI (match_dup 0)
1283 (match_operand:SI 1 "const_int_operand" "")))]
1284 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1285 && GET_CODE (operands[0]) == REG
1286 && M16_REG_P (REGNO (operands[0]))
1287 && GET_CODE (operands[1]) == CONST_INT
1288 && ((INTVAL (operands[1]) > 0x80
1289 && INTVAL (operands[1]) <= 0x80 + 0x80)
1290 || (INTVAL (operands[1]) < - 0x7f
1291 && INTVAL (operands[1]) >= - 0x7f - 0x7f))"
1292 [(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 1)))
1293 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1296 HOST_WIDE_INT val = INTVAL (operands[1]);
1300 operands[1] = GEN_INT (0x80);
1301 operands[2] = GEN_INT (val - 0x80);
1305 operands[1] = GEN_INT (- 0x7f);
1306 operands[2] = GEN_INT (val + 0x7f);
1311 [(set (match_operand:SI 0 "register_operand" "")
1312 (minus:SI (match_operand:SI 1 "register_operand" "")
1313 (match_operand:SI 2 "const_int_operand" "")))]
1314 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
1315 && GET_CODE (operands[0]) == REG
1316 && M16_REG_P (REGNO (operands[0]))
1317 && GET_CODE (operands[1]) == REG
1318 && M16_REG_P (REGNO (operands[1]))
1319 && REGNO (operands[0]) != REGNO (operands[1])
1320 && GET_CODE (operands[2]) == CONST_INT
1321 && ((INTVAL (operands[2]) > 0x8
1322 && INTVAL (operands[2]) <= 0x8 + 0x80)
1323 || (INTVAL (operands[2]) < - 0x7
1324 && INTVAL (operands[2]) >= - 0x7 - 0x7f))"
1325 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1326 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 3)))]
1329 HOST_WIDE_INT val = INTVAL (operands[2]);
1333 operands[2] = GEN_INT (0x8);
1334 operands[3] = GEN_INT (val - 0x8);
1338 operands[2] = GEN_INT (- 0x7);
1339 operands[3] = GEN_INT (val + 0x7);
1343 (define_expand "subdi3"
1344 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
1345 (minus:DI (match_operand:DI 1 "se_register_operand" "d")
1346 (match_operand:DI 2 "se_register_operand" "d")))
1347 (clobber (match_dup 3))])]
1348 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
1353 emit_insn (gen_subdi3_internal_3 (operands[0], operands[1],
1358 operands[3] = gen_reg_rtx (SImode);
1361 (define_insn "subdi3_internal"
1362 [(set (match_operand:DI 0 "register_operand" "=d")
1363 (minus:DI (match_operand:DI 1 "register_operand" "d")
1364 (match_operand:DI 2 "register_operand" "d")))
1365 (clobber (match_operand:SI 3 "register_operand" "=d"))]
1366 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
1367 "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
1368 [(set_attr "type" "darith")
1369 (set_attr "mode" "DI")
1370 (set_attr "length" "16")])
1373 [(set (match_operand:DI 0 "register_operand" "")
1374 (minus:DI (match_operand:DI 1 "register_operand" "")
1375 (match_operand:DI 2 "register_operand" "")))
1376 (clobber (match_operand:SI 3 "register_operand" ""))]
1377 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
1378 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1379 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1380 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1381 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1384 (ltu:SI (subreg:SI (match_dup 1) 0)
1385 (subreg:SI (match_dup 2) 0)))
1387 (set (subreg:SI (match_dup 0) 0)
1388 (minus:SI (subreg:SI (match_dup 1) 0)
1389 (subreg:SI (match_dup 2) 0)))
1391 (set (subreg:SI (match_dup 0) 4)
1392 (minus:SI (subreg:SI (match_dup 1) 4)
1393 (subreg:SI (match_dup 2) 4)))
1395 (set (subreg:SI (match_dup 0) 4)
1396 (minus:SI (subreg:SI (match_dup 0) 4)
1401 [(set (match_operand:DI 0 "register_operand" "")
1402 (minus:DI (match_operand:DI 1 "register_operand" "")
1403 (match_operand:DI 2 "register_operand" "")))
1404 (clobber (match_operand:SI 3 "register_operand" ""))]
1405 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
1406 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1407 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1408 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1409 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1412 (ltu:SI (subreg:SI (match_dup 1) 4)
1413 (subreg:SI (match_dup 2) 4)))
1415 (set (subreg:SI (match_dup 0) 4)
1416 (minus:SI (subreg:SI (match_dup 1) 4)
1417 (subreg:SI (match_dup 2) 4)))
1419 (set (subreg:SI (match_dup 0) 0)
1420 (minus:SI (subreg:SI (match_dup 1) 0)
1421 (subreg:SI (match_dup 2) 0)))
1423 (set (subreg:SI (match_dup 0) 0)
1424 (minus:SI (subreg:SI (match_dup 0) 0)
1428 (define_insn "subdi3_internal_2"
1429 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1430 (minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
1431 (match_operand:DI 2 "small_int" "P,J,N")))
1432 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
1433 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1434 && INTVAL (operands[2]) != -32768"
1436 sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3
1437 move\\t%L0,%L1\;move\\t%M0,%M1
1438 sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3"
1439 [(set_attr "type" "darith")
1440 (set_attr "mode" "DI")
1441 (set_attr "length" "12,8,16")])
1444 [(set (match_operand:DI 0 "register_operand" "")
1445 (minus:DI (match_operand:DI 1 "register_operand" "")
1446 (match_operand:DI 2 "small_int" "")))
1447 (clobber (match_operand:SI 3 "register_operand" ""))]
1448 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
1449 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1450 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1451 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1452 && INTVAL (operands[2]) > 0"
1455 (ltu:SI (subreg:SI (match_dup 1) 0)
1458 (set (subreg:SI (match_dup 0) 0)
1459 (minus:SI (subreg:SI (match_dup 1) 0)
1462 (set (subreg:SI (match_dup 0) 4)
1463 (minus:SI (subreg:SI (match_dup 1) 4)
1468 [(set (match_operand:DI 0 "register_operand" "")
1469 (minus:DI (match_operand:DI 1 "register_operand" "")
1470 (match_operand:DI 2 "small_int" "")))
1471 (clobber (match_operand:SI 3 "register_operand" ""))]
1472 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
1473 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
1474 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1475 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1476 && INTVAL (operands[2]) > 0"
1479 (ltu:SI (subreg:SI (match_dup 1) 4)
1482 (set (subreg:SI (match_dup 0) 4)
1483 (minus:SI (subreg:SI (match_dup 1) 4)
1486 (set (subreg:SI (match_dup 0) 0)
1487 (minus:SI (subreg:SI (match_dup 1) 0)
1491 (define_insn "subdi3_internal_3"
1492 [(set (match_operand:DI 0 "register_operand" "=d")
1493 (minus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ")
1494 (match_operand:DI 2 "se_arith_operand" "dI")))]
1495 "TARGET_64BIT && !TARGET_MIPS16
1496 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1499 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1500 ? \"daddu\\t%0,%z1,%n2\"
1501 : \"dsubu\\t%0,%z1,%2\";
1503 [(set_attr "type" "darith")
1504 (set_attr "mode" "DI")])
1506 ;; For the mips16, we need to recognize stack pointer subtractions
1507 ;; explicitly, since we don't have a constraint for $sp. These insns
1508 ;; will be generated by the save_restore_insns functions.
1512 (minus:DI (reg:DI 29)
1513 (match_operand:DI 0 "small_int" "I")))]
1515 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1517 [(set_attr "type" "arith")
1518 (set_attr "mode" "DI")
1519 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
1524 [(set (match_operand:DI 0 "register_operand" "=d")
1525 (minus:DI (reg:DI 29)
1526 (match_operand:DI 1 "small_int" "I")))]
1528 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1530 [(set_attr "type" "arith")
1531 (set_attr "mode" "DI")
1532 (set (attr "length") (if_then_else (match_operand:VOID 0 "m16_nuimm5_4" "")
1537 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1538 (minus:DI (match_operand:DI 1 "register_operand" "0,d,d")
1539 (match_operand:DI 2 "arith_operand" "I,O,d")))]
1541 && (GET_CODE (operands[2]) != CONST_INT
1542 || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
1545 if (REGNO (operands[0]) == REGNO (operands[1]))
1546 return \"dsubu\\t%0,%2\";
1547 return \"dsubu\\t%0,%1,%2\";
1549 [(set_attr "type" "arith")
1550 (set_attr "mode" "DI")
1551 (set_attr_alternative "length"
1552 [(if_then_else (match_operand:VOID 2 "m16_nsimm5_1" "")
1555 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
1560 ;; On the mips16, we can sometimes split an add of a constant which is
1561 ;; a 4 byte instruction into two adds which are both 2 byte
1562 ;; instructions. There are two cases: one where we are adding a
1563 ;; constant plus a register to another register, and one where we are
1564 ;; simply adding a constant to a register.
1567 [(set (match_operand:DI 0 "register_operand" "")
1568 (minus:DI (match_dup 0)
1569 (match_operand:DI 1 "const_int_operand" "")))]
1570 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1571 && GET_CODE (operands[0]) == REG
1572 && M16_REG_P (REGNO (operands[0]))
1573 && GET_CODE (operands[1]) == CONST_INT
1574 && ((INTVAL (operands[1]) > 0x10
1575 && INTVAL (operands[1]) <= 0x10 + 0x10)
1576 || (INTVAL (operands[1]) < - 0xf
1577 && INTVAL (operands[1]) >= - 0xf - 0xf))"
1578 [(set (match_dup 0) (minus:DI (match_dup 0) (match_dup 1)))
1579 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
1582 HOST_WIDE_INT val = INTVAL (operands[1]);
1586 operands[1] = GEN_INT (0xf);
1587 operands[2] = GEN_INT (val - 0xf);
1591 operands[1] = GEN_INT (- 0x10);
1592 operands[2] = GEN_INT (val + 0x10);
1597 [(set (match_operand:DI 0 "register_operand" "")
1598 (minus:DI (match_operand:DI 1 "register_operand" "")
1599 (match_operand:DI 2 "const_int_operand" "")))]
1600 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
1601 && GET_CODE (operands[0]) == REG
1602 && M16_REG_P (REGNO (operands[0]))
1603 && GET_CODE (operands[1]) == REG
1604 && M16_REG_P (REGNO (operands[1]))
1605 && REGNO (operands[0]) != REGNO (operands[1])
1606 && GET_CODE (operands[2]) == CONST_INT
1607 && ((INTVAL (operands[2]) > 0x8
1608 && INTVAL (operands[2]) <= 0x8 + 0x10)
1609 || (INTVAL (operands[2]) < - 0x7
1610 && INTVAL (operands[2]) >= - 0x7 - 0xf))"
1611 [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
1612 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))]
1615 HOST_WIDE_INT val = INTVAL (operands[2]);
1619 operands[2] = GEN_INT (0x8);
1620 operands[3] = GEN_INT (val - 0x8);
1624 operands[2] = GEN_INT (- 0x7);
1625 operands[3] = GEN_INT (val + 0x7);
1629 (define_insn "subsi3_internal_2"
1630 [(set (match_operand:DI 0 "register_operand" "=d")
1631 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
1632 (match_operand:SI 2 "arith_operand" "dI"))))]
1633 "TARGET_64BIT && !TARGET_MIPS16
1634 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
1637 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
1638 ? \"addu\\t%0,%z1,%n2\"
1639 : \"subu\\t%0,%z1,%2\";
1641 [(set_attr "type" "arith")
1642 (set_attr "mode" "DI")])
1645 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
1646 (sign_extend:DI (minus:SI (match_operand:SI 1 "register_operand" "0,d,d")
1647 (match_operand:SI 2 "arith_operand" "I,O,d"))))]
1648 "TARGET_64BIT && TARGET_MIPS16
1649 && (GET_CODE (operands[2]) != CONST_INT
1650 || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
1653 if (REGNO (operands[0]) == REGNO (operands[1]))
1654 return \"subu\\t%0,%2\";
1655 return \"subu\\t%0,%1,%2\";
1657 [(set_attr "type" "arith")
1658 (set_attr "mode" "SI")
1659 (set_attr_alternative "length"
1660 [(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
1663 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
1671 ;; ....................
1675 ;; ....................
1678 ;; Early Vr4300 silicon has a CPU bug where multiplies with certain
1679 ;; operands may corrupt immediately following multiplies. This is a
1680 ;; simple fix to insert NOPs.
1682 (define_expand "muldf3"
1683 [(set (match_operand:DF 0 "register_operand" "=f")
1684 (mult:DF (match_operand:DF 1 "register_operand" "f")
1685 (match_operand:DF 2 "register_operand" "f")))]
1686 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
1689 if (!TARGET_MIPS4300)
1690 emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
1692 emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
1696 (define_insn "muldf3_internal"
1697 [(set (match_operand:DF 0 "register_operand" "=f")
1698 (mult:DF (match_operand:DF 1 "register_operand" "f")
1699 (match_operand:DF 2 "register_operand" "f")))]
1700 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_MIPS4300"
1702 [(set_attr "type" "fmul")
1703 (set_attr "mode" "DF")])
1705 (define_insn "muldf3_r4300"
1706 [(set (match_operand:DF 0 "register_operand" "=f")
1707 (mult:DF (match_operand:DF 1 "register_operand" "f")
1708 (match_operand:DF 2 "register_operand" "f")))]
1709 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_MIPS4300"
1712 output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
1713 if (TARGET_4300_MUL_FIX)
1714 output_asm_insn (\"nop\", operands);
1717 [(set_attr "type" "fmul")
1718 (set_attr "mode" "DF")
1719 (set_attr "length" "8")]) ;; mul.d + nop
1721 (define_expand "mulsf3"
1722 [(set (match_operand:SF 0 "register_operand" "=f")
1723 (mult:SF (match_operand:SF 1 "register_operand" "f")
1724 (match_operand:SF 2 "register_operand" "f")))]
1728 if (!TARGET_MIPS4300)
1729 emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
1731 emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
1735 (define_insn "mulsf3_internal"
1736 [(set (match_operand:SF 0 "register_operand" "=f")
1737 (mult:SF (match_operand:SF 1 "register_operand" "f")
1738 (match_operand:SF 2 "register_operand" "f")))]
1739 "TARGET_HARD_FLOAT && !TARGET_MIPS4300"
1741 [(set_attr "type" "fmul")
1742 (set_attr "mode" "SF")])
1744 (define_insn "mulsf3_r4300"
1745 [(set (match_operand:SF 0 "register_operand" "=f")
1746 (mult:SF (match_operand:SF 1 "register_operand" "f")
1747 (match_operand:SF 2 "register_operand" "f")))]
1748 "TARGET_HARD_FLOAT && TARGET_MIPS4300"
1751 output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
1752 if (TARGET_4300_MUL_FIX)
1753 output_asm_insn (\"nop\", operands);
1756 [(set_attr "type" "fmul")
1757 (set_attr "mode" "SF")
1758 (set_attr "length" "8")]) ;; mul.s + nop
1761 ;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while
1762 ;; a multiply is in progress, it may give an incorrect result. Avoid
1763 ;; this by keeping the mflo with the mult on the R4000.
1765 (define_expand "mulsi3"
1766 [(set (match_operand:SI 0 "register_operand" "=l")
1767 (mult:SI (match_operand:SI 1 "register_operand" "d")
1768 (match_operand:SI 2 "register_operand" "d")))
1769 (clobber (match_scratch:SI 3 "=h"))
1770 (clobber (match_scratch:SI 4 "=a"))]
1774 if (GENERATE_MULT3_SI || TARGET_MAD)
1775 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1776 else if (!TARGET_MIPS4000 || TARGET_MIPS16)
1777 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1779 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1783 (define_insn "mulsi3_mult3"
1784 [(set (match_operand:SI 0 "register_operand" "=d,l")
1785 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1786 (match_operand:SI 2 "register_operand" "d,d")))
1787 (clobber (match_scratch:SI 3 "=h,h"))
1788 (clobber (match_scratch:SI 4 "=l,X"))
1789 (clobber (match_scratch:SI 5 "=a,a"))]
1794 if (which_alternative == 1)
1795 return \"mult\\t%1,%2\";
1799 return \"mul\\t%0,%1,%2\";
1800 return \"mult\\t%0,%1,%2\";
1802 [(set_attr "type" "imul")
1803 (set_attr "mode" "SI")])
1805 (define_insn "mulsi3_internal"
1806 [(set (match_operand:SI 0 "register_operand" "=l")
1807 (mult:SI (match_operand:SI 1 "register_operand" "d")
1808 (match_operand:SI 2 "register_operand" "d")))
1809 (clobber (match_scratch:SI 3 "=h"))
1810 (clobber (match_scratch:SI 4 "=a"))]
1811 "!TARGET_MIPS4000 || TARGET_MIPS16"
1813 [(set_attr "type" "imul")
1814 (set_attr "mode" "SI")])
1816 (define_insn "mulsi3_r4000"
1817 [(set (match_operand:SI 0 "register_operand" "=d")
1818 (mult:SI (match_operand:SI 1 "register_operand" "d")
1819 (match_operand:SI 2 "register_operand" "d")))
1820 (clobber (match_scratch:SI 3 "=h"))
1821 (clobber (match_scratch:SI 4 "=l"))
1822 (clobber (match_scratch:SI 5 "=a"))]
1823 "TARGET_MIPS4000 && !TARGET_MIPS16"
1828 xoperands[0] = operands[0];
1829 xoperands[1] = gen_rtx_REG (SImode, LO_REGNUM);
1831 output_asm_insn (\"mult\\t%1,%2\", operands);
1832 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
1835 [(set_attr "type" "imul")
1836 (set_attr "mode" "SI")
1837 (set_attr "length" "12")]) ;; mult + mflo + delay
1839 ;; Multiply-accumulate patterns
1841 ;; For processors that can copy the output to a general register:
1843 ;; The all-d alternative is needed because the combiner will find this
1844 ;; pattern and then register alloc/reload will move registers around to
1845 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1847 ;; The last alternative should be made slightly less desirable, but adding
1848 ;; "?" to the constraint is too strong, and causes values to be loaded into
1849 ;; LO even when that's more costly. For now, using "*d" mostly does the
1851 (define_insn "*mul_acc_si"
1852 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1853 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1854 (match_operand:SI 2 "register_operand" "d,d,d"))
1855 (match_operand:SI 3 "register_operand" "0,l,*d")))
1856 (clobber (match_scratch:SI 4 "=h,h,h"))
1857 (clobber (match_scratch:SI 5 "=X,3,l"))
1858 (clobber (match_scratch:SI 6 "=a,a,a"))
1859 (clobber (match_scratch:SI 7 "=X,X,d"))]
1861 || ISA_HAS_MADD_MSUB)
1865 static const char *const madd[] = { \"madd\\t%1,%2\", \"madd\\t%0,%1,%2\" };
1866 if (which_alternative == 2)
1868 if (ISA_HAS_MADD_MSUB && which_alternative != 0)
1870 return madd[which_alternative];
1872 [(set_attr "type" "imadd,imadd,multi")
1873 (set_attr "mode" "SI")
1874 (set_attr "length" "4,4,8")])
1876 ;; Split the above insn if we failed to get LO allocated.
1878 [(set (match_operand:SI 0 "register_operand" "")
1879 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
1880 (match_operand:SI 2 "register_operand" ""))
1881 (match_operand:SI 3 "register_operand" "")))
1882 (clobber (match_scratch:SI 4 ""))
1883 (clobber (match_scratch:SI 5 ""))
1884 (clobber (match_scratch:SI 6 ""))
1885 (clobber (match_scratch:SI 7 ""))]
1886 "reload_completed && !TARGET_DEBUG_D_MODE
1887 && GP_REG_P (true_regnum (operands[0]))
1888 && GP_REG_P (true_regnum (operands[3]))"
1889 [(parallel [(set (match_dup 7)
1890 (mult:SI (match_dup 1) (match_dup 2)))
1891 (clobber (match_dup 4))
1892 (clobber (match_dup 5))
1893 (clobber (match_dup 6))])
1894 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 3)))]
1897 ;; Splitter to copy result of MADD to a general register
1899 [(set (match_operand:SI 0 "register_operand" "")
1900 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
1901 (match_operand:SI 2 "register_operand" ""))
1902 (match_operand:SI 3 "register_operand" "")))
1903 (clobber (match_scratch:SI 4 ""))
1904 (clobber (match_scratch:SI 5 ""))
1905 (clobber (match_scratch:SI 6 ""))
1906 (clobber (match_scratch:SI 7 ""))]
1907 "reload_completed && !TARGET_DEBUG_D_MODE
1908 && GP_REG_P (true_regnum (operands[0]))
1909 && true_regnum (operands[3]) == LO_REGNUM"
1910 [(parallel [(set (match_dup 3)
1911 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1913 (clobber (match_dup 4))
1914 (clobber (match_dup 5))
1915 (clobber (match_dup 6))
1916 (clobber (match_dup 7))])
1917 (set (match_dup 0) (match_dup 3))]
1920 (define_insn "*mul_sub_si"
1921 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1922 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1923 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1924 (match_operand:SI 3 "register_operand" "d,d,d"))))
1925 (clobber (match_scratch:SI 4 "=h,h,h"))
1926 (clobber (match_scratch:SI 5 "=X,3,l"))
1927 (clobber (match_scratch:SI 6 "=a,a,a"))
1928 (clobber (match_scratch:SI 7 "=X,X,d"))]
1932 if (which_alternative != 0)
1934 return \"msub\\t%2,%3\";
1936 [(set_attr "type" "imadd,multi,multi")
1937 (set_attr "mode" "SI")
1938 (set_attr "length" "4,8,8")])
1940 ;; Split the above insn if we failed to get LO allocated.
1942 [(set (match_operand:SI 0 "register_operand" "")
1943 (minus:SI (match_operand:SI 1 "register_operand" "")
1944 (mult:SI (match_operand:SI 2 "register_operand" "")
1945 (match_operand:SI 3 "register_operand" ""))))
1946 (clobber (match_scratch:SI 4 ""))
1947 (clobber (match_scratch:SI 5 ""))
1948 (clobber (match_scratch:SI 6 ""))
1949 (clobber (match_scratch:SI 7 ""))]
1950 "reload_completed && !TARGET_DEBUG_D_MODE
1951 && GP_REG_P (true_regnum (operands[0]))
1952 && GP_REG_P (true_regnum (operands[1]))"
1953 [(parallel [(set (match_dup 7)
1954 (mult:SI (match_dup 2) (match_dup 3)))
1955 (clobber (match_dup 4))
1956 (clobber (match_dup 5))
1957 (clobber (match_dup 6))])
1958 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 7)))]
1961 ;; Splitter to copy result of MSUB to a general register
1963 [(set (match_operand:SI 0 "register_operand" "")
1964 (minus:SI (match_operand:SI 1 "register_operand" "")
1965 (mult:SI (match_operand:SI 2 "register_operand" "")
1966 (match_operand:SI 3 "register_operand" ""))))
1967 (clobber (match_scratch:SI 4 ""))
1968 (clobber (match_scratch:SI 5 ""))
1969 (clobber (match_scratch:SI 6 ""))
1970 (clobber (match_scratch:SI 7 ""))]
1971 "reload_completed && !TARGET_DEBUG_D_MODE
1972 && GP_REG_P (true_regnum (operands[0]))
1973 && true_regnum (operands[1]) == LO_REGNUM"
1974 [(parallel [(set (match_dup 1)
1975 (minus:SI (match_dup 1)
1976 (mult:SI (match_dup 2) (match_dup 3))))
1977 (clobber (match_dup 4))
1978 (clobber (match_dup 5))
1979 (clobber (match_dup 6))
1980 (clobber (match_dup 7))])
1981 (set (match_dup 0) (match_dup 1))]
1986 [(set (match_operand:SI 0 "register_operand" "")
1987 (minus:SI (match_operand:SI 1 "register_operand" "")
1988 (mult:SI (match_operand:SI 2 "register_operand" "")
1989 (match_operand:SI 3 "register_operand" ""))))
1990 (clobber (match_scratch:SI 4 ""))
1991 (clobber (match_scratch:SI 5 ""))
1992 (clobber (match_scratch:SI 6 ""))
1993 (clobber (match_scratch:SI 7 ""))]
1994 "reload_completed && !TARGET_DEBUG_D_MODE
1995 && GP_REG_P (true_regnum (operands[0]))
1996 && GP_REG_P (true_regnum (operands[1]))"
1997 [(parallel [(set (match_dup 7)
1998 (mult:SI (match_dup 2) (match_dup 3)))
1999 (clobber (match_dup 4))
2000 (clobber (match_dup 5))
2001 (clobber (match_dup 6))])
2002 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 7)))]
2005 (define_expand "muldi3"
2006 [(set (match_operand:DI 0 "register_operand" "=l")
2007 (mult:DI (match_operand:DI 1 "se_register_operand" "d")
2008 (match_operand:DI 2 "register_operand" "d")))
2009 (clobber (match_scratch:DI 3 "=h"))
2010 (clobber (match_scratch:DI 4 "=a"))]
2015 if (GENERATE_MULT3_DI || TARGET_MIPS4000 || TARGET_MIPS16)
2016 emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
2018 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
2022 ;; Don't accept both operands using se_register_operand, because if
2023 ;; both operands are sign extended we would prefer to use mult in the
2024 ;; mulsidi3 pattern. Commutativity should permit either operand to be
2027 (define_insn "muldi3_internal"
2028 [(set (match_operand:DI 0 "register_operand" "=l")
2029 (mult:DI (match_operand:DI 1 "se_register_operand" "d")
2030 (match_operand:DI 2 "register_operand" "d")))
2031 (clobber (match_scratch:DI 3 "=h"))
2032 (clobber (match_scratch:DI 4 "=a"))]
2033 "TARGET_64BIT && !TARGET_MIPS4000 && !TARGET_MIPS16"
2035 [(set_attr "type" "imul")
2036 (set_attr "mode" "DI")])
2038 (define_insn "muldi3_internal2"
2039 [(set (match_operand:DI 0 "register_operand" "=d")
2040 (mult:DI (match_operand:DI 1 "se_register_operand" "d")
2041 (match_operand:DI 2 "register_operand" "d")))
2042 (clobber (match_scratch:DI 3 "=h"))
2043 (clobber (match_scratch:DI 4 "=l"))
2044 (clobber (match_scratch:DI 5 "=a"))]
2045 "TARGET_64BIT && (GENERATE_MULT3_DI || TARGET_MIPS4000 || TARGET_MIPS16)"
2048 if (GENERATE_MULT3_DI)
2049 output_asm_insn (\"dmult\\t%0,%1,%2\", operands);
2054 xoperands[0] = operands[0];
2055 xoperands[1] = gen_rtx_REG (DImode, LO_REGNUM);
2057 output_asm_insn (\"dmult\\t%1,%2\", operands);
2058 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
2062 [(set_attr "type" "imul")
2063 (set_attr "mode" "DI")
2064 (set (attr "length")
2065 (if_then_else (ne (symbol_ref "GENERATE_MULT3_DI") (const_int 0))
2067 (const_int 12)))]) ;; mult + mflo + delay
2069 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
2071 (define_expand "mulsidi3"
2072 [(set (match_operand:DI 0 "register_operand" "=x")
2073 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2074 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
2078 rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
2080 emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
2083 emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2],
2088 (define_expand "umulsidi3"
2089 [(set (match_operand:DI 0 "register_operand" "=x")
2090 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
2091 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
2095 rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
2097 emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2],
2100 emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2],
2105 (define_insn "mulsidi3_internal"
2106 [(set (match_operand:DI 0 "register_operand" "=x")
2107 (mult:DI (match_operator:DI 3 "extend_operator"
2108 [(match_operand:SI 1 "register_operand" "d")])
2109 (match_operator:DI 4 "extend_operator"
2110 [(match_operand:SI 2 "register_operand" "d")])))
2111 (clobber (match_scratch:SI 5 "=a"))]
2112 "!TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])"
2115 if (GET_CODE (operands[3]) == SIGN_EXTEND)
2116 return \"mult\\t%1,%2\";
2117 return \"multu\\t%1,%2\";
2119 [(set_attr "type" "imul")
2120 (set_attr "mode" "SI")])
2122 (define_insn "mulsidi3_64bit"
2123 [(set (match_operand:DI 0 "register_operand" "=a")
2124 (mult:DI (match_operator:DI 3 "extend_operator"
2125 [(match_operand:SI 1 "register_operand" "d")])
2126 (match_operator:DI 4 "extend_operator"
2127 [(match_operand:SI 2 "register_operand" "d")])))
2128 (clobber (match_scratch:DI 5 "=l"))
2129 (clobber (match_scratch:DI 6 "=h"))]
2130 "TARGET_64BIT && GET_CODE (operands[3]) == GET_CODE (operands[4])"
2133 if (GET_CODE (operands[3]) == SIGN_EXTEND)
2134 return \"mult\\t%1,%2\";
2135 return \"multu\\t%1,%2\";
2137 [(set_attr "type" "imul")
2138 (set_attr "mode" "SI")])
2140 ;; _highpart patterns
2141 (define_expand "smulsi3_highpart"
2142 [(set (match_operand:SI 0 "register_operand" "=h")
2144 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
2145 (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
2150 rtx dummy = gen_rtx (SIGN_EXTEND, DImode, const0_rtx);
2151 rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
2152 #ifndef NO_MD_PROTOTYPES
2153 rtx (*genfn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
2157 genfn = gen_xmulsi3_highpart_internal;
2158 emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
2163 (define_expand "umulsi3_highpart"
2164 [(set (match_operand:SI 0 "register_operand" "=h")
2166 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
2167 (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
2172 rtx dummy = gen_rtx (ZERO_EXTEND, DImode, const0_rtx);
2173 rtx dummy2 = gen_rtx_LSHIFTRT (DImode, const0_rtx, const0_rtx);
2174 #ifndef NO_MD_PROTOTYPES
2175 rtx (*genfn) PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
2179 genfn = gen_xmulsi3_highpart_internal;
2180 emit_insn ((*genfn) (operands[0], operands[1], operands[2], dummy,
2185 (define_insn "xmulsi3_highpart_internal"
2186 [(set (match_operand:SI 0 "register_operand" "=h")
2188 (match_operator:DI 5 "highpart_shift_operator"
2189 [(mult:DI (match_operator:DI 3 "extend_operator"
2190 [(match_operand:SI 1 "register_operand" "d")])
2191 (match_operator:DI 4 "extend_operator"
2192 [(match_operand:SI 2 "register_operand" "d")]))
2194 (clobber (match_scratch:SI 6 "=l"))
2195 (clobber (match_scratch:SI 7 "=a"))]
2196 "GET_CODE (operands[3]) == GET_CODE (operands[4])"
2199 if (GET_CODE (operands[3]) == SIGN_EXTEND)
2200 return \"mult\\t%1,%2\";
2202 return \"multu\\t%1,%2\";
2204 [(set_attr "type" "imul")
2205 (set_attr "mode" "SI")])
2207 (define_insn "smuldi3_highpart"
2208 [(set (match_operand:DI 0 "register_operand" "=h")
2210 (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "se_register_operand" "d"))
2211 (sign_extend:TI (match_operand:DI 2 "se_register_operand" "d")))
2213 (clobber (match_scratch:DI 3 "=l"))
2214 (clobber (match_scratch:DI 4 "=a"))]
2217 [(set_attr "type" "imul")
2218 (set_attr "mode" "DI")])
2220 (define_insn "umuldi3_highpart"
2221 [(set (match_operand:DI 0 "register_operand" "=h")
2223 (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "se_register_operand" "d"))
2224 (zero_extend:TI (match_operand:DI 2 "se_register_operand" "d")))
2226 (clobber (match_scratch:DI 3 "=l"))
2227 (clobber (match_scratch:DI 4 "=a"))]
2230 [(set_attr "type" "imul")
2231 (set_attr "mode" "DI")])
2233 ;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
2234 ;; instruction. The HI/LO registers are used as a 64 bit accumulator.
2236 (define_insn "madsi"
2237 [(set (match_operand:SI 0 "register_operand" "+l")
2238 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
2239 (match_operand:SI 2 "register_operand" "d"))
2241 (clobber (match_scratch:SI 3 "=h"))
2242 (clobber (match_scratch:SI 4 "=a"))]
2245 [(set_attr "type" "imadd")
2246 (set_attr "mode" "SI")])
2248 (define_insn "*mul_acc_di"
2249 [(set (match_operand:DI 0 "register_operand" "+x")
2250 (plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
2251 [(match_operand:SI 1 "register_operand" "d")])
2252 (match_operator:DI 4 "extend_operator"
2253 [(match_operand:SI 2 "register_operand" "d")]))
2255 (clobber (match_scratch:SI 5 "=a"))]
2258 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
2261 if (GET_CODE (operands[3]) == SIGN_EXTEND)
2262 return \"mad\\t%1,%2\";
2264 return \"madu\\t%1,%2\";
2266 [(set_attr "type" "imadd")
2267 (set_attr "mode" "SI")])
2269 (define_insn "*mul_acc_64bit_di"
2270 [(set (match_operand:DI 0 "register_operand" "+a")
2271 (plus:DI (mult:DI (match_operator:DI 3 "extend_operator"
2272 [(match_operand:SI 1 "register_operand" "d")])
2273 (match_operator:DI 4 "extend_operator"
2274 [(match_operand:SI 2 "register_operand" "d")]))
2276 (clobber (match_scratch:SI 5 "=h"))
2277 (clobber (match_scratch:SI 6 "=l"))]
2280 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
2283 if (GET_CODE (operands[3]) == SIGN_EXTEND)
2284 return \"mad\\t%1,%2\";
2286 return \"madu\\t%1,%2\";
2288 [(set_attr "type" "imadd")
2289 (set_attr "mode" "SI")])
2291 ;; Floating point multiply accumulate instructions.
2294 [(set (match_operand:DF 0 "register_operand" "=f")
2295 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
2296 (match_operand:DF 2 "register_operand" "f"))
2297 (match_operand:DF 3 "register_operand" "f")))]
2298 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
2299 "madd.d\\t%0,%3,%1,%2"
2300 [(set_attr "type" "fmadd")
2301 (set_attr "mode" "DF")])
2304 [(set (match_operand:SF 0 "register_operand" "=f")
2305 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
2306 (match_operand:SF 2 "register_operand" "f"))
2307 (match_operand:SF 3 "register_operand" "f")))]
2308 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
2309 "madd.s\\t%0,%3,%1,%2"
2310 [(set_attr "type" "fmadd")
2311 (set_attr "mode" "SF")])
2314 [(set (match_operand:DF 0 "register_operand" "=f")
2315 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
2316 (match_operand:DF 2 "register_operand" "f"))
2317 (match_operand:DF 3 "register_operand" "f")))]
2318 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
2319 "msub.d\\t%0,%3,%1,%2"
2320 [(set_attr "type" "fmadd")
2321 (set_attr "mode" "DF")])
2324 [(set (match_operand:SF 0 "register_operand" "=f")
2325 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
2326 (match_operand:SF 2 "register_operand" "f"))
2327 (match_operand:SF 3 "register_operand" "f")))]
2329 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
2330 "msub.s\\t%0,%3,%1,%2"
2331 [(set_attr "type" "fmadd")
2332 (set_attr "mode" "SF")])
2335 [(set (match_operand:DF 0 "register_operand" "=f")
2336 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
2337 (match_operand:DF 2 "register_operand" "f"))
2338 (match_operand:DF 3 "register_operand" "f"))))]
2339 "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
2340 "nmadd.d\\t%0,%3,%1,%2"
2341 [(set_attr "type" "fmadd")
2342 (set_attr "mode" "DF")])
2345 [(set (match_operand:SF 0 "register_operand" "=f")
2346 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
2347 (match_operand:SF 2 "register_operand" "f"))
2348 (match_operand:SF 3 "register_operand" "f"))))]
2349 "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
2350 "nmadd.s\\t%0,%3,%1,%2"
2351 [(set_attr "type" "fmadd")
2352 (set_attr "mode" "SF")])
2355 [(set (match_operand:DF 0 "register_operand" "=f")
2356 (minus:DF (match_operand:DF 1 "register_operand" "f")
2357 (mult:DF (match_operand:DF 2 "register_operand" "f")
2358 (match_operand:DF 3 "register_operand" "f"))))]
2359 "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
2360 "nmsub.d\\t%0,%1,%2,%3"
2361 [(set_attr "type" "fmadd")
2362 (set_attr "mode" "DF")])
2365 [(set (match_operand:SF 0 "register_operand" "=f")
2366 (minus:SF (match_operand:SF 1 "register_operand" "f")
2367 (mult:SF (match_operand:SF 2 "register_operand" "f")
2368 (match_operand:SF 3 "register_operand" "f"))))]
2369 "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
2370 "nmsub.s\\t%0,%1,%2,%3"
2371 [(set_attr "type" "fmadd")
2372 (set_attr "mode" "SF")])
2375 ;; ....................
2377 ;; DIVISION and REMAINDER
2379 ;; ....................
2382 (define_insn "divdf3"
2383 [(set (match_operand:DF 0 "register_operand" "=f")
2384 (div:DF (match_operand:DF 1 "register_operand" "f")
2385 (match_operand:DF 2 "register_operand" "f")))]
2386 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2388 [(set_attr "type" "fdiv")
2389 (set_attr "mode" "DF")])
2391 (define_insn "divsf3"
2392 [(set (match_operand:SF 0 "register_operand" "=f")
2393 (div:SF (match_operand:SF 1 "register_operand" "f")
2394 (match_operand:SF 2 "register_operand" "f")))]
2397 [(set_attr "type" "fdiv")
2398 (set_attr "mode" "SF")])
2401 [(set (match_operand:DF 0 "register_operand" "=f")
2402 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
2403 (match_operand:DF 2 "register_operand" "f")))]
2404 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
2406 [(set_attr "type" "fdiv")
2407 (set_attr "mode" "DF")])
2410 [(set (match_operand:SF 0 "register_operand" "=f")
2411 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
2412 (match_operand:SF 2 "register_operand" "f")))]
2413 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
2415 [(set_attr "type" "fdiv")
2416 (set_attr "mode" "SF")])
2418 ;; If optimizing, prefer the divmod functions over separate div and
2419 ;; mod functions, since this will allow using one instruction for both
2420 ;; the quotient and remainder. At present, the divmod is not moved out
2421 ;; of loops if it is constant within the loop, so allow -mdebugc to
2422 ;; use the old method of doing things.
2424 ;; 64 is the multiply/divide hi register
2425 ;; 65 is the multiply/divide lo register
2427 ;; ??? We can't accept constants here, because the MIPS assembler will replace
2428 ;; a divide by power of 2 with a shift, and then the remainder is no longer
2431 (define_expand "divmodsi4"
2432 [(set (match_operand:SI 0 "register_operand" "=d")
2433 (div:SI (match_operand:SI 1 "register_operand" "d")
2434 (match_operand:SI 2 "register_operand" "d")))
2435 (set (match_operand:SI 3 "register_operand" "=d")
2436 (mod:SI (match_dup 1)
2438 (clobber (match_scratch:SI 4 "=l"))
2439 (clobber (match_scratch:SI 5 "=h"))
2440 (clobber (match_scratch:SI 6 "=a"))]
2444 emit_insn (gen_divmodsi4_internal (operands[0], operands[1], operands[2],
2446 if (!TARGET_NO_CHECK_ZERO_DIV)
2448 emit_insn (gen_div_trap (operands[2],
2452 if (TARGET_CHECK_RANGE_DIV)
2454 emit_insn (gen_div_trap (operands[2],
2455 copy_to_mode_reg (SImode, GEN_INT (-1)),
2457 emit_insn (gen_div_trap (operands[2],
2458 copy_to_mode_reg (SImode,
2461 (BITMASK_HIGH, SImode))),
2468 (define_insn "divmodsi4_internal"
2469 [(set (match_operand:SI 0 "register_operand" "=l")
2470 (div:SI (match_operand:SI 1 "register_operand" "d")
2471 (match_operand:SI 2 "register_operand" "d")))
2472 (set (match_operand:SI 3 "register_operand" "=h")
2473 (mod:SI (match_dup 1)
2475 (clobber (match_scratch:SI 4 "=a"))]
2478 [(set_attr "type" "idiv")
2479 (set_attr "mode" "SI")])
2481 (define_expand "divmoddi4"
2482 [(set (match_operand:DI 0 "register_operand" "=d")
2483 (div:DI (match_operand:DI 1 "se_register_operand" "d")
2484 (match_operand:DI 2 "se_register_operand" "d")))
2485 (set (match_operand:DI 3 "register_operand" "=d")
2486 (mod:DI (match_dup 1)
2488 (clobber (match_scratch:DI 4 "=l"))
2489 (clobber (match_scratch:DI 5 "=h"))
2490 (clobber (match_scratch:DI 6 "=a"))]
2491 "TARGET_64BIT && optimize"
2494 emit_insn (gen_divmoddi4_internal (operands[0], operands[1], operands[2],
2496 if (!TARGET_NO_CHECK_ZERO_DIV)
2498 emit_insn (gen_div_trap (operands[2],
2502 if (TARGET_CHECK_RANGE_DIV)
2504 emit_insn (gen_div_trap (operands[2],
2505 copy_to_mode_reg (DImode, GEN_INT (-1)),
2507 emit_insn (gen_div_trap (operands[2],
2508 copy_to_mode_reg (DImode,
2509 GEN_INT (BITMASK_HIGH)),
2516 (define_insn "divmoddi4_internal"
2517 [(set (match_operand:DI 0 "register_operand" "=l")
2518 (div:DI (match_operand:DI 1 "se_register_operand" "d")
2519 (match_operand:DI 2 "se_register_operand" "d")))
2520 (set (match_operand:DI 3 "register_operand" "=h")
2521 (mod:DI (match_dup 1)
2523 (clobber (match_scratch:DI 4 "=a"))]
2524 "TARGET_64BIT && optimize"
2526 [(set_attr "type" "idiv")
2527 (set_attr "mode" "SI")])
2529 (define_expand "udivmodsi4"
2530 [(set (match_operand:SI 0 "register_operand" "=d")
2531 (udiv:SI (match_operand:SI 1 "register_operand" "d")
2532 (match_operand:SI 2 "register_operand" "d")))
2533 (set (match_operand:SI 3 "register_operand" "=d")
2534 (umod:SI (match_dup 1)
2536 (clobber (match_scratch:SI 4 "=l"))
2537 (clobber (match_scratch:SI 5 "=h"))
2538 (clobber (match_scratch:SI 6 "=a"))]
2542 emit_insn (gen_udivmodsi4_internal (operands[0], operands[1], operands[2],
2544 if (!TARGET_NO_CHECK_ZERO_DIV)
2546 emit_insn (gen_div_trap (operands[2],
2554 (define_insn "udivmodsi4_internal"
2555 [(set (match_operand:SI 0 "register_operand" "=l")
2556 (udiv:SI (match_operand:SI 1 "register_operand" "d")
2557 (match_operand:SI 2 "register_operand" "d")))
2558 (set (match_operand:SI 3 "register_operand" "=h")
2559 (umod:SI (match_dup 1)
2561 (clobber (match_scratch:SI 4 "=a"))]
2564 [(set_attr "type" "idiv")
2565 (set_attr "mode" "SI")])
2567 (define_expand "udivmoddi4"
2568 [(set (match_operand:DI 0 "register_operand" "=d")
2569 (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
2570 (match_operand:DI 2 "se_register_operand" "d")))
2571 (set (match_operand:DI 3 "register_operand" "=d")
2572 (umod:DI (match_dup 1)
2574 (clobber (match_scratch:DI 4 "=l"))
2575 (clobber (match_scratch:DI 5 "=h"))
2576 (clobber (match_scratch:DI 6 "=a"))]
2577 "TARGET_64BIT && optimize"
2580 emit_insn (gen_udivmoddi4_internal (operands[0], operands[1], operands[2],
2582 if (!TARGET_NO_CHECK_ZERO_DIV)
2584 emit_insn (gen_div_trap (operands[2],
2592 (define_insn "udivmoddi4_internal"
2593 [(set (match_operand:DI 0 "register_operand" "=l")
2594 (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
2595 (match_operand:DI 2 "se_register_operand" "d")))
2596 (set (match_operand:DI 3 "register_operand" "=h")
2597 (umod:DI (match_dup 1)
2599 (clobber (match_scratch:DI 4 "=a"))]
2600 "TARGET_64BIT && optimize"
2602 [(set_attr "type" "idiv")
2603 (set_attr "mode" "SI")])
2607 (define_expand "div_trap"
2608 [(trap_if (eq (match_operand 0 "register_operand" "d")
2609 (match_operand 1 "true_reg_or_0_operand" "dJ"))
2610 (match_operand 2 "immediate_operand" ""))]
2615 emit_insn (gen_div_trap_mips16 (operands[0],operands[1],operands[2]));
2617 emit_insn (gen_div_trap_normal (operands[0],operands[1],operands[2]));
2621 (define_insn "div_trap_normal"
2622 [(trap_if (eq (match_operand 0 "register_operand" "d,d")
2623 (match_operand 1 "true_reg_or_0_operand" "d,J"))
2624 (match_operand 2 "immediate_operand" ""))]
2629 int have_dep_anti = 0;
2631 /* For divmod if one division is not needed then we don't need an extra
2632 divide by zero trap, which is anti dependent on previous trap */
2633 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
2635 if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
2636 && GET_CODE (XEXP (link, 0)) == INSN
2637 && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
2638 && which_alternative == 1)
2640 if (! have_dep_anti)
2642 if (GENERATE_BRANCHLIKELY)
2644 if (which_alternative == 1)
2645 return \"%(beql\\t%0,$0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
2647 return \"%(beql\\t%0,%1,1f\\n\\tbreak\\t%2\\n%~1:%)\";
2651 if (which_alternative == 1)
2652 return \"%(bne\\t%0,$0,1f\\n\\tnop\\n\\tbreak\\t%2\\n%~1:%)\";
2654 return \"%(bne\\t%0,%1,1f\\n\\tnop\\n\\tbreak\\t%2\\n%~1:%)\";
2659 [(set_attr "type" "unknown")
2660 (set_attr "length" "12")])
2663 ;; The mips16 bne insns is a macro which uses reg 24 as an intermediate.
2665 (define_insn "div_trap_mips16"
2666 [(trap_if (eq (match_operand 0 "register_operand" "d,d")
2667 (match_operand 1 "true_reg_or_0_operand" "d,J"))
2668 (match_operand 2 "immediate_operand" ""))
2669 (clobber (reg:SI 24))]
2674 int have_dep_anti = 0;
2676 /* For divmod if one division is not needed then we don't need an extra
2677 divide by zero trap, which is anti dependent on previous trap */
2678 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
2680 if ((int) REG_DEP_ANTI == (int) REG_NOTE_KIND (link)
2681 && GET_CODE (XEXP (link, 0)) == INSN
2682 && GET_CODE (PATTERN (XEXP (link, 0))) == TRAP_IF
2683 && which_alternative == 1)
2685 if (! have_dep_anti)
2687 /* No branch delay slots on mips16. */
2688 if (which_alternative == 1)
2689 return \"%(bnez\\t%0,1f\\n\\tbreak\\t%2\\n%~1:%)\";
2691 return \"%(bne\\t%0,%1,1f\\n\\tbreak\\t%2\\n%~1:%)\";
2695 [(set_attr "type" "unknown")
2696 (set_attr "length" "12")])
2698 (define_expand "divsi3"
2699 [(set (match_operand:SI 0 "register_operand" "=l")
2700 (div:SI (match_operand:SI 1 "register_operand" "d")
2701 (match_operand:SI 2 "register_operand" "d")))
2702 (clobber (match_scratch:SI 3 "=h"))
2703 (clobber (match_scratch:SI 4 "=a"))]
2707 emit_insn (gen_divsi3_internal (operands[0], operands[1], operands[2]));
2708 if (!TARGET_NO_CHECK_ZERO_DIV)
2710 emit_insn (gen_div_trap (operands[2],
2714 if (TARGET_CHECK_RANGE_DIV)
2716 emit_insn (gen_div_trap (operands[2],
2717 copy_to_mode_reg (SImode, GEN_INT (-1)),
2719 emit_insn (gen_div_trap (operands[2],
2720 copy_to_mode_reg (SImode,
2723 (BITMASK_HIGH, SImode))),
2730 (define_insn "divsi3_internal"
2731 [(set (match_operand:SI 0 "register_operand" "=l")
2732 (div:SI (match_operand:SI 1 "register_operand" "d")
2733 (match_operand:SI 2 "nonmemory_operand" "di")))
2734 (clobber (match_scratch:SI 3 "=h"))
2735 (clobber (match_scratch:SI 4 "=a"))]
2738 [(set_attr "type" "idiv")
2739 (set_attr "mode" "SI")])
2741 (define_expand "divdi3"
2742 [(set (match_operand:DI 0 "register_operand" "=l")
2743 (div:DI (match_operand:DI 1 "se_register_operand" "d")
2744 (match_operand:DI 2 "se_register_operand" "d")))
2745 (clobber (match_scratch:DI 3 "=h"))
2746 (clobber (match_scratch:DI 4 "=a"))]
2747 "TARGET_64BIT && !optimize"
2750 emit_insn (gen_divdi3_internal (operands[0], operands[1], operands[2]));
2751 if (!TARGET_NO_CHECK_ZERO_DIV)
2753 emit_insn (gen_div_trap (operands[2],
2757 if (TARGET_CHECK_RANGE_DIV)
2759 emit_insn (gen_div_trap (operands[2],
2760 copy_to_mode_reg (DImode, GEN_INT (-1)),
2762 emit_insn (gen_div_trap (operands[2],
2763 copy_to_mode_reg (DImode,
2764 GEN_INT (BITMASK_HIGH)),
2771 (define_insn "divdi3_internal"
2772 [(set (match_operand:DI 0 "register_operand" "=l")
2773 (div:DI (match_operand:DI 1 "se_register_operand" "d")
2774 (match_operand:DI 2 "se_nonmemory_operand" "di")))
2775 (clobber (match_scratch:SI 3 "=h"))
2776 (clobber (match_scratch:SI 4 "=a"))]
2777 "TARGET_64BIT && !optimize"
2779 [(set_attr "type" "idiv")
2780 (set_attr "mode" "DI")])
2782 (define_expand "modsi3"
2783 [(set (match_operand:SI 0 "register_operand" "=h")
2784 (mod:SI (match_operand:SI 1 "register_operand" "d")
2785 (match_operand:SI 2 "register_operand" "d")))
2786 (clobber (match_scratch:SI 3 "=l"))
2787 (clobber (match_scratch:SI 4 "=a"))]
2791 emit_insn (gen_modsi3_internal (operands[0], operands[1], operands[2]));
2792 if (!TARGET_NO_CHECK_ZERO_DIV)
2794 emit_insn (gen_div_trap (operands[2],
2798 if (TARGET_CHECK_RANGE_DIV)
2800 emit_insn (gen_div_trap (operands[2],
2801 copy_to_mode_reg (SImode, GEN_INT (-1)),
2803 emit_insn (gen_div_trap (operands[2],
2804 copy_to_mode_reg (SImode,
2807 (BITMASK_HIGH, SImode))),
2814 (define_insn "modsi3_internal"
2815 [(set (match_operand:SI 0 "register_operand" "=h")
2816 (mod:SI (match_operand:SI 1 "register_operand" "d")
2817 (match_operand:SI 2 "nonmemory_operand" "di")))
2818 (clobber (match_scratch:SI 3 "=l"))
2819 (clobber (match_scratch:SI 4 "=a"))]
2822 [(set_attr "type" "idiv")
2823 (set_attr "mode" "SI")])
2825 (define_expand "moddi3"
2826 [(set (match_operand:DI 0 "register_operand" "=h")
2827 (mod:DI (match_operand:DI 1 "se_register_operand" "d")
2828 (match_operand:DI 2 "se_register_operand" "d")))
2829 (clobber (match_scratch:DI 3 "=l"))
2830 (clobber (match_scratch:DI 4 "=a"))]
2831 "TARGET_64BIT && !optimize"
2834 emit_insn (gen_moddi3_internal (operands[0], operands[1], operands[2]));
2835 if (!TARGET_NO_CHECK_ZERO_DIV)
2837 emit_insn (gen_div_trap (operands[2],
2841 if (TARGET_CHECK_RANGE_DIV)
2843 emit_insn (gen_div_trap (operands[2],
2844 copy_to_mode_reg (DImode, GEN_INT (-1)),
2846 emit_insn (gen_div_trap (operands[2],
2847 copy_to_mode_reg (DImode,
2848 GEN_INT (BITMASK_HIGH)),
2855 (define_insn "moddi3_internal"
2856 [(set (match_operand:DI 0 "register_operand" "=h")
2857 (mod:DI (match_operand:DI 1 "se_register_operand" "d")
2858 (match_operand:DI 2 "se_nonmemory_operand" "di")))
2859 (clobber (match_scratch:SI 3 "=l"))
2860 (clobber (match_scratch:SI 4 "=a"))]
2861 "TARGET_64BIT && !optimize"
2863 [(set_attr "type" "idiv")
2864 (set_attr "mode" "DI")])
2866 (define_expand "udivsi3"
2867 [(set (match_operand:SI 0 "register_operand" "=l")
2868 (udiv:SI (match_operand:SI 1 "register_operand" "d")
2869 (match_operand:SI 2 "register_operand" "d")))
2870 (clobber (match_scratch:SI 3 "=h"))
2871 (clobber (match_scratch:SI 4 "=a"))]
2875 emit_insn (gen_udivsi3_internal (operands[0], operands[1], operands[2]));
2876 if (!TARGET_NO_CHECK_ZERO_DIV)
2878 emit_insn (gen_div_trap (operands[2],
2886 (define_insn "udivsi3_internal"
2887 [(set (match_operand:SI 0 "register_operand" "=l")
2888 (udiv:SI (match_operand:SI 1 "register_operand" "d")
2889 (match_operand:SI 2 "nonmemory_operand" "di")))
2890 (clobber (match_scratch:SI 3 "=h"))
2891 (clobber (match_scratch:SI 4 "=a"))]
2894 [(set_attr "type" "idiv")
2895 (set_attr "mode" "SI")])
2897 (define_expand "udivdi3"
2898 [(set (match_operand:DI 0 "register_operand" "=l")
2899 (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
2900 (match_operand:DI 2 "se_register_operand" "di")))
2901 (clobber (match_scratch:DI 3 "=h"))
2902 (clobber (match_scratch:DI 4 "=a"))]
2903 "TARGET_64BIT && !optimize"
2906 emit_insn (gen_udivdi3_internal (operands[0], operands[1], operands[2]));
2907 if (!TARGET_NO_CHECK_ZERO_DIV)
2909 emit_insn (gen_div_trap (operands[2],
2917 (define_insn "udivdi3_internal"
2918 [(set (match_operand:DI 0 "register_operand" "=l")
2919 (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
2920 (match_operand:DI 2 "se_nonmemory_operand" "di")))
2921 (clobber (match_scratch:SI 3 "=h"))
2922 (clobber (match_scratch:SI 4 "=a"))]
2923 "TARGET_64BIT && !optimize"
2925 [(set_attr "type" "idiv")
2926 (set_attr "mode" "DI")])
2928 (define_expand "umodsi3"
2929 [(set (match_operand:SI 0 "register_operand" "=h")
2930 (umod:SI (match_operand:SI 1 "register_operand" "d")
2931 (match_operand:SI 2 "register_operand" "d")))
2932 (clobber (match_scratch:SI 3 "=l"))
2933 (clobber (match_scratch:SI 4 "=a"))]
2937 emit_insn (gen_umodsi3_internal (operands[0], operands[1], operands[2]));
2938 if (!TARGET_NO_CHECK_ZERO_DIV)
2940 emit_insn (gen_div_trap (operands[2],
2948 (define_insn "umodsi3_internal"
2949 [(set (match_operand:SI 0 "register_operand" "=h")
2950 (umod:SI (match_operand:SI 1 "register_operand" "d")
2951 (match_operand:SI 2 "nonmemory_operand" "di")))
2952 (clobber (match_scratch:SI 3 "=l"))
2953 (clobber (match_scratch:SI 4 "=a"))]
2956 [(set_attr "type" "idiv")
2957 (set_attr "mode" "SI")])
2959 (define_expand "umoddi3"
2960 [(set (match_operand:DI 0 "register_operand" "=h")
2961 (umod:DI (match_operand:DI 1 "se_register_operand" "d")
2962 (match_operand:DI 2 "se_register_operand" "di")))
2963 (clobber (match_scratch:DI 3 "=l"))
2964 (clobber (match_scratch:DI 4 "=a"))]
2965 "TARGET_64BIT && !optimize"
2968 emit_insn (gen_umoddi3_internal (operands[0], operands[1], operands[2]));
2969 if (!TARGET_NO_CHECK_ZERO_DIV)
2971 emit_insn (gen_div_trap (operands[2],
2979 (define_insn "umoddi3_internal"
2980 [(set (match_operand:DI 0 "register_operand" "=h")
2981 (umod:DI (match_operand:DI 1 "se_register_operand" "d")
2982 (match_operand:DI 2 "se_nonmemory_operand" "di")))
2983 (clobber (match_scratch:SI 3 "=l"))
2984 (clobber (match_scratch:SI 4 "=a"))]
2985 "TARGET_64BIT && !optimize"
2987 [(set_attr "type" "idiv")
2988 (set_attr "mode" "DI")])
2991 ;; ....................
2995 ;; ....................
2997 (define_insn "sqrtdf2"
2998 [(set (match_operand:DF 0 "register_operand" "=f")
2999 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
3000 "TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT"
3002 [(set_attr "type" "fsqrt")
3003 (set_attr "mode" "DF")])
3005 (define_insn "sqrtsf2"
3006 [(set (match_operand:SF 0 "register_operand" "=f")
3007 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
3008 "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
3010 [(set_attr "type" "fsqrt")
3011 (set_attr "mode" "SF")])
3014 [(set (match_operand:DF 0 "register_operand" "=f")
3015 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
3016 (sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
3017 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
3019 [(set_attr "type" "fsqrt")
3020 (set_attr "mode" "DF")])
3023 [(set (match_operand:SF 0 "register_operand" "=f")
3024 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
3025 (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
3026 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
3028 [(set_attr "type" "fsqrt")
3029 (set_attr "mode" "SF")])
3033 ;; ....................
3037 ;; ....................
3039 ;; Do not use the integer abs macro instruction, since that signals an
3040 ;; exception on -2147483648 (sigh).
3042 (define_insn "abssi2"
3043 [(set (match_operand:SI 0 "register_operand" "=d")
3044 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
3048 dslots_jump_total++;
3049 dslots_jump_filled++;
3050 operands[2] = const0_rtx;
3052 if (REGNO (operands[0]) == REGNO (operands[1]))
3054 if (GENERATE_BRANCHLIKELY)
3055 return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\";
3057 return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n%~1:\";
3060 return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\";
3062 [(set_attr "type" "multi")
3063 (set_attr "mode" "SI")
3064 (set_attr "length" "12")])
3066 (define_insn "absdi2"
3067 [(set (match_operand:DI 0 "register_operand" "=d")
3068 (abs:DI (match_operand:DI 1 "se_register_operand" "d")))]
3069 "TARGET_64BIT && !TARGET_MIPS16"
3072 unsigned int regno1;
3073 dslots_jump_total++;
3074 dslots_jump_filled++;
3075 operands[2] = const0_rtx;
3077 if (GET_CODE (operands[1]) == REG)
3078 regno1 = REGNO (operands[1]);
3080 regno1 = REGNO (XEXP (operands[1], 0));
3082 if (REGNO (operands[0]) == regno1)
3083 return \"%(bltzl\\t%1,1f\\n\\tdsubu\\t%0,%z2,%0\\n%~1:%)\";
3085 return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tdsubu\\t%0,%z2,%0\\n%~1:%)\";
3087 [(set_attr "type" "multi")
3088 (set_attr "mode" "DI")
3089 (set_attr "length" "12")])
3091 (define_insn "absdf2"
3092 [(set (match_operand:DF 0 "register_operand" "=f")
3093 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
3094 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3096 [(set_attr "type" "fabs")
3097 (set_attr "mode" "DF")])
3099 (define_insn "abssf2"
3100 [(set (match_operand:SF 0 "register_operand" "=f")
3101 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
3104 [(set_attr "type" "fabs")
3105 (set_attr "mode" "SF")])
3109 ;; ....................
3111 ;; FIND FIRST BIT INSTRUCTION
3113 ;; ....................
3116 (define_insn "ffssi2"
3117 [(set (match_operand:SI 0 "register_operand" "=&d")
3118 (ffs:SI (match_operand:SI 1 "register_operand" "d")))
3119 (clobber (match_scratch:SI 2 "=&d"))
3120 (clobber (match_scratch:SI 3 "=&d"))]
3124 dslots_jump_total += 2;
3125 dslots_jump_filled += 2;
3126 operands[4] = const0_rtx;
3128 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
3131 \\tbeq\\t%1,%z4,2f\\n\\
3132 %~1:\\tand\\t%2,%1,0x0001\\n\\
3133 \\taddu\\t%0,%0,1\\n\\
3134 \\tbeq\\t%2,%z4,1b\\n\\
3135 \\tsrl\\t%1,%1,1\\n\\
3140 \\tmove\\t%3,%1\\n\\
3141 \\tbeq\\t%3,%z4,2f\\n\\
3142 %~1:\\tand\\t%2,%3,0x0001\\n\\
3143 \\taddu\\t%0,%0,1\\n\\
3144 \\tbeq\\t%2,%z4,1b\\n\\
3145 \\tsrl\\t%3,%3,1\\n\\
3148 [(set_attr "type" "multi")
3149 (set_attr "mode" "SI")
3150 (set_attr "length" "12")])
3152 (define_insn "ffsdi2"
3153 [(set (match_operand:DI 0 "register_operand" "=&d")
3154 (ffs:DI (match_operand:DI 1 "se_register_operand" "d")))
3155 (clobber (match_scratch:DI 2 "=&d"))
3156 (clobber (match_scratch:DI 3 "=&d"))]
3157 "TARGET_64BIT && !TARGET_MIPS16"
3160 dslots_jump_total += 2;
3161 dslots_jump_filled += 2;
3162 operands[4] = const0_rtx;
3164 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
3167 \\tbeq\\t%1,%z4,2f\\n\\
3168 %~1:\\tand\\t%2,%1,0x0001\\n\\
3169 \\tdaddu\\t%0,%0,1\\n\\
3170 \\tbeq\\t%2,%z4,1b\\n\\
3171 \\tdsrl\\t%1,%1,1\\n\\
3176 \\tmove\\t%3,%1\\n\\
3177 \\tbeq\\t%3,%z4,2f\\n\\
3178 %~1:\\tand\\t%2,%3,0x0001\\n\\
3179 \\tdaddu\\t%0,%0,1\\n\\
3180 \\tbeq\\t%2,%z4,1b\\n\\
3181 \\tdsrl\\t%3,%3,1\\n\\
3184 [(set_attr "type" "multi")
3185 (set_attr "mode" "DI")
3186 (set_attr "length" "24")])
3190 ;; ....................
3192 ;; NEGATION and ONE'S COMPLEMENT
3194 ;; ....................
3196 (define_insn "negsi2"
3197 [(set (match_operand:SI 0 "register_operand" "=d")
3198 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
3203 return \"neg\\t%0,%1\";
3204 operands[2] = const0_rtx;
3205 return \"subu\\t%0,%z2,%1\";
3207 [(set_attr "type" "arith")
3208 (set_attr "mode" "SI")])
3210 (define_expand "negdi2"
3211 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
3212 (neg:DI (match_operand:DI 1 "se_register_operand" "d")))
3213 (clobber (match_dup 2))])]
3214 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
3219 emit_insn (gen_negdi2_internal_2 (operands[0], operands[1]));
3223 operands[2] = gen_reg_rtx (SImode);
3226 (define_insn "negdi2_internal"
3227 [(set (match_operand:DI 0 "register_operand" "=d")
3228 (neg:DI (match_operand:DI 1 "register_operand" "d")))
3229 (clobber (match_operand:SI 2 "register_operand" "=d"))]
3230 "! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
3233 operands[3] = const0_rtx;
3234 return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\";
3236 [(set_attr "type" "darith")
3237 (set_attr "mode" "DI")
3238 (set_attr "length" "16")])
3240 (define_insn "negdi2_internal_2"
3241 [(set (match_operand:DI 0 "register_operand" "=d")
3242 (neg:DI (match_operand:DI 1 "se_register_operand" "d")))]
3243 "TARGET_64BIT && !TARGET_MIPS16"
3246 operands[2] = const0_rtx;
3247 return \"dsubu\\t%0,%z2,%1\";
3249 [(set_attr "type" "arith")
3250 (set_attr "mode" "DI")])
3252 (define_insn "negdf2"
3253 [(set (match_operand:DF 0 "register_operand" "=f")
3254 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
3255 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3257 [(set_attr "type" "fneg")
3258 (set_attr "mode" "DF")])
3260 (define_insn "negsf2"
3261 [(set (match_operand:SF 0 "register_operand" "=f")
3262 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
3265 [(set_attr "type" "fneg")
3266 (set_attr "mode" "SF")])
3268 (define_insn "one_cmplsi2"
3269 [(set (match_operand:SI 0 "register_operand" "=d")
3270 (not:SI (match_operand:SI 1 "register_operand" "d")))]
3275 return \"not\\t%0,%1\";
3276 operands[2] = const0_rtx;
3277 return \"nor\\t%0,%z2,%1\";
3279 [(set_attr "type" "arith")
3280 (set_attr "mode" "SI")])
3282 (define_insn "one_cmpldi2"
3283 [(set (match_operand:DI 0 "register_operand" "=d")
3284 (not:DI (match_operand:DI 1 "se_register_operand" "d")))]
3291 return \"not\\t%0,%1\";
3292 return \"not\\t%M0,%M1\;not\\t%L0,%L1\";
3294 operands[2] = const0_rtx;
3296 return \"nor\\t%0,%z2,%1\";
3297 return \"nor\\t%M0,%z2,%M1\;nor\\t%L0,%z2,%L1\";
3299 [(set_attr "type" "darith")
3300 (set_attr "mode" "DI")
3301 (set (attr "length")
3302 (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
3307 [(set (match_operand:DI 0 "register_operand" "")
3308 (not:DI (match_operand:DI 1 "register_operand" "")))]
3309 "reload_completed && !TARGET_64BIT
3310 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
3311 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3312 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
3314 [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
3315 (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
3320 ;; ....................
3324 ;; ....................
3327 ;; Many of these instructions uses trivial define_expands, because we
3328 ;; want to use a different set of constraints when TARGET_MIPS16.
3330 (define_expand "andsi3"
3331 [(set (match_operand:SI 0 "register_operand" "=d,d")
3332 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3333 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3339 operands[1] = force_reg (SImode, operands[1]);
3340 operands[2] = force_reg (SImode, operands[2]);
3345 [(set (match_operand:SI 0 "register_operand" "=d,d")
3346 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3347 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3352 [(set_attr "type" "arith")
3353 (set_attr "mode" "SI")])
3356 [(set (match_operand:SI 0 "register_operand" "=d")
3357 (and:SI (match_operand:SI 1 "register_operand" "%0")
3358 (match_operand:SI 2 "register_operand" "d")))]
3361 [(set_attr "type" "arith")
3362 (set_attr "mode" "SI")])
3364 (define_expand "anddi3"
3365 [(set (match_operand:DI 0 "register_operand" "=d")
3366 (and:DI (match_operand:DI 1 "se_register_operand" "d")
3367 (match_operand:DI 2 "se_register_operand" "d")))]
3368 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
3373 operands[1] = force_reg (DImode, operands[1]);
3374 operands[2] = force_reg (DImode, operands[2]);
3379 [(set (match_operand:DI 0 "register_operand" "=d")
3380 (and:DI (match_operand:DI 1 "se_register_operand" "d")
3381 (match_operand:DI 2 "se_register_operand" "d")))]
3382 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
3386 return \"and\\t%0,%1,%2\";
3387 return \"and\\t%M0,%M1,%M2\;and\\t%L0,%L1,%L2\";
3389 [(set_attr "type" "darith")
3390 (set_attr "mode" "DI")
3391 (set (attr "length")
3392 (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
3397 [(set (match_operand:DI 0 "register_operand" "=d")
3398 (and:DI (match_operand:DI 1 "se_register_operand" "0")
3399 (match_operand:DI 2 "se_register_operand" "d")))]
3400 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && TARGET_MIPS16"
3404 return \"and\\t%0,%2\";
3405 return \"and\\t%M0,%M2\;and\\t%L0,%L2\";
3407 [(set_attr "type" "darith")
3408 (set_attr "mode" "DI")
3409 (set (attr "length")
3410 (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
3415 [(set (match_operand:DI 0 "register_operand" "")
3416 (and:DI (match_operand:DI 1 "register_operand" "")
3417 (match_operand:DI 2 "register_operand" "")))]
3418 "reload_completed && !TARGET_64BIT
3419 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
3420 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3421 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
3422 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
3424 [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
3425 (set (subreg:SI (match_dup 0) 4) (and:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))]
3428 (define_insn "anddi3_internal1"
3429 [(set (match_operand:DI 0 "register_operand" "=d,d")
3430 (and:DI (match_operand:DI 1 "se_register_operand" "%d,d")
3431 (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
3432 "TARGET_64BIT && !TARGET_MIPS16"
3436 [(set_attr "type" "arith")
3437 (set_attr "mode" "DI")])
3439 (define_expand "iorsi3"
3440 [(set (match_operand:SI 0 "register_operand" "=d,d")
3441 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3442 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3448 operands[1] = force_reg (SImode, operands[1]);
3449 operands[2] = force_reg (SImode, operands[2]);
3454 [(set (match_operand:SI 0 "register_operand" "=d,d")
3455 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3456 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3461 [(set_attr "type" "arith")
3462 (set_attr "mode" "SI")])
3465 [(set (match_operand:SI 0 "register_operand" "=d")
3466 (ior:SI (match_operand:SI 1 "register_operand" "%0")
3467 (match_operand:SI 2 "register_operand" "d")))]
3470 [(set_attr "type" "arith")
3471 (set_attr "mode" "SI")])
3473 ;;; ??? There is no iordi3 pattern which accepts 'K' constants when
3476 (define_expand "iordi3"
3477 [(set (match_operand:DI 0 "register_operand" "=d")
3478 (ior:DI (match_operand:DI 1 "se_register_operand" "d")
3479 (match_operand:DI 2 "se_register_operand" "d")))]
3480 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
3484 [(set (match_operand:DI 0 "register_operand" "=d")
3485 (ior:DI (match_operand:DI 1 "se_register_operand" "d")
3486 (match_operand:DI 2 "se_register_operand" "d")))]
3487 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
3491 return \"or\\t%0,%1,%2\";
3492 return \"or\\t%M0,%M1,%M2\;or\\t%L0,%L1,%L2\";
3494 [(set_attr "type" "darith")
3495 (set_attr "mode" "DI")
3496 (set (attr "length")
3497 (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
3502 [(set (match_operand:DI 0 "register_operand" "=d")
3503 (ior:DI (match_operand:DI 1 "se_register_operand" "0")
3504 (match_operand:DI 2 "se_register_operand" "d")))]
3505 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && TARGET_MIPS16"
3509 return \"or\\t%0,%2\";
3510 return \"or\\t%M0,%M2\;or\\t%L0,%L2\";
3512 [(set_attr "type" "darith")
3513 (set_attr "mode" "DI")
3514 (set (attr "length")
3515 (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
3520 [(set (match_operand:DI 0 "register_operand" "")
3521 (ior:DI (match_operand:DI 1 "register_operand" "")
3522 (match_operand:DI 2 "register_operand" "")))]
3523 "reload_completed && !TARGET_64BIT
3524 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
3525 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3526 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
3527 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
3529 [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
3530 (set (subreg:SI (match_dup 0) 4) (ior:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))]
3533 (define_expand "xorsi3"
3534 [(set (match_operand:SI 0 "register_operand" "=d,d")
3535 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3536 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3541 [(set (match_operand:SI 0 "register_operand" "=d,d")
3542 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
3543 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
3548 [(set_attr "type" "arith")
3549 (set_attr "mode" "SI")])
3552 [(set (match_operand:SI 0 "register_operand" "=d,t,t")
3553 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%0,d,d")
3554 (match_operand:SI 2 "uns_arith_operand" "d,K,d")))]
3560 [(set_attr "type" "arith")
3561 (set_attr "mode" "SI")
3562 (set_attr_alternative "length"
3564 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
3569 ;; ??? If delete the 32-bit long long patterns, then could merge this with
3570 ;; the following xordi3_internal pattern.
3571 (define_expand "xordi3"
3572 [(set (match_operand:DI 0 "register_operand" "=d")
3573 (xor:DI (match_operand:DI 1 "se_register_operand" "d")
3574 (match_operand:DI 2 "se_register_operand" "d")))]
3575 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
3579 [(set (match_operand:DI 0 "register_operand" "=d")
3580 (xor:DI (match_operand:DI 1 "se_register_operand" "d")
3581 (match_operand:DI 2 "se_register_operand" "d")))]
3582 "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
3586 return \"xor\\t%0,%1,%2\";
3587 return \"xor\\t%M0,%M1,%M2\;xor\\t%L0,%L1,%L2\";
3589 [(set_attr "type" "darith")
3590 (set_attr "mode" "DI")
3591 (set (attr "length")
3592 (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
3597 [(set (match_operand:DI 0 "register_operand" "=d")
3598 (xor:DI (match_operand:DI 1 "se_register_operand" "0")
3599 (match_operand:DI 2 "se_register_operand" "d")))]
3600 "!TARGET_64BIT && TARGET_MIPS16"
3601 "xor\\t%M0,%M2\;xor\\t%L0,%L2"
3602 [(set_attr "type" "darith")
3603 (set_attr "mode" "DI")
3604 (set_attr "length" "8")])
3607 [(set (match_operand:DI 0 "register_operand" "=d,t,t")
3608 (xor:DI (match_operand:DI 1 "se_register_operand" "%0,d,d")
3609 (match_operand:DI 2 "se_uns_arith_operand" "d,K,d")))]
3610 "TARGET_64BIT && TARGET_MIPS16"
3615 [(set_attr "type" "arith")
3616 (set_attr "mode" "DI")
3617 (set_attr_alternative "length"
3619 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
3625 [(set (match_operand:DI 0 "register_operand" "")
3626 (xor:DI (match_operand:DI 1 "register_operand" "")
3627 (match_operand:DI 2 "register_operand" "")))]
3628 "reload_completed && !TARGET_64BIT
3629 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
3630 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3631 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
3632 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
3634 [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
3635 (set (subreg:SI (match_dup 0) 4) (xor:SI (subreg:SI (match_dup 1) 4) (subreg:SI (match_dup 2) 4)))]
3638 (define_insn "xordi3_immed"
3639 [(set (match_operand:DI 0 "register_operand" "=d")
3640 (xor:DI (match_operand:DI 1 "se_register_operand" "d")
3641 (match_operand:DI 2 "se_uns_arith_operand" "K")))]
3642 "TARGET_64BIT && !TARGET_MIPS16"
3644 [(set_attr "type" "arith")
3645 (set_attr "mode" "DI")])
3647 (define_insn "*norsi3"
3648 [(set (match_operand:SI 0 "register_operand" "=d")
3649 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
3650 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
3653 [(set_attr "type" "arith")
3654 (set_attr "mode" "SI")])
3656 (define_insn "*nordi3"
3657 [(set (match_operand:DI 0 "register_operand" "=d")
3658 (and:DI (not:DI (match_operand:DI 1 "se_register_operand" "d"))
3659 (not:DI (match_operand:DI 2 "se_register_operand" "d"))))]
3664 return \"nor\\t%0,%z1,%z2\";
3665 return \"nor\\t%M0,%M1,%M2\;nor\\t%L0,%L1,%L2\";
3667 [(set_attr "type" "darith")
3668 (set_attr "mode" "DI")
3669 (set (attr "length")
3670 (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
3675 [(set (match_operand:DI 0 "register_operand" "")
3676 (and:DI (not:DI (match_operand:DI 1 "register_operand" ""))
3677 (not:DI (match_operand:DI 2 "register_operand" ""))))]
3678 "reload_completed && !TARGET_MIPS16 && !TARGET_64BIT
3679 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
3680 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3681 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
3682 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
3684 [(set (subreg:SI (match_dup 0) 0) (and:SI (not:SI (subreg:SI (match_dup 1) 0)) (not:SI (subreg:SI (match_dup 2) 0))))
3685 (set (subreg:SI (match_dup 0) 4) (and:SI (not:SI (subreg:SI (match_dup 1) 4)) (not:SI (subreg:SI (match_dup 2) 4))))]
3689 ;; ....................
3693 ;; ....................
3695 (define_insn "truncdfsf2"
3696 [(set (match_operand:SF 0 "register_operand" "=f")
3697 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3698 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3700 [(set_attr "type" "fcvt")
3701 (set_attr "mode" "SF")])
3703 (define_insn "truncdisi2"
3704 [(set (match_operand:SI 0 "register_operand" "=d")
3705 (truncate:SI (match_operand:DI 1 "se_register_operand" "d")))]
3710 return \"dsll\\t%0,%1,32\;dsra\\t%0,32\";
3711 return \"dsll\\t%0,%1,32\;dsra\\t%0,%0,32\";
3713 [(set_attr "type" "darith")
3714 (set_attr "mode" "SI")
3715 (set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0))
3719 (define_insn "truncdihi2"
3720 [(set (match_operand:HI 0 "register_operand" "=d")
3721 (truncate:HI (match_operand:DI 1 "se_register_operand" "d")))]
3726 return \"dsll\\t%0,%1,48\;dsra\\t%0,48\";
3727 return \"andi\\t%0,%1,0xffff\";
3729 [(set_attr "type" "darith")
3730 (set_attr "mode" "HI")
3731 (set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0))
3734 (define_insn "truncdiqi2"
3735 [(set (match_operand:QI 0 "register_operand" "=d")
3736 (truncate:QI (match_operand:DI 1 "se_register_operand" "d")))]
3741 return \"dsll\\t%0,%1,56\;dsra\\t%0,56\";
3742 return \"andi\\t%0,%1,0x00ff\";
3744 [(set_attr "type" "darith")
3745 (set_attr "mode" "QI")
3746 (set (attr "length") (if_then_else (eq (symbol_ref "mips16") (const_int 0))
3750 ;; Combiner patterns to optimize shift/truncate combinations.
3752 [(set (match_operand:SI 0 "register_operand" "=d")
3753 (truncate:SI (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
3754 (match_operand:DI 2 "small_int" "I"))))]
3755 "TARGET_64BIT && !TARGET_MIPS16"
3758 int shift_amt = INTVAL (operands[2]) & 0x3f;
3762 operands[2] = GEN_INT (32 - shift_amt);
3763 return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
3767 operands[2] = GEN_INT (shift_amt);
3768 return \"dsra\\t%0,%1,%2\";
3771 [(set_attr "type" "darith")
3772 (set_attr "mode" "SI")
3773 (set_attr "length" "8")])
3776 [(set (match_operand:SI 0 "register_operand" "=d")
3777 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
3778 (match_operand:DI 2 "small_int" "I"))))]
3779 "TARGET_64BIT && !TARGET_MIPS16"
3782 int shift_amt = INTVAL (operands[2]) & 0x3f;
3786 operands[2] = GEN_INT (32 - shift_amt);
3787 return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
3789 else if (shift_amt == 32)
3790 return \"dsra\\t%0,%1,32\";
3793 operands[2] = GEN_INT (shift_amt);
3794 return \"dsrl\\t%0,%1,%2\";
3797 [(set_attr "type" "darith")
3798 (set_attr "mode" "SI")
3799 (set_attr "length" "8")])
3802 [(set (match_operand:SI 0 "register_operand" "=d")
3803 (truncate:SI (ashift:DI (match_operand:DI 1 "se_register_operand" "d")
3804 (match_operand:DI 2 "small_int" "I"))))]
3808 int shift_amt = INTVAL (operands[2]) & 0x3f;
3812 operands[2] = GEN_INT (32 + shift_amt);
3814 return \"dsll\\t%0,%1,%2\;dsra\\t%0,32\";
3815 return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
3818 return \"move\\t%0,%.\";
3820 [(set_attr "type" "darith")
3821 (set_attr "mode" "SI")
3822 (set_attr "length" "8")])
3824 ;; Combiner patterns to optimize truncate/zero_extend combinations.
3827 [(set (match_operand:SI 0 "register_operand" "=d")
3828 (zero_extend:SI (truncate:HI
3829 (match_operand:DI 1 "se_register_operand" "d"))))]
3830 "TARGET_64BIT && !TARGET_MIPS16"
3831 "andi\\t%0,%1,0xffff"
3832 [(set_attr "type" "darith")
3833 (set_attr "mode" "SI")])
3836 [(set (match_operand:SI 0 "register_operand" "=d")
3837 (zero_extend:SI (truncate:QI
3838 (match_operand:DI 1 "se_register_operand" "d"))))]
3839 "TARGET_64BIT && !TARGET_MIPS16"
3841 [(set_attr "type" "darith")
3842 (set_attr "mode" "SI")])
3845 [(set (match_operand:HI 0 "register_operand" "=d")
3846 (zero_extend:HI (truncate:QI
3847 (match_operand:DI 1 "se_register_operand" "d"))))]
3848 "TARGET_64BIT && !TARGET_MIPS16"
3850 [(set_attr "type" "darith")
3851 (set_attr "mode" "HI")])
3854 ;; ....................
3858 ;; ....................
3861 ;; Those for integer source operand are ordered widest source type first.
3863 (define_expand "zero_extendsidi2"
3864 [(set (match_operand:DI 0 "register_operand" "")
3865 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
3869 if ((optimize || TARGET_MIPS16) && GET_CODE (operands[1]) == MEM)
3870 operands[1] = force_not_mem (operands[1]);
3872 if (GET_CODE (operands[1]) != MEM)
3874 rtx op1 = gen_lowpart (DImode, operands[1]);
3875 rtx temp = gen_reg_rtx (DImode);
3876 rtx shift = GEN_INT (32);
3878 emit_insn (gen_ashldi3 (temp, op1, shift));
3879 emit_insn (gen_lshrdi3 (operands[0], temp, shift));
3884 (define_insn "zero_extendsidi2_internal"
3885 [(set (match_operand:DI 0 "register_operand" "=d,d")
3886 (zero_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))]
3887 "TARGET_64BIT && !TARGET_MIPS16"
3888 "* return mips_move_1word (operands, insn, TRUE);"
3889 [(set_attr "type" "load")
3890 (set_attr "mode" "DI")
3891 (set_attr "length" "4,8")])
3893 (define_expand "zero_extendhisi2"
3894 [(set (match_operand:SI 0 "register_operand" "")
3895 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
3899 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3901 rtx op = gen_lowpart (SImode, operands[1]);
3902 rtx temp = force_reg (SImode, GEN_INT (0xffff));
3904 emit_insn (gen_andsi3 (operands[0], op, temp));
3910 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3911 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
3915 if (which_alternative == 0)
3916 return \"andi\\t%0,%1,0xffff\";
3918 return mips_move_1word (operands, insn, TRUE);
3920 [(set_attr "type" "arith,load,load")
3921 (set_attr "mode" "SI")
3922 (set_attr "length" "4,4,8")])
3925 [(set (match_operand:SI 0 "register_operand" "=d,d")
3926 (zero_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
3928 "* return mips_move_1word (operands, insn, TRUE);"
3929 [(set_attr "type" "load,load")
3930 (set_attr "mode" "SI")
3931 (set_attr "length" "4,8")])
3933 (define_expand "zero_extendhidi2"
3934 [(set (match_operand:DI 0 "register_operand" "")
3935 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
3939 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3941 rtx op = gen_lowpart (DImode, operands[1]);
3942 rtx temp = force_reg (DImode, GEN_INT (0xffff));
3944 emit_insn (gen_anddi3 (operands[0], op, temp));
3950 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3951 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
3952 "TARGET_64BIT && !TARGET_MIPS16"
3955 if (which_alternative == 0)
3956 return \"andi\\t%0,%1,0xffff\";
3958 return mips_move_1word (operands, insn, TRUE);
3960 [(set_attr "type" "arith,load,load")
3961 (set_attr "mode" "DI")
3962 (set_attr "length" "4,4,8")])
3965 [(set (match_operand:DI 0 "register_operand" "=d,d")
3966 (zero_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
3967 "TARGET_64BIT && TARGET_MIPS16"
3968 "* return mips_move_1word (operands, insn, TRUE);"
3969 [(set_attr "type" "load,load")
3970 (set_attr "mode" "DI")
3971 (set_attr "length" "4,8")])
3973 (define_expand "zero_extendqihi2"
3974 [(set (match_operand:HI 0 "register_operand" "")
3975 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
3979 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
3981 rtx op0 = gen_lowpart (SImode, operands[0]);
3982 rtx op1 = gen_lowpart (SImode, operands[1]);
3983 rtx temp = force_reg (SImode, GEN_INT (0xff));
3985 emit_insn (gen_andsi3 (op0, op1, temp));
3991 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3992 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
3996 if (which_alternative == 0)
3997 return \"andi\\t%0,%1,0x00ff\";
3999 return mips_move_1word (operands, insn, TRUE);
4001 [(set_attr "type" "arith,load,load")
4002 (set_attr "mode" "HI")
4003 (set_attr "length" "4,4,8")])
4006 [(set (match_operand:HI 0 "register_operand" "=d,d")
4007 (zero_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
4009 "* return mips_move_1word (operands, insn, TRUE);"
4010 [(set_attr "type" "load,load")
4011 (set_attr "mode" "HI")
4012 (set_attr "length" "4,8")])
4014 (define_expand "zero_extendqisi2"
4015 [(set (match_operand:SI 0 "register_operand" "")
4016 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
4020 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
4022 rtx op = gen_lowpart (SImode, operands[1]);
4023 rtx temp = force_reg (SImode, GEN_INT (0xff));
4025 emit_insn (gen_andsi3 (operands[0], op, temp));
4031 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4032 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
4036 if (which_alternative == 0)
4037 return \"andi\\t%0,%1,0x00ff\";
4039 return mips_move_1word (operands, insn, TRUE);
4041 [(set_attr "type" "arith,load,load")
4042 (set_attr "mode" "SI")
4043 (set_attr "length" "4,4,8")])
4046 [(set (match_operand:SI 0 "register_operand" "=d,d")
4047 (zero_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
4049 "* return mips_move_1word (operands, insn, TRUE);"
4050 [(set_attr "type" "load,load")
4051 (set_attr "mode" "SI")
4052 (set_attr "length" "4,8")])
4054 (define_expand "zero_extendqidi2"
4055 [(set (match_operand:DI 0 "register_operand" "")
4056 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
4060 if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
4062 rtx op = gen_lowpart (DImode, operands[1]);
4063 rtx temp = force_reg (DImode, GEN_INT (0xff));
4065 emit_insn (gen_anddi3 (operands[0], op, temp));
4071 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4072 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
4073 "TARGET_64BIT && !TARGET_MIPS16"
4076 if (which_alternative == 0)
4077 return \"andi\\t%0,%1,0x00ff\";
4079 return mips_move_1word (operands, insn, TRUE);
4081 [(set_attr "type" "arith,load,load")
4082 (set_attr "mode" "DI")
4083 (set_attr "length" "4,4,8")])
4085 ;; These can be created when a paradoxical subreg operand with an implicit
4086 ;; sign_extend operator is reloaded. Because of the subreg, this is really
4088 ;; ??? It might be possible to eliminate the need for these patterns by adding
4089 ;; more support to reload for implicit sign_extend operators.
4090 (define_insn "*paradoxical_extendhidi2"
4091 [(set (match_operand:DI 0 "register_operand" "=d,d")
4093 (subreg:SI (match_operand:HI 1 "memory_operand" "R,m") 0)))]
4097 return mips_move_1word (operands, insn, TRUE);
4099 [(set_attr "type" "load,load")
4100 (set_attr "mode" "DI")
4101 (set_attr "length" "4,8")])
4104 [(set (match_operand:DI 0 "register_operand" "=d,d")
4105 (zero_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
4106 "TARGET_64BIT && TARGET_MIPS16"
4107 "* return mips_move_1word (operands, insn, TRUE);"
4108 [(set_attr "type" "load,load")
4109 (set_attr "mode" "DI")
4110 (set_attr "length" "4,8")])
4113 ;; ....................
4117 ;; ....................
4120 ;; Those for integer source operand are ordered widest source type first.
4122 ;; In 64 bit mode, 32 bit values in general registers are always
4123 ;; correctly sign extended. That means that if the target is a
4124 ;; general register, we can sign extend from SImode to DImode just by
4127 (define_insn "extendsidi2"
4128 [(set (match_operand:DI 0 "register_operand" "=d,y,d,*d,d,d")
4129 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,d,y,*x,R,m")))]
4131 "* return mips_move_1word (operands, insn, FALSE);"
4132 [(set_attr "type" "move,move,move,hilo,load,load")
4133 (set_attr "mode" "DI")
4134 (set_attr "length" "4,4,4,4,4,8")])
4136 ;; These patterns originally accepted general_operands, however, slightly
4137 ;; better code is generated by only accepting register_operands, and then
4138 ;; letting combine generate the lh and lb insns.
4140 (define_expand "extendhidi2"
4141 [(set (match_operand:DI 0 "register_operand" "")
4142 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
4146 if (optimize && GET_CODE (operands[1]) == MEM)
4147 operands[1] = force_not_mem (operands[1]);
4149 if (GET_CODE (operands[1]) != MEM)
4151 rtx op1 = gen_lowpart (DImode, operands[1]);
4152 rtx temp = gen_reg_rtx (DImode);
4153 rtx shift = GEN_INT (48);
4155 emit_insn (gen_ashldi3 (temp, op1, shift));
4156 emit_insn (gen_ashrdi3 (operands[0], temp, shift));
4161 (define_insn "extendhidi2_internal"
4162 [(set (match_operand:DI 0 "register_operand" "=d,d")
4163 (sign_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
4165 "* return mips_move_1word (operands, insn, FALSE);"
4166 [(set_attr "type" "load")
4167 (set_attr "mode" "DI")
4168 (set_attr "length" "4,8")])
4170 (define_expand "extendhisi2"
4171 [(set (match_operand:SI 0 "register_operand" "")
4172 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
4176 if (optimize && GET_CODE (operands[1]) == MEM)
4177 operands[1] = force_not_mem (operands[1]);
4179 if (GET_CODE (operands[1]) != MEM)
4181 rtx op1 = gen_lowpart (SImode, operands[1]);
4182 rtx temp = gen_reg_rtx (SImode);
4183 rtx shift = GEN_INT (16);
4185 emit_insn (gen_ashlsi3 (temp, op1, shift));
4186 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
4191 (define_insn "extendhisi2_internal"
4192 [(set (match_operand:SI 0 "register_operand" "=d,d")
4193 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
4195 "* return mips_move_1word (operands, insn, FALSE);"
4196 [(set_attr "type" "load")
4197 (set_attr "mode" "SI")
4198 (set_attr "length" "4,8")])
4200 (define_expand "extendqihi2"
4201 [(set (match_operand:HI 0 "register_operand" "")
4202 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
4206 if (optimize && GET_CODE (operands[1]) == MEM)
4207 operands[1] = force_not_mem (operands[1]);
4209 if (GET_CODE (operands[1]) != MEM)
4211 rtx op0 = gen_lowpart (SImode, operands[0]);
4212 rtx op1 = gen_lowpart (SImode, operands[1]);
4213 rtx temp = gen_reg_rtx (SImode);
4214 rtx shift = GEN_INT (24);
4216 emit_insn (gen_ashlsi3 (temp, op1, shift));
4217 emit_insn (gen_ashrsi3 (op0, temp, shift));
4222 (define_insn "extendqihi2_internal"
4223 [(set (match_operand:HI 0 "register_operand" "=d,d")
4224 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
4226 "* return mips_move_1word (operands, insn, FALSE);"
4227 [(set_attr "type" "load")
4228 (set_attr "mode" "SI")
4229 (set_attr "length" "4,8")])
4232 (define_expand "extendqisi2"
4233 [(set (match_operand:SI 0 "register_operand" "")
4234 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
4238 if (optimize && GET_CODE (operands[1]) == MEM)
4239 operands[1] = force_not_mem (operands[1]);
4241 if (GET_CODE (operands[1]) != MEM)
4243 rtx op1 = gen_lowpart (SImode, operands[1]);
4244 rtx temp = gen_reg_rtx (SImode);
4245 rtx shift = GEN_INT (24);
4247 emit_insn (gen_ashlsi3 (temp, op1, shift));
4248 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
4253 (define_insn "extendqisi2_insn"
4254 [(set (match_operand:SI 0 "register_operand" "=d,d")
4255 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
4257 "* return mips_move_1word (operands, insn, FALSE);"
4258 [(set_attr "type" "load")
4259 (set_attr "mode" "SI")
4260 (set_attr "length" "4,8")])
4262 (define_expand "extendqidi2"
4263 [(set (match_operand:DI 0 "register_operand" "")
4264 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
4268 if (optimize && GET_CODE (operands[1]) == MEM)
4269 operands[1] = force_not_mem (operands[1]);
4271 if (GET_CODE (operands[1]) != MEM)
4273 rtx op1 = gen_lowpart (DImode, operands[1]);
4274 rtx temp = gen_reg_rtx (DImode);
4275 rtx shift = GEN_INT (56);
4277 emit_insn (gen_ashldi3 (temp, op1, shift));
4278 emit_insn (gen_ashrdi3 (operands[0], temp, shift));
4283 (define_insn "extendqidi2_insn"
4284 [(set (match_operand:DI 0 "register_operand" "=d,d")
4285 (sign_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
4287 "* return mips_move_1word (operands, insn, FALSE);"
4288 [(set_attr "type" "load")
4289 (set_attr "mode" "DI")
4290 (set_attr "length" "4,8")])
4293 (define_insn "extendsfdf2"
4294 [(set (match_operand:DF 0 "register_operand" "=f")
4295 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
4296 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4298 [(set_attr "type" "fcvt")
4299 (set_attr "mode" "DF")])
4304 ;; ....................
4308 ;; ....................
4310 ;; The SImode scratch register can not be shared with address regs used for
4311 ;; operand zero, because then the address in the move instruction will be
4312 ;; clobbered. We mark the scratch register as early clobbered to prevent this.
4314 ;; We need the ?X in alternative 1 so that it will be chosen only if the
4315 ;; destination is a floating point register. Otherwise, alternative 1 can
4316 ;; have lower cost than alternative 0 (because there is one less loser), and
4317 ;; can be chosen when it won't work (because integral reloads into FP
4318 ;; registers are not supported).
4320 (define_insn "fix_truncdfsi2"
4321 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,*f,R,To")
4322 (fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
4323 (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
4324 (clobber (match_scratch:DF 3 "=f,?*X,f,f"))]
4325 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4330 if (which_alternative == 1)
4331 return \"trunc.w.d %0,%1,%2\";
4333 output_asm_insn (\"trunc.w.d %3,%1,%2\", operands);
4335 xoperands[0] = operands[0];
4336 xoperands[1] = operands[3];
4337 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
4340 [(set_attr "type" "fcvt")
4341 (set_attr "mode" "DF")
4342 (set_attr "length" "44,36,40,44")])
4345 (define_insn "fix_truncsfsi2"
4346 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,*f,R,To")
4347 (fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
4348 (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
4349 (clobber (match_scratch:SF 3 "=f,?*X,f,f"))]
4355 if (which_alternative == 1)
4356 return \"trunc.w.s %0,%1,%2\";
4358 output_asm_insn (\"trunc.w.s %3,%1,%2\", operands);
4360 xoperands[0] = operands[0];
4361 xoperands[1] = operands[3];
4362 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
4365 [(set_attr "type" "fcvt")
4366 (set_attr "mode" "SF")
4367 (set_attr "length" "44,36,40,44")])
4370 ;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
4371 ;;; but not in the chapter that describes the FPU. It is not mentioned at all
4372 ;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
4374 ;;; Deleting this means that we now need two libgcc2.a libraries. One for
4375 ;;; the 32 bit calling convention and one for the 64 bit calling convention.
4377 ;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also.
4379 (define_insn "fix_truncdfdi2"
4380 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,*f,R,To")
4381 (fix:DI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
4382 (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
4383 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4388 if (which_alternative == 1)
4389 return \"trunc.l.d %0,%1\";
4391 output_asm_insn (\"trunc.l.d %2,%1\", operands);
4393 xoperands[0] = operands[0];
4394 xoperands[1] = operands[2];
4395 output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
4398 [(set_attr "type" "fcvt")
4399 (set_attr "mode" "DF")
4400 (set_attr "length" "8,4,8,12")])
4403 ;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
4404 ;;; but not in the chapter that describes the FPU. It is not mentioned at all
4405 ;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
4406 (define_insn "fix_truncsfdi2"
4407 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,*f,R,To")
4408 (fix:DI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
4409 (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
4410 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4415 if (which_alternative == 1)
4416 return \"trunc.l.s %0,%1\";
4418 output_asm_insn (\"trunc.l.s %2,%1\", operands);
4420 xoperands[0] = operands[0];
4421 xoperands[1] = operands[2];
4422 output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
4425 [(set_attr "type" "fcvt")
4426 (set_attr "mode" "SF")
4427 (set_attr "length" "8,4,8,12")])
4430 (define_insn "floatsidf2"
4431 [(set (match_operand:DF 0 "register_operand" "=f,f,f")
4432 (float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
4433 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4436 dslots_load_total++;
4437 if (GET_CODE (operands[1]) == MEM)
4438 return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\";
4440 return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\";
4442 [(set_attr "type" "fcvt")
4443 (set_attr "mode" "DF")
4444 (set_attr "length" "12,16,12")])
4447 (define_insn "floatdidf2"
4448 [(set (match_operand:DF 0 "register_operand" "=f,f,f")
4449 (float:DF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
4450 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4453 dslots_load_total++;
4454 if (GET_CODE (operands[1]) == MEM)
4455 return \"l.d\\t%0,%1%#\;cvt.d.l\\t%0,%0\";
4457 return \"dmtc1\\t%1,%0%#\;cvt.d.l\\t%0,%0\";
4459 [(set_attr "type" "fcvt")
4460 (set_attr "mode" "DF")
4461 (set_attr "length" "12,16,12")])
4464 (define_insn "floatsisf2"
4465 [(set (match_operand:SF 0 "register_operand" "=f,f,f")
4466 (float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
4470 dslots_load_total++;
4471 if (GET_CODE (operands[1]) == MEM)
4472 return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\";
4474 return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\";
4476 [(set_attr "type" "fcvt")
4477 (set_attr "mode" "SF")
4478 (set_attr "length" "12,16,12")])
4481 (define_insn "floatdisf2"
4482 [(set (match_operand:SF 0 "register_operand" "=f,f,f")
4483 (float:SF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
4484 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4487 dslots_load_total++;
4488 if (GET_CODE (operands[1]) == MEM)
4489 return \"l.d\\t%0,%1%#\;cvt.s.l\\t%0,%0\";
4491 return \"dmtc1\\t%1,%0%#\;cvt.s.l\\t%0,%0\";
4493 [(set_attr "type" "fcvt")
4494 (set_attr "mode" "SF")
4495 (set_attr "length" "12,16,12")])
4498 (define_expand "fixuns_truncdfsi2"
4499 [(set (match_operand:SI 0 "register_operand" "")
4500 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
4501 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4504 rtx reg1 = gen_reg_rtx (DFmode);
4505 rtx reg2 = gen_reg_rtx (DFmode);
4506 rtx reg3 = gen_reg_rtx (SImode);
4507 rtx label1 = gen_label_rtx ();
4508 rtx label2 = gen_label_rtx ();
4509 REAL_VALUE_TYPE offset;
4511 offset = REAL_VALUE_LDEXP (dconst1, 31);
4513 if (reg1) /* turn off complaints about unreached code */
4515 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
4516 do_pending_stack_adjust ();
4518 emit_insn (gen_cmpdf (operands[1], reg1));
4519 emit_jump_insn (gen_bge (label1));
4521 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
4522 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4523 gen_rtx_LABEL_REF (VOIDmode, label2)));
4526 emit_label (label1);
4527 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
4528 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
4529 (BITMASK_HIGH, SImode)));
4531 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
4532 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
4534 emit_label (label2);
4536 /* allow REG_NOTES to be set on last insn (labels don't have enough
4537 fields, and can't be used for REG_NOTES anyway). */
4538 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4544 (define_expand "fixuns_truncdfdi2"
4545 [(set (match_operand:DI 0 "register_operand" "")
4546 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
4547 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4550 rtx reg1 = gen_reg_rtx (DFmode);
4551 rtx reg2 = gen_reg_rtx (DFmode);
4552 rtx reg3 = gen_reg_rtx (DImode);
4553 rtx label1 = gen_label_rtx ();
4554 rtx label2 = gen_label_rtx ();
4555 REAL_VALUE_TYPE offset;
4557 offset = REAL_VALUE_LDEXP (dconst1, 63);
4559 if (reg1) /* turn off complaints about unreached code */
4561 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
4562 do_pending_stack_adjust ();
4564 emit_insn (gen_cmpdf (operands[1], reg1));
4565 emit_jump_insn (gen_bge (label1));
4567 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
4568 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4569 gen_rtx_LABEL_REF (VOIDmode, label2)));
4572 emit_label (label1);
4573 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
4574 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
4575 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
4577 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
4578 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
4580 emit_label (label2);
4582 /* allow REG_NOTES to be set on last insn (labels don't have enough
4583 fields, and can't be used for REG_NOTES anyway). */
4584 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4590 (define_expand "fixuns_truncsfsi2"
4591 [(set (match_operand:SI 0 "register_operand" "")
4592 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
4596 rtx reg1 = gen_reg_rtx (SFmode);
4597 rtx reg2 = gen_reg_rtx (SFmode);
4598 rtx reg3 = gen_reg_rtx (SImode);
4599 rtx label1 = gen_label_rtx ();
4600 rtx label2 = gen_label_rtx ();
4601 REAL_VALUE_TYPE offset;
4603 offset = REAL_VALUE_LDEXP (dconst1, 31);
4605 if (reg1) /* turn off complaints about unreached code */
4607 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
4608 do_pending_stack_adjust ();
4610 emit_insn (gen_cmpsf (operands[1], reg1));
4611 emit_jump_insn (gen_bge (label1));
4613 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
4614 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4615 gen_rtx_LABEL_REF (VOIDmode, label2)));
4618 emit_label (label1);
4619 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
4620 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
4621 (BITMASK_HIGH, SImode)));
4623 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
4624 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
4626 emit_label (label2);
4628 /* allow REG_NOTES to be set on last insn (labels don't have enough
4629 fields, and can't be used for REG_NOTES anyway). */
4630 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4636 (define_expand "fixuns_truncsfdi2"
4637 [(set (match_operand:DI 0 "register_operand" "")
4638 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
4639 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
4642 rtx reg1 = gen_reg_rtx (SFmode);
4643 rtx reg2 = gen_reg_rtx (SFmode);
4644 rtx reg3 = gen_reg_rtx (DImode);
4645 rtx label1 = gen_label_rtx ();
4646 rtx label2 = gen_label_rtx ();
4647 REAL_VALUE_TYPE offset;
4649 offset = REAL_VALUE_LDEXP (dconst1, 63);
4651 if (reg1) /* turn off complaints about unreached code */
4653 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
4654 do_pending_stack_adjust ();
4656 emit_insn (gen_cmpsf (operands[1], reg1));
4657 emit_jump_insn (gen_bge (label1));
4659 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
4660 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4661 gen_rtx_LABEL_REF (VOIDmode, label2)));
4664 emit_label (label1);
4665 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
4666 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
4667 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
4669 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
4670 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
4672 emit_label (label2);
4674 /* allow REG_NOTES to be set on last insn (labels don't have enough
4675 fields, and can't be used for REG_NOTES anyway). */
4676 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4683 ;; ....................
4687 ;; ....................
4689 ;; Bit field extract patterns which use lwl/lwr.
4691 ;; ??? There could be HImode variants for the ulh/ulhu/ush macros.
4692 ;; It isn't clear whether this will give better code.
4694 ;; Only specify the mode operand 1, the rest are assumed to be word_mode.
4695 (define_expand "extv"
4696 [(set (match_operand 0 "register_operand" "")
4697 (sign_extract (match_operand:QI 1 "memory_operand" "")
4698 (match_operand 2 "immediate_operand" "")
4699 (match_operand 3 "immediate_operand" "")))]
4703 /* If the field does not start on a byte boundary, then fail. */
4704 if (INTVAL (operands[3]) % 8 != 0)
4707 /* MIPS I and MIPS II can only handle a 32bit field. */
4708 if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
4711 /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
4713 && INTVAL (operands[2]) != 64
4714 && INTVAL (operands[2]) != 32)
4717 /* This can happen for a 64 bit target, when extracting a value from
4718 a 64 bit union member. extract_bit_field doesn't verify that our
4719 source matches the predicate, so we force it to be a MEM here. */
4720 if (GET_CODE (operands[1]) != MEM)
4723 /* Change the mode to BLKmode for aliasing purposes. */
4724 operands[1] = adjust_address (operands[1], BLKmode, 0);
4726 /* Otherwise, emit a l[wd]l/l[wd]r pair to load the value. */
4727 if (INTVAL (operands[2]) == 64)
4728 emit_insn (gen_movdi_uld (operands[0], operands[1]));
4733 operands[0] = gen_lowpart (SImode, operands[0]);
4734 if (operands[0] == NULL_RTX)
4737 emit_insn (gen_movsi_ulw (operands[0], operands[1]));
4742 ;; Only specify the mode operand 1, the rest are assumed to be word_mode.
4743 (define_expand "extzv"
4744 [(set (match_operand 0 "register_operand" "")
4745 (zero_extract (match_operand:QI 1 "memory_operand" "")
4746 (match_operand 2 "immediate_operand" "")
4747 (match_operand 3 "immediate_operand" "")))]
4751 /* If the field does not start on a byte boundary, then fail. */
4752 if (INTVAL (operands[3]) % 8 != 0)
4755 /* MIPS I and MIPS II can only handle a 32bit field. */
4756 if (!TARGET_64BIT && INTVAL (operands[2]) != 32)
4759 /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
4761 && INTVAL (operands[2]) != 64
4762 && INTVAL (operands[2]) != 32)
4765 /* This can happen for a 64 bit target, when extracting a value from
4766 a 64 bit union member. extract_bit_field doesn't verify that our
4767 source matches the predicate, so we force it to be a MEM here. */
4768 if (GET_CODE (operands[1]) != MEM)
4771 /* Change the mode to BLKmode for aliasing purposes. */
4772 operands[1] = adjust_address (operands[1], BLKmode, 0);
4774 /* Otherwise, emit a lwl/lwr pair to load the value. */
4775 if (INTVAL (operands[2]) == 64)
4776 emit_insn (gen_movdi_uld (operands[0], operands[1]));
4781 operands[0] = gen_lowpart (SImode, operands[0]);
4782 if (operands[0] == NULL_RTX)
4785 emit_insn (gen_movsi_ulw (operands[0], operands[1]));
4790 ;; Only specify the mode operands 0, the rest are assumed to be word_mode.
4791 (define_expand "insv"
4792 [(set (zero_extract (match_operand:QI 0 "memory_operand" "")
4793 (match_operand 1 "immediate_operand" "")
4794 (match_operand 2 "immediate_operand" ""))
4795 (match_operand 3 "register_operand" ""))]
4799 /* If the field does not start on a byte boundary, then fail. */
4800 if (INTVAL (operands[2]) % 8 != 0)
4803 /* MIPS I and MIPS II can only handle a 32bit field. */
4804 if (!TARGET_64BIT && INTVAL (operands[1]) != 32)
4807 /* MIPS III and MIPS IV can handle both 32bit and 64bit fields. */
4809 && INTVAL (operands[1]) != 64
4810 && INTVAL (operands[1]) != 32)
4813 /* This can happen for a 64 bit target, when storing into a 32 bit union
4814 member. store_bit_field doesn't verify that our target matches the
4815 predicate, so we force it to be a MEM here. */
4816 if (GET_CODE (operands[0]) != MEM)
4819 /* Change the mode to BLKmode for aliasing purposes. */
4820 operands[0] = adjust_address (operands[0], BLKmode, 0);
4822 /* Otherwise, emit a s[wd]l/s[wd]r pair to load the value. */
4823 if (INTVAL (operands[1]) == 64)
4824 emit_insn (gen_movdi_usd (operands[0], operands[3]));
4829 operands[3] = gen_lowpart (SImode, operands[3]);
4830 if (operands[3] == NULL_RTX)
4833 emit_insn (gen_movsi_usw (operands[0], operands[3]));
4838 ;; unaligned word moves generated by the bit field patterns
4840 (define_insn "movsi_ulw"
4841 [(set (match_operand:SI 0 "register_operand" "=&d,&d")
4842 (unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")]
4847 rtx offset = const0_rtx;
4848 rtx addr = XEXP (operands[1], 0);
4849 rtx mem_addr = eliminate_constant_term (addr, &offset);
4853 mips_count_memory_refs (operands[1], 2);
4855 /* The stack/frame pointers are always aligned, so we can convert
4856 to the faster lw if we are referencing an aligned stack location. */
4858 if ((INTVAL (offset) & 3) == 0
4859 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
4860 ret = \"lw\\t%0,%1\";
4862 ret = \"ulw\\t%0,%1\";
4864 return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
4866 [(set_attr "type" "load,load")
4867 (set_attr "mode" "SI")
4868 (set_attr "length" "8,16")])
4870 (define_insn "movsi_usw"
4871 [(set (match_operand:BLK 0 "memory_operand" "=R,o")
4872 (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")]
4877 rtx offset = const0_rtx;
4878 rtx addr = XEXP (operands[0], 0);
4879 rtx mem_addr = eliminate_constant_term (addr, &offset);
4882 mips_count_memory_refs (operands[0], 2);
4884 /* The stack/frame pointers are always aligned, so we can convert
4885 to the faster sw if we are referencing an aligned stack location. */
4887 if ((INTVAL (offset) & 3) == 0
4888 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
4889 return \"sw\\t%z1,%0\";
4891 return \"usw\\t%z1,%0\";
4893 [(set_attr "type" "store")
4894 (set_attr "mode" "SI")
4895 (set_attr "length" "8,16")])
4897 ;; Bit field extract patterns which use ldl/ldr.
4899 ;; unaligned double word moves generated by the bit field patterns
4901 (define_insn "movdi_uld"
4902 [(set (match_operand:DI 0 "register_operand" "=&d,&d")
4903 (unspec:DI [(match_operand:BLK 1 "general_operand" "R,o")]
4908 rtx offset = const0_rtx;
4909 rtx addr = XEXP (operands[1], 0);
4910 rtx mem_addr = eliminate_constant_term (addr, &offset);
4914 mips_count_memory_refs (operands[1], 2);
4916 /* The stack/frame pointers are always aligned, so we can convert
4917 to the faster lw if we are referencing an aligned stack location. */
4919 if ((INTVAL (offset) & 7) == 0
4920 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
4921 ret = \"ld\\t%0,%1\";
4923 ret = \"uld\\t%0,%1\";
4925 return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
4927 [(set_attr "type" "load,load")
4928 (set_attr "mode" "SI")
4929 (set_attr "length" "8,16")])
4931 (define_insn "movdi_usd"
4932 [(set (match_operand:BLK 0 "memory_operand" "=R,o")
4933 (unspec:BLK [(match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")]
4938 rtx offset = const0_rtx;
4939 rtx addr = XEXP (operands[0], 0);
4940 rtx mem_addr = eliminate_constant_term (addr, &offset);
4943 mips_count_memory_refs (operands[0], 2);
4945 /* The stack/frame pointers are always aligned, so we can convert
4946 to the faster sw if we are referencing an aligned stack location. */
4948 if ((INTVAL (offset) & 7) == 0
4949 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
4950 return \"sd\\t%z1,%0\";
4952 return \"usd\\t%z1,%0\";
4954 [(set_attr "type" "store")
4955 (set_attr "mode" "SI")
4956 (set_attr "length" "8,16")])
4958 ;; These two patterns support loading addresses with two instructions instead
4959 ;; of using the macro instruction la.
4961 ;; ??? mips_move_1word has support for HIGH, so this pattern may be
4965 [(set (match_operand:SI 0 "register_operand" "=r")
4966 (high:SI (match_operand:SI 1 "immediate_operand" "")))]
4967 "mips_split_addresses && !TARGET_MIPS16"
4968 "lui\\t%0,%%hi(%1) # high"
4969 [(set_attr "type" "move")])
4972 [(set (match_operand:SI 0 "register_operand" "=r")
4973 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
4974 (match_operand:SI 2 "immediate_operand" "")))]
4975 "mips_split_addresses && !TARGET_MIPS16"
4976 "addiu\\t%0,%1,%%lo(%2) # low"
4977 [(set_attr "type" "arith")
4978 (set_attr "mode" "SI")])
4980 ;; 64-bit integer moves
4982 ;; Unlike most other insns, the move insns can't be split with
4983 ;; different predicates, because register spilling and other parts of
4984 ;; the compiler, have memoized the insn number already.
4986 (define_expand "movdi"
4987 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4988 (match_operand:DI 1 "general_operand" ""))]
4992 if (mips_split_addresses && mips_check_split (operands[1], DImode))
4994 enum machine_mode mode = GET_MODE (operands[0]);
4995 rtx tem = ((reload_in_progress | reload_completed)
4996 ? operands[0] : gen_reg_rtx (mode));
4998 emit_insn (gen_rtx_SET (VOIDmode, tem,
4999 gen_rtx_HIGH (mode, operands[1])));
5001 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
5004 /* If we are generating embedded PIC code, and we are referring to a
5005 symbol in the .text section, we must use an offset from the start
5007 if (TARGET_EMBEDDED_PIC
5008 && (GET_CODE (operands[1]) == LABEL_REF
5009 || (GET_CODE (operands[1]) == SYMBOL_REF
5010 && ! SYMBOL_REF_FLAG (operands[1]))))
5014 temp = embedded_pic_offset (operands[1]);
5015 temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_reg (),
5016 force_reg (DImode, temp));
5017 emit_move_insn (operands[0], force_reg (DImode, temp));
5021 /* If operands[1] is a constant address illegal for pic, then we need to
5022 handle it just like LEGITIMIZE_ADDRESS does. */
5023 if (flag_pic && pic_address_needs_scratch (operands[1]))
5025 rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
5026 rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
5028 if (! SMALL_INT (temp2))
5029 temp2 = force_reg (DImode, temp2);
5031 emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2));
5035 /* On the mips16, we can handle a GP relative reference by adding in
5036 $gp. We need to check the name to see whether this is a string
5039 && register_operand (operands[0], DImode)
5040 && GET_CODE (operands[1]) == SYMBOL_REF
5041 && SYMBOL_REF_FLAG (operands[1]))
5043 const char *name = XSTR (operands[1], 0);
5046 || strncmp (name + 1, LOCAL_LABEL_PREFIX,
5047 sizeof LOCAL_LABEL_PREFIX - 1) != 0)
5051 if (reload_in_progress || reload_completed)
5053 /* In movsi we use the constant table here. However, in
5054 this case, we're better off copying $28 into a
5055 register and adding, because the constant table entry
5056 would be 8 bytes. */
5057 base_reg = operands[0];
5058 emit_move_insn (base_reg,
5059 gen_rtx (CONST, DImode,
5060 gen_rtx (REG, DImode,
5061 GP_REG_FIRST + 28)));
5065 base_reg = gen_reg_rtx (Pmode);
5066 emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
5069 emit_move_insn (operands[0],
5070 gen_rtx (PLUS, Pmode, base_reg,
5071 mips16_gp_offset (operands[1])));
5076 if ((reload_in_progress | reload_completed) == 0
5077 && !register_operand (operands[0], DImode)
5078 && !register_operand (operands[1], DImode)
5080 || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
5081 && operands[1] != CONST0_RTX (DImode))))
5083 rtx temp = force_reg (DImode, operands[1]);
5084 emit_move_insn (operands[0], temp);
5089 ;; For mips16, we need a special case to handle storing $31 into
5090 ;; memory, since we don't have a constraint to match $31. This
5091 ;; instruction can be generated by save_restore_insns.
5094 [(set (match_operand:DI 0 "memory_operand" "=R,m")
5096 "TARGET_MIPS16 && TARGET_64BIT"
5099 operands[1] = gen_rtx (REG, DImode, 31);
5100 return mips_move_2words (operands, insn);
5102 [(set_attr "type" "store")
5103 (set_attr "mode" "DI")
5104 (set_attr "length" "4,8")])
5106 (define_insn "movdi_internal"
5107 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x,*d,*x,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
5108 (match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,J,*x,*d,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
5109 "!TARGET_64BIT && !TARGET_MIPS16
5110 && (register_operand (operands[0], DImode)
5111 || register_operand (operands[1], DImode)
5112 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
5113 || operands[1] == CONST0_RTX (DImode))"
5114 "* return mips_move_2words (operands, insn); "
5115 [(set_attr "type" "move,arith,load,load,store,store,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
5116 (set_attr "mode" "DI")
5117 (set_attr "length" "8,16,8,16,8,16,8,8,8,8,8,8,8,8,8")])
5120 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,To,*d")
5121 (match_operand:DI 1 "general_operand" "d,d,y,K,N,R,To,d,d,*x"))]
5122 "!TARGET_64BIT && TARGET_MIPS16
5123 && (register_operand (operands[0], DImode)
5124 || register_operand (operands[1], DImode))"
5125 "* return mips_move_2words (operands, insn);"
5126 [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
5127 (set_attr "mode" "DI")
5128 (set_attr "length" "8,8,8,8,12,8,16,8,16,8")])
5131 [(set (match_operand:DI 0 "register_operand" "")
5132 (match_operand:DI 1 "register_operand" ""))]
5133 "reload_completed && !TARGET_64BIT
5134 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
5135 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
5136 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
5138 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
5139 (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
5142 (define_insn "movdi_internal2"
5143 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m,*x,*d,*x,*a,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
5144 (match_operand:DI 1 "movdi_operand" "d,IKL,Mnis,R,m,dJ,dJ,J,*x,*d,*J,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
5145 "TARGET_64BIT && !TARGET_MIPS16
5146 && (register_operand (operands[0], DImode)
5147 || se_register_operand (operands[1], DImode)
5148 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
5149 || operands[1] == CONST0_RTX (DImode))"
5150 "* return mips_move_2words (operands, insn); "
5151 [(set_attr "type" "move,arith,arith,load,load,store,store,hilo,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
5152 (set_attr "mode" "DI")
5153 (set_attr "length" "4,4,8,4,8,4,8,4,4,4,8,8,8,8,8,8,8")])
5156 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,R,m,*d")
5157 (match_operand:DI 1 "movdi_operand" "d,d,y,K,N,s,R,m,d,d,*x"))]
5158 "TARGET_64BIT && TARGET_MIPS16
5159 && (register_operand (operands[0], DImode)
5160 || se_register_operand (operands[1], DImode))"
5161 "* return mips_move_2words (operands, insn);"
5162 [(set_attr "type" "move,move,move,arith,arith,arith,load,load,store,store,hilo")
5163 (set_attr "mode" "DI")
5164 (set_attr_alternative "length"
5168 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
5171 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
5174 (if_then_else (match_operand:VOID 1 "m16_usym5_4" "")
5183 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
5184 ;; when the original load is a 4 byte instruction but the add and the
5185 ;; load are 2 2 byte instructions.
5188 [(set (match_operand:DI 0 "register_operand" "")
5189 (mem:DI (plus:DI (match_dup 0)
5190 (match_operand:DI 1 "const_int_operand" ""))))]
5191 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
5192 && !TARGET_DEBUG_D_MODE
5193 && GET_CODE (operands[0]) == REG
5194 && M16_REG_P (REGNO (operands[0]))
5195 && GET_CODE (operands[1]) == CONST_INT
5196 && ((INTVAL (operands[1]) < 0
5197 && INTVAL (operands[1]) >= -0x10)
5198 || (INTVAL (operands[1]) >= 32 * 8
5199 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
5200 || (INTVAL (operands[1]) >= 0
5201 && INTVAL (operands[1]) < 32 * 8
5202 && (INTVAL (operands[1]) & 7) != 0))"
5203 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
5204 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
5207 HOST_WIDE_INT val = INTVAL (operands[1]);
5210 operands[2] = GEN_INT (0);
5211 else if (val >= 32 * 8)
5215 operands[1] = GEN_INT (0x8 + off);
5216 operands[2] = GEN_INT (val - off - 0x8);
5222 operands[1] = GEN_INT (off);
5223 operands[2] = GEN_INT (val - off);
5227 ;; Handle input reloads in DImode.
5228 ;; This is mainly to handle reloading HILO_REGNUM. Note that we may
5229 ;; see it as the source or the destination, depending upon which way
5230 ;; reload handles the instruction.
5231 ;; Making the second operand TImode is a trick. The compiler may
5232 ;; reuse the same register for operand 0 and operand 2. Using TImode
5233 ;; gives us two registers, so we can always use the one which is not
5236 (define_expand "reload_indi"
5237 [(set (match_operand:DI 0 "register_operand" "=b")
5238 (match_operand:DI 1 "" "b"))
5239 (clobber (match_operand:TI 2 "register_operand" "=&d"))]
5243 rtx scratch = gen_rtx_REG (DImode,
5244 (REGNO (operands[0]) == REGNO (operands[2])
5245 ? REGNO (operands[2]) + 1
5246 : REGNO (operands[2])));
5248 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
5250 if (GET_CODE (operands[1]) == MEM)
5252 rtx memword, offword, hi_word, lo_word;
5253 rtx addr = find_replacement (&XEXP (operands[1], 0));
5254 rtx op1 = replace_equiv_address (operands[1], addr);
5256 scratch = gen_rtx_REG (SImode, REGNO (scratch));
5257 memword = adjust_address (op1, SImode, 0);
5258 offword = adjust_address (op1, SImode, 4);
5260 if (BYTES_BIG_ENDIAN)
5270 emit_move_insn (scratch, hi_word);
5271 emit_move_insn (gen_rtx_REG (SImode, 64), scratch);
5272 emit_move_insn (scratch, lo_word);
5273 emit_move_insn (gen_rtx (REG, SImode, 65), scratch);
5274 emit_insn (gen_hilo_delay (operands[0]));
5278 emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
5279 emit_insn (gen_movdi (gen_rtx_REG (DImode, 64), scratch));
5280 emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
5281 emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
5282 emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
5283 emit_insn (gen_hilo_delay (operands[0]));
5287 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
5289 emit_insn (gen_movdi (scratch, gen_rtx_REG (DImode, 65)));
5290 emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
5291 emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
5292 emit_insn (gen_movdi (operands[0], gen_rtx_REG (DImode, 64)));
5293 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5294 emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
5295 emit_insn (gen_hilo_delay (operands[1]));
5298 /* This handles moves between a float register and HI/LO. */
5299 emit_move_insn (scratch, operands[1]);
5300 emit_move_insn (operands[0], scratch);
5304 ;; Handle output reloads in DImode.
5306 ;; Reloading HILO_REG in MIPS16 mode requires two scratch registers, so we
5307 ;; use a TImode scratch reg.
5309 (define_expand "reload_outdi"
5310 [(set (match_operand:DI 0 "general_operand" "=b")
5311 (match_operand:DI 1 "se_register_operand" "b"))
5312 (clobber (match_operand:TI 2 "register_operand" "=&d"))]
5316 rtx scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
5318 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
5320 emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
5321 emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch));
5322 emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
5323 emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
5324 emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
5325 emit_insn (gen_hilo_delay (operands[0]));
5328 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
5330 if (GET_CODE (operands[0]) == MEM)
5332 rtx scratch, memword, offword, hi_word, lo_word;
5333 rtx addr = find_replacement (&XEXP (operands[0], 0));
5334 rtx op0 = replace_equiv_address (operands[0], addr);
5336 scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
5337 memword = adjust_address (op0, SImode, 0);
5338 offword = adjust_address (op0, SImode, 4);
5340 if (BYTES_BIG_ENDIAN)
5350 emit_move_insn (scratch, gen_rtx_REG (SImode, 64));
5351 emit_move_insn (hi_word, scratch);
5352 emit_move_insn (scratch, gen_rtx_REG (SImode, 65));
5353 emit_move_insn (lo_word, scratch);
5354 emit_insn (gen_hilo_delay (operands[1]));
5356 else if (TARGET_MIPS16 && ! M16_REG_P (REGNO (operands[0])))
5358 /* Handle the case where operand[0] is not a 'd' register,
5359 and hence we can not directly move from the HILO register
5361 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5362 emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
5363 emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
5364 emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
5365 emit_insn (gen_movdi (scratch2, gen_rtx (REG, DImode, 64)));
5366 emit_insn (gen_ashldi3 (scratch2, scratch2, GEN_INT (32)));
5367 emit_insn (gen_iordi3 (scratch, scratch, scratch2));
5368 emit_insn (gen_movdi (operands[0], scratch));
5369 emit_insn (gen_hilo_delay (operands[1]));
5373 emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
5374 emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
5375 emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
5376 emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
5377 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5378 emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
5379 emit_insn (gen_hilo_delay (operands[1]));
5383 /* This handles moves between a float register and HI/LO. */
5384 emit_move_insn (scratch, operands[1]);
5385 emit_move_insn (operands[0], scratch);
5389 ;; 32-bit Integer moves
5392 [(set (match_operand:SI 0 "register_operand" "")
5393 (match_operand:SI 1 "large_int" ""))]
5394 "!TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
5398 (ior:SI (match_dup 0)
5402 operands[2] = GEN_INT (trunc_int_for_mode (INTVAL (operands[1])
5405 operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
5408 ;; Unlike most other insns, the move insns can't be split with
5409 ;; different predicates, because register spilling and other parts of
5410 ;; the compiler, have memoized the insn number already.
5412 (define_expand "movsi"
5413 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5414 (match_operand:SI 1 "general_operand" ""))]
5418 if (mips_split_addresses && mips_check_split (operands[1], SImode))
5420 enum machine_mode mode = GET_MODE (operands[0]);
5421 rtx tem = ((reload_in_progress | reload_completed)
5422 ? operands[0] : gen_reg_rtx (mode));
5424 emit_insn (gen_rtx_SET (VOIDmode, tem,
5425 gen_rtx_HIGH (mode, operands[1])));
5427 operands[1] = gen_rtx_LO_SUM (mode, tem, operands[1]);
5430 /* If we are generating embedded PIC code, and we are referring to a
5431 symbol in the .text section, we must use an offset from the start
5433 if (TARGET_EMBEDDED_PIC
5434 && (GET_CODE (operands[1]) == LABEL_REF
5435 || (GET_CODE (operands[1]) == SYMBOL_REF
5436 && ! SYMBOL_REF_FLAG (operands[1]))))
5440 temp = embedded_pic_offset (operands[1]);
5441 temp = gen_rtx_PLUS (Pmode, embedded_pic_fnaddr_reg (),
5442 force_reg (SImode, temp));
5443 emit_move_insn (operands[0], force_reg (SImode, temp));
5447 /* If operands[1] is a constant address invalid for pic, then we need to
5448 handle it just like LEGITIMIZE_ADDRESS does. */
5449 if (flag_pic && pic_address_needs_scratch (operands[1]))
5451 rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0));
5452 rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
5454 if (! SMALL_INT (temp2))
5455 temp2 = force_reg (SImode, temp2);
5457 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, temp2));
5461 /* On the mips16, we can handle a GP relative reference by adding in
5462 $gp. We need to check the name to see whether this is a string
5465 && register_operand (operands[0], SImode)
5466 && GET_CODE (operands[1]) == SYMBOL_REF
5467 && SYMBOL_REF_FLAG (operands[1]))
5469 const char *name = XSTR (operands[1], 0);
5472 || strncmp (name + 1, LOCAL_LABEL_PREFIX,
5473 sizeof LOCAL_LABEL_PREFIX - 1) != 0)
5477 if (reload_in_progress || reload_completed)
5479 /* We need to reload this address. In this case we
5480 aren't going to have a chance to combine loading the
5481 address with the load or store. That means that we
5482 can either generate a 2 byte move followed by a 4
5483 byte addition, or a 2 byte load with a 4 byte entry
5484 in the constant table. Since the entry in the
5485 constant table might be shared, we're better off, on
5486 average, loading the address from the constant table. */
5487 emit_move_insn (operands[0],
5488 force_const_mem (SImode, operands[1]));
5492 base_reg = gen_reg_rtx (Pmode);
5493 emit_move_insn (base_reg, mips16_gp_pseudo_reg ());
5495 emit_move_insn (operands[0],
5496 gen_rtx (PLUS, Pmode, base_reg,
5497 mips16_gp_offset (operands[1])));
5502 if ((reload_in_progress | reload_completed) == 0
5503 && !register_operand (operands[0], SImode)
5504 && !register_operand (operands[1], SImode)
5506 || GET_CODE (operands[1]) != CONST_INT
5507 || INTVAL (operands[1]) != 0))
5509 rtx temp = force_reg (SImode, operands[1]);
5510 emit_move_insn (operands[0], temp);
5515 ;; We can only store $ra directly into a small sp offset. Should the
5516 ;; offset be too wide, non-constant or not sp-based, leave it up to
5517 ;; reload to choose a scratch register.
5520 [(set (mem:SI (plus:SI (reg:SI 29)
5521 (match_operand:SI 0 "small_int" "n")))
5525 [(set_attr "type" "store")
5526 (set_attr "mode" "SI")
5527 (set_attr_alternative
5530 (lt (symbol_ref "(unsigned HOST_WIDE_INT) INTVAL (operands[0])")
5535 ;; The difference between these two is whether or not ints are allowed
5536 ;; in FP registers (off by default, use -mdebugh to enable).
5538 (define_insn "movsi_internal1"
5539 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*x,*d,*d,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
5540 (match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x,*a,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
5541 "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
5542 && (register_operand (operands[0], SImode)
5543 || register_operand (operands[1], SImode)
5544 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
5545 "* return mips_move_1word (operands, insn, FALSE);"
5546 [(set_attr "type" "move,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
5547 (set_attr "mode" "SI")
5548 (set_attr "length" "4,4,8,4,8,4,8,4,4,4,4,8,4,8,4,4,4,4,4,4,8,4,4,8")])
5550 (define_insn "movsi_internal2"
5551 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d,*B*C*D,*B*C*D,*B*C*D,*d,*m,*R")
5552 (match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a,*d,*m,*R,*B*C*D,*B*C*D,*B*C*D"))]
5553 "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
5554 && (register_operand (operands[0], SImode)
5555 || register_operand (operands[1], SImode)
5556 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
5557 "* return mips_move_1word (operands, insn, FALSE);"
5558 [(set_attr "type" "move,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo,xfer,load,load,xfer,store,store")
5559 (set_attr "mode" "SI")
5560 (set_attr "length" "4,4,8,4,8,4,8,4,4,4,4,4,4,4,4,8,4,4,8")])
5562 ;; This is the mips16 movsi instruction. We accept a small integer as
5563 ;; the source if the destination is a GP memory reference. This is
5564 ;; because we want the combine pass to turn adding a GP reference to a
5565 ;; register into a direct GP reference, but the combine pass will pass
5566 ;; in the source as a constant if it finds an equivalent one. If the
5567 ;; instruction is recognized, reload will force the constant back out
5571 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,R,m,*d,*d")
5572 (match_operand:SI 1 "move_operand" "d,d,y,K,N,s,R,m,d,d,*x,*a"))]
5574 && (register_operand (operands[0], SImode)
5575 || register_operand (operands[1], SImode)
5576 || (GET_CODE (operands[0]) == MEM
5577 && GET_CODE (XEXP (operands[0], 0)) == PLUS
5578 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST
5579 && mips16_gp_offset_p (XEXP (XEXP (operands[0], 0), 1))
5580 && GET_CODE (operands[1]) == CONST_INT
5581 && (SMALL_INT (operands[1])
5582 || SMALL_INT_UNSIGNED (operands[1]))))"
5583 "* return mips_move_1word (operands, insn, FALSE);"
5584 [(set_attr "type" "move,move,move,arith,arith,arith,load,load,store,store,hilo,hilo")
5585 (set_attr "mode" "SI")
5586 (set_attr_alternative "length"
5590 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
5593 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
5596 (if_then_else (match_operand:VOID 1 "m16_usym8_4" "")
5606 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
5607 ;; when the original load is a 4 byte instruction but the add and the
5608 ;; load are 2 2 byte instructions.
5611 [(set (match_operand:SI 0 "register_operand" "")
5612 (mem:SI (plus:SI (match_dup 0)
5613 (match_operand:SI 1 "const_int_operand" ""))))]
5614 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5615 && GET_CODE (operands[0]) == REG
5616 && M16_REG_P (REGNO (operands[0]))
5617 && GET_CODE (operands[1]) == CONST_INT
5618 && ((INTVAL (operands[1]) < 0
5619 && INTVAL (operands[1]) >= -0x80)
5620 || (INTVAL (operands[1]) >= 32 * 4
5621 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
5622 || (INTVAL (operands[1]) >= 0
5623 && INTVAL (operands[1]) < 32 * 4
5624 && (INTVAL (operands[1]) & 3) != 0))"
5625 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
5626 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
5629 HOST_WIDE_INT val = INTVAL (operands[1]);
5632 operands[2] = GEN_INT (0);
5633 else if (val >= 32 * 4)
5637 operands[1] = GEN_INT (0x7c + off);
5638 operands[2] = GEN_INT (val - off - 0x7c);
5644 operands[1] = GEN_INT (off);
5645 operands[2] = GEN_INT (val - off);
5649 ;; On the mips16, we can split a load of certain constants into a load
5650 ;; and an add. This turns a 4 byte instruction into 2 2 byte
5654 [(set (match_operand:SI 0 "register_operand" "")
5655 (match_operand:SI 1 "const_int_operand" ""))]
5656 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5657 && GET_CODE (operands[0]) == REG
5658 && M16_REG_P (REGNO (operands[0]))
5659 && GET_CODE (operands[1]) == CONST_INT
5660 && INTVAL (operands[1]) >= 0x100
5661 && INTVAL (operands[1]) <= 0xff + 0x7f"
5662 [(set (match_dup 0) (match_dup 1))
5663 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
5666 int val = INTVAL (operands[1]);
5668 operands[1] = GEN_INT (0xff);
5669 operands[2] = GEN_INT (val - 0xff);
5672 ;; On the mips16, we can split a load of a negative constant into a
5673 ;; load and a neg. That's what mips_move_1word will generate anyhow.
5676 [(set (match_operand:SI 0 "register_operand" "")
5677 (match_operand:SI 1 "const_int_operand" ""))]
5678 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
5679 && GET_CODE (operands[0]) == REG
5680 && M16_REG_P (REGNO (operands[0]))
5681 && GET_CODE (operands[1]) == CONST_INT
5682 && INTVAL (operands[1]) < 0
5683 && INTVAL (operands[1]) > - 0x8000"
5684 [(set (match_dup 0) (match_dup 1))
5685 (set (match_dup 0) (neg:SI (match_dup 0)))]
5688 operands[1] = GEN_INT (- INTVAL (operands[1]));
5691 ;; Reload HILO_REGNUM in SI mode. This needs a scratch register in
5692 ;; order to set the sign bit correctly in the HI register.
5694 (define_expand "reload_outsi"
5695 [(set (match_operand:SI 0 "general_operand" "=b")
5696 (match_operand:SI 1 "register_operand" "b"))
5697 (clobber (match_operand:SI 2 "register_operand" "=&d"))]
5698 "TARGET_64BIT || TARGET_MIPS16"
5702 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
5704 emit_insn (gen_movsi (gen_rtx_REG (SImode, 65), operands[1]));
5705 emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31)));
5706 emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2]));
5707 emit_insn (gen_hilo_delay (operands[0]));
5710 /* Use a mult to reload LO on mips16. ??? This is hideous. */
5712 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
5714 emit_insn (gen_movsi (operands[2], GEN_INT (1)));
5715 /* This is gen_mulsi3_internal, but we need to fill in the
5716 scratch registers. */
5717 emit_insn (gen_rtx (PARALLEL, VOIDmode,
5719 gen_rtx (SET, VOIDmode,
5721 gen_rtx (MULT, SImode,
5724 gen_rtx (CLOBBER, VOIDmode,
5725 gen_rtx (REG, SImode, 64)),
5726 gen_rtx (CLOBBER, VOIDmode,
5727 gen_rtx (REG, SImode, 66)))));
5730 /* FIXME: I don't know how to get a value into the HI register. */
5731 if (GET_CODE (operands[0]) == REG
5732 && (TARGET_MIPS16 ? M16_REG_P (REGNO (operands[0]))
5733 : GP_REG_P (REGNO (operands[0]))))
5735 emit_move_insn (operands[0], operands[1]);
5738 /* This handles moves between a float register and HI/LO. */
5739 emit_move_insn (operands[2], operands[1]);
5740 emit_move_insn (operands[0], operands[2]);
5744 ;; Reload a value into HI or LO. There is no mthi or mtlo on mips16,
5745 ;; so we use a mult. ??? This is hideous, and we ought to figure out
5746 ;; something better.
5748 ;; We use no predicate for operand1, because it may be a PLUS, and there
5749 ;; is no convenient predicate for that.
5751 (define_expand "reload_insi"
5752 [(set (match_operand:SI 0 "register_operand" "=b")
5753 (match_operand:SI 1 "" "b"))
5754 (clobber (match_operand:SI 2 "register_operand" "=&d"))]
5759 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) == LO_REGNUM)
5761 emit_insn (gen_movsi (operands[2], GEN_INT (1)));
5762 /* This is gen_mulsi3_internal, but we need to fill in the
5763 scratch registers. */
5764 emit_insn (gen_rtx (PARALLEL, VOIDmode,
5766 gen_rtx (SET, VOIDmode,
5768 gen_rtx (MULT, SImode,
5771 gen_rtx (CLOBBER, VOIDmode,
5772 gen_rtx (REG, SImode, 64)),
5773 gen_rtx (CLOBBER, VOIDmode,
5774 gen_rtx (REG, SImode, 66)))));
5778 /* If this is a plus, then this must be an add of the stack pointer against
5779 either a hard register or a pseudo. */
5780 if (TARGET_MIPS16 && GET_CODE (operands[1]) == PLUS)
5784 if (XEXP (operands[1], 0) == stack_pointer_rtx)
5785 plus_op = XEXP (operands[1], 1);
5786 else if (XEXP (operands[1], 1) == stack_pointer_rtx)
5787 plus_op = XEXP (operands[1], 0);
5791 /* We should have a register now. */
5792 if (GET_CODE (plus_op) != REG)
5795 if (REGNO (plus_op) < FIRST_PSEUDO_REGISTER)
5797 /* We have to have at least one temporary register which is not
5798 overlapping plus_op. */
5799 if (! rtx_equal_p (plus_op, operands[0]))
5801 emit_move_insn (operands[0], stack_pointer_rtx);
5802 emit_insn (gen_addsi3 (operands[0], operands[0], plus_op));
5804 else if (! rtx_equal_p (plus_op, operands[2]))
5806 emit_move_insn (operands[2], stack_pointer_rtx);
5807 emit_insn (gen_addsi3 (operands[0], plus_op, operands[2]));
5814 /* We need two registers in this case. */
5815 if (! rtx_equal_p (operands[0], operands[2]))
5817 emit_move_insn (operands[0], stack_pointer_rtx);
5818 emit_move_insn (operands[2], plus_op);
5819 emit_insn (gen_addsi3 (operands[0], operands[0], operands[2]));
5827 /* FIXME: I don't know how to get a value into the HI register. */
5828 emit_move_insn (operands[0], operands[1]);
5832 ;; This insn is for the unspec delay for HILO.
5834 (define_insn "hilo_delay"
5835 [(unspec [(match_operand 0 "register_operand" "=b")] UNSPEC_HILO_DELAY)]
5838 [(set_attr "type" "nop")
5839 (set_attr "mode" "none")
5840 (set_attr "can_delay" "no")])
5842 ;; This insn handles moving CCmode values. It's really just a
5843 ;; slightly simplified copy of movsi_internal2, with additional cases
5844 ;; to move a condition register to a general register and to move
5845 ;; between the general registers and the floating point registers.
5847 (define_insn "movcc"
5848 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m")
5849 (match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))]
5850 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
5851 "* return mips_move_1word (operands, insn, FALSE);"
5852 [(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
5853 (set_attr "mode" "SI")
5854 (set_attr "length" "8,4,4,8,4,8,4,4,4,4,8,4,8")])
5856 ;; Reload condition code registers. These need scratch registers.
5858 (define_expand "reload_incc"
5859 [(set (match_operand:CC 0 "register_operand" "=z")
5860 (match_operand:CC 1 "general_operand" "z"))
5861 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
5862 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
5869 /* This is called when are copying some value into a condition code
5870 register. Operand 0 is the condition code register. Operand 1
5871 is the source. Operand 2 is a scratch register; we use TFmode
5872 because we actually need two floating point registers. */
5873 if (! ST_REG_P (true_regnum (operands[0]))
5874 || ! FP_REG_P (true_regnum (operands[2])))
5877 /* We need to get the source in SFmode so that the insn is
5879 if (GET_CODE (operands[1]) == MEM)
5880 source = adjust_address (operands[1], SFmode, 0);
5881 else if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)
5882 source = gen_rtx_REG (SFmode, true_regnum (operands[1]));
5884 source = operands[1];
5886 /* FP1 and FP2 are the two halves of the TFmode scratch operand. They
5887 will be single registers in 64-bit mode and register pairs in 32-bit
5888 mode. SOURCE is loaded into FP1 and zero is loaded into FP2. */
5889 regno = REGNO (operands[2]);
5890 fp1 = gen_rtx_REG (SFmode, regno);
5891 fp2 = gen_rtx_REG (SFmode, regno + HARD_REGNO_NREGS (regno, DFmode));
5893 emit_insn (gen_move_insn (fp1, source));
5894 emit_insn (gen_move_insn (fp2, gen_rtx_REG (SFmode, 0)));
5895 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
5896 gen_rtx_LT (CCmode, fp2, fp1)));
5901 (define_expand "reload_outcc"
5902 [(set (match_operand:CC 0 "general_operand" "=z")
5903 (match_operand:CC 1 "register_operand" "z"))
5904 (clobber (match_operand:CC 2 "register_operand" "=&d"))]
5905 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
5908 /* This is called when we are copying a condition code register out
5909 to save it somewhere. Operand 0 should be the location we are
5910 going to save it to. Operand 1 should be the condition code
5911 register. Operand 2 should be a scratch general purpose register
5912 created for us by reload. The mips_secondary_reload_class
5913 function should have told reload that we don't need a scratch
5914 register if the destination is a general purpose register anyhow. */
5915 if (ST_REG_P (true_regnum (operands[0]))
5916 || GP_REG_P (true_regnum (operands[0]))
5917 || ! ST_REG_P (true_regnum (operands[1]))
5918 || ! GP_REG_P (true_regnum (operands[2])))
5921 /* All we have to do is copy the value from the condition code to
5922 the data register, which movcc can handle, and then store the
5923 value into the real final destination. */
5924 emit_insn (gen_move_insn (operands[2], operands[1]));
5925 emit_insn (gen_move_insn (operands[0], operands[2]));
5930 ;; MIPS4 supports loading and storing a floating point register from
5931 ;; the sum of two general registers. We use two versions for each of
5932 ;; these four instructions: one where the two general registers are
5933 ;; SImode, and one where they are DImode. This is because general
5934 ;; registers will be in SImode when they hold 32 bit values, but,
5935 ;; since the 32 bit values are always sign extended, the [ls][wd]xc1
5936 ;; instructions will still work correctly.
5938 ;; ??? Perhaps it would be better to support these instructions by
5939 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
5940 ;; these instructions can only be used to load and store floating
5941 ;; point registers, that would probably cause trouble in reload.
5944 [(set (match_operand:SF 0 "register_operand" "=f")
5945 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
5946 (match_operand:SI 2 "register_operand" "d"))))]
5947 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
5949 [(set_attr "type" "load")
5950 (set_attr "mode" "SF")])
5953 [(set (match_operand:SF 0 "register_operand" "=f")
5954 (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
5955 (match_operand:DI 2 "se_register_operand" "d"))))]
5956 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
5958 [(set_attr "type" "load")
5959 (set_attr "mode" "SF")])
5962 [(set (match_operand:DF 0 "register_operand" "=f")
5963 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
5964 (match_operand:SI 2 "register_operand" "d"))))]
5965 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5967 [(set_attr "type" "load")
5968 (set_attr "mode" "DF")])
5971 [(set (match_operand:DF 0 "register_operand" "=f")
5972 (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
5973 (match_operand:DI 2 "se_register_operand" "d"))))]
5974 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5976 [(set_attr "type" "load")
5977 (set_attr "mode" "DF")])
5980 [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
5981 (match_operand:SI 2 "register_operand" "d")))
5982 (match_operand:SF 0 "register_operand" "f"))]
5983 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
5985 [(set_attr "type" "store")
5986 (set_attr "mode" "SF")])
5989 [(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
5990 (match_operand:DI 2 "se_register_operand" "d")))
5991 (match_operand:SF 0 "register_operand" "f"))]
5992 "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
5994 [(set_attr "type" "store")
5995 (set_attr "mode" "SF")])
5998 [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
5999 (match_operand:SI 2 "register_operand" "d")))
6000 (match_operand:DF 0 "register_operand" "f"))]
6001 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6003 [(set_attr "type" "store")
6004 (set_attr "mode" "DF")])
6007 [(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
6008 (match_operand:DI 2 "se_register_operand" "d")))
6009 (match_operand:DF 0 "register_operand" "f"))]
6010 "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6012 [(set_attr "type" "store")
6013 (set_attr "mode" "DF")])
6015 ;; 16-bit Integer moves
6017 ;; Unlike most other insns, the move insns can't be split with
6018 ;; different predicates, because register spilling and other parts of
6019 ;; the compiler, have memoized the insn number already.
6020 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
6022 (define_expand "movhi"
6023 [(set (match_operand:HI 0 "nonimmediate_operand" "")
6024 (match_operand:HI 1 "general_operand" ""))]
6028 if ((reload_in_progress | reload_completed) == 0
6029 && !register_operand (operands[0], HImode)
6030 && !register_operand (operands[1], HImode)
6032 || (GET_CODE (operands[1]) != CONST_INT
6033 || INTVAL (operands[1]) != 0)))
6035 rtx temp = force_reg (HImode, operands[1]);
6036 emit_move_insn (operands[0], temp);
6041 ;; The difference between these two is whether or not ints are allowed
6042 ;; in FP registers (off by default, use -mdebugh to enable).
6044 (define_insn "movhi_internal1"
6045 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d")
6046 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
6047 "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
6048 && (register_operand (operands[0], HImode)
6049 || register_operand (operands[1], HImode)
6050 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
6051 "* return mips_move_1word (operands, insn, TRUE);"
6052 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
6053 (set_attr "mode" "HI")
6054 (set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
6056 (define_insn "movhi_internal2"
6057 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
6058 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
6059 "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
6060 && (register_operand (operands[0], HImode)
6061 || register_operand (operands[1], HImode)
6062 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
6063 "* return mips_move_1word (operands, insn, TRUE);"
6064 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
6065 (set_attr "mode" "HI")
6066 (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
6069 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
6070 (match_operand:HI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))]
6072 && (register_operand (operands[0], HImode)
6073 || register_operand (operands[1], HImode))"
6074 "* return mips_move_1word (operands, insn, TRUE);"
6075 [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
6076 (set_attr "mode" "HI")
6077 (set_attr_alternative "length"
6081 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
6084 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
6094 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
6095 ;; when the original load is a 4 byte instruction but the add and the
6096 ;; load are 2 2 byte instructions.
6099 [(set (match_operand:HI 0 "register_operand" "")
6100 (mem:HI (plus:SI (match_dup 0)
6101 (match_operand:SI 1 "const_int_operand" ""))))]
6102 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
6103 && GET_CODE (operands[0]) == REG
6104 && M16_REG_P (REGNO (operands[0]))
6105 && GET_CODE (operands[1]) == CONST_INT
6106 && ((INTVAL (operands[1]) < 0
6107 && INTVAL (operands[1]) >= -0x80)
6108 || (INTVAL (operands[1]) >= 32 * 2
6109 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
6110 || (INTVAL (operands[1]) >= 0
6111 && INTVAL (operands[1]) < 32 * 2
6112 && (INTVAL (operands[1]) & 1) != 0))"
6113 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
6114 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
6117 HOST_WIDE_INT val = INTVAL (operands[1]);
6120 operands[2] = GEN_INT (0);
6121 else if (val >= 32 * 2)
6125 operands[1] = GEN_INT (0x7e + off);
6126 operands[2] = GEN_INT (val - off - 0x7e);
6132 operands[1] = GEN_INT (off);
6133 operands[2] = GEN_INT (val - off);
6137 ;; 8-bit Integer moves
6139 ;; Unlike most other insns, the move insns can't be split with
6140 ;; different predicates, because register spilling and other parts of
6141 ;; the compiler, have memoized the insn number already.
6142 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
6144 (define_expand "movqi"
6145 [(set (match_operand:QI 0 "nonimmediate_operand" "")
6146 (match_operand:QI 1 "general_operand" ""))]
6150 if ((reload_in_progress | reload_completed) == 0
6151 && !register_operand (operands[0], QImode)
6152 && !register_operand (operands[1], QImode)
6154 || (GET_CODE (operands[1]) != CONST_INT
6155 || INTVAL (operands[1]) != 0)))
6157 rtx temp = force_reg (QImode, operands[1]);
6158 emit_move_insn (operands[0], temp);
6163 ;; The difference between these two is whether or not ints are allowed
6164 ;; in FP registers (off by default, use -mdebugh to enable).
6166 (define_insn "movqi_internal1"
6167 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
6168 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
6169 "TARGET_DEBUG_H_MODE && !TARGET_MIPS16
6170 && (register_operand (operands[0], QImode)
6171 || register_operand (operands[1], QImode)
6172 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
6173 "* return mips_move_1word (operands, insn, TRUE);"
6174 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
6175 (set_attr "mode" "QI")
6176 (set_attr "length" "4,4,4,8,4,8,4,4,4,4,4")])
6178 (define_insn "movqi_internal2"
6179 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
6180 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
6181 "!TARGET_DEBUG_H_MODE && !TARGET_MIPS16
6182 && (register_operand (operands[0], QImode)
6183 || register_operand (operands[1], QImode)
6184 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
6185 "* return mips_move_1word (operands, insn, TRUE);"
6186 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
6187 (set_attr "mode" "QI")
6188 (set_attr "length" "4,4,4,8,4,8,4,4,4,4")])
6191 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,R,m,*d")
6192 (match_operand:QI 1 "general_operand" "d,d,y,K,N,R,m,d,d,*x"))]
6194 && (register_operand (operands[0], QImode)
6195 || register_operand (operands[1], QImode))"
6196 "* return mips_move_1word (operands, insn, TRUE);"
6197 [(set_attr "type" "move,move,move,arith,arith,load,load,store,store,hilo")
6198 (set_attr "mode" "QI")
6199 (set_attr_alternative "length"
6203 (if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
6206 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
6216 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
6217 ;; when the original load is a 4 byte instruction but the add and the
6218 ;; load are 2 2 byte instructions.
6221 [(set (match_operand:QI 0 "register_operand" "")
6222 (mem:QI (plus:SI (match_dup 0)
6223 (match_operand:SI 1 "const_int_operand" ""))))]
6224 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
6225 && GET_CODE (operands[0]) == REG
6226 && M16_REG_P (REGNO (operands[0]))
6227 && GET_CODE (operands[1]) == CONST_INT
6228 && ((INTVAL (operands[1]) < 0
6229 && INTVAL (operands[1]) >= -0x80)
6230 || (INTVAL (operands[1]) >= 32
6231 && INTVAL (operands[1]) <= 31 + 0x7f))"
6232 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
6233 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
6236 HOST_WIDE_INT val = INTVAL (operands[1]);
6239 operands[2] = GEN_INT (0);
6242 operands[1] = GEN_INT (0x7f);
6243 operands[2] = GEN_INT (val - 0x7f);
6247 ;; 32-bit floating point moves
6249 (define_expand "movsf"
6250 [(set (match_operand:SF 0 "nonimmediate_operand" "")
6251 (match_operand:SF 1 "general_operand" ""))]
6255 if ((reload_in_progress | reload_completed) == 0
6256 && !register_operand (operands[0], SFmode)
6257 && !register_operand (operands[1], SFmode)
6259 || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
6260 && operands[1] != CONST0_RTX (SFmode))))
6262 rtx temp = force_reg (SFmode, operands[1]);
6263 emit_move_insn (operands[0], temp);
6268 (define_insn "movsf_internal1"
6269 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m")
6270 (match_operand:SF 1 "general_operand" "f,G,R,Fm,fG,fG,*d,*f,*G*d,*R,*F*m,*d,*d"))]
6272 && (register_operand (operands[0], SFmode)
6273 || register_operand (operands[1], SFmode)
6274 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
6275 || operands[1] == CONST0_RTX (SFmode))"
6276 "* return mips_move_1word (operands, insn, FALSE);"
6277 [(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
6278 (set_attr "mode" "SF")
6279 (set_attr "length" "4,4,4,8,4,8,4,4,4,4,8,4,8")])
6282 (define_insn "movsf_internal2"
6283 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,R,m")
6284 (match_operand:SF 1 "general_operand" " Gd,R,Fm,d,d"))]
6285 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
6286 && (register_operand (operands[0], SFmode)
6287 || register_operand (operands[1], SFmode)
6288 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
6289 || operands[1] == CONST0_RTX (SFmode))"
6290 "* return mips_move_1word (operands, insn, FALSE);"
6291 [(set_attr "type" "move,load,load,store,store")
6292 (set_attr "mode" "SF")
6293 (set_attr "length" "4,4,8,4,8")])
6296 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,d,R,m")
6297 (match_operand:SF 1 "general_operand" "d,d,y,R,Fm,d,d"))]
6299 && (register_operand (operands[0], SFmode)
6300 || register_operand (operands[1], SFmode))"
6301 "* return mips_move_1word (operands, insn, FALSE);"
6302 [(set_attr "type" "move,move,move,load,load,store,store")
6303 (set_attr "mode" "SF")
6304 (set_attr "length" "4,4,4,4,8,4,8")])
6307 ;; 64-bit floating point moves
6309 (define_expand "movdf"
6310 [(set (match_operand:DF 0 "nonimmediate_operand" "")
6311 (match_operand:DF 1 "general_operand" ""))]
6315 if ((reload_in_progress | reload_completed) == 0
6316 && !register_operand (operands[0], DFmode)
6317 && !register_operand (operands[1], DFmode)
6319 || ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
6320 && operands[1] != CONST0_RTX (DFmode))))
6322 rtx temp = force_reg (DFmode, operands[1]);
6323 emit_move_insn (operands[0], temp);
6328 (define_insn "movdf_internal1"
6329 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,To,f,*f,*d,*d,*d,*d,*R,*T")
6330 (match_operand:DF 1 "general_operand" "f,R,To,fG,fG,F,*d,*f,*d*G,*R,*T*F,*d,*d"))]
6331 "TARGET_HARD_FLOAT && !(TARGET_FLOAT64 && !TARGET_64BIT)
6332 && TARGET_DOUBLE_FLOAT
6333 && (register_operand (operands[0], DFmode)
6334 || register_operand (operands[1], DFmode)
6335 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
6336 || operands[1] == CONST0_RTX (DFmode))"
6337 "* return mips_move_2words (operands, insn); "
6338 [(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
6339 (set_attr "mode" "DF")
6340 (set_attr "length" "4,8,16,8,16,16,8,8,8,8,16,8,16")])
6342 (define_insn "movdf_internal1a"
6343 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,R,R,To,To,*d,*d,*d,*To,*R,*d")
6344 (match_operand:DF 1 "general_operand" " f,To,f,G,f,G,*F,*To,*R,*d,*d,*d"))]
6345 "TARGET_HARD_FLOAT && (TARGET_FLOAT64 && !TARGET_64BIT)
6346 && TARGET_DOUBLE_FLOAT
6347 && (register_operand (operands[0], DFmode)
6348 || register_operand (operands[1], DFmode)
6349 || (GET_CODE (operands [0]) == MEM
6350 && ((GET_CODE (operands[1]) == CONST_INT
6351 && INTVAL (operands[1]) == 0)
6352 || operands[1] == CONST0_RTX (DFmode))))"
6353 "* return mips_move_2words (operands, insn); "
6354 [(set_attr "type" "move,load,store,store,store,store,load,load,load,store,store,move")
6355 (set_attr "mode" "DF")
6356 (set_attr "length" "4,8,4,4,8,8,8,8,4,8,4,4")])
6358 (define_insn "movdf_internal2"
6359 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,To,d,f,f")
6360 (match_operand:DF 1 "general_operand" "dG,R,ToF,d,d,f,d,f"))]
6361 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
6362 && (register_operand (operands[0], DFmode)
6363 || register_operand (operands[1], DFmode)
6364 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
6365 || operands[1] == CONST0_RTX (DFmode))"
6366 "* return mips_move_2words (operands, insn); "
6367 [(set_attr "type" "move,load,load,store,store,xfer,load,move")
6368 (set_attr "mode" "DF")
6369 (set_attr "length" "8,8,16,8,16,8,8,4")])
6372 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,d,R,To")
6373 (match_operand:DF 1 "general_operand" "d,d,y,R,ToF,d,d"))]
6375 && (register_operand (operands[0], DFmode)
6376 || register_operand (operands[1], DFmode))"
6377 "* return mips_move_2words (operands, insn);"
6378 [(set_attr "type" "move,move,move,load,load,store,store")
6379 (set_attr "mode" "DF")
6380 (set_attr "length" "8,8,8,8,16,8,16")])
6383 [(set (match_operand:DF 0 "register_operand" "")
6384 (match_operand:DF 1 "register_operand" ""))]
6385 "reload_completed && !TARGET_64BIT
6386 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
6387 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
6388 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
6389 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
6390 (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
6393 ;; Instructions to load the global pointer register.
6394 ;; This is volatile to make sure that the scheduler won't move any symbol_ref
6395 ;; uses in front of it. All symbol_refs implicitly use the gp reg.
6397 (define_insn "loadgp"
6399 (unspec_volatile:DI [(match_operand:DI 0 "address_operand" "")
6400 (match_operand:DI 1 "register_operand" "")]
6402 (clobber (reg:DI 1))]
6404 "%[lui\\t$1,%%hi(%%neg(%%gp_rel(%a0)))\\n\\taddiu\\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\\n\\tdaddu\\t$gp,$1,%1%]"
6405 [(set_attr "type" "move")
6406 (set_attr "mode" "DI")
6407 (set_attr "length" "12")])
6409 ;; Block moves, see mips.c for more details.
6410 ;; Argument 0 is the destination
6411 ;; Argument 1 is the source
6412 ;; Argument 2 is the length
6413 ;; Argument 3 is the alignment
6415 (define_expand "movstrsi"
6416 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
6417 (match_operand:BLK 1 "general_operand" ""))
6418 (use (match_operand:SI 2 "arith32_operand" ""))
6419 (use (match_operand:SI 3 "immediate_operand" ""))])]
6423 if (operands[0]) /* avoid unused code messages */
6425 expand_block_move (operands);
6430 ;; Insn generated by block moves
6432 (define_insn "movstrsi_internal"
6433 [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
6434 (match_operand:BLK 1 "memory_operand" "o")) ;; source
6435 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
6436 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
6437 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
6438 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
6439 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
6440 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
6441 (use (const_int 0))] ;; normal block move
6443 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
6444 [(set_attr "type" "store")
6445 (set_attr "mode" "none")
6446 (set_attr "length" "80")])
6448 ;; We need mips16 versions, because an offset from the stack pointer
6449 ;; is not offsettable, since the stack pointer can only handle 4 and 8
6453 [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
6454 (match_operand:BLK 1 "memory_operand" "o")) ;; source
6455 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
6456 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
6457 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
6458 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
6459 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
6460 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
6461 (use (const_int 0))] ;; normal block move
6463 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
6464 [(set_attr "type" "multi")
6465 (set_attr "mode" "none")
6466 (set_attr "length" "80")])
6468 ;; Split a block move into 2 parts, the first part is everything
6469 ;; except for the last move, and the second part is just the last
6470 ;; store, which is exactly 1 instruction (ie, not a usw), so it can
6471 ;; fill a delay slot. This also prevents a bug in delayed branches
6472 ;; from showing up, which reuses one of the registers in our clobbers.
6475 [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
6476 (mem:BLK (match_operand:SI 1 "register_operand" "")))
6477 (clobber (match_operand:SI 4 "register_operand" ""))
6478 (clobber (match_operand:SI 5 "register_operand" ""))
6479 (clobber (match_operand:SI 6 "register_operand" ""))
6480 (clobber (match_operand:SI 7 "register_operand" ""))
6481 (use (match_operand:SI 2 "small_int" ""))
6482 (use (match_operand:SI 3 "small_int" ""))
6483 (use (const_int 0))]
6485 "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0"
6487 ;; All but the last move
6488 [(parallel [(set (mem:BLK (match_dup 0))
6489 (mem:BLK (match_dup 1)))
6490 (clobber (match_dup 4))
6491 (clobber (match_dup 5))
6492 (clobber (match_dup 6))
6493 (clobber (match_dup 7))
6496 (use (const_int 1))])
6498 ;; The last store, so it can fill a delay slot
6499 (parallel [(set (mem:BLK (match_dup 0))
6500 (mem:BLK (match_dup 1)))
6501 (clobber (match_dup 4))
6502 (clobber (match_dup 5))
6503 (clobber (match_dup 6))
6504 (clobber (match_dup 7))
6507 (use (const_int 2))])]
6511 (define_insn "movstrsi_internal2"
6512 [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
6513 (match_operand:BLK 1 "memory_operand" "o")) ;; source
6514 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
6515 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
6516 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
6517 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
6518 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
6519 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
6520 (use (const_int 1))] ;; all but last store
6522 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
6523 [(set_attr "type" "store")
6524 (set_attr "mode" "none")
6525 (set_attr "length" "80")])
6528 [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
6529 (match_operand:BLK 1 "memory_operand" "o")) ;; source
6530 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
6531 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
6532 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
6533 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
6534 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
6535 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
6536 (use (const_int 1))] ;; all but last store
6538 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
6539 [(set_attr "type" "multi")
6540 (set_attr "mode" "none")
6541 (set_attr "length" "80")])
6543 (define_insn "movstrsi_internal3"
6544 [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
6545 (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
6546 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
6547 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
6548 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
6549 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
6550 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
6551 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
6552 (use (const_int 2))] ;; just last store of block move
6554 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
6555 [(set_attr "type" "store")
6556 (set_attr "mode" "none")])
6559 ;; ....................
6563 ;; ....................
6565 ;; Many of these instructions uses trivial define_expands, because we
6566 ;; want to use a different set of constraints when TARGET_MIPS16.
6568 (define_expand "ashlsi3"
6569 [(set (match_operand:SI 0 "register_operand" "=d")
6570 (ashift:SI (match_operand:SI 1 "register_operand" "d")
6571 (match_operand:SI 2 "arith_operand" "dI")))]
6575 /* On the mips16, a shift of more than 8 is a four byte instruction,
6576 so, for a shift between 8 and 16, it is just as fast to do two
6577 shifts of 8 or less. If there is a lot of shifting going on, we
6578 may win in CSE. Otherwise combine will put the shifts back
6579 together again. This can be called by function_arg, so we must
6580 be careful not to allocate a new register if we've reached the
6584 && GET_CODE (operands[2]) == CONST_INT
6585 && INTVAL (operands[2]) > 8
6586 && INTVAL (operands[2]) <= 16
6587 && ! reload_in_progress
6588 && ! reload_completed)
6590 rtx temp = gen_reg_rtx (SImode);
6592 emit_insn (gen_ashlsi3_internal2 (temp, operands[1], GEN_INT (8)));
6593 emit_insn (gen_ashlsi3_internal2 (operands[0], temp,
6594 GEN_INT (INTVAL (operands[2]) - 8)));
6599 (define_insn "ashlsi3_internal1"
6600 [(set (match_operand:SI 0 "register_operand" "=d")
6601 (ashift:SI (match_operand:SI 1 "register_operand" "d")
6602 (match_operand:SI 2 "arith_operand" "dI")))]
6606 if (GET_CODE (operands[2]) == CONST_INT)
6607 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6609 return \"sll\\t%0,%1,%2\";
6611 [(set_attr "type" "arith")
6612 (set_attr "mode" "SI")])
6614 (define_insn "ashlsi3_internal2"
6615 [(set (match_operand:SI 0 "register_operand" "=d,d")
6616 (ashift:SI (match_operand:SI 1 "register_operand" "0,d")
6617 (match_operand:SI 2 "arith_operand" "d,I")))]
6621 if (which_alternative == 0)
6622 return \"sll\\t%0,%2\";
6624 if (GET_CODE (operands[2]) == CONST_INT)
6625 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6627 return \"sll\\t%0,%1,%2\";
6629 [(set_attr "type" "arith")
6630 (set_attr "mode" "SI")
6631 (set_attr_alternative "length"
6633 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
6637 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
6640 [(set (match_operand:SI 0 "register_operand" "")
6641 (ashift:SI (match_operand:SI 1 "register_operand" "")
6642 (match_operand:SI 2 "const_int_operand" "")))]
6643 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
6644 && GET_CODE (operands[2]) == CONST_INT
6645 && INTVAL (operands[2]) > 8
6646 && INTVAL (operands[2]) <= 16"
6647 [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 8)))
6648 (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
6651 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
6654 (define_expand "ashldi3"
6655 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6656 (ashift:DI (match_operand:DI 1 "se_register_operand" "")
6657 (match_operand:SI 2 "arith_operand" "")))
6658 (clobber (match_dup 3))])]
6659 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
6664 /* On the mips16, a shift of more than 8 is a four byte
6665 instruction, so, for a shift between 8 and 16, it is just as
6666 fast to do two shifts of 8 or less. If there is a lot of
6667 shifting going on, we may win in CSE. Otherwise combine will
6668 put the shifts back together again. This can be called by
6669 function_arg, so we must be careful not to allocate a new
6670 register if we've reached the reload pass. */
6673 && GET_CODE (operands[2]) == CONST_INT
6674 && INTVAL (operands[2]) > 8
6675 && INTVAL (operands[2]) <= 16
6676 && ! reload_in_progress
6677 && ! reload_completed)
6679 rtx temp = gen_reg_rtx (DImode);
6681 emit_insn (gen_ashldi3_internal4 (temp, operands[1], GEN_INT (8)));
6682 emit_insn (gen_ashldi3_internal4 (operands[0], temp,
6683 GEN_INT (INTVAL (operands[2]) - 8)));
6687 emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
6692 operands[3] = gen_reg_rtx (SImode);
6696 (define_insn "ashldi3_internal"
6697 [(set (match_operand:DI 0 "register_operand" "=&d")
6698 (ashift:DI (match_operand:DI 1 "register_operand" "d")
6699 (match_operand:SI 2 "register_operand" "d")))
6700 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6701 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
6704 operands[4] = const0_rtx;
6705 dslots_jump_total += 3;
6706 dslots_jump_filled += 2;
6708 return \"sll\\t%3,%2,26\\n\\
6709 \\tbgez\\t%3,1f\\n\\
6710 \\tsll\\t%M0,%L1,%2\\n\\
6712 \\tmove\\t%L0,%z4%)\\n\\
6715 \\t%(beq\\t%3,%z4,2f\\n\\
6716 \\tsll\\t%M0,%M1,%2%)\\n\\
6718 \\tsubu\\t%3,%z4,%2\\n\\
6719 \\tsrl\\t%3,%L1,%3\\n\\
6720 \\tor\\t%M0,%M0,%3\\n\\
6722 \\tsll\\t%L0,%L1,%2\\n\\
6725 [(set_attr "type" "darith")
6726 (set_attr "mode" "SI")
6727 (set_attr "length" "48")])
6730 (define_insn "ashldi3_internal2"
6731 [(set (match_operand:DI 0 "register_operand" "=d")
6732 (ashift:DI (match_operand:DI 1 "register_operand" "d")
6733 (match_operand:SI 2 "small_int" "IJK")))
6734 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6735 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6736 && (INTVAL (operands[2]) & 32) != 0"
6739 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6740 operands[4] = const0_rtx;
6741 return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\";
6743 [(set_attr "type" "darith")
6744 (set_attr "mode" "DI")
6745 (set_attr "length" "8")])
6749 [(set (match_operand:DI 0 "register_operand" "")
6750 (ashift:DI (match_operand:DI 1 "register_operand" "")
6751 (match_operand:SI 2 "small_int" "")))
6752 (clobber (match_operand:SI 3 "register_operand" ""))]
6753 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
6754 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6755 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6756 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6757 && (INTVAL (operands[2]) & 32) != 0"
6759 [(set (subreg:SI (match_dup 0) 4) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
6760 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
6762 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
6766 [(set (match_operand:DI 0 "register_operand" "")
6767 (ashift:DI (match_operand:DI 1 "register_operand" "")
6768 (match_operand:SI 2 "small_int" "")))
6769 (clobber (match_operand:SI 3 "register_operand" ""))]
6770 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
6771 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6772 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6773 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6774 && (INTVAL (operands[2]) & 32) != 0"
6776 [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
6777 (set (subreg:SI (match_dup 0) 4) (const_int 0))]
6779 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
6782 (define_insn "ashldi3_internal3"
6783 [(set (match_operand:DI 0 "register_operand" "=d")
6784 (ashift:DI (match_operand:DI 1 "register_operand" "d")
6785 (match_operand:SI 2 "small_int" "IJK")))
6786 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6787 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6788 && (INTVAL (operands[2]) & 63) < 32
6789 && (INTVAL (operands[2]) & 63) != 0"
6792 int amount = INTVAL (operands[2]);
6794 operands[2] = GEN_INT (amount & 31);
6795 operands[4] = const0_rtx;
6796 operands[5] = GEN_INT ((-amount) & 31);
6798 return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
6800 [(set_attr "type" "darith")
6801 (set_attr "mode" "DI")
6802 (set_attr "length" "16")])
6806 [(set (match_operand:DI 0 "register_operand" "")
6807 (ashift:DI (match_operand:DI 1 "register_operand" "")
6808 (match_operand:SI 2 "small_int" "")))
6809 (clobber (match_operand:SI 3 "register_operand" ""))]
6810 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
6811 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6812 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6813 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6814 && (INTVAL (operands[2]) & 63) < 32
6815 && (INTVAL (operands[2]) & 63) != 0"
6817 [(set (subreg:SI (match_dup 0) 4)
6818 (ashift:SI (subreg:SI (match_dup 1) 4)
6822 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
6825 (set (subreg:SI (match_dup 0) 4)
6826 (ior:SI (subreg:SI (match_dup 0) 4)
6829 (set (subreg:SI (match_dup 0) 0)
6830 (ashift:SI (subreg:SI (match_dup 1) 0)
6834 int amount = INTVAL (operands[2]);
6835 operands[2] = GEN_INT (amount & 31);
6836 operands[4] = GEN_INT ((-amount) & 31);
6841 [(set (match_operand:DI 0 "register_operand" "")
6842 (ashift:DI (match_operand:DI 1 "register_operand" "")
6843 (match_operand:SI 2 "small_int" "")))
6844 (clobber (match_operand:SI 3 "register_operand" ""))]
6845 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
6846 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
6847 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
6848 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
6849 && (INTVAL (operands[2]) & 63) < 32
6850 && (INTVAL (operands[2]) & 63) != 0"
6852 [(set (subreg:SI (match_dup 0) 0)
6853 (ashift:SI (subreg:SI (match_dup 1) 0)
6857 (lshiftrt:SI (subreg:SI (match_dup 1) 4)
6860 (set (subreg:SI (match_dup 0) 0)
6861 (ior:SI (subreg:SI (match_dup 0) 0)
6864 (set (subreg:SI (match_dup 0) 4)
6865 (ashift:SI (subreg:SI (match_dup 1) 4)
6869 int amount = INTVAL (operands[2]);
6870 operands[2] = GEN_INT (amount & 31);
6871 operands[4] = GEN_INT ((-amount) & 31);
6875 (define_insn "ashldi3_internal4"
6876 [(set (match_operand:DI 0 "register_operand" "=d")
6877 (ashift:DI (match_operand:DI 1 "se_register_operand" "d")
6878 (match_operand:SI 2 "arith_operand" "dI")))]
6879 "TARGET_64BIT && !TARGET_MIPS16"
6882 if (GET_CODE (operands[2]) == CONST_INT)
6883 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6885 return \"dsll\\t%0,%1,%2\";
6887 [(set_attr "type" "arith")
6888 (set_attr "mode" "DI")])
6891 [(set (match_operand:DI 0 "register_operand" "=d,d")
6892 (ashift:DI (match_operand:DI 1 "se_register_operand" "0,d")
6893 (match_operand:SI 2 "arith_operand" "d,I")))]
6894 "TARGET_64BIT && TARGET_MIPS16"
6897 if (which_alternative == 0)
6898 return \"dsll\\t%0,%2\";
6900 if (GET_CODE (operands[2]) == CONST_INT)
6901 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
6903 return \"dsll\\t%0,%1,%2\";
6905 [(set_attr "type" "arith")
6906 (set_attr "mode" "DI")
6907 (set_attr_alternative "length"
6909 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
6914 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
6917 [(set (match_operand:DI 0 "register_operand" "")
6918 (ashift:DI (match_operand:DI 1 "register_operand" "")
6919 (match_operand:SI 2 "const_int_operand" "")))]
6920 "TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE
6922 && GET_CODE (operands[2]) == CONST_INT
6923 && INTVAL (operands[2]) > 8
6924 && INTVAL (operands[2]) <= 16"
6925 [(set (match_dup 0) (ashift:DI (match_dup 1) (const_int 8)))
6926 (set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))]
6929 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
6932 (define_expand "ashrsi3"
6933 [(set (match_operand:SI 0 "register_operand" "=d")
6934 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
6935 (match_operand:SI 2 "arith_operand" "dI")))]
6939 /* On the mips16, a shift of more than 8 is a four byte instruction,
6940 so, for a shift between 8 and 16, it is just as fast to do two
6941 shifts of 8 or less. If there is a lot of shifting going on, we
6942 may win in CSE. Otherwise combine will put the shifts back
6946 && GET_CODE (operands[2]) == CONST_INT
6947 && INTVAL (operands[2]) > 8
6948 && INTVAL (operands[2]) <= 16)
6950 rtx temp = gen_reg_rtx (SImode);
6952 emit_insn (gen_ashrsi3_internal2 (temp, operands[1], GEN_INT (8)));
6953 emit_insn (gen_ashrsi3_internal2 (operands[0], temp,
6954 GEN_INT (INTVAL (operands[2]) - 8)));
6959 (define_insn "ashrsi3_internal1"
6960 [(set (match_operand:SI 0 "register_operand" "=d")
6961 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
6962 (match_operand:SI 2 "arith_operand" "dI")))]
6966 if (GET_CODE (operands[2]) == CONST_INT)
6967 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6969 return \"sra\\t%0,%1,%2\";
6971 [(set_attr "type" "arith")
6972 (set_attr "mode" "SI")])
6974 (define_insn "ashrsi3_internal2"
6975 [(set (match_operand:SI 0 "register_operand" "=d,d")
6976 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
6977 (match_operand:SI 2 "arith_operand" "d,I")))]
6981 if (which_alternative == 0)
6982 return \"sra\\t%0,%2\";
6984 if (GET_CODE (operands[2]) == CONST_INT)
6985 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
6987 return \"sra\\t%0,%1,%2\";
6989 [(set_attr "type" "arith")
6990 (set_attr "mode" "SI")
6991 (set_attr_alternative "length"
6993 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
6998 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
7001 [(set (match_operand:SI 0 "register_operand" "")
7002 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
7003 (match_operand:SI 2 "const_int_operand" "")))]
7004 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
7005 && GET_CODE (operands[2]) == CONST_INT
7006 && INTVAL (operands[2]) > 8
7007 && INTVAL (operands[2]) <= 16"
7008 [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 8)))
7009 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
7012 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
7015 (define_expand "ashrdi3"
7016 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7017 (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "")
7018 (match_operand:SI 2 "arith_operand" "")))
7019 (clobber (match_dup 3))])]
7020 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
7025 /* On the mips16, a shift of more than 8 is a four byte
7026 instruction, so, for a shift between 8 and 16, it is just as
7027 fast to do two shifts of 8 or less. If there is a lot of
7028 shifting going on, we may win in CSE. Otherwise combine will
7029 put the shifts back together again. */
7032 && GET_CODE (operands[2]) == CONST_INT
7033 && INTVAL (operands[2]) > 8
7034 && INTVAL (operands[2]) <= 16)
7036 rtx temp = gen_reg_rtx (DImode);
7038 emit_insn (gen_ashrdi3_internal4 (temp, operands[1], GEN_INT (8)));
7039 emit_insn (gen_ashrdi3_internal4 (operands[0], temp,
7040 GEN_INT (INTVAL (operands[2]) - 8)));
7044 emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
7049 operands[3] = gen_reg_rtx (SImode);
7053 (define_insn "ashrdi3_internal"
7054 [(set (match_operand:DI 0 "register_operand" "=&d")
7055 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
7056 (match_operand:SI 2 "register_operand" "d")))
7057 (clobber (match_operand:SI 3 "register_operand" "=d"))]
7058 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
7061 operands[4] = const0_rtx;
7062 dslots_jump_total += 3;
7063 dslots_jump_filled += 2;
7065 return \"sll\\t%3,%2,26\\n\\
7066 \\tbgez\\t%3,1f\\n\\
7067 \\tsra\\t%L0,%M1,%2\\n\\
7069 \\tsra\\t%M0,%M1,31%)\\n\\
7072 \\t%(beq\\t%3,%z4,2f\\n\\
7073 \\tsrl\\t%L0,%L1,%2%)\\n\\
7075 \\tsubu\\t%3,%z4,%2\\n\\
7076 \\tsll\\t%3,%M1,%3\\n\\
7077 \\tor\\t%L0,%L0,%3\\n\\
7079 \\tsra\\t%M0,%M1,%2\\n\\
7082 [(set_attr "type" "darith")
7083 (set_attr "mode" "DI")
7084 (set_attr "length" "48")])
7087 (define_insn "ashrdi3_internal2"
7088 [(set (match_operand:DI 0 "register_operand" "=d")
7089 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
7090 (match_operand:SI 2 "small_int" "IJK")))
7091 (clobber (match_operand:SI 3 "register_operand" "=d"))]
7092 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
7095 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
7096 return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\";
7098 [(set_attr "type" "darith")
7099 (set_attr "mode" "DI")
7100 (set_attr "length" "8")])
7104 [(set (match_operand:DI 0 "register_operand" "")
7105 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
7106 (match_operand:SI 2 "small_int" "")))
7107 (clobber (match_operand:SI 3 "register_operand" ""))]
7108 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
7109 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
7110 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
7111 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
7112 && (INTVAL (operands[2]) & 32) != 0"
7114 [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
7115 (set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (const_int 31)))]
7117 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
7121 [(set (match_operand:DI 0 "register_operand" "")
7122 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
7123 (match_operand:SI 2 "small_int" "")))
7124 (clobber (match_operand:SI 3 "register_operand" ""))]
7125 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
7126 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
7127 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
7128 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
7129 && (INTVAL (operands[2]) & 32) != 0"
7131 [(set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
7132 (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
7134 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
7137 (define_insn "ashrdi3_internal3"
7138 [(set (match_operand:DI 0 "register_operand" "=d")
7139 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
7140 (match_operand:SI 2 "small_int" "IJK")))
7141 (clobber (match_operand:SI 3 "register_operand" "=d"))]
7142 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7143 && (INTVAL (operands[2]) & 63) < 32
7144 && (INTVAL (operands[2]) & 63) != 0"
7147 int amount = INTVAL (operands[2]);
7149 operands[2] = GEN_INT (amount & 31);
7150 operands[4] = GEN_INT ((-amount) & 31);
7152 return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
7154 [(set_attr "type" "darith")
7155 (set_attr "mode" "DI")
7156 (set_attr "length" "16")])
7160 [(set (match_operand:DI 0 "register_operand" "")
7161 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
7162 (match_operand:SI 2 "small_int" "")))
7163 (clobber (match_operand:SI 3 "register_operand" ""))]
7164 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
7165 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7166 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
7167 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
7168 && (INTVAL (operands[2]) & 63) < 32
7169 && (INTVAL (operands[2]) & 63) != 0"
7171 [(set (subreg:SI (match_dup 0) 0)
7172 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
7176 (ashift:SI (subreg:SI (match_dup 1) 4)
7179 (set (subreg:SI (match_dup 0) 0)
7180 (ior:SI (subreg:SI (match_dup 0) 0)
7183 (set (subreg:SI (match_dup 0) 4)
7184 (ashiftrt:SI (subreg:SI (match_dup 1) 4)
7188 int amount = INTVAL (operands[2]);
7189 operands[2] = GEN_INT (amount & 31);
7190 operands[4] = GEN_INT ((-amount) & 31);
7195 [(set (match_operand:DI 0 "register_operand" "")
7196 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
7197 (match_operand:SI 2 "small_int" "")))
7198 (clobber (match_operand:SI 3 "register_operand" ""))]
7199 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
7200 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7201 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
7202 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
7203 && (INTVAL (operands[2]) & 63) < 32
7204 && (INTVAL (operands[2]) & 63) != 0"
7206 [(set (subreg:SI (match_dup 0) 4)
7207 (lshiftrt:SI (subreg:SI (match_dup 1) 4)
7211 (ashift:SI (subreg:SI (match_dup 1) 0)
7214 (set (subreg:SI (match_dup 0) 4)
7215 (ior:SI (subreg:SI (match_dup 0) 4)
7218 (set (subreg:SI (match_dup 0) 0)
7219 (ashiftrt:SI (subreg:SI (match_dup 1) 0)
7223 int amount = INTVAL (operands[2]);
7224 operands[2] = GEN_INT (amount & 31);
7225 operands[4] = GEN_INT ((-amount) & 31);
7229 (define_insn "ashrdi3_internal4"
7230 [(set (match_operand:DI 0 "register_operand" "=d")
7231 (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
7232 (match_operand:SI 2 "arith_operand" "dI")))]
7233 "TARGET_64BIT && !TARGET_MIPS16"
7236 if (GET_CODE (operands[2]) == CONST_INT)
7237 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7239 return \"dsra\\t%0,%1,%2\";
7241 [(set_attr "type" "arith")
7242 (set_attr "mode" "DI")])
7245 [(set (match_operand:DI 0 "register_operand" "=d,d")
7246 (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0")
7247 (match_operand:SI 2 "arith_operand" "d,I")))]
7248 "TARGET_64BIT && TARGET_MIPS16"
7251 if (GET_CODE (operands[2]) == CONST_INT)
7252 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7254 return \"dsra\\t%0,%2\";
7256 [(set_attr "type" "arith")
7257 (set_attr "mode" "DI")
7258 (set_attr_alternative "length"
7260 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
7264 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
7267 [(set (match_operand:DI 0 "register_operand" "")
7268 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
7269 (match_operand:SI 2 "const_int_operand" "")))]
7270 "TARGET_MIPS16 && TARGET_64BIT && !TARGET_DEBUG_D_MODE
7272 && GET_CODE (operands[2]) == CONST_INT
7273 && INTVAL (operands[2]) > 8
7274 && INTVAL (operands[2]) <= 16"
7275 [(set (match_dup 0) (ashiftrt:DI (match_dup 1) (const_int 8)))
7276 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (match_dup 2)))]
7279 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
7282 (define_expand "lshrsi3"
7283 [(set (match_operand:SI 0 "register_operand" "=d")
7284 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
7285 (match_operand:SI 2 "arith_operand" "dI")))]
7289 /* On the mips16, a shift of more than 8 is a four byte instruction,
7290 so, for a shift between 8 and 16, it is just as fast to do two
7291 shifts of 8 or less. If there is a lot of shifting going on, we
7292 may win in CSE. Otherwise combine will put the shifts back
7296 && GET_CODE (operands[2]) == CONST_INT
7297 && INTVAL (operands[2]) > 8
7298 && INTVAL (operands[2]) <= 16)
7300 rtx temp = gen_reg_rtx (SImode);
7302 emit_insn (gen_lshrsi3_internal2 (temp, operands[1], GEN_INT (8)));
7303 emit_insn (gen_lshrsi3_internal2 (operands[0], temp,
7304 GEN_INT (INTVAL (operands[2]) - 8)));
7309 (define_insn "lshrsi3_internal1"
7310 [(set (match_operand:SI 0 "register_operand" "=d")
7311 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
7312 (match_operand:SI 2 "arith_operand" "dI")))]
7316 if (GET_CODE (operands[2]) == CONST_INT)
7317 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
7319 return \"srl\\t%0,%1,%2\";
7321 [(set_attr "type" "arith")
7322 (set_attr "mode" "SI")])
7324 (define_insn "lshrsi3_internal2"
7325 [(set (match_operand:SI 0 "register_operand" "=d,d")
7326 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
7327 (match_operand:SI 2 "arith_operand" "d,I")))]
7331 if (which_alternative == 0)
7332 return \"srl\\t%0,%2\";
7334 if (GET_CODE (operands[2]) == CONST_INT)
7335 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
7337 return \"srl\\t%0,%1,%2\";
7339 [(set_attr "type" "arith")
7340 (set_attr "mode" "SI")
7341 (set_attr_alternative "length"
7343 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
7348 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
7351 [(set (match_operand:SI 0 "register_operand" "")
7352 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
7353 (match_operand:SI 2 "const_int_operand" "")))]
7354 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
7355 && GET_CODE (operands[2]) == CONST_INT
7356 && INTVAL (operands[2]) > 8
7357 && INTVAL (operands[2]) <= 16"
7358 [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 8)))
7359 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
7362 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
7365 ;; If we load a byte on the mips16 as a bitfield, the resulting
7366 ;; sequence of instructions is too complicated for combine, because it
7367 ;; involves four instructions: a load, a shift, a constant load into a
7368 ;; register, and an and (the key problem here is that the mips16 does
7369 ;; not have and immediate). We recognize a shift of a load in order
7370 ;; to make it simple enough for combine to understand.
7373 [(set (match_operand:SI 0 "register_operand" "=d,d")
7374 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "R,m")
7375 (match_operand:SI 2 "immediate_operand" "I,I")))]
7377 "lw\\t%0,%1\;srl\\t%0,%2"
7378 [(set_attr "type" "load")
7379 (set_attr "mode" "SI")
7380 (set_attr_alternative "length"
7381 [(if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
7384 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
7389 [(set (match_operand:SI 0 "register_operand" "")
7390 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "")
7391 (match_operand:SI 2 "immediate_operand" "")))]
7392 "TARGET_MIPS16 && !TARGET_DEBUG_D_MODE"
7393 [(set (match_dup 0) (match_dup 1))
7394 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
7397 (define_expand "lshrdi3"
7398 [(parallel [(set (match_operand:DI 0 "register_operand" "")
7399 (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "")
7400 (match_operand:SI 2 "arith_operand" "")))
7401 (clobber (match_dup 3))])]
7402 "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
7407 /* On the mips16, a shift of more than 8 is a four byte
7408 instruction, so, for a shift between 8 and 16, it is just as
7409 fast to do two shifts of 8 or less. If there is a lot of
7410 shifting going on, we may win in CSE. Otherwise combine will
7411 put the shifts back together again. */
7414 && GET_CODE (operands[2]) == CONST_INT
7415 && INTVAL (operands[2]) > 8
7416 && INTVAL (operands[2]) <= 16)
7418 rtx temp = gen_reg_rtx (DImode);
7420 emit_insn (gen_lshrdi3_internal4 (temp, operands[1], GEN_INT (8)));
7421 emit_insn (gen_lshrdi3_internal4 (operands[0], temp,
7422 GEN_INT (INTVAL (operands[2]) - 8)));
7426 emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
7431 operands[3] = gen_reg_rtx (SImode);
7435 (define_insn "lshrdi3_internal"
7436 [(set (match_operand:DI 0 "register_operand" "=&d")
7437 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
7438 (match_operand:SI 2 "register_operand" "d")))
7439 (clobber (match_operand:SI 3 "register_operand" "=d"))]
7440 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
7443 operands[4] = const0_rtx;
7444 dslots_jump_total += 3;
7445 dslots_jump_filled += 2;
7447 return \"sll\\t%3,%2,26\\n\\
7448 \\tbgez\\t%3,1f\\n\\
7449 \\tsrl\\t%L0,%M1,%2\\n\\
7451 \\tmove\\t%M0,%z4%)\\n\\
7454 \\t%(beq\\t%3,%z4,2f\\n\\
7455 \\tsrl\\t%L0,%L1,%2%)\\n\\
7457 \\tsubu\\t%3,%z4,%2\\n\\
7458 \\tsll\\t%3,%M1,%3\\n\\
7459 \\tor\\t%L0,%L0,%3\\n\\
7461 \\tsrl\\t%M0,%M1,%2\\n\\
7464 [(set_attr "type" "darith")
7465 (set_attr "mode" "DI")
7466 (set_attr "length" "48")])
7469 (define_insn "lshrdi3_internal2"
7470 [(set (match_operand:DI 0 "register_operand" "=d")
7471 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
7472 (match_operand:SI 2 "small_int" "IJK")))
7473 (clobber (match_operand:SI 3 "register_operand" "=d"))]
7474 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7475 && (INTVAL (operands[2]) & 32) != 0"
7478 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
7479 operands[4] = const0_rtx;
7480 return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\";
7482 [(set_attr "type" "darith")
7483 (set_attr "mode" "DI")
7484 (set_attr "length" "8")])
7488 [(set (match_operand:DI 0 "register_operand" "")
7489 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
7490 (match_operand:SI 2 "small_int" "")))
7491 (clobber (match_operand:SI 3 "register_operand" ""))]
7492 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
7493 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7494 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
7495 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
7496 && (INTVAL (operands[2]) & 32) != 0"
7498 [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
7499 (set (subreg:SI (match_dup 0) 4) (const_int 0))]
7501 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
7505 [(set (match_operand:DI 0 "register_operand" "")
7506 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
7507 (match_operand:SI 2 "small_int" "")))
7508 (clobber (match_operand:SI 3 "register_operand" ""))]
7509 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
7510 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7511 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
7512 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
7513 && (INTVAL (operands[2]) & 32) != 0"
7515 [(set (subreg:SI (match_dup 0) 4) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
7516 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
7518 "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
7521 (define_insn "lshrdi3_internal3"
7522 [(set (match_operand:DI 0 "register_operand" "=d")
7523 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
7524 (match_operand:SI 2 "small_int" "IJK")))
7525 (clobber (match_operand:SI 3 "register_operand" "=d"))]
7526 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7527 && (INTVAL (operands[2]) & 63) < 32
7528 && (INTVAL (operands[2]) & 63) != 0"
7531 int amount = INTVAL (operands[2]);
7533 operands[2] = GEN_INT (amount & 31);
7534 operands[4] = GEN_INT ((-amount) & 31);
7536 return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
7538 [(set_attr "type" "darith")
7539 (set_attr "mode" "DI")
7540 (set_attr "length" "16")])
7544 [(set (match_operand:DI 0 "register_operand" "")
7545 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
7546 (match_operand:SI 2 "small_int" "")))
7547 (clobber (match_operand:SI 3 "register_operand" ""))]
7548 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
7549 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7550 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
7551 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
7552 && (INTVAL (operands[2]) & 63) < 32
7553 && (INTVAL (operands[2]) & 63) != 0"
7555 [(set (subreg:SI (match_dup 0) 0)
7556 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
7560 (ashift:SI (subreg:SI (match_dup 1) 4)
7563 (set (subreg:SI (match_dup 0) 0)
7564 (ior:SI (subreg:SI (match_dup 0) 0)
7567 (set (subreg:SI (match_dup 0) 4)
7568 (lshiftrt:SI (subreg:SI (match_dup 1) 4)
7572 int amount = INTVAL (operands[2]);
7573 operands[2] = GEN_INT (amount & 31);
7574 operands[4] = GEN_INT ((-amount) & 31);
7579 [(set (match_operand:DI 0 "register_operand" "")
7580 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
7581 (match_operand:SI 2 "small_int" "")))
7582 (clobber (match_operand:SI 3 "register_operand" ""))]
7583 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
7584 && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
7585 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
7586 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
7587 && (INTVAL (operands[2]) & 63) < 32
7588 && (INTVAL (operands[2]) & 63) != 0"
7590 [(set (subreg:SI (match_dup 0) 4)
7591 (lshiftrt:SI (subreg:SI (match_dup 1) 4)
7595 (ashift:SI (subreg:SI (match_dup 1) 0)
7598 (set (subreg:SI (match_dup 0) 4)
7599 (ior:SI (subreg:SI (match_dup 0) 4)
7602 (set (subreg:SI (match_dup 0) 0)
7603 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
7607 int amount = INTVAL (operands[2]);
7608 operands[2] = GEN_INT (amount & 31);
7609 operands[4] = GEN_INT ((-amount) & 31);
7613 (define_insn "lshrdi3_internal4"
7614 [(set (match_operand:DI 0 "register_operand" "=d")
7615 (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
7616 (match_operand:SI 2 "arith_operand" "dI")))]
7617 "TARGET_64BIT && !TARGET_MIPS16"
7620 if (GET_CODE (operands[2]) == CONST_INT)
7621 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7623 return \"dsrl\\t%0,%1,%2\";
7625 [(set_attr "type" "arith")
7626 (set_attr "mode" "DI")])
7629 [(set (match_operand:DI 0 "register_operand" "=d,d")
7630 (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "0,0")
7631 (match_operand:SI 2 "arith_operand" "d,I")))]
7632 "TARGET_64BIT && TARGET_MIPS16"
7635 if (GET_CODE (operands[2]) == CONST_INT)
7636 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
7638 return \"dsrl\\t%0,%2\";
7640 [(set_attr "type" "arith")
7641 (set_attr "mode" "DI")
7642 (set_attr_alternative "length"
7644 (if_then_else (match_operand:VOID 2 "m16_uimm3_b" "")
7648 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
7651 [(set (match_operand:DI 0 "register_operand" "")
7652 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
7653 (match_operand:SI 2 "const_int_operand" "")))]
7654 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
7655 && GET_CODE (operands[2]) == CONST_INT
7656 && INTVAL (operands[2]) > 8
7657 && INTVAL (operands[2]) <= 16"
7658 [(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 8)))
7659 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (match_dup 2)))]
7662 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
7667 ;; ....................
7671 ;; ....................
7673 ;; Flow here is rather complex:
7675 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
7676 ;; arguments into the branch_cmp array, and the type into
7677 ;; branch_type. No RTL is generated.
7679 ;; 2) The appropriate branch define_expand is called, which then
7680 ;; creates the appropriate RTL for the comparison and branch.
7681 ;; Different CC modes are used, based on what type of branch is
7682 ;; done, so that we can constrain things appropriately. There
7683 ;; are assumptions in the rest of GCC that break if we fold the
7684 ;; operands into the branchs for integer operations, and use cc0
7685 ;; for floating point, so we use the fp status register instead.
7686 ;; If needed, an appropriate temporary is created to hold the
7687 ;; of the integer compare.
7689 (define_expand "cmpsi"
7691 (compare:CC (match_operand:SI 0 "register_operand" "")
7692 (match_operand:SI 1 "arith_operand" "")))]
7696 if (operands[0]) /* avoid unused code message */
7698 branch_cmp[0] = operands[0];
7699 branch_cmp[1] = operands[1];
7700 branch_type = CMP_SI;
7705 (define_expand "tstsi"
7707 (match_operand:SI 0 "register_operand" ""))]
7711 if (operands[0]) /* avoid unused code message */
7713 branch_cmp[0] = operands[0];
7714 branch_cmp[1] = const0_rtx;
7715 branch_type = CMP_SI;
7720 (define_expand "cmpdi"
7722 (compare:CC (match_operand:DI 0 "se_register_operand" "")
7723 (match_operand:DI 1 "se_arith_operand" "")))]
7727 if (operands[0]) /* avoid unused code message */
7729 branch_cmp[0] = operands[0];
7730 branch_cmp[1] = operands[1];
7731 branch_type = CMP_DI;
7736 (define_expand "tstdi"
7738 (match_operand:DI 0 "se_register_operand" ""))]
7742 if (operands[0]) /* avoid unused code message */
7744 branch_cmp[0] = operands[0];
7745 branch_cmp[1] = const0_rtx;
7746 branch_type = CMP_DI;
7751 (define_expand "cmpdf"
7753 (compare:CC (match_operand:DF 0 "register_operand" "")
7754 (match_operand:DF 1 "register_operand" "")))]
7755 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7758 if (operands[0]) /* avoid unused code message */
7760 branch_cmp[0] = operands[0];
7761 branch_cmp[1] = operands[1];
7762 branch_type = CMP_DF;
7767 (define_expand "cmpsf"
7769 (compare:CC (match_operand:SF 0 "register_operand" "")
7770 (match_operand:SF 1 "register_operand" "")))]
7774 if (operands[0]) /* avoid unused code message */
7776 branch_cmp[0] = operands[0];
7777 branch_cmp[1] = operands[1];
7778 branch_type = CMP_SF;
7785 ;; ....................
7787 ;; CONDITIONAL BRANCHES
7789 ;; ....................
7791 ;; Conditional branches on floating-point equality tests.
7793 (define_insn "branch_fp"
7796 (match_operator:CC 0 "cmp_op"
7797 [(match_operand:CC 2 "register_operand" "z")
7799 (label_ref (match_operand 1 "" ""))
7804 return mips_output_conditional_branch (insn,
7806 /*two_operands_p=*/0,
7809 get_attr_length (insn));
7811 [(set_attr "type" "branch")
7812 (set_attr "mode" "none")])
7814 (define_insn "branch_fp_inverted"
7817 (match_operator:CC 0 "cmp_op"
7818 [(match_operand:CC 2 "register_operand" "z")
7821 (label_ref (match_operand 1 "" ""))))]
7825 return mips_output_conditional_branch (insn,
7827 /*two_operands_p=*/0,
7830 get_attr_length (insn));
7832 [(set_attr "type" "branch")
7833 (set_attr "mode" "none")])
7835 ;; Conditional branches on comparisons with zero.
7837 (define_insn "branch_zero"
7840 (match_operator:SI 0 "cmp_op"
7841 [(match_operand:SI 2 "register_operand" "d")
7843 (label_ref (match_operand 1 "" ""))
7848 return mips_output_conditional_branch (insn,
7850 /*two_operands_p=*/0,
7853 get_attr_length (insn));
7855 [(set_attr "type" "branch")
7856 (set_attr "mode" "none")])
7858 (define_insn "branch_zero_inverted"
7861 (match_operator:SI 0 "cmp_op"
7862 [(match_operand:SI 2 "register_operand" "d")
7865 (label_ref (match_operand 1 "" ""))))]
7869 return mips_output_conditional_branch (insn,
7871 /*two_operands_p=*/0,
7874 get_attr_length (insn));
7876 [(set_attr "type" "branch")
7877 (set_attr "mode" "none")])
7879 (define_insn "branch_zero_di"
7882 (match_operator:DI 0 "cmp_op"
7883 [(match_operand:DI 2 "se_register_operand" "d")
7885 (label_ref (match_operand 1 "" ""))
7890 return mips_output_conditional_branch (insn,
7892 /*two_operands_p=*/0,
7895 get_attr_length (insn));
7897 [(set_attr "type" "branch")
7898 (set_attr "mode" "none")])
7900 (define_insn "branch_zero_di_inverted"
7903 (match_operator:DI 0 "cmp_op"
7904 [(match_operand:DI 2 "se_register_operand" "d")
7907 (label_ref (match_operand 1 "" ""))))]
7911 return mips_output_conditional_branch (insn,
7913 /*two_operands_p=*/0,
7916 get_attr_length (insn));
7918 [(set_attr "type" "branch")
7919 (set_attr "mode" "none")])
7921 ;; Conditional branch on equality comparision.
7923 (define_insn "branch_equality"
7926 (match_operator:SI 0 "equality_op"
7927 [(match_operand:SI 2 "register_operand" "d")
7928 (match_operand:SI 3 "register_operand" "d")])
7929 (label_ref (match_operand 1 "" ""))
7934 return mips_output_conditional_branch (insn,
7936 /*two_operands_p=*/1,
7939 get_attr_length (insn));
7941 [(set_attr "type" "branch")
7942 (set_attr "mode" "none")])
7944 (define_insn "branch_equality_di"
7947 (match_operator:DI 0 "equality_op"
7948 [(match_operand:DI 2 "se_register_operand" "d")
7949 (match_operand:DI 3 "se_register_operand" "d")])
7950 (label_ref (match_operand 1 "" ""))
7955 return mips_output_conditional_branch (insn,
7957 /*two_operands_p=*/1,
7960 get_attr_length (insn));
7962 [(set_attr "type" "branch")
7963 (set_attr "mode" "none")])
7965 (define_insn "branch_equality_inverted"
7968 (match_operator:SI 0 "equality_op"
7969 [(match_operand:SI 2 "register_operand" "d")
7970 (match_operand:SI 3 "register_operand" "d")])
7972 (label_ref (match_operand 1 "" ""))))]
7976 return mips_output_conditional_branch (insn,
7978 /*two_operands_p=*/1,
7981 get_attr_length (insn));
7983 [(set_attr "type" "branch")
7984 (set_attr "mode" "none")])
7986 (define_insn "branch_equality_di_inverted"
7989 (match_operator:DI 0 "equality_op"
7990 [(match_operand:DI 2 "se_register_operand" "d")
7991 (match_operand:DI 3 "se_register_operand" "d")])
7993 (label_ref (match_operand 1 "" ""))))]
7997 return mips_output_conditional_branch (insn,
7999 /*two_operands_p=*/1,
8002 get_attr_length (insn));
8004 [(set_attr "type" "branch")
8005 (set_attr "mode" "none")])
8011 (if_then_else (match_operator:SI 0 "equality_op"
8012 [(match_operand:SI 1 "register_operand" "d,t")
8014 (match_operand 2 "pc_or_label_operand" "")
8015 (match_operand 3 "pc_or_label_operand" "")))]
8019 if (operands[2] != pc_rtx)
8021 if (which_alternative == 0)
8022 return \"%*b%C0z\\t%1,%2\";
8024 return \"%*bt%C0z\\t%2\";
8028 if (which_alternative == 0)
8029 return \"%*b%N0z\\t%1,%3\";
8031 return \"%*bt%N0z\\t%3\";
8034 [(set_attr "type" "branch")
8035 (set_attr "mode" "none")
8036 (set_attr "length" "8")])
8040 (if_then_else (match_operator:DI 0 "equality_op"
8041 [(match_operand:DI 1 "se_register_operand" "d,t")
8043 (match_operand 2 "pc_or_label_operand" "")
8044 (match_operand 3 "pc_or_label_operand" "")))]
8048 if (operands[2] != pc_rtx)
8050 if (which_alternative == 0)
8051 return \"%*b%C0z\\t%1,%2\";
8053 return \"%*bt%C0z\\t%2\";
8057 if (which_alternative == 0)
8058 return \"%*b%N0z\\t%1,%3\";
8060 return \"%*bt%N0z\\t%3\";
8063 [(set_attr "type" "branch")
8064 (set_attr "mode" "none")
8065 (set_attr "length" "8")])
8067 (define_expand "bunordered"
8069 (if_then_else (unordered:CC (cc0)
8071 (label_ref (match_operand 0 "" ""))
8076 if (operands[0]) /* avoid unused code warning */
8078 gen_conditional_branch (operands, UNORDERED);
8083 (define_expand "bordered"
8085 (if_then_else (ordered:CC (cc0)
8087 (label_ref (match_operand 0 "" ""))
8092 if (operands[0]) /* avoid unused code warning */
8094 gen_conditional_branch (operands, ORDERED);
8099 (define_expand "bunlt"
8101 (if_then_else (unlt:CC (cc0)
8103 (label_ref (match_operand 0 "" ""))
8108 if (operands[0]) /* avoid unused code warning */
8110 gen_conditional_branch (operands, UNLT);
8115 (define_expand "buneq"
8117 (if_then_else (uneq:CC (cc0)
8119 (label_ref (match_operand 0 "" ""))
8124 if (operands[0]) /* avoid unused code warning */
8126 gen_conditional_branch (operands, UNEQ);
8131 (define_expand "bunle"
8133 (if_then_else (unle:CC (cc0)
8135 (label_ref (match_operand 0 "" ""))
8140 if (operands[0]) /* avoid unused code warning */
8142 gen_conditional_branch (operands, UNLE);
8147 (define_expand "beq"
8149 (if_then_else (eq:CC (cc0)
8151 (label_ref (match_operand 0 "" ""))
8156 if (operands[0]) /* avoid unused code warning */
8158 gen_conditional_branch (operands, EQ);
8163 (define_expand "bne"
8165 (if_then_else (ne:CC (cc0)
8167 (label_ref (match_operand 0 "" ""))
8172 if (operands[0]) /* avoid unused code warning */
8174 gen_conditional_branch (operands, NE);
8179 (define_expand "bgt"
8181 (if_then_else (gt:CC (cc0)
8183 (label_ref (match_operand 0 "" ""))
8188 if (operands[0]) /* avoid unused code warning */
8190 gen_conditional_branch (operands, GT);
8195 (define_expand "bge"
8197 (if_then_else (ge:CC (cc0)
8199 (label_ref (match_operand 0 "" ""))
8204 if (operands[0]) /* avoid unused code warning */
8206 gen_conditional_branch (operands, GE);
8211 (define_expand "blt"
8213 (if_then_else (lt:CC (cc0)
8215 (label_ref (match_operand 0 "" ""))
8220 if (operands[0]) /* avoid unused code warning */
8222 gen_conditional_branch (operands, LT);
8227 (define_expand "ble"
8229 (if_then_else (le:CC (cc0)
8231 (label_ref (match_operand 0 "" ""))
8236 if (operands[0]) /* avoid unused code warning */
8238 gen_conditional_branch (operands, LE);
8243 (define_expand "bgtu"
8245 (if_then_else (gtu:CC (cc0)
8247 (label_ref (match_operand 0 "" ""))
8252 if (operands[0]) /* avoid unused code warning */
8254 gen_conditional_branch (operands, GTU);
8259 (define_expand "bgeu"
8261 (if_then_else (geu:CC (cc0)
8263 (label_ref (match_operand 0 "" ""))
8268 if (operands[0]) /* avoid unused code warning */
8270 gen_conditional_branch (operands, GEU);
8276 (define_expand "bltu"
8278 (if_then_else (ltu:CC (cc0)
8280 (label_ref (match_operand 0 "" ""))
8285 if (operands[0]) /* avoid unused code warning */
8287 gen_conditional_branch (operands, LTU);
8292 (define_expand "bleu"
8294 (if_then_else (leu:CC (cc0)
8296 (label_ref (match_operand 0 "" ""))
8301 if (operands[0]) /* avoid unused code warning */
8303 gen_conditional_branch (operands, LEU);
8310 ;; ....................
8312 ;; SETTING A REGISTER FROM A COMPARISON
8314 ;; ....................
8316 (define_expand "seq"
8317 [(set (match_operand:SI 0 "register_operand" "=d")
8318 (eq:SI (match_dup 1)
8323 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8326 /* set up operands from compare. */
8327 operands[1] = branch_cmp[0];
8328 operands[2] = branch_cmp[1];
8330 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8332 gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
8336 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
8337 operands[2] = force_reg (SImode, operands[2]);
8339 /* fall through and generate default code */
8343 (define_insn "seq_si_zero"
8344 [(set (match_operand:SI 0 "register_operand" "=d")
8345 (eq:SI (match_operand:SI 1 "register_operand" "d")
8349 [(set_attr "type" "arith")
8350 (set_attr "mode" "SI")])
8353 [(set (match_operand:SI 0 "register_operand" "=t")
8354 (eq:SI (match_operand:SI 1 "register_operand" "d")
8358 [(set_attr "type" "arith")
8359 (set_attr "mode" "SI")])
8361 (define_insn "seq_di_zero"
8362 [(set (match_operand:DI 0 "register_operand" "=d")
8363 (eq:DI (match_operand:DI 1 "se_register_operand" "d")
8365 "TARGET_64BIT && !TARGET_MIPS16"
8367 [(set_attr "type" "arith")
8368 (set_attr "mode" "DI")])
8371 [(set (match_operand:DI 0 "register_operand" "=t")
8372 (eq:DI (match_operand:DI 1 "se_register_operand" "d")
8374 "TARGET_64BIT && TARGET_MIPS16"
8376 [(set_attr "type" "arith")
8377 (set_attr "mode" "DI")])
8379 (define_insn "seq_si"
8380 [(set (match_operand:SI 0 "register_operand" "=d,d")
8381 (eq:SI (match_operand:SI 1 "register_operand" "%d,d")
8382 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
8383 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8385 xor\\t%0,%1,%2\;sltu\\t%0,%0,1
8386 xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
8387 [(set_attr "type" "arith")
8388 (set_attr "mode" "SI")
8389 (set_attr "length" "8")])
8392 [(set (match_operand:SI 0 "register_operand" "")
8393 (eq:SI (match_operand:SI 1 "register_operand" "")
8394 (match_operand:SI 2 "uns_arith_operand" "")))]
8395 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
8396 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8398 (xor:SI (match_dup 1)
8401 (ltu:SI (match_dup 0)
8405 (define_insn "seq_di"
8406 [(set (match_operand:DI 0 "register_operand" "=d,d")
8407 (eq:DI (match_operand:DI 1 "se_register_operand" "%d,d")
8408 (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
8409 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8411 xor\\t%0,%1,%2\;sltu\\t%0,%0,1
8412 xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
8413 [(set_attr "type" "arith")
8414 (set_attr "mode" "DI")
8415 (set_attr "length" "8")])
8418 [(set (match_operand:DI 0 "register_operand" "")
8419 (eq:DI (match_operand:DI 1 "se_register_operand" "")
8420 (match_operand:DI 2 "se_uns_arith_operand" "")))]
8421 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
8423 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8425 (xor:DI (match_dup 1)
8428 (ltu:DI (match_dup 0)
8432 ;; On the mips16 the default code is better than using sltu.
8434 (define_expand "sne"
8435 [(set (match_operand:SI 0 "register_operand" "=d")
8436 (ne:SI (match_dup 1)
8441 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8444 /* set up operands from compare. */
8445 operands[1] = branch_cmp[0];
8446 operands[2] = branch_cmp[1];
8448 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
8450 gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
8454 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
8455 operands[2] = force_reg (SImode, operands[2]);
8457 /* fall through and generate default code */
8460 (define_insn "sne_si_zero"
8461 [(set (match_operand:SI 0 "register_operand" "=d")
8462 (ne:SI (match_operand:SI 1 "register_operand" "d")
8466 [(set_attr "type" "arith")
8467 (set_attr "mode" "SI")])
8469 (define_insn "sne_di_zero"
8470 [(set (match_operand:DI 0 "register_operand" "=d")
8471 (ne:DI (match_operand:DI 1 "se_register_operand" "d")
8473 "TARGET_64BIT && !TARGET_MIPS16"
8475 [(set_attr "type" "arith")
8476 (set_attr "mode" "DI")])
8478 (define_insn "sne_si"
8479 [(set (match_operand:SI 0 "register_operand" "=d,d")
8480 (ne:SI (match_operand:SI 1 "register_operand" "%d,d")
8481 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
8482 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8484 xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
8485 xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
8486 [(set_attr "type" "arith")
8487 (set_attr "mode" "SI")
8488 (set_attr "length" "8")])
8491 [(set (match_operand:SI 0 "register_operand" "")
8492 (ne:SI (match_operand:SI 1 "register_operand" "")
8493 (match_operand:SI 2 "uns_arith_operand" "")))]
8494 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
8495 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8497 (xor:SI (match_dup 1)
8500 (gtu:SI (match_dup 0)
8504 (define_insn "sne_di"
8505 [(set (match_operand:DI 0 "register_operand" "=d,d")
8506 (ne:DI (match_operand:DI 1 "se_register_operand" "%d,d")
8507 (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
8508 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8510 xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
8511 xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
8512 [(set_attr "type" "arith")
8513 (set_attr "mode" "DI")
8514 (set_attr "length" "8")])
8517 [(set (match_operand:DI 0 "register_operand" "")
8518 (ne:DI (match_operand:DI 1 "se_register_operand" "")
8519 (match_operand:DI 2 "se_uns_arith_operand" "")))]
8520 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
8522 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
8524 (xor:DI (match_dup 1)
8527 (gtu:DI (match_dup 0)
8531 (define_expand "sgt"
8532 [(set (match_operand:SI 0 "register_operand" "=d")
8533 (gt:SI (match_dup 1)
8538 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8541 /* set up operands from compare. */
8542 operands[1] = branch_cmp[0];
8543 operands[2] = branch_cmp[1];
8545 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8547 gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
8551 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
8552 operands[2] = force_reg (SImode, operands[2]);
8554 /* fall through and generate default code */
8557 (define_insn "sgt_si"
8558 [(set (match_operand:SI 0 "register_operand" "=d")
8559 (gt:SI (match_operand:SI 1 "register_operand" "d")
8560 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
8563 [(set_attr "type" "arith")
8564 (set_attr "mode" "SI")])
8567 [(set (match_operand:SI 0 "register_operand" "=t")
8568 (gt:SI (match_operand:SI 1 "register_operand" "d")
8569 (match_operand:SI 2 "register_operand" "d")))]
8572 [(set_attr "type" "arith")
8573 (set_attr "mode" "SI")])
8575 (define_insn "sgt_di"
8576 [(set (match_operand:DI 0 "register_operand" "=d")
8577 (gt:DI (match_operand:DI 1 "se_register_operand" "d")
8578 (match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
8579 "TARGET_64BIT && !TARGET_MIPS16"
8581 [(set_attr "type" "arith")
8582 (set_attr "mode" "DI")])
8585 [(set (match_operand:DI 0 "register_operand" "=d")
8586 (gt:DI (match_operand:DI 1 "se_register_operand" "d")
8587 (match_operand:DI 2 "se_register_operand" "d")))]
8588 "TARGET_64BIT && TARGET_MIPS16"
8590 [(set_attr "type" "arith")
8591 (set_attr "mode" "DI")])
8593 (define_expand "sge"
8594 [(set (match_operand:SI 0 "register_operand" "=d")
8595 (ge:SI (match_dup 1)
8600 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8603 /* set up operands from compare. */
8604 operands[1] = branch_cmp[0];
8605 operands[2] = branch_cmp[1];
8607 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8609 gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
8613 /* fall through and generate default code */
8616 (define_insn "sge_si"
8617 [(set (match_operand:SI 0 "register_operand" "=d")
8618 (ge:SI (match_operand:SI 1 "register_operand" "d")
8619 (match_operand:SI 2 "arith_operand" "dI")))]
8620 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8621 "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
8622 [(set_attr "type" "arith")
8623 (set_attr "mode" "SI")
8624 (set_attr "length" "8")])
8627 [(set (match_operand:SI 0 "register_operand" "")
8628 (ge:SI (match_operand:SI 1 "register_operand" "")
8629 (match_operand:SI 2 "arith_operand" "")))]
8630 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
8632 (lt:SI (match_dup 1)
8635 (xor:SI (match_dup 0)
8639 (define_insn "sge_di"
8640 [(set (match_operand:DI 0 "register_operand" "=d")
8641 (ge:DI (match_operand:DI 1 "se_register_operand" "d")
8642 (match_operand:DI 2 "se_arith_operand" "dI")))]
8643 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8644 "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
8645 [(set_attr "type" "arith")
8646 (set_attr "mode" "DI")
8647 (set_attr "length" "8")])
8650 [(set (match_operand:DI 0 "register_operand" "")
8651 (ge:DI (match_operand:DI 1 "se_register_operand" "")
8652 (match_operand:DI 2 "se_arith_operand" "")))]
8653 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
8656 (lt:DI (match_dup 1)
8659 (xor:DI (match_dup 0)
8663 (define_expand "slt"
8664 [(set (match_operand:SI 0 "register_operand" "=d")
8665 (lt:SI (match_dup 1)
8670 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8673 /* set up operands from compare. */
8674 operands[1] = branch_cmp[0];
8675 operands[2] = branch_cmp[1];
8677 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8679 gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
8683 /* fall through and generate default code */
8686 (define_insn "slt_si"
8687 [(set (match_operand:SI 0 "register_operand" "=d")
8688 (lt:SI (match_operand:SI 1 "register_operand" "d")
8689 (match_operand:SI 2 "arith_operand" "dI")))]
8692 [(set_attr "type" "arith")
8693 (set_attr "mode" "SI")])
8696 [(set (match_operand:SI 0 "register_operand" "=t,t")
8697 (lt:SI (match_operand:SI 1 "register_operand" "d,d")
8698 (match_operand:SI 2 "arith_operand" "d,I")))]
8701 [(set_attr "type" "arith")
8702 (set_attr "mode" "SI")
8703 (set_attr_alternative "length"
8705 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
8709 (define_insn "slt_di"
8710 [(set (match_operand:DI 0 "register_operand" "=d")
8711 (lt:DI (match_operand:DI 1 "se_register_operand" "d")
8712 (match_operand:DI 2 "se_arith_operand" "dI")))]
8713 "TARGET_64BIT && !TARGET_MIPS16"
8715 [(set_attr "type" "arith")
8716 (set_attr "mode" "DI")])
8719 [(set (match_operand:DI 0 "register_operand" "=t,t")
8720 (lt:DI (match_operand:DI 1 "se_register_operand" "d,d")
8721 (match_operand:DI 2 "se_arith_operand" "d,I")))]
8722 "TARGET_64BIT && TARGET_MIPS16"
8724 [(set_attr "type" "arith")
8725 (set_attr "mode" "DI")
8726 (set_attr_alternative "length"
8728 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
8732 (define_expand "sle"
8733 [(set (match_operand:SI 0 "register_operand" "=d")
8734 (le:SI (match_dup 1)
8739 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8742 /* set up operands from compare. */
8743 operands[1] = branch_cmp[0];
8744 operands[2] = branch_cmp[1];
8746 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8748 gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
8752 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
8753 operands[2] = force_reg (SImode, operands[2]);
8755 /* fall through and generate default code */
8758 (define_insn "sle_si_const"
8759 [(set (match_operand:SI 0 "register_operand" "=d")
8760 (le:SI (match_operand:SI 1 "register_operand" "d")
8761 (match_operand:SI 2 "small_int" "I")))]
8762 "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
8765 operands[2] = GEN_INT (INTVAL (operands[2])+1);
8766 return \"slt\\t%0,%1,%2\";
8768 [(set_attr "type" "arith")
8769 (set_attr "mode" "SI")])
8772 [(set (match_operand:SI 0 "register_operand" "=t")
8773 (le:SI (match_operand:SI 1 "register_operand" "d")
8774 (match_operand:SI 2 "small_int" "I")))]
8775 "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
8778 operands[2] = GEN_INT (INTVAL (operands[2])+1);
8779 return \"slt\\t%1,%2\";
8781 [(set_attr "type" "arith")
8782 (set_attr "mode" "SI")
8783 (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
8787 (define_insn "sle_di_const"
8788 [(set (match_operand:DI 0 "register_operand" "=d")
8789 (le:DI (match_operand:DI 1 "se_register_operand" "d")
8790 (match_operand:DI 2 "small_int" "I")))]
8791 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
8794 operands[2] = GEN_INT (INTVAL (operands[2])+1);
8795 return \"slt\\t%0,%1,%2\";
8797 [(set_attr "type" "arith")
8798 (set_attr "mode" "DI")])
8801 [(set (match_operand:DI 0 "register_operand" "=t")
8802 (le:DI (match_operand:DI 1 "se_register_operand" "d")
8803 (match_operand:DI 2 "small_int" "I")))]
8804 "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
8807 operands[2] = GEN_INT (INTVAL (operands[2])+1);
8808 return \"slt\\t%1,%2\";
8810 [(set_attr "type" "arith")
8811 (set_attr "mode" "DI")
8812 (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
8816 (define_insn "sle_si_reg"
8817 [(set (match_operand:SI 0 "register_operand" "=d")
8818 (le:SI (match_operand:SI 1 "register_operand" "d")
8819 (match_operand:SI 2 "register_operand" "d")))]
8820 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8821 "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
8822 [(set_attr "type" "arith")
8823 (set_attr "mode" "SI")
8824 (set_attr "length" "8")])
8827 [(set (match_operand:SI 0 "register_operand" "")
8828 (le:SI (match_operand:SI 1 "register_operand" "")
8829 (match_operand:SI 2 "register_operand" "")))]
8830 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
8832 (lt:SI (match_dup 2)
8835 (xor:SI (match_dup 0)
8839 (define_insn "sle_di_reg"
8840 [(set (match_operand:DI 0 "register_operand" "=d")
8841 (le:DI (match_operand:DI 1 "se_register_operand" "d")
8842 (match_operand:DI 2 "se_register_operand" "d")))]
8843 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8844 "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
8845 [(set_attr "type" "arith")
8846 (set_attr "mode" "DI")
8847 (set_attr "length" "8")])
8850 [(set (match_operand:DI 0 "register_operand" "")
8851 (le:DI (match_operand:DI 1 "se_register_operand" "")
8852 (match_operand:DI 2 "se_register_operand" "")))]
8853 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
8856 (lt:DI (match_dup 2)
8859 (xor:DI (match_dup 0)
8863 (define_expand "sgtu"
8864 [(set (match_operand:SI 0 "register_operand" "=d")
8865 (gtu:SI (match_dup 1)
8870 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8873 /* set up operands from compare. */
8874 operands[1] = branch_cmp[0];
8875 operands[2] = branch_cmp[1];
8877 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8879 gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
8883 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
8884 operands[2] = force_reg (SImode, operands[2]);
8886 /* fall through and generate default code */
8889 (define_insn "sgtu_si"
8890 [(set (match_operand:SI 0 "register_operand" "=d")
8891 (gtu:SI (match_operand:SI 1 "register_operand" "d")
8892 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
8895 [(set_attr "type" "arith")
8896 (set_attr "mode" "SI")])
8899 [(set (match_operand:SI 0 "register_operand" "=t")
8900 (gtu:SI (match_operand:SI 1 "register_operand" "d")
8901 (match_operand:SI 2 "register_operand" "d")))]
8904 [(set_attr "type" "arith")
8905 (set_attr "mode" "SI")])
8907 (define_insn "sgtu_di"
8908 [(set (match_operand:DI 0 "register_operand" "=d")
8909 (gtu:DI (match_operand:DI 1 "se_register_operand" "d")
8910 (match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
8913 [(set_attr "type" "arith")
8914 (set_attr "mode" "DI")])
8917 [(set (match_operand:DI 0 "register_operand" "=t")
8918 (gtu:DI (match_operand:DI 1 "se_register_operand" "d")
8919 (match_operand:DI 2 "se_register_operand" "d")))]
8922 [(set_attr "type" "arith")
8923 (set_attr "mode" "DI")])
8925 (define_expand "sgeu"
8926 [(set (match_operand:SI 0 "register_operand" "=d")
8927 (geu:SI (match_dup 1)
8932 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
8935 /* set up operands from compare. */
8936 operands[1] = branch_cmp[0];
8937 operands[2] = branch_cmp[1];
8939 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
8941 gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
8945 /* fall through and generate default code */
8948 (define_insn "sgeu_si"
8949 [(set (match_operand:SI 0 "register_operand" "=d")
8950 (geu:SI (match_operand:SI 1 "register_operand" "d")
8951 (match_operand:SI 2 "arith_operand" "dI")))]
8952 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8953 "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
8954 [(set_attr "type" "arith")
8955 (set_attr "mode" "SI")
8956 (set_attr "length" "8")])
8959 [(set (match_operand:SI 0 "register_operand" "")
8960 (geu:SI (match_operand:SI 1 "register_operand" "")
8961 (match_operand:SI 2 "arith_operand" "")))]
8962 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
8964 (ltu:SI (match_dup 1)
8967 (xor:SI (match_dup 0)
8971 (define_insn "sgeu_di"
8972 [(set (match_operand:DI 0 "register_operand" "=d")
8973 (geu:DI (match_operand:DI 1 "se_register_operand" "d")
8974 (match_operand:DI 2 "se_arith_operand" "dI")))]
8975 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
8976 "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
8977 [(set_attr "type" "arith")
8978 (set_attr "mode" "DI")
8979 (set_attr "length" "8")])
8982 [(set (match_operand:DI 0 "register_operand" "")
8983 (geu:DI (match_operand:DI 1 "se_register_operand" "")
8984 (match_operand:DI 2 "se_arith_operand" "")))]
8985 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
8988 (ltu:DI (match_dup 1)
8991 (xor:DI (match_dup 0)
8995 (define_expand "sltu"
8996 [(set (match_operand:SI 0 "register_operand" "=d")
8997 (ltu:SI (match_dup 1)
9002 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
9005 /* set up operands from compare. */
9006 operands[1] = branch_cmp[0];
9007 operands[2] = branch_cmp[1];
9009 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
9011 gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
9015 /* fall through and generate default code */
9018 (define_insn "sltu_si"
9019 [(set (match_operand:SI 0 "register_operand" "=d")
9020 (ltu:SI (match_operand:SI 1 "register_operand" "d")
9021 (match_operand:SI 2 "arith_operand" "dI")))]
9024 [(set_attr "type" "arith")
9025 (set_attr "mode" "SI")])
9028 [(set (match_operand:SI 0 "register_operand" "=t,t")
9029 (ltu:SI (match_operand:SI 1 "register_operand" "d,d")
9030 (match_operand:SI 2 "arith_operand" "d,I")))]
9033 [(set_attr "type" "arith")
9034 (set_attr "mode" "SI")
9035 (set_attr_alternative "length"
9037 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
9041 (define_insn "sltu_di"
9042 [(set (match_operand:DI 0 "register_operand" "=d")
9043 (ltu:DI (match_operand:DI 1 "se_register_operand" "d")
9044 (match_operand:DI 2 "se_arith_operand" "dI")))]
9045 "TARGET_64BIT && !TARGET_MIPS16"
9047 [(set_attr "type" "arith")
9048 (set_attr "mode" "DI")])
9051 [(set (match_operand:DI 0 "register_operand" "=t,t")
9052 (ltu:DI (match_operand:DI 1 "se_register_operand" "d,d")
9053 (match_operand:DI 2 "se_arith_operand" "d,I")))]
9054 "TARGET_64BIT && TARGET_MIPS16"
9056 [(set_attr "type" "arith")
9057 (set_attr "mode" "DI")
9058 (set_attr_alternative "length"
9060 (if_then_else (match_operand:VOID 2 "m16_uimm8_1" "")
9064 (define_expand "sleu"
9065 [(set (match_operand:SI 0 "register_operand" "=d")
9066 (leu:SI (match_dup 1)
9071 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
9074 /* set up operands from compare. */
9075 operands[1] = branch_cmp[0];
9076 operands[2] = branch_cmp[1];
9078 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
9080 gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
9084 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
9085 operands[2] = force_reg (SImode, operands[2]);
9087 /* fall through and generate default code */
9090 (define_insn "sleu_si_const"
9091 [(set (match_operand:SI 0 "register_operand" "=d")
9092 (leu:SI (match_operand:SI 1 "register_operand" "d")
9093 (match_operand:SI 2 "small_int" "I")))]
9094 "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
9097 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
9098 return \"sltu\\t%0,%1,%2\";
9100 [(set_attr "type" "arith")
9101 (set_attr "mode" "SI")])
9104 [(set (match_operand:SI 0 "register_operand" "=t")
9105 (leu:SI (match_operand:SI 1 "register_operand" "d")
9106 (match_operand:SI 2 "small_int" "I")))]
9107 "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
9110 operands[2] = GEN_INT (INTVAL (operands[2])+1);
9111 return \"sltu\\t%1,%2\";
9113 [(set_attr "type" "arith")
9114 (set_attr "mode" "SI")
9115 (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
9119 (define_insn "sleu_di_const"
9120 [(set (match_operand:DI 0 "register_operand" "=d")
9121 (leu:DI (match_operand:DI 1 "se_register_operand" "d")
9122 (match_operand:DI 2 "small_int" "I")))]
9123 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
9126 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
9127 return \"sltu\\t%0,%1,%2\";
9129 [(set_attr "type" "arith")
9130 (set_attr "mode" "DI")])
9133 [(set (match_operand:DI 0 "register_operand" "=t")
9134 (leu:DI (match_operand:DI 1 "se_register_operand" "d")
9135 (match_operand:DI 2 "small_int" "I")))]
9136 "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
9139 operands[2] = GEN_INT (INTVAL (operands[2])+1);
9140 return \"sltu\\t%1,%2\";
9142 [(set_attr "type" "arith")
9143 (set_attr "mode" "DI")
9144 (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
9148 (define_insn "sleu_si_reg"
9149 [(set (match_operand:SI 0 "register_operand" "=d")
9150 (leu:SI (match_operand:SI 1 "register_operand" "d")
9151 (match_operand:SI 2 "register_operand" "d")))]
9152 "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
9153 "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
9154 [(set_attr "type" "arith")
9155 (set_attr "mode" "SI")
9156 (set_attr "length" "8")])
9159 [(set (match_operand:SI 0 "register_operand" "")
9160 (leu:SI (match_operand:SI 1 "register_operand" "")
9161 (match_operand:SI 2 "register_operand" "")))]
9162 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
9164 (ltu:SI (match_dup 2)
9167 (xor:SI (match_dup 0)
9171 (define_insn "sleu_di_reg"
9172 [(set (match_operand:DI 0 "register_operand" "=d")
9173 (leu:DI (match_operand:DI 1 "se_register_operand" "d")
9174 (match_operand:DI 2 "se_register_operand" "d")))]
9175 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
9176 "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
9177 [(set_attr "type" "arith")
9178 (set_attr "mode" "DI")
9179 (set_attr "length" "8")])
9182 [(set (match_operand:DI 0 "register_operand" "")
9183 (leu:DI (match_operand:DI 1 "se_register_operand" "")
9184 (match_operand:DI 2 "se_register_operand" "")))]
9185 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
9188 (ltu:DI (match_dup 2)
9191 (xor:DI (match_dup 0)
9197 ;; ....................
9199 ;; FLOATING POINT COMPARISONS
9201 ;; ....................
9203 (define_insn "sunordered_df"
9204 [(set (match_operand:CC 0 "register_operand" "=z")
9205 (unordered:CC (match_operand:DF 1 "register_operand" "f")
9206 (match_operand:DF 2 "register_operand" "f")))]
9207 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9210 return mips_fill_delay_slot (\"c.un.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9212 [(set_attr "type" "fcmp")
9213 (set_attr "mode" "FPSW")])
9215 (define_insn "sordered_df"
9216 [(set (match_operand:CC 0 "register_operand" "=z")
9217 (ordered:CC (match_operand:DF 1 "register_operand" "f")
9218 (match_operand:DF 2 "register_operand" "f")))]
9219 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9222 return mips_fill_delay_slot (\"c.or.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9224 [(set_attr "type" "fcmp")
9225 (set_attr "mode" "FPSW")])
9227 (define_insn "sunlt_df"
9228 [(set (match_operand:CC 0 "register_operand" "=z")
9229 (unlt:CC (match_operand:DF 1 "register_operand" "f")
9230 (match_operand:DF 2 "register_operand" "f")))]
9231 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9234 return mips_fill_delay_slot (\"c.ult.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9236 [(set_attr "type" "fcmp")
9237 (set_attr "mode" "FPSW")])
9239 (define_insn "suneq_df"
9240 [(set (match_operand:CC 0 "register_operand" "=z")
9241 (uneq:CC (match_operand:DF 1 "register_operand" "f")
9242 (match_operand:DF 2 "register_operand" "f")))]
9243 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9246 return mips_fill_delay_slot (\"c.ueq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9248 [(set_attr "type" "fcmp")
9249 (set_attr "mode" "FPSW")])
9251 (define_insn "sunle_df"
9252 [(set (match_operand:CC 0 "register_operand" "=z")
9253 (unle:CC (match_operand:DF 1 "register_operand" "f")
9254 (match_operand:DF 2 "register_operand" "f")))]
9255 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9258 return mips_fill_delay_slot (\"c.ule.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9260 [(set_attr "type" "fcmp")
9261 (set_attr "mode" "FPSW")])
9263 (define_insn "seq_df"
9264 [(set (match_operand:CC 0 "register_operand" "=z")
9265 (eq:CC (match_operand:DF 1 "register_operand" "f")
9266 (match_operand:DF 2 "register_operand" "f")))]
9267 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9270 return mips_fill_delay_slot (\"c.eq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9272 [(set_attr "type" "fcmp")
9273 (set_attr "mode" "FPSW")])
9275 (define_insn "slt_df"
9276 [(set (match_operand:CC 0 "register_operand" "=z")
9277 (lt:CC (match_operand:DF 1 "register_operand" "f")
9278 (match_operand:DF 2 "register_operand" "f")))]
9279 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9282 return mips_fill_delay_slot (\"c.lt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9284 [(set_attr "type" "fcmp")
9285 (set_attr "mode" "FPSW")])
9287 (define_insn "sle_df"
9288 [(set (match_operand:CC 0 "register_operand" "=z")
9289 (le:CC (match_operand:DF 1 "register_operand" "f")
9290 (match_operand:DF 2 "register_operand" "f")))]
9291 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9294 return mips_fill_delay_slot (\"c.le.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9296 [(set_attr "type" "fcmp")
9297 (set_attr "mode" "FPSW")])
9299 (define_insn "sgt_df"
9300 [(set (match_operand:CC 0 "register_operand" "=z")
9301 (gt:CC (match_operand:DF 1 "register_operand" "f")
9302 (match_operand:DF 2 "register_operand" "f")))]
9303 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9306 return mips_fill_delay_slot (\"c.lt.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
9308 [(set_attr "type" "fcmp")
9309 (set_attr "mode" "FPSW")])
9311 (define_insn "sge_df"
9312 [(set (match_operand:CC 0 "register_operand" "=z")
9313 (ge:CC (match_operand:DF 1 "register_operand" "f")
9314 (match_operand:DF 2 "register_operand" "f")))]
9315 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9318 return mips_fill_delay_slot (\"c.le.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
9320 [(set_attr "type" "fcmp")
9321 (set_attr "mode" "FPSW")])
9323 (define_insn "sunordered_sf"
9324 [(set (match_operand:CC 0 "register_operand" "=z")
9325 (unordered:CC (match_operand:SF 1 "register_operand" "f")
9326 (match_operand:SF 2 "register_operand" "f")))]
9330 return mips_fill_delay_slot (\"c.un.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9332 [(set_attr "type" "fcmp")
9333 (set_attr "mode" "FPSW")])
9335 (define_insn "sordered_sf"
9336 [(set (match_operand:CC 0 "register_operand" "=z")
9337 (ordered:CC (match_operand:SF 1 "register_operand" "f")
9338 (match_operand:SF 2 "register_operand" "f")))]
9342 return mips_fill_delay_slot (\"c.or.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9344 [(set_attr "type" "fcmp")
9345 (set_attr "mode" "FPSW")])
9347 (define_insn "sunlt_sf"
9348 [(set (match_operand:CC 0 "register_operand" "=z")
9349 (unlt:CC (match_operand:SF 1 "register_operand" "f")
9350 (match_operand:SF 2 "register_operand" "f")))]
9351 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9354 return mips_fill_delay_slot (\"c.ult.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9356 [(set_attr "type" "fcmp")
9357 (set_attr "mode" "FPSW")])
9359 (define_insn "suneq_sf"
9360 [(set (match_operand:CC 0 "register_operand" "=z")
9361 (uneq:CC (match_operand:SF 1 "register_operand" "f")
9362 (match_operand:SF 2 "register_operand" "f")))]
9363 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9366 return mips_fill_delay_slot (\"c.ueq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9368 [(set_attr "type" "fcmp")
9369 (set_attr "mode" "FPSW")])
9371 (define_insn "sunle_sf"
9372 [(set (match_operand:CC 0 "register_operand" "=z")
9373 (unle:CC (match_operand:SF 1 "register_operand" "f")
9374 (match_operand:SF 2 "register_operand" "f")))]
9375 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
9378 return mips_fill_delay_slot (\"c.ule.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9380 [(set_attr "type" "fcmp")
9381 (set_attr "mode" "FPSW")])
9383 (define_insn "seq_sf"
9384 [(set (match_operand:CC 0 "register_operand" "=z")
9385 (eq:CC (match_operand:SF 1 "register_operand" "f")
9386 (match_operand:SF 2 "register_operand" "f")))]
9390 return mips_fill_delay_slot (\"c.eq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9392 [(set_attr "type" "fcmp")
9393 (set_attr "mode" "FPSW")])
9395 (define_insn "slt_sf"
9396 [(set (match_operand:CC 0 "register_operand" "=z")
9397 (lt:CC (match_operand:SF 1 "register_operand" "f")
9398 (match_operand:SF 2 "register_operand" "f")))]
9402 return mips_fill_delay_slot (\"c.lt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9404 [(set_attr "type" "fcmp")
9405 (set_attr "mode" "FPSW")])
9407 (define_insn "sle_sf"
9408 [(set (match_operand:CC 0 "register_operand" "=z")
9409 (le:CC (match_operand:SF 1 "register_operand" "f")
9410 (match_operand:SF 2 "register_operand" "f")))]
9414 return mips_fill_delay_slot (\"c.le.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
9416 [(set_attr "type" "fcmp")
9417 (set_attr "mode" "FPSW")])
9419 (define_insn "sgt_sf"
9420 [(set (match_operand:CC 0 "register_operand" "=z")
9421 (gt:CC (match_operand:SF 1 "register_operand" "f")
9422 (match_operand:SF 2 "register_operand" "f")))]
9426 return mips_fill_delay_slot (\"c.lt.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
9428 [(set_attr "type" "fcmp")
9429 (set_attr "mode" "FPSW")])
9431 (define_insn "sge_sf"
9432 [(set (match_operand:CC 0 "register_operand" "=z")
9433 (ge:CC (match_operand:SF 1 "register_operand" "f")
9434 (match_operand:SF 2 "register_operand" "f")))]
9438 return mips_fill_delay_slot (\"c.le.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
9440 [(set_attr "type" "fcmp")
9441 (set_attr "mode" "FPSW")])
9445 ;; ....................
9447 ;; UNCONDITIONAL BRANCHES
9449 ;; ....................
9451 ;; Unconditional branches.
9455 (label_ref (match_operand 0 "" "")))]
9459 if (GET_CODE (operands[0]) == REG)
9460 return \"%*j\\t%0\";
9461 /* ??? I don't know why this is necessary. This works around an
9462 assembler problem that appears when a label is defined, then referenced
9463 in a switch table, then used in a `j' instruction. */
9464 else if (mips_abi != ABI_32 && mips_abi != ABI_O64)
9465 return \"%*b\\t%l0\";
9467 return \"%*j\\t%l0\";
9469 [(set_attr "type" "jump")
9470 (set_attr "mode" "none")])
9472 ;; We need a different insn for the mips16, because a mips16 branch
9473 ;; does not have a delay slot.
9477 (label_ref (match_operand 0 "" "")))]
9478 "TARGET_MIPS16 && GET_CODE (operands[0]) != REG"
9480 [(set_attr "type" "branch")
9481 (set_attr "mode" "none")
9482 (set_attr "length" "8")])
9484 (define_expand "indirect_jump"
9485 [(set (pc) (match_operand 0 "register_operand" "d"))]
9491 if (operands[0]) /* eliminate unused code warnings */
9494 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
9495 operands[0] = copy_to_mode_reg (Pmode, dest);
9497 if (!(Pmode == DImode))
9498 emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
9500 emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
9506 (define_insn "indirect_jump_internal1"
9507 [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
9508 "!(Pmode == DImode)"
9510 [(set_attr "type" "jump")
9511 (set_attr "mode" "none")])
9513 (define_insn "indirect_jump_internal2"
9514 [(set (pc) (match_operand:DI 0 "se_register_operand" "d"))]
9517 [(set_attr "type" "jump")
9518 (set_attr "mode" "none")])
9520 (define_expand "tablejump"
9522 (match_operand 0 "register_operand" "d"))
9523 (use (label_ref (match_operand 1 "" "")))]
9527 if (operands[0]) /* eliminate unused code warnings */
9531 if (GET_MODE (operands[0]) != HImode)
9533 if (!(Pmode == DImode))
9534 emit_insn (gen_tablejump_mips161 (operands[0], operands[1]));
9536 emit_insn (gen_tablejump_mips162 (operands[0], operands[1]));
9540 if (GET_MODE (operands[0]) != Pmode)
9545 if (!(Pmode == DImode))
9546 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
9548 emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
9552 if (!(Pmode == DImode))
9553 emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
9555 emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
9562 (define_insn "tablejump_internal1"
9564 (match_operand:SI 0 "register_operand" "d"))
9565 (use (label_ref (match_operand 1 "" "")))]
9566 "!(Pmode == DImode)"
9568 [(set_attr "type" "jump")
9569 (set_attr "mode" "none")])
9571 (define_insn "tablejump_internal2"
9573 (match_operand:DI 0 "se_register_operand" "d"))
9574 (use (label_ref (match_operand 1 "" "")))]
9577 [(set_attr "type" "jump")
9578 (set_attr "mode" "none")])
9580 (define_expand "tablejump_internal3"
9581 [(parallel [(set (pc)
9582 (plus:SI (match_operand:SI 0 "register_operand" "d")
9583 (label_ref:SI (match_operand 1 "" ""))))
9584 (use (label_ref:SI (match_dup 1)))])]
9588 (define_expand "tablejump_mips161"
9589 [(set (pc) (plus:SI (sign_extend:SI
9590 (match_operand:HI 0 "register_operand" "d"))
9591 (label_ref:SI (match_operand 1 "" ""))))]
9592 "TARGET_MIPS16 && !(Pmode == DImode)"
9595 if (operands[0]) /* eliminate unused code warnings. */
9599 t1 = gen_reg_rtx (SImode);
9600 t2 = gen_reg_rtx (SImode);
9601 t3 = gen_reg_rtx (SImode);
9602 emit_insn (gen_extendhisi2 (t1, operands[0]));
9603 emit_move_insn (t2, gen_rtx (LABEL_REF, SImode, operands[1]));
9604 emit_insn (gen_addsi3 (t3, t1, t2));
9605 emit_jump_insn (gen_tablejump_internal1 (t3, operands[1]));
9610 (define_expand "tablejump_mips162"
9611 [(set (pc) (plus:DI (sign_extend:DI
9612 (match_operand:HI 0 "register_operand" "d"))
9613 (label_ref:DI (match_operand 1 "" ""))))]
9614 "TARGET_MIPS16 && Pmode == DImode"
9617 if (operands[0]) /* eliminate unused code warnings. */
9621 t1 = gen_reg_rtx (DImode);
9622 t2 = gen_reg_rtx (DImode);
9623 t3 = gen_reg_rtx (DImode);
9624 emit_insn (gen_extendhidi2 (t1, operands[0]));
9625 emit_move_insn (t2, gen_rtx (LABEL_REF, DImode, operands[1]));
9626 emit_insn (gen_adddi3 (t3, t1, t2));
9627 emit_jump_insn (gen_tablejump_internal2 (t3, operands[1]));
9632 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
9633 ;;; it is not valid. ??? With the USE, the condition tests may not be required
9636 ;;; ??? The length depends on the ABI. It is two for o32, and one for n32.
9637 ;;; We just use the conservative number here.
9641 (plus:SI (match_operand:SI 0 "register_operand" "d")
9642 (label_ref:SI (match_operand 1 "" ""))))
9643 (use (label_ref:SI (match_dup 1)))]
9644 "!(Pmode == DImode) && next_active_insn (insn) != 0
9645 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
9646 && PREV_INSN (next_active_insn (insn)) == operands[1]"
9649 /* .cpadd expands to add REG,REG,$gp when pic, and nothing when not pic. */
9650 if (mips_abi == ABI_32 || mips_abi == ABI_O64)
9651 output_asm_insn (\".cpadd\\t%0\", operands);
9652 return \"%*j\\t%0\";
9654 [(set_attr "type" "jump")
9655 (set_attr "mode" "none")
9656 (set_attr "length" "8")])
9658 (define_expand "tablejump_internal4"
9659 [(parallel [(set (pc)
9660 (plus:DI (match_operand:DI 0 "se_register_operand" "d")
9661 (label_ref:DI (match_operand 1 "" ""))))
9662 (use (label_ref:DI (match_dup 1)))])]
9666 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
9667 ;;; it is not valid. ??? With the USE, the condition tests may not be required
9672 (plus:DI (match_operand:DI 0 "se_register_operand" "d")
9673 (label_ref:DI (match_operand 1 "" ""))))
9674 (use (label_ref:DI (match_dup 1)))]
9675 "Pmode == DImode && next_active_insn (insn) != 0
9676 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
9677 && PREV_INSN (next_active_insn (insn)) == operands[1]"
9679 [(set_attr "type" "jump")
9680 (set_attr "mode" "none")])
9682 ;; Implement a switch statement when generating embedded PIC code.
9683 ;; Switches are implemented by `tablejump' when not using -membedded-pic.
9685 (define_expand "casesi"
9687 (minus:SI (match_operand:SI 0 "register_operand" "d")
9688 (match_operand:SI 1 "arith_operand" "dI")))
9690 (compare:CC (match_dup 5)
9691 (match_operand:SI 2 "arith_operand" "")))
9693 (if_then_else (gtu (cc0)
9695 (label_ref (match_operand 4 "" ""))
9699 (mem:SI (plus:SI (mult:SI (match_dup 5)
9701 (label_ref (match_operand 3 "" "")))))
9702 (clobber (match_scratch:SI 6 ""))
9703 (clobber (reg:SI 31))])]
9704 "TARGET_EMBEDDED_PIC"
9709 rtx reg = gen_reg_rtx (SImode);
9711 /* If the index is too large, go to the default label. */
9712 emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
9713 emit_insn (gen_cmpsi (reg, operands[2]));
9714 emit_insn (gen_bgtu (operands[4]));
9716 /* Do the PIC jump. */
9717 if (Pmode != DImode)
9718 emit_jump_insn (gen_casesi_internal (reg, operands[3],
9719 gen_reg_rtx (SImode)));
9721 emit_jump_insn (gen_casesi_internal_di (reg, operands[3],
9722 gen_reg_rtx (DImode)));
9728 ;; An embedded PIC switch statement looks like this:
9730 ;; sll $reg,$index,2
9732 ;; addu $reg,$reg,$31
9733 ;; lw $reg,$L1-$LS1($reg)
9734 ;; addu $reg,$reg,$31
9741 (define_insn "casesi_internal"
9743 (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d")
9745 (label_ref (match_operand 1 "" "")))))
9746 (clobber (match_operand:SI 2 "register_operand" "=d"))
9747 (clobber (reg:SI 31))]
9748 "TARGET_EMBEDDED_PIC"
9749 "%(bal\\t%S1\;sll\\t%2,%0,2\\n%~%S1:\;addu\\t%2,%2,$31%)\;\\
9750 lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\\n\\t%*j\\t%2"
9751 [(set_attr "type" "jump")
9752 (set_attr "mode" "none")
9753 (set_attr "length" "24")])
9755 ;; This code assumes that the table index will never be >= 29 bits wide,
9756 ;; which allows the 'sign extend' from SI to DI be a no-op.
9757 (define_insn "casesi_internal_di"
9759 (mem:DI (plus:DI (sign_extend:DI
9760 (mult:SI (match_operand:SI 0 "register_operand" "d")
9762 (label_ref (match_operand 1 "" "")))))
9763 (clobber (match_operand:DI 2 "register_operand" "=d"))
9764 (clobber (reg:DI 31))]
9765 "TARGET_EMBEDDED_PIC"
9766 "%(bal\\t%S1\;sll\\t%2,%0,3\\n%~%S1:\;daddu\\t%2,%2,$31%)\;\\
9767 ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
9768 [(set_attr "type" "jump")
9769 (set_attr "mode" "none")
9770 (set_attr "length" "24")])
9772 ;; For o32/n32/n64, we save the gp in the jmp_buf as well. While it is
9773 ;; possible to either pull it off the stack (in the o32 case) or recalculate
9774 ;; it given t9 and our target label, it takes 3 or 4 insns to do so, and
9777 (define_expand "builtin_setjmp_setup"
9778 [(unspec [(match_operand 0 "register_operand" "r")] UNSPEC_SETJMP)]
9782 if (Pmode == DImode)
9783 emit_insn (gen_builtin_setjmp_setup_64 (operands[0]));
9785 emit_insn (gen_builtin_setjmp_setup_32 (operands[0]));
9789 (define_expand "builtin_setjmp_setup_32"
9790 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
9793 "TARGET_ABICALLS && ! (Pmode == DImode)"
9796 (define_expand "builtin_setjmp_setup_64"
9797 [(set (mem:DI (plus:DI (match_operand:DI 0 "register_operand" "r")
9800 "TARGET_ABICALLS && Pmode == DImode"
9803 ;; For o32/n32/n64, we need to arrange for longjmp to put the
9804 ;; target address in t9 so that we can use it for loading $gp.
9806 (define_expand "builtin_longjmp"
9807 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPEC_LONGJMP)]
9811 /* The elements of the buffer are, in order: */
9812 int W = (Pmode == DImode ? 8 : 4);
9813 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
9814 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
9815 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
9816 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
9817 rtx pv = gen_rtx_REG (Pmode, 25);
9818 rtx gp = gen_rtx_REG (Pmode, 28);
9820 /* This bit is the same as expand_builtin_longjmp. */
9821 emit_move_insn (hard_frame_pointer_rtx, fp);
9822 emit_move_insn (pv, lab);
9823 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
9824 emit_move_insn (gp, gpv);
9825 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
9826 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
9827 emit_insn (gen_rtx_USE (VOIDmode, gp));
9828 emit_indirect_jump (pv);
9833 ;; ....................
9835 ;; Function prologue/epilogue
9837 ;; ....................
9840 (define_expand "prologue"
9845 if (mips_isa >= 0) /* avoid unused code warnings */
9847 mips_expand_prologue ();
9852 ;; Block any insns from being moved before this point, since the
9853 ;; profiling call to mcount can use various registers that aren't
9854 ;; saved or used to pass arguments.
9856 (define_insn "blockage"
9857 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
9860 [(set_attr "type" "unknown")
9861 (set_attr "mode" "none")
9862 (set_attr "length" "0")])
9864 (define_expand "epilogue"
9869 if (mips_isa >= 0) /* avoid unused code warnings */
9871 mips_expand_epilogue ();
9876 ;; Trivial return. Make it look like a normal return insn as that
9877 ;; allows jump optimizations to work better .
9878 (define_insn "return"
9880 "mips_can_use_return_insn ()"
9882 [(set_attr "type" "jump")
9883 (set_attr "mode" "none")])
9887 (define_insn "return_internal"
9888 [(use (match_operand 0 "pmode_register_operand" ""))
9893 return \"%*j\\t%0\";
9895 [(set_attr "type" "jump")
9896 (set_attr "mode" "none")])
9898 ;; When generating embedded PIC code we need to get the address of the
9899 ;; current function. This specialized instruction does just that.
9901 (define_insn "get_fnaddr"
9902 [(set (match_operand 0 "register_operand" "=d")
9903 (unspec [(match_operand 1 "" "")] UNSPEC_GET_FNADDR))
9904 (clobber (reg:SI 31))]
9905 "TARGET_EMBEDDED_PIC
9906 && GET_CODE (operands[1]) == SYMBOL_REF"
9907 "%($LF%= = . + 8\;bal\\t$LF%=\;la\\t%0,%1-$LF%=%)\;addu\\t%0,%0,$31"
9908 [(set_attr "type" "call")
9909 (set_attr "mode" "none")
9910 (set_attr "length" "16")])
9912 ;; This is used in compiling the unwind routines.
9913 (define_expand "eh_return"
9914 [(use (match_operand 0 "general_operand" ""))
9915 (use (match_operand 1 "general_operand" ""))]
9919 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
9921 if (GET_MODE (operands[1]) != gpr_mode)
9922 operands[1] = convert_to_mode (gpr_mode, operands[1], 0);
9924 emit_insn (gen_eh_set_lr_di (operands[1]));
9926 emit_insn (gen_eh_set_lr_si (operands[1]));
9928 emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]);
9932 ;; Clobber the return address on the stack. We can't expand this
9933 ;; until we know where it will be put in the stack frame.
9935 (define_insn "eh_set_lr_si"
9936 [(unspec [(match_operand:SI 0 "register_operand" "r")] UNSPEC_EH_RETURN)
9937 (clobber (match_scratch:SI 1 "=&r"))]
9941 (define_insn "eh_set_lr_di"
9942 [(unspec [(match_operand:DI 0 "register_operand" "r")] UNSPEC_EH_RETURN)
9943 (clobber (match_scratch:DI 1 "=&r"))]
9948 [(unspec [(match_operand 0 "register_operand" "")] UNSPEC_EH_RETURN)
9949 (clobber (match_scratch 1 ""))]
9950 "reload_completed && !TARGET_DEBUG_D_MODE"
9954 mips_set_return_address (operands[0], operands[1]);
9958 (define_insn "exception_receiver"
9959 [(unspec_volatile [(const_int 0)] UNSPEC_EH_RECEIVER)]
9960 "TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64)"
9961 "* return mips_restore_gp (operands, insn);"
9962 [(set_attr "type" "load")
9963 (set_attr "length" "8")])
9966 ;; ....................
9970 ;; ....................
9972 ;; calls.c now passes a third argument, make saber happy
9974 (define_expand "call"
9975 [(parallel [(call (match_operand 0 "memory_operand" "m")
9976 (match_operand 1 "" "i"))
9977 (clobber (reg:SI 31))
9978 (use (match_operand 2 "" "")) ;; next_arg_reg
9979 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
9985 if (operands[0]) /* eliminate unused code warnings */
9987 addr = XEXP (operands[0], 0);
9988 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
9989 || ! call_insn_operand (addr, VOIDmode))
9990 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
9992 /* In order to pass small structures by value in registers
9993 compatibly with the MIPS compiler, we need to shift the value
9994 into the high part of the register. Function_arg has encoded
9995 a PARALLEL rtx, holding a vector of adjustments to be made
9996 as the next_arg_reg variable, so we split up the insns,
9997 and emit them separately. */
9999 if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
10001 rtvec adjust = XVEC (operands[2], 0);
10002 int num = GET_NUM_ELEM (adjust);
10005 for (i = 0; i < num; i++)
10006 emit_insn (RTVEC_ELT (adjust, i));
10010 && mips16_hard_float
10011 && operands[2] != 0
10012 && (int) GET_MODE (operands[2]) != 0)
10014 if (build_mips16_call_stub (NULL_RTX, operands[0], operands[1],
10015 (int) GET_MODE (operands[2])))
10019 emit_call_insn (gen_call_internal0 (operands[0], operands[1],
10020 gen_rtx_REG (SImode,
10021 GP_REG_FIRST + 31)));
10026 (define_expand "call_internal0"
10027 [(parallel [(call (match_operand 0 "" "")
10028 (match_operand 1 "" ""))
10029 (clobber (match_operand:SI 2 "" ""))])]
10033 ;; We need to recognize reg:SI 31 specially for the mips16, because we
10034 ;; don't have a constraint letter for it.
10037 [(call (mem (match_operand 0 "call_insn_operand" "ei"))
10038 (match_operand 1 "" "i"))
10039 (clobber (match_operand:SI 2 "register_operand" "=y"))]
10040 "TARGET_MIPS16 && !TARGET_ABICALLS && !TARGET_LONG_CALLS
10041 && GET_CODE (operands[2]) == REG && REGNO (operands[2]) == 31"
10043 [(set_attr "type" "call")
10044 (set_attr "mode" "none")
10045 (set_attr "length" "8")])
10047 (define_insn "call_internal1"
10048 [(call (mem (match_operand 0 "call_insn_operand" "ri"))
10049 (match_operand 1 "" "i"))
10050 (clobber (match_operand:SI 2 "register_operand" "=d"))]
10051 "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
10054 register rtx target = operands[0];
10056 if (GET_CODE (target) == CONST_INT)
10057 return \"%[li\\t%@,%0\\n\\t%*jal\\t%2,%@%]\";
10058 else if (CONSTANT_ADDRESS_P (target))
10059 return \"%*jal\\t%0\";
10061 return \"%*jal\\t%2,%0\";
10063 [(set_attr "type" "call")
10064 (set_attr "mode" "none")])
10066 (define_insn "call_internal2"
10067 [(call (mem (match_operand 0 "call_insn_operand" "ri"))
10068 (match_operand 1 "" "i"))
10069 (clobber (match_operand:SI 2 "register_operand" "=d"))]
10070 "TARGET_ABICALLS && !TARGET_LONG_CALLS"
10073 register rtx target = operands[0];
10075 if (GET_CODE (target) == CONST_INT)
10076 return \"li\\t%^,%0\\n\\tjal\\t%2,%^\";
10077 else if (CONSTANT_ADDRESS_P (target))
10079 if (GET_MODE (target) == SImode)
10080 return \"la\\t%^,%0\\n\\tjal\\t%2,%^\";
10082 return \"dla\\t%^,%0\\n\\tjal\\t%2,%^\";
10084 else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
10085 return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
10087 return \"jal\\t%2,%0\";
10089 [(set_attr "type" "call")
10090 (set_attr "mode" "none")
10091 (set_attr "length" "8")])
10093 (define_insn "call_internal3a"
10094 [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
10095 (match_operand 1 "" "i"))
10096 (clobber (match_operand:SI 2 "register_operand" "=d"))]
10098 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
10100 [(set_attr "type" "call")
10101 (set_attr "mode" "none")])
10103 (define_insn "call_internal3b"
10104 [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
10105 (match_operand 1 "" "i"))
10106 (clobber (match_operand:SI 2 "register_operand" "=d"))]
10108 && Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
10110 [(set_attr "type" "call")
10111 (set_attr "mode" "none")
10112 (set_attr "length" "1")])
10114 (define_insn "call_internal3c"
10115 [(call (mem:SI (match_operand:SI 0 "register_operand" "e"))
10116 (match_operand 1 "" "i"))
10117 (clobber (match_operand:SI 2 "register_operand" "=y"))]
10118 "TARGET_MIPS16 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS
10119 && GET_CODE (operands[2]) == REG && REGNO (operands[2]) == 31"
10121 [(set_attr "type" "call")
10122 (set_attr "mode" "none")])
10124 (define_insn "call_internal4a"
10125 [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
10126 (match_operand 1 "" "i"))
10127 (clobber (match_operand:SI 2 "register_operand" "=d"))]
10128 "!(Pmode == DImode) && TARGET_ABICALLS && TARGET_LONG_CALLS"
10131 if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
10132 return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
10134 return \"jal\\t%2,%0\";
10136 [(set_attr "type" "call")
10137 (set_attr "mode" "none")
10138 (set_attr "length" "8")])
10140 (define_insn "call_internal4b"
10141 [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
10142 (match_operand 1 "" "i"))
10143 (clobber (match_operand:SI 2 "register_operand" "=d"))]
10144 "Pmode == DImode && TARGET_ABICALLS && TARGET_LONG_CALLS"
10147 if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
10148 return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
10150 return \"jal\\t%2,%0\";
10152 [(set_attr "type" "call")
10153 (set_attr "mode" "none")
10154 (set_attr "length" "8")])
10156 ;; calls.c now passes a fourth argument, make saber happy
10158 (define_expand "call_value"
10159 [(parallel [(set (match_operand 0 "register_operand" "=df")
10160 (call (match_operand 1 "memory_operand" "m")
10161 (match_operand 2 "" "i")))
10162 (clobber (reg:SI 31))
10163 (use (match_operand 3 "" ""))])] ;; next_arg_reg
10169 if (operands[0]) /* eliminate unused code warning */
10171 addr = XEXP (operands[1], 0);
10172 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
10173 || ! call_insn_operand (addr, VOIDmode))
10174 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
10176 /* In order to pass small structures by value in registers
10177 compatibly with the MIPS compiler, we need to shift the value
10178 into the high part of the register. Function_arg has encoded
10179 a PARALLEL rtx, holding a vector of adjustments to be made
10180 as the next_arg_reg variable, so we split up the insns,
10181 and emit them separately. */
10183 if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
10185 rtvec adjust = XVEC (operands[3], 0);
10186 int num = GET_NUM_ELEM (adjust);
10189 for (i = 0; i < num; i++)
10190 emit_insn (RTVEC_ELT (adjust, i));
10194 && mips16_hard_float
10195 && ((operands[3] != 0
10196 && (int) GET_MODE (operands[3]) != 0)
10197 || GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT))
10199 if (build_mips16_call_stub (operands[0], operands[1], operands[2],
10200 (operands[3] == 0 ? 0
10201 : (int) GET_MODE (operands[3]))))
10205 /* Handle Irix6 function calls that have multiple non-contiguous
10207 if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
10209 emit_call_insn (gen_call_value_multiple_internal0
10210 (XEXP (XVECEXP (operands[0], 0, 0), 0),
10211 operands[1], operands[2],
10212 XEXP (XVECEXP (operands[0], 0, 1), 0),
10213 gen_rtx_REG (SImode, GP_REG_FIRST + 31)));
10217 /* We have a call returning a DImode structure in an FP reg.
10218 Strip off the now unnecessary PARALLEL. */
10219 if (GET_CODE (operands[0]) == PARALLEL)
10220 operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
10222 emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
10223 gen_rtx_REG (SImode,
10224 GP_REG_FIRST + 31)));
10230 (define_expand "call_value_internal0"
10231 [(parallel [(set (match_operand 0 "" "")
10232 (call (match_operand 1 "" "")
10233 (match_operand 2 "" "")))
10234 (clobber (match_operand:SI 3 "" ""))])]
10238 ;; Recognize $31 specially on the mips16, because we don't have a
10239 ;; constraint letter for it.
10242 [(set (match_operand 0 "register_operand" "=d")
10243 (call (mem (match_operand 1 "call_insn_operand" "ei"))
10244 (match_operand 2 "" "i")))
10245 (clobber (match_operand:SI 3 "register_operand" "=y"))]
10246 "TARGET_MIPS16 && !TARGET_ABICALLS && !TARGET_LONG_CALLS
10247 && GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31"
10249 [(set_attr "type" "call")
10250 (set_attr "mode" "none")
10251 (set_attr "length" "8")])
10253 (define_insn "call_value_internal1"
10254 [(set (match_operand 0 "register_operand" "=df")
10255 (call (mem (match_operand 1 "call_insn_operand" "ri"))
10256 (match_operand 2 "" "i")))
10257 (clobber (match_operand:SI 3 "register_operand" "=d"))]
10258 "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
10261 register rtx target = operands[1];
10263 if (GET_CODE (target) == CONST_INT)
10264 return \"%[li\\t%@,%1\\n\\t%*jal\\t%3,%@%]\";
10265 else if (CONSTANT_ADDRESS_P (target))
10266 return \"%*jal\\t%1\";
10268 return \"%*jal\\t%3,%1\";
10270 [(set_attr "type" "call")
10271 (set_attr "mode" "none")])
10273 (define_insn "call_value_internal2"
10274 [(set (match_operand 0 "register_operand" "=df")
10275 (call (mem (match_operand 1 "call_insn_operand" "ri"))
10276 (match_operand 2 "" "i")))
10277 (clobber (match_operand:SI 3 "register_operand" "=d"))]
10278 "TARGET_ABICALLS && !TARGET_LONG_CALLS"
10281 register rtx target = operands[1];
10283 if (GET_CODE (target) == CONST_INT)
10284 return \"li\\t%^,%1\\n\\tjal\\t%3,%^\";
10285 else if (CONSTANT_ADDRESS_P (target))
10287 if (GET_MODE (target) == SImode)
10288 return \"la\\t%^,%1\\n\\tjal\\t%3,%^\";
10290 return \"dla\\t%^,%1\\n\\tjal\\t%3,%^\";
10292 else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
10293 return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
10295 return \"jal\\t%3,%1\";
10297 [(set_attr "type" "call")
10298 (set_attr "mode" "none")
10299 (set_attr "length" "8")])
10301 (define_insn "call_value_internal3a"
10302 [(set (match_operand 0 "register_operand" "=df")
10303 (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
10304 (match_operand 2 "" "i")))
10305 (clobber (match_operand:SI 3 "register_operand" "=d"))]
10307 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS"
10309 [(set_attr "type" "call")
10310 (set_attr "mode" "none")])
10312 (define_insn "call_value_internal3b"
10313 [(set (match_operand 0 "register_operand" "=df")
10314 (call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
10315 (match_operand 2 "" "i")))
10316 (clobber (match_operand:SI 3 "register_operand" "=d"))]
10318 && Pmode == DImode && !TARGET_ABICALLS && TARGET_LONG_CALLS"
10320 [(set_attr "type" "call")
10321 (set_attr "mode" "none")])
10323 (define_insn "call_value_internal3c"
10324 [(set (match_operand 0 "register_operand" "=df")
10325 (call (mem:SI (match_operand:SI 1 "register_operand" "e"))
10326 (match_operand 2 "" "i")))
10327 (clobber (match_operand:SI 3 "register_operand" "=y"))]
10328 "TARGET_MIPS16 && !(Pmode == DImode) && !TARGET_ABICALLS && TARGET_LONG_CALLS
10329 && GET_CODE (operands[3]) == REG && REGNO (operands[3]) == 31"
10331 [(set_attr "type" "call")
10332 (set_attr "mode" "none")])
10334 (define_insn "call_value_internal4a"
10335 [(set (match_operand 0 "register_operand" "=df")
10336 (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
10337 (match_operand 2 "" "i")))
10338 (clobber (match_operand:SI 3 "register_operand" "=d"))]
10339 "!(Pmode == DImode) && TARGET_ABICALLS && TARGET_LONG_CALLS"
10342 if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
10343 return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
10345 return \"jal\\t%3,%1\";
10347 [(set_attr "type" "call")
10348 (set_attr "mode" "none")
10349 (set_attr "length" "8")])
10351 (define_insn "call_value_internal4b"
10352 [(set (match_operand 0 "register_operand" "=df")
10353 (call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
10354 (match_operand 2 "" "i")))
10355 (clobber (match_operand:SI 3 "register_operand" "=d"))]
10356 "Pmode == DImode && TARGET_ABICALLS && TARGET_LONG_CALLS"
10359 if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
10360 return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
10362 return \"jal\\t%3,%1\";
10364 [(set_attr "type" "call")
10365 (set_attr "mode" "none")
10366 (set_attr "length" "8")])
10368 (define_expand "call_value_multiple_internal0"
10369 [(parallel [(set (match_operand 0 "" "")
10370 (call (match_operand 1 "" "")
10371 (match_operand 2 "" "")))
10372 (set (match_operand 3 "" "")
10373 (call (match_dup 1)
10375 (clobber (match_operand:SI 4 "" ""))])]
10379 ;; ??? May eventually need all 6 versions of the call patterns with multiple
10382 (define_insn "call_value_multiple_internal1"
10383 [(set (match_operand 0 "register_operand" "=df")
10384 (call (mem (match_operand 1 "call_insn_operand" "ri"))
10385 (match_operand 2 "" "i")))
10386 (set (match_operand 3 "register_operand" "=df")
10387 (call (mem (match_dup 1))
10389 (clobber (match_operand:SI 4 "register_operand" "=d"))]
10390 "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
10393 register rtx target = operands[1];
10395 if (GET_CODE (target) == CONST_INT)
10396 return \"%[li\\t%@,%1\\n\\t%*jal\\t%4,%@%]\";
10397 else if (CONSTANT_ADDRESS_P (target))
10398 return \"%*jal\\t%1\";
10400 return \"%*jal\\t%4,%1\";
10402 [(set_attr "type" "call")
10403 (set_attr "mode" "none")])
10405 (define_insn "call_value_multiple_internal2"
10406 [(set (match_operand 0 "register_operand" "=df")
10407 (call (mem (match_operand 1 "call_insn_operand" "ri"))
10408 (match_operand 2 "" "i")))
10409 (set (match_operand 3 "register_operand" "=df")
10410 (call (mem (match_dup 1))
10412 (clobber (match_operand:SI 4 "register_operand" "=d"))]
10413 "TARGET_ABICALLS && !TARGET_LONG_CALLS"
10416 register rtx target = operands[1];
10418 if (GET_CODE (target) == CONST_INT)
10419 return \"li\\t%^,%1\\n\\tjal\\t%4,%^\";
10420 else if (CONSTANT_ADDRESS_P (target))
10422 if (GET_MODE (target) == SImode)
10423 return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
10425 return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
10427 else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
10428 return \"move\\t%^,%1\\n\\tjal\\t%4,%^\";
10430 return \"jal\\t%4,%1\";
10432 [(set_attr "type" "call")
10433 (set_attr "mode" "none")
10434 (set_attr "length" "8")])
10437 ;; Call subroutine returning any type.
10439 (define_expand "untyped_call"
10440 [(parallel [(call (match_operand 0 "" "")
10442 (match_operand 1 "" "")
10443 (match_operand 2 "" "")])]
10447 if (operands[0]) /* silence statement not reached warnings */
10451 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
10453 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10455 rtx set = XVECEXP (operands[2], 0, i);
10456 emit_move_insn (SET_DEST (set), SET_SRC (set));
10459 emit_insn (gen_blockage ());
10465 ;; ....................
10469 ;; ....................
10473 (define_expand "prefetch"
10474 [(prefetch (match_operand 0 "address_operand" "")
10475 (match_operand 1 "const_int_operand" "")
10476 (match_operand 2 "const_int_operand" ""))]
10479 if (symbolic_operand (operands[0], GET_MODE (operands[0])))
10480 operands[0] = force_reg (GET_MODE (operands[0]), operands[0]);
10483 (define_insn "prefetch_si_address"
10484 [(prefetch (plus:SI (match_operand:SI 0 "register_operand" "r")
10485 (match_operand:SI 3 "const_int_operand" "i"))
10486 (match_operand:SI 1 "const_int_operand" "n")
10487 (match_operand:SI 2 "const_int_operand" "n"))]
10488 "ISA_HAS_PREFETCH && Pmode == SImode"
10489 "* return mips_emit_prefetch (operands);"
10490 [(set_attr "type" "load")])
10492 (define_insn "prefetch_si"
10493 [(prefetch (match_operand:SI 0 "register_operand" "r")
10494 (match_operand:SI 1 "const_int_operand" "n")
10495 (match_operand:SI 2 "const_int_operand" "n"))]
10496 "ISA_HAS_PREFETCH && Pmode == SImode"
10497 "* return mips_emit_prefetch (operands);"
10498 [(set_attr "type" "load")])
10500 (define_insn "prefetch_di_address"
10501 [(prefetch (plus:DI (match_operand:DI 0 "se_register_operand" "r")
10502 (match_operand:DI 3 "const_int_operand" "i"))
10503 (match_operand:DI 1 "const_int_operand" "n")
10504 (match_operand:DI 2 "const_int_operand" "n"))]
10505 "ISA_HAS_PREFETCH && Pmode == DImode"
10506 "* return mips_emit_prefetch (operands);"
10507 [(set_attr "type" "load")])
10509 (define_insn "prefetch_di"
10510 [(prefetch (match_operand:DI 0 "se_register_operand" "r")
10511 (match_operand:DI 1 "const_int_operand" "n")
10512 (match_operand:DI 2 "const_int_operand" "n"))]
10513 "ISA_HAS_PREFETCH && Pmode == DImode"
10514 "* return mips_emit_prefetch (operands);"
10515 [(set_attr "type" "load")])
10521 [(set_attr "type" "nop")
10522 (set_attr "mode" "none")])
10524 ;; The MIPS chip does not seem to require stack probes.
10526 ;; (define_expand "probe"
10527 ;; [(set (match_dup 0)
10532 ;; operands[0] = gen_reg_rtx (SImode);
10533 ;; operands[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
10534 ;; MEM_VOLATILE_P (operands[1]) = TRUE;
10536 ;; /* fall through and generate default code */
10541 ;; MIPS4 Conditional move instructions.
10544 [(set (match_operand:SI 0 "register_operand" "=d,d")
10546 (match_operator 4 "equality_op"
10547 [(match_operand:SI 1 "register_operand" "d,d")
10549 (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
10550 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
10551 "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
10554 mov%b4\\t%0,%z3,%1"
10555 [(set_attr "type" "move")
10556 (set_attr "mode" "SI")])
10559 [(set (match_operand:SI 0 "register_operand" "=d,d")
10561 (match_operator 4 "equality_op"
10562 [(match_operand:DI 1 "se_register_operand" "d,d")
10564 (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
10565 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
10566 "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
10569 mov%b4\\t%0,%z3,%1"
10570 [(set_attr "type" "move")
10571 (set_attr "mode" "SI")])
10574 [(set (match_operand:SI 0 "register_operand" "=d,d")
10576 (match_operator 3 "equality_op" [(match_operand:CC 4
10580 (match_operand:SI 1 "reg_or_0_operand" "dJ,0")
10581 (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
10582 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
10585 mov%t3\\t%0,%z2,%4"
10586 [(set_attr "type" "move")
10587 (set_attr "mode" "SI")])
10590 [(set (match_operand:DI 0 "register_operand" "=d,d")
10592 (match_operator 4 "equality_op"
10593 [(match_operand:SI 1 "register_operand" "d,d")
10595 (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
10596 (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
10597 "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
10600 mov%b4\\t%0,%z3,%1"
10601 [(set_attr "type" "move")
10602 (set_attr "mode" "DI")])
10605 [(set (match_operand:DI 0 "register_operand" "=d,d")
10607 (match_operator 4 "equality_op"
10608 [(match_operand:DI 1 "se_register_operand" "d,d")
10610 (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
10611 (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
10612 "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
10615 mov%b4\\t%0,%z3,%1"
10616 [(set_attr "type" "move")
10617 (set_attr "mode" "DI")])
10620 [(set (match_operand:DI 0 "register_operand" "=d,d")
10622 (match_operator 3 "equality_op" [(match_operand:CC 4
10626 (match_operand:DI 1 "se_reg_or_0_operand" "dJ,0")
10627 (match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))]
10628 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
10631 mov%t3\\t%0,%z2,%4"
10632 [(set_attr "type" "move")
10633 (set_attr "mode" "DI")])
10636 [(set (match_operand:SF 0 "register_operand" "=f,f")
10638 (match_operator 4 "equality_op"
10639 [(match_operand:SI 1 "register_operand" "d,d")
10641 (match_operand:SF 2 "register_operand" "f,0")
10642 (match_operand:SF 3 "register_operand" "0,f")))]
10643 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
10645 mov%B4.s\\t%0,%2,%1
10646 mov%b4.s\\t%0,%3,%1"
10647 [(set_attr "type" "move")
10648 (set_attr "mode" "SF")])
10651 [(set (match_operand:SF 0 "register_operand" "=f,f")
10653 (match_operator 4 "equality_op"
10654 [(match_operand:DI 1 "se_register_operand" "d,d")
10656 (match_operand:SF 2 "register_operand" "f,0")
10657 (match_operand:SF 3 "register_operand" "0,f")))]
10658 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
10660 mov%B4.s\\t%0,%2,%1
10661 mov%b4.s\\t%0,%3,%1"
10662 [(set_attr "type" "move")
10663 (set_attr "mode" "SF")])
10666 [(set (match_operand:SF 0 "register_operand" "=f,f")
10668 (match_operator 3 "equality_op" [(match_operand:CC 4
10672 (match_operand:SF 1 "register_operand" "f,0")
10673 (match_operand:SF 2 "register_operand" "0,f")))]
10674 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
10676 mov%T3.s\\t%0,%1,%4
10677 mov%t3.s\\t%0,%2,%4"
10678 [(set_attr "type" "move")
10679 (set_attr "mode" "SF")])
10682 [(set (match_operand:DF 0 "register_operand" "=f,f")
10684 (match_operator 4 "equality_op"
10685 [(match_operand:SI 1 "register_operand" "d,d")
10687 (match_operand:DF 2 "register_operand" "f,0")
10688 (match_operand:DF 3 "register_operand" "0,f")))]
10689 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
10691 mov%B4.d\\t%0,%2,%1
10692 mov%b4.d\\t%0,%3,%1"
10693 [(set_attr "type" "move")
10694 (set_attr "mode" "DF")])
10697 [(set (match_operand:DF 0 "register_operand" "=f,f")
10699 (match_operator 4 "equality_op"
10700 [(match_operand:DI 1 "se_register_operand" "d,d")
10702 (match_operand:DF 2 "register_operand" "f,0")
10703 (match_operand:DF 3 "register_operand" "0,f")))]
10704 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
10706 mov%B4.d\\t%0,%2,%1
10707 mov%b4.d\\t%0,%3,%1"
10708 [(set_attr "type" "move")
10709 (set_attr "mode" "DF")])
10712 [(set (match_operand:DF 0 "register_operand" "=f,f")
10714 (match_operator 3 "equality_op" [(match_operand:CC 4
10718 (match_operand:DF 1 "register_operand" "f,0")
10719 (match_operand:DF 2 "register_operand" "0,f")))]
10720 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
10722 mov%T3.d\\t%0,%1,%4
10723 mov%t3.d\\t%0,%2,%4"
10724 [(set_attr "type" "move")
10725 (set_attr "mode" "DF")])
10727 ;; These are the main define_expand's used to make conditional moves.
10729 (define_expand "movsicc"
10730 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
10731 (set (match_operand:SI 0 "register_operand" "")
10732 (if_then_else:SI (match_dup 5)
10733 (match_operand:SI 2 "reg_or_0_operand" "")
10734 (match_operand:SI 3 "reg_or_0_operand" "")))]
10735 "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
10738 gen_conditional_move (operands);
10742 (define_expand "movdicc"
10743 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
10744 (set (match_operand:DI 0 "register_operand" "")
10745 (if_then_else:DI (match_dup 5)
10746 (match_operand:DI 2 "se_reg_or_0_operand" "")
10747 (match_operand:DI 3 "se_reg_or_0_operand" "")))]
10748 "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
10751 gen_conditional_move (operands);
10755 (define_expand "movsfcc"
10756 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
10757 (set (match_operand:SF 0 "register_operand" "")
10758 (if_then_else:SF (match_dup 5)
10759 (match_operand:SF 2 "register_operand" "")
10760 (match_operand:SF 3 "register_operand" "")))]
10761 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
10764 gen_conditional_move (operands);
10768 (define_expand "movdfcc"
10769 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
10770 (set (match_operand:DF 0 "register_operand" "")
10771 (if_then_else:DF (match_dup 5)
10772 (match_operand:DF 2 "register_operand" "")
10773 (match_operand:DF 3 "register_operand" "")))]
10774 "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
10777 gen_conditional_move (operands);
10782 ;; ....................
10784 ;; mips16 inline constant tables
10786 ;; ....................
10789 (define_insn "consttable_qi"
10790 [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "=g")]
10791 UNSPEC_CONSTTABLE_QI)]
10795 assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
10798 [(set_attr "type" "unknown")
10799 (set_attr "mode" "QI")
10800 (set_attr "length" "8")])
10802 (define_insn "consttable_hi"
10803 [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "=g")]
10804 UNSPEC_CONSTTABLE_HI)]
10808 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
10811 [(set_attr "type" "unknown")
10812 (set_attr "mode" "HI")
10813 (set_attr "length" "8")])
10815 (define_insn "consttable_si"
10816 [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "=g")]
10817 UNSPEC_CONSTTABLE_SI)]
10821 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
10824 [(set_attr "type" "unknown")
10825 (set_attr "mode" "SI")
10826 (set_attr "length" "8")])
10828 (define_insn "consttable_di"
10829 [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "=g")]
10830 UNSPEC_CONSTTABLE_DI)]
10834 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
10837 [(set_attr "type" "unknown")
10838 (set_attr "mode" "DI")
10839 (set_attr "length" "16")])
10841 (define_insn "consttable_sf"
10842 [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "=g")]
10843 UNSPEC_CONSTTABLE_SF)]
10849 if (GET_CODE (operands[0]) != CONST_DOUBLE)
10851 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
10852 assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
10855 [(set_attr "type" "unknown")
10856 (set_attr "mode" "SF")
10857 (set_attr "length" "8")])
10859 (define_insn "consttable_df"
10860 [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "=g")]
10861 UNSPEC_CONSTTABLE_DF)]
10867 if (GET_CODE (operands[0]) != CONST_DOUBLE)
10869 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
10870 assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
10873 [(set_attr "type" "unknown")
10874 (set_attr "mode" "DF")
10875 (set_attr "length" "16")])
10877 (define_insn "align_2"
10878 [(unspec_volatile [(const_int 0)] UNSPEC_ALIGN_2)]
10881 [(set_attr "type" "unknown")
10882 (set_attr "mode" "HI")
10883 (set_attr "length" "8")])
10885 (define_insn "align_4"
10886 [(unspec_volatile [(const_int 0)] UNSPEC_ALIGN_4)]
10889 [(set_attr "type" "unknown")
10890 (set_attr "mode" "SI")
10891 (set_attr "length" "8")])
10893 (define_insn "align_8"
10894 [(unspec_volatile [(const_int 0)] UNSPEC_ALIGN_8)]
10897 [(set_attr "type" "unknown")
10898 (set_attr "mode" "DI")
10899 (set_attr "length" "12")])
10902 ;; ....................
10904 ;; mips16 peepholes
10906 ;; ....................
10909 ;; On the mips16, reload will sometimes decide that a pseudo register
10910 ;; should go into $24, and then later on have to reload that register.
10911 ;; When that happens, we get a load of a general register followed by
10912 ;; a move from the general register to $24 followed by a branch.
10913 ;; These peepholes catch the common case, and fix it to just use the
10914 ;; general register for the branch.
10917 [(set (match_operand:SI 0 "register_operand" "=t")
10918 (match_operand:SI 1 "register_operand" "d"))
10920 (if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
10922 (match_operand 3 "pc_or_label_operand" "")
10923 (match_operand 4 "pc_or_label_operand" "")))]
10925 && GET_CODE (operands[0]) == REG
10926 && REGNO (operands[0]) == 24
10927 && dead_or_set_p (insn, operands[0])
10928 && GET_CODE (operands[1]) == REG
10929 && M16_REG_P (REGNO (operands[1]))"
10932 if (operands[3] != pc_rtx)
10933 return \"%*b%C2z\\t%1,%3\";
10935 return \"%*b%N2z\\t%1,%4\";
10937 [(set_attr "type" "branch")
10938 (set_attr "mode" "none")
10939 (set_attr "length" "8")])
10942 [(set (match_operand:DI 0 "register_operand" "=t")
10943 (match_operand:DI 1 "register_operand" "d"))
10945 (if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
10947 (match_operand 3 "pc_or_label_operand" "")
10948 (match_operand 4 "pc_or_label_operand" "")))]
10949 "TARGET_MIPS16 && TARGET_64BIT
10950 && GET_CODE (operands[0]) == REG
10951 && REGNO (operands[0]) == 24
10952 && dead_or_set_p (insn, operands[0])
10953 && GET_CODE (operands[1]) == REG
10954 && M16_REG_P (REGNO (operands[1]))"
10957 if (operands[3] != pc_rtx)
10958 return \"%*b%C2z\\t%1,%3\";
10960 return \"%*b%N2z\\t%1,%4\";
10962 [(set_attr "type" "branch")
10963 (set_attr "mode" "none")
10964 (set_attr "length" "8")])
10966 ;; We can also have the reverse reload: reload will spill $24 into
10967 ;; another register, and then do a branch on that register when it
10968 ;; could have just stuck with $24.
10971 [(set (match_operand:SI 0 "register_operand" "=d")
10972 (match_operand:SI 1 "register_operand" "t"))
10974 (if_then_else (match_operator:SI 2 "equality_op" [(match_dup 0)
10976 (match_operand 3 "pc_or_label_operand" "")
10977 (match_operand 4 "pc_or_label_operand" "")))]
10979 && GET_CODE (operands[1]) == REG
10980 && REGNO (operands[1]) == 24
10981 && GET_CODE (operands[0]) == REG
10982 && M16_REG_P (REGNO (operands[0]))
10983 && dead_or_set_p (insn, operands[0])"
10986 if (operands[3] != pc_rtx)
10987 return \"%*bt%C2z\\t%3\";
10989 return \"%*bt%N2z\\t%4\";
10991 [(set_attr "type" "branch")
10992 (set_attr "mode" "none")
10993 (set_attr "length" "8")])
10996 [(set (match_operand:DI 0 "register_operand" "=d")
10997 (match_operand:DI 1 "register_operand" "t"))
10999 (if_then_else (match_operator:DI 2 "equality_op" [(match_dup 0)
11001 (match_operand 3 "pc_or_label_operand" "")
11002 (match_operand 4 "pc_or_label_operand" "")))]
11003 "TARGET_MIPS16 && TARGET_64BIT
11004 && GET_CODE (operands[1]) == REG
11005 && REGNO (operands[1]) == 24
11006 && GET_CODE (operands[0]) == REG
11007 && M16_REG_P (REGNO (operands[0]))
11008 && dead_or_set_p (insn, operands[0])"
11011 if (operands[3] != pc_rtx)
11012 return \"%*bt%C2z\\t%3\";
11014 return \"%*bt%N2z\\t%4\";
11016 [(set_attr "type" "branch")
11017 (set_attr "mode" "none")
11018 (set_attr "length" "8")])
11020 ;; For the rare case where we need to load an address into a register
11021 ;; that can not be recognized by the normal movsi/addsi instructions.
11022 ;; I have no idea how many insns this can actually generate. It should
11023 ;; be rare, so over-estimating as 10 instructions should not have any
11024 ;; real performance impact.
11025 (define_insn "leasi"
11026 [(set (match_operand:SI 0 "register_operand" "=d")
11027 (match_operand:SI 1 "address_operand" "p"))]
11030 [(set_attr "type" "arith")
11031 (set_attr "mode" "SI")
11032 (set_attr "length" "40")])
11034 ;; Similarly for targets where we have 64bit pointers.
11035 (define_insn "leadi"
11036 [(set (match_operand:DI 0 "register_operand" "=d")
11037 (match_operand:DI 1 "address_operand" "p"))]
11040 [(set_attr "type" "arith")
11041 (set_attr "mode" "DI")
11042 (set_attr "length" "40")])