1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-6, 1997 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern int flag_omit_frame_pointer;
32 extern int frame_pointer_needed;
33 extern char *language_string;
34 extern int may_call_alloca;
36 extern char **save_argv;
37 extern int target_flags;
38 extern char *version_string;
40 /* MIPS external variables defined in mips.c. */
44 CMP_SI, /* compare four byte integers */
45 CMP_DI, /* compare eight byte integers */
46 CMP_SF, /* compare single precision floats */
47 CMP_DF, /* compare double precision floats */
48 CMP_MAX /* max comparison type */
51 /* types of delay slot */
53 DELAY_NONE, /* no delay slot */
54 DELAY_LOAD, /* load from memory delay */
55 DELAY_HILO, /* move from/to hi/lo registers */
56 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
59 /* Which processor to schedule for. Since there is no difference between
60 a R2000 and R3000 in terms of the scheduler, we collapse them into
61 just an R3000. The elements of the enumeration must match exactly
62 the cpu attribute in the mips.md machine description. */
77 /* Recast the cpu class to be the cpu attribute. */
78 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
80 /* Which ABI to use. This is only used by the Irix 6 port currently. */
89 #ifndef MIPS_ABI_DEFAULT
90 /* We define this away so that there is no extra runtime cost if the target
91 doesn't support multiple ABIs. */
92 #define mips_abi ABI_32
94 extern enum mips_abi_type mips_abi;
97 /* Whether to emit abicalls code sequences or not. */
99 enum mips_abicalls_type {
104 /* Recast the abicalls class to be the abicalls attribute. */
105 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
107 /* Which type of block move to do (whether or not the last store is
108 split out so it can fill a branch delay slot). */
110 enum block_move_type {
111 BLOCK_MOVE_NORMAL, /* generate complete block move */
112 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
113 BLOCK_MOVE_LAST /* generate just the last store */
116 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
117 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
118 extern char *current_function_file; /* filename current function is in */
119 extern int num_source_filenames; /* current .file # */
120 extern int inside_function; /* != 0 if inside of a function */
121 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
122 extern int file_in_function_warning; /* warning given about .file in func */
123 extern int sdb_label_count; /* block start/end next label # */
124 extern int sdb_begin_function_line; /* Starting Line of current function */
125 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
126 extern int g_switch_value; /* value of the -G xx switch */
127 extern int g_switch_set; /* whether -G xx was passed. */
128 extern int sym_lineno; /* sgi next label # for each stmt */
129 extern int set_noreorder; /* # of nested .set noreorder's */
130 extern int set_nomacro; /* # of nested .set nomacro's */
131 extern int set_noat; /* # of nested .set noat's */
132 extern int set_volatile; /* # of nested .set volatile's */
133 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
134 extern int mips_dbx_regno[]; /* Map register # to debug register # */
135 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
136 extern enum cmp_type branch_type; /* what type of branch to use */
137 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
138 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
139 extern int mips_isa; /* architectural level */
140 extern char *mips_cpu_string; /* for -mcpu=<xxx> */
141 extern char *mips_isa_string; /* for -mips{1,2,3,4} */
142 extern char *mips_abi_string; /* for -misa={32,n32,64} */
143 extern int mips_split_addresses; /* perform high/lo_sum support */
144 extern int dslots_load_total; /* total # load related delay slots */
145 extern int dslots_load_filled; /* # filled load delay slots */
146 extern int dslots_jump_total; /* total # jump related delay slots */
147 extern int dslots_jump_filled; /* # filled jump delay slots */
148 extern int dslots_number_nops; /* # of nops needed by previous insn */
149 extern int num_refs[3]; /* # 1/2/3 word references */
150 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
151 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
152 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
153 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
154 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
156 /* Functions within mips.c that we reference. */
158 extern void abort_with_insn ();
159 extern int arith32_operand ();
160 extern int arith_operand ();
161 extern int cmp_op ();
162 extern long compute_frame_size ();
163 extern int epilogue_reg_mentioned_p ();
164 extern void expand_block_move ();
165 extern int equality_op ();
166 extern void final_prescan_insn ();
167 extern struct rtx_def * function_arg ();
168 extern void function_arg_advance ();
169 extern int function_arg_partial_nregs ();
170 extern int function_arg_pass_by_reference ();
171 extern void function_epilogue ();
172 extern void function_prologue ();
173 extern void gen_conditional_branch ();
174 extern void gen_conditional_move ();
175 extern struct rtx_def * gen_int_relational ();
176 extern void init_cumulative_args ();
177 extern int large_int ();
178 extern int mips_address_cost ();
179 extern void mips_asm_file_end ();
180 extern void mips_asm_file_start ();
181 extern int mips_const_double_ok ();
182 extern void mips_count_memory_refs ();
183 extern int mips_debugger_offset ();
184 extern void mips_declare_object ();
185 extern int mips_epilogue_delay_slots ();
186 extern void mips_expand_epilogue ();
187 extern void mips_expand_prologue ();
188 extern int mips_check_split ();
189 extern char *mips_fill_delay_slot ();
190 extern char *mips_move_1word ();
191 extern char *mips_move_2words ();
192 extern void mips_output_double ();
193 extern int mips_output_external ();
194 extern void mips_output_float ();
195 extern void mips_output_filename ();
196 extern void mips_output_lineno ();
197 extern char *output_block_move ();
198 extern void override_options ();
199 extern int pc_or_label_operand ();
200 extern void print_operand_address ();
201 extern void print_operand ();
202 extern void print_options ();
203 extern int reg_or_0_operand ();
204 extern int simple_epilogue_p ();
205 extern int simple_memory_operand ();
206 extern int small_int ();
208 extern int uns_arith_operand ();
209 extern struct rtx_def * embedded_pic_offset ();
211 /* Recognition functions that return if a condition is true. */
212 extern int address_operand ();
213 extern int const_double_operand ();
214 extern int const_int_operand ();
215 extern int general_operand ();
216 extern int immediate_operand ();
217 extern int memory_address_p ();
218 extern int memory_operand ();
219 extern int nonimmediate_operand ();
220 extern int nonmemory_operand ();
221 extern int register_operand ();
222 extern int scratch_operand ();
223 extern int move_operand ();
224 extern int movdi_operand ();
225 extern int se_register_operand ();
226 extern int se_reg_or_0_operand ();
227 extern int se_uns_arith_operand ();
228 extern int se_arith_operand ();
229 extern int se_nonmemory_operand ();
230 extern int se_nonimmediate_operand ();
232 /* Functions to change what output section we are using. */
233 extern void data_section ();
234 extern void rdata_section ();
235 extern void readonly_data_section ();
236 extern void sdata_section ();
237 extern void text_section ();
239 /* Stubs for half-pic support if not OSF/1 reference platform. */
242 #define HALF_PIC_P() 0
243 #define HALF_PIC_NUMBER_PTRS 0
244 #define HALF_PIC_NUMBER_REFS 0
245 #define HALF_PIC_ENCODE(DECL)
246 #define HALF_PIC_DECLARE(NAME)
247 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
248 #define HALF_PIC_ADDRESS_P(X) 0
249 #define HALF_PIC_PTR(X) X
250 #define HALF_PIC_FINISH(STREAM)
254 /* Run-time compilation parameters selecting different hardware subsets. */
256 /* Macros used in the machine description to test the flags. */
258 /* Bits for real switches */
259 #define MASK_INT64 0x00000001 /* ints are 64 bits */
260 #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
261 #define MASK_UNUSED 0x00000004
262 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
263 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
264 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
265 #define MASK_STATS 0x00000040 /* print statistics to stderr */
266 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
267 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
268 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
269 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
270 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
271 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
272 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
273 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
274 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
275 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
276 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
277 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
278 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
280 /* Dummy switches used only in spec's*/
281 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
283 /* Debug switches, not documented */
284 #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */
285 #define MASK_DEBUG_A 0x20000000 /* don't allow <label>($reg) addrs */
286 #define MASK_DEBUG_B 0x10000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
287 #define MASK_DEBUG_C 0x08000000 /* don't expand seq, etc. */
288 #define MASK_DEBUG_D 0x04000000 /* don't do define_split's */
289 #define MASK_DEBUG_E 0x02000000 /* function_arg debug */
290 #define MASK_DEBUG_F 0x01000000 /* don't try to suppress load nop's */
291 #define MASK_DEBUG_G 0x00800000 /* don't support 64 bit arithmetic */
292 #define MASK_DEBUG_H 0x00400000 /* allow ints in FP registers */
293 #define MASK_DEBUG_I 0x00200000 /* unused */
294 #define MASK_DEBUG_J 0x00100000 /* unused */
296 /* r4000 64 bit sizes */
297 #define TARGET_INT64 (target_flags & MASK_INT64)
298 #define TARGET_LONG64 (target_flags & MASK_LONG64)
299 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
300 #define TARGET_64BIT (target_flags & MASK_64BIT)
302 /* Mips vs. GNU assembler */
303 #define TARGET_GAS (target_flags & MASK_GAS)
304 #define TARGET_UNIX_ASM (!TARGET_GAS)
305 #define TARGET_MIPS_AS TARGET_UNIX_ASM
308 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
309 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
310 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
311 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
312 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
313 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
314 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
315 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
316 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
317 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
318 #define TARGET_DEBUG_J_MODE (target_flags & MASK_DEBUG_J)
320 /* Reg. Naming in .s ($21 vs. $a0) */
321 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
323 /* Optimize for Sdata/Sbss */
324 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
326 /* print program statistics */
327 #define TARGET_STATS (target_flags & MASK_STATS)
329 /* call memcpy instead of inline code */
330 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
332 /* .abicalls, etc from Pyramid V.4 */
333 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
335 /* OSF pic references to externs */
336 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
338 /* software floating point */
339 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
340 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
342 /* always call through a register */
343 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
345 /* generate embedded PIC code;
347 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
349 /* for embedded systems, optimize for
350 reduced RAM space instead of for
352 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
354 /* generate big endian code. */
355 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
357 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
358 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
360 #define TARGET_MAD (target_flags & MASK_MAD)
362 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
364 /* Macro to define tables used to set the flags.
365 This is a list in braces of pairs in braces,
366 each pair being { "NAME", VALUE }
367 where VALUE is the bits to set or minus the bits to clear.
368 An empty string NAME is used to identify the default VALUE. */
370 #define TARGET_SWITCHES \
372 {"int64", MASK_INT64 | MASK_LONG64}, \
373 {"long64", MASK_LONG64}, \
374 {"mips-as", -MASK_GAS}, \
376 {"rnames", MASK_NAME_REGS}, \
377 {"no-rnames", -MASK_NAME_REGS}, \
378 {"gpOPT", MASK_GPOPT}, \
379 {"gpopt", MASK_GPOPT}, \
380 {"no-gpOPT", -MASK_GPOPT}, \
381 {"no-gpopt", -MASK_GPOPT}, \
382 {"stats", MASK_STATS}, \
383 {"no-stats", -MASK_STATS}, \
384 {"memcpy", MASK_MEMCPY}, \
385 {"no-memcpy", -MASK_MEMCPY}, \
386 {"mips-tfile", MASK_MIPS_TFILE}, \
387 {"no-mips-tfile", -MASK_MIPS_TFILE}, \
388 {"soft-float", MASK_SOFT_FLOAT}, \
389 {"hard-float", -MASK_SOFT_FLOAT}, \
390 {"fp64", MASK_FLOAT64}, \
391 {"fp32", -MASK_FLOAT64}, \
392 {"gp64", MASK_64BIT}, \
393 {"gp32", -MASK_64BIT}, \
394 {"abicalls", MASK_ABICALLS}, \
395 {"no-abicalls", -MASK_ABICALLS}, \
396 {"half-pic", MASK_HALF_PIC}, \
397 {"no-half-pic", -MASK_HALF_PIC}, \
398 {"long-calls", MASK_LONG_CALLS}, \
399 {"no-long-calls", -MASK_LONG_CALLS}, \
400 {"embedded-pic", MASK_EMBEDDED_PIC}, \
401 {"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
402 {"embedded-data", MASK_EMBEDDED_DATA}, \
403 {"no-embedded-data", -MASK_EMBEDDED_DATA}, \
404 {"eb", MASK_BIG_ENDIAN}, \
405 {"el", -MASK_BIG_ENDIAN}, \
406 {"single-float", MASK_SINGLE_FLOAT}, \
407 {"double-float", -MASK_SINGLE_FLOAT}, \
409 {"no-mad", -MASK_MAD}, \
410 {"fix4300", MASK_4300_MUL_FIX}, \
411 {"no-fix4300", -MASK_4300_MUL_FIX}, \
412 {"4650", MASK_MAD | MASK_SINGLE_FLOAT}, \
413 {"debug", MASK_DEBUG}, \
414 {"debuga", MASK_DEBUG_A}, \
415 {"debugb", MASK_DEBUG_B}, \
416 {"debugc", MASK_DEBUG_C}, \
417 {"debugd", MASK_DEBUG_D}, \
418 {"debuge", MASK_DEBUG_E}, \
419 {"debugf", MASK_DEBUG_F}, \
420 {"debugg", MASK_DEBUG_G}, \
421 {"debugh", MASK_DEBUG_H}, \
422 {"debugi", MASK_DEBUG_I}, \
423 {"debugj", MASK_DEBUG_J}, \
424 {"", (TARGET_DEFAULT \
425 | TARGET_CPU_DEFAULT \
426 | TARGET_ENDIAN_DEFAULT)} \
429 /* Default target_flags if no switches are specified */
431 #ifndef TARGET_DEFAULT
432 #define TARGET_DEFAULT 0
435 #ifndef TARGET_CPU_DEFAULT
436 #define TARGET_CPU_DEFAULT 0
439 #ifndef TARGET_ENDIAN_DEFAULT
441 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
443 #define TARGET_ENDIAN_DEFAULT 0
447 #ifndef MULTILIB_DEFAULTS
448 #if TARGET_ENDIAN_DEFAULT == 0
449 #define MULTILIB_DEFAULTS { "EL", "mips1" }
451 #define MULTILIB_DEFAULTS { "EB", "mips1" }
455 /* This macro is similar to `TARGET_SWITCHES' but defines names of
456 command options that have values. Its definition is an
457 initializer with a subgrouping for each command option.
459 Each subgrouping contains a string constant, that defines the
460 fixed part of the option name, and the address of a variable.
461 The variable, type `char *', is set to the variable part of the
462 given option if the fixed part matches. The actual option name
463 is made by appending `-m' to the specified name.
465 Here is an example which defines `-mshort-data-NUMBER'. If the
466 given option is `-mshort-data-512', the variable `m88k_short_data'
467 will be set to the string `"512"'.
469 extern char *m88k_short_data;
470 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
472 #define TARGET_OPTIONS \
474 SUBTARGET_TARGET_OPTIONS \
475 { "cpu=", &mips_cpu_string }, \
476 { "ips", &mips_isa_string } \
479 /* This is meant to be redefined in the host dependent files. */
480 #define SUBTARGET_TARGET_OPTIONS
482 /* Macros to decide whether certain features are available or not,
483 depending on the instruction set architecture level. */
485 #define BRANCH_LIKELY_P() (mips_isa >= 2)
486 #define HAVE_SQRT_P() (mips_isa >= 2)
488 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
489 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
490 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
491 target_flags, and -mgp64 sets MASK_64BIT.
493 Setting MASK_64BIT in target_flags will cause gcc to assume that
494 registers are 64 bits wide. int, long and void * will be 32 bit;
495 this may be changed with -mint64 or -mlong64.
497 The gen* programs link code that refers to MASK_64BIT. They don't
498 actually use the information in target_flags; they just refer to
501 /* Switch Recognition by gcc.c. Add -G xx support */
503 #ifdef SWITCH_TAKES_ARG
504 #undef SWITCH_TAKES_ARG
507 #define SWITCH_TAKES_ARG(CHAR) \
508 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
510 /* Sometimes certain combinations of command options do not make sense
511 on a particular target machine. You can define a macro
512 `OVERRIDE_OPTIONS' to take account of this. This macro, if
513 defined, is executed once just after all the command options have
516 On the MIPS, it is used to handle -G. We also use it to set up all
517 of the tables referenced in the other macros. */
519 #define OVERRIDE_OPTIONS override_options ()
521 /* Zero or more C statements that may conditionally modify two
522 variables `fixed_regs' and `call_used_regs' (both of type `char
523 []') after they have been initialized from the two preceding
526 This is necessary in case the fixed or call-clobbered registers
527 depend on target flags.
529 You need not define this macro if it has no work to do.
531 If the usage of an entire class of registers depends on the target
532 flags, you may indicate this to GCC by using this macro to modify
533 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
534 the classes which should not be used by GCC. Also define the macro
535 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
536 letter for a class that shouldn't be used.
538 (However, if this class is not included in `GENERAL_REGS' and all
539 of the insn patterns whose constraints permit this class are
540 controlled by target switches, then GCC will automatically avoid
541 using these registers when the target switches are opposed to
544 #define CONDITIONAL_REGISTER_USAGE \
547 if (!TARGET_HARD_FLOAT) \
551 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
552 fixed_regs[regno] = call_used_regs[regno] = 1; \
553 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
554 fixed_regs[regno] = call_used_regs[regno] = 1; \
556 else if (mips_isa < 4) \
560 /* We only have a single condition code register. We \
561 implement this by hiding all the condition code registers, \
562 and generating RTL that refers directly to ST_REG_FIRST. */ \
563 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
564 fixed_regs[regno] = call_used_regs[regno] = 1; \
566 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
570 /* This is meant to be redefined in the host dependent files. */
571 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
573 /* Show we can debug even without a frame pointer. */
574 #define CAN_DEBUG_WITHOUT_FP
576 /* Complain about missing specs and predefines that should be defined in each
577 of the target tm files to override the defaults. This is mostly a place-
578 holder until I can get each of the files updated [mm]. */
580 #if defined(OSF_OS) \
581 || defined(DECSTATION) \
582 || defined(SGI_TARGET) \
583 || defined(MIPS_NEWS) \
584 || defined(MIPS_SYSV) \
585 || defined(MIPS_SVR4) \
586 || defined(MIPS_BSD43)
588 #ifndef CPP_PREDEFINES
589 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
593 #error "Define LIB_SPEC in the appropriate tm.h file"
596 #ifndef STARTFILE_SPEC
597 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
601 #error "Define MACHINE_TYPE in the appropriate tm.h file"
605 /* Tell collect what flags to pass to nm. */
607 #define NM_FLAGS "-Bp"
611 /* Names to predefine in the preprocessor for this target machine. */
613 #ifndef CPP_PREDEFINES
614 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
615 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
616 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
619 /* Assembler specs. */
621 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
624 #define MIPS_AS_ASM_SPEC "\
625 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
626 %{pipe: %e-pipe is not supported.} \
627 %{K} %(subtarget_mips_as_asm_spec)"
629 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
630 rather than gas. It may be overridden by subtargets. */
632 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
633 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
636 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
639 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{v}"
641 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
642 GAS_ASM_SPEC as the default, depending upon the value of
645 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
648 #define TARGET_ASM_SPEC "\
649 %{mmips-as: %(mips_as_asm_spec)} \
650 %{!mmips-as: %(gas_asm_spec)}"
654 #define TARGET_ASM_SPEC "\
655 %{!mgas: %(mips_as_asm_spec)} \
656 %{mgas: %(gas_asm_spec)}"
660 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
661 to the assembler. It may be overridden by subtargets. */
662 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
663 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
665 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
668 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
669 the assembler. It may be overridden by subtargets. */
670 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
671 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
672 %{g} %{g0} %{g1} %{g2} %{g3} \
673 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
674 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
675 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
676 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
679 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
680 overridden by subtargets. */
682 #ifndef SUBTARGET_ASM_SPEC
683 #define SUBTARGET_ASM_SPEC ""
686 /* ASM_SPEC is the set of arguments to pass to the assembler. */
689 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
690 %(subtarget_asm_optimizing_spec) \
691 %(subtarget_asm_debugging_spec) \
693 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
695 %(subtarget_asm_spec)"
697 /* Specify to run a post-processor, mips-tfile after the assembler
698 has run to stuff the mips debug information into the object file.
699 This is needed because the $#!%^ MIPS assembler provides no way
700 of specifying such information in the assembly file. If we are
701 cross compiling, disable mips-tfile unless the user specifies
704 #ifndef ASM_FINAL_SPEC
705 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
707 #define ASM_FINAL_SPEC "\
708 %{mmips-as: %{!mno-mips-tfile: \
709 \n mips-tfile %{v*: -v} \
711 %{!K: %{save-temps: -I %b.o~}} \
712 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
713 %{.s:%i} %{!.s:%g.s}}}"
717 #define ASM_FINAL_SPEC "\
718 %{!mgas: %{!mno-mips-tfile: \
719 \n mips-tfile %{v*: -v} \
721 %{!K: %{save-temps: -I %b.o~}} \
722 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
723 %{.s:%i} %{!.s:%g.s}}}"
726 #endif /* ASM_FINAL_SPEC */
728 /* Redefinition of libraries used. Mips doesn't support normal
729 UNIX style profiling via calling _mcount. It does offer
730 profiling that samples the PC, so do what we can... */
733 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
736 /* Extra switches sometimes passed to the linker. */
737 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
738 will interpret it as a -b option. */
742 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
743 %{bestGnum} %{shared} %{non_shared}"
744 #endif /* LINK_SPEC defined */
746 /* Specs for the compiler proper */
750 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
751 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
752 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
753 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
754 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
755 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
756 %{m4650:-mcpu=r4650} \
757 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
758 %{pic-none: -mno-half-pic} \
759 %{pic-lib: -mhalf-pic} \
760 %{pic-extern: -mhalf-pic} \
761 %{pic-calls: -mhalf-pic} \
765 /* Preprocessor specs. */
767 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
768 be overridden by subtargets. */
770 #ifndef SUBTARGET_CPP_SIZE_SPEC
771 #define SUBTARGET_CPP_SIZE_SPEC "\
772 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
773 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
776 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
777 overridden by subtargets. */
778 #ifndef SUBTARGET_CPP_SPEC
779 #define SUBTARGET_CPP_SPEC ""
782 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
786 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
787 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
788 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
789 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
790 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
791 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
792 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
793 %(subtarget_cpp_size_spec) \
794 %{mips3:-U__mips -D__mips=3 -D__mips64} \
795 %{mips4:-U__mips -D__mips=4 -D__mips64} \
796 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
797 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
798 %{m4650:%{!msoft-float:-D__mips_single_float}} \
799 %{msoft-float:-D__mips_soft_float} \
800 %{mabi=eabi:-D__mips_eabi} \
801 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
802 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
803 %(subtarget_cpp_spec) "
806 /* This macro defines names of additional specifications to put in the specs
807 that can be used in various specifications like CC1_SPEC. Its definition
808 is an initializer with a subgrouping for each command option.
810 Each subgrouping contains a string constant, that defines the
811 specification name, and a string constant that used by the GNU CC driver
814 Do not define this macro if it does not need to do anything. */
816 #define EXTRA_SPECS \
817 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
818 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
819 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
820 { "gas_asm_spec", GAS_ASM_SPEC }, \
821 { "target_asm_spec", TARGET_ASM_SPEC }, \
822 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
823 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
824 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
825 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
826 SUBTARGET_EXTRA_SPECS
828 #ifndef SUBTARGET_EXTRA_SPECS
829 #define SUBTARGET_EXTRA_SPECS
832 /* If defined, this macro is an additional prefix to try after
833 `STANDARD_EXEC_PREFIX'. */
835 #ifndef MD_EXEC_PREFIX
836 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
839 #ifndef MD_STARTFILE_PREFIX
840 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
844 /* Print subsidiary information on the compiler version in use. */
846 #define MIPS_VERSION "[AL 1.1, MM 40]"
849 #define MACHINE_TYPE "BSD Mips"
852 #ifndef TARGET_VERSION_INTERNAL
853 #define TARGET_VERSION_INTERNAL(STREAM) \
854 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
857 #ifndef TARGET_VERSION
858 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
862 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
863 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
864 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
866 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
867 #define PREFERRED_DEBUGGING_TYPE ((!strncmp (str, "ggdb", 4)) ? DBX_DEBUG : SDB_DEBUG)
870 /* By default, turn on GDB extensions. */
871 #define DEFAULT_GDB_EXTENSIONS 1
873 /* If we are passing smuggling stabs through the MIPS ECOFF object
874 format, put a comment in front of the .stab<x> operation so
875 that the MIPS assembler does not choke. The mips-tfile program
876 will correctly put the stab into the object file. */
878 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
879 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
880 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
882 /* Local compiler-generated symbols must have a prefix that the assembler
883 understands. By default, this is $, although some targets (e.g.,
884 NetBSD-ELF) need to override this. */
886 #ifndef LOCAL_LABEL_PREFIX
887 #define LOCAL_LABEL_PREFIX "$"
890 /* By default on the mips, external symbols do not have an underscore
891 prepended, but some targets (e.g., NetBSD) require this. */
893 #ifndef USER_LABEL_PREFIX
894 #define USER_LABEL_PREFIX ""
897 /* Forward references to tags are allowed. */
898 #define SDB_ALLOW_FORWARD_REFERENCES
900 /* Unknown tags are also allowed. */
901 #define SDB_ALLOW_UNKNOWN_REFERENCES
903 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
904 since the length can run past this up to a continuation point. */
905 #define DBX_CONTIN_LENGTH 1500
907 /* How to renumber registers for dbx and gdb. */
908 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
910 /* The mapping from gcc register number to DWARF 2 CFA column number.
911 This mapping does not allow for tracking DBX register 0, since column 0
912 is used for the frame address, but since register 0 is fixed this is
913 not really a problem. */
914 #define DWARF_FRAME_REGNUM(REG) \
915 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN \
916 : DBX_REGISTER_NUMBER (REG))
918 /* The DWARF 2 CFA column which tracks the return address. */
919 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
921 /* Before the prologue, RA lives in r31. */
922 #define INCOMING_RETURN_ADDR_RTX gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
924 /* Overrides for the COFF debug format. */
925 #define PUT_SDB_SCL(a) \
927 extern FILE *asm_out_text_file; \
928 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
931 #define PUT_SDB_INT_VAL(a) \
933 extern FILE *asm_out_text_file; \
934 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
937 #define PUT_SDB_VAL(a) \
939 extern FILE *asm_out_text_file; \
940 fputs ("\t.val\t", asm_out_text_file); \
941 output_addr_const (asm_out_text_file, (a)); \
942 fputc (';', asm_out_text_file); \
945 #define PUT_SDB_DEF(a) \
947 extern FILE *asm_out_text_file; \
948 fprintf (asm_out_text_file, "\t%s.def\t", \
949 (TARGET_GAS) ? "" : "#"); \
950 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
951 fputc (';', asm_out_text_file); \
954 #define PUT_SDB_PLAIN_DEF(a) \
956 extern FILE *asm_out_text_file; \
957 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
958 (TARGET_GAS) ? "" : "#", (a)); \
961 #define PUT_SDB_ENDEF \
963 extern FILE *asm_out_text_file; \
964 fprintf (asm_out_text_file, "\t.endef\n"); \
967 #define PUT_SDB_TYPE(a) \
969 extern FILE *asm_out_text_file; \
970 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
973 #define PUT_SDB_SIZE(a) \
975 extern FILE *asm_out_text_file; \
976 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
979 #define PUT_SDB_DIM(a) \
981 extern FILE *asm_out_text_file; \
982 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
985 #ifndef PUT_SDB_START_DIM
986 #define PUT_SDB_START_DIM \
988 extern FILE *asm_out_text_file; \
989 fprintf (asm_out_text_file, "\t.dim\t"); \
993 #ifndef PUT_SDB_NEXT_DIM
994 #define PUT_SDB_NEXT_DIM(a) \
996 extern FILE *asm_out_text_file; \
997 fprintf (asm_out_text_file, "%d,", a); \
1001 #ifndef PUT_SDB_LAST_DIM
1002 #define PUT_SDB_LAST_DIM(a) \
1004 extern FILE *asm_out_text_file; \
1005 fprintf (asm_out_text_file, "%d;", a); \
1009 #define PUT_SDB_TAG(a) \
1011 extern FILE *asm_out_text_file; \
1012 fprintf (asm_out_text_file, "\t.tag\t"); \
1013 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1014 fputc (';', asm_out_text_file); \
1017 /* For block start and end, we create labels, so that
1018 later we can figure out where the correct offset is.
1019 The normal .ent/.end serve well enough for functions,
1020 so those are just commented out. */
1022 #define PUT_SDB_BLOCK_START(LINE) \
1024 extern FILE *asm_out_text_file; \
1025 fprintf (asm_out_text_file, \
1026 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1027 LOCAL_LABEL_PREFIX, \
1029 (TARGET_GAS) ? "" : "#", \
1030 LOCAL_LABEL_PREFIX, \
1033 sdb_label_count++; \
1036 #define PUT_SDB_BLOCK_END(LINE) \
1038 extern FILE *asm_out_text_file; \
1039 fprintf (asm_out_text_file, \
1040 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1041 LOCAL_LABEL_PREFIX, \
1043 (TARGET_GAS) ? "" : "#", \
1044 LOCAL_LABEL_PREFIX, \
1047 sdb_label_count++; \
1050 #define PUT_SDB_FUNCTION_START(LINE)
1052 #define PUT_SDB_FUNCTION_END(LINE) \
1054 extern FILE *asm_out_text_file; \
1055 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1058 #define PUT_SDB_EPILOGUE_END(NAME)
1060 #define PUT_SDB_SRC_FILE(FILENAME) \
1062 extern FILE *asm_out_text_file; \
1063 output_file_directive (asm_out_text_file, (FILENAME)); \
1066 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1067 sprintf ((BUFFER), ".%dfake", (NUMBER));
1069 /* Correct the offset of automatic variables and arguments. Note that
1070 the MIPS debug format wants all automatic variables and arguments
1071 to be in terms of the virtual frame pointer (stack pointer before
1072 any adjustment in the function), while the MIPS 3.0 linker wants
1073 the frame pointer to be the stack pointer after the initial
1076 #define DEBUGGER_AUTO_OFFSET(X) mips_debugger_offset (X, 0)
1077 #define DEBUGGER_ARG_OFFSET(OFFSET, X) mips_debugger_offset (X, OFFSET)
1080 /* Tell collect that the object format is ECOFF */
1081 #ifndef OBJECT_FORMAT_ROSE
1082 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1083 #define EXTENDED_COFF /* ECOFF, not normal coff */
1086 #if 0 /* These definitions normally have no effect because
1087 MIPS systems define USE_COLLECT2, so
1088 assemble_constructor does nothing anyway. */
1090 /* Don't use the default definitions, because we don't have gld.
1091 Also, we don't want stabs when generating ECOFF output.
1092 Instead we depend on collect to handle these. */
1094 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1095 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1099 /* Target machine storage layout */
1101 /* Define in order to support both big and little endian float formats
1102 in the same gcc binary. */
1103 #define REAL_ARITHMETIC
1105 /* Define this if most significant bit is lowest numbered
1106 in instructions that operate on numbered bit-fields.
1108 #define BITS_BIG_ENDIAN 0
1110 /* Define this if most significant byte of a word is the lowest numbered. */
1111 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1113 /* Define this if most significant word of a multiword number is the lowest. */
1114 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1116 /* Define this to set the endianness to use in libgcc2.c, which can
1117 not depend on target_flags. */
1118 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1119 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1121 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1124 /* Number of bits in an addressable storage unit */
1125 #define BITS_PER_UNIT 8
1127 /* Width in bits of a "word", which is the contents of a machine register.
1128 Note that this is not necessarily the width of data type `int';
1129 if using 16-bit ints on a 68000, this would still be 32.
1130 But on a machine with 16-bit registers, this would be 16. */
1131 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1132 #define MAX_BITS_PER_WORD 64
1134 /* Width of a word, in units (bytes). */
1135 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1136 #define MIN_UNITS_PER_WORD 4
1138 /* For MIPS, width of a floating point register. */
1139 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1141 /* A C expression for the size in bits of the type `int' on the
1142 target machine. If you don't define this, the default is one
1144 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1145 #define MAX_INT_TYPE_SIZE 64
1147 /* Tell the preprocessor the maximum size of wchar_t. */
1148 #ifndef MAX_WCHAR_TYPE_SIZE
1149 #ifndef WCHAR_TYPE_SIZE
1150 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1154 /* A C expression for the size in bits of the type `short' on the
1155 target machine. If you don't define this, the default is half a
1156 word. (If this would be less than one storage unit, it is
1157 rounded up to one unit.) */
1158 #define SHORT_TYPE_SIZE 16
1160 /* A C expression for the size in bits of the type `long' on the
1161 target machine. If you don't define this, the default is one
1163 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1164 #define MAX_LONG_TYPE_SIZE 64
1166 /* A C expression for the size in bits of the type `long long' on the
1167 target machine. If you don't define this, the default is two
1169 #define LONG_LONG_TYPE_SIZE 64
1171 /* A C expression for the size in bits of the type `char' on the
1172 target machine. If you don't define this, the default is one
1173 quarter of a word. (If this would be less than one storage unit,
1174 it is rounded up to one unit.) */
1175 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1177 /* A C expression for the size in bits of the type `float' on the
1178 target machine. If you don't define this, the default is one
1180 #define FLOAT_TYPE_SIZE 32
1182 /* A C expression for the size in bits of the type `double' on the
1183 target machine. If you don't define this, the default is two
1185 #define DOUBLE_TYPE_SIZE 64
1187 /* A C expression for the size in bits of the type `long double' on
1188 the target machine. If you don't define this, the default is two
1190 #define LONG_DOUBLE_TYPE_SIZE 64
1192 /* Width in bits of a pointer.
1193 See also the macro `Pmode' defined below. */
1194 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1196 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1197 #define POINTER_BOUNDARY (TARGET_LONG64 ? 64 : 32)
1199 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1200 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1202 /* Allocation boundary (in *bits*) for the code of a function. */
1203 #define FUNCTION_BOUNDARY 32
1205 /* Alignment of field after `int : 0' in a structure. */
1206 #define EMPTY_FIELD_BOUNDARY 32
1208 /* Every structure's size must be a multiple of this. */
1209 /* 8 is observed right on a DECstation and on riscos 4.02. */
1210 #define STRUCTURE_SIZE_BOUNDARY 8
1212 /* There is no point aligning anything to a rounder boundary than this. */
1213 #define BIGGEST_ALIGNMENT 64
1215 /* Biggest alignment any structure field can require in bits. */
1216 #define BIGGEST_FIELD_ALIGNMENT 64
1218 /* Set this nonzero if move instructions will actually fail to work
1219 when given unaligned data. */
1220 #define STRICT_ALIGNMENT 1
1222 /* Define this if you wish to imitate the way many other C compilers
1223 handle alignment of bitfields and the structures that contain
1226 The behavior is that the type written for a bitfield (`int',
1227 `short', or other integer type) imposes an alignment for the
1228 entire structure, as if the structure really did contain an
1229 ordinary field of that type. In addition, the bitfield is placed
1230 within the structure so that it would fit within such a field,
1231 not crossing a boundary for it.
1233 Thus, on most machines, a bitfield whose type is written as `int'
1234 would not cross a four-byte boundary, and would force four-byte
1235 alignment for the whole structure. (The alignment used may not
1236 be four bytes; it is controlled by the other alignment
1239 If the macro is defined, its definition should be a C expression;
1240 a nonzero value for the expression enables this behavior. */
1242 #define PCC_BITFIELD_TYPE_MATTERS 1
1244 /* If defined, a C expression to compute the alignment given to a
1245 constant that is being placed in memory. CONSTANT is the constant
1246 and ALIGN is the alignment that the object would ordinarily have.
1247 The value of this macro is used instead of that alignment to align
1250 If this macro is not defined, then ALIGN is used.
1252 The typical use of this macro is to increase alignment for string
1253 constants to be word aligned so that `strcpy' calls that copy
1254 constants can be done inline. */
1256 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1257 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1258 && (ALIGN) < BITS_PER_WORD \
1262 /* If defined, a C expression to compute the alignment for a static
1263 variable. TYPE is the data type, and ALIGN is the alignment that
1264 the object would ordinarily have. The value of this macro is used
1265 instead of that alignment to align the object.
1267 If this macro is not defined, then ALIGN is used.
1269 One use of this macro is to increase alignment of medium-size
1270 data to make it all fit in fewer cache lines. Another is to
1271 cause character arrays to be word-aligned so that `strcpy' calls
1272 that copy constants to character arrays can be done inline. */
1274 #undef DATA_ALIGNMENT
1275 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1276 ((((ALIGN) < BITS_PER_WORD) \
1277 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1278 || TREE_CODE (TYPE) == UNION_TYPE \
1279 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1281 /* Define this macro if an argument declared as `char' or `short' in a
1282 prototype should actually be passed as an `int'. In addition to
1283 avoiding errors in certain cases of mismatch, it also makes for
1284 better code on certain machines. */
1286 #define PROMOTE_PROTOTYPES
1288 /* Define if operations between registers always perform the operation
1289 on the full register even if a narrower mode is specified. */
1290 #define WORD_REGISTER_OPERATIONS
1292 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1293 will either zero-extend or sign-extend. The value of this macro should
1294 be the code that says which one of the two operations is implicitly
1295 done, NIL if none. */
1296 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1298 /* Standard register usage. */
1300 /* Number of actual hardware registers.
1301 The hardware registers are assigned numbers for the compiler
1302 from 0 to just below FIRST_PSEUDO_REGISTER.
1303 All registers that the compiler knows about must be given numbers,
1304 even those that are not normally considered general registers.
1306 On the Mips, we have 32 integer registers, 32 floating point
1307 registers, 8 condition code registers, and the special registers
1308 hi, lo, hilo, and rap. The 8 condition code registers are only
1309 used if mips_isa >= 4. The hilo register is only used in 64 bit
1310 mode. It represents a 64 bit value stored as two 32 bit values in
1311 the hi and lo registers; this is the result of the mult
1312 instruction. rap is a pointer to the stack where the return
1313 address reg ($31) was stored. This is needed for C++ exception
1316 #define FIRST_PSEUDO_REGISTER 76
1318 /* 1 for registers that have pervasive standard uses
1319 and are not available for the register allocator.
1321 On the MIPS, see conventions, page D-2 */
1323 #define FIXED_REGISTERS \
1325 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1326 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1327 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1328 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1329 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1333 /* 1 for registers not available across function calls.
1334 These must include the FIXED_REGISTERS and also any
1335 registers that can be used without being saved.
1336 The latter must include the registers where values are returned
1337 and the register where structure-value addresses are passed.
1338 Aside from that, you can include as many other registers as you like. */
1340 #define CALL_USED_REGISTERS \
1342 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1343 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1344 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1345 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1346 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1350 /* Internal macros to classify a register number as to whether it's a
1351 general purpose register, a floating point register, a
1352 multiply/divide register, or a status register. */
1354 #define GP_REG_FIRST 0
1355 #define GP_REG_LAST 31
1356 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1357 #define GP_DBX_FIRST 0
1359 #define FP_REG_FIRST 32
1360 #define FP_REG_LAST 63
1361 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1362 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1364 #define MD_REG_FIRST 64
1365 #define MD_REG_LAST 66
1366 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1368 #define ST_REG_FIRST 67
1369 #define ST_REG_LAST 74
1370 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1372 #define RAP_REG_NUM 75
1374 #define AT_REGNUM (GP_REG_FIRST + 1)
1375 #define HI_REGNUM (MD_REG_FIRST + 0)
1376 #define LO_REGNUM (MD_REG_FIRST + 1)
1377 #define HILO_REGNUM (MD_REG_FIRST + 2)
1379 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1380 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1381 should be used instead. */
1382 #define FPSW_REGNUM ST_REG_FIRST
1384 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1385 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1386 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1387 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1389 /* Return number of consecutive hard regs needed starting at reg REGNO
1390 to hold something of mode MODE.
1391 This is ordinarily the length in words of a value of mode MODE
1392 but can be less for certain modes in special long registers.
1394 On the MIPS, all general registers are one word long. Except on
1395 the R4000 with the FR bit set, the floating point uses register
1396 pairs, with the second register not being allocatable. */
1398 #define HARD_REGNO_NREGS(REGNO, MODE) \
1399 (! FP_REG_P (REGNO) \
1400 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1401 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1403 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1404 MODE. In 32 bit mode, require that DImode and DFmode be in even
1405 registers. For DImode, this makes some of the insns easier to
1406 write, since you don't have to worry about a DImode value in
1407 registers 3 & 4, producing a result in 4 & 5.
1409 To make the code simpler HARD_REGNO_MODE_OK now just references an
1410 array built in override_options. Because machmodes.h is not yet
1411 included before this file is processed, the MODE bound can't be
1414 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1416 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1417 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1419 /* Value is 1 if it is a good idea to tie two pseudo registers
1420 when one has mode MODE1 and one has mode MODE2.
1421 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1422 for any hard reg, then this must be 0 for correct output. */
1423 #define MODES_TIEABLE_P(MODE1, MODE2) \
1424 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1425 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1426 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1427 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1429 /* MIPS pc is not overloaded on a register. */
1430 /* #define PC_REGNUM xx */
1432 /* Register to use for pushing function arguments. */
1433 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1435 /* Offset from the stack pointer to the first available location. */
1436 #define STACK_POINTER_OFFSET 0
1438 /* Base register for access to local variables of the function. */
1439 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 30)
1441 /* Value should be nonzero if functions must have frame pointers.
1442 Zero means the frame pointer need not be set up (and parms
1443 may be accessed via the stack pointer) in functions that seem suitable.
1444 This is computed in `reload', in reload1.c. */
1445 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1447 /* Base register for access to arguments of the function. */
1448 #define ARG_POINTER_REGNUM GP_REG_FIRST
1450 /* Fake register that holds the address on the stack of the
1451 current function's return address. */
1452 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1454 /* Register in which static-chain is passed to a function. */
1455 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1457 /* If the structure value address is passed in a register, then
1458 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1459 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1461 /* If the structure value address is not passed in a register, define
1462 `STRUCT_VALUE' as an expression returning an RTX for the place
1463 where the address is passed. If it returns 0, the address is
1464 passed as an "invisible" first argument. */
1465 #define STRUCT_VALUE 0
1467 /* Mips registers used in prologue/epilogue code when the stack frame
1468 is larger than 32K bytes. These registers must come from the
1469 scratch register set, and not used for passing and returning
1470 arguments and any other information used in the calling sequence
1471 (such as pic). Must start at 12, since t0/t3 are parameter passing
1472 registers in the 64 bit ABI. */
1474 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1475 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1477 /* Define this macro if it is as good or better to call a constant
1478 function address than to call an address kept in a register. */
1479 #define NO_FUNCTION_CSE 1
1481 /* Define this macro if it is as good or better for a function to
1482 call itself with an explicit address than to call an address
1483 kept in a register. */
1484 #define NO_RECURSIVE_FUNCTION_CSE 1
1486 /* The register number of the register used to address a table of
1487 static data addresses in memory. In some cases this register is
1488 defined by a processor's "application binary interface" (ABI).
1489 When this macro is defined, RTL is generated for this register
1490 once, as with the stack pointer and frame pointer registers. If
1491 this macro is not defined, it is up to the machine-dependent
1492 files to allocate such a register (if necessary). */
1493 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1495 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1497 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1498 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1499 isn't always called for static inline functions. */
1500 #define INIT_EXPANDERS embedded_pic_fnaddr_rtx = NULL;
1502 /* Define the classes of registers for register constraints in the
1503 machine description. Also define ranges of constants.
1505 One of the classes must always be named ALL_REGS and include all hard regs.
1506 If there is more than one class, another class must be named NO_REGS
1507 and contain no registers.
1509 The name GENERAL_REGS must be the name of a class (or an alias for
1510 another name such as ALL_REGS). This is the class of registers
1511 that is allowed by "g" or "r" in a register constraint.
1512 Also, registers outside this class are allocated only when
1513 instructions express preferences for them.
1515 The classes must be numbered in nondecreasing order; that is,
1516 a larger-numbered class must never be contained completely
1517 in a smaller-numbered class.
1519 For any two classes, it is very desirable that there be another
1520 class that represents their union. */
1524 NO_REGS, /* no registers in set */
1525 GR_REGS, /* integer registers */
1526 FP_REGS, /* floating point registers */
1527 HI_REG, /* hi register */
1528 LO_REG, /* lo register */
1529 HILO_REG, /* hilo register pair for 64 bit mode mult */
1530 MD_REGS, /* multiply/divide registers (hi/lo) */
1531 ST_REGS, /* status registers (fp status) */
1532 ALL_REGS, /* all registers */
1533 LIM_REG_CLASSES /* max value + 1 */
1536 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1538 #define GENERAL_REGS GR_REGS
1540 /* An initializer containing the names of the register classes as C
1541 string constants. These names are used in writing some of the
1544 #define REG_CLASS_NAMES \
1557 /* An initializer containing the contents of the register classes,
1558 as integers which are bit masks. The Nth integer specifies the
1559 contents of class N. The way the integer MASK is interpreted is
1560 that register R is in the class if `MASK & (1 << R)' is 1.
1562 When the machine has more than 32 registers, an integer does not
1563 suffice. Then the integers are replaced by sub-initializers,
1564 braced groupings containing several integers. Each
1565 sub-initializer must be suitable as an initializer for the type
1566 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1568 #define REG_CLASS_CONTENTS \
1570 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1571 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1572 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1573 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1574 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1575 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1576 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1577 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1578 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1582 /* A C expression whose value is a register class containing hard
1583 register REGNO. In general there is more that one such class;
1584 choose a class which is "minimal", meaning that no smaller class
1585 also contains the register. */
1587 extern enum reg_class mips_regno_to_class[];
1589 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1591 /* A macro whose definition is the name of the class to which a
1592 valid base register must belong. A base register is one used in
1593 an address which is the register value plus a displacement. */
1595 #define BASE_REG_CLASS GR_REGS
1597 /* A macro whose definition is the name of the class to which a
1598 valid index register must belong. An index register is one used
1599 in an address where its value is either multiplied by a scale
1600 factor or added to another register (as well as added to a
1603 #define INDEX_REG_CLASS NO_REGS
1606 /* REGISTER AND CONSTANT CLASSES */
1608 /* Get reg_class from a letter such as appears in the machine
1611 DEFINED REGISTER CLASSES:
1613 'd' General (aka integer) registers
1614 'f' Floating point registers
1617 'x' Multiply/divide registers
1619 'z' FP Status register
1620 'b' All registers */
1622 extern enum reg_class mips_char_to_class[];
1624 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1626 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1627 string can be used to stand for particular ranges of immediate
1628 operands. This macro defines what the ranges are. C is the
1629 letter, and VALUE is a constant value. Return 1 if VALUE is
1630 in the range specified by C. */
1634 `I' is used for the range of constants an arithmetic insn can
1635 actually contain (16 bits signed integers).
1637 `J' is used for the range which is just zero (ie, $r0).
1639 `K' is used for the range of constants a logical insn can actually
1640 contain (16 bit zero-extended integers).
1642 `L' is used for the range of constants that be loaded with lui
1643 (ie, the bottom 16 bits are zero).
1645 `M' is used for the range of constants that take two words to load
1646 (ie, not matched by `I', `K', and `L').
1648 `N' is used for negative 16 bit constants.
1650 `O' is an exact power of 2 (not yet used in the md file).
1652 `P' is used for positive 16 bit constants. */
1654 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1655 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1657 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1658 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1659 : (C) == 'J' ? ((VALUE) == 0) \
1660 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1661 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1662 && (((VALUE) & ~2147483647) == 0 \
1663 || ((VALUE) & ~2147483647) == ~2147483647)) \
1664 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1665 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1666 && (((VALUE) & 0x0000ffff) != 0 \
1667 || (((VALUE) & ~2147483647) != 0 \
1668 && ((VALUE) & ~2147483647) != ~2147483647))) \
1669 : (C) == 'N' ? (((VALUE) & ~0x0000ffff) == ~0x0000ffff) \
1670 : (C) == 'O' ? (exact_log2 (VALUE) >= 0) \
1671 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1674 /* Similar, but for floating constants, and defining letters G and H.
1675 Here VALUE is the CONST_DOUBLE rtx itself. */
1679 'G' : Floating point 0 */
1681 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1683 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1685 /* Letters in the range `Q' through `U' may be defined in a
1686 machine-dependent fashion to stand for arbitrary operand types.
1687 The machine description macro `EXTRA_CONSTRAINT' is passed the
1688 operand as its first argument and the constraint letter as its
1691 `Q' is for memory references which take more than 1 instruction.
1692 `R' is for memory references which take 1 word for the instruction.
1693 `S' is for references to extern items which are PIC for OSF/rose. */
1695 #define EXTRA_CONSTRAINT(OP,CODE) \
1696 ((GET_CODE (OP) != MEM) ? FALSE \
1697 : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \
1698 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1699 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1700 && HALF_PIC_ADDRESS_P (OP)) \
1703 /* Given an rtx X being reloaded into a reg required to be
1704 in class CLASS, return the class of reg to actually use.
1705 In general this is just CLASS; but on some machines
1706 in some cases it is preferable to use a more restrictive class. */
1708 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1709 ((CLASS) != ALL_REGS \
1711 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1712 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1713 ? (TARGET_SOFT_FLOAT ? GR_REGS : FP_REGS) \
1714 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1715 || GET_MODE (X) == VOIDmode) \
1719 /* Certain machines have the property that some registers cannot be
1720 copied to some other registers without using memory. Define this
1721 macro on those machines to be a C expression that is non-zero if
1722 objects of mode MODE in registers of CLASS1 can only be copied to
1723 registers of class CLASS2 by storing a register of CLASS1 into
1724 memory and loading that memory location into a register of CLASS2.
1726 Do not define this macro if its value would always be zero. */
1728 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1729 ((!TARGET_DEBUG_H_MODE \
1730 && GET_MODE_CLASS (MODE) == MODE_INT \
1731 && ((CLASS1 == FP_REGS && CLASS2 == GR_REGS) \
1732 || (CLASS1 == GR_REGS && CLASS2 == FP_REGS))) \
1733 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1734 && ((CLASS1 == GR_REGS && CLASS2 == FP_REGS) \
1735 || (CLASS2 == GR_REGS && CLASS1 == FP_REGS))))
1737 /* The HI and LO registers can only be reloaded via the general
1738 registers. Condition code registers can only be loaded to the
1739 general registers, and from the floating point registers. */
1741 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1742 mips_secondary_reload_class (CLASS, MODE, X, 1)
1743 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1744 mips_secondary_reload_class (CLASS, MODE, X, 0)
1746 /* Not declared above, with the other functions, because enum
1747 reg_class is not declared yet. */
1748 extern enum reg_class mips_secondary_reload_class ();
1750 /* Return the maximum number of consecutive registers
1751 needed to represent mode MODE in a register of class CLASS. */
1753 #define CLASS_UNITS(mode, size) \
1754 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1756 #define CLASS_MAX_NREGS(CLASS, MODE) \
1757 ((CLASS) == FP_REGS \
1759 ? CLASS_UNITS (MODE, 8) \
1760 : 2 * CLASS_UNITS (MODE, 8)) \
1761 : CLASS_UNITS (MODE, UNITS_PER_WORD))
1763 /* If defined, this is a C expression whose value should be
1764 nonzero if the insn INSN has the effect of mysteriously
1765 clobbering the contents of hard register number REGNO. By
1766 "mysterious" we mean that the insn's RTL expression doesn't
1767 describe such an effect.
1769 If this macro is not defined, it means that no insn clobbers
1770 registers mysteriously. This is the usual situation; all else
1771 being equal, it is best for the RTL expression to show all the
1774 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
1777 /* Stack layout; function entry, exit and calling. */
1779 /* Define this if pushing a word on the stack
1780 makes the stack pointer a smaller address. */
1781 #define STACK_GROWS_DOWNWARD
1783 /* Define this if the nominal address of the stack frame
1784 is at the high-address end of the local variables;
1785 that is, each additional local variable allocated
1786 goes at a more negative offset in the frame. */
1787 /* #define FRAME_GROWS_DOWNWARD */
1789 /* Offset within stack frame to start allocating local variables at.
1790 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1791 first local allocated. Otherwise, it is the offset to the BEGINNING
1792 of the first local allocated. */
1793 #define STARTING_FRAME_OFFSET \
1794 (current_function_outgoing_args_size \
1795 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1797 /* Offset from the stack pointer register to an item dynamically
1798 allocated on the stack, e.g., by `alloca'.
1800 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1801 length of the outgoing arguments. The default is correct for most
1802 machines. See `function.c' for details.
1804 The MIPS ABI states that functions which dynamically allocate the
1805 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
1806 we are trying to create a second frame pointer to the function, so
1807 allocate some stack space to make it happy.
1809 However, the linker currently complains about linking any code that
1810 dynamically allocates stack space, and there seems to be a bug in
1811 STACK_DYNAMIC_OFFSET, so don't define this right now. */
1814 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1815 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
1816 ? 4*UNITS_PER_WORD \
1817 : current_function_outgoing_args_size)
1820 /* The return address for the current frame is in r31 is this is a leaf
1821 function. Otherwise, it is on the stack. It is at a variable offset
1822 from sp/fp/ap, so we define a fake hard register rap which is a
1823 poiner to the return address on the stack. This always gets eliminated
1824 during reload to be either the frame pointer or the stack pointer plus
1827 /* ??? This definition fails for leaf functions. There is currently no
1828 general solution for this problem. */
1830 /* ??? There appears to be no way to get the return address of any previous
1831 frame except by disassembling instructions in the prologue/epilogue.
1832 So currently we support only the current frame. */
1834 #define RETURN_ADDR_RTX(count, frame) \
1836 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
1839 /* Structure to be filled in by compute_frame_size with register
1840 save masks, and offsets for the current function. */
1842 struct mips_frame_info
1844 long total_size; /* # bytes that the entire frame takes up */
1845 long var_size; /* # bytes that variables take up */
1846 long args_size; /* # bytes that outgoing arguments take up */
1847 long extra_size; /* # bytes of extra gunk */
1848 int gp_reg_size; /* # bytes needed to store gp regs */
1849 int fp_reg_size; /* # bytes needed to store fp regs */
1850 long mask; /* mask of saved gp registers */
1851 long fmask; /* mask of saved fp registers */
1852 long gp_save_offset; /* offset from vfp to store gp registers */
1853 long fp_save_offset; /* offset from vfp to store fp registers */
1854 long gp_sp_offset; /* offset from new sp to store gp registers */
1855 long fp_sp_offset; /* offset from new sp to store fp registers */
1856 int initialized; /* != 0 if frame size already calculated */
1857 int num_gp; /* number of gp registers saved */
1858 int num_fp; /* number of fp registers saved */
1861 extern struct mips_frame_info current_frame_info;
1863 /* If defined, this macro specifies a table of register pairs used to
1864 eliminate unneeded registers that point into the stack frame. If
1865 it is not defined, the only elimination attempted by the compiler
1866 is to replace references to the frame pointer with references to
1869 The definition of this macro is a list of structure
1870 initializations, each of which specifies an original and
1871 replacement register.
1873 On some machines, the position of the argument pointer is not
1874 known until the compilation is completed. In such a case, a
1875 separate hard register must be used for the argument pointer.
1876 This register can be eliminated by replacing it with either the
1877 frame pointer or the argument pointer, depending on whether or not
1878 the frame pointer has been eliminated.
1880 In this case, you might specify:
1881 #define ELIMINABLE_REGS \
1882 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1883 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1884 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1886 Note that the elimination of the argument pointer with the stack
1887 pointer is specified first since that is the preferred elimination. */
1889 #define ELIMINABLE_REGS \
1890 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1891 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1892 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1893 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1894 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1896 /* A C expression that returns non-zero if the compiler is allowed to
1897 try to replace register number FROM-REG with register number
1898 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
1899 defined, and will usually be the constant 1, since most of the
1900 cases preventing register elimination are things that the compiler
1901 already knows about. */
1903 #define CAN_ELIMINATE(FROM, TO) \
1904 (!frame_pointer_needed \
1905 || ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1906 || ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
1907 && (TO) == FRAME_POINTER_REGNUM))
1909 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1910 specifies the initial difference between the specified pair of
1911 registers. This macro must be defined if `ELIMINABLE_REGS' is
1914 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1915 { compute_frame_size (get_frame_size ()); \
1916 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1918 else if ((FROM) == ARG_POINTER_REGNUM \
1919 && ((TO) == FRAME_POINTER_REGNUM \
1920 || (TO) == STACK_POINTER_REGNUM)) \
1921 (OFFSET) = (current_frame_info.total_size \
1922 - ((mips_abi != ABI_32 && mips_abi != ABI_EABI) \
1923 ? current_function_pretend_args_size \
1925 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
1926 && ((TO) == FRAME_POINTER_REGNUM \
1927 || (TO) == STACK_POINTER_REGNUM)) \
1928 (OFFSET) = current_frame_info.gp_sp_offset; \
1933 /* If we generate an insn to push BYTES bytes,
1934 this says how many the stack pointer really advances by.
1935 On the vax, sp@- in a byte insn really pushes a word. */
1937 /* #define PUSH_ROUNDING(BYTES) 0 */
1939 /* If defined, the maximum amount of space required for outgoing
1940 arguments will be computed and placed into the variable
1941 `current_function_outgoing_args_size'. No space will be pushed
1942 onto the stack for each call; instead, the function prologue
1943 should increase the stack frame size by this amount.
1945 It is not proper to define both `PUSH_ROUNDING' and
1946 `ACCUMULATE_OUTGOING_ARGS'. */
1947 #define ACCUMULATE_OUTGOING_ARGS
1949 /* Offset from the argument pointer register to the first argument's
1950 address. On some machines it may depend on the data type of the
1953 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
1954 the first argument's address.
1956 On the MIPS, we must skip the first argument position if we are
1957 returning a structure or a union, to account for its address being
1958 passed in $4. However, at the current time, this produces a compiler
1959 that can't bootstrap, so comment it out for now. */
1962 #define FIRST_PARM_OFFSET(FNDECL) \
1964 && TREE_TYPE (FNDECL) != 0 \
1965 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
1966 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
1967 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
1971 #define FIRST_PARM_OFFSET(FNDECL) 0
1974 /* When a parameter is passed in a register, stack space is still
1975 allocated for it. For the MIPS, stack space must be allocated, cf
1976 Asm Lang Prog Guide page 7-8.
1978 BEWARE that some space is also allocated for non existing arguments
1979 in register. In case an argument list is of form GF used registers
1980 are a0 (a2,a3), but we should push over a1... */
1982 #define REG_PARM_STACK_SPACE(FNDECL) \
1983 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
1985 /* Define this if it is the responsibility of the caller to
1986 allocate the area reserved for arguments passed in registers.
1987 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1988 of this macro is to determine whether the space is included in
1989 `current_function_outgoing_args_size'. */
1990 #define OUTGOING_REG_PARM_STACK_SPACE
1992 /* Align stack frames on 64 bits (Double Word ). */
1993 #define STACK_BOUNDARY 64
1995 /* Make sure 4 words are always allocated on the stack. */
1997 #ifndef STACK_ARGS_ADJUST
1998 #define STACK_ARGS_ADJUST(SIZE) \
2000 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2001 SIZE.constant = 4 * UNITS_PER_WORD; \
2006 /* A C expression that should indicate the number of bytes of its
2007 own arguments that a function function pops on returning, or 0
2008 if the function pops no arguments and the caller must therefore
2009 pop them all after the function returns.
2011 FUNDECL is the declaration node of the function (as a tree).
2013 FUNTYPE is a C variable whose value is a tree node that
2014 describes the function in question. Normally it is a node of
2015 type `FUNCTION_TYPE' that describes the data type of the function.
2016 From this it is possible to obtain the data types of the value
2017 and arguments (if known).
2019 When a call to a library function is being considered, FUNTYPE
2020 will contain an identifier node for the library function. Thus,
2021 if you need to distinguish among various library functions, you
2022 can do so by their names. Note that "library function" in this
2023 context means a function used to perform arithmetic, whose name
2024 is known specially in the compiler and was not mentioned in the
2025 C code being compiled.
2027 STACK-SIZE is the number of bytes of arguments passed on the
2028 stack. If a variable number of bytes is passed, it is zero, and
2029 argument popping will always be the responsibility of the
2030 calling function. */
2032 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2035 /* Symbolic macros for the registers used to return integer and floating
2038 #define GP_RETURN (GP_REG_FIRST + 2)
2039 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2041 /* Symbolic macros for the first/last argument registers. */
2043 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2044 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2045 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2046 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2048 #define MAX_ARGS_IN_REGISTERS 4
2050 /* Define how to find the value returned by a library function
2051 assuming the value has mode MODE. */
2053 #define LIBCALL_VALUE(MODE) \
2054 gen_rtx (REG, MODE, \
2055 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2056 && (! TARGET_SINGLE_FLOAT \
2057 || GET_MODE_SIZE (MODE) <= 4)) \
2061 /* Define how to find the value returned by a function.
2062 VALTYPE is the data type of the value (as a tree).
2063 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2064 otherwise, FUNC is 0. */
2066 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2069 /* 1 if N is a possible register number for a function value.
2070 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2071 Currently, R2 and F0 are only implemented here (C has no complex type) */
2073 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2075 /* 1 if N is a possible register number for function argument passing.
2076 We have no FP argument registers when soft-float. When FP registers
2077 are 32 bits, we can't directly reference the odd numbered ones. */
2079 #define FUNCTION_ARG_REGNO_P(N) \
2080 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2081 || (! TARGET_SOFT_FLOAT \
2082 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2083 && (TARGET_FLOAT64 || (0 == (N) % 2))))
2085 /* A C expression which can inhibit the returning of certain function
2086 values in registers, based on the type of value. A nonzero value says
2087 to return the function value in memory, just as large structures are
2088 always returned. Here TYPE will be a C expression of type
2089 `tree', representing the data type of the value.
2091 Note that values of mode `BLKmode' must be explicitly
2092 handled by this macro. Also, the option `-fpcc-struct-return'
2093 takes effect regardless of this macro. On most systems, it is
2094 possible to leave the macro undefined; this causes a default
2095 definition to be used, whose value is the constant 1 for BLKmode
2096 values, and 0 otherwise.
2098 GCC normally converts 1 byte structures into chars, 2 byte
2099 structs into shorts, and 4 byte structs into ints, and returns
2100 them this way. Defining the following macro overrides this,
2101 to give us MIPS cc compatibility. */
2103 #define RETURN_IN_MEMORY(TYPE) \
2104 (TYPE_MODE (TYPE) == BLKmode)
2106 /* A code distinguishing the floating point format of the target
2107 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2108 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2110 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2113 /* Define a data type for recording info about an argument list
2114 during the scan of that argument list. This data type should
2115 hold all necessary information about the function itself
2116 and about the args processed so far, enough to enable macros
2117 such as FUNCTION_ARG to determine where the next arg should go.
2120 typedef struct mips_args {
2121 int gp_reg_found; /* whether a gp register was found yet */
2122 int arg_number; /* argument number */
2123 int arg_words; /* # total words the arguments take */
2124 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2125 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2126 int num_adjusts; /* number of adjustments made */
2127 /* Adjustments made to args pass in regs. */
2128 /* ??? The size is doubled to work around a
2129 bug in the code that sets the adjustments
2131 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2134 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2135 for a call to a function whose data type is FNTYPE.
2136 For a library call, FNTYPE is 0.
2140 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2141 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2143 /* Update the data in CUM to advance over an argument
2144 of mode MODE and data type TYPE.
2145 (TYPE is null for libcalls where that information may not be available.) */
2147 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2148 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2150 /* Determine where to put an argument to a function.
2151 Value is zero to push the argument on the stack,
2152 or a hard register in which to store the argument.
2154 MODE is the argument's machine mode.
2155 TYPE is the data type of the argument (as a tree).
2156 This is null for libcalls where that information may
2158 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2159 the preceding args and about the function being called.
2160 NAMED is nonzero if this argument is a named parameter
2161 (otherwise it is an extra parameter matching an ellipsis). */
2163 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2164 function_arg( &CUM, MODE, TYPE, NAMED)
2166 /* For an arg passed partly in registers and partly in memory,
2167 this is the number of registers used.
2168 For args passed entirely in registers or entirely in memory, zero. */
2170 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2171 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2173 /* If defined, a C expression that gives the alignment boundary, in
2174 bits, of an argument with the specified mode and type. If it is
2175 not defined, `PARM_BOUNDARY' is used for all arguments. */
2177 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2179 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2181 : TYPE_ALIGN(TYPE)) \
2182 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2184 : GET_MODE_ALIGNMENT(MODE)))
2187 /* This macro generates the assembly code for function entry.
2188 FILE is a stdio stream to output the code to.
2189 SIZE is an int: how many units of temporary storage to allocate.
2190 Refer to the array `regs_ever_live' to determine which registers
2191 to save; `regs_ever_live[I]' is nonzero if register number I
2192 is ever used in the function. This macro is responsible for
2193 knowing which registers should not be saved even if used. */
2195 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2197 /* This macro generates the assembly code for function exit,
2198 on machines that need it. If FUNCTION_EPILOGUE is not defined
2199 then individual return instructions are generated for each
2200 return statement. Args are same as for FUNCTION_PROLOGUE. */
2202 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2204 /* Define the number of delay slots needed for the function epilogue.
2206 On the mips, we need a slot if either no stack has been allocated,
2207 or the only register saved is the return register. */
2209 #define DELAY_SLOTS_FOR_EPILOGUE mips_epilogue_delay_slots ()
2211 /* Define whether INSN can be placed in delay slot N for the epilogue.
2212 No references to the stack must be made, since on the MIPS, the
2213 delay slot is done after the stack has been cleaned up. */
2215 #define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N) \
2216 (get_attr_dslot (INSN) == DSLOT_NO \
2217 && get_attr_length (INSN) == 1 \
2218 && ! epilogue_reg_mentioned_p (PATTERN (INSN)))
2220 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2222 #define MUST_SAVE_REGISTER(regno) \
2223 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2224 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
2225 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2227 /* ALIGN FRAMES on double word boundaries */
2229 #define MIPS_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
2232 /* Output assembler code to FILE to increment profiler label # LABELNO
2233 for profiling a function entry. */
2235 #define FUNCTION_PROFILER(FILE, LABELNO) \
2237 fprintf (FILE, "\t.set\tnoreorder\n"); \
2238 fprintf (FILE, "\t.set\tnoat\n"); \
2239 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2240 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2241 fprintf (FILE, "\tjal\t_mcount\n"); \
2243 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2244 TARGET_64BIT ? "dsubu" : "subu", \
2245 reg_names[STACK_POINTER_REGNUM], \
2246 reg_names[STACK_POINTER_REGNUM], \
2247 TARGET_LONG64 ? 16 : 8); \
2248 fprintf (FILE, "\t.set\treorder\n"); \
2249 fprintf (FILE, "\t.set\tat\n"); \
2252 /* Define this macro if the code for function profiling should come
2253 before the function prologue. Normally, the profiling code comes
2256 /* #define PROFILE_BEFORE_PROLOGUE */
2258 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2259 the stack pointer does not matter. The value is tested only in
2260 functions that have frame pointers.
2261 No definition is equivalent to always zero. */
2263 #define EXIT_IGNORE_STACK 1
2266 /* A C statement to output, on the stream FILE, assembler code for a
2267 block of data that contains the constant parts of a trampoline.
2268 This code should not include a label--the label is taken care of
2271 #define TRAMPOLINE_TEMPLATE(STREAM) \
2273 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2274 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2275 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2276 if (TARGET_LONG64) \
2278 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2279 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2283 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2284 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2286 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2287 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2288 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2289 if (TARGET_LONG64) \
2291 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2292 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2296 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2297 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2301 /* A C expression for the size in bytes of the trampoline, as an
2304 #define TRAMPOLINE_SIZE (32 + (TARGET_LONG64 ? 16 : 8))
2306 /* Alignment required for trampolines, in bits. */
2308 #define TRAMPOLINE_ALIGNMENT (TARGET_LONG64 ? 64 : 32)
2310 /* A C statement to initialize the variable parts of a trampoline.
2311 ADDR is an RTX for the address of the trampoline; FNADDR is an
2312 RTX for the address of the nested function; STATIC_CHAIN is an
2313 RTX for the static chain value that should be passed to the
2314 function when it is called. */
2316 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2319 if (TARGET_LONG64) \
2321 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2322 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2326 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2327 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2330 /* Flush both caches. We need to flush the data cache in case \
2331 the system has a write-back cache. */ \
2332 /* ??? Should check the return value for errors. */ \
2333 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "_flush_cache"), \
2334 0, VOIDmode, 3, addr, Pmode, \
2335 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2336 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2339 /* Addressing modes, and classification of registers for them. */
2341 /* #define HAVE_POST_INCREMENT */
2342 /* #define HAVE_POST_DECREMENT */
2344 /* #define HAVE_PRE_DECREMENT */
2345 /* #define HAVE_PRE_INCREMENT */
2347 /* These assume that REGNO is a hard or pseudo reg number.
2348 They give nonzero only if REGNO is a hard reg of the suitable class
2349 or a pseudo reg currently allocated to a suitable hard reg.
2350 These definitions are NOT overridden anywhere. */
2352 #define GP_REG_OR_PSEUDO_STRICT_P(regno) \
2353 GP_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno])
2355 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno) \
2356 (((regno) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (regno)))
2358 #define REGNO_OK_FOR_INDEX_P(regno) 0
2359 #define REGNO_OK_FOR_BASE_P(regno) GP_REG_OR_PSEUDO_STRICT_P (regno)
2361 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2362 and check its validity for a certain class.
2363 We have two alternate definitions for each of them.
2364 The usual definition accepts all pseudo regs; the other rejects them all.
2365 The symbol REG_OK_STRICT causes the latter definition to be used.
2367 Most source files want to accept pseudo regs in the hope that
2368 they will get allocated to the class that the insn wants them to be in.
2369 Some source files that are used after register allocation
2370 need to be strict. */
2372 #ifndef REG_OK_STRICT
2374 #define REG_OK_STRICT_P 0
2375 #define REG_OK_FOR_INDEX_P(X) 0
2376 #define REG_OK_FOR_BASE_P(X) GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X))
2380 #define REG_OK_STRICT_P 1
2381 #define REG_OK_FOR_INDEX_P(X) 0
2382 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2387 /* Maximum number of registers that can appear in a valid memory address. */
2389 #define MAX_REGS_PER_ADDRESS 1
2391 /* A C compound statement with a conditional `goto LABEL;' executed
2392 if X (an RTX) is a legitimate memory address on the target
2393 machine for a memory operand of mode MODE.
2395 It usually pays to define several simpler macros to serve as
2396 subroutines for this one. Otherwise it may be too complicated
2399 This macro must exist in two variants: a strict variant and a
2400 non-strict one. The strict variant is used in the reload pass.
2401 It must be defined so that any pseudo-register that has not been
2402 allocated a hard register is considered a memory reference. In
2403 contexts where some kind of register is required, a
2404 pseudo-register with no hard register must be rejected.
2406 The non-strict variant is used in other passes. It must be
2407 defined to accept all pseudo-registers in every context where
2408 some kind of register is required.
2410 Compiler source files that want to use the strict variant of
2411 this macro define the macro `REG_OK_STRICT'. You should use an
2412 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2413 in that case and the non-strict variant otherwise.
2415 Typically among the subroutines used to define
2416 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2417 acceptable registers for various purposes (one for base
2418 registers, one for index registers, and so on). Then only these
2419 subroutine macros need have two variants; the higher levels of
2420 macros may be the same whether strict or not.
2422 Normally, constant addresses which are the sum of a `symbol_ref'
2423 and an integer are stored inside a `const' RTX to mark them as
2424 constant. Therefore, there is no need to recognize such sums
2425 specifically as legitimate addresses. Normally you would simply
2426 recognize any `const' as legitimate.
2428 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2429 constant sums that are not marked with `const'. It assumes
2430 that a naked `plus' indicates indexing. If so, then you *must*
2431 reject such naked constant sums as illegitimate addresses, so
2432 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2434 On some machines, whether a symbolic address is legitimate
2435 depends on the section that the address refers to. On these
2436 machines, define the macro `ENCODE_SECTION_INFO' to store the
2437 information into the `symbol_ref', and then check for it here.
2438 When you see a `const', you will have to look inside it to find
2439 the `symbol_ref' in order to determine the section. */
2442 #define GO_PRINTF(x) trace(x)
2443 #define GO_PRINTF2(x,y) trace(x,y)
2444 #define GO_DEBUG_RTX(x) debug_rtx(x)
2447 #define GO_PRINTF(x)
2448 #define GO_PRINTF2(x,y)
2449 #define GO_DEBUG_RTX(x)
2452 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2454 register rtx xinsn = (X); \
2456 if (TARGET_DEBUG_B_MODE) \
2458 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2459 (REG_OK_STRICT_P) ? "" : "not "); \
2460 GO_DEBUG_RTX (xinsn); \
2463 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
2466 if (CONSTANT_ADDRESS_P (xinsn) \
2467 && ! (mips_split_addresses && mips_check_split (xinsn, MODE))) \
2470 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2472 register rtx xlow0 = XEXP (xinsn, 0); \
2473 register rtx xlow1 = XEXP (xinsn, 1); \
2475 if (GET_CODE (xlow0) == REG && REG_OK_FOR_BASE_P (xlow0) \
2476 && mips_check_split (xlow1, MODE)) \
2480 if (GET_CODE (xinsn) == PLUS) \
2482 register rtx xplus0 = XEXP (xinsn, 0); \
2483 register rtx xplus1 = XEXP (xinsn, 1); \
2484 register enum rtx_code code0 = GET_CODE (xplus0); \
2485 register enum rtx_code code1 = GET_CODE (xplus1); \
2487 if (code0 != REG && code1 == REG) \
2489 xplus0 = XEXP (xinsn, 1); \
2490 xplus1 = XEXP (xinsn, 0); \
2491 code0 = GET_CODE (xplus0); \
2492 code1 = GET_CODE (xplus1); \
2495 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0)) \
2497 if (code1 == CONST_INT \
2498 && INTVAL (xplus1) >= -32768 \
2499 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2502 /* For some code sequences, you actually get better code by \
2503 pretending that the MIPS supports an address mode of a \
2504 constant address + a register, even though the real \
2505 machine doesn't support it. This is because the \
2506 assembler can use $r1 to load just the high 16 bits, add \
2507 in the register, and fold the low 16 bits into the memory \
2508 reference, whereas the compiler generates a 4 instruction \
2509 sequence. On the other hand, CSE is not as effective. \
2510 It would be a win to generate the lui directly, but the \
2511 MIPS assembler does not have syntax to generate the \
2512 appropriate relocation. */ \
2514 /* Also accept CONST_INT addresses here, so no else. */ \
2515 /* Reject combining an embedded PIC text segment reference \
2516 with a register. That requires an additional \
2518 /* ??? Reject combining an address with a register for the MIPS \
2519 64 bit ABI, because the SGI assembler can not handle this. */ \
2520 if (!TARGET_DEBUG_A_MODE \
2521 && (mips_abi == ABI_32 || mips_abi == ABI_EABI) \
2522 && CONSTANT_ADDRESS_P (xplus1) \
2523 && ! mips_split_addresses \
2524 && (!TARGET_EMBEDDED_PIC \
2526 || GET_CODE (XEXP (xplus1, 0)) != MINUS)) \
2531 if (TARGET_DEBUG_B_MODE) \
2532 GO_PRINTF ("Not a legitimate address\n"); \
2536 /* A C expression that is 1 if the RTX X is a constant which is a
2537 valid address. This is defined to be the same as `CONSTANT_P (X)',
2538 but rejecting CONST_DOUBLE. */
2539 /* When pic, we must reject addresses of the form symbol+large int.
2540 This is because an instruction `sw $4,s+70000' needs to be converted
2541 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2542 assembler would use $at as a temp to load in the large offset. In this
2543 case $at is already in use. We convert such problem addresses to
2544 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2545 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2546 #define CONSTANT_ADDRESS_P(X) \
2547 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2548 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2549 || (GET_CODE (X) == CONST \
2550 && ! (flag_pic && pic_address_needs_scratch (X)) \
2551 && (mips_abi == ABI_32 || mips_abi == ABI_EABI))) \
2552 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2554 /* Define this, so that when PIC, reload won't try to reload invalid
2555 addresses which require two reload registers. */
2557 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2559 /* Nonzero if the constant value X is a legitimate general operand.
2560 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2562 At present, GAS doesn't understand li.[sd], so don't allow it
2563 to be generated at present. Also, the MIPS assembler does not
2564 grok li.d Infinity. */
2566 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2567 #define LEGITIMATE_CONSTANT_P(X) \
2568 ((GET_CODE (X) != CONST_DOUBLE \
2569 || mips_const_double_ok (X, GET_MODE (X))) \
2570 && ! (GET_CODE (X) == CONST \
2571 && mips_abi != ABI_32 && mips_abi != ABI_EABI))
2573 /* A C compound statement that attempts to replace X with a valid
2574 memory address for an operand of mode MODE. WIN will be a C
2575 statement label elsewhere in the code; the macro definition may
2578 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2580 to avoid further processing if the address has become legitimate.
2582 X will always be the result of a call to `break_out_memory_refs',
2583 and OLDX will be the operand that was given to that function to
2586 The code generated by this macro should not alter the
2587 substructure of X. If it transforms X into a more legitimate
2588 form, it should assign X (which will always be a C variable) a
2591 It is not necessary for this macro to come up with a legitimate
2592 address. The compiler has standard ways of doing so in all
2593 cases. In fact, it is safe for this macro to do nothing. But
2594 often a machine-dependent strategy can generate better code.
2596 For the MIPS, transform:
2598 memory(X + <large int>)
2602 Y = <large int> & ~0x7fff;
2604 memory (Z + (<large int> & 0x7fff));
2606 This is for CSE to find several similar references, and only use one Z.
2608 When PIC, convert addresses of the form memory (symbol+large int) to
2609 memory (reg+large int). */
2612 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2614 register rtx xinsn = (X); \
2616 if (TARGET_DEBUG_B_MODE) \
2618 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2619 GO_DEBUG_RTX (xinsn); \
2622 if (mips_split_addresses && mips_check_split (X, MODE)) \
2624 /* ??? Is this ever executed? */ \
2625 X = gen_rtx (LO_SUM, Pmode, \
2626 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2630 if (GET_CODE (xinsn) == CONST \
2631 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2632 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2633 || (mips_abi != ABI_32 && mips_abi != ABI_EABI))) \
2635 rtx ptr_reg = gen_reg_rtx (Pmode); \
2636 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2638 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2640 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2641 if (SMALL_INT (constant)) \
2643 /* Otherwise we fall through so the code below will fix the \
2648 if (GET_CODE (xinsn) == PLUS) \
2650 register rtx xplus0 = XEXP (xinsn, 0); \
2651 register rtx xplus1 = XEXP (xinsn, 1); \
2652 register enum rtx_code code0 = GET_CODE (xplus0); \
2653 register enum rtx_code code1 = GET_CODE (xplus1); \
2655 if (code0 != REG && code1 == REG) \
2657 xplus0 = XEXP (xinsn, 1); \
2658 xplus1 = XEXP (xinsn, 0); \
2659 code0 = GET_CODE (xplus0); \
2660 code1 = GET_CODE (xplus1); \
2663 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
2664 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2666 rtx int_reg = gen_reg_rtx (Pmode); \
2667 rtx ptr_reg = gen_reg_rtx (Pmode); \
2669 emit_move_insn (int_reg, \
2670 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2672 emit_insn (gen_rtx (SET, VOIDmode, \
2674 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
2676 X = gen_rtx (PLUS, Pmode, ptr_reg, \
2677 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
2682 if (TARGET_DEBUG_B_MODE) \
2683 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
2687 /* A C statement or compound statement with a conditional `goto
2688 LABEL;' executed if memory address X (an RTX) can have different
2689 meanings depending on the machine mode of the memory reference it
2692 Autoincrement and autodecrement addresses typically have
2693 mode-dependent effects because the amount of the increment or
2694 decrement is the size of the operand being addressed. Some
2695 machines have other mode-dependent addresses. Many RISC machines
2696 have no mode-dependent addresses.
2698 You may assume that ADDR is a valid address for the machine. */
2700 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2703 /* Define this macro if references to a symbol must be treated
2704 differently depending on something about the variable or
2705 function named by the symbol (such as what section it is in).
2707 The macro definition, if any, is executed immediately after the
2708 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
2709 The value of the rtl will be a `mem' whose address is a
2712 The usual thing for this macro to do is to a flag in the
2713 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
2714 name string in the `symbol_ref' (if one bit is not enough
2717 The best way to modify the name string is by adding text to the
2718 beginning, with suitable punctuation to prevent any ambiguity.
2719 Allocate the new name in `saveable_obstack'. You will have to
2720 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
2721 and output the name accordingly.
2723 You can also check the information stored in the `symbol_ref' in
2724 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
2725 `PRINT_OPERAND_ADDRESS'. */
2727 #define ENCODE_SECTION_INFO(DECL) \
2730 if (TARGET_EMBEDDED_PIC) \
2732 if (TREE_CODE (DECL) == VAR_DECL) \
2733 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2734 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
2735 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
2736 else if (TREE_CODE (DECL) == STRING_CST \
2737 && ! flag_writable_strings) \
2738 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
2740 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
2743 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
2745 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
2747 if (size > 0 && size <= mips_section_threshold) \
2748 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2751 else if (HALF_PIC_P ()) \
2752 HALF_PIC_ENCODE (DECL); \
2757 /* Specify the machine mode that this machine uses
2758 for the index in the tablejump instruction. */
2759 #define CASE_VECTOR_MODE (TARGET_LONG64 ? DImode : SImode)
2761 /* Define this if the tablejump instruction expects the table
2762 to contain offsets from the address of the table.
2763 Do not define this if the table should contain absolute addresses. */
2764 /* #define CASE_VECTOR_PC_RELATIVE */
2766 /* Specify the tree operation to be used to convert reals to integers. */
2767 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2769 /* This is the kind of divide that is easiest to do in the general case. */
2770 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2772 /* Define this as 1 if `char' should by default be signed; else as 0. */
2773 #ifndef DEFAULT_SIGNED_CHAR
2774 #define DEFAULT_SIGNED_CHAR 1
2777 /* Max number of bytes we can move from memory to memory
2778 in one reasonably fast instruction. */
2779 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2780 #define MAX_MOVE_MAX 8
2782 /* Define this macro as a C expression which is nonzero if
2783 accessing less than a word of memory (i.e. a `char' or a
2784 `short') is no faster than accessing a word of memory, i.e., if
2785 such access require more than one instruction or if there is no
2786 difference in cost between byte and (aligned) word loads.
2788 On RISC machines, it tends to generate better code to define
2789 this as 1, since it avoids making a QI or HI mode register. */
2790 #define SLOW_BYTE_ACCESS 1
2792 /* We assume that the store-condition-codes instructions store 0 for false
2793 and some other value for true. This is the value stored for true. */
2795 #define STORE_FLAG_VALUE 1
2797 /* Define this if zero-extension is slow (more than one real instruction). */
2798 #define SLOW_ZERO_EXTEND
2800 /* Define this to be nonzero if shift instructions ignore all but the low-order
2802 #define SHIFT_COUNT_TRUNCATED 1
2804 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2805 is done just by pretending it is already truncated. */
2806 /* In 64 bit mode, 32 bit instructions require that register values be properly
2807 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
2808 converts a value >32 bits to a value <32 bits. */
2809 /* ??? This results in inefficient code for 64 bit to 32 conversions.
2810 Something needs to be done about this. Perhaps not use any 32 bit
2811 instructions? Perhaps use PROMOTE_MODE? */
2812 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2813 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2815 /* Specify the machine mode that pointers have.
2816 After generation of rtl, the compiler makes no further distinction
2817 between pointers and any other objects of this machine mode. */
2819 #define Pmode (TARGET_LONG64 ? DImode : SImode)
2821 /* A function address in a call instruction
2822 is a word address (for indexing purposes)
2823 so give the MEM rtx a words's mode. */
2825 #define FUNCTION_MODE (TARGET_LONG64 ? DImode : SImode)
2827 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
2828 memset, instead of the BSD functions bcopy and bzero. */
2830 #if defined(MIPS_SYSV) || defined(OSF_OS)
2831 #define TARGET_MEM_FUNCTIONS
2835 /* A part of a C `switch' statement that describes the relative
2836 costs of constant RTL expressions. It must contain `case'
2837 labels for expression codes `const_int', `const', `symbol_ref',
2838 `label_ref' and `const_double'. Each case must ultimately reach
2839 a `return' statement to return the relative cost of the use of
2840 that kind of constant value in an expression. The cost may
2841 depend on the precise value of the constant, which is available
2842 for examination in X.
2844 CODE is the expression code--redundant, since it can be obtained
2845 with `GET_CODE (X)'. */
2847 #define CONST_COSTS(X,CODE,OUTER_CODE) \
2849 /* Always return 0, since we don't have different sized \
2850 instructions, hence different costs according to Richard \
2855 return COSTS_N_INSNS (2); \
2859 rtx offset = const0_rtx; \
2860 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
2862 if (GET_CODE (symref) == LABEL_REF) \
2863 return COSTS_N_INSNS (2); \
2865 if (GET_CODE (symref) != SYMBOL_REF) \
2866 return COSTS_N_INSNS (4); \
2868 /* let's be paranoid.... */ \
2869 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
2870 return COSTS_N_INSNS (2); \
2872 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
2876 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
2878 case CONST_DOUBLE: \
2881 split_double (X, &high, &low); \
2882 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
2883 || low == CONST0_RTX (GET_MODE (low))) \
2887 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2888 This can be used, for example, to indicate how costly a multiply
2889 instruction is. In writing this macro, you can use the construct
2890 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
2892 This macro is optional; do not define it if the default cost
2893 assumptions are adequate for the target machine.
2895 If -mdebugd is used, change the multiply cost to 2, so multiply by
2896 a constant isn't converted to a series of shifts. This helps
2897 strength reduction, and also makes it easier to identify what the
2898 compiler is doing. */
2900 /* ??? Fix this to be right for the R8000. */
2901 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2904 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
2905 if (simple_memory_operand (X, GET_MODE (X))) \
2906 return COSTS_N_INSNS (num_words); \
2908 return COSTS_N_INSNS (2*num_words); \
2912 return COSTS_N_INSNS (6); \
2915 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
2920 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
2921 return COSTS_N_INSNS (2); \
2923 return COSTS_N_INSNS (1); \
2928 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
2929 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
2931 return COSTS_N_INSNS (1); \
2935 enum machine_mode xmode = GET_MODE (X); \
2936 if (xmode == SFmode || xmode == DFmode) \
2937 return COSTS_N_INSNS (1); \
2939 return COSTS_N_INSNS (4); \
2945 enum machine_mode xmode = GET_MODE (X); \
2946 if (xmode == SFmode || xmode == DFmode) \
2948 if (mips_cpu == PROCESSOR_R3000) \
2949 return COSTS_N_INSNS (2); \
2950 else if (mips_cpu == PROCESSOR_R6000) \
2951 return COSTS_N_INSNS (3); \
2953 return COSTS_N_INSNS (6); \
2956 if (xmode == DImode && !TARGET_64BIT) \
2957 return COSTS_N_INSNS (4); \
2959 return COSTS_N_INSNS (1); \
2963 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 4 : 1); \
2967 enum machine_mode xmode = GET_MODE (X); \
2968 if (xmode == SFmode) \
2970 if (mips_cpu == PROCESSOR_R3000 \
2971 || mips_cpu == PROCESSOR_R5000) \
2972 return COSTS_N_INSNS (4); \
2973 else if (mips_cpu == PROCESSOR_R6000) \
2974 return COSTS_N_INSNS (5); \
2976 return COSTS_N_INSNS (7); \
2979 if (xmode == DFmode) \
2981 if (mips_cpu == PROCESSOR_R3000 \
2982 || mips_cpu == PROCESSOR_R5000) \
2983 return COSTS_N_INSNS (5); \
2984 else if (mips_cpu == PROCESSOR_R6000) \
2985 return COSTS_N_INSNS (6); \
2987 return COSTS_N_INSNS (8); \
2990 if (mips_cpu == PROCESSOR_R3000) \
2991 return COSTS_N_INSNS (12); \
2992 else if (mips_cpu == PROCESSOR_R6000) \
2993 return COSTS_N_INSNS (17); \
2994 else if (mips_cpu == PROCESSOR_R5000) \
2995 return COSTS_N_INSNS (5); \
2997 return COSTS_N_INSNS (10); \
3003 enum machine_mode xmode = GET_MODE (X); \
3004 if (xmode == SFmode) \
3006 if (mips_cpu == PROCESSOR_R3000) \
3007 return COSTS_N_INSNS (12); \
3008 else if (mips_cpu == PROCESSOR_R6000) \
3009 return COSTS_N_INSNS (15); \
3011 return COSTS_N_INSNS (23); \
3014 if (xmode == DFmode) \
3016 if (mips_cpu == PROCESSOR_R3000) \
3017 return COSTS_N_INSNS (19); \
3018 else if (mips_cpu == PROCESSOR_R6000) \
3019 return COSTS_N_INSNS (16); \
3021 return COSTS_N_INSNS (36); \
3024 /* fall through */ \
3028 if (mips_cpu == PROCESSOR_R3000) \
3029 return COSTS_N_INSNS (35); \
3030 else if (mips_cpu == PROCESSOR_R6000) \
3031 return COSTS_N_INSNS (38); \
3032 else if (mips_cpu == PROCESSOR_R5000) \
3033 return COSTS_N_INSNS (36); \
3035 return COSTS_N_INSNS (69); \
3038 /* A sign extend from SImode to DImode in 64 bit mode is often \
3039 zero instructions, because the result can often be used \
3040 directly by another instruction; we'll call it one. */ \
3041 if (TARGET_64BIT && GET_MODE (X) == DImode \
3042 && GET_MODE (XEXP (X, 0)) == SImode) \
3043 return COSTS_N_INSNS (1); \
3045 return COSTS_N_INSNS (2); \
3048 if (TARGET_64BIT && GET_MODE (X) == DImode \
3049 && GET_MODE (XEXP (X, 0)) == SImode) \
3050 return COSTS_N_INSNS (2); \
3052 return COSTS_N_INSNS (1);
3054 /* An expression giving the cost of an addressing mode that
3055 contains ADDRESS. If not defined, the cost is computed from the
3056 form of the ADDRESS expression and the `CONST_COSTS' values.
3058 For most CISC machines, the default cost is a good approximation
3059 of the true cost of the addressing mode. However, on RISC
3060 machines, all instructions normally have the same length and
3061 execution time. Hence all addresses will have equal costs.
3063 In cases where more than one form of an address is known, the
3064 form with the lowest cost will be used. If multiple forms have
3065 the same, lowest, cost, the one that is the most complex will be
3068 For example, suppose an address that is equal to the sum of a
3069 register and a constant is used twice in the same basic block.
3070 When this macro is not defined, the address will be computed in
3071 a register and memory references will be indirect through that
3072 register. On machines where the cost of the addressing mode
3073 containing the sum is no higher than that of a simple indirect
3074 reference, this will produce an additional instruction and
3075 possibly require an additional register. Proper specification
3076 of this macro eliminates this overhead for such machines.
3078 Similar use of this macro is made in strength reduction of loops.
3080 ADDRESS need not be valid as an address. In such a case, the
3081 cost is not relevant and can be any value; invalid addresses
3082 need not be assigned a different cost.
3084 On machines where an address involving more than one register is
3085 as cheap as an address computation involving only one register,
3086 defining `ADDRESS_COST' to reflect this can cause two registers
3087 to be live over a region of code where only one would have been
3088 if `ADDRESS_COST' were not defined in that manner. This effect
3089 should be considered in the definition of this macro.
3090 Equivalent costs should probably only be given to addresses with
3091 different numbers of registers on machines with lots of registers.
3093 This macro will normally either not be defined or be defined as
3096 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3098 /* A C expression for the cost of moving data from a register in
3099 class FROM to one in class TO. The classes are expressed using
3100 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3101 the default; other values are interpreted relative to that.
3103 It is not required that the cost always equal 2 when FROM is the
3104 same as TO; on some machines it is expensive to move between
3105 registers if they are not general registers.
3107 If reload sees an insn consisting of a single `set' between two
3108 hard registers, and if `REGISTER_MOVE_COST' applied to their
3109 classes returns a value of 2, reload does not check to ensure
3110 that the constraints of the insn are met. Setting a cost of
3111 other than 2 will allow reload to verify that the constraints are
3112 met. You should do this if the `movM' pattern's constraints do
3113 not allow such copying. */
3115 #define REGISTER_MOVE_COST(FROM, TO) \
3116 ((FROM) == GR_REGS && (TO) == GR_REGS ? 2 \
3117 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3118 : (FROM) == GR_REGS && (TO) == FP_REGS ? 4 \
3119 : (FROM) == FP_REGS && (TO) == GR_REGS ? 4 \
3120 : (((FROM) == HI_REG || (FROM) == LO_REG \
3121 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3122 && (TO) == GR_REGS) ? 6 \
3123 : (((TO) == HI_REG || (TO) == LO_REG \
3124 || (TO) == MD_REGS || (FROM) == HILO_REG) \
3125 && (FROM) == GR_REGS) ? 6 \
3126 : (FROM) == ST_REGS && (TO) == GR_REGS ? 4 \
3127 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3130 /* ??? Fix this to be right for the R8000. */
3131 #define MEMORY_MOVE_COST(MODE) \
3132 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4)
3134 /* A C expression for the cost of a branch instruction. A value of
3135 1 is the default; other values are interpreted relative to that. */
3137 /* ??? Fix this to be right for the R8000. */
3138 #define BRANCH_COST \
3139 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 2 : 1)
3141 /* A C statement (sans semicolon) to update the integer variable COST
3142 based on the relationship between INSN that is dependent on
3143 DEP_INSN through the dependence LINK. The default is to make no
3144 adjustment to COST. On the MIPS, ignore the cost of anti- and
3145 output-dependencies. */
3147 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3148 if (REG_NOTE_KIND (LINK) != 0) \
3149 (COST) = 0; /* Anti or output dependence. */
3151 /* Optionally define this if you have added predicates to
3152 `MACHINE.c'. This macro is called within an initializer of an
3153 array of structures. The first field in the structure is the
3154 name of a predicate and the second field is an array of rtl
3155 codes. For each predicate, list all rtl codes that can be in
3156 expressions matched by the predicate. The list should have a
3157 trailing comma. Here is an example of two entries in the list
3158 for a typical RISC machine:
3160 #define PREDICATE_CODES \
3161 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3162 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3164 Defining this macro does not affect the generated code (however,
3165 incorrect definitions that omit an rtl code that may be matched
3166 by the predicate can cause the compiler to malfunction).
3167 Instead, it allows the table built by `genrecog' to be more
3168 compact and efficient, thus speeding up the compiler. The most
3169 important predicates to include in the list specified by this
3170 macro are thoses used in the most insn patterns. */
3172 #define PREDICATE_CODES \
3173 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3174 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3175 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3176 {"reg_or_0_operand", { REG, CONST_INT, SUBREG }}, \
3177 {"small_int", { CONST_INT }}, \
3178 {"large_int", { CONST_INT }}, \
3179 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3180 {"const_float_1_operand", { CONST_DOUBLE }}, \
3181 {"simple_memory_operand", { MEM, SUBREG }}, \
3182 {"equality_op", { EQ, NE }}, \
3183 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3185 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3186 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3187 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3188 SYMBOL_REF, LABEL_REF, SUBREG, \
3190 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3191 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3192 MEM, SIGN_EXTEND }}, \
3193 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3194 {"se_reg_or_0_operand", { REG, CONST_INT, SUBREG, \
3196 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3198 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3200 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3201 SYMBOL_REF, LABEL_REF, SUBREG, \
3202 REG, SIGN_EXTEND }}, \
3203 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }},
3206 /* If defined, a C statement to be executed just prior to the
3207 output of assembler code for INSN, to modify the extracted
3208 operands so they will be output differently.
3210 Here the argument OPVEC is the vector containing the operands
3211 extracted from INSN, and NOPERANDS is the number of elements of
3212 the vector which contain meaningful data for this insn. The
3213 contents of this vector are what will be used to convert the
3214 insn template into assembler code, so you can change the
3215 assembler output by changing the contents of the vector.
3217 We use it to check if the current insn needs a nop in front of it
3218 because of load delays, and also to update the delay slot
3221 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3222 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3225 /* Control the assembler format that we output. */
3227 /* Output at beginning of assembler file.
3228 If we are optimizing to use the global pointer, create a temporary
3229 file to hold all of the text stuff, and write it out to the end.
3230 This is needed because the MIPS assembler is evidently one pass,
3231 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3232 declaration when the code is processed, it generates a two
3233 instruction sequence. */
3235 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3237 /* Output to assembler file text saying following lines
3238 may contain character constants, extra white space, comments, etc. */
3240 #define ASM_APP_ON " #APP\n"
3242 /* Output to assembler file text saying following lines
3243 no longer contain unusual constructs. */
3245 #define ASM_APP_OFF " #NO_APP\n"
3247 /* How to refer to registers in assembler output.
3248 This sequence is indexed by compiler's hard-register-number (see above).
3250 In order to support the two different conventions for register names,
3251 we use the name of a table set up in mips.c, which is overwritten
3252 if -mrnames is used. */
3254 #define REGISTER_NAMES \
3256 &mips_reg_names[ 0][0], \
3257 &mips_reg_names[ 1][0], \
3258 &mips_reg_names[ 2][0], \
3259 &mips_reg_names[ 3][0], \
3260 &mips_reg_names[ 4][0], \
3261 &mips_reg_names[ 5][0], \
3262 &mips_reg_names[ 6][0], \
3263 &mips_reg_names[ 7][0], \
3264 &mips_reg_names[ 8][0], \
3265 &mips_reg_names[ 9][0], \
3266 &mips_reg_names[10][0], \
3267 &mips_reg_names[11][0], \
3268 &mips_reg_names[12][0], \
3269 &mips_reg_names[13][0], \
3270 &mips_reg_names[14][0], \
3271 &mips_reg_names[15][0], \
3272 &mips_reg_names[16][0], \
3273 &mips_reg_names[17][0], \
3274 &mips_reg_names[18][0], \
3275 &mips_reg_names[19][0], \
3276 &mips_reg_names[20][0], \
3277 &mips_reg_names[21][0], \
3278 &mips_reg_names[22][0], \
3279 &mips_reg_names[23][0], \
3280 &mips_reg_names[24][0], \
3281 &mips_reg_names[25][0], \
3282 &mips_reg_names[26][0], \
3283 &mips_reg_names[27][0], \
3284 &mips_reg_names[28][0], \
3285 &mips_reg_names[29][0], \
3286 &mips_reg_names[30][0], \
3287 &mips_reg_names[31][0], \
3288 &mips_reg_names[32][0], \
3289 &mips_reg_names[33][0], \
3290 &mips_reg_names[34][0], \
3291 &mips_reg_names[35][0], \
3292 &mips_reg_names[36][0], \
3293 &mips_reg_names[37][0], \
3294 &mips_reg_names[38][0], \
3295 &mips_reg_names[39][0], \
3296 &mips_reg_names[40][0], \
3297 &mips_reg_names[41][0], \
3298 &mips_reg_names[42][0], \
3299 &mips_reg_names[43][0], \
3300 &mips_reg_names[44][0], \
3301 &mips_reg_names[45][0], \
3302 &mips_reg_names[46][0], \
3303 &mips_reg_names[47][0], \
3304 &mips_reg_names[48][0], \
3305 &mips_reg_names[49][0], \
3306 &mips_reg_names[50][0], \
3307 &mips_reg_names[51][0], \
3308 &mips_reg_names[52][0], \
3309 &mips_reg_names[53][0], \
3310 &mips_reg_names[54][0], \
3311 &mips_reg_names[55][0], \
3312 &mips_reg_names[56][0], \
3313 &mips_reg_names[57][0], \
3314 &mips_reg_names[58][0], \
3315 &mips_reg_names[59][0], \
3316 &mips_reg_names[60][0], \
3317 &mips_reg_names[61][0], \
3318 &mips_reg_names[62][0], \
3319 &mips_reg_names[63][0], \
3320 &mips_reg_names[64][0], \
3321 &mips_reg_names[65][0], \
3322 &mips_reg_names[66][0], \
3323 &mips_reg_names[67][0], \
3324 &mips_reg_names[68][0], \
3325 &mips_reg_names[69][0], \
3326 &mips_reg_names[70][0], \
3327 &mips_reg_names[71][0], \
3328 &mips_reg_names[72][0], \
3329 &mips_reg_names[73][0], \
3330 &mips_reg_names[74][0], \
3331 &mips_reg_names[75][0], \
3334 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3335 So define this for it. */
3336 #define DEBUG_REGISTER_NAMES \
3338 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3339 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3340 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3341 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3342 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3343 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3344 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3345 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3346 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3347 "$fcc5","$fcc6","$fcc7","$rap" \
3350 /* If defined, a C initializer for an array of structures
3351 containing a name and a register number. This macro defines
3352 additional names for hard registers, thus allowing the `asm'
3353 option in declarations to refer to registers using alternate
3356 We define both names for the integer registers here. */
3358 #define ADDITIONAL_REGISTER_NAMES \
3360 { "$0", 0 + GP_REG_FIRST }, \
3361 { "$1", 1 + GP_REG_FIRST }, \
3362 { "$2", 2 + GP_REG_FIRST }, \
3363 { "$3", 3 + GP_REG_FIRST }, \
3364 { "$4", 4 + GP_REG_FIRST }, \
3365 { "$5", 5 + GP_REG_FIRST }, \
3366 { "$6", 6 + GP_REG_FIRST }, \
3367 { "$7", 7 + GP_REG_FIRST }, \
3368 { "$8", 8 + GP_REG_FIRST }, \
3369 { "$9", 9 + GP_REG_FIRST }, \
3370 { "$10", 10 + GP_REG_FIRST }, \
3371 { "$11", 11 + GP_REG_FIRST }, \
3372 { "$12", 12 + GP_REG_FIRST }, \
3373 { "$13", 13 + GP_REG_FIRST }, \
3374 { "$14", 14 + GP_REG_FIRST }, \
3375 { "$15", 15 + GP_REG_FIRST }, \
3376 { "$16", 16 + GP_REG_FIRST }, \
3377 { "$17", 17 + GP_REG_FIRST }, \
3378 { "$18", 18 + GP_REG_FIRST }, \
3379 { "$19", 19 + GP_REG_FIRST }, \
3380 { "$20", 20 + GP_REG_FIRST }, \
3381 { "$21", 21 + GP_REG_FIRST }, \
3382 { "$22", 22 + GP_REG_FIRST }, \
3383 { "$23", 23 + GP_REG_FIRST }, \
3384 { "$24", 24 + GP_REG_FIRST }, \
3385 { "$25", 25 + GP_REG_FIRST }, \
3386 { "$26", 26 + GP_REG_FIRST }, \
3387 { "$27", 27 + GP_REG_FIRST }, \
3388 { "$28", 28 + GP_REG_FIRST }, \
3389 { "$29", 29 + GP_REG_FIRST }, \
3390 { "$30", 30 + GP_REG_FIRST }, \
3391 { "$31", 31 + GP_REG_FIRST }, \
3392 { "$sp", 29 + GP_REG_FIRST }, \
3393 { "$fp", 30 + GP_REG_FIRST }, \
3394 { "at", 1 + GP_REG_FIRST }, \
3395 { "v0", 2 + GP_REG_FIRST }, \
3396 { "v1", 3 + GP_REG_FIRST }, \
3397 { "a0", 4 + GP_REG_FIRST }, \
3398 { "a1", 5 + GP_REG_FIRST }, \
3399 { "a2", 6 + GP_REG_FIRST }, \
3400 { "a3", 7 + GP_REG_FIRST }, \
3401 { "t0", 8 + GP_REG_FIRST }, \
3402 { "t1", 9 + GP_REG_FIRST }, \
3403 { "t2", 10 + GP_REG_FIRST }, \
3404 { "t3", 11 + GP_REG_FIRST }, \
3405 { "t4", 12 + GP_REG_FIRST }, \
3406 { "t5", 13 + GP_REG_FIRST }, \
3407 { "t6", 14 + GP_REG_FIRST }, \
3408 { "t7", 15 + GP_REG_FIRST }, \
3409 { "s0", 16 + GP_REG_FIRST }, \
3410 { "s1", 17 + GP_REG_FIRST }, \
3411 { "s2", 18 + GP_REG_FIRST }, \
3412 { "s3", 19 + GP_REG_FIRST }, \
3413 { "s4", 20 + GP_REG_FIRST }, \
3414 { "s5", 21 + GP_REG_FIRST }, \
3415 { "s6", 22 + GP_REG_FIRST }, \
3416 { "s7", 23 + GP_REG_FIRST }, \
3417 { "t8", 24 + GP_REG_FIRST }, \
3418 { "t9", 25 + GP_REG_FIRST }, \
3419 { "k0", 26 + GP_REG_FIRST }, \
3420 { "k1", 27 + GP_REG_FIRST }, \
3421 { "gp", 28 + GP_REG_FIRST }, \
3422 { "sp", 29 + GP_REG_FIRST }, \
3423 { "fp", 30 + GP_REG_FIRST }, \
3424 { "ra", 31 + GP_REG_FIRST }, \
3425 { "$sp", 29 + GP_REG_FIRST }, \
3426 { "$fp", 30 + GP_REG_FIRST } \
3429 /* Define results of standard character escape sequences. */
3430 #define TARGET_BELL 007
3431 #define TARGET_BS 010
3432 #define TARGET_TAB 011
3433 #define TARGET_NEWLINE 012
3434 #define TARGET_VT 013
3435 #define TARGET_FF 014
3436 #define TARGET_CR 015
3438 /* A C compound statement to output to stdio stream STREAM the
3439 assembler syntax for an instruction operand X. X is an RTL
3442 CODE is a value that can be used to specify one of several ways
3443 of printing the operand. It is used when identical operands
3444 must be printed differently depending on the context. CODE
3445 comes from the `%' specification that was used to request
3446 printing of the operand. If the specification was just `%DIGIT'
3447 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3448 is the ASCII code for LTR.
3450 If X is a register, this macro should print the register's name.
3451 The names can be found in an array `reg_names' whose type is
3452 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3454 When the machine description has a specification `%PUNCT' (a `%'
3455 followed by a punctuation character), this macro is called with
3456 a null pointer for X and the punctuation character for CODE.
3458 See mips.c for the MIPS specific codes. */
3460 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3462 /* A C expression which evaluates to true if CODE is a valid
3463 punctuation character for use in the `PRINT_OPERAND' macro. If
3464 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3465 punctuation characters (except for the standard one, `%') are
3466 used in this way. */
3468 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3470 /* A C compound statement to output to stdio stream STREAM the
3471 assembler syntax for an instruction operand that is a memory
3472 reference whose address is ADDR. ADDR is an RTL expression.
3474 On some machines, the syntax for a symbolic address depends on
3475 the section that the address refers to. On these machines,
3476 define the macro `ENCODE_SECTION_INFO' to store the information
3477 into the `symbol_ref', and then check for it here. */
3479 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3482 /* A C statement, to be executed after all slot-filler instructions
3483 have been output. If necessary, call `dbr_sequence_length' to
3484 determine the number of slots filled in a sequence (zero if not
3485 currently outputting a sequence), to decide how many no-ops to
3486 output, or whatever.
3488 Don't define this macro if it has nothing to do, but it is
3489 helpful in reading assembly output if the extent of the delay
3490 sequence is made explicit (e.g. with white space).
3492 Note that output routines for instructions with delay slots must
3493 be prepared to deal with not being output as part of a sequence
3494 (i.e. when the scheduling pass is not run, or when no slot
3495 fillers could be found.) The variable `final_sequence' is null
3496 when not processing a sequence, otherwise it contains the
3497 `sequence' rtx being output. */
3499 #define DBR_OUTPUT_SEQEND(STREAM) \
3502 if (set_nomacro > 0 && --set_nomacro == 0) \
3503 fputs ("\t.set\tmacro\n", STREAM); \
3505 if (set_noreorder > 0 && --set_noreorder == 0) \
3506 fputs ("\t.set\treorder\n", STREAM); \
3508 dslots_jump_filled++; \
3509 fputs ("\n", STREAM); \
3514 /* How to tell the debugger about changes of source files. Note, the
3515 mips ECOFF format cannot deal with changes of files inside of
3516 functions, which means the output of parser generators like bison
3517 is generally not debuggable without using the -l switch. Lose,
3518 lose, lose. Silicon graphics seems to want all .file's hardwired
3521 #ifndef SET_FILE_NUMBER
3522 #define SET_FILE_NUMBER() ++num_source_filenames
3525 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3526 mips_output_filename (STREAM, NAME)
3528 /* This is defined so that it can be overridden in iris6.h. */
3529 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3532 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3533 output_quoted_string (STREAM, NAME); \
3534 fputs ("\n", STREAM); \
3538 /* This is how to output a note the debugger telling it the line number
3539 to which the following sequence of instructions corresponds.
3540 Silicon graphics puts a label after each .loc. */
3542 #ifndef LABEL_AFTER_LOC
3543 #define LABEL_AFTER_LOC(STREAM)
3546 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3547 mips_output_lineno (STREAM, LINE)
3549 /* The MIPS implementation uses some labels for it's own purpose. The
3550 following lists what labels are created, and are all formed by the
3551 pattern $L[a-z].*. The machine independent portion of GCC creates
3552 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3554 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3555 $Lb[0-9]+ Begin blocks for MIPS debug support
3556 $Lc[0-9]+ Label for use in s<xx> operation.
3557 $Le[0-9]+ End blocks for MIPS debug support
3558 $Lp\..+ Half-pic labels. */
3560 /* This is how to output the definition of a user-level label named NAME,
3561 such as the label on a static function or variable NAME.
3563 If we are optimizing the gp, remember that this label has been put
3564 out, so we know not to emit an .extern for it in mips_asm_file_end.
3565 We use one of the common bits in the IDENTIFIER tree node for this,
3566 since those bits seem to be unused, and we don't have any method
3567 of getting the decl nodes from the name. */
3569 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
3571 assemble_name (STREAM, NAME); \
3572 fputs (":\n", STREAM); \
3576 /* A C statement (sans semicolon) to output to the stdio stream
3577 STREAM any text necessary for declaring the name NAME of an
3578 initialized variable which is being defined. This macro must
3579 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3580 The argument DECL is the `VAR_DECL' tree node representing the
3583 If this macro is not defined, then the variable name is defined
3584 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3586 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3589 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3590 HALF_PIC_DECLARE (NAME); \
3595 /* This is how to output a command to make the user-level label named NAME
3596 defined for reference from other files. */
3598 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
3600 fputs ("\t.globl\t", STREAM); \
3601 assemble_name (STREAM, NAME); \
3602 fputs ("\n", STREAM); \
3605 /* This says how to define a global common symbol. */
3607 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
3608 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
3610 /* This says how to define a local common symbol (ie, not visible to
3613 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3614 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
3617 /* This says how to output an external. It would be possible not to
3618 output anything and let undefined symbol become external. However
3619 the assembler uses length information on externals to allocate in
3620 data/sdata bss/sbss, thereby saving exec time. */
3622 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3623 mips_output_external(STREAM,DECL,NAME)
3625 /* This says what to print at the end of the assembly file */
3626 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
3629 /* This is how to declare a function name. The actual work of
3630 emitting the label is moved to function_prologue, so that we can
3631 get the line number correctly emitted before the .ent directive,
3632 and after any .file directives.
3634 Also, switch files if we are optimizing the global pointer. */
3636 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
3638 extern FILE *asm_out_text_file; \
3639 if (TARGET_GP_OPT) \
3641 STREAM = asm_out_text_file; \
3642 /* ??? text_section gets called too soon. If the previous \
3643 function is in a special section and we're not, we have \
3644 to switch back to the text section. We can't call \
3645 text_section again as gcc thinks we're already there. */ \
3646 /* ??? See varasm.c. There are other things that get output \
3647 too early, like alignment (before we've switched STREAM). */ \
3648 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
3649 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
3652 HALF_PIC_DECLARE (NAME); \
3655 /* This is how to output an internal numbered label where
3656 PREFIX is the class of label and NUM is the number within the class. */
3658 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
3659 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
3661 /* This is how to store into the string LABEL
3662 the symbol_ref name of an internal numbered label where
3663 PREFIX is the class of label and NUM is the number within the class.
3664 This is suitable for output with `assemble_name'. */
3666 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3667 sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
3669 /* This is how to output an assembler line defining a `double' constant. */
3671 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
3672 mips_output_double (STREAM, VALUE)
3675 /* This is how to output an assembler line defining a `float' constant. */
3677 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
3678 mips_output_float (STREAM, VALUE)
3681 /* This is how to output an assembler line defining an `int' constant. */
3683 #define ASM_OUTPUT_INT(STREAM,VALUE) \
3685 fprintf (STREAM, "\t.word\t"); \
3686 output_addr_const (STREAM, (VALUE)); \
3687 fprintf (STREAM, "\n"); \
3690 /* Likewise for 64 bit, `char' and `short' constants. */
3692 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
3696 fprintf (STREAM, "\t.dword\t"); \
3697 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
3698 /* We can't use 'X' for negative numbers, because then we won't \
3699 get the right value for the upper 32 bits. */ \
3700 output_addr_const (STREAM, VALUE); \
3702 /* We must use 'X', because otherwise LONG_MIN will print as \
3703 a number that the Irix 6 assembler won't accept. */ \
3704 print_operand (STREAM, VALUE, 'X'); \
3705 fprintf (STREAM, "\n"); \
3709 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
3710 UNITS_PER_WORD, 1); \
3711 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
3712 UNITS_PER_WORD, 1); \
3716 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
3718 fprintf (STREAM, "\t.half\t"); \
3719 output_addr_const (STREAM, (VALUE)); \
3720 fprintf (STREAM, "\n"); \
3723 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
3725 fprintf (STREAM, "\t.byte\t"); \
3726 output_addr_const (STREAM, (VALUE)); \
3727 fprintf (STREAM, "\n"); \
3730 /* This is how to output an assembler line for a numeric constant byte. */
3732 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
3733 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
3735 /* This is how to output an element of a case-vector that is absolute. */
3737 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3738 fprintf (STREAM, "\t%s\t%sL%d\n", \
3739 TARGET_LONG64 ? ".dword" : ".word", \
3740 LOCAL_LABEL_PREFIX, \
3743 /* This is how to output an element of a case-vector that is relative.
3744 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3745 TARGET_EMBEDDED_PIC). */
3747 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, VALUE, REL) \
3749 if (TARGET_EMBEDDED_PIC) \
3750 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3751 TARGET_LONG64 ? ".dword" : ".word", \
3752 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3753 else if (mips_abi == ABI_32) \
3754 fprintf (STREAM, "\t%s\t%sL%d\n", \
3755 TARGET_LONG64 ? ".gpdword" : ".gpword", \
3756 LOCAL_LABEL_PREFIX, VALUE); \
3758 fprintf (STREAM, "\t%s\t%sL%d\n", \
3759 TARGET_LONG64 ? ".dword" : ".word", \
3760 LOCAL_LABEL_PREFIX, VALUE); \
3763 /* When generating embedded PIC code we want to put the jump table in
3764 the .text section. In all other cases, we want to put the jump
3765 table in the .rdata section. Unfortunately, we can't use
3766 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3767 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3768 section if appropriate. */
3769 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3771 if (TARGET_EMBEDDED_PIC) \
3773 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
3776 /* This is how to output an assembler line
3777 that says to advance the location counter
3778 to a multiple of 2**LOG bytes. */
3780 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3782 int mask = (1 << (LOG)) - 1; \
3783 fprintf (STREAM, "\t.align\t%d\n", (LOG)); \
3786 /* This is how to output an assembler line to to advance the location
3787 counter by SIZE bytes. */
3789 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3790 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
3792 /* This is how to output a string. */
3793 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3795 register int i, c, len = (LEN), cur_pos = 17; \
3796 register unsigned char *string = (unsigned char *)(STRING); \
3797 fprintf ((STREAM), "\t.ascii\t\""); \
3798 for (i = 0; i < len; i++) \
3800 register int c = string[i]; \
3806 putc ('\\', (STREAM)); \
3807 putc (c, (STREAM)); \
3811 case TARGET_NEWLINE: \
3812 fputs ("\\n", (STREAM)); \
3814 && (((c = string[i+1]) >= '\040' && c <= '~') \
3815 || c == TARGET_TAB)) \
3816 cur_pos = 32767; /* break right here */ \
3822 fputs ("\\t", (STREAM)); \
3827 fputs ("\\f", (STREAM)); \
3832 fputs ("\\b", (STREAM)); \
3837 fputs ("\\r", (STREAM)); \
3842 if (c >= ' ' && c < 0177) \
3844 putc (c, (STREAM)); \
3849 fprintf ((STREAM), "\\%03o", c); \
3854 if (cur_pos > 72 && i+1 < len) \
3857 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
3860 fprintf ((STREAM), "\"\n"); \
3863 /* Handle certain cpp directives used in header files on sysV. */
3864 #define SCCS_DIRECTIVE
3866 /* Output #ident as a in the read-only data section. */
3867 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3870 int size = strlen (p) + 1; \
3872 assemble_string (p, size); \
3875 /* Default to -G 8 */
3876 #ifndef MIPS_DEFAULT_GVALUE
3877 #define MIPS_DEFAULT_GVALUE 8
3880 /* Define the strings to put out for each section in the object file. */
3881 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3882 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3883 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3884 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3885 #define READONLY_DATA_SECTION rdata_section
3886 #define SMALL_DATA_SECTION sdata_section
3888 /* What other sections we support other than the normal .data/.text. */
3890 #define EXTRA_SECTIONS in_sdata, in_rdata
3892 /* Define the additional functions to select our additional sections. */
3894 /* on the MIPS it is not a good idea to put constants in the text
3895 section, since this defeats the sdata/data mechanism. This is
3896 especially true when -O is used. In this case an effort is made to
3897 address with faster (gp) register relative addressing, which can
3898 only get at sdata and sbss items (there is no stext !!) However,
3899 if the constant is too large for sdata, and it's readonly, it
3900 will go into the .rdata section. */
3902 #define EXTRA_SECTION_FUNCTIONS \
3906 if (in_section != in_sdata) \
3908 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
3909 in_section = in_sdata; \
3916 if (in_section != in_rdata) \
3918 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
3919 in_section = in_rdata; \
3923 /* Given a decl node or constant node, choose the section to output it in
3924 and select that section. */
3926 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
3928 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
3931 /* Store in OUTPUT a string (made with alloca) containing
3932 an assembler-name for a local static variable named NAME.
3933 LABELNO is an integer which is different for each call. */
3935 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
3936 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
3937 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
3939 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3942 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3943 TARGET_64BIT ? "dsubu" : "subu", \
3944 reg_names[STACK_POINTER_REGNUM], \
3945 reg_names[STACK_POINTER_REGNUM], \
3946 TARGET_64BIT ? "sd" : "sw", \
3948 reg_names[STACK_POINTER_REGNUM]); \
3952 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3955 if (! set_noreorder) \
3956 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3958 dslots_load_total++; \
3959 dslots_load_filled++; \
3960 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3961 TARGET_64BIT ? "ld" : "lw", \
3963 reg_names[STACK_POINTER_REGNUM], \
3964 TARGET_64BIT ? "daddu" : "addu", \
3965 reg_names[STACK_POINTER_REGNUM], \
3966 reg_names[STACK_POINTER_REGNUM]); \
3968 if (! set_noreorder) \
3969 fprintf (STREAM, "\t.set\treorder\n"); \
3973 /* Define the parentheses used to group arithmetic operations
3974 in assembler code. */
3976 #define ASM_OPEN_PAREN "("
3977 #define ASM_CLOSE_PAREN ")"
3979 /* How to start an assembler comment.
3980 The leading space is important (the mips native assembler requires it). */
3981 #ifndef ASM_COMMENT_START
3982 #define ASM_COMMENT_START " #"
3986 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
3987 and mips-tdump.c to print them out.
3989 These must match the corresponding definitions in gdb/mipsread.c.
3990 Unfortunately, gcc and gdb do not currently share any directories. */
3992 #define CODE_MASK 0x8F300
3993 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
3994 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
3995 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
3998 /* Default definitions for size_t and ptrdiff_t. */
4001 #define NO_BUILTIN_SIZE_TYPE
4002 #define SIZE_TYPE (TARGET_LONG64 ? "long unsigned int" : "unsigned int")
4005 #ifndef PTRDIFF_TYPE
4006 #define NO_BUILTIN_PTRDIFF_TYPE
4007 #define PTRDIFF_TYPE (TARGET_LONG64 ? "long int" : "int")
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