1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-97, 1998 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern char *language_string;
32 extern int may_call_alloca;
33 extern char **save_argv;
34 extern int target_flags;
35 extern char *version_string;
37 /* MIPS external variables defined in mips.c. */
41 CMP_SI, /* compare four byte integers */
42 CMP_DI, /* compare eight byte integers */
43 CMP_SF, /* compare single precision floats */
44 CMP_DF, /* compare double precision floats */
45 CMP_MAX /* max comparison type */
48 /* types of delay slot */
50 DELAY_NONE, /* no delay slot */
51 DELAY_LOAD, /* load from memory delay */
52 DELAY_HILO, /* move from/to hi/lo registers */
53 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
56 /* Which processor to schedule for. Since there is no difference between
57 a R2000 and R3000 in terms of the scheduler, we collapse them into
58 just an R3000. The elements of the enumeration must match exactly
59 the cpu attribute in the mips.md machine description. */
75 /* Recast the cpu class to be the cpu attribute. */
76 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
78 /* Which ABI to use. These are constants because abi64.h must check their
79 value at preprocessing time. */
86 #ifndef MIPS_ABI_DEFAULT
87 /* We define this away so that there is no extra runtime cost if the target
88 doesn't support multiple ABIs. */
89 #define mips_abi ABI_32
94 /* Whether to emit abicalls code sequences or not. */
96 enum mips_abicalls_type {
101 /* Recast the abicalls class to be the abicalls attribute. */
102 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
104 /* Which type of block move to do (whether or not the last store is
105 split out so it can fill a branch delay slot). */
107 enum block_move_type {
108 BLOCK_MOVE_NORMAL, /* generate complete block move */
109 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
110 BLOCK_MOVE_LAST /* generate just the last store */
113 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
114 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
115 extern char *current_function_file; /* filename current function is in */
116 extern int num_source_filenames; /* current .file # */
117 extern int inside_function; /* != 0 if inside of a function */
118 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
119 extern int file_in_function_warning; /* warning given about .file in func */
120 extern int sdb_label_count; /* block start/end next label # */
121 extern int sdb_begin_function_line; /* Starting Line of current function */
122 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
123 extern int g_switch_value; /* value of the -G xx switch */
124 extern int g_switch_set; /* whether -G xx was passed. */
125 extern int sym_lineno; /* sgi next label # for each stmt */
126 extern int set_noreorder; /* # of nested .set noreorder's */
127 extern int set_nomacro; /* # of nested .set nomacro's */
128 extern int set_noat; /* # of nested .set noat's */
129 extern int set_volatile; /* # of nested .set volatile's */
130 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
131 extern int mips_dbx_regno[]; /* Map register # to debug register # */
132 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
133 extern enum cmp_type branch_type; /* what type of branch to use */
134 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
135 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
136 extern int mips_isa; /* architectural level */
137 extern int mips16; /* whether generating mips16 code */
138 extern int mips16_hard_float; /* mips16 without -msoft-float */
139 extern int mips_entry; /* generate entry/exit for mips16 */
140 extern char *mips_cpu_string; /* for -mcpu=<xxx> */
141 extern char *mips_isa_string; /* for -mips{1,2,3,4} */
142 extern char *mips_abi_string; /* for -mabi={32,n32,64} */
143 extern char *mips_entry_string; /* for -mentry */
144 extern char *mips_no_mips16_string; /* for -mno-mips16 */
145 extern int mips_split_addresses; /* perform high/lo_sum support */
146 extern int dslots_load_total; /* total # load related delay slots */
147 extern int dslots_load_filled; /* # filled load delay slots */
148 extern int dslots_jump_total; /* total # jump related delay slots */
149 extern int dslots_jump_filled; /* # filled jump delay slots */
150 extern int dslots_number_nops; /* # of nops needed by previous insn */
151 extern int num_refs[3]; /* # 1/2/3 word references */
152 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
153 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
154 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
155 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
156 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
157 extern int mips_string_length; /* length of strings for mips16 */
158 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
160 /* Functions within mips.c that we reference. Some of these return type
161 HOST_WIDE_INT, so define that here. This is a copy of code in machmode.h.
163 ??? It would be good to try to put this as common code someplace. */
165 #ifndef HOST_BITS_PER_WIDE_INT
167 #if HOST_BITS_PER_LONG > HOST_BITS_PER_INT
168 #define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONG
169 #define HOST_WIDE_INT long
171 #define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_INT
172 #define HOST_WIDE_INT int
177 extern void abort_with_insn ();
178 extern int arith32_operand ();
179 extern int arith_operand ();
180 extern int cmp_op ();
181 extern HOST_WIDE_INT compute_frame_size ();
182 extern int const_float_1_operand ();
183 extern void expand_block_move ();
184 extern int equality_op ();
185 extern void final_prescan_insn ();
186 extern struct rtx_def * function_arg ();
187 extern void function_arg_advance ();
188 extern int function_arg_partial_nregs ();
189 extern int function_arg_pass_by_reference ();
190 extern void function_epilogue ();
191 extern void function_prologue ();
192 extern void gen_conditional_branch ();
193 extern void gen_conditional_move ();
194 extern struct rtx_def * gen_int_relational ();
195 extern void init_cumulative_args ();
196 extern int large_int ();
197 extern void machine_dependent_reorg ();
198 extern int mips_address_cost ();
199 extern void mips_asm_file_end ();
200 extern void mips_asm_file_start ();
201 extern int mips_can_use_return_insn ();
202 extern int mips_const_double_ok ();
203 extern void mips_count_memory_refs ();
204 extern HOST_WIDE_INT mips_debugger_offset ();
205 extern void mips_declare_object ();
206 extern int mips_epilogue_delay_slots ();
207 extern void mips_expand_epilogue ();
208 extern void mips_expand_prologue ();
209 extern int mips_check_split ();
210 extern char *mips_fill_delay_slot ();
211 extern char *mips_move_1word ();
212 extern char *mips_move_2words ();
213 extern void mips_output_double ();
214 extern int mips_output_external ();
215 extern void mips_output_float ();
216 extern void mips_output_filename ();
217 extern void mips_output_lineno ();
218 extern char *output_block_move ();
219 extern void override_options ();
220 extern int pc_or_label_operand ();
221 extern void print_operand_address ();
222 extern void print_operand ();
223 extern void print_options ();
224 extern int reg_or_0_operand ();
225 extern int simple_epilogue_p ();
226 extern int simple_memory_operand ();
227 extern int double_memory_operand ();
228 extern int small_int ();
229 extern void trace ();
230 extern int uns_arith_operand ();
231 extern struct rtx_def * embedded_pic_offset ();
232 extern void mips_order_regs_for_local_alloc ();
233 extern struct rtx_def * mips16_gp_pseudo_reg ();
234 extern struct rtx_def * mips16_gp_offset ();
235 extern int mips16_gp_offset_p ();
236 extern int mips16_constant ();
237 extern int mips16_constant_after_function_p ();
238 extern int build_mips16_call_stub ();
240 /* Recognition functions that return if a condition is true. */
241 extern int address_operand ();
242 extern int call_insn_operand ();
243 extern int const_double_operand ();
244 extern int const_int_operand ();
245 extern int consttable_operand ();
246 extern int general_operand ();
247 extern int immediate_operand ();
248 extern int memory_address_p ();
249 extern int memory_operand ();
250 extern int nonimmediate_operand ();
251 extern int nonmemory_operand ();
252 extern int pic_address_needs_scratch ();
253 extern int register_operand ();
254 extern int scratch_operand ();
255 extern int move_operand ();
256 extern int movdi_operand ();
257 extern int se_register_operand ();
258 extern int se_reg_or_0_operand ();
259 extern int se_uns_arith_operand ();
260 extern int se_arith_operand ();
261 extern int se_nonmemory_operand ();
262 extern int se_nonimmediate_operand ();
263 extern int extend_operator ();
264 extern int highpart_shift_operator ();
265 extern int m16_uimm3_b ();
266 extern int m16_simm4_1 ();
267 extern int m16_nsimm4_1 ();
268 extern int m16_simm5_1 ();
269 extern int m16_nsimm5_1 ();
270 extern int m16_uimm5_4 ();
271 extern int m16_nuimm5_4 ();
272 extern int m16_simm8_1 ();
273 extern int m16_nsimm8_1 ();
274 extern int m16_uimm8_1 ();
275 extern int m16_nuimm8_1 ();
276 extern int m16_uimm8_m1_1 ();
277 extern int m16_uimm8_4 ();
278 extern int m16_nuimm8_4 ();
279 extern int m16_simm8_8 ();
280 extern int m16_nsimm8_8 ();
281 extern int m16_usym8_4 ();
282 extern int m16_usym5_4 ();
284 /* Functions to change what output section we are using. */
285 extern void data_section ();
286 extern void rdata_section ();
287 extern void readonly_data_section ();
288 extern void sdata_section ();
289 extern void text_section ();
290 extern void mips_select_rtx_section ();
291 extern void mips_select_section ();
293 /* Stubs for half-pic support if not OSF/1 reference platform. */
296 #define HALF_PIC_P() 0
297 #define HALF_PIC_NUMBER_PTRS 0
298 #define HALF_PIC_NUMBER_REFS 0
299 #define HALF_PIC_ENCODE(DECL)
300 #define HALF_PIC_DECLARE(NAME)
301 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
302 #define HALF_PIC_ADDRESS_P(X) 0
303 #define HALF_PIC_PTR(X) X
304 #define HALF_PIC_FINISH(STREAM)
308 /* Run-time compilation parameters selecting different hardware subsets. */
310 /* Macros used in the machine description to test the flags. */
312 /* Bits for real switches */
313 #define MASK_INT64 0x00000001 /* ints are 64 bits */
314 #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
315 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
316 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
317 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
318 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
319 #define MASK_STATS 0x00000040 /* print statistics to stderr */
320 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
321 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
322 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
323 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
324 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
325 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
326 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
327 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
328 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
329 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
330 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
331 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
332 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
333 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
334 #define MASK_MIPS16 0x01000000 /* Generate mips16 code */
336 /* Dummy switches used only in spec's*/
337 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
339 /* Debug switches, not documented */
340 #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */
341 #define MASK_DEBUG_A 0x20000000 /* don't allow <label>($reg) addrs */
342 #define MASK_DEBUG_B 0x10000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
343 #define MASK_DEBUG_C 0x08000000 /* don't expand seq, etc. */
344 #define MASK_DEBUG_D 0x04000000 /* don't do define_split's */
345 #define MASK_DEBUG_E 0x02000000 /* function_arg debug */
346 #define MASK_DEBUG_F 0
347 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
348 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
349 #define MASK_DEBUG_I 0x00200000 /* unused */
351 /* r4000 64 bit sizes */
352 #define TARGET_INT64 (target_flags & MASK_INT64)
353 #define TARGET_LONG64 (target_flags & MASK_LONG64)
354 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
355 #define TARGET_64BIT (target_flags & MASK_64BIT)
357 /* Mips vs. GNU linker */
358 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
360 /* generate mips 3900 insns */
361 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
363 /* Mips vs. GNU assembler */
364 #define TARGET_GAS (target_flags & MASK_GAS)
365 #define TARGET_UNIX_ASM (!TARGET_GAS)
366 #define TARGET_MIPS_AS TARGET_UNIX_ASM
369 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
370 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
371 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
372 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
373 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
374 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
375 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
376 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
377 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
378 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
380 /* Reg. Naming in .s ($21 vs. $a0) */
381 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
383 /* Optimize for Sdata/Sbss */
384 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
386 /* print program statistics */
387 #define TARGET_STATS (target_flags & MASK_STATS)
389 /* call memcpy instead of inline code */
390 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
392 /* .abicalls, etc from Pyramid V.4 */
393 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
395 /* OSF pic references to externs */
396 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
398 /* software floating point */
399 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
400 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
402 /* always call through a register */
403 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
405 /* generate embedded PIC code;
407 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
409 /* for embedded systems, optimize for
410 reduced RAM space instead of for
412 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
414 /* generate big endian code. */
415 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
417 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
418 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
420 #define TARGET_MAD (target_flags & MASK_MAD)
422 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
424 /* This is true if we must enable the assembly language file switching
427 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
429 /* We must disable the function end stabs when doing the file switching trick,
430 because the Lscope stabs end up in the wrong place, making it impossible
431 to debug the resulting code. */
432 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
434 /* Generate mips16 code */
435 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
437 /* Macro to define tables used to set the flags.
438 This is a list in braces of pairs in braces,
439 each pair being { "NAME", VALUE }
440 where VALUE is the bits to set or minus the bits to clear.
441 An empty string NAME is used to identify the default VALUE. */
443 #define TARGET_SWITCHES \
445 {"int64", MASK_INT64 | MASK_LONG64}, \
446 {"long64", MASK_LONG64}, \
447 {"split-addresses", MASK_SPLIT_ADDR}, \
448 {"no-split-addresses", -MASK_SPLIT_ADDR}, \
449 {"mips-as", -MASK_GAS}, \
451 {"rnames", MASK_NAME_REGS}, \
452 {"no-rnames", -MASK_NAME_REGS}, \
453 {"gpOPT", MASK_GPOPT}, \
454 {"gpopt", MASK_GPOPT}, \
455 {"no-gpOPT", -MASK_GPOPT}, \
456 {"no-gpopt", -MASK_GPOPT}, \
457 {"stats", MASK_STATS}, \
458 {"no-stats", -MASK_STATS}, \
459 {"memcpy", MASK_MEMCPY}, \
460 {"no-memcpy", -MASK_MEMCPY}, \
461 {"mips-tfile", MASK_MIPS_TFILE}, \
462 {"no-mips-tfile", -MASK_MIPS_TFILE}, \
463 {"soft-float", MASK_SOFT_FLOAT}, \
464 {"hard-float", -MASK_SOFT_FLOAT}, \
465 {"fp64", MASK_FLOAT64}, \
466 {"fp32", -MASK_FLOAT64}, \
467 {"gp64", MASK_64BIT}, \
468 {"gp32", -MASK_64BIT}, \
469 {"abicalls", MASK_ABICALLS}, \
470 {"no-abicalls", -MASK_ABICALLS}, \
471 {"half-pic", MASK_HALF_PIC}, \
472 {"no-half-pic", -MASK_HALF_PIC}, \
473 {"long-calls", MASK_LONG_CALLS}, \
474 {"no-long-calls", -MASK_LONG_CALLS}, \
475 {"embedded-pic", MASK_EMBEDDED_PIC}, \
476 {"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
477 {"embedded-data", MASK_EMBEDDED_DATA}, \
478 {"no-embedded-data", -MASK_EMBEDDED_DATA}, \
479 {"eb", MASK_BIG_ENDIAN}, \
480 {"el", -MASK_BIG_ENDIAN}, \
481 {"single-float", MASK_SINGLE_FLOAT}, \
482 {"double-float", -MASK_SINGLE_FLOAT}, \
484 {"no-mad", -MASK_MAD}, \
485 {"fix4300", MASK_4300_MUL_FIX}, \
486 {"no-fix4300", -MASK_4300_MUL_FIX}, \
487 {"4650", MASK_MAD | MASK_SINGLE_FLOAT}, \
488 {"3900", MASK_MIPS3900}, \
489 {"debug", MASK_DEBUG}, \
490 {"debuga", MASK_DEBUG_A}, \
491 {"debugb", MASK_DEBUG_B}, \
492 {"debugc", MASK_DEBUG_C}, \
493 {"debugd", MASK_DEBUG_D}, \
494 {"debuge", MASK_DEBUG_E}, \
495 {"debugf", MASK_DEBUG_F}, \
496 {"debugg", MASK_DEBUG_G}, \
497 {"debugh", MASK_DEBUG_H}, \
498 {"debugi", MASK_DEBUG_I}, \
499 {"", (TARGET_DEFAULT \
500 | TARGET_CPU_DEFAULT \
501 | TARGET_ENDIAN_DEFAULT)} \
504 /* Default target_flags if no switches are specified */
506 #ifndef TARGET_DEFAULT
507 #define TARGET_DEFAULT 0
510 #ifndef TARGET_CPU_DEFAULT
511 #define TARGET_CPU_DEFAULT 0
514 #ifndef TARGET_ENDIAN_DEFAULT
516 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
518 #define TARGET_ENDIAN_DEFAULT 0
522 #ifndef MULTILIB_DEFAULTS
523 #if TARGET_ENDIAN_DEFAULT == 0
524 #define MULTILIB_DEFAULTS { "EL", "mips1" }
526 #define MULTILIB_DEFAULTS { "EB", "mips1" }
530 /* We must pass -EL to the linker by default for little endian embedded
531 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
532 linker will default to using big-endian output files. The OUTPUT_FORMAT
533 line must be in the linker script, otherwise -EB/-EL will not work. */
535 #ifndef LINKER_ENDIAN_SPEC
536 #if TARGET_ENDIAN_DEFAULT == 0
537 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
539 #define LINKER_ENDIAN_SPEC ""
543 /* This macro is similar to `TARGET_SWITCHES' but defines names of
544 command options that have values. Its definition is an
545 initializer with a subgrouping for each command option.
547 Each subgrouping contains a string constant, that defines the
548 fixed part of the option name, and the address of a variable.
549 The variable, type `char *', is set to the variable part of the
550 given option if the fixed part matches. The actual option name
551 is made by appending `-m' to the specified name.
553 Here is an example which defines `-mshort-data-NUMBER'. If the
554 given option is `-mshort-data-512', the variable `m88k_short_data'
555 will be set to the string `"512"'.
557 extern char *m88k_short_data;
558 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
560 #define TARGET_OPTIONS \
562 SUBTARGET_TARGET_OPTIONS \
563 { "cpu=", &mips_cpu_string }, \
564 { "ips", &mips_isa_string }, \
565 { "entry", &mips_entry_string }, \
566 { "no-mips16", &mips_no_mips16_string } \
569 /* This is meant to be redefined in the host dependent files. */
570 #define SUBTARGET_TARGET_OPTIONS
572 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
573 #define GENERATE_MULT3 (TARGET_MIPS3900 \
575 #define GENERATE_MADD (TARGET_MIPS3900 \
580 /* Macros to decide whether certain features are available or not,
581 depending on the instruction set architecture level. */
583 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
584 #define HAVE_SQRT_P() (mips_isa >= 2)
586 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
587 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
588 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
589 target_flags, and -mgp64 sets MASK_64BIT.
591 Setting MASK_64BIT in target_flags will cause gcc to assume that
592 registers are 64 bits wide. int, long and void * will be 32 bit;
593 this may be changed with -mint64 or -mlong64.
595 The gen* programs link code that refers to MASK_64BIT. They don't
596 actually use the information in target_flags; they just refer to
599 /* Switch Recognition by gcc.c. Add -G xx support */
601 #ifdef SWITCH_TAKES_ARG
602 #undef SWITCH_TAKES_ARG
605 #define SWITCH_TAKES_ARG(CHAR) \
606 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
608 /* Sometimes certain combinations of command options do not make sense
609 on a particular target machine. You can define a macro
610 `OVERRIDE_OPTIONS' to take account of this. This macro, if
611 defined, is executed once just after all the command options have
614 On the MIPS, it is used to handle -G. We also use it to set up all
615 of the tables referenced in the other macros. */
617 #define OVERRIDE_OPTIONS override_options ()
619 /* Zero or more C statements that may conditionally modify two
620 variables `fixed_regs' and `call_used_regs' (both of type `char
621 []') after they have been initialized from the two preceding
624 This is necessary in case the fixed or call-clobbered registers
625 depend on target flags.
627 You need not define this macro if it has no work to do.
629 If the usage of an entire class of registers depends on the target
630 flags, you may indicate this to GCC by using this macro to modify
631 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
632 the classes which should not be used by GCC. Also define the macro
633 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
634 letter for a class that shouldn't be used.
636 (However, if this class is not included in `GENERAL_REGS' and all
637 of the insn patterns whose constraints permit this class are
638 controlled by target switches, then GCC will automatically avoid
639 using these registers when the target switches are opposed to
642 #define CONDITIONAL_REGISTER_USAGE \
645 if (!TARGET_HARD_FLOAT) \
649 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
650 fixed_regs[regno] = call_used_regs[regno] = 1; \
651 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
652 fixed_regs[regno] = call_used_regs[regno] = 1; \
654 else if (mips_isa < 4) \
658 /* We only have a single condition code register. We \
659 implement this by hiding all the condition code registers, \
660 and generating RTL that refers directly to ST_REG_FIRST. */ \
661 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
662 fixed_regs[regno] = call_used_regs[regno] = 1; \
664 /* In mips16 mode, we permit the $t temporary registers to be used \
665 for reload. We prohibit the unused $s registers, since they \
666 are caller saved, and saving them via a mips16 register would \
667 probably waste more time than just reloading the value. */ \
670 fixed_regs[18] = call_used_regs[18] = 1; \
671 fixed_regs[19] = call_used_regs[19] = 1; \
672 fixed_regs[20] = call_used_regs[20] = 1; \
673 fixed_regs[21] = call_used_regs[21] = 1; \
674 fixed_regs[22] = call_used_regs[22] = 1; \
675 fixed_regs[23] = call_used_regs[23] = 1; \
676 fixed_regs[26] = call_used_regs[26] = 1; \
677 fixed_regs[27] = call_used_regs[27] = 1; \
678 fixed_regs[30] = call_used_regs[30] = 1; \
680 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
684 /* This is meant to be redefined in the host dependent files. */
685 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
687 /* Show we can debug even without a frame pointer. */
688 #define CAN_DEBUG_WITHOUT_FP
690 /* Complain about missing specs and predefines that should be defined in each
691 of the target tm files to override the defaults. This is mostly a place-
692 holder until I can get each of the files updated [mm]. */
694 #if defined(OSF_OS) \
695 || defined(DECSTATION) \
696 || defined(SGI_TARGET) \
697 || defined(MIPS_NEWS) \
698 || defined(MIPS_SYSV) \
699 || defined(MIPS_SVR4) \
700 || defined(MIPS_BSD43)
702 #ifndef CPP_PREDEFINES
703 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
707 #error "Define LIB_SPEC in the appropriate tm.h file"
710 #ifndef STARTFILE_SPEC
711 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
715 #error "Define MACHINE_TYPE in the appropriate tm.h file"
719 /* Tell collect what flags to pass to nm. */
721 #define NM_FLAGS "-Bp"
725 /* Names to predefine in the preprocessor for this target machine. */
727 #ifndef CPP_PREDEFINES
728 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
729 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
730 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
733 /* Assembler specs. */
735 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
738 #define MIPS_AS_ASM_SPEC "\
739 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
740 %{pipe: %e-pipe is not supported.} \
741 %{K} %(subtarget_mips_as_asm_spec)"
743 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
744 rather than gas. It may be overridden by subtargets. */
746 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
747 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
750 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
753 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
755 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
756 GAS_ASM_SPEC as the default, depending upon the value of
759 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
762 #define TARGET_ASM_SPEC "\
763 %{mmips-as: %(mips_as_asm_spec)} \
764 %{!mmips-as: %(gas_asm_spec)}"
768 #define TARGET_ASM_SPEC "\
769 %{!mgas: %(mips_as_asm_spec)} \
770 %{mgas: %(gas_asm_spec)}"
774 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
775 to the assembler. It may be overridden by subtargets. */
776 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
777 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
779 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
782 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
783 the assembler. It may be overridden by subtargets. */
784 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
785 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
786 %{g} %{g0} %{g1} %{g2} %{g3} \
787 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
788 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
789 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
790 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
793 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
794 overridden by subtargets. */
796 #ifndef SUBTARGET_ASM_SPEC
797 #define SUBTARGET_ASM_SPEC ""
800 /* ASM_SPEC is the set of arguments to pass to the assembler. */
803 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
804 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
805 %(subtarget_asm_optimizing_spec) \
806 %(subtarget_asm_debugging_spec) \
808 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
810 %(subtarget_asm_spec)"
812 /* Specify to run a post-processor, mips-tfile after the assembler
813 has run to stuff the mips debug information into the object file.
814 This is needed because the $#!%^ MIPS assembler provides no way
815 of specifying such information in the assembly file. If we are
816 cross compiling, disable mips-tfile unless the user specifies
819 #ifndef ASM_FINAL_SPEC
820 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
822 #define ASM_FINAL_SPEC "\
823 %{mmips-as: %{!mno-mips-tfile: \
824 \n mips-tfile %{v*: -v} \
826 %{!K: %{save-temps: -I %b.o~}} \
827 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
828 %{.s:%i} %{!.s:%g.s}}}"
832 #define ASM_FINAL_SPEC "\
833 %{!mgas: %{!mno-mips-tfile: \
834 \n mips-tfile %{v*: -v} \
836 %{!K: %{save-temps: -I %b.o~}} \
837 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
838 %{.s:%i} %{!.s:%g.s}}}"
841 #endif /* ASM_FINAL_SPEC */
843 /* Redefinition of libraries used. Mips doesn't support normal
844 UNIX style profiling via calling _mcount. It does offer
845 profiling that samples the PC, so do what we can... */
848 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
851 /* Extra switches sometimes passed to the linker. */
852 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
853 will interpret it as a -b option. */
857 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
858 %{bestGnum} %{shared} %{non_shared} \
859 %(linker_endian_spec)"
860 #endif /* LINK_SPEC defined */
862 /* Specs for the compiler proper */
864 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
865 overridden by subtargets. */
866 #ifndef SUBTARGET_CC1_SPEC
867 #define SUBTARGET_CC1_SPEC ""
870 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
874 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
875 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
876 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
877 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
878 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
879 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
880 %{m4650:-mcpu=r4650} \
881 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
882 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
883 %{pic-none: -mno-half-pic} \
884 %{pic-lib: -mhalf-pic} \
885 %{pic-extern: -mhalf-pic} \
886 %{pic-calls: -mhalf-pic} \
888 %(subtarget_cc1_spec) "
891 /* Preprocessor specs. */
893 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
894 be overridden by subtargets. */
896 #ifndef SUBTARGET_CPP_SIZE_SPEC
897 #define SUBTARGET_CPP_SIZE_SPEC "\
898 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
899 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
902 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
903 overridden by subtargets. */
904 #ifndef SUBTARGET_CPP_SPEC
905 #define SUBTARGET_CPP_SPEC ""
908 /* If we're using 64bit longs, then we have to define __LONG_MAX__
909 correctly. Similarly for 64bit ints and __INT_MAX__. */
910 #ifndef LONG_MAX_SPEC
911 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
912 #define LONG_MAX_SPEC "%{!mno-long64:-D__LONG_MAX__=9223372036854775807L}"
914 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
918 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
922 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
923 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
924 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
925 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
926 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
927 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
928 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
929 %(subtarget_cpp_size_spec) \
930 %{mips3:-U__mips -D__mips=3 -D__mips64} \
931 %{mips4:-U__mips -D__mips=4 -D__mips64} \
932 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
933 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
934 %{m4650:%{!msoft-float:-D__mips_single_float}} \
935 %{msoft-float:-D__mips_soft_float} \
936 %{mabi=eabi:-D__mips_eabi} \
937 %{mips16:%{!mno-mips16:-D__mips16}} \
938 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
939 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
941 %(subtarget_cpp_spec) "
944 /* This macro defines names of additional specifications to put in the specs
945 that can be used in various specifications like CC1_SPEC. Its definition
946 is an initializer with a subgrouping for each command option.
948 Each subgrouping contains a string constant, that defines the
949 specification name, and a string constant that used by the GNU CC driver
952 Do not define this macro if it does not need to do anything. */
954 #define EXTRA_SPECS \
955 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
956 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
957 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
958 { "long_max_spec", LONG_MAX_SPEC }, \
959 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
960 { "gas_asm_spec", GAS_ASM_SPEC }, \
961 { "target_asm_spec", TARGET_ASM_SPEC }, \
962 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
963 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
964 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
965 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
966 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
967 SUBTARGET_EXTRA_SPECS
969 #ifndef SUBTARGET_EXTRA_SPECS
970 #define SUBTARGET_EXTRA_SPECS
973 /* If defined, this macro is an additional prefix to try after
974 `STANDARD_EXEC_PREFIX'. */
976 #ifndef MD_EXEC_PREFIX
977 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
980 #ifndef MD_STARTFILE_PREFIX
981 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
985 /* Print subsidiary information on the compiler version in use. */
987 #define MIPS_VERSION "[AL 1.1, MM 40]"
990 #define MACHINE_TYPE "BSD Mips"
993 #ifndef TARGET_VERSION_INTERNAL
994 #define TARGET_VERSION_INTERNAL(STREAM) \
995 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
998 #ifndef TARGET_VERSION
999 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1003 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1004 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1005 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1007 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1008 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1011 /* By default, turn on GDB extensions. */
1012 #define DEFAULT_GDB_EXTENSIONS 1
1014 /* If we are passing smuggling stabs through the MIPS ECOFF object
1015 format, put a comment in front of the .stab<x> operation so
1016 that the MIPS assembler does not choke. The mips-tfile program
1017 will correctly put the stab into the object file. */
1019 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
1020 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
1021 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
1023 /* Local compiler-generated symbols must have a prefix that the assembler
1024 understands. By default, this is $, although some targets (e.g.,
1025 NetBSD-ELF) need to override this. */
1027 #ifndef LOCAL_LABEL_PREFIX
1028 #define LOCAL_LABEL_PREFIX "$"
1031 /* By default on the mips, external symbols do not have an underscore
1032 prepended, but some targets (e.g., NetBSD) require this. */
1034 #ifndef USER_LABEL_PREFIX
1035 #define USER_LABEL_PREFIX ""
1038 /* Forward references to tags are allowed. */
1039 #define SDB_ALLOW_FORWARD_REFERENCES
1041 /* Unknown tags are also allowed. */
1042 #define SDB_ALLOW_UNKNOWN_REFERENCES
1044 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1045 since the length can run past this up to a continuation point. */
1046 #define DBX_CONTIN_LENGTH 1500
1048 /* How to renumber registers for dbx and gdb. */
1049 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1051 /* The mapping from gcc register number to DWARF 2 CFA column number.
1052 This mapping does not allow for tracking register 0, since SGI's broken
1053 dwarf reader thinks column 0 is used for the frame address, but since
1054 register 0 is fixed this is not a problem. */
1055 #define DWARF_FRAME_REGNUM(REG) \
1056 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1058 /* The DWARF 2 CFA column which tracks the return address. */
1059 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1061 /* Before the prologue, RA lives in r31. */
1062 #define INCOMING_RETURN_ADDR_RTX gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
1064 /* Overrides for the COFF debug format. */
1065 #define PUT_SDB_SCL(a) \
1067 extern FILE *asm_out_text_file; \
1068 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1071 #define PUT_SDB_INT_VAL(a) \
1073 extern FILE *asm_out_text_file; \
1074 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1077 #define PUT_SDB_VAL(a) \
1079 extern FILE *asm_out_text_file; \
1080 fputs ("\t.val\t", asm_out_text_file); \
1081 output_addr_const (asm_out_text_file, (a)); \
1082 fputc (';', asm_out_text_file); \
1085 #define PUT_SDB_DEF(a) \
1087 extern FILE *asm_out_text_file; \
1088 fprintf (asm_out_text_file, "\t%s.def\t", \
1089 (TARGET_GAS) ? "" : "#"); \
1090 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1091 fputc (';', asm_out_text_file); \
1094 #define PUT_SDB_PLAIN_DEF(a) \
1096 extern FILE *asm_out_text_file; \
1097 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1098 (TARGET_GAS) ? "" : "#", (a)); \
1101 #define PUT_SDB_ENDEF \
1103 extern FILE *asm_out_text_file; \
1104 fprintf (asm_out_text_file, "\t.endef\n"); \
1107 #define PUT_SDB_TYPE(a) \
1109 extern FILE *asm_out_text_file; \
1110 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1113 #define PUT_SDB_SIZE(a) \
1115 extern FILE *asm_out_text_file; \
1116 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1119 #define PUT_SDB_DIM(a) \
1121 extern FILE *asm_out_text_file; \
1122 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1125 #ifndef PUT_SDB_START_DIM
1126 #define PUT_SDB_START_DIM \
1128 extern FILE *asm_out_text_file; \
1129 fprintf (asm_out_text_file, "\t.dim\t"); \
1133 #ifndef PUT_SDB_NEXT_DIM
1134 #define PUT_SDB_NEXT_DIM(a) \
1136 extern FILE *asm_out_text_file; \
1137 fprintf (asm_out_text_file, "%d,", a); \
1141 #ifndef PUT_SDB_LAST_DIM
1142 #define PUT_SDB_LAST_DIM(a) \
1144 extern FILE *asm_out_text_file; \
1145 fprintf (asm_out_text_file, "%d;", a); \
1149 #define PUT_SDB_TAG(a) \
1151 extern FILE *asm_out_text_file; \
1152 fprintf (asm_out_text_file, "\t.tag\t"); \
1153 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1154 fputc (';', asm_out_text_file); \
1157 /* For block start and end, we create labels, so that
1158 later we can figure out where the correct offset is.
1159 The normal .ent/.end serve well enough for functions,
1160 so those are just commented out. */
1162 #define PUT_SDB_BLOCK_START(LINE) \
1164 extern FILE *asm_out_text_file; \
1165 fprintf (asm_out_text_file, \
1166 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1167 LOCAL_LABEL_PREFIX, \
1169 (TARGET_GAS) ? "" : "#", \
1170 LOCAL_LABEL_PREFIX, \
1173 sdb_label_count++; \
1176 #define PUT_SDB_BLOCK_END(LINE) \
1178 extern FILE *asm_out_text_file; \
1179 fprintf (asm_out_text_file, \
1180 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1181 LOCAL_LABEL_PREFIX, \
1183 (TARGET_GAS) ? "" : "#", \
1184 LOCAL_LABEL_PREFIX, \
1187 sdb_label_count++; \
1190 #define PUT_SDB_FUNCTION_START(LINE)
1192 #define PUT_SDB_FUNCTION_END(LINE) \
1194 extern FILE *asm_out_text_file; \
1195 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1198 #define PUT_SDB_EPILOGUE_END(NAME)
1200 #define PUT_SDB_SRC_FILE(FILENAME) \
1202 extern FILE *asm_out_text_file; \
1203 output_file_directive (asm_out_text_file, (FILENAME)); \
1206 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1207 sprintf ((BUFFER), ".%dfake", (NUMBER));
1209 /* Correct the offset of automatic variables and arguments. Note that
1210 the MIPS debug format wants all automatic variables and arguments
1211 to be in terms of the virtual frame pointer (stack pointer before
1212 any adjustment in the function), while the MIPS 3.0 linker wants
1213 the frame pointer to be the stack pointer after the initial
1216 #define DEBUGGER_AUTO_OFFSET(X) \
1217 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1218 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1219 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1221 /* Tell collect that the object format is ECOFF */
1222 #ifndef OBJECT_FORMAT_ROSE
1223 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1224 #define EXTENDED_COFF /* ECOFF, not normal coff */
1227 #if 0 /* These definitions normally have no effect because
1228 MIPS systems define USE_COLLECT2, so
1229 assemble_constructor does nothing anyway. */
1231 /* Don't use the default definitions, because we don't have gld.
1232 Also, we don't want stabs when generating ECOFF output.
1233 Instead we depend on collect to handle these. */
1235 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1236 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1240 /* Target machine storage layout */
1242 /* Define in order to support both big and little endian float formats
1243 in the same gcc binary. */
1244 #define REAL_ARITHMETIC
1246 /* Define this if most significant bit is lowest numbered
1247 in instructions that operate on numbered bit-fields.
1249 #define BITS_BIG_ENDIAN 0
1251 /* Define this if most significant byte of a word is the lowest numbered. */
1252 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1254 /* Define this if most significant word of a multiword number is the lowest. */
1255 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1257 /* Define this to set the endianness to use in libgcc2.c, which can
1258 not depend on target_flags. */
1259 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1260 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1262 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1265 /* Number of bits in an addressable storage unit */
1266 #define BITS_PER_UNIT 8
1268 /* Width in bits of a "word", which is the contents of a machine register.
1269 Note that this is not necessarily the width of data type `int';
1270 if using 16-bit ints on a 68000, this would still be 32.
1271 But on a machine with 16-bit registers, this would be 16. */
1272 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1273 #define MAX_BITS_PER_WORD 64
1275 /* Width of a word, in units (bytes). */
1276 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1277 #define MIN_UNITS_PER_WORD 4
1279 /* For MIPS, width of a floating point register. */
1280 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1282 /* A C expression for the size in bits of the type `int' on the
1283 target machine. If you don't define this, the default is one
1285 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1286 #define MAX_INT_TYPE_SIZE 64
1288 /* Tell the preprocessor the maximum size of wchar_t. */
1289 #ifndef MAX_WCHAR_TYPE_SIZE
1290 #ifndef WCHAR_TYPE_SIZE
1291 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1295 /* A C expression for the size in bits of the type `short' on the
1296 target machine. If you don't define this, the default is half a
1297 word. (If this would be less than one storage unit, it is
1298 rounded up to one unit.) */
1299 #define SHORT_TYPE_SIZE 16
1301 /* A C expression for the size in bits of the type `long' on the
1302 target machine. If you don't define this, the default is one
1304 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1305 #define MAX_LONG_TYPE_SIZE 64
1307 /* A C expression for the size in bits of the type `long long' on the
1308 target machine. If you don't define this, the default is two
1310 #define LONG_LONG_TYPE_SIZE 64
1312 /* A C expression for the size in bits of the type `char' on the
1313 target machine. If you don't define this, the default is one
1314 quarter of a word. (If this would be less than one storage unit,
1315 it is rounded up to one unit.) */
1316 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1318 /* A C expression for the size in bits of the type `float' on the
1319 target machine. If you don't define this, the default is one
1321 #define FLOAT_TYPE_SIZE 32
1323 /* A C expression for the size in bits of the type `double' on the
1324 target machine. If you don't define this, the default is two
1326 #define DOUBLE_TYPE_SIZE 64
1328 /* A C expression for the size in bits of the type `long double' on
1329 the target machine. If you don't define this, the default is two
1331 #define LONG_DOUBLE_TYPE_SIZE 64
1333 /* Width in bits of a pointer.
1334 See also the macro `Pmode' defined below. */
1335 #ifndef POINTER_SIZE
1336 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1339 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1340 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1342 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1343 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1345 /* Allocation boundary (in *bits*) for the code of a function. */
1346 #define FUNCTION_BOUNDARY 32
1348 /* Alignment of field after `int : 0' in a structure. */
1349 #define EMPTY_FIELD_BOUNDARY 32
1351 /* Every structure's size must be a multiple of this. */
1352 /* 8 is observed right on a DECstation and on riscos 4.02. */
1353 #define STRUCTURE_SIZE_BOUNDARY 8
1355 /* There is no point aligning anything to a rounder boundary than this. */
1356 #define BIGGEST_ALIGNMENT 64
1358 /* Set this nonzero if move instructions will actually fail to work
1359 when given unaligned data. */
1360 #define STRICT_ALIGNMENT 1
1362 /* Define this if you wish to imitate the way many other C compilers
1363 handle alignment of bitfields and the structures that contain
1366 The behavior is that the type written for a bitfield (`int',
1367 `short', or other integer type) imposes an alignment for the
1368 entire structure, as if the structure really did contain an
1369 ordinary field of that type. In addition, the bitfield is placed
1370 within the structure so that it would fit within such a field,
1371 not crossing a boundary for it.
1373 Thus, on most machines, a bitfield whose type is written as `int'
1374 would not cross a four-byte boundary, and would force four-byte
1375 alignment for the whole structure. (The alignment used may not
1376 be four bytes; it is controlled by the other alignment
1379 If the macro is defined, its definition should be a C expression;
1380 a nonzero value for the expression enables this behavior. */
1382 #define PCC_BITFIELD_TYPE_MATTERS 1
1384 /* If defined, a C expression to compute the alignment given to a
1385 constant that is being placed in memory. CONSTANT is the constant
1386 and ALIGN is the alignment that the object would ordinarily have.
1387 The value of this macro is used instead of that alignment to align
1390 If this macro is not defined, then ALIGN is used.
1392 The typical use of this macro is to increase alignment for string
1393 constants to be word aligned so that `strcpy' calls that copy
1394 constants can be done inline. */
1396 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1397 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1398 && (ALIGN) < BITS_PER_WORD \
1402 /* If defined, a C expression to compute the alignment for a static
1403 variable. TYPE is the data type, and ALIGN is the alignment that
1404 the object would ordinarily have. The value of this macro is used
1405 instead of that alignment to align the object.
1407 If this macro is not defined, then ALIGN is used.
1409 One use of this macro is to increase alignment of medium-size
1410 data to make it all fit in fewer cache lines. Another is to
1411 cause character arrays to be word-aligned so that `strcpy' calls
1412 that copy constants to character arrays can be done inline. */
1414 #undef DATA_ALIGNMENT
1415 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1416 ((((ALIGN) < BITS_PER_WORD) \
1417 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1418 || TREE_CODE (TYPE) == UNION_TYPE \
1419 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1421 /* Define this macro if an argument declared as `char' or `short' in a
1422 prototype should actually be passed as an `int'. In addition to
1423 avoiding errors in certain cases of mismatch, it also makes for
1424 better code on certain machines. */
1426 #define PROMOTE_PROTOTYPES
1428 /* Define if operations between registers always perform the operation
1429 on the full register even if a narrower mode is specified. */
1430 #define WORD_REGISTER_OPERATIONS
1432 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1433 will either zero-extend or sign-extend. The value of this macro should
1434 be the code that says which one of the two operations is implicitly
1435 done, NIL if none. */
1436 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1438 /* Define this macro if it is advisable to hold scalars in registers
1439 in a wider mode than that declared by the program. In such cases,
1440 the value is constrained to be within the bounds of the declared
1441 type, but kept valid in the wider mode. The signedness of the
1442 extension may differ from that of the type.
1444 We promote any value smaller than SImode up to SImode. We don't
1445 want to promote to DImode when in 64 bit mode, because that would
1446 prevent us from using the faster SImode multiply and divide
1449 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1450 if (GET_MODE_CLASS (MODE) == MODE_INT \
1451 && GET_MODE_SIZE (MODE) < 4) \
1454 /* Define this if function arguments should also be promoted using the above
1457 #define PROMOTE_FUNCTION_ARGS
1459 /* Likewise, if the function return value is promoted. */
1461 #define PROMOTE_FUNCTION_RETURN
1463 /* Standard register usage. */
1465 /* Number of actual hardware registers.
1466 The hardware registers are assigned numbers for the compiler
1467 from 0 to just below FIRST_PSEUDO_REGISTER.
1468 All registers that the compiler knows about must be given numbers,
1469 even those that are not normally considered general registers.
1471 On the Mips, we have 32 integer registers, 32 floating point
1472 registers, 8 condition code registers, and the special registers
1473 hi, lo, hilo, and rap. The 8 condition code registers are only
1474 used if mips_isa >= 4. The hilo register is only used in 64 bit
1475 mode. It represents a 64 bit value stored as two 32 bit values in
1476 the hi and lo registers; this is the result of the mult
1477 instruction. rap is a pointer to the stack where the return
1478 address reg ($31) was stored. This is needed for C++ exception
1481 #define FIRST_PSEUDO_REGISTER 76
1483 /* 1 for registers that have pervasive standard uses
1484 and are not available for the register allocator.
1486 On the MIPS, see conventions, page D-2 */
1488 #define FIXED_REGISTERS \
1490 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1491 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1492 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1493 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1494 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1498 /* 1 for registers not available across function calls.
1499 These must include the FIXED_REGISTERS and also any
1500 registers that can be used without being saved.
1501 The latter must include the registers where values are returned
1502 and the register where structure-value addresses are passed.
1503 Aside from that, you can include as many other registers as you like. */
1505 #define CALL_USED_REGISTERS \
1507 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1508 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1509 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1510 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1511 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1515 /* Internal macros to classify a register number as to whether it's a
1516 general purpose register, a floating point register, a
1517 multiply/divide register, or a status register. */
1519 #define GP_REG_FIRST 0
1520 #define GP_REG_LAST 31
1521 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1522 #define GP_DBX_FIRST 0
1524 #define FP_REG_FIRST 32
1525 #define FP_REG_LAST 63
1526 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1527 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1529 #define MD_REG_FIRST 64
1530 #define MD_REG_LAST 66
1531 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1533 #define ST_REG_FIRST 67
1534 #define ST_REG_LAST 74
1535 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1537 #define RAP_REG_NUM 75
1539 #define AT_REGNUM (GP_REG_FIRST + 1)
1540 #define HI_REGNUM (MD_REG_FIRST + 0)
1541 #define LO_REGNUM (MD_REG_FIRST + 1)
1542 #define HILO_REGNUM (MD_REG_FIRST + 2)
1544 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1545 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1546 should be used instead. */
1547 #define FPSW_REGNUM ST_REG_FIRST
1549 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1550 #define M16_REG_P(REGNO) \
1551 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1552 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1553 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1554 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1556 /* Return number of consecutive hard regs needed starting at reg REGNO
1557 to hold something of mode MODE.
1558 This is ordinarily the length in words of a value of mode MODE
1559 but can be less for certain modes in special long registers.
1561 On the MIPS, all general registers are one word long. Except on
1562 the R4000 with the FR bit set, the floating point uses register
1563 pairs, with the second register not being allocable. */
1565 #define HARD_REGNO_NREGS(REGNO, MODE) \
1566 (! FP_REG_P (REGNO) \
1567 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1568 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1570 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1571 MODE. In 32 bit mode, require that DImode and DFmode be in even
1572 registers. For DImode, this makes some of the insns easier to
1573 write, since you don't have to worry about a DImode value in
1574 registers 3 & 4, producing a result in 4 & 5.
1576 To make the code simpler HARD_REGNO_MODE_OK now just references an
1577 array built in override_options. Because machmodes.h is not yet
1578 included before this file is processed, the MODE bound can't be
1581 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1583 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1584 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1586 /* Value is 1 if it is a good idea to tie two pseudo registers
1587 when one has mode MODE1 and one has mode MODE2.
1588 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1589 for any hard reg, then this must be 0 for correct output. */
1590 #define MODES_TIEABLE_P(MODE1, MODE2) \
1591 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1592 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1593 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1594 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1596 /* MIPS pc is not overloaded on a register. */
1597 /* #define PC_REGNUM xx */
1599 /* Register to use for pushing function arguments. */
1600 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1602 /* Offset from the stack pointer to the first available location. Use
1603 the default value zero. */
1604 /* #define STACK_POINTER_OFFSET 0 */
1606 /* Base register for access to local variables of the function. We
1607 pretend that the frame pointer is $1, and then eliminate it to
1608 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1609 a fixed register, and will not be used for anything else. */
1610 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1612 /* $30 is not available on the mips16, so we use $17 as the frame
1614 #define HARD_FRAME_POINTER_REGNUM \
1615 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1617 /* Value should be nonzero if functions must have frame pointers.
1618 Zero means the frame pointer need not be set up (and parms
1619 may be accessed via the stack pointer) in functions that seem suitable.
1620 This is computed in `reload', in reload1.c. */
1621 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1623 /* Base register for access to arguments of the function. */
1624 #define ARG_POINTER_REGNUM GP_REG_FIRST
1626 /* Fake register that holds the address on the stack of the
1627 current function's return address. */
1628 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1630 /* Register in which static-chain is passed to a function. */
1631 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1633 /* If the structure value address is passed in a register, then
1634 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1635 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1637 /* If the structure value address is not passed in a register, define
1638 `STRUCT_VALUE' as an expression returning an RTX for the place
1639 where the address is passed. If it returns 0, the address is
1640 passed as an "invisible" first argument. */
1641 #define STRUCT_VALUE 0
1643 /* Mips registers used in prologue/epilogue code when the stack frame
1644 is larger than 32K bytes. These registers must come from the
1645 scratch register set, and not used for passing and returning
1646 arguments and any other information used in the calling sequence
1647 (such as pic). Must start at 12, since t0/t3 are parameter passing
1648 registers in the 64 bit ABI. */
1650 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1651 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1653 /* Define this macro if it is as good or better to call a constant
1654 function address than to call an address kept in a register. */
1655 #define NO_FUNCTION_CSE 1
1657 /* Define this macro if it is as good or better for a function to
1658 call itself with an explicit address than to call an address
1659 kept in a register. */
1660 #define NO_RECURSIVE_FUNCTION_CSE 1
1662 /* The register number of the register used to address a table of
1663 static data addresses in memory. In some cases this register is
1664 defined by a processor's "application binary interface" (ABI).
1665 When this macro is defined, RTL is generated for this register
1666 once, as with the stack pointer and frame pointer registers. If
1667 this macro is not defined, it is up to the machine-dependent
1668 files to allocate such a register (if necessary). */
1669 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1671 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1673 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1674 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1675 isn't always called for static inline functions. */
1676 #define INIT_EXPANDERS \
1678 embedded_pic_fnaddr_rtx = NULL; \
1679 mips16_gp_pseudo_rtx = NULL; \
1682 /* Define the classes of registers for register constraints in the
1683 machine description. Also define ranges of constants.
1685 One of the classes must always be named ALL_REGS and include all hard regs.
1686 If there is more than one class, another class must be named NO_REGS
1687 and contain no registers.
1689 The name GENERAL_REGS must be the name of a class (or an alias for
1690 another name such as ALL_REGS). This is the class of registers
1691 that is allowed by "g" or "r" in a register constraint.
1692 Also, registers outside this class are allocated only when
1693 instructions express preferences for them.
1695 The classes must be numbered in nondecreasing order; that is,
1696 a larger-numbered class must never be contained completely
1697 in a smaller-numbered class.
1699 For any two classes, it is very desirable that there be another
1700 class that represents their union. */
1704 NO_REGS, /* no registers in set */
1705 M16_NA_REGS, /* mips16 regs not used to pass args */
1706 M16_REGS, /* mips16 directly accessible registers */
1707 T_REG, /* mips16 T register ($24) */
1708 M16_T_REGS, /* mips16 registers plus T register */
1709 GR_REGS, /* integer registers */
1710 FP_REGS, /* floating point registers */
1711 HI_REG, /* hi register */
1712 LO_REG, /* lo register */
1713 HILO_REG, /* hilo register pair for 64 bit mode mult */
1714 MD_REGS, /* multiply/divide registers (hi/lo) */
1715 ST_REGS, /* status registers (fp status) */
1716 ALL_REGS, /* all registers */
1717 LIM_REG_CLASSES /* max value + 1 */
1720 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1722 #define GENERAL_REGS GR_REGS
1724 /* An initializer containing the names of the register classes as C
1725 string constants. These names are used in writing some of the
1728 #define REG_CLASS_NAMES \
1745 /* An initializer containing the contents of the register classes,
1746 as integers which are bit masks. The Nth integer specifies the
1747 contents of class N. The way the integer MASK is interpreted is
1748 that register R is in the class if `MASK & (1 << R)' is 1.
1750 When the machine has more than 32 registers, an integer does not
1751 suffice. Then the integers are replaced by sub-initializers,
1752 braced groupings containing several integers. Each
1753 sub-initializer must be suitable as an initializer for the type
1754 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1756 #define REG_CLASS_CONTENTS \
1758 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1759 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1760 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1761 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1762 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1763 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1764 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1765 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1766 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1767 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1768 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1769 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1770 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1774 /* A C expression whose value is a register class containing hard
1775 register REGNO. In general there is more that one such class;
1776 choose a class which is "minimal", meaning that no smaller class
1777 also contains the register. */
1779 extern enum reg_class mips_regno_to_class[];
1781 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1783 /* A macro whose definition is the name of the class to which a
1784 valid base register must belong. A base register is one used in
1785 an address which is the register value plus a displacement. */
1787 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1789 /* A macro whose definition is the name of the class to which a
1790 valid index register must belong. An index register is one used
1791 in an address where its value is either multiplied by a scale
1792 factor or added to another register (as well as added to a
1795 #define INDEX_REG_CLASS NO_REGS
1797 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1798 registers explicitly used in the rtl to be used as spill registers
1799 but prevents the compiler from extending the lifetime of these
1802 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1804 /* This macro is used later on in the file. */
1805 #define GR_REG_CLASS_P(CLASS) \
1806 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1807 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1809 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1810 is the default value (allocate the registers in numeric order). We
1811 define it just so that we can override it for the mips16 target in
1812 ORDER_REGS_FOR_LOCAL_ALLOC. */
1814 #define REG_ALLOC_ORDER \
1815 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1816 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1817 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1818 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1819 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1822 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1823 to be rearranged based on a particular function. On the mips16, we
1824 want to allocate $24 (T_REG) before other registers for
1825 instructions for which it is possible. */
1827 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1829 /* REGISTER AND CONSTANT CLASSES */
1831 /* Get reg_class from a letter such as appears in the machine
1834 DEFINED REGISTER CLASSES:
1836 'd' General (aka integer) registers
1837 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1838 'y' General registers (in both mips16 and non mips16 mode)
1839 'e' mips16 non argument registers (M16_NA_REGS)
1840 't' mips16 temporary register ($24)
1841 'f' Floating point registers
1844 'x' Multiply/divide registers
1846 'z' FP Status register
1847 'b' All registers */
1849 extern enum reg_class mips_char_to_class[];
1851 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1853 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1854 string can be used to stand for particular ranges of immediate
1855 operands. This macro defines what the ranges are. C is the
1856 letter, and VALUE is a constant value. Return 1 if VALUE is
1857 in the range specified by C. */
1861 `I' is used for the range of constants an arithmetic insn can
1862 actually contain (16 bits signed integers).
1864 `J' is used for the range which is just zero (ie, $r0).
1866 `K' is used for the range of constants a logical insn can actually
1867 contain (16 bit zero-extended integers).
1869 `L' is used for the range of constants that be loaded with lui
1870 (ie, the bottom 16 bits are zero).
1872 `M' is used for the range of constants that take two words to load
1873 (ie, not matched by `I', `K', and `L').
1875 `N' is used for negative 16 bit constants other than -65536.
1877 `O' is a 15 bit signed integer.
1879 `P' is used for positive 16 bit constants. */
1881 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1882 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1884 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1885 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1886 : (C) == 'J' ? ((VALUE) == 0) \
1887 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1888 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1889 && (((VALUE) & ~2147483647) == 0 \
1890 || ((VALUE) & ~2147483647) == ~2147483647)) \
1891 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1892 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1893 && (((VALUE) & 0x0000ffff) != 0 \
1894 || (((VALUE) & ~2147483647) != 0 \
1895 && ((VALUE) & ~2147483647) != ~2147483647))) \
1896 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1897 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1898 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1901 /* Similar, but for floating constants, and defining letters G and H.
1902 Here VALUE is the CONST_DOUBLE rtx itself. */
1906 'G' : Floating point 0 */
1908 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1910 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1912 /* Letters in the range `Q' through `U' may be defined in a
1913 machine-dependent fashion to stand for arbitrary operand types.
1914 The machine description macro `EXTRA_CONSTRAINT' is passed the
1915 operand as its first argument and the constraint letter as its
1918 `Q' is for mips16 GP relative constants
1919 `R' is for memory references which take 1 word for the instruction.
1920 `S' is for references to extern items which are PIC for OSF/rose.
1921 `T' is for memory addresses that can be used to load two words. */
1923 #define EXTRA_CONSTRAINT(OP,CODE) \
1924 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
1925 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
1926 && mips16_gp_offset_p (OP)) \
1927 : (GET_CODE (OP) != MEM) ? FALSE \
1928 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1929 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1930 && HALF_PIC_ADDRESS_P (OP)) \
1933 /* Given an rtx X being reloaded into a reg required to be
1934 in class CLASS, return the class of reg to actually use.
1935 In general this is just CLASS; but on some machines
1936 in some cases it is preferable to use a more restrictive class. */
1938 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1939 ((CLASS) != ALL_REGS \
1940 ? (! TARGET_MIPS16 \
1942 : ((CLASS) != GR_REGS \
1945 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1946 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1947 ? (TARGET_SOFT_FLOAT \
1948 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1950 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1951 || GET_MODE (X) == VOIDmode) \
1952 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1955 /* Certain machines have the property that some registers cannot be
1956 copied to some other registers without using memory. Define this
1957 macro on those machines to be a C expression that is non-zero if
1958 objects of mode MODE in registers of CLASS1 can only be copied to
1959 registers of class CLASS2 by storing a register of CLASS1 into
1960 memory and loading that memory location into a register of CLASS2.
1962 Do not define this macro if its value would always be zero. */
1964 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1965 ((!TARGET_DEBUG_H_MODE \
1966 && GET_MODE_CLASS (MODE) == MODE_INT \
1967 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1968 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1969 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1970 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1971 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1973 /* The HI and LO registers can only be reloaded via the general
1974 registers. Condition code registers can only be loaded to the
1975 general registers, and from the floating point registers. */
1977 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1978 mips_secondary_reload_class (CLASS, MODE, X, 1)
1979 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1980 mips_secondary_reload_class (CLASS, MODE, X, 0)
1982 /* Not declared above, with the other functions, because enum
1983 reg_class is not declared yet. */
1984 extern enum reg_class mips_secondary_reload_class ();
1986 /* Return the maximum number of consecutive registers
1987 needed to represent mode MODE in a register of class CLASS. */
1989 #define CLASS_UNITS(mode, size) \
1990 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1992 #define CLASS_MAX_NREGS(CLASS, MODE) \
1993 ((CLASS) == FP_REGS \
1995 ? CLASS_UNITS (MODE, 8) \
1996 : 2 * CLASS_UNITS (MODE, 8)) \
1997 : CLASS_UNITS (MODE, UNITS_PER_WORD))
1999 /* If defined, this is a C expression whose value should be
2000 nonzero if the insn INSN has the effect of mysteriously
2001 clobbering the contents of hard register number REGNO. By
2002 "mysterious" we mean that the insn's RTL expression doesn't
2003 describe such an effect.
2005 If this macro is not defined, it means that no insn clobbers
2006 registers mysteriously. This is the usual situation; all else
2007 being equal, it is best for the RTL expression to show all the
2010 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
2013 /* Stack layout; function entry, exit and calling. */
2015 /* Define this if pushing a word on the stack
2016 makes the stack pointer a smaller address. */
2017 #define STACK_GROWS_DOWNWARD
2019 /* Define this if the nominal address of the stack frame
2020 is at the high-address end of the local variables;
2021 that is, each additional local variable allocated
2022 goes at a more negative offset in the frame. */
2023 /* #define FRAME_GROWS_DOWNWARD */
2025 /* Offset within stack frame to start allocating local variables at.
2026 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2027 first local allocated. Otherwise, it is the offset to the BEGINNING
2028 of the first local allocated. */
2029 #define STARTING_FRAME_OFFSET \
2030 (current_function_outgoing_args_size \
2031 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2033 /* Offset from the stack pointer register to an item dynamically
2034 allocated on the stack, e.g., by `alloca'.
2036 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2037 length of the outgoing arguments. The default is correct for most
2038 machines. See `function.c' for details.
2040 The MIPS ABI states that functions which dynamically allocate the
2041 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2042 we are trying to create a second frame pointer to the function, so
2043 allocate some stack space to make it happy.
2045 However, the linker currently complains about linking any code that
2046 dynamically allocates stack space, and there seems to be a bug in
2047 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2050 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2051 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2052 ? 4*UNITS_PER_WORD \
2053 : current_function_outgoing_args_size)
2056 /* The return address for the current frame is in r31 is this is a leaf
2057 function. Otherwise, it is on the stack. It is at a variable offset
2058 from sp/fp/ap, so we define a fake hard register rap which is a
2059 poiner to the return address on the stack. This always gets eliminated
2060 during reload to be either the frame pointer or the stack pointer plus
2063 /* ??? This definition fails for leaf functions. There is currently no
2064 general solution for this problem. */
2066 /* ??? There appears to be no way to get the return address of any previous
2067 frame except by disassembling instructions in the prologue/epilogue.
2068 So currently we support only the current frame. */
2070 #define RETURN_ADDR_RTX(count, frame) \
2072 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2075 /* Structure to be filled in by compute_frame_size with register
2076 save masks, and offsets for the current function. */
2078 struct mips_frame_info
2080 long total_size; /* # bytes that the entire frame takes up */
2081 long var_size; /* # bytes that variables take up */
2082 long args_size; /* # bytes that outgoing arguments take up */
2083 long extra_size; /* # bytes of extra gunk */
2084 int gp_reg_size; /* # bytes needed to store gp regs */
2085 int fp_reg_size; /* # bytes needed to store fp regs */
2086 long mask; /* mask of saved gp registers */
2087 long fmask; /* mask of saved fp registers */
2088 long gp_save_offset; /* offset from vfp to store gp registers */
2089 long fp_save_offset; /* offset from vfp to store fp registers */
2090 long gp_sp_offset; /* offset from new sp to store gp registers */
2091 long fp_sp_offset; /* offset from new sp to store fp registers */
2092 int initialized; /* != 0 if frame size already calculated */
2093 int num_gp; /* number of gp registers saved */
2094 int num_fp; /* number of fp registers saved */
2095 long insns_len; /* length of insns; mips16 only */
2098 extern struct mips_frame_info current_frame_info;
2100 /* If defined, this macro specifies a table of register pairs used to
2101 eliminate unneeded registers that point into the stack frame. If
2102 it is not defined, the only elimination attempted by the compiler
2103 is to replace references to the frame pointer with references to
2106 The definition of this macro is a list of structure
2107 initializations, each of which specifies an original and
2108 replacement register.
2110 On some machines, the position of the argument pointer is not
2111 known until the compilation is completed. In such a case, a
2112 separate hard register must be used for the argument pointer.
2113 This register can be eliminated by replacing it with either the
2114 frame pointer or the argument pointer, depending on whether or not
2115 the frame pointer has been eliminated.
2117 In this case, you might specify:
2118 #define ELIMINABLE_REGS \
2119 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2120 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2121 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2123 Note that the elimination of the argument pointer with the stack
2124 pointer is specified first since that is the preferred elimination.
2126 The eliminations to $17 are only used on the mips16. See the
2127 definition of HARD_FRAME_POINTER_REGNUM. */
2129 #define ELIMINABLE_REGS \
2130 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2131 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2132 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2133 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2134 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2135 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2136 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2137 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2138 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2140 /* A C expression that returns non-zero if the compiler is allowed to
2141 try to replace register number FROM-REG with register number
2142 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2143 defined, and will usually be the constant 1, since most of the
2144 cases preventing register elimination are things that the compiler
2145 already knows about.
2147 When not in mips16 and mips64, we can always eliminate to the
2148 frame pointer. We can eliminate to the stack pointer unless
2149 a frame pointer is needed. In mips16 mode, we need a frame
2150 pointer for a large frame; otherwise, reload may be unable
2151 to compute the address of a local variable, since there is
2152 no way to add a large constant to the stack pointer
2153 without using a temporary register.
2155 In mips16, for some instructions (eg lwu), we can't eliminate the
2156 frame pointer for the stack pointer. These instructions are
2157 only generated in TARGET_64BIT mode.
2160 #define CAN_ELIMINATE(FROM, TO) \
2161 ((TO) == HARD_FRAME_POINTER_REGNUM \
2162 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2163 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2164 && (! TARGET_MIPS16 \
2165 || compute_frame_size (get_frame_size ()) < 32768)))
2167 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2168 specifies the initial difference between the specified pair of
2169 registers. This macro must be defined if `ELIMINABLE_REGS' is
2172 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2173 { compute_frame_size (get_frame_size ()); \
2174 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2175 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2176 (OFFSET) = - current_function_outgoing_args_size; \
2177 else if ((FROM) == FRAME_POINTER_REGNUM) \
2179 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2180 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2181 (OFFSET) = (current_frame_info.total_size \
2182 - current_function_outgoing_args_size \
2183 - ((mips_abi != ABI_32 && mips_abi != ABI_EABI) \
2184 ? current_function_pretend_args_size \
2186 else if ((FROM) == ARG_POINTER_REGNUM) \
2187 (OFFSET) = (current_frame_info.total_size \
2188 - ((mips_abi != ABI_32 && mips_abi != ABI_EABI) \
2189 ? current_function_pretend_args_size \
2191 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2192 so we must add 4 bytes to the offset to get the right value. */ \
2193 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2194 (OFFSET) = current_frame_info.gp_sp_offset \
2195 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2196 * (BYTES_BIG_ENDIAN != 0)); \
2199 /* If we generate an insn to push BYTES bytes,
2200 this says how many the stack pointer really advances by.
2201 On the vax, sp@- in a byte insn really pushes a word. */
2203 /* #define PUSH_ROUNDING(BYTES) 0 */
2205 /* If defined, the maximum amount of space required for outgoing
2206 arguments will be computed and placed into the variable
2207 `current_function_outgoing_args_size'. No space will be pushed
2208 onto the stack for each call; instead, the function prologue
2209 should increase the stack frame size by this amount.
2211 It is not proper to define both `PUSH_ROUNDING' and
2212 `ACCUMULATE_OUTGOING_ARGS'. */
2213 #define ACCUMULATE_OUTGOING_ARGS
2215 /* Offset from the argument pointer register to the first argument's
2216 address. On some machines it may depend on the data type of the
2219 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2220 the first argument's address.
2222 On the MIPS, we must skip the first argument position if we are
2223 returning a structure or a union, to account for its address being
2224 passed in $4. However, at the current time, this produces a compiler
2225 that can't bootstrap, so comment it out for now. */
2228 #define FIRST_PARM_OFFSET(FNDECL) \
2230 && TREE_TYPE (FNDECL) != 0 \
2231 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2232 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2233 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2237 #define FIRST_PARM_OFFSET(FNDECL) 0
2240 /* When a parameter is passed in a register, stack space is still
2241 allocated for it. For the MIPS, stack space must be allocated, cf
2242 Asm Lang Prog Guide page 7-8.
2244 BEWARE that some space is also allocated for non existing arguments
2245 in register. In case an argument list is of form GF used registers
2246 are a0 (a2,a3), but we should push over a1... */
2248 #define REG_PARM_STACK_SPACE(FNDECL) \
2249 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2251 /* Define this if it is the responsibility of the caller to
2252 allocate the area reserved for arguments passed in registers.
2253 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2254 of this macro is to determine whether the space is included in
2255 `current_function_outgoing_args_size'. */
2256 #define OUTGOING_REG_PARM_STACK_SPACE
2258 /* Align stack frames on 64 bits (Double Word ). */
2259 #ifndef STACK_BOUNDARY
2260 #define STACK_BOUNDARY 64
2263 /* Make sure 4 words are always allocated on the stack. */
2265 #ifndef STACK_ARGS_ADJUST
2266 #define STACK_ARGS_ADJUST(SIZE) \
2268 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2269 SIZE.constant = 4 * UNITS_PER_WORD; \
2274 /* A C expression that should indicate the number of bytes of its
2275 own arguments that a function pops on returning, or 0
2276 if the function pops no arguments and the caller must therefore
2277 pop them all after the function returns.
2279 FUNDECL is the declaration node of the function (as a tree).
2281 FUNTYPE is a C variable whose value is a tree node that
2282 describes the function in question. Normally it is a node of
2283 type `FUNCTION_TYPE' that describes the data type of the function.
2284 From this it is possible to obtain the data types of the value
2285 and arguments (if known).
2287 When a call to a library function is being considered, FUNTYPE
2288 will contain an identifier node for the library function. Thus,
2289 if you need to distinguish among various library functions, you
2290 can do so by their names. Note that "library function" in this
2291 context means a function used to perform arithmetic, whose name
2292 is known specially in the compiler and was not mentioned in the
2293 C code being compiled.
2295 STACK-SIZE is the number of bytes of arguments passed on the
2296 stack. If a variable number of bytes is passed, it is zero, and
2297 argument popping will always be the responsibility of the
2298 calling function. */
2300 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2303 /* Symbolic macros for the registers used to return integer and floating
2306 #define GP_RETURN (GP_REG_FIRST + 2)
2307 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2309 /* Symbolic macros for the first/last argument registers. */
2311 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2312 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2313 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2314 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2316 #define MAX_ARGS_IN_REGISTERS 4
2318 /* Define how to find the value returned by a library function
2319 assuming the value has mode MODE. Because we define
2320 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2321 PROMOTE_MODE does. */
2323 #define LIBCALL_VALUE(MODE) \
2325 ((GET_MODE_CLASS (MODE) != MODE_INT \
2326 || GET_MODE_SIZE (MODE) >= 4) \
2329 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2330 && (! TARGET_SINGLE_FLOAT \
2331 || GET_MODE_SIZE (MODE) <= 4)) \
2335 /* Define how to find the value returned by a function.
2336 VALTYPE is the data type of the value (as a tree).
2337 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2338 otherwise, FUNC is 0. */
2340 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2343 /* 1 if N is a possible register number for a function value.
2344 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2345 Currently, R2 and F0 are only implemented here (C has no complex type) */
2347 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2349 /* 1 if N is a possible register number for function argument passing.
2350 We have no FP argument registers when soft-float. When FP registers
2351 are 32 bits, we can't directly reference the odd numbered ones. */
2353 #define FUNCTION_ARG_REGNO_P(N) \
2354 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2355 || ((! TARGET_SOFT_FLOAT \
2356 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2357 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2358 && ! fixed_regs[N]))
2360 /* A C expression which can inhibit the returning of certain function
2361 values in registers, based on the type of value. A nonzero value says
2362 to return the function value in memory, just as large structures are
2363 always returned. Here TYPE will be a C expression of type
2364 `tree', representing the data type of the value.
2366 Note that values of mode `BLKmode' must be explicitly
2367 handled by this macro. Also, the option `-fpcc-struct-return'
2368 takes effect regardless of this macro. On most systems, it is
2369 possible to leave the macro undefined; this causes a default
2370 definition to be used, whose value is the constant 1 for BLKmode
2371 values, and 0 otherwise.
2373 GCC normally converts 1 byte structures into chars, 2 byte
2374 structs into shorts, and 4 byte structs into ints, and returns
2375 them this way. Defining the following macro overrides this,
2376 to give us MIPS cc compatibility. */
2378 #define RETURN_IN_MEMORY(TYPE) \
2379 (TYPE_MODE (TYPE) == BLKmode)
2381 /* A code distinguishing the floating point format of the target
2382 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2383 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2385 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2388 /* Define a data type for recording info about an argument list
2389 during the scan of that argument list. This data type should
2390 hold all necessary information about the function itself
2391 and about the args processed so far, enough to enable macros
2392 such as FUNCTION_ARG to determine where the next arg should go.
2394 On the mips16, we need to keep track of which floating point
2395 arguments were passed in general registers, but would have been
2396 passed in the FP regs if this were a 32 bit function, so that we
2397 can move them to the FP regs if we wind up calling a 32 bit
2398 function. We record this information in fp_code, encoded in base
2399 four. A zero digit means no floating point argument, a one digit
2400 means an SFmode argument, and a two digit means a DFmode argument,
2401 and a three digit is not used. The low order digit is the first
2402 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2403 an SFmode argument. ??? A more sophisticated approach will be
2404 needed if MIPS_ABI != ABI_32. */
2406 typedef struct mips_args {
2407 int gp_reg_found; /* whether a gp register was found yet */
2408 int arg_number; /* argument number */
2409 int arg_words; /* # total words the arguments take */
2410 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2411 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2412 int fp_code; /* Mode of FP arguments (mips16) */
2413 int num_adjusts; /* number of adjustments made */
2414 /* Adjustments made to args pass in regs. */
2415 /* ??? The size is doubled to work around a
2416 bug in the code that sets the adjustments
2418 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2421 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2422 for a call to a function whose data type is FNTYPE.
2423 For a library call, FNTYPE is 0.
2427 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2428 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2430 /* Update the data in CUM to advance over an argument
2431 of mode MODE and data type TYPE.
2432 (TYPE is null for libcalls where that information may not be available.) */
2434 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2435 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2437 /* Determine where to put an argument to a function.
2438 Value is zero to push the argument on the stack,
2439 or a hard register in which to store the argument.
2441 MODE is the argument's machine mode.
2442 TYPE is the data type of the argument (as a tree).
2443 This is null for libcalls where that information may
2445 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2446 the preceding args and about the function being called.
2447 NAMED is nonzero if this argument is a named parameter
2448 (otherwise it is an extra parameter matching an ellipsis). */
2450 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2451 function_arg( &CUM, MODE, TYPE, NAMED)
2453 /* For an arg passed partly in registers and partly in memory,
2454 this is the number of registers used.
2455 For args passed entirely in registers or entirely in memory, zero. */
2457 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2458 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2460 /* If defined, a C expression that gives the alignment boundary, in
2461 bits, of an argument with the specified mode and type. If it is
2462 not defined, `PARM_BOUNDARY' is used for all arguments. */
2464 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2466 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2468 : TYPE_ALIGN(TYPE)) \
2469 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2471 : GET_MODE_ALIGNMENT(MODE)))
2474 /* This macro generates the assembly code for function entry.
2475 FILE is a stdio stream to output the code to.
2476 SIZE is an int: how many units of temporary storage to allocate.
2477 Refer to the array `regs_ever_live' to determine which registers
2478 to save; `regs_ever_live[I]' is nonzero if register number I
2479 is ever used in the function. This macro is responsible for
2480 knowing which registers should not be saved even if used. */
2482 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2484 /* This macro generates the assembly code for function exit,
2485 on machines that need it. If FUNCTION_EPILOGUE is not defined
2486 then individual return instructions are generated for each
2487 return statement. Args are same as for FUNCTION_PROLOGUE. */
2489 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2491 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2493 #define MUST_SAVE_REGISTER(regno) \
2494 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2495 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2496 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2498 /* ALIGN FRAMES on double word boundaries */
2499 #ifndef MIPS_STACK_ALIGN
2500 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2504 /* Output assembler code to FILE to increment profiler label # LABELNO
2505 for profiling a function entry. */
2507 #define FUNCTION_PROFILER(FILE, LABELNO) \
2509 if (TARGET_MIPS16) \
2510 sorry ("mips16 function profiling"); \
2511 fprintf (FILE, "\t.set\tnoreorder\n"); \
2512 fprintf (FILE, "\t.set\tnoat\n"); \
2513 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2514 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2515 fprintf (FILE, "\tjal\t_mcount\n"); \
2517 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2518 TARGET_64BIT ? "dsubu" : "subu", \
2519 reg_names[STACK_POINTER_REGNUM], \
2520 reg_names[STACK_POINTER_REGNUM], \
2521 Pmode == DImode ? 16 : 8); \
2522 fprintf (FILE, "\t.set\treorder\n"); \
2523 fprintf (FILE, "\t.set\tat\n"); \
2526 /* Define this macro if the code for function profiling should come
2527 before the function prologue. Normally, the profiling code comes
2530 /* #define PROFILE_BEFORE_PROLOGUE */
2532 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2533 the stack pointer does not matter. The value is tested only in
2534 functions that have frame pointers.
2535 No definition is equivalent to always zero. */
2537 #define EXIT_IGNORE_STACK 1
2540 /* A C statement to output, on the stream FILE, assembler code for a
2541 block of data that contains the constant parts of a trampoline.
2542 This code should not include a label--the label is taken care of
2545 #define TRAMPOLINE_TEMPLATE(STREAM) \
2547 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2548 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2549 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2550 if (Pmode == DImode) \
2552 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2553 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2557 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2558 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2560 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2561 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2562 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2563 if (Pmode == DImode) \
2565 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2566 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2570 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2571 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2575 /* A C expression for the size in bytes of the trampoline, as an
2578 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2580 /* Alignment required for trampolines, in bits. */
2582 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2584 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2585 program and data caches. */
2587 #ifndef CACHE_FLUSH_FUNC
2588 #define CACHE_FLUSH_FUNC "_flush_cache"
2591 /* A C statement to initialize the variable parts of a trampoline.
2592 ADDR is an RTX for the address of the trampoline; FNADDR is an
2593 RTX for the address of the nested function; STATIC_CHAIN is an
2594 RTX for the static chain value that should be passed to the
2595 function when it is called. */
2597 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2600 if (Pmode == DImode) \
2602 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2603 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2607 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2608 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2611 /* Flush both caches. We need to flush the data cache in case \
2612 the system has a write-back cache. */ \
2613 /* ??? Should check the return value for errors. */ \
2614 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, CACHE_FLUSH_FUNC), \
2615 0, VOIDmode, 3, addr, Pmode, \
2616 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2617 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2620 /* Addressing modes, and classification of registers for them. */
2622 /* #define HAVE_POST_INCREMENT */
2623 /* #define HAVE_POST_DECREMENT */
2625 /* #define HAVE_PRE_DECREMENT */
2626 /* #define HAVE_PRE_INCREMENT */
2628 /* These assume that REGNO is a hard or pseudo reg number.
2629 They give nonzero only if REGNO is a hard reg of the suitable class
2630 or a pseudo reg currently allocated to a suitable hard reg.
2631 These definitions are NOT overridden anywhere. */
2633 #define BASE_REG_P(regno, mode) \
2635 ? (M16_REG_P (regno) \
2636 || (regno) == FRAME_POINTER_REGNUM \
2637 || (regno) == ARG_POINTER_REGNUM \
2638 || ((regno) == STACK_POINTER_REGNUM \
2639 && (GET_MODE_SIZE (mode) == 4 \
2640 || GET_MODE_SIZE (mode) == 8))) \
2643 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2644 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2647 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2648 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2650 #define REGNO_OK_FOR_INDEX_P(regno) 0
2651 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2652 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2654 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2655 and check its validity for a certain class.
2656 We have two alternate definitions for each of them.
2657 The usual definition accepts all pseudo regs; the other rejects them all.
2658 The symbol REG_OK_STRICT causes the latter definition to be used.
2660 Most source files want to accept pseudo regs in the hope that
2661 they will get allocated to the class that the insn wants them to be in.
2662 Some source files that are used after register allocation
2663 need to be strict. */
2665 #ifndef REG_OK_STRICT
2667 #define REG_OK_STRICT_P 0
2668 #define REG_OK_FOR_INDEX_P(X) 0
2669 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2670 GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
2674 #define REG_OK_STRICT_P 1
2675 #define REG_OK_FOR_INDEX_P(X) 0
2676 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2677 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
2682 /* Maximum number of registers that can appear in a valid memory address. */
2684 #define MAX_REGS_PER_ADDRESS 1
2686 /* A C compound statement with a conditional `goto LABEL;' executed
2687 if X (an RTX) is a legitimate memory address on the target
2688 machine for a memory operand of mode MODE.
2690 It usually pays to define several simpler macros to serve as
2691 subroutines for this one. Otherwise it may be too complicated
2694 This macro must exist in two variants: a strict variant and a
2695 non-strict one. The strict variant is used in the reload pass.
2696 It must be defined so that any pseudo-register that has not been
2697 allocated a hard register is considered a memory reference. In
2698 contexts where some kind of register is required, a
2699 pseudo-register with no hard register must be rejected.
2701 The non-strict variant is used in other passes. It must be
2702 defined to accept all pseudo-registers in every context where
2703 some kind of register is required.
2705 Compiler source files that want to use the strict variant of
2706 this macro define the macro `REG_OK_STRICT'. You should use an
2707 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2708 in that case and the non-strict variant otherwise.
2710 Typically among the subroutines used to define
2711 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2712 acceptable registers for various purposes (one for base
2713 registers, one for index registers, and so on). Then only these
2714 subroutine macros need have two variants; the higher levels of
2715 macros may be the same whether strict or not.
2717 Normally, constant addresses which are the sum of a `symbol_ref'
2718 and an integer are stored inside a `const' RTX to mark them as
2719 constant. Therefore, there is no need to recognize such sums
2720 specifically as legitimate addresses. Normally you would simply
2721 recognize any `const' as legitimate.
2723 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2724 constant sums that are not marked with `const'. It assumes
2725 that a naked `plus' indicates indexing. If so, then you *must*
2726 reject such naked constant sums as illegitimate addresses, so
2727 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2729 On some machines, whether a symbolic address is legitimate
2730 depends on the section that the address refers to. On these
2731 machines, define the macro `ENCODE_SECTION_INFO' to store the
2732 information into the `symbol_ref', and then check for it here.
2733 When you see a `const', you will have to look inside it to find
2734 the `symbol_ref' in order to determine the section. */
2737 #define GO_PRINTF(x) trace(x)
2738 #define GO_PRINTF2(x,y) trace(x,y)
2739 #define GO_DEBUG_RTX(x) debug_rtx(x)
2742 #define GO_PRINTF(x)
2743 #define GO_PRINTF2(x,y)
2744 #define GO_DEBUG_RTX(x)
2747 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2749 register rtx xinsn = (X); \
2751 if (TARGET_DEBUG_B_MODE) \
2753 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2754 (REG_OK_STRICT_P) ? "" : "not "); \
2755 GO_DEBUG_RTX (xinsn); \
2758 /* The mips16 can only use the stack pointer as a base register when \
2759 loading SImode or DImode values. */ \
2760 if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \
2763 if (CONSTANT_ADDRESS_P (xinsn) \
2764 && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \
2765 && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \
2768 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2770 register rtx xlow0 = XEXP (xinsn, 0); \
2771 register rtx xlow1 = XEXP (xinsn, 1); \
2773 if (GET_CODE (xlow0) == REG \
2774 && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \
2775 && mips_check_split (xlow1, MODE)) \
2779 if (GET_CODE (xinsn) == PLUS) \
2781 register rtx xplus0 = XEXP (xinsn, 0); \
2782 register rtx xplus1 = XEXP (xinsn, 1); \
2783 register enum rtx_code code0 = GET_CODE (xplus0); \
2784 register enum rtx_code code1 = GET_CODE (xplus1); \
2786 /* The mips16 can only use the stack pointer as a base register \
2787 when loading SImode or DImode values. */ \
2788 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \
2790 if (code1 == CONST_INT \
2791 && INTVAL (xplus1) >= -32768 \
2792 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2795 /* On the mips16, we represent GP relative offsets in RTL. \
2796 These are 16 bit signed values, and can serve as register \
2799 && mips16_gp_offset_p (xplus1)) \
2802 /* For some code sequences, you actually get better code by \
2803 pretending that the MIPS supports an address mode of a \
2804 constant address + a register, even though the real \
2805 machine doesn't support it. This is because the \
2806 assembler can use $r1 to load just the high 16 bits, add \
2807 in the register, and fold the low 16 bits into the memory \
2808 reference, whereas the compiler generates a 4 instruction \
2809 sequence. On the other hand, CSE is not as effective. \
2810 It would be a win to generate the lui directly, but the \
2811 MIPS assembler does not have syntax to generate the \
2812 appropriate relocation. */ \
2814 /* Also accept CONST_INT addresses here, so no else. */ \
2815 /* Reject combining an embedded PIC text segment reference \
2816 with a register. That requires an additional \
2818 /* ??? Reject combining an address with a register for the MIPS \
2819 64 bit ABI, because the SGI assembler can not handle this. */ \
2820 if (!TARGET_DEBUG_A_MODE \
2821 && (mips_abi == ABI_32 || mips_abi == ABI_EABI) \
2822 && CONSTANT_ADDRESS_P (xplus1) \
2823 && ! mips_split_addresses \
2824 && (!TARGET_EMBEDDED_PIC \
2826 || GET_CODE (XEXP (xplus1, 0)) != MINUS) \
2827 && !TARGET_MIPS16) \
2832 if (TARGET_DEBUG_B_MODE) \
2833 GO_PRINTF ("Not a legitimate address\n"); \
2837 /* A C expression that is 1 if the RTX X is a constant which is a
2838 valid address. This is defined to be the same as `CONSTANT_P (X)',
2839 but rejecting CONST_DOUBLE. */
2840 /* When pic, we must reject addresses of the form symbol+large int.
2841 This is because an instruction `sw $4,s+70000' needs to be converted
2842 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2843 assembler would use $at as a temp to load in the large offset. In this
2844 case $at is already in use. We convert such problem addresses to
2845 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2846 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2847 #define CONSTANT_ADDRESS_P(X) \
2848 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2849 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2850 || (GET_CODE (X) == CONST \
2851 && ! (flag_pic && pic_address_needs_scratch (X)) \
2852 && (mips_abi == ABI_32 || mips_abi == ABI_EABI))) \
2853 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2855 /* Define this, so that when PIC, reload won't try to reload invalid
2856 addresses which require two reload registers. */
2858 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2860 /* Nonzero if the constant value X is a legitimate general operand.
2861 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2863 At present, GAS doesn't understand li.[sd], so don't allow it
2864 to be generated at present. Also, the MIPS assembler does not
2865 grok li.d Infinity. */
2867 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2868 #define LEGITIMATE_CONSTANT_P(X) \
2869 ((GET_CODE (X) != CONST_DOUBLE \
2870 || mips_const_double_ok (X, GET_MODE (X))) \
2871 && ! (GET_CODE (X) == CONST \
2872 && mips_abi != ABI_32 && mips_abi != ABI_EABI) \
2873 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2875 /* A C compound statement that attempts to replace X with a valid
2876 memory address for an operand of mode MODE. WIN will be a C
2877 statement label elsewhere in the code; the macro definition may
2880 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2882 to avoid further processing if the address has become legitimate.
2884 X will always be the result of a call to `break_out_memory_refs',
2885 and OLDX will be the operand that was given to that function to
2888 The code generated by this macro should not alter the
2889 substructure of X. If it transforms X into a more legitimate
2890 form, it should assign X (which will always be a C variable) a
2893 It is not necessary for this macro to come up with a legitimate
2894 address. The compiler has standard ways of doing so in all
2895 cases. In fact, it is safe for this macro to do nothing. But
2896 often a machine-dependent strategy can generate better code.
2898 For the MIPS, transform:
2900 memory(X + <large int>)
2904 Y = <large int> & ~0x7fff;
2906 memory (Z + (<large int> & 0x7fff));
2908 This is for CSE to find several similar references, and only use one Z.
2910 When PIC, convert addresses of the form memory (symbol+large int) to
2911 memory (reg+large int). */
2914 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2916 register rtx xinsn = (X); \
2918 if (TARGET_DEBUG_B_MODE) \
2920 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2921 GO_DEBUG_RTX (xinsn); \
2924 if (mips_split_addresses && mips_check_split (X, MODE)) \
2926 /* ??? Is this ever executed? */ \
2927 X = gen_rtx (LO_SUM, Pmode, \
2928 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2932 if (GET_CODE (xinsn) == CONST \
2933 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2934 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2935 || (mips_abi != ABI_32 && mips_abi != ABI_EABI))) \
2937 rtx ptr_reg = gen_reg_rtx (Pmode); \
2938 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2940 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2942 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2943 if (SMALL_INT (constant)) \
2945 /* Otherwise we fall through so the code below will fix the \
2950 if (GET_CODE (xinsn) == PLUS) \
2952 register rtx xplus0 = XEXP (xinsn, 0); \
2953 register rtx xplus1 = XEXP (xinsn, 1); \
2954 register enum rtx_code code0 = GET_CODE (xplus0); \
2955 register enum rtx_code code1 = GET_CODE (xplus1); \
2957 if (code0 != REG && code1 == REG) \
2959 xplus0 = XEXP (xinsn, 1); \
2960 xplus1 = XEXP (xinsn, 0); \
2961 code0 = GET_CODE (xplus0); \
2962 code1 = GET_CODE (xplus1); \
2965 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
2966 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2968 rtx int_reg = gen_reg_rtx (Pmode); \
2969 rtx ptr_reg = gen_reg_rtx (Pmode); \
2971 emit_move_insn (int_reg, \
2972 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2974 emit_insn (gen_rtx (SET, VOIDmode, \
2976 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
2978 X = gen_rtx (PLUS, Pmode, ptr_reg, \
2979 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
2984 if (TARGET_DEBUG_B_MODE) \
2985 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
2989 /* A C statement or compound statement with a conditional `goto
2990 LABEL;' executed if memory address X (an RTX) can have different
2991 meanings depending on the machine mode of the memory reference it
2994 Autoincrement and autodecrement addresses typically have
2995 mode-dependent effects because the amount of the increment or
2996 decrement is the size of the operand being addressed. Some
2997 machines have other mode-dependent addresses. Many RISC machines
2998 have no mode-dependent addresses.
3000 You may assume that ADDR is a valid address for the machine. */
3002 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3005 /* Define this macro if references to a symbol must be treated
3006 differently depending on something about the variable or
3007 function named by the symbol (such as what section it is in).
3009 The macro definition, if any, is executed immediately after the
3010 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3011 The value of the rtl will be a `mem' whose address is a
3014 The usual thing for this macro to do is to a flag in the
3015 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3016 name string in the `symbol_ref' (if one bit is not enough
3019 The best way to modify the name string is by adding text to the
3020 beginning, with suitable punctuation to prevent any ambiguity.
3021 Allocate the new name in `saveable_obstack'. You will have to
3022 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3023 and output the name accordingly.
3025 You can also check the information stored in the `symbol_ref' in
3026 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3027 `PRINT_OPERAND_ADDRESS'.
3029 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3032 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3033 symbols which are not in the .text section.
3035 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3036 constants which are put in the .text section. We also record the
3037 total length of all such strings; this total is used to decide
3038 whether we need to split the constant table, and need not be
3039 precisely correct. */
3041 #define ENCODE_SECTION_INFO(DECL) \
3044 if (TARGET_MIPS16) \
3046 if (TREE_CODE (DECL) == STRING_CST \
3047 && ! flag_writable_strings) \
3049 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3050 mips_string_length += TREE_STRING_LENGTH (DECL); \
3053 if (TARGET_EMBEDDED_PIC) \
3055 if (TREE_CODE (DECL) == VAR_DECL) \
3056 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3057 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3058 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3059 else if (TREE_CODE (DECL) == STRING_CST \
3060 && ! flag_writable_strings) \
3061 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3063 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3066 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
3068 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3070 if (size > 0 && size <= mips_section_threshold) \
3071 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3074 else if (HALF_PIC_P ()) \
3076 HALF_PIC_ENCODE (DECL); \
3081 /* The mips16 wants the constant pool to be after the function,
3082 because the PC relative load instructions use unsigned offsets. */
3084 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3086 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3087 mips_string_length = 0;
3090 /* In mips16 mode, put most string constants after the function. */
3091 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3092 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3095 /* Specify the machine mode that this machine uses
3096 for the index in the tablejump instruction.
3097 ??? Using HImode in mips16 mode can cause overflow. However, the
3098 overflow is no more likely than the overflow in a branch
3099 instruction. Large functions can currently break in both ways. */
3100 #define CASE_VECTOR_MODE \
3101 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3103 /* Define as C expression which evaluates to nonzero if the tablejump
3104 instruction expects the table to contain offsets from the address of the
3106 Do not define this if the table should contain absolute addresses. */
3107 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3109 /* Specify the tree operation to be used to convert reals to integers. */
3110 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3112 /* This is the kind of divide that is easiest to do in the general case. */
3113 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3115 /* Define this as 1 if `char' should by default be signed; else as 0. */
3116 #ifndef DEFAULT_SIGNED_CHAR
3117 #define DEFAULT_SIGNED_CHAR 1
3120 /* Max number of bytes we can move from memory to memory
3121 in one reasonably fast instruction. */
3122 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3123 #define MAX_MOVE_MAX 8
3125 /* Define this macro as a C expression which is nonzero if
3126 accessing less than a word of memory (i.e. a `char' or a
3127 `short') is no faster than accessing a word of memory, i.e., if
3128 such access require more than one instruction or if there is no
3129 difference in cost between byte and (aligned) word loads.
3131 On RISC machines, it tends to generate better code to define
3132 this as 1, since it avoids making a QI or HI mode register. */
3133 #define SLOW_BYTE_ACCESS 1
3135 /* We assume that the store-condition-codes instructions store 0 for false
3136 and some other value for true. This is the value stored for true. */
3138 #define STORE_FLAG_VALUE 1
3140 /* Define this if zero-extension is slow (more than one real instruction). */
3141 #define SLOW_ZERO_EXTEND
3143 /* Define this to be nonzero if shift instructions ignore all but the low-order
3145 #define SHIFT_COUNT_TRUNCATED 1
3147 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3148 is done just by pretending it is already truncated. */
3149 /* In 64 bit mode, 32 bit instructions require that register values be properly
3150 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3151 converts a value >32 bits to a value <32 bits. */
3152 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3153 Something needs to be done about this. Perhaps not use any 32 bit
3154 instructions? Perhaps use PROMOTE_MODE? */
3155 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3156 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3158 /* Specify the machine mode that pointers have.
3159 After generation of rtl, the compiler makes no further distinction
3160 between pointers and any other objects of this machine mode. */
3163 #define Pmode (TARGET_LONG64 ? DImode : SImode)
3166 /* A function address in a call instruction
3167 is a word address (for indexing purposes)
3168 so give the MEM rtx a words's mode. */
3170 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3172 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3173 memset, instead of the BSD functions bcopy and bzero. */
3175 #if defined(MIPS_SYSV) || defined(OSF_OS)
3176 #define TARGET_MEM_FUNCTIONS
3180 /* A part of a C `switch' statement that describes the relative
3181 costs of constant RTL expressions. It must contain `case'
3182 labels for expression codes `const_int', `const', `symbol_ref',
3183 `label_ref' and `const_double'. Each case must ultimately reach
3184 a `return' statement to return the relative cost of the use of
3185 that kind of constant value in an expression. The cost may
3186 depend on the precise value of the constant, which is available
3187 for examination in X.
3189 CODE is the expression code--redundant, since it can be obtained
3190 with `GET_CODE (X)'. */
3192 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3194 if (! TARGET_MIPS16) \
3196 /* Always return 0, since we don't have different sized \
3197 instructions, hence different costs according to Richard \
3201 if ((OUTER_CODE) == SET) \
3203 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3205 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3206 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3207 return COSTS_N_INSNS (1); \
3209 return COSTS_N_INSNS (2); \
3211 /* A PLUS could be an address. We don't want to force an address \
3212 to use a register, so accept any signed 16 bit value without \
3214 if ((OUTER_CODE) == PLUS \
3215 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3217 /* A number between 1 and 8 inclusive is efficient for a shift. \
3218 Otherwise, we will need an extended instruction. */ \
3219 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3220 || (OUTER_CODE) == LSHIFTRT) \
3222 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3224 return COSTS_N_INSNS (1); \
3226 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3227 if ((OUTER_CODE) == XOR \
3228 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3230 /* We may be able to use slt or sltu for a comparison with a \
3231 signed 16 bit value. (The boundary conditions aren't quite \
3232 right, but this is just a heuristic anyhow.) */ \
3233 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3234 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3235 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3236 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3237 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3239 /* Equality comparisons with 0 are cheap. */ \
3240 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3241 && INTVAL (X) == 0) \
3244 /* Otherwise, work out the cost to load the value into a \
3246 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3247 return COSTS_N_INSNS (1); \
3248 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3249 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3250 return COSTS_N_INSNS (2); \
3252 return COSTS_N_INSNS (3); \
3255 return COSTS_N_INSNS (2); \
3259 rtx offset = const0_rtx; \
3260 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3262 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3264 /* Treat this like a signed 16 bit CONST_INT. */ \
3265 if ((OUTER_CODE) == PLUS) \
3267 else if ((OUTER_CODE) == SET) \
3268 return COSTS_N_INSNS (1); \
3270 return COSTS_N_INSNS (2); \
3273 if (GET_CODE (symref) == LABEL_REF) \
3274 return COSTS_N_INSNS (2); \
3276 if (GET_CODE (symref) != SYMBOL_REF) \
3277 return COSTS_N_INSNS (4); \
3279 /* let's be paranoid.... */ \
3280 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3281 return COSTS_N_INSNS (2); \
3283 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3287 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3289 case CONST_DOUBLE: \
3292 if (TARGET_MIPS16) \
3293 return COSTS_N_INSNS (4); \
3294 split_double (X, &high, &low); \
3295 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3296 || low == CONST0_RTX (GET_MODE (low))) \
3300 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3301 This can be used, for example, to indicate how costly a multiply
3302 instruction is. In writing this macro, you can use the construct
3303 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3305 This macro is optional; do not define it if the default cost
3306 assumptions are adequate for the target machine.
3308 If -mdebugd is used, change the multiply cost to 2, so multiply by
3309 a constant isn't converted to a series of shifts. This helps
3310 strength reduction, and also makes it easier to identify what the
3311 compiler is doing. */
3313 /* ??? Fix this to be right for the R8000. */
3314 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3317 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3318 if (simple_memory_operand (X, GET_MODE (X))) \
3319 return COSTS_N_INSNS (num_words); \
3321 return COSTS_N_INSNS (2*num_words); \
3325 return COSTS_N_INSNS (6); \
3328 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3333 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3334 return COSTS_N_INSNS (2); \
3341 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3342 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3348 enum machine_mode xmode = GET_MODE (X); \
3349 if (xmode == SFmode || xmode == DFmode) \
3350 return COSTS_N_INSNS (1); \
3352 return COSTS_N_INSNS (4); \
3358 enum machine_mode xmode = GET_MODE (X); \
3359 if (xmode == SFmode || xmode == DFmode) \
3361 if (mips_cpu == PROCESSOR_R3000 \
3362 || mips_cpu == PROCESSOR_R3900) \
3363 return COSTS_N_INSNS (2); \
3364 else if (mips_cpu == PROCESSOR_R6000) \
3365 return COSTS_N_INSNS (3); \
3367 return COSTS_N_INSNS (6); \
3370 if (xmode == DImode && !TARGET_64BIT) \
3371 return COSTS_N_INSNS (4); \
3377 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3384 enum machine_mode xmode = GET_MODE (X); \
3385 if (xmode == SFmode) \
3387 if (mips_cpu == PROCESSOR_R3000 \
3388 || mips_cpu == PROCESSOR_R3900 \
3389 || mips_cpu == PROCESSOR_R5000) \
3390 return COSTS_N_INSNS (4); \
3391 else if (mips_cpu == PROCESSOR_R6000) \
3392 return COSTS_N_INSNS (5); \
3394 return COSTS_N_INSNS (7); \
3397 if (xmode == DFmode) \
3399 if (mips_cpu == PROCESSOR_R3000 \
3400 || mips_cpu == PROCESSOR_R3900 \
3401 || mips_cpu == PROCESSOR_R5000) \
3402 return COSTS_N_INSNS (5); \
3403 else if (mips_cpu == PROCESSOR_R6000) \
3404 return COSTS_N_INSNS (6); \
3406 return COSTS_N_INSNS (8); \
3409 if (mips_cpu == PROCESSOR_R3000) \
3410 return COSTS_N_INSNS (12); \
3411 else if (mips_cpu == PROCESSOR_R3900) \
3412 return COSTS_N_INSNS (2); \
3413 else if (mips_cpu == PROCESSOR_R6000) \
3414 return COSTS_N_INSNS (17); \
3415 else if (mips_cpu == PROCESSOR_R5000) \
3416 return COSTS_N_INSNS (5); \
3418 return COSTS_N_INSNS (10); \
3424 enum machine_mode xmode = GET_MODE (X); \
3425 if (xmode == SFmode) \
3427 if (mips_cpu == PROCESSOR_R3000 \
3428 || mips_cpu == PROCESSOR_R3900) \
3429 return COSTS_N_INSNS (12); \
3430 else if (mips_cpu == PROCESSOR_R6000) \
3431 return COSTS_N_INSNS (15); \
3433 return COSTS_N_INSNS (23); \
3436 if (xmode == DFmode) \
3438 if (mips_cpu == PROCESSOR_R3000 \
3439 || mips_cpu == PROCESSOR_R3900) \
3440 return COSTS_N_INSNS (19); \
3441 else if (mips_cpu == PROCESSOR_R6000) \
3442 return COSTS_N_INSNS (16); \
3444 return COSTS_N_INSNS (36); \
3447 /* fall through */ \
3451 if (mips_cpu == PROCESSOR_R3000 \
3452 || mips_cpu == PROCESSOR_R3900) \
3453 return COSTS_N_INSNS (35); \
3454 else if (mips_cpu == PROCESSOR_R6000) \
3455 return COSTS_N_INSNS (38); \
3456 else if (mips_cpu == PROCESSOR_R5000) \
3457 return COSTS_N_INSNS (36); \
3459 return COSTS_N_INSNS (69); \
3462 /* A sign extend from SImode to DImode in 64 bit mode is often \
3463 zero instructions, because the result can often be used \
3464 directly by another instruction; we'll call it one. */ \
3465 if (TARGET_64BIT && GET_MODE (X) == DImode \
3466 && GET_MODE (XEXP (X, 0)) == SImode) \
3467 return COSTS_N_INSNS (1); \
3469 return COSTS_N_INSNS (2); \
3472 if (TARGET_64BIT && GET_MODE (X) == DImode \
3473 && GET_MODE (XEXP (X, 0)) == SImode) \
3474 return COSTS_N_INSNS (2); \
3476 return COSTS_N_INSNS (1);
3478 /* An expression giving the cost of an addressing mode that
3479 contains ADDRESS. If not defined, the cost is computed from the
3480 form of the ADDRESS expression and the `CONST_COSTS' values.
3482 For most CISC machines, the default cost is a good approximation
3483 of the true cost of the addressing mode. However, on RISC
3484 machines, all instructions normally have the same length and
3485 execution time. Hence all addresses will have equal costs.
3487 In cases where more than one form of an address is known, the
3488 form with the lowest cost will be used. If multiple forms have
3489 the same, lowest, cost, the one that is the most complex will be
3492 For example, suppose an address that is equal to the sum of a
3493 register and a constant is used twice in the same basic block.
3494 When this macro is not defined, the address will be computed in
3495 a register and memory references will be indirect through that
3496 register. On machines where the cost of the addressing mode
3497 containing the sum is no higher than that of a simple indirect
3498 reference, this will produce an additional instruction and
3499 possibly require an additional register. Proper specification
3500 of this macro eliminates this overhead for such machines.
3502 Similar use of this macro is made in strength reduction of loops.
3504 ADDRESS need not be valid as an address. In such a case, the
3505 cost is not relevant and can be any value; invalid addresses
3506 need not be assigned a different cost.
3508 On machines where an address involving more than one register is
3509 as cheap as an address computation involving only one register,
3510 defining `ADDRESS_COST' to reflect this can cause two registers
3511 to be live over a region of code where only one would have been
3512 if `ADDRESS_COST' were not defined in that manner. This effect
3513 should be considered in the definition of this macro.
3514 Equivalent costs should probably only be given to addresses with
3515 different numbers of registers on machines with lots of registers.
3517 This macro will normally either not be defined or be defined as
3520 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3522 /* A C expression for the cost of moving data from a register in
3523 class FROM to one in class TO. The classes are expressed using
3524 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3525 the default; other values are interpreted relative to that.
3527 It is not required that the cost always equal 2 when FROM is the
3528 same as TO; on some machines it is expensive to move between
3529 registers if they are not general registers.
3531 If reload sees an insn consisting of a single `set' between two
3532 hard registers, and if `REGISTER_MOVE_COST' applied to their
3533 classes returns a value of 2, reload does not check to ensure
3534 that the constraints of the insn are met. Setting a cost of
3535 other than 2 will allow reload to verify that the constraints are
3536 met. You should do this if the `movM' pattern's constraints do
3537 not allow such copying. */
3539 #define REGISTER_MOVE_COST(FROM, TO) \
3540 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3541 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3542 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3543 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3544 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3545 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3546 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3547 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3548 : (((FROM) == HI_REG || (FROM) == LO_REG \
3549 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3550 && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6 \
3551 : (((FROM) == HI_REG || (FROM) == LO_REG \
3552 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3553 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 8 : 6) \
3554 : (((TO) == HI_REG || (TO) == LO_REG \
3555 || (TO) == MD_REGS || (TO) == HILO_REG) \
3556 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3557 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3558 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3561 /* ??? Fix this to be right for the R8000. */
3562 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3563 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3564 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3566 /* Define if copies to/from condition code registers should be avoided.
3568 This is needed for the MIPS because reload_outcc is not complete;
3569 it needs to handle cases where the source is a general or another
3570 condition code register. */
3571 #define AVOID_CCMODE_COPIES
3573 /* A C expression for the cost of a branch instruction. A value of
3574 1 is the default; other values are interpreted relative to that. */
3576 /* ??? Fix this to be right for the R8000. */
3577 #define BRANCH_COST \
3579 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3582 /* A C statement (sans semicolon) to update the integer variable COST
3583 based on the relationship between INSN that is dependent on
3584 DEP_INSN through the dependence LINK. The default is to make no
3585 adjustment to COST. On the MIPS, ignore the cost of anti- and
3586 output-dependencies. */
3588 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3589 if (REG_NOTE_KIND (LINK) != 0) \
3590 (COST) = 0; /* Anti or output dependence. */
3592 /* Optionally define this if you have added predicates to
3593 `MACHINE.c'. This macro is called within an initializer of an
3594 array of structures. The first field in the structure is the
3595 name of a predicate and the second field is an array of rtl
3596 codes. For each predicate, list all rtl codes that can be in
3597 expressions matched by the predicate. The list should have a
3598 trailing comma. Here is an example of two entries in the list
3599 for a typical RISC machine:
3601 #define PREDICATE_CODES \
3602 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3603 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3605 Defining this macro does not affect the generated code (however,
3606 incorrect definitions that omit an rtl code that may be matched
3607 by the predicate can cause the compiler to malfunction).
3608 Instead, it allows the table built by `genrecog' to be more
3609 compact and efficient, thus speeding up the compiler. The most
3610 important predicates to include in the list specified by this
3611 macro are thoses used in the most insn patterns. */
3613 #define PREDICATE_CODES \
3614 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3615 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3616 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3617 {"reg_or_0_operand", { REG, CONST_INT, SUBREG }}, \
3618 {"small_int", { CONST_INT }}, \
3619 {"large_int", { CONST_INT }}, \
3620 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3621 {"const_float_1_operand", { CONST_DOUBLE }}, \
3622 {"simple_memory_operand", { MEM, SUBREG }}, \
3623 {"equality_op", { EQ, NE }}, \
3624 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3626 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3627 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3628 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3629 SYMBOL_REF, LABEL_REF, SUBREG, \
3631 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3632 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3633 MEM, SIGN_EXTEND }}, \
3634 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3635 {"se_reg_or_0_operand", { REG, CONST_INT, SUBREG, \
3637 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3639 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3641 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3642 SYMBOL_REF, LABEL_REF, SUBREG, \
3643 REG, SIGN_EXTEND }}, \
3644 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3645 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3646 CONST_DOUBLE, CONST }}, \
3647 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3648 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3652 /* If defined, a C statement to be executed just prior to the
3653 output of assembler code for INSN, to modify the extracted
3654 operands so they will be output differently.
3656 Here the argument OPVEC is the vector containing the operands
3657 extracted from INSN, and NOPERANDS is the number of elements of
3658 the vector which contain meaningful data for this insn. The
3659 contents of this vector are what will be used to convert the
3660 insn template into assembler code, so you can change the
3661 assembler output by changing the contents of the vector.
3663 We use it to check if the current insn needs a nop in front of it
3664 because of load delays, and also to update the delay slot
3667 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3668 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3671 /* Control the assembler format that we output. */
3673 /* Output at beginning of assembler file.
3674 If we are optimizing to use the global pointer, create a temporary
3675 file to hold all of the text stuff, and write it out to the end.
3676 This is needed because the MIPS assembler is evidently one pass,
3677 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3678 declaration when the code is processed, it generates a two
3679 instruction sequence. */
3681 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3683 /* Output to assembler file text saying following lines
3684 may contain character constants, extra white space, comments, etc. */
3686 #define ASM_APP_ON " #APP\n"
3688 /* Output to assembler file text saying following lines
3689 no longer contain unusual constructs. */
3691 #define ASM_APP_OFF " #NO_APP\n"
3693 /* How to refer to registers in assembler output.
3694 This sequence is indexed by compiler's hard-register-number (see above).
3696 In order to support the two different conventions for register names,
3697 we use the name of a table set up in mips.c, which is overwritten
3698 if -mrnames is used. */
3700 #define REGISTER_NAMES \
3702 &mips_reg_names[ 0][0], \
3703 &mips_reg_names[ 1][0], \
3704 &mips_reg_names[ 2][0], \
3705 &mips_reg_names[ 3][0], \
3706 &mips_reg_names[ 4][0], \
3707 &mips_reg_names[ 5][0], \
3708 &mips_reg_names[ 6][0], \
3709 &mips_reg_names[ 7][0], \
3710 &mips_reg_names[ 8][0], \
3711 &mips_reg_names[ 9][0], \
3712 &mips_reg_names[10][0], \
3713 &mips_reg_names[11][0], \
3714 &mips_reg_names[12][0], \
3715 &mips_reg_names[13][0], \
3716 &mips_reg_names[14][0], \
3717 &mips_reg_names[15][0], \
3718 &mips_reg_names[16][0], \
3719 &mips_reg_names[17][0], \
3720 &mips_reg_names[18][0], \
3721 &mips_reg_names[19][0], \
3722 &mips_reg_names[20][0], \
3723 &mips_reg_names[21][0], \
3724 &mips_reg_names[22][0], \
3725 &mips_reg_names[23][0], \
3726 &mips_reg_names[24][0], \
3727 &mips_reg_names[25][0], \
3728 &mips_reg_names[26][0], \
3729 &mips_reg_names[27][0], \
3730 &mips_reg_names[28][0], \
3731 &mips_reg_names[29][0], \
3732 &mips_reg_names[30][0], \
3733 &mips_reg_names[31][0], \
3734 &mips_reg_names[32][0], \
3735 &mips_reg_names[33][0], \
3736 &mips_reg_names[34][0], \
3737 &mips_reg_names[35][0], \
3738 &mips_reg_names[36][0], \
3739 &mips_reg_names[37][0], \
3740 &mips_reg_names[38][0], \
3741 &mips_reg_names[39][0], \
3742 &mips_reg_names[40][0], \
3743 &mips_reg_names[41][0], \
3744 &mips_reg_names[42][0], \
3745 &mips_reg_names[43][0], \
3746 &mips_reg_names[44][0], \
3747 &mips_reg_names[45][0], \
3748 &mips_reg_names[46][0], \
3749 &mips_reg_names[47][0], \
3750 &mips_reg_names[48][0], \
3751 &mips_reg_names[49][0], \
3752 &mips_reg_names[50][0], \
3753 &mips_reg_names[51][0], \
3754 &mips_reg_names[52][0], \
3755 &mips_reg_names[53][0], \
3756 &mips_reg_names[54][0], \
3757 &mips_reg_names[55][0], \
3758 &mips_reg_names[56][0], \
3759 &mips_reg_names[57][0], \
3760 &mips_reg_names[58][0], \
3761 &mips_reg_names[59][0], \
3762 &mips_reg_names[60][0], \
3763 &mips_reg_names[61][0], \
3764 &mips_reg_names[62][0], \
3765 &mips_reg_names[63][0], \
3766 &mips_reg_names[64][0], \
3767 &mips_reg_names[65][0], \
3768 &mips_reg_names[66][0], \
3769 &mips_reg_names[67][0], \
3770 &mips_reg_names[68][0], \
3771 &mips_reg_names[69][0], \
3772 &mips_reg_names[70][0], \
3773 &mips_reg_names[71][0], \
3774 &mips_reg_names[72][0], \
3775 &mips_reg_names[73][0], \
3776 &mips_reg_names[74][0], \
3777 &mips_reg_names[75][0], \
3780 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3781 So define this for it. */
3782 #define DEBUG_REGISTER_NAMES \
3784 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3785 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3786 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3787 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3788 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3789 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3790 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3791 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3792 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3793 "$fcc5","$fcc6","$fcc7","$rap" \
3796 /* If defined, a C initializer for an array of structures
3797 containing a name and a register number. This macro defines
3798 additional names for hard registers, thus allowing the `asm'
3799 option in declarations to refer to registers using alternate
3802 We define both names for the integer registers here. */
3804 #define ADDITIONAL_REGISTER_NAMES \
3806 { "$0", 0 + GP_REG_FIRST }, \
3807 { "$1", 1 + GP_REG_FIRST }, \
3808 { "$2", 2 + GP_REG_FIRST }, \
3809 { "$3", 3 + GP_REG_FIRST }, \
3810 { "$4", 4 + GP_REG_FIRST }, \
3811 { "$5", 5 + GP_REG_FIRST }, \
3812 { "$6", 6 + GP_REG_FIRST }, \
3813 { "$7", 7 + GP_REG_FIRST }, \
3814 { "$8", 8 + GP_REG_FIRST }, \
3815 { "$9", 9 + GP_REG_FIRST }, \
3816 { "$10", 10 + GP_REG_FIRST }, \
3817 { "$11", 11 + GP_REG_FIRST }, \
3818 { "$12", 12 + GP_REG_FIRST }, \
3819 { "$13", 13 + GP_REG_FIRST }, \
3820 { "$14", 14 + GP_REG_FIRST }, \
3821 { "$15", 15 + GP_REG_FIRST }, \
3822 { "$16", 16 + GP_REG_FIRST }, \
3823 { "$17", 17 + GP_REG_FIRST }, \
3824 { "$18", 18 + GP_REG_FIRST }, \
3825 { "$19", 19 + GP_REG_FIRST }, \
3826 { "$20", 20 + GP_REG_FIRST }, \
3827 { "$21", 21 + GP_REG_FIRST }, \
3828 { "$22", 22 + GP_REG_FIRST }, \
3829 { "$23", 23 + GP_REG_FIRST }, \
3830 { "$24", 24 + GP_REG_FIRST }, \
3831 { "$25", 25 + GP_REG_FIRST }, \
3832 { "$26", 26 + GP_REG_FIRST }, \
3833 { "$27", 27 + GP_REG_FIRST }, \
3834 { "$28", 28 + GP_REG_FIRST }, \
3835 { "$29", 29 + GP_REG_FIRST }, \
3836 { "$30", 30 + GP_REG_FIRST }, \
3837 { "$31", 31 + GP_REG_FIRST }, \
3838 { "$sp", 29 + GP_REG_FIRST }, \
3839 { "$fp", 30 + GP_REG_FIRST }, \
3840 { "at", 1 + GP_REG_FIRST }, \
3841 { "v0", 2 + GP_REG_FIRST }, \
3842 { "v1", 3 + GP_REG_FIRST }, \
3843 { "a0", 4 + GP_REG_FIRST }, \
3844 { "a1", 5 + GP_REG_FIRST }, \
3845 { "a2", 6 + GP_REG_FIRST }, \
3846 { "a3", 7 + GP_REG_FIRST }, \
3847 { "t0", 8 + GP_REG_FIRST }, \
3848 { "t1", 9 + GP_REG_FIRST }, \
3849 { "t2", 10 + GP_REG_FIRST }, \
3850 { "t3", 11 + GP_REG_FIRST }, \
3851 { "t4", 12 + GP_REG_FIRST }, \
3852 { "t5", 13 + GP_REG_FIRST }, \
3853 { "t6", 14 + GP_REG_FIRST }, \
3854 { "t7", 15 + GP_REG_FIRST }, \
3855 { "s0", 16 + GP_REG_FIRST }, \
3856 { "s1", 17 + GP_REG_FIRST }, \
3857 { "s2", 18 + GP_REG_FIRST }, \
3858 { "s3", 19 + GP_REG_FIRST }, \
3859 { "s4", 20 + GP_REG_FIRST }, \
3860 { "s5", 21 + GP_REG_FIRST }, \
3861 { "s6", 22 + GP_REG_FIRST }, \
3862 { "s7", 23 + GP_REG_FIRST }, \
3863 { "t8", 24 + GP_REG_FIRST }, \
3864 { "t9", 25 + GP_REG_FIRST }, \
3865 { "k0", 26 + GP_REG_FIRST }, \
3866 { "k1", 27 + GP_REG_FIRST }, \
3867 { "gp", 28 + GP_REG_FIRST }, \
3868 { "sp", 29 + GP_REG_FIRST }, \
3869 { "fp", 30 + GP_REG_FIRST }, \
3870 { "ra", 31 + GP_REG_FIRST }, \
3871 { "$sp", 29 + GP_REG_FIRST }, \
3872 { "$fp", 30 + GP_REG_FIRST } \
3875 /* Define results of standard character escape sequences. */
3876 #define TARGET_BELL 007
3877 #define TARGET_BS 010
3878 #define TARGET_TAB 011
3879 #define TARGET_NEWLINE 012
3880 #define TARGET_VT 013
3881 #define TARGET_FF 014
3882 #define TARGET_CR 015
3884 /* A C compound statement to output to stdio stream STREAM the
3885 assembler syntax for an instruction operand X. X is an RTL
3888 CODE is a value that can be used to specify one of several ways
3889 of printing the operand. It is used when identical operands
3890 must be printed differently depending on the context. CODE
3891 comes from the `%' specification that was used to request
3892 printing of the operand. If the specification was just `%DIGIT'
3893 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3894 is the ASCII code for LTR.
3896 If X is a register, this macro should print the register's name.
3897 The names can be found in an array `reg_names' whose type is
3898 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3900 When the machine description has a specification `%PUNCT' (a `%'
3901 followed by a punctuation character), this macro is called with
3902 a null pointer for X and the punctuation character for CODE.
3904 See mips.c for the MIPS specific codes. */
3906 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3908 /* A C expression which evaluates to true if CODE is a valid
3909 punctuation character for use in the `PRINT_OPERAND' macro. If
3910 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3911 punctuation characters (except for the standard one, `%') are
3912 used in this way. */
3914 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3916 /* A C compound statement to output to stdio stream STREAM the
3917 assembler syntax for an instruction operand that is a memory
3918 reference whose address is ADDR. ADDR is an RTL expression.
3920 On some machines, the syntax for a symbolic address depends on
3921 the section that the address refers to. On these machines,
3922 define the macro `ENCODE_SECTION_INFO' to store the information
3923 into the `symbol_ref', and then check for it here. */
3925 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3928 /* A C statement, to be executed after all slot-filler instructions
3929 have been output. If necessary, call `dbr_sequence_length' to
3930 determine the number of slots filled in a sequence (zero if not
3931 currently outputting a sequence), to decide how many no-ops to
3932 output, or whatever.
3934 Don't define this macro if it has nothing to do, but it is
3935 helpful in reading assembly output if the extent of the delay
3936 sequence is made explicit (e.g. with white space).
3938 Note that output routines for instructions with delay slots must
3939 be prepared to deal with not being output as part of a sequence
3940 (i.e. when the scheduling pass is not run, or when no slot
3941 fillers could be found.) The variable `final_sequence' is null
3942 when not processing a sequence, otherwise it contains the
3943 `sequence' rtx being output. */
3945 #define DBR_OUTPUT_SEQEND(STREAM) \
3948 if (set_nomacro > 0 && --set_nomacro == 0) \
3949 fputs ("\t.set\tmacro\n", STREAM); \
3951 if (set_noreorder > 0 && --set_noreorder == 0) \
3952 fputs ("\t.set\treorder\n", STREAM); \
3954 dslots_jump_filled++; \
3955 fputs ("\n", STREAM); \
3960 /* How to tell the debugger about changes of source files. Note, the
3961 mips ECOFF format cannot deal with changes of files inside of
3962 functions, which means the output of parser generators like bison
3963 is generally not debuggable without using the -l switch. Lose,
3964 lose, lose. Silicon graphics seems to want all .file's hardwired
3967 #ifndef SET_FILE_NUMBER
3968 #define SET_FILE_NUMBER() ++num_source_filenames
3971 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3972 mips_output_filename (STREAM, NAME)
3974 /* This is defined so that it can be overridden in iris6.h. */
3975 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3978 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3979 output_quoted_string (STREAM, NAME); \
3980 fputs ("\n", STREAM); \
3984 /* This is how to output a note the debugger telling it the line number
3985 to which the following sequence of instructions corresponds.
3986 Silicon graphics puts a label after each .loc. */
3988 #ifndef LABEL_AFTER_LOC
3989 #define LABEL_AFTER_LOC(STREAM)
3992 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3993 mips_output_lineno (STREAM, LINE)
3995 /* The MIPS implementation uses some labels for its own purpose. The
3996 following lists what labels are created, and are all formed by the
3997 pattern $L[a-z].*. The machine independent portion of GCC creates
3998 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4000 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4001 $Lb[0-9]+ Begin blocks for MIPS debug support
4002 $Lc[0-9]+ Label for use in s<xx> operation.
4003 $Le[0-9]+ End blocks for MIPS debug support
4004 $Lp\..+ Half-pic labels. */
4006 /* This is how to output the definition of a user-level label named NAME,
4007 such as the label on a static function or variable NAME.
4009 If we are optimizing the gp, remember that this label has been put
4010 out, so we know not to emit an .extern for it in mips_asm_file_end.
4011 We use one of the common bits in the IDENTIFIER tree node for this,
4012 since those bits seem to be unused, and we don't have any method
4013 of getting the decl nodes from the name. */
4015 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4017 assemble_name (STREAM, NAME); \
4018 fputs (":\n", STREAM); \
4022 /* A C statement (sans semicolon) to output to the stdio stream
4023 STREAM any text necessary for declaring the name NAME of an
4024 initialized variable which is being defined. This macro must
4025 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4026 The argument DECL is the `VAR_DECL' tree node representing the
4029 If this macro is not defined, then the variable name is defined
4030 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4032 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4035 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4036 HALF_PIC_DECLARE (NAME); \
4041 /* This is how to output a command to make the user-level label named NAME
4042 defined for reference from other files. */
4044 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4046 fputs ("\t.globl\t", STREAM); \
4047 assemble_name (STREAM, NAME); \
4048 fputs ("\n", STREAM); \
4051 /* This says how to define a global common symbol. */
4053 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
4054 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
4056 /* This says how to define a local common symbol (ie, not visible to
4059 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4060 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4063 /* This says how to output an external. It would be possible not to
4064 output anything and let undefined symbol become external. However
4065 the assembler uses length information on externals to allocate in
4066 data/sdata bss/sbss, thereby saving exec time. */
4068 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4069 mips_output_external(STREAM,DECL,NAME)
4071 /* This says what to print at the end of the assembly file */
4072 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4075 /* This is how to declare a function name. The actual work of
4076 emitting the label is moved to function_prologue, so that we can
4077 get the line number correctly emitted before the .ent directive,
4078 and after any .file directives.
4080 Also, switch files if we are optimizing the global pointer. */
4082 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4084 extern FILE *asm_out_text_file; \
4085 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4087 STREAM = asm_out_text_file; \
4088 /* ??? text_section gets called too soon. If the previous \
4089 function is in a special section and we're not, we have \
4090 to switch back to the text section. We can't call \
4091 text_section again as gcc thinks we're already there. */ \
4092 /* ??? See varasm.c. There are other things that get output \
4093 too early, like alignment (before we've switched STREAM). */ \
4094 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4095 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4098 HALF_PIC_DECLARE (NAME); \
4101 /* This is how to output an internal numbered label where
4102 PREFIX is the class of label and NUM is the number within the class. */
4104 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4105 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4107 /* This is how to store into the string LABEL
4108 the symbol_ref name of an internal numbered label where
4109 PREFIX is the class of label and NUM is the number within the class.
4110 This is suitable for output with `assemble_name'. */
4112 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4113 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4115 /* This is how to output an assembler line defining a `double' constant. */
4117 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4118 mips_output_double (STREAM, VALUE)
4121 /* This is how to output an assembler line defining a `float' constant. */
4123 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4124 mips_output_float (STREAM, VALUE)
4127 /* This is how to output an assembler line defining an `int' constant. */
4129 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4131 fprintf (STREAM, "\t.word\t"); \
4132 output_addr_const (STREAM, (VALUE)); \
4133 fprintf (STREAM, "\n"); \
4136 /* Likewise for 64 bit, `char' and `short' constants. */
4138 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4142 fprintf (STREAM, "\t.dword\t"); \
4143 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4144 /* We can't use 'X' for negative numbers, because then we won't \
4145 get the right value for the upper 32 bits. */ \
4146 output_addr_const (STREAM, VALUE); \
4148 /* We must use 'X', because otherwise LONG_MIN will print as \
4149 a number that the Irix 6 assembler won't accept. */ \
4150 print_operand (STREAM, VALUE, 'X'); \
4151 fprintf (STREAM, "\n"); \
4155 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4156 UNITS_PER_WORD, 1); \
4157 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4158 UNITS_PER_WORD, 1); \
4162 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4164 fprintf (STREAM, "\t.half\t"); \
4165 output_addr_const (STREAM, (VALUE)); \
4166 fprintf (STREAM, "\n"); \
4169 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4171 fprintf (STREAM, "\t.byte\t"); \
4172 output_addr_const (STREAM, (VALUE)); \
4173 fprintf (STREAM, "\n"); \
4176 /* This is how to output an assembler line for a numeric constant byte. */
4178 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4179 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4181 /* This is how to output an element of a case-vector that is absolute. */
4183 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4184 fprintf (STREAM, "\t%s\t%sL%d\n", \
4185 Pmode == DImode ? ".dword" : ".word", \
4186 LOCAL_LABEL_PREFIX, \
4189 /* This is how to output an element of a case-vector that is relative.
4190 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4191 TARGET_EMBEDDED_PIC). */
4193 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4195 if (TARGET_MIPS16) \
4196 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4197 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4198 else if (TARGET_EMBEDDED_PIC) \
4199 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4200 Pmode == DImode ? ".dword" : ".word", \
4201 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4202 else if (mips_abi == ABI_32) \
4203 fprintf (STREAM, "\t%s\t%sL%d\n", \
4204 Pmode == DImode ? ".gpdword" : ".gpword", \
4205 LOCAL_LABEL_PREFIX, VALUE); \
4207 fprintf (STREAM, "\t%s\t%sL%d\n", \
4208 Pmode == DImode ? ".dword" : ".word", \
4209 LOCAL_LABEL_PREFIX, VALUE); \
4212 /* When generating embedded PIC or mips16 code we want to put the jump
4213 table in the .text section. In all other cases, we want to put the
4214 jump table in the .rdata section. Unfortunately, we can't use
4215 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4216 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4217 section if appropriate. */
4218 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4220 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4221 function_section (current_function_decl); \
4222 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4225 /* This is how to output an assembler line
4226 that says to advance the location counter
4227 to a multiple of 2**LOG bytes. */
4229 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4230 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4232 /* This is how to output an assembler line to advance the location
4233 counter by SIZE bytes. */
4235 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4236 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4238 /* This is how to output a string. */
4239 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4241 register int i, c, len = (LEN), cur_pos = 17; \
4242 register unsigned char *string = (unsigned char *)(STRING); \
4243 fprintf ((STREAM), "\t.ascii\t\""); \
4244 for (i = 0; i < len; i++) \
4246 register int c = string[i]; \
4252 putc ('\\', (STREAM)); \
4253 putc (c, (STREAM)); \
4257 case TARGET_NEWLINE: \
4258 fputs ("\\n", (STREAM)); \
4260 && (((c = string[i+1]) >= '\040' && c <= '~') \
4261 || c == TARGET_TAB)) \
4262 cur_pos = 32767; /* break right here */ \
4268 fputs ("\\t", (STREAM)); \
4273 fputs ("\\f", (STREAM)); \
4278 fputs ("\\b", (STREAM)); \
4283 fputs ("\\r", (STREAM)); \
4288 if (c >= ' ' && c < 0177) \
4290 putc (c, (STREAM)); \
4295 fprintf ((STREAM), "\\%03o", c); \
4300 if (cur_pos > 72 && i+1 < len) \
4303 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4306 fprintf ((STREAM), "\"\n"); \
4309 /* Handle certain cpp directives used in header files on sysV. */
4310 #define SCCS_DIRECTIVE
4312 /* Output #ident as a in the read-only data section. */
4313 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4316 int size = strlen (p) + 1; \
4318 assemble_string (p, size); \
4321 /* Default to -G 8 */
4322 #ifndef MIPS_DEFAULT_GVALUE
4323 #define MIPS_DEFAULT_GVALUE 8
4326 /* Define the strings to put out for each section in the object file. */
4327 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4328 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4329 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4330 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4331 #define READONLY_DATA_SECTION rdata_section
4332 #define SMALL_DATA_SECTION sdata_section
4334 /* What other sections we support other than the normal .data/.text. */
4336 #define EXTRA_SECTIONS in_sdata, in_rdata
4338 /* Define the additional functions to select our additional sections. */
4340 /* on the MIPS it is not a good idea to put constants in the text
4341 section, since this defeats the sdata/data mechanism. This is
4342 especially true when -O is used. In this case an effort is made to
4343 address with faster (gp) register relative addressing, which can
4344 only get at sdata and sbss items (there is no stext !!) However,
4345 if the constant is too large for sdata, and it's readonly, it
4346 will go into the .rdata section. */
4348 #define EXTRA_SECTION_FUNCTIONS \
4352 if (in_section != in_sdata) \
4354 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4355 in_section = in_sdata; \
4362 if (in_section != in_rdata) \
4364 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4365 in_section = in_rdata; \
4369 /* Given a decl node or constant node, choose the section to output it in
4370 and select that section. */
4372 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4374 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4377 /* Store in OUTPUT a string (made with alloca) containing
4378 an assembler-name for a local static variable named NAME.
4379 LABELNO is an integer which is different for each call. */
4381 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4382 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4383 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4385 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4388 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4389 TARGET_64BIT ? "dsubu" : "subu", \
4390 reg_names[STACK_POINTER_REGNUM], \
4391 reg_names[STACK_POINTER_REGNUM], \
4392 TARGET_64BIT ? "sd" : "sw", \
4394 reg_names[STACK_POINTER_REGNUM]); \
4398 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4401 if (! set_noreorder) \
4402 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4404 dslots_load_total++; \
4405 dslots_load_filled++; \
4406 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4407 TARGET_64BIT ? "ld" : "lw", \
4409 reg_names[STACK_POINTER_REGNUM], \
4410 TARGET_64BIT ? "daddu" : "addu", \
4411 reg_names[STACK_POINTER_REGNUM], \
4412 reg_names[STACK_POINTER_REGNUM]); \
4414 if (! set_noreorder) \
4415 fprintf (STREAM, "\t.set\treorder\n"); \
4419 /* Define the parentheses used to group arithmetic operations
4420 in assembler code. */
4422 #define ASM_OPEN_PAREN "("
4423 #define ASM_CLOSE_PAREN ")"
4425 /* How to start an assembler comment.
4426 The leading space is important (the mips native assembler requires it). */
4427 #ifndef ASM_COMMENT_START
4428 #define ASM_COMMENT_START " #"
4432 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4433 and mips-tdump.c to print them out.
4435 These must match the corresponding definitions in gdb/mipsread.c.
4436 Unfortunately, gcc and gdb do not currently share any directories. */
4438 #define CODE_MASK 0x8F300
4439 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4440 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4441 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4444 /* Default definitions for size_t and ptrdiff_t. */
4447 #define NO_BUILTIN_SIZE_TYPE
4448 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4451 #ifndef PTRDIFF_TYPE
4452 #define NO_BUILTIN_PTRDIFF_TYPE
4453 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4456 /* See mips_expand_prologue's use of loadgp for when this should be
4459 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && mips_abi != ABI_32)
4461 /* In mips16 mode, we need to look through the function to check for
4462 PC relative loads that are out of range. */
4463 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4465 /* We need to use a special set of functions to handle hard floating
4466 point code in mips16 mode. */
4468 #ifndef INIT_SUBTARGET_OPTABS
4469 #define INIT_SUBTARGET_OPTABS
4472 #define INIT_TARGET_OPTABS \
4475 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4476 INIT_SUBTARGET_OPTABS; \
4479 add_optab->handlers[(int) SFmode].libfunc = \
4480 gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3"); \
4481 sub_optab->handlers[(int) SFmode].libfunc = \
4482 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3"); \
4483 smul_optab->handlers[(int) SFmode].libfunc = \
4484 gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3"); \
4485 flodiv_optab->handlers[(int) SFmode].libfunc = \
4486 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3"); \
4488 eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2"); \
4489 nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2"); \
4490 gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2"); \
4491 gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2"); \
4492 ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2"); \
4493 lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2"); \
4495 floatsisf_libfunc = \
4496 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf"); \
4498 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi"); \
4500 if (TARGET_DOUBLE_FLOAT) \
4502 add_optab->handlers[(int) DFmode].libfunc = \
4503 gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3"); \
4504 sub_optab->handlers[(int) DFmode].libfunc = \
4505 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3"); \
4506 smul_optab->handlers[(int) DFmode].libfunc = \
4507 gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3"); \
4508 flodiv_optab->handlers[(int) DFmode].libfunc = \
4509 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3"); \
4511 extendsfdf2_libfunc = \
4512 gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2"); \
4513 truncdfsf2_libfunc = \
4514 gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2"); \
4517 gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2"); \
4519 gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2"); \
4521 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2"); \
4523 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2"); \
4525 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2"); \
4527 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2"); \
4529 floatsidf_libfunc = \
4530 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf"); \
4532 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi"); \
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