1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-5, 1996 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern int flag_omit_frame_pointer;
32 extern int frame_pointer_needed;
33 extern char *language_string;
34 extern int may_call_alloca;
36 extern char **save_argv;
37 extern int target_flags;
38 extern char *version_string;
40 /* MIPS external variables defined in mips.c. */
44 CMP_SI, /* compare four byte integers */
45 CMP_DI, /* compare eight byte integers */
46 CMP_SF, /* compare single precision floats */
47 CMP_DF, /* compare double precision floats */
48 CMP_MAX /* max comparison type */
51 /* types of delay slot */
53 DELAY_NONE, /* no delay slot */
54 DELAY_LOAD, /* load from memory delay */
55 DELAY_HILO, /* move from/to hi/lo registers */
56 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
59 /* Which processor to schedule for. Since there is no difference between
60 a R2000 and R3000 in terms of the scheduler, we collapse them into
61 just an R3000. The elements of the enumeration must match exactly
62 the cpu attribute in the mips.md machine description. */
77 /* Recast the cpu class to be the cpu attribute. */
78 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
80 /* Which ABI to use. This is only used by the Irix 6 port currently. */
88 #ifndef MIPS_ABI_DEFAULT
89 /* We define this away so that there is no extra runtime cost if the target
90 doesn't support multiple ABIs. */
91 #define mips_abi ABI_32
93 extern enum mips_abi_type mips_abi;
96 /* Whether to emit abicalls code sequences or not. */
98 enum mips_abicalls_type {
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
109 enum block_move_type {
110 BLOCK_MOVE_NORMAL, /* generate complete block move */
111 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
112 BLOCK_MOVE_LAST /* generate just the last store */
115 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
116 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
117 extern char *current_function_file; /* filename current function is in */
118 extern int num_source_filenames; /* current .file # */
119 extern int inside_function; /* != 0 if inside of a function */
120 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
121 extern int file_in_function_warning; /* warning given about .file in func */
122 extern int sdb_label_count; /* block start/end next label # */
123 extern int sdb_begin_function_line; /* Starting Line of current function */
124 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
125 extern int g_switch_value; /* value of the -G xx switch */
126 extern int g_switch_set; /* whether -G xx was passed. */
127 extern int sym_lineno; /* sgi next label # for each stmt */
128 extern int set_noreorder; /* # of nested .set noreorder's */
129 extern int set_nomacro; /* # of nested .set nomacro's */
130 extern int set_noat; /* # of nested .set noat's */
131 extern int set_volatile; /* # of nested .set volatile's */
132 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
133 extern int mips_dbx_regno[]; /* Map register # to debug register # */
134 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
135 extern enum cmp_type branch_type; /* what type of branch to use */
136 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
137 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
138 extern int mips_isa; /* architectural level */
139 extern char *mips_cpu_string; /* for -mcpu=<xxx> */
140 extern char *mips_isa_string; /* for -mips{1,2,3,4} */
141 extern char *mips_abi_string; /* for -misa={32,n32,64} */
142 extern int mips_split_addresses; /* perform high/lo_sum support */
143 extern int dslots_load_total; /* total # load related delay slots */
144 extern int dslots_load_filled; /* # filled load delay slots */
145 extern int dslots_jump_total; /* total # jump related delay slots */
146 extern int dslots_jump_filled; /* # filled jump delay slots */
147 extern int dslots_number_nops; /* # of nops needed by previous insn */
148 extern int num_refs[3]; /* # 1/2/3 word references */
149 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
150 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
151 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
152 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
153 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
155 /* Functions within mips.c that we reference. */
157 extern void abort_with_insn ();
158 extern int arith32_operand ();
159 extern int arith_operand ();
160 extern int cmp_op ();
161 extern long compute_frame_size ();
162 extern int epilogue_reg_mentioned_p ();
163 extern void expand_block_move ();
164 extern int equality_op ();
165 extern void final_prescan_insn ();
166 extern struct rtx_def * function_arg ();
167 extern void function_arg_advance ();
168 extern int function_arg_partial_nregs ();
169 extern void function_epilogue ();
170 extern void function_prologue ();
171 extern void gen_conditional_branch ();
172 extern void gen_conditional_move ();
173 extern struct rtx_def * gen_int_relational ();
174 extern void init_cumulative_args ();
175 extern int large_int ();
176 extern int mips_address_cost ();
177 extern void mips_asm_file_end ();
178 extern void mips_asm_file_start ();
179 extern int mips_const_double_ok ();
180 extern void mips_count_memory_refs ();
181 extern int mips_debugger_offset ();
182 extern void mips_declare_object ();
183 extern int mips_epilogue_delay_slots ();
184 extern void mips_expand_epilogue ();
185 extern void mips_expand_prologue ();
186 extern int mips_check_split ();
187 extern char *mips_fill_delay_slot ();
188 extern char *mips_move_1word ();
189 extern char *mips_move_2words ();
190 extern void mips_output_double ();
191 extern int mips_output_external ();
192 extern void mips_output_float ();
193 extern void mips_output_filename ();
194 extern void mips_output_lineno ();
195 extern char *output_block_move ();
196 extern void override_options ();
197 extern int pc_or_label_operand ();
198 extern void print_operand_address ();
199 extern void print_operand ();
200 extern void print_options ();
201 extern int reg_or_0_operand ();
202 extern int simple_epilogue_p ();
203 extern int simple_memory_operand ();
204 extern int small_int ();
206 extern int uns_arith_operand ();
207 extern struct rtx_def * embedded_pic_offset ();
209 /* Recognition functions that return if a condition is true. */
210 extern int address_operand ();
211 extern int const_double_operand ();
212 extern int const_int_operand ();
213 extern int general_operand ();
214 extern int immediate_operand ();
215 extern int memory_address_p ();
216 extern int memory_operand ();
217 extern int nonimmediate_operand ();
218 extern int nonmemory_operand ();
219 extern int register_operand ();
220 extern int scratch_operand ();
221 extern int move_operand ();
223 /* Functions to change what output section we are using. */
224 extern void data_section ();
225 extern void rdata_section ();
226 extern void readonly_data_section ();
227 extern void sdata_section ();
228 extern void text_section ();
230 /* Functions in the rest of the compiler that we reference. */
231 extern void abort_with_insn ();
232 extern void debug_rtx ();
233 extern void fatal_io_error ();
234 extern int get_frame_size ();
235 extern int offsettable_address_p ();
236 extern void output_address ();
237 extern char *permalloc ();
238 extern int reg_mentioned_p ();
240 /* Functions in the standard library that we reference. */
242 extern char *getenv ();
243 extern char *mktemp ();
246 /* Stubs for half-pic support if not OSF/1 reference platform. */
249 #define HALF_PIC_P() 0
250 #define HALF_PIC_NUMBER_PTRS 0
251 #define HALF_PIC_NUMBER_REFS 0
252 #define HALF_PIC_ENCODE(DECL)
253 #define HALF_PIC_DECLARE(NAME)
254 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
255 #define HALF_PIC_ADDRESS_P(X) 0
256 #define HALF_PIC_PTR(X) X
257 #define HALF_PIC_FINISH(STREAM)
261 /* Run-time compilation parameters selecting different hardware subsets. */
263 /* Macros used in the machine description to test the flags. */
265 /* Bits for real switches */
266 #define MASK_INT64 0x00000001 /* ints are 64 bits */
267 #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
268 #define MASK_UNUSED 0x00000004
269 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
270 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
271 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
272 #define MASK_STATS 0x00000040 /* print statistics to stderr */
273 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
274 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
275 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
276 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
277 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
278 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
279 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
280 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
281 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
282 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
283 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
284 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
285 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
287 /* Dummy switches used only in spec's*/
288 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
290 /* Debug switches, not documented */
291 #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */
292 #define MASK_DEBUG_A 0x20000000 /* don't allow <label>($reg) addrs */
293 #define MASK_DEBUG_B 0x10000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
294 #define MASK_DEBUG_C 0x08000000 /* don't expand seq, etc. */
295 #define MASK_DEBUG_D 0x04000000 /* don't do define_split's */
296 #define MASK_DEBUG_E 0x02000000 /* function_arg debug */
297 #define MASK_DEBUG_F 0x01000000 /* don't try to suppress load nop's */
298 #define MASK_DEBUG_G 0x00800000 /* don't support 64 bit arithmetic */
299 #define MASK_DEBUG_H 0x00400000 /* allow ints in FP registers */
300 #define MASK_DEBUG_I 0x00200000 /* unused */
301 #define MASK_DEBUG_J 0x00100000 /* unused */
303 /* r4000 64 bit sizes */
304 #define TARGET_INT64 (target_flags & MASK_INT64)
305 #define TARGET_LONG64 (target_flags & MASK_LONG64)
306 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
307 #define TARGET_64BIT (target_flags & MASK_64BIT)
309 /* Mips vs. GNU assembler */
310 #define TARGET_GAS (target_flags & MASK_GAS)
311 #define TARGET_UNIX_ASM (!TARGET_GAS)
312 #define TARGET_MIPS_AS TARGET_UNIX_ASM
315 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
316 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
317 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
318 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
319 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
320 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
321 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
322 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
323 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
324 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
325 #define TARGET_DEBUG_J_MODE (target_flags & MASK_DEBUG_J)
327 /* Reg. Naming in .s ($21 vs. $a0) */
328 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
330 /* Optimize for Sdata/Sbss */
331 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
333 /* print program statistics */
334 #define TARGET_STATS (target_flags & MASK_STATS)
336 /* call memcpy instead of inline code */
337 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
339 /* .abicalls, etc from Pyramid V.4 */
340 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
342 /* OSF pic references to externs */
343 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
345 /* software floating point */
346 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
347 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
349 /* always call through a register */
350 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
352 /* generate embedded PIC code;
354 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
356 /* for embedded systems, optimize for
357 reduced RAM space instead of for
359 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
361 /* generate big endian code. */
362 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
364 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
365 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
367 #define TARGET_MAD (target_flags & MASK_MAD)
369 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
371 /* Macro to define tables used to set the flags.
372 This is a list in braces of pairs in braces,
373 each pair being { "NAME", VALUE }
374 where VALUE is the bits to set or minus the bits to clear.
375 An empty string NAME is used to identify the default VALUE. */
377 #define TARGET_SWITCHES \
379 {"int64", MASK_INT64 | MASK_LONG64}, \
380 {"long64", MASK_LONG64}, \
381 {"mips-as", -MASK_GAS}, \
383 {"rnames", MASK_NAME_REGS}, \
384 {"no-rnames", -MASK_NAME_REGS}, \
385 {"gpOPT", MASK_GPOPT}, \
386 {"gpopt", MASK_GPOPT}, \
387 {"no-gpOPT", -MASK_GPOPT}, \
388 {"no-gpopt", -MASK_GPOPT}, \
389 {"stats", MASK_STATS}, \
390 {"no-stats", -MASK_STATS}, \
391 {"memcpy", MASK_MEMCPY}, \
392 {"no-memcpy", -MASK_MEMCPY}, \
393 {"mips-tfile", MASK_MIPS_TFILE}, \
394 {"no-mips-tfile", -MASK_MIPS_TFILE}, \
395 {"soft-float", MASK_SOFT_FLOAT}, \
396 {"hard-float", -MASK_SOFT_FLOAT}, \
397 {"fp64", MASK_FLOAT64}, \
398 {"fp32", -MASK_FLOAT64}, \
399 {"gp64", MASK_64BIT}, \
400 {"gp32", -MASK_64BIT}, \
401 {"abicalls", MASK_ABICALLS}, \
402 {"no-abicalls", -MASK_ABICALLS}, \
403 {"half-pic", MASK_HALF_PIC}, \
404 {"no-half-pic", -MASK_HALF_PIC}, \
405 {"long-calls", MASK_LONG_CALLS}, \
406 {"no-long-calls", -MASK_LONG_CALLS}, \
407 {"embedded-pic", MASK_EMBEDDED_PIC}, \
408 {"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
409 {"embedded-data", MASK_EMBEDDED_DATA}, \
410 {"no-embedded-data", -MASK_EMBEDDED_DATA}, \
411 {"eb", MASK_BIG_ENDIAN}, \
412 {"el", -MASK_BIG_ENDIAN}, \
413 {"single-float", MASK_SINGLE_FLOAT}, \
414 {"double-float", -MASK_SINGLE_FLOAT}, \
416 {"no-mad", -MASK_MAD}, \
417 {"fix4300", MASK_4300_MUL_FIX}, \
418 {"no-fix4300", -MASK_4300_MUL_FIX}, \
419 {"4650", MASK_MAD | MASK_SINGLE_FLOAT}, \
420 {"debug", MASK_DEBUG}, \
421 {"debuga", MASK_DEBUG_A}, \
422 {"debugb", MASK_DEBUG_B}, \
423 {"debugc", MASK_DEBUG_C}, \
424 {"debugd", MASK_DEBUG_D}, \
425 {"debuge", MASK_DEBUG_E}, \
426 {"debugf", MASK_DEBUG_F}, \
427 {"debugg", MASK_DEBUG_G}, \
428 {"debugh", MASK_DEBUG_H}, \
429 {"debugi", MASK_DEBUG_I}, \
430 {"debugj", MASK_DEBUG_J}, \
431 {"", (TARGET_DEFAULT \
432 | TARGET_CPU_DEFAULT \
433 | TARGET_ENDIAN_DEFAULT)} \
436 /* Default target_flags if no switches are specified */
438 #ifndef TARGET_DEFAULT
439 #define TARGET_DEFAULT 0
442 #ifndef TARGET_CPU_DEFAULT
443 #define TARGET_CPU_DEFAULT 0
446 #ifndef TARGET_ENDIAN_DEFAULT
448 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
450 #define TARGET_ENDIAN_DEFAULT 0
454 #ifndef MULTILIB_DEFAULTS
455 #if TARGET_ENDIAN_DEFAULT == 0
456 #define MULTILIB_DEFAULTS { "EL", "mips1" }
458 #define MULTILIB_DEFAULTS { "EB", "mips1" }
462 /* This macro is similar to `TARGET_SWITCHES' but defines names of
463 command options that have values. Its definition is an
464 initializer with a subgrouping for each command option.
466 Each subgrouping contains a string constant, that defines the
467 fixed part of the option name, and the address of a variable.
468 The variable, type `char *', is set to the variable part of the
469 given option if the fixed part matches. The actual option name
470 is made by appending `-m' to the specified name.
472 Here is an example which defines `-mshort-data-NUMBER'. If the
473 given option is `-mshort-data-512', the variable `m88k_short_data'
474 will be set to the string `"512"'.
476 extern char *m88k_short_data;
477 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
479 #define TARGET_OPTIONS \
481 SUBTARGET_TARGET_OPTIONS \
482 { "cpu=", &mips_cpu_string }, \
483 { "ips", &mips_isa_string } \
486 /* This is meant to be redefined in the host dependent files. */
487 #define SUBTARGET_TARGET_OPTIONS
489 /* Macros to decide whether certain features are available or not,
490 depending on the instruction set architecture level. */
492 #define BRANCH_LIKELY_P() (mips_isa >= 2)
493 #define HAVE_SQRT_P() (mips_isa >= 2)
495 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
496 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
497 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
498 target_flags, and -mgp64 sets MASK_64BIT.
500 Setting MASK_64BIT in target_flags will cause gcc to assume that
501 registers are 64 bits wide. int, long and void * will be 32 bit;
502 this may be changed with -mint64 or -mlong64.
504 The gen* programs link code that refers to MASK_64BIT. They don't
505 actually use the information in target_flags; they just refer to
508 /* Switch Recognition by gcc.c. Add -G xx support */
510 #ifdef SWITCH_TAKES_ARG
511 #undef SWITCH_TAKES_ARG
514 #define SWITCH_TAKES_ARG(CHAR) \
515 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
517 /* Sometimes certain combinations of command options do not make sense
518 on a particular target machine. You can define a macro
519 `OVERRIDE_OPTIONS' to take account of this. This macro, if
520 defined, is executed once just after all the command options have
523 On the MIPS, it is used to handle -G. We also use it to set up all
524 of the tables referenced in the other macros. */
526 #define OVERRIDE_OPTIONS override_options ()
528 /* Zero or more C statements that may conditionally modify two
529 variables `fixed_regs' and `call_used_regs' (both of type `char
530 []') after they have been initialized from the two preceding
533 This is necessary in case the fixed or call-clobbered registers
534 depend on target flags.
536 You need not define this macro if it has no work to do.
538 If the usage of an entire class of registers depends on the target
539 flags, you may indicate this to GCC by using this macro to modify
540 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
541 the classes which should not be used by GCC. Also define the macro
542 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
543 letter for a class that shouldn't be used.
545 (However, if this class is not included in `GENERAL_REGS' and all
546 of the insn patterns whose constraints permit this class are
547 controlled by target switches, then GCC will automatically avoid
548 using these registers when the target switches are opposed to
551 #define CONDITIONAL_REGISTER_USAGE \
554 if (!TARGET_HARD_FLOAT) \
558 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
559 fixed_regs[regno] = call_used_regs[regno] = 1; \
560 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
561 fixed_regs[regno] = call_used_regs[regno] = 1; \
563 else if (mips_isa < 4) \
567 /* We only have a single condition code register. We \
568 implement this by hiding all the condition code registers, \
569 and generating RTL that refers directly to ST_REG_FIRST. */ \
570 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
571 fixed_regs[regno] = call_used_regs[regno] = 1; \
573 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
577 /* This is meant to be redefined in the host dependent files. */
578 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
580 /* Show we can debug even without a frame pointer. */
581 #define CAN_DEBUG_WITHOUT_FP
583 /* Complain about missing specs and predefines that should be defined in each
584 of the target tm files to override the defaults. This is mostly a place-
585 holder until I can get each of the files updated [mm]. */
587 #if defined(OSF_OS) \
588 || defined(DECSTATION) \
589 || defined(SGI_TARGET) \
590 || defined(MIPS_NEWS) \
591 || defined(MIPS_SYSV) \
592 || defined(MIPS_SVR4) \
593 || defined(MIPS_BSD43)
595 #ifndef CPP_PREDEFINES
596 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
600 #error "Define LIB_SPEC in the appropriate tm.h file"
603 #ifndef STARTFILE_SPEC
604 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
608 #error "Define MACHINE_TYPE in the appropriate tm.h file"
612 /* Tell collect what flags to pass to nm. */
614 #define NM_FLAGS "-Bp"
618 /* Names to predefine in the preprocessor for this target machine. */
620 #ifndef CPP_PREDEFINES
621 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
622 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
623 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
626 /* Extra switches sometimes passed to the assembler. */
629 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
633 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
634 %{pipe: %e-pipe is not supported.} \
637 %{mcpu=*} %{m4650} %{mmad:-m4650}} \
638 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{v} \
640 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}} \
641 %{g} %{g0} %{g1} %{g2} %{g3} \
642 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
643 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
644 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
645 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
652 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
653 %{pipe: %e-pipe is not supported.} \
656 %{mcpu=*} %{m4650} %{mmad:-m4650}} \
657 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{v} \
659 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}} \
660 %{g} %{g0} %{g1} %{g2} %{g3} \
661 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
662 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
663 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
664 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
668 #endif /* ASM_SPEC */
670 /* Specify to run a post-processor, mips-tfile after the assembler
671 has run to stuff the mips debug information into the object file.
672 This is needed because the $#!%^ MIPS assembler provides no way
673 of specifying such information in the assembly file. If we are
674 cross compiling, disable mips-tfile unless the user specifies
677 #ifndef ASM_FINAL_SPEC
678 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
680 #define ASM_FINAL_SPEC "\
681 %{mmips-as: %{!mno-mips-tfile: \
682 \n mips-tfile %{v*: -v} \
684 %{!K: %{save-temps: -I %b.o~}} \
685 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
686 %{.s:%i} %{!.s:%g.s}}}"
690 #define ASM_FINAL_SPEC "\
691 %{!mgas: %{!mno-mips-tfile: \
692 \n mips-tfile %{v*: -v} \
694 %{!K: %{save-temps: -I %b.o~}} \
695 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
696 %{.s:%i} %{!.s:%g.s}}}"
699 #endif /* ASM_FINAL_SPEC */
701 /* Redefinition of libraries used. Mips doesn't support normal
702 UNIX style profiling via calling _mcount. It does offer
703 profiling that samples the PC, so do what we can... */
706 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
709 /* Extra switches sometimes passed to the linker. */
710 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
711 will interpret it as a -b option. */
715 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
716 %{bestGnum} %{shared} %{non_shared}"
717 #endif /* LINK_SPEC defined */
719 /* Specs for the compiler proper */
723 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
724 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
725 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
726 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
727 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
728 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
729 %{m4650:-mcpu=r4650} \
730 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
731 %{pic-none: -mno-half-pic} \
732 %{pic-lib: -mhalf-pic} \
733 %{pic-extern: -mhalf-pic} \
734 %{pic-calls: -mhalf-pic} \
738 /* Preprocessor specs */
742 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
743 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
744 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
745 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C} \
746 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
747 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
748 %{!.S:%{!.s: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}} \
749 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
750 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
751 %{mips3:-U__mips -D__mips=3 -D__mips64} \
752 %{mips4:-U__mips -D__mips=4 -D__mips64} \
753 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
754 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
755 %{m4650:%{!msoft-float:-D__mips_single_float}} \
756 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
757 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}}"
760 /* If defined, this macro is an additional prefix to try after
761 `STANDARD_EXEC_PREFIX'. */
763 #ifndef MD_EXEC_PREFIX
764 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
767 #ifndef MD_STARTFILE_PREFIX
768 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
772 /* Print subsidiary information on the compiler version in use. */
774 #define MIPS_VERSION "[AL 1.1, MM 40]"
777 #define MACHINE_TYPE "BSD Mips"
780 #ifndef TARGET_VERSION_INTERNAL
781 #define TARGET_VERSION_INTERNAL(STREAM) \
782 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
785 #ifndef TARGET_VERSION
786 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
790 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
791 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
792 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
794 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
795 #define PREFERRED_DEBUGGING_TYPE ((len > 1 && !strncmp (str, "ggdb", len)) ? DBX_DEBUG : SDB_DEBUG)
798 /* By default, turn on GDB extensions. */
799 #define DEFAULT_GDB_EXTENSIONS 1
801 /* If we are passing smuggling stabs through the MIPS ECOFF object
802 format, put a comment in front of the .stab<x> operation so
803 that the MIPS assembler does not choke. The mips-tfile program
804 will correctly put the stab into the object file. */
806 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
807 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
808 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
810 /* Local compiler-generated symbols must have a prefix that the assembler
811 understands. By default, this is $, although some targets (e.g.,
812 NetBSD-ELF) need to override this. */
814 #ifndef LOCAL_LABEL_PREFIX
815 #define LOCAL_LABEL_PREFIX "$"
818 /* By default on the mips, external symbols do not have an underscore
819 prepended, but some targets (e.g., NetBSD) require this. */
821 #ifndef USER_LABEL_PREFIX
822 #define USER_LABEL_PREFIX ""
825 /* Forward references to tags are allowed. */
826 #define SDB_ALLOW_FORWARD_REFERENCES
828 /* Unknown tags are also allowed. */
829 #define SDB_ALLOW_UNKNOWN_REFERENCES
831 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
832 since the length can run past this up to a continuation point. */
833 #define DBX_CONTIN_LENGTH 1500
836 /* How to renumber registers for dbx and gdb. */
837 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
840 /* Overrides for the COFF debug format. */
841 #define PUT_SDB_SCL(a) \
843 extern FILE *asm_out_text_file; \
844 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
847 #define PUT_SDB_INT_VAL(a) \
849 extern FILE *asm_out_text_file; \
850 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
853 #define PUT_SDB_VAL(a) \
855 extern FILE *asm_out_text_file; \
856 fputs ("\t.val\t", asm_out_text_file); \
857 output_addr_const (asm_out_text_file, (a)); \
858 fputc (';', asm_out_text_file); \
861 #define PUT_SDB_DEF(a) \
863 extern FILE *asm_out_text_file; \
864 fprintf (asm_out_text_file, "\t%s.def\t", \
865 (TARGET_GAS) ? "" : "#"); \
866 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
867 fputc (';', asm_out_text_file); \
870 #define PUT_SDB_PLAIN_DEF(a) \
872 extern FILE *asm_out_text_file; \
873 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
874 (TARGET_GAS) ? "" : "#", (a)); \
877 #define PUT_SDB_ENDEF \
879 extern FILE *asm_out_text_file; \
880 fprintf (asm_out_text_file, "\t.endef\n"); \
883 #define PUT_SDB_TYPE(a) \
885 extern FILE *asm_out_text_file; \
886 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
889 #define PUT_SDB_SIZE(a) \
891 extern FILE *asm_out_text_file; \
892 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
895 #define PUT_SDB_DIM(a) \
897 extern FILE *asm_out_text_file; \
898 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
901 #ifndef PUT_SDB_START_DIM
902 #define PUT_SDB_START_DIM \
904 extern FILE *asm_out_text_file; \
905 fprintf (asm_out_text_file, "\t.dim\t"); \
909 #ifndef PUT_SDB_NEXT_DIM
910 #define PUT_SDB_NEXT_DIM(a) \
912 extern FILE *asm_out_text_file; \
913 fprintf (asm_out_text_file, "%d,", a); \
917 #ifndef PUT_SDB_LAST_DIM
918 #define PUT_SDB_LAST_DIM(a) \
920 extern FILE *asm_out_text_file; \
921 fprintf (asm_out_text_file, "%d;", a); \
925 #define PUT_SDB_TAG(a) \
927 extern FILE *asm_out_text_file; \
928 fprintf (asm_out_text_file, "\t.tag\t"); \
929 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
930 fputc (';', asm_out_text_file); \
933 /* For block start and end, we create labels, so that
934 later we can figure out where the correct offset is.
935 The normal .ent/.end serve well enough for functions,
936 so those are just commented out. */
938 #define PUT_SDB_BLOCK_START(LINE) \
940 extern FILE *asm_out_text_file; \
941 fprintf (asm_out_text_file, \
942 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
943 LOCAL_LABEL_PREFIX, \
945 (TARGET_GAS) ? "" : "#", \
946 LOCAL_LABEL_PREFIX, \
952 #define PUT_SDB_BLOCK_END(LINE) \
954 extern FILE *asm_out_text_file; \
955 fprintf (asm_out_text_file, \
956 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
957 LOCAL_LABEL_PREFIX, \
959 (TARGET_GAS) ? "" : "#", \
960 LOCAL_LABEL_PREFIX, \
966 #define PUT_SDB_FUNCTION_START(LINE)
968 #define PUT_SDB_FUNCTION_END(LINE) \
970 extern FILE *asm_out_text_file; \
971 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
974 #define PUT_SDB_EPILOGUE_END(NAME)
976 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
977 sprintf ((BUFFER), ".%dfake", (NUMBER));
979 /* Correct the offset of automatic variables and arguments. Note that
980 the MIPS debug format wants all automatic variables and arguments
981 to be in terms of the virtual frame pointer (stack pointer before
982 any adjustment in the function), while the MIPS 3.0 linker wants
983 the frame pointer to be the stack pointer after the initial
986 #define DEBUGGER_AUTO_OFFSET(X) mips_debugger_offset (X, 0)
987 #define DEBUGGER_ARG_OFFSET(OFFSET, X) mips_debugger_offset (X, OFFSET)
990 /* Tell collect that the object format is ECOFF */
991 #ifndef OBJECT_FORMAT_ROSE
992 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
993 #define EXTENDED_COFF /* ECOFF, not normal coff */
996 #if 0 /* These definitions normally have no effect because
997 MIPS systems define USE_COLLECT2, so
998 assemble_constructor does nothing anyway. */
1000 /* Don't use the default definitions, because we don't have gld.
1001 Also, we don't want stabs when generating ECOFF output.
1002 Instead we depend on collect to handle these. */
1004 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1005 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1009 /* Target machine storage layout */
1011 /* Define in order to support both big and little endian float formats
1012 in the same gcc binary. */
1013 #define REAL_ARITHMETIC
1015 /* Define this if most significant bit is lowest numbered
1016 in instructions that operate on numbered bit-fields.
1018 #define BITS_BIG_ENDIAN 0
1020 /* Define this if most significant byte of a word is the lowest numbered. */
1021 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1023 /* Define this if most significant word of a multiword number is the lowest. */
1024 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1026 /* Define this to set the endianness to use in libgcc2.c, which can
1027 not depend on target_flags. */
1028 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1029 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1031 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1034 /* Number of bits in an addressable storage unit */
1035 #define BITS_PER_UNIT 8
1037 /* Width in bits of a "word", which is the contents of a machine register.
1038 Note that this is not necessarily the width of data type `int';
1039 if using 16-bit ints on a 68000, this would still be 32.
1040 But on a machine with 16-bit registers, this would be 16. */
1041 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1042 #define MAX_BITS_PER_WORD 64
1044 /* Width of a word, in units (bytes). */
1045 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1046 #define MIN_UNITS_PER_WORD 4
1048 /* For MIPS, width of a floating point register. */
1049 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1051 /* A C expression for the size in bits of the type `int' on the
1052 target machine. If you don't define this, the default is one
1054 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1055 #define MAX_INT_TYPE_SIZE 64
1057 /* Tell the preprocessor the maximum size of wchar_t. */
1058 #ifndef MAX_WCHAR_TYPE_SIZE
1059 #ifndef WCHAR_TYPE_SIZE
1060 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1064 /* A C expression for the size in bits of the type `short' on the
1065 target machine. If you don't define this, the default is half a
1066 word. (If this would be less than one storage unit, it is
1067 rounded up to one unit.) */
1068 #define SHORT_TYPE_SIZE 16
1070 /* A C expression for the size in bits of the type `long' on the
1071 target machine. If you don't define this, the default is one
1073 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1074 #define MAX_LONG_TYPE_SIZE 64
1076 /* A C expression for the size in bits of the type `long long' on the
1077 target machine. If you don't define this, the default is two
1079 #define LONG_LONG_TYPE_SIZE 64
1081 /* A C expression for the size in bits of the type `char' on the
1082 target machine. If you don't define this, the default is one
1083 quarter of a word. (If this would be less than one storage unit,
1084 it is rounded up to one unit.) */
1085 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1087 /* A C expression for the size in bits of the type `float' on the
1088 target machine. If you don't define this, the default is one
1090 #define FLOAT_TYPE_SIZE 32
1092 /* A C expression for the size in bits of the type `double' on the
1093 target machine. If you don't define this, the default is two
1095 #define DOUBLE_TYPE_SIZE 64
1097 /* A C expression for the size in bits of the type `long double' on
1098 the target machine. If you don't define this, the default is two
1100 #define LONG_DOUBLE_TYPE_SIZE 64
1102 /* Width in bits of a pointer.
1103 See also the macro `Pmode' defined below. */
1104 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1106 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1107 #define POINTER_BOUNDARY (TARGET_LONG64 ? 64 : 32)
1109 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1110 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1112 /* Allocation boundary (in *bits*) for the code of a function. */
1113 #define FUNCTION_BOUNDARY 32
1115 /* Alignment of field after `int : 0' in a structure. */
1116 #define EMPTY_FIELD_BOUNDARY (TARGET_LONG64 ? 64 : 32)
1118 /* Every structure's size must be a multiple of this. */
1119 /* 8 is observed right on a DECstation and on riscos 4.02. */
1120 #define STRUCTURE_SIZE_BOUNDARY 8
1122 /* There is no point aligning anything to a rounder boundary than this. */
1123 #define BIGGEST_ALIGNMENT 64
1125 /* Biggest alignment any structure field can require in bits. */
1126 #define BIGGEST_FIELD_ALIGNMENT 64
1128 /* Set this nonzero if move instructions will actually fail to work
1129 when given unaligned data. */
1130 #define STRICT_ALIGNMENT 1
1132 /* Define this if you wish to imitate the way many other C compilers
1133 handle alignment of bitfields and the structures that contain
1136 The behavior is that the type written for a bitfield (`int',
1137 `short', or other integer type) imposes an alignment for the
1138 entire structure, as if the structure really did contain an
1139 ordinary field of that type. In addition, the bitfield is placed
1140 within the structure so that it would fit within such a field,
1141 not crossing a boundary for it.
1143 Thus, on most machines, a bitfield whose type is written as `int'
1144 would not cross a four-byte boundary, and would force four-byte
1145 alignment for the whole structure. (The alignment used may not
1146 be four bytes; it is controlled by the other alignment
1149 If the macro is defined, its definition should be a C expression;
1150 a nonzero value for the expression enables this behavior. */
1152 #define PCC_BITFIELD_TYPE_MATTERS 1
1154 /* If defined, a C expression to compute the alignment given to a
1155 constant that is being placed in memory. CONSTANT is the constant
1156 and ALIGN is the alignment that the object would ordinarily have.
1157 The value of this macro is used instead of that alignment to align
1160 If this macro is not defined, then ALIGN is used.
1162 The typical use of this macro is to increase alignment for string
1163 constants to be word aligned so that `strcpy' calls that copy
1164 constants can be done inline. */
1166 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1167 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1168 && (ALIGN) < BITS_PER_WORD \
1172 /* If defined, a C expression to compute the alignment for a static
1173 variable. TYPE is the data type, and ALIGN is the alignment that
1174 the object would ordinarily have. The value of this macro is used
1175 instead of that alignment to align the object.
1177 If this macro is not defined, then ALIGN is used.
1179 One use of this macro is to increase alignment of medium-size
1180 data to make it all fit in fewer cache lines. Another is to
1181 cause character arrays to be word-aligned so that `strcpy' calls
1182 that copy constants to character arrays can be done inline. */
1184 #undef DATA_ALIGNMENT
1185 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1186 ((((ALIGN) < BITS_PER_WORD) \
1187 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1188 || TREE_CODE (TYPE) == UNION_TYPE \
1189 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1191 /* Define this macro if an argument declared as `char' or `short' in a
1192 prototype should actually be passed as an `int'. In addition to
1193 avoiding errors in certain cases of mismatch, it also makes for
1194 better code on certain machines. */
1196 #define PROMOTE_PROTOTYPES
1198 /* Define if operations between registers always perform the operation
1199 on the full register even if a narrower mode is specified. */
1200 #define WORD_REGISTER_OPERATIONS
1202 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1203 will either zero-extend or sign-extend. The value of this macro should
1204 be the code that says which one of the two operations is implicitly
1205 done, NIL if none. */
1206 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1208 /* Standard register usage. */
1210 /* Number of actual hardware registers.
1211 The hardware registers are assigned numbers for the compiler
1212 from 0 to just below FIRST_PSEUDO_REGISTER.
1213 All registers that the compiler knows about must be given numbers,
1214 even those that are not normally considered general registers.
1216 On the Mips, we have 32 integer registers, 32 floating point
1217 registers, 8 condition code registers, and the special registers
1218 hi, lo, hilo, and rap. The 8 condition code registers are only
1219 used if mips_isa >= 4. The hilo register is only used in 64 bit
1220 mode. It represents a 64 bit value stored as two 32 bit values in
1221 the hi and lo registers; this is the result of the mult
1222 instruction. rap is a pointer to the stack where the return
1223 address reg ($31) was stored. This is needed for C++ exception
1226 #define FIRST_PSEUDO_REGISTER 76
1228 /* 1 for registers that have pervasive standard uses
1229 and are not available for the register allocator.
1231 On the MIPS, see conventions, page D-2 */
1233 #define FIXED_REGISTERS \
1235 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1237 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1243 /* 1 for registers not available across function calls.
1244 These must include the FIXED_REGISTERS and also any
1245 registers that can be used without being saved.
1246 The latter must include the registers where values are returned
1247 and the register where structure-value addresses are passed.
1248 Aside from that, you can include as many other registers as you like. */
1250 #define CALL_USED_REGISTERS \
1252 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1253 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1254 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1255 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1256 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1260 /* Internal macros to classify a register number as to whether it's a
1261 general purpose register, a floating point register, a
1262 multiply/divide register, or a status register. */
1264 #define GP_REG_FIRST 0
1265 #define GP_REG_LAST 31
1266 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1267 #define GP_DBX_FIRST 0
1269 #define FP_REG_FIRST 32
1270 #define FP_REG_LAST 63
1271 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1272 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1274 #define MD_REG_FIRST 64
1275 #define MD_REG_LAST 66
1276 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1278 #define ST_REG_FIRST 67
1279 #define ST_REG_LAST 74
1280 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1282 #define RAP_REG_NUM 75
1284 #define AT_REGNUM (GP_REG_FIRST + 1)
1285 #define HI_REGNUM (MD_REG_FIRST + 0)
1286 #define LO_REGNUM (MD_REG_FIRST + 1)
1287 #define HILO_REGNUM (MD_REG_FIRST + 2)
1289 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1290 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1291 should be used instead. */
1292 #define FPSW_REGNUM ST_REG_FIRST
1294 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1295 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1296 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1297 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1299 /* Return number of consecutive hard regs needed starting at reg REGNO
1300 to hold something of mode MODE.
1301 This is ordinarily the length in words of a value of mode MODE
1302 but can be less for certain modes in special long registers.
1304 On the MIPS, all general registers are one word long. Except on
1305 the R4000 with the FR bit set, the floating point uses register
1306 pairs, with the second register not being allocatable. */
1308 #define HARD_REGNO_NREGS(REGNO, MODE) \
1309 (! FP_REG_P (REGNO) \
1310 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1311 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1313 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1314 MODE. In 32 bit mode, require that DImode and DFmode be in even
1315 registers. For DImode, this makes some of the insns easier to
1316 write, since you don't have to worry about a DImode value in
1317 registers 3 & 4, producing a result in 4 & 5.
1319 To make the code simpler HARD_REGNO_MODE_OK now just references an
1320 array built in override_options. Because machmodes.h is not yet
1321 included before this file is processed, the MODE bound can't be
1324 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1326 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1327 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1329 /* Value is 1 if it is a good idea to tie two pseudo registers
1330 when one has mode MODE1 and one has mode MODE2.
1331 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1332 for any hard reg, then this must be 0 for correct output. */
1333 #define MODES_TIEABLE_P(MODE1, MODE2) \
1334 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1335 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1336 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1337 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1339 /* MIPS pc is not overloaded on a register. */
1340 /* #define PC_REGNUM xx */
1342 /* Register to use for pushing function arguments. */
1343 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1345 /* Offset from the stack pointer to the first available location. */
1346 #define STACK_POINTER_OFFSET 0
1348 /* Base register for access to local variables of the function. */
1349 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 30)
1351 /* Value should be nonzero if functions must have frame pointers.
1352 Zero means the frame pointer need not be set up (and parms
1353 may be accessed via the stack pointer) in functions that seem suitable.
1354 This is computed in `reload', in reload1.c. */
1355 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1357 /* Base register for access to arguments of the function. */
1358 #define ARG_POINTER_REGNUM GP_REG_FIRST
1360 /* Fake register that holds the address on the stack of the
1361 current function's return address. */
1362 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1364 /* Register in which static-chain is passed to a function. */
1365 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1367 /* If the structure value address is passed in a register, then
1368 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1369 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1371 /* If the structure value address is not passed in a register, define
1372 `STRUCT_VALUE' as an expression returning an RTX for the place
1373 where the address is passed. If it returns 0, the address is
1374 passed as an "invisible" first argument. */
1375 #define STRUCT_VALUE 0
1377 /* Mips registers used in prologue/epilogue code when the stack frame
1378 is larger than 32K bytes. These registers must come from the
1379 scratch register set, and not used for passing and returning
1380 arguments and any other information used in the calling sequence
1381 (such as pic). Must start at 12, since t0/t3 are parameter passing
1382 registers in the 64 bit ABI. */
1384 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1385 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1387 /* Define this macro if it is as good or better to call a constant
1388 function address than to call an address kept in a register. */
1389 #define NO_FUNCTION_CSE 1
1391 /* Define this macro if it is as good or better for a function to
1392 call itself with an explicit address than to call an address
1393 kept in a register. */
1394 #define NO_RECURSIVE_FUNCTION_CSE 1
1396 /* The register number of the register used to address a table of
1397 static data addresses in memory. In some cases this register is
1398 defined by a processor's "application binary interface" (ABI).
1399 When this macro is defined, RTL is generated for this register
1400 once, as with the stack pointer and frame pointer registers. If
1401 this macro is not defined, it is up to the machine-dependent
1402 files to allocate such a register (if necessary). */
1403 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1405 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1407 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1408 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1409 isn't always called for static inline functions. */
1410 #define INIT_EXPANDERS embedded_pic_fnaddr_rtx = NULL;
1412 /* Define the classes of registers for register constraints in the
1413 machine description. Also define ranges of constants.
1415 One of the classes must always be named ALL_REGS and include all hard regs.
1416 If there is more than one class, another class must be named NO_REGS
1417 and contain no registers.
1419 The name GENERAL_REGS must be the name of a class (or an alias for
1420 another name such as ALL_REGS). This is the class of registers
1421 that is allowed by "g" or "r" in a register constraint.
1422 Also, registers outside this class are allocated only when
1423 instructions express preferences for them.
1425 The classes must be numbered in nondecreasing order; that is,
1426 a larger-numbered class must never be contained completely
1427 in a smaller-numbered class.
1429 For any two classes, it is very desirable that there be another
1430 class that represents their union. */
1434 NO_REGS, /* no registers in set */
1435 GR_REGS, /* integer registers */
1436 FP_REGS, /* floating point registers */
1437 HI_REG, /* hi register */
1438 LO_REG, /* lo register */
1439 HILO_REG, /* hilo register pair for 64 bit mode mult */
1440 MD_REGS, /* multiply/divide registers (hi/lo) */
1441 ST_REGS, /* status registers (fp status) */
1442 ALL_REGS, /* all registers */
1443 LIM_REG_CLASSES /* max value + 1 */
1446 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1448 #define GENERAL_REGS GR_REGS
1450 /* An initializer containing the names of the register classes as C
1451 string constants. These names are used in writing some of the
1454 #define REG_CLASS_NAMES \
1467 /* An initializer containing the contents of the register classes,
1468 as integers which are bit masks. The Nth integer specifies the
1469 contents of class N. The way the integer MASK is interpreted is
1470 that register R is in the class if `MASK & (1 << R)' is 1.
1472 When the machine has more than 32 registers, an integer does not
1473 suffice. Then the integers are replaced by sub-initializers,
1474 braced groupings containing several integers. Each
1475 sub-initializer must be suitable as an initializer for the type
1476 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1478 #define REG_CLASS_CONTENTS \
1480 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1481 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1482 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1483 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1484 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1485 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1486 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1487 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1488 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1492 /* A C expression whose value is a register class containing hard
1493 register REGNO. In general there is more that one such class;
1494 choose a class which is "minimal", meaning that no smaller class
1495 also contains the register. */
1497 extern enum reg_class mips_regno_to_class[];
1499 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1501 /* A macro whose definition is the name of the class to which a
1502 valid base register must belong. A base register is one used in
1503 an address which is the register value plus a displacement. */
1505 #define BASE_REG_CLASS GR_REGS
1507 /* A macro whose definition is the name of the class to which a
1508 valid index register must belong. An index register is one used
1509 in an address where its value is either multiplied by a scale
1510 factor or added to another register (as well as added to a
1513 #define INDEX_REG_CLASS NO_REGS
1516 /* REGISTER AND CONSTANT CLASSES */
1518 /* Get reg_class from a letter such as appears in the machine
1521 DEFINED REGISTER CLASSES:
1523 'd' General (aka integer) registers
1524 'f' Floating point registers
1527 'x' Multiply/divide registers
1529 'z' FP Status register
1530 'b' All registers */
1532 extern enum reg_class mips_char_to_class[];
1534 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1536 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1537 string can be used to stand for particular ranges of immediate
1538 operands. This macro defines what the ranges are. C is the
1539 letter, and VALUE is a constant value. Return 1 if VALUE is
1540 in the range specified by C. */
1544 `I' is used for the range of constants an arithmetic insn can
1545 actually contain (16 bits signed integers).
1547 `J' is used for the range which is just zero (ie, $r0).
1549 `K' is used for the range of constants a logical insn can actually
1550 contain (16 bit zero-extended integers).
1552 `L' is used for the range of constants that be loaded with lui
1553 (ie, the bottom 16 bits are zero).
1555 `M' is used for the range of constants that take two words to load
1556 (ie, not matched by `I', `K', and `L').
1558 `N' is used for negative 16 bit constants.
1560 `O' is an exact power of 2 (not yet used in the md file).
1562 `P' is used for positive 16 bit constants. */
1564 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1565 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1567 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1568 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1569 : (C) == 'J' ? ((VALUE) == 0) \
1570 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1571 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1572 && (((VALUE) & ~2147483647) == 0 \
1573 || ((VALUE) & ~2147483647) == ~2147483647)) \
1574 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1575 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1576 && (((VALUE) & 0x0000ffff) != 0 \
1577 || (((VALUE) & ~2147483647) != 0 \
1578 && ((VALUE) & ~2147483647) != ~2147483647))) \
1579 : (C) == 'N' ? (((VALUE) & ~0x0000ffff) == ~0x0000ffff) \
1580 : (C) == 'O' ? (exact_log2 (VALUE) >= 0) \
1581 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1584 /* Similar, but for floating constants, and defining letters G and H.
1585 Here VALUE is the CONST_DOUBLE rtx itself. */
1589 'G' : Floating point 0 */
1591 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1593 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1595 /* Letters in the range `Q' through `U' may be defined in a
1596 machine-dependent fashion to stand for arbitrary operand types.
1597 The machine description macro `EXTRA_CONSTRAINT' is passed the
1598 operand as its first argument and the constraint letter as its
1601 `Q' is for memory references which take more than 1 instruction.
1602 `R' is for memory references which take 1 word for the instruction.
1603 `S' is for references to extern items which are PIC for OSF/rose. */
1605 #define EXTRA_CONSTRAINT(OP,CODE) \
1606 ((GET_CODE (OP) != MEM) ? FALSE \
1607 : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \
1608 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1609 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1610 && HALF_PIC_ADDRESS_P (OP)) \
1613 /* Given an rtx X being reloaded into a reg required to be
1614 in class CLASS, return the class of reg to actually use.
1615 In general this is just CLASS; but on some machines
1616 in some cases it is preferable to use a more restrictive class. */
1618 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1619 ((CLASS) != ALL_REGS \
1621 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1622 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1623 ? (TARGET_SOFT_FLOAT ? GR_REGS : FP_REGS) \
1624 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1625 || GET_MODE (X) == VOIDmode) \
1629 /* Certain machines have the property that some registers cannot be
1630 copied to some other registers without using memory. Define this
1631 macro on those machines to be a C expression that is non-zero if
1632 objects of mode MODE in registers of CLASS1 can only be copied to
1633 registers of class CLASS2 by storing a register of CLASS1 into
1634 memory and loading that memory location into a register of CLASS2.
1636 Do not define this macro if its value would always be zero. */
1638 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1639 ((!TARGET_DEBUG_H_MODE \
1640 && GET_MODE_CLASS (MODE) == MODE_INT \
1641 && ((CLASS1 == FP_REGS && CLASS2 == GR_REGS) \
1642 || (CLASS1 == GR_REGS && CLASS2 == FP_REGS))) \
1643 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1644 && ((CLASS1 == GR_REGS && CLASS2 == FP_REGS) \
1645 || (CLASS2 == GR_REGS && CLASS1 == FP_REGS))))
1647 /* The HI and LO registers can only be reloaded via the general
1648 registers. Condition code registers can only be loaded to the
1649 general registers, and from the floating point registers. */
1651 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1652 mips_secondary_reload_class (CLASS, MODE, X, 1)
1653 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1654 mips_secondary_reload_class (CLASS, MODE, X, 0)
1656 /* Not declared above, with the other functions, because enum
1657 reg_class is not declared yet. */
1658 extern enum reg_class mips_secondary_reload_class ();
1660 /* Return the maximum number of consecutive registers
1661 needed to represent mode MODE in a register of class CLASS. */
1663 #define CLASS_UNITS(mode, size) \
1664 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1666 #define CLASS_MAX_NREGS(CLASS, MODE) \
1667 ((CLASS) == FP_REGS \
1669 ? CLASS_UNITS (MODE, 8) \
1670 : 2 * CLASS_UNITS (MODE, 8)) \
1671 : CLASS_UNITS (MODE, UNITS_PER_WORD))
1673 /* If defined, this is a C expression whose value should be
1674 nonzero if the insn INSN has the effect of mysteriously
1675 clobbering the contents of hard register number REGNO. By
1676 "mysterious" we mean that the insn's RTL expression doesn't
1677 describe such an effect.
1679 If this macro is not defined, it means that no insn clobbers
1680 registers mysteriously. This is the usual situation; all else
1681 being equal, it is best for the RTL expression to show all the
1684 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
1687 /* Stack layout; function entry, exit and calling. */
1689 /* Define this if pushing a word on the stack
1690 makes the stack pointer a smaller address. */
1691 #define STACK_GROWS_DOWNWARD
1693 /* Define this if the nominal address of the stack frame
1694 is at the high-address end of the local variables;
1695 that is, each additional local variable allocated
1696 goes at a more negative offset in the frame. */
1697 /* #define FRAME_GROWS_DOWNWARD */
1699 /* Offset within stack frame to start allocating local variables at.
1700 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1701 first local allocated. Otherwise, it is the offset to the BEGINNING
1702 of the first local allocated. */
1703 #define STARTING_FRAME_OFFSET \
1704 (current_function_outgoing_args_size \
1705 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1707 /* Offset from the stack pointer register to an item dynamically
1708 allocated on the stack, e.g., by `alloca'.
1710 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1711 length of the outgoing arguments. The default is correct for most
1712 machines. See `function.c' for details.
1714 The MIPS ABI states that functions which dynamically allocate the
1715 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
1716 we are trying to create a second frame pointer to the function, so
1717 allocate some stack space to make it happy.
1719 However, the linker currently complains about linking any code that
1720 dynamically allocates stack space, and there seems to be a bug in
1721 STACK_DYNAMIC_OFFSET, so don't define this right now. */
1724 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1725 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
1726 ? 4*UNITS_PER_WORD \
1727 : current_function_outgoing_args_size)
1730 /* The return address for the current frame is in r31 is this is a leaf
1731 function. Otherwise, it is on the stack. It is at a variable offset
1732 from sp/fp/ap, so we define a fake hard register rap which is a
1733 poiner to the return address on the stack. This always gets eliminated
1734 during reload to be either the frame pointer or the stack pointer plus
1737 /* ??? This definition fails for leaf functions. There is currently no
1738 general solution for this problem. */
1740 /* ??? There appears to be no way to get the return address of any previous
1741 frame except by disassembling instructions in the prologue/epilogue.
1742 So currently we support only the current frame. */
1744 #define RETURN_ADDR_RTX(count, frame) \
1746 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
1749 /* Structure to be filled in by compute_frame_size with register
1750 save masks, and offsets for the current function. */
1752 struct mips_frame_info
1754 long total_size; /* # bytes that the entire frame takes up */
1755 long var_size; /* # bytes that variables take up */
1756 long args_size; /* # bytes that outgoing arguments take up */
1757 long extra_size; /* # bytes of extra gunk */
1758 int gp_reg_size; /* # bytes needed to store gp regs */
1759 int fp_reg_size; /* # bytes needed to store fp regs */
1760 long mask; /* mask of saved gp registers */
1761 long fmask; /* mask of saved fp registers */
1762 long gp_save_offset; /* offset from vfp to store gp registers */
1763 long fp_save_offset; /* offset from vfp to store fp registers */
1764 long gp_sp_offset; /* offset from new sp to store gp registers */
1765 long fp_sp_offset; /* offset from new sp to store fp registers */
1766 int initialized; /* != 0 if frame size already calculated */
1767 int num_gp; /* number of gp registers saved */
1768 int num_fp; /* number of fp registers saved */
1771 extern struct mips_frame_info current_frame_info;
1773 /* Store in the variable DEPTH the initial difference between the
1774 frame pointer reg contents and the stack pointer reg contents,
1775 as of the start of the function body. This depends on the layout
1776 of the fixed parts of the stack frame and on how registers are saved. */
1778 /* #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
1779 ((VAR) = compute_frame_size (get_frame_size ())) */
1781 /* If defined, this macro specifies a table of register pairs used to
1782 eliminate unneeded registers that point into the stack frame. If
1783 it is not defined, the only elimination attempted by the compiler
1784 is to replace references to the frame pointer with references to
1787 The definition of this macro is a list of structure
1788 initializations, each of which specifies an original and
1789 replacement register.
1791 On some machines, the position of the argument pointer is not
1792 known until the compilation is completed. In such a case, a
1793 separate hard register must be used for the argument pointer.
1794 This register can be eliminated by replacing it with either the
1795 frame pointer or the argument pointer, depending on whether or not
1796 the frame pointer has been eliminated.
1798 In this case, you might specify:
1799 #define ELIMINABLE_REGS \
1800 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1801 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1802 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1804 Note that the elimination of the argument pointer with the stack
1805 pointer is specified first since that is the preferred elimination. */
1807 #define ELIMINABLE_REGS \
1808 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1809 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1810 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1811 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1812 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1814 /* A C expression that returns non-zero if the compiler is allowed to
1815 try to replace register number FROM-REG with register number
1816 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
1817 defined, and will usually be the constant 1, since most of the
1818 cases preventing register elimination are things that the compiler
1819 already knows about. */
1821 #define CAN_ELIMINATE(FROM, TO) \
1822 (!frame_pointer_needed \
1823 || ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1824 || ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
1825 && (TO) == FRAME_POINTER_REGNUM))
1827 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1828 specifies the initial difference between the specified pair of
1829 registers. This macro must be defined if `ELIMINABLE_REGS' is
1832 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1833 { compute_frame_size (get_frame_size ()); \
1834 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1836 else if ((FROM) == ARG_POINTER_REGNUM \
1837 && ((TO) == FRAME_POINTER_REGNUM \
1838 || (TO) == STACK_POINTER_REGNUM)) \
1839 (OFFSET) = (current_frame_info.total_size \
1840 - (mips_abi != ABI_32 \
1841 ? current_function_pretend_args_size \
1843 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
1844 && ((TO) == FRAME_POINTER_REGNUM \
1845 || (TO) == STACK_POINTER_REGNUM)) \
1846 (OFFSET) = current_frame_info.gp_sp_offset; \
1851 /* If we generate an insn to push BYTES bytes,
1852 this says how many the stack pointer really advances by.
1853 On the vax, sp@- in a byte insn really pushes a word. */
1855 /* #define PUSH_ROUNDING(BYTES) 0 */
1857 /* If defined, the maximum amount of space required for outgoing
1858 arguments will be computed and placed into the variable
1859 `current_function_outgoing_args_size'. No space will be pushed
1860 onto the stack for each call; instead, the function prologue
1861 should increase the stack frame size by this amount.
1863 It is not proper to define both `PUSH_ROUNDING' and
1864 `ACCUMULATE_OUTGOING_ARGS'. */
1865 #define ACCUMULATE_OUTGOING_ARGS
1867 /* Offset from the argument pointer register to the first argument's
1868 address. On some machines it may depend on the data type of the
1871 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
1872 the first argument's address.
1874 On the MIPS, we must skip the first argument position if we are
1875 returning a structure or a union, to account for its address being
1876 passed in $4. However, at the current time, this produces a compiler
1877 that can't bootstrap, so comment it out for now. */
1880 #define FIRST_PARM_OFFSET(FNDECL) \
1882 && TREE_TYPE (FNDECL) != 0 \
1883 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
1884 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
1885 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
1889 #define FIRST_PARM_OFFSET(FNDECL) 0
1892 /* When a parameter is passed in a register, stack space is still
1893 allocated for it. For the MIPS, stack space must be allocated, cf
1894 Asm Lang Prog Guide page 7-8.
1896 BEWARE that some space is also allocated for non existing arguments
1897 in register. In case an argument list is of form GF used registers
1898 are a0 (a2,a3), but we should push over a1... */
1900 #define REG_PARM_STACK_SPACE(FNDECL) \
1901 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
1903 /* Define this if it is the responsibility of the caller to
1904 allocate the area reserved for arguments passed in registers.
1905 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1906 of this macro is to determine whether the space is included in
1907 `current_function_outgoing_args_size'. */
1908 #define OUTGOING_REG_PARM_STACK_SPACE
1910 /* Align stack frames on 64 bits (Double Word ). */
1911 #define STACK_BOUNDARY 64
1913 /* Make sure 4 words are always allocated on the stack. */
1915 #ifndef STACK_ARGS_ADJUST
1916 #define STACK_ARGS_ADJUST(SIZE) \
1918 if (SIZE.constant < 4 * UNITS_PER_WORD) \
1919 SIZE.constant = 4 * UNITS_PER_WORD; \
1924 /* A C expression that should indicate the number of bytes of its
1925 own arguments that a function function pops on returning, or 0
1926 if the function pops no arguments and the caller must therefore
1927 pop them all after the function returns.
1929 FUNDECL is the declaration node of the function (as a tree).
1931 FUNTYPE is a C variable whose value is a tree node that
1932 describes the function in question. Normally it is a node of
1933 type `FUNCTION_TYPE' that describes the data type of the function.
1934 From this it is possible to obtain the data types of the value
1935 and arguments (if known).
1937 When a call to a library function is being considered, FUNTYPE
1938 will contain an identifier node for the library function. Thus,
1939 if you need to distinguish among various library functions, you
1940 can do so by their names. Note that "library function" in this
1941 context means a function used to perform arithmetic, whose name
1942 is known specially in the compiler and was not mentioned in the
1943 C code being compiled.
1945 STACK-SIZE is the number of bytes of arguments passed on the
1946 stack. If a variable number of bytes is passed, it is zero, and
1947 argument popping will always be the responsibility of the
1948 calling function. */
1950 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1953 /* Symbolic macros for the registers used to return integer and floating
1956 #define GP_RETURN (GP_REG_FIRST + 2)
1957 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1959 /* Symbolic macros for the first/last argument registers. */
1961 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1962 #define GP_ARG_LAST (GP_REG_FIRST + 7)
1963 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1964 #define FP_ARG_LAST (FP_REG_FIRST + 15)
1966 #define MAX_ARGS_IN_REGISTERS 4
1968 /* Define how to find the value returned by a library function
1969 assuming the value has mode MODE. */
1971 #define LIBCALL_VALUE(MODE) \
1972 gen_rtx (REG, MODE, \
1973 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
1974 && (! TARGET_SINGLE_FLOAT \
1975 || GET_MODE_SIZE (MODE) <= 4)) \
1979 /* Define how to find the value returned by a function.
1980 VALTYPE is the data type of the value (as a tree).
1981 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1982 otherwise, FUNC is 0. */
1984 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1987 /* 1 if N is a possible register number for a function value.
1988 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1989 Currently, R2 and F0 are only implemented here (C has no complex type) */
1991 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
1993 /* 1 if N is a possible register number for function argument passing. */
1995 #define FUNCTION_ARG_REGNO_P(N) (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
1996 || ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST \
1999 /* A C expression which can inhibit the returning of certain function
2000 values in registers, based on the type of value. A nonzero value says
2001 to return the function value in memory, just as large structures are
2002 always returned. Here TYPE will be a C expression of type
2003 `tree', representing the data type of the value.
2005 Note that values of mode `BLKmode' must be explicitly
2006 handled by this macro. Also, the option `-fpcc-struct-return'
2007 takes effect regardless of this macro. On most systems, it is
2008 possible to leave the macro undefined; this causes a default
2009 definition to be used, whose value is the constant 1 for BLKmode
2010 values, and 0 otherwise.
2012 GCC normally converts 1 byte structures into chars, 2 byte
2013 structs into shorts, and 4 byte structs into ints, and returns
2014 them this way. Defining the following macro overrides this,
2015 to give us MIPS cc compatibility. */
2017 #define RETURN_IN_MEMORY(TYPE) \
2018 (TYPE_MODE (TYPE) == BLKmode)
2020 /* A code distinguishing the floating point format of the target
2021 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2022 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2024 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2027 /* Define a data type for recording info about an argument list
2028 during the scan of that argument list. This data type should
2029 hold all necessary information about the function itself
2030 and about the args processed so far, enough to enable macros
2031 such as FUNCTION_ARG to determine where the next arg should go.
2034 typedef struct mips_args {
2035 int gp_reg_found; /* whether a gp register was found yet */
2036 int arg_number; /* argument number */
2037 int arg_words; /* # total words the arguments take */
2038 int num_adjusts; /* number of adjustments made */
2039 /* Adjustments made to args pass in regs. */
2040 /* ??? The size is doubled to work around a
2041 bug in the code that sets the adjustments
2043 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2046 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2047 for a call to a function whose data type is FNTYPE.
2048 For a library call, FNTYPE is 0.
2052 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2053 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2055 /* Update the data in CUM to advance over an argument
2056 of mode MODE and data type TYPE.
2057 (TYPE is null for libcalls where that information may not be available.) */
2059 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2060 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2062 /* Determine where to put an argument to a function.
2063 Value is zero to push the argument on the stack,
2064 or a hard register in which to store the argument.
2066 MODE is the argument's machine mode.
2067 TYPE is the data type of the argument (as a tree).
2068 This is null for libcalls where that information may
2070 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2071 the preceding args and about the function being called.
2072 NAMED is nonzero if this argument is a named parameter
2073 (otherwise it is an extra parameter matching an ellipsis). */
2075 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2076 function_arg( &CUM, MODE, TYPE, NAMED)
2078 /* For an arg passed partly in registers and partly in memory,
2079 this is the number of registers used.
2080 For args passed entirely in registers or entirely in memory, zero. */
2082 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2083 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2085 /* If defined, a C expression that gives the alignment boundary, in
2086 bits, of an argument with the specified mode and type. If it is
2087 not defined, `PARM_BOUNDARY' is used for all arguments. */
2089 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2091 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2093 : TYPE_ALIGN(TYPE)) \
2094 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2096 : GET_MODE_ALIGNMENT(MODE)))
2099 /* This macro generates the assembly code for function entry.
2100 FILE is a stdio stream to output the code to.
2101 SIZE is an int: how many units of temporary storage to allocate.
2102 Refer to the array `regs_ever_live' to determine which registers
2103 to save; `regs_ever_live[I]' is nonzero if register number I
2104 is ever used in the function. This macro is responsible for
2105 knowing which registers should not be saved even if used. */
2107 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2109 /* This macro generates the assembly code for function exit,
2110 on machines that need it. If FUNCTION_EPILOGUE is not defined
2111 then individual return instructions are generated for each
2112 return statement. Args are same as for FUNCTION_PROLOGUE. */
2114 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2116 /* Define the number of delay slots needed for the function epilogue.
2118 On the mips, we need a slot if either no stack has been allocated,
2119 or the only register saved is the return register. */
2121 #define DELAY_SLOTS_FOR_EPILOGUE mips_epilogue_delay_slots ()
2123 /* Define whether INSN can be placed in delay slot N for the epilogue.
2124 No references to the stack must be made, since on the MIPS, the
2125 delay slot is done after the stack has been cleaned up. */
2127 #define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N) \
2128 (get_attr_dslot (INSN) == DSLOT_NO \
2129 && get_attr_length (INSN) == 1 \
2130 && ! epilogue_reg_mentioned_p (PATTERN (INSN)))
2132 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2134 #define MUST_SAVE_REGISTER(regno) \
2135 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2136 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
2137 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2139 /* ALIGN FRAMES on double word boundaries */
2141 #define MIPS_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
2144 /* Output assembler code to FILE to increment profiler label # LABELNO
2145 for profiling a function entry. */
2147 #define FUNCTION_PROFILER(FILE, LABELNO) \
2149 fprintf (FILE, "\t.set\tnoreorder\n"); \
2150 fprintf (FILE, "\t.set\tnoat\n"); \
2151 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2152 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2153 fprintf (FILE, "\tjal\t_mcount\n"); \
2155 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2156 TARGET_64BIT ? "dsubu" : "subu", \
2157 reg_names[STACK_POINTER_REGNUM], \
2158 reg_names[STACK_POINTER_REGNUM], \
2159 TARGET_LONG64 ? 16 : 8); \
2160 fprintf (FILE, "\t.set\treorder\n"); \
2161 fprintf (FILE, "\t.set\tat\n"); \
2164 /* Define this macro if the code for function profiling should come
2165 before the function prologue. Normally, the profiling code comes
2168 /* #define PROFILE_BEFORE_PROLOGUE */
2170 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2171 the stack pointer does not matter. The value is tested only in
2172 functions that have frame pointers.
2173 No definition is equivalent to always zero. */
2175 #define EXIT_IGNORE_STACK 1
2178 /* A C statement to output, on the stream FILE, assembler code for a
2179 block of data that contains the constant parts of a trampoline.
2180 This code should not include a label--the label is taken care of
2183 #define TRAMPOLINE_TEMPLATE(STREAM) \
2185 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2186 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2187 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2188 if (TARGET_LONG64) \
2190 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2191 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2195 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2196 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2198 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2199 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2200 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2201 if (TARGET_LONG64) \
2203 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2204 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2208 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2209 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2213 /* A C expression for the size in bytes of the trampoline, as an
2216 #define TRAMPOLINE_SIZE (32 + (TARGET_LONG64 ? 16 : 8))
2218 /* Alignment required for trampolines, in bits. */
2220 #define TRAMPOLINE_ALIGNMENT (TARGET_LONG64 ? 64 : 32)
2222 /* A C statement to initialize the variable parts of a trampoline.
2223 ADDR is an RTX for the address of the trampoline; FNADDR is an
2224 RTX for the address of the nested function; STATIC_CHAIN is an
2225 RTX for the static chain value that should be passed to the
2226 function when it is called. */
2228 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2231 if (TARGET_LONG64) \
2233 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2234 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2238 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2239 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2242 /* Flush both caches. We need to flush the data cache in case \
2243 the system has a write-back cache. */ \
2244 /* ??? Should check the return value for errors. */ \
2245 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "_flush_cache"), \
2246 0, VOIDmode, 3, addr, Pmode, \
2247 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2248 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2251 /* Addressing modes, and classification of registers for them. */
2253 /* #define HAVE_POST_INCREMENT */
2254 /* #define HAVE_POST_DECREMENT */
2256 /* #define HAVE_PRE_DECREMENT */
2257 /* #define HAVE_PRE_INCREMENT */
2259 /* These assume that REGNO is a hard or pseudo reg number.
2260 They give nonzero only if REGNO is a hard reg of the suitable class
2261 or a pseudo reg currently allocated to a suitable hard reg.
2262 These definitions are NOT overridden anywhere. */
2264 #define GP_REG_OR_PSEUDO_STRICT_P(regno) \
2265 GP_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno])
2267 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno) \
2268 (((regno) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (regno)))
2270 #define REGNO_OK_FOR_INDEX_P(regno) 0
2271 #define REGNO_OK_FOR_BASE_P(regno) GP_REG_OR_PSEUDO_STRICT_P (regno)
2273 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2274 and check its validity for a certain class.
2275 We have two alternate definitions for each of them.
2276 The usual definition accepts all pseudo regs; the other rejects them all.
2277 The symbol REG_OK_STRICT causes the latter definition to be used.
2279 Most source files want to accept pseudo regs in the hope that
2280 they will get allocated to the class that the insn wants them to be in.
2281 Some source files that are used after register allocation
2282 need to be strict. */
2284 #ifndef REG_OK_STRICT
2286 #define REG_OK_STRICT_P 0
2287 #define REG_OK_FOR_INDEX_P(X) 0
2288 #define REG_OK_FOR_BASE_P(X) GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X))
2292 #define REG_OK_STRICT_P 1
2293 #define REG_OK_FOR_INDEX_P(X) 0
2294 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2299 /* Maximum number of registers that can appear in a valid memory address. */
2301 #define MAX_REGS_PER_ADDRESS 1
2303 /* A C compound statement with a conditional `goto LABEL;' executed
2304 if X (an RTX) is a legitimate memory address on the target
2305 machine for a memory operand of mode MODE.
2307 It usually pays to define several simpler macros to serve as
2308 subroutines for this one. Otherwise it may be too complicated
2311 This macro must exist in two variants: a strict variant and a
2312 non-strict one. The strict variant is used in the reload pass.
2313 It must be defined so that any pseudo-register that has not been
2314 allocated a hard register is considered a memory reference. In
2315 contexts where some kind of register is required, a
2316 pseudo-register with no hard register must be rejected.
2318 The non-strict variant is used in other passes. It must be
2319 defined to accept all pseudo-registers in every context where
2320 some kind of register is required.
2322 Compiler source files that want to use the strict variant of
2323 this macro define the macro `REG_OK_STRICT'. You should use an
2324 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2325 in that case and the non-strict variant otherwise.
2327 Typically among the subroutines used to define
2328 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2329 acceptable registers for various purposes (one for base
2330 registers, one for index registers, and so on). Then only these
2331 subroutine macros need have two variants; the higher levels of
2332 macros may be the same whether strict or not.
2334 Normally, constant addresses which are the sum of a `symbol_ref'
2335 and an integer are stored inside a `const' RTX to mark them as
2336 constant. Therefore, there is no need to recognize such sums
2337 specifically as legitimate addresses. Normally you would simply
2338 recognize any `const' as legitimate.
2340 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2341 constant sums that are not marked with `const'. It assumes
2342 that a naked `plus' indicates indexing. If so, then you *must*
2343 reject such naked constant sums as illegitimate addresses, so
2344 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2346 On some machines, whether a symbolic address is legitimate
2347 depends on the section that the address refers to. On these
2348 machines, define the macro `ENCODE_SECTION_INFO' to store the
2349 information into the `symbol_ref', and then check for it here.
2350 When you see a `const', you will have to look inside it to find
2351 the `symbol_ref' in order to determine the section. */
2354 #define GO_PRINTF(x) trace(x)
2355 #define GO_PRINTF2(x,y) trace(x,y)
2356 #define GO_DEBUG_RTX(x) debug_rtx(x)
2359 #define GO_PRINTF(x)
2360 #define GO_PRINTF2(x,y)
2361 #define GO_DEBUG_RTX(x)
2364 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2366 register rtx xinsn = (X); \
2368 if (TARGET_DEBUG_B_MODE) \
2370 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2371 (REG_OK_STRICT_P) ? "" : "not "); \
2372 GO_DEBUG_RTX (xinsn); \
2375 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
2378 if (CONSTANT_ADDRESS_P (xinsn) \
2379 && ! (mips_split_addresses && mips_check_split (xinsn, MODE))) \
2382 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2384 register rtx xlow0 = XEXP (xinsn, 0); \
2385 register rtx xlow1 = XEXP (xinsn, 1); \
2387 if (GET_CODE (xlow0) == REG && REG_OK_FOR_BASE_P (xlow0) \
2388 && mips_check_split (xlow1, MODE)) \
2392 if (GET_CODE (xinsn) == PLUS) \
2394 register rtx xplus0 = XEXP (xinsn, 0); \
2395 register rtx xplus1 = XEXP (xinsn, 1); \
2396 register enum rtx_code code0 = GET_CODE (xplus0); \
2397 register enum rtx_code code1 = GET_CODE (xplus1); \
2399 if (code0 != REG && code1 == REG) \
2401 xplus0 = XEXP (xinsn, 1); \
2402 xplus1 = XEXP (xinsn, 0); \
2403 code0 = GET_CODE (xplus0); \
2404 code1 = GET_CODE (xplus1); \
2407 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0)) \
2409 if (code1 == CONST_INT \
2410 && INTVAL (xplus1) >= -32768 \
2411 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2414 /* For some code sequences, you actually get better code by \
2415 pretending that the MIPS supports an address mode of a \
2416 constant address + a register, even though the real \
2417 machine doesn't support it. This is because the \
2418 assembler can use $r1 to load just the high 16 bits, add \
2419 in the register, and fold the low 16 bits into the memory \
2420 reference, whereas the compiler generates a 4 instruction \
2421 sequence. On the other hand, CSE is not as effective. \
2422 It would be a win to generate the lui directly, but the \
2423 MIPS assembler does not have syntax to generate the \
2424 appropriate relocation. */ \
2426 /* Also accept CONST_INT addresses here, so no else. */ \
2427 /* Reject combining an embedded PIC text segment reference \
2428 with a register. That requires an additional \
2430 /* ??? Reject combining an address with a register for the MIPS \
2431 64 bit ABI, because the SGI assembler can not handle this. */ \
2432 if (!TARGET_DEBUG_A_MODE \
2433 && mips_abi == ABI_32 \
2434 && CONSTANT_ADDRESS_P (xplus1) \
2435 && ! mips_split_addresses \
2436 && (!TARGET_EMBEDDED_PIC \
2438 || GET_CODE (XEXP (xplus1, 0)) != MINUS)) \
2443 if (TARGET_DEBUG_B_MODE) \
2444 GO_PRINTF ("Not a legitimate address\n"); \
2448 /* A C expression that is 1 if the RTX X is a constant which is a
2449 valid address. This is defined to be the same as `CONSTANT_P (X)',
2450 but rejecting CONST_DOUBLE. */
2451 /* When pic, we must reject addresses of the form symbol+large int.
2452 This is because an instruction `sw $4,s+70000' needs to be converted
2453 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2454 assembler would use $at as a temp to load in the large offset. In this
2455 case $at is already in use. We convert such problem addresses to
2456 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2457 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2458 #define CONSTANT_ADDRESS_P(X) \
2459 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2460 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2461 || (GET_CODE (X) == CONST \
2462 && ! (flag_pic && pic_address_needs_scratch (X)) \
2463 && mips_abi == ABI_32)) \
2464 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2466 /* Define this, so that when PIC, reload won't try to reload invalid
2467 addresses which require two reload registers. */
2469 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2471 /* Nonzero if the constant value X is a legitimate general operand.
2472 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2474 At present, GAS doesn't understand li.[sd], so don't allow it
2475 to be generated at present. Also, the MIPS assembler does not
2476 grok li.d Infinity. */
2478 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2479 #define LEGITIMATE_CONSTANT_P(X) \
2480 ((GET_CODE (X) != CONST_DOUBLE \
2481 || mips_const_double_ok (X, GET_MODE (X))) \
2482 && ! (GET_CODE (X) == CONST && mips_abi != ABI_32))
2484 /* A C compound statement that attempts to replace X with a valid
2485 memory address for an operand of mode MODE. WIN will be a C
2486 statement label elsewhere in the code; the macro definition may
2489 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2491 to avoid further processing if the address has become legitimate.
2493 X will always be the result of a call to `break_out_memory_refs',
2494 and OLDX will be the operand that was given to that function to
2497 The code generated by this macro should not alter the
2498 substructure of X. If it transforms X into a more legitimate
2499 form, it should assign X (which will always be a C variable) a
2502 It is not necessary for this macro to come up with a legitimate
2503 address. The compiler has standard ways of doing so in all
2504 cases. In fact, it is safe for this macro to do nothing. But
2505 often a machine-dependent strategy can generate better code.
2507 For the MIPS, transform:
2509 memory(X + <large int>)
2513 Y = <large int> & ~0x7fff;
2515 memory (Z + (<large int> & 0x7fff));
2517 This is for CSE to find several similar references, and only use one Z.
2519 When PIC, convert addresses of the form memory (symbol+large int) to
2520 memory (reg+large int). */
2523 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2525 register rtx xinsn = (X); \
2527 if (TARGET_DEBUG_B_MODE) \
2529 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2530 GO_DEBUG_RTX (xinsn); \
2533 if (mips_split_addresses && mips_check_split (X, MODE)) \
2535 /* ??? Is this ever executed? */ \
2536 X = gen_rtx (LO_SUM, Pmode, \
2537 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2541 if (GET_CODE (xinsn) == CONST \
2542 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2543 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2544 || mips_abi != ABI_32)) \
2546 rtx ptr_reg = gen_reg_rtx (Pmode); \
2547 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2549 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2551 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2552 if (SMALL_INT (constant)) \
2554 /* Otherwise we fall through so the code below will fix the \
2559 if (GET_CODE (xinsn) == PLUS) \
2561 register rtx xplus0 = XEXP (xinsn, 0); \
2562 register rtx xplus1 = XEXP (xinsn, 1); \
2563 register enum rtx_code code0 = GET_CODE (xplus0); \
2564 register enum rtx_code code1 = GET_CODE (xplus1); \
2566 if (code0 != REG && code1 == REG) \
2568 xplus0 = XEXP (xinsn, 1); \
2569 xplus1 = XEXP (xinsn, 0); \
2570 code0 = GET_CODE (xplus0); \
2571 code1 = GET_CODE (xplus1); \
2574 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
2575 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2577 rtx int_reg = gen_reg_rtx (Pmode); \
2578 rtx ptr_reg = gen_reg_rtx (Pmode); \
2580 emit_move_insn (int_reg, \
2581 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2583 emit_insn (gen_rtx (SET, VOIDmode, \
2585 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
2587 X = gen_rtx (PLUS, Pmode, ptr_reg, \
2588 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
2593 if (TARGET_DEBUG_B_MODE) \
2594 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
2598 /* A C statement or compound statement with a conditional `goto
2599 LABEL;' executed if memory address X (an RTX) can have different
2600 meanings depending on the machine mode of the memory reference it
2603 Autoincrement and autodecrement addresses typically have
2604 mode-dependent effects because the amount of the increment or
2605 decrement is the size of the operand being addressed. Some
2606 machines have other mode-dependent addresses. Many RISC machines
2607 have no mode-dependent addresses.
2609 You may assume that ADDR is a valid address for the machine. */
2611 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2614 /* Define this macro if references to a symbol must be treated
2615 differently depending on something about the variable or
2616 function named by the symbol (such as what section it is in).
2618 The macro definition, if any, is executed immediately after the
2619 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
2620 The value of the rtl will be a `mem' whose address is a
2623 The usual thing for this macro to do is to a flag in the
2624 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
2625 name string in the `symbol_ref' (if one bit is not enough
2628 The best way to modify the name string is by adding text to the
2629 beginning, with suitable punctuation to prevent any ambiguity.
2630 Allocate the new name in `saveable_obstack'. You will have to
2631 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
2632 and output the name accordingly.
2634 You can also check the information stored in the `symbol_ref' in
2635 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
2636 `PRINT_OPERAND_ADDRESS'. */
2638 #define ENCODE_SECTION_INFO(DECL) \
2641 if (TARGET_EMBEDDED_PIC) \
2643 if (TREE_CODE (DECL) == VAR_DECL) \
2644 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2645 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
2646 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
2647 else if (TREE_CODE (DECL) == STRING_CST \
2648 && ! flag_writable_strings) \
2649 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
2651 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
2654 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
2656 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
2658 if (size > 0 && size <= mips_section_threshold) \
2659 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2662 else if (HALF_PIC_P ()) \
2663 HALF_PIC_ENCODE (DECL); \
2668 /* Specify the machine mode that this machine uses
2669 for the index in the tablejump instruction. */
2670 #define CASE_VECTOR_MODE (TARGET_LONG64 ? DImode : SImode)
2672 /* Define this if the tablejump instruction expects the table
2673 to contain offsets from the address of the table.
2674 Do not define this if the table should contain absolute addresses. */
2675 /* #define CASE_VECTOR_PC_RELATIVE */
2677 /* Specify the tree operation to be used to convert reals to integers. */
2678 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2680 /* This is the kind of divide that is easiest to do in the general case. */
2681 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2683 /* Define this as 1 if `char' should by default be signed; else as 0. */
2684 #ifndef DEFAULT_SIGNED_CHAR
2685 #define DEFAULT_SIGNED_CHAR 1
2688 /* Max number of bytes we can move from memory to memory
2689 in one reasonably fast instruction. */
2690 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2691 #define MAX_MOVE_MAX 8
2693 /* Define this macro as a C expression which is nonzero if
2694 accessing less than a word of memory (i.e. a `char' or a
2695 `short') is no faster than accessing a word of memory, i.e., if
2696 such access require more than one instruction or if there is no
2697 difference in cost between byte and (aligned) word loads.
2699 On RISC machines, it tends to generate better code to define
2700 this as 1, since it avoids making a QI or HI mode register. */
2701 #define SLOW_BYTE_ACCESS 1
2703 /* We assume that the store-condition-codes instructions store 0 for false
2704 and some other value for true. This is the value stored for true. */
2706 #define STORE_FLAG_VALUE 1
2708 /* Define this if zero-extension is slow (more than one real instruction). */
2709 #define SLOW_ZERO_EXTEND
2711 /* Define this to be nonzero if shift instructions ignore all but the low-order
2713 #define SHIFT_COUNT_TRUNCATED 1
2715 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2716 is done just by pretending it is already truncated. */
2717 /* In 64 bit mode, 32 bit instructions require that register values be properly
2718 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
2719 converts a value >32 bits to a value <32 bits. */
2720 /* ??? This results in inefficient code for 64 bit to 32 conversions.
2721 Something needs to be done about this. Perhaps not use any 32 bit
2722 instructions? Perhaps use PROMOTE_MODE? */
2723 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2724 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2726 /* Specify the machine mode that pointers have.
2727 After generation of rtl, the compiler makes no further distinction
2728 between pointers and any other objects of this machine mode. */
2730 #define Pmode (TARGET_LONG64 ? DImode : SImode)
2732 /* A function address in a call instruction
2733 is a word address (for indexing purposes)
2734 so give the MEM rtx a words's mode. */
2736 #define FUNCTION_MODE (TARGET_LONG64 ? DImode : SImode)
2738 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
2739 memset, instead of the BSD functions bcopy and bzero. */
2741 #if defined(MIPS_SYSV) || defined(OSF_OS)
2742 #define TARGET_MEM_FUNCTIONS
2746 /* A part of a C `switch' statement that describes the relative
2747 costs of constant RTL expressions. It must contain `case'
2748 labels for expression codes `const_int', `const', `symbol_ref',
2749 `label_ref' and `const_double'. Each case must ultimately reach
2750 a `return' statement to return the relative cost of the use of
2751 that kind of constant value in an expression. The cost may
2752 depend on the precise value of the constant, which is available
2753 for examination in X.
2755 CODE is the expression code--redundant, since it can be obtained
2756 with `GET_CODE (X)'. */
2758 #define CONST_COSTS(X,CODE,OUTER_CODE) \
2760 /* Always return 0, since we don't have different sized \
2761 instructions, hence different costs according to Richard \
2766 return COSTS_N_INSNS (2); \
2770 rtx offset = const0_rtx; \
2771 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
2773 if (GET_CODE (symref) == LABEL_REF) \
2774 return COSTS_N_INSNS (2); \
2776 if (GET_CODE (symref) != SYMBOL_REF) \
2777 return COSTS_N_INSNS (4); \
2779 /* let's be paranoid.... */ \
2780 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
2781 return COSTS_N_INSNS (2); \
2783 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
2787 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
2789 case CONST_DOUBLE: \
2792 split_double (X, &high, &low); \
2793 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
2794 || low == CONST0_RTX (GET_MODE (low))) \
2798 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2799 This can be used, for example, to indicate how costly a multiply
2800 instruction is. In writing this macro, you can use the construct
2801 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
2803 This macro is optional; do not define it if the default cost
2804 assumptions are adequate for the target machine.
2806 If -mdebugd is used, change the multiply cost to 2, so multiply by
2807 a constant isn't converted to a series of shifts. This helps
2808 strength reduction, and also makes it easier to identify what the
2809 compiler is doing. */
2811 /* ??? Fix this to be right for the R8000. */
2812 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2815 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
2816 if (simple_memory_operand (X, GET_MODE (X))) \
2817 return COSTS_N_INSNS (num_words); \
2819 return COSTS_N_INSNS (2*num_words); \
2823 return COSTS_N_INSNS (6); \
2826 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
2831 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
2832 return COSTS_N_INSNS (2); \
2834 return COSTS_N_INSNS (1); \
2839 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
2840 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
2842 return COSTS_N_INSNS (1); \
2846 enum machine_mode xmode = GET_MODE (X); \
2847 if (xmode == SFmode || xmode == DFmode) \
2848 return COSTS_N_INSNS (1); \
2850 return COSTS_N_INSNS (4); \
2856 enum machine_mode xmode = GET_MODE (X); \
2857 if (xmode == SFmode || xmode == DFmode) \
2859 if (mips_cpu == PROCESSOR_R3000) \
2860 return COSTS_N_INSNS (2); \
2861 else if (mips_cpu == PROCESSOR_R6000) \
2862 return COSTS_N_INSNS (3); \
2864 return COSTS_N_INSNS (6); \
2867 if (xmode == DImode && !TARGET_64BIT) \
2868 return COSTS_N_INSNS (4); \
2870 return COSTS_N_INSNS (1); \
2874 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 4 : 1); \
2878 enum machine_mode xmode = GET_MODE (X); \
2879 if (xmode == SFmode) \
2881 if (mips_cpu == PROCESSOR_R3000 \
2882 || mips_cpu == PROCESSOR_R5000) \
2883 return COSTS_N_INSNS (4); \
2884 else if (mips_cpu == PROCESSOR_R6000) \
2885 return COSTS_N_INSNS (5); \
2887 return COSTS_N_INSNS (7); \
2890 if (xmode == DFmode) \
2892 if (mips_cpu == PROCESSOR_R3000 \
2893 || mips_cpu == PROCESSOR_R5000) \
2894 return COSTS_N_INSNS (5); \
2895 else if (mips_cpu == PROCESSOR_R6000) \
2896 return COSTS_N_INSNS (6); \
2898 return COSTS_N_INSNS (8); \
2901 if (mips_cpu == PROCESSOR_R3000) \
2902 return COSTS_N_INSNS (12); \
2903 else if (mips_cpu == PROCESSOR_R6000) \
2904 return COSTS_N_INSNS (17); \
2905 else if (mips_cpu == PROCESSOR_R5000) \
2906 return COSTS_N_INSNS (5); \
2908 return COSTS_N_INSNS (10); \
2914 enum machine_mode xmode = GET_MODE (X); \
2915 if (xmode == SFmode) \
2917 if (mips_cpu == PROCESSOR_R3000) \
2918 return COSTS_N_INSNS (12); \
2919 else if (mips_cpu == PROCESSOR_R6000) \
2920 return COSTS_N_INSNS (15); \
2922 return COSTS_N_INSNS (23); \
2925 if (xmode == DFmode) \
2927 if (mips_cpu == PROCESSOR_R3000) \
2928 return COSTS_N_INSNS (19); \
2929 else if (mips_cpu == PROCESSOR_R6000) \
2930 return COSTS_N_INSNS (16); \
2932 return COSTS_N_INSNS (36); \
2935 /* fall through */ \
2939 if (mips_cpu == PROCESSOR_R3000) \
2940 return COSTS_N_INSNS (35); \
2941 else if (mips_cpu == PROCESSOR_R6000) \
2942 return COSTS_N_INSNS (38); \
2943 else if (mips_cpu == PROCESSOR_R5000) \
2944 return COSTS_N_INSNS (36); \
2946 return COSTS_N_INSNS (69);
2948 /* An expression giving the cost of an addressing mode that
2949 contains ADDRESS. If not defined, the cost is computed from the
2950 form of the ADDRESS expression and the `CONST_COSTS' values.
2952 For most CISC machines, the default cost is a good approximation
2953 of the true cost of the addressing mode. However, on RISC
2954 machines, all instructions normally have the same length and
2955 execution time. Hence all addresses will have equal costs.
2957 In cases where more than one form of an address is known, the
2958 form with the lowest cost will be used. If multiple forms have
2959 the same, lowest, cost, the one that is the most complex will be
2962 For example, suppose an address that is equal to the sum of a
2963 register and a constant is used twice in the same basic block.
2964 When this macro is not defined, the address will be computed in
2965 a register and memory references will be indirect through that
2966 register. On machines where the cost of the addressing mode
2967 containing the sum is no higher than that of a simple indirect
2968 reference, this will produce an additional instruction and
2969 possibly require an additional register. Proper specification
2970 of this macro eliminates this overhead for such machines.
2972 Similar use of this macro is made in strength reduction of loops.
2974 ADDRESS need not be valid as an address. In such a case, the
2975 cost is not relevant and can be any value; invalid addresses
2976 need not be assigned a different cost.
2978 On machines where an address involving more than one register is
2979 as cheap as an address computation involving only one register,
2980 defining `ADDRESS_COST' to reflect this can cause two registers
2981 to be live over a region of code where only one would have been
2982 if `ADDRESS_COST' were not defined in that manner. This effect
2983 should be considered in the definition of this macro.
2984 Equivalent costs should probably only be given to addresses with
2985 different numbers of registers on machines with lots of registers.
2987 This macro will normally either not be defined or be defined as
2990 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
2992 /* A C expression for the cost of moving data from a register in
2993 class FROM to one in class TO. The classes are expressed using
2994 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2995 the default; other values are interpreted relative to that.
2997 It is not required that the cost always equal 2 when FROM is the
2998 same as TO; on some machines it is expensive to move between
2999 registers if they are not general registers.
3001 If reload sees an insn consisting of a single `set' between two
3002 hard registers, and if `REGISTER_MOVE_COST' applied to their
3003 classes returns a value of 2, reload does not check to ensure
3004 that the constraints of the insn are met. Setting a cost of
3005 other than 2 will allow reload to verify that the constraints are
3006 met. You should do this if the `movM' pattern's constraints do
3007 not allow such copying. */
3009 #define REGISTER_MOVE_COST(FROM, TO) \
3010 ((FROM) == GR_REGS && (TO) == GR_REGS ? 2 \
3011 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3012 : (FROM) == GR_REGS && (TO) == FP_REGS ? 4 \
3013 : (FROM) == FP_REGS && (TO) == GR_REGS ? 4 \
3014 : (((FROM) == HI_REG || (FROM) == LO_REG \
3015 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3016 && (TO) == GR_REGS) ? 6 \
3017 : (((TO) == HI_REG || (TO) == LO_REG \
3018 || (TO) == MD_REGS || (FROM) == HILO_REG) \
3019 && (FROM) == GR_REGS) ? 6 \
3020 : (FROM) == ST_REGS && (TO) == GR_REGS ? 4 \
3021 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3024 /* ??? Fix this to be right for the R8000. */
3025 #define MEMORY_MOVE_COST(MODE) \
3026 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4)
3028 /* A C expression for the cost of a branch instruction. A value of
3029 1 is the default; other values are interpreted relative to that. */
3031 /* ??? Fix this to be right for the R8000. */
3032 #define BRANCH_COST \
3033 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 2 : 1)
3035 /* A C statement (sans semicolon) to update the integer variable COST
3036 based on the relationship between INSN that is dependent on
3037 DEP_INSN through the dependence LINK. The default is to make no
3038 adjustment to COST. On the MIPS, ignore the cost of anti- and
3039 output-dependencies. */
3041 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3042 if (REG_NOTE_KIND (LINK) != 0) \
3043 (COST) = 0; /* Anti or output dependence. */
3045 /* Optionally define this if you have added predicates to
3046 `MACHINE.c'. This macro is called within an initializer of an
3047 array of structures. The first field in the structure is the
3048 name of a predicate and the second field is an array of rtl
3049 codes. For each predicate, list all rtl codes that can be in
3050 expressions matched by the predicate. The list should have a
3051 trailing comma. Here is an example of two entries in the list
3052 for a typical RISC machine:
3054 #define PREDICATE_CODES \
3055 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3056 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3058 Defining this macro does not affect the generated code (however,
3059 incorrect definitions that omit an rtl code that may be matched
3060 by the predicate can cause the compiler to malfunction).
3061 Instead, it allows the table built by `genrecog' to be more
3062 compact and efficient, thus speeding up the compiler. The most
3063 important predicates to include in the list specified by this
3064 macro are thoses used in the most insn patterns. */
3066 #define PREDICATE_CODES \
3067 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3068 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3069 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3070 {"reg_or_0_operand", { REG, CONST_INT, SUBREG }}, \
3071 {"small_int", { CONST_INT }}, \
3072 {"large_int", { CONST_INT }}, \
3073 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3074 {"const_float_1_operand", { CONST_DOUBLE }}, \
3075 {"simple_memory_operand", { MEM, SUBREG }}, \
3076 {"equality_op", { EQ, NE }}, \
3077 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3079 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3080 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3081 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3082 SYMBOL_REF, LABEL_REF, SUBREG, \
3086 /* If defined, a C statement to be executed just prior to the
3087 output of assembler code for INSN, to modify the extracted
3088 operands so they will be output differently.
3090 Here the argument OPVEC is the vector containing the operands
3091 extracted from INSN, and NOPERANDS is the number of elements of
3092 the vector which contain meaningful data for this insn. The
3093 contents of this vector are what will be used to convert the
3094 insn template into assembler code, so you can change the
3095 assembler output by changing the contents of the vector.
3097 We use it to check if the current insn needs a nop in front of it
3098 because of load delays, and also to update the delay slot
3101 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3102 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3105 /* Control the assembler format that we output. */
3107 /* Output at beginning of assembler file.
3108 If we are optimizing to use the global pointer, create a temporary
3109 file to hold all of the text stuff, and write it out to the end.
3110 This is needed because the MIPS assembler is evidently one pass,
3111 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3112 declaration when the code is processed, it generates a two
3113 instruction sequence. */
3115 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3117 /* Output to assembler file text saying following lines
3118 may contain character constants, extra white space, comments, etc. */
3120 #define ASM_APP_ON " #APP\n"
3122 /* Output to assembler file text saying following lines
3123 no longer contain unusual constructs. */
3125 #define ASM_APP_OFF " #NO_APP\n"
3127 /* How to refer to registers in assembler output.
3128 This sequence is indexed by compiler's hard-register-number (see above).
3130 In order to support the two different conventions for register names,
3131 we use the name of a table set up in mips.c, which is overwritten
3132 if -mrnames is used. */
3134 #define REGISTER_NAMES \
3136 &mips_reg_names[ 0][0], \
3137 &mips_reg_names[ 1][0], \
3138 &mips_reg_names[ 2][0], \
3139 &mips_reg_names[ 3][0], \
3140 &mips_reg_names[ 4][0], \
3141 &mips_reg_names[ 5][0], \
3142 &mips_reg_names[ 6][0], \
3143 &mips_reg_names[ 7][0], \
3144 &mips_reg_names[ 8][0], \
3145 &mips_reg_names[ 9][0], \
3146 &mips_reg_names[10][0], \
3147 &mips_reg_names[11][0], \
3148 &mips_reg_names[12][0], \
3149 &mips_reg_names[13][0], \
3150 &mips_reg_names[14][0], \
3151 &mips_reg_names[15][0], \
3152 &mips_reg_names[16][0], \
3153 &mips_reg_names[17][0], \
3154 &mips_reg_names[18][0], \
3155 &mips_reg_names[19][0], \
3156 &mips_reg_names[20][0], \
3157 &mips_reg_names[21][0], \
3158 &mips_reg_names[22][0], \
3159 &mips_reg_names[23][0], \
3160 &mips_reg_names[24][0], \
3161 &mips_reg_names[25][0], \
3162 &mips_reg_names[26][0], \
3163 &mips_reg_names[27][0], \
3164 &mips_reg_names[28][0], \
3165 &mips_reg_names[29][0], \
3166 &mips_reg_names[30][0], \
3167 &mips_reg_names[31][0], \
3168 &mips_reg_names[32][0], \
3169 &mips_reg_names[33][0], \
3170 &mips_reg_names[34][0], \
3171 &mips_reg_names[35][0], \
3172 &mips_reg_names[36][0], \
3173 &mips_reg_names[37][0], \
3174 &mips_reg_names[38][0], \
3175 &mips_reg_names[39][0], \
3176 &mips_reg_names[40][0], \
3177 &mips_reg_names[41][0], \
3178 &mips_reg_names[42][0], \
3179 &mips_reg_names[43][0], \
3180 &mips_reg_names[44][0], \
3181 &mips_reg_names[45][0], \
3182 &mips_reg_names[46][0], \
3183 &mips_reg_names[47][0], \
3184 &mips_reg_names[48][0], \
3185 &mips_reg_names[49][0], \
3186 &mips_reg_names[50][0], \
3187 &mips_reg_names[51][0], \
3188 &mips_reg_names[52][0], \
3189 &mips_reg_names[53][0], \
3190 &mips_reg_names[54][0], \
3191 &mips_reg_names[55][0], \
3192 &mips_reg_names[56][0], \
3193 &mips_reg_names[57][0], \
3194 &mips_reg_names[58][0], \
3195 &mips_reg_names[59][0], \
3196 &mips_reg_names[60][0], \
3197 &mips_reg_names[61][0], \
3198 &mips_reg_names[62][0], \
3199 &mips_reg_names[63][0], \
3200 &mips_reg_names[64][0], \
3201 &mips_reg_names[65][0], \
3202 &mips_reg_names[66][0], \
3203 &mips_reg_names[67][0], \
3204 &mips_reg_names[68][0], \
3205 &mips_reg_names[69][0], \
3206 &mips_reg_names[70][0], \
3207 &mips_reg_names[71][0], \
3208 &mips_reg_names[72][0], \
3209 &mips_reg_names[73][0], \
3210 &mips_reg_names[74][0], \
3211 &mips_reg_names[75][0], \
3214 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3215 So define this for it. */
3216 #define DEBUG_REGISTER_NAMES \
3218 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3219 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3220 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3221 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3222 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3223 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3224 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3225 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3226 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3227 "$fcc5","$fcc6","$fcc7","$rap" \
3230 /* If defined, a C initializer for an array of structures
3231 containing a name and a register number. This macro defines
3232 additional names for hard registers, thus allowing the `asm'
3233 option in declarations to refer to registers using alternate
3236 We define both names for the integer registers here. */
3238 #define ADDITIONAL_REGISTER_NAMES \
3240 { "$0", 0 + GP_REG_FIRST }, \
3241 { "$1", 1 + GP_REG_FIRST }, \
3242 { "$2", 2 + GP_REG_FIRST }, \
3243 { "$3", 3 + GP_REG_FIRST }, \
3244 { "$4", 4 + GP_REG_FIRST }, \
3245 { "$5", 5 + GP_REG_FIRST }, \
3246 { "$6", 6 + GP_REG_FIRST }, \
3247 { "$7", 7 + GP_REG_FIRST }, \
3248 { "$8", 8 + GP_REG_FIRST }, \
3249 { "$9", 9 + GP_REG_FIRST }, \
3250 { "$10", 10 + GP_REG_FIRST }, \
3251 { "$11", 11 + GP_REG_FIRST }, \
3252 { "$12", 12 + GP_REG_FIRST }, \
3253 { "$13", 13 + GP_REG_FIRST }, \
3254 { "$14", 14 + GP_REG_FIRST }, \
3255 { "$15", 15 + GP_REG_FIRST }, \
3256 { "$16", 16 + GP_REG_FIRST }, \
3257 { "$17", 17 + GP_REG_FIRST }, \
3258 { "$18", 18 + GP_REG_FIRST }, \
3259 { "$19", 19 + GP_REG_FIRST }, \
3260 { "$20", 20 + GP_REG_FIRST }, \
3261 { "$21", 21 + GP_REG_FIRST }, \
3262 { "$22", 22 + GP_REG_FIRST }, \
3263 { "$23", 23 + GP_REG_FIRST }, \
3264 { "$24", 24 + GP_REG_FIRST }, \
3265 { "$25", 25 + GP_REG_FIRST }, \
3266 { "$26", 26 + GP_REG_FIRST }, \
3267 { "$27", 27 + GP_REG_FIRST }, \
3268 { "$28", 28 + GP_REG_FIRST }, \
3269 { "$29", 29 + GP_REG_FIRST }, \
3270 { "$30", 30 + GP_REG_FIRST }, \
3271 { "$31", 31 + GP_REG_FIRST }, \
3272 { "$sp", 29 + GP_REG_FIRST }, \
3273 { "$fp", 30 + GP_REG_FIRST }, \
3274 { "at", 1 + GP_REG_FIRST }, \
3275 { "v0", 2 + GP_REG_FIRST }, \
3276 { "v1", 3 + GP_REG_FIRST }, \
3277 { "a0", 4 + GP_REG_FIRST }, \
3278 { "a1", 5 + GP_REG_FIRST }, \
3279 { "a2", 6 + GP_REG_FIRST }, \
3280 { "a3", 7 + GP_REG_FIRST }, \
3281 { "t0", 8 + GP_REG_FIRST }, \
3282 { "t1", 9 + GP_REG_FIRST }, \
3283 { "t2", 10 + GP_REG_FIRST }, \
3284 { "t3", 11 + GP_REG_FIRST }, \
3285 { "t4", 12 + GP_REG_FIRST }, \
3286 { "t5", 13 + GP_REG_FIRST }, \
3287 { "t6", 14 + GP_REG_FIRST }, \
3288 { "t7", 15 + GP_REG_FIRST }, \
3289 { "s0", 16 + GP_REG_FIRST }, \
3290 { "s1", 17 + GP_REG_FIRST }, \
3291 { "s2", 18 + GP_REG_FIRST }, \
3292 { "s3", 19 + GP_REG_FIRST }, \
3293 { "s4", 20 + GP_REG_FIRST }, \
3294 { "s5", 21 + GP_REG_FIRST }, \
3295 { "s6", 22 + GP_REG_FIRST }, \
3296 { "s7", 23 + GP_REG_FIRST }, \
3297 { "t8", 24 + GP_REG_FIRST }, \
3298 { "t9", 25 + GP_REG_FIRST }, \
3299 { "k0", 26 + GP_REG_FIRST }, \
3300 { "k1", 27 + GP_REG_FIRST }, \
3301 { "gp", 28 + GP_REG_FIRST }, \
3302 { "sp", 29 + GP_REG_FIRST }, \
3303 { "fp", 30 + GP_REG_FIRST }, \
3304 { "ra", 31 + GP_REG_FIRST }, \
3305 { "$sp", 29 + GP_REG_FIRST }, \
3306 { "$fp", 30 + GP_REG_FIRST } \
3309 /* Define results of standard character escape sequences. */
3310 #define TARGET_BELL 007
3311 #define TARGET_BS 010
3312 #define TARGET_TAB 011
3313 #define TARGET_NEWLINE 012
3314 #define TARGET_VT 013
3315 #define TARGET_FF 014
3316 #define TARGET_CR 015
3318 /* A C compound statement to output to stdio stream STREAM the
3319 assembler syntax for an instruction operand X. X is an RTL
3322 CODE is a value that can be used to specify one of several ways
3323 of printing the operand. It is used when identical operands
3324 must be printed differently depending on the context. CODE
3325 comes from the `%' specification that was used to request
3326 printing of the operand. If the specification was just `%DIGIT'
3327 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3328 is the ASCII code for LTR.
3330 If X is a register, this macro should print the register's name.
3331 The names can be found in an array `reg_names' whose type is
3332 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3334 When the machine description has a specification `%PUNCT' (a `%'
3335 followed by a punctuation character), this macro is called with
3336 a null pointer for X and the punctuation character for CODE.
3338 See mips.c for the MIPS specific codes. */
3340 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3342 /* A C expression which evaluates to true if CODE is a valid
3343 punctuation character for use in the `PRINT_OPERAND' macro. If
3344 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3345 punctuation characters (except for the standard one, `%') are
3346 used in this way. */
3348 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3350 /* A C compound statement to output to stdio stream STREAM the
3351 assembler syntax for an instruction operand that is a memory
3352 reference whose address is ADDR. ADDR is an RTL expression.
3354 On some machines, the syntax for a symbolic address depends on
3355 the section that the address refers to. On these machines,
3356 define the macro `ENCODE_SECTION_INFO' to store the information
3357 into the `symbol_ref', and then check for it here. */
3359 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3362 /* A C statement, to be executed after all slot-filler instructions
3363 have been output. If necessary, call `dbr_sequence_length' to
3364 determine the number of slots filled in a sequence (zero if not
3365 currently outputting a sequence), to decide how many no-ops to
3366 output, or whatever.
3368 Don't define this macro if it has nothing to do, but it is
3369 helpful in reading assembly output if the extent of the delay
3370 sequence is made explicit (e.g. with white space).
3372 Note that output routines for instructions with delay slots must
3373 be prepared to deal with not being output as part of a sequence
3374 (i.e. when the scheduling pass is not run, or when no slot
3375 fillers could be found.) The variable `final_sequence' is null
3376 when not processing a sequence, otherwise it contains the
3377 `sequence' rtx being output. */
3379 #define DBR_OUTPUT_SEQEND(STREAM) \
3382 if (set_nomacro > 0 && --set_nomacro == 0) \
3383 fputs ("\t.set\tmacro\n", STREAM); \
3385 if (set_noreorder > 0 && --set_noreorder == 0) \
3386 fputs ("\t.set\treorder\n", STREAM); \
3388 dslots_jump_filled++; \
3389 fputs ("\n", STREAM); \
3394 /* How to tell the debugger about changes of source files. Note, the
3395 mips ECOFF format cannot deal with changes of files inside of
3396 functions, which means the output of parser generators like bison
3397 is generally not debuggable without using the -l switch. Lose,
3398 lose, lose. Silicon graphics seems to want all .file's hardwired
3401 #ifndef SET_FILE_NUMBER
3402 #define SET_FILE_NUMBER() ++num_source_filenames
3405 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3406 mips_output_filename (STREAM, NAME)
3408 /* This is defined so that it can be overridden in iris6.h. */
3409 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3412 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3413 output_quoted_string (STREAM, NAME); \
3414 fputs ("\n", STREAM); \
3418 /* This is how to output a note the debugger telling it the line number
3419 to which the following sequence of instructions corresponds.
3420 Silicon graphics puts a label after each .loc. */
3422 #ifndef LABEL_AFTER_LOC
3423 #define LABEL_AFTER_LOC(STREAM)
3426 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3427 mips_output_lineno (STREAM, LINE)
3429 /* The MIPS implementation uses some labels for it's own purpose. The
3430 following lists what labels are created, and are all formed by the
3431 pattern $L[a-z].*. The machine independent portion of GCC creates
3432 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3434 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3435 $Lb[0-9]+ Begin blocks for MIPS debug support
3436 $Lc[0-9]+ Label for use in s<xx> operation.
3437 $Le[0-9]+ End blocks for MIPS debug support
3438 $Lp\..+ Half-pic labels. */
3440 /* This is how to output the definition of a user-level label named NAME,
3441 such as the label on a static function or variable NAME.
3443 If we are optimizing the gp, remember that this label has been put
3444 out, so we know not to emit an .extern for it in mips_asm_file_end.
3445 We use one of the common bits in the IDENTIFIER tree node for this,
3446 since those bits seem to be unused, and we don't have any method
3447 of getting the decl nodes from the name. */
3449 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
3451 assemble_name (STREAM, NAME); \
3452 fputs (":\n", STREAM); \
3456 /* A C statement (sans semicolon) to output to the stdio stream
3457 STREAM any text necessary for declaring the name NAME of an
3458 initialized variable which is being defined. This macro must
3459 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3460 The argument DECL is the `VAR_DECL' tree node representing the
3463 If this macro is not defined, then the variable name is defined
3464 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3466 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3469 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3470 HALF_PIC_DECLARE (NAME); \
3475 /* This is how to output a command to make the user-level label named NAME
3476 defined for reference from other files. */
3478 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
3480 fputs ("\t.globl\t", STREAM); \
3481 assemble_name (STREAM, NAME); \
3482 fputs ("\n", STREAM); \
3485 /* This says how to define a global common symbol. */
3487 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
3488 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
3490 /* This says how to define a local common symbol (ie, not visible to
3493 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3494 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
3497 /* This says how to output an external. It would be possible not to
3498 output anything and let undefined symbol become external. However
3499 the assembler uses length information on externals to allocate in
3500 data/sdata bss/sbss, thereby saving exec time. */
3502 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3503 mips_output_external(STREAM,DECL,NAME)
3505 /* This says what to print at the end of the assembly file */
3506 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
3509 /* This is how to declare a function name. The actual work of
3510 emitting the label is moved to function_prologue, so that we can
3511 get the line number correctly emitted before the .ent directive,
3512 and after any .file directives.
3514 Also, switch files if we are optimizing the global pointer. */
3516 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
3518 extern FILE *asm_out_text_file; \
3519 if (TARGET_GP_OPT) \
3521 STREAM = asm_out_text_file; \
3522 /* ??? text_section gets called too soon. If the previous \
3523 function is in a special section and we're not, we have \
3524 to switch back to the text section. We can't call \
3525 text_section again as gcc thinks we're already there. */ \
3526 /* ??? See varasm.c. There are other things that get output \
3527 too early, like alignment (before we've switched STREAM). */ \
3528 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
3529 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
3532 HALF_PIC_DECLARE (NAME); \
3535 /* This is how to output an internal numbered label where
3536 PREFIX is the class of label and NUM is the number within the class. */
3538 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
3539 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
3541 /* This is how to store into the string LABEL
3542 the symbol_ref name of an internal numbered label where
3543 PREFIX is the class of label and NUM is the number within the class.
3544 This is suitable for output with `assemble_name'. */
3546 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3547 sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
3549 /* This is how to output an assembler line defining a `double' constant. */
3551 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
3552 mips_output_double (STREAM, VALUE)
3555 /* This is how to output an assembler line defining a `float' constant. */
3557 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
3558 mips_output_float (STREAM, VALUE)
3561 /* This is how to output an assembler line defining an `int' constant. */
3563 #define ASM_OUTPUT_INT(STREAM,VALUE) \
3565 fprintf (STREAM, "\t.word\t"); \
3566 output_addr_const (STREAM, (VALUE)); \
3567 fprintf (STREAM, "\n"); \
3570 /* Likewise for 64 bit, `char' and `short' constants. */
3572 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
3576 fprintf (STREAM, "\t.dword\t"); \
3577 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
3578 /* We can't use 'X' for negative numbers, because then we won't \
3579 get the right value for the upper 32 bits. */ \
3580 output_addr_const (STREAM, VALUE); \
3582 /* We must use 'X', because otherwise LONG_MIN will print as \
3583 a number that the Irix 6 assembler won't accept. */ \
3584 print_operand (STREAM, VALUE, 'X'); \
3585 fprintf (STREAM, "\n"); \
3589 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
3590 UNITS_PER_WORD, 1); \
3591 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
3592 UNITS_PER_WORD, 1); \
3596 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
3598 fprintf (STREAM, "\t.half\t"); \
3599 output_addr_const (STREAM, (VALUE)); \
3600 fprintf (STREAM, "\n"); \
3603 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
3605 fprintf (STREAM, "\t.byte\t"); \
3606 output_addr_const (STREAM, (VALUE)); \
3607 fprintf (STREAM, "\n"); \
3610 /* This is how to output an assembler line for a numeric constant byte. */
3612 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
3613 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
3615 /* This is how to output an element of a case-vector that is absolute. */
3617 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3618 fprintf (STREAM, "\t%s\t%sL%d\n", \
3619 TARGET_LONG64 ? ".dword" : ".word", \
3620 LOCAL_LABEL_PREFIX, \
3623 /* This is how to output an element of a case-vector that is relative.
3624 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3625 TARGET_EMBEDDED_PIC). */
3627 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, VALUE, REL) \
3629 if (TARGET_EMBEDDED_PIC) \
3630 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3631 TARGET_LONG64 ? ".dword" : ".word", \
3632 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3633 else if (mips_abi == ABI_32) \
3634 fprintf (STREAM, "\t%s\t%sL%d\n", \
3635 TARGET_LONG64 ? ".gpdword" : ".gpword", \
3636 LOCAL_LABEL_PREFIX, VALUE); \
3638 fprintf (STREAM, "\t%s\t%sL%d\n", \
3639 TARGET_LONG64 ? ".dword" : ".word", \
3640 LOCAL_LABEL_PREFIX, VALUE); \
3643 /* When generating embedded PIC code we want to put the jump table in
3644 the .text section. In all other cases, we want to put the jump
3645 table in the .rdata section. Unfortunately, we can't use
3646 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3647 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3648 section if appropriate. */
3649 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3651 if (TARGET_EMBEDDED_PIC) \
3653 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
3656 /* This is how to output an assembler line
3657 that says to advance the location counter
3658 to a multiple of 2**LOG bytes. */
3660 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3662 int mask = (1 << (LOG)) - 1; \
3663 fprintf (STREAM, "\t.align\t%d\n", (LOG)); \
3666 /* This is how to output an assembler line to to advance the location
3667 counter by SIZE bytes. */
3669 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3670 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
3672 /* This is how to output a string. */
3673 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3675 register int i, c, len = (LEN), cur_pos = 17; \
3676 register unsigned char *string = (unsigned char *)(STRING); \
3677 fprintf ((STREAM), "\t.ascii\t\""); \
3678 for (i = 0; i < len; i++) \
3680 register int c = string[i]; \
3686 putc ('\\', (STREAM)); \
3687 putc (c, (STREAM)); \
3691 case TARGET_NEWLINE: \
3692 fputs ("\\n", (STREAM)); \
3694 && (((c = string[i+1]) >= '\040' && c <= '~') \
3695 || c == TARGET_TAB)) \
3696 cur_pos = 32767; /* break right here */ \
3702 fputs ("\\t", (STREAM)); \
3707 fputs ("\\f", (STREAM)); \
3712 fputs ("\\b", (STREAM)); \
3717 fputs ("\\r", (STREAM)); \
3722 if (c >= ' ' && c < 0177) \
3724 putc (c, (STREAM)); \
3729 fprintf ((STREAM), "\\%03o", c); \
3734 if (cur_pos > 72 && i+1 < len) \
3737 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
3740 fprintf ((STREAM), "\"\n"); \
3743 /* Handle certain cpp directives used in header files on sysV. */
3744 #define SCCS_DIRECTIVE
3746 /* Output #ident as a in the read-only data section. */
3747 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3750 int size = strlen (p) + 1; \
3752 assemble_string (p, size); \
3755 /* Default to -G 8 */
3756 #ifndef MIPS_DEFAULT_GVALUE
3757 #define MIPS_DEFAULT_GVALUE 8
3760 /* Define the strings to put out for each section in the object file. */
3761 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3762 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3763 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3764 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3765 #define READONLY_DATA_SECTION rdata_section
3766 #define SMALL_DATA_SECTION sdata_section
3768 /* What other sections we support other than the normal .data/.text. */
3770 #define EXTRA_SECTIONS in_sdata, in_rdata
3772 /* Define the additional functions to select our additional sections. */
3774 /* on the MIPS it is not a good idea to put constants in the text
3775 section, since this defeats the sdata/data mechanism. This is
3776 especially true when -O is used. In this case an effort is made to
3777 address with faster (gp) register relative addressing, which can
3778 only get at sdata and sbss items (there is no stext !!) However,
3779 if the constant is too large for sdata, and it's readonly, it
3780 will go into the .rdata section. */
3782 #define EXTRA_SECTION_FUNCTIONS \
3786 if (in_section != in_sdata) \
3788 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
3789 in_section = in_sdata; \
3796 if (in_section != in_rdata) \
3798 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
3799 in_section = in_rdata; \
3803 /* Given a decl node or constant node, choose the section to output it in
3804 and select that section. */
3806 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
3808 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
3811 /* Store in OUTPUT a string (made with alloca) containing
3812 an assembler-name for a local static variable named NAME.
3813 LABELNO is an integer which is different for each call. */
3815 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
3816 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
3817 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
3819 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3822 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3823 TARGET_64BIT ? "dsubu" : "subu", \
3824 reg_names[STACK_POINTER_REGNUM], \
3825 reg_names[STACK_POINTER_REGNUM], \
3826 TARGET_64BIT ? "sd" : "sw", \
3828 reg_names[STACK_POINTER_REGNUM]); \
3832 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3835 if (! set_noreorder) \
3836 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3838 dslots_load_total++; \
3839 dslots_load_filled++; \
3840 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3841 TARGET_64BIT ? "ld" : "lw", \
3843 reg_names[STACK_POINTER_REGNUM], \
3844 TARGET_64BIT ? "daddu" : "addu", \
3845 reg_names[STACK_POINTER_REGNUM], \
3846 reg_names[STACK_POINTER_REGNUM]); \
3848 if (! set_noreorder) \
3849 fprintf (STREAM, "\t.set\treorder\n"); \
3853 /* Define the parentheses used to group arithmetic operations
3854 in assembler code. */
3856 #define ASM_OPEN_PAREN "("
3857 #define ASM_CLOSE_PAREN ")"
3859 /* How to start an assembler comment.
3860 The leading space is important (the mips native assembler requires it). */
3861 #ifndef ASM_COMMENT_START
3862 #define ASM_COMMENT_START " #"
3866 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
3867 and mips-tdump.c to print them out.
3869 These must match the corresponding definitions in gdb/mipsread.c.
3870 Unfortunately, gcc and gdb do not currently share any directories. */
3872 #define CODE_MASK 0x8F300
3873 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
3874 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
3875 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
3878 /* Default definitions for size_t and ptrdiff_t. */
3881 #define NO_BUILTIN_SIZE_TYPE
3882 #define SIZE_TYPE (TARGET_LONG64 ? "long unsigned int" : "unsigned int")
3885 #ifndef PTRDIFF_TYPE
3886 #define NO_BUILTIN_PTRDIFF_TYPE
3887 #define PTRDIFF_TYPE (TARGET_LONG64 ? "long int" : "int")
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