1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-97, 1998 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern char *language_string;
32 extern int may_call_alloca;
33 extern char **save_argv;
34 extern int target_flags;
35 extern char *version_string;
37 /* MIPS external variables defined in mips.c. */
41 CMP_SI, /* compare four byte integers */
42 CMP_DI, /* compare eight byte integers */
43 CMP_SF, /* compare single precision floats */
44 CMP_DF, /* compare double precision floats */
45 CMP_MAX /* max comparison type */
48 /* types of delay slot */
50 DELAY_NONE, /* no delay slot */
51 DELAY_LOAD, /* load from memory delay */
52 DELAY_HILO, /* move from/to hi/lo registers */
53 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
56 /* Which processor to schedule for. Since there is no difference between
57 a R2000 and R3000 in terms of the scheduler, we collapse them into
58 just an R3000. The elements of the enumeration must match exactly
59 the cpu attribute in the mips.md machine description. */
75 /* Recast the cpu class to be the cpu attribute. */
76 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
78 /* Which ABI to use. These are constants because abi64.h must check their
79 value at preprocessing time.
81 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
82 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
90 #ifndef MIPS_ABI_DEFAULT
91 /* We define this away so that there is no extra runtime cost if the target
92 doesn't support multiple ABIs. */
93 #define mips_abi ABI_32
98 /* Whether to emit abicalls code sequences or not. */
100 enum mips_abicalls_type {
105 /* Recast the abicalls class to be the abicalls attribute. */
106 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
108 /* Which type of block move to do (whether or not the last store is
109 split out so it can fill a branch delay slot). */
111 enum block_move_type {
112 BLOCK_MOVE_NORMAL, /* generate complete block move */
113 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
114 BLOCK_MOVE_LAST /* generate just the last store */
117 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
118 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
119 extern char *current_function_file; /* filename current function is in */
120 extern int num_source_filenames; /* current .file # */
121 extern int inside_function; /* != 0 if inside of a function */
122 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
123 extern int file_in_function_warning; /* warning given about .file in func */
124 extern int sdb_label_count; /* block start/end next label # */
125 extern int sdb_begin_function_line; /* Starting Line of current function */
126 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
127 extern int g_switch_value; /* value of the -G xx switch */
128 extern int g_switch_set; /* whether -G xx was passed. */
129 extern int sym_lineno; /* sgi next label # for each stmt */
130 extern int set_noreorder; /* # of nested .set noreorder's */
131 extern int set_nomacro; /* # of nested .set nomacro's */
132 extern int set_noat; /* # of nested .set noat's */
133 extern int set_volatile; /* # of nested .set volatile's */
134 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
135 extern int mips_dbx_regno[]; /* Map register # to debug register # */
136 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
137 extern enum cmp_type branch_type; /* what type of branch to use */
138 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
139 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
140 extern int mips_isa; /* architectural level */
141 extern int mips16; /* whether generating mips16 code */
142 extern int mips16_hard_float; /* mips16 without -msoft-float */
143 extern int mips_entry; /* generate entry/exit for mips16 */
144 extern char *mips_cpu_string; /* for -mcpu=<xxx> */
145 extern char *mips_isa_string; /* for -mips{1,2,3,4} */
146 extern char *mips_abi_string; /* for -mabi={32,n32,64} */
147 extern char *mips_entry_string; /* for -mentry */
148 extern char *mips_no_mips16_string; /* for -mno-mips16 */
149 extern int mips_split_addresses; /* perform high/lo_sum support */
150 extern int dslots_load_total; /* total # load related delay slots */
151 extern int dslots_load_filled; /* # filled load delay slots */
152 extern int dslots_jump_total; /* total # jump related delay slots */
153 extern int dslots_jump_filled; /* # filled jump delay slots */
154 extern int dslots_number_nops; /* # of nops needed by previous insn */
155 extern int num_refs[3]; /* # 1/2/3 word references */
156 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
157 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
158 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
159 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
160 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
161 extern int mips_string_length; /* length of strings for mips16 */
162 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
164 /* Functions within mips.c that we reference. Some of these return type
165 HOST_WIDE_INT, so define that here. This is a copy of code in machmode.h.
167 ??? It would be good to try to put this as common code someplace. */
169 #ifndef HOST_BITS_PER_WIDE_INT
171 #if HOST_BITS_PER_LONG > HOST_BITS_PER_INT
172 #define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONG
173 #define HOST_WIDE_INT long
175 #define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_INT
176 #define HOST_WIDE_INT int
181 extern void abort_with_insn ();
182 extern int arith32_operand ();
183 extern int arith_operand ();
184 extern int cmp_op ();
185 extern HOST_WIDE_INT compute_frame_size ();
186 extern int const_float_1_operand ();
187 extern void expand_block_move ();
188 extern int equality_op ();
189 extern void final_prescan_insn ();
190 extern struct rtx_def * function_arg ();
191 extern void function_arg_advance ();
192 extern int function_arg_partial_nregs ();
193 extern int function_arg_pass_by_reference ();
194 extern void function_epilogue ();
195 extern void function_prologue ();
196 extern void gen_conditional_branch ();
197 extern void gen_conditional_move ();
198 extern struct rtx_def * gen_int_relational ();
199 extern void init_cumulative_args ();
200 extern int large_int ();
201 extern void machine_dependent_reorg ();
202 extern int mips_address_cost ();
203 extern void mips_asm_file_end ();
204 extern void mips_asm_file_start ();
205 extern int mips_can_use_return_insn ();
206 extern int mips_const_double_ok ();
207 extern void mips_count_memory_refs ();
208 extern HOST_WIDE_INT mips_debugger_offset ();
209 extern void mips_declare_object ();
210 extern int mips_epilogue_delay_slots ();
211 extern void mips_expand_epilogue ();
212 extern void mips_expand_prologue ();
213 extern int mips_check_split ();
214 extern char *mips_fill_delay_slot ();
215 extern char *mips_move_1word ();
216 extern char *mips_move_2words ();
217 extern void mips_output_double ();
218 extern int mips_output_external ();
219 extern void mips_output_float ();
220 extern void mips_output_filename ();
221 extern void mips_output_lineno ();
222 extern char *output_block_move ();
223 extern void override_options ();
224 extern int pc_or_label_operand ();
225 extern void print_operand_address ();
226 extern void print_operand ();
227 extern void print_options ();
228 extern int reg_or_0_operand ();
229 extern int simple_epilogue_p ();
230 extern int simple_memory_operand ();
231 extern int double_memory_operand ();
232 extern int small_int ();
233 extern void trace ();
234 extern int uns_arith_operand ();
235 extern struct rtx_def * embedded_pic_offset ();
236 extern void mips_order_regs_for_local_alloc ();
237 extern struct rtx_def * mips16_gp_pseudo_reg ();
238 extern struct rtx_def * mips16_gp_offset ();
239 extern int mips16_gp_offset_p ();
240 extern int mips16_constant ();
241 extern int mips16_constant_after_function_p ();
242 extern int build_mips16_call_stub ();
244 /* Recognition functions that return if a condition is true. */
245 extern int address_operand ();
246 extern int call_insn_operand ();
247 extern int const_double_operand ();
248 extern int const_int_operand ();
249 extern int consttable_operand ();
250 extern int general_operand ();
251 extern int immediate_operand ();
252 extern int memory_address_p ();
253 extern int memory_operand ();
254 extern int nonimmediate_operand ();
255 extern int nonmemory_operand ();
256 extern int pic_address_needs_scratch ();
257 extern int register_operand ();
258 extern int scratch_operand ();
259 extern int move_operand ();
260 extern int movdi_operand ();
261 extern int se_register_operand ();
262 extern int se_reg_or_0_operand ();
263 extern int se_uns_arith_operand ();
264 extern int se_arith_operand ();
265 extern int se_nonmemory_operand ();
266 extern int se_nonimmediate_operand ();
267 extern int extend_operator ();
268 extern int highpart_shift_operator ();
269 extern int m16_uimm3_b ();
270 extern int m16_simm4_1 ();
271 extern int m16_nsimm4_1 ();
272 extern int m16_simm5_1 ();
273 extern int m16_nsimm5_1 ();
274 extern int m16_uimm5_4 ();
275 extern int m16_nuimm5_4 ();
276 extern int m16_simm8_1 ();
277 extern int m16_nsimm8_1 ();
278 extern int m16_uimm8_1 ();
279 extern int m16_nuimm8_1 ();
280 extern int m16_uimm8_m1_1 ();
281 extern int m16_uimm8_4 ();
282 extern int m16_nuimm8_4 ();
283 extern int m16_simm8_8 ();
284 extern int m16_nsimm8_8 ();
285 extern int m16_usym8_4 ();
286 extern int m16_usym5_4 ();
288 /* Functions to change what output section we are using. */
289 extern void data_section ();
290 extern void rdata_section ();
291 extern void readonly_data_section ();
292 extern void sdata_section ();
293 extern void text_section ();
294 extern void mips_select_rtx_section ();
295 extern void mips_select_section ();
297 /* Stubs for half-pic support if not OSF/1 reference platform. */
300 #define HALF_PIC_P() 0
301 #define HALF_PIC_NUMBER_PTRS 0
302 #define HALF_PIC_NUMBER_REFS 0
303 #define HALF_PIC_ENCODE(DECL)
304 #define HALF_PIC_DECLARE(NAME)
305 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
306 #define HALF_PIC_ADDRESS_P(X) 0
307 #define HALF_PIC_PTR(X) X
308 #define HALF_PIC_FINISH(STREAM)
312 /* Run-time compilation parameters selecting different hardware subsets. */
314 /* Macros used in the machine description to test the flags. */
316 /* Bits for real switches */
317 #define MASK_INT64 0x00000001 /* ints are 64 bits */
318 #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
319 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
320 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
321 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
322 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
323 #define MASK_STATS 0x00000040 /* print statistics to stderr */
324 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
325 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
326 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
327 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
328 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
329 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
330 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
331 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
332 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
333 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
334 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
335 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
336 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
337 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
338 #define MASK_MIPS16 0x01000000 /* Generate mips16 code */
340 /* Dummy switches used only in spec's*/
341 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
343 /* Debug switches, not documented */
344 #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */
345 #define MASK_DEBUG_A 0x20000000 /* don't allow <label>($reg) addrs */
346 #define MASK_DEBUG_B 0x10000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
347 #define MASK_DEBUG_C 0x08000000 /* don't expand seq, etc. */
348 #define MASK_DEBUG_D 0x04000000 /* don't do define_split's */
349 #define MASK_DEBUG_E 0 /* function_arg debug */
350 #define MASK_DEBUG_F 0
351 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
352 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
353 #define MASK_DEBUG_I 0 /* unused */
355 /* r4000 64 bit sizes */
356 #define TARGET_INT64 (target_flags & MASK_INT64)
357 #define TARGET_LONG64 (target_flags & MASK_LONG64)
358 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
359 #define TARGET_64BIT (target_flags & MASK_64BIT)
361 /* Mips vs. GNU linker */
362 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
364 /* generate mips 3900 insns */
365 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
367 /* Mips vs. GNU assembler */
368 #define TARGET_GAS (target_flags & MASK_GAS)
369 #define TARGET_UNIX_ASM (!TARGET_GAS)
370 #define TARGET_MIPS_AS TARGET_UNIX_ASM
373 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
374 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
375 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
376 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
377 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
378 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
379 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
380 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
381 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
382 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
384 /* Reg. Naming in .s ($21 vs. $a0) */
385 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
387 /* Optimize for Sdata/Sbss */
388 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
390 /* print program statistics */
391 #define TARGET_STATS (target_flags & MASK_STATS)
393 /* call memcpy instead of inline code */
394 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
396 /* .abicalls, etc from Pyramid V.4 */
397 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
399 /* OSF pic references to externs */
400 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
402 /* software floating point */
403 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
404 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
406 /* always call through a register */
407 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
409 /* generate embedded PIC code;
411 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
413 /* for embedded systems, optimize for
414 reduced RAM space instead of for
416 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
418 /* generate big endian code. */
419 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
421 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
422 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
424 #define TARGET_MAD (target_flags & MASK_MAD)
426 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
428 /* This is true if we must enable the assembly language file switching
431 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
433 /* We must disable the function end stabs when doing the file switching trick,
434 because the Lscope stabs end up in the wrong place, making it impossible
435 to debug the resulting code. */
436 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
438 /* Generate mips16 code */
439 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
441 /* Macro to define tables used to set the flags.
442 This is a list in braces of pairs in braces,
443 each pair being { "NAME", VALUE }
444 where VALUE is the bits to set or minus the bits to clear.
445 An empty string NAME is used to identify the default VALUE. */
447 #define TARGET_SWITCHES \
449 {"int64", MASK_INT64 | MASK_LONG64}, \
450 {"long64", MASK_LONG64}, \
451 {"split-addresses", MASK_SPLIT_ADDR}, \
452 {"no-split-addresses", -MASK_SPLIT_ADDR}, \
453 {"mips-as", -MASK_GAS}, \
455 {"rnames", MASK_NAME_REGS}, \
456 {"no-rnames", -MASK_NAME_REGS}, \
457 {"gpOPT", MASK_GPOPT}, \
458 {"gpopt", MASK_GPOPT}, \
459 {"no-gpOPT", -MASK_GPOPT}, \
460 {"no-gpopt", -MASK_GPOPT}, \
461 {"stats", MASK_STATS}, \
462 {"no-stats", -MASK_STATS}, \
463 {"memcpy", MASK_MEMCPY}, \
464 {"no-memcpy", -MASK_MEMCPY}, \
465 {"mips-tfile", MASK_MIPS_TFILE}, \
466 {"no-mips-tfile", -MASK_MIPS_TFILE}, \
467 {"soft-float", MASK_SOFT_FLOAT}, \
468 {"hard-float", -MASK_SOFT_FLOAT}, \
469 {"fp64", MASK_FLOAT64}, \
470 {"fp32", -MASK_FLOAT64}, \
471 {"gp64", MASK_64BIT}, \
472 {"gp32", -MASK_64BIT}, \
473 {"abicalls", MASK_ABICALLS}, \
474 {"no-abicalls", -MASK_ABICALLS}, \
475 {"half-pic", MASK_HALF_PIC}, \
476 {"no-half-pic", -MASK_HALF_PIC}, \
477 {"long-calls", MASK_LONG_CALLS}, \
478 {"no-long-calls", -MASK_LONG_CALLS}, \
479 {"embedded-pic", MASK_EMBEDDED_PIC}, \
480 {"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
481 {"embedded-data", MASK_EMBEDDED_DATA}, \
482 {"no-embedded-data", -MASK_EMBEDDED_DATA}, \
483 {"eb", MASK_BIG_ENDIAN}, \
484 {"el", -MASK_BIG_ENDIAN}, \
485 {"single-float", MASK_SINGLE_FLOAT}, \
486 {"double-float", -MASK_SINGLE_FLOAT}, \
488 {"no-mad", -MASK_MAD}, \
489 {"fix4300", MASK_4300_MUL_FIX}, \
490 {"no-fix4300", -MASK_4300_MUL_FIX}, \
491 {"4650", MASK_MAD | MASK_SINGLE_FLOAT}, \
492 {"3900", MASK_MIPS3900}, \
493 {"debug", MASK_DEBUG}, \
494 {"debuga", MASK_DEBUG_A}, \
495 {"debugb", MASK_DEBUG_B}, \
496 {"debugc", MASK_DEBUG_C}, \
497 {"debugd", MASK_DEBUG_D}, \
498 {"debuge", MASK_DEBUG_E}, \
499 {"debugf", MASK_DEBUG_F}, \
500 {"debugg", MASK_DEBUG_G}, \
501 {"debugh", MASK_DEBUG_H}, \
502 {"debugi", MASK_DEBUG_I}, \
503 {"", (TARGET_DEFAULT \
504 | TARGET_CPU_DEFAULT \
505 | TARGET_ENDIAN_DEFAULT)} \
508 /* Default target_flags if no switches are specified */
510 #ifndef TARGET_DEFAULT
511 #define TARGET_DEFAULT 0
514 #ifndef TARGET_CPU_DEFAULT
515 #define TARGET_CPU_DEFAULT 0
518 #ifndef TARGET_ENDIAN_DEFAULT
520 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
522 #define TARGET_ENDIAN_DEFAULT 0
526 #ifndef MULTILIB_DEFAULTS
527 #if TARGET_ENDIAN_DEFAULT == 0
528 #define MULTILIB_DEFAULTS { "EL", "mips1" }
530 #define MULTILIB_DEFAULTS { "EB", "mips1" }
534 /* We must pass -EL to the linker by default for little endian embedded
535 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
536 linker will default to using big-endian output files. The OUTPUT_FORMAT
537 line must be in the linker script, otherwise -EB/-EL will not work. */
539 #ifndef LINKER_ENDIAN_SPEC
540 #if TARGET_ENDIAN_DEFAULT == 0
541 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
543 #define LINKER_ENDIAN_SPEC ""
547 /* This macro is similar to `TARGET_SWITCHES' but defines names of
548 command options that have values. Its definition is an
549 initializer with a subgrouping for each command option.
551 Each subgrouping contains a string constant, that defines the
552 fixed part of the option name, and the address of a variable.
553 The variable, type `char *', is set to the variable part of the
554 given option if the fixed part matches. The actual option name
555 is made by appending `-m' to the specified name.
557 Here is an example which defines `-mshort-data-NUMBER'. If the
558 given option is `-mshort-data-512', the variable `m88k_short_data'
559 will be set to the string `"512"'.
561 extern char *m88k_short_data;
562 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
564 #define TARGET_OPTIONS \
566 SUBTARGET_TARGET_OPTIONS \
567 { "cpu=", &mips_cpu_string }, \
568 { "ips", &mips_isa_string }, \
569 { "entry", &mips_entry_string }, \
570 { "no-mips16", &mips_no_mips16_string } \
573 /* This is meant to be redefined in the host dependent files. */
574 #define SUBTARGET_TARGET_OPTIONS
576 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
578 /* Generate three-operand multiply instructions for both SImode and DImode. */
579 #define GENERATE_MULT3 (TARGET_MIPS3900 \
582 /* Macros to decide whether certain features are available or not,
583 depending on the instruction set architecture level. */
585 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
586 #define HAVE_SQRT_P() (mips_isa >= 2)
588 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
589 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
590 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
591 target_flags, and -mgp64 sets MASK_64BIT.
593 Setting MASK_64BIT in target_flags will cause gcc to assume that
594 registers are 64 bits wide. int, long and void * will be 32 bit;
595 this may be changed with -mint64 or -mlong64.
597 The gen* programs link code that refers to MASK_64BIT. They don't
598 actually use the information in target_flags; they just refer to
601 /* Switch Recognition by gcc.c. Add -G xx support */
603 #ifdef SWITCH_TAKES_ARG
604 #undef SWITCH_TAKES_ARG
607 #define SWITCH_TAKES_ARG(CHAR) \
608 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
610 /* Sometimes certain combinations of command options do not make sense
611 on a particular target machine. You can define a macro
612 `OVERRIDE_OPTIONS' to take account of this. This macro, if
613 defined, is executed once just after all the command options have
616 On the MIPS, it is used to handle -G. We also use it to set up all
617 of the tables referenced in the other macros. */
619 #define OVERRIDE_OPTIONS override_options ()
621 /* Zero or more C statements that may conditionally modify two
622 variables `fixed_regs' and `call_used_regs' (both of type `char
623 []') after they have been initialized from the two preceding
626 This is necessary in case the fixed or call-clobbered registers
627 depend on target flags.
629 You need not define this macro if it has no work to do.
631 If the usage of an entire class of registers depends on the target
632 flags, you may indicate this to GCC by using this macro to modify
633 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
634 the classes which should not be used by GCC. Also define the macro
635 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
636 letter for a class that shouldn't be used.
638 (However, if this class is not included in `GENERAL_REGS' and all
639 of the insn patterns whose constraints permit this class are
640 controlled by target switches, then GCC will automatically avoid
641 using these registers when the target switches are opposed to
644 #define CONDITIONAL_REGISTER_USAGE \
647 if (!TARGET_HARD_FLOAT) \
651 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
652 fixed_regs[regno] = call_used_regs[regno] = 1; \
653 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
654 fixed_regs[regno] = call_used_regs[regno] = 1; \
656 else if (mips_isa < 4) \
660 /* We only have a single condition code register. We \
661 implement this by hiding all the condition code registers, \
662 and generating RTL that refers directly to ST_REG_FIRST. */ \
663 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
664 fixed_regs[regno] = call_used_regs[regno] = 1; \
666 /* In mips16 mode, we permit the $t temporary registers to be used \
667 for reload. We prohibit the unused $s registers, since they \
668 are caller saved, and saving them via a mips16 register would \
669 probably waste more time than just reloading the value. */ \
672 fixed_regs[18] = call_used_regs[18] = 1; \
673 fixed_regs[19] = call_used_regs[19] = 1; \
674 fixed_regs[20] = call_used_regs[20] = 1; \
675 fixed_regs[21] = call_used_regs[21] = 1; \
676 fixed_regs[22] = call_used_regs[22] = 1; \
677 fixed_regs[23] = call_used_regs[23] = 1; \
678 fixed_regs[26] = call_used_regs[26] = 1; \
679 fixed_regs[27] = call_used_regs[27] = 1; \
680 fixed_regs[30] = call_used_regs[30] = 1; \
682 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
686 /* This is meant to be redefined in the host dependent files. */
687 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
689 /* Show we can debug even without a frame pointer. */
690 #define CAN_DEBUG_WITHOUT_FP
692 /* Complain about missing specs and predefines that should be defined in each
693 of the target tm files to override the defaults. This is mostly a place-
694 holder until I can get each of the files updated [mm]. */
696 #if defined(OSF_OS) \
697 || defined(DECSTATION) \
698 || defined(SGI_TARGET) \
699 || defined(MIPS_NEWS) \
700 || defined(MIPS_SYSV) \
701 || defined(MIPS_SVR4) \
702 || defined(MIPS_BSD43)
704 #ifndef CPP_PREDEFINES
705 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
709 #error "Define LIB_SPEC in the appropriate tm.h file"
712 #ifndef STARTFILE_SPEC
713 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
717 #error "Define MACHINE_TYPE in the appropriate tm.h file"
721 /* Tell collect what flags to pass to nm. */
723 #define NM_FLAGS "-Bn"
727 /* Names to predefine in the preprocessor for this target machine. */
729 #ifndef CPP_PREDEFINES
730 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
731 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
732 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
735 /* Assembler specs. */
737 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
740 #define MIPS_AS_ASM_SPEC "\
741 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
742 %{pipe: %e-pipe is not supported.} \
743 %{K} %(subtarget_mips_as_asm_spec)"
745 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
746 rather than gas. It may be overridden by subtargets. */
748 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
749 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
752 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
755 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
757 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
758 GAS_ASM_SPEC as the default, depending upon the value of
761 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
764 #define TARGET_ASM_SPEC "\
765 %{mmips-as: %(mips_as_asm_spec)} \
766 %{!mmips-as: %(gas_asm_spec)}"
770 #define TARGET_ASM_SPEC "\
771 %{!mgas: %(mips_as_asm_spec)} \
772 %{mgas: %(gas_asm_spec)}"
776 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
777 to the assembler. It may be overridden by subtargets. */
778 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
779 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
781 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
784 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
785 the assembler. It may be overridden by subtargets. */
786 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
787 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
788 %{g} %{g0} %{g1} %{g2} %{g3} \
789 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
790 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
791 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
792 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
795 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
796 overridden by subtargets. */
798 #ifndef SUBTARGET_ASM_SPEC
799 #define SUBTARGET_ASM_SPEC ""
802 /* ASM_SPEC is the set of arguments to pass to the assembler. */
805 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
806 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
807 %(subtarget_asm_optimizing_spec) \
808 %(subtarget_asm_debugging_spec) \
810 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
812 %(subtarget_asm_spec)"
814 /* Specify to run a post-processor, mips-tfile after the assembler
815 has run to stuff the mips debug information into the object file.
816 This is needed because the $#!%^ MIPS assembler provides no way
817 of specifying such information in the assembly file. If we are
818 cross compiling, disable mips-tfile unless the user specifies
821 #ifndef ASM_FINAL_SPEC
822 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
824 #define ASM_FINAL_SPEC "\
825 %{mmips-as: %{!mno-mips-tfile: \
826 \n mips-tfile %{v*: -v} \
828 %{!K: %{save-temps: -I %b.o~}} \
829 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
830 %{.s:%i} %{!.s:%g.s}}}"
834 #define ASM_FINAL_SPEC "\
835 %{!mgas: %{!mno-mips-tfile: \
836 \n mips-tfile %{v*: -v} \
838 %{!K: %{save-temps: -I %b.o~}} \
839 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
840 %{.s:%i} %{!.s:%g.s}}}"
843 #endif /* ASM_FINAL_SPEC */
845 /* Redefinition of libraries used. Mips doesn't support normal
846 UNIX style profiling via calling _mcount. It does offer
847 profiling that samples the PC, so do what we can... */
850 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
853 /* Extra switches sometimes passed to the linker. */
854 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
855 will interpret it as a -b option. */
859 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
860 %{bestGnum} %{shared} %{non_shared} \
861 %(linker_endian_spec)"
862 #endif /* LINK_SPEC defined */
864 /* Specs for the compiler proper */
866 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
867 overridden by subtargets. */
868 #ifndef SUBTARGET_CC1_SPEC
869 #define SUBTARGET_CC1_SPEC ""
872 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
876 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
877 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
878 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
879 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
880 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
881 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
882 %{m4650:-mcpu=r4650} \
883 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
884 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
885 %{pic-none: -mno-half-pic} \
886 %{pic-lib: -mhalf-pic} \
887 %{pic-extern: -mhalf-pic} \
888 %{pic-calls: -mhalf-pic} \
890 %(subtarget_cc1_spec) "
893 /* Preprocessor specs. */
895 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
896 be overridden by subtargets. */
898 #ifndef SUBTARGET_CPP_SIZE_SPEC
899 #define SUBTARGET_CPP_SIZE_SPEC "\
900 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
901 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
904 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
905 overridden by subtargets. */
906 #ifndef SUBTARGET_CPP_SPEC
907 #define SUBTARGET_CPP_SPEC ""
910 /* If we're using 64bit longs, then we have to define __LONG_MAX__
911 correctly. Similarly for 64bit ints and __INT_MAX__. */
912 #ifndef LONG_MAX_SPEC
913 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
914 #define LONG_MAX_SPEC "%{!mno-long64:-D__LONG_MAX__=9223372036854775807L}"
916 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
920 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
924 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
925 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
926 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
927 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
928 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
929 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
930 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
931 %(subtarget_cpp_size_spec) \
932 %{mips3:-U__mips -D__mips=3 -D__mips64} \
933 %{mips4:-U__mips -D__mips=4 -D__mips64} \
934 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
935 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
936 %{m4650:%{!msoft-float:-D__mips_single_float}} \
937 %{msoft-float:-D__mips_soft_float} \
938 %{mabi=eabi:-D__mips_eabi} \
939 %{mips16:%{!mno-mips16:-D__mips16}} \
940 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
941 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
943 %(subtarget_cpp_spec) "
946 /* This macro defines names of additional specifications to put in the specs
947 that can be used in various specifications like CC1_SPEC. Its definition
948 is an initializer with a subgrouping for each command option.
950 Each subgrouping contains a string constant, that defines the
951 specification name, and a string constant that used by the GNU CC driver
954 Do not define this macro if it does not need to do anything. */
956 #define EXTRA_SPECS \
957 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
958 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
959 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
960 { "long_max_spec", LONG_MAX_SPEC }, \
961 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
962 { "gas_asm_spec", GAS_ASM_SPEC }, \
963 { "target_asm_spec", TARGET_ASM_SPEC }, \
964 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
965 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
966 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
967 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
968 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
969 SUBTARGET_EXTRA_SPECS
971 #ifndef SUBTARGET_EXTRA_SPECS
972 #define SUBTARGET_EXTRA_SPECS
975 /* If defined, this macro is an additional prefix to try after
976 `STANDARD_EXEC_PREFIX'. */
978 #ifndef MD_EXEC_PREFIX
979 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
982 #ifndef MD_STARTFILE_PREFIX
983 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
987 /* Print subsidiary information on the compiler version in use. */
989 #define MIPS_VERSION "[AL 1.1, MM 40]"
992 #define MACHINE_TYPE "BSD Mips"
995 #ifndef TARGET_VERSION_INTERNAL
996 #define TARGET_VERSION_INTERNAL(STREAM) \
997 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1000 #ifndef TARGET_VERSION
1001 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1005 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1006 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1007 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1009 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1010 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1013 /* By default, turn on GDB extensions. */
1014 #define DEFAULT_GDB_EXTENSIONS 1
1016 /* If we are passing smuggling stabs through the MIPS ECOFF object
1017 format, put a comment in front of the .stab<x> operation so
1018 that the MIPS assembler does not choke. The mips-tfile program
1019 will correctly put the stab into the object file. */
1021 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
1022 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
1023 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
1025 /* Local compiler-generated symbols must have a prefix that the assembler
1026 understands. By default, this is $, although some targets (e.g.,
1027 NetBSD-ELF) need to override this. */
1029 #ifndef LOCAL_LABEL_PREFIX
1030 #define LOCAL_LABEL_PREFIX "$"
1033 /* By default on the mips, external symbols do not have an underscore
1034 prepended, but some targets (e.g., NetBSD) require this. */
1036 #ifndef USER_LABEL_PREFIX
1037 #define USER_LABEL_PREFIX ""
1040 /* Forward references to tags are allowed. */
1041 #define SDB_ALLOW_FORWARD_REFERENCES
1043 /* Unknown tags are also allowed. */
1044 #define SDB_ALLOW_UNKNOWN_REFERENCES
1046 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1047 since the length can run past this up to a continuation point. */
1048 #define DBX_CONTIN_LENGTH 1500
1050 /* How to renumber registers for dbx and gdb. */
1051 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1053 /* The mapping from gcc register number to DWARF 2 CFA column number.
1054 This mapping does not allow for tracking register 0, since SGI's broken
1055 dwarf reader thinks column 0 is used for the frame address, but since
1056 register 0 is fixed this is not a problem. */
1057 #define DWARF_FRAME_REGNUM(REG) \
1058 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1060 /* The DWARF 2 CFA column which tracks the return address. */
1061 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1063 /* Before the prologue, RA lives in r31. */
1064 #define INCOMING_RETURN_ADDR_RTX gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
1066 /* Overrides for the COFF debug format. */
1067 #define PUT_SDB_SCL(a) \
1069 extern FILE *asm_out_text_file; \
1070 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1073 #define PUT_SDB_INT_VAL(a) \
1075 extern FILE *asm_out_text_file; \
1076 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1079 #define PUT_SDB_VAL(a) \
1081 extern FILE *asm_out_text_file; \
1082 fputs ("\t.val\t", asm_out_text_file); \
1083 output_addr_const (asm_out_text_file, (a)); \
1084 fputc (';', asm_out_text_file); \
1087 #define PUT_SDB_DEF(a) \
1089 extern FILE *asm_out_text_file; \
1090 fprintf (asm_out_text_file, "\t%s.def\t", \
1091 (TARGET_GAS) ? "" : "#"); \
1092 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1093 fputc (';', asm_out_text_file); \
1096 #define PUT_SDB_PLAIN_DEF(a) \
1098 extern FILE *asm_out_text_file; \
1099 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1100 (TARGET_GAS) ? "" : "#", (a)); \
1103 #define PUT_SDB_ENDEF \
1105 extern FILE *asm_out_text_file; \
1106 fprintf (asm_out_text_file, "\t.endef\n"); \
1109 #define PUT_SDB_TYPE(a) \
1111 extern FILE *asm_out_text_file; \
1112 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1115 #define PUT_SDB_SIZE(a) \
1117 extern FILE *asm_out_text_file; \
1118 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1121 #define PUT_SDB_DIM(a) \
1123 extern FILE *asm_out_text_file; \
1124 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1127 #ifndef PUT_SDB_START_DIM
1128 #define PUT_SDB_START_DIM \
1130 extern FILE *asm_out_text_file; \
1131 fprintf (asm_out_text_file, "\t.dim\t"); \
1135 #ifndef PUT_SDB_NEXT_DIM
1136 #define PUT_SDB_NEXT_DIM(a) \
1138 extern FILE *asm_out_text_file; \
1139 fprintf (asm_out_text_file, "%d,", a); \
1143 #ifndef PUT_SDB_LAST_DIM
1144 #define PUT_SDB_LAST_DIM(a) \
1146 extern FILE *asm_out_text_file; \
1147 fprintf (asm_out_text_file, "%d;", a); \
1151 #define PUT_SDB_TAG(a) \
1153 extern FILE *asm_out_text_file; \
1154 fprintf (asm_out_text_file, "\t.tag\t"); \
1155 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1156 fputc (';', asm_out_text_file); \
1159 /* For block start and end, we create labels, so that
1160 later we can figure out where the correct offset is.
1161 The normal .ent/.end serve well enough for functions,
1162 so those are just commented out. */
1164 #define PUT_SDB_BLOCK_START(LINE) \
1166 extern FILE *asm_out_text_file; \
1167 fprintf (asm_out_text_file, \
1168 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1169 LOCAL_LABEL_PREFIX, \
1171 (TARGET_GAS) ? "" : "#", \
1172 LOCAL_LABEL_PREFIX, \
1175 sdb_label_count++; \
1178 #define PUT_SDB_BLOCK_END(LINE) \
1180 extern FILE *asm_out_text_file; \
1181 fprintf (asm_out_text_file, \
1182 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1183 LOCAL_LABEL_PREFIX, \
1185 (TARGET_GAS) ? "" : "#", \
1186 LOCAL_LABEL_PREFIX, \
1189 sdb_label_count++; \
1192 #define PUT_SDB_FUNCTION_START(LINE)
1194 #define PUT_SDB_FUNCTION_END(LINE) \
1196 extern FILE *asm_out_text_file; \
1197 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1200 #define PUT_SDB_EPILOGUE_END(NAME)
1202 #define PUT_SDB_SRC_FILE(FILENAME) \
1204 extern FILE *asm_out_text_file; \
1205 output_file_directive (asm_out_text_file, (FILENAME)); \
1208 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1209 sprintf ((BUFFER), ".%dfake", (NUMBER));
1211 /* Correct the offset of automatic variables and arguments. Note that
1212 the MIPS debug format wants all automatic variables and arguments
1213 to be in terms of the virtual frame pointer (stack pointer before
1214 any adjustment in the function), while the MIPS 3.0 linker wants
1215 the frame pointer to be the stack pointer after the initial
1218 #define DEBUGGER_AUTO_OFFSET(X) \
1219 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1220 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1221 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1223 /* Tell collect that the object format is ECOFF */
1224 #ifndef OBJECT_FORMAT_ROSE
1225 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1226 #define EXTENDED_COFF /* ECOFF, not normal coff */
1229 #if 0 /* These definitions normally have no effect because
1230 MIPS systems define USE_COLLECT2, so
1231 assemble_constructor does nothing anyway. */
1233 /* Don't use the default definitions, because we don't have gld.
1234 Also, we don't want stabs when generating ECOFF output.
1235 Instead we depend on collect to handle these. */
1237 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1238 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1242 /* Target machine storage layout */
1244 /* Define in order to support both big and little endian float formats
1245 in the same gcc binary. */
1246 #define REAL_ARITHMETIC
1248 /* Define this if most significant bit is lowest numbered
1249 in instructions that operate on numbered bit-fields.
1251 #define BITS_BIG_ENDIAN 0
1253 /* Define this if most significant byte of a word is the lowest numbered. */
1254 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1256 /* Define this if most significant word of a multiword number is the lowest. */
1257 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1259 /* Define this to set the endianness to use in libgcc2.c, which can
1260 not depend on target_flags. */
1261 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1262 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1264 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1267 /* Number of bits in an addressable storage unit */
1268 #define BITS_PER_UNIT 8
1270 /* Width in bits of a "word", which is the contents of a machine register.
1271 Note that this is not necessarily the width of data type `int';
1272 if using 16-bit ints on a 68000, this would still be 32.
1273 But on a machine with 16-bit registers, this would be 16. */
1274 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1275 #define MAX_BITS_PER_WORD 64
1277 /* Width of a word, in units (bytes). */
1278 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1279 #define MIN_UNITS_PER_WORD 4
1281 /* For MIPS, width of a floating point register. */
1282 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1284 /* A C expression for the size in bits of the type `int' on the
1285 target machine. If you don't define this, the default is one
1287 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1288 #define MAX_INT_TYPE_SIZE 64
1290 /* Tell the preprocessor the maximum size of wchar_t. */
1291 #ifndef MAX_WCHAR_TYPE_SIZE
1292 #ifndef WCHAR_TYPE_SIZE
1293 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1297 /* A C expression for the size in bits of the type `short' on the
1298 target machine. If you don't define this, the default is half a
1299 word. (If this would be less than one storage unit, it is
1300 rounded up to one unit.) */
1301 #define SHORT_TYPE_SIZE 16
1303 /* A C expression for the size in bits of the type `long' on the
1304 target machine. If you don't define this, the default is one
1306 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1307 #define MAX_LONG_TYPE_SIZE 64
1309 /* A C expression for the size in bits of the type `long long' on the
1310 target machine. If you don't define this, the default is two
1312 #define LONG_LONG_TYPE_SIZE 64
1314 /* A C expression for the size in bits of the type `char' on the
1315 target machine. If you don't define this, the default is one
1316 quarter of a word. (If this would be less than one storage unit,
1317 it is rounded up to one unit.) */
1318 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1320 /* A C expression for the size in bits of the type `float' on the
1321 target machine. If you don't define this, the default is one
1323 #define FLOAT_TYPE_SIZE 32
1325 /* A C expression for the size in bits of the type `double' on the
1326 target machine. If you don't define this, the default is two
1328 #define DOUBLE_TYPE_SIZE 64
1330 /* A C expression for the size in bits of the type `long double' on
1331 the target machine. If you don't define this, the default is two
1333 #define LONG_DOUBLE_TYPE_SIZE 64
1335 /* Width in bits of a pointer.
1336 See also the macro `Pmode' defined below. */
1337 #ifndef POINTER_SIZE
1338 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1341 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1342 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1344 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1345 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1347 /* Allocation boundary (in *bits*) for the code of a function. */
1348 #define FUNCTION_BOUNDARY 32
1350 /* Alignment of field after `int : 0' in a structure. */
1351 #define EMPTY_FIELD_BOUNDARY 32
1353 /* Every structure's size must be a multiple of this. */
1354 /* 8 is observed right on a DECstation and on riscos 4.02. */
1355 #define STRUCTURE_SIZE_BOUNDARY 8
1357 /* There is no point aligning anything to a rounder boundary than this. */
1358 #define BIGGEST_ALIGNMENT 64
1360 /* Set this nonzero if move instructions will actually fail to work
1361 when given unaligned data. */
1362 #define STRICT_ALIGNMENT 1
1364 /* Define this if you wish to imitate the way many other C compilers
1365 handle alignment of bitfields and the structures that contain
1368 The behavior is that the type written for a bitfield (`int',
1369 `short', or other integer type) imposes an alignment for the
1370 entire structure, as if the structure really did contain an
1371 ordinary field of that type. In addition, the bitfield is placed
1372 within the structure so that it would fit within such a field,
1373 not crossing a boundary for it.
1375 Thus, on most machines, a bitfield whose type is written as `int'
1376 would not cross a four-byte boundary, and would force four-byte
1377 alignment for the whole structure. (The alignment used may not
1378 be four bytes; it is controlled by the other alignment
1381 If the macro is defined, its definition should be a C expression;
1382 a nonzero value for the expression enables this behavior. */
1384 #define PCC_BITFIELD_TYPE_MATTERS 1
1386 /* If defined, a C expression to compute the alignment given to a
1387 constant that is being placed in memory. CONSTANT is the constant
1388 and ALIGN is the alignment that the object would ordinarily have.
1389 The value of this macro is used instead of that alignment to align
1392 If this macro is not defined, then ALIGN is used.
1394 The typical use of this macro is to increase alignment for string
1395 constants to be word aligned so that `strcpy' calls that copy
1396 constants can be done inline. */
1398 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1399 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1400 && (ALIGN) < BITS_PER_WORD \
1404 /* If defined, a C expression to compute the alignment for a static
1405 variable. TYPE is the data type, and ALIGN is the alignment that
1406 the object would ordinarily have. The value of this macro is used
1407 instead of that alignment to align the object.
1409 If this macro is not defined, then ALIGN is used.
1411 One use of this macro is to increase alignment of medium-size
1412 data to make it all fit in fewer cache lines. Another is to
1413 cause character arrays to be word-aligned so that `strcpy' calls
1414 that copy constants to character arrays can be done inline. */
1416 #undef DATA_ALIGNMENT
1417 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1418 ((((ALIGN) < BITS_PER_WORD) \
1419 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1420 || TREE_CODE (TYPE) == UNION_TYPE \
1421 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1423 /* Define this macro if an argument declared as `char' or `short' in a
1424 prototype should actually be passed as an `int'. In addition to
1425 avoiding errors in certain cases of mismatch, it also makes for
1426 better code on certain machines. */
1428 #define PROMOTE_PROTOTYPES
1430 /* Define if operations between registers always perform the operation
1431 on the full register even if a narrower mode is specified. */
1432 #define WORD_REGISTER_OPERATIONS
1434 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1435 will either zero-extend or sign-extend. The value of this macro should
1436 be the code that says which one of the two operations is implicitly
1437 done, NIL if none. */
1438 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1440 /* Define this macro if it is advisable to hold scalars in registers
1441 in a wider mode than that declared by the program. In such cases,
1442 the value is constrained to be within the bounds of the declared
1443 type, but kept valid in the wider mode. The signedness of the
1444 extension may differ from that of the type.
1446 We promote any value smaller than SImode up to SImode. We don't
1447 want to promote to DImode when in 64 bit mode, because that would
1448 prevent us from using the faster SImode multiply and divide
1451 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1452 if (GET_MODE_CLASS (MODE) == MODE_INT \
1453 && GET_MODE_SIZE (MODE) < 4) \
1456 /* Define this if function arguments should also be promoted using the above
1459 #define PROMOTE_FUNCTION_ARGS
1461 /* Likewise, if the function return value is promoted. */
1463 #define PROMOTE_FUNCTION_RETURN
1465 /* Standard register usage. */
1467 /* Number of actual hardware registers.
1468 The hardware registers are assigned numbers for the compiler
1469 from 0 to just below FIRST_PSEUDO_REGISTER.
1470 All registers that the compiler knows about must be given numbers,
1471 even those that are not normally considered general registers.
1473 On the Mips, we have 32 integer registers, 32 floating point
1474 registers, 8 condition code registers, and the special registers
1475 hi, lo, hilo, and rap. The 8 condition code registers are only
1476 used if mips_isa >= 4. The hilo register is only used in 64 bit
1477 mode. It represents a 64 bit value stored as two 32 bit values in
1478 the hi and lo registers; this is the result of the mult
1479 instruction. rap is a pointer to the stack where the return
1480 address reg ($31) was stored. This is needed for C++ exception
1483 #define FIRST_PSEUDO_REGISTER 76
1485 /* 1 for registers that have pervasive standard uses
1486 and are not available for the register allocator.
1488 On the MIPS, see conventions, page D-2 */
1490 #define FIXED_REGISTERS \
1492 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1493 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1494 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1495 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1496 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1500 /* 1 for registers not available across function calls.
1501 These must include the FIXED_REGISTERS and also any
1502 registers that can be used without being saved.
1503 The latter must include the registers where values are returned
1504 and the register where structure-value addresses are passed.
1505 Aside from that, you can include as many other registers as you like. */
1507 #define CALL_USED_REGISTERS \
1509 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1510 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1511 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1512 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1513 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1517 /* Internal macros to classify a register number as to whether it's a
1518 general purpose register, a floating point register, a
1519 multiply/divide register, or a status register. */
1521 #define GP_REG_FIRST 0
1522 #define GP_REG_LAST 31
1523 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1524 #define GP_DBX_FIRST 0
1526 #define FP_REG_FIRST 32
1527 #define FP_REG_LAST 63
1528 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1529 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1531 #define MD_REG_FIRST 64
1532 #define MD_REG_LAST 66
1533 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1535 #define ST_REG_FIRST 67
1536 #define ST_REG_LAST 74
1537 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1539 #define RAP_REG_NUM 75
1541 #define AT_REGNUM (GP_REG_FIRST + 1)
1542 #define HI_REGNUM (MD_REG_FIRST + 0)
1543 #define LO_REGNUM (MD_REG_FIRST + 1)
1544 #define HILO_REGNUM (MD_REG_FIRST + 2)
1546 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1547 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1548 should be used instead. */
1549 #define FPSW_REGNUM ST_REG_FIRST
1551 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1552 #define M16_REG_P(REGNO) \
1553 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1554 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1555 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1556 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1558 /* Return number of consecutive hard regs needed starting at reg REGNO
1559 to hold something of mode MODE.
1560 This is ordinarily the length in words of a value of mode MODE
1561 but can be less for certain modes in special long registers.
1563 On the MIPS, all general registers are one word long. Except on
1564 the R4000 with the FR bit set, the floating point uses register
1565 pairs, with the second register not being allocable. */
1567 #define HARD_REGNO_NREGS(REGNO, MODE) \
1568 (! FP_REG_P (REGNO) \
1569 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1570 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1572 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1573 MODE. In 32 bit mode, require that DImode and DFmode be in even
1574 registers. For DImode, this makes some of the insns easier to
1575 write, since you don't have to worry about a DImode value in
1576 registers 3 & 4, producing a result in 4 & 5.
1578 To make the code simpler HARD_REGNO_MODE_OK now just references an
1579 array built in override_options. Because machmodes.h is not yet
1580 included before this file is processed, the MODE bound can't be
1583 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1585 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1586 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1588 /* Value is 1 if it is a good idea to tie two pseudo registers
1589 when one has mode MODE1 and one has mode MODE2.
1590 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1591 for any hard reg, then this must be 0 for correct output. */
1592 #define MODES_TIEABLE_P(MODE1, MODE2) \
1593 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1594 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1595 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1596 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1598 /* MIPS pc is not overloaded on a register. */
1599 /* #define PC_REGNUM xx */
1601 /* Register to use for pushing function arguments. */
1602 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1604 /* Offset from the stack pointer to the first available location. Use
1605 the default value zero. */
1606 /* #define STACK_POINTER_OFFSET 0 */
1608 /* Base register for access to local variables of the function. We
1609 pretend that the frame pointer is $1, and then eliminate it to
1610 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1611 a fixed register, and will not be used for anything else. */
1612 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1614 /* $30 is not available on the mips16, so we use $17 as the frame
1616 #define HARD_FRAME_POINTER_REGNUM \
1617 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1619 /* Value should be nonzero if functions must have frame pointers.
1620 Zero means the frame pointer need not be set up (and parms
1621 may be accessed via the stack pointer) in functions that seem suitable.
1622 This is computed in `reload', in reload1.c. */
1623 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1625 /* Base register for access to arguments of the function. */
1626 #define ARG_POINTER_REGNUM GP_REG_FIRST
1628 /* Fake register that holds the address on the stack of the
1629 current function's return address. */
1630 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1632 /* Register in which static-chain is passed to a function. */
1633 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1635 /* If the structure value address is passed in a register, then
1636 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1637 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1639 /* If the structure value address is not passed in a register, define
1640 `STRUCT_VALUE' as an expression returning an RTX for the place
1641 where the address is passed. If it returns 0, the address is
1642 passed as an "invisible" first argument. */
1643 #define STRUCT_VALUE 0
1645 /* Mips registers used in prologue/epilogue code when the stack frame
1646 is larger than 32K bytes. These registers must come from the
1647 scratch register set, and not used for passing and returning
1648 arguments and any other information used in the calling sequence
1649 (such as pic). Must start at 12, since t0/t3 are parameter passing
1650 registers in the 64 bit ABI. */
1652 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1653 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1655 /* Define this macro if it is as good or better to call a constant
1656 function address than to call an address kept in a register. */
1657 #define NO_FUNCTION_CSE 1
1659 /* Define this macro if it is as good or better for a function to
1660 call itself with an explicit address than to call an address
1661 kept in a register. */
1662 #define NO_RECURSIVE_FUNCTION_CSE 1
1664 /* The register number of the register used to address a table of
1665 static data addresses in memory. In some cases this register is
1666 defined by a processor's "application binary interface" (ABI).
1667 When this macro is defined, RTL is generated for this register
1668 once, as with the stack pointer and frame pointer registers. If
1669 this macro is not defined, it is up to the machine-dependent
1670 files to allocate such a register (if necessary). */
1671 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1673 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1675 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1676 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1677 isn't always called for static inline functions. */
1678 #define INIT_EXPANDERS \
1680 embedded_pic_fnaddr_rtx = NULL; \
1681 mips16_gp_pseudo_rtx = NULL; \
1684 /* Define the classes of registers for register constraints in the
1685 machine description. Also define ranges of constants.
1687 One of the classes must always be named ALL_REGS and include all hard regs.
1688 If there is more than one class, another class must be named NO_REGS
1689 and contain no registers.
1691 The name GENERAL_REGS must be the name of a class (or an alias for
1692 another name such as ALL_REGS). This is the class of registers
1693 that is allowed by "g" or "r" in a register constraint.
1694 Also, registers outside this class are allocated only when
1695 instructions express preferences for them.
1697 The classes must be numbered in nondecreasing order; that is,
1698 a larger-numbered class must never be contained completely
1699 in a smaller-numbered class.
1701 For any two classes, it is very desirable that there be another
1702 class that represents their union. */
1706 NO_REGS, /* no registers in set */
1707 M16_NA_REGS, /* mips16 regs not used to pass args */
1708 M16_REGS, /* mips16 directly accessible registers */
1709 T_REG, /* mips16 T register ($24) */
1710 M16_T_REGS, /* mips16 registers plus T register */
1711 GR_REGS, /* integer registers */
1712 FP_REGS, /* floating point registers */
1713 HI_REG, /* hi register */
1714 LO_REG, /* lo register */
1715 HILO_REG, /* hilo register pair for 64 bit mode mult */
1716 MD_REGS, /* multiply/divide registers (hi/lo) */
1717 HI_AND_GR_REGS, /* union classes */
1720 ST_REGS, /* status registers (fp status) */
1721 ALL_REGS, /* all registers */
1722 LIM_REG_CLASSES /* max value + 1 */
1725 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1727 #define GENERAL_REGS GR_REGS
1729 /* An initializer containing the names of the register classes as C
1730 string constants. These names are used in writing some of the
1733 #define REG_CLASS_NAMES \
1748 "HILO_AND_GR_REGS", \
1753 /* An initializer containing the contents of the register classes,
1754 as integers which are bit masks. The Nth integer specifies the
1755 contents of class N. The way the integer MASK is interpreted is
1756 that register R is in the class if `MASK & (1 << R)' is 1.
1758 When the machine has more than 32 registers, an integer does not
1759 suffice. Then the integers are replaced by sub-initializers,
1760 braced groupings containing several integers. Each
1761 sub-initializer must be suitable as an initializer for the type
1762 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1764 #define REG_CLASS_CONTENTS \
1766 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1767 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1768 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1769 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1770 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1771 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1772 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1773 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1774 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1775 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1776 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1777 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1778 { 0xffffffff, 0x00000000, 0x00000002 }, \
1779 { 0xffffffff, 0x00000000, 0x00000004 }, \
1780 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1781 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1785 /* A C expression whose value is a register class containing hard
1786 register REGNO. In general there is more that one such class;
1787 choose a class which is "minimal", meaning that no smaller class
1788 also contains the register. */
1790 extern enum reg_class mips_regno_to_class[];
1792 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1794 /* A macro whose definition is the name of the class to which a
1795 valid base register must belong. A base register is one used in
1796 an address which is the register value plus a displacement. */
1798 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1800 /* A macro whose definition is the name of the class to which a
1801 valid index register must belong. An index register is one used
1802 in an address where its value is either multiplied by a scale
1803 factor or added to another register (as well as added to a
1806 #define INDEX_REG_CLASS NO_REGS
1808 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1809 registers explicitly used in the rtl to be used as spill registers
1810 but prevents the compiler from extending the lifetime of these
1813 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1815 /* This macro is used later on in the file. */
1816 #define GR_REG_CLASS_P(CLASS) \
1817 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1818 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1820 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1821 is the default value (allocate the registers in numeric order). We
1822 define it just so that we can override it for the mips16 target in
1823 ORDER_REGS_FOR_LOCAL_ALLOC. */
1825 #define REG_ALLOC_ORDER \
1826 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1827 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1828 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1829 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1830 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1833 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1834 to be rearranged based on a particular function. On the mips16, we
1835 want to allocate $24 (T_REG) before other registers for
1836 instructions for which it is possible. */
1838 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1840 /* REGISTER AND CONSTANT CLASSES */
1842 /* Get reg_class from a letter such as appears in the machine
1845 DEFINED REGISTER CLASSES:
1847 'd' General (aka integer) registers
1848 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1849 'y' General registers (in both mips16 and non mips16 mode)
1850 'e' mips16 non argument registers (M16_NA_REGS)
1851 't' mips16 temporary register ($24)
1852 'f' Floating point registers
1855 'x' Multiply/divide registers
1857 'z' FP Status register
1858 'b' All registers */
1860 extern enum reg_class mips_char_to_class[];
1862 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1864 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1865 string can be used to stand for particular ranges of immediate
1866 operands. This macro defines what the ranges are. C is the
1867 letter, and VALUE is a constant value. Return 1 if VALUE is
1868 in the range specified by C. */
1872 `I' is used for the range of constants an arithmetic insn can
1873 actually contain (16 bits signed integers).
1875 `J' is used for the range which is just zero (ie, $r0).
1877 `K' is used for the range of constants a logical insn can actually
1878 contain (16 bit zero-extended integers).
1880 `L' is used for the range of constants that be loaded with lui
1881 (ie, the bottom 16 bits are zero).
1883 `M' is used for the range of constants that take two words to load
1884 (ie, not matched by `I', `K', and `L').
1886 `N' is used for negative 16 bit constants other than -65536.
1888 `O' is a 15 bit signed integer.
1890 `P' is used for positive 16 bit constants. */
1892 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1893 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1895 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1896 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1897 : (C) == 'J' ? ((VALUE) == 0) \
1898 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1899 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1900 && (((VALUE) & ~2147483647) == 0 \
1901 || ((VALUE) & ~2147483647) == ~2147483647)) \
1902 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1903 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1904 && (((VALUE) & 0x0000ffff) != 0 \
1905 || (((VALUE) & ~2147483647) != 0 \
1906 && ((VALUE) & ~2147483647) != ~2147483647))) \
1907 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1908 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1909 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1912 /* Similar, but for floating constants, and defining letters G and H.
1913 Here VALUE is the CONST_DOUBLE rtx itself. */
1917 'G' : Floating point 0 */
1919 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1921 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1923 /* Letters in the range `Q' through `U' may be defined in a
1924 machine-dependent fashion to stand for arbitrary operand types.
1925 The machine description macro `EXTRA_CONSTRAINT' is passed the
1926 operand as its first argument and the constraint letter as its
1929 `Q' is for mips16 GP relative constants
1930 `R' is for memory references which take 1 word for the instruction.
1931 `S' is for references to extern items which are PIC for OSF/rose.
1932 `T' is for memory addresses that can be used to load two words. */
1934 #define EXTRA_CONSTRAINT(OP,CODE) \
1935 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
1936 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
1937 && mips16_gp_offset_p (OP)) \
1938 : (GET_CODE (OP) != MEM) ? FALSE \
1939 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1940 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1941 && HALF_PIC_ADDRESS_P (OP)) \
1944 /* Given an rtx X being reloaded into a reg required to be
1945 in class CLASS, return the class of reg to actually use.
1946 In general this is just CLASS; but on some machines
1947 in some cases it is preferable to use a more restrictive class. */
1949 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1950 ((CLASS) != ALL_REGS \
1951 ? (! TARGET_MIPS16 \
1953 : ((CLASS) != GR_REGS \
1956 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1957 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1958 ? (TARGET_SOFT_FLOAT \
1959 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1961 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1962 || GET_MODE (X) == VOIDmode) \
1963 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1966 /* Certain machines have the property that some registers cannot be
1967 copied to some other registers without using memory. Define this
1968 macro on those machines to be a C expression that is non-zero if
1969 objects of mode MODE in registers of CLASS1 can only be copied to
1970 registers of class CLASS2 by storing a register of CLASS1 into
1971 memory and loading that memory location into a register of CLASS2.
1973 Do not define this macro if its value would always be zero. */
1975 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1976 ((!TARGET_DEBUG_H_MODE \
1977 && GET_MODE_CLASS (MODE) == MODE_INT \
1978 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1979 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1980 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1981 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1982 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1984 /* The HI and LO registers can only be reloaded via the general
1985 registers. Condition code registers can only be loaded to the
1986 general registers, and from the floating point registers. */
1988 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1989 mips_secondary_reload_class (CLASS, MODE, X, 1)
1990 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1991 mips_secondary_reload_class (CLASS, MODE, X, 0)
1993 /* Not declared above, with the other functions, because enum
1994 reg_class is not declared yet. */
1995 extern enum reg_class mips_secondary_reload_class ();
1997 /* Return the maximum number of consecutive registers
1998 needed to represent mode MODE in a register of class CLASS. */
2000 #define CLASS_UNITS(mode, size) \
2001 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2003 #define CLASS_MAX_NREGS(CLASS, MODE) \
2004 ((CLASS) == FP_REGS \
2006 ? CLASS_UNITS (MODE, 8) \
2007 : 2 * CLASS_UNITS (MODE, 8)) \
2008 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2010 /* If defined, this is a C expression whose value should be
2011 nonzero if the insn INSN has the effect of mysteriously
2012 clobbering the contents of hard register number REGNO. By
2013 "mysterious" we mean that the insn's RTL expression doesn't
2014 describe such an effect.
2016 If this macro is not defined, it means that no insn clobbers
2017 registers mysteriously. This is the usual situation; all else
2018 being equal, it is best for the RTL expression to show all the
2021 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
2024 /* Stack layout; function entry, exit and calling. */
2026 /* Define this if pushing a word on the stack
2027 makes the stack pointer a smaller address. */
2028 #define STACK_GROWS_DOWNWARD
2030 /* Define this if the nominal address of the stack frame
2031 is at the high-address end of the local variables;
2032 that is, each additional local variable allocated
2033 goes at a more negative offset in the frame. */
2034 /* #define FRAME_GROWS_DOWNWARD */
2036 /* Offset within stack frame to start allocating local variables at.
2037 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2038 first local allocated. Otherwise, it is the offset to the BEGINNING
2039 of the first local allocated. */
2040 #define STARTING_FRAME_OFFSET \
2041 (current_function_outgoing_args_size \
2042 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2044 /* Offset from the stack pointer register to an item dynamically
2045 allocated on the stack, e.g., by `alloca'.
2047 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2048 length of the outgoing arguments. The default is correct for most
2049 machines. See `function.c' for details.
2051 The MIPS ABI states that functions which dynamically allocate the
2052 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2053 we are trying to create a second frame pointer to the function, so
2054 allocate some stack space to make it happy.
2056 However, the linker currently complains about linking any code that
2057 dynamically allocates stack space, and there seems to be a bug in
2058 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2061 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2062 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2063 ? 4*UNITS_PER_WORD \
2064 : current_function_outgoing_args_size)
2067 /* The return address for the current frame is in r31 is this is a leaf
2068 function. Otherwise, it is on the stack. It is at a variable offset
2069 from sp/fp/ap, so we define a fake hard register rap which is a
2070 poiner to the return address on the stack. This always gets eliminated
2071 during reload to be either the frame pointer or the stack pointer plus
2074 /* ??? This definition fails for leaf functions. There is currently no
2075 general solution for this problem. */
2077 /* ??? There appears to be no way to get the return address of any previous
2078 frame except by disassembling instructions in the prologue/epilogue.
2079 So currently we support only the current frame. */
2081 #define RETURN_ADDR_RTX(count, frame) \
2083 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2086 /* Structure to be filled in by compute_frame_size with register
2087 save masks, and offsets for the current function. */
2089 struct mips_frame_info
2091 long total_size; /* # bytes that the entire frame takes up */
2092 long var_size; /* # bytes that variables take up */
2093 long args_size; /* # bytes that outgoing arguments take up */
2094 long extra_size; /* # bytes of extra gunk */
2095 int gp_reg_size; /* # bytes needed to store gp regs */
2096 int fp_reg_size; /* # bytes needed to store fp regs */
2097 long mask; /* mask of saved gp registers */
2098 long fmask; /* mask of saved fp registers */
2099 long gp_save_offset; /* offset from vfp to store gp registers */
2100 long fp_save_offset; /* offset from vfp to store fp registers */
2101 long gp_sp_offset; /* offset from new sp to store gp registers */
2102 long fp_sp_offset; /* offset from new sp to store fp registers */
2103 int initialized; /* != 0 if frame size already calculated */
2104 int num_gp; /* number of gp registers saved */
2105 int num_fp; /* number of fp registers saved */
2106 long insns_len; /* length of insns; mips16 only */
2109 extern struct mips_frame_info current_frame_info;
2111 /* If defined, this macro specifies a table of register pairs used to
2112 eliminate unneeded registers that point into the stack frame. If
2113 it is not defined, the only elimination attempted by the compiler
2114 is to replace references to the frame pointer with references to
2117 The definition of this macro is a list of structure
2118 initializations, each of which specifies an original and
2119 replacement register.
2121 On some machines, the position of the argument pointer is not
2122 known until the compilation is completed. In such a case, a
2123 separate hard register must be used for the argument pointer.
2124 This register can be eliminated by replacing it with either the
2125 frame pointer or the argument pointer, depending on whether or not
2126 the frame pointer has been eliminated.
2128 In this case, you might specify:
2129 #define ELIMINABLE_REGS \
2130 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2131 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2132 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2134 Note that the elimination of the argument pointer with the stack
2135 pointer is specified first since that is the preferred elimination.
2137 The eliminations to $17 are only used on the mips16. See the
2138 definition of HARD_FRAME_POINTER_REGNUM. */
2140 #define ELIMINABLE_REGS \
2141 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2142 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2143 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2144 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2145 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2146 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2147 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2148 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2149 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2151 /* A C expression that returns non-zero if the compiler is allowed to
2152 try to replace register number FROM-REG with register number
2153 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2154 defined, and will usually be the constant 1, since most of the
2155 cases preventing register elimination are things that the compiler
2156 already knows about.
2158 When not in mips16 and mips64, we can always eliminate to the
2159 frame pointer. We can eliminate to the stack pointer unless
2160 a frame pointer is needed. In mips16 mode, we need a frame
2161 pointer for a large frame; otherwise, reload may be unable
2162 to compute the address of a local variable, since there is
2163 no way to add a large constant to the stack pointer
2164 without using a temporary register.
2166 In mips16, for some instructions (eg lwu), we can't eliminate the
2167 frame pointer for the stack pointer. These instructions are
2168 only generated in TARGET_64BIT mode.
2171 #define CAN_ELIMINATE(FROM, TO) \
2172 ((TO) == HARD_FRAME_POINTER_REGNUM \
2173 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2174 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2175 && (! TARGET_MIPS16 \
2176 || compute_frame_size (get_frame_size ()) < 32768)))
2178 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2179 specifies the initial difference between the specified pair of
2180 registers. This macro must be defined if `ELIMINABLE_REGS' is
2183 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2184 { compute_frame_size (get_frame_size ()); \
2185 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2186 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2187 (OFFSET) = - current_function_outgoing_args_size; \
2188 else if ((FROM) == FRAME_POINTER_REGNUM) \
2190 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2191 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2192 (OFFSET) = (current_frame_info.total_size \
2193 - current_function_outgoing_args_size \
2194 - ((mips_abi != ABI_32 \
2195 && mips_abi != ABI_O64 \
2196 && mips_abi != ABI_EABI) \
2197 ? current_function_pretend_args_size \
2199 else if ((FROM) == ARG_POINTER_REGNUM) \
2200 (OFFSET) = (current_frame_info.total_size \
2201 - ((mips_abi != ABI_32 \
2202 && mips_abi != ABI_O64 \
2203 && mips_abi != ABI_EABI) \
2204 ? current_function_pretend_args_size \
2206 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2207 so we must add 4 bytes to the offset to get the right value. */ \
2208 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2209 (OFFSET) = current_frame_info.gp_sp_offset \
2210 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2211 * (BYTES_BIG_ENDIAN != 0)); \
2214 /* If we generate an insn to push BYTES bytes,
2215 this says how many the stack pointer really advances by.
2216 On the vax, sp@- in a byte insn really pushes a word. */
2218 /* #define PUSH_ROUNDING(BYTES) 0 */
2220 /* If defined, the maximum amount of space required for outgoing
2221 arguments will be computed and placed into the variable
2222 `current_function_outgoing_args_size'. No space will be pushed
2223 onto the stack for each call; instead, the function prologue
2224 should increase the stack frame size by this amount.
2226 It is not proper to define both `PUSH_ROUNDING' and
2227 `ACCUMULATE_OUTGOING_ARGS'. */
2228 #define ACCUMULATE_OUTGOING_ARGS
2230 /* Offset from the argument pointer register to the first argument's
2231 address. On some machines it may depend on the data type of the
2234 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2235 the first argument's address.
2237 On the MIPS, we must skip the first argument position if we are
2238 returning a structure or a union, to account for its address being
2239 passed in $4. However, at the current time, this produces a compiler
2240 that can't bootstrap, so comment it out for now. */
2243 #define FIRST_PARM_OFFSET(FNDECL) \
2245 && TREE_TYPE (FNDECL) != 0 \
2246 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2247 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2248 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2252 #define FIRST_PARM_OFFSET(FNDECL) 0
2255 /* When a parameter is passed in a register, stack space is still
2256 allocated for it. For the MIPS, stack space must be allocated, cf
2257 Asm Lang Prog Guide page 7-8.
2259 BEWARE that some space is also allocated for non existing arguments
2260 in register. In case an argument list is of form GF used registers
2261 are a0 (a2,a3), but we should push over a1... */
2263 #define REG_PARM_STACK_SPACE(FNDECL) \
2264 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2266 /* Define this if it is the responsibility of the caller to
2267 allocate the area reserved for arguments passed in registers.
2268 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2269 of this macro is to determine whether the space is included in
2270 `current_function_outgoing_args_size'. */
2271 #define OUTGOING_REG_PARM_STACK_SPACE
2273 /* Align stack frames on 64 bits (Double Word ). */
2274 #ifndef STACK_BOUNDARY
2275 #define STACK_BOUNDARY 64
2278 /* Make sure 4 words are always allocated on the stack. */
2280 #ifndef STACK_ARGS_ADJUST
2281 #define STACK_ARGS_ADJUST(SIZE) \
2283 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2284 SIZE.constant = 4 * UNITS_PER_WORD; \
2289 /* A C expression that should indicate the number of bytes of its
2290 own arguments that a function pops on returning, or 0
2291 if the function pops no arguments and the caller must therefore
2292 pop them all after the function returns.
2294 FUNDECL is the declaration node of the function (as a tree).
2296 FUNTYPE is a C variable whose value is a tree node that
2297 describes the function in question. Normally it is a node of
2298 type `FUNCTION_TYPE' that describes the data type of the function.
2299 From this it is possible to obtain the data types of the value
2300 and arguments (if known).
2302 When a call to a library function is being considered, FUNTYPE
2303 will contain an identifier node for the library function. Thus,
2304 if you need to distinguish among various library functions, you
2305 can do so by their names. Note that "library function" in this
2306 context means a function used to perform arithmetic, whose name
2307 is known specially in the compiler and was not mentioned in the
2308 C code being compiled.
2310 STACK-SIZE is the number of bytes of arguments passed on the
2311 stack. If a variable number of bytes is passed, it is zero, and
2312 argument popping will always be the responsibility of the
2313 calling function. */
2315 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2318 /* Symbolic macros for the registers used to return integer and floating
2321 #define GP_RETURN (GP_REG_FIRST + 2)
2322 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2324 /* Symbolic macros for the first/last argument registers. */
2326 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2327 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2328 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2329 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2331 #define MAX_ARGS_IN_REGISTERS 4
2333 /* Define how to find the value returned by a library function
2334 assuming the value has mode MODE. Because we define
2335 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2336 PROMOTE_MODE does. */
2338 #define LIBCALL_VALUE(MODE) \
2340 ((GET_MODE_CLASS (MODE) != MODE_INT \
2341 || GET_MODE_SIZE (MODE) >= 4) \
2344 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2345 && (! TARGET_SINGLE_FLOAT \
2346 || GET_MODE_SIZE (MODE) <= 4)) \
2350 /* Define how to find the value returned by a function.
2351 VALTYPE is the data type of the value (as a tree).
2352 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2353 otherwise, FUNC is 0. */
2355 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2358 /* 1 if N is a possible register number for a function value.
2359 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2360 Currently, R2 and F0 are only implemented here (C has no complex type) */
2362 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2364 /* 1 if N is a possible register number for function argument passing.
2365 We have no FP argument registers when soft-float. When FP registers
2366 are 32 bits, we can't directly reference the odd numbered ones. */
2368 #define FUNCTION_ARG_REGNO_P(N) \
2369 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2370 || ((! TARGET_SOFT_FLOAT \
2371 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2372 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2373 && ! fixed_regs[N]))
2375 /* A C expression which can inhibit the returning of certain function
2376 values in registers, based on the type of value. A nonzero value says
2377 to return the function value in memory, just as large structures are
2378 always returned. Here TYPE will be a C expression of type
2379 `tree', representing the data type of the value.
2381 Note that values of mode `BLKmode' must be explicitly
2382 handled by this macro. Also, the option `-fpcc-struct-return'
2383 takes effect regardless of this macro. On most systems, it is
2384 possible to leave the macro undefined; this causes a default
2385 definition to be used, whose value is the constant 1 for BLKmode
2386 values, and 0 otherwise.
2388 GCC normally converts 1 byte structures into chars, 2 byte
2389 structs into shorts, and 4 byte structs into ints, and returns
2390 them this way. Defining the following macro overrides this,
2391 to give us MIPS cc compatibility. */
2393 #define RETURN_IN_MEMORY(TYPE) \
2394 (TYPE_MODE (TYPE) == BLKmode)
2396 /* A code distinguishing the floating point format of the target
2397 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2398 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2400 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2403 /* Define a data type for recording info about an argument list
2404 during the scan of that argument list. This data type should
2405 hold all necessary information about the function itself
2406 and about the args processed so far, enough to enable macros
2407 such as FUNCTION_ARG to determine where the next arg should go.
2409 On the mips16, we need to keep track of which floating point
2410 arguments were passed in general registers, but would have been
2411 passed in the FP regs if this were a 32 bit function, so that we
2412 can move them to the FP regs if we wind up calling a 32 bit
2413 function. We record this information in fp_code, encoded in base
2414 four. A zero digit means no floating point argument, a one digit
2415 means an SFmode argument, and a two digit means a DFmode argument,
2416 and a three digit is not used. The low order digit is the first
2417 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2418 an SFmode argument. ??? A more sophisticated approach will be
2419 needed if MIPS_ABI != ABI_32. */
2421 typedef struct mips_args {
2422 int gp_reg_found; /* whether a gp register was found yet */
2423 int arg_number; /* argument number */
2424 int arg_words; /* # total words the arguments take */
2425 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2426 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2427 int fp_code; /* Mode of FP arguments (mips16) */
2428 int num_adjusts; /* number of adjustments made */
2429 /* Adjustments made to args pass in regs. */
2430 /* ??? The size is doubled to work around a
2431 bug in the code that sets the adjustments
2433 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2436 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2437 for a call to a function whose data type is FNTYPE.
2438 For a library call, FNTYPE is 0.
2442 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2443 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2445 /* Update the data in CUM to advance over an argument
2446 of mode MODE and data type TYPE.
2447 (TYPE is null for libcalls where that information may not be available.) */
2449 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2450 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2452 /* Determine where to put an argument to a function.
2453 Value is zero to push the argument on the stack,
2454 or a hard register in which to store the argument.
2456 MODE is the argument's machine mode.
2457 TYPE is the data type of the argument (as a tree).
2458 This is null for libcalls where that information may
2460 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2461 the preceding args and about the function being called.
2462 NAMED is nonzero if this argument is a named parameter
2463 (otherwise it is an extra parameter matching an ellipsis). */
2465 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2466 function_arg( &CUM, MODE, TYPE, NAMED)
2468 /* For an arg passed partly in registers and partly in memory,
2469 this is the number of registers used.
2470 For args passed entirely in registers or entirely in memory, zero. */
2472 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2473 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2475 /* If defined, a C expression that gives the alignment boundary, in
2476 bits, of an argument with the specified mode and type. If it is
2477 not defined, `PARM_BOUNDARY' is used for all arguments. */
2479 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2481 ? ((TYPE_ALIGN(TYPE) <= (unsigned)PARM_BOUNDARY) \
2483 : TYPE_ALIGN(TYPE)) \
2484 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2486 : GET_MODE_ALIGNMENT(MODE)))
2489 /* This macro generates the assembly code for function entry.
2490 FILE is a stdio stream to output the code to.
2491 SIZE is an int: how many units of temporary storage to allocate.
2492 Refer to the array `regs_ever_live' to determine which registers
2493 to save; `regs_ever_live[I]' is nonzero if register number I
2494 is ever used in the function. This macro is responsible for
2495 knowing which registers should not be saved even if used. */
2497 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2499 /* This macro generates the assembly code for function exit,
2500 on machines that need it. If FUNCTION_EPILOGUE is not defined
2501 then individual return instructions are generated for each
2502 return statement. Args are same as for FUNCTION_PROLOGUE. */
2504 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2506 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2508 #define MUST_SAVE_REGISTER(regno) \
2509 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2510 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2511 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2513 /* ALIGN FRAMES on double word boundaries */
2514 #ifndef MIPS_STACK_ALIGN
2515 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2519 /* Output assembler code to FILE to increment profiler label # LABELNO
2520 for profiling a function entry. */
2522 #define FUNCTION_PROFILER(FILE, LABELNO) \
2524 if (TARGET_MIPS16) \
2525 sorry ("mips16 function profiling"); \
2526 fprintf (FILE, "\t.set\tnoreorder\n"); \
2527 fprintf (FILE, "\t.set\tnoat\n"); \
2528 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2529 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2530 fprintf (FILE, "\tjal\t_mcount\n"); \
2532 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2533 TARGET_64BIT ? "dsubu" : "subu", \
2534 reg_names[STACK_POINTER_REGNUM], \
2535 reg_names[STACK_POINTER_REGNUM], \
2536 Pmode == DImode ? 16 : 8); \
2537 fprintf (FILE, "\t.set\treorder\n"); \
2538 fprintf (FILE, "\t.set\tat\n"); \
2541 /* Define this macro if the code for function profiling should come
2542 before the function prologue. Normally, the profiling code comes
2545 /* #define PROFILE_BEFORE_PROLOGUE */
2547 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2548 the stack pointer does not matter. The value is tested only in
2549 functions that have frame pointers.
2550 No definition is equivalent to always zero. */
2552 #define EXIT_IGNORE_STACK 1
2555 /* A C statement to output, on the stream FILE, assembler code for a
2556 block of data that contains the constant parts of a trampoline.
2557 This code should not include a label--the label is taken care of
2560 #define TRAMPOLINE_TEMPLATE(STREAM) \
2562 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2563 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2564 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2565 if (Pmode == DImode) \
2567 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2568 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2572 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2573 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2575 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2576 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2577 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2578 if (Pmode == DImode) \
2580 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2581 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2585 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2586 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2590 /* A C expression for the size in bytes of the trampoline, as an
2593 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2595 /* Alignment required for trampolines, in bits. */
2597 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2599 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2600 program and data caches. */
2602 #ifndef CACHE_FLUSH_FUNC
2603 #define CACHE_FLUSH_FUNC "_flush_cache"
2606 /* A C statement to initialize the variable parts of a trampoline.
2607 ADDR is an RTX for the address of the trampoline; FNADDR is an
2608 RTX for the address of the nested function; STATIC_CHAIN is an
2609 RTX for the static chain value that should be passed to the
2610 function when it is called. */
2612 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2615 if (Pmode == DImode) \
2617 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2618 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2622 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2623 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2626 /* Flush both caches. We need to flush the data cache in case \
2627 the system has a write-back cache. */ \
2628 /* ??? Should check the return value for errors. */ \
2629 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, CACHE_FLUSH_FUNC), \
2630 0, VOIDmode, 3, addr, Pmode, \
2631 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2632 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2635 /* Addressing modes, and classification of registers for them. */
2637 /* #define HAVE_POST_INCREMENT 0 */
2638 /* #define HAVE_POST_DECREMENT 0 */
2640 /* #define HAVE_PRE_DECREMENT 0 */
2641 /* #define HAVE_PRE_INCREMENT 0 */
2643 /* These assume that REGNO is a hard or pseudo reg number.
2644 They give nonzero only if REGNO is a hard reg of the suitable class
2645 or a pseudo reg currently allocated to a suitable hard reg.
2646 These definitions are NOT overridden anywhere. */
2648 #define BASE_REG_P(regno, mode) \
2650 ? (M16_REG_P (regno) \
2651 || (regno) == FRAME_POINTER_REGNUM \
2652 || (regno) == ARG_POINTER_REGNUM \
2653 || ((regno) == STACK_POINTER_REGNUM \
2654 && (GET_MODE_SIZE (mode) == 4 \
2655 || GET_MODE_SIZE (mode) == 8))) \
2658 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2659 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2662 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2663 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2665 #define REGNO_OK_FOR_INDEX_P(regno) 0
2666 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2667 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2669 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2670 and check its validity for a certain class.
2671 We have two alternate definitions for each of them.
2672 The usual definition accepts all pseudo regs; the other rejects them all.
2673 The symbol REG_OK_STRICT causes the latter definition to be used.
2675 Most source files want to accept pseudo regs in the hope that
2676 they will get allocated to the class that the insn wants them to be in.
2677 Some source files that are used after register allocation
2678 need to be strict. */
2680 #ifndef REG_OK_STRICT
2682 #define REG_OK_STRICT_P 0
2683 #define REG_OK_FOR_INDEX_P(X) 0
2684 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2685 GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
2689 #define REG_OK_STRICT_P 1
2690 #define REG_OK_FOR_INDEX_P(X) 0
2691 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2692 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
2697 /* Maximum number of registers that can appear in a valid memory address. */
2699 #define MAX_REGS_PER_ADDRESS 1
2701 /* A C compound statement with a conditional `goto LABEL;' executed
2702 if X (an RTX) is a legitimate memory address on the target
2703 machine for a memory operand of mode MODE.
2705 It usually pays to define several simpler macros to serve as
2706 subroutines for this one. Otherwise it may be too complicated
2709 This macro must exist in two variants: a strict variant and a
2710 non-strict one. The strict variant is used in the reload pass.
2711 It must be defined so that any pseudo-register that has not been
2712 allocated a hard register is considered a memory reference. In
2713 contexts where some kind of register is required, a
2714 pseudo-register with no hard register must be rejected.
2716 The non-strict variant is used in other passes. It must be
2717 defined to accept all pseudo-registers in every context where
2718 some kind of register is required.
2720 Compiler source files that want to use the strict variant of
2721 this macro define the macro `REG_OK_STRICT'. You should use an
2722 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2723 in that case and the non-strict variant otherwise.
2725 Typically among the subroutines used to define
2726 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2727 acceptable registers for various purposes (one for base
2728 registers, one for index registers, and so on). Then only these
2729 subroutine macros need have two variants; the higher levels of
2730 macros may be the same whether strict or not.
2732 Normally, constant addresses which are the sum of a `symbol_ref'
2733 and an integer are stored inside a `const' RTX to mark them as
2734 constant. Therefore, there is no need to recognize such sums
2735 specifically as legitimate addresses. Normally you would simply
2736 recognize any `const' as legitimate.
2738 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2739 constant sums that are not marked with `const'. It assumes
2740 that a naked `plus' indicates indexing. If so, then you *must*
2741 reject such naked constant sums as illegitimate addresses, so
2742 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2744 On some machines, whether a symbolic address is legitimate
2745 depends on the section that the address refers to. On these
2746 machines, define the macro `ENCODE_SECTION_INFO' to store the
2747 information into the `symbol_ref', and then check for it here.
2748 When you see a `const', you will have to look inside it to find
2749 the `symbol_ref' in order to determine the section. */
2752 #define GO_PRINTF(x) trace(x)
2753 #define GO_PRINTF2(x,y) trace(x,y)
2754 #define GO_DEBUG_RTX(x) debug_rtx(x)
2757 #define GO_PRINTF(x)
2758 #define GO_PRINTF2(x,y)
2759 #define GO_DEBUG_RTX(x)
2762 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2764 register rtx xinsn = (X); \
2766 if (TARGET_DEBUG_B_MODE) \
2768 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2769 (REG_OK_STRICT_P) ? "" : "not "); \
2770 GO_DEBUG_RTX (xinsn); \
2773 /* The mips16 can only use the stack pointer as a base register when \
2774 loading SImode or DImode values. */ \
2775 if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \
2778 if (CONSTANT_ADDRESS_P (xinsn) \
2779 && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \
2780 && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \
2783 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2785 register rtx xlow0 = XEXP (xinsn, 0); \
2786 register rtx xlow1 = XEXP (xinsn, 1); \
2788 if (GET_CODE (xlow0) == REG \
2789 && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \
2790 && mips_check_split (xlow1, MODE)) \
2794 if (GET_CODE (xinsn) == PLUS) \
2796 register rtx xplus0 = XEXP (xinsn, 0); \
2797 register rtx xplus1 = XEXP (xinsn, 1); \
2798 register enum rtx_code code0 = GET_CODE (xplus0); \
2799 register enum rtx_code code1 = GET_CODE (xplus1); \
2801 /* The mips16 can only use the stack pointer as a base register \
2802 when loading SImode or DImode values. */ \
2803 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \
2805 if (code1 == CONST_INT \
2806 && INTVAL (xplus1) >= -32768 \
2807 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2810 /* On the mips16, we represent GP relative offsets in RTL. \
2811 These are 16 bit signed values, and can serve as register \
2814 && mips16_gp_offset_p (xplus1)) \
2817 /* For some code sequences, you actually get better code by \
2818 pretending that the MIPS supports an address mode of a \
2819 constant address + a register, even though the real \
2820 machine doesn't support it. This is because the \
2821 assembler can use $r1 to load just the high 16 bits, add \
2822 in the register, and fold the low 16 bits into the memory \
2823 reference, whereas the compiler generates a 4 instruction \
2824 sequence. On the other hand, CSE is not as effective. \
2825 It would be a win to generate the lui directly, but the \
2826 MIPS assembler does not have syntax to generate the \
2827 appropriate relocation. */ \
2829 /* Also accept CONST_INT addresses here, so no else. */ \
2830 /* Reject combining an embedded PIC text segment reference \
2831 with a register. That requires an additional \
2833 /* ??? Reject combining an address with a register for the MIPS \
2834 64 bit ABI, because the SGI assembler can not handle this. */ \
2835 if (!TARGET_DEBUG_A_MODE \
2836 && (mips_abi == ABI_32 \
2837 || mips_abi == ABI_O64 \
2838 || mips_abi == ABI_EABI) \
2839 && CONSTANT_ADDRESS_P (xplus1) \
2840 && ! mips_split_addresses \
2841 && (!TARGET_EMBEDDED_PIC \
2843 || GET_CODE (XEXP (xplus1, 0)) != MINUS) \
2844 && !TARGET_MIPS16) \
2849 if (TARGET_DEBUG_B_MODE) \
2850 GO_PRINTF ("Not a legitimate address\n"); \
2854 /* A C expression that is 1 if the RTX X is a constant which is a
2855 valid address. This is defined to be the same as `CONSTANT_P (X)',
2856 but rejecting CONST_DOUBLE. */
2857 /* When pic, we must reject addresses of the form symbol+large int.
2858 This is because an instruction `sw $4,s+70000' needs to be converted
2859 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2860 assembler would use $at as a temp to load in the large offset. In this
2861 case $at is already in use. We convert such problem addresses to
2862 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2863 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2864 #define CONSTANT_ADDRESS_P(X) \
2865 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2866 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2867 || (GET_CODE (X) == CONST \
2868 && ! (flag_pic && pic_address_needs_scratch (X)) \
2869 && (mips_abi == ABI_32 \
2870 || mips_abi == ABI_O64 \
2871 || mips_abi == ABI_EABI))) \
2872 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2874 /* Define this, so that when PIC, reload won't try to reload invalid
2875 addresses which require two reload registers. */
2877 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2879 /* Nonzero if the constant value X is a legitimate general operand.
2880 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2882 At present, GAS doesn't understand li.[sd], so don't allow it
2883 to be generated at present. Also, the MIPS assembler does not
2884 grok li.d Infinity. */
2886 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2887 #define LEGITIMATE_CONSTANT_P(X) \
2888 ((GET_CODE (X) != CONST_DOUBLE \
2889 || mips_const_double_ok (X, GET_MODE (X))) \
2890 && ! (GET_CODE (X) == CONST \
2891 && mips_abi != ABI_32 \
2892 && mips_abi != ABI_O64 \
2893 && mips_abi != ABI_EABI) \
2894 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2896 /* A C compound statement that attempts to replace X with a valid
2897 memory address for an operand of mode MODE. WIN will be a C
2898 statement label elsewhere in the code; the macro definition may
2901 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2903 to avoid further processing if the address has become legitimate.
2905 X will always be the result of a call to `break_out_memory_refs',
2906 and OLDX will be the operand that was given to that function to
2909 The code generated by this macro should not alter the
2910 substructure of X. If it transforms X into a more legitimate
2911 form, it should assign X (which will always be a C variable) a
2914 It is not necessary for this macro to come up with a legitimate
2915 address. The compiler has standard ways of doing so in all
2916 cases. In fact, it is safe for this macro to do nothing. But
2917 often a machine-dependent strategy can generate better code.
2919 For the MIPS, transform:
2921 memory(X + <large int>)
2925 Y = <large int> & ~0x7fff;
2927 memory (Z + (<large int> & 0x7fff));
2929 This is for CSE to find several similar references, and only use one Z.
2931 When PIC, convert addresses of the form memory (symbol+large int) to
2932 memory (reg+large int). */
2935 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2937 register rtx xinsn = (X); \
2939 if (TARGET_DEBUG_B_MODE) \
2941 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2942 GO_DEBUG_RTX (xinsn); \
2945 if (mips_split_addresses && mips_check_split (X, MODE)) \
2947 /* ??? Is this ever executed? */ \
2948 X = gen_rtx (LO_SUM, Pmode, \
2949 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2953 if (GET_CODE (xinsn) == CONST \
2954 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2955 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2956 || (mips_abi != ABI_32 \
2957 && mips_abi != ABI_O64 \
2958 && mips_abi != ABI_EABI))) \
2960 rtx ptr_reg = gen_reg_rtx (Pmode); \
2961 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2963 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2965 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2966 if (SMALL_INT (constant)) \
2968 /* Otherwise we fall through so the code below will fix the \
2973 if (GET_CODE (xinsn) == PLUS) \
2975 register rtx xplus0 = XEXP (xinsn, 0); \
2976 register rtx xplus1 = XEXP (xinsn, 1); \
2977 register enum rtx_code code0 = GET_CODE (xplus0); \
2978 register enum rtx_code code1 = GET_CODE (xplus1); \
2980 if (code0 != REG && code1 == REG) \
2982 xplus0 = XEXP (xinsn, 1); \
2983 xplus1 = XEXP (xinsn, 0); \
2984 code0 = GET_CODE (xplus0); \
2985 code1 = GET_CODE (xplus1); \
2988 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
2989 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2991 rtx int_reg = gen_reg_rtx (Pmode); \
2992 rtx ptr_reg = gen_reg_rtx (Pmode); \
2994 emit_move_insn (int_reg, \
2995 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2997 emit_insn (gen_rtx (SET, VOIDmode, \
2999 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
3001 X = gen_rtx (PLUS, Pmode, ptr_reg, \
3002 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
3007 if (TARGET_DEBUG_B_MODE) \
3008 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3012 /* A C statement or compound statement with a conditional `goto
3013 LABEL;' executed if memory address X (an RTX) can have different
3014 meanings depending on the machine mode of the memory reference it
3017 Autoincrement and autodecrement addresses typically have
3018 mode-dependent effects because the amount of the increment or
3019 decrement is the size of the operand being addressed. Some
3020 machines have other mode-dependent addresses. Many RISC machines
3021 have no mode-dependent addresses.
3023 You may assume that ADDR is a valid address for the machine. */
3025 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3028 /* Define this macro if references to a symbol must be treated
3029 differently depending on something about the variable or
3030 function named by the symbol (such as what section it is in).
3032 The macro definition, if any, is executed immediately after the
3033 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3034 The value of the rtl will be a `mem' whose address is a
3037 The usual thing for this macro to do is to a flag in the
3038 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3039 name string in the `symbol_ref' (if one bit is not enough
3042 The best way to modify the name string is by adding text to the
3043 beginning, with suitable punctuation to prevent any ambiguity.
3044 Allocate the new name in `saveable_obstack'. You will have to
3045 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3046 and output the name accordingly.
3048 You can also check the information stored in the `symbol_ref' in
3049 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3050 `PRINT_OPERAND_ADDRESS'.
3052 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3055 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3056 symbols which are not in the .text section.
3058 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3059 constants which are put in the .text section. We also record the
3060 total length of all such strings; this total is used to decide
3061 whether we need to split the constant table, and need not be
3064 When not mips16 code nor embedded PIC, if a symbol is in a
3065 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3066 splitting the reference so that gas can generate a gp relative
3070 #define ENCODE_SECTION_INFO(DECL) \
3073 if (TARGET_MIPS16) \
3075 if (TREE_CODE (DECL) == STRING_CST \
3076 && ! flag_writable_strings) \
3078 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3079 mips_string_length += TREE_STRING_LENGTH (DECL); \
3082 if (TARGET_EMBEDDED_PIC) \
3084 if (TREE_CODE (DECL) == VAR_DECL) \
3085 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3086 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3087 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3088 else if (TREE_CODE (DECL) == STRING_CST \
3089 && ! flag_writable_strings) \
3090 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3092 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3095 else if (TREE_CODE (DECL) == VAR_DECL \
3096 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3097 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3099 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3102 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3105 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
3107 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3109 if (size > 0 && size <= mips_section_threshold) \
3110 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3113 else if (HALF_PIC_P ()) \
3115 HALF_PIC_ENCODE (DECL); \
3120 /* The mips16 wants the constant pool to be after the function,
3121 because the PC relative load instructions use unsigned offsets. */
3123 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3125 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3126 mips_string_length = 0;
3129 /* In mips16 mode, put most string constants after the function. */
3130 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3131 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3134 /* Specify the machine mode that this machine uses
3135 for the index in the tablejump instruction.
3136 ??? Using HImode in mips16 mode can cause overflow. However, the
3137 overflow is no more likely than the overflow in a branch
3138 instruction. Large functions can currently break in both ways. */
3139 #define CASE_VECTOR_MODE \
3140 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3142 /* Define as C expression which evaluates to nonzero if the tablejump
3143 instruction expects the table to contain offsets from the address of the
3145 Do not define this if the table should contain absolute addresses. */
3146 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3148 /* Specify the tree operation to be used to convert reals to integers. */
3149 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3151 /* This is the kind of divide that is easiest to do in the general case. */
3152 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3154 /* Define this as 1 if `char' should by default be signed; else as 0. */
3155 #ifndef DEFAULT_SIGNED_CHAR
3156 #define DEFAULT_SIGNED_CHAR 1
3159 /* Max number of bytes we can move from memory to memory
3160 in one reasonably fast instruction. */
3161 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3162 #define MAX_MOVE_MAX 8
3164 /* Define this macro as a C expression which is nonzero if
3165 accessing less than a word of memory (i.e. a `char' or a
3166 `short') is no faster than accessing a word of memory, i.e., if
3167 such access require more than one instruction or if there is no
3168 difference in cost between byte and (aligned) word loads.
3170 On RISC machines, it tends to generate better code to define
3171 this as 1, since it avoids making a QI or HI mode register. */
3172 #define SLOW_BYTE_ACCESS 1
3174 /* We assume that the store-condition-codes instructions store 0 for false
3175 and some other value for true. This is the value stored for true. */
3177 #define STORE_FLAG_VALUE 1
3179 /* Define this if zero-extension is slow (more than one real instruction). */
3180 #define SLOW_ZERO_EXTEND
3182 /* Define this to be nonzero if shift instructions ignore all but the low-order
3184 #define SHIFT_COUNT_TRUNCATED 1
3186 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3187 is done just by pretending it is already truncated. */
3188 /* In 64 bit mode, 32 bit instructions require that register values be properly
3189 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3190 converts a value >32 bits to a value <32 bits. */
3191 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3192 Something needs to be done about this. Perhaps not use any 32 bit
3193 instructions? Perhaps use PROMOTE_MODE? */
3194 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3195 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3197 /* Specify the machine mode that pointers have.
3198 After generation of rtl, the compiler makes no further distinction
3199 between pointers and any other objects of this machine mode. */
3202 #define Pmode ((enum machine_mode)(TARGET_LONG64 ? DImode : SImode))
3205 /* A function address in a call instruction
3206 is a word address (for indexing purposes)
3207 so give the MEM rtx a words's mode. */
3209 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3211 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3212 memset, instead of the BSD functions bcopy and bzero. */
3214 #if defined(MIPS_SYSV) || defined(OSF_OS)
3215 #define TARGET_MEM_FUNCTIONS
3219 /* A part of a C `switch' statement that describes the relative
3220 costs of constant RTL expressions. It must contain `case'
3221 labels for expression codes `const_int', `const', `symbol_ref',
3222 `label_ref' and `const_double'. Each case must ultimately reach
3223 a `return' statement to return the relative cost of the use of
3224 that kind of constant value in an expression. The cost may
3225 depend on the precise value of the constant, which is available
3226 for examination in X.
3228 CODE is the expression code--redundant, since it can be obtained
3229 with `GET_CODE (X)'. */
3231 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3233 if (! TARGET_MIPS16) \
3235 /* Always return 0, since we don't have different sized \
3236 instructions, hence different costs according to Richard \
3240 if ((OUTER_CODE) == SET) \
3242 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3244 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3245 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3246 return COSTS_N_INSNS (1); \
3248 return COSTS_N_INSNS (2); \
3250 /* A PLUS could be an address. We don't want to force an address \
3251 to use a register, so accept any signed 16 bit value without \
3253 if ((OUTER_CODE) == PLUS \
3254 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3256 /* A number between 1 and 8 inclusive is efficient for a shift. \
3257 Otherwise, we will need an extended instruction. */ \
3258 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3259 || (OUTER_CODE) == LSHIFTRT) \
3261 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3263 return COSTS_N_INSNS (1); \
3265 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3266 if ((OUTER_CODE) == XOR \
3267 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3269 /* We may be able to use slt or sltu for a comparison with a \
3270 signed 16 bit value. (The boundary conditions aren't quite \
3271 right, but this is just a heuristic anyhow.) */ \
3272 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3273 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3274 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3275 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3276 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3278 /* Equality comparisons with 0 are cheap. */ \
3279 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3280 && INTVAL (X) == 0) \
3283 /* Otherwise, work out the cost to load the value into a \
3285 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3286 return COSTS_N_INSNS (1); \
3287 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3288 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3289 return COSTS_N_INSNS (2); \
3291 return COSTS_N_INSNS (3); \
3294 return COSTS_N_INSNS (2); \
3298 rtx offset = const0_rtx; \
3299 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3301 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3303 /* Treat this like a signed 16 bit CONST_INT. */ \
3304 if ((OUTER_CODE) == PLUS) \
3306 else if ((OUTER_CODE) == SET) \
3307 return COSTS_N_INSNS (1); \
3309 return COSTS_N_INSNS (2); \
3312 if (GET_CODE (symref) == LABEL_REF) \
3313 return COSTS_N_INSNS (2); \
3315 if (GET_CODE (symref) != SYMBOL_REF) \
3316 return COSTS_N_INSNS (4); \
3318 /* let's be paranoid.... */ \
3319 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3320 return COSTS_N_INSNS (2); \
3322 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3326 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3328 case CONST_DOUBLE: \
3331 if (TARGET_MIPS16) \
3332 return COSTS_N_INSNS (4); \
3333 split_double (X, &high, &low); \
3334 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3335 || low == CONST0_RTX (GET_MODE (low))) \
3339 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3340 This can be used, for example, to indicate how costly a multiply
3341 instruction is. In writing this macro, you can use the construct
3342 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3344 This macro is optional; do not define it if the default cost
3345 assumptions are adequate for the target machine.
3347 If -mdebugd is used, change the multiply cost to 2, so multiply by
3348 a constant isn't converted to a series of shifts. This helps
3349 strength reduction, and also makes it easier to identify what the
3350 compiler is doing. */
3352 /* ??? Fix this to be right for the R8000. */
3353 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3356 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3357 if (simple_memory_operand (X, GET_MODE (X))) \
3358 return COSTS_N_INSNS (num_words); \
3360 return COSTS_N_INSNS (2*num_words); \
3364 return COSTS_N_INSNS (6); \
3367 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3372 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3373 return COSTS_N_INSNS (2); \
3380 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3381 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3387 enum machine_mode xmode = GET_MODE (X); \
3388 if (xmode == SFmode || xmode == DFmode) \
3389 return COSTS_N_INSNS (1); \
3391 return COSTS_N_INSNS (4); \
3397 enum machine_mode xmode = GET_MODE (X); \
3398 if (xmode == SFmode || xmode == DFmode) \
3400 if (mips_cpu == PROCESSOR_R3000 \
3401 || mips_cpu == PROCESSOR_R3900) \
3402 return COSTS_N_INSNS (2); \
3403 else if (mips_cpu == PROCESSOR_R6000) \
3404 return COSTS_N_INSNS (3); \
3406 return COSTS_N_INSNS (6); \
3409 if (xmode == DImode && !TARGET_64BIT) \
3410 return COSTS_N_INSNS (4); \
3416 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3423 enum machine_mode xmode = GET_MODE (X); \
3424 if (xmode == SFmode) \
3426 if (mips_cpu == PROCESSOR_R3000 \
3427 || mips_cpu == PROCESSOR_R3900 \
3428 || mips_cpu == PROCESSOR_R5000) \
3429 return COSTS_N_INSNS (4); \
3430 else if (mips_cpu == PROCESSOR_R6000) \
3431 return COSTS_N_INSNS (5); \
3433 return COSTS_N_INSNS (7); \
3436 if (xmode == DFmode) \
3438 if (mips_cpu == PROCESSOR_R3000 \
3439 || mips_cpu == PROCESSOR_R3900 \
3440 || mips_cpu == PROCESSOR_R5000) \
3441 return COSTS_N_INSNS (5); \
3442 else if (mips_cpu == PROCESSOR_R6000) \
3443 return COSTS_N_INSNS (6); \
3445 return COSTS_N_INSNS (8); \
3448 if (mips_cpu == PROCESSOR_R3000) \
3449 return COSTS_N_INSNS (12); \
3450 else if (mips_cpu == PROCESSOR_R3900) \
3451 return COSTS_N_INSNS (2); \
3452 else if (mips_cpu == PROCESSOR_R6000) \
3453 return COSTS_N_INSNS (17); \
3454 else if (mips_cpu == PROCESSOR_R5000) \
3455 return COSTS_N_INSNS (5); \
3457 return COSTS_N_INSNS (10); \
3463 enum machine_mode xmode = GET_MODE (X); \
3464 if (xmode == SFmode) \
3466 if (mips_cpu == PROCESSOR_R3000 \
3467 || mips_cpu == PROCESSOR_R3900) \
3468 return COSTS_N_INSNS (12); \
3469 else if (mips_cpu == PROCESSOR_R6000) \
3470 return COSTS_N_INSNS (15); \
3472 return COSTS_N_INSNS (23); \
3475 if (xmode == DFmode) \
3477 if (mips_cpu == PROCESSOR_R3000 \
3478 || mips_cpu == PROCESSOR_R3900) \
3479 return COSTS_N_INSNS (19); \
3480 else if (mips_cpu == PROCESSOR_R6000) \
3481 return COSTS_N_INSNS (16); \
3483 return COSTS_N_INSNS (36); \
3486 /* fall through */ \
3490 if (mips_cpu == PROCESSOR_R3000 \
3491 || mips_cpu == PROCESSOR_R3900) \
3492 return COSTS_N_INSNS (35); \
3493 else if (mips_cpu == PROCESSOR_R6000) \
3494 return COSTS_N_INSNS (38); \
3495 else if (mips_cpu == PROCESSOR_R5000) \
3496 return COSTS_N_INSNS (36); \
3498 return COSTS_N_INSNS (69); \
3501 /* A sign extend from SImode to DImode in 64 bit mode is often \
3502 zero instructions, because the result can often be used \
3503 directly by another instruction; we'll call it one. */ \
3504 if (TARGET_64BIT && GET_MODE (X) == DImode \
3505 && GET_MODE (XEXP (X, 0)) == SImode) \
3506 return COSTS_N_INSNS (1); \
3508 return COSTS_N_INSNS (2); \
3511 if (TARGET_64BIT && GET_MODE (X) == DImode \
3512 && GET_MODE (XEXP (X, 0)) == SImode) \
3513 return COSTS_N_INSNS (2); \
3515 return COSTS_N_INSNS (1);
3517 /* An expression giving the cost of an addressing mode that
3518 contains ADDRESS. If not defined, the cost is computed from the
3519 form of the ADDRESS expression and the `CONST_COSTS' values.
3521 For most CISC machines, the default cost is a good approximation
3522 of the true cost of the addressing mode. However, on RISC
3523 machines, all instructions normally have the same length and
3524 execution time. Hence all addresses will have equal costs.
3526 In cases where more than one form of an address is known, the
3527 form with the lowest cost will be used. If multiple forms have
3528 the same, lowest, cost, the one that is the most complex will be
3531 For example, suppose an address that is equal to the sum of a
3532 register and a constant is used twice in the same basic block.
3533 When this macro is not defined, the address will be computed in
3534 a register and memory references will be indirect through that
3535 register. On machines where the cost of the addressing mode
3536 containing the sum is no higher than that of a simple indirect
3537 reference, this will produce an additional instruction and
3538 possibly require an additional register. Proper specification
3539 of this macro eliminates this overhead for such machines.
3541 Similar use of this macro is made in strength reduction of loops.
3543 ADDRESS need not be valid as an address. In such a case, the
3544 cost is not relevant and can be any value; invalid addresses
3545 need not be assigned a different cost.
3547 On machines where an address involving more than one register is
3548 as cheap as an address computation involving only one register,
3549 defining `ADDRESS_COST' to reflect this can cause two registers
3550 to be live over a region of code where only one would have been
3551 if `ADDRESS_COST' were not defined in that manner. This effect
3552 should be considered in the definition of this macro.
3553 Equivalent costs should probably only be given to addresses with
3554 different numbers of registers on machines with lots of registers.
3556 This macro will normally either not be defined or be defined as
3559 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3561 /* A C expression for the cost of moving data from a register in
3562 class FROM to one in class TO. The classes are expressed using
3563 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3564 the default; other values are interpreted relative to that.
3566 It is not required that the cost always equal 2 when FROM is the
3567 same as TO; on some machines it is expensive to move between
3568 registers if they are not general registers.
3570 If reload sees an insn consisting of a single `set' between two
3571 hard registers, and if `REGISTER_MOVE_COST' applied to their
3572 classes returns a value of 2, reload does not check to ensure
3573 that the constraints of the insn are met. Setting a cost of
3574 other than 2 will allow reload to verify that the constraints are
3575 met. You should do this if the `movM' pattern's constraints do
3576 not allow such copying. */
3578 #define REGISTER_MOVE_COST(FROM, TO) \
3579 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3580 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3581 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3582 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3583 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3584 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3585 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3586 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3587 : (((FROM) == HI_REG || (FROM) == LO_REG \
3588 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3589 && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6 \
3590 : (((FROM) == HI_REG || (FROM) == LO_REG \
3591 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3592 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 8 : 6) \
3593 : (((TO) == HI_REG || (TO) == LO_REG \
3594 || (TO) == MD_REGS || (TO) == HILO_REG) \
3595 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3596 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3597 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3600 /* ??? Fix this to be right for the R8000. */
3601 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3602 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3603 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3605 /* Define if copies to/from condition code registers should be avoided.
3607 This is needed for the MIPS because reload_outcc is not complete;
3608 it needs to handle cases where the source is a general or another
3609 condition code register. */
3610 #define AVOID_CCMODE_COPIES
3612 /* A C expression for the cost of a branch instruction. A value of
3613 1 is the default; other values are interpreted relative to that. */
3615 /* ??? Fix this to be right for the R8000. */
3616 #define BRANCH_COST \
3618 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3621 /* A C statement (sans semicolon) to update the integer variable COST
3622 based on the relationship between INSN that is dependent on
3623 DEP_INSN through the dependence LINK. The default is to make no
3624 adjustment to COST. On the MIPS, ignore the cost of anti- and
3625 output-dependencies. */
3627 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3628 if (REG_NOTE_KIND (LINK) != 0) \
3629 (COST) = 0; /* Anti or output dependence. */
3631 /* Optionally define this if you have added predicates to
3632 `MACHINE.c'. This macro is called within an initializer of an
3633 array of structures. The first field in the structure is the
3634 name of a predicate and the second field is an array of rtl
3635 codes. For each predicate, list all rtl codes that can be in
3636 expressions matched by the predicate. The list should have a
3637 trailing comma. Here is an example of two entries in the list
3638 for a typical RISC machine:
3640 #define PREDICATE_CODES \
3641 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3642 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3644 Defining this macro does not affect the generated code (however,
3645 incorrect definitions that omit an rtl code that may be matched
3646 by the predicate can cause the compiler to malfunction).
3647 Instead, it allows the table built by `genrecog' to be more
3648 compact and efficient, thus speeding up the compiler. The most
3649 important predicates to include in the list specified by this
3650 macro are thoses used in the most insn patterns. */
3652 #define PREDICATE_CODES \
3653 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3654 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3655 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3656 {"reg_or_0_operand", { REG, CONST_INT, SUBREG }}, \
3657 {"small_int", { CONST_INT }}, \
3658 {"large_int", { CONST_INT }}, \
3659 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3660 {"const_float_1_operand", { CONST_DOUBLE }}, \
3661 {"simple_memory_operand", { MEM, SUBREG }}, \
3662 {"equality_op", { EQ, NE }}, \
3663 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3665 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3666 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3667 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3668 SYMBOL_REF, LABEL_REF, SUBREG, \
3670 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3671 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3672 MEM, SIGN_EXTEND }}, \
3673 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3674 {"se_reg_or_0_operand", { REG, CONST_INT, SUBREG, \
3676 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3678 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3680 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3681 SYMBOL_REF, LABEL_REF, SUBREG, \
3682 REG, SIGN_EXTEND }}, \
3683 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3684 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3685 CONST_DOUBLE, CONST }}, \
3686 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3687 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3691 /* If defined, a C statement to be executed just prior to the
3692 output of assembler code for INSN, to modify the extracted
3693 operands so they will be output differently.
3695 Here the argument OPVEC is the vector containing the operands
3696 extracted from INSN, and NOPERANDS is the number of elements of
3697 the vector which contain meaningful data for this insn. The
3698 contents of this vector are what will be used to convert the
3699 insn template into assembler code, so you can change the
3700 assembler output by changing the contents of the vector.
3702 We use it to check if the current insn needs a nop in front of it
3703 because of load delays, and also to update the delay slot
3706 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3707 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3710 /* Control the assembler format that we output. */
3712 /* Output at beginning of assembler file.
3713 If we are optimizing to use the global pointer, create a temporary
3714 file to hold all of the text stuff, and write it out to the end.
3715 This is needed because the MIPS assembler is evidently one pass,
3716 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3717 declaration when the code is processed, it generates a two
3718 instruction sequence. */
3720 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3722 /* Output to assembler file text saying following lines
3723 may contain character constants, extra white space, comments, etc. */
3725 #define ASM_APP_ON " #APP\n"
3727 /* Output to assembler file text saying following lines
3728 no longer contain unusual constructs. */
3730 #define ASM_APP_OFF " #NO_APP\n"
3732 /* How to refer to registers in assembler output.
3733 This sequence is indexed by compiler's hard-register-number (see above).
3735 In order to support the two different conventions for register names,
3736 we use the name of a table set up in mips.c, which is overwritten
3737 if -mrnames is used. */
3739 #define REGISTER_NAMES \
3741 &mips_reg_names[ 0][0], \
3742 &mips_reg_names[ 1][0], \
3743 &mips_reg_names[ 2][0], \
3744 &mips_reg_names[ 3][0], \
3745 &mips_reg_names[ 4][0], \
3746 &mips_reg_names[ 5][0], \
3747 &mips_reg_names[ 6][0], \
3748 &mips_reg_names[ 7][0], \
3749 &mips_reg_names[ 8][0], \
3750 &mips_reg_names[ 9][0], \
3751 &mips_reg_names[10][0], \
3752 &mips_reg_names[11][0], \
3753 &mips_reg_names[12][0], \
3754 &mips_reg_names[13][0], \
3755 &mips_reg_names[14][0], \
3756 &mips_reg_names[15][0], \
3757 &mips_reg_names[16][0], \
3758 &mips_reg_names[17][0], \
3759 &mips_reg_names[18][0], \
3760 &mips_reg_names[19][0], \
3761 &mips_reg_names[20][0], \
3762 &mips_reg_names[21][0], \
3763 &mips_reg_names[22][0], \
3764 &mips_reg_names[23][0], \
3765 &mips_reg_names[24][0], \
3766 &mips_reg_names[25][0], \
3767 &mips_reg_names[26][0], \
3768 &mips_reg_names[27][0], \
3769 &mips_reg_names[28][0], \
3770 &mips_reg_names[29][0], \
3771 &mips_reg_names[30][0], \
3772 &mips_reg_names[31][0], \
3773 &mips_reg_names[32][0], \
3774 &mips_reg_names[33][0], \
3775 &mips_reg_names[34][0], \
3776 &mips_reg_names[35][0], \
3777 &mips_reg_names[36][0], \
3778 &mips_reg_names[37][0], \
3779 &mips_reg_names[38][0], \
3780 &mips_reg_names[39][0], \
3781 &mips_reg_names[40][0], \
3782 &mips_reg_names[41][0], \
3783 &mips_reg_names[42][0], \
3784 &mips_reg_names[43][0], \
3785 &mips_reg_names[44][0], \
3786 &mips_reg_names[45][0], \
3787 &mips_reg_names[46][0], \
3788 &mips_reg_names[47][0], \
3789 &mips_reg_names[48][0], \
3790 &mips_reg_names[49][0], \
3791 &mips_reg_names[50][0], \
3792 &mips_reg_names[51][0], \
3793 &mips_reg_names[52][0], \
3794 &mips_reg_names[53][0], \
3795 &mips_reg_names[54][0], \
3796 &mips_reg_names[55][0], \
3797 &mips_reg_names[56][0], \
3798 &mips_reg_names[57][0], \
3799 &mips_reg_names[58][0], \
3800 &mips_reg_names[59][0], \
3801 &mips_reg_names[60][0], \
3802 &mips_reg_names[61][0], \
3803 &mips_reg_names[62][0], \
3804 &mips_reg_names[63][0], \
3805 &mips_reg_names[64][0], \
3806 &mips_reg_names[65][0], \
3807 &mips_reg_names[66][0], \
3808 &mips_reg_names[67][0], \
3809 &mips_reg_names[68][0], \
3810 &mips_reg_names[69][0], \
3811 &mips_reg_names[70][0], \
3812 &mips_reg_names[71][0], \
3813 &mips_reg_names[72][0], \
3814 &mips_reg_names[73][0], \
3815 &mips_reg_names[74][0], \
3816 &mips_reg_names[75][0], \
3819 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3820 So define this for it. */
3821 #define DEBUG_REGISTER_NAMES \
3823 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3824 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3825 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3826 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3827 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3828 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3829 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3830 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3831 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3832 "$fcc5","$fcc6","$fcc7","$rap" \
3835 /* If defined, a C initializer for an array of structures
3836 containing a name and a register number. This macro defines
3837 additional names for hard registers, thus allowing the `asm'
3838 option in declarations to refer to registers using alternate
3841 We define both names for the integer registers here. */
3843 #define ADDITIONAL_REGISTER_NAMES \
3845 { "$0", 0 + GP_REG_FIRST }, \
3846 { "$1", 1 + GP_REG_FIRST }, \
3847 { "$2", 2 + GP_REG_FIRST }, \
3848 { "$3", 3 + GP_REG_FIRST }, \
3849 { "$4", 4 + GP_REG_FIRST }, \
3850 { "$5", 5 + GP_REG_FIRST }, \
3851 { "$6", 6 + GP_REG_FIRST }, \
3852 { "$7", 7 + GP_REG_FIRST }, \
3853 { "$8", 8 + GP_REG_FIRST }, \
3854 { "$9", 9 + GP_REG_FIRST }, \
3855 { "$10", 10 + GP_REG_FIRST }, \
3856 { "$11", 11 + GP_REG_FIRST }, \
3857 { "$12", 12 + GP_REG_FIRST }, \
3858 { "$13", 13 + GP_REG_FIRST }, \
3859 { "$14", 14 + GP_REG_FIRST }, \
3860 { "$15", 15 + GP_REG_FIRST }, \
3861 { "$16", 16 + GP_REG_FIRST }, \
3862 { "$17", 17 + GP_REG_FIRST }, \
3863 { "$18", 18 + GP_REG_FIRST }, \
3864 { "$19", 19 + GP_REG_FIRST }, \
3865 { "$20", 20 + GP_REG_FIRST }, \
3866 { "$21", 21 + GP_REG_FIRST }, \
3867 { "$22", 22 + GP_REG_FIRST }, \
3868 { "$23", 23 + GP_REG_FIRST }, \
3869 { "$24", 24 + GP_REG_FIRST }, \
3870 { "$25", 25 + GP_REG_FIRST }, \
3871 { "$26", 26 + GP_REG_FIRST }, \
3872 { "$27", 27 + GP_REG_FIRST }, \
3873 { "$28", 28 + GP_REG_FIRST }, \
3874 { "$29", 29 + GP_REG_FIRST }, \
3875 { "$30", 30 + GP_REG_FIRST }, \
3876 { "$31", 31 + GP_REG_FIRST }, \
3877 { "$sp", 29 + GP_REG_FIRST }, \
3878 { "$fp", 30 + GP_REG_FIRST }, \
3879 { "at", 1 + GP_REG_FIRST }, \
3880 { "v0", 2 + GP_REG_FIRST }, \
3881 { "v1", 3 + GP_REG_FIRST }, \
3882 { "a0", 4 + GP_REG_FIRST }, \
3883 { "a1", 5 + GP_REG_FIRST }, \
3884 { "a2", 6 + GP_REG_FIRST }, \
3885 { "a3", 7 + GP_REG_FIRST }, \
3886 { "t0", 8 + GP_REG_FIRST }, \
3887 { "t1", 9 + GP_REG_FIRST }, \
3888 { "t2", 10 + GP_REG_FIRST }, \
3889 { "t3", 11 + GP_REG_FIRST }, \
3890 { "t4", 12 + GP_REG_FIRST }, \
3891 { "t5", 13 + GP_REG_FIRST }, \
3892 { "t6", 14 + GP_REG_FIRST }, \
3893 { "t7", 15 + GP_REG_FIRST }, \
3894 { "s0", 16 + GP_REG_FIRST }, \
3895 { "s1", 17 + GP_REG_FIRST }, \
3896 { "s2", 18 + GP_REG_FIRST }, \
3897 { "s3", 19 + GP_REG_FIRST }, \
3898 { "s4", 20 + GP_REG_FIRST }, \
3899 { "s5", 21 + GP_REG_FIRST }, \
3900 { "s6", 22 + GP_REG_FIRST }, \
3901 { "s7", 23 + GP_REG_FIRST }, \
3902 { "t8", 24 + GP_REG_FIRST }, \
3903 { "t9", 25 + GP_REG_FIRST }, \
3904 { "k0", 26 + GP_REG_FIRST }, \
3905 { "k1", 27 + GP_REG_FIRST }, \
3906 { "gp", 28 + GP_REG_FIRST }, \
3907 { "sp", 29 + GP_REG_FIRST }, \
3908 { "fp", 30 + GP_REG_FIRST }, \
3909 { "ra", 31 + GP_REG_FIRST }, \
3910 { "$sp", 29 + GP_REG_FIRST }, \
3911 { "$fp", 30 + GP_REG_FIRST } \
3914 /* Define results of standard character escape sequences. */
3915 #define TARGET_BELL 007
3916 #define TARGET_BS 010
3917 #define TARGET_TAB 011
3918 #define TARGET_NEWLINE 012
3919 #define TARGET_VT 013
3920 #define TARGET_FF 014
3921 #define TARGET_CR 015
3923 /* A C compound statement to output to stdio stream STREAM the
3924 assembler syntax for an instruction operand X. X is an RTL
3927 CODE is a value that can be used to specify one of several ways
3928 of printing the operand. It is used when identical operands
3929 must be printed differently depending on the context. CODE
3930 comes from the `%' specification that was used to request
3931 printing of the operand. If the specification was just `%DIGIT'
3932 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3933 is the ASCII code for LTR.
3935 If X is a register, this macro should print the register's name.
3936 The names can be found in an array `reg_names' whose type is
3937 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3939 When the machine description has a specification `%PUNCT' (a `%'
3940 followed by a punctuation character), this macro is called with
3941 a null pointer for X and the punctuation character for CODE.
3943 See mips.c for the MIPS specific codes. */
3945 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3947 /* A C expression which evaluates to true if CODE is a valid
3948 punctuation character for use in the `PRINT_OPERAND' macro. If
3949 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3950 punctuation characters (except for the standard one, `%') are
3951 used in this way. */
3953 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3955 /* A C compound statement to output to stdio stream STREAM the
3956 assembler syntax for an instruction operand that is a memory
3957 reference whose address is ADDR. ADDR is an RTL expression.
3959 On some machines, the syntax for a symbolic address depends on
3960 the section that the address refers to. On these machines,
3961 define the macro `ENCODE_SECTION_INFO' to store the information
3962 into the `symbol_ref', and then check for it here. */
3964 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3967 /* A C statement, to be executed after all slot-filler instructions
3968 have been output. If necessary, call `dbr_sequence_length' to
3969 determine the number of slots filled in a sequence (zero if not
3970 currently outputting a sequence), to decide how many no-ops to
3971 output, or whatever.
3973 Don't define this macro if it has nothing to do, but it is
3974 helpful in reading assembly output if the extent of the delay
3975 sequence is made explicit (e.g. with white space).
3977 Note that output routines for instructions with delay slots must
3978 be prepared to deal with not being output as part of a sequence
3979 (i.e. when the scheduling pass is not run, or when no slot
3980 fillers could be found.) The variable `final_sequence' is null
3981 when not processing a sequence, otherwise it contains the
3982 `sequence' rtx being output. */
3984 #define DBR_OUTPUT_SEQEND(STREAM) \
3987 if (set_nomacro > 0 && --set_nomacro == 0) \
3988 fputs ("\t.set\tmacro\n", STREAM); \
3990 if (set_noreorder > 0 && --set_noreorder == 0) \
3991 fputs ("\t.set\treorder\n", STREAM); \
3993 dslots_jump_filled++; \
3994 fputs ("\n", STREAM); \
3999 /* How to tell the debugger about changes of source files. Note, the
4000 mips ECOFF format cannot deal with changes of files inside of
4001 functions, which means the output of parser generators like bison
4002 is generally not debuggable without using the -l switch. Lose,
4003 lose, lose. Silicon graphics seems to want all .file's hardwired
4006 #ifndef SET_FILE_NUMBER
4007 #define SET_FILE_NUMBER() ++num_source_filenames
4010 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4011 mips_output_filename (STREAM, NAME)
4013 /* This is defined so that it can be overridden in iris6.h. */
4014 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4017 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4018 output_quoted_string (STREAM, NAME); \
4019 fputs ("\n", STREAM); \
4023 /* This is how to output a note the debugger telling it the line number
4024 to which the following sequence of instructions corresponds.
4025 Silicon graphics puts a label after each .loc. */
4027 #ifndef LABEL_AFTER_LOC
4028 #define LABEL_AFTER_LOC(STREAM)
4031 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4032 mips_output_lineno (STREAM, LINE)
4034 /* The MIPS implementation uses some labels for its own purpose. The
4035 following lists what labels are created, and are all formed by the
4036 pattern $L[a-z].*. The machine independent portion of GCC creates
4037 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4039 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4040 $Lb[0-9]+ Begin blocks for MIPS debug support
4041 $Lc[0-9]+ Label for use in s<xx> operation.
4042 $Le[0-9]+ End blocks for MIPS debug support
4043 $Lp\..+ Half-pic labels. */
4045 /* This is how to output the definition of a user-level label named NAME,
4046 such as the label on a static function or variable NAME.
4048 If we are optimizing the gp, remember that this label has been put
4049 out, so we know not to emit an .extern for it in mips_asm_file_end.
4050 We use one of the common bits in the IDENTIFIER tree node for this,
4051 since those bits seem to be unused, and we don't have any method
4052 of getting the decl nodes from the name. */
4054 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4056 assemble_name (STREAM, NAME); \
4057 fputs (":\n", STREAM); \
4061 /* A C statement (sans semicolon) to output to the stdio stream
4062 STREAM any text necessary for declaring the name NAME of an
4063 initialized variable which is being defined. This macro must
4064 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4065 The argument DECL is the `VAR_DECL' tree node representing the
4068 If this macro is not defined, then the variable name is defined
4069 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4071 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4074 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4075 HALF_PIC_DECLARE (NAME); \
4080 /* This is how to output a command to make the user-level label named NAME
4081 defined for reference from other files. */
4083 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4085 fputs ("\t.globl\t", STREAM); \
4086 assemble_name (STREAM, NAME); \
4087 fputs ("\n", STREAM); \
4090 /* This says how to define a global common symbol. */
4092 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
4093 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
4095 /* This says how to define a local common symbol (ie, not visible to
4098 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4099 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4102 /* This says how to output an external. It would be possible not to
4103 output anything and let undefined symbol become external. However
4104 the assembler uses length information on externals to allocate in
4105 data/sdata bss/sbss, thereby saving exec time. */
4107 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4108 mips_output_external(STREAM,DECL,NAME)
4110 /* This says what to print at the end of the assembly file */
4111 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4114 /* This is how to declare a function name. The actual work of
4115 emitting the label is moved to function_prologue, so that we can
4116 get the line number correctly emitted before the .ent directive,
4117 and after any .file directives.
4119 Also, switch files if we are optimizing the global pointer. */
4121 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4123 extern FILE *asm_out_text_file; \
4124 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4126 STREAM = asm_out_text_file; \
4127 /* ??? text_section gets called too soon. If the previous \
4128 function is in a special section and we're not, we have \
4129 to switch back to the text section. We can't call \
4130 text_section again as gcc thinks we're already there. */ \
4131 /* ??? See varasm.c. There are other things that get output \
4132 too early, like alignment (before we've switched STREAM). */ \
4133 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4134 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4137 HALF_PIC_DECLARE (NAME); \
4140 /* This is how to output an internal numbered label where
4141 PREFIX is the class of label and NUM is the number within the class. */
4143 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4144 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4146 /* This is how to store into the string LABEL
4147 the symbol_ref name of an internal numbered label where
4148 PREFIX is the class of label and NUM is the number within the class.
4149 This is suitable for output with `assemble_name'. */
4151 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4152 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4154 /* This is how to output an assembler line defining a `double' constant. */
4156 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4157 mips_output_double (STREAM, VALUE)
4160 /* This is how to output an assembler line defining a `float' constant. */
4162 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4163 mips_output_float (STREAM, VALUE)
4166 /* This is how to output an assembler line defining an `int' constant. */
4168 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4170 fprintf (STREAM, "\t.word\t"); \
4171 output_addr_const (STREAM, (VALUE)); \
4172 fprintf (STREAM, "\n"); \
4175 /* Likewise for 64 bit, `char' and `short' constants. */
4177 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4181 fprintf (STREAM, "\t.dword\t"); \
4182 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4183 /* We can't use 'X' for negative numbers, because then we won't \
4184 get the right value for the upper 32 bits. */ \
4185 output_addr_const (STREAM, VALUE); \
4187 /* We must use 'X', because otherwise LONG_MIN will print as \
4188 a number that the Irix 6 assembler won't accept. */ \
4189 print_operand (STREAM, VALUE, 'X'); \
4190 fprintf (STREAM, "\n"); \
4194 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4195 UNITS_PER_WORD, 1); \
4196 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4197 UNITS_PER_WORD, 1); \
4201 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4203 fprintf (STREAM, "\t.half\t"); \
4204 output_addr_const (STREAM, (VALUE)); \
4205 fprintf (STREAM, "\n"); \
4208 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4210 fprintf (STREAM, "\t.byte\t"); \
4211 output_addr_const (STREAM, (VALUE)); \
4212 fprintf (STREAM, "\n"); \
4215 /* This is how to output an assembler line for a numeric constant byte. */
4217 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4218 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4220 /* This is how to output an element of a case-vector that is absolute. */
4222 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4223 fprintf (STREAM, "\t%s\t%sL%d\n", \
4224 Pmode == DImode ? ".dword" : ".word", \
4225 LOCAL_LABEL_PREFIX, \
4228 /* This is how to output an element of a case-vector that is relative.
4229 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4230 TARGET_EMBEDDED_PIC). */
4232 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4234 if (TARGET_MIPS16) \
4235 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4236 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4237 else if (TARGET_EMBEDDED_PIC) \
4238 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4239 Pmode == DImode ? ".dword" : ".word", \
4240 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4241 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4242 fprintf (STREAM, "\t%s\t%sL%d\n", \
4243 Pmode == DImode ? ".gpdword" : ".gpword", \
4244 LOCAL_LABEL_PREFIX, VALUE); \
4246 fprintf (STREAM, "\t%s\t%sL%d\n", \
4247 Pmode == DImode ? ".dword" : ".word", \
4248 LOCAL_LABEL_PREFIX, VALUE); \
4251 /* When generating embedded PIC or mips16 code we want to put the jump
4252 table in the .text section. In all other cases, we want to put the
4253 jump table in the .rdata section. Unfortunately, we can't use
4254 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4255 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4256 section if appropriate. */
4257 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4259 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4260 function_section (current_function_decl); \
4261 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4264 /* This is how to output an assembler line
4265 that says to advance the location counter
4266 to a multiple of 2**LOG bytes. */
4268 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4269 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4271 /* This is how to output an assembler line to advance the location
4272 counter by SIZE bytes. */
4274 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4275 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4277 /* This is how to output a string. */
4278 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4280 register int i, c, len = (LEN), cur_pos = 17; \
4281 register unsigned char *string = (unsigned char *)(STRING); \
4282 fprintf ((STREAM), "\t.ascii\t\""); \
4283 for (i = 0; i < len; i++) \
4285 register int c = string[i]; \
4291 putc ('\\', (STREAM)); \
4292 putc (c, (STREAM)); \
4296 case TARGET_NEWLINE: \
4297 fputs ("\\n", (STREAM)); \
4299 && (((c = string[i+1]) >= '\040' && c <= '~') \
4300 || c == TARGET_TAB)) \
4301 cur_pos = 32767; /* break right here */ \
4307 fputs ("\\t", (STREAM)); \
4312 fputs ("\\f", (STREAM)); \
4317 fputs ("\\b", (STREAM)); \
4322 fputs ("\\r", (STREAM)); \
4327 if (c >= ' ' && c < 0177) \
4329 putc (c, (STREAM)); \
4334 fprintf ((STREAM), "\\%03o", c); \
4339 if (cur_pos > 72 && i+1 < len) \
4342 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4345 fprintf ((STREAM), "\"\n"); \
4348 /* Handle certain cpp directives used in header files on sysV. */
4349 #define SCCS_DIRECTIVE
4351 /* Output #ident as a in the read-only data section. */
4352 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4355 int size = strlen (p) + 1; \
4357 assemble_string (p, size); \
4360 /* Default to -G 8 */
4361 #ifndef MIPS_DEFAULT_GVALUE
4362 #define MIPS_DEFAULT_GVALUE 8
4365 /* Define the strings to put out for each section in the object file. */
4366 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4367 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4368 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4369 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4370 #define READONLY_DATA_SECTION rdata_section
4371 #define SMALL_DATA_SECTION sdata_section
4373 /* What other sections we support other than the normal .data/.text. */
4375 #define EXTRA_SECTIONS in_sdata, in_rdata
4377 /* Define the additional functions to select our additional sections. */
4379 /* on the MIPS it is not a good idea to put constants in the text
4380 section, since this defeats the sdata/data mechanism. This is
4381 especially true when -O is used. In this case an effort is made to
4382 address with faster (gp) register relative addressing, which can
4383 only get at sdata and sbss items (there is no stext !!) However,
4384 if the constant is too large for sdata, and it's readonly, it
4385 will go into the .rdata section. */
4387 #define EXTRA_SECTION_FUNCTIONS \
4391 if (in_section != in_sdata) \
4393 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4394 in_section = in_sdata; \
4401 if (in_section != in_rdata) \
4403 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4404 in_section = in_rdata; \
4408 /* Given a decl node or constant node, choose the section to output it in
4409 and select that section. */
4411 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4413 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4416 /* Store in OUTPUT a string (made with alloca) containing
4417 an assembler-name for a local static variable named NAME.
4418 LABELNO is an integer which is different for each call. */
4420 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4421 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4422 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4424 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4427 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4428 TARGET_64BIT ? "dsubu" : "subu", \
4429 reg_names[STACK_POINTER_REGNUM], \
4430 reg_names[STACK_POINTER_REGNUM], \
4431 TARGET_64BIT ? "sd" : "sw", \
4433 reg_names[STACK_POINTER_REGNUM]); \
4437 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4440 if (! set_noreorder) \
4441 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4443 dslots_load_total++; \
4444 dslots_load_filled++; \
4445 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4446 TARGET_64BIT ? "ld" : "lw", \
4448 reg_names[STACK_POINTER_REGNUM], \
4449 TARGET_64BIT ? "daddu" : "addu", \
4450 reg_names[STACK_POINTER_REGNUM], \
4451 reg_names[STACK_POINTER_REGNUM]); \
4453 if (! set_noreorder) \
4454 fprintf (STREAM, "\t.set\treorder\n"); \
4458 /* Define the parentheses used to group arithmetic operations
4459 in assembler code. */
4461 #define ASM_OPEN_PAREN "("
4462 #define ASM_CLOSE_PAREN ")"
4464 /* How to start an assembler comment.
4465 The leading space is important (the mips native assembler requires it). */
4466 #ifndef ASM_COMMENT_START
4467 #define ASM_COMMENT_START " #"
4471 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4472 and mips-tdump.c to print them out.
4474 These must match the corresponding definitions in gdb/mipsread.c.
4475 Unfortunately, gcc and gdb do not currently share any directories. */
4477 #define CODE_MASK 0x8F300
4478 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4479 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4480 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4483 /* Default definitions for size_t and ptrdiff_t. */
4486 #define NO_BUILTIN_SIZE_TYPE
4487 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4490 #ifndef PTRDIFF_TYPE
4491 #define NO_BUILTIN_PTRDIFF_TYPE
4492 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4495 /* See mips_expand_prologue's use of loadgp for when this should be
4498 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4499 && mips_abi != ABI_32 \
4500 && mips_abi != ABI_O64)
4502 /* In mips16 mode, we need to look through the function to check for
4503 PC relative loads that are out of range. */
4504 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4506 /* We need to use a special set of functions to handle hard floating
4507 point code in mips16 mode. */
4509 #ifndef INIT_SUBTARGET_OPTABS
4510 #define INIT_SUBTARGET_OPTABS
4513 #define INIT_TARGET_OPTABS \
4516 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4517 INIT_SUBTARGET_OPTABS; \
4520 add_optab->handlers[(int) SFmode].libfunc = \
4521 gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3"); \
4522 sub_optab->handlers[(int) SFmode].libfunc = \
4523 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3"); \
4524 smul_optab->handlers[(int) SFmode].libfunc = \
4525 gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3"); \
4526 flodiv_optab->handlers[(int) SFmode].libfunc = \
4527 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3"); \
4529 eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2"); \
4530 nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2"); \
4531 gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2"); \
4532 gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2"); \
4533 ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2"); \
4534 lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2"); \
4536 floatsisf_libfunc = \
4537 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf"); \
4539 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi"); \
4541 if (TARGET_DOUBLE_FLOAT) \
4543 add_optab->handlers[(int) DFmode].libfunc = \
4544 gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3"); \
4545 sub_optab->handlers[(int) DFmode].libfunc = \
4546 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3"); \
4547 smul_optab->handlers[(int) DFmode].libfunc = \
4548 gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3"); \
4549 flodiv_optab->handlers[(int) DFmode].libfunc = \
4550 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3"); \
4552 extendsfdf2_libfunc = \
4553 gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2"); \
4554 truncdfsf2_libfunc = \
4555 gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2"); \
4558 gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2"); \
4560 gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2"); \
4562 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2"); \
4564 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2"); \
4566 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2"); \
4568 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2"); \
4570 floatsidf_libfunc = \
4571 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf"); \
4573 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi"); \
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