1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-97, 1998 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern char *language_string;
32 extern int may_call_alloca;
33 extern char **save_argv;
34 extern int target_flags;
35 extern char *version_string;
37 /* MIPS external variables defined in mips.c. */
41 CMP_SI, /* compare four byte integers */
42 CMP_DI, /* compare eight byte integers */
43 CMP_SF, /* compare single precision floats */
44 CMP_DF, /* compare double precision floats */
45 CMP_MAX /* max comparison type */
48 /* types of delay slot */
50 DELAY_NONE, /* no delay slot */
51 DELAY_LOAD, /* load from memory delay */
52 DELAY_HILO, /* move from/to hi/lo registers */
53 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
56 /* Which processor to schedule for. Since there is no difference between
57 a R2000 and R3000 in terms of the scheduler, we collapse them into
58 just an R3000. The elements of the enumeration must match exactly
59 the cpu attribute in the mips.md machine description. */
75 /* Recast the cpu class to be the cpu attribute. */
76 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
78 /* Which ABI to use. These are constants because abi64.h must check their
79 value at preprocessing time. */
86 #ifndef MIPS_ABI_DEFAULT
87 /* We define this away so that there is no extra runtime cost if the target
88 doesn't support multiple ABIs. */
89 #define mips_abi ABI_32
94 /* Whether to emit abicalls code sequences or not. */
96 enum mips_abicalls_type {
101 /* Recast the abicalls class to be the abicalls attribute. */
102 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
104 /* Which type of block move to do (whether or not the last store is
105 split out so it can fill a branch delay slot). */
107 enum block_move_type {
108 BLOCK_MOVE_NORMAL, /* generate complete block move */
109 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
110 BLOCK_MOVE_LAST /* generate just the last store */
113 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
114 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
115 extern char *current_function_file; /* filename current function is in */
116 extern int num_source_filenames; /* current .file # */
117 extern int inside_function; /* != 0 if inside of a function */
118 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
119 extern int file_in_function_warning; /* warning given about .file in func */
120 extern int sdb_label_count; /* block start/end next label # */
121 extern int sdb_begin_function_line; /* Starting Line of current function */
122 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
123 extern int g_switch_value; /* value of the -G xx switch */
124 extern int g_switch_set; /* whether -G xx was passed. */
125 extern int sym_lineno; /* sgi next label # for each stmt */
126 extern int set_noreorder; /* # of nested .set noreorder's */
127 extern int set_nomacro; /* # of nested .set nomacro's */
128 extern int set_noat; /* # of nested .set noat's */
129 extern int set_volatile; /* # of nested .set volatile's */
130 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
131 extern int mips_dbx_regno[]; /* Map register # to debug register # */
132 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
133 extern enum cmp_type branch_type; /* what type of branch to use */
134 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
135 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
136 extern int mips_isa; /* architectural level */
137 extern int mips16; /* whether generating mips16 code */
138 extern int mips16_hard_float; /* mips16 without -msoft-float */
139 extern int mips_entry; /* generate entry/exit for mips16 */
140 extern char *mips_cpu_string; /* for -mcpu=<xxx> */
141 extern char *mips_isa_string; /* for -mips{1,2,3,4} */
142 extern char *mips_abi_string; /* for -misa={32,n32,64} */
143 extern char *mips_entry_string; /* for -mentry */
144 extern char *mips_no_mips16_string; /* for -mno-mips16 */
145 extern int mips_split_addresses; /* perform high/lo_sum support */
146 extern int dslots_load_total; /* total # load related delay slots */
147 extern int dslots_load_filled; /* # filled load delay slots */
148 extern int dslots_jump_total; /* total # jump related delay slots */
149 extern int dslots_jump_filled; /* # filled jump delay slots */
150 extern int dslots_number_nops; /* # of nops needed by previous insn */
151 extern int num_refs[3]; /* # 1/2/3 word references */
152 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
153 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
154 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
155 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
156 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
157 extern int mips_string_length; /* length of strings for mips16 */
158 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
160 /* Functions within mips.c that we reference. */
162 extern void abort_with_insn ();
163 extern int arith32_operand ();
164 extern int arith_operand ();
165 extern int cmp_op ();
166 extern long compute_frame_size ();
167 extern void expand_block_move ();
168 extern int equality_op ();
169 extern void final_prescan_insn ();
170 extern struct rtx_def * function_arg ();
171 extern void function_arg_advance ();
172 extern int function_arg_partial_nregs ();
173 extern int function_arg_pass_by_reference ();
174 extern void function_epilogue ();
175 extern void function_prologue ();
176 extern void gen_conditional_branch ();
177 extern void gen_conditional_move ();
178 extern struct rtx_def * gen_int_relational ();
179 extern void init_cumulative_args ();
180 extern int large_int ();
181 extern int mips_address_cost ();
182 extern void mips_asm_file_end ();
183 extern void mips_asm_file_start ();
184 extern int mips_const_double_ok ();
185 extern void mips_count_memory_refs ();
186 extern int mips_debugger_offset ();
187 extern void mips_declare_object ();
188 extern int mips_epilogue_delay_slots ();
189 extern void mips_expand_epilogue ();
190 extern void mips_expand_prologue ();
191 extern int mips_check_split ();
192 extern char *mips_fill_delay_slot ();
193 extern char *mips_move_1word ();
194 extern char *mips_move_2words ();
195 extern void mips_output_double ();
196 extern int mips_output_external ();
197 extern void mips_output_float ();
198 extern void mips_output_filename ();
199 extern void mips_output_lineno ();
200 extern char *output_block_move ();
201 extern void override_options ();
202 extern int pc_or_label_operand ();
203 extern void print_operand_address ();
204 extern void print_operand ();
205 extern void print_options ();
206 extern int reg_or_0_operand ();
207 extern int simple_epilogue_p ();
208 extern int simple_memory_operand ();
209 extern int double_memory_operand ();
210 extern int small_int ();
212 extern int uns_arith_operand ();
213 extern struct rtx_def * embedded_pic_offset ();
214 extern void mips_order_regs_for_local_alloc ();
215 extern struct rtx_def * mips16_gp_pseudo_reg ();
216 extern struct rtx_def * mips16_gp_offset ();
217 extern int mips16_gp_offset_p ();
218 extern int mips16_constant_after_function_p ();
219 extern int build_mips16_call_stub ();
221 /* Recognition functions that return if a condition is true. */
222 extern int address_operand ();
223 extern int const_double_operand ();
224 extern int const_int_operand ();
225 extern int general_operand ();
226 extern int immediate_operand ();
227 extern int memory_address_p ();
228 extern int memory_operand ();
229 extern int nonimmediate_operand ();
230 extern int nonmemory_operand ();
231 extern int register_operand ();
232 extern int scratch_operand ();
233 extern int move_operand ();
234 extern int movdi_operand ();
235 extern int se_register_operand ();
236 extern int se_reg_or_0_operand ();
237 extern int se_uns_arith_operand ();
238 extern int se_arith_operand ();
239 extern int se_nonmemory_operand ();
240 extern int se_nonimmediate_operand ();
241 extern int m16_uimm3_b ();
242 extern int m16_simm4_1 ();
243 extern int m16_nsimm4_1 ();
244 extern int m16_simm5_1 ();
245 extern int m16_nsimm5_1 ();
246 extern int m16_uimm5_4 ();
247 extern int m16_nuimm5_4 ();
248 extern int m16_simm8_1 ();
249 extern int m16_nsimm8_1 ();
250 extern int m16_uimm8_1 ();
251 extern int m16_nuimm8_1 ();
252 extern int m16_uimm8_m1_1 ();
253 extern int m16_uimm8_4 ();
254 extern int m16_nuimm8_4 ();
255 extern int m16_simm8_8 ();
256 extern int m16_nsimm8_8 ();
257 extern int m16_usym8_4 ();
258 extern int m16_usym5_4 ();
260 /* Functions to change what output section we are using. */
261 extern void data_section ();
262 extern void rdata_section ();
263 extern void readonly_data_section ();
264 extern void sdata_section ();
265 extern void text_section ();
267 /* Stubs for half-pic support if not OSF/1 reference platform. */
270 #define HALF_PIC_P() 0
271 #define HALF_PIC_NUMBER_PTRS 0
272 #define HALF_PIC_NUMBER_REFS 0
273 #define HALF_PIC_ENCODE(DECL)
274 #define HALF_PIC_DECLARE(NAME)
275 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
276 #define HALF_PIC_ADDRESS_P(X) 0
277 #define HALF_PIC_PTR(X) X
278 #define HALF_PIC_FINISH(STREAM)
282 /* Run-time compilation parameters selecting different hardware subsets. */
284 /* Macros used in the machine description to test the flags. */
286 /* Bits for real switches */
287 #define MASK_INT64 0x00000001 /* ints are 64 bits */
288 #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
289 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
290 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
291 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
292 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
293 #define MASK_STATS 0x00000040 /* print statistics to stderr */
294 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
295 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
296 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
297 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
298 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
299 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
300 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
301 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
302 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
303 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
304 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
305 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
306 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
307 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
308 #define MASK_MIPS16 0x01000000 /* Generate mips16 code */
310 /* Dummy switches used only in spec's*/
311 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
313 /* Debug switches, not documented */
314 #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */
315 #define MASK_DEBUG_A 0x20000000 /* don't allow <label>($reg) addrs */
316 #define MASK_DEBUG_B 0x10000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
317 #define MASK_DEBUG_C 0x08000000 /* don't expand seq, etc. */
318 #define MASK_DEBUG_D 0x04000000 /* don't do define_split's */
319 #define MASK_DEBUG_E 0x02000000 /* function_arg debug */
320 #define MASK_DEBUG_F 0
321 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
322 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
323 #define MASK_DEBUG_I 0x00200000 /* unused */
325 /* r4000 64 bit sizes */
326 #define TARGET_INT64 (target_flags & MASK_INT64)
327 #define TARGET_LONG64 (target_flags & MASK_LONG64)
328 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
329 #define TARGET_64BIT (target_flags & MASK_64BIT)
331 /* Mips vs. GNU linker */
332 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
334 /* generate mips 3900 insns */
335 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
337 /* Mips vs. GNU assembler */
338 #define TARGET_GAS (target_flags & MASK_GAS)
339 #define TARGET_UNIX_ASM (!TARGET_GAS)
340 #define TARGET_MIPS_AS TARGET_UNIX_ASM
343 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
344 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
345 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
346 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
347 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
348 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
349 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
350 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
351 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
352 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
354 /* Reg. Naming in .s ($21 vs. $a0) */
355 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
357 /* Optimize for Sdata/Sbss */
358 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
360 /* print program statistics */
361 #define TARGET_STATS (target_flags & MASK_STATS)
363 /* call memcpy instead of inline code */
364 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
366 /* .abicalls, etc from Pyramid V.4 */
367 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
369 /* OSF pic references to externs */
370 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
372 /* software floating point */
373 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
374 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
376 /* always call through a register */
377 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
379 /* generate embedded PIC code;
381 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
383 /* for embedded systems, optimize for
384 reduced RAM space instead of for
386 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
388 /* generate big endian code. */
389 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
391 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
392 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
394 #define TARGET_MAD (target_flags & MASK_MAD)
396 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
398 /* This is true if we must enable the assembly language file switching
401 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
403 /* We must disable the function end stabs when doing the file switching trick,
404 because the Lscope stabs end up in the wrong place, making it impossible
405 to debug the resulting code. */
406 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
408 /* Generate mips16 code */
409 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
411 /* Macro to define tables used to set the flags.
412 This is a list in braces of pairs in braces,
413 each pair being { "NAME", VALUE }
414 where VALUE is the bits to set or minus the bits to clear.
415 An empty string NAME is used to identify the default VALUE. */
417 #define TARGET_SWITCHES \
419 {"int64", MASK_INT64 | MASK_LONG64}, \
420 {"long64", MASK_LONG64}, \
421 {"split-addresses", MASK_SPLIT_ADDR}, \
422 {"no-split-addresses", -MASK_SPLIT_ADDR}, \
423 {"mips-as", -MASK_GAS}, \
425 {"rnames", MASK_NAME_REGS}, \
426 {"no-rnames", -MASK_NAME_REGS}, \
427 {"gpOPT", MASK_GPOPT}, \
428 {"gpopt", MASK_GPOPT}, \
429 {"no-gpOPT", -MASK_GPOPT}, \
430 {"no-gpopt", -MASK_GPOPT}, \
431 {"stats", MASK_STATS}, \
432 {"no-stats", -MASK_STATS}, \
433 {"memcpy", MASK_MEMCPY}, \
434 {"no-memcpy", -MASK_MEMCPY}, \
435 {"mips-tfile", MASK_MIPS_TFILE}, \
436 {"no-mips-tfile", -MASK_MIPS_TFILE}, \
437 {"soft-float", MASK_SOFT_FLOAT}, \
438 {"hard-float", -MASK_SOFT_FLOAT}, \
439 {"fp64", MASK_FLOAT64}, \
440 {"fp32", -MASK_FLOAT64}, \
441 {"gp64", MASK_64BIT}, \
442 {"gp32", -MASK_64BIT}, \
443 {"abicalls", MASK_ABICALLS}, \
444 {"no-abicalls", -MASK_ABICALLS}, \
445 {"half-pic", MASK_HALF_PIC}, \
446 {"no-half-pic", -MASK_HALF_PIC}, \
447 {"long-calls", MASK_LONG_CALLS}, \
448 {"no-long-calls", -MASK_LONG_CALLS}, \
449 {"embedded-pic", MASK_EMBEDDED_PIC}, \
450 {"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
451 {"embedded-data", MASK_EMBEDDED_DATA}, \
452 {"no-embedded-data", -MASK_EMBEDDED_DATA}, \
453 {"eb", MASK_BIG_ENDIAN}, \
454 {"el", -MASK_BIG_ENDIAN}, \
455 {"single-float", MASK_SINGLE_FLOAT}, \
456 {"double-float", -MASK_SINGLE_FLOAT}, \
458 {"no-mad", -MASK_MAD}, \
459 {"fix4300", MASK_4300_MUL_FIX}, \
460 {"no-fix4300", -MASK_4300_MUL_FIX}, \
461 {"4650", MASK_MAD | MASK_SINGLE_FLOAT}, \
462 {"3900", MASK_MIPS3900}, \
463 {"debug", MASK_DEBUG}, \
464 {"debuga", MASK_DEBUG_A}, \
465 {"debugb", MASK_DEBUG_B}, \
466 {"debugc", MASK_DEBUG_C}, \
467 {"debugd", MASK_DEBUG_D}, \
468 {"debuge", MASK_DEBUG_E}, \
469 {"debugf", MASK_DEBUG_F}, \
470 {"debugg", MASK_DEBUG_G}, \
471 {"debugh", MASK_DEBUG_H}, \
472 {"debugi", MASK_DEBUG_I}, \
473 {"", (TARGET_DEFAULT \
474 | TARGET_CPU_DEFAULT \
475 | TARGET_ENDIAN_DEFAULT)} \
478 /* Default target_flags if no switches are specified */
480 #ifndef TARGET_DEFAULT
481 #define TARGET_DEFAULT 0
484 #ifndef TARGET_CPU_DEFAULT
485 #define TARGET_CPU_DEFAULT 0
488 #ifndef TARGET_ENDIAN_DEFAULT
490 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
492 #define TARGET_ENDIAN_DEFAULT 0
496 #ifndef MULTILIB_DEFAULTS
497 #if TARGET_ENDIAN_DEFAULT == 0
498 #define MULTILIB_DEFAULTS { "EL", "mips1" }
500 #define MULTILIB_DEFAULTS { "EB", "mips1" }
504 /* We must pass -EL to the linker by default for little endian embedded
505 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
506 linker will default to using big-endian output files. The OUTPUT_FORMAT
507 line must be in the linker script, otherwise -EB/-EL will not work. */
509 #ifndef LINKER_ENDIAN_SPEC
510 #if TARGET_ENDIAN_DEFAULT == 0
511 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
513 #define LINKER_ENDIAN_SPEC ""
517 /* This macro is similar to `TARGET_SWITCHES' but defines names of
518 command options that have values. Its definition is an
519 initializer with a subgrouping for each command option.
521 Each subgrouping contains a string constant, that defines the
522 fixed part of the option name, and the address of a variable.
523 The variable, type `char *', is set to the variable part of the
524 given option if the fixed part matches. The actual option name
525 is made by appending `-m' to the specified name.
527 Here is an example which defines `-mshort-data-NUMBER'. If the
528 given option is `-mshort-data-512', the variable `m88k_short_data'
529 will be set to the string `"512"'.
531 extern char *m88k_short_data;
532 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
534 #define TARGET_OPTIONS \
536 SUBTARGET_TARGET_OPTIONS \
537 { "cpu=", &mips_cpu_string }, \
538 { "ips", &mips_isa_string }, \
539 { "entry", &mips_entry_string }, \
540 { "no-mips16", &mips_no_mips16_string }
543 /* This is meant to be redefined in the host dependent files. */
544 #define SUBTARGET_TARGET_OPTIONS
546 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
547 #define GENERATE_MULT3 (TARGET_MIPS3900 \
549 #define GENERATE_MADD (TARGET_MIPS3900 \
554 /* Macros to decide whether certain features are available or not,
555 depending on the instruction set architecture level. */
557 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
558 #define HAVE_SQRT_P() (mips_isa >= 2)
560 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
561 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
562 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
563 target_flags, and -mgp64 sets MASK_64BIT.
565 Setting MASK_64BIT in target_flags will cause gcc to assume that
566 registers are 64 bits wide. int, long and void * will be 32 bit;
567 this may be changed with -mint64 or -mlong64.
569 The gen* programs link code that refers to MASK_64BIT. They don't
570 actually use the information in target_flags; they just refer to
573 /* Switch Recognition by gcc.c. Add -G xx support */
575 #ifdef SWITCH_TAKES_ARG
576 #undef SWITCH_TAKES_ARG
579 #define SWITCH_TAKES_ARG(CHAR) \
580 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
582 /* Sometimes certain combinations of command options do not make sense
583 on a particular target machine. You can define a macro
584 `OVERRIDE_OPTIONS' to take account of this. This macro, if
585 defined, is executed once just after all the command options have
588 On the MIPS, it is used to handle -G. We also use it to set up all
589 of the tables referenced in the other macros. */
591 #define OVERRIDE_OPTIONS override_options ()
593 /* Zero or more C statements that may conditionally modify two
594 variables `fixed_regs' and `call_used_regs' (both of type `char
595 []') after they have been initialized from the two preceding
598 This is necessary in case the fixed or call-clobbered registers
599 depend on target flags.
601 You need not define this macro if it has no work to do.
603 If the usage of an entire class of registers depends on the target
604 flags, you may indicate this to GCC by using this macro to modify
605 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
606 the classes which should not be used by GCC. Also define the macro
607 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
608 letter for a class that shouldn't be used.
610 (However, if this class is not included in `GENERAL_REGS' and all
611 of the insn patterns whose constraints permit this class are
612 controlled by target switches, then GCC will automatically avoid
613 using these registers when the target switches are opposed to
616 #define CONDITIONAL_REGISTER_USAGE \
619 if (!TARGET_HARD_FLOAT) \
623 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
624 fixed_regs[regno] = call_used_regs[regno] = 1; \
625 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
626 fixed_regs[regno] = call_used_regs[regno] = 1; \
628 else if (mips_isa < 4) \
632 /* We only have a single condition code register. We \
633 implement this by hiding all the condition code registers, \
634 and generating RTL that refers directly to ST_REG_FIRST. */ \
635 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
636 fixed_regs[regno] = call_used_regs[regno] = 1; \
638 /* In mips16 mode, we permit the $t temporary registers to be used \
639 for reload. We prohibit the unused $s registers, since they \
640 are caller saved, and saving them via a mips16 register would \
641 probably waste more time than just reloading the value. */ \
644 fixed_regs[18] = call_used_regs[18] = 1; \
645 fixed_regs[19] = call_used_regs[19] = 1; \
646 fixed_regs[20] = call_used_regs[20] = 1; \
647 fixed_regs[21] = call_used_regs[21] = 1; \
648 fixed_regs[22] = call_used_regs[22] = 1; \
649 fixed_regs[23] = call_used_regs[23] = 1; \
650 fixed_regs[26] = call_used_regs[26] = 1; \
651 fixed_regs[27] = call_used_regs[27] = 1; \
652 fixed_regs[30] = call_used_regs[30] = 1; \
654 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
658 /* This is meant to be redefined in the host dependent files. */
659 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
661 /* Show we can debug even without a frame pointer. */
662 #define CAN_DEBUG_WITHOUT_FP
664 /* Complain about missing specs and predefines that should be defined in each
665 of the target tm files to override the defaults. This is mostly a place-
666 holder until I can get each of the files updated [mm]. */
668 #if defined(OSF_OS) \
669 || defined(DECSTATION) \
670 || defined(SGI_TARGET) \
671 || defined(MIPS_NEWS) \
672 || defined(MIPS_SYSV) \
673 || defined(MIPS_SVR4) \
674 || defined(MIPS_BSD43)
676 #ifndef CPP_PREDEFINES
677 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
681 #error "Define LIB_SPEC in the appropriate tm.h file"
684 #ifndef STARTFILE_SPEC
685 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
689 #error "Define MACHINE_TYPE in the appropriate tm.h file"
693 /* Tell collect what flags to pass to nm. */
695 #define NM_FLAGS "-Bp"
699 /* Names to predefine in the preprocessor for this target machine. */
701 #ifndef CPP_PREDEFINES
702 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
703 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
704 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
707 /* Assembler specs. */
709 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
712 #define MIPS_AS_ASM_SPEC "\
713 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
714 %{pipe: %e-pipe is not supported.} \
715 %{K} %(subtarget_mips_as_asm_spec)"
717 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
718 rather than gas. It may be overridden by subtargets. */
720 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
721 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
724 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
727 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
729 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
730 GAS_ASM_SPEC as the default, depending upon the value of
733 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
736 #define TARGET_ASM_SPEC "\
737 %{mmips-as: %(mips_as_asm_spec)} \
738 %{!mmips-as: %(gas_asm_spec)}"
742 #define TARGET_ASM_SPEC "\
743 %{!mgas: %(mips_as_asm_spec)} \
744 %{mgas: %(gas_asm_spec)}"
748 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
749 to the assembler. It may be overridden by subtargets. */
750 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
751 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
753 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
756 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
757 the assembler. It may be overridden by subtargets. */
758 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
759 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
760 %{g} %{g0} %{g1} %{g2} %{g3} \
761 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
762 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
763 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
764 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
767 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
768 overridden by subtargets. */
770 #ifndef SUBTARGET_ASM_SPEC
771 #define SUBTARGET_ASM_SPEC ""
774 /* ASM_SPEC is the set of arguments to pass to the assembler. */
777 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
778 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
779 %(subtarget_asm_optimizing_spec) \
780 %(subtarget_asm_debugging_spec) \
782 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
784 %(subtarget_asm_spec)"
786 /* Specify to run a post-processor, mips-tfile after the assembler
787 has run to stuff the mips debug information into the object file.
788 This is needed because the $#!%^ MIPS assembler provides no way
789 of specifying such information in the assembly file. If we are
790 cross compiling, disable mips-tfile unless the user specifies
793 #ifndef ASM_FINAL_SPEC
794 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
796 #define ASM_FINAL_SPEC "\
797 %{mmips-as: %{!mno-mips-tfile: \
798 \n mips-tfile %{v*: -v} \
800 %{!K: %{save-temps: -I %b.o~}} \
801 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
802 %{.s:%i} %{!.s:%g.s}}}"
806 #define ASM_FINAL_SPEC "\
807 %{!mgas: %{!mno-mips-tfile: \
808 \n mips-tfile %{v*: -v} \
810 %{!K: %{save-temps: -I %b.o~}} \
811 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
812 %{.s:%i} %{!.s:%g.s}}}"
815 #endif /* ASM_FINAL_SPEC */
817 /* Redefinition of libraries used. Mips doesn't support normal
818 UNIX style profiling via calling _mcount. It does offer
819 profiling that samples the PC, so do what we can... */
822 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
825 /* Extra switches sometimes passed to the linker. */
826 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
827 will interpret it as a -b option. */
831 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
832 %{bestGnum} %{shared} %{non_shared} \
833 %(linker_endian_spec)"
834 #endif /* LINK_SPEC defined */
836 /* Specs for the compiler proper */
838 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
839 overridden by subtargets. */
840 #ifndef SUBTARGET_CC1_SPEC
841 #define SUBTARGET_CC1_SPEC ""
844 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
848 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
849 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
850 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
851 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
852 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
853 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
854 %{m4650:-mcpu=r4650} \
855 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
856 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
857 %{pic-none: -mno-half-pic} \
858 %{pic-lib: -mhalf-pic} \
859 %{pic-extern: -mhalf-pic} \
860 %{pic-calls: -mhalf-pic} \
862 %(subtarget_cc1_spec) "
865 /* Preprocessor specs. */
867 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
868 be overridden by subtargets. */
870 #ifndef SUBTARGET_CPP_SIZE_SPEC
871 #define SUBTARGET_CPP_SIZE_SPEC "\
872 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
873 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
876 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
877 overridden by subtargets. */
878 #ifndef SUBTARGET_CPP_SPEC
879 #define SUBTARGET_CPP_SPEC ""
882 /* If we're using 64bit longs, then we have to define __LONG_MAX__
883 correctly. Similarly for 64bit ints and __INT_MAX__. */
884 #ifndef LONG_MAX_SPEC
885 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
886 #define LONG_MAX_SPEC "%{!mno-long64:-D__LONG_MAX__=9223372036854775807L}"
888 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
892 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
896 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
897 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
898 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
899 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
900 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
901 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
902 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
903 %(subtarget_cpp_size_spec) \
904 %{mips3:-U__mips -D__mips=3 -D__mips64} \
905 %{mips4:-U__mips -D__mips=4 -D__mips64} \
906 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
907 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
908 %{m4650:%{!msoft-float:-D__mips_single_float}} \
909 %{msoft-float:-D__mips_soft_float} \
910 %{mabi=eabi:-D__mips_eabi} \
911 %{mips16:%{!mno-mips16:-D__mips16}} \
912 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
913 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
915 %(subtarget_cpp_spec) "
918 /* This macro defines names of additional specifications to put in the specs
919 that can be used in various specifications like CC1_SPEC. Its definition
920 is an initializer with a subgrouping for each command option.
922 Each subgrouping contains a string constant, that defines the
923 specification name, and a string constant that used by the GNU CC driver
926 Do not define this macro if it does not need to do anything. */
928 #define EXTRA_SPECS \
929 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
930 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
931 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
932 { "long_max_spec", LONG_MAX_SPEC }, \
933 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
934 { "gas_asm_spec", GAS_ASM_SPEC }, \
935 { "target_asm_spec", TARGET_ASM_SPEC }, \
936 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
937 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
938 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
939 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
940 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
941 SUBTARGET_EXTRA_SPECS
943 #ifndef SUBTARGET_EXTRA_SPECS
944 #define SUBTARGET_EXTRA_SPECS
947 /* If defined, this macro is an additional prefix to try after
948 `STANDARD_EXEC_PREFIX'. */
950 #ifndef MD_EXEC_PREFIX
951 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
954 #ifndef MD_STARTFILE_PREFIX
955 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
959 /* Print subsidiary information on the compiler version in use. */
961 #define MIPS_VERSION "[AL 1.1, MM 40]"
964 #define MACHINE_TYPE "BSD Mips"
967 #ifndef TARGET_VERSION_INTERNAL
968 #define TARGET_VERSION_INTERNAL(STREAM) \
969 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
972 #ifndef TARGET_VERSION
973 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
977 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
978 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
979 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
981 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
982 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
985 /* By default, turn on GDB extensions. */
986 #define DEFAULT_GDB_EXTENSIONS 1
988 /* If we are passing smuggling stabs through the MIPS ECOFF object
989 format, put a comment in front of the .stab<x> operation so
990 that the MIPS assembler does not choke. The mips-tfile program
991 will correctly put the stab into the object file. */
993 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
994 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
995 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
997 /* Local compiler-generated symbols must have a prefix that the assembler
998 understands. By default, this is $, although some targets (e.g.,
999 NetBSD-ELF) need to override this. */
1001 #ifndef LOCAL_LABEL_PREFIX
1002 #define LOCAL_LABEL_PREFIX "$"
1005 /* By default on the mips, external symbols do not have an underscore
1006 prepended, but some targets (e.g., NetBSD) require this. */
1008 #ifndef USER_LABEL_PREFIX
1009 #define USER_LABEL_PREFIX ""
1012 /* Forward references to tags are allowed. */
1013 #define SDB_ALLOW_FORWARD_REFERENCES
1015 /* Unknown tags are also allowed. */
1016 #define SDB_ALLOW_UNKNOWN_REFERENCES
1018 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1019 since the length can run past this up to a continuation point. */
1020 #define DBX_CONTIN_LENGTH 1500
1022 /* How to renumber registers for dbx and gdb. */
1023 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1025 /* The mapping from gcc register number to DWARF 2 CFA column number.
1026 This mapping does not allow for tracking register 0, since SGI's broken
1027 dwarf reader thinks column 0 is used for the frame address, but since
1028 register 0 is fixed this is not a problem. */
1029 #define DWARF_FRAME_REGNUM(REG) \
1030 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1032 /* The DWARF 2 CFA column which tracks the return address. */
1033 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1035 /* Before the prologue, RA lives in r31. */
1036 #define INCOMING_RETURN_ADDR_RTX gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
1038 /* Overrides for the COFF debug format. */
1039 #define PUT_SDB_SCL(a) \
1041 extern FILE *asm_out_text_file; \
1042 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1045 #define PUT_SDB_INT_VAL(a) \
1047 extern FILE *asm_out_text_file; \
1048 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1051 #define PUT_SDB_VAL(a) \
1053 extern FILE *asm_out_text_file; \
1054 fputs ("\t.val\t", asm_out_text_file); \
1055 output_addr_const (asm_out_text_file, (a)); \
1056 fputc (';', asm_out_text_file); \
1059 #define PUT_SDB_DEF(a) \
1061 extern FILE *asm_out_text_file; \
1062 fprintf (asm_out_text_file, "\t%s.def\t", \
1063 (TARGET_GAS) ? "" : "#"); \
1064 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1065 fputc (';', asm_out_text_file); \
1068 #define PUT_SDB_PLAIN_DEF(a) \
1070 extern FILE *asm_out_text_file; \
1071 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1072 (TARGET_GAS) ? "" : "#", (a)); \
1075 #define PUT_SDB_ENDEF \
1077 extern FILE *asm_out_text_file; \
1078 fprintf (asm_out_text_file, "\t.endef\n"); \
1081 #define PUT_SDB_TYPE(a) \
1083 extern FILE *asm_out_text_file; \
1084 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1087 #define PUT_SDB_SIZE(a) \
1089 extern FILE *asm_out_text_file; \
1090 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1093 #define PUT_SDB_DIM(a) \
1095 extern FILE *asm_out_text_file; \
1096 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1099 #ifndef PUT_SDB_START_DIM
1100 #define PUT_SDB_START_DIM \
1102 extern FILE *asm_out_text_file; \
1103 fprintf (asm_out_text_file, "\t.dim\t"); \
1107 #ifndef PUT_SDB_NEXT_DIM
1108 #define PUT_SDB_NEXT_DIM(a) \
1110 extern FILE *asm_out_text_file; \
1111 fprintf (asm_out_text_file, "%d,", a); \
1115 #ifndef PUT_SDB_LAST_DIM
1116 #define PUT_SDB_LAST_DIM(a) \
1118 extern FILE *asm_out_text_file; \
1119 fprintf (asm_out_text_file, "%d;", a); \
1123 #define PUT_SDB_TAG(a) \
1125 extern FILE *asm_out_text_file; \
1126 fprintf (asm_out_text_file, "\t.tag\t"); \
1127 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1128 fputc (';', asm_out_text_file); \
1131 /* For block start and end, we create labels, so that
1132 later we can figure out where the correct offset is.
1133 The normal .ent/.end serve well enough for functions,
1134 so those are just commented out. */
1136 #define PUT_SDB_BLOCK_START(LINE) \
1138 extern FILE *asm_out_text_file; \
1139 fprintf (asm_out_text_file, \
1140 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1141 LOCAL_LABEL_PREFIX, \
1143 (TARGET_GAS) ? "" : "#", \
1144 LOCAL_LABEL_PREFIX, \
1147 sdb_label_count++; \
1150 #define PUT_SDB_BLOCK_END(LINE) \
1152 extern FILE *asm_out_text_file; \
1153 fprintf (asm_out_text_file, \
1154 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1155 LOCAL_LABEL_PREFIX, \
1157 (TARGET_GAS) ? "" : "#", \
1158 LOCAL_LABEL_PREFIX, \
1161 sdb_label_count++; \
1164 #define PUT_SDB_FUNCTION_START(LINE)
1166 #define PUT_SDB_FUNCTION_END(LINE) \
1168 extern FILE *asm_out_text_file; \
1169 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1172 #define PUT_SDB_EPILOGUE_END(NAME)
1174 #define PUT_SDB_SRC_FILE(FILENAME) \
1176 extern FILE *asm_out_text_file; \
1177 output_file_directive (asm_out_text_file, (FILENAME)); \
1180 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1181 sprintf ((BUFFER), ".%dfake", (NUMBER));
1183 /* Correct the offset of automatic variables and arguments. Note that
1184 the MIPS debug format wants all automatic variables and arguments
1185 to be in terms of the virtual frame pointer (stack pointer before
1186 any adjustment in the function), while the MIPS 3.0 linker wants
1187 the frame pointer to be the stack pointer after the initial
1190 #define DEBUGGER_AUTO_OFFSET(X) mips_debugger_offset (X, 0)
1191 #define DEBUGGER_ARG_OFFSET(OFFSET, X) mips_debugger_offset (X, OFFSET)
1194 /* Tell collect that the object format is ECOFF */
1195 #ifndef OBJECT_FORMAT_ROSE
1196 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1197 #define EXTENDED_COFF /* ECOFF, not normal coff */
1200 #if 0 /* These definitions normally have no effect because
1201 MIPS systems define USE_COLLECT2, so
1202 assemble_constructor does nothing anyway. */
1204 /* Don't use the default definitions, because we don't have gld.
1205 Also, we don't want stabs when generating ECOFF output.
1206 Instead we depend on collect to handle these. */
1208 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1209 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1213 /* Target machine storage layout */
1215 /* Define in order to support both big and little endian float formats
1216 in the same gcc binary. */
1217 #define REAL_ARITHMETIC
1219 /* Define this if most significant bit is lowest numbered
1220 in instructions that operate on numbered bit-fields.
1222 #define BITS_BIG_ENDIAN 0
1224 /* Define this if most significant byte of a word is the lowest numbered. */
1225 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1227 /* Define this if most significant word of a multiword number is the lowest. */
1228 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1230 /* Define this to set the endianness to use in libgcc2.c, which can
1231 not depend on target_flags. */
1232 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1233 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1235 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1238 /* Number of bits in an addressable storage unit */
1239 #define BITS_PER_UNIT 8
1241 /* Width in bits of a "word", which is the contents of a machine register.
1242 Note that this is not necessarily the width of data type `int';
1243 if using 16-bit ints on a 68000, this would still be 32.
1244 But on a machine with 16-bit registers, this would be 16. */
1245 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1246 #define MAX_BITS_PER_WORD 64
1248 /* Width of a word, in units (bytes). */
1249 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1250 #define MIN_UNITS_PER_WORD 4
1252 /* For MIPS, width of a floating point register. */
1253 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1255 /* A C expression for the size in bits of the type `int' on the
1256 target machine. If you don't define this, the default is one
1258 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1259 #define MAX_INT_TYPE_SIZE 64
1261 /* Tell the preprocessor the maximum size of wchar_t. */
1262 #ifndef MAX_WCHAR_TYPE_SIZE
1263 #ifndef WCHAR_TYPE_SIZE
1264 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1268 /* A C expression for the size in bits of the type `short' on the
1269 target machine. If you don't define this, the default is half a
1270 word. (If this would be less than one storage unit, it is
1271 rounded up to one unit.) */
1272 #define SHORT_TYPE_SIZE 16
1274 /* A C expression for the size in bits of the type `long' on the
1275 target machine. If you don't define this, the default is one
1277 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1278 #define MAX_LONG_TYPE_SIZE 64
1280 /* A C expression for the size in bits of the type `long long' on the
1281 target machine. If you don't define this, the default is two
1283 #define LONG_LONG_TYPE_SIZE 64
1285 /* A C expression for the size in bits of the type `char' on the
1286 target machine. If you don't define this, the default is one
1287 quarter of a word. (If this would be less than one storage unit,
1288 it is rounded up to one unit.) */
1289 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1291 /* A C expression for the size in bits of the type `float' on the
1292 target machine. If you don't define this, the default is one
1294 #define FLOAT_TYPE_SIZE 32
1296 /* A C expression for the size in bits of the type `double' on the
1297 target machine. If you don't define this, the default is two
1299 #define DOUBLE_TYPE_SIZE 64
1301 /* A C expression for the size in bits of the type `long double' on
1302 the target machine. If you don't define this, the default is two
1304 #define LONG_DOUBLE_TYPE_SIZE 64
1306 /* Width in bits of a pointer.
1307 See also the macro `Pmode' defined below. */
1308 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1310 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1311 #define POINTER_BOUNDARY (TARGET_LONG64 ? 64 : 32)
1313 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1314 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1316 /* Allocation boundary (in *bits*) for the code of a function. */
1317 #define FUNCTION_BOUNDARY 32
1319 /* Alignment of field after `int : 0' in a structure. */
1320 #define EMPTY_FIELD_BOUNDARY 32
1322 /* Every structure's size must be a multiple of this. */
1323 /* 8 is observed right on a DECstation and on riscos 4.02. */
1324 #define STRUCTURE_SIZE_BOUNDARY 8
1326 /* There is no point aligning anything to a rounder boundary than this. */
1327 #define BIGGEST_ALIGNMENT 64
1329 /* Set this nonzero if move instructions will actually fail to work
1330 when given unaligned data. */
1331 #define STRICT_ALIGNMENT 1
1333 /* Define this if you wish to imitate the way many other C compilers
1334 handle alignment of bitfields and the structures that contain
1337 The behavior is that the type written for a bitfield (`int',
1338 `short', or other integer type) imposes an alignment for the
1339 entire structure, as if the structure really did contain an
1340 ordinary field of that type. In addition, the bitfield is placed
1341 within the structure so that it would fit within such a field,
1342 not crossing a boundary for it.
1344 Thus, on most machines, a bitfield whose type is written as `int'
1345 would not cross a four-byte boundary, and would force four-byte
1346 alignment for the whole structure. (The alignment used may not
1347 be four bytes; it is controlled by the other alignment
1350 If the macro is defined, its definition should be a C expression;
1351 a nonzero value for the expression enables this behavior. */
1353 #define PCC_BITFIELD_TYPE_MATTERS 1
1355 /* If defined, a C expression to compute the alignment given to a
1356 constant that is being placed in memory. CONSTANT is the constant
1357 and ALIGN is the alignment that the object would ordinarily have.
1358 The value of this macro is used instead of that alignment to align
1361 If this macro is not defined, then ALIGN is used.
1363 The typical use of this macro is to increase alignment for string
1364 constants to be word aligned so that `strcpy' calls that copy
1365 constants can be done inline. */
1367 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1368 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1369 && (ALIGN) < BITS_PER_WORD \
1373 /* If defined, a C expression to compute the alignment for a static
1374 variable. TYPE is the data type, and ALIGN is the alignment that
1375 the object would ordinarily have. The value of this macro is used
1376 instead of that alignment to align the object.
1378 If this macro is not defined, then ALIGN is used.
1380 One use of this macro is to increase alignment of medium-size
1381 data to make it all fit in fewer cache lines. Another is to
1382 cause character arrays to be word-aligned so that `strcpy' calls
1383 that copy constants to character arrays can be done inline. */
1385 #undef DATA_ALIGNMENT
1386 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1387 ((((ALIGN) < BITS_PER_WORD) \
1388 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1389 || TREE_CODE (TYPE) == UNION_TYPE \
1390 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1392 /* Define this macro if an argument declared as `char' or `short' in a
1393 prototype should actually be passed as an `int'. In addition to
1394 avoiding errors in certain cases of mismatch, it also makes for
1395 better code on certain machines. */
1397 #define PROMOTE_PROTOTYPES
1399 /* Define if operations between registers always perform the operation
1400 on the full register even if a narrower mode is specified. */
1401 #define WORD_REGISTER_OPERATIONS
1403 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1404 will either zero-extend or sign-extend. The value of this macro should
1405 be the code that says which one of the two operations is implicitly
1406 done, NIL if none. */
1407 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1409 /* Define this macro if it is advisable to hold scalars in registers
1410 in a wider mode than that declared by the program. In such cases,
1411 the value is constrained to be within the bounds of the declared
1412 type, but kept valid in the wider mode. The signedness of the
1413 extension may differ from that of the type.
1415 We promote any value smaller than SImode up to SImode. We don't
1416 want to promote to DImode when in 64 bit mode, because that would
1417 prevent us from using the faster SImode multiply and divide
1420 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1421 if (GET_MODE_CLASS (MODE) == MODE_INT \
1422 && GET_MODE_SIZE (MODE) < 4) \
1425 /* Define this if function arguments should also be promoted using the above
1428 #define PROMOTE_FUNCTION_ARGS
1430 /* Likewise, if the function return value is promoted. */
1432 #define PROMOTE_FUNCTION_RETURN
1434 /* Standard register usage. */
1436 /* Number of actual hardware registers.
1437 The hardware registers are assigned numbers for the compiler
1438 from 0 to just below FIRST_PSEUDO_REGISTER.
1439 All registers that the compiler knows about must be given numbers,
1440 even those that are not normally considered general registers.
1442 On the Mips, we have 32 integer registers, 32 floating point
1443 registers, 8 condition code registers, and the special registers
1444 hi, lo, hilo, and rap. The 8 condition code registers are only
1445 used if mips_isa >= 4. The hilo register is only used in 64 bit
1446 mode. It represents a 64 bit value stored as two 32 bit values in
1447 the hi and lo registers; this is the result of the mult
1448 instruction. rap is a pointer to the stack where the return
1449 address reg ($31) was stored. This is needed for C++ exception
1452 #define FIRST_PSEUDO_REGISTER 76
1454 /* 1 for registers that have pervasive standard uses
1455 and are not available for the register allocator.
1457 On the MIPS, see conventions, page D-2 */
1459 #define FIXED_REGISTERS \
1461 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1469 /* 1 for registers not available across function calls.
1470 These must include the FIXED_REGISTERS and also any
1471 registers that can be used without being saved.
1472 The latter must include the registers where values are returned
1473 and the register where structure-value addresses are passed.
1474 Aside from that, you can include as many other registers as you like. */
1476 #define CALL_USED_REGISTERS \
1478 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1479 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1480 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1481 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1482 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1486 /* Internal macros to classify a register number as to whether it's a
1487 general purpose register, a floating point register, a
1488 multiply/divide register, or a status register. */
1490 #define GP_REG_FIRST 0
1491 #define GP_REG_LAST 31
1492 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1493 #define GP_DBX_FIRST 0
1495 #define FP_REG_FIRST 32
1496 #define FP_REG_LAST 63
1497 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1498 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1500 #define MD_REG_FIRST 64
1501 #define MD_REG_LAST 66
1502 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1504 #define ST_REG_FIRST 67
1505 #define ST_REG_LAST 74
1506 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1508 #define RAP_REG_NUM 75
1510 #define AT_REGNUM (GP_REG_FIRST + 1)
1511 #define HI_REGNUM (MD_REG_FIRST + 0)
1512 #define LO_REGNUM (MD_REG_FIRST + 1)
1513 #define HILO_REGNUM (MD_REG_FIRST + 2)
1515 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1516 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1517 should be used instead. */
1518 #define FPSW_REGNUM ST_REG_FIRST
1520 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1521 #define M16_REG_P(REGNO) \
1522 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1523 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1524 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1525 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1527 /* Return number of consecutive hard regs needed starting at reg REGNO
1528 to hold something of mode MODE.
1529 This is ordinarily the length in words of a value of mode MODE
1530 but can be less for certain modes in special long registers.
1532 On the MIPS, all general registers are one word long. Except on
1533 the R4000 with the FR bit set, the floating point uses register
1534 pairs, with the second register not being allocable. */
1536 #define HARD_REGNO_NREGS(REGNO, MODE) \
1537 (! FP_REG_P (REGNO) \
1538 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1539 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1541 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1542 MODE. In 32 bit mode, require that DImode and DFmode be in even
1543 registers. For DImode, this makes some of the insns easier to
1544 write, since you don't have to worry about a DImode value in
1545 registers 3 & 4, producing a result in 4 & 5.
1547 To make the code simpler HARD_REGNO_MODE_OK now just references an
1548 array built in override_options. Because machmodes.h is not yet
1549 included before this file is processed, the MODE bound can't be
1552 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1554 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1555 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1557 /* Value is 1 if it is a good idea to tie two pseudo registers
1558 when one has mode MODE1 and one has mode MODE2.
1559 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1560 for any hard reg, then this must be 0 for correct output. */
1561 #define MODES_TIEABLE_P(MODE1, MODE2) \
1562 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1563 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1564 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1565 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1567 /* MIPS pc is not overloaded on a register. */
1568 /* #define PC_REGNUM xx */
1570 /* Register to use for pushing function arguments. */
1571 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1573 /* Offset from the stack pointer to the first available location. Use
1574 the default value zero. */
1575 /* #define STACK_POINTER_OFFSET 0 */
1577 /* Base register for access to local variables of the function. We
1578 pretend that the frame pointer is $1, and then eliminate it to
1579 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1580 a fixed register, and will not be used for anything else. */
1581 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1583 /* $30 is not available on the mips16, so we use $17 as the frame
1585 #define HARD_FRAME_POINTER_REGNUM \
1586 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1588 /* Value should be nonzero if functions must have frame pointers.
1589 Zero means the frame pointer need not be set up (and parms
1590 may be accessed via the stack pointer) in functions that seem suitable.
1591 This is computed in `reload', in reload1.c. */
1592 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1594 /* Base register for access to arguments of the function. */
1595 #define ARG_POINTER_REGNUM GP_REG_FIRST
1597 /* Fake register that holds the address on the stack of the
1598 current function's return address. */
1599 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1601 /* Register in which static-chain is passed to a function. */
1602 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1604 /* If the structure value address is passed in a register, then
1605 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1606 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1608 /* If the structure value address is not passed in a register, define
1609 `STRUCT_VALUE' as an expression returning an RTX for the place
1610 where the address is passed. If it returns 0, the address is
1611 passed as an "invisible" first argument. */
1612 #define STRUCT_VALUE 0
1614 /* Mips registers used in prologue/epilogue code when the stack frame
1615 is larger than 32K bytes. These registers must come from the
1616 scratch register set, and not used for passing and returning
1617 arguments and any other information used in the calling sequence
1618 (such as pic). Must start at 12, since t0/t3 are parameter passing
1619 registers in the 64 bit ABI. */
1621 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1622 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1624 /* Define this macro if it is as good or better to call a constant
1625 function address than to call an address kept in a register. */
1626 #define NO_FUNCTION_CSE 1
1628 /* Define this macro if it is as good or better for a function to
1629 call itself with an explicit address than to call an address
1630 kept in a register. */
1631 #define NO_RECURSIVE_FUNCTION_CSE 1
1633 /* The register number of the register used to address a table of
1634 static data addresses in memory. In some cases this register is
1635 defined by a processor's "application binary interface" (ABI).
1636 When this macro is defined, RTL is generated for this register
1637 once, as with the stack pointer and frame pointer registers. If
1638 this macro is not defined, it is up to the machine-dependent
1639 files to allocate such a register (if necessary). */
1640 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1642 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1644 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1645 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1646 isn't always called for static inline functions. */
1647 #define INIT_EXPANDERS \
1649 embedded_pic_fnaddr_rtx = NULL; \
1650 mips16_gp_pseudo_rtx = NULL; \
1653 /* Define the classes of registers for register constraints in the
1654 machine description. Also define ranges of constants.
1656 One of the classes must always be named ALL_REGS and include all hard regs.
1657 If there is more than one class, another class must be named NO_REGS
1658 and contain no registers.
1660 The name GENERAL_REGS must be the name of a class (or an alias for
1661 another name such as ALL_REGS). This is the class of registers
1662 that is allowed by "g" or "r" in a register constraint.
1663 Also, registers outside this class are allocated only when
1664 instructions express preferences for them.
1666 The classes must be numbered in nondecreasing order; that is,
1667 a larger-numbered class must never be contained completely
1668 in a smaller-numbered class.
1670 For any two classes, it is very desirable that there be another
1671 class that represents their union. */
1675 NO_REGS, /* no registers in set */
1676 M16_NA_REGS, /* mips16 regs not used to pass args */
1677 M16_REGS, /* mips16 directly accessible registers */
1678 T_REG, /* mips16 T register ($24) */
1679 M16_T_REGS, /* mips16 registers plus T register */
1680 GR_REGS, /* integer registers */
1681 FP_REGS, /* floating point registers */
1682 HI_REG, /* hi register */
1683 LO_REG, /* lo register */
1684 HILO_REG, /* hilo register pair for 64 bit mode mult */
1685 MD_REGS, /* multiply/divide registers (hi/lo) */
1686 ST_REGS, /* status registers (fp status) */
1687 ALL_REGS, /* all registers */
1688 LIM_REG_CLASSES /* max value + 1 */
1691 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1693 #define GENERAL_REGS GR_REGS
1695 /* An initializer containing the names of the register classes as C
1696 string constants. These names are used in writing some of the
1699 #define REG_CLASS_NAMES \
1716 /* An initializer containing the contents of the register classes,
1717 as integers which are bit masks. The Nth integer specifies the
1718 contents of class N. The way the integer MASK is interpreted is
1719 that register R is in the class if `MASK & (1 << R)' is 1.
1721 When the machine has more than 32 registers, an integer does not
1722 suffice. Then the integers are replaced by sub-initializers,
1723 braced groupings containing several integers. Each
1724 sub-initializer must be suitable as an initializer for the type
1725 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1727 #define REG_CLASS_CONTENTS \
1729 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1730 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1731 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1732 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1733 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1734 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1735 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1736 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1737 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1738 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1739 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1740 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1741 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1745 /* A C expression whose value is a register class containing hard
1746 register REGNO. In general there is more that one such class;
1747 choose a class which is "minimal", meaning that no smaller class
1748 also contains the register. */
1750 extern enum reg_class mips_regno_to_class[];
1752 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1754 /* A macro whose definition is the name of the class to which a
1755 valid base register must belong. A base register is one used in
1756 an address which is the register value plus a displacement. */
1758 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1760 /* A macro whose definition is the name of the class to which a
1761 valid index register must belong. An index register is one used
1762 in an address where its value is either multiplied by a scale
1763 factor or added to another register (as well as added to a
1766 #define INDEX_REG_CLASS NO_REGS
1768 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1769 registers explicitly used in the rtl to be used as spill registers
1770 but prevents the compiler from extending the lifetime of these
1773 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1775 /* This macro is used later on in the file. */
1776 #define GR_REG_CLASS_P(CLASS) \
1777 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1778 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1780 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1781 is the default value (allocate the registers in numeric order). We
1782 define it just so that we can override it for the mips16 target in
1783 ORDER_REGS_FOR_LOCAL_ALLOC. */
1785 #define REG_ALLOC_ORDER \
1786 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1787 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1788 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1789 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1790 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1793 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1794 to be rearranged based on a particular function. On the mips16, we
1795 want to allocate $24 (T_REG) before other registers for
1796 instructions for which it is possible. */
1798 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1800 /* REGISTER AND CONSTANT CLASSES */
1802 /* Get reg_class from a letter such as appears in the machine
1805 DEFINED REGISTER CLASSES:
1807 'd' General (aka integer) registers
1808 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1809 'y' General registers (in both mips16 and non mips16 mode)
1810 'e' mips16 non argument registers (M16_NA_REGS)
1811 't' mips16 temporary register ($24)
1812 'f' Floating point registers
1815 'x' Multiply/divide registers
1817 'z' FP Status register
1818 'b' All registers */
1820 extern enum reg_class mips_char_to_class[];
1822 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1824 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1825 string can be used to stand for particular ranges of immediate
1826 operands. This macro defines what the ranges are. C is the
1827 letter, and VALUE is a constant value. Return 1 if VALUE is
1828 in the range specified by C. */
1832 `I' is used for the range of constants an arithmetic insn can
1833 actually contain (16 bits signed integers).
1835 `J' is used for the range which is just zero (ie, $r0).
1837 `K' is used for the range of constants a logical insn can actually
1838 contain (16 bit zero-extended integers).
1840 `L' is used for the range of constants that be loaded with lui
1841 (ie, the bottom 16 bits are zero).
1843 `M' is used for the range of constants that take two words to load
1844 (ie, not matched by `I', `K', and `L').
1846 `N' is used for negative 16 bit constants other than -65536.
1848 `O' is a 15 bit signed integer.
1850 `P' is used for positive 16 bit constants. */
1852 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1853 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1855 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1856 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1857 : (C) == 'J' ? ((VALUE) == 0) \
1858 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1859 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1860 && (((VALUE) & ~2147483647) == 0 \
1861 || ((VALUE) & ~2147483647) == ~2147483647)) \
1862 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1863 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1864 && (((VALUE) & 0x0000ffff) != 0 \
1865 || (((VALUE) & ~2147483647) != 0 \
1866 && ((VALUE) & ~2147483647) != ~2147483647))) \
1867 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1868 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1869 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1872 /* Similar, but for floating constants, and defining letters G and H.
1873 Here VALUE is the CONST_DOUBLE rtx itself. */
1877 'G' : Floating point 0 */
1879 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1881 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1883 /* Letters in the range `Q' through `U' may be defined in a
1884 machine-dependent fashion to stand for arbitrary operand types.
1885 The machine description macro `EXTRA_CONSTRAINT' is passed the
1886 operand as its first argument and the constraint letter as its
1889 `Q' is for mips16 GP relative constants
1890 `R' is for memory references which take 1 word for the instruction.
1891 `S' is for references to extern items which are PIC for OSF/rose.
1892 `T' is for memory addresses that can be used to load two words. */
1894 #define EXTRA_CONSTRAINT(OP,CODE) \
1895 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
1896 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
1897 && mips16_gp_offset_p (OP)) \
1898 : (GET_CODE (OP) != MEM) ? FALSE \
1899 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1900 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1901 && HALF_PIC_ADDRESS_P (OP)) \
1904 /* Given an rtx X being reloaded into a reg required to be
1905 in class CLASS, return the class of reg to actually use.
1906 In general this is just CLASS; but on some machines
1907 in some cases it is preferable to use a more restrictive class. */
1909 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1910 ((CLASS) != ALL_REGS \
1911 ? (! TARGET_MIPS16 \
1913 : ((CLASS) != GR_REGS \
1916 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1917 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1918 ? (TARGET_SOFT_FLOAT \
1919 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1921 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1922 || GET_MODE (X) == VOIDmode) \
1923 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1926 /* Certain machines have the property that some registers cannot be
1927 copied to some other registers without using memory. Define this
1928 macro on those machines to be a C expression that is non-zero if
1929 objects of mode MODE in registers of CLASS1 can only be copied to
1930 registers of class CLASS2 by storing a register of CLASS1 into
1931 memory and loading that memory location into a register of CLASS2.
1933 Do not define this macro if its value would always be zero. */
1935 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1936 ((!TARGET_DEBUG_H_MODE \
1937 && GET_MODE_CLASS (MODE) == MODE_INT \
1938 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1939 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1940 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1941 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1942 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1944 /* The HI and LO registers can only be reloaded via the general
1945 registers. Condition code registers can only be loaded to the
1946 general registers, and from the floating point registers. */
1948 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1949 mips_secondary_reload_class (CLASS, MODE, X, 1)
1950 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1951 mips_secondary_reload_class (CLASS, MODE, X, 0)
1953 /* Not declared above, with the other functions, because enum
1954 reg_class is not declared yet. */
1955 extern enum reg_class mips_secondary_reload_class ();
1957 /* Return the maximum number of consecutive registers
1958 needed to represent mode MODE in a register of class CLASS. */
1960 #define CLASS_UNITS(mode, size) \
1961 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1963 #define CLASS_MAX_NREGS(CLASS, MODE) \
1964 ((CLASS) == FP_REGS \
1966 ? CLASS_UNITS (MODE, 8) \
1967 : 2 * CLASS_UNITS (MODE, 8)) \
1968 : CLASS_UNITS (MODE, UNITS_PER_WORD))
1970 /* If defined, this is a C expression whose value should be
1971 nonzero if the insn INSN has the effect of mysteriously
1972 clobbering the contents of hard register number REGNO. By
1973 "mysterious" we mean that the insn's RTL expression doesn't
1974 describe such an effect.
1976 If this macro is not defined, it means that no insn clobbers
1977 registers mysteriously. This is the usual situation; all else
1978 being equal, it is best for the RTL expression to show all the
1981 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
1984 /* Stack layout; function entry, exit and calling. */
1986 /* Define this if pushing a word on the stack
1987 makes the stack pointer a smaller address. */
1988 #define STACK_GROWS_DOWNWARD
1990 /* Define this if the nominal address of the stack frame
1991 is at the high-address end of the local variables;
1992 that is, each additional local variable allocated
1993 goes at a more negative offset in the frame. */
1994 /* #define FRAME_GROWS_DOWNWARD */
1996 /* Offset within stack frame to start allocating local variables at.
1997 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1998 first local allocated. Otherwise, it is the offset to the BEGINNING
1999 of the first local allocated. */
2000 #define STARTING_FRAME_OFFSET \
2001 (current_function_outgoing_args_size \
2002 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2004 /* Offset from the stack pointer register to an item dynamically
2005 allocated on the stack, e.g., by `alloca'.
2007 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2008 length of the outgoing arguments. The default is correct for most
2009 machines. See `function.c' for details.
2011 The MIPS ABI states that functions which dynamically allocate the
2012 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2013 we are trying to create a second frame pointer to the function, so
2014 allocate some stack space to make it happy.
2016 However, the linker currently complains about linking any code that
2017 dynamically allocates stack space, and there seems to be a bug in
2018 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2021 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2022 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2023 ? 4*UNITS_PER_WORD \
2024 : current_function_outgoing_args_size)
2027 /* The return address for the current frame is in r31 is this is a leaf
2028 function. Otherwise, it is on the stack. It is at a variable offset
2029 from sp/fp/ap, so we define a fake hard register rap which is a
2030 poiner to the return address on the stack. This always gets eliminated
2031 during reload to be either the frame pointer or the stack pointer plus
2034 /* ??? This definition fails for leaf functions. There is currently no
2035 general solution for this problem. */
2037 /* ??? There appears to be no way to get the return address of any previous
2038 frame except by disassembling instructions in the prologue/epilogue.
2039 So currently we support only the current frame. */
2041 #define RETURN_ADDR_RTX(count, frame) \
2043 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2046 /* Structure to be filled in by compute_frame_size with register
2047 save masks, and offsets for the current function. */
2049 struct mips_frame_info
2051 long total_size; /* # bytes that the entire frame takes up */
2052 long var_size; /* # bytes that variables take up */
2053 long args_size; /* # bytes that outgoing arguments take up */
2054 long extra_size; /* # bytes of extra gunk */
2055 int gp_reg_size; /* # bytes needed to store gp regs */
2056 int fp_reg_size; /* # bytes needed to store fp regs */
2057 long mask; /* mask of saved gp registers */
2058 long fmask; /* mask of saved fp registers */
2059 long gp_save_offset; /* offset from vfp to store gp registers */
2060 long fp_save_offset; /* offset from vfp to store fp registers */
2061 long gp_sp_offset; /* offset from new sp to store gp registers */
2062 long fp_sp_offset; /* offset from new sp to store fp registers */
2063 int initialized; /* != 0 if frame size already calculated */
2064 int num_gp; /* number of gp registers saved */
2065 int num_fp; /* number of fp registers saved */
2066 long insns_len; /* length of insns; mips16 only */
2069 extern struct mips_frame_info current_frame_info;
2071 /* If defined, this macro specifies a table of register pairs used to
2072 eliminate unneeded registers that point into the stack frame. If
2073 it is not defined, the only elimination attempted by the compiler
2074 is to replace references to the frame pointer with references to
2077 The definition of this macro is a list of structure
2078 initializations, each of which specifies an original and
2079 replacement register.
2081 On some machines, the position of the argument pointer is not
2082 known until the compilation is completed. In such a case, a
2083 separate hard register must be used for the argument pointer.
2084 This register can be eliminated by replacing it with either the
2085 frame pointer or the argument pointer, depending on whether or not
2086 the frame pointer has been eliminated.
2088 In this case, you might specify:
2089 #define ELIMINABLE_REGS \
2090 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2091 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2092 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2094 Note that the elimination of the argument pointer with the stack
2095 pointer is specified first since that is the preferred elimination.
2097 The eliminations to $17 are only used on the mips16. See the
2098 definition of HARD_FRAME_POINTER_REGNUM. */
2100 #define ELIMINABLE_REGS \
2101 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2102 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2103 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2104 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2105 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2106 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2107 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2108 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2109 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2111 /* A C expression that returns non-zero if the compiler is allowed to
2112 try to replace register number FROM-REG with register number
2113 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2114 defined, and will usually be the constant 1, since most of the
2115 cases preventing register elimination are things that the compiler
2116 already knows about.
2118 We can always eliminate to the frame pointer. We can eliminate to
2119 the stack pointer unless a frame pointer is needed. In mips16
2120 mode, we need a frame pointer for a large frame; otherwise, reload
2121 may be unable to compute the address of a local variable, since
2122 there is no way to add a large constant to the stack pointer
2123 without using a temporary register. */
2125 #define CAN_ELIMINATE(FROM, TO) \
2126 ((TO) == HARD_FRAME_POINTER_REGNUM \
2127 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2128 && (! TARGET_MIPS16 \
2129 || compute_frame_size (get_frame_size ()) < 32768)))
2131 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2132 specifies the initial difference between the specified pair of
2133 registers. This macro must be defined if `ELIMINABLE_REGS' is
2136 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2137 { compute_frame_size (get_frame_size ()); \
2138 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2139 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2140 (OFFSET) = - current_function_outgoing_args_size; \
2141 else if ((FROM) == FRAME_POINTER_REGNUM) \
2143 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2144 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2145 (OFFSET) = (current_frame_info.total_size \
2146 - current_function_outgoing_args_size \
2147 - ((mips_abi != ABI_32 && mips_abi != ABI_EABI) \
2148 ? current_function_pretend_args_size \
2150 else if ((FROM) == ARG_POINTER_REGNUM) \
2151 (OFFSET) = (current_frame_info.total_size \
2152 - ((mips_abi != ABI_32 && mips_abi != ABI_EABI) \
2153 ? current_function_pretend_args_size \
2155 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2156 (OFFSET) = current_frame_info.gp_sp_offset; \
2159 /* If we generate an insn to push BYTES bytes,
2160 this says how many the stack pointer really advances by.
2161 On the vax, sp@- in a byte insn really pushes a word. */
2163 /* #define PUSH_ROUNDING(BYTES) 0 */
2165 /* If defined, the maximum amount of space required for outgoing
2166 arguments will be computed and placed into the variable
2167 `current_function_outgoing_args_size'. No space will be pushed
2168 onto the stack for each call; instead, the function prologue
2169 should increase the stack frame size by this amount.
2171 It is not proper to define both `PUSH_ROUNDING' and
2172 `ACCUMULATE_OUTGOING_ARGS'. */
2173 #define ACCUMULATE_OUTGOING_ARGS
2175 /* Offset from the argument pointer register to the first argument's
2176 address. On some machines it may depend on the data type of the
2179 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2180 the first argument's address.
2182 On the MIPS, we must skip the first argument position if we are
2183 returning a structure or a union, to account for its address being
2184 passed in $4. However, at the current time, this produces a compiler
2185 that can't bootstrap, so comment it out for now. */
2188 #define FIRST_PARM_OFFSET(FNDECL) \
2190 && TREE_TYPE (FNDECL) != 0 \
2191 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2192 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2193 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2197 #define FIRST_PARM_OFFSET(FNDECL) 0
2200 /* When a parameter is passed in a register, stack space is still
2201 allocated for it. For the MIPS, stack space must be allocated, cf
2202 Asm Lang Prog Guide page 7-8.
2204 BEWARE that some space is also allocated for non existing arguments
2205 in register. In case an argument list is of form GF used registers
2206 are a0 (a2,a3), but we should push over a1... */
2208 #define REG_PARM_STACK_SPACE(FNDECL) \
2209 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2211 /* Define this if it is the responsibility of the caller to
2212 allocate the area reserved for arguments passed in registers.
2213 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2214 of this macro is to determine whether the space is included in
2215 `current_function_outgoing_args_size'. */
2216 #define OUTGOING_REG_PARM_STACK_SPACE
2218 /* Align stack frames on 64 bits (Double Word ). */
2219 #define STACK_BOUNDARY 64
2221 /* Make sure 4 words are always allocated on the stack. */
2223 #ifndef STACK_ARGS_ADJUST
2224 #define STACK_ARGS_ADJUST(SIZE) \
2226 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2227 SIZE.constant = 4 * UNITS_PER_WORD; \
2232 /* A C expression that should indicate the number of bytes of its
2233 own arguments that a function function pops on returning, or 0
2234 if the function pops no arguments and the caller must therefore
2235 pop them all after the function returns.
2237 FUNDECL is the declaration node of the function (as a tree).
2239 FUNTYPE is a C variable whose value is a tree node that
2240 describes the function in question. Normally it is a node of
2241 type `FUNCTION_TYPE' that describes the data type of the function.
2242 From this it is possible to obtain the data types of the value
2243 and arguments (if known).
2245 When a call to a library function is being considered, FUNTYPE
2246 will contain an identifier node for the library function. Thus,
2247 if you need to distinguish among various library functions, you
2248 can do so by their names. Note that "library function" in this
2249 context means a function used to perform arithmetic, whose name
2250 is known specially in the compiler and was not mentioned in the
2251 C code being compiled.
2253 STACK-SIZE is the number of bytes of arguments passed on the
2254 stack. If a variable number of bytes is passed, it is zero, and
2255 argument popping will always be the responsibility of the
2256 calling function. */
2258 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2261 /* Symbolic macros for the registers used to return integer and floating
2264 #define GP_RETURN (GP_REG_FIRST + 2)
2265 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2267 /* Symbolic macros for the first/last argument registers. */
2269 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2270 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2271 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2272 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2274 #define MAX_ARGS_IN_REGISTERS 4
2276 /* Define how to find the value returned by a library function
2277 assuming the value has mode MODE. Because we define
2278 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2279 PROMOTE_MODE does. */
2281 #define LIBCALL_VALUE(MODE) \
2283 ((GET_MODE_CLASS (MODE) != MODE_INT \
2284 || GET_MODE_SIZE (MODE) >= 4) \
2287 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2288 && (! TARGET_SINGLE_FLOAT \
2289 || GET_MODE_SIZE (MODE) <= 4)) \
2293 /* Define how to find the value returned by a function.
2294 VALTYPE is the data type of the value (as a tree).
2295 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2296 otherwise, FUNC is 0. */
2298 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2301 /* 1 if N is a possible register number for a function value.
2302 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2303 Currently, R2 and F0 are only implemented here (C has no complex type) */
2305 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2307 /* 1 if N is a possible register number for function argument passing.
2308 We have no FP argument registers when soft-float. When FP registers
2309 are 32 bits, we can't directly reference the odd numbered ones. */
2311 #define FUNCTION_ARG_REGNO_P(N) \
2312 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2313 || (! TARGET_SOFT_FLOAT \
2314 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2315 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2318 /* A C expression which can inhibit the returning of certain function
2319 values in registers, based on the type of value. A nonzero value says
2320 to return the function value in memory, just as large structures are
2321 always returned. Here TYPE will be a C expression of type
2322 `tree', representing the data type of the value.
2324 Note that values of mode `BLKmode' must be explicitly
2325 handled by this macro. Also, the option `-fpcc-struct-return'
2326 takes effect regardless of this macro. On most systems, it is
2327 possible to leave the macro undefined; this causes a default
2328 definition to be used, whose value is the constant 1 for BLKmode
2329 values, and 0 otherwise.
2331 GCC normally converts 1 byte structures into chars, 2 byte
2332 structs into shorts, and 4 byte structs into ints, and returns
2333 them this way. Defining the following macro overrides this,
2334 to give us MIPS cc compatibility. */
2336 #define RETURN_IN_MEMORY(TYPE) \
2337 (TYPE_MODE (TYPE) == BLKmode)
2339 /* A code distinguishing the floating point format of the target
2340 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2341 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2343 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2346 /* Define a data type for recording info about an argument list
2347 during the scan of that argument list. This data type should
2348 hold all necessary information about the function itself
2349 and about the args processed so far, enough to enable macros
2350 such as FUNCTION_ARG to determine where the next arg should go.
2352 On the mips16, we need to keep track of which floating point
2353 arguments were passed in general registers, but would have been
2354 passed in the FP regs if this were a 32 bit function, so that we
2355 can move them to the FP regs if we wind up calling a 32 bit
2356 function. We record this information in fp_code, encoded in base
2357 four. A zero digit means no floating point argument, a one digit
2358 means an SFmode argument, and a two digit means a DFmode argument,
2359 and a three digit is not used. The low order digit is the first
2360 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2361 an SFmode argument. ??? A more sophisticated approach will be
2362 needed if MIPS_ABI != ABI_32. */
2364 typedef struct mips_args {
2365 int gp_reg_found; /* whether a gp register was found yet */
2366 int arg_number; /* argument number */
2367 int arg_words; /* # total words the arguments take */
2368 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2369 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2370 int fp_code; /* Mode of FP arguments (mips16) */
2371 int num_adjusts; /* number of adjustments made */
2372 /* Adjustments made to args pass in regs. */
2373 /* ??? The size is doubled to work around a
2374 bug in the code that sets the adjustments
2376 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2379 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2380 for a call to a function whose data type is FNTYPE.
2381 For a library call, FNTYPE is 0.
2385 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2386 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2388 /* Update the data in CUM to advance over an argument
2389 of mode MODE and data type TYPE.
2390 (TYPE is null for libcalls where that information may not be available.) */
2392 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2393 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2395 /* Determine where to put an argument to a function.
2396 Value is zero to push the argument on the stack,
2397 or a hard register in which to store the argument.
2399 MODE is the argument's machine mode.
2400 TYPE is the data type of the argument (as a tree).
2401 This is null for libcalls where that information may
2403 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2404 the preceding args and about the function being called.
2405 NAMED is nonzero if this argument is a named parameter
2406 (otherwise it is an extra parameter matching an ellipsis). */
2408 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2409 function_arg( &CUM, MODE, TYPE, NAMED)
2411 /* For an arg passed partly in registers and partly in memory,
2412 this is the number of registers used.
2413 For args passed entirely in registers or entirely in memory, zero. */
2415 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2416 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2418 /* If defined, a C expression that gives the alignment boundary, in
2419 bits, of an argument with the specified mode and type. If it is
2420 not defined, `PARM_BOUNDARY' is used for all arguments. */
2422 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2424 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2426 : TYPE_ALIGN(TYPE)) \
2427 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2429 : GET_MODE_ALIGNMENT(MODE)))
2432 /* This macro generates the assembly code for function entry.
2433 FILE is a stdio stream to output the code to.
2434 SIZE is an int: how many units of temporary storage to allocate.
2435 Refer to the array `regs_ever_live' to determine which registers
2436 to save; `regs_ever_live[I]' is nonzero if register number I
2437 is ever used in the function. This macro is responsible for
2438 knowing which registers should not be saved even if used. */
2440 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2442 /* This macro generates the assembly code for function exit,
2443 on machines that need it. If FUNCTION_EPILOGUE is not defined
2444 then individual return instructions are generated for each
2445 return statement. Args are same as for FUNCTION_PROLOGUE. */
2447 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2449 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2451 #define MUST_SAVE_REGISTER(regno) \
2452 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2453 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2454 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2456 /* ALIGN FRAMES on double word boundaries */
2458 #define MIPS_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
2461 /* Output assembler code to FILE to increment profiler label # LABELNO
2462 for profiling a function entry. */
2464 #define FUNCTION_PROFILER(FILE, LABELNO) \
2466 if (TARGET_MIPS16) \
2467 sorry ("mips16 function profiling"); \
2468 fprintf (FILE, "\t.set\tnoreorder\n"); \
2469 fprintf (FILE, "\t.set\tnoat\n"); \
2470 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2471 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2472 fprintf (FILE, "\tjal\t_mcount\n"); \
2474 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2475 TARGET_64BIT ? "dsubu" : "subu", \
2476 reg_names[STACK_POINTER_REGNUM], \
2477 reg_names[STACK_POINTER_REGNUM], \
2478 TARGET_LONG64 ? 16 : 8); \
2479 fprintf (FILE, "\t.set\treorder\n"); \
2480 fprintf (FILE, "\t.set\tat\n"); \
2483 /* Define this macro if the code for function profiling should come
2484 before the function prologue. Normally, the profiling code comes
2487 /* #define PROFILE_BEFORE_PROLOGUE */
2489 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2490 the stack pointer does not matter. The value is tested only in
2491 functions that have frame pointers.
2492 No definition is equivalent to always zero. */
2494 #define EXIT_IGNORE_STACK 1
2497 /* A C statement to output, on the stream FILE, assembler code for a
2498 block of data that contains the constant parts of a trampoline.
2499 This code should not include a label--the label is taken care of
2502 #define TRAMPOLINE_TEMPLATE(STREAM) \
2504 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2505 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2506 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2507 if (TARGET_LONG64) \
2509 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2510 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2514 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2515 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2517 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2518 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2519 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2520 if (TARGET_LONG64) \
2522 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2523 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2527 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2528 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2532 /* A C expression for the size in bytes of the trampoline, as an
2535 #define TRAMPOLINE_SIZE (32 + (TARGET_LONG64 ? 16 : 8))
2537 /* Alignment required for trampolines, in bits. */
2539 #define TRAMPOLINE_ALIGNMENT (TARGET_LONG64 ? 64 : 32)
2541 /* A C statement to initialize the variable parts of a trampoline.
2542 ADDR is an RTX for the address of the trampoline; FNADDR is an
2543 RTX for the address of the nested function; STATIC_CHAIN is an
2544 RTX for the static chain value that should be passed to the
2545 function when it is called. */
2547 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2550 if (TARGET_LONG64) \
2552 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2553 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2557 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2558 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2561 /* Flush both caches. We need to flush the data cache in case \
2562 the system has a write-back cache. */ \
2563 /* ??? Should check the return value for errors. */ \
2564 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "_flush_cache"), \
2565 0, VOIDmode, 3, addr, Pmode, \
2566 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2567 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2570 /* Addressing modes, and classification of registers for them. */
2572 /* #define HAVE_POST_INCREMENT */
2573 /* #define HAVE_POST_DECREMENT */
2575 /* #define HAVE_PRE_DECREMENT */
2576 /* #define HAVE_PRE_INCREMENT */
2578 /* These assume that REGNO is a hard or pseudo reg number.
2579 They give nonzero only if REGNO is a hard reg of the suitable class
2580 or a pseudo reg currently allocated to a suitable hard reg.
2581 These definitions are NOT overridden anywhere. */
2583 #define BASE_REG_P(regno, mode) \
2585 ? (M16_REG_P (regno) \
2586 || (regno) == FRAME_POINTER_REGNUM \
2587 || (regno) == ARG_POINTER_REGNUM \
2588 || ((regno) == STACK_POINTER_REGNUM \
2589 && (GET_MODE_SIZE (mode) == 4 \
2590 || GET_MODE_SIZE (mode) == 8))) \
2593 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2594 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2597 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2598 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2600 #define REGNO_OK_FOR_INDEX_P(regno) 0
2601 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2602 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2604 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2605 and check its validity for a certain class.
2606 We have two alternate definitions for each of them.
2607 The usual definition accepts all pseudo regs; the other rejects them all.
2608 The symbol REG_OK_STRICT causes the latter definition to be used.
2610 Most source files want to accept pseudo regs in the hope that
2611 they will get allocated to the class that the insn wants them to be in.
2612 Some source files that are used after register allocation
2613 need to be strict. */
2615 #ifndef REG_OK_STRICT
2617 #define REG_OK_STRICT_P 0
2618 #define REG_OK_FOR_INDEX_P(X) 0
2619 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2620 GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
2624 #define REG_OK_STRICT_P 1
2625 #define REG_OK_FOR_INDEX_P(X) 0
2626 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2627 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
2632 /* Maximum number of registers that can appear in a valid memory address. */
2634 #define MAX_REGS_PER_ADDRESS 1
2636 /* A C compound statement with a conditional `goto LABEL;' executed
2637 if X (an RTX) is a legitimate memory address on the target
2638 machine for a memory operand of mode MODE.
2640 It usually pays to define several simpler macros to serve as
2641 subroutines for this one. Otherwise it may be too complicated
2644 This macro must exist in two variants: a strict variant and a
2645 non-strict one. The strict variant is used in the reload pass.
2646 It must be defined so that any pseudo-register that has not been
2647 allocated a hard register is considered a memory reference. In
2648 contexts where some kind of register is required, a
2649 pseudo-register with no hard register must be rejected.
2651 The non-strict variant is used in other passes. It must be
2652 defined to accept all pseudo-registers in every context where
2653 some kind of register is required.
2655 Compiler source files that want to use the strict variant of
2656 this macro define the macro `REG_OK_STRICT'. You should use an
2657 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2658 in that case and the non-strict variant otherwise.
2660 Typically among the subroutines used to define
2661 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2662 acceptable registers for various purposes (one for base
2663 registers, one for index registers, and so on). Then only these
2664 subroutine macros need have two variants; the higher levels of
2665 macros may be the same whether strict or not.
2667 Normally, constant addresses which are the sum of a `symbol_ref'
2668 and an integer are stored inside a `const' RTX to mark them as
2669 constant. Therefore, there is no need to recognize such sums
2670 specifically as legitimate addresses. Normally you would simply
2671 recognize any `const' as legitimate.
2673 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2674 constant sums that are not marked with `const'. It assumes
2675 that a naked `plus' indicates indexing. If so, then you *must*
2676 reject such naked constant sums as illegitimate addresses, so
2677 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2679 On some machines, whether a symbolic address is legitimate
2680 depends on the section that the address refers to. On these
2681 machines, define the macro `ENCODE_SECTION_INFO' to store the
2682 information into the `symbol_ref', and then check for it here.
2683 When you see a `const', you will have to look inside it to find
2684 the `symbol_ref' in order to determine the section. */
2687 #define GO_PRINTF(x) trace(x)
2688 #define GO_PRINTF2(x,y) trace(x,y)
2689 #define GO_DEBUG_RTX(x) debug_rtx(x)
2692 #define GO_PRINTF(x)
2693 #define GO_PRINTF2(x,y)
2694 #define GO_DEBUG_RTX(x)
2697 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2699 register rtx xinsn = (X); \
2701 if (TARGET_DEBUG_B_MODE) \
2703 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2704 (REG_OK_STRICT_P) ? "" : "not "); \
2705 GO_DEBUG_RTX (xinsn); \
2708 /* The mips16 can only use the stack pointer as a base register when \
2709 loading SImode or DImode values. */ \
2710 if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \
2713 if (CONSTANT_ADDRESS_P (xinsn) \
2714 && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \
2715 && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \
2718 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2720 register rtx xlow0 = XEXP (xinsn, 0); \
2721 register rtx xlow1 = XEXP (xinsn, 1); \
2723 if (GET_CODE (xlow0) == REG \
2724 && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \
2725 && mips_check_split (xlow1, MODE)) \
2729 if (GET_CODE (xinsn) == PLUS) \
2731 register rtx xplus0 = XEXP (xinsn, 0); \
2732 register rtx xplus1 = XEXP (xinsn, 1); \
2733 register enum rtx_code code0 = GET_CODE (xplus0); \
2734 register enum rtx_code code1 = GET_CODE (xplus1); \
2736 /* The mips16 can only use the stack pointer as a base register \
2737 when loading SImode or DImode values. */ \
2738 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \
2740 if (code1 == CONST_INT \
2741 && INTVAL (xplus1) >= -32768 \
2742 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2745 /* On the mips16, we represent GP relative offsets in RTL. \
2746 These are 16 bit signed values, and can serve as register \
2749 && mips16_gp_offset_p (xplus1)) \
2752 /* For some code sequences, you actually get better code by \
2753 pretending that the MIPS supports an address mode of a \
2754 constant address + a register, even though the real \
2755 machine doesn't support it. This is because the \
2756 assembler can use $r1 to load just the high 16 bits, add \
2757 in the register, and fold the low 16 bits into the memory \
2758 reference, whereas the compiler generates a 4 instruction \
2759 sequence. On the other hand, CSE is not as effective. \
2760 It would be a win to generate the lui directly, but the \
2761 MIPS assembler does not have syntax to generate the \
2762 appropriate relocation. */ \
2764 /* Also accept CONST_INT addresses here, so no else. */ \
2765 /* Reject combining an embedded PIC text segment reference \
2766 with a register. That requires an additional \
2768 /* ??? Reject combining an address with a register for the MIPS \
2769 64 bit ABI, because the SGI assembler can not handle this. */ \
2770 if (!TARGET_DEBUG_A_MODE \
2771 && (mips_abi == ABI_32 || mips_abi == ABI_EABI) \
2772 && CONSTANT_ADDRESS_P (xplus1) \
2773 && ! mips_split_addresses \
2774 && (!TARGET_EMBEDDED_PIC \
2776 || GET_CODE (XEXP (xplus1, 0)) != MINUS) \
2777 && !TARGET_MIPS16) \
2782 if (TARGET_DEBUG_B_MODE) \
2783 GO_PRINTF ("Not a legitimate address\n"); \
2787 /* A C expression that is 1 if the RTX X is a constant which is a
2788 valid address. This is defined to be the same as `CONSTANT_P (X)',
2789 but rejecting CONST_DOUBLE. */
2790 /* When pic, we must reject addresses of the form symbol+large int.
2791 This is because an instruction `sw $4,s+70000' needs to be converted
2792 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2793 assembler would use $at as a temp to load in the large offset. In this
2794 case $at is already in use. We convert such problem addresses to
2795 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2796 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2797 #define CONSTANT_ADDRESS_P(X) \
2798 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2799 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2800 || (GET_CODE (X) == CONST \
2801 && ! (flag_pic && pic_address_needs_scratch (X)) \
2802 && (mips_abi == ABI_32 || mips_abi == ABI_EABI))) \
2803 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2805 /* Define this, so that when PIC, reload won't try to reload invalid
2806 addresses which require two reload registers. */
2808 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2810 /* Nonzero if the constant value X is a legitimate general operand.
2811 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2813 At present, GAS doesn't understand li.[sd], so don't allow it
2814 to be generated at present. Also, the MIPS assembler does not
2815 grok li.d Infinity. */
2817 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2818 #define LEGITIMATE_CONSTANT_P(X) \
2819 ((GET_CODE (X) != CONST_DOUBLE \
2820 || mips_const_double_ok (X, GET_MODE (X))) \
2821 && ! (GET_CODE (X) == CONST \
2822 && mips_abi != ABI_32 && mips_abi != ABI_EABI) \
2823 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2825 /* A C compound statement that attempts to replace X with a valid
2826 memory address for an operand of mode MODE. WIN will be a C
2827 statement label elsewhere in the code; the macro definition may
2830 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2832 to avoid further processing if the address has become legitimate.
2834 X will always be the result of a call to `break_out_memory_refs',
2835 and OLDX will be the operand that was given to that function to
2838 The code generated by this macro should not alter the
2839 substructure of X. If it transforms X into a more legitimate
2840 form, it should assign X (which will always be a C variable) a
2843 It is not necessary for this macro to come up with a legitimate
2844 address. The compiler has standard ways of doing so in all
2845 cases. In fact, it is safe for this macro to do nothing. But
2846 often a machine-dependent strategy can generate better code.
2848 For the MIPS, transform:
2850 memory(X + <large int>)
2854 Y = <large int> & ~0x7fff;
2856 memory (Z + (<large int> & 0x7fff));
2858 This is for CSE to find several similar references, and only use one Z.
2860 When PIC, convert addresses of the form memory (symbol+large int) to
2861 memory (reg+large int). */
2864 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2866 register rtx xinsn = (X); \
2868 if (TARGET_DEBUG_B_MODE) \
2870 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2871 GO_DEBUG_RTX (xinsn); \
2874 if (mips_split_addresses && mips_check_split (X, MODE)) \
2876 /* ??? Is this ever executed? */ \
2877 X = gen_rtx (LO_SUM, Pmode, \
2878 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2882 if (GET_CODE (xinsn) == CONST \
2883 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2884 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2885 || (mips_abi != ABI_32 && mips_abi != ABI_EABI))) \
2887 rtx ptr_reg = gen_reg_rtx (Pmode); \
2888 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2890 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2892 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2893 if (SMALL_INT (constant)) \
2895 /* Otherwise we fall through so the code below will fix the \
2900 if (GET_CODE (xinsn) == PLUS) \
2902 register rtx xplus0 = XEXP (xinsn, 0); \
2903 register rtx xplus1 = XEXP (xinsn, 1); \
2904 register enum rtx_code code0 = GET_CODE (xplus0); \
2905 register enum rtx_code code1 = GET_CODE (xplus1); \
2907 if (code0 != REG && code1 == REG) \
2909 xplus0 = XEXP (xinsn, 1); \
2910 xplus1 = XEXP (xinsn, 0); \
2911 code0 = GET_CODE (xplus0); \
2912 code1 = GET_CODE (xplus1); \
2915 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
2916 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2918 rtx int_reg = gen_reg_rtx (Pmode); \
2919 rtx ptr_reg = gen_reg_rtx (Pmode); \
2921 emit_move_insn (int_reg, \
2922 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2924 emit_insn (gen_rtx (SET, VOIDmode, \
2926 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
2928 X = gen_rtx (PLUS, Pmode, ptr_reg, \
2929 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
2934 if (TARGET_DEBUG_B_MODE) \
2935 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
2939 /* A C statement or compound statement with a conditional `goto
2940 LABEL;' executed if memory address X (an RTX) can have different
2941 meanings depending on the machine mode of the memory reference it
2944 Autoincrement and autodecrement addresses typically have
2945 mode-dependent effects because the amount of the increment or
2946 decrement is the size of the operand being addressed. Some
2947 machines have other mode-dependent addresses. Many RISC machines
2948 have no mode-dependent addresses.
2950 You may assume that ADDR is a valid address for the machine. */
2952 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2955 /* Define this macro if references to a symbol must be treated
2956 differently depending on something about the variable or
2957 function named by the symbol (such as what section it is in).
2959 The macro definition, if any, is executed immediately after the
2960 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
2961 The value of the rtl will be a `mem' whose address is a
2964 The usual thing for this macro to do is to a flag in the
2965 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
2966 name string in the `symbol_ref' (if one bit is not enough
2969 The best way to modify the name string is by adding text to the
2970 beginning, with suitable punctuation to prevent any ambiguity.
2971 Allocate the new name in `saveable_obstack'. You will have to
2972 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
2973 and output the name accordingly.
2975 You can also check the information stored in the `symbol_ref' in
2976 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
2977 `PRINT_OPERAND_ADDRESS'.
2979 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
2982 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
2983 symbols which are not in the .text section.
2985 When generating mips16 code, SYMBOL_REF_FLAG is set for string
2986 constants which are put in the .text section. We also record the
2987 total length of all such strings; this total is used to decide
2988 whether we need to split the constant table, and need not be
2989 precisely correct. */
2991 #define ENCODE_SECTION_INFO(DECL) \
2994 if (TARGET_MIPS16) \
2996 if (TREE_CODE (DECL) == STRING_CST \
2997 && ! flag_writable_strings) \
2999 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3000 mips_string_length += TREE_STRING_LENGTH (DECL); \
3003 if (TARGET_EMBEDDED_PIC) \
3005 if (TREE_CODE (DECL) == VAR_DECL) \
3006 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3007 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3008 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3009 else if (TREE_CODE (DECL) == STRING_CST \
3010 && ! flag_writable_strings) \
3011 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3013 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3016 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
3018 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3020 if (size > 0 && size <= mips_section_threshold) \
3021 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3024 else if (HALF_PIC_P ()) \
3025 HALF_PIC_ENCODE (DECL); \
3029 /* The mips16 wants the constant pool to be after the function,
3030 because the PC relative load instructions use unsigned offsets. */
3032 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3034 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3035 mips_string_length = 0;
3038 /* In mips16 mode, put most string constants after the function. */
3039 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3040 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3043 /* Specify the machine mode that this machine uses
3044 for the index in the tablejump instruction.
3045 ??? Using HImode in mips16 mode can cause overflow. However, the
3046 overflow is no more likely than the overflow in a branch
3047 instruction. Large functions can currently break in both ways. */
3048 #define CASE_VECTOR_MODE \
3049 (TARGET_MIPS16 ? HImode : TARGET_LONG64 ? DImode : SImode)
3051 /* Define as C expression which evaluates to nonzero if the tablejump
3052 instruction expects the table to contain offsets from the address of the
3054 Do not define this if the table should contain absolute addresses. */
3055 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3057 /* Specify the tree operation to be used to convert reals to integers. */
3058 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3060 /* This is the kind of divide that is easiest to do in the general case. */
3061 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3063 /* Define this as 1 if `char' should by default be signed; else as 0. */
3064 #ifndef DEFAULT_SIGNED_CHAR
3065 #define DEFAULT_SIGNED_CHAR 1
3068 /* Max number of bytes we can move from memory to memory
3069 in one reasonably fast instruction. */
3070 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3071 #define MAX_MOVE_MAX 8
3073 /* Define this macro as a C expression which is nonzero if
3074 accessing less than a word of memory (i.e. a `char' or a
3075 `short') is no faster than accessing a word of memory, i.e., if
3076 such access require more than one instruction or if there is no
3077 difference in cost between byte and (aligned) word loads.
3079 On RISC machines, it tends to generate better code to define
3080 this as 1, since it avoids making a QI or HI mode register. */
3081 #define SLOW_BYTE_ACCESS 1
3083 /* We assume that the store-condition-codes instructions store 0 for false
3084 and some other value for true. This is the value stored for true. */
3086 #define STORE_FLAG_VALUE 1
3088 /* Define this if zero-extension is slow (more than one real instruction). */
3089 #define SLOW_ZERO_EXTEND
3091 /* Define this to be nonzero if shift instructions ignore all but the low-order
3093 #define SHIFT_COUNT_TRUNCATED 1
3095 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3096 is done just by pretending it is already truncated. */
3097 /* In 64 bit mode, 32 bit instructions require that register values be properly
3098 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3099 converts a value >32 bits to a value <32 bits. */
3100 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3101 Something needs to be done about this. Perhaps not use any 32 bit
3102 instructions? Perhaps use PROMOTE_MODE? */
3103 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3104 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3106 /* Specify the machine mode that pointers have.
3107 After generation of rtl, the compiler makes no further distinction
3108 between pointers and any other objects of this machine mode. */
3110 #define Pmode (TARGET_LONG64 ? DImode : SImode)
3112 /* A function address in a call instruction
3113 is a word address (for indexing purposes)
3114 so give the MEM rtx a words's mode. */
3116 #define FUNCTION_MODE (TARGET_LONG64 ? DImode : SImode)
3118 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3119 memset, instead of the BSD functions bcopy and bzero. */
3121 #if defined(MIPS_SYSV) || defined(OSF_OS)
3122 #define TARGET_MEM_FUNCTIONS
3126 /* A part of a C `switch' statement that describes the relative
3127 costs of constant RTL expressions. It must contain `case'
3128 labels for expression codes `const_int', `const', `symbol_ref',
3129 `label_ref' and `const_double'. Each case must ultimately reach
3130 a `return' statement to return the relative cost of the use of
3131 that kind of constant value in an expression. The cost may
3132 depend on the precise value of the constant, which is available
3133 for examination in X.
3135 CODE is the expression code--redundant, since it can be obtained
3136 with `GET_CODE (X)'. */
3138 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3140 if (! TARGET_MIPS16) \
3142 /* Always return 0, since we don't have different sized \
3143 instructions, hence different costs according to Richard \
3147 if ((OUTER_CODE) == SET) \
3149 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3151 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3152 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3153 return COSTS_N_INSNS (1); \
3155 return COSTS_N_INSNS (2); \
3157 /* A PLUS could be an address. We don't want to force an address \
3158 to use a register, so accept any signed 16 bit value without \
3160 if ((OUTER_CODE) == PLUS \
3161 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3163 /* A number between 1 and 8 inclusive is efficient for a shift. \
3164 Otherwise, we will need an extended instruction. */ \
3165 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3166 || (OUTER_CODE) == LSHIFTRT) \
3168 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3170 return COSTS_N_INSNS (1); \
3172 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3173 if ((OUTER_CODE) == XOR \
3174 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3176 /* We may be able to use slt or sltu for a comparison with a \
3177 signed 16 bit value. (The boundary conditions aren't quite \
3178 right, but this is just a heuristic anyhow.) */ \
3179 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3180 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3181 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3182 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3183 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3185 /* Equality comparisons with 0 are cheap. */ \
3186 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3187 && INTVAL (X) == 0) \
3190 /* Otherwise, work out the cost to load the value into a \
3192 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3193 return COSTS_N_INSNS (1); \
3194 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3195 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3196 return COSTS_N_INSNS (2); \
3198 return COSTS_N_INSNS (3); \
3201 return COSTS_N_INSNS (2); \
3205 rtx offset = const0_rtx; \
3206 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3208 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3210 /* Treat this like a signed 16 bit CONST_INT. */ \
3211 if ((OUTER_CODE) == PLUS) \
3213 else if ((OUTER_CODE) == SET) \
3214 return COSTS_N_INSNS (1); \
3216 return COSTS_N_INSNS (2); \
3219 if (GET_CODE (symref) == LABEL_REF) \
3220 return COSTS_N_INSNS (2); \
3222 if (GET_CODE (symref) != SYMBOL_REF) \
3223 return COSTS_N_INSNS (4); \
3225 /* let's be paranoid.... */ \
3226 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3227 return COSTS_N_INSNS (2); \
3229 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3233 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3235 case CONST_DOUBLE: \
3238 if (TARGET_MIPS16) \
3239 return COSTS_N_INSNS (4); \
3240 split_double (X, &high, &low); \
3241 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3242 || low == CONST0_RTX (GET_MODE (low))) \
3246 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3247 This can be used, for example, to indicate how costly a multiply
3248 instruction is. In writing this macro, you can use the construct
3249 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3251 This macro is optional; do not define it if the default cost
3252 assumptions are adequate for the target machine.
3254 If -mdebugd is used, change the multiply cost to 2, so multiply by
3255 a constant isn't converted to a series of shifts. This helps
3256 strength reduction, and also makes it easier to identify what the
3257 compiler is doing. */
3259 /* ??? Fix this to be right for the R8000. */
3260 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3263 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3264 if (simple_memory_operand (X, GET_MODE (X))) \
3265 return COSTS_N_INSNS (num_words); \
3267 return COSTS_N_INSNS (2*num_words); \
3271 return COSTS_N_INSNS (6); \
3274 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3279 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3280 return COSTS_N_INSNS (2); \
3287 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3288 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3294 enum machine_mode xmode = GET_MODE (X); \
3295 if (xmode == SFmode || xmode == DFmode) \
3296 return COSTS_N_INSNS (1); \
3298 return COSTS_N_INSNS (4); \
3304 enum machine_mode xmode = GET_MODE (X); \
3305 if (xmode == SFmode || xmode == DFmode) \
3307 if (mips_cpu == PROCESSOR_R3000 \
3308 || mips_cpu == PROCESSOR_R3900) \
3309 return COSTS_N_INSNS (2); \
3310 else if (mips_cpu == PROCESSOR_R6000) \
3311 return COSTS_N_INSNS (3); \
3313 return COSTS_N_INSNS (6); \
3316 if (xmode == DImode && !TARGET_64BIT) \
3317 return COSTS_N_INSNS (4); \
3323 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3330 enum machine_mode xmode = GET_MODE (X); \
3331 if (xmode == SFmode) \
3333 if (mips_cpu == PROCESSOR_R3000 \
3334 || mips_cpu == PROCESSOR_R3900 \
3335 || mips_cpu == PROCESSOR_R5000) \
3336 return COSTS_N_INSNS (4); \
3337 else if (mips_cpu == PROCESSOR_R6000) \
3338 return COSTS_N_INSNS (5); \
3340 return COSTS_N_INSNS (7); \
3343 if (xmode == DFmode) \
3345 if (mips_cpu == PROCESSOR_R3000 \
3346 || mips_cpu == PROCESSOR_R3900 \
3347 || mips_cpu == PROCESSOR_R5000) \
3348 return COSTS_N_INSNS (5); \
3349 else if (mips_cpu == PROCESSOR_R6000) \
3350 return COSTS_N_INSNS (6); \
3352 return COSTS_N_INSNS (8); \
3355 if (mips_cpu == PROCESSOR_R3000) \
3356 return COSTS_N_INSNS (12); \
3357 else if (mips_cpu == PROCESSOR_R3900) \
3358 return COSTS_N_INSNS (2); \
3359 else if (mips_cpu == PROCESSOR_R6000) \
3360 return COSTS_N_INSNS (17); \
3361 else if (mips_cpu == PROCESSOR_R5000) \
3362 return COSTS_N_INSNS (5); \
3364 return COSTS_N_INSNS (10); \
3370 enum machine_mode xmode = GET_MODE (X); \
3371 if (xmode == SFmode) \
3373 if (mips_cpu == PROCESSOR_R3000 \
3374 || mips_cpu == PROCESSOR_R3900) \
3375 return COSTS_N_INSNS (12); \
3376 else if (mips_cpu == PROCESSOR_R6000) \
3377 return COSTS_N_INSNS (15); \
3379 return COSTS_N_INSNS (23); \
3382 if (xmode == DFmode) \
3384 if (mips_cpu == PROCESSOR_R3000 \
3385 || mips_cpu == PROCESSOR_R3900) \
3386 return COSTS_N_INSNS (19); \
3387 else if (mips_cpu == PROCESSOR_R6000) \
3388 return COSTS_N_INSNS (16); \
3390 return COSTS_N_INSNS (36); \
3393 /* fall through */ \
3397 if (mips_cpu == PROCESSOR_R3000 \
3398 || mips_cpu == PROCESSOR_R3900) \
3399 return COSTS_N_INSNS (35); \
3400 else if (mips_cpu == PROCESSOR_R6000) \
3401 return COSTS_N_INSNS (38); \
3402 else if (mips_cpu == PROCESSOR_R5000) \
3403 return COSTS_N_INSNS (36); \
3405 return COSTS_N_INSNS (69); \
3408 /* A sign extend from SImode to DImode in 64 bit mode is often \
3409 zero instructions, because the result can often be used \
3410 directly by another instruction; we'll call it one. */ \
3411 if (TARGET_64BIT && GET_MODE (X) == DImode \
3412 && GET_MODE (XEXP (X, 0)) == SImode) \
3413 return COSTS_N_INSNS (1); \
3415 return COSTS_N_INSNS (2); \
3418 if (TARGET_64BIT && GET_MODE (X) == DImode \
3419 && GET_MODE (XEXP (X, 0)) == SImode) \
3420 return COSTS_N_INSNS (2); \
3422 return COSTS_N_INSNS (1);
3424 /* An expression giving the cost of an addressing mode that
3425 contains ADDRESS. If not defined, the cost is computed from the
3426 form of the ADDRESS expression and the `CONST_COSTS' values.
3428 For most CISC machines, the default cost is a good approximation
3429 of the true cost of the addressing mode. However, on RISC
3430 machines, all instructions normally have the same length and
3431 execution time. Hence all addresses will have equal costs.
3433 In cases where more than one form of an address is known, the
3434 form with the lowest cost will be used. If multiple forms have
3435 the same, lowest, cost, the one that is the most complex will be
3438 For example, suppose an address that is equal to the sum of a
3439 register and a constant is used twice in the same basic block.
3440 When this macro is not defined, the address will be computed in
3441 a register and memory references will be indirect through that
3442 register. On machines where the cost of the addressing mode
3443 containing the sum is no higher than that of a simple indirect
3444 reference, this will produce an additional instruction and
3445 possibly require an additional register. Proper specification
3446 of this macro eliminates this overhead for such machines.
3448 Similar use of this macro is made in strength reduction of loops.
3450 ADDRESS need not be valid as an address. In such a case, the
3451 cost is not relevant and can be any value; invalid addresses
3452 need not be assigned a different cost.
3454 On machines where an address involving more than one register is
3455 as cheap as an address computation involving only one register,
3456 defining `ADDRESS_COST' to reflect this can cause two registers
3457 to be live over a region of code where only one would have been
3458 if `ADDRESS_COST' were not defined in that manner. This effect
3459 should be considered in the definition of this macro.
3460 Equivalent costs should probably only be given to addresses with
3461 different numbers of registers on machines with lots of registers.
3463 This macro will normally either not be defined or be defined as
3466 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3468 /* A C expression for the cost of moving data from a register in
3469 class FROM to one in class TO. The classes are expressed using
3470 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3471 the default; other values are interpreted relative to that.
3473 It is not required that the cost always equal 2 when FROM is the
3474 same as TO; on some machines it is expensive to move between
3475 registers if they are not general registers.
3477 If reload sees an insn consisting of a single `set' between two
3478 hard registers, and if `REGISTER_MOVE_COST' applied to their
3479 classes returns a value of 2, reload does not check to ensure
3480 that the constraints of the insn are met. Setting a cost of
3481 other than 2 will allow reload to verify that the constraints are
3482 met. You should do this if the `movM' pattern's constraints do
3483 not allow such copying. */
3485 #define REGISTER_MOVE_COST(FROM, TO) \
3486 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3487 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3488 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3489 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3490 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3491 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3492 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3493 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3494 : (((FROM) == HI_REG || (FROM) == LO_REG \
3495 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3496 && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6 \
3497 : (((FROM) == HI_REG || (FROM) == LO_REG \
3498 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3499 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 8 : 6) \
3500 : (((TO) == HI_REG || (TO) == LO_REG \
3501 || (TO) == MD_REGS || (TO) == HILO_REG) \
3502 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3503 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3504 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3507 /* ??? Fix this to be right for the R8000. */
3508 #define MEMORY_MOVE_COST(MODE) \
3509 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4)
3511 /* A C expression for the cost of a branch instruction. A value of
3512 1 is the default; other values are interpreted relative to that. */
3514 /* ??? Fix this to be right for the R8000. */
3515 #define BRANCH_COST \
3517 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3520 /* A C statement (sans semicolon) to update the integer variable COST
3521 based on the relationship between INSN that is dependent on
3522 DEP_INSN through the dependence LINK. The default is to make no
3523 adjustment to COST. On the MIPS, ignore the cost of anti- and
3524 output-dependencies. */
3526 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3527 if (REG_NOTE_KIND (LINK) != 0) \
3528 (COST) = 0; /* Anti or output dependence. */
3530 /* Optionally define this if you have added predicates to
3531 `MACHINE.c'. This macro is called within an initializer of an
3532 array of structures. The first field in the structure is the
3533 name of a predicate and the second field is an array of rtl
3534 codes. For each predicate, list all rtl codes that can be in
3535 expressions matched by the predicate. The list should have a
3536 trailing comma. Here is an example of two entries in the list
3537 for a typical RISC machine:
3539 #define PREDICATE_CODES \
3540 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3541 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3543 Defining this macro does not affect the generated code (however,
3544 incorrect definitions that omit an rtl code that may be matched
3545 by the predicate can cause the compiler to malfunction).
3546 Instead, it allows the table built by `genrecog' to be more
3547 compact and efficient, thus speeding up the compiler. The most
3548 important predicates to include in the list specified by this
3549 macro are thoses used in the most insn patterns. */
3551 #define PREDICATE_CODES \
3552 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3553 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3554 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3555 {"reg_or_0_operand", { REG, CONST_INT, SUBREG }}, \
3556 {"small_int", { CONST_INT }}, \
3557 {"large_int", { CONST_INT }}, \
3558 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3559 {"const_float_1_operand", { CONST_DOUBLE }}, \
3560 {"simple_memory_operand", { MEM, SUBREG }}, \
3561 {"equality_op", { EQ, NE }}, \
3562 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3564 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3565 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3566 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3567 SYMBOL_REF, LABEL_REF, SUBREG, \
3569 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3570 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3571 MEM, SIGN_EXTEND }}, \
3572 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3573 {"se_reg_or_0_operand", { REG, CONST_INT, SUBREG, \
3575 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3577 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3579 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3580 SYMBOL_REF, LABEL_REF, SUBREG, \
3581 REG, SIGN_EXTEND }}, \
3582 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3583 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3584 CONST_DOUBLE, CONST }},
3587 /* If defined, a C statement to be executed just prior to the
3588 output of assembler code for INSN, to modify the extracted
3589 operands so they will be output differently.
3591 Here the argument OPVEC is the vector containing the operands
3592 extracted from INSN, and NOPERANDS is the number of elements of
3593 the vector which contain meaningful data for this insn. The
3594 contents of this vector are what will be used to convert the
3595 insn template into assembler code, so you can change the
3596 assembler output by changing the contents of the vector.
3598 We use it to check if the current insn needs a nop in front of it
3599 because of load delays, and also to update the delay slot
3602 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3603 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3606 /* Control the assembler format that we output. */
3608 /* Output at beginning of assembler file.
3609 If we are optimizing to use the global pointer, create a temporary
3610 file to hold all of the text stuff, and write it out to the end.
3611 This is needed because the MIPS assembler is evidently one pass,
3612 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3613 declaration when the code is processed, it generates a two
3614 instruction sequence. */
3616 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3618 /* Output to assembler file text saying following lines
3619 may contain character constants, extra white space, comments, etc. */
3621 #define ASM_APP_ON " #APP\n"
3623 /* Output to assembler file text saying following lines
3624 no longer contain unusual constructs. */
3626 #define ASM_APP_OFF " #NO_APP\n"
3628 /* How to refer to registers in assembler output.
3629 This sequence is indexed by compiler's hard-register-number (see above).
3631 In order to support the two different conventions for register names,
3632 we use the name of a table set up in mips.c, which is overwritten
3633 if -mrnames is used. */
3635 #define REGISTER_NAMES \
3637 &mips_reg_names[ 0][0], \
3638 &mips_reg_names[ 1][0], \
3639 &mips_reg_names[ 2][0], \
3640 &mips_reg_names[ 3][0], \
3641 &mips_reg_names[ 4][0], \
3642 &mips_reg_names[ 5][0], \
3643 &mips_reg_names[ 6][0], \
3644 &mips_reg_names[ 7][0], \
3645 &mips_reg_names[ 8][0], \
3646 &mips_reg_names[ 9][0], \
3647 &mips_reg_names[10][0], \
3648 &mips_reg_names[11][0], \
3649 &mips_reg_names[12][0], \
3650 &mips_reg_names[13][0], \
3651 &mips_reg_names[14][0], \
3652 &mips_reg_names[15][0], \
3653 &mips_reg_names[16][0], \
3654 &mips_reg_names[17][0], \
3655 &mips_reg_names[18][0], \
3656 &mips_reg_names[19][0], \
3657 &mips_reg_names[20][0], \
3658 &mips_reg_names[21][0], \
3659 &mips_reg_names[22][0], \
3660 &mips_reg_names[23][0], \
3661 &mips_reg_names[24][0], \
3662 &mips_reg_names[25][0], \
3663 &mips_reg_names[26][0], \
3664 &mips_reg_names[27][0], \
3665 &mips_reg_names[28][0], \
3666 &mips_reg_names[29][0], \
3667 &mips_reg_names[30][0], \
3668 &mips_reg_names[31][0], \
3669 &mips_reg_names[32][0], \
3670 &mips_reg_names[33][0], \
3671 &mips_reg_names[34][0], \
3672 &mips_reg_names[35][0], \
3673 &mips_reg_names[36][0], \
3674 &mips_reg_names[37][0], \
3675 &mips_reg_names[38][0], \
3676 &mips_reg_names[39][0], \
3677 &mips_reg_names[40][0], \
3678 &mips_reg_names[41][0], \
3679 &mips_reg_names[42][0], \
3680 &mips_reg_names[43][0], \
3681 &mips_reg_names[44][0], \
3682 &mips_reg_names[45][0], \
3683 &mips_reg_names[46][0], \
3684 &mips_reg_names[47][0], \
3685 &mips_reg_names[48][0], \
3686 &mips_reg_names[49][0], \
3687 &mips_reg_names[50][0], \
3688 &mips_reg_names[51][0], \
3689 &mips_reg_names[52][0], \
3690 &mips_reg_names[53][0], \
3691 &mips_reg_names[54][0], \
3692 &mips_reg_names[55][0], \
3693 &mips_reg_names[56][0], \
3694 &mips_reg_names[57][0], \
3695 &mips_reg_names[58][0], \
3696 &mips_reg_names[59][0], \
3697 &mips_reg_names[60][0], \
3698 &mips_reg_names[61][0], \
3699 &mips_reg_names[62][0], \
3700 &mips_reg_names[63][0], \
3701 &mips_reg_names[64][0], \
3702 &mips_reg_names[65][0], \
3703 &mips_reg_names[66][0], \
3704 &mips_reg_names[67][0], \
3705 &mips_reg_names[68][0], \
3706 &mips_reg_names[69][0], \
3707 &mips_reg_names[70][0], \
3708 &mips_reg_names[71][0], \
3709 &mips_reg_names[72][0], \
3710 &mips_reg_names[73][0], \
3711 &mips_reg_names[74][0], \
3712 &mips_reg_names[75][0], \
3715 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3716 So define this for it. */
3717 #define DEBUG_REGISTER_NAMES \
3719 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3720 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3721 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3722 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3723 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3724 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3725 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3726 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3727 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3728 "$fcc5","$fcc6","$fcc7","$rap" \
3731 /* If defined, a C initializer for an array of structures
3732 containing a name and a register number. This macro defines
3733 additional names for hard registers, thus allowing the `asm'
3734 option in declarations to refer to registers using alternate
3737 We define both names for the integer registers here. */
3739 #define ADDITIONAL_REGISTER_NAMES \
3741 { "$0", 0 + GP_REG_FIRST }, \
3742 { "$1", 1 + GP_REG_FIRST }, \
3743 { "$2", 2 + GP_REG_FIRST }, \
3744 { "$3", 3 + GP_REG_FIRST }, \
3745 { "$4", 4 + GP_REG_FIRST }, \
3746 { "$5", 5 + GP_REG_FIRST }, \
3747 { "$6", 6 + GP_REG_FIRST }, \
3748 { "$7", 7 + GP_REG_FIRST }, \
3749 { "$8", 8 + GP_REG_FIRST }, \
3750 { "$9", 9 + GP_REG_FIRST }, \
3751 { "$10", 10 + GP_REG_FIRST }, \
3752 { "$11", 11 + GP_REG_FIRST }, \
3753 { "$12", 12 + GP_REG_FIRST }, \
3754 { "$13", 13 + GP_REG_FIRST }, \
3755 { "$14", 14 + GP_REG_FIRST }, \
3756 { "$15", 15 + GP_REG_FIRST }, \
3757 { "$16", 16 + GP_REG_FIRST }, \
3758 { "$17", 17 + GP_REG_FIRST }, \
3759 { "$18", 18 + GP_REG_FIRST }, \
3760 { "$19", 19 + GP_REG_FIRST }, \
3761 { "$20", 20 + GP_REG_FIRST }, \
3762 { "$21", 21 + GP_REG_FIRST }, \
3763 { "$22", 22 + GP_REG_FIRST }, \
3764 { "$23", 23 + GP_REG_FIRST }, \
3765 { "$24", 24 + GP_REG_FIRST }, \
3766 { "$25", 25 + GP_REG_FIRST }, \
3767 { "$26", 26 + GP_REG_FIRST }, \
3768 { "$27", 27 + GP_REG_FIRST }, \
3769 { "$28", 28 + GP_REG_FIRST }, \
3770 { "$29", 29 + GP_REG_FIRST }, \
3771 { "$30", 30 + GP_REG_FIRST }, \
3772 { "$31", 31 + GP_REG_FIRST }, \
3773 { "$sp", 29 + GP_REG_FIRST }, \
3774 { "$fp", 30 + GP_REG_FIRST }, \
3775 { "at", 1 + GP_REG_FIRST }, \
3776 { "v0", 2 + GP_REG_FIRST }, \
3777 { "v1", 3 + GP_REG_FIRST }, \
3778 { "a0", 4 + GP_REG_FIRST }, \
3779 { "a1", 5 + GP_REG_FIRST }, \
3780 { "a2", 6 + GP_REG_FIRST }, \
3781 { "a3", 7 + GP_REG_FIRST }, \
3782 { "t0", 8 + GP_REG_FIRST }, \
3783 { "t1", 9 + GP_REG_FIRST }, \
3784 { "t2", 10 + GP_REG_FIRST }, \
3785 { "t3", 11 + GP_REG_FIRST }, \
3786 { "t4", 12 + GP_REG_FIRST }, \
3787 { "t5", 13 + GP_REG_FIRST }, \
3788 { "t6", 14 + GP_REG_FIRST }, \
3789 { "t7", 15 + GP_REG_FIRST }, \
3790 { "s0", 16 + GP_REG_FIRST }, \
3791 { "s1", 17 + GP_REG_FIRST }, \
3792 { "s2", 18 + GP_REG_FIRST }, \
3793 { "s3", 19 + GP_REG_FIRST }, \
3794 { "s4", 20 + GP_REG_FIRST }, \
3795 { "s5", 21 + GP_REG_FIRST }, \
3796 { "s6", 22 + GP_REG_FIRST }, \
3797 { "s7", 23 + GP_REG_FIRST }, \
3798 { "t8", 24 + GP_REG_FIRST }, \
3799 { "t9", 25 + GP_REG_FIRST }, \
3800 { "k0", 26 + GP_REG_FIRST }, \
3801 { "k1", 27 + GP_REG_FIRST }, \
3802 { "gp", 28 + GP_REG_FIRST }, \
3803 { "sp", 29 + GP_REG_FIRST }, \
3804 { "fp", 30 + GP_REG_FIRST }, \
3805 { "ra", 31 + GP_REG_FIRST }, \
3806 { "$sp", 29 + GP_REG_FIRST }, \
3807 { "$fp", 30 + GP_REG_FIRST } \
3810 /* Define results of standard character escape sequences. */
3811 #define TARGET_BELL 007
3812 #define TARGET_BS 010
3813 #define TARGET_TAB 011
3814 #define TARGET_NEWLINE 012
3815 #define TARGET_VT 013
3816 #define TARGET_FF 014
3817 #define TARGET_CR 015
3819 /* A C compound statement to output to stdio stream STREAM the
3820 assembler syntax for an instruction operand X. X is an RTL
3823 CODE is a value that can be used to specify one of several ways
3824 of printing the operand. It is used when identical operands
3825 must be printed differently depending on the context. CODE
3826 comes from the `%' specification that was used to request
3827 printing of the operand. If the specification was just `%DIGIT'
3828 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3829 is the ASCII code for LTR.
3831 If X is a register, this macro should print the register's name.
3832 The names can be found in an array `reg_names' whose type is
3833 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3835 When the machine description has a specification `%PUNCT' (a `%'
3836 followed by a punctuation character), this macro is called with
3837 a null pointer for X and the punctuation character for CODE.
3839 See mips.c for the MIPS specific codes. */
3841 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3843 /* A C expression which evaluates to true if CODE is a valid
3844 punctuation character for use in the `PRINT_OPERAND' macro. If
3845 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3846 punctuation characters (except for the standard one, `%') are
3847 used in this way. */
3849 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3851 /* A C compound statement to output to stdio stream STREAM the
3852 assembler syntax for an instruction operand that is a memory
3853 reference whose address is ADDR. ADDR is an RTL expression.
3855 On some machines, the syntax for a symbolic address depends on
3856 the section that the address refers to. On these machines,
3857 define the macro `ENCODE_SECTION_INFO' to store the information
3858 into the `symbol_ref', and then check for it here. */
3860 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3863 /* A C statement, to be executed after all slot-filler instructions
3864 have been output. If necessary, call `dbr_sequence_length' to
3865 determine the number of slots filled in a sequence (zero if not
3866 currently outputting a sequence), to decide how many no-ops to
3867 output, or whatever.
3869 Don't define this macro if it has nothing to do, but it is
3870 helpful in reading assembly output if the extent of the delay
3871 sequence is made explicit (e.g. with white space).
3873 Note that output routines for instructions with delay slots must
3874 be prepared to deal with not being output as part of a sequence
3875 (i.e. when the scheduling pass is not run, or when no slot
3876 fillers could be found.) The variable `final_sequence' is null
3877 when not processing a sequence, otherwise it contains the
3878 `sequence' rtx being output. */
3880 #define DBR_OUTPUT_SEQEND(STREAM) \
3883 if (set_nomacro > 0 && --set_nomacro == 0) \
3884 fputs ("\t.set\tmacro\n", STREAM); \
3886 if (set_noreorder > 0 && --set_noreorder == 0) \
3887 fputs ("\t.set\treorder\n", STREAM); \
3889 dslots_jump_filled++; \
3890 fputs ("\n", STREAM); \
3895 /* How to tell the debugger about changes of source files. Note, the
3896 mips ECOFF format cannot deal with changes of files inside of
3897 functions, which means the output of parser generators like bison
3898 is generally not debuggable without using the -l switch. Lose,
3899 lose, lose. Silicon graphics seems to want all .file's hardwired
3902 #ifndef SET_FILE_NUMBER
3903 #define SET_FILE_NUMBER() ++num_source_filenames
3906 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3907 mips_output_filename (STREAM, NAME)
3909 /* This is defined so that it can be overridden in iris6.h. */
3910 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3913 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3914 output_quoted_string (STREAM, NAME); \
3915 fputs ("\n", STREAM); \
3919 /* This is how to output a note the debugger telling it the line number
3920 to which the following sequence of instructions corresponds.
3921 Silicon graphics puts a label after each .loc. */
3923 #ifndef LABEL_AFTER_LOC
3924 #define LABEL_AFTER_LOC(STREAM)
3927 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3928 mips_output_lineno (STREAM, LINE)
3930 /* The MIPS implementation uses some labels for it's own purpose. The
3931 following lists what labels are created, and are all formed by the
3932 pattern $L[a-z].*. The machine independent portion of GCC creates
3933 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3935 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3936 $Lb[0-9]+ Begin blocks for MIPS debug support
3937 $Lc[0-9]+ Label for use in s<xx> operation.
3938 $Le[0-9]+ End blocks for MIPS debug support
3939 $Lp\..+ Half-pic labels. */
3941 /* This is how to output the definition of a user-level label named NAME,
3942 such as the label on a static function or variable NAME.
3944 If we are optimizing the gp, remember that this label has been put
3945 out, so we know not to emit an .extern for it in mips_asm_file_end.
3946 We use one of the common bits in the IDENTIFIER tree node for this,
3947 since those bits seem to be unused, and we don't have any method
3948 of getting the decl nodes from the name. */
3950 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
3952 assemble_name (STREAM, NAME); \
3953 fputs (":\n", STREAM); \
3957 /* A C statement (sans semicolon) to output to the stdio stream
3958 STREAM any text necessary for declaring the name NAME of an
3959 initialized variable which is being defined. This macro must
3960 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3961 The argument DECL is the `VAR_DECL' tree node representing the
3964 If this macro is not defined, then the variable name is defined
3965 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3967 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3970 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3971 HALF_PIC_DECLARE (NAME); \
3976 /* This is how to output a command to make the user-level label named NAME
3977 defined for reference from other files. */
3979 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
3981 fputs ("\t.globl\t", STREAM); \
3982 assemble_name (STREAM, NAME); \
3983 fputs ("\n", STREAM); \
3986 /* This says how to define a global common symbol. */
3988 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
3989 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
3991 /* This says how to define a local common symbol (ie, not visible to
3994 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3995 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
3998 /* This says how to output an external. It would be possible not to
3999 output anything and let undefined symbol become external. However
4000 the assembler uses length information on externals to allocate in
4001 data/sdata bss/sbss, thereby saving exec time. */
4003 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4004 mips_output_external(STREAM,DECL,NAME)
4006 /* This says what to print at the end of the assembly file */
4007 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4010 /* This is how to declare a function name. The actual work of
4011 emitting the label is moved to function_prologue, so that we can
4012 get the line number correctly emitted before the .ent directive,
4013 and after any .file directives.
4015 Also, switch files if we are optimizing the global pointer. */
4017 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4019 extern FILE *asm_out_text_file; \
4020 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4022 STREAM = asm_out_text_file; \
4023 /* ??? text_section gets called too soon. If the previous \
4024 function is in a special section and we're not, we have \
4025 to switch back to the text section. We can't call \
4026 text_section again as gcc thinks we're already there. */ \
4027 /* ??? See varasm.c. There are other things that get output \
4028 too early, like alignment (before we've switched STREAM). */ \
4029 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4030 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4033 HALF_PIC_DECLARE (NAME); \
4036 /* This is how to output an internal numbered label where
4037 PREFIX is the class of label and NUM is the number within the class. */
4039 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4040 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4042 /* This is how to store into the string LABEL
4043 the symbol_ref name of an internal numbered label where
4044 PREFIX is the class of label and NUM is the number within the class.
4045 This is suitable for output with `assemble_name'. */
4047 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4048 sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4050 /* This is how to output an assembler line defining a `double' constant. */
4052 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4053 mips_output_double (STREAM, VALUE)
4056 /* This is how to output an assembler line defining a `float' constant. */
4058 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4059 mips_output_float (STREAM, VALUE)
4062 /* This is how to output an assembler line defining an `int' constant. */
4064 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4066 fprintf (STREAM, "\t.word\t"); \
4067 output_addr_const (STREAM, (VALUE)); \
4068 fprintf (STREAM, "\n"); \
4071 /* Likewise for 64 bit, `char' and `short' constants. */
4073 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4077 fprintf (STREAM, "\t.dword\t"); \
4078 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4079 /* We can't use 'X' for negative numbers, because then we won't \
4080 get the right value for the upper 32 bits. */ \
4081 output_addr_const (STREAM, VALUE); \
4083 /* We must use 'X', because otherwise LONG_MIN will print as \
4084 a number that the Irix 6 assembler won't accept. */ \
4085 print_operand (STREAM, VALUE, 'X'); \
4086 fprintf (STREAM, "\n"); \
4090 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4091 UNITS_PER_WORD, 1); \
4092 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4093 UNITS_PER_WORD, 1); \
4097 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4099 fprintf (STREAM, "\t.half\t"); \
4100 output_addr_const (STREAM, (VALUE)); \
4101 fprintf (STREAM, "\n"); \
4104 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4106 fprintf (STREAM, "\t.byte\t"); \
4107 output_addr_const (STREAM, (VALUE)); \
4108 fprintf (STREAM, "\n"); \
4111 /* This is how to output an assembler line for a numeric constant byte. */
4113 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4114 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4116 /* This is how to output an element of a case-vector that is absolute. */
4118 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4119 fprintf (STREAM, "\t%s\t%sL%d\n", \
4120 TARGET_LONG64 ? ".dword" : ".word", \
4121 LOCAL_LABEL_PREFIX, \
4124 /* This is how to output an element of a case-vector that is relative.
4125 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4126 TARGET_EMBEDDED_PIC). */
4128 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, VALUE, REL) \
4130 if (TARGET_MIPS16) \
4131 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4132 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4133 else if (TARGET_EMBEDDED_PIC) \
4134 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4135 TARGET_LONG64 ? ".dword" : ".word", \
4136 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4137 else if (mips_abi == ABI_32) \
4138 fprintf (STREAM, "\t%s\t%sL%d\n", \
4139 TARGET_LONG64 ? ".gpdword" : ".gpword", \
4140 LOCAL_LABEL_PREFIX, VALUE); \
4142 fprintf (STREAM, "\t%s\t%sL%d\n", \
4143 TARGET_LONG64 ? ".dword" : ".word", \
4144 LOCAL_LABEL_PREFIX, VALUE); \
4147 /* When generating embedded PIC or mips16 code we want to put the jump
4148 table in the .text section. In all other cases, we want to put the
4149 jump table in the .rdata section. Unfortunately, we can't use
4150 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4151 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4152 section if appropriate. */
4153 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4155 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4156 function_section (current_function_decl); \
4157 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4160 /* This is how to output an assembler line
4161 that says to advance the location counter
4162 to a multiple of 2**LOG bytes. */
4164 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4166 int mask = (1 << (LOG)) - 1; \
4167 fprintf (STREAM, "\t.align\t%d\n", (LOG)); \
4170 /* This is how to output an assembler line to to advance the location
4171 counter by SIZE bytes. */
4173 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4174 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4176 /* This is how to output a string. */
4177 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4179 register int i, c, len = (LEN), cur_pos = 17; \
4180 register unsigned char *string = (unsigned char *)(STRING); \
4181 fprintf ((STREAM), "\t.ascii\t\""); \
4182 for (i = 0; i < len; i++) \
4184 register int c = string[i]; \
4190 putc ('\\', (STREAM)); \
4191 putc (c, (STREAM)); \
4195 case TARGET_NEWLINE: \
4196 fputs ("\\n", (STREAM)); \
4198 && (((c = string[i+1]) >= '\040' && c <= '~') \
4199 || c == TARGET_TAB)) \
4200 cur_pos = 32767; /* break right here */ \
4206 fputs ("\\t", (STREAM)); \
4211 fputs ("\\f", (STREAM)); \
4216 fputs ("\\b", (STREAM)); \
4221 fputs ("\\r", (STREAM)); \
4226 if (c >= ' ' && c < 0177) \
4228 putc (c, (STREAM)); \
4233 fprintf ((STREAM), "\\%03o", c); \
4238 if (cur_pos > 72 && i+1 < len) \
4241 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4244 fprintf ((STREAM), "\"\n"); \
4247 /* Handle certain cpp directives used in header files on sysV. */
4248 #define SCCS_DIRECTIVE
4250 /* Output #ident as a in the read-only data section. */
4251 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4254 int size = strlen (p) + 1; \
4256 assemble_string (p, size); \
4259 /* Default to -G 8 */
4260 #ifndef MIPS_DEFAULT_GVALUE
4261 #define MIPS_DEFAULT_GVALUE 8
4264 /* Define the strings to put out for each section in the object file. */
4265 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4266 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4267 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4268 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4269 #define READONLY_DATA_SECTION rdata_section
4270 #define SMALL_DATA_SECTION sdata_section
4272 /* What other sections we support other than the normal .data/.text. */
4274 #define EXTRA_SECTIONS in_sdata, in_rdata
4276 /* Define the additional functions to select our additional sections. */
4278 /* on the MIPS it is not a good idea to put constants in the text
4279 section, since this defeats the sdata/data mechanism. This is
4280 especially true when -O is used. In this case an effort is made to
4281 address with faster (gp) register relative addressing, which can
4282 only get at sdata and sbss items (there is no stext !!) However,
4283 if the constant is too large for sdata, and it's readonly, it
4284 will go into the .rdata section. */
4286 #define EXTRA_SECTION_FUNCTIONS \
4290 if (in_section != in_sdata) \
4292 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4293 in_section = in_sdata; \
4300 if (in_section != in_rdata) \
4302 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4303 in_section = in_rdata; \
4307 /* Given a decl node or constant node, choose the section to output it in
4308 and select that section. */
4310 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4312 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4315 /* Store in OUTPUT a string (made with alloca) containing
4316 an assembler-name for a local static variable named NAME.
4317 LABELNO is an integer which is different for each call. */
4319 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4320 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4321 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4323 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4326 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4327 TARGET_64BIT ? "dsubu" : "subu", \
4328 reg_names[STACK_POINTER_REGNUM], \
4329 reg_names[STACK_POINTER_REGNUM], \
4330 TARGET_64BIT ? "sd" : "sw", \
4332 reg_names[STACK_POINTER_REGNUM]); \
4336 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4339 if (! set_noreorder) \
4340 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4342 dslots_load_total++; \
4343 dslots_load_filled++; \
4344 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4345 TARGET_64BIT ? "ld" : "lw", \
4347 reg_names[STACK_POINTER_REGNUM], \
4348 TARGET_64BIT ? "daddu" : "addu", \
4349 reg_names[STACK_POINTER_REGNUM], \
4350 reg_names[STACK_POINTER_REGNUM]); \
4352 if (! set_noreorder) \
4353 fprintf (STREAM, "\t.set\treorder\n"); \
4357 /* Define the parentheses used to group arithmetic operations
4358 in assembler code. */
4360 #define ASM_OPEN_PAREN "("
4361 #define ASM_CLOSE_PAREN ")"
4363 /* How to start an assembler comment.
4364 The leading space is important (the mips native assembler requires it). */
4365 #ifndef ASM_COMMENT_START
4366 #define ASM_COMMENT_START " #"
4370 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4371 and mips-tdump.c to print them out.
4373 These must match the corresponding definitions in gdb/mipsread.c.
4374 Unfortunately, gcc and gdb do not currently share any directories. */
4376 #define CODE_MASK 0x8F300
4377 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4378 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4379 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4382 /* Default definitions for size_t and ptrdiff_t. */
4385 #define NO_BUILTIN_SIZE_TYPE
4386 #define SIZE_TYPE (TARGET_LONG64 ? "long unsigned int" : "unsigned int")
4389 #ifndef PTRDIFF_TYPE
4390 #define NO_BUILTIN_PTRDIFF_TYPE
4391 #define PTRDIFF_TYPE (TARGET_LONG64 ? "long int" : "int")
4394 /* See mips_expand_prologue's use of loadgp for when this should be
4397 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && mips_abi != ABI_32)
4399 /* In mips16 mode, we need to look through the function to check for
4400 PC relative loads that are out of range. */
4401 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4403 /* We need to use a special set of functions to handle hard floating
4404 point code in mips16 mode. */
4406 #ifndef INIT_SUBTARGET_OPTABS
4407 #define INIT_SUBTARGET_OPTABS
4410 #define INIT_TARGET_OPTABS \
4413 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4414 INIT_SUBTARGET_OPTABS; \
4417 add_optab->handlers[(int) SFmode].libfunc = \
4418 gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3"); \
4419 sub_optab->handlers[(int) SFmode].libfunc = \
4420 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3"); \
4421 smul_optab->handlers[(int) SFmode].libfunc = \
4422 gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3"); \
4423 flodiv_optab->handlers[(int) SFmode].libfunc = \
4424 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3"); \
4426 eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2"); \
4427 nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2"); \
4428 gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2"); \
4429 gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2"); \
4430 ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2"); \
4431 lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2"); \
4433 floatsisf_libfunc = \
4434 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf"); \
4436 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi"); \
4438 if (TARGET_DOUBLE_FLOAT) \
4440 add_optab->handlers[(int) DFmode].libfunc = \
4441 gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3"); \
4442 sub_optab->handlers[(int) DFmode].libfunc = \
4443 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3"); \
4444 smul_optab->handlers[(int) DFmode].libfunc = \
4445 gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3"); \
4446 flodiv_optab->handlers[(int) DFmode].libfunc = \
4447 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3"); \
4449 extendsfdf2_libfunc = \
4450 gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2"); \
4451 truncdfsf2_libfunc = \
4452 gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2"); \
4455 gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2"); \
4457 gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2"); \
4459 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2"); \
4461 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2"); \
4463 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2"); \
4465 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2"); \
4467 floatsidf_libfunc = \
4468 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf"); \
4470 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi"); \
projects / platform / upstream / gcc.git / blob