1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-97, 1998 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern char *language_string;
32 extern int may_call_alloca;
33 extern char **save_argv;
34 extern int target_flags;
35 extern char *version_string;
37 /* MIPS external variables defined in mips.c. */
41 CMP_SI, /* compare four byte integers */
42 CMP_DI, /* compare eight byte integers */
43 CMP_SF, /* compare single precision floats */
44 CMP_DF, /* compare double precision floats */
45 CMP_MAX /* max comparison type */
48 /* types of delay slot */
50 DELAY_NONE, /* no delay slot */
51 DELAY_LOAD, /* load from memory delay */
52 DELAY_HILO, /* move from/to hi/lo registers */
53 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
56 /* Which processor to schedule for. Since there is no difference between
57 a R2000 and R3000 in terms of the scheduler, we collapse them into
58 just an R3000. The elements of the enumeration must match exactly
59 the cpu attribute in the mips.md machine description. */
75 /* Recast the cpu class to be the cpu attribute. */
76 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
78 /* Which ABI to use. These are constants because abi64.h must check their
79 value at preprocessing time. */
86 #ifndef MIPS_ABI_DEFAULT
87 /* We define this away so that there is no extra runtime cost if the target
88 doesn't support multiple ABIs. */
89 #define mips_abi ABI_32
94 /* Whether to emit abicalls code sequences or not. */
96 enum mips_abicalls_type {
101 /* Recast the abicalls class to be the abicalls attribute. */
102 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
104 /* Which type of block move to do (whether or not the last store is
105 split out so it can fill a branch delay slot). */
107 enum block_move_type {
108 BLOCK_MOVE_NORMAL, /* generate complete block move */
109 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
110 BLOCK_MOVE_LAST /* generate just the last store */
113 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
114 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
115 extern char *current_function_file; /* filename current function is in */
116 extern int num_source_filenames; /* current .file # */
117 extern int inside_function; /* != 0 if inside of a function */
118 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
119 extern int file_in_function_warning; /* warning given about .file in func */
120 extern int sdb_label_count; /* block start/end next label # */
121 extern int sdb_begin_function_line; /* Starting Line of current function */
122 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
123 extern int g_switch_value; /* value of the -G xx switch */
124 extern int g_switch_set; /* whether -G xx was passed. */
125 extern int sym_lineno; /* sgi next label # for each stmt */
126 extern int set_noreorder; /* # of nested .set noreorder's */
127 extern int set_nomacro; /* # of nested .set nomacro's */
128 extern int set_noat; /* # of nested .set noat's */
129 extern int set_volatile; /* # of nested .set volatile's */
130 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
131 extern int mips_dbx_regno[]; /* Map register # to debug register # */
132 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
133 extern enum cmp_type branch_type; /* what type of branch to use */
134 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
135 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
136 extern int mips_isa; /* architectural level */
137 extern int mips16; /* whether generating mips16 code */
138 extern int mips16_hard_float; /* mips16 without -msoft-float */
139 extern int mips_entry; /* generate entry/exit for mips16 */
140 extern char *mips_cpu_string; /* for -mcpu=<xxx> */
141 extern char *mips_isa_string; /* for -mips{1,2,3,4} */
142 extern char *mips_abi_string; /* for -mabi={32,n32,64} */
143 extern char *mips_entry_string; /* for -mentry */
144 extern char *mips_no_mips16_string; /* for -mno-mips16 */
145 extern int mips_split_addresses; /* perform high/lo_sum support */
146 extern int dslots_load_total; /* total # load related delay slots */
147 extern int dslots_load_filled; /* # filled load delay slots */
148 extern int dslots_jump_total; /* total # jump related delay slots */
149 extern int dslots_jump_filled; /* # filled jump delay slots */
150 extern int dslots_number_nops; /* # of nops needed by previous insn */
151 extern int num_refs[3]; /* # 1/2/3 word references */
152 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
153 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
154 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
155 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
156 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
157 extern int mips_string_length; /* length of strings for mips16 */
158 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
160 /* Functions within mips.c that we reference. */
162 extern void abort_with_insn ();
163 extern int arith32_operand ();
164 extern int arith_operand ();
165 extern int cmp_op ();
166 extern long compute_frame_size ();
167 extern int const_float_1_operand ();
168 extern void expand_block_move ();
169 extern int equality_op ();
170 extern void final_prescan_insn ();
171 extern struct rtx_def * function_arg ();
172 extern void function_arg_advance ();
173 extern int function_arg_partial_nregs ();
174 extern int function_arg_pass_by_reference ();
175 extern void function_epilogue ();
176 extern void function_prologue ();
177 extern void gen_conditional_branch ();
178 extern void gen_conditional_move ();
179 extern struct rtx_def * gen_int_relational ();
180 extern void init_cumulative_args ();
181 extern int large_int ();
182 extern int mips_address_cost ();
183 extern void mips_asm_file_end ();
184 extern void mips_asm_file_start ();
185 extern int mips_can_use_return_insn ();
186 extern int mips_const_double_ok ();
187 extern void mips_count_memory_refs ();
188 extern int mips_debugger_offset ();
189 extern void mips_declare_object ();
190 extern int mips_epilogue_delay_slots ();
191 extern void mips_expand_epilogue ();
192 extern void mips_expand_prologue ();
193 extern int mips_check_split ();
194 extern char *mips_fill_delay_slot ();
195 extern char *mips_move_1word ();
196 extern char *mips_move_2words ();
197 extern void mips_output_double ();
198 extern int mips_output_external ();
199 extern void mips_output_float ();
200 extern void mips_output_filename ();
201 extern void mips_output_lineno ();
202 extern char *output_block_move ();
203 extern void override_options ();
204 extern int pc_or_label_operand ();
205 extern void print_operand_address ();
206 extern void print_operand ();
207 extern void print_options ();
208 extern int reg_or_0_operand ();
209 extern int simple_epilogue_p ();
210 extern int simple_memory_operand ();
211 extern int double_memory_operand ();
212 extern int small_int ();
214 extern int uns_arith_operand ();
215 extern struct rtx_def * embedded_pic_offset ();
216 extern void mips_order_regs_for_local_alloc ();
217 extern struct rtx_def * mips16_gp_pseudo_reg ();
218 extern struct rtx_def * mips16_gp_offset ();
219 extern int mips16_gp_offset_p ();
220 extern int mips16_constant ();
221 extern int mips16_constant_after_function_p ();
222 extern int build_mips16_call_stub ();
224 /* Recognition functions that return if a condition is true. */
225 extern int address_operand ();
226 extern int call_insn_operand ();
227 extern int const_double_operand ();
228 extern int const_int_operand ();
229 extern int consttable_operand ();
230 extern int general_operand ();
231 extern int immediate_operand ();
232 extern int memory_address_p ();
233 extern int memory_operand ();
234 extern int nonimmediate_operand ();
235 extern int nonmemory_operand ();
236 extern int pic_address_needs_scratch ();
237 extern int register_operand ();
238 extern int scratch_operand ();
239 extern int move_operand ();
240 extern int movdi_operand ();
241 extern int se_register_operand ();
242 extern int se_reg_or_0_operand ();
243 extern int se_uns_arith_operand ();
244 extern int se_arith_operand ();
245 extern int se_nonmemory_operand ();
246 extern int se_nonimmediate_operand ();
247 extern int m16_uimm3_b ();
248 extern int m16_simm4_1 ();
249 extern int m16_nsimm4_1 ();
250 extern int m16_simm5_1 ();
251 extern int m16_nsimm5_1 ();
252 extern int m16_uimm5_4 ();
253 extern int m16_nuimm5_4 ();
254 extern int m16_simm8_1 ();
255 extern int m16_nsimm8_1 ();
256 extern int m16_uimm8_1 ();
257 extern int m16_nuimm8_1 ();
258 extern int m16_uimm8_m1_1 ();
259 extern int m16_uimm8_4 ();
260 extern int m16_nuimm8_4 ();
261 extern int m16_simm8_8 ();
262 extern int m16_nsimm8_8 ();
263 extern int m16_usym8_4 ();
264 extern int m16_usym5_4 ();
266 /* Functions to change what output section we are using. */
267 extern void data_section ();
268 extern void rdata_section ();
269 extern void readonly_data_section ();
270 extern void sdata_section ();
271 extern void text_section ();
272 extern void mips_select_rtx_section ();
273 extern void mips_select_section ();
275 /* Stubs for half-pic support if not OSF/1 reference platform. */
278 #define HALF_PIC_P() 0
279 #define HALF_PIC_NUMBER_PTRS 0
280 #define HALF_PIC_NUMBER_REFS 0
281 #define HALF_PIC_ENCODE(DECL)
282 #define HALF_PIC_DECLARE(NAME)
283 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
284 #define HALF_PIC_ADDRESS_P(X) 0
285 #define HALF_PIC_PTR(X) X
286 #define HALF_PIC_FINISH(STREAM)
290 /* Run-time compilation parameters selecting different hardware subsets. */
292 /* Macros used in the machine description to test the flags. */
294 /* Bits for real switches */
295 #define MASK_INT64 0x00000001 /* ints are 64 bits */
296 #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
297 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
298 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
299 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
300 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
301 #define MASK_STATS 0x00000040 /* print statistics to stderr */
302 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
303 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
304 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
305 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
306 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
307 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
308 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
309 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
310 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
311 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
312 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
313 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
314 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
315 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
316 #define MASK_MIPS16 0x01000000 /* Generate mips16 code */
318 /* Dummy switches used only in spec's*/
319 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
321 /* Debug switches, not documented */
322 #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */
323 #define MASK_DEBUG_A 0x20000000 /* don't allow <label>($reg) addrs */
324 #define MASK_DEBUG_B 0x10000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
325 #define MASK_DEBUG_C 0x08000000 /* don't expand seq, etc. */
326 #define MASK_DEBUG_D 0x04000000 /* don't do define_split's */
327 #define MASK_DEBUG_E 0x02000000 /* function_arg debug */
328 #define MASK_DEBUG_F 0
329 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
330 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
331 #define MASK_DEBUG_I 0x00200000 /* unused */
333 /* r4000 64 bit sizes */
334 #define TARGET_INT64 (target_flags & MASK_INT64)
335 #define TARGET_LONG64 (target_flags & MASK_LONG64)
336 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
337 #define TARGET_64BIT (target_flags & MASK_64BIT)
339 /* Mips vs. GNU linker */
340 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
342 /* generate mips 3900 insns */
343 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
345 /* Mips vs. GNU assembler */
346 #define TARGET_GAS (target_flags & MASK_GAS)
347 #define TARGET_UNIX_ASM (!TARGET_GAS)
348 #define TARGET_MIPS_AS TARGET_UNIX_ASM
351 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
352 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
353 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
354 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
355 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
356 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
357 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
358 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
359 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
360 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
362 /* Reg. Naming in .s ($21 vs. $a0) */
363 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
365 /* Optimize for Sdata/Sbss */
366 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
368 /* print program statistics */
369 #define TARGET_STATS (target_flags & MASK_STATS)
371 /* call memcpy instead of inline code */
372 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
374 /* .abicalls, etc from Pyramid V.4 */
375 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
377 /* OSF pic references to externs */
378 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
380 /* software floating point */
381 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
382 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
384 /* always call through a register */
385 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
387 /* generate embedded PIC code;
389 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
391 /* for embedded systems, optimize for
392 reduced RAM space instead of for
394 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
396 /* generate big endian code. */
397 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
399 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
400 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
402 #define TARGET_MAD (target_flags & MASK_MAD)
404 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
406 /* This is true if we must enable the assembly language file switching
409 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
411 /* We must disable the function end stabs when doing the file switching trick,
412 because the Lscope stabs end up in the wrong place, making it impossible
413 to debug the resulting code. */
414 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
416 /* Generate mips16 code */
417 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
419 /* Macro to define tables used to set the flags.
420 This is a list in braces of pairs in braces,
421 each pair being { "NAME", VALUE }
422 where VALUE is the bits to set or minus the bits to clear.
423 An empty string NAME is used to identify the default VALUE. */
425 #define TARGET_SWITCHES \
427 {"int64", MASK_INT64 | MASK_LONG64}, \
428 {"long64", MASK_LONG64}, \
429 {"split-addresses", MASK_SPLIT_ADDR}, \
430 {"no-split-addresses", -MASK_SPLIT_ADDR}, \
431 {"mips-as", -MASK_GAS}, \
433 {"rnames", MASK_NAME_REGS}, \
434 {"no-rnames", -MASK_NAME_REGS}, \
435 {"gpOPT", MASK_GPOPT}, \
436 {"gpopt", MASK_GPOPT}, \
437 {"no-gpOPT", -MASK_GPOPT}, \
438 {"no-gpopt", -MASK_GPOPT}, \
439 {"stats", MASK_STATS}, \
440 {"no-stats", -MASK_STATS}, \
441 {"memcpy", MASK_MEMCPY}, \
442 {"no-memcpy", -MASK_MEMCPY}, \
443 {"mips-tfile", MASK_MIPS_TFILE}, \
444 {"no-mips-tfile", -MASK_MIPS_TFILE}, \
445 {"soft-float", MASK_SOFT_FLOAT}, \
446 {"hard-float", -MASK_SOFT_FLOAT}, \
447 {"fp64", MASK_FLOAT64}, \
448 {"fp32", -MASK_FLOAT64}, \
449 {"gp64", MASK_64BIT}, \
450 {"gp32", -MASK_64BIT}, \
451 {"abicalls", MASK_ABICALLS}, \
452 {"no-abicalls", -MASK_ABICALLS}, \
453 {"half-pic", MASK_HALF_PIC}, \
454 {"no-half-pic", -MASK_HALF_PIC}, \
455 {"long-calls", MASK_LONG_CALLS}, \
456 {"no-long-calls", -MASK_LONG_CALLS}, \
457 {"embedded-pic", MASK_EMBEDDED_PIC}, \
458 {"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
459 {"embedded-data", MASK_EMBEDDED_DATA}, \
460 {"no-embedded-data", -MASK_EMBEDDED_DATA}, \
461 {"eb", MASK_BIG_ENDIAN}, \
462 {"el", -MASK_BIG_ENDIAN}, \
463 {"single-float", MASK_SINGLE_FLOAT}, \
464 {"double-float", -MASK_SINGLE_FLOAT}, \
466 {"no-mad", -MASK_MAD}, \
467 {"fix4300", MASK_4300_MUL_FIX}, \
468 {"no-fix4300", -MASK_4300_MUL_FIX}, \
469 {"4650", MASK_MAD | MASK_SINGLE_FLOAT}, \
470 {"3900", MASK_MIPS3900}, \
471 {"debug", MASK_DEBUG}, \
472 {"debuga", MASK_DEBUG_A}, \
473 {"debugb", MASK_DEBUG_B}, \
474 {"debugc", MASK_DEBUG_C}, \
475 {"debugd", MASK_DEBUG_D}, \
476 {"debuge", MASK_DEBUG_E}, \
477 {"debugf", MASK_DEBUG_F}, \
478 {"debugg", MASK_DEBUG_G}, \
479 {"debugh", MASK_DEBUG_H}, \
480 {"debugi", MASK_DEBUG_I}, \
481 {"", (TARGET_DEFAULT \
482 | TARGET_CPU_DEFAULT \
483 | TARGET_ENDIAN_DEFAULT)} \
486 /* Default target_flags if no switches are specified */
488 #ifndef TARGET_DEFAULT
489 #define TARGET_DEFAULT 0
492 #ifndef TARGET_CPU_DEFAULT
493 #define TARGET_CPU_DEFAULT 0
496 #ifndef TARGET_ENDIAN_DEFAULT
498 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
500 #define TARGET_ENDIAN_DEFAULT 0
504 #ifndef MULTILIB_DEFAULTS
505 #if TARGET_ENDIAN_DEFAULT == 0
506 #define MULTILIB_DEFAULTS { "EL", "mips1" }
508 #define MULTILIB_DEFAULTS { "EB", "mips1" }
512 /* We must pass -EL to the linker by default for little endian embedded
513 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
514 linker will default to using big-endian output files. The OUTPUT_FORMAT
515 line must be in the linker script, otherwise -EB/-EL will not work. */
517 #ifndef LINKER_ENDIAN_SPEC
518 #if TARGET_ENDIAN_DEFAULT == 0
519 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
521 #define LINKER_ENDIAN_SPEC ""
525 /* This macro is similar to `TARGET_SWITCHES' but defines names of
526 command options that have values. Its definition is an
527 initializer with a subgrouping for each command option.
529 Each subgrouping contains a string constant, that defines the
530 fixed part of the option name, and the address of a variable.
531 The variable, type `char *', is set to the variable part of the
532 given option if the fixed part matches. The actual option name
533 is made by appending `-m' to the specified name.
535 Here is an example which defines `-mshort-data-NUMBER'. If the
536 given option is `-mshort-data-512', the variable `m88k_short_data'
537 will be set to the string `"512"'.
539 extern char *m88k_short_data;
540 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
542 #define TARGET_OPTIONS \
544 SUBTARGET_TARGET_OPTIONS \
545 { "cpu=", &mips_cpu_string }, \
546 { "ips", &mips_isa_string }, \
547 { "entry", &mips_entry_string }, \
548 { "no-mips16", &mips_no_mips16_string } \
551 /* This is meant to be redefined in the host dependent files. */
552 #define SUBTARGET_TARGET_OPTIONS
554 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
555 #define GENERATE_MULT3 (TARGET_MIPS3900 \
557 #define GENERATE_MADD (TARGET_MIPS3900 \
562 /* Macros to decide whether certain features are available or not,
563 depending on the instruction set architecture level. */
565 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
566 #define HAVE_SQRT_P() (mips_isa >= 2)
568 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
569 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
570 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
571 target_flags, and -mgp64 sets MASK_64BIT.
573 Setting MASK_64BIT in target_flags will cause gcc to assume that
574 registers are 64 bits wide. int, long and void * will be 32 bit;
575 this may be changed with -mint64 or -mlong64.
577 The gen* programs link code that refers to MASK_64BIT. They don't
578 actually use the information in target_flags; they just refer to
581 /* Switch Recognition by gcc.c. Add -G xx support */
583 #ifdef SWITCH_TAKES_ARG
584 #undef SWITCH_TAKES_ARG
587 #define SWITCH_TAKES_ARG(CHAR) \
588 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
590 /* Sometimes certain combinations of command options do not make sense
591 on a particular target machine. You can define a macro
592 `OVERRIDE_OPTIONS' to take account of this. This macro, if
593 defined, is executed once just after all the command options have
596 On the MIPS, it is used to handle -G. We also use it to set up all
597 of the tables referenced in the other macros. */
599 #define OVERRIDE_OPTIONS override_options ()
601 /* Zero or more C statements that may conditionally modify two
602 variables `fixed_regs' and `call_used_regs' (both of type `char
603 []') after they have been initialized from the two preceding
606 This is necessary in case the fixed or call-clobbered registers
607 depend on target flags.
609 You need not define this macro if it has no work to do.
611 If the usage of an entire class of registers depends on the target
612 flags, you may indicate this to GCC by using this macro to modify
613 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
614 the classes which should not be used by GCC. Also define the macro
615 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
616 letter for a class that shouldn't be used.
618 (However, if this class is not included in `GENERAL_REGS' and all
619 of the insn patterns whose constraints permit this class are
620 controlled by target switches, then GCC will automatically avoid
621 using these registers when the target switches are opposed to
624 #define CONDITIONAL_REGISTER_USAGE \
627 if (!TARGET_HARD_FLOAT) \
631 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
632 fixed_regs[regno] = call_used_regs[regno] = 1; \
633 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
634 fixed_regs[regno] = call_used_regs[regno] = 1; \
636 else if (mips_isa < 4) \
640 /* We only have a single condition code register. We \
641 implement this by hiding all the condition code registers, \
642 and generating RTL that refers directly to ST_REG_FIRST. */ \
643 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
644 fixed_regs[regno] = call_used_regs[regno] = 1; \
646 /* In mips16 mode, we permit the $t temporary registers to be used \
647 for reload. We prohibit the unused $s registers, since they \
648 are caller saved, and saving them via a mips16 register would \
649 probably waste more time than just reloading the value. */ \
652 fixed_regs[18] = call_used_regs[18] = 1; \
653 fixed_regs[19] = call_used_regs[19] = 1; \
654 fixed_regs[20] = call_used_regs[20] = 1; \
655 fixed_regs[21] = call_used_regs[21] = 1; \
656 fixed_regs[22] = call_used_regs[22] = 1; \
657 fixed_regs[23] = call_used_regs[23] = 1; \
658 fixed_regs[26] = call_used_regs[26] = 1; \
659 fixed_regs[27] = call_used_regs[27] = 1; \
660 fixed_regs[30] = call_used_regs[30] = 1; \
662 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
666 /* This is meant to be redefined in the host dependent files. */
667 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
669 /* Show we can debug even without a frame pointer. */
670 #define CAN_DEBUG_WITHOUT_FP
672 /* Complain about missing specs and predefines that should be defined in each
673 of the target tm files to override the defaults. This is mostly a place-
674 holder until I can get each of the files updated [mm]. */
676 #if defined(OSF_OS) \
677 || defined(DECSTATION) \
678 || defined(SGI_TARGET) \
679 || defined(MIPS_NEWS) \
680 || defined(MIPS_SYSV) \
681 || defined(MIPS_SVR4) \
682 || defined(MIPS_BSD43)
684 #ifndef CPP_PREDEFINES
685 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
689 #error "Define LIB_SPEC in the appropriate tm.h file"
692 #ifndef STARTFILE_SPEC
693 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
697 #error "Define MACHINE_TYPE in the appropriate tm.h file"
701 /* Tell collect what flags to pass to nm. */
703 #define NM_FLAGS "-Bp"
707 /* Names to predefine in the preprocessor for this target machine. */
709 #ifndef CPP_PREDEFINES
710 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
711 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
712 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
715 /* Assembler specs. */
717 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
720 #define MIPS_AS_ASM_SPEC "\
721 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
722 %{pipe: %e-pipe is not supported.} \
723 %{K} %(subtarget_mips_as_asm_spec)"
725 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
726 rather than gas. It may be overridden by subtargets. */
728 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
729 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
732 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
735 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
737 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
738 GAS_ASM_SPEC as the default, depending upon the value of
741 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
744 #define TARGET_ASM_SPEC "\
745 %{mmips-as: %(mips_as_asm_spec)} \
746 %{!mmips-as: %(gas_asm_spec)}"
750 #define TARGET_ASM_SPEC "\
751 %{!mgas: %(mips_as_asm_spec)} \
752 %{mgas: %(gas_asm_spec)}"
756 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
757 to the assembler. It may be overridden by subtargets. */
758 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
759 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
761 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
764 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
765 the assembler. It may be overridden by subtargets. */
766 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
767 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
768 %{g} %{g0} %{g1} %{g2} %{g3} \
769 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
770 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
771 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
772 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
775 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
776 overridden by subtargets. */
778 #ifndef SUBTARGET_ASM_SPEC
779 #define SUBTARGET_ASM_SPEC ""
782 /* ASM_SPEC is the set of arguments to pass to the assembler. */
785 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
786 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
787 %(subtarget_asm_optimizing_spec) \
788 %(subtarget_asm_debugging_spec) \
790 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
792 %(subtarget_asm_spec)"
794 /* Specify to run a post-processor, mips-tfile after the assembler
795 has run to stuff the mips debug information into the object file.
796 This is needed because the $#!%^ MIPS assembler provides no way
797 of specifying such information in the assembly file. If we are
798 cross compiling, disable mips-tfile unless the user specifies
801 #ifndef ASM_FINAL_SPEC
802 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
804 #define ASM_FINAL_SPEC "\
805 %{mmips-as: %{!mno-mips-tfile: \
806 \n mips-tfile %{v*: -v} \
808 %{!K: %{save-temps: -I %b.o~}} \
809 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
810 %{.s:%i} %{!.s:%g.s}}}"
814 #define ASM_FINAL_SPEC "\
815 %{!mgas: %{!mno-mips-tfile: \
816 \n mips-tfile %{v*: -v} \
818 %{!K: %{save-temps: -I %b.o~}} \
819 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
820 %{.s:%i} %{!.s:%g.s}}}"
823 #endif /* ASM_FINAL_SPEC */
825 /* Redefinition of libraries used. Mips doesn't support normal
826 UNIX style profiling via calling _mcount. It does offer
827 profiling that samples the PC, so do what we can... */
830 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
833 /* Extra switches sometimes passed to the linker. */
834 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
835 will interpret it as a -b option. */
839 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
840 %{bestGnum} %{shared} %{non_shared} \
841 %(linker_endian_spec)"
842 #endif /* LINK_SPEC defined */
844 /* Specs for the compiler proper */
846 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
847 overridden by subtargets. */
848 #ifndef SUBTARGET_CC1_SPEC
849 #define SUBTARGET_CC1_SPEC ""
852 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
856 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
857 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
858 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
859 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
860 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
861 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
862 %{m4650:-mcpu=r4650} \
863 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
864 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
865 %{pic-none: -mno-half-pic} \
866 %{pic-lib: -mhalf-pic} \
867 %{pic-extern: -mhalf-pic} \
868 %{pic-calls: -mhalf-pic} \
870 %(subtarget_cc1_spec) "
873 /* Preprocessor specs. */
875 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
876 be overridden by subtargets. */
878 #ifndef SUBTARGET_CPP_SIZE_SPEC
879 #define SUBTARGET_CPP_SIZE_SPEC "\
880 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
881 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
884 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
885 overridden by subtargets. */
886 #ifndef SUBTARGET_CPP_SPEC
887 #define SUBTARGET_CPP_SPEC ""
890 /* If we're using 64bit longs, then we have to define __LONG_MAX__
891 correctly. Similarly for 64bit ints and __INT_MAX__. */
892 #ifndef LONG_MAX_SPEC
893 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
894 #define LONG_MAX_SPEC "%{!mno-long64:-D__LONG_MAX__=9223372036854775807L}"
896 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
900 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
904 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
905 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
906 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
907 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
908 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
909 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
910 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
911 %(subtarget_cpp_size_spec) \
912 %{mips3:-U__mips -D__mips=3 -D__mips64} \
913 %{mips4:-U__mips -D__mips=4 -D__mips64} \
914 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
915 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
916 %{m4650:%{!msoft-float:-D__mips_single_float}} \
917 %{msoft-float:-D__mips_soft_float} \
918 %{mabi=eabi:-D__mips_eabi} \
919 %{mips16:%{!mno-mips16:-D__mips16}} \
920 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
921 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
923 %(subtarget_cpp_spec) "
926 /* This macro defines names of additional specifications to put in the specs
927 that can be used in various specifications like CC1_SPEC. Its definition
928 is an initializer with a subgrouping for each command option.
930 Each subgrouping contains a string constant, that defines the
931 specification name, and a string constant that used by the GNU CC driver
934 Do not define this macro if it does not need to do anything. */
936 #define EXTRA_SPECS \
937 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
938 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
939 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
940 { "long_max_spec", LONG_MAX_SPEC }, \
941 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
942 { "gas_asm_spec", GAS_ASM_SPEC }, \
943 { "target_asm_spec", TARGET_ASM_SPEC }, \
944 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
945 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
946 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
947 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
948 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
949 SUBTARGET_EXTRA_SPECS
951 #ifndef SUBTARGET_EXTRA_SPECS
952 #define SUBTARGET_EXTRA_SPECS
955 /* If defined, this macro is an additional prefix to try after
956 `STANDARD_EXEC_PREFIX'. */
958 #ifndef MD_EXEC_PREFIX
959 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
962 #ifndef MD_STARTFILE_PREFIX
963 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
967 /* Print subsidiary information on the compiler version in use. */
969 #define MIPS_VERSION "[AL 1.1, MM 40]"
972 #define MACHINE_TYPE "BSD Mips"
975 #ifndef TARGET_VERSION_INTERNAL
976 #define TARGET_VERSION_INTERNAL(STREAM) \
977 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
980 #ifndef TARGET_VERSION
981 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
985 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
986 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
987 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
989 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
990 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
993 /* By default, turn on GDB extensions. */
994 #define DEFAULT_GDB_EXTENSIONS 1
996 /* If we are passing smuggling stabs through the MIPS ECOFF object
997 format, put a comment in front of the .stab<x> operation so
998 that the MIPS assembler does not choke. The mips-tfile program
999 will correctly put the stab into the object file. */
1001 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
1002 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
1003 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
1005 /* Local compiler-generated symbols must have a prefix that the assembler
1006 understands. By default, this is $, although some targets (e.g.,
1007 NetBSD-ELF) need to override this. */
1009 #ifndef LOCAL_LABEL_PREFIX
1010 #define LOCAL_LABEL_PREFIX "$"
1013 /* By default on the mips, external symbols do not have an underscore
1014 prepended, but some targets (e.g., NetBSD) require this. */
1016 #ifndef USER_LABEL_PREFIX
1017 #define USER_LABEL_PREFIX ""
1020 /* Forward references to tags are allowed. */
1021 #define SDB_ALLOW_FORWARD_REFERENCES
1023 /* Unknown tags are also allowed. */
1024 #define SDB_ALLOW_UNKNOWN_REFERENCES
1026 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1027 since the length can run past this up to a continuation point. */
1028 #define DBX_CONTIN_LENGTH 1500
1030 /* How to renumber registers for dbx and gdb. */
1031 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1033 /* The mapping from gcc register number to DWARF 2 CFA column number.
1034 This mapping does not allow for tracking register 0, since SGI's broken
1035 dwarf reader thinks column 0 is used for the frame address, but since
1036 register 0 is fixed this is not a problem. */
1037 #define DWARF_FRAME_REGNUM(REG) \
1038 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1040 /* The DWARF 2 CFA column which tracks the return address. */
1041 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1043 /* Before the prologue, RA lives in r31. */
1044 #define INCOMING_RETURN_ADDR_RTX gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
1046 /* Overrides for the COFF debug format. */
1047 #define PUT_SDB_SCL(a) \
1049 extern FILE *asm_out_text_file; \
1050 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1053 #define PUT_SDB_INT_VAL(a) \
1055 extern FILE *asm_out_text_file; \
1056 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1059 #define PUT_SDB_VAL(a) \
1061 extern FILE *asm_out_text_file; \
1062 fputs ("\t.val\t", asm_out_text_file); \
1063 output_addr_const (asm_out_text_file, (a)); \
1064 fputc (';', asm_out_text_file); \
1067 #define PUT_SDB_DEF(a) \
1069 extern FILE *asm_out_text_file; \
1070 fprintf (asm_out_text_file, "\t%s.def\t", \
1071 (TARGET_GAS) ? "" : "#"); \
1072 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1073 fputc (';', asm_out_text_file); \
1076 #define PUT_SDB_PLAIN_DEF(a) \
1078 extern FILE *asm_out_text_file; \
1079 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1080 (TARGET_GAS) ? "" : "#", (a)); \
1083 #define PUT_SDB_ENDEF \
1085 extern FILE *asm_out_text_file; \
1086 fprintf (asm_out_text_file, "\t.endef\n"); \
1089 #define PUT_SDB_TYPE(a) \
1091 extern FILE *asm_out_text_file; \
1092 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1095 #define PUT_SDB_SIZE(a) \
1097 extern FILE *asm_out_text_file; \
1098 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1101 #define PUT_SDB_DIM(a) \
1103 extern FILE *asm_out_text_file; \
1104 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1107 #ifndef PUT_SDB_START_DIM
1108 #define PUT_SDB_START_DIM \
1110 extern FILE *asm_out_text_file; \
1111 fprintf (asm_out_text_file, "\t.dim\t"); \
1115 #ifndef PUT_SDB_NEXT_DIM
1116 #define PUT_SDB_NEXT_DIM(a) \
1118 extern FILE *asm_out_text_file; \
1119 fprintf (asm_out_text_file, "%d,", a); \
1123 #ifndef PUT_SDB_LAST_DIM
1124 #define PUT_SDB_LAST_DIM(a) \
1126 extern FILE *asm_out_text_file; \
1127 fprintf (asm_out_text_file, "%d;", a); \
1131 #define PUT_SDB_TAG(a) \
1133 extern FILE *asm_out_text_file; \
1134 fprintf (asm_out_text_file, "\t.tag\t"); \
1135 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1136 fputc (';', asm_out_text_file); \
1139 /* For block start and end, we create labels, so that
1140 later we can figure out where the correct offset is.
1141 The normal .ent/.end serve well enough for functions,
1142 so those are just commented out. */
1144 #define PUT_SDB_BLOCK_START(LINE) \
1146 extern FILE *asm_out_text_file; \
1147 fprintf (asm_out_text_file, \
1148 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1149 LOCAL_LABEL_PREFIX, \
1151 (TARGET_GAS) ? "" : "#", \
1152 LOCAL_LABEL_PREFIX, \
1155 sdb_label_count++; \
1158 #define PUT_SDB_BLOCK_END(LINE) \
1160 extern FILE *asm_out_text_file; \
1161 fprintf (asm_out_text_file, \
1162 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1163 LOCAL_LABEL_PREFIX, \
1165 (TARGET_GAS) ? "" : "#", \
1166 LOCAL_LABEL_PREFIX, \
1169 sdb_label_count++; \
1172 #define PUT_SDB_FUNCTION_START(LINE)
1174 #define PUT_SDB_FUNCTION_END(LINE) \
1176 extern FILE *asm_out_text_file; \
1177 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1180 #define PUT_SDB_EPILOGUE_END(NAME)
1182 #define PUT_SDB_SRC_FILE(FILENAME) \
1184 extern FILE *asm_out_text_file; \
1185 output_file_directive (asm_out_text_file, (FILENAME)); \
1188 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1189 sprintf ((BUFFER), ".%dfake", (NUMBER));
1191 /* Correct the offset of automatic variables and arguments. Note that
1192 the MIPS debug format wants all automatic variables and arguments
1193 to be in terms of the virtual frame pointer (stack pointer before
1194 any adjustment in the function), while the MIPS 3.0 linker wants
1195 the frame pointer to be the stack pointer after the initial
1198 #define DEBUGGER_AUTO_OFFSET(X) mips_debugger_offset (X, 0)
1199 #define DEBUGGER_ARG_OFFSET(OFFSET, X) mips_debugger_offset (X, OFFSET)
1202 /* Tell collect that the object format is ECOFF */
1203 #ifndef OBJECT_FORMAT_ROSE
1204 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1205 #define EXTENDED_COFF /* ECOFF, not normal coff */
1208 #if 0 /* These definitions normally have no effect because
1209 MIPS systems define USE_COLLECT2, so
1210 assemble_constructor does nothing anyway. */
1212 /* Don't use the default definitions, because we don't have gld.
1213 Also, we don't want stabs when generating ECOFF output.
1214 Instead we depend on collect to handle these. */
1216 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1217 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1221 /* Target machine storage layout */
1223 /* Define in order to support both big and little endian float formats
1224 in the same gcc binary. */
1225 #define REAL_ARITHMETIC
1227 /* Define this if most significant bit is lowest numbered
1228 in instructions that operate on numbered bit-fields.
1230 #define BITS_BIG_ENDIAN 0
1232 /* Define this if most significant byte of a word is the lowest numbered. */
1233 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1235 /* Define this if most significant word of a multiword number is the lowest. */
1236 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1238 /* Define this to set the endianness to use in libgcc2.c, which can
1239 not depend on target_flags. */
1240 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1241 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1243 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1246 /* Number of bits in an addressable storage unit */
1247 #define BITS_PER_UNIT 8
1249 /* Width in bits of a "word", which is the contents of a machine register.
1250 Note that this is not necessarily the width of data type `int';
1251 if using 16-bit ints on a 68000, this would still be 32.
1252 But on a machine with 16-bit registers, this would be 16. */
1253 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1254 #define MAX_BITS_PER_WORD 64
1256 /* Width of a word, in units (bytes). */
1257 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1258 #define MIN_UNITS_PER_WORD 4
1260 /* For MIPS, width of a floating point register. */
1261 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1263 /* A C expression for the size in bits of the type `int' on the
1264 target machine. If you don't define this, the default is one
1266 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1267 #define MAX_INT_TYPE_SIZE 64
1269 /* Tell the preprocessor the maximum size of wchar_t. */
1270 #ifndef MAX_WCHAR_TYPE_SIZE
1271 #ifndef WCHAR_TYPE_SIZE
1272 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1276 /* A C expression for the size in bits of the type `short' on the
1277 target machine. If you don't define this, the default is half a
1278 word. (If this would be less than one storage unit, it is
1279 rounded up to one unit.) */
1280 #define SHORT_TYPE_SIZE 16
1282 /* A C expression for the size in bits of the type `long' on the
1283 target machine. If you don't define this, the default is one
1285 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1286 #define MAX_LONG_TYPE_SIZE 64
1288 /* A C expression for the size in bits of the type `long long' on the
1289 target machine. If you don't define this, the default is two
1291 #define LONG_LONG_TYPE_SIZE 64
1293 /* A C expression for the size in bits of the type `char' on the
1294 target machine. If you don't define this, the default is one
1295 quarter of a word. (If this would be less than one storage unit,
1296 it is rounded up to one unit.) */
1297 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1299 /* A C expression for the size in bits of the type `float' on the
1300 target machine. If you don't define this, the default is one
1302 #define FLOAT_TYPE_SIZE 32
1304 /* A C expression for the size in bits of the type `double' on the
1305 target machine. If you don't define this, the default is two
1307 #define DOUBLE_TYPE_SIZE 64
1309 /* A C expression for the size in bits of the type `long double' on
1310 the target machine. If you don't define this, the default is two
1312 #define LONG_DOUBLE_TYPE_SIZE 64
1314 /* Width in bits of a pointer.
1315 See also the macro `Pmode' defined below. */
1316 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1318 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1319 #define POINTER_BOUNDARY (TARGET_LONG64 ? 64 : 32)
1321 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1322 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1324 /* Allocation boundary (in *bits*) for the code of a function. */
1325 #define FUNCTION_BOUNDARY 32
1327 /* Alignment of field after `int : 0' in a structure. */
1328 #define EMPTY_FIELD_BOUNDARY 32
1330 /* Every structure's size must be a multiple of this. */
1331 /* 8 is observed right on a DECstation and on riscos 4.02. */
1332 #define STRUCTURE_SIZE_BOUNDARY 8
1334 /* There is no point aligning anything to a rounder boundary than this. */
1335 #define BIGGEST_ALIGNMENT 64
1337 /* Set this nonzero if move instructions will actually fail to work
1338 when given unaligned data. */
1339 #define STRICT_ALIGNMENT 1
1341 /* Define this if you wish to imitate the way many other C compilers
1342 handle alignment of bitfields and the structures that contain
1345 The behavior is that the type written for a bitfield (`int',
1346 `short', or other integer type) imposes an alignment for the
1347 entire structure, as if the structure really did contain an
1348 ordinary field of that type. In addition, the bitfield is placed
1349 within the structure so that it would fit within such a field,
1350 not crossing a boundary for it.
1352 Thus, on most machines, a bitfield whose type is written as `int'
1353 would not cross a four-byte boundary, and would force four-byte
1354 alignment for the whole structure. (The alignment used may not
1355 be four bytes; it is controlled by the other alignment
1358 If the macro is defined, its definition should be a C expression;
1359 a nonzero value for the expression enables this behavior. */
1361 #define PCC_BITFIELD_TYPE_MATTERS 1
1363 /* If defined, a C expression to compute the alignment given to a
1364 constant that is being placed in memory. CONSTANT is the constant
1365 and ALIGN is the alignment that the object would ordinarily have.
1366 The value of this macro is used instead of that alignment to align
1369 If this macro is not defined, then ALIGN is used.
1371 The typical use of this macro is to increase alignment for string
1372 constants to be word aligned so that `strcpy' calls that copy
1373 constants can be done inline. */
1375 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1376 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1377 && (ALIGN) < BITS_PER_WORD \
1381 /* If defined, a C expression to compute the alignment for a static
1382 variable. TYPE is the data type, and ALIGN is the alignment that
1383 the object would ordinarily have. The value of this macro is used
1384 instead of that alignment to align the object.
1386 If this macro is not defined, then ALIGN is used.
1388 One use of this macro is to increase alignment of medium-size
1389 data to make it all fit in fewer cache lines. Another is to
1390 cause character arrays to be word-aligned so that `strcpy' calls
1391 that copy constants to character arrays can be done inline. */
1393 #undef DATA_ALIGNMENT
1394 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1395 ((((ALIGN) < BITS_PER_WORD) \
1396 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1397 || TREE_CODE (TYPE) == UNION_TYPE \
1398 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1400 /* Define this macro if an argument declared as `char' or `short' in a
1401 prototype should actually be passed as an `int'. In addition to
1402 avoiding errors in certain cases of mismatch, it also makes for
1403 better code on certain machines. */
1405 #define PROMOTE_PROTOTYPES
1407 /* Define if operations between registers always perform the operation
1408 on the full register even if a narrower mode is specified. */
1409 #define WORD_REGISTER_OPERATIONS
1411 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1412 will either zero-extend or sign-extend. The value of this macro should
1413 be the code that says which one of the two operations is implicitly
1414 done, NIL if none. */
1415 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1417 /* Define this macro if it is advisable to hold scalars in registers
1418 in a wider mode than that declared by the program. In such cases,
1419 the value is constrained to be within the bounds of the declared
1420 type, but kept valid in the wider mode. The signedness of the
1421 extension may differ from that of the type.
1423 We promote any value smaller than SImode up to SImode. We don't
1424 want to promote to DImode when in 64 bit mode, because that would
1425 prevent us from using the faster SImode multiply and divide
1428 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1429 if (GET_MODE_CLASS (MODE) == MODE_INT \
1430 && GET_MODE_SIZE (MODE) < 4) \
1433 /* Define this if function arguments should also be promoted using the above
1436 #define PROMOTE_FUNCTION_ARGS
1438 /* Likewise, if the function return value is promoted. */
1440 #define PROMOTE_FUNCTION_RETURN
1442 /* Standard register usage. */
1444 /* Number of actual hardware registers.
1445 The hardware registers are assigned numbers for the compiler
1446 from 0 to just below FIRST_PSEUDO_REGISTER.
1447 All registers that the compiler knows about must be given numbers,
1448 even those that are not normally considered general registers.
1450 On the Mips, we have 32 integer registers, 32 floating point
1451 registers, 8 condition code registers, and the special registers
1452 hi, lo, hilo, and rap. The 8 condition code registers are only
1453 used if mips_isa >= 4. The hilo register is only used in 64 bit
1454 mode. It represents a 64 bit value stored as two 32 bit values in
1455 the hi and lo registers; this is the result of the mult
1456 instruction. rap is a pointer to the stack where the return
1457 address reg ($31) was stored. This is needed for C++ exception
1460 #define FIRST_PSEUDO_REGISTER 76
1462 /* 1 for registers that have pervasive standard uses
1463 and are not available for the register allocator.
1465 On the MIPS, see conventions, page D-2 */
1467 #define FIXED_REGISTERS \
1469 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1470 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1471 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1472 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1473 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1477 /* 1 for registers not available across function calls.
1478 These must include the FIXED_REGISTERS and also any
1479 registers that can be used without being saved.
1480 The latter must include the registers where values are returned
1481 and the register where structure-value addresses are passed.
1482 Aside from that, you can include as many other registers as you like. */
1484 #define CALL_USED_REGISTERS \
1486 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1487 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1488 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1489 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1490 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1494 /* Internal macros to classify a register number as to whether it's a
1495 general purpose register, a floating point register, a
1496 multiply/divide register, or a status register. */
1498 #define GP_REG_FIRST 0
1499 #define GP_REG_LAST 31
1500 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1501 #define GP_DBX_FIRST 0
1503 #define FP_REG_FIRST 32
1504 #define FP_REG_LAST 63
1505 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1506 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1508 #define MD_REG_FIRST 64
1509 #define MD_REG_LAST 66
1510 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1512 #define ST_REG_FIRST 67
1513 #define ST_REG_LAST 74
1514 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1516 #define RAP_REG_NUM 75
1518 #define AT_REGNUM (GP_REG_FIRST + 1)
1519 #define HI_REGNUM (MD_REG_FIRST + 0)
1520 #define LO_REGNUM (MD_REG_FIRST + 1)
1521 #define HILO_REGNUM (MD_REG_FIRST + 2)
1523 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1524 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1525 should be used instead. */
1526 #define FPSW_REGNUM ST_REG_FIRST
1528 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1529 #define M16_REG_P(REGNO) \
1530 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1531 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1532 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1533 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1535 /* Return number of consecutive hard regs needed starting at reg REGNO
1536 to hold something of mode MODE.
1537 This is ordinarily the length in words of a value of mode MODE
1538 but can be less for certain modes in special long registers.
1540 On the MIPS, all general registers are one word long. Except on
1541 the R4000 with the FR bit set, the floating point uses register
1542 pairs, with the second register not being allocable. */
1544 #define HARD_REGNO_NREGS(REGNO, MODE) \
1545 (! FP_REG_P (REGNO) \
1546 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1547 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1549 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1550 MODE. In 32 bit mode, require that DImode and DFmode be in even
1551 registers. For DImode, this makes some of the insns easier to
1552 write, since you don't have to worry about a DImode value in
1553 registers 3 & 4, producing a result in 4 & 5.
1555 To make the code simpler HARD_REGNO_MODE_OK now just references an
1556 array built in override_options. Because machmodes.h is not yet
1557 included before this file is processed, the MODE bound can't be
1560 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1562 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1563 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1565 /* Value is 1 if it is a good idea to tie two pseudo registers
1566 when one has mode MODE1 and one has mode MODE2.
1567 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1568 for any hard reg, then this must be 0 for correct output. */
1569 #define MODES_TIEABLE_P(MODE1, MODE2) \
1570 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1571 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1572 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1573 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1575 /* MIPS pc is not overloaded on a register. */
1576 /* #define PC_REGNUM xx */
1578 /* Register to use for pushing function arguments. */
1579 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1581 /* Offset from the stack pointer to the first available location. Use
1582 the default value zero. */
1583 /* #define STACK_POINTER_OFFSET 0 */
1585 /* Base register for access to local variables of the function. We
1586 pretend that the frame pointer is $1, and then eliminate it to
1587 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1588 a fixed register, and will not be used for anything else. */
1589 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1591 /* $30 is not available on the mips16, so we use $17 as the frame
1593 #define HARD_FRAME_POINTER_REGNUM \
1594 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1596 /* Value should be nonzero if functions must have frame pointers.
1597 Zero means the frame pointer need not be set up (and parms
1598 may be accessed via the stack pointer) in functions that seem suitable.
1599 This is computed in `reload', in reload1.c. */
1600 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1602 /* Base register for access to arguments of the function. */
1603 #define ARG_POINTER_REGNUM GP_REG_FIRST
1605 /* Fake register that holds the address on the stack of the
1606 current function's return address. */
1607 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1609 /* Register in which static-chain is passed to a function. */
1610 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1612 /* If the structure value address is passed in a register, then
1613 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1614 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1616 /* If the structure value address is not passed in a register, define
1617 `STRUCT_VALUE' as an expression returning an RTX for the place
1618 where the address is passed. If it returns 0, the address is
1619 passed as an "invisible" first argument. */
1620 #define STRUCT_VALUE 0
1622 /* Mips registers used in prologue/epilogue code when the stack frame
1623 is larger than 32K bytes. These registers must come from the
1624 scratch register set, and not used for passing and returning
1625 arguments and any other information used in the calling sequence
1626 (such as pic). Must start at 12, since t0/t3 are parameter passing
1627 registers in the 64 bit ABI. */
1629 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1630 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1632 /* Define this macro if it is as good or better to call a constant
1633 function address than to call an address kept in a register. */
1634 #define NO_FUNCTION_CSE 1
1636 /* Define this macro if it is as good or better for a function to
1637 call itself with an explicit address than to call an address
1638 kept in a register. */
1639 #define NO_RECURSIVE_FUNCTION_CSE 1
1641 /* The register number of the register used to address a table of
1642 static data addresses in memory. In some cases this register is
1643 defined by a processor's "application binary interface" (ABI).
1644 When this macro is defined, RTL is generated for this register
1645 once, as with the stack pointer and frame pointer registers. If
1646 this macro is not defined, it is up to the machine-dependent
1647 files to allocate such a register (if necessary). */
1648 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1650 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1652 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1653 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1654 isn't always called for static inline functions. */
1655 #define INIT_EXPANDERS \
1657 embedded_pic_fnaddr_rtx = NULL; \
1658 mips16_gp_pseudo_rtx = NULL; \
1661 /* Define the classes of registers for register constraints in the
1662 machine description. Also define ranges of constants.
1664 One of the classes must always be named ALL_REGS and include all hard regs.
1665 If there is more than one class, another class must be named NO_REGS
1666 and contain no registers.
1668 The name GENERAL_REGS must be the name of a class (or an alias for
1669 another name such as ALL_REGS). This is the class of registers
1670 that is allowed by "g" or "r" in a register constraint.
1671 Also, registers outside this class are allocated only when
1672 instructions express preferences for them.
1674 The classes must be numbered in nondecreasing order; that is,
1675 a larger-numbered class must never be contained completely
1676 in a smaller-numbered class.
1678 For any two classes, it is very desirable that there be another
1679 class that represents their union. */
1683 NO_REGS, /* no registers in set */
1684 M16_NA_REGS, /* mips16 regs not used to pass args */
1685 M16_REGS, /* mips16 directly accessible registers */
1686 T_REG, /* mips16 T register ($24) */
1687 M16_T_REGS, /* mips16 registers plus T register */
1688 GR_REGS, /* integer registers */
1689 FP_REGS, /* floating point registers */
1690 HI_REG, /* hi register */
1691 LO_REG, /* lo register */
1692 HILO_REG, /* hilo register pair for 64 bit mode mult */
1693 MD_REGS, /* multiply/divide registers (hi/lo) */
1694 ST_REGS, /* status registers (fp status) */
1695 ALL_REGS, /* all registers */
1696 LIM_REG_CLASSES /* max value + 1 */
1699 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1701 #define GENERAL_REGS GR_REGS
1703 /* An initializer containing the names of the register classes as C
1704 string constants. These names are used in writing some of the
1707 #define REG_CLASS_NAMES \
1724 /* An initializer containing the contents of the register classes,
1725 as integers which are bit masks. The Nth integer specifies the
1726 contents of class N. The way the integer MASK is interpreted is
1727 that register R is in the class if `MASK & (1 << R)' is 1.
1729 When the machine has more than 32 registers, an integer does not
1730 suffice. Then the integers are replaced by sub-initializers,
1731 braced groupings containing several integers. Each
1732 sub-initializer must be suitable as an initializer for the type
1733 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1735 #define REG_CLASS_CONTENTS \
1737 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1738 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1739 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1740 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1741 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1742 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1743 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1744 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1745 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1746 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1747 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1748 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1749 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1753 /* A C expression whose value is a register class containing hard
1754 register REGNO. In general there is more that one such class;
1755 choose a class which is "minimal", meaning that no smaller class
1756 also contains the register. */
1758 extern enum reg_class mips_regno_to_class[];
1760 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1762 /* A macro whose definition is the name of the class to which a
1763 valid base register must belong. A base register is one used in
1764 an address which is the register value plus a displacement. */
1766 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1768 /* A macro whose definition is the name of the class to which a
1769 valid index register must belong. An index register is one used
1770 in an address where its value is either multiplied by a scale
1771 factor or added to another register (as well as added to a
1774 #define INDEX_REG_CLASS NO_REGS
1776 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1777 registers explicitly used in the rtl to be used as spill registers
1778 but prevents the compiler from extending the lifetime of these
1781 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1783 /* This macro is used later on in the file. */
1784 #define GR_REG_CLASS_P(CLASS) \
1785 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1786 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1788 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1789 is the default value (allocate the registers in numeric order). We
1790 define it just so that we can override it for the mips16 target in
1791 ORDER_REGS_FOR_LOCAL_ALLOC. */
1793 #define REG_ALLOC_ORDER \
1794 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1795 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1796 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1797 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1798 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1801 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1802 to be rearranged based on a particular function. On the mips16, we
1803 want to allocate $24 (T_REG) before other registers for
1804 instructions for which it is possible. */
1806 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1808 /* REGISTER AND CONSTANT CLASSES */
1810 /* Get reg_class from a letter such as appears in the machine
1813 DEFINED REGISTER CLASSES:
1815 'd' General (aka integer) registers
1816 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1817 'y' General registers (in both mips16 and non mips16 mode)
1818 'e' mips16 non argument registers (M16_NA_REGS)
1819 't' mips16 temporary register ($24)
1820 'f' Floating point registers
1823 'x' Multiply/divide registers
1825 'z' FP Status register
1826 'b' All registers */
1828 extern enum reg_class mips_char_to_class[];
1830 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1832 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1833 string can be used to stand for particular ranges of immediate
1834 operands. This macro defines what the ranges are. C is the
1835 letter, and VALUE is a constant value. Return 1 if VALUE is
1836 in the range specified by C. */
1840 `I' is used for the range of constants an arithmetic insn can
1841 actually contain (16 bits signed integers).
1843 `J' is used for the range which is just zero (ie, $r0).
1845 `K' is used for the range of constants a logical insn can actually
1846 contain (16 bit zero-extended integers).
1848 `L' is used for the range of constants that be loaded with lui
1849 (ie, the bottom 16 bits are zero).
1851 `M' is used for the range of constants that take two words to load
1852 (ie, not matched by `I', `K', and `L').
1854 `N' is used for negative 16 bit constants other than -65536.
1856 `O' is a 15 bit signed integer.
1858 `P' is used for positive 16 bit constants. */
1860 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1861 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1863 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1864 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1865 : (C) == 'J' ? ((VALUE) == 0) \
1866 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1867 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1868 && (((VALUE) & ~2147483647) == 0 \
1869 || ((VALUE) & ~2147483647) == ~2147483647)) \
1870 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1871 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1872 && (((VALUE) & 0x0000ffff) != 0 \
1873 || (((VALUE) & ~2147483647) != 0 \
1874 && ((VALUE) & ~2147483647) != ~2147483647))) \
1875 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1876 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1877 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1880 /* Similar, but for floating constants, and defining letters G and H.
1881 Here VALUE is the CONST_DOUBLE rtx itself. */
1885 'G' : Floating point 0 */
1887 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1889 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1891 /* Letters in the range `Q' through `U' may be defined in a
1892 machine-dependent fashion to stand for arbitrary operand types.
1893 The machine description macro `EXTRA_CONSTRAINT' is passed the
1894 operand as its first argument and the constraint letter as its
1897 `Q' is for mips16 GP relative constants
1898 `R' is for memory references which take 1 word for the instruction.
1899 `S' is for references to extern items which are PIC for OSF/rose.
1900 `T' is for memory addresses that can be used to load two words. */
1902 #define EXTRA_CONSTRAINT(OP,CODE) \
1903 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
1904 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
1905 && mips16_gp_offset_p (OP)) \
1906 : (GET_CODE (OP) != MEM) ? FALSE \
1907 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1908 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1909 && HALF_PIC_ADDRESS_P (OP)) \
1912 /* Given an rtx X being reloaded into a reg required to be
1913 in class CLASS, return the class of reg to actually use.
1914 In general this is just CLASS; but on some machines
1915 in some cases it is preferable to use a more restrictive class. */
1917 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1918 ((CLASS) != ALL_REGS \
1919 ? (! TARGET_MIPS16 \
1921 : ((CLASS) != GR_REGS \
1924 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1925 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1926 ? (TARGET_SOFT_FLOAT \
1927 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1929 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1930 || GET_MODE (X) == VOIDmode) \
1931 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1934 /* Certain machines have the property that some registers cannot be
1935 copied to some other registers without using memory. Define this
1936 macro on those machines to be a C expression that is non-zero if
1937 objects of mode MODE in registers of CLASS1 can only be copied to
1938 registers of class CLASS2 by storing a register of CLASS1 into
1939 memory and loading that memory location into a register of CLASS2.
1941 Do not define this macro if its value would always be zero. */
1943 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1944 ((!TARGET_DEBUG_H_MODE \
1945 && GET_MODE_CLASS (MODE) == MODE_INT \
1946 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1947 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1948 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1949 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1950 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1952 /* The HI and LO registers can only be reloaded via the general
1953 registers. Condition code registers can only be loaded to the
1954 general registers, and from the floating point registers. */
1956 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1957 mips_secondary_reload_class (CLASS, MODE, X, 1)
1958 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1959 mips_secondary_reload_class (CLASS, MODE, X, 0)
1961 /* Not declared above, with the other functions, because enum
1962 reg_class is not declared yet. */
1963 extern enum reg_class mips_secondary_reload_class ();
1965 /* Return the maximum number of consecutive registers
1966 needed to represent mode MODE in a register of class CLASS. */
1968 #define CLASS_UNITS(mode, size) \
1969 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1971 #define CLASS_MAX_NREGS(CLASS, MODE) \
1972 ((CLASS) == FP_REGS \
1974 ? CLASS_UNITS (MODE, 8) \
1975 : 2 * CLASS_UNITS (MODE, 8)) \
1976 : CLASS_UNITS (MODE, UNITS_PER_WORD))
1978 /* If defined, this is a C expression whose value should be
1979 nonzero if the insn INSN has the effect of mysteriously
1980 clobbering the contents of hard register number REGNO. By
1981 "mysterious" we mean that the insn's RTL expression doesn't
1982 describe such an effect.
1984 If this macro is not defined, it means that no insn clobbers
1985 registers mysteriously. This is the usual situation; all else
1986 being equal, it is best for the RTL expression to show all the
1989 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
1992 /* Stack layout; function entry, exit and calling. */
1994 /* Define this if pushing a word on the stack
1995 makes the stack pointer a smaller address. */
1996 #define STACK_GROWS_DOWNWARD
1998 /* Define this if the nominal address of the stack frame
1999 is at the high-address end of the local variables;
2000 that is, each additional local variable allocated
2001 goes at a more negative offset in the frame. */
2002 /* #define FRAME_GROWS_DOWNWARD */
2004 /* Offset within stack frame to start allocating local variables at.
2005 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2006 first local allocated. Otherwise, it is the offset to the BEGINNING
2007 of the first local allocated. */
2008 #define STARTING_FRAME_OFFSET \
2009 (current_function_outgoing_args_size \
2010 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2012 /* Offset from the stack pointer register to an item dynamically
2013 allocated on the stack, e.g., by `alloca'.
2015 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2016 length of the outgoing arguments. The default is correct for most
2017 machines. See `function.c' for details.
2019 The MIPS ABI states that functions which dynamically allocate the
2020 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2021 we are trying to create a second frame pointer to the function, so
2022 allocate some stack space to make it happy.
2024 However, the linker currently complains about linking any code that
2025 dynamically allocates stack space, and there seems to be a bug in
2026 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2029 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2030 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2031 ? 4*UNITS_PER_WORD \
2032 : current_function_outgoing_args_size)
2035 /* The return address for the current frame is in r31 is this is a leaf
2036 function. Otherwise, it is on the stack. It is at a variable offset
2037 from sp/fp/ap, so we define a fake hard register rap which is a
2038 poiner to the return address on the stack. This always gets eliminated
2039 during reload to be either the frame pointer or the stack pointer plus
2042 /* ??? This definition fails for leaf functions. There is currently no
2043 general solution for this problem. */
2045 /* ??? There appears to be no way to get the return address of any previous
2046 frame except by disassembling instructions in the prologue/epilogue.
2047 So currently we support only the current frame. */
2049 #define RETURN_ADDR_RTX(count, frame) \
2051 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2054 /* Structure to be filled in by compute_frame_size with register
2055 save masks, and offsets for the current function. */
2057 struct mips_frame_info
2059 long total_size; /* # bytes that the entire frame takes up */
2060 long var_size; /* # bytes that variables take up */
2061 long args_size; /* # bytes that outgoing arguments take up */
2062 long extra_size; /* # bytes of extra gunk */
2063 int gp_reg_size; /* # bytes needed to store gp regs */
2064 int fp_reg_size; /* # bytes needed to store fp regs */
2065 long mask; /* mask of saved gp registers */
2066 long fmask; /* mask of saved fp registers */
2067 long gp_save_offset; /* offset from vfp to store gp registers */
2068 long fp_save_offset; /* offset from vfp to store fp registers */
2069 long gp_sp_offset; /* offset from new sp to store gp registers */
2070 long fp_sp_offset; /* offset from new sp to store fp registers */
2071 int initialized; /* != 0 if frame size already calculated */
2072 int num_gp; /* number of gp registers saved */
2073 int num_fp; /* number of fp registers saved */
2074 long insns_len; /* length of insns; mips16 only */
2077 extern struct mips_frame_info current_frame_info;
2079 /* If defined, this macro specifies a table of register pairs used to
2080 eliminate unneeded registers that point into the stack frame. If
2081 it is not defined, the only elimination attempted by the compiler
2082 is to replace references to the frame pointer with references to
2085 The definition of this macro is a list of structure
2086 initializations, each of which specifies an original and
2087 replacement register.
2089 On some machines, the position of the argument pointer is not
2090 known until the compilation is completed. In such a case, a
2091 separate hard register must be used for the argument pointer.
2092 This register can be eliminated by replacing it with either the
2093 frame pointer or the argument pointer, depending on whether or not
2094 the frame pointer has been eliminated.
2096 In this case, you might specify:
2097 #define ELIMINABLE_REGS \
2098 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2099 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2100 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2102 Note that the elimination of the argument pointer with the stack
2103 pointer is specified first since that is the preferred elimination.
2105 The eliminations to $17 are only used on the mips16. See the
2106 definition of HARD_FRAME_POINTER_REGNUM. */
2108 #define ELIMINABLE_REGS \
2109 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2110 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2111 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2112 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2113 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2114 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2115 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2116 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2117 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2119 /* A C expression that returns non-zero if the compiler is allowed to
2120 try to replace register number FROM-REG with register number
2121 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2122 defined, and will usually be the constant 1, since most of the
2123 cases preventing register elimination are things that the compiler
2124 already knows about.
2126 When not in mips16 and mips64, we can always eliminate to the
2127 frame pointer. We can eliminate to the stack pointer unless
2128 a frame pointer is needed. In mips16 mode, we need a frame
2129 pointer for a large frame; otherwise, reload may be unable
2130 to compute the address of a local variable, since there is
2131 no way to add a large constant to the stack pointer
2132 without using a temporary register.
2134 In mips16, for some instructions (eg lwu), we can't eliminate the
2135 frame pointer for the stack pointer. These instructions are
2136 only generated in TARGET_64BIT mode.
2139 #define CAN_ELIMINATE(FROM, TO) \
2140 ((TO) == HARD_FRAME_POINTER_REGNUM \
2141 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2142 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2143 && (! TARGET_MIPS16 \
2144 || compute_frame_size (get_frame_size ()) < 32768)))
2146 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2147 specifies the initial difference between the specified pair of
2148 registers. This macro must be defined if `ELIMINABLE_REGS' is
2151 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2152 { compute_frame_size (get_frame_size ()); \
2153 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2154 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2155 (OFFSET) = - current_function_outgoing_args_size; \
2156 else if ((FROM) == FRAME_POINTER_REGNUM) \
2158 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2159 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2160 (OFFSET) = (current_frame_info.total_size \
2161 - current_function_outgoing_args_size \
2162 - ((mips_abi != ABI_32 && mips_abi != ABI_EABI) \
2163 ? current_function_pretend_args_size \
2165 else if ((FROM) == ARG_POINTER_REGNUM) \
2166 (OFFSET) = (current_frame_info.total_size \
2167 - ((mips_abi != ABI_32 && mips_abi != ABI_EABI) \
2168 ? current_function_pretend_args_size \
2170 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2171 so we must add 4 bytes to the offset to get the right value. */ \
2172 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2173 (OFFSET) = current_frame_info.gp_sp_offset \
2174 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2175 * (BYTES_BIG_ENDIAN != 0)); \
2178 /* If we generate an insn to push BYTES bytes,
2179 this says how many the stack pointer really advances by.
2180 On the vax, sp@- in a byte insn really pushes a word. */
2182 /* #define PUSH_ROUNDING(BYTES) 0 */
2184 /* If defined, the maximum amount of space required for outgoing
2185 arguments will be computed and placed into the variable
2186 `current_function_outgoing_args_size'. No space will be pushed
2187 onto the stack for each call; instead, the function prologue
2188 should increase the stack frame size by this amount.
2190 It is not proper to define both `PUSH_ROUNDING' and
2191 `ACCUMULATE_OUTGOING_ARGS'. */
2192 #define ACCUMULATE_OUTGOING_ARGS
2194 /* Offset from the argument pointer register to the first argument's
2195 address. On some machines it may depend on the data type of the
2198 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2199 the first argument's address.
2201 On the MIPS, we must skip the first argument position if we are
2202 returning a structure or a union, to account for its address being
2203 passed in $4. However, at the current time, this produces a compiler
2204 that can't bootstrap, so comment it out for now. */
2207 #define FIRST_PARM_OFFSET(FNDECL) \
2209 && TREE_TYPE (FNDECL) != 0 \
2210 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2211 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2212 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2216 #define FIRST_PARM_OFFSET(FNDECL) 0
2219 /* When a parameter is passed in a register, stack space is still
2220 allocated for it. For the MIPS, stack space must be allocated, cf
2221 Asm Lang Prog Guide page 7-8.
2223 BEWARE that some space is also allocated for non existing arguments
2224 in register. In case an argument list is of form GF used registers
2225 are a0 (a2,a3), but we should push over a1... */
2227 #define REG_PARM_STACK_SPACE(FNDECL) \
2228 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2230 /* Define this if it is the responsibility of the caller to
2231 allocate the area reserved for arguments passed in registers.
2232 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2233 of this macro is to determine whether the space is included in
2234 `current_function_outgoing_args_size'. */
2235 #define OUTGOING_REG_PARM_STACK_SPACE
2237 /* Align stack frames on 64 bits (Double Word ). */
2238 #define STACK_BOUNDARY 64
2240 /* Make sure 4 words are always allocated on the stack. */
2242 #ifndef STACK_ARGS_ADJUST
2243 #define STACK_ARGS_ADJUST(SIZE) \
2245 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2246 SIZE.constant = 4 * UNITS_PER_WORD; \
2251 /* A C expression that should indicate the number of bytes of its
2252 own arguments that a function function pops on returning, or 0
2253 if the function pops no arguments and the caller must therefore
2254 pop them all after the function returns.
2256 FUNDECL is the declaration node of the function (as a tree).
2258 FUNTYPE is a C variable whose value is a tree node that
2259 describes the function in question. Normally it is a node of
2260 type `FUNCTION_TYPE' that describes the data type of the function.
2261 From this it is possible to obtain the data types of the value
2262 and arguments (if known).
2264 When a call to a library function is being considered, FUNTYPE
2265 will contain an identifier node for the library function. Thus,
2266 if you need to distinguish among various library functions, you
2267 can do so by their names. Note that "library function" in this
2268 context means a function used to perform arithmetic, whose name
2269 is known specially in the compiler and was not mentioned in the
2270 C code being compiled.
2272 STACK-SIZE is the number of bytes of arguments passed on the
2273 stack. If a variable number of bytes is passed, it is zero, and
2274 argument popping will always be the responsibility of the
2275 calling function. */
2277 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2280 /* Symbolic macros for the registers used to return integer and floating
2283 #define GP_RETURN (GP_REG_FIRST + 2)
2284 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2286 /* Symbolic macros for the first/last argument registers. */
2288 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2289 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2290 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2291 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2293 #define MAX_ARGS_IN_REGISTERS 4
2295 /* Define how to find the value returned by a library function
2296 assuming the value has mode MODE. Because we define
2297 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2298 PROMOTE_MODE does. */
2300 #define LIBCALL_VALUE(MODE) \
2302 ((GET_MODE_CLASS (MODE) != MODE_INT \
2303 || GET_MODE_SIZE (MODE) >= 4) \
2306 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2307 && (! TARGET_SINGLE_FLOAT \
2308 || GET_MODE_SIZE (MODE) <= 4)) \
2312 /* Define how to find the value returned by a function.
2313 VALTYPE is the data type of the value (as a tree).
2314 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2315 otherwise, FUNC is 0. */
2317 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2320 /* 1 if N is a possible register number for a function value.
2321 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2322 Currently, R2 and F0 are only implemented here (C has no complex type) */
2324 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2326 /* 1 if N is a possible register number for function argument passing.
2327 We have no FP argument registers when soft-float. When FP registers
2328 are 32 bits, we can't directly reference the odd numbered ones. */
2330 #define FUNCTION_ARG_REGNO_P(N) \
2331 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2332 || ((! TARGET_SOFT_FLOAT \
2333 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2334 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2335 && ! fixed_regs[N]))
2337 /* A C expression which can inhibit the returning of certain function
2338 values in registers, based on the type of value. A nonzero value says
2339 to return the function value in memory, just as large structures are
2340 always returned. Here TYPE will be a C expression of type
2341 `tree', representing the data type of the value.
2343 Note that values of mode `BLKmode' must be explicitly
2344 handled by this macro. Also, the option `-fpcc-struct-return'
2345 takes effect regardless of this macro. On most systems, it is
2346 possible to leave the macro undefined; this causes a default
2347 definition to be used, whose value is the constant 1 for BLKmode
2348 values, and 0 otherwise.
2350 GCC normally converts 1 byte structures into chars, 2 byte
2351 structs into shorts, and 4 byte structs into ints, and returns
2352 them this way. Defining the following macro overrides this,
2353 to give us MIPS cc compatibility. */
2355 #define RETURN_IN_MEMORY(TYPE) \
2356 (TYPE_MODE (TYPE) == BLKmode)
2358 /* A code distinguishing the floating point format of the target
2359 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2360 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2362 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2365 /* Define a data type for recording info about an argument list
2366 during the scan of that argument list. This data type should
2367 hold all necessary information about the function itself
2368 and about the args processed so far, enough to enable macros
2369 such as FUNCTION_ARG to determine where the next arg should go.
2371 On the mips16, we need to keep track of which floating point
2372 arguments were passed in general registers, but would have been
2373 passed in the FP regs if this were a 32 bit function, so that we
2374 can move them to the FP regs if we wind up calling a 32 bit
2375 function. We record this information in fp_code, encoded in base
2376 four. A zero digit means no floating point argument, a one digit
2377 means an SFmode argument, and a two digit means a DFmode argument,
2378 and a three digit is not used. The low order digit is the first
2379 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2380 an SFmode argument. ??? A more sophisticated approach will be
2381 needed if MIPS_ABI != ABI_32. */
2383 typedef struct mips_args {
2384 int gp_reg_found; /* whether a gp register was found yet */
2385 int arg_number; /* argument number */
2386 int arg_words; /* # total words the arguments take */
2387 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2388 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2389 int fp_code; /* Mode of FP arguments (mips16) */
2390 int num_adjusts; /* number of adjustments made */
2391 /* Adjustments made to args pass in regs. */
2392 /* ??? The size is doubled to work around a
2393 bug in the code that sets the adjustments
2395 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2398 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2399 for a call to a function whose data type is FNTYPE.
2400 For a library call, FNTYPE is 0.
2404 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2405 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2407 /* Update the data in CUM to advance over an argument
2408 of mode MODE and data type TYPE.
2409 (TYPE is null for libcalls where that information may not be available.) */
2411 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2412 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2414 /* Determine where to put an argument to a function.
2415 Value is zero to push the argument on the stack,
2416 or a hard register in which to store the argument.
2418 MODE is the argument's machine mode.
2419 TYPE is the data type of the argument (as a tree).
2420 This is null for libcalls where that information may
2422 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2423 the preceding args and about the function being called.
2424 NAMED is nonzero if this argument is a named parameter
2425 (otherwise it is an extra parameter matching an ellipsis). */
2427 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2428 function_arg( &CUM, MODE, TYPE, NAMED)
2430 /* For an arg passed partly in registers and partly in memory,
2431 this is the number of registers used.
2432 For args passed entirely in registers or entirely in memory, zero. */
2434 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2435 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2437 /* If defined, a C expression that gives the alignment boundary, in
2438 bits, of an argument with the specified mode and type. If it is
2439 not defined, `PARM_BOUNDARY' is used for all arguments. */
2441 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2443 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2445 : TYPE_ALIGN(TYPE)) \
2446 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2448 : GET_MODE_ALIGNMENT(MODE)))
2451 /* This macro generates the assembly code for function entry.
2452 FILE is a stdio stream to output the code to.
2453 SIZE is an int: how many units of temporary storage to allocate.
2454 Refer to the array `regs_ever_live' to determine which registers
2455 to save; `regs_ever_live[I]' is nonzero if register number I
2456 is ever used in the function. This macro is responsible for
2457 knowing which registers should not be saved even if used. */
2459 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2461 /* This macro generates the assembly code for function exit,
2462 on machines that need it. If FUNCTION_EPILOGUE is not defined
2463 then individual return instructions are generated for each
2464 return statement. Args are same as for FUNCTION_PROLOGUE. */
2466 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2468 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2470 #define MUST_SAVE_REGISTER(regno) \
2471 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2472 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2473 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2475 /* ALIGN FRAMES on double word boundaries */
2477 #define MIPS_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
2480 /* Output assembler code to FILE to increment profiler label # LABELNO
2481 for profiling a function entry. */
2483 #define FUNCTION_PROFILER(FILE, LABELNO) \
2485 if (TARGET_MIPS16) \
2486 sorry ("mips16 function profiling"); \
2487 fprintf (FILE, "\t.set\tnoreorder\n"); \
2488 fprintf (FILE, "\t.set\tnoat\n"); \
2489 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2490 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2491 fprintf (FILE, "\tjal\t_mcount\n"); \
2493 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2494 TARGET_64BIT ? "dsubu" : "subu", \
2495 reg_names[STACK_POINTER_REGNUM], \
2496 reg_names[STACK_POINTER_REGNUM], \
2497 TARGET_LONG64 ? 16 : 8); \
2498 fprintf (FILE, "\t.set\treorder\n"); \
2499 fprintf (FILE, "\t.set\tat\n"); \
2502 /* Define this macro if the code for function profiling should come
2503 before the function prologue. Normally, the profiling code comes
2506 /* #define PROFILE_BEFORE_PROLOGUE */
2508 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2509 the stack pointer does not matter. The value is tested only in
2510 functions that have frame pointers.
2511 No definition is equivalent to always zero. */
2513 #define EXIT_IGNORE_STACK 1
2516 /* A C statement to output, on the stream FILE, assembler code for a
2517 block of data that contains the constant parts of a trampoline.
2518 This code should not include a label--the label is taken care of
2521 #define TRAMPOLINE_TEMPLATE(STREAM) \
2523 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2524 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2525 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2526 if (TARGET_LONG64) \
2528 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2529 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2533 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2534 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2536 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2537 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2538 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2539 if (TARGET_LONG64) \
2541 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2542 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2546 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2547 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2551 /* A C expression for the size in bytes of the trampoline, as an
2554 #define TRAMPOLINE_SIZE (32 + (TARGET_LONG64 ? 16 : 8))
2556 /* Alignment required for trampolines, in bits. */
2558 #define TRAMPOLINE_ALIGNMENT (TARGET_LONG64 ? 64 : 32)
2560 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2561 program and data caches. */
2563 #ifndef CACHE_FLUSH_FUNC
2564 #define CACHE_FLUSH_FUNC "_flush_cache"
2567 /* A C statement to initialize the variable parts of a trampoline.
2568 ADDR is an RTX for the address of the trampoline; FNADDR is an
2569 RTX for the address of the nested function; STATIC_CHAIN is an
2570 RTX for the static chain value that should be passed to the
2571 function when it is called. */
2573 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2576 if (TARGET_LONG64) \
2578 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2579 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2583 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2584 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2587 /* Flush both caches. We need to flush the data cache in case \
2588 the system has a write-back cache. */ \
2589 /* ??? Should check the return value for errors. */ \
2590 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, CACHE_FLUSH_FUNC), \
2591 0, VOIDmode, 3, addr, Pmode, \
2592 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2593 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2596 /* Addressing modes, and classification of registers for them. */
2598 /* #define HAVE_POST_INCREMENT */
2599 /* #define HAVE_POST_DECREMENT */
2601 /* #define HAVE_PRE_DECREMENT */
2602 /* #define HAVE_PRE_INCREMENT */
2604 /* These assume that REGNO is a hard or pseudo reg number.
2605 They give nonzero only if REGNO is a hard reg of the suitable class
2606 or a pseudo reg currently allocated to a suitable hard reg.
2607 These definitions are NOT overridden anywhere. */
2609 #define BASE_REG_P(regno, mode) \
2611 ? (M16_REG_P (regno) \
2612 || (regno) == FRAME_POINTER_REGNUM \
2613 || (regno) == ARG_POINTER_REGNUM \
2614 || ((regno) == STACK_POINTER_REGNUM \
2615 && (GET_MODE_SIZE (mode) == 4 \
2616 || GET_MODE_SIZE (mode) == 8))) \
2619 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2620 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2623 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2624 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2626 #define REGNO_OK_FOR_INDEX_P(regno) 0
2627 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2628 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2630 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2631 and check its validity for a certain class.
2632 We have two alternate definitions for each of them.
2633 The usual definition accepts all pseudo regs; the other rejects them all.
2634 The symbol REG_OK_STRICT causes the latter definition to be used.
2636 Most source files want to accept pseudo regs in the hope that
2637 they will get allocated to the class that the insn wants them to be in.
2638 Some source files that are used after register allocation
2639 need to be strict. */
2641 #ifndef REG_OK_STRICT
2643 #define REG_OK_STRICT_P 0
2644 #define REG_OK_FOR_INDEX_P(X) 0
2645 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2646 GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
2650 #define REG_OK_STRICT_P 1
2651 #define REG_OK_FOR_INDEX_P(X) 0
2652 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2653 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
2658 /* Maximum number of registers that can appear in a valid memory address. */
2660 #define MAX_REGS_PER_ADDRESS 1
2662 /* A C compound statement with a conditional `goto LABEL;' executed
2663 if X (an RTX) is a legitimate memory address on the target
2664 machine for a memory operand of mode MODE.
2666 It usually pays to define several simpler macros to serve as
2667 subroutines for this one. Otherwise it may be too complicated
2670 This macro must exist in two variants: a strict variant and a
2671 non-strict one. The strict variant is used in the reload pass.
2672 It must be defined so that any pseudo-register that has not been
2673 allocated a hard register is considered a memory reference. In
2674 contexts where some kind of register is required, a
2675 pseudo-register with no hard register must be rejected.
2677 The non-strict variant is used in other passes. It must be
2678 defined to accept all pseudo-registers in every context where
2679 some kind of register is required.
2681 Compiler source files that want to use the strict variant of
2682 this macro define the macro `REG_OK_STRICT'. You should use an
2683 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2684 in that case and the non-strict variant otherwise.
2686 Typically among the subroutines used to define
2687 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2688 acceptable registers for various purposes (one for base
2689 registers, one for index registers, and so on). Then only these
2690 subroutine macros need have two variants; the higher levels of
2691 macros may be the same whether strict or not.
2693 Normally, constant addresses which are the sum of a `symbol_ref'
2694 and an integer are stored inside a `const' RTX to mark them as
2695 constant. Therefore, there is no need to recognize such sums
2696 specifically as legitimate addresses. Normally you would simply
2697 recognize any `const' as legitimate.
2699 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2700 constant sums that are not marked with `const'. It assumes
2701 that a naked `plus' indicates indexing. If so, then you *must*
2702 reject such naked constant sums as illegitimate addresses, so
2703 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2705 On some machines, whether a symbolic address is legitimate
2706 depends on the section that the address refers to. On these
2707 machines, define the macro `ENCODE_SECTION_INFO' to store the
2708 information into the `symbol_ref', and then check for it here.
2709 When you see a `const', you will have to look inside it to find
2710 the `symbol_ref' in order to determine the section. */
2713 #define GO_PRINTF(x) trace(x)
2714 #define GO_PRINTF2(x,y) trace(x,y)
2715 #define GO_DEBUG_RTX(x) debug_rtx(x)
2718 #define GO_PRINTF(x)
2719 #define GO_PRINTF2(x,y)
2720 #define GO_DEBUG_RTX(x)
2723 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2725 register rtx xinsn = (X); \
2727 if (TARGET_DEBUG_B_MODE) \
2729 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2730 (REG_OK_STRICT_P) ? "" : "not "); \
2731 GO_DEBUG_RTX (xinsn); \
2734 /* The mips16 can only use the stack pointer as a base register when \
2735 loading SImode or DImode values. */ \
2736 if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \
2739 if (CONSTANT_ADDRESS_P (xinsn) \
2740 && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \
2741 && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \
2744 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2746 register rtx xlow0 = XEXP (xinsn, 0); \
2747 register rtx xlow1 = XEXP (xinsn, 1); \
2749 if (GET_CODE (xlow0) == REG \
2750 && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \
2751 && mips_check_split (xlow1, MODE)) \
2755 if (GET_CODE (xinsn) == PLUS) \
2757 register rtx xplus0 = XEXP (xinsn, 0); \
2758 register rtx xplus1 = XEXP (xinsn, 1); \
2759 register enum rtx_code code0 = GET_CODE (xplus0); \
2760 register enum rtx_code code1 = GET_CODE (xplus1); \
2762 /* The mips16 can only use the stack pointer as a base register \
2763 when loading SImode or DImode values. */ \
2764 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \
2766 if (code1 == CONST_INT \
2767 && INTVAL (xplus1) >= -32768 \
2768 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2771 /* On the mips16, we represent GP relative offsets in RTL. \
2772 These are 16 bit signed values, and can serve as register \
2775 && mips16_gp_offset_p (xplus1)) \
2778 /* For some code sequences, you actually get better code by \
2779 pretending that the MIPS supports an address mode of a \
2780 constant address + a register, even though the real \
2781 machine doesn't support it. This is because the \
2782 assembler can use $r1 to load just the high 16 bits, add \
2783 in the register, and fold the low 16 bits into the memory \
2784 reference, whereas the compiler generates a 4 instruction \
2785 sequence. On the other hand, CSE is not as effective. \
2786 It would be a win to generate the lui directly, but the \
2787 MIPS assembler does not have syntax to generate the \
2788 appropriate relocation. */ \
2790 /* Also accept CONST_INT addresses here, so no else. */ \
2791 /* Reject combining an embedded PIC text segment reference \
2792 with a register. That requires an additional \
2794 /* ??? Reject combining an address with a register for the MIPS \
2795 64 bit ABI, because the SGI assembler can not handle this. */ \
2796 if (!TARGET_DEBUG_A_MODE \
2797 && (mips_abi == ABI_32 || mips_abi == ABI_EABI) \
2798 && CONSTANT_ADDRESS_P (xplus1) \
2799 && ! mips_split_addresses \
2800 && (!TARGET_EMBEDDED_PIC \
2802 || GET_CODE (XEXP (xplus1, 0)) != MINUS) \
2803 && !TARGET_MIPS16) \
2808 if (TARGET_DEBUG_B_MODE) \
2809 GO_PRINTF ("Not a legitimate address\n"); \
2813 /* A C expression that is 1 if the RTX X is a constant which is a
2814 valid address. This is defined to be the same as `CONSTANT_P (X)',
2815 but rejecting CONST_DOUBLE. */
2816 /* When pic, we must reject addresses of the form symbol+large int.
2817 This is because an instruction `sw $4,s+70000' needs to be converted
2818 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2819 assembler would use $at as a temp to load in the large offset. In this
2820 case $at is already in use. We convert such problem addresses to
2821 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2822 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2823 #define CONSTANT_ADDRESS_P(X) \
2824 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2825 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2826 || (GET_CODE (X) == CONST \
2827 && ! (flag_pic && pic_address_needs_scratch (X)) \
2828 && (mips_abi == ABI_32 || mips_abi == ABI_EABI))) \
2829 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2831 /* Define this, so that when PIC, reload won't try to reload invalid
2832 addresses which require two reload registers. */
2834 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2836 /* Nonzero if the constant value X is a legitimate general operand.
2837 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2839 At present, GAS doesn't understand li.[sd], so don't allow it
2840 to be generated at present. Also, the MIPS assembler does not
2841 grok li.d Infinity. */
2843 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2844 #define LEGITIMATE_CONSTANT_P(X) \
2845 ((GET_CODE (X) != CONST_DOUBLE \
2846 || mips_const_double_ok (X, GET_MODE (X))) \
2847 && ! (GET_CODE (X) == CONST \
2848 && mips_abi != ABI_32 && mips_abi != ABI_EABI) \
2849 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2851 /* A C compound statement that attempts to replace X with a valid
2852 memory address for an operand of mode MODE. WIN will be a C
2853 statement label elsewhere in the code; the macro definition may
2856 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2858 to avoid further processing if the address has become legitimate.
2860 X will always be the result of a call to `break_out_memory_refs',
2861 and OLDX will be the operand that was given to that function to
2864 The code generated by this macro should not alter the
2865 substructure of X. If it transforms X into a more legitimate
2866 form, it should assign X (which will always be a C variable) a
2869 It is not necessary for this macro to come up with a legitimate
2870 address. The compiler has standard ways of doing so in all
2871 cases. In fact, it is safe for this macro to do nothing. But
2872 often a machine-dependent strategy can generate better code.
2874 For the MIPS, transform:
2876 memory(X + <large int>)
2880 Y = <large int> & ~0x7fff;
2882 memory (Z + (<large int> & 0x7fff));
2884 This is for CSE to find several similar references, and only use one Z.
2886 When PIC, convert addresses of the form memory (symbol+large int) to
2887 memory (reg+large int). */
2890 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2892 register rtx xinsn = (X); \
2894 if (TARGET_DEBUG_B_MODE) \
2896 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2897 GO_DEBUG_RTX (xinsn); \
2900 if (mips_split_addresses && mips_check_split (X, MODE)) \
2902 /* ??? Is this ever executed? */ \
2903 X = gen_rtx (LO_SUM, Pmode, \
2904 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2908 if (GET_CODE (xinsn) == CONST \
2909 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2910 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2911 || (mips_abi != ABI_32 && mips_abi != ABI_EABI))) \
2913 rtx ptr_reg = gen_reg_rtx (Pmode); \
2914 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2916 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2918 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2919 if (SMALL_INT (constant)) \
2921 /* Otherwise we fall through so the code below will fix the \
2926 if (GET_CODE (xinsn) == PLUS) \
2928 register rtx xplus0 = XEXP (xinsn, 0); \
2929 register rtx xplus1 = XEXP (xinsn, 1); \
2930 register enum rtx_code code0 = GET_CODE (xplus0); \
2931 register enum rtx_code code1 = GET_CODE (xplus1); \
2933 if (code0 != REG && code1 == REG) \
2935 xplus0 = XEXP (xinsn, 1); \
2936 xplus1 = XEXP (xinsn, 0); \
2937 code0 = GET_CODE (xplus0); \
2938 code1 = GET_CODE (xplus1); \
2941 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
2942 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2944 rtx int_reg = gen_reg_rtx (Pmode); \
2945 rtx ptr_reg = gen_reg_rtx (Pmode); \
2947 emit_move_insn (int_reg, \
2948 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2950 emit_insn (gen_rtx (SET, VOIDmode, \
2952 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
2954 X = gen_rtx (PLUS, Pmode, ptr_reg, \
2955 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
2960 if (TARGET_DEBUG_B_MODE) \
2961 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
2965 /* A C statement or compound statement with a conditional `goto
2966 LABEL;' executed if memory address X (an RTX) can have different
2967 meanings depending on the machine mode of the memory reference it
2970 Autoincrement and autodecrement addresses typically have
2971 mode-dependent effects because the amount of the increment or
2972 decrement is the size of the operand being addressed. Some
2973 machines have other mode-dependent addresses. Many RISC machines
2974 have no mode-dependent addresses.
2976 You may assume that ADDR is a valid address for the machine. */
2978 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2981 /* Define this macro if references to a symbol must be treated
2982 differently depending on something about the variable or
2983 function named by the symbol (such as what section it is in).
2985 The macro definition, if any, is executed immediately after the
2986 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
2987 The value of the rtl will be a `mem' whose address is a
2990 The usual thing for this macro to do is to a flag in the
2991 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
2992 name string in the `symbol_ref' (if one bit is not enough
2995 The best way to modify the name string is by adding text to the
2996 beginning, with suitable punctuation to prevent any ambiguity.
2997 Allocate the new name in `saveable_obstack'. You will have to
2998 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
2999 and output the name accordingly.
3001 You can also check the information stored in the `symbol_ref' in
3002 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3003 `PRINT_OPERAND_ADDRESS'.
3005 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3008 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3009 symbols which are not in the .text section.
3011 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3012 constants which are put in the .text section. We also record the
3013 total length of all such strings; this total is used to decide
3014 whether we need to split the constant table, and need not be
3015 precisely correct. */
3017 #define ENCODE_SECTION_INFO(DECL) \
3020 if (TARGET_MIPS16) \
3022 if (TREE_CODE (DECL) == STRING_CST \
3023 && ! flag_writable_strings) \
3025 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3026 mips_string_length += TREE_STRING_LENGTH (DECL); \
3029 if (TARGET_EMBEDDED_PIC) \
3031 if (TREE_CODE (DECL) == VAR_DECL) \
3032 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3033 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3034 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3035 else if (TREE_CODE (DECL) == STRING_CST \
3036 && ! flag_writable_strings) \
3037 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3039 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3042 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
3044 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3046 if (size > 0 && size <= mips_section_threshold) \
3047 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3050 else if (HALF_PIC_P ()) \
3052 HALF_PIC_ENCODE (DECL); \
3057 /* The mips16 wants the constant pool to be after the function,
3058 because the PC relative load instructions use unsigned offsets. */
3060 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3062 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3063 mips_string_length = 0;
3066 /* In mips16 mode, put most string constants after the function. */
3067 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3068 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3071 /* Specify the machine mode that this machine uses
3072 for the index in the tablejump instruction.
3073 ??? Using HImode in mips16 mode can cause overflow. However, the
3074 overflow is no more likely than the overflow in a branch
3075 instruction. Large functions can currently break in both ways. */
3076 #define CASE_VECTOR_MODE \
3077 (TARGET_MIPS16 ? HImode : TARGET_LONG64 ? DImode : SImode)
3079 /* Define as C expression which evaluates to nonzero if the tablejump
3080 instruction expects the table to contain offsets from the address of the
3082 Do not define this if the table should contain absolute addresses. */
3083 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3085 /* Specify the tree operation to be used to convert reals to integers. */
3086 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3088 /* This is the kind of divide that is easiest to do in the general case. */
3089 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3091 /* Define this as 1 if `char' should by default be signed; else as 0. */
3092 #ifndef DEFAULT_SIGNED_CHAR
3093 #define DEFAULT_SIGNED_CHAR 1
3096 /* Max number of bytes we can move from memory to memory
3097 in one reasonably fast instruction. */
3098 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3099 #define MAX_MOVE_MAX 8
3101 /* Define this macro as a C expression which is nonzero if
3102 accessing less than a word of memory (i.e. a `char' or a
3103 `short') is no faster than accessing a word of memory, i.e., if
3104 such access require more than one instruction or if there is no
3105 difference in cost between byte and (aligned) word loads.
3107 On RISC machines, it tends to generate better code to define
3108 this as 1, since it avoids making a QI or HI mode register. */
3109 #define SLOW_BYTE_ACCESS 1
3111 /* We assume that the store-condition-codes instructions store 0 for false
3112 and some other value for true. This is the value stored for true. */
3114 #define STORE_FLAG_VALUE 1
3116 /* Define this if zero-extension is slow (more than one real instruction). */
3117 #define SLOW_ZERO_EXTEND
3119 /* Define this to be nonzero if shift instructions ignore all but the low-order
3121 #define SHIFT_COUNT_TRUNCATED 1
3123 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3124 is done just by pretending it is already truncated. */
3125 /* In 64 bit mode, 32 bit instructions require that register values be properly
3126 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3127 converts a value >32 bits to a value <32 bits. */
3128 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3129 Something needs to be done about this. Perhaps not use any 32 bit
3130 instructions? Perhaps use PROMOTE_MODE? */
3131 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3132 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3134 /* Specify the machine mode that pointers have.
3135 After generation of rtl, the compiler makes no further distinction
3136 between pointers and any other objects of this machine mode. */
3138 #define Pmode (TARGET_LONG64 ? DImode : SImode)
3140 /* A function address in a call instruction
3141 is a word address (for indexing purposes)
3142 so give the MEM rtx a words's mode. */
3144 #define FUNCTION_MODE (TARGET_LONG64 ? DImode : SImode)
3146 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3147 memset, instead of the BSD functions bcopy and bzero. */
3149 #if defined(MIPS_SYSV) || defined(OSF_OS)
3150 #define TARGET_MEM_FUNCTIONS
3154 /* A part of a C `switch' statement that describes the relative
3155 costs of constant RTL expressions. It must contain `case'
3156 labels for expression codes `const_int', `const', `symbol_ref',
3157 `label_ref' and `const_double'. Each case must ultimately reach
3158 a `return' statement to return the relative cost of the use of
3159 that kind of constant value in an expression. The cost may
3160 depend on the precise value of the constant, which is available
3161 for examination in X.
3163 CODE is the expression code--redundant, since it can be obtained
3164 with `GET_CODE (X)'. */
3166 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3168 if (! TARGET_MIPS16) \
3170 /* Always return 0, since we don't have different sized \
3171 instructions, hence different costs according to Richard \
3175 if ((OUTER_CODE) == SET) \
3177 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3179 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3180 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3181 return COSTS_N_INSNS (1); \
3183 return COSTS_N_INSNS (2); \
3185 /* A PLUS could be an address. We don't want to force an address \
3186 to use a register, so accept any signed 16 bit value without \
3188 if ((OUTER_CODE) == PLUS \
3189 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3191 /* A number between 1 and 8 inclusive is efficient for a shift. \
3192 Otherwise, we will need an extended instruction. */ \
3193 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3194 || (OUTER_CODE) == LSHIFTRT) \
3196 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3198 return COSTS_N_INSNS (1); \
3200 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3201 if ((OUTER_CODE) == XOR \
3202 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3204 /* We may be able to use slt or sltu for a comparison with a \
3205 signed 16 bit value. (The boundary conditions aren't quite \
3206 right, but this is just a heuristic anyhow.) */ \
3207 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3208 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3209 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3210 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3211 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3213 /* Equality comparisons with 0 are cheap. */ \
3214 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3215 && INTVAL (X) == 0) \
3218 /* Otherwise, work out the cost to load the value into a \
3220 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3221 return COSTS_N_INSNS (1); \
3222 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3223 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3224 return COSTS_N_INSNS (2); \
3226 return COSTS_N_INSNS (3); \
3229 return COSTS_N_INSNS (2); \
3233 rtx offset = const0_rtx; \
3234 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3236 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3238 /* Treat this like a signed 16 bit CONST_INT. */ \
3239 if ((OUTER_CODE) == PLUS) \
3241 else if ((OUTER_CODE) == SET) \
3242 return COSTS_N_INSNS (1); \
3244 return COSTS_N_INSNS (2); \
3247 if (GET_CODE (symref) == LABEL_REF) \
3248 return COSTS_N_INSNS (2); \
3250 if (GET_CODE (symref) != SYMBOL_REF) \
3251 return COSTS_N_INSNS (4); \
3253 /* let's be paranoid.... */ \
3254 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3255 return COSTS_N_INSNS (2); \
3257 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3261 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3263 case CONST_DOUBLE: \
3266 if (TARGET_MIPS16) \
3267 return COSTS_N_INSNS (4); \
3268 split_double (X, &high, &low); \
3269 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3270 || low == CONST0_RTX (GET_MODE (low))) \
3274 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3275 This can be used, for example, to indicate how costly a multiply
3276 instruction is. In writing this macro, you can use the construct
3277 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3279 This macro is optional; do not define it if the default cost
3280 assumptions are adequate for the target machine.
3282 If -mdebugd is used, change the multiply cost to 2, so multiply by
3283 a constant isn't converted to a series of shifts. This helps
3284 strength reduction, and also makes it easier to identify what the
3285 compiler is doing. */
3287 /* ??? Fix this to be right for the R8000. */
3288 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3291 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3292 if (simple_memory_operand (X, GET_MODE (X))) \
3293 return COSTS_N_INSNS (num_words); \
3295 return COSTS_N_INSNS (2*num_words); \
3299 return COSTS_N_INSNS (6); \
3302 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3307 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3308 return COSTS_N_INSNS (2); \
3315 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3316 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3322 enum machine_mode xmode = GET_MODE (X); \
3323 if (xmode == SFmode || xmode == DFmode) \
3324 return COSTS_N_INSNS (1); \
3326 return COSTS_N_INSNS (4); \
3332 enum machine_mode xmode = GET_MODE (X); \
3333 if (xmode == SFmode || xmode == DFmode) \
3335 if (mips_cpu == PROCESSOR_R3000 \
3336 || mips_cpu == PROCESSOR_R3900) \
3337 return COSTS_N_INSNS (2); \
3338 else if (mips_cpu == PROCESSOR_R6000) \
3339 return COSTS_N_INSNS (3); \
3341 return COSTS_N_INSNS (6); \
3344 if (xmode == DImode && !TARGET_64BIT) \
3345 return COSTS_N_INSNS (4); \
3351 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3358 enum machine_mode xmode = GET_MODE (X); \
3359 if (xmode == SFmode) \
3361 if (mips_cpu == PROCESSOR_R3000 \
3362 || mips_cpu == PROCESSOR_R3900 \
3363 || mips_cpu == PROCESSOR_R5000) \
3364 return COSTS_N_INSNS (4); \
3365 else if (mips_cpu == PROCESSOR_R6000) \
3366 return COSTS_N_INSNS (5); \
3368 return COSTS_N_INSNS (7); \
3371 if (xmode == DFmode) \
3373 if (mips_cpu == PROCESSOR_R3000 \
3374 || mips_cpu == PROCESSOR_R3900 \
3375 || mips_cpu == PROCESSOR_R5000) \
3376 return COSTS_N_INSNS (5); \
3377 else if (mips_cpu == PROCESSOR_R6000) \
3378 return COSTS_N_INSNS (6); \
3380 return COSTS_N_INSNS (8); \
3383 if (mips_cpu == PROCESSOR_R3000) \
3384 return COSTS_N_INSNS (12); \
3385 else if (mips_cpu == PROCESSOR_R3900) \
3386 return COSTS_N_INSNS (2); \
3387 else if (mips_cpu == PROCESSOR_R6000) \
3388 return COSTS_N_INSNS (17); \
3389 else if (mips_cpu == PROCESSOR_R5000) \
3390 return COSTS_N_INSNS (5); \
3392 return COSTS_N_INSNS (10); \
3398 enum machine_mode xmode = GET_MODE (X); \
3399 if (xmode == SFmode) \
3401 if (mips_cpu == PROCESSOR_R3000 \
3402 || mips_cpu == PROCESSOR_R3900) \
3403 return COSTS_N_INSNS (12); \
3404 else if (mips_cpu == PROCESSOR_R6000) \
3405 return COSTS_N_INSNS (15); \
3407 return COSTS_N_INSNS (23); \
3410 if (xmode == DFmode) \
3412 if (mips_cpu == PROCESSOR_R3000 \
3413 || mips_cpu == PROCESSOR_R3900) \
3414 return COSTS_N_INSNS (19); \
3415 else if (mips_cpu == PROCESSOR_R6000) \
3416 return COSTS_N_INSNS (16); \
3418 return COSTS_N_INSNS (36); \
3421 /* fall through */ \
3425 if (mips_cpu == PROCESSOR_R3000 \
3426 || mips_cpu == PROCESSOR_R3900) \
3427 return COSTS_N_INSNS (35); \
3428 else if (mips_cpu == PROCESSOR_R6000) \
3429 return COSTS_N_INSNS (38); \
3430 else if (mips_cpu == PROCESSOR_R5000) \
3431 return COSTS_N_INSNS (36); \
3433 return COSTS_N_INSNS (69); \
3436 /* A sign extend from SImode to DImode in 64 bit mode is often \
3437 zero instructions, because the result can often be used \
3438 directly by another instruction; we'll call it one. */ \
3439 if (TARGET_64BIT && GET_MODE (X) == DImode \
3440 && GET_MODE (XEXP (X, 0)) == SImode) \
3441 return COSTS_N_INSNS (1); \
3443 return COSTS_N_INSNS (2); \
3446 if (TARGET_64BIT && GET_MODE (X) == DImode \
3447 && GET_MODE (XEXP (X, 0)) == SImode) \
3448 return COSTS_N_INSNS (2); \
3450 return COSTS_N_INSNS (1);
3452 /* An expression giving the cost of an addressing mode that
3453 contains ADDRESS. If not defined, the cost is computed from the
3454 form of the ADDRESS expression and the `CONST_COSTS' values.
3456 For most CISC machines, the default cost is a good approximation
3457 of the true cost of the addressing mode. However, on RISC
3458 machines, all instructions normally have the same length and
3459 execution time. Hence all addresses will have equal costs.
3461 In cases where more than one form of an address is known, the
3462 form with the lowest cost will be used. If multiple forms have
3463 the same, lowest, cost, the one that is the most complex will be
3466 For example, suppose an address that is equal to the sum of a
3467 register and a constant is used twice in the same basic block.
3468 When this macro is not defined, the address will be computed in
3469 a register and memory references will be indirect through that
3470 register. On machines where the cost of the addressing mode
3471 containing the sum is no higher than that of a simple indirect
3472 reference, this will produce an additional instruction and
3473 possibly require an additional register. Proper specification
3474 of this macro eliminates this overhead for such machines.
3476 Similar use of this macro is made in strength reduction of loops.
3478 ADDRESS need not be valid as an address. In such a case, the
3479 cost is not relevant and can be any value; invalid addresses
3480 need not be assigned a different cost.
3482 On machines where an address involving more than one register is
3483 as cheap as an address computation involving only one register,
3484 defining `ADDRESS_COST' to reflect this can cause two registers
3485 to be live over a region of code where only one would have been
3486 if `ADDRESS_COST' were not defined in that manner. This effect
3487 should be considered in the definition of this macro.
3488 Equivalent costs should probably only be given to addresses with
3489 different numbers of registers on machines with lots of registers.
3491 This macro will normally either not be defined or be defined as
3494 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3496 /* A C expression for the cost of moving data from a register in
3497 class FROM to one in class TO. The classes are expressed using
3498 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3499 the default; other values are interpreted relative to that.
3501 It is not required that the cost always equal 2 when FROM is the
3502 same as TO; on some machines it is expensive to move between
3503 registers if they are not general registers.
3505 If reload sees an insn consisting of a single `set' between two
3506 hard registers, and if `REGISTER_MOVE_COST' applied to their
3507 classes returns a value of 2, reload does not check to ensure
3508 that the constraints of the insn are met. Setting a cost of
3509 other than 2 will allow reload to verify that the constraints are
3510 met. You should do this if the `movM' pattern's constraints do
3511 not allow such copying. */
3513 #define REGISTER_MOVE_COST(FROM, TO) \
3514 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3515 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3516 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3517 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3518 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3519 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3520 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3521 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3522 : (((FROM) == HI_REG || (FROM) == LO_REG \
3523 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3524 && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6 \
3525 : (((FROM) == HI_REG || (FROM) == LO_REG \
3526 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3527 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 8 : 6) \
3528 : (((TO) == HI_REG || (TO) == LO_REG \
3529 || (TO) == MD_REGS || (TO) == HILO_REG) \
3530 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3531 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3532 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3535 /* ??? Fix this to be right for the R8000. */
3536 #define MEMORY_MOVE_COST(MODE) \
3537 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4)
3539 /* A C expression for the cost of a branch instruction. A value of
3540 1 is the default; other values are interpreted relative to that. */
3542 /* ??? Fix this to be right for the R8000. */
3543 #define BRANCH_COST \
3545 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3548 /* A C statement (sans semicolon) to update the integer variable COST
3549 based on the relationship between INSN that is dependent on
3550 DEP_INSN through the dependence LINK. The default is to make no
3551 adjustment to COST. On the MIPS, ignore the cost of anti- and
3552 output-dependencies. */
3554 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3555 if (REG_NOTE_KIND (LINK) != 0) \
3556 (COST) = 0; /* Anti or output dependence. */
3558 /* Optionally define this if you have added predicates to
3559 `MACHINE.c'. This macro is called within an initializer of an
3560 array of structures. The first field in the structure is the
3561 name of a predicate and the second field is an array of rtl
3562 codes. For each predicate, list all rtl codes that can be in
3563 expressions matched by the predicate. The list should have a
3564 trailing comma. Here is an example of two entries in the list
3565 for a typical RISC machine:
3567 #define PREDICATE_CODES \
3568 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3569 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3571 Defining this macro does not affect the generated code (however,
3572 incorrect definitions that omit an rtl code that may be matched
3573 by the predicate can cause the compiler to malfunction).
3574 Instead, it allows the table built by `genrecog' to be more
3575 compact and efficient, thus speeding up the compiler. The most
3576 important predicates to include in the list specified by this
3577 macro are thoses used in the most insn patterns. */
3579 #define PREDICATE_CODES \
3580 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3581 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3582 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3583 {"reg_or_0_operand", { REG, CONST_INT, SUBREG }}, \
3584 {"small_int", { CONST_INT }}, \
3585 {"large_int", { CONST_INT }}, \
3586 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3587 {"const_float_1_operand", { CONST_DOUBLE }}, \
3588 {"simple_memory_operand", { MEM, SUBREG }}, \
3589 {"equality_op", { EQ, NE }}, \
3590 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3592 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3593 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3594 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3595 SYMBOL_REF, LABEL_REF, SUBREG, \
3597 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3598 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3599 MEM, SIGN_EXTEND }}, \
3600 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3601 {"se_reg_or_0_operand", { REG, CONST_INT, SUBREG, \
3603 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3605 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3607 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3608 SYMBOL_REF, LABEL_REF, SUBREG, \
3609 REG, SIGN_EXTEND }}, \
3610 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3611 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3612 CONST_DOUBLE, CONST }},
3615 /* If defined, a C statement to be executed just prior to the
3616 output of assembler code for INSN, to modify the extracted
3617 operands so they will be output differently.
3619 Here the argument OPVEC is the vector containing the operands
3620 extracted from INSN, and NOPERANDS is the number of elements of
3621 the vector which contain meaningful data for this insn. The
3622 contents of this vector are what will be used to convert the
3623 insn template into assembler code, so you can change the
3624 assembler output by changing the contents of the vector.
3626 We use it to check if the current insn needs a nop in front of it
3627 because of load delays, and also to update the delay slot
3630 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3631 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3634 /* Control the assembler format that we output. */
3636 /* Output at beginning of assembler file.
3637 If we are optimizing to use the global pointer, create a temporary
3638 file to hold all of the text stuff, and write it out to the end.
3639 This is needed because the MIPS assembler is evidently one pass,
3640 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3641 declaration when the code is processed, it generates a two
3642 instruction sequence. */
3644 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3646 /* Output to assembler file text saying following lines
3647 may contain character constants, extra white space, comments, etc. */
3649 #define ASM_APP_ON " #APP\n"
3651 /* Output to assembler file text saying following lines
3652 no longer contain unusual constructs. */
3654 #define ASM_APP_OFF " #NO_APP\n"
3656 /* How to refer to registers in assembler output.
3657 This sequence is indexed by compiler's hard-register-number (see above).
3659 In order to support the two different conventions for register names,
3660 we use the name of a table set up in mips.c, which is overwritten
3661 if -mrnames is used. */
3663 #define REGISTER_NAMES \
3665 &mips_reg_names[ 0][0], \
3666 &mips_reg_names[ 1][0], \
3667 &mips_reg_names[ 2][0], \
3668 &mips_reg_names[ 3][0], \
3669 &mips_reg_names[ 4][0], \
3670 &mips_reg_names[ 5][0], \
3671 &mips_reg_names[ 6][0], \
3672 &mips_reg_names[ 7][0], \
3673 &mips_reg_names[ 8][0], \
3674 &mips_reg_names[ 9][0], \
3675 &mips_reg_names[10][0], \
3676 &mips_reg_names[11][0], \
3677 &mips_reg_names[12][0], \
3678 &mips_reg_names[13][0], \
3679 &mips_reg_names[14][0], \
3680 &mips_reg_names[15][0], \
3681 &mips_reg_names[16][0], \
3682 &mips_reg_names[17][0], \
3683 &mips_reg_names[18][0], \
3684 &mips_reg_names[19][0], \
3685 &mips_reg_names[20][0], \
3686 &mips_reg_names[21][0], \
3687 &mips_reg_names[22][0], \
3688 &mips_reg_names[23][0], \
3689 &mips_reg_names[24][0], \
3690 &mips_reg_names[25][0], \
3691 &mips_reg_names[26][0], \
3692 &mips_reg_names[27][0], \
3693 &mips_reg_names[28][0], \
3694 &mips_reg_names[29][0], \
3695 &mips_reg_names[30][0], \
3696 &mips_reg_names[31][0], \
3697 &mips_reg_names[32][0], \
3698 &mips_reg_names[33][0], \
3699 &mips_reg_names[34][0], \
3700 &mips_reg_names[35][0], \
3701 &mips_reg_names[36][0], \
3702 &mips_reg_names[37][0], \
3703 &mips_reg_names[38][0], \
3704 &mips_reg_names[39][0], \
3705 &mips_reg_names[40][0], \
3706 &mips_reg_names[41][0], \
3707 &mips_reg_names[42][0], \
3708 &mips_reg_names[43][0], \
3709 &mips_reg_names[44][0], \
3710 &mips_reg_names[45][0], \
3711 &mips_reg_names[46][0], \
3712 &mips_reg_names[47][0], \
3713 &mips_reg_names[48][0], \
3714 &mips_reg_names[49][0], \
3715 &mips_reg_names[50][0], \
3716 &mips_reg_names[51][0], \
3717 &mips_reg_names[52][0], \
3718 &mips_reg_names[53][0], \
3719 &mips_reg_names[54][0], \
3720 &mips_reg_names[55][0], \
3721 &mips_reg_names[56][0], \
3722 &mips_reg_names[57][0], \
3723 &mips_reg_names[58][0], \
3724 &mips_reg_names[59][0], \
3725 &mips_reg_names[60][0], \
3726 &mips_reg_names[61][0], \
3727 &mips_reg_names[62][0], \
3728 &mips_reg_names[63][0], \
3729 &mips_reg_names[64][0], \
3730 &mips_reg_names[65][0], \
3731 &mips_reg_names[66][0], \
3732 &mips_reg_names[67][0], \
3733 &mips_reg_names[68][0], \
3734 &mips_reg_names[69][0], \
3735 &mips_reg_names[70][0], \
3736 &mips_reg_names[71][0], \
3737 &mips_reg_names[72][0], \
3738 &mips_reg_names[73][0], \
3739 &mips_reg_names[74][0], \
3740 &mips_reg_names[75][0], \
3743 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3744 So define this for it. */
3745 #define DEBUG_REGISTER_NAMES \
3747 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3748 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3749 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3750 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3751 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3752 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3753 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3754 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3755 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3756 "$fcc5","$fcc6","$fcc7","$rap" \
3759 /* If defined, a C initializer for an array of structures
3760 containing a name and a register number. This macro defines
3761 additional names for hard registers, thus allowing the `asm'
3762 option in declarations to refer to registers using alternate
3765 We define both names for the integer registers here. */
3767 #define ADDITIONAL_REGISTER_NAMES \
3769 { "$0", 0 + GP_REG_FIRST }, \
3770 { "$1", 1 + GP_REG_FIRST }, \
3771 { "$2", 2 + GP_REG_FIRST }, \
3772 { "$3", 3 + GP_REG_FIRST }, \
3773 { "$4", 4 + GP_REG_FIRST }, \
3774 { "$5", 5 + GP_REG_FIRST }, \
3775 { "$6", 6 + GP_REG_FIRST }, \
3776 { "$7", 7 + GP_REG_FIRST }, \
3777 { "$8", 8 + GP_REG_FIRST }, \
3778 { "$9", 9 + GP_REG_FIRST }, \
3779 { "$10", 10 + GP_REG_FIRST }, \
3780 { "$11", 11 + GP_REG_FIRST }, \
3781 { "$12", 12 + GP_REG_FIRST }, \
3782 { "$13", 13 + GP_REG_FIRST }, \
3783 { "$14", 14 + GP_REG_FIRST }, \
3784 { "$15", 15 + GP_REG_FIRST }, \
3785 { "$16", 16 + GP_REG_FIRST }, \
3786 { "$17", 17 + GP_REG_FIRST }, \
3787 { "$18", 18 + GP_REG_FIRST }, \
3788 { "$19", 19 + GP_REG_FIRST }, \
3789 { "$20", 20 + GP_REG_FIRST }, \
3790 { "$21", 21 + GP_REG_FIRST }, \
3791 { "$22", 22 + GP_REG_FIRST }, \
3792 { "$23", 23 + GP_REG_FIRST }, \
3793 { "$24", 24 + GP_REG_FIRST }, \
3794 { "$25", 25 + GP_REG_FIRST }, \
3795 { "$26", 26 + GP_REG_FIRST }, \
3796 { "$27", 27 + GP_REG_FIRST }, \
3797 { "$28", 28 + GP_REG_FIRST }, \
3798 { "$29", 29 + GP_REG_FIRST }, \
3799 { "$30", 30 + GP_REG_FIRST }, \
3800 { "$31", 31 + GP_REG_FIRST }, \
3801 { "$sp", 29 + GP_REG_FIRST }, \
3802 { "$fp", 30 + GP_REG_FIRST }, \
3803 { "at", 1 + GP_REG_FIRST }, \
3804 { "v0", 2 + GP_REG_FIRST }, \
3805 { "v1", 3 + GP_REG_FIRST }, \
3806 { "a0", 4 + GP_REG_FIRST }, \
3807 { "a1", 5 + GP_REG_FIRST }, \
3808 { "a2", 6 + GP_REG_FIRST }, \
3809 { "a3", 7 + GP_REG_FIRST }, \
3810 { "t0", 8 + GP_REG_FIRST }, \
3811 { "t1", 9 + GP_REG_FIRST }, \
3812 { "t2", 10 + GP_REG_FIRST }, \
3813 { "t3", 11 + GP_REG_FIRST }, \
3814 { "t4", 12 + GP_REG_FIRST }, \
3815 { "t5", 13 + GP_REG_FIRST }, \
3816 { "t6", 14 + GP_REG_FIRST }, \
3817 { "t7", 15 + GP_REG_FIRST }, \
3818 { "s0", 16 + GP_REG_FIRST }, \
3819 { "s1", 17 + GP_REG_FIRST }, \
3820 { "s2", 18 + GP_REG_FIRST }, \
3821 { "s3", 19 + GP_REG_FIRST }, \
3822 { "s4", 20 + GP_REG_FIRST }, \
3823 { "s5", 21 + GP_REG_FIRST }, \
3824 { "s6", 22 + GP_REG_FIRST }, \
3825 { "s7", 23 + GP_REG_FIRST }, \
3826 { "t8", 24 + GP_REG_FIRST }, \
3827 { "t9", 25 + GP_REG_FIRST }, \
3828 { "k0", 26 + GP_REG_FIRST }, \
3829 { "k1", 27 + GP_REG_FIRST }, \
3830 { "gp", 28 + GP_REG_FIRST }, \
3831 { "sp", 29 + GP_REG_FIRST }, \
3832 { "fp", 30 + GP_REG_FIRST }, \
3833 { "ra", 31 + GP_REG_FIRST }, \
3834 { "$sp", 29 + GP_REG_FIRST }, \
3835 { "$fp", 30 + GP_REG_FIRST } \
3838 /* Define results of standard character escape sequences. */
3839 #define TARGET_BELL 007
3840 #define TARGET_BS 010
3841 #define TARGET_TAB 011
3842 #define TARGET_NEWLINE 012
3843 #define TARGET_VT 013
3844 #define TARGET_FF 014
3845 #define TARGET_CR 015
3847 /* A C compound statement to output to stdio stream STREAM the
3848 assembler syntax for an instruction operand X. X is an RTL
3851 CODE is a value that can be used to specify one of several ways
3852 of printing the operand. It is used when identical operands
3853 must be printed differently depending on the context. CODE
3854 comes from the `%' specification that was used to request
3855 printing of the operand. If the specification was just `%DIGIT'
3856 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3857 is the ASCII code for LTR.
3859 If X is a register, this macro should print the register's name.
3860 The names can be found in an array `reg_names' whose type is
3861 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3863 When the machine description has a specification `%PUNCT' (a `%'
3864 followed by a punctuation character), this macro is called with
3865 a null pointer for X and the punctuation character for CODE.
3867 See mips.c for the MIPS specific codes. */
3869 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3871 /* A C expression which evaluates to true if CODE is a valid
3872 punctuation character for use in the `PRINT_OPERAND' macro. If
3873 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3874 punctuation characters (except for the standard one, `%') are
3875 used in this way. */
3877 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3879 /* A C compound statement to output to stdio stream STREAM the
3880 assembler syntax for an instruction operand that is a memory
3881 reference whose address is ADDR. ADDR is an RTL expression.
3883 On some machines, the syntax for a symbolic address depends on
3884 the section that the address refers to. On these machines,
3885 define the macro `ENCODE_SECTION_INFO' to store the information
3886 into the `symbol_ref', and then check for it here. */
3888 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3891 /* A C statement, to be executed after all slot-filler instructions
3892 have been output. If necessary, call `dbr_sequence_length' to
3893 determine the number of slots filled in a sequence (zero if not
3894 currently outputting a sequence), to decide how many no-ops to
3895 output, or whatever.
3897 Don't define this macro if it has nothing to do, but it is
3898 helpful in reading assembly output if the extent of the delay
3899 sequence is made explicit (e.g. with white space).
3901 Note that output routines for instructions with delay slots must
3902 be prepared to deal with not being output as part of a sequence
3903 (i.e. when the scheduling pass is not run, or when no slot
3904 fillers could be found.) The variable `final_sequence' is null
3905 when not processing a sequence, otherwise it contains the
3906 `sequence' rtx being output. */
3908 #define DBR_OUTPUT_SEQEND(STREAM) \
3911 if (set_nomacro > 0 && --set_nomacro == 0) \
3912 fputs ("\t.set\tmacro\n", STREAM); \
3914 if (set_noreorder > 0 && --set_noreorder == 0) \
3915 fputs ("\t.set\treorder\n", STREAM); \
3917 dslots_jump_filled++; \
3918 fputs ("\n", STREAM); \
3923 /* How to tell the debugger about changes of source files. Note, the
3924 mips ECOFF format cannot deal with changes of files inside of
3925 functions, which means the output of parser generators like bison
3926 is generally not debuggable without using the -l switch. Lose,
3927 lose, lose. Silicon graphics seems to want all .file's hardwired
3930 #ifndef SET_FILE_NUMBER
3931 #define SET_FILE_NUMBER() ++num_source_filenames
3934 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3935 mips_output_filename (STREAM, NAME)
3937 /* This is defined so that it can be overridden in iris6.h. */
3938 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3941 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3942 output_quoted_string (STREAM, NAME); \
3943 fputs ("\n", STREAM); \
3947 /* This is how to output a note the debugger telling it the line number
3948 to which the following sequence of instructions corresponds.
3949 Silicon graphics puts a label after each .loc. */
3951 #ifndef LABEL_AFTER_LOC
3952 #define LABEL_AFTER_LOC(STREAM)
3955 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3956 mips_output_lineno (STREAM, LINE)
3958 /* The MIPS implementation uses some labels for it's own purpose. The
3959 following lists what labels are created, and are all formed by the
3960 pattern $L[a-z].*. The machine independent portion of GCC creates
3961 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3963 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3964 $Lb[0-9]+ Begin blocks for MIPS debug support
3965 $Lc[0-9]+ Label for use in s<xx> operation.
3966 $Le[0-9]+ End blocks for MIPS debug support
3967 $Lp\..+ Half-pic labels. */
3969 /* This is how to output the definition of a user-level label named NAME,
3970 such as the label on a static function or variable NAME.
3972 If we are optimizing the gp, remember that this label has been put
3973 out, so we know not to emit an .extern for it in mips_asm_file_end.
3974 We use one of the common bits in the IDENTIFIER tree node for this,
3975 since those bits seem to be unused, and we don't have any method
3976 of getting the decl nodes from the name. */
3978 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
3980 assemble_name (STREAM, NAME); \
3981 fputs (":\n", STREAM); \
3985 /* A C statement (sans semicolon) to output to the stdio stream
3986 STREAM any text necessary for declaring the name NAME of an
3987 initialized variable which is being defined. This macro must
3988 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3989 The argument DECL is the `VAR_DECL' tree node representing the
3992 If this macro is not defined, then the variable name is defined
3993 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3995 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3998 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3999 HALF_PIC_DECLARE (NAME); \
4004 /* This is how to output a command to make the user-level label named NAME
4005 defined for reference from other files. */
4007 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4009 fputs ("\t.globl\t", STREAM); \
4010 assemble_name (STREAM, NAME); \
4011 fputs ("\n", STREAM); \
4014 /* This says how to define a global common symbol. */
4016 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
4017 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
4019 /* This says how to define a local common symbol (ie, not visible to
4022 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4023 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4026 /* This says how to output an external. It would be possible not to
4027 output anything and let undefined symbol become external. However
4028 the assembler uses length information on externals to allocate in
4029 data/sdata bss/sbss, thereby saving exec time. */
4031 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4032 mips_output_external(STREAM,DECL,NAME)
4034 /* This says what to print at the end of the assembly file */
4035 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4038 /* This is how to declare a function name. The actual work of
4039 emitting the label is moved to function_prologue, so that we can
4040 get the line number correctly emitted before the .ent directive,
4041 and after any .file directives.
4043 Also, switch files if we are optimizing the global pointer. */
4045 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4047 extern FILE *asm_out_text_file; \
4048 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4050 STREAM = asm_out_text_file; \
4051 /* ??? text_section gets called too soon. If the previous \
4052 function is in a special section and we're not, we have \
4053 to switch back to the text section. We can't call \
4054 text_section again as gcc thinks we're already there. */ \
4055 /* ??? See varasm.c. There are other things that get output \
4056 too early, like alignment (before we've switched STREAM). */ \
4057 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4058 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4061 HALF_PIC_DECLARE (NAME); \
4064 /* This is how to output an internal numbered label where
4065 PREFIX is the class of label and NUM is the number within the class. */
4067 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4068 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4070 /* This is how to store into the string LABEL
4071 the symbol_ref name of an internal numbered label where
4072 PREFIX is the class of label and NUM is the number within the class.
4073 This is suitable for output with `assemble_name'. */
4075 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4076 sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4078 /* This is how to output an assembler line defining a `double' constant. */
4080 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4081 mips_output_double (STREAM, VALUE)
4084 /* This is how to output an assembler line defining a `float' constant. */
4086 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4087 mips_output_float (STREAM, VALUE)
4090 /* This is how to output an assembler line defining an `int' constant. */
4092 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4094 fprintf (STREAM, "\t.word\t"); \
4095 output_addr_const (STREAM, (VALUE)); \
4096 fprintf (STREAM, "\n"); \
4099 /* Likewise for 64 bit, `char' and `short' constants. */
4101 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4105 fprintf (STREAM, "\t.dword\t"); \
4106 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4107 /* We can't use 'X' for negative numbers, because then we won't \
4108 get the right value for the upper 32 bits. */ \
4109 output_addr_const (STREAM, VALUE); \
4111 /* We must use 'X', because otherwise LONG_MIN will print as \
4112 a number that the Irix 6 assembler won't accept. */ \
4113 print_operand (STREAM, VALUE, 'X'); \
4114 fprintf (STREAM, "\n"); \
4118 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4119 UNITS_PER_WORD, 1); \
4120 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4121 UNITS_PER_WORD, 1); \
4125 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4127 fprintf (STREAM, "\t.half\t"); \
4128 output_addr_const (STREAM, (VALUE)); \
4129 fprintf (STREAM, "\n"); \
4132 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4134 fprintf (STREAM, "\t.byte\t"); \
4135 output_addr_const (STREAM, (VALUE)); \
4136 fprintf (STREAM, "\n"); \
4139 /* This is how to output an assembler line for a numeric constant byte. */
4141 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4142 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4144 /* This is how to output an element of a case-vector that is absolute. */
4146 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4147 fprintf (STREAM, "\t%s\t%sL%d\n", \
4148 TARGET_LONG64 ? ".dword" : ".word", \
4149 LOCAL_LABEL_PREFIX, \
4152 /* This is how to output an element of a case-vector that is relative.
4153 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4154 TARGET_EMBEDDED_PIC). */
4156 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, VALUE, REL) \
4158 if (TARGET_MIPS16) \
4159 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4160 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4161 else if (TARGET_EMBEDDED_PIC) \
4162 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4163 TARGET_LONG64 ? ".dword" : ".word", \
4164 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4165 else if (mips_abi == ABI_32) \
4166 fprintf (STREAM, "\t%s\t%sL%d\n", \
4167 TARGET_LONG64 ? ".gpdword" : ".gpword", \
4168 LOCAL_LABEL_PREFIX, VALUE); \
4170 fprintf (STREAM, "\t%s\t%sL%d\n", \
4171 TARGET_LONG64 ? ".dword" : ".word", \
4172 LOCAL_LABEL_PREFIX, VALUE); \
4175 /* When generating embedded PIC or mips16 code we want to put the jump
4176 table in the .text section. In all other cases, we want to put the
4177 jump table in the .rdata section. Unfortunately, we can't use
4178 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4179 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4180 section if appropriate. */
4181 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4183 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4184 function_section (current_function_decl); \
4185 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4188 /* This is how to output an assembler line
4189 that says to advance the location counter
4190 to a multiple of 2**LOG bytes. */
4192 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4194 int mask = (1 << (LOG)) - 1; \
4195 fprintf (STREAM, "\t.align\t%d\n", (LOG)); \
4198 /* This is how to output an assembler line to to advance the location
4199 counter by SIZE bytes. */
4201 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4202 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4204 /* This is how to output a string. */
4205 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4207 register int i, c, len = (LEN), cur_pos = 17; \
4208 register unsigned char *string = (unsigned char *)(STRING); \
4209 fprintf ((STREAM), "\t.ascii\t\""); \
4210 for (i = 0; i < len; i++) \
4212 register int c = string[i]; \
4218 putc ('\\', (STREAM)); \
4219 putc (c, (STREAM)); \
4223 case TARGET_NEWLINE: \
4224 fputs ("\\n", (STREAM)); \
4226 && (((c = string[i+1]) >= '\040' && c <= '~') \
4227 || c == TARGET_TAB)) \
4228 cur_pos = 32767; /* break right here */ \
4234 fputs ("\\t", (STREAM)); \
4239 fputs ("\\f", (STREAM)); \
4244 fputs ("\\b", (STREAM)); \
4249 fputs ("\\r", (STREAM)); \
4254 if (c >= ' ' && c < 0177) \
4256 putc (c, (STREAM)); \
4261 fprintf ((STREAM), "\\%03o", c); \
4266 if (cur_pos > 72 && i+1 < len) \
4269 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4272 fprintf ((STREAM), "\"\n"); \
4275 /* Handle certain cpp directives used in header files on sysV. */
4276 #define SCCS_DIRECTIVE
4278 /* Output #ident as a in the read-only data section. */
4279 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4282 int size = strlen (p) + 1; \
4284 assemble_string (p, size); \
4287 /* Default to -G 8 */
4288 #ifndef MIPS_DEFAULT_GVALUE
4289 #define MIPS_DEFAULT_GVALUE 8
4292 /* Define the strings to put out for each section in the object file. */
4293 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4294 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4295 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4296 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4297 #define READONLY_DATA_SECTION rdata_section
4298 #define SMALL_DATA_SECTION sdata_section
4300 /* What other sections we support other than the normal .data/.text. */
4302 #define EXTRA_SECTIONS in_sdata, in_rdata
4304 /* Define the additional functions to select our additional sections. */
4306 /* on the MIPS it is not a good idea to put constants in the text
4307 section, since this defeats the sdata/data mechanism. This is
4308 especially true when -O is used. In this case an effort is made to
4309 address with faster (gp) register relative addressing, which can
4310 only get at sdata and sbss items (there is no stext !!) However,
4311 if the constant is too large for sdata, and it's readonly, it
4312 will go into the .rdata section. */
4314 #define EXTRA_SECTION_FUNCTIONS \
4318 if (in_section != in_sdata) \
4320 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4321 in_section = in_sdata; \
4328 if (in_section != in_rdata) \
4330 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4331 in_section = in_rdata; \
4335 /* Given a decl node or constant node, choose the section to output it in
4336 and select that section. */
4338 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4340 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4343 /* Store in OUTPUT a string (made with alloca) containing
4344 an assembler-name for a local static variable named NAME.
4345 LABELNO is an integer which is different for each call. */
4347 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4348 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4349 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4351 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4354 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4355 TARGET_64BIT ? "dsubu" : "subu", \
4356 reg_names[STACK_POINTER_REGNUM], \
4357 reg_names[STACK_POINTER_REGNUM], \
4358 TARGET_64BIT ? "sd" : "sw", \
4360 reg_names[STACK_POINTER_REGNUM]); \
4364 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4367 if (! set_noreorder) \
4368 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4370 dslots_load_total++; \
4371 dslots_load_filled++; \
4372 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4373 TARGET_64BIT ? "ld" : "lw", \
4375 reg_names[STACK_POINTER_REGNUM], \
4376 TARGET_64BIT ? "daddu" : "addu", \
4377 reg_names[STACK_POINTER_REGNUM], \
4378 reg_names[STACK_POINTER_REGNUM]); \
4380 if (! set_noreorder) \
4381 fprintf (STREAM, "\t.set\treorder\n"); \
4385 /* Define the parentheses used to group arithmetic operations
4386 in assembler code. */
4388 #define ASM_OPEN_PAREN "("
4389 #define ASM_CLOSE_PAREN ")"
4391 /* How to start an assembler comment.
4392 The leading space is important (the mips native assembler requires it). */
4393 #ifndef ASM_COMMENT_START
4394 #define ASM_COMMENT_START " #"
4398 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4399 and mips-tdump.c to print them out.
4401 These must match the corresponding definitions in gdb/mipsread.c.
4402 Unfortunately, gcc and gdb do not currently share any directories. */
4404 #define CODE_MASK 0x8F300
4405 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4406 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4407 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4410 /* Default definitions for size_t and ptrdiff_t. */
4413 #define NO_BUILTIN_SIZE_TYPE
4414 #define SIZE_TYPE (TARGET_LONG64 ? "long unsigned int" : "unsigned int")
4417 #ifndef PTRDIFF_TYPE
4418 #define NO_BUILTIN_PTRDIFF_TYPE
4419 #define PTRDIFF_TYPE (TARGET_LONG64 ? "long int" : "int")
4422 /* See mips_expand_prologue's use of loadgp for when this should be
4425 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && mips_abi != ABI_32)
4427 /* In mips16 mode, we need to look through the function to check for
4428 PC relative loads that are out of range. */
4429 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4431 /* We need to use a special set of functions to handle hard floating
4432 point code in mips16 mode. */
4434 #ifndef INIT_SUBTARGET_OPTABS
4435 #define INIT_SUBTARGET_OPTABS
4438 #define INIT_TARGET_OPTABS \
4441 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4442 INIT_SUBTARGET_OPTABS; \
4445 add_optab->handlers[(int) SFmode].libfunc = \
4446 gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3"); \
4447 sub_optab->handlers[(int) SFmode].libfunc = \
4448 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3"); \
4449 smul_optab->handlers[(int) SFmode].libfunc = \
4450 gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3"); \
4451 flodiv_optab->handlers[(int) SFmode].libfunc = \
4452 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3"); \
4454 eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2"); \
4455 nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2"); \
4456 gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2"); \
4457 gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2"); \
4458 ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2"); \
4459 lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2"); \
4461 floatsisf_libfunc = \
4462 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf"); \
4464 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi"); \
4466 if (TARGET_DOUBLE_FLOAT) \
4468 add_optab->handlers[(int) DFmode].libfunc = \
4469 gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3"); \
4470 sub_optab->handlers[(int) DFmode].libfunc = \
4471 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3"); \
4472 smul_optab->handlers[(int) DFmode].libfunc = \
4473 gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3"); \
4474 flodiv_optab->handlers[(int) DFmode].libfunc = \
4475 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3"); \
4477 extendsfdf2_libfunc = \
4478 gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2"); \
4479 truncdfsf2_libfunc = \
4480 gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2"); \
4483 gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2"); \
4485 gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2"); \
4487 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2"); \
4489 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2"); \
4491 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2"); \
4493 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2"); \
4495 floatsidf_libfunc = \
4496 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf"); \
4498 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi"); \