1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-6, 1997 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern int flag_omit_frame_pointer;
32 extern int frame_pointer_needed;
33 extern char *language_string;
34 extern int may_call_alloca;
36 extern char **save_argv;
37 extern int target_flags;
38 extern char *version_string;
40 /* MIPS external variables defined in mips.c. */
44 CMP_SI, /* compare four byte integers */
45 CMP_DI, /* compare eight byte integers */
46 CMP_SF, /* compare single precision floats */
47 CMP_DF, /* compare double precision floats */
48 CMP_MAX /* max comparison type */
51 /* types of delay slot */
53 DELAY_NONE, /* no delay slot */
54 DELAY_LOAD, /* load from memory delay */
55 DELAY_HILO, /* move from/to hi/lo registers */
56 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
59 /* Which processor to schedule for. Since there is no difference between
60 a R2000 and R3000 in terms of the scheduler, we collapse them into
61 just an R3000. The elements of the enumeration must match exactly
62 the cpu attribute in the mips.md machine description. */
77 /* Recast the cpu class to be the cpu attribute. */
78 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
80 /* Which ABI to use. This is only used by the Irix 6 port currently. */
89 #ifndef MIPS_ABI_DEFAULT
90 /* We define this away so that there is no extra runtime cost if the target
91 doesn't support multiple ABIs. */
92 #define mips_abi ABI_32
94 extern enum mips_abi_type mips_abi;
97 /* Whether to emit abicalls code sequences or not. */
99 enum mips_abicalls_type {
104 /* Recast the abicalls class to be the abicalls attribute. */
105 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
107 /* Which type of block move to do (whether or not the last store is
108 split out so it can fill a branch delay slot). */
110 enum block_move_type {
111 BLOCK_MOVE_NORMAL, /* generate complete block move */
112 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
113 BLOCK_MOVE_LAST /* generate just the last store */
116 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
117 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
118 extern char *current_function_file; /* filename current function is in */
119 extern int num_source_filenames; /* current .file # */
120 extern int inside_function; /* != 0 if inside of a function */
121 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
122 extern int file_in_function_warning; /* warning given about .file in func */
123 extern int sdb_label_count; /* block start/end next label # */
124 extern int sdb_begin_function_line; /* Starting Line of current function */
125 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
126 extern int g_switch_value; /* value of the -G xx switch */
127 extern int g_switch_set; /* whether -G xx was passed. */
128 extern int sym_lineno; /* sgi next label # for each stmt */
129 extern int set_noreorder; /* # of nested .set noreorder's */
130 extern int set_nomacro; /* # of nested .set nomacro's */
131 extern int set_noat; /* # of nested .set noat's */
132 extern int set_volatile; /* # of nested .set volatile's */
133 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
134 extern int mips_dbx_regno[]; /* Map register # to debug register # */
135 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
136 extern enum cmp_type branch_type; /* what type of branch to use */
137 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
138 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
139 extern int mips_isa; /* architectural level */
140 extern char *mips_cpu_string; /* for -mcpu=<xxx> */
141 extern char *mips_isa_string; /* for -mips{1,2,3,4} */
142 extern char *mips_abi_string; /* for -misa={32,n32,64} */
143 extern int mips_split_addresses; /* perform high/lo_sum support */
144 extern int dslots_load_total; /* total # load related delay slots */
145 extern int dslots_load_filled; /* # filled load delay slots */
146 extern int dslots_jump_total; /* total # jump related delay slots */
147 extern int dslots_jump_filled; /* # filled jump delay slots */
148 extern int dslots_number_nops; /* # of nops needed by previous insn */
149 extern int num_refs[3]; /* # 1/2/3 word references */
150 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
151 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
152 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
153 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
154 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
156 /* Functions within mips.c that we reference. */
158 extern void abort_with_insn ();
159 extern int arith32_operand ();
160 extern int arith_operand ();
161 extern int cmp_op ();
162 extern long compute_frame_size ();
163 extern int epilogue_reg_mentioned_p ();
164 extern void expand_block_move ();
165 extern int equality_op ();
166 extern void final_prescan_insn ();
167 extern struct rtx_def * function_arg ();
168 extern void function_arg_advance ();
169 extern int function_arg_partial_nregs ();
170 extern int function_arg_pass_by_reference ();
171 extern void function_epilogue ();
172 extern void function_prologue ();
173 extern void gen_conditional_branch ();
174 extern void gen_conditional_move ();
175 extern struct rtx_def * gen_int_relational ();
176 extern void init_cumulative_args ();
177 extern int large_int ();
178 extern int mips_address_cost ();
179 extern void mips_asm_file_end ();
180 extern void mips_asm_file_start ();
181 extern int mips_const_double_ok ();
182 extern void mips_count_memory_refs ();
183 extern int mips_debugger_offset ();
184 extern void mips_declare_object ();
185 extern int mips_epilogue_delay_slots ();
186 extern void mips_expand_epilogue ();
187 extern void mips_expand_prologue ();
188 extern int mips_check_split ();
189 extern char *mips_fill_delay_slot ();
190 extern char *mips_move_1word ();
191 extern char *mips_move_2words ();
192 extern void mips_output_double ();
193 extern int mips_output_external ();
194 extern void mips_output_float ();
195 extern void mips_output_filename ();
196 extern void mips_output_lineno ();
197 extern char *output_block_move ();
198 extern void override_options ();
199 extern int pc_or_label_operand ();
200 extern void print_operand_address ();
201 extern void print_operand ();
202 extern void print_options ();
203 extern int reg_or_0_operand ();
204 extern int simple_epilogue_p ();
205 extern int simple_memory_operand ();
206 extern int small_int ();
208 extern int uns_arith_operand ();
209 extern struct rtx_def * embedded_pic_offset ();
211 /* Recognition functions that return if a condition is true. */
212 extern int address_operand ();
213 extern int const_double_operand ();
214 extern int const_int_operand ();
215 extern int general_operand ();
216 extern int immediate_operand ();
217 extern int memory_address_p ();
218 extern int memory_operand ();
219 extern int nonimmediate_operand ();
220 extern int nonmemory_operand ();
221 extern int register_operand ();
222 extern int scratch_operand ();
223 extern int move_operand ();
224 extern int movdi_operand ();
225 extern int se_register_operand ();
226 extern int se_reg_or_0_operand ();
227 extern int se_uns_arith_operand ();
228 extern int se_arith_operand ();
229 extern int se_nonmemory_operand ();
230 extern int se_nonimmediate_operand ();
232 /* Functions to change what output section we are using. */
233 extern void data_section ();
234 extern void rdata_section ();
235 extern void readonly_data_section ();
236 extern void sdata_section ();
237 extern void text_section ();
239 /* Stubs for half-pic support if not OSF/1 reference platform. */
242 #define HALF_PIC_P() 0
243 #define HALF_PIC_NUMBER_PTRS 0
244 #define HALF_PIC_NUMBER_REFS 0
245 #define HALF_PIC_ENCODE(DECL)
246 #define HALF_PIC_DECLARE(NAME)
247 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
248 #define HALF_PIC_ADDRESS_P(X) 0
249 #define HALF_PIC_PTR(X) X
250 #define HALF_PIC_FINISH(STREAM)
254 /* Run-time compilation parameters selecting different hardware subsets. */
256 /* Macros used in the machine description to test the flags. */
258 /* Bits for real switches */
259 #define MASK_INT64 0x00000001 /* ints are 64 bits */
260 #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
261 #define MASK_UNUSED 0x00000004
262 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
263 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
264 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
265 #define MASK_STATS 0x00000040 /* print statistics to stderr */
266 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
267 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
268 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
269 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
270 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
271 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
272 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
273 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
274 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
275 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
276 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
277 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
278 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
280 /* Dummy switches used only in spec's*/
281 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
283 /* Debug switches, not documented */
284 #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */
285 #define MASK_DEBUG_A 0x20000000 /* don't allow <label>($reg) addrs */
286 #define MASK_DEBUG_B 0x10000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
287 #define MASK_DEBUG_C 0x08000000 /* don't expand seq, etc. */
288 #define MASK_DEBUG_D 0x04000000 /* don't do define_split's */
289 #define MASK_DEBUG_E 0x02000000 /* function_arg debug */
290 #define MASK_DEBUG_F 0x01000000 /* don't try to suppress load nop's */
291 #define MASK_DEBUG_G 0x00800000 /* don't support 64 bit arithmetic */
292 #define MASK_DEBUG_H 0x00400000 /* allow ints in FP registers */
293 #define MASK_DEBUG_I 0x00200000 /* unused */
294 #define MASK_DEBUG_J 0x00100000 /* unused */
296 /* r4000 64 bit sizes */
297 #define TARGET_INT64 (target_flags & MASK_INT64)
298 #define TARGET_LONG64 (target_flags & MASK_LONG64)
299 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
300 #define TARGET_64BIT (target_flags & MASK_64BIT)
302 /* Mips vs. GNU assembler */
303 #define TARGET_GAS (target_flags & MASK_GAS)
304 #define TARGET_UNIX_ASM (!TARGET_GAS)
305 #define TARGET_MIPS_AS TARGET_UNIX_ASM
308 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
309 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
310 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
311 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
312 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
313 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
314 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
315 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
316 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
317 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
318 #define TARGET_DEBUG_J_MODE (target_flags & MASK_DEBUG_J)
320 /* Reg. Naming in .s ($21 vs. $a0) */
321 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
323 /* Optimize for Sdata/Sbss */
324 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
326 /* print program statistics */
327 #define TARGET_STATS (target_flags & MASK_STATS)
329 /* call memcpy instead of inline code */
330 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
332 /* .abicalls, etc from Pyramid V.4 */
333 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
335 /* OSF pic references to externs */
336 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
338 /* software floating point */
339 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
340 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
342 /* always call through a register */
343 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
345 /* generate embedded PIC code;
347 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
349 /* for embedded systems, optimize for
350 reduced RAM space instead of for
352 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
354 /* generate big endian code. */
355 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
357 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
358 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
360 #define TARGET_MAD (target_flags & MASK_MAD)
362 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
364 /* Macro to define tables used to set the flags.
365 This is a list in braces of pairs in braces,
366 each pair being { "NAME", VALUE }
367 where VALUE is the bits to set or minus the bits to clear.
368 An empty string NAME is used to identify the default VALUE. */
370 #define TARGET_SWITCHES \
372 {"int64", MASK_INT64 | MASK_LONG64}, \
373 {"long64", MASK_LONG64}, \
374 {"mips-as", -MASK_GAS}, \
376 {"rnames", MASK_NAME_REGS}, \
377 {"no-rnames", -MASK_NAME_REGS}, \
378 {"gpOPT", MASK_GPOPT}, \
379 {"gpopt", MASK_GPOPT}, \
380 {"no-gpOPT", -MASK_GPOPT}, \
381 {"no-gpopt", -MASK_GPOPT}, \
382 {"stats", MASK_STATS}, \
383 {"no-stats", -MASK_STATS}, \
384 {"memcpy", MASK_MEMCPY}, \
385 {"no-memcpy", -MASK_MEMCPY}, \
386 {"mips-tfile", MASK_MIPS_TFILE}, \
387 {"no-mips-tfile", -MASK_MIPS_TFILE}, \
388 {"soft-float", MASK_SOFT_FLOAT}, \
389 {"hard-float", -MASK_SOFT_FLOAT}, \
390 {"fp64", MASK_FLOAT64}, \
391 {"fp32", -MASK_FLOAT64}, \
392 {"gp64", MASK_64BIT}, \
393 {"gp32", -MASK_64BIT}, \
394 {"abicalls", MASK_ABICALLS}, \
395 {"no-abicalls", -MASK_ABICALLS}, \
396 {"half-pic", MASK_HALF_PIC}, \
397 {"no-half-pic", -MASK_HALF_PIC}, \
398 {"long-calls", MASK_LONG_CALLS}, \
399 {"no-long-calls", -MASK_LONG_CALLS}, \
400 {"embedded-pic", MASK_EMBEDDED_PIC}, \
401 {"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
402 {"embedded-data", MASK_EMBEDDED_DATA}, \
403 {"no-embedded-data", -MASK_EMBEDDED_DATA}, \
404 {"eb", MASK_BIG_ENDIAN}, \
405 {"el", -MASK_BIG_ENDIAN}, \
406 {"single-float", MASK_SINGLE_FLOAT}, \
407 {"double-float", -MASK_SINGLE_FLOAT}, \
409 {"no-mad", -MASK_MAD}, \
410 {"fix4300", MASK_4300_MUL_FIX}, \
411 {"no-fix4300", -MASK_4300_MUL_FIX}, \
412 {"4650", MASK_MAD | MASK_SINGLE_FLOAT}, \
413 {"debug", MASK_DEBUG}, \
414 {"debuga", MASK_DEBUG_A}, \
415 {"debugb", MASK_DEBUG_B}, \
416 {"debugc", MASK_DEBUG_C}, \
417 {"debugd", MASK_DEBUG_D}, \
418 {"debuge", MASK_DEBUG_E}, \
419 {"debugf", MASK_DEBUG_F}, \
420 {"debugg", MASK_DEBUG_G}, \
421 {"debugh", MASK_DEBUG_H}, \
422 {"debugi", MASK_DEBUG_I}, \
423 {"debugj", MASK_DEBUG_J}, \
424 {"", (TARGET_DEFAULT \
425 | TARGET_CPU_DEFAULT \
426 | TARGET_ENDIAN_DEFAULT)} \
429 /* Default target_flags if no switches are specified */
431 #ifndef TARGET_DEFAULT
432 #define TARGET_DEFAULT 0
435 #ifndef TARGET_CPU_DEFAULT
436 #define TARGET_CPU_DEFAULT 0
439 #ifndef TARGET_ENDIAN_DEFAULT
441 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
443 #define TARGET_ENDIAN_DEFAULT 0
447 #ifndef MULTILIB_DEFAULTS
448 #if TARGET_ENDIAN_DEFAULT == 0
449 #define MULTILIB_DEFAULTS { "EL", "mips1" }
451 #define MULTILIB_DEFAULTS { "EB", "mips1" }
455 /* We must pass -EL to the linker by default for little endian embedded
456 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
457 linker will default to using big-endian output files. The OUTPUT_FORMAT
458 line must be in the linker script, otherwise -EB/-EL will not work. */
460 #ifndef LINKER_ENDIAN_SPEC
461 #if TARGET_ENDIAN_DEFAULT == 0
462 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
464 #define LINKER_ENDIAN_SPEC ""
468 /* This macro is similar to `TARGET_SWITCHES' but defines names of
469 command options that have values. Its definition is an
470 initializer with a subgrouping for each command option.
472 Each subgrouping contains a string constant, that defines the
473 fixed part of the option name, and the address of a variable.
474 The variable, type `char *', is set to the variable part of the
475 given option if the fixed part matches. The actual option name
476 is made by appending `-m' to the specified name.
478 Here is an example which defines `-mshort-data-NUMBER'. If the
479 given option is `-mshort-data-512', the variable `m88k_short_data'
480 will be set to the string `"512"'.
482 extern char *m88k_short_data;
483 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
485 #define TARGET_OPTIONS \
487 SUBTARGET_TARGET_OPTIONS \
488 { "cpu=", &mips_cpu_string }, \
489 { "ips", &mips_isa_string } \
492 /* This is meant to be redefined in the host dependent files. */
493 #define SUBTARGET_TARGET_OPTIONS
495 /* Macros to decide whether certain features are available or not,
496 depending on the instruction set architecture level. */
498 #define BRANCH_LIKELY_P() (mips_isa >= 2)
499 #define HAVE_SQRT_P() (mips_isa >= 2)
501 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
502 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
503 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
504 target_flags, and -mgp64 sets MASK_64BIT.
506 Setting MASK_64BIT in target_flags will cause gcc to assume that
507 registers are 64 bits wide. int, long and void * will be 32 bit;
508 this may be changed with -mint64 or -mlong64.
510 The gen* programs link code that refers to MASK_64BIT. They don't
511 actually use the information in target_flags; they just refer to
514 /* Switch Recognition by gcc.c. Add -G xx support */
516 #ifdef SWITCH_TAKES_ARG
517 #undef SWITCH_TAKES_ARG
520 #define SWITCH_TAKES_ARG(CHAR) \
521 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
523 /* Sometimes certain combinations of command options do not make sense
524 on a particular target machine. You can define a macro
525 `OVERRIDE_OPTIONS' to take account of this. This macro, if
526 defined, is executed once just after all the command options have
529 On the MIPS, it is used to handle -G. We also use it to set up all
530 of the tables referenced in the other macros. */
532 #define OVERRIDE_OPTIONS override_options ()
534 /* Zero or more C statements that may conditionally modify two
535 variables `fixed_regs' and `call_used_regs' (both of type `char
536 []') after they have been initialized from the two preceding
539 This is necessary in case the fixed or call-clobbered registers
540 depend on target flags.
542 You need not define this macro if it has no work to do.
544 If the usage of an entire class of registers depends on the target
545 flags, you may indicate this to GCC by using this macro to modify
546 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
547 the classes which should not be used by GCC. Also define the macro
548 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
549 letter for a class that shouldn't be used.
551 (However, if this class is not included in `GENERAL_REGS' and all
552 of the insn patterns whose constraints permit this class are
553 controlled by target switches, then GCC will automatically avoid
554 using these registers when the target switches are opposed to
557 #define CONDITIONAL_REGISTER_USAGE \
560 if (!TARGET_HARD_FLOAT) \
564 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
565 fixed_regs[regno] = call_used_regs[regno] = 1; \
566 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
567 fixed_regs[regno] = call_used_regs[regno] = 1; \
569 else if (mips_isa < 4) \
573 /* We only have a single condition code register. We \
574 implement this by hiding all the condition code registers, \
575 and generating RTL that refers directly to ST_REG_FIRST. */ \
576 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
577 fixed_regs[regno] = call_used_regs[regno] = 1; \
579 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
583 /* This is meant to be redefined in the host dependent files. */
584 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
586 /* Show we can debug even without a frame pointer. */
587 #define CAN_DEBUG_WITHOUT_FP
589 /* Complain about missing specs and predefines that should be defined in each
590 of the target tm files to override the defaults. This is mostly a place-
591 holder until I can get each of the files updated [mm]. */
593 #if defined(OSF_OS) \
594 || defined(DECSTATION) \
595 || defined(SGI_TARGET) \
596 || defined(MIPS_NEWS) \
597 || defined(MIPS_SYSV) \
598 || defined(MIPS_SVR4) \
599 || defined(MIPS_BSD43)
601 #ifndef CPP_PREDEFINES
602 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
606 #error "Define LIB_SPEC in the appropriate tm.h file"
609 #ifndef STARTFILE_SPEC
610 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
614 #error "Define MACHINE_TYPE in the appropriate tm.h file"
618 /* Tell collect what flags to pass to nm. */
620 #define NM_FLAGS "-Bp"
624 /* Names to predefine in the preprocessor for this target machine. */
626 #ifndef CPP_PREDEFINES
627 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
628 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
629 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
632 /* Assembler specs. */
634 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
637 #define MIPS_AS_ASM_SPEC "\
638 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
639 %{pipe: %e-pipe is not supported.} \
640 %{K} %(subtarget_mips_as_asm_spec)"
642 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
643 rather than gas. It may be overridden by subtargets. */
645 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
646 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
649 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
652 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{v}"
654 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
655 GAS_ASM_SPEC as the default, depending upon the value of
658 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
661 #define TARGET_ASM_SPEC "\
662 %{mmips-as: %(mips_as_asm_spec)} \
663 %{!mmips-as: %(gas_asm_spec)}"
667 #define TARGET_ASM_SPEC "\
668 %{!mgas: %(mips_as_asm_spec)} \
669 %{mgas: %(gas_asm_spec)}"
673 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
674 to the assembler. It may be overridden by subtargets. */
675 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
676 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
678 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
681 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
682 the assembler. It may be overridden by subtargets. */
683 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
684 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
685 %{g} %{g0} %{g1} %{g2} %{g3} \
686 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
687 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
688 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
689 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
692 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
693 overridden by subtargets. */
695 #ifndef SUBTARGET_ASM_SPEC
696 #define SUBTARGET_ASM_SPEC ""
699 /* ASM_SPEC is the set of arguments to pass to the assembler. */
702 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
703 %(subtarget_asm_optimizing_spec) \
704 %(subtarget_asm_debugging_spec) \
706 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
708 %(subtarget_asm_spec)"
710 /* Specify to run a post-processor, mips-tfile after the assembler
711 has run to stuff the mips debug information into the object file.
712 This is needed because the $#!%^ MIPS assembler provides no way
713 of specifying such information in the assembly file. If we are
714 cross compiling, disable mips-tfile unless the user specifies
717 #ifndef ASM_FINAL_SPEC
718 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
720 #define ASM_FINAL_SPEC "\
721 %{mmips-as: %{!mno-mips-tfile: \
722 \n mips-tfile %{v*: -v} \
724 %{!K: %{save-temps: -I %b.o~}} \
725 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
726 %{.s:%i} %{!.s:%g.s}}}"
730 #define ASM_FINAL_SPEC "\
731 %{!mgas: %{!mno-mips-tfile: \
732 \n mips-tfile %{v*: -v} \
734 %{!K: %{save-temps: -I %b.o~}} \
735 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
736 %{.s:%i} %{!.s:%g.s}}}"
739 #endif /* ASM_FINAL_SPEC */
741 /* Redefinition of libraries used. Mips doesn't support normal
742 UNIX style profiling via calling _mcount. It does offer
743 profiling that samples the PC, so do what we can... */
746 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
749 /* Extra switches sometimes passed to the linker. */
750 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
751 will interpret it as a -b option. */
755 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
756 %{bestGnum} %{shared} %{non_shared} \
757 %(linker_endian_spec)"
758 #endif /* LINK_SPEC defined */
760 /* Specs for the compiler proper */
764 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
765 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
766 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
767 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
768 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
769 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
770 %{m4650:-mcpu=r4650} \
771 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
772 %{pic-none: -mno-half-pic} \
773 %{pic-lib: -mhalf-pic} \
774 %{pic-extern: -mhalf-pic} \
775 %{pic-calls: -mhalf-pic} \
779 /* Preprocessor specs. */
781 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
782 be overridden by subtargets. */
784 #ifndef SUBTARGET_CPP_SIZE_SPEC
785 #define SUBTARGET_CPP_SIZE_SPEC "\
786 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
787 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
790 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
791 overridden by subtargets. */
792 #ifndef SUBTARGET_CPP_SPEC
793 #define SUBTARGET_CPP_SPEC ""
796 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
800 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
801 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
802 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
803 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
804 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
805 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
806 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
807 %(subtarget_cpp_size_spec) \
808 %{mips3:-U__mips -D__mips=3 -D__mips64} \
809 %{mips4:-U__mips -D__mips=4 -D__mips64} \
810 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
811 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
812 %{m4650:%{!msoft-float:-D__mips_single_float}} \
813 %{msoft-float:-D__mips_soft_float} \
814 %{mabi=eabi:-D__mips_eabi} \
815 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
816 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
817 %(subtarget_cpp_spec) "
820 /* This macro defines names of additional specifications to put in the specs
821 that can be used in various specifications like CC1_SPEC. Its definition
822 is an initializer with a subgrouping for each command option.
824 Each subgrouping contains a string constant, that defines the
825 specification name, and a string constant that used by the GNU CC driver
828 Do not define this macro if it does not need to do anything. */
830 #define EXTRA_SPECS \
831 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
832 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
833 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
834 { "gas_asm_spec", GAS_ASM_SPEC }, \
835 { "target_asm_spec", TARGET_ASM_SPEC }, \
836 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
837 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
838 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
839 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
840 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
841 SUBTARGET_EXTRA_SPECS
843 #ifndef SUBTARGET_EXTRA_SPECS
844 #define SUBTARGET_EXTRA_SPECS
847 /* If defined, this macro is an additional prefix to try after
848 `STANDARD_EXEC_PREFIX'. */
850 #ifndef MD_EXEC_PREFIX
851 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
854 #ifndef MD_STARTFILE_PREFIX
855 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
859 /* Print subsidiary information on the compiler version in use. */
861 #define MIPS_VERSION "[AL 1.1, MM 40]"
864 #define MACHINE_TYPE "BSD Mips"
867 #ifndef TARGET_VERSION_INTERNAL
868 #define TARGET_VERSION_INTERNAL(STREAM) \
869 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
872 #ifndef TARGET_VERSION
873 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
877 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
878 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
879 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
881 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
882 #define PREFERRED_DEBUGGING_TYPE ((!strncmp (str, "ggdb", 4)) ? DBX_DEBUG : SDB_DEBUG)
885 /* By default, turn on GDB extensions. */
886 #define DEFAULT_GDB_EXTENSIONS 1
888 /* If we are passing smuggling stabs through the MIPS ECOFF object
889 format, put a comment in front of the .stab<x> operation so
890 that the MIPS assembler does not choke. The mips-tfile program
891 will correctly put the stab into the object file. */
893 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
894 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
895 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
897 /* Local compiler-generated symbols must have a prefix that the assembler
898 understands. By default, this is $, although some targets (e.g.,
899 NetBSD-ELF) need to override this. */
901 #ifndef LOCAL_LABEL_PREFIX
902 #define LOCAL_LABEL_PREFIX "$"
905 /* By default on the mips, external symbols do not have an underscore
906 prepended, but some targets (e.g., NetBSD) require this. */
908 #ifndef USER_LABEL_PREFIX
909 #define USER_LABEL_PREFIX ""
912 /* Forward references to tags are allowed. */
913 #define SDB_ALLOW_FORWARD_REFERENCES
915 /* Unknown tags are also allowed. */
916 #define SDB_ALLOW_UNKNOWN_REFERENCES
918 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
919 since the length can run past this up to a continuation point. */
920 #define DBX_CONTIN_LENGTH 1500
922 /* How to renumber registers for dbx and gdb. */
923 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
925 /* The mapping from gcc register number to DWARF 2 CFA column number.
926 This mapping does not allow for tracking DBX register 0, since column 0
927 is used for the frame address, but since register 0 is fixed this is
928 not really a problem. */
929 #define DWARF_FRAME_REGNUM(REG) \
930 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN \
931 : DBX_REGISTER_NUMBER (REG))
933 /* The DWARF 2 CFA column which tracks the return address. */
934 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
936 /* Before the prologue, RA lives in r31. */
937 #define INCOMING_RETURN_ADDR_RTX gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
939 /* Overrides for the COFF debug format. */
940 #define PUT_SDB_SCL(a) \
942 extern FILE *asm_out_text_file; \
943 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
946 #define PUT_SDB_INT_VAL(a) \
948 extern FILE *asm_out_text_file; \
949 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
952 #define PUT_SDB_VAL(a) \
954 extern FILE *asm_out_text_file; \
955 fputs ("\t.val\t", asm_out_text_file); \
956 output_addr_const (asm_out_text_file, (a)); \
957 fputc (';', asm_out_text_file); \
960 #define PUT_SDB_DEF(a) \
962 extern FILE *asm_out_text_file; \
963 fprintf (asm_out_text_file, "\t%s.def\t", \
964 (TARGET_GAS) ? "" : "#"); \
965 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
966 fputc (';', asm_out_text_file); \
969 #define PUT_SDB_PLAIN_DEF(a) \
971 extern FILE *asm_out_text_file; \
972 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
973 (TARGET_GAS) ? "" : "#", (a)); \
976 #define PUT_SDB_ENDEF \
978 extern FILE *asm_out_text_file; \
979 fprintf (asm_out_text_file, "\t.endef\n"); \
982 #define PUT_SDB_TYPE(a) \
984 extern FILE *asm_out_text_file; \
985 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
988 #define PUT_SDB_SIZE(a) \
990 extern FILE *asm_out_text_file; \
991 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
994 #define PUT_SDB_DIM(a) \
996 extern FILE *asm_out_text_file; \
997 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1000 #ifndef PUT_SDB_START_DIM
1001 #define PUT_SDB_START_DIM \
1003 extern FILE *asm_out_text_file; \
1004 fprintf (asm_out_text_file, "\t.dim\t"); \
1008 #ifndef PUT_SDB_NEXT_DIM
1009 #define PUT_SDB_NEXT_DIM(a) \
1011 extern FILE *asm_out_text_file; \
1012 fprintf (asm_out_text_file, "%d,", a); \
1016 #ifndef PUT_SDB_LAST_DIM
1017 #define PUT_SDB_LAST_DIM(a) \
1019 extern FILE *asm_out_text_file; \
1020 fprintf (asm_out_text_file, "%d;", a); \
1024 #define PUT_SDB_TAG(a) \
1026 extern FILE *asm_out_text_file; \
1027 fprintf (asm_out_text_file, "\t.tag\t"); \
1028 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1029 fputc (';', asm_out_text_file); \
1032 /* For block start and end, we create labels, so that
1033 later we can figure out where the correct offset is.
1034 The normal .ent/.end serve well enough for functions,
1035 so those are just commented out. */
1037 #define PUT_SDB_BLOCK_START(LINE) \
1039 extern FILE *asm_out_text_file; \
1040 fprintf (asm_out_text_file, \
1041 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1042 LOCAL_LABEL_PREFIX, \
1044 (TARGET_GAS) ? "" : "#", \
1045 LOCAL_LABEL_PREFIX, \
1048 sdb_label_count++; \
1051 #define PUT_SDB_BLOCK_END(LINE) \
1053 extern FILE *asm_out_text_file; \
1054 fprintf (asm_out_text_file, \
1055 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1056 LOCAL_LABEL_PREFIX, \
1058 (TARGET_GAS) ? "" : "#", \
1059 LOCAL_LABEL_PREFIX, \
1062 sdb_label_count++; \
1065 #define PUT_SDB_FUNCTION_START(LINE)
1067 #define PUT_SDB_FUNCTION_END(LINE) \
1069 extern FILE *asm_out_text_file; \
1070 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1073 #define PUT_SDB_EPILOGUE_END(NAME)
1075 #define PUT_SDB_SRC_FILE(FILENAME) \
1077 extern FILE *asm_out_text_file; \
1078 output_file_directive (asm_out_text_file, (FILENAME)); \
1081 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1082 sprintf ((BUFFER), ".%dfake", (NUMBER));
1084 /* Correct the offset of automatic variables and arguments. Note that
1085 the MIPS debug format wants all automatic variables and arguments
1086 to be in terms of the virtual frame pointer (stack pointer before
1087 any adjustment in the function), while the MIPS 3.0 linker wants
1088 the frame pointer to be the stack pointer after the initial
1091 #define DEBUGGER_AUTO_OFFSET(X) mips_debugger_offset (X, 0)
1092 #define DEBUGGER_ARG_OFFSET(OFFSET, X) mips_debugger_offset (X, OFFSET)
1095 /* Tell collect that the object format is ECOFF */
1096 #ifndef OBJECT_FORMAT_ROSE
1097 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1098 #define EXTENDED_COFF /* ECOFF, not normal coff */
1101 #if 0 /* These definitions normally have no effect because
1102 MIPS systems define USE_COLLECT2, so
1103 assemble_constructor does nothing anyway. */
1105 /* Don't use the default definitions, because we don't have gld.
1106 Also, we don't want stabs when generating ECOFF output.
1107 Instead we depend on collect to handle these. */
1109 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1110 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1114 /* Target machine storage layout */
1116 /* Define in order to support both big and little endian float formats
1117 in the same gcc binary. */
1118 #define REAL_ARITHMETIC
1120 /* Define this if most significant bit is lowest numbered
1121 in instructions that operate on numbered bit-fields.
1123 #define BITS_BIG_ENDIAN 0
1125 /* Define this if most significant byte of a word is the lowest numbered. */
1126 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1128 /* Define this if most significant word of a multiword number is the lowest. */
1129 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1131 /* Define this to set the endianness to use in libgcc2.c, which can
1132 not depend on target_flags. */
1133 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1134 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1136 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1139 /* Number of bits in an addressable storage unit */
1140 #define BITS_PER_UNIT 8
1142 /* Width in bits of a "word", which is the contents of a machine register.
1143 Note that this is not necessarily the width of data type `int';
1144 if using 16-bit ints on a 68000, this would still be 32.
1145 But on a machine with 16-bit registers, this would be 16. */
1146 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1147 #define MAX_BITS_PER_WORD 64
1149 /* Width of a word, in units (bytes). */
1150 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1151 #define MIN_UNITS_PER_WORD 4
1153 /* For MIPS, width of a floating point register. */
1154 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1156 /* A C expression for the size in bits of the type `int' on the
1157 target machine. If you don't define this, the default is one
1159 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1160 #define MAX_INT_TYPE_SIZE 64
1162 /* Tell the preprocessor the maximum size of wchar_t. */
1163 #ifndef MAX_WCHAR_TYPE_SIZE
1164 #ifndef WCHAR_TYPE_SIZE
1165 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1169 /* A C expression for the size in bits of the type `short' on the
1170 target machine. If you don't define this, the default is half a
1171 word. (If this would be less than one storage unit, it is
1172 rounded up to one unit.) */
1173 #define SHORT_TYPE_SIZE 16
1175 /* A C expression for the size in bits of the type `long' on the
1176 target machine. If you don't define this, the default is one
1178 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1179 #define MAX_LONG_TYPE_SIZE 64
1181 /* A C expression for the size in bits of the type `long long' on the
1182 target machine. If you don't define this, the default is two
1184 #define LONG_LONG_TYPE_SIZE 64
1186 /* A C expression for the size in bits of the type `char' on the
1187 target machine. If you don't define this, the default is one
1188 quarter of a word. (If this would be less than one storage unit,
1189 it is rounded up to one unit.) */
1190 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1192 /* A C expression for the size in bits of the type `float' on the
1193 target machine. If you don't define this, the default is one
1195 #define FLOAT_TYPE_SIZE 32
1197 /* A C expression for the size in bits of the type `double' on the
1198 target machine. If you don't define this, the default is two
1200 #define DOUBLE_TYPE_SIZE 64
1202 /* A C expression for the size in bits of the type `long double' on
1203 the target machine. If you don't define this, the default is two
1205 #define LONG_DOUBLE_TYPE_SIZE 64
1207 /* Width in bits of a pointer.
1208 See also the macro `Pmode' defined below. */
1209 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1211 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1212 #define POINTER_BOUNDARY (TARGET_LONG64 ? 64 : 32)
1214 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1215 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1217 /* Allocation boundary (in *bits*) for the code of a function. */
1218 #define FUNCTION_BOUNDARY 32
1220 /* Alignment of field after `int : 0' in a structure. */
1221 #define EMPTY_FIELD_BOUNDARY 32
1223 /* Every structure's size must be a multiple of this. */
1224 /* 8 is observed right on a DECstation and on riscos 4.02. */
1225 #define STRUCTURE_SIZE_BOUNDARY 8
1227 /* There is no point aligning anything to a rounder boundary than this. */
1228 #define BIGGEST_ALIGNMENT 64
1230 /* Biggest alignment any structure field can require in bits. */
1231 #define BIGGEST_FIELD_ALIGNMENT 64
1233 /* Set this nonzero if move instructions will actually fail to work
1234 when given unaligned data. */
1235 #define STRICT_ALIGNMENT 1
1237 /* Define this if you wish to imitate the way many other C compilers
1238 handle alignment of bitfields and the structures that contain
1241 The behavior is that the type written for a bitfield (`int',
1242 `short', or other integer type) imposes an alignment for the
1243 entire structure, as if the structure really did contain an
1244 ordinary field of that type. In addition, the bitfield is placed
1245 within the structure so that it would fit within such a field,
1246 not crossing a boundary for it.
1248 Thus, on most machines, a bitfield whose type is written as `int'
1249 would not cross a four-byte boundary, and would force four-byte
1250 alignment for the whole structure. (The alignment used may not
1251 be four bytes; it is controlled by the other alignment
1254 If the macro is defined, its definition should be a C expression;
1255 a nonzero value for the expression enables this behavior. */
1257 #define PCC_BITFIELD_TYPE_MATTERS 1
1259 /* If defined, a C expression to compute the alignment given to a
1260 constant that is being placed in memory. CONSTANT is the constant
1261 and ALIGN is the alignment that the object would ordinarily have.
1262 The value of this macro is used instead of that alignment to align
1265 If this macro is not defined, then ALIGN is used.
1267 The typical use of this macro is to increase alignment for string
1268 constants to be word aligned so that `strcpy' calls that copy
1269 constants can be done inline. */
1271 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1272 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1273 && (ALIGN) < BITS_PER_WORD \
1277 /* If defined, a C expression to compute the alignment for a static
1278 variable. TYPE is the data type, and ALIGN is the alignment that
1279 the object would ordinarily have. The value of this macro is used
1280 instead of that alignment to align the object.
1282 If this macro is not defined, then ALIGN is used.
1284 One use of this macro is to increase alignment of medium-size
1285 data to make it all fit in fewer cache lines. Another is to
1286 cause character arrays to be word-aligned so that `strcpy' calls
1287 that copy constants to character arrays can be done inline. */
1289 #undef DATA_ALIGNMENT
1290 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1291 ((((ALIGN) < BITS_PER_WORD) \
1292 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1293 || TREE_CODE (TYPE) == UNION_TYPE \
1294 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1296 /* Define this macro if an argument declared as `char' or `short' in a
1297 prototype should actually be passed as an `int'. In addition to
1298 avoiding errors in certain cases of mismatch, it also makes for
1299 better code on certain machines. */
1301 #define PROMOTE_PROTOTYPES
1303 /* Define if operations between registers always perform the operation
1304 on the full register even if a narrower mode is specified. */
1305 #define WORD_REGISTER_OPERATIONS
1307 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1308 will either zero-extend or sign-extend. The value of this macro should
1309 be the code that says which one of the two operations is implicitly
1310 done, NIL if none. */
1311 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1313 /* Standard register usage. */
1315 /* Number of actual hardware registers.
1316 The hardware registers are assigned numbers for the compiler
1317 from 0 to just below FIRST_PSEUDO_REGISTER.
1318 All registers that the compiler knows about must be given numbers,
1319 even those that are not normally considered general registers.
1321 On the Mips, we have 32 integer registers, 32 floating point
1322 registers, 8 condition code registers, and the special registers
1323 hi, lo, hilo, and rap. The 8 condition code registers are only
1324 used if mips_isa >= 4. The hilo register is only used in 64 bit
1325 mode. It represents a 64 bit value stored as two 32 bit values in
1326 the hi and lo registers; this is the result of the mult
1327 instruction. rap is a pointer to the stack where the return
1328 address reg ($31) was stored. This is needed for C++ exception
1331 #define FIRST_PSEUDO_REGISTER 76
1333 /* 1 for registers that have pervasive standard uses
1334 and are not available for the register allocator.
1336 On the MIPS, see conventions, page D-2 */
1338 #define FIXED_REGISTERS \
1340 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1341 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1342 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1343 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1344 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1348 /* 1 for registers not available across function calls.
1349 These must include the FIXED_REGISTERS and also any
1350 registers that can be used without being saved.
1351 The latter must include the registers where values are returned
1352 and the register where structure-value addresses are passed.
1353 Aside from that, you can include as many other registers as you like. */
1355 #define CALL_USED_REGISTERS \
1357 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1358 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1359 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1360 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1361 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1365 /* Internal macros to classify a register number as to whether it's a
1366 general purpose register, a floating point register, a
1367 multiply/divide register, or a status register. */
1369 #define GP_REG_FIRST 0
1370 #define GP_REG_LAST 31
1371 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1372 #define GP_DBX_FIRST 0
1374 #define FP_REG_FIRST 32
1375 #define FP_REG_LAST 63
1376 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1377 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1379 #define MD_REG_FIRST 64
1380 #define MD_REG_LAST 66
1381 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1383 #define ST_REG_FIRST 67
1384 #define ST_REG_LAST 74
1385 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1387 #define RAP_REG_NUM 75
1389 #define AT_REGNUM (GP_REG_FIRST + 1)
1390 #define HI_REGNUM (MD_REG_FIRST + 0)
1391 #define LO_REGNUM (MD_REG_FIRST + 1)
1392 #define HILO_REGNUM (MD_REG_FIRST + 2)
1394 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1395 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1396 should be used instead. */
1397 #define FPSW_REGNUM ST_REG_FIRST
1399 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1400 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1401 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1402 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1404 /* Return number of consecutive hard regs needed starting at reg REGNO
1405 to hold something of mode MODE.
1406 This is ordinarily the length in words of a value of mode MODE
1407 but can be less for certain modes in special long registers.
1409 On the MIPS, all general registers are one word long. Except on
1410 the R4000 with the FR bit set, the floating point uses register
1411 pairs, with the second register not being allocatable. */
1413 #define HARD_REGNO_NREGS(REGNO, MODE) \
1414 (! FP_REG_P (REGNO) \
1415 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1416 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1418 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1419 MODE. In 32 bit mode, require that DImode and DFmode be in even
1420 registers. For DImode, this makes some of the insns easier to
1421 write, since you don't have to worry about a DImode value in
1422 registers 3 & 4, producing a result in 4 & 5.
1424 To make the code simpler HARD_REGNO_MODE_OK now just references an
1425 array built in override_options. Because machmodes.h is not yet
1426 included before this file is processed, the MODE bound can't be
1429 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1431 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1432 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1434 /* Value is 1 if it is a good idea to tie two pseudo registers
1435 when one has mode MODE1 and one has mode MODE2.
1436 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1437 for any hard reg, then this must be 0 for correct output. */
1438 #define MODES_TIEABLE_P(MODE1, MODE2) \
1439 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1440 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1441 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1442 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1444 /* MIPS pc is not overloaded on a register. */
1445 /* #define PC_REGNUM xx */
1447 /* Register to use for pushing function arguments. */
1448 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1450 /* Offset from the stack pointer to the first available location. */
1451 #define STACK_POINTER_OFFSET 0
1453 /* Base register for access to local variables of the function. */
1454 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 30)
1456 /* Value should be nonzero if functions must have frame pointers.
1457 Zero means the frame pointer need not be set up (and parms
1458 may be accessed via the stack pointer) in functions that seem suitable.
1459 This is computed in `reload', in reload1.c. */
1460 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1462 /* Base register for access to arguments of the function. */
1463 #define ARG_POINTER_REGNUM GP_REG_FIRST
1465 /* Fake register that holds the address on the stack of the
1466 current function's return address. */
1467 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1469 /* Register in which static-chain is passed to a function. */
1470 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1472 /* If the structure value address is passed in a register, then
1473 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1474 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1476 /* If the structure value address is not passed in a register, define
1477 `STRUCT_VALUE' as an expression returning an RTX for the place
1478 where the address is passed. If it returns 0, the address is
1479 passed as an "invisible" first argument. */
1480 #define STRUCT_VALUE 0
1482 /* Mips registers used in prologue/epilogue code when the stack frame
1483 is larger than 32K bytes. These registers must come from the
1484 scratch register set, and not used for passing and returning
1485 arguments and any other information used in the calling sequence
1486 (such as pic). Must start at 12, since t0/t3 are parameter passing
1487 registers in the 64 bit ABI. */
1489 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1490 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1492 /* Define this macro if it is as good or better to call a constant
1493 function address than to call an address kept in a register. */
1494 #define NO_FUNCTION_CSE 1
1496 /* Define this macro if it is as good or better for a function to
1497 call itself with an explicit address than to call an address
1498 kept in a register. */
1499 #define NO_RECURSIVE_FUNCTION_CSE 1
1501 /* The register number of the register used to address a table of
1502 static data addresses in memory. In some cases this register is
1503 defined by a processor's "application binary interface" (ABI).
1504 When this macro is defined, RTL is generated for this register
1505 once, as with the stack pointer and frame pointer registers. If
1506 this macro is not defined, it is up to the machine-dependent
1507 files to allocate such a register (if necessary). */
1508 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1510 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1512 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1513 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1514 isn't always called for static inline functions. */
1515 #define INIT_EXPANDERS embedded_pic_fnaddr_rtx = NULL;
1517 /* Define the classes of registers for register constraints in the
1518 machine description. Also define ranges of constants.
1520 One of the classes must always be named ALL_REGS and include all hard regs.
1521 If there is more than one class, another class must be named NO_REGS
1522 and contain no registers.
1524 The name GENERAL_REGS must be the name of a class (or an alias for
1525 another name such as ALL_REGS). This is the class of registers
1526 that is allowed by "g" or "r" in a register constraint.
1527 Also, registers outside this class are allocated only when
1528 instructions express preferences for them.
1530 The classes must be numbered in nondecreasing order; that is,
1531 a larger-numbered class must never be contained completely
1532 in a smaller-numbered class.
1534 For any two classes, it is very desirable that there be another
1535 class that represents their union. */
1539 NO_REGS, /* no registers in set */
1540 GR_REGS, /* integer registers */
1541 FP_REGS, /* floating point registers */
1542 HI_REG, /* hi register */
1543 LO_REG, /* lo register */
1544 HILO_REG, /* hilo register pair for 64 bit mode mult */
1545 MD_REGS, /* multiply/divide registers (hi/lo) */
1546 ST_REGS, /* status registers (fp status) */
1547 ALL_REGS, /* all registers */
1548 LIM_REG_CLASSES /* max value + 1 */
1551 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1553 #define GENERAL_REGS GR_REGS
1555 /* An initializer containing the names of the register classes as C
1556 string constants. These names are used in writing some of the
1559 #define REG_CLASS_NAMES \
1572 /* An initializer containing the contents of the register classes,
1573 as integers which are bit masks. The Nth integer specifies the
1574 contents of class N. The way the integer MASK is interpreted is
1575 that register R is in the class if `MASK & (1 << R)' is 1.
1577 When the machine has more than 32 registers, an integer does not
1578 suffice. Then the integers are replaced by sub-initializers,
1579 braced groupings containing several integers. Each
1580 sub-initializer must be suitable as an initializer for the type
1581 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1583 #define REG_CLASS_CONTENTS \
1585 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1586 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1587 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1588 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1589 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1590 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1591 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1592 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1593 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1597 /* A C expression whose value is a register class containing hard
1598 register REGNO. In general there is more that one such class;
1599 choose a class which is "minimal", meaning that no smaller class
1600 also contains the register. */
1602 extern enum reg_class mips_regno_to_class[];
1604 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1606 /* A macro whose definition is the name of the class to which a
1607 valid base register must belong. A base register is one used in
1608 an address which is the register value plus a displacement. */
1610 #define BASE_REG_CLASS GR_REGS
1612 /* A macro whose definition is the name of the class to which a
1613 valid index register must belong. An index register is one used
1614 in an address where its value is either multiplied by a scale
1615 factor or added to another register (as well as added to a
1618 #define INDEX_REG_CLASS NO_REGS
1621 /* REGISTER AND CONSTANT CLASSES */
1623 /* Get reg_class from a letter such as appears in the machine
1626 DEFINED REGISTER CLASSES:
1628 'd' General (aka integer) registers
1629 'f' Floating point registers
1632 'x' Multiply/divide registers
1634 'z' FP Status register
1635 'b' All registers */
1637 extern enum reg_class mips_char_to_class[];
1639 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1641 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1642 string can be used to stand for particular ranges of immediate
1643 operands. This macro defines what the ranges are. C is the
1644 letter, and VALUE is a constant value. Return 1 if VALUE is
1645 in the range specified by C. */
1649 `I' is used for the range of constants an arithmetic insn can
1650 actually contain (16 bits signed integers).
1652 `J' is used for the range which is just zero (ie, $r0).
1654 `K' is used for the range of constants a logical insn can actually
1655 contain (16 bit zero-extended integers).
1657 `L' is used for the range of constants that be loaded with lui
1658 (ie, the bottom 16 bits are zero).
1660 `M' is used for the range of constants that take two words to load
1661 (ie, not matched by `I', `K', and `L').
1663 `N' is used for negative 16 bit constants.
1665 `O' is an exact power of 2 (not yet used in the md file).
1667 `P' is used for positive 16 bit constants. */
1669 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1670 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1672 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1673 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1674 : (C) == 'J' ? ((VALUE) == 0) \
1675 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1676 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1677 && (((VALUE) & ~2147483647) == 0 \
1678 || ((VALUE) & ~2147483647) == ~2147483647)) \
1679 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1680 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1681 && (((VALUE) & 0x0000ffff) != 0 \
1682 || (((VALUE) & ~2147483647) != 0 \
1683 && ((VALUE) & ~2147483647) != ~2147483647))) \
1684 : (C) == 'N' ? (((VALUE) & ~0x0000ffff) == ~0x0000ffff) \
1685 : (C) == 'O' ? (exact_log2 (VALUE) >= 0) \
1686 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1689 /* Similar, but for floating constants, and defining letters G and H.
1690 Here VALUE is the CONST_DOUBLE rtx itself. */
1694 'G' : Floating point 0 */
1696 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1698 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1700 /* Letters in the range `Q' through `U' may be defined in a
1701 machine-dependent fashion to stand for arbitrary operand types.
1702 The machine description macro `EXTRA_CONSTRAINT' is passed the
1703 operand as its first argument and the constraint letter as its
1706 `Q' is for memory references which take more than 1 instruction.
1707 `R' is for memory references which take 1 word for the instruction.
1708 `S' is for references to extern items which are PIC for OSF/rose. */
1710 #define EXTRA_CONSTRAINT(OP,CODE) \
1711 ((GET_CODE (OP) != MEM) ? FALSE \
1712 : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \
1713 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1714 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1715 && HALF_PIC_ADDRESS_P (OP)) \
1718 /* Given an rtx X being reloaded into a reg required to be
1719 in class CLASS, return the class of reg to actually use.
1720 In general this is just CLASS; but on some machines
1721 in some cases it is preferable to use a more restrictive class. */
1723 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1724 ((CLASS) != ALL_REGS \
1726 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1727 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1728 ? (TARGET_SOFT_FLOAT ? GR_REGS : FP_REGS) \
1729 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1730 || GET_MODE (X) == VOIDmode) \
1734 /* Certain machines have the property that some registers cannot be
1735 copied to some other registers without using memory. Define this
1736 macro on those machines to be a C expression that is non-zero if
1737 objects of mode MODE in registers of CLASS1 can only be copied to
1738 registers of class CLASS2 by storing a register of CLASS1 into
1739 memory and loading that memory location into a register of CLASS2.
1741 Do not define this macro if its value would always be zero. */
1743 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1744 ((!TARGET_DEBUG_H_MODE \
1745 && GET_MODE_CLASS (MODE) == MODE_INT \
1746 && ((CLASS1 == FP_REGS && CLASS2 == GR_REGS) \
1747 || (CLASS1 == GR_REGS && CLASS2 == FP_REGS))) \
1748 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1749 && ((CLASS1 == GR_REGS && CLASS2 == FP_REGS) \
1750 || (CLASS2 == GR_REGS && CLASS1 == FP_REGS))))
1752 /* The HI and LO registers can only be reloaded via the general
1753 registers. Condition code registers can only be loaded to the
1754 general registers, and from the floating point registers. */
1756 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1757 mips_secondary_reload_class (CLASS, MODE, X, 1)
1758 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1759 mips_secondary_reload_class (CLASS, MODE, X, 0)
1761 /* Not declared above, with the other functions, because enum
1762 reg_class is not declared yet. */
1763 extern enum reg_class mips_secondary_reload_class ();
1765 /* Return the maximum number of consecutive registers
1766 needed to represent mode MODE in a register of class CLASS. */
1768 #define CLASS_UNITS(mode, size) \
1769 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1771 #define CLASS_MAX_NREGS(CLASS, MODE) \
1772 ((CLASS) == FP_REGS \
1774 ? CLASS_UNITS (MODE, 8) \
1775 : 2 * CLASS_UNITS (MODE, 8)) \
1776 : CLASS_UNITS (MODE, UNITS_PER_WORD))
1778 /* If defined, this is a C expression whose value should be
1779 nonzero if the insn INSN has the effect of mysteriously
1780 clobbering the contents of hard register number REGNO. By
1781 "mysterious" we mean that the insn's RTL expression doesn't
1782 describe such an effect.
1784 If this macro is not defined, it means that no insn clobbers
1785 registers mysteriously. This is the usual situation; all else
1786 being equal, it is best for the RTL expression to show all the
1789 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
1792 /* Stack layout; function entry, exit and calling. */
1794 /* Define this if pushing a word on the stack
1795 makes the stack pointer a smaller address. */
1796 #define STACK_GROWS_DOWNWARD
1798 /* Define this if the nominal address of the stack frame
1799 is at the high-address end of the local variables;
1800 that is, each additional local variable allocated
1801 goes at a more negative offset in the frame. */
1802 /* #define FRAME_GROWS_DOWNWARD */
1804 /* Offset within stack frame to start allocating local variables at.
1805 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1806 first local allocated. Otherwise, it is the offset to the BEGINNING
1807 of the first local allocated. */
1808 #define STARTING_FRAME_OFFSET \
1809 (current_function_outgoing_args_size \
1810 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1812 /* Offset from the stack pointer register to an item dynamically
1813 allocated on the stack, e.g., by `alloca'.
1815 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1816 length of the outgoing arguments. The default is correct for most
1817 machines. See `function.c' for details.
1819 The MIPS ABI states that functions which dynamically allocate the
1820 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
1821 we are trying to create a second frame pointer to the function, so
1822 allocate some stack space to make it happy.
1824 However, the linker currently complains about linking any code that
1825 dynamically allocates stack space, and there seems to be a bug in
1826 STACK_DYNAMIC_OFFSET, so don't define this right now. */
1829 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1830 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
1831 ? 4*UNITS_PER_WORD \
1832 : current_function_outgoing_args_size)
1835 /* The return address for the current frame is in r31 is this is a leaf
1836 function. Otherwise, it is on the stack. It is at a variable offset
1837 from sp/fp/ap, so we define a fake hard register rap which is a
1838 poiner to the return address on the stack. This always gets eliminated
1839 during reload to be either the frame pointer or the stack pointer plus
1842 /* ??? This definition fails for leaf functions. There is currently no
1843 general solution for this problem. */
1845 /* ??? There appears to be no way to get the return address of any previous
1846 frame except by disassembling instructions in the prologue/epilogue.
1847 So currently we support only the current frame. */
1849 #define RETURN_ADDR_RTX(count, frame) \
1851 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
1854 /* Structure to be filled in by compute_frame_size with register
1855 save masks, and offsets for the current function. */
1857 struct mips_frame_info
1859 long total_size; /* # bytes that the entire frame takes up */
1860 long var_size; /* # bytes that variables take up */
1861 long args_size; /* # bytes that outgoing arguments take up */
1862 long extra_size; /* # bytes of extra gunk */
1863 int gp_reg_size; /* # bytes needed to store gp regs */
1864 int fp_reg_size; /* # bytes needed to store fp regs */
1865 long mask; /* mask of saved gp registers */
1866 long fmask; /* mask of saved fp registers */
1867 long gp_save_offset; /* offset from vfp to store gp registers */
1868 long fp_save_offset; /* offset from vfp to store fp registers */
1869 long gp_sp_offset; /* offset from new sp to store gp registers */
1870 long fp_sp_offset; /* offset from new sp to store fp registers */
1871 int initialized; /* != 0 if frame size already calculated */
1872 int num_gp; /* number of gp registers saved */
1873 int num_fp; /* number of fp registers saved */
1876 extern struct mips_frame_info current_frame_info;
1878 /* If defined, this macro specifies a table of register pairs used to
1879 eliminate unneeded registers that point into the stack frame. If
1880 it is not defined, the only elimination attempted by the compiler
1881 is to replace references to the frame pointer with references to
1884 The definition of this macro is a list of structure
1885 initializations, each of which specifies an original and
1886 replacement register.
1888 On some machines, the position of the argument pointer is not
1889 known until the compilation is completed. In such a case, a
1890 separate hard register must be used for the argument pointer.
1891 This register can be eliminated by replacing it with either the
1892 frame pointer or the argument pointer, depending on whether or not
1893 the frame pointer has been eliminated.
1895 In this case, you might specify:
1896 #define ELIMINABLE_REGS \
1897 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1898 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1899 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1901 Note that the elimination of the argument pointer with the stack
1902 pointer is specified first since that is the preferred elimination. */
1904 #define ELIMINABLE_REGS \
1905 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1906 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1907 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1908 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1909 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1911 /* A C expression that returns non-zero if the compiler is allowed to
1912 try to replace register number FROM-REG with register number
1913 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
1914 defined, and will usually be the constant 1, since most of the
1915 cases preventing register elimination are things that the compiler
1916 already knows about. */
1918 #define CAN_ELIMINATE(FROM, TO) \
1919 (!frame_pointer_needed \
1920 || ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1921 || ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
1922 && (TO) == FRAME_POINTER_REGNUM))
1924 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1925 specifies the initial difference between the specified pair of
1926 registers. This macro must be defined if `ELIMINABLE_REGS' is
1929 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1930 { compute_frame_size (get_frame_size ()); \
1931 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1933 else if ((FROM) == ARG_POINTER_REGNUM \
1934 && ((TO) == FRAME_POINTER_REGNUM \
1935 || (TO) == STACK_POINTER_REGNUM)) \
1936 (OFFSET) = (current_frame_info.total_size \
1937 - ((mips_abi != ABI_32 && mips_abi != ABI_EABI) \
1938 ? current_function_pretend_args_size \
1940 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
1941 && ((TO) == FRAME_POINTER_REGNUM \
1942 || (TO) == STACK_POINTER_REGNUM)) \
1943 (OFFSET) = current_frame_info.gp_sp_offset; \
1948 /* If we generate an insn to push BYTES bytes,
1949 this says how many the stack pointer really advances by.
1950 On the vax, sp@- in a byte insn really pushes a word. */
1952 /* #define PUSH_ROUNDING(BYTES) 0 */
1954 /* If defined, the maximum amount of space required for outgoing
1955 arguments will be computed and placed into the variable
1956 `current_function_outgoing_args_size'. No space will be pushed
1957 onto the stack for each call; instead, the function prologue
1958 should increase the stack frame size by this amount.
1960 It is not proper to define both `PUSH_ROUNDING' and
1961 `ACCUMULATE_OUTGOING_ARGS'. */
1962 #define ACCUMULATE_OUTGOING_ARGS
1964 /* Offset from the argument pointer register to the first argument's
1965 address. On some machines it may depend on the data type of the
1968 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
1969 the first argument's address.
1971 On the MIPS, we must skip the first argument position if we are
1972 returning a structure or a union, to account for its address being
1973 passed in $4. However, at the current time, this produces a compiler
1974 that can't bootstrap, so comment it out for now. */
1977 #define FIRST_PARM_OFFSET(FNDECL) \
1979 && TREE_TYPE (FNDECL) != 0 \
1980 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
1981 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
1982 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
1986 #define FIRST_PARM_OFFSET(FNDECL) 0
1989 /* When a parameter is passed in a register, stack space is still
1990 allocated for it. For the MIPS, stack space must be allocated, cf
1991 Asm Lang Prog Guide page 7-8.
1993 BEWARE that some space is also allocated for non existing arguments
1994 in register. In case an argument list is of form GF used registers
1995 are a0 (a2,a3), but we should push over a1... */
1997 #define REG_PARM_STACK_SPACE(FNDECL) \
1998 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2000 /* Define this if it is the responsibility of the caller to
2001 allocate the area reserved for arguments passed in registers.
2002 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2003 of this macro is to determine whether the space is included in
2004 `current_function_outgoing_args_size'. */
2005 #define OUTGOING_REG_PARM_STACK_SPACE
2007 /* Align stack frames on 64 bits (Double Word ). */
2008 #define STACK_BOUNDARY 64
2010 /* Make sure 4 words are always allocated on the stack. */
2012 #ifndef STACK_ARGS_ADJUST
2013 #define STACK_ARGS_ADJUST(SIZE) \
2015 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2016 SIZE.constant = 4 * UNITS_PER_WORD; \
2021 /* A C expression that should indicate the number of bytes of its
2022 own arguments that a function function pops on returning, or 0
2023 if the function pops no arguments and the caller must therefore
2024 pop them all after the function returns.
2026 FUNDECL is the declaration node of the function (as a tree).
2028 FUNTYPE is a C variable whose value is a tree node that
2029 describes the function in question. Normally it is a node of
2030 type `FUNCTION_TYPE' that describes the data type of the function.
2031 From this it is possible to obtain the data types of the value
2032 and arguments (if known).
2034 When a call to a library function is being considered, FUNTYPE
2035 will contain an identifier node for the library function. Thus,
2036 if you need to distinguish among various library functions, you
2037 can do so by their names. Note that "library function" in this
2038 context means a function used to perform arithmetic, whose name
2039 is known specially in the compiler and was not mentioned in the
2040 C code being compiled.
2042 STACK-SIZE is the number of bytes of arguments passed on the
2043 stack. If a variable number of bytes is passed, it is zero, and
2044 argument popping will always be the responsibility of the
2045 calling function. */
2047 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2050 /* Symbolic macros for the registers used to return integer and floating
2053 #define GP_RETURN (GP_REG_FIRST + 2)
2054 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2056 /* Symbolic macros for the first/last argument registers. */
2058 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2059 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2060 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2061 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2063 #define MAX_ARGS_IN_REGISTERS 4
2065 /* Define how to find the value returned by a library function
2066 assuming the value has mode MODE. */
2068 #define LIBCALL_VALUE(MODE) \
2069 gen_rtx (REG, MODE, \
2070 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2071 && (! TARGET_SINGLE_FLOAT \
2072 || GET_MODE_SIZE (MODE) <= 4)) \
2076 /* Define how to find the value returned by a function.
2077 VALTYPE is the data type of the value (as a tree).
2078 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2079 otherwise, FUNC is 0. */
2081 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2084 /* 1 if N is a possible register number for a function value.
2085 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2086 Currently, R2 and F0 are only implemented here (C has no complex type) */
2088 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2090 /* 1 if N is a possible register number for function argument passing.
2091 We have no FP argument registers when soft-float. When FP registers
2092 are 32 bits, we can't directly reference the odd numbered ones. */
2094 #define FUNCTION_ARG_REGNO_P(N) \
2095 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2096 || (! TARGET_SOFT_FLOAT \
2097 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2098 && (TARGET_FLOAT64 || (0 == (N) % 2))))
2100 /* A C expression which can inhibit the returning of certain function
2101 values in registers, based on the type of value. A nonzero value says
2102 to return the function value in memory, just as large structures are
2103 always returned. Here TYPE will be a C expression of type
2104 `tree', representing the data type of the value.
2106 Note that values of mode `BLKmode' must be explicitly
2107 handled by this macro. Also, the option `-fpcc-struct-return'
2108 takes effect regardless of this macro. On most systems, it is
2109 possible to leave the macro undefined; this causes a default
2110 definition to be used, whose value is the constant 1 for BLKmode
2111 values, and 0 otherwise.
2113 GCC normally converts 1 byte structures into chars, 2 byte
2114 structs into shorts, and 4 byte structs into ints, and returns
2115 them this way. Defining the following macro overrides this,
2116 to give us MIPS cc compatibility. */
2118 #define RETURN_IN_MEMORY(TYPE) \
2119 (TYPE_MODE (TYPE) == BLKmode)
2121 /* A code distinguishing the floating point format of the target
2122 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2123 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2125 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2128 /* Define a data type for recording info about an argument list
2129 during the scan of that argument list. This data type should
2130 hold all necessary information about the function itself
2131 and about the args processed so far, enough to enable macros
2132 such as FUNCTION_ARG to determine where the next arg should go.
2135 typedef struct mips_args {
2136 int gp_reg_found; /* whether a gp register was found yet */
2137 int arg_number; /* argument number */
2138 int arg_words; /* # total words the arguments take */
2139 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2140 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2141 int num_adjusts; /* number of adjustments made */
2142 /* Adjustments made to args pass in regs. */
2143 /* ??? The size is doubled to work around a
2144 bug in the code that sets the adjustments
2146 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2149 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2150 for a call to a function whose data type is FNTYPE.
2151 For a library call, FNTYPE is 0.
2155 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2156 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2158 /* Update the data in CUM to advance over an argument
2159 of mode MODE and data type TYPE.
2160 (TYPE is null for libcalls where that information may not be available.) */
2162 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2163 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2165 /* Determine where to put an argument to a function.
2166 Value is zero to push the argument on the stack,
2167 or a hard register in which to store the argument.
2169 MODE is the argument's machine mode.
2170 TYPE is the data type of the argument (as a tree).
2171 This is null for libcalls where that information may
2173 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2174 the preceding args and about the function being called.
2175 NAMED is nonzero if this argument is a named parameter
2176 (otherwise it is an extra parameter matching an ellipsis). */
2178 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2179 function_arg( &CUM, MODE, TYPE, NAMED)
2181 /* For an arg passed partly in registers and partly in memory,
2182 this is the number of registers used.
2183 For args passed entirely in registers or entirely in memory, zero. */
2185 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2186 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2188 /* If defined, a C expression that gives the alignment boundary, in
2189 bits, of an argument with the specified mode and type. If it is
2190 not defined, `PARM_BOUNDARY' is used for all arguments. */
2192 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2194 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2196 : TYPE_ALIGN(TYPE)) \
2197 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2199 : GET_MODE_ALIGNMENT(MODE)))
2202 /* This macro generates the assembly code for function entry.
2203 FILE is a stdio stream to output the code to.
2204 SIZE is an int: how many units of temporary storage to allocate.
2205 Refer to the array `regs_ever_live' to determine which registers
2206 to save; `regs_ever_live[I]' is nonzero if register number I
2207 is ever used in the function. This macro is responsible for
2208 knowing which registers should not be saved even if used. */
2210 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2212 /* This macro generates the assembly code for function exit,
2213 on machines that need it. If FUNCTION_EPILOGUE is not defined
2214 then individual return instructions are generated for each
2215 return statement. Args are same as for FUNCTION_PROLOGUE. */
2217 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2219 /* Define the number of delay slots needed for the function epilogue.
2221 On the mips, we need a slot if either no stack has been allocated,
2222 or the only register saved is the return register. */
2224 #define DELAY_SLOTS_FOR_EPILOGUE mips_epilogue_delay_slots ()
2226 /* Define whether INSN can be placed in delay slot N for the epilogue.
2227 No references to the stack must be made, since on the MIPS, the
2228 delay slot is done after the stack has been cleaned up. */
2230 #define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N) \
2231 (get_attr_dslot (INSN) == DSLOT_NO \
2232 && get_attr_length (INSN) == 1 \
2233 && ! epilogue_reg_mentioned_p (PATTERN (INSN)))
2235 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2237 #define MUST_SAVE_REGISTER(regno) \
2238 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2239 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
2240 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2242 /* ALIGN FRAMES on double word boundaries */
2244 #define MIPS_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
2247 /* Output assembler code to FILE to increment profiler label # LABELNO
2248 for profiling a function entry. */
2250 #define FUNCTION_PROFILER(FILE, LABELNO) \
2252 fprintf (FILE, "\t.set\tnoreorder\n"); \
2253 fprintf (FILE, "\t.set\tnoat\n"); \
2254 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2255 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2256 fprintf (FILE, "\tjal\t_mcount\n"); \
2258 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2259 TARGET_64BIT ? "dsubu" : "subu", \
2260 reg_names[STACK_POINTER_REGNUM], \
2261 reg_names[STACK_POINTER_REGNUM], \
2262 TARGET_LONG64 ? 16 : 8); \
2263 fprintf (FILE, "\t.set\treorder\n"); \
2264 fprintf (FILE, "\t.set\tat\n"); \
2267 /* Define this macro if the code for function profiling should come
2268 before the function prologue. Normally, the profiling code comes
2271 /* #define PROFILE_BEFORE_PROLOGUE */
2273 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2274 the stack pointer does not matter. The value is tested only in
2275 functions that have frame pointers.
2276 No definition is equivalent to always zero. */
2278 #define EXIT_IGNORE_STACK 1
2281 /* A C statement to output, on the stream FILE, assembler code for a
2282 block of data that contains the constant parts of a trampoline.
2283 This code should not include a label--the label is taken care of
2286 #define TRAMPOLINE_TEMPLATE(STREAM) \
2288 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2289 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2290 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2291 if (TARGET_LONG64) \
2293 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2294 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2298 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2299 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2301 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2302 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2303 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2304 if (TARGET_LONG64) \
2306 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2307 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2311 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2312 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2316 /* A C expression for the size in bytes of the trampoline, as an
2319 #define TRAMPOLINE_SIZE (32 + (TARGET_LONG64 ? 16 : 8))
2321 /* Alignment required for trampolines, in bits. */
2323 #define TRAMPOLINE_ALIGNMENT (TARGET_LONG64 ? 64 : 32)
2325 /* A C statement to initialize the variable parts of a trampoline.
2326 ADDR is an RTX for the address of the trampoline; FNADDR is an
2327 RTX for the address of the nested function; STATIC_CHAIN is an
2328 RTX for the static chain value that should be passed to the
2329 function when it is called. */
2331 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2334 if (TARGET_LONG64) \
2336 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2337 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2341 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2342 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2345 /* Flush both caches. We need to flush the data cache in case \
2346 the system has a write-back cache. */ \
2347 /* ??? Should check the return value for errors. */ \
2348 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "_flush_cache"), \
2349 0, VOIDmode, 3, addr, Pmode, \
2350 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2351 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2354 /* Addressing modes, and classification of registers for them. */
2356 /* #define HAVE_POST_INCREMENT */
2357 /* #define HAVE_POST_DECREMENT */
2359 /* #define HAVE_PRE_DECREMENT */
2360 /* #define HAVE_PRE_INCREMENT */
2362 /* These assume that REGNO is a hard or pseudo reg number.
2363 They give nonzero only if REGNO is a hard reg of the suitable class
2364 or a pseudo reg currently allocated to a suitable hard reg.
2365 These definitions are NOT overridden anywhere. */
2367 #define GP_REG_OR_PSEUDO_STRICT_P(regno) \
2368 GP_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno])
2370 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno) \
2371 (((regno) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (regno)))
2373 #define REGNO_OK_FOR_INDEX_P(regno) 0
2374 #define REGNO_OK_FOR_BASE_P(regno) GP_REG_OR_PSEUDO_STRICT_P (regno)
2376 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2377 and check its validity for a certain class.
2378 We have two alternate definitions for each of them.
2379 The usual definition accepts all pseudo regs; the other rejects them all.
2380 The symbol REG_OK_STRICT causes the latter definition to be used.
2382 Most source files want to accept pseudo regs in the hope that
2383 they will get allocated to the class that the insn wants them to be in.
2384 Some source files that are used after register allocation
2385 need to be strict. */
2387 #ifndef REG_OK_STRICT
2389 #define REG_OK_STRICT_P 0
2390 #define REG_OK_FOR_INDEX_P(X) 0
2391 #define REG_OK_FOR_BASE_P(X) GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X))
2395 #define REG_OK_STRICT_P 1
2396 #define REG_OK_FOR_INDEX_P(X) 0
2397 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2402 /* Maximum number of registers that can appear in a valid memory address. */
2404 #define MAX_REGS_PER_ADDRESS 1
2406 /* A C compound statement with a conditional `goto LABEL;' executed
2407 if X (an RTX) is a legitimate memory address on the target
2408 machine for a memory operand of mode MODE.
2410 It usually pays to define several simpler macros to serve as
2411 subroutines for this one. Otherwise it may be too complicated
2414 This macro must exist in two variants: a strict variant and a
2415 non-strict one. The strict variant is used in the reload pass.
2416 It must be defined so that any pseudo-register that has not been
2417 allocated a hard register is considered a memory reference. In
2418 contexts where some kind of register is required, a
2419 pseudo-register with no hard register must be rejected.
2421 The non-strict variant is used in other passes. It must be
2422 defined to accept all pseudo-registers in every context where
2423 some kind of register is required.
2425 Compiler source files that want to use the strict variant of
2426 this macro define the macro `REG_OK_STRICT'. You should use an
2427 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2428 in that case and the non-strict variant otherwise.
2430 Typically among the subroutines used to define
2431 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2432 acceptable registers for various purposes (one for base
2433 registers, one for index registers, and so on). Then only these
2434 subroutine macros need have two variants; the higher levels of
2435 macros may be the same whether strict or not.
2437 Normally, constant addresses which are the sum of a `symbol_ref'
2438 and an integer are stored inside a `const' RTX to mark them as
2439 constant. Therefore, there is no need to recognize such sums
2440 specifically as legitimate addresses. Normally you would simply
2441 recognize any `const' as legitimate.
2443 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2444 constant sums that are not marked with `const'. It assumes
2445 that a naked `plus' indicates indexing. If so, then you *must*
2446 reject such naked constant sums as illegitimate addresses, so
2447 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2449 On some machines, whether a symbolic address is legitimate
2450 depends on the section that the address refers to. On these
2451 machines, define the macro `ENCODE_SECTION_INFO' to store the
2452 information into the `symbol_ref', and then check for it here.
2453 When you see a `const', you will have to look inside it to find
2454 the `symbol_ref' in order to determine the section. */
2457 #define GO_PRINTF(x) trace(x)
2458 #define GO_PRINTF2(x,y) trace(x,y)
2459 #define GO_DEBUG_RTX(x) debug_rtx(x)
2462 #define GO_PRINTF(x)
2463 #define GO_PRINTF2(x,y)
2464 #define GO_DEBUG_RTX(x)
2467 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2469 register rtx xinsn = (X); \
2471 if (TARGET_DEBUG_B_MODE) \
2473 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2474 (REG_OK_STRICT_P) ? "" : "not "); \
2475 GO_DEBUG_RTX (xinsn); \
2478 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
2481 if (CONSTANT_ADDRESS_P (xinsn) \
2482 && ! (mips_split_addresses && mips_check_split (xinsn, MODE))) \
2485 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2487 register rtx xlow0 = XEXP (xinsn, 0); \
2488 register rtx xlow1 = XEXP (xinsn, 1); \
2490 if (GET_CODE (xlow0) == REG && REG_OK_FOR_BASE_P (xlow0) \
2491 && mips_check_split (xlow1, MODE)) \
2495 if (GET_CODE (xinsn) == PLUS) \
2497 register rtx xplus0 = XEXP (xinsn, 0); \
2498 register rtx xplus1 = XEXP (xinsn, 1); \
2499 register enum rtx_code code0 = GET_CODE (xplus0); \
2500 register enum rtx_code code1 = GET_CODE (xplus1); \
2502 if (code0 != REG && code1 == REG) \
2504 xplus0 = XEXP (xinsn, 1); \
2505 xplus1 = XEXP (xinsn, 0); \
2506 code0 = GET_CODE (xplus0); \
2507 code1 = GET_CODE (xplus1); \
2510 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0)) \
2512 if (code1 == CONST_INT \
2513 && INTVAL (xplus1) >= -32768 \
2514 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2517 /* For some code sequences, you actually get better code by \
2518 pretending that the MIPS supports an address mode of a \
2519 constant address + a register, even though the real \
2520 machine doesn't support it. This is because the \
2521 assembler can use $r1 to load just the high 16 bits, add \
2522 in the register, and fold the low 16 bits into the memory \
2523 reference, whereas the compiler generates a 4 instruction \
2524 sequence. On the other hand, CSE is not as effective. \
2525 It would be a win to generate the lui directly, but the \
2526 MIPS assembler does not have syntax to generate the \
2527 appropriate relocation. */ \
2529 /* Also accept CONST_INT addresses here, so no else. */ \
2530 /* Reject combining an embedded PIC text segment reference \
2531 with a register. That requires an additional \
2533 /* ??? Reject combining an address with a register for the MIPS \
2534 64 bit ABI, because the SGI assembler can not handle this. */ \
2535 if (!TARGET_DEBUG_A_MODE \
2536 && (mips_abi == ABI_32 || mips_abi == ABI_EABI) \
2537 && CONSTANT_ADDRESS_P (xplus1) \
2538 && ! mips_split_addresses \
2539 && (!TARGET_EMBEDDED_PIC \
2541 || GET_CODE (XEXP (xplus1, 0)) != MINUS)) \
2546 if (TARGET_DEBUG_B_MODE) \
2547 GO_PRINTF ("Not a legitimate address\n"); \
2551 /* A C expression that is 1 if the RTX X is a constant which is a
2552 valid address. This is defined to be the same as `CONSTANT_P (X)',
2553 but rejecting CONST_DOUBLE. */
2554 /* When pic, we must reject addresses of the form symbol+large int.
2555 This is because an instruction `sw $4,s+70000' needs to be converted
2556 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2557 assembler would use $at as a temp to load in the large offset. In this
2558 case $at is already in use. We convert such problem addresses to
2559 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2560 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2561 #define CONSTANT_ADDRESS_P(X) \
2562 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2563 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2564 || (GET_CODE (X) == CONST \
2565 && ! (flag_pic && pic_address_needs_scratch (X)) \
2566 && (mips_abi == ABI_32 || mips_abi == ABI_EABI))) \
2567 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2569 /* Define this, so that when PIC, reload won't try to reload invalid
2570 addresses which require two reload registers. */
2572 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2574 /* Nonzero if the constant value X is a legitimate general operand.
2575 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2577 At present, GAS doesn't understand li.[sd], so don't allow it
2578 to be generated at present. Also, the MIPS assembler does not
2579 grok li.d Infinity. */
2581 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2582 #define LEGITIMATE_CONSTANT_P(X) \
2583 ((GET_CODE (X) != CONST_DOUBLE \
2584 || mips_const_double_ok (X, GET_MODE (X))) \
2585 && ! (GET_CODE (X) == CONST \
2586 && mips_abi != ABI_32 && mips_abi != ABI_EABI))
2588 /* A C compound statement that attempts to replace X with a valid
2589 memory address for an operand of mode MODE. WIN will be a C
2590 statement label elsewhere in the code; the macro definition may
2593 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2595 to avoid further processing if the address has become legitimate.
2597 X will always be the result of a call to `break_out_memory_refs',
2598 and OLDX will be the operand that was given to that function to
2601 The code generated by this macro should not alter the
2602 substructure of X. If it transforms X into a more legitimate
2603 form, it should assign X (which will always be a C variable) a
2606 It is not necessary for this macro to come up with a legitimate
2607 address. The compiler has standard ways of doing so in all
2608 cases. In fact, it is safe for this macro to do nothing. But
2609 often a machine-dependent strategy can generate better code.
2611 For the MIPS, transform:
2613 memory(X + <large int>)
2617 Y = <large int> & ~0x7fff;
2619 memory (Z + (<large int> & 0x7fff));
2621 This is for CSE to find several similar references, and only use one Z.
2623 When PIC, convert addresses of the form memory (symbol+large int) to
2624 memory (reg+large int). */
2627 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2629 register rtx xinsn = (X); \
2631 if (TARGET_DEBUG_B_MODE) \
2633 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2634 GO_DEBUG_RTX (xinsn); \
2637 if (mips_split_addresses && mips_check_split (X, MODE)) \
2639 /* ??? Is this ever executed? */ \
2640 X = gen_rtx (LO_SUM, Pmode, \
2641 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2645 if (GET_CODE (xinsn) == CONST \
2646 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2647 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2648 || (mips_abi != ABI_32 && mips_abi != ABI_EABI))) \
2650 rtx ptr_reg = gen_reg_rtx (Pmode); \
2651 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2653 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2655 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2656 if (SMALL_INT (constant)) \
2658 /* Otherwise we fall through so the code below will fix the \
2663 if (GET_CODE (xinsn) == PLUS) \
2665 register rtx xplus0 = XEXP (xinsn, 0); \
2666 register rtx xplus1 = XEXP (xinsn, 1); \
2667 register enum rtx_code code0 = GET_CODE (xplus0); \
2668 register enum rtx_code code1 = GET_CODE (xplus1); \
2670 if (code0 != REG && code1 == REG) \
2672 xplus0 = XEXP (xinsn, 1); \
2673 xplus1 = XEXP (xinsn, 0); \
2674 code0 = GET_CODE (xplus0); \
2675 code1 = GET_CODE (xplus1); \
2678 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
2679 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2681 rtx int_reg = gen_reg_rtx (Pmode); \
2682 rtx ptr_reg = gen_reg_rtx (Pmode); \
2684 emit_move_insn (int_reg, \
2685 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2687 emit_insn (gen_rtx (SET, VOIDmode, \
2689 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
2691 X = gen_rtx (PLUS, Pmode, ptr_reg, \
2692 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
2697 if (TARGET_DEBUG_B_MODE) \
2698 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
2702 /* A C statement or compound statement with a conditional `goto
2703 LABEL;' executed if memory address X (an RTX) can have different
2704 meanings depending on the machine mode of the memory reference it
2707 Autoincrement and autodecrement addresses typically have
2708 mode-dependent effects because the amount of the increment or
2709 decrement is the size of the operand being addressed. Some
2710 machines have other mode-dependent addresses. Many RISC machines
2711 have no mode-dependent addresses.
2713 You may assume that ADDR is a valid address for the machine. */
2715 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2718 /* Define this macro if references to a symbol must be treated
2719 differently depending on something about the variable or
2720 function named by the symbol (such as what section it is in).
2722 The macro definition, if any, is executed immediately after the
2723 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
2724 The value of the rtl will be a `mem' whose address is a
2727 The usual thing for this macro to do is to a flag in the
2728 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
2729 name string in the `symbol_ref' (if one bit is not enough
2732 The best way to modify the name string is by adding text to the
2733 beginning, with suitable punctuation to prevent any ambiguity.
2734 Allocate the new name in `saveable_obstack'. You will have to
2735 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
2736 and output the name accordingly.
2738 You can also check the information stored in the `symbol_ref' in
2739 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
2740 `PRINT_OPERAND_ADDRESS'. */
2742 #define ENCODE_SECTION_INFO(DECL) \
2745 if (TARGET_EMBEDDED_PIC) \
2747 if (TREE_CODE (DECL) == VAR_DECL) \
2748 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2749 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
2750 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
2751 else if (TREE_CODE (DECL) == STRING_CST \
2752 && ! flag_writable_strings) \
2753 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
2755 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
2758 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
2760 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
2762 if (size > 0 && size <= mips_section_threshold) \
2763 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2766 else if (HALF_PIC_P ()) \
2767 HALF_PIC_ENCODE (DECL); \
2772 /* Specify the machine mode that this machine uses
2773 for the index in the tablejump instruction. */
2774 #define CASE_VECTOR_MODE (TARGET_LONG64 ? DImode : SImode)
2776 /* Define this if the tablejump instruction expects the table
2777 to contain offsets from the address of the table.
2778 Do not define this if the table should contain absolute addresses. */
2779 /* #define CASE_VECTOR_PC_RELATIVE */
2781 /* Specify the tree operation to be used to convert reals to integers. */
2782 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2784 /* This is the kind of divide that is easiest to do in the general case. */
2785 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2787 /* Define this as 1 if `char' should by default be signed; else as 0. */
2788 #ifndef DEFAULT_SIGNED_CHAR
2789 #define DEFAULT_SIGNED_CHAR 1
2792 /* Max number of bytes we can move from memory to memory
2793 in one reasonably fast instruction. */
2794 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2795 #define MAX_MOVE_MAX 8
2797 /* Define this macro as a C expression which is nonzero if
2798 accessing less than a word of memory (i.e. a `char' or a
2799 `short') is no faster than accessing a word of memory, i.e., if
2800 such access require more than one instruction or if there is no
2801 difference in cost between byte and (aligned) word loads.
2803 On RISC machines, it tends to generate better code to define
2804 this as 1, since it avoids making a QI or HI mode register. */
2805 #define SLOW_BYTE_ACCESS 1
2807 /* We assume that the store-condition-codes instructions store 0 for false
2808 and some other value for true. This is the value stored for true. */
2810 #define STORE_FLAG_VALUE 1
2812 /* Define this if zero-extension is slow (more than one real instruction). */
2813 #define SLOW_ZERO_EXTEND
2815 /* Define this to be nonzero if shift instructions ignore all but the low-order
2817 #define SHIFT_COUNT_TRUNCATED 1
2819 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2820 is done just by pretending it is already truncated. */
2821 /* In 64 bit mode, 32 bit instructions require that register values be properly
2822 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
2823 converts a value >32 bits to a value <32 bits. */
2824 /* ??? This results in inefficient code for 64 bit to 32 conversions.
2825 Something needs to be done about this. Perhaps not use any 32 bit
2826 instructions? Perhaps use PROMOTE_MODE? */
2827 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2828 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2830 /* Specify the machine mode that pointers have.
2831 After generation of rtl, the compiler makes no further distinction
2832 between pointers and any other objects of this machine mode. */
2834 #define Pmode (TARGET_LONG64 ? DImode : SImode)
2836 /* A function address in a call instruction
2837 is a word address (for indexing purposes)
2838 so give the MEM rtx a words's mode. */
2840 #define FUNCTION_MODE (TARGET_LONG64 ? DImode : SImode)
2842 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
2843 memset, instead of the BSD functions bcopy and bzero. */
2845 #if defined(MIPS_SYSV) || defined(OSF_OS)
2846 #define TARGET_MEM_FUNCTIONS
2850 /* A part of a C `switch' statement that describes the relative
2851 costs of constant RTL expressions. It must contain `case'
2852 labels for expression codes `const_int', `const', `symbol_ref',
2853 `label_ref' and `const_double'. Each case must ultimately reach
2854 a `return' statement to return the relative cost of the use of
2855 that kind of constant value in an expression. The cost may
2856 depend on the precise value of the constant, which is available
2857 for examination in X.
2859 CODE is the expression code--redundant, since it can be obtained
2860 with `GET_CODE (X)'. */
2862 #define CONST_COSTS(X,CODE,OUTER_CODE) \
2864 /* Always return 0, since we don't have different sized \
2865 instructions, hence different costs according to Richard \
2870 return COSTS_N_INSNS (2); \
2874 rtx offset = const0_rtx; \
2875 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
2877 if (GET_CODE (symref) == LABEL_REF) \
2878 return COSTS_N_INSNS (2); \
2880 if (GET_CODE (symref) != SYMBOL_REF) \
2881 return COSTS_N_INSNS (4); \
2883 /* let's be paranoid.... */ \
2884 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
2885 return COSTS_N_INSNS (2); \
2887 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
2891 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
2893 case CONST_DOUBLE: \
2896 split_double (X, &high, &low); \
2897 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
2898 || low == CONST0_RTX (GET_MODE (low))) \
2902 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2903 This can be used, for example, to indicate how costly a multiply
2904 instruction is. In writing this macro, you can use the construct
2905 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
2907 This macro is optional; do not define it if the default cost
2908 assumptions are adequate for the target machine.
2910 If -mdebugd is used, change the multiply cost to 2, so multiply by
2911 a constant isn't converted to a series of shifts. This helps
2912 strength reduction, and also makes it easier to identify what the
2913 compiler is doing. */
2915 /* ??? Fix this to be right for the R8000. */
2916 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2919 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
2920 if (simple_memory_operand (X, GET_MODE (X))) \
2921 return COSTS_N_INSNS (num_words); \
2923 return COSTS_N_INSNS (2*num_words); \
2927 return COSTS_N_INSNS (6); \
2930 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
2935 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
2936 return COSTS_N_INSNS (2); \
2938 return COSTS_N_INSNS (1); \
2943 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
2944 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
2946 return COSTS_N_INSNS (1); \
2950 enum machine_mode xmode = GET_MODE (X); \
2951 if (xmode == SFmode || xmode == DFmode) \
2952 return COSTS_N_INSNS (1); \
2954 return COSTS_N_INSNS (4); \
2960 enum machine_mode xmode = GET_MODE (X); \
2961 if (xmode == SFmode || xmode == DFmode) \
2963 if (mips_cpu == PROCESSOR_R3000) \
2964 return COSTS_N_INSNS (2); \
2965 else if (mips_cpu == PROCESSOR_R6000) \
2966 return COSTS_N_INSNS (3); \
2968 return COSTS_N_INSNS (6); \
2971 if (xmode == DImode && !TARGET_64BIT) \
2972 return COSTS_N_INSNS (4); \
2974 return COSTS_N_INSNS (1); \
2978 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 4 : 1); \
2982 enum machine_mode xmode = GET_MODE (X); \
2983 if (xmode == SFmode) \
2985 if (mips_cpu == PROCESSOR_R3000 \
2986 || mips_cpu == PROCESSOR_R5000) \
2987 return COSTS_N_INSNS (4); \
2988 else if (mips_cpu == PROCESSOR_R6000) \
2989 return COSTS_N_INSNS (5); \
2991 return COSTS_N_INSNS (7); \
2994 if (xmode == DFmode) \
2996 if (mips_cpu == PROCESSOR_R3000 \
2997 || mips_cpu == PROCESSOR_R5000) \
2998 return COSTS_N_INSNS (5); \
2999 else if (mips_cpu == PROCESSOR_R6000) \
3000 return COSTS_N_INSNS (6); \
3002 return COSTS_N_INSNS (8); \
3005 if (mips_cpu == PROCESSOR_R3000) \
3006 return COSTS_N_INSNS (12); \
3007 else if (mips_cpu == PROCESSOR_R6000) \
3008 return COSTS_N_INSNS (17); \
3009 else if (mips_cpu == PROCESSOR_R5000) \
3010 return COSTS_N_INSNS (5); \
3012 return COSTS_N_INSNS (10); \
3018 enum machine_mode xmode = GET_MODE (X); \
3019 if (xmode == SFmode) \
3021 if (mips_cpu == PROCESSOR_R3000) \
3022 return COSTS_N_INSNS (12); \
3023 else if (mips_cpu == PROCESSOR_R6000) \
3024 return COSTS_N_INSNS (15); \
3026 return COSTS_N_INSNS (23); \
3029 if (xmode == DFmode) \
3031 if (mips_cpu == PROCESSOR_R3000) \
3032 return COSTS_N_INSNS (19); \
3033 else if (mips_cpu == PROCESSOR_R6000) \
3034 return COSTS_N_INSNS (16); \
3036 return COSTS_N_INSNS (36); \
3039 /* fall through */ \
3043 if (mips_cpu == PROCESSOR_R3000) \
3044 return COSTS_N_INSNS (35); \
3045 else if (mips_cpu == PROCESSOR_R6000) \
3046 return COSTS_N_INSNS (38); \
3047 else if (mips_cpu == PROCESSOR_R5000) \
3048 return COSTS_N_INSNS (36); \
3050 return COSTS_N_INSNS (69); \
3053 /* A sign extend from SImode to DImode in 64 bit mode is often \
3054 zero instructions, because the result can often be used \
3055 directly by another instruction; we'll call it one. */ \
3056 if (TARGET_64BIT && GET_MODE (X) == DImode \
3057 && GET_MODE (XEXP (X, 0)) == SImode) \
3058 return COSTS_N_INSNS (1); \
3060 return COSTS_N_INSNS (2); \
3063 if (TARGET_64BIT && GET_MODE (X) == DImode \
3064 && GET_MODE (XEXP (X, 0)) == SImode) \
3065 return COSTS_N_INSNS (2); \
3067 return COSTS_N_INSNS (1);
3069 /* An expression giving the cost of an addressing mode that
3070 contains ADDRESS. If not defined, the cost is computed from the
3071 form of the ADDRESS expression and the `CONST_COSTS' values.
3073 For most CISC machines, the default cost is a good approximation
3074 of the true cost of the addressing mode. However, on RISC
3075 machines, all instructions normally have the same length and
3076 execution time. Hence all addresses will have equal costs.
3078 In cases where more than one form of an address is known, the
3079 form with the lowest cost will be used. If multiple forms have
3080 the same, lowest, cost, the one that is the most complex will be
3083 For example, suppose an address that is equal to the sum of a
3084 register and a constant is used twice in the same basic block.
3085 When this macro is not defined, the address will be computed in
3086 a register and memory references will be indirect through that
3087 register. On machines where the cost of the addressing mode
3088 containing the sum is no higher than that of a simple indirect
3089 reference, this will produce an additional instruction and
3090 possibly require an additional register. Proper specification
3091 of this macro eliminates this overhead for such machines.
3093 Similar use of this macro is made in strength reduction of loops.
3095 ADDRESS need not be valid as an address. In such a case, the
3096 cost is not relevant and can be any value; invalid addresses
3097 need not be assigned a different cost.
3099 On machines where an address involving more than one register is
3100 as cheap as an address computation involving only one register,
3101 defining `ADDRESS_COST' to reflect this can cause two registers
3102 to be live over a region of code where only one would have been
3103 if `ADDRESS_COST' were not defined in that manner. This effect
3104 should be considered in the definition of this macro.
3105 Equivalent costs should probably only be given to addresses with
3106 different numbers of registers on machines with lots of registers.
3108 This macro will normally either not be defined or be defined as
3111 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3113 /* A C expression for the cost of moving data from a register in
3114 class FROM to one in class TO. The classes are expressed using
3115 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3116 the default; other values are interpreted relative to that.
3118 It is not required that the cost always equal 2 when FROM is the
3119 same as TO; on some machines it is expensive to move between
3120 registers if they are not general registers.
3122 If reload sees an insn consisting of a single `set' between two
3123 hard registers, and if `REGISTER_MOVE_COST' applied to their
3124 classes returns a value of 2, reload does not check to ensure
3125 that the constraints of the insn are met. Setting a cost of
3126 other than 2 will allow reload to verify that the constraints are
3127 met. You should do this if the `movM' pattern's constraints do
3128 not allow such copying. */
3130 #define REGISTER_MOVE_COST(FROM, TO) \
3131 ((FROM) == GR_REGS && (TO) == GR_REGS ? 2 \
3132 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3133 : (FROM) == GR_REGS && (TO) == FP_REGS ? 4 \
3134 : (FROM) == FP_REGS && (TO) == GR_REGS ? 4 \
3135 : (((FROM) == HI_REG || (FROM) == LO_REG \
3136 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3137 && (TO) == GR_REGS) ? 6 \
3138 : (((TO) == HI_REG || (TO) == LO_REG \
3139 || (TO) == MD_REGS || (FROM) == HILO_REG) \
3140 && (FROM) == GR_REGS) ? 6 \
3141 : (FROM) == ST_REGS && (TO) == GR_REGS ? 4 \
3142 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3145 /* ??? Fix this to be right for the R8000. */
3146 #define MEMORY_MOVE_COST(MODE) \
3147 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4)
3149 /* A C expression for the cost of a branch instruction. A value of
3150 1 is the default; other values are interpreted relative to that. */
3152 /* ??? Fix this to be right for the R8000. */
3153 #define BRANCH_COST \
3154 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 2 : 1)
3156 /* A C statement (sans semicolon) to update the integer variable COST
3157 based on the relationship between INSN that is dependent on
3158 DEP_INSN through the dependence LINK. The default is to make no
3159 adjustment to COST. On the MIPS, ignore the cost of anti- and
3160 output-dependencies. */
3162 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3163 if (REG_NOTE_KIND (LINK) != 0) \
3164 (COST) = 0; /* Anti or output dependence. */
3166 /* Optionally define this if you have added predicates to
3167 `MACHINE.c'. This macro is called within an initializer of an
3168 array of structures. The first field in the structure is the
3169 name of a predicate and the second field is an array of rtl
3170 codes. For each predicate, list all rtl codes that can be in
3171 expressions matched by the predicate. The list should have a
3172 trailing comma. Here is an example of two entries in the list
3173 for a typical RISC machine:
3175 #define PREDICATE_CODES \
3176 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3177 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3179 Defining this macro does not affect the generated code (however,
3180 incorrect definitions that omit an rtl code that may be matched
3181 by the predicate can cause the compiler to malfunction).
3182 Instead, it allows the table built by `genrecog' to be more
3183 compact and efficient, thus speeding up the compiler. The most
3184 important predicates to include in the list specified by this
3185 macro are thoses used in the most insn patterns. */
3187 #define PREDICATE_CODES \
3188 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3189 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3190 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3191 {"reg_or_0_operand", { REG, CONST_INT, SUBREG }}, \
3192 {"small_int", { CONST_INT }}, \
3193 {"large_int", { CONST_INT }}, \
3194 {"complemented_arith_operand",{ CONST_INT }}, \
3195 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3196 {"const_float_1_operand", { CONST_DOUBLE }}, \
3197 {"simple_memory_operand", { MEM, SUBREG }}, \
3198 {"equality_op", { EQ, NE }}, \
3199 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3201 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3202 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3203 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3204 SYMBOL_REF, LABEL_REF, SUBREG, \
3206 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3207 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3208 MEM, SIGN_EXTEND }}, \
3209 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3210 {"se_reg_or_0_operand", { REG, CONST_INT, SUBREG, \
3212 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3214 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3216 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3217 SYMBOL_REF, LABEL_REF, SUBREG, \
3218 REG, SIGN_EXTEND }}, \
3219 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }},
3222 /* If defined, a C statement to be executed just prior to the
3223 output of assembler code for INSN, to modify the extracted
3224 operands so they will be output differently.
3226 Here the argument OPVEC is the vector containing the operands
3227 extracted from INSN, and NOPERANDS is the number of elements of
3228 the vector which contain meaningful data for this insn. The
3229 contents of this vector are what will be used to convert the
3230 insn template into assembler code, so you can change the
3231 assembler output by changing the contents of the vector.
3233 We use it to check if the current insn needs a nop in front of it
3234 because of load delays, and also to update the delay slot
3237 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3238 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3241 /* Control the assembler format that we output. */
3243 /* Output at beginning of assembler file.
3244 If we are optimizing to use the global pointer, create a temporary
3245 file to hold all of the text stuff, and write it out to the end.
3246 This is needed because the MIPS assembler is evidently one pass,
3247 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3248 declaration when the code is processed, it generates a two
3249 instruction sequence. */
3251 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3253 /* Output to assembler file text saying following lines
3254 may contain character constants, extra white space, comments, etc. */
3256 #define ASM_APP_ON " #APP\n"
3258 /* Output to assembler file text saying following lines
3259 no longer contain unusual constructs. */
3261 #define ASM_APP_OFF " #NO_APP\n"
3263 /* How to refer to registers in assembler output.
3264 This sequence is indexed by compiler's hard-register-number (see above).
3266 In order to support the two different conventions for register names,
3267 we use the name of a table set up in mips.c, which is overwritten
3268 if -mrnames is used. */
3270 #define REGISTER_NAMES \
3272 &mips_reg_names[ 0][0], \
3273 &mips_reg_names[ 1][0], \
3274 &mips_reg_names[ 2][0], \
3275 &mips_reg_names[ 3][0], \
3276 &mips_reg_names[ 4][0], \
3277 &mips_reg_names[ 5][0], \
3278 &mips_reg_names[ 6][0], \
3279 &mips_reg_names[ 7][0], \
3280 &mips_reg_names[ 8][0], \
3281 &mips_reg_names[ 9][0], \
3282 &mips_reg_names[10][0], \
3283 &mips_reg_names[11][0], \
3284 &mips_reg_names[12][0], \
3285 &mips_reg_names[13][0], \
3286 &mips_reg_names[14][0], \
3287 &mips_reg_names[15][0], \
3288 &mips_reg_names[16][0], \
3289 &mips_reg_names[17][0], \
3290 &mips_reg_names[18][0], \
3291 &mips_reg_names[19][0], \
3292 &mips_reg_names[20][0], \
3293 &mips_reg_names[21][0], \
3294 &mips_reg_names[22][0], \
3295 &mips_reg_names[23][0], \
3296 &mips_reg_names[24][0], \
3297 &mips_reg_names[25][0], \
3298 &mips_reg_names[26][0], \
3299 &mips_reg_names[27][0], \
3300 &mips_reg_names[28][0], \
3301 &mips_reg_names[29][0], \
3302 &mips_reg_names[30][0], \
3303 &mips_reg_names[31][0], \
3304 &mips_reg_names[32][0], \
3305 &mips_reg_names[33][0], \
3306 &mips_reg_names[34][0], \
3307 &mips_reg_names[35][0], \
3308 &mips_reg_names[36][0], \
3309 &mips_reg_names[37][0], \
3310 &mips_reg_names[38][0], \
3311 &mips_reg_names[39][0], \
3312 &mips_reg_names[40][0], \
3313 &mips_reg_names[41][0], \
3314 &mips_reg_names[42][0], \
3315 &mips_reg_names[43][0], \
3316 &mips_reg_names[44][0], \
3317 &mips_reg_names[45][0], \
3318 &mips_reg_names[46][0], \
3319 &mips_reg_names[47][0], \
3320 &mips_reg_names[48][0], \
3321 &mips_reg_names[49][0], \
3322 &mips_reg_names[50][0], \
3323 &mips_reg_names[51][0], \
3324 &mips_reg_names[52][0], \
3325 &mips_reg_names[53][0], \
3326 &mips_reg_names[54][0], \
3327 &mips_reg_names[55][0], \
3328 &mips_reg_names[56][0], \
3329 &mips_reg_names[57][0], \
3330 &mips_reg_names[58][0], \
3331 &mips_reg_names[59][0], \
3332 &mips_reg_names[60][0], \
3333 &mips_reg_names[61][0], \
3334 &mips_reg_names[62][0], \
3335 &mips_reg_names[63][0], \
3336 &mips_reg_names[64][0], \
3337 &mips_reg_names[65][0], \
3338 &mips_reg_names[66][0], \
3339 &mips_reg_names[67][0], \
3340 &mips_reg_names[68][0], \
3341 &mips_reg_names[69][0], \
3342 &mips_reg_names[70][0], \
3343 &mips_reg_names[71][0], \
3344 &mips_reg_names[72][0], \
3345 &mips_reg_names[73][0], \
3346 &mips_reg_names[74][0], \
3347 &mips_reg_names[75][0], \
3350 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3351 So define this for it. */
3352 #define DEBUG_REGISTER_NAMES \
3354 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3355 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3356 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3357 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3358 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3359 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3360 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3361 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3362 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3363 "$fcc5","$fcc6","$fcc7","$rap" \
3366 /* If defined, a C initializer for an array of structures
3367 containing a name and a register number. This macro defines
3368 additional names for hard registers, thus allowing the `asm'
3369 option in declarations to refer to registers using alternate
3372 We define both names for the integer registers here. */
3374 #define ADDITIONAL_REGISTER_NAMES \
3376 { "$0", 0 + GP_REG_FIRST }, \
3377 { "$1", 1 + GP_REG_FIRST }, \
3378 { "$2", 2 + GP_REG_FIRST }, \
3379 { "$3", 3 + GP_REG_FIRST }, \
3380 { "$4", 4 + GP_REG_FIRST }, \
3381 { "$5", 5 + GP_REG_FIRST }, \
3382 { "$6", 6 + GP_REG_FIRST }, \
3383 { "$7", 7 + GP_REG_FIRST }, \
3384 { "$8", 8 + GP_REG_FIRST }, \
3385 { "$9", 9 + GP_REG_FIRST }, \
3386 { "$10", 10 + GP_REG_FIRST }, \
3387 { "$11", 11 + GP_REG_FIRST }, \
3388 { "$12", 12 + GP_REG_FIRST }, \
3389 { "$13", 13 + GP_REG_FIRST }, \
3390 { "$14", 14 + GP_REG_FIRST }, \
3391 { "$15", 15 + GP_REG_FIRST }, \
3392 { "$16", 16 + GP_REG_FIRST }, \
3393 { "$17", 17 + GP_REG_FIRST }, \
3394 { "$18", 18 + GP_REG_FIRST }, \
3395 { "$19", 19 + GP_REG_FIRST }, \
3396 { "$20", 20 + GP_REG_FIRST }, \
3397 { "$21", 21 + GP_REG_FIRST }, \
3398 { "$22", 22 + GP_REG_FIRST }, \
3399 { "$23", 23 + GP_REG_FIRST }, \
3400 { "$24", 24 + GP_REG_FIRST }, \
3401 { "$25", 25 + GP_REG_FIRST }, \
3402 { "$26", 26 + GP_REG_FIRST }, \
3403 { "$27", 27 + GP_REG_FIRST }, \
3404 { "$28", 28 + GP_REG_FIRST }, \
3405 { "$29", 29 + GP_REG_FIRST }, \
3406 { "$30", 30 + GP_REG_FIRST }, \
3407 { "$31", 31 + GP_REG_FIRST }, \
3408 { "$sp", 29 + GP_REG_FIRST }, \
3409 { "$fp", 30 + GP_REG_FIRST }, \
3410 { "at", 1 + GP_REG_FIRST }, \
3411 { "v0", 2 + GP_REG_FIRST }, \
3412 { "v1", 3 + GP_REG_FIRST }, \
3413 { "a0", 4 + GP_REG_FIRST }, \
3414 { "a1", 5 + GP_REG_FIRST }, \
3415 { "a2", 6 + GP_REG_FIRST }, \
3416 { "a3", 7 + GP_REG_FIRST }, \
3417 { "t0", 8 + GP_REG_FIRST }, \
3418 { "t1", 9 + GP_REG_FIRST }, \
3419 { "t2", 10 + GP_REG_FIRST }, \
3420 { "t3", 11 + GP_REG_FIRST }, \
3421 { "t4", 12 + GP_REG_FIRST }, \
3422 { "t5", 13 + GP_REG_FIRST }, \
3423 { "t6", 14 + GP_REG_FIRST }, \
3424 { "t7", 15 + GP_REG_FIRST }, \
3425 { "s0", 16 + GP_REG_FIRST }, \
3426 { "s1", 17 + GP_REG_FIRST }, \
3427 { "s2", 18 + GP_REG_FIRST }, \
3428 { "s3", 19 + GP_REG_FIRST }, \
3429 { "s4", 20 + GP_REG_FIRST }, \
3430 { "s5", 21 + GP_REG_FIRST }, \
3431 { "s6", 22 + GP_REG_FIRST }, \
3432 { "s7", 23 + GP_REG_FIRST }, \
3433 { "t8", 24 + GP_REG_FIRST }, \
3434 { "t9", 25 + GP_REG_FIRST }, \
3435 { "k0", 26 + GP_REG_FIRST }, \
3436 { "k1", 27 + GP_REG_FIRST }, \
3437 { "gp", 28 + GP_REG_FIRST }, \
3438 { "sp", 29 + GP_REG_FIRST }, \
3439 { "fp", 30 + GP_REG_FIRST }, \
3440 { "ra", 31 + GP_REG_FIRST }, \
3441 { "$sp", 29 + GP_REG_FIRST }, \
3442 { "$fp", 30 + GP_REG_FIRST } \
3445 /* Define results of standard character escape sequences. */
3446 #define TARGET_BELL 007
3447 #define TARGET_BS 010
3448 #define TARGET_TAB 011
3449 #define TARGET_NEWLINE 012
3450 #define TARGET_VT 013
3451 #define TARGET_FF 014
3452 #define TARGET_CR 015
3454 /* A C compound statement to output to stdio stream STREAM the
3455 assembler syntax for an instruction operand X. X is an RTL
3458 CODE is a value that can be used to specify one of several ways
3459 of printing the operand. It is used when identical operands
3460 must be printed differently depending on the context. CODE
3461 comes from the `%' specification that was used to request
3462 printing of the operand. If the specification was just `%DIGIT'
3463 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3464 is the ASCII code for LTR.
3466 If X is a register, this macro should print the register's name.
3467 The names can be found in an array `reg_names' whose type is
3468 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3470 When the machine description has a specification `%PUNCT' (a `%'
3471 followed by a punctuation character), this macro is called with
3472 a null pointer for X and the punctuation character for CODE.
3474 See mips.c for the MIPS specific codes. */
3476 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3478 /* A C expression which evaluates to true if CODE is a valid
3479 punctuation character for use in the `PRINT_OPERAND' macro. If
3480 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3481 punctuation characters (except for the standard one, `%') are
3482 used in this way. */
3484 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3486 /* A C compound statement to output to stdio stream STREAM the
3487 assembler syntax for an instruction operand that is a memory
3488 reference whose address is ADDR. ADDR is an RTL expression.
3490 On some machines, the syntax for a symbolic address depends on
3491 the section that the address refers to. On these machines,
3492 define the macro `ENCODE_SECTION_INFO' to store the information
3493 into the `symbol_ref', and then check for it here. */
3495 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3498 /* A C statement, to be executed after all slot-filler instructions
3499 have been output. If necessary, call `dbr_sequence_length' to
3500 determine the number of slots filled in a sequence (zero if not
3501 currently outputting a sequence), to decide how many no-ops to
3502 output, or whatever.
3504 Don't define this macro if it has nothing to do, but it is
3505 helpful in reading assembly output if the extent of the delay
3506 sequence is made explicit (e.g. with white space).
3508 Note that output routines for instructions with delay slots must
3509 be prepared to deal with not being output as part of a sequence
3510 (i.e. when the scheduling pass is not run, or when no slot
3511 fillers could be found.) The variable `final_sequence' is null
3512 when not processing a sequence, otherwise it contains the
3513 `sequence' rtx being output. */
3515 #define DBR_OUTPUT_SEQEND(STREAM) \
3518 if (set_nomacro > 0 && --set_nomacro == 0) \
3519 fputs ("\t.set\tmacro\n", STREAM); \
3521 if (set_noreorder > 0 && --set_noreorder == 0) \
3522 fputs ("\t.set\treorder\n", STREAM); \
3524 dslots_jump_filled++; \
3525 fputs ("\n", STREAM); \
3530 /* How to tell the debugger about changes of source files. Note, the
3531 mips ECOFF format cannot deal with changes of files inside of
3532 functions, which means the output of parser generators like bison
3533 is generally not debuggable without using the -l switch. Lose,
3534 lose, lose. Silicon graphics seems to want all .file's hardwired
3537 #ifndef SET_FILE_NUMBER
3538 #define SET_FILE_NUMBER() ++num_source_filenames
3541 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3542 mips_output_filename (STREAM, NAME)
3544 /* This is defined so that it can be overridden in iris6.h. */
3545 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3548 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3549 output_quoted_string (STREAM, NAME); \
3550 fputs ("\n", STREAM); \
3554 /* This is how to output a note the debugger telling it the line number
3555 to which the following sequence of instructions corresponds.
3556 Silicon graphics puts a label after each .loc. */
3558 #ifndef LABEL_AFTER_LOC
3559 #define LABEL_AFTER_LOC(STREAM)
3562 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3563 mips_output_lineno (STREAM, LINE)
3565 /* The MIPS implementation uses some labels for it's own purpose. The
3566 following lists what labels are created, and are all formed by the
3567 pattern $L[a-z].*. The machine independent portion of GCC creates
3568 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3570 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3571 $Lb[0-9]+ Begin blocks for MIPS debug support
3572 $Lc[0-9]+ Label for use in s<xx> operation.
3573 $Le[0-9]+ End blocks for MIPS debug support
3574 $Lp\..+ Half-pic labels. */
3576 /* This is how to output the definition of a user-level label named NAME,
3577 such as the label on a static function or variable NAME.
3579 If we are optimizing the gp, remember that this label has been put
3580 out, so we know not to emit an .extern for it in mips_asm_file_end.
3581 We use one of the common bits in the IDENTIFIER tree node for this,
3582 since those bits seem to be unused, and we don't have any method
3583 of getting the decl nodes from the name. */
3585 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
3587 assemble_name (STREAM, NAME); \
3588 fputs (":\n", STREAM); \
3592 /* A C statement (sans semicolon) to output to the stdio stream
3593 STREAM any text necessary for declaring the name NAME of an
3594 initialized variable which is being defined. This macro must
3595 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3596 The argument DECL is the `VAR_DECL' tree node representing the
3599 If this macro is not defined, then the variable name is defined
3600 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3602 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3605 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3606 HALF_PIC_DECLARE (NAME); \
3611 /* This is how to output a command to make the user-level label named NAME
3612 defined for reference from other files. */
3614 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
3616 fputs ("\t.globl\t", STREAM); \
3617 assemble_name (STREAM, NAME); \
3618 fputs ("\n", STREAM); \
3621 /* This says how to define a global common symbol. */
3623 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
3624 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
3626 /* This says how to define a local common symbol (ie, not visible to
3629 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3630 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
3633 /* This says how to output an external. It would be possible not to
3634 output anything and let undefined symbol become external. However
3635 the assembler uses length information on externals to allocate in
3636 data/sdata bss/sbss, thereby saving exec time. */
3638 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3639 mips_output_external(STREAM,DECL,NAME)
3641 /* This says what to print at the end of the assembly file */
3642 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
3645 /* This is how to declare a function name. The actual work of
3646 emitting the label is moved to function_prologue, so that we can
3647 get the line number correctly emitted before the .ent directive,
3648 and after any .file directives.
3650 Also, switch files if we are optimizing the global pointer. */
3652 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
3654 extern FILE *asm_out_text_file; \
3655 if (TARGET_GP_OPT) \
3657 STREAM = asm_out_text_file; \
3658 /* ??? text_section gets called too soon. If the previous \
3659 function is in a special section and we're not, we have \
3660 to switch back to the text section. We can't call \
3661 text_section again as gcc thinks we're already there. */ \
3662 /* ??? See varasm.c. There are other things that get output \
3663 too early, like alignment (before we've switched STREAM). */ \
3664 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
3665 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
3668 HALF_PIC_DECLARE (NAME); \
3671 /* This is how to output an internal numbered label where
3672 PREFIX is the class of label and NUM is the number within the class. */
3674 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
3675 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
3677 /* This is how to store into the string LABEL
3678 the symbol_ref name of an internal numbered label where
3679 PREFIX is the class of label and NUM is the number within the class.
3680 This is suitable for output with `assemble_name'. */
3682 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3683 sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
3685 /* This is how to output an assembler line defining a `double' constant. */
3687 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
3688 mips_output_double (STREAM, VALUE)
3691 /* This is how to output an assembler line defining a `float' constant. */
3693 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
3694 mips_output_float (STREAM, VALUE)
3697 /* This is how to output an assembler line defining an `int' constant. */
3699 #define ASM_OUTPUT_INT(STREAM,VALUE) \
3701 fprintf (STREAM, "\t.word\t"); \
3702 output_addr_const (STREAM, (VALUE)); \
3703 fprintf (STREAM, "\n"); \
3706 /* Likewise for 64 bit, `char' and `short' constants. */
3708 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
3712 fprintf (STREAM, "\t.dword\t"); \
3713 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
3714 /* We can't use 'X' for negative numbers, because then we won't \
3715 get the right value for the upper 32 bits. */ \
3716 output_addr_const (STREAM, VALUE); \
3718 /* We must use 'X', because otherwise LONG_MIN will print as \
3719 a number that the Irix 6 assembler won't accept. */ \
3720 print_operand (STREAM, VALUE, 'X'); \
3721 fprintf (STREAM, "\n"); \
3725 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
3726 UNITS_PER_WORD, 1); \
3727 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
3728 UNITS_PER_WORD, 1); \
3732 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
3734 fprintf (STREAM, "\t.half\t"); \
3735 output_addr_const (STREAM, (VALUE)); \
3736 fprintf (STREAM, "\n"); \
3739 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
3741 fprintf (STREAM, "\t.byte\t"); \
3742 output_addr_const (STREAM, (VALUE)); \
3743 fprintf (STREAM, "\n"); \
3746 /* This is how to output an assembler line for a numeric constant byte. */
3748 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
3749 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
3751 /* This is how to output an element of a case-vector that is absolute. */
3753 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3754 fprintf (STREAM, "\t%s\t%sL%d\n", \
3755 TARGET_LONG64 ? ".dword" : ".word", \
3756 LOCAL_LABEL_PREFIX, \
3759 /* This is how to output an element of a case-vector that is relative.
3760 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3761 TARGET_EMBEDDED_PIC). */
3763 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, VALUE, REL) \
3765 if (TARGET_EMBEDDED_PIC) \
3766 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3767 TARGET_LONG64 ? ".dword" : ".word", \
3768 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3769 else if (mips_abi == ABI_32) \
3770 fprintf (STREAM, "\t%s\t%sL%d\n", \
3771 TARGET_LONG64 ? ".gpdword" : ".gpword", \
3772 LOCAL_LABEL_PREFIX, VALUE); \
3774 fprintf (STREAM, "\t%s\t%sL%d\n", \
3775 TARGET_LONG64 ? ".dword" : ".word", \
3776 LOCAL_LABEL_PREFIX, VALUE); \
3779 /* When generating embedded PIC code we want to put the jump table in
3780 the .text section. In all other cases, we want to put the jump
3781 table in the .rdata section. Unfortunately, we can't use
3782 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3783 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3784 section if appropriate. */
3785 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3787 if (TARGET_EMBEDDED_PIC) \
3789 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
3792 /* This is how to output an assembler line
3793 that says to advance the location counter
3794 to a multiple of 2**LOG bytes. */
3796 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3798 int mask = (1 << (LOG)) - 1; \
3799 fprintf (STREAM, "\t.align\t%d\n", (LOG)); \
3802 /* This is how to output an assembler line to to advance the location
3803 counter by SIZE bytes. */
3805 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3806 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
3808 /* This is how to output a string. */
3809 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3811 register int i, c, len = (LEN), cur_pos = 17; \
3812 register unsigned char *string = (unsigned char *)(STRING); \
3813 fprintf ((STREAM), "\t.ascii\t\""); \
3814 for (i = 0; i < len; i++) \
3816 register int c = string[i]; \
3822 putc ('\\', (STREAM)); \
3823 putc (c, (STREAM)); \
3827 case TARGET_NEWLINE: \
3828 fputs ("\\n", (STREAM)); \
3830 && (((c = string[i+1]) >= '\040' && c <= '~') \
3831 || c == TARGET_TAB)) \
3832 cur_pos = 32767; /* break right here */ \
3838 fputs ("\\t", (STREAM)); \
3843 fputs ("\\f", (STREAM)); \
3848 fputs ("\\b", (STREAM)); \
3853 fputs ("\\r", (STREAM)); \
3858 if (c >= ' ' && c < 0177) \
3860 putc (c, (STREAM)); \
3865 fprintf ((STREAM), "\\%03o", c); \
3870 if (cur_pos > 72 && i+1 < len) \
3873 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
3876 fprintf ((STREAM), "\"\n"); \
3879 /* Handle certain cpp directives used in header files on sysV. */
3880 #define SCCS_DIRECTIVE
3882 /* Output #ident as a in the read-only data section. */
3883 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3886 int size = strlen (p) + 1; \
3888 assemble_string (p, size); \
3891 /* Default to -G 8 */
3892 #ifndef MIPS_DEFAULT_GVALUE
3893 #define MIPS_DEFAULT_GVALUE 8
3896 /* Define the strings to put out for each section in the object file. */
3897 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3898 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3899 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3900 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3901 #define READONLY_DATA_SECTION rdata_section
3902 #define SMALL_DATA_SECTION sdata_section
3904 /* What other sections we support other than the normal .data/.text. */
3906 #define EXTRA_SECTIONS in_sdata, in_rdata
3908 /* Define the additional functions to select our additional sections. */
3910 /* on the MIPS it is not a good idea to put constants in the text
3911 section, since this defeats the sdata/data mechanism. This is
3912 especially true when -O is used. In this case an effort is made to
3913 address with faster (gp) register relative addressing, which can
3914 only get at sdata and sbss items (there is no stext !!) However,
3915 if the constant is too large for sdata, and it's readonly, it
3916 will go into the .rdata section. */
3918 #define EXTRA_SECTION_FUNCTIONS \
3922 if (in_section != in_sdata) \
3924 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
3925 in_section = in_sdata; \
3932 if (in_section != in_rdata) \
3934 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
3935 in_section = in_rdata; \
3939 /* Given a decl node or constant node, choose the section to output it in
3940 and select that section. */
3942 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
3944 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
3947 /* Store in OUTPUT a string (made with alloca) containing
3948 an assembler-name for a local static variable named NAME.
3949 LABELNO is an integer which is different for each call. */
3951 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
3952 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
3953 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
3955 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3958 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3959 TARGET_64BIT ? "dsubu" : "subu", \
3960 reg_names[STACK_POINTER_REGNUM], \
3961 reg_names[STACK_POINTER_REGNUM], \
3962 TARGET_64BIT ? "sd" : "sw", \
3964 reg_names[STACK_POINTER_REGNUM]); \
3968 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3971 if (! set_noreorder) \
3972 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3974 dslots_load_total++; \
3975 dslots_load_filled++; \
3976 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3977 TARGET_64BIT ? "ld" : "lw", \
3979 reg_names[STACK_POINTER_REGNUM], \
3980 TARGET_64BIT ? "daddu" : "addu", \
3981 reg_names[STACK_POINTER_REGNUM], \
3982 reg_names[STACK_POINTER_REGNUM]); \
3984 if (! set_noreorder) \
3985 fprintf (STREAM, "\t.set\treorder\n"); \
3989 /* Define the parentheses used to group arithmetic operations
3990 in assembler code. */
3992 #define ASM_OPEN_PAREN "("
3993 #define ASM_CLOSE_PAREN ")"
3995 /* How to start an assembler comment.
3996 The leading space is important (the mips native assembler requires it). */
3997 #ifndef ASM_COMMENT_START
3998 #define ASM_COMMENT_START " #"
4002 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4003 and mips-tdump.c to print them out.
4005 These must match the corresponding definitions in gdb/mipsread.c.
4006 Unfortunately, gcc and gdb do not currently share any directories. */
4008 #define CODE_MASK 0x8F300
4009 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4010 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4011 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4014 /* Default definitions for size_t and ptrdiff_t. */
4017 #define NO_BUILTIN_SIZE_TYPE
4018 #define SIZE_TYPE (TARGET_LONG64 ? "long unsigned int" : "unsigned int")
4021 #ifndef PTRDIFF_TYPE
4022 #define NO_BUILTIN_PTRDIFF_TYPE
4023 #define PTRDIFF_TYPE (TARGET_LONG64 ? "long int" : "int")
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