1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Contributed by A. Lichnewsky, lich@inria.inria.fr
3 Changed by Michael Meissner, meissner@osf.org
4 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
5 Brendan Eich, brendan@microunity.com.
6 Copyright (C) 1989, 90-5, 1996 Free Software Foundation, Inc.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern int flag_omit_frame_pointer;
32 extern int frame_pointer_needed;
33 extern char *language_string;
34 extern int may_call_alloca;
36 extern char **save_argv;
37 extern int target_flags;
38 extern char *version_string;
40 /* MIPS external variables defined in mips.c. */
44 CMP_SI, /* compare four byte integers */
45 CMP_DI, /* compare eight byte integers */
46 CMP_SF, /* compare single precision floats */
47 CMP_DF, /* compare double precision floats */
48 CMP_MAX /* max comparison type */
51 /* types of delay slot */
53 DELAY_NONE, /* no delay slot */
54 DELAY_LOAD, /* load from memory delay */
55 DELAY_HILO, /* move from/to hi/lo registers */
56 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
59 /* Which processor to schedule for. Since there is no difference between
60 a R2000 and R3000 in terms of the scheduler, we collapse them into
61 just an R3000. The elements of the enumeration must match exactly
62 the cpu attribute in the mips.md machine description. */
76 /* Recast the cpu class to be the cpu attribute. */
77 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
79 /* Which ABI to use. This is only used by the Irix 6 port currently. */
87 #ifndef MIPS_ABI_DEFAULT
88 /* We define this away so that there is no extra runtime cost if the target
89 doesn't support multiple ABIs. */
90 #define mips_abi ABI_32
92 extern enum mips_abi_type mips_abi;
95 /* Whether to emit abicalls code sequences or not. */
97 enum mips_abicalls_type {
102 /* Recast the abicalls class to be the abicalls attribute. */
103 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
105 /* Which type of block move to do (whether or not the last store is
106 split out so it can fill a branch delay slot). */
108 enum block_move_type {
109 BLOCK_MOVE_NORMAL, /* generate complete block move */
110 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
111 BLOCK_MOVE_LAST /* generate just the last store */
114 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
115 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
116 extern char *current_function_file; /* filename current function is in */
117 extern int num_source_filenames; /* current .file # */
118 extern int inside_function; /* != 0 if inside of a function */
119 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
120 extern int file_in_function_warning; /* warning given about .file in func */
121 extern int sdb_label_count; /* block start/end next label # */
122 extern int sdb_begin_function_line; /* Starting Line of current function */
123 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
124 extern int g_switch_value; /* value of the -G xx switch */
125 extern int g_switch_set; /* whether -G xx was passed. */
126 extern int sym_lineno; /* sgi next label # for each stmt */
127 extern int set_noreorder; /* # of nested .set noreorder's */
128 extern int set_nomacro; /* # of nested .set nomacro's */
129 extern int set_noat; /* # of nested .set noat's */
130 extern int set_volatile; /* # of nested .set volatile's */
131 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
132 extern int mips_dbx_regno[]; /* Map register # to debug register # */
133 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
134 extern enum cmp_type branch_type; /* what type of branch to use */
135 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
136 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
137 extern int mips_isa; /* architectural level */
138 extern char *mips_cpu_string; /* for -mcpu=<xxx> */
139 extern char *mips_isa_string; /* for -mips{1,2,3,4} */
140 extern char *mips_abi_string; /* for -misa={32,n32,64} */
141 extern int mips_split_addresses; /* perform high/lo_sum support */
142 extern int dslots_load_total; /* total # load related delay slots */
143 extern int dslots_load_filled; /* # filled load delay slots */
144 extern int dslots_jump_total; /* total # jump related delay slots */
145 extern int dslots_jump_filled; /* # filled jump delay slots */
146 extern int dslots_number_nops; /* # of nops needed by previous insn */
147 extern int num_refs[3]; /* # 1/2/3 word references */
148 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
149 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
150 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
151 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
152 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
154 /* Functions within mips.c that we reference. */
156 extern void abort_with_insn ();
157 extern int arith32_operand ();
158 extern int arith_operand ();
159 extern int cmp_op ();
160 extern long compute_frame_size ();
161 extern int epilogue_reg_mentioned_p ();
162 extern void expand_block_move ();
163 extern int equality_op ();
164 extern void final_prescan_insn ();
165 extern struct rtx_def * function_arg ();
166 extern void function_arg_advance ();
167 extern int function_arg_partial_nregs ();
168 extern void function_epilogue ();
169 extern void function_prologue ();
170 extern void gen_conditional_branch ();
171 extern struct rtx_def * gen_int_relational ();
172 extern void init_cumulative_args ();
173 extern int large_int ();
174 extern int mips_address_cost ();
175 extern void mips_asm_file_end ();
176 extern void mips_asm_file_start ();
177 extern int mips_const_double_ok ();
178 extern void mips_count_memory_refs ();
179 extern int mips_debugger_offset ();
180 extern void mips_declare_object ();
181 extern int mips_epilogue_delay_slots ();
182 extern void mips_expand_epilogue ();
183 extern void mips_expand_prologue ();
184 extern int mips_check_split ();
185 extern char *mips_fill_delay_slot ();
186 extern char *mips_move_1word ();
187 extern char *mips_move_2words ();
188 extern void mips_output_double ();
189 extern int mips_output_external ();
190 extern void mips_output_float ();
191 extern void mips_output_filename ();
192 extern void mips_output_lineno ();
193 extern char *output_block_move ();
194 extern void override_options ();
195 extern int pc_or_label_operand ();
196 extern void print_operand_address ();
197 extern void print_operand ();
198 extern void print_options ();
199 extern int reg_or_0_operand ();
200 extern int simple_epilogue_p ();
201 extern int simple_memory_operand ();
202 extern int small_int ();
204 extern int uns_arith_operand ();
205 extern struct rtx_def * embedded_pic_offset ();
207 /* Recognition functions that return if a condition is true. */
208 extern int address_operand ();
209 extern int const_double_operand ();
210 extern int const_int_operand ();
211 extern int general_operand ();
212 extern int immediate_operand ();
213 extern int memory_address_p ();
214 extern int memory_operand ();
215 extern int nonimmediate_operand ();
216 extern int nonmemory_operand ();
217 extern int register_operand ();
218 extern int scratch_operand ();
219 extern int move_operand ();
221 /* Functions to change what output section we are using. */
222 extern void data_section ();
223 extern void rdata_section ();
224 extern void readonly_data_section ();
225 extern void sdata_section ();
226 extern void text_section ();
228 /* Functions in the rest of the compiler that we reference. */
229 extern void abort_with_insn ();
230 extern void debug_rtx ();
231 extern void fatal_io_error ();
232 extern int get_frame_size ();
233 extern int offsettable_address_p ();
234 extern void output_address ();
235 extern char *permalloc ();
236 extern int reg_mentioned_p ();
238 /* Functions in the standard library that we reference. */
240 extern char *getenv ();
241 extern char *mktemp ();
244 /* Stubs for half-pic support if not OSF/1 reference platform. */
247 #define HALF_PIC_P() 0
248 #define HALF_PIC_NUMBER_PTRS 0
249 #define HALF_PIC_NUMBER_REFS 0
250 #define HALF_PIC_ENCODE(DECL)
251 #define HALF_PIC_DECLARE(NAME)
252 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
253 #define HALF_PIC_ADDRESS_P(X) 0
254 #define HALF_PIC_PTR(X) X
255 #define HALF_PIC_FINISH(STREAM)
259 /* Run-time compilation parameters selecting different hardware subsets. */
261 /* Macros used in the machine description to test the flags. */
263 /* Bits for real switches */
264 #define MASK_INT64 0x00000001 /* ints are 64 bits */
265 #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
266 #define MASK_UNUSED 0x00000004
267 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
268 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
269 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
270 #define MASK_STATS 0x00000040 /* print statistics to stderr */
271 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
272 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
273 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
274 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
275 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
276 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
277 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
278 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
279 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
280 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
281 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
282 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
283 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
285 /* Dummy switches used only in spec's*/
286 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
288 /* Debug switches, not documented */
289 #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */
290 #define MASK_DEBUG_A 0x20000000 /* don't allow <label>($reg) addrs */
291 #define MASK_DEBUG_B 0x10000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
292 #define MASK_DEBUG_C 0x08000000 /* don't expand seq, etc. */
293 #define MASK_DEBUG_D 0x04000000 /* don't do define_split's */
294 #define MASK_DEBUG_E 0x02000000 /* function_arg debug */
295 #define MASK_DEBUG_F 0x01000000 /* don't try to suppress load nop's */
296 #define MASK_DEBUG_G 0x00800000 /* don't support 64 bit arithmetic */
297 #define MASK_DEBUG_H 0x00400000 /* allow ints in FP registers */
298 #define MASK_DEBUG_I 0x00200000 /* unused */
299 #define MASK_DEBUG_J 0x00100000 /* unused */
301 /* r4000 64 bit sizes */
302 #define TARGET_INT64 (target_flags & MASK_INT64)
303 #define TARGET_LONG64 (target_flags & MASK_LONG64)
304 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
305 #define TARGET_64BIT (target_flags & MASK_64BIT)
307 /* Mips vs. GNU assembler */
308 #define TARGET_GAS (target_flags & MASK_GAS)
309 #define TARGET_UNIX_ASM (!TARGET_GAS)
310 #define TARGET_MIPS_AS TARGET_UNIX_ASM
313 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
314 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
315 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
316 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
317 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
318 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
319 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
320 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
321 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
322 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
323 #define TARGET_DEBUG_J_MODE (target_flags & MASK_DEBUG_J)
325 /* Reg. Naming in .s ($21 vs. $a0) */
326 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
328 /* Optimize for Sdata/Sbss */
329 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
331 /* print program statistics */
332 #define TARGET_STATS (target_flags & MASK_STATS)
334 /* call memcpy instead of inline code */
335 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
337 /* .abicalls, etc from Pyramid V.4 */
338 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
340 /* OSF pic references to externs */
341 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
343 /* software floating point */
344 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
345 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
347 /* always call through a register */
348 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
350 /* generate embedded PIC code;
352 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
354 /* for embedded systems, optimize for
355 reduced RAM space instead of for
357 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
359 /* generate big endian code. */
360 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
362 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
363 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
365 #define TARGET_MAD (target_flags & MASK_MAD)
367 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
369 /* Macro to define tables used to set the flags.
370 This is a list in braces of pairs in braces,
371 each pair being { "NAME", VALUE }
372 where VALUE is the bits to set or minus the bits to clear.
373 An empty string NAME is used to identify the default VALUE. */
375 #define TARGET_SWITCHES \
377 {"int64", MASK_INT64 | MASK_LONG64}, \
378 {"long64", MASK_LONG64}, \
379 {"mips-as", -MASK_GAS}, \
381 {"rnames", MASK_NAME_REGS}, \
382 {"no-rnames", -MASK_NAME_REGS}, \
383 {"gpOPT", MASK_GPOPT}, \
384 {"gpopt", MASK_GPOPT}, \
385 {"no-gpOPT", -MASK_GPOPT}, \
386 {"no-gpopt", -MASK_GPOPT}, \
387 {"stats", MASK_STATS}, \
388 {"no-stats", -MASK_STATS}, \
389 {"memcpy", MASK_MEMCPY}, \
390 {"no-memcpy", -MASK_MEMCPY}, \
391 {"mips-tfile", MASK_MIPS_TFILE}, \
392 {"no-mips-tfile", -MASK_MIPS_TFILE}, \
393 {"soft-float", MASK_SOFT_FLOAT}, \
394 {"hard-float", -MASK_SOFT_FLOAT}, \
395 {"fp64", MASK_FLOAT64}, \
396 {"fp32", -MASK_FLOAT64}, \
397 {"gp64", MASK_64BIT}, \
398 {"gp32", -MASK_64BIT}, \
399 {"abicalls", MASK_ABICALLS}, \
400 {"no-abicalls", -MASK_ABICALLS}, \
401 {"half-pic", MASK_HALF_PIC}, \
402 {"no-half-pic", -MASK_HALF_PIC}, \
403 {"long-calls", MASK_LONG_CALLS}, \
404 {"no-long-calls", -MASK_LONG_CALLS}, \
405 {"embedded-pic", MASK_EMBEDDED_PIC}, \
406 {"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
407 {"embedded-data", MASK_EMBEDDED_DATA}, \
408 {"no-embedded-data", -MASK_EMBEDDED_DATA}, \
409 {"eb", MASK_BIG_ENDIAN}, \
410 {"el", -MASK_BIG_ENDIAN}, \
411 {"single-float", MASK_SINGLE_FLOAT}, \
412 {"double-float", -MASK_SINGLE_FLOAT}, \
414 {"no-mad", -MASK_MAD}, \
415 {"fix4300", MASK_4300_MUL_FIX}, \
416 {"no-fix4300", -MASK_4300_MUL_FIX}, \
417 {"4650", MASK_MAD | MASK_SINGLE_FLOAT}, \
418 {"debug", MASK_DEBUG}, \
419 {"debuga", MASK_DEBUG_A}, \
420 {"debugb", MASK_DEBUG_B}, \
421 {"debugc", MASK_DEBUG_C}, \
422 {"debugd", MASK_DEBUG_D}, \
423 {"debuge", MASK_DEBUG_E}, \
424 {"debugf", MASK_DEBUG_F}, \
425 {"debugg", MASK_DEBUG_G}, \
426 {"debugh", MASK_DEBUG_H}, \
427 {"debugi", MASK_DEBUG_I}, \
428 {"debugj", MASK_DEBUG_J}, \
429 {"", (TARGET_DEFAULT \
430 | TARGET_CPU_DEFAULT \
431 | TARGET_ENDIAN_DEFAULT)} \
434 /* Default target_flags if no switches are specified */
436 #ifndef TARGET_DEFAULT
437 #define TARGET_DEFAULT 0
440 #ifndef TARGET_CPU_DEFAULT
441 #define TARGET_CPU_DEFAULT 0
444 #ifndef TARGET_ENDIAN_DEFAULT
446 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
448 #define TARGET_ENDIAN_DEFAULT 0
452 #ifndef MULTILIB_DEFAULTS
453 #if TARGET_ENDIAN_DEFAULT == 0
454 #define MULTILIB_DEFAULTS { "EL", "mips1" }
456 #define MULTILIB_DEFAULTS { "EB", "mips1" }
460 /* This macro is similar to `TARGET_SWITCHES' but defines names of
461 command options that have values. Its definition is an
462 initializer with a subgrouping for each command option.
464 Each subgrouping contains a string constant, that defines the
465 fixed part of the option name, and the address of a variable.
466 The variable, type `char *', is set to the variable part of the
467 given option if the fixed part matches. The actual option name
468 is made by appending `-m' to the specified name.
470 Here is an example which defines `-mshort-data-NUMBER'. If the
471 given option is `-mshort-data-512', the variable `m88k_short_data'
472 will be set to the string `"512"'.
474 extern char *m88k_short_data;
475 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
477 #define TARGET_OPTIONS \
479 SUBTARGET_TARGET_OPTIONS \
480 { "cpu=", &mips_cpu_string }, \
481 { "ips", &mips_isa_string } \
484 /* This is meant to be redefined in the host dependent files. */
485 #define SUBTARGET_TARGET_OPTIONS
487 /* Macros to decide whether certain features are available or not,
488 depending on the instruction set architecture level. */
490 #define BRANCH_LIKELY_P() (mips_isa >= 2)
491 #define HAVE_SQRT_P() (mips_isa >= 2)
493 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
494 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
495 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
496 target_flags, and -mgp64 sets MASK_64BIT.
498 Setting MASK_64BIT in target_flags will cause gcc to assume that
499 registers are 64 bits wide. int, long and void * will be 32 bit;
500 this may be changed with -mint64 or -mlong64.
502 The gen* programs link code that refers to MASK_64BIT. They don't
503 actually use the information in target_flags; they just refer to
506 /* Switch Recognition by gcc.c. Add -G xx support */
508 #ifdef SWITCH_TAKES_ARG
509 #undef SWITCH_TAKES_ARG
512 #define SWITCH_TAKES_ARG(CHAR) \
513 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
515 /* Sometimes certain combinations of command options do not make sense
516 on a particular target machine. You can define a macro
517 `OVERRIDE_OPTIONS' to take account of this. This macro, if
518 defined, is executed once just after all the command options have
521 On the MIPS, it is used to handle -G. We also use it to set up all
522 of the tables referenced in the other macros. */
524 #define OVERRIDE_OPTIONS override_options ()
526 /* Zero or more C statements that may conditionally modify two
527 variables `fixed_regs' and `call_used_regs' (both of type `char
528 []') after they have been initialized from the two preceding
531 This is necessary in case the fixed or call-clobbered registers
532 depend on target flags.
534 You need not define this macro if it has no work to do.
536 If the usage of an entire class of registers depends on the target
537 flags, you may indicate this to GCC by using this macro to modify
538 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
539 the classes which should not be used by GCC. Also define the macro
540 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
541 letter for a class that shouldn't be used.
543 (However, if this class is not included in `GENERAL_REGS' and all
544 of the insn patterns whose constraints permit this class are
545 controlled by target switches, then GCC will automatically avoid
546 using these registers when the target switches are opposed to
549 #define CONDITIONAL_REGISTER_USAGE \
552 if (!TARGET_HARD_FLOAT) \
556 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
557 fixed_regs[regno] = call_used_regs[regno] = 1; \
559 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
563 /* This is meant to be redefined in the host dependent files. */
564 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
566 /* Show we can debug even without a frame pointer. */
567 #define CAN_DEBUG_WITHOUT_FP
569 /* Complain about missing specs and predefines that should be defined in each
570 of the target tm files to override the defaults. This is mostly a place-
571 holder until I can get each of the files updated [mm]. */
573 #if defined(OSF_OS) \
574 || defined(DECSTATION) \
575 || defined(SGI_TARGET) \
576 || defined(MIPS_NEWS) \
577 || defined(MIPS_SYSV) \
578 || defined(MIPS_SVR4) \
579 || defined(MIPS_BSD43)
581 #ifndef CPP_PREDEFINES
582 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
586 #error "Define LIB_SPEC in the appropriate tm.h file"
589 #ifndef STARTFILE_SPEC
590 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
594 #error "Define MACHINE_TYPE in the appropriate tm.h file"
598 /* Tell collect what flags to pass to nm. */
600 #define NM_FLAGS "-Bp"
604 /* Names to predefine in the preprocessor for this target machine. */
606 #ifndef CPP_PREDEFINES
607 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
608 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
609 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
612 /* Extra switches sometimes passed to the assembler. */
615 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
619 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
620 %{pipe: %e-pipe is not supported.} \
623 %{mcpu=*} %{m4650} %{mmad:-m4650}} \
624 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{v} \
626 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}} \
627 %{g} %{g0} %{g1} %{g2} %{g3} \
628 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
629 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
630 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
631 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
638 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
639 %{pipe: %e-pipe is not supported.} \
642 %{mcpu=*} %{m4650} %{mmad:-m4650}} \
643 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{v} \
645 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}} \
646 %{g} %{g0} %{g1} %{g2} %{g3} \
647 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
648 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
649 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
650 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
654 #endif /* ASM_SPEC */
656 /* Specify to run a post-processor, mips-tfile after the assembler
657 has run to stuff the mips debug information into the object file.
658 This is needed because the $#!%^ MIPS assembler provides no way
659 of specifying such information in the assembly file. If we are
660 cross compiling, disable mips-tfile unless the user specifies
663 #ifndef ASM_FINAL_SPEC
664 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
666 #define ASM_FINAL_SPEC "\
667 %{mmips-as: %{!mno-mips-tfile: \
668 \n mips-tfile %{v*: -v} \
670 %{!K: %{save-temps: -I %b.o~}} \
671 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
672 %{.s:%i} %{!.s:%g.s}}}"
676 #define ASM_FINAL_SPEC "\
677 %{!mgas: %{!mno-mips-tfile: \
678 \n mips-tfile %{v*: -v} \
680 %{!K: %{save-temps: -I %b.o~}} \
681 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
682 %{.s:%i} %{!.s:%g.s}}}"
685 #endif /* ASM_FINAL_SPEC */
687 /* Redefinition of libraries used. Mips doesn't support normal
688 UNIX style profiling via calling _mcount. It does offer
689 profiling that samples the PC, so do what we can... */
692 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
695 /* Extra switches sometimes passed to the linker. */
696 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
697 will interpret it as a -b option. */
701 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
702 %{bestGnum} %{shared} %{non_shared}"
703 #endif /* LINK_SPEC defined */
705 /* Specs for the compiler proper */
709 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
710 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
711 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
712 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
713 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
714 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
715 %{m4650:-mcpu=r4650} \
716 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
717 %{pic-none: -mno-half-pic} \
718 %{pic-lib: -mhalf-pic} \
719 %{pic-extern: -mhalf-pic} \
720 %{pic-calls: -mhalf-pic} \
724 /* Preprocessor specs */
728 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
729 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
730 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
731 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C} \
732 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
733 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
734 %{!.S:%{!.s: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}} \
735 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
736 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
737 %{mips3:-U__mips -D__mips=3 -D__mips64} \
738 %{mips4:-U__mips -D__mips=4 -D__mips64} \
739 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
740 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
741 %{m4650:%{!msoft-float:-D__mips_single_float}} \
742 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
743 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}}"
746 /* If defined, this macro is an additional prefix to try after
747 `STANDARD_EXEC_PREFIX'. */
749 #ifndef MD_EXEC_PREFIX
750 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
753 #ifndef MD_STARTFILE_PREFIX
754 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
758 /* Print subsidiary information on the compiler version in use. */
760 #define MIPS_VERSION "[AL 1.1, MM 40]"
763 #define MACHINE_TYPE "BSD Mips"
766 #ifndef TARGET_VERSION_INTERNAL
767 #define TARGET_VERSION_INTERNAL(STREAM) \
768 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
771 #ifndef TARGET_VERSION
772 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
776 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
777 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
778 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
780 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
781 #define PREFERRED_DEBUGGING_TYPE ((len > 1 && !strncmp (str, "ggdb", len)) ? DBX_DEBUG : SDB_DEBUG)
784 /* By default, turn on GDB extensions. */
785 #define DEFAULT_GDB_EXTENSIONS 1
787 /* If we are passing smuggling stabs through the MIPS ECOFF object
788 format, put a comment in front of the .stab<x> operation so
789 that the MIPS assembler does not choke. The mips-tfile program
790 will correctly put the stab into the object file. */
792 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
793 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
794 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
796 /* Local compiler-generated symbols must have a prefix that the assembler
797 understands. By default, this is $, although some targets (e.g.,
798 NetBSD-ELF) need to override this. */
800 #ifndef LOCAL_LABEL_PREFIX
801 #define LOCAL_LABEL_PREFIX "$"
804 /* By default on the mips, external symbols do not have an underscore
805 prepended, but some targets (e.g., NetBSD) require this. */
807 #ifndef USER_LABEL_PREFIX
808 #define USER_LABEL_PREFIX ""
811 /* Forward references to tags are allowed. */
812 #define SDB_ALLOW_FORWARD_REFERENCES
814 /* Unknown tags are also allowed. */
815 #define SDB_ALLOW_UNKNOWN_REFERENCES
817 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
818 since the length can run past this up to a continuation point. */
819 #define DBX_CONTIN_LENGTH 1500
822 /* How to renumber registers for dbx and gdb. */
823 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
826 /* Overrides for the COFF debug format. */
827 #define PUT_SDB_SCL(a) \
829 extern FILE *asm_out_text_file; \
830 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
833 #define PUT_SDB_INT_VAL(a) \
835 extern FILE *asm_out_text_file; \
836 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
839 #define PUT_SDB_VAL(a) \
841 extern FILE *asm_out_text_file; \
842 fputs ("\t.val\t", asm_out_text_file); \
843 output_addr_const (asm_out_text_file, (a)); \
844 fputc (';', asm_out_text_file); \
847 #define PUT_SDB_DEF(a) \
849 extern FILE *asm_out_text_file; \
850 fprintf (asm_out_text_file, "\t%s.def\t", \
851 (TARGET_GAS) ? "" : "#"); \
852 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
853 fputc (';', asm_out_text_file); \
856 #define PUT_SDB_PLAIN_DEF(a) \
858 extern FILE *asm_out_text_file; \
859 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
860 (TARGET_GAS) ? "" : "#", (a)); \
863 #define PUT_SDB_ENDEF \
865 extern FILE *asm_out_text_file; \
866 fprintf (asm_out_text_file, "\t.endef\n"); \
869 #define PUT_SDB_TYPE(a) \
871 extern FILE *asm_out_text_file; \
872 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
875 #define PUT_SDB_SIZE(a) \
877 extern FILE *asm_out_text_file; \
878 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
881 #define PUT_SDB_DIM(a) \
883 extern FILE *asm_out_text_file; \
884 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
887 #ifndef PUT_SDB_START_DIM
888 #define PUT_SDB_START_DIM \
890 extern FILE *asm_out_text_file; \
891 fprintf (asm_out_text_file, "\t.dim\t"); \
895 #ifndef PUT_SDB_NEXT_DIM
896 #define PUT_SDB_NEXT_DIM(a) \
898 extern FILE *asm_out_text_file; \
899 fprintf (asm_out_text_file, "%d,", a); \
903 #ifndef PUT_SDB_LAST_DIM
904 #define PUT_SDB_LAST_DIM(a) \
906 extern FILE *asm_out_text_file; \
907 fprintf (asm_out_text_file, "%d;", a); \
911 #define PUT_SDB_TAG(a) \
913 extern FILE *asm_out_text_file; \
914 fprintf (asm_out_text_file, "\t.tag\t"); \
915 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
916 fputc (';', asm_out_text_file); \
919 /* For block start and end, we create labels, so that
920 later we can figure out where the correct offset is.
921 The normal .ent/.end serve well enough for functions,
922 so those are just commented out. */
924 #define PUT_SDB_BLOCK_START(LINE) \
926 extern FILE *asm_out_text_file; \
927 fprintf (asm_out_text_file, \
928 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
929 LOCAL_LABEL_PREFIX, \
931 (TARGET_GAS) ? "" : "#", \
932 LOCAL_LABEL_PREFIX, \
938 #define PUT_SDB_BLOCK_END(LINE) \
940 extern FILE *asm_out_text_file; \
941 fprintf (asm_out_text_file, \
942 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
943 LOCAL_LABEL_PREFIX, \
945 (TARGET_GAS) ? "" : "#", \
946 LOCAL_LABEL_PREFIX, \
952 #define PUT_SDB_FUNCTION_START(LINE)
954 #define PUT_SDB_FUNCTION_END(LINE) \
956 extern FILE *asm_out_text_file; \
957 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
960 #define PUT_SDB_EPILOGUE_END(NAME)
962 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
963 sprintf ((BUFFER), ".%dfake", (NUMBER));
965 /* Correct the offset of automatic variables and arguments. Note that
966 the MIPS debug format wants all automatic variables and arguments
967 to be in terms of the virtual frame pointer (stack pointer before
968 any adjustment in the function), while the MIPS 3.0 linker wants
969 the frame pointer to be the stack pointer after the initial
972 #define DEBUGGER_AUTO_OFFSET(X) mips_debugger_offset (X, 0)
973 #define DEBUGGER_ARG_OFFSET(OFFSET, X) mips_debugger_offset (X, OFFSET)
976 /* Tell collect that the object format is ECOFF */
977 #ifndef OBJECT_FORMAT_ROSE
978 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
979 #define EXTENDED_COFF /* ECOFF, not normal coff */
982 #if 0 /* These definitions normally have no effect because
983 MIPS systems define USE_COLLECT2, so
984 assemble_constructor does nothing anyway. */
986 /* Don't use the default definitions, because we don't have gld.
987 Also, we don't want stabs when generating ECOFF output.
988 Instead we depend on collect to handle these. */
990 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
991 #define ASM_OUTPUT_DESTRUCTOR(file, name)
995 /* Target machine storage layout */
997 /* Define in order to support both big and little endian float formats
998 in the same gcc binary. */
999 #define REAL_ARITHMETIC
1001 /* Define this if most significant bit is lowest numbered
1002 in instructions that operate on numbered bit-fields.
1004 #define BITS_BIG_ENDIAN 0
1006 /* Define this if most significant byte of a word is the lowest numbered. */
1007 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1009 /* Define this if most significant word of a multiword number is the lowest. */
1010 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1012 /* Define this to set the endianness to use in libgcc2.c, which can
1013 not depend on target_flags. */
1014 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1015 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1017 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1020 /* Number of bits in an addressable storage unit */
1021 #define BITS_PER_UNIT 8
1023 /* Width in bits of a "word", which is the contents of a machine register.
1024 Note that this is not necessarily the width of data type `int';
1025 if using 16-bit ints on a 68000, this would still be 32.
1026 But on a machine with 16-bit registers, this would be 16. */
1027 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1028 #define MAX_BITS_PER_WORD 64
1030 /* Width of a word, in units (bytes). */
1031 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1032 #define MIN_UNITS_PER_WORD 4
1034 /* For MIPS, width of a floating point register. */
1035 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1037 /* A C expression for the size in bits of the type `int' on the
1038 target machine. If you don't define this, the default is one
1040 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1041 #define MAX_INT_TYPE_SIZE 64
1043 /* Tell the preprocessor the maximum size of wchar_t. */
1044 #ifndef MAX_WCHAR_TYPE_SIZE
1045 #ifndef WCHAR_TYPE_SIZE
1046 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1050 /* A C expression for the size in bits of the type `short' on the
1051 target machine. If you don't define this, the default is half a
1052 word. (If this would be less than one storage unit, it is
1053 rounded up to one unit.) */
1054 #define SHORT_TYPE_SIZE 16
1056 /* A C expression for the size in bits of the type `long' on the
1057 target machine. If you don't define this, the default is one
1059 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1060 #define MAX_LONG_TYPE_SIZE 64
1062 /* A C expression for the size in bits of the type `long long' on the
1063 target machine. If you don't define this, the default is two
1065 #define LONG_LONG_TYPE_SIZE 64
1067 /* A C expression for the size in bits of the type `char' on the
1068 target machine. If you don't define this, the default is one
1069 quarter of a word. (If this would be less than one storage unit,
1070 it is rounded up to one unit.) */
1071 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1073 /* A C expression for the size in bits of the type `float' on the
1074 target machine. If you don't define this, the default is one
1076 #define FLOAT_TYPE_SIZE 32
1078 /* A C expression for the size in bits of the type `double' on the
1079 target machine. If you don't define this, the default is two
1081 #define DOUBLE_TYPE_SIZE 64
1083 /* A C expression for the size in bits of the type `long double' on
1084 the target machine. If you don't define this, the default is two
1086 #define LONG_DOUBLE_TYPE_SIZE 64
1088 /* Width in bits of a pointer.
1089 See also the macro `Pmode' defined below. */
1090 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1092 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1093 #define POINTER_BOUNDARY (TARGET_LONG64 ? 64 : 32)
1095 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1096 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1098 /* Allocation boundary (in *bits*) for the code of a function. */
1099 #define FUNCTION_BOUNDARY 32
1101 /* Alignment of field after `int : 0' in a structure. */
1102 #define EMPTY_FIELD_BOUNDARY (TARGET_LONG64 ? 64 : 32)
1104 /* Every structure's size must be a multiple of this. */
1105 /* 8 is observed right on a DECstation and on riscos 4.02. */
1106 #define STRUCTURE_SIZE_BOUNDARY 8
1108 /* There is no point aligning anything to a rounder boundary than this. */
1109 #define BIGGEST_ALIGNMENT 64
1111 /* Biggest alignment any structure field can require in bits. */
1112 #define BIGGEST_FIELD_ALIGNMENT 64
1114 /* Set this nonzero if move instructions will actually fail to work
1115 when given unaligned data. */
1116 #define STRICT_ALIGNMENT 1
1118 /* Define this if you wish to imitate the way many other C compilers
1119 handle alignment of bitfields and the structures that contain
1122 The behavior is that the type written for a bitfield (`int',
1123 `short', or other integer type) imposes an alignment for the
1124 entire structure, as if the structure really did contain an
1125 ordinary field of that type. In addition, the bitfield is placed
1126 within the structure so that it would fit within such a field,
1127 not crossing a boundary for it.
1129 Thus, on most machines, a bitfield whose type is written as `int'
1130 would not cross a four-byte boundary, and would force four-byte
1131 alignment for the whole structure. (The alignment used may not
1132 be four bytes; it is controlled by the other alignment
1135 If the macro is defined, its definition should be a C expression;
1136 a nonzero value for the expression enables this behavior. */
1138 #define PCC_BITFIELD_TYPE_MATTERS 1
1140 /* If defined, a C expression to compute the alignment given to a
1141 constant that is being placed in memory. CONSTANT is the constant
1142 and ALIGN is the alignment that the object would ordinarily have.
1143 The value of this macro is used instead of that alignment to align
1146 If this macro is not defined, then ALIGN is used.
1148 The typical use of this macro is to increase alignment for string
1149 constants to be word aligned so that `strcpy' calls that copy
1150 constants can be done inline. */
1152 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1153 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1154 && (ALIGN) < BITS_PER_WORD \
1158 /* If defined, a C expression to compute the alignment for a static
1159 variable. TYPE is the data type, and ALIGN is the alignment that
1160 the object would ordinarily have. The value of this macro is used
1161 instead of that alignment to align the object.
1163 If this macro is not defined, then ALIGN is used.
1165 One use of this macro is to increase alignment of medium-size
1166 data to make it all fit in fewer cache lines. Another is to
1167 cause character arrays to be word-aligned so that `strcpy' calls
1168 that copy constants to character arrays can be done inline. */
1170 #undef DATA_ALIGNMENT
1171 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1172 ((((ALIGN) < BITS_PER_WORD) \
1173 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1174 || TREE_CODE (TYPE) == UNION_TYPE \
1175 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1177 /* Define this macro if an argument declared as `char' or `short' in a
1178 prototype should actually be passed as an `int'. In addition to
1179 avoiding errors in certain cases of mismatch, it also makes for
1180 better code on certain machines. */
1182 #define PROMOTE_PROTOTYPES
1184 /* Define if operations between registers always perform the operation
1185 on the full register even if a narrower mode is specified. */
1186 #define WORD_REGISTER_OPERATIONS
1188 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1189 will either zero-extend or sign-extend. The value of this macro should
1190 be the code that says which one of the two operations is implicitly
1191 done, NIL if none. */
1192 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1194 /* Standard register usage. */
1196 /* Number of actual hardware registers.
1197 The hardware registers are assigned numbers for the compiler
1198 from 0 to just below FIRST_PSEUDO_REGISTER.
1199 All registers that the compiler knows about must be given numbers,
1200 even those that are not normally considered general registers.
1202 On the Mips, we have 32 integer registers, 32 floating point
1203 registers and the special registers hi, lo, hilo, fp status, and rap.
1204 The hilo register is only used in 64 bit mode. It represents a 64
1205 bit value stored as two 32 bit values in the hi and lo registers;
1206 this is the result of the mult instruction. rap is a pointer to the
1207 stack where the return address reg ($31) was stored. This is needed
1208 for C++ exception handling. */
1210 #define FIRST_PSEUDO_REGISTER 69
1212 /* 1 for registers that have pervasive standard uses
1213 and are not available for the register allocator.
1215 On the MIPS, see conventions, page D-2 */
1217 #define FIXED_REGISTERS \
1219 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1227 /* 1 for registers not available across function calls.
1228 These must include the FIXED_REGISTERS and also any
1229 registers that can be used without being saved.
1230 The latter must include the registers where values are returned
1231 and the register where structure-value addresses are passed.
1232 Aside from that, you can include as many other registers as you like. */
1234 #define CALL_USED_REGISTERS \
1236 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1237 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1238 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1239 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1244 /* Internal macros to classify a register number as to whether it's a
1245 general purpose register, a floating point register, a
1246 multiply/divide register, or a status register. */
1248 #define GP_REG_FIRST 0
1249 #define GP_REG_LAST 31
1250 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1251 #define GP_DBX_FIRST 0
1253 #define FP_REG_FIRST 32
1254 #define FP_REG_LAST 63
1255 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1256 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1258 #define MD_REG_FIRST 64
1259 #define MD_REG_LAST 66
1260 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1262 #define ST_REG_FIRST 67
1263 #define ST_REG_LAST 67
1264 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1266 #define RAP_REG_NUM 68
1268 #define AT_REGNUM (GP_REG_FIRST + 1)
1269 #define HI_REGNUM (MD_REG_FIRST + 0)
1270 #define LO_REGNUM (MD_REG_FIRST + 1)
1271 #define HILO_REGNUM (MD_REG_FIRST + 2)
1272 #define FPSW_REGNUM ST_REG_FIRST
1274 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1275 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1276 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1277 #define ST_REG_P(REGNO) ((REGNO) == ST_REG_FIRST)
1279 /* Return number of consecutive hard regs needed starting at reg REGNO
1280 to hold something of mode MODE.
1281 This is ordinarily the length in words of a value of mode MODE
1282 but can be less for certain modes in special long registers.
1284 On the MIPS, all general registers are one word long. Except on
1285 the R4000 with the FR bit set, the floating point uses register
1286 pairs, with the second register not being allocatable. */
1288 #define HARD_REGNO_NREGS(REGNO, MODE) \
1289 (! FP_REG_P (REGNO) \
1290 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1291 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1293 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1294 MODE. In 32 bit mode, require that DImode and DFmode be in even
1295 registers. For DImode, this makes some of the insns easier to
1296 write, since you don't have to worry about a DImode value in
1297 registers 3 & 4, producing a result in 4 & 5.
1299 To make the code simpler HARD_REGNO_MODE_OK now just references an
1300 array built in override_options. Because machmodes.h is not yet
1301 included before this file is processed, the MODE bound can't be
1304 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1306 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1307 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1309 /* Value is 1 if it is a good idea to tie two pseudo registers
1310 when one has mode MODE1 and one has mode MODE2.
1311 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1312 for any hard reg, then this must be 0 for correct output. */
1313 #define MODES_TIEABLE_P(MODE1, MODE2) \
1314 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1315 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1316 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1317 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1319 /* MIPS pc is not overloaded on a register. */
1320 /* #define PC_REGNUM xx */
1322 /* Register to use for pushing function arguments. */
1323 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1325 /* Offset from the stack pointer to the first available location. */
1326 #define STACK_POINTER_OFFSET 0
1328 /* Base register for access to local variables of the function. */
1329 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 30)
1331 /* Value should be nonzero if functions must have frame pointers.
1332 Zero means the frame pointer need not be set up (and parms
1333 may be accessed via the stack pointer) in functions that seem suitable.
1334 This is computed in `reload', in reload1.c. */
1335 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1337 /* Base register for access to arguments of the function. */
1338 #define ARG_POINTER_REGNUM GP_REG_FIRST
1340 /* Fake register that holds the address on the stack of the
1341 current function's return address. */
1342 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1344 /* Register in which static-chain is passed to a function. */
1345 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1347 /* If the structure value address is passed in a register, then
1348 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1349 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1351 /* If the structure value address is not passed in a register, define
1352 `STRUCT_VALUE' as an expression returning an RTX for the place
1353 where the address is passed. If it returns 0, the address is
1354 passed as an "invisible" first argument. */
1355 #define STRUCT_VALUE 0
1357 /* Mips registers used in prologue/epilogue code when the stack frame
1358 is larger than 32K bytes. These registers must come from the
1359 scratch register set, and not used for passing and returning
1360 arguments and any other information used in the calling sequence
1361 (such as pic). Must start at 12, since t0/t3 are parameter passing
1362 registers in the 64 bit ABI. */
1364 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1365 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1367 /* Define this macro if it is as good or better to call a constant
1368 function address than to call an address kept in a register. */
1369 #define NO_FUNCTION_CSE 1
1371 /* Define this macro if it is as good or better for a function to
1372 call itself with an explicit address than to call an address
1373 kept in a register. */
1374 #define NO_RECURSIVE_FUNCTION_CSE 1
1376 /* The register number of the register used to address a table of
1377 static data addresses in memory. In some cases this register is
1378 defined by a processor's "application binary interface" (ABI).
1379 When this macro is defined, RTL is generated for this register
1380 once, as with the stack pointer and frame pointer registers. If
1381 this macro is not defined, it is up to the machine-dependent
1382 files to allocate such a register (if necessary). */
1383 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1385 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1387 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1388 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1389 isn't always called for static inline functions. */
1390 #define INIT_EXPANDERS embedded_pic_fnaddr_rtx = NULL;
1392 /* Define the classes of registers for register constraints in the
1393 machine description. Also define ranges of constants.
1395 One of the classes must always be named ALL_REGS and include all hard regs.
1396 If there is more than one class, another class must be named NO_REGS
1397 and contain no registers.
1399 The name GENERAL_REGS must be the name of a class (or an alias for
1400 another name such as ALL_REGS). This is the class of registers
1401 that is allowed by "g" or "r" in a register constraint.
1402 Also, registers outside this class are allocated only when
1403 instructions express preferences for them.
1405 The classes must be numbered in nondecreasing order; that is,
1406 a larger-numbered class must never be contained completely
1407 in a smaller-numbered class.
1409 For any two classes, it is very desirable that there be another
1410 class that represents their union. */
1414 NO_REGS, /* no registers in set */
1415 GR_REGS, /* integer registers */
1416 FP_REGS, /* floating point registers */
1417 HI_REG, /* hi register */
1418 LO_REG, /* lo register */
1419 HILO_REG, /* hilo register pair for 64 bit mode mult */
1420 MD_REGS, /* multiply/divide registers (hi/lo) */
1421 ST_REGS, /* status registers (fp status) */
1422 ALL_REGS, /* all registers */
1423 LIM_REG_CLASSES /* max value + 1 */
1426 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1428 #define GENERAL_REGS GR_REGS
1430 /* An initializer containing the names of the register classes as C
1431 string constants. These names are used in writing some of the
1434 #define REG_CLASS_NAMES \
1447 /* An initializer containing the contents of the register classes,
1448 as integers which are bit masks. The Nth integer specifies the
1449 contents of class N. The way the integer MASK is interpreted is
1450 that register R is in the class if `MASK & (1 << R)' is 1.
1452 When the machine has more than 32 registers, an integer does not
1453 suffice. Then the integers are replaced by sub-initializers,
1454 braced groupings containing several integers. Each
1455 sub-initializer must be suitable as an initializer for the type
1456 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1458 #define REG_CLASS_CONTENTS \
1460 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1461 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1462 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1463 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1464 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1465 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1466 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1467 { 0x00000000, 0x00000000, 0x00000008 }, /* status registers */ \
1468 { 0xffffffff, 0xffffffff, 0x0000000f } /* all registers */ \
1472 /* A C expression whose value is a register class containing hard
1473 register REGNO. In general there is more that one such class;
1474 choose a class which is "minimal", meaning that no smaller class
1475 also contains the register. */
1477 extern enum reg_class mips_regno_to_class[];
1479 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1481 /* A macro whose definition is the name of the class to which a
1482 valid base register must belong. A base register is one used in
1483 an address which is the register value plus a displacement. */
1485 #define BASE_REG_CLASS GR_REGS
1487 /* A macro whose definition is the name of the class to which a
1488 valid index register must belong. An index register is one used
1489 in an address where its value is either multiplied by a scale
1490 factor or added to another register (as well as added to a
1493 #define INDEX_REG_CLASS NO_REGS
1496 /* REGISTER AND CONSTANT CLASSES */
1498 /* Get reg_class from a letter such as appears in the machine
1501 DEFINED REGISTER CLASSES:
1503 'd' General (aka integer) registers
1504 'f' Floating point registers
1507 'x' Multiply/divide registers
1509 'z' FP Status register
1510 'b' All registers */
1512 extern enum reg_class mips_char_to_class[];
1514 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1516 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1517 string can be used to stand for particular ranges of immediate
1518 operands. This macro defines what the ranges are. C is the
1519 letter, and VALUE is a constant value. Return 1 if VALUE is
1520 in the range specified by C. */
1524 `I' is used for the range of constants an arithmetic insn can
1525 actually contain (16 bits signed integers).
1527 `J' is used for the range which is just zero (ie, $r0).
1529 `K' is used for the range of constants a logical insn can actually
1530 contain (16 bit zero-extended integers).
1532 `L' is used for the range of constants that be loaded with lui
1533 (ie, the bottom 16 bits are zero).
1535 `M' is used for the range of constants that take two words to load
1536 (ie, not matched by `I', `K', and `L').
1538 `N' is used for negative 16 bit constants.
1540 `O' is an exact power of 2 (not yet used in the md file).
1542 `P' is used for positive 16 bit constants. */
1544 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1545 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1547 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1548 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1549 : (C) == 'J' ? ((VALUE) == 0) \
1550 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1551 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1552 && (((VALUE) & ~2147483647) == 0 \
1553 || ((VALUE) & ~2147483647) == ~2147483647)) \
1554 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1555 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1556 && (((VALUE) & 0x0000ffff) != 0 \
1557 || (((VALUE) & ~2147483647) != 0 \
1558 && ((VALUE) & ~2147483647) != ~2147483647))) \
1559 : (C) == 'N' ? (((VALUE) & ~0x0000ffff) == ~0x0000ffff) \
1560 : (C) == 'O' ? (exact_log2 (VALUE) >= 0) \
1561 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1564 /* Similar, but for floating constants, and defining letters G and H.
1565 Here VALUE is the CONST_DOUBLE rtx itself. */
1569 'G' : Floating point 0 */
1571 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1573 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1575 /* Letters in the range `Q' through `U' may be defined in a
1576 machine-dependent fashion to stand for arbitrary operand types.
1577 The machine description macro `EXTRA_CONSTRAINT' is passed the
1578 operand as its first argument and the constraint letter as its
1581 `Q' is for memory references which take more than 1 instruction.
1582 `R' is for memory references which take 1 word for the instruction.
1583 `S' is for references to extern items which are PIC for OSF/rose. */
1585 #define EXTRA_CONSTRAINT(OP,CODE) \
1586 ((GET_CODE (OP) != MEM) ? FALSE \
1587 : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \
1588 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1589 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1590 && HALF_PIC_ADDRESS_P (OP)) \
1593 /* Given an rtx X being reloaded into a reg required to be
1594 in class CLASS, return the class of reg to actually use.
1595 In general this is just CLASS; but on some machines
1596 in some cases it is preferable to use a more restrictive class. */
1598 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1599 ((CLASS) != ALL_REGS \
1601 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1602 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1603 ? (TARGET_SOFT_FLOAT ? GR_REGS : FP_REGS) \
1604 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1605 || GET_MODE (X) == VOIDmode) \
1609 /* Certain machines have the property that some registers cannot be
1610 copied to some other registers without using memory. Define this
1611 macro on those machines to be a C expression that is non-zero if
1612 objects of mode MODE in registers of CLASS1 can only be copied to
1613 registers of class CLASS2 by storing a register of CLASS1 into
1614 memory and loading that memory location into a register of CLASS2.
1616 Do not define this macro if its value would always be zero. */
1618 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1619 ((!TARGET_DEBUG_H_MODE \
1620 && GET_MODE_CLASS (MODE) == MODE_INT \
1621 && ((CLASS1 == FP_REGS && CLASS2 == GR_REGS) \
1622 || (CLASS1 == GR_REGS && CLASS2 == FP_REGS))) \
1623 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1624 && ((CLASS1 == GR_REGS && CLASS2 == FP_REGS) \
1625 || (CLASS2 == GR_REGS && CLASS1 == FP_REGS))))
1627 /* The HI and LO registers can only be reloaded via the general
1630 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1631 mips_secondary_reload_class (CLASS, MODE, X, 1)
1632 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1633 mips_secondary_reload_class (CLASS, MODE, X, 0)
1635 /* Not declared above, with the other functions, because enum
1636 reg_class is not declared yet. */
1637 extern enum reg_class mips_secondary_reload_class ();
1639 /* Return the maximum number of consecutive registers
1640 needed to represent mode MODE in a register of class CLASS. */
1642 #define CLASS_UNITS(mode, size) \
1643 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1645 #define CLASS_MAX_NREGS(CLASS, MODE) \
1646 ((CLASS) == FP_REGS \
1648 ? CLASS_UNITS (MODE, 8) \
1649 : 2 * CLASS_UNITS (MODE, 8)) \
1650 : CLASS_UNITS (MODE, UNITS_PER_WORD))
1652 /* If defined, this is a C expression whose value should be
1653 nonzero if the insn INSN has the effect of mysteriously
1654 clobbering the contents of hard register number REGNO. By
1655 "mysterious" we mean that the insn's RTL expression doesn't
1656 describe such an effect.
1658 If this macro is not defined, it means that no insn clobbers
1659 registers mysteriously. This is the usual situation; all else
1660 being equal, it is best for the RTL expression to show all the
1663 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
1666 /* Stack layout; function entry, exit and calling. */
1668 /* Define this if pushing a word on the stack
1669 makes the stack pointer a smaller address. */
1670 #define STACK_GROWS_DOWNWARD
1672 /* Define this if the nominal address of the stack frame
1673 is at the high-address end of the local variables;
1674 that is, each additional local variable allocated
1675 goes at a more negative offset in the frame. */
1676 /* #define FRAME_GROWS_DOWNWARD */
1678 /* Offset within stack frame to start allocating local variables at.
1679 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1680 first local allocated. Otherwise, it is the offset to the BEGINNING
1681 of the first local allocated. */
1682 #define STARTING_FRAME_OFFSET \
1683 (current_function_outgoing_args_size \
1684 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1686 /* Offset from the stack pointer register to an item dynamically
1687 allocated on the stack, e.g., by `alloca'.
1689 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1690 length of the outgoing arguments. The default is correct for most
1691 machines. See `function.c' for details.
1693 The MIPS ABI states that functions which dynamically allocate the
1694 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
1695 we are trying to create a second frame pointer to the function, so
1696 allocate some stack space to make it happy.
1698 However, the linker currently complains about linking any code that
1699 dynamically allocates stack space, and there seems to be a bug in
1700 STACK_DYNAMIC_OFFSET, so don't define this right now. */
1703 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1704 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
1705 ? 4*UNITS_PER_WORD \
1706 : current_function_outgoing_args_size)
1709 /* The return address for the current frame is in r31 is this is a leaf
1710 function. Otherwise, it is on the stack. It is at a variable offset
1711 from sp/fp/ap, so we define a fake hard register rap which is a
1712 poiner to the return address on the stack. This always gets eliminated
1713 during reload to be either the frame pointer or the stack pointer plus
1716 /* ??? This definition fails for leaf functions. There is currently no
1717 general solution for this problem. */
1719 /* ??? There appears to be no way to get the return address of any previous
1720 frame except by disassembling instructions in the prologue/epilogue.
1721 So currently we support only the current frame. */
1723 #define RETURN_ADDR_RTX(count, frame) \
1725 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
1726 : (fatal ("RETURN_ADDR_RTX not supported for count != 0"), (rtx) 0))
1728 /* Structure to be filled in by compute_frame_size with register
1729 save masks, and offsets for the current function. */
1731 struct mips_frame_info
1733 long total_size; /* # bytes that the entire frame takes up */
1734 long var_size; /* # bytes that variables take up */
1735 long args_size; /* # bytes that outgoing arguments take up */
1736 long extra_size; /* # bytes of extra gunk */
1737 int gp_reg_size; /* # bytes needed to store gp regs */
1738 int fp_reg_size; /* # bytes needed to store fp regs */
1739 long mask; /* mask of saved gp registers */
1740 long fmask; /* mask of saved fp registers */
1741 long gp_save_offset; /* offset from vfp to store gp registers */
1742 long fp_save_offset; /* offset from vfp to store fp registers */
1743 long gp_sp_offset; /* offset from new sp to store gp registers */
1744 long fp_sp_offset; /* offset from new sp to store fp registers */
1745 int initialized; /* != 0 if frame size already calculated */
1746 int num_gp; /* number of gp registers saved */
1747 int num_fp; /* number of fp registers saved */
1750 extern struct mips_frame_info current_frame_info;
1752 /* Store in the variable DEPTH the initial difference between the
1753 frame pointer reg contents and the stack pointer reg contents,
1754 as of the start of the function body. This depends on the layout
1755 of the fixed parts of the stack frame and on how registers are saved. */
1757 /* #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
1758 ((VAR) = compute_frame_size (get_frame_size ())) */
1760 /* If defined, this macro specifies a table of register pairs used to
1761 eliminate unneeded registers that point into the stack frame. If
1762 it is not defined, the only elimination attempted by the compiler
1763 is to replace references to the frame pointer with references to
1766 The definition of this macro is a list of structure
1767 initializations, each of which specifies an original and
1768 replacement register.
1770 On some machines, the position of the argument pointer is not
1771 known until the compilation is completed. In such a case, a
1772 separate hard register must be used for the argument pointer.
1773 This register can be eliminated by replacing it with either the
1774 frame pointer or the argument pointer, depending on whether or not
1775 the frame pointer has been eliminated.
1777 In this case, you might specify:
1778 #define ELIMINABLE_REGS \
1779 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1780 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1781 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1783 Note that the elimination of the argument pointer with the stack
1784 pointer is specified first since that is the preferred elimination. */
1786 #define ELIMINABLE_REGS \
1787 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1788 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1789 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1790 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1791 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
1793 /* A C expression that returns non-zero if the compiler is allowed to
1794 try to replace register number FROM-REG with register number
1795 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
1796 defined, and will usually be the constant 1, since most of the
1797 cases preventing register elimination are things that the compiler
1798 already knows about. */
1800 #define CAN_ELIMINATE(FROM, TO) \
1801 (!frame_pointer_needed \
1802 || ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1803 || ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
1804 && (TO) == FRAME_POINTER_REGNUM))
1806 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
1807 specifies the initial difference between the specified pair of
1808 registers. This macro must be defined if `ELIMINABLE_REGS' is
1811 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1812 { compute_frame_size (get_frame_size ()); \
1813 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1815 else if ((FROM) == ARG_POINTER_REGNUM \
1816 && ((TO) == FRAME_POINTER_REGNUM \
1817 || (TO) == STACK_POINTER_REGNUM)) \
1818 (OFFSET) = (current_frame_info.total_size \
1819 - (mips_abi != ABI_32 \
1820 ? current_function_pretend_args_size \
1822 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
1823 && ((TO) == FRAME_POINTER_REGNUM \
1824 || (TO) == STACK_POINTER_REGNUM)) \
1825 (OFFSET) = current_frame_info.gp_sp_offset; \
1830 /* If we generate an insn to push BYTES bytes,
1831 this says how many the stack pointer really advances by.
1832 On the vax, sp@- in a byte insn really pushes a word. */
1834 /* #define PUSH_ROUNDING(BYTES) 0 */
1836 /* If defined, the maximum amount of space required for outgoing
1837 arguments will be computed and placed into the variable
1838 `current_function_outgoing_args_size'. No space will be pushed
1839 onto the stack for each call; instead, the function prologue
1840 should increase the stack frame size by this amount.
1842 It is not proper to define both `PUSH_ROUNDING' and
1843 `ACCUMULATE_OUTGOING_ARGS'. */
1844 #define ACCUMULATE_OUTGOING_ARGS
1846 /* Offset from the argument pointer register to the first argument's
1847 address. On some machines it may depend on the data type of the
1850 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
1851 the first argument's address.
1853 On the MIPS, we must skip the first argument position if we are
1854 returning a structure or a union, to account for its address being
1855 passed in $4. However, at the current time, this produces a compiler
1856 that can't bootstrap, so comment it out for now. */
1859 #define FIRST_PARM_OFFSET(FNDECL) \
1861 && TREE_TYPE (FNDECL) != 0 \
1862 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
1863 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
1864 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
1868 #define FIRST_PARM_OFFSET(FNDECL) 0
1871 /* When a parameter is passed in a register, stack space is still
1872 allocated for it. For the MIPS, stack space must be allocated, cf
1873 Asm Lang Prog Guide page 7-8.
1875 BEWARE that some space is also allocated for non existing arguments
1876 in register. In case an argument list is of form GF used registers
1877 are a0 (a2,a3), but we should push over a1... */
1879 #define REG_PARM_STACK_SPACE(FNDECL) \
1880 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
1882 /* Define this if it is the responsibility of the caller to
1883 allocate the area reserved for arguments passed in registers.
1884 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1885 of this macro is to determine whether the space is included in
1886 `current_function_outgoing_args_size'. */
1887 #define OUTGOING_REG_PARM_STACK_SPACE
1889 /* Align stack frames on 64 bits (Double Word ). */
1890 #define STACK_BOUNDARY 64
1892 /* Make sure 4 words are always allocated on the stack. */
1894 #ifndef STACK_ARGS_ADJUST
1895 #define STACK_ARGS_ADJUST(SIZE) \
1897 if (SIZE.constant < 4 * UNITS_PER_WORD) \
1898 SIZE.constant = 4 * UNITS_PER_WORD; \
1903 /* A C expression that should indicate the number of bytes of its
1904 own arguments that a function function pops on returning, or 0
1905 if the function pops no arguments and the caller must therefore
1906 pop them all after the function returns.
1908 FUNDECL is the declaration node of the function (as a tree).
1910 FUNTYPE is a C variable whose value is a tree node that
1911 describes the function in question. Normally it is a node of
1912 type `FUNCTION_TYPE' that describes the data type of the function.
1913 From this it is possible to obtain the data types of the value
1914 and arguments (if known).
1916 When a call to a library function is being considered, FUNTYPE
1917 will contain an identifier node for the library function. Thus,
1918 if you need to distinguish among various library functions, you
1919 can do so by their names. Note that "library function" in this
1920 context means a function used to perform arithmetic, whose name
1921 is known specially in the compiler and was not mentioned in the
1922 C code being compiled.
1924 STACK-SIZE is the number of bytes of arguments passed on the
1925 stack. If a variable number of bytes is passed, it is zero, and
1926 argument popping will always be the responsibility of the
1927 calling function. */
1929 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1932 /* Symbolic macros for the registers used to return integer and floating
1935 #define GP_RETURN (GP_REG_FIRST + 2)
1936 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1938 /* Symbolic macros for the first/last argument registers. */
1940 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1941 #define GP_ARG_LAST (GP_REG_FIRST + 7)
1942 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1943 #define FP_ARG_LAST (FP_REG_FIRST + 15)
1945 #define MAX_ARGS_IN_REGISTERS 4
1947 /* Define how to find the value returned by a library function
1948 assuming the value has mode MODE. */
1950 #define LIBCALL_VALUE(MODE) \
1951 gen_rtx (REG, MODE, \
1952 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
1953 && (! TARGET_SINGLE_FLOAT \
1954 || GET_MODE_SIZE (MODE) <= 4)) \
1958 /* Define how to find the value returned by a function.
1959 VALTYPE is the data type of the value (as a tree).
1960 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1961 otherwise, FUNC is 0. */
1963 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1966 /* 1 if N is a possible register number for a function value.
1967 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1968 Currently, R2 and F0 are only implemented here (C has no complex type) */
1970 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
1972 /* 1 if N is a possible register number for function argument passing. */
1974 #define FUNCTION_ARG_REGNO_P(N) (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
1975 || ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST \
1978 /* A C expression which can inhibit the returning of certain function
1979 values in registers, based on the type of value. A nonzero value says
1980 to return the function value in memory, just as large structures are
1981 always returned. Here TYPE will be a C expression of type
1982 `tree', representing the data type of the value.
1984 Note that values of mode `BLKmode' must be explicitly
1985 handled by this macro. Also, the option `-fpcc-struct-return'
1986 takes effect regardless of this macro. On most systems, it is
1987 possible to leave the macro undefined; this causes a default
1988 definition to be used, whose value is the constant 1 for BLKmode
1989 values, and 0 otherwise.
1991 GCC normally converts 1 byte structures into chars, 2 byte
1992 structs into shorts, and 4 byte structs into ints, and returns
1993 them this way. Defining the following macro overrides this,
1994 to give us MIPS cc compatibility. */
1996 #define RETURN_IN_MEMORY(TYPE) \
1997 (TYPE_MODE (TYPE) == BLKmode)
1999 /* A code distinguishing the floating point format of the target
2000 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2001 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2003 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2006 /* Define a data type for recording info about an argument list
2007 during the scan of that argument list. This data type should
2008 hold all necessary information about the function itself
2009 and about the args processed so far, enough to enable macros
2010 such as FUNCTION_ARG to determine where the next arg should go.
2013 typedef struct mips_args {
2014 int gp_reg_found; /* whether a gp register was found yet */
2015 int arg_number; /* argument number */
2016 int arg_words; /* # total words the arguments take */
2017 int num_adjusts; /* number of adjustments made */
2018 /* Adjustments made to args pass in regs. */
2019 /* ??? The size is doubled to work around a
2020 bug in the code that sets the adjustments
2022 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2025 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2026 for a call to a function whose data type is FNTYPE.
2027 For a library call, FNTYPE is 0.
2031 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2032 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2034 /* Update the data in CUM to advance over an argument
2035 of mode MODE and data type TYPE.
2036 (TYPE is null for libcalls where that information may not be available.) */
2038 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2039 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2041 /* Determine where to put an argument to a function.
2042 Value is zero to push the argument on the stack,
2043 or a hard register in which to store the argument.
2045 MODE is the argument's machine mode.
2046 TYPE is the data type of the argument (as a tree).
2047 This is null for libcalls where that information may
2049 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2050 the preceding args and about the function being called.
2051 NAMED is nonzero if this argument is a named parameter
2052 (otherwise it is an extra parameter matching an ellipsis). */
2054 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2055 function_arg( &CUM, MODE, TYPE, NAMED)
2057 /* For an arg passed partly in registers and partly in memory,
2058 this is the number of registers used.
2059 For args passed entirely in registers or entirely in memory, zero. */
2061 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2062 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2064 /* If defined, a C expression that gives the alignment boundary, in
2065 bits, of an argument with the specified mode and type. If it is
2066 not defined, `PARM_BOUNDARY' is used for all arguments. */
2068 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2070 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2072 : TYPE_ALIGN(TYPE)) \
2073 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2075 : GET_MODE_ALIGNMENT(MODE)))
2078 /* This macro generates the assembly code for function entry.
2079 FILE is a stdio stream to output the code to.
2080 SIZE is an int: how many units of temporary storage to allocate.
2081 Refer to the array `regs_ever_live' to determine which registers
2082 to save; `regs_ever_live[I]' is nonzero if register number I
2083 is ever used in the function. This macro is responsible for
2084 knowing which registers should not be saved even if used. */
2086 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2088 /* This macro generates the assembly code for function exit,
2089 on machines that need it. If FUNCTION_EPILOGUE is not defined
2090 then individual return instructions are generated for each
2091 return statement. Args are same as for FUNCTION_PROLOGUE. */
2093 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2095 /* Define the number of delay slots needed for the function epilogue.
2097 On the mips, we need a slot if either no stack has been allocated,
2098 or the only register saved is the return register. */
2100 #define DELAY_SLOTS_FOR_EPILOGUE mips_epilogue_delay_slots ()
2102 /* Define whether INSN can be placed in delay slot N for the epilogue.
2103 No references to the stack must be made, since on the MIPS, the
2104 delay slot is done after the stack has been cleaned up. */
2106 #define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N) \
2107 (get_attr_dslot (INSN) == DSLOT_NO \
2108 && get_attr_length (INSN) == 1 \
2109 && ! epilogue_reg_mentioned_p (PATTERN (INSN)))
2111 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2113 #define MUST_SAVE_REGISTER(regno) \
2114 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2115 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
2116 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2118 /* ALIGN FRAMES on double word boundaries */
2120 #define MIPS_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
2123 /* Output assembler code to FILE to increment profiler label # LABELNO
2124 for profiling a function entry. */
2126 #define FUNCTION_PROFILER(FILE, LABELNO) \
2128 fprintf (FILE, "\t.set\tnoreorder\n"); \
2129 fprintf (FILE, "\t.set\tnoat\n"); \
2130 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2131 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2132 fprintf (FILE, "\tjal\t_mcount\n"); \
2134 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2135 TARGET_64BIT ? "dsubu" : "subu", \
2136 reg_names[STACK_POINTER_REGNUM], \
2137 reg_names[STACK_POINTER_REGNUM], \
2138 TARGET_LONG64 ? 16 : 8); \
2139 fprintf (FILE, "\t.set\treorder\n"); \
2140 fprintf (FILE, "\t.set\tat\n"); \
2143 /* Define this macro if the code for function profiling should come
2144 before the function prologue. Normally, the profiling code comes
2147 /* #define PROFILE_BEFORE_PROLOGUE */
2149 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2150 the stack pointer does not matter. The value is tested only in
2151 functions that have frame pointers.
2152 No definition is equivalent to always zero. */
2154 #define EXIT_IGNORE_STACK 1
2157 /* A C statement to output, on the stream FILE, assembler code for a
2158 block of data that contains the constant parts of a trampoline.
2159 This code should not include a label--the label is taken care of
2162 #define TRAMPOLINE_TEMPLATE(STREAM) \
2164 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2165 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2166 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2167 if (TARGET_LONG64) \
2169 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2170 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2174 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2175 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2177 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2178 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2179 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2180 if (TARGET_LONG64) \
2182 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2183 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2187 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2188 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2192 /* A C expression for the size in bytes of the trampoline, as an
2195 #define TRAMPOLINE_SIZE (32 + (TARGET_LONG64 ? 16 : 8))
2197 /* Alignment required for trampolines, in bits. */
2199 #define TRAMPOLINE_ALIGNMENT (TARGET_LONG64 ? 64 : 32)
2201 /* A C statement to initialize the variable parts of a trampoline.
2202 ADDR is an RTX for the address of the trampoline; FNADDR is an
2203 RTX for the address of the nested function; STATIC_CHAIN is an
2204 RTX for the static chain value that should be passed to the
2205 function when it is called. */
2207 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2210 if (TARGET_LONG64) \
2212 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2213 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2217 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2218 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2221 /* Flush both caches. We need to flush the data cache in case \
2222 the system has a write-back cache. */ \
2223 /* ??? Should check the return value for errors. */ \
2224 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "_flush_cache"), \
2225 0, VOIDmode, 3, addr, Pmode, \
2226 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2227 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2230 /* Addressing modes, and classification of registers for them. */
2232 /* #define HAVE_POST_INCREMENT */
2233 /* #define HAVE_POST_DECREMENT */
2235 /* #define HAVE_PRE_DECREMENT */
2236 /* #define HAVE_PRE_INCREMENT */
2238 /* These assume that REGNO is a hard or pseudo reg number.
2239 They give nonzero only if REGNO is a hard reg of the suitable class
2240 or a pseudo reg currently allocated to a suitable hard reg.
2241 These definitions are NOT overridden anywhere. */
2243 #define GP_REG_OR_PSEUDO_STRICT_P(regno) \
2244 GP_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno])
2246 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno) \
2247 (((regno) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (regno)))
2249 #define REGNO_OK_FOR_INDEX_P(regno) 0
2250 #define REGNO_OK_FOR_BASE_P(regno) GP_REG_OR_PSEUDO_STRICT_P (regno)
2252 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2253 and check its validity for a certain class.
2254 We have two alternate definitions for each of them.
2255 The usual definition accepts all pseudo regs; the other rejects them all.
2256 The symbol REG_OK_STRICT causes the latter definition to be used.
2258 Most source files want to accept pseudo regs in the hope that
2259 they will get allocated to the class that the insn wants them to be in.
2260 Some source files that are used after register allocation
2261 need to be strict. */
2263 #ifndef REG_OK_STRICT
2265 #define REG_OK_STRICT_P 0
2266 #define REG_OK_FOR_INDEX_P(X) 0
2267 #define REG_OK_FOR_BASE_P(X) GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X))
2271 #define REG_OK_STRICT_P 1
2272 #define REG_OK_FOR_INDEX_P(X) 0
2273 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
2278 /* Maximum number of registers that can appear in a valid memory address. */
2280 #define MAX_REGS_PER_ADDRESS 1
2282 /* A C compound statement with a conditional `goto LABEL;' executed
2283 if X (an RTX) is a legitimate memory address on the target
2284 machine for a memory operand of mode MODE.
2286 It usually pays to define several simpler macros to serve as
2287 subroutines for this one. Otherwise it may be too complicated
2290 This macro must exist in two variants: a strict variant and a
2291 non-strict one. The strict variant is used in the reload pass.
2292 It must be defined so that any pseudo-register that has not been
2293 allocated a hard register is considered a memory reference. In
2294 contexts where some kind of register is required, a
2295 pseudo-register with no hard register must be rejected.
2297 The non-strict variant is used in other passes. It must be
2298 defined to accept all pseudo-registers in every context where
2299 some kind of register is required.
2301 Compiler source files that want to use the strict variant of
2302 this macro define the macro `REG_OK_STRICT'. You should use an
2303 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2304 in that case and the non-strict variant otherwise.
2306 Typically among the subroutines used to define
2307 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2308 acceptable registers for various purposes (one for base
2309 registers, one for index registers, and so on). Then only these
2310 subroutine macros need have two variants; the higher levels of
2311 macros may be the same whether strict or not.
2313 Normally, constant addresses which are the sum of a `symbol_ref'
2314 and an integer are stored inside a `const' RTX to mark them as
2315 constant. Therefore, there is no need to recognize such sums
2316 specifically as legitimate addresses. Normally you would simply
2317 recognize any `const' as legitimate.
2319 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2320 constant sums that are not marked with `const'. It assumes
2321 that a naked `plus' indicates indexing. If so, then you *must*
2322 reject such naked constant sums as illegitimate addresses, so
2323 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2325 On some machines, whether a symbolic address is legitimate
2326 depends on the section that the address refers to. On these
2327 machines, define the macro `ENCODE_SECTION_INFO' to store the
2328 information into the `symbol_ref', and then check for it here.
2329 When you see a `const', you will have to look inside it to find
2330 the `symbol_ref' in order to determine the section. */
2333 #define GO_PRINTF(x) trace(x)
2334 #define GO_PRINTF2(x,y) trace(x,y)
2335 #define GO_DEBUG_RTX(x) debug_rtx(x)
2338 #define GO_PRINTF(x)
2339 #define GO_PRINTF2(x,y)
2340 #define GO_DEBUG_RTX(x)
2343 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2345 register rtx xinsn = (X); \
2347 if (TARGET_DEBUG_B_MODE) \
2349 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2350 (REG_OK_STRICT_P) ? "" : "not "); \
2351 GO_DEBUG_RTX (xinsn); \
2354 if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
2357 if (CONSTANT_ADDRESS_P (xinsn) \
2358 && ! (mips_split_addresses && mips_check_split (xinsn, MODE))) \
2361 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2363 register rtx xlow0 = XEXP (xinsn, 0); \
2364 register rtx xlow1 = XEXP (xinsn, 1); \
2366 if (GET_CODE (xlow0) == REG && REG_OK_FOR_BASE_P (xlow0) \
2367 && mips_check_split (xlow1, MODE)) \
2371 if (GET_CODE (xinsn) == PLUS) \
2373 register rtx xplus0 = XEXP (xinsn, 0); \
2374 register rtx xplus1 = XEXP (xinsn, 1); \
2375 register enum rtx_code code0 = GET_CODE (xplus0); \
2376 register enum rtx_code code1 = GET_CODE (xplus1); \
2378 if (code0 != REG && code1 == REG) \
2380 xplus0 = XEXP (xinsn, 1); \
2381 xplus1 = XEXP (xinsn, 0); \
2382 code0 = GET_CODE (xplus0); \
2383 code1 = GET_CODE (xplus1); \
2386 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0)) \
2388 if (code1 == CONST_INT \
2389 && INTVAL (xplus1) >= -32768 \
2390 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2393 /* For some code sequences, you actually get better code by \
2394 pretending that the MIPS supports an address mode of a \
2395 constant address + a register, even though the real \
2396 machine doesn't support it. This is because the \
2397 assembler can use $r1 to load just the high 16 bits, add \
2398 in the register, and fold the low 16 bits into the memory \
2399 reference, whereas the compiler generates a 4 instruction \
2400 sequence. On the other hand, CSE is not as effective. \
2401 It would be a win to generate the lui directly, but the \
2402 MIPS assembler does not have syntax to generate the \
2403 appropriate relocation. */ \
2405 /* Also accept CONST_INT addresses here, so no else. */ \
2406 /* Reject combining an embedded PIC text segment reference \
2407 with a register. That requires an additional \
2409 /* ??? Reject combining an address with a register for the MIPS \
2410 64 bit ABI, because the SGI assembler can not handle this. */ \
2411 if (!TARGET_DEBUG_A_MODE \
2412 && mips_abi == ABI_32 \
2413 && CONSTANT_ADDRESS_P (xplus1) \
2414 && ! mips_split_addresses \
2415 && (!TARGET_EMBEDDED_PIC \
2417 || GET_CODE (XEXP (xplus1, 0)) != MINUS)) \
2422 if (TARGET_DEBUG_B_MODE) \
2423 GO_PRINTF ("Not a legitimate address\n"); \
2427 /* A C expression that is 1 if the RTX X is a constant which is a
2428 valid address. This is defined to be the same as `CONSTANT_P (X)',
2429 but rejecting CONST_DOUBLE. */
2430 /* When pic, we must reject addresses of the form symbol+large int.
2431 This is because an instruction `sw $4,s+70000' needs to be converted
2432 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2433 assembler would use $at as a temp to load in the large offset. In this
2434 case $at is already in use. We convert such problem addresses to
2435 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2436 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2437 #define CONSTANT_ADDRESS_P(X) \
2438 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2439 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2440 || (GET_CODE (X) == CONST \
2441 && ! (flag_pic && pic_address_needs_scratch (X)) \
2442 && mips_abi == ABI_32)) \
2443 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2445 /* Define this, so that when PIC, reload won't try to reload invalid
2446 addresses which require two reload registers. */
2448 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2450 /* Nonzero if the constant value X is a legitimate general operand.
2451 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2453 At present, GAS doesn't understand li.[sd], so don't allow it
2454 to be generated at present. Also, the MIPS assembler does not
2455 grok li.d Infinity. */
2457 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2458 #define LEGITIMATE_CONSTANT_P(X) \
2459 ((GET_CODE (X) != CONST_DOUBLE \
2460 || mips_const_double_ok (X, GET_MODE (X))) \
2461 && ! (GET_CODE (X) == CONST && mips_abi != ABI_32))
2463 /* A C compound statement that attempts to replace X with a valid
2464 memory address for an operand of mode MODE. WIN will be a C
2465 statement label elsewhere in the code; the macro definition may
2468 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2470 to avoid further processing if the address has become legitimate.
2472 X will always be the result of a call to `break_out_memory_refs',
2473 and OLDX will be the operand that was given to that function to
2476 The code generated by this macro should not alter the
2477 substructure of X. If it transforms X into a more legitimate
2478 form, it should assign X (which will always be a C variable) a
2481 It is not necessary for this macro to come up with a legitimate
2482 address. The compiler has standard ways of doing so in all
2483 cases. In fact, it is safe for this macro to do nothing. But
2484 often a machine-dependent strategy can generate better code.
2486 For the MIPS, transform:
2488 memory(X + <large int>)
2492 Y = <large int> & ~0x7fff;
2494 memory (Z + (<large int> & 0x7fff));
2496 This is for CSE to find several similar references, and only use one Z.
2498 When PIC, convert addresses of the form memory (symbol+large int) to
2499 memory (reg+large int). */
2502 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2504 register rtx xinsn = (X); \
2506 if (TARGET_DEBUG_B_MODE) \
2508 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2509 GO_DEBUG_RTX (xinsn); \
2512 if (mips_split_addresses && mips_check_split (X, MODE)) \
2514 /* ??? Is this ever executed? */ \
2515 X = gen_rtx (LO_SUM, Pmode, \
2516 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2520 if (GET_CODE (xinsn) == CONST \
2521 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2522 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2523 || mips_abi != ABI_32)) \
2525 rtx ptr_reg = gen_reg_rtx (Pmode); \
2526 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2528 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2530 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2531 if (SMALL_INT (constant)) \
2533 /* Otherwise we fall through so the code below will fix the \
2538 if (GET_CODE (xinsn) == PLUS) \
2540 register rtx xplus0 = XEXP (xinsn, 0); \
2541 register rtx xplus1 = XEXP (xinsn, 1); \
2542 register enum rtx_code code0 = GET_CODE (xplus0); \
2543 register enum rtx_code code1 = GET_CODE (xplus1); \
2545 if (code0 != REG && code1 == REG) \
2547 xplus0 = XEXP (xinsn, 1); \
2548 xplus1 = XEXP (xinsn, 0); \
2549 code0 = GET_CODE (xplus0); \
2550 code1 = GET_CODE (xplus1); \
2553 if (code0 == REG && REG_OK_FOR_BASE_P (xplus0) \
2554 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2556 rtx int_reg = gen_reg_rtx (Pmode); \
2557 rtx ptr_reg = gen_reg_rtx (Pmode); \
2559 emit_move_insn (int_reg, \
2560 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2562 emit_insn (gen_rtx (SET, VOIDmode, \
2564 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
2566 X = gen_rtx (PLUS, Pmode, ptr_reg, \
2567 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
2572 if (TARGET_DEBUG_B_MODE) \
2573 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
2577 /* A C statement or compound statement with a conditional `goto
2578 LABEL;' executed if memory address X (an RTX) can have different
2579 meanings depending on the machine mode of the memory reference it
2582 Autoincrement and autodecrement addresses typically have
2583 mode-dependent effects because the amount of the increment or
2584 decrement is the size of the operand being addressed. Some
2585 machines have other mode-dependent addresses. Many RISC machines
2586 have no mode-dependent addresses.
2588 You may assume that ADDR is a valid address for the machine. */
2590 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2593 /* Define this macro if references to a symbol must be treated
2594 differently depending on something about the variable or
2595 function named by the symbol (such as what section it is in).
2597 The macro definition, if any, is executed immediately after the
2598 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
2599 The value of the rtl will be a `mem' whose address is a
2602 The usual thing for this macro to do is to a flag in the
2603 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
2604 name string in the `symbol_ref' (if one bit is not enough
2607 The best way to modify the name string is by adding text to the
2608 beginning, with suitable punctuation to prevent any ambiguity.
2609 Allocate the new name in `saveable_obstack'. You will have to
2610 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
2611 and output the name accordingly.
2613 You can also check the information stored in the `symbol_ref' in
2614 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
2615 `PRINT_OPERAND_ADDRESS'. */
2617 #define ENCODE_SECTION_INFO(DECL) \
2620 if (TARGET_EMBEDDED_PIC) \
2622 if (TREE_CODE (DECL) == VAR_DECL) \
2623 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2624 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
2625 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
2626 else if (TREE_CODE (DECL) == STRING_CST \
2627 && ! flag_writable_strings) \
2628 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
2630 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
2633 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
2635 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
2637 if (size > 0 && size <= mips_section_threshold) \
2638 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2641 else if (HALF_PIC_P ()) \
2642 HALF_PIC_ENCODE (DECL); \
2647 /* Specify the machine mode that this machine uses
2648 for the index in the tablejump instruction. */
2649 #define CASE_VECTOR_MODE (TARGET_LONG64 ? DImode : SImode)
2651 /* Define this if the tablejump instruction expects the table
2652 to contain offsets from the address of the table.
2653 Do not define this if the table should contain absolute addresses. */
2654 /* #define CASE_VECTOR_PC_RELATIVE */
2656 /* Specify the tree operation to be used to convert reals to integers. */
2657 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2659 /* This is the kind of divide that is easiest to do in the general case. */
2660 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2662 /* Define this as 1 if `char' should by default be signed; else as 0. */
2663 #ifndef DEFAULT_SIGNED_CHAR
2664 #define DEFAULT_SIGNED_CHAR 1
2667 /* Max number of bytes we can move from memory to memory
2668 in one reasonably fast instruction. */
2669 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2670 #define MAX_MOVE_MAX 8
2672 /* Define this macro as a C expression which is nonzero if
2673 accessing less than a word of memory (i.e. a `char' or a
2674 `short') is no faster than accessing a word of memory, i.e., if
2675 such access require more than one instruction or if there is no
2676 difference in cost between byte and (aligned) word loads.
2678 On RISC machines, it tends to generate better code to define
2679 this as 1, since it avoids making a QI or HI mode register. */
2680 #define SLOW_BYTE_ACCESS 1
2682 /* We assume that the store-condition-codes instructions store 0 for false
2683 and some other value for true. This is the value stored for true. */
2685 #define STORE_FLAG_VALUE 1
2687 /* Define this if zero-extension is slow (more than one real instruction). */
2688 #define SLOW_ZERO_EXTEND
2690 /* Define this to be nonzero if shift instructions ignore all but the low-order
2692 #define SHIFT_COUNT_TRUNCATED 1
2694 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2695 is done just by pretending it is already truncated. */
2696 /* In 64 bit mode, 32 bit instructions require that register values be properly
2697 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
2698 converts a value >32 bits to a value <32 bits. */
2699 /* ??? This results in inefficient code for 64 bit to 32 conversions.
2700 Something needs to be done about this. Perhaps not use any 32 bit
2701 instructions? Perhaps use PROMOTE_MODE? */
2702 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2703 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2705 /* Define this macro to control use of the character `$' in
2706 identifier names. The value should be 0, 1, or 2. 0 means `$'
2707 is not allowed by default; 1 means it is allowed by default if
2708 `-traditional' is used; 2 means it is allowed by default provided
2709 `-ansi' is not used. 1 is the default; there is no need to
2710 define this macro in that case. */
2712 #ifndef DOLLARS_IN_IDENTIFIERS
2713 #define DOLLARS_IN_IDENTIFIERS 1
2716 /* Specify the machine mode that pointers have.
2717 After generation of rtl, the compiler makes no further distinction
2718 between pointers and any other objects of this machine mode. */
2720 #define Pmode (TARGET_LONG64 ? DImode : SImode)
2722 /* A function address in a call instruction
2723 is a word address (for indexing purposes)
2724 so give the MEM rtx a words's mode. */
2726 #define FUNCTION_MODE (TARGET_LONG64 ? DImode : SImode)
2728 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
2729 memset, instead of the BSD functions bcopy and bzero. */
2731 #if defined(MIPS_SYSV) || defined(OSF_OS)
2732 #define TARGET_MEM_FUNCTIONS
2736 /* A part of a C `switch' statement that describes the relative
2737 costs of constant RTL expressions. It must contain `case'
2738 labels for expression codes `const_int', `const', `symbol_ref',
2739 `label_ref' and `const_double'. Each case must ultimately reach
2740 a `return' statement to return the relative cost of the use of
2741 that kind of constant value in an expression. The cost may
2742 depend on the precise value of the constant, which is available
2743 for examination in X.
2745 CODE is the expression code--redundant, since it can be obtained
2746 with `GET_CODE (X)'. */
2748 #define CONST_COSTS(X,CODE,OUTER_CODE) \
2750 /* Always return 0, since we don't have different sized \
2751 instructions, hence different costs according to Richard \
2756 return COSTS_N_INSNS (2); \
2760 rtx offset = const0_rtx; \
2761 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
2763 if (GET_CODE (symref) == LABEL_REF) \
2764 return COSTS_N_INSNS (2); \
2766 if (GET_CODE (symref) != SYMBOL_REF) \
2767 return COSTS_N_INSNS (4); \
2769 /* let's be paranoid.... */ \
2770 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
2771 return COSTS_N_INSNS (2); \
2773 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
2777 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
2779 case CONST_DOUBLE: \
2782 split_double (X, &high, &low); \
2783 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
2784 || low == CONST0_RTX (GET_MODE (low))) \
2788 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2789 This can be used, for example, to indicate how costly a multiply
2790 instruction is. In writing this macro, you can use the construct
2791 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
2793 This macro is optional; do not define it if the default cost
2794 assumptions are adequate for the target machine.
2796 If -mdebugd is used, change the multiply cost to 2, so multiply by
2797 a constant isn't converted to a series of shifts. This helps
2798 strength reduction, and also makes it easier to identify what the
2799 compiler is doing. */
2801 /* ??? Fix this to be right for the R8000. */
2802 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2805 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
2806 if (simple_memory_operand (X, GET_MODE (X))) \
2807 return COSTS_N_INSNS (num_words); \
2809 return COSTS_N_INSNS (2*num_words); \
2813 return COSTS_N_INSNS (6); \
2816 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
2821 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
2822 return COSTS_N_INSNS (2); \
2824 return COSTS_N_INSNS (1); \
2829 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
2830 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
2832 return COSTS_N_INSNS (1); \
2836 enum machine_mode xmode = GET_MODE (X); \
2837 if (xmode == SFmode || xmode == DFmode) \
2838 return COSTS_N_INSNS (1); \
2840 return COSTS_N_INSNS (4); \
2846 enum machine_mode xmode = GET_MODE (X); \
2847 if (xmode == SFmode || xmode == DFmode) \
2849 if (mips_cpu == PROCESSOR_R3000) \
2850 return COSTS_N_INSNS (2); \
2851 else if (mips_cpu == PROCESSOR_R6000) \
2852 return COSTS_N_INSNS (3); \
2854 return COSTS_N_INSNS (6); \
2857 if (xmode == DImode && !TARGET_64BIT) \
2858 return COSTS_N_INSNS (4); \
2860 return COSTS_N_INSNS (1); \
2864 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 4 : 1); \
2868 enum machine_mode xmode = GET_MODE (X); \
2869 if (xmode == SFmode) \
2871 if (mips_cpu == PROCESSOR_R3000) \
2872 return COSTS_N_INSNS (4); \
2873 else if (mips_cpu == PROCESSOR_R6000) \
2874 return COSTS_N_INSNS (5); \
2876 return COSTS_N_INSNS (7); \
2879 if (xmode == DFmode) \
2881 if (mips_cpu == PROCESSOR_R3000) \
2882 return COSTS_N_INSNS (5); \
2883 else if (mips_cpu == PROCESSOR_R6000) \
2884 return COSTS_N_INSNS (6); \
2886 return COSTS_N_INSNS (8); \
2889 if (mips_cpu == PROCESSOR_R3000) \
2890 return COSTS_N_INSNS (12); \
2891 else if (mips_cpu == PROCESSOR_R6000) \
2892 return COSTS_N_INSNS (17); \
2894 return COSTS_N_INSNS (10); \
2900 enum machine_mode xmode = GET_MODE (X); \
2901 if (xmode == SFmode) \
2903 if (mips_cpu == PROCESSOR_R3000) \
2904 return COSTS_N_INSNS (12); \
2905 else if (mips_cpu == PROCESSOR_R6000) \
2906 return COSTS_N_INSNS (15); \
2908 return COSTS_N_INSNS (23); \
2911 if (xmode == DFmode) \
2913 if (mips_cpu == PROCESSOR_R3000) \
2914 return COSTS_N_INSNS (19); \
2915 else if (mips_cpu == PROCESSOR_R6000) \
2916 return COSTS_N_INSNS (16); \
2918 return COSTS_N_INSNS (36); \
2921 /* fall through */ \
2925 if (mips_cpu == PROCESSOR_R3000) \
2926 return COSTS_N_INSNS (35); \
2927 else if (mips_cpu == PROCESSOR_R6000) \
2928 return COSTS_N_INSNS (38); \
2930 return COSTS_N_INSNS (69);
2932 /* An expression giving the cost of an addressing mode that
2933 contains ADDRESS. If not defined, the cost is computed from the
2934 form of the ADDRESS expression and the `CONST_COSTS' values.
2936 For most CISC machines, the default cost is a good approximation
2937 of the true cost of the addressing mode. However, on RISC
2938 machines, all instructions normally have the same length and
2939 execution time. Hence all addresses will have equal costs.
2941 In cases where more than one form of an address is known, the
2942 form with the lowest cost will be used. If multiple forms have
2943 the same, lowest, cost, the one that is the most complex will be
2946 For example, suppose an address that is equal to the sum of a
2947 register and a constant is used twice in the same basic block.
2948 When this macro is not defined, the address will be computed in
2949 a register and memory references will be indirect through that
2950 register. On machines where the cost of the addressing mode
2951 containing the sum is no higher than that of a simple indirect
2952 reference, this will produce an additional instruction and
2953 possibly require an additional register. Proper specification
2954 of this macro eliminates this overhead for such machines.
2956 Similar use of this macro is made in strength reduction of loops.
2958 ADDRESS need not be valid as an address. In such a case, the
2959 cost is not relevant and can be any value; invalid addresses
2960 need not be assigned a different cost.
2962 On machines where an address involving more than one register is
2963 as cheap as an address computation involving only one register,
2964 defining `ADDRESS_COST' to reflect this can cause two registers
2965 to be live over a region of code where only one would have been
2966 if `ADDRESS_COST' were not defined in that manner. This effect
2967 should be considered in the definition of this macro.
2968 Equivalent costs should probably only be given to addresses with
2969 different numbers of registers on machines with lots of registers.
2971 This macro will normally either not be defined or be defined as
2974 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
2976 /* A C expression for the cost of moving data from a register in
2977 class FROM to one in class TO. The classes are expressed using
2978 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2979 the default; other values are interpreted relative to that.
2981 It is not required that the cost always equal 2 when FROM is the
2982 same as TO; on some machines it is expensive to move between
2983 registers if they are not general registers.
2985 If reload sees an insn consisting of a single `set' between two
2986 hard registers, and if `REGISTER_MOVE_COST' applied to their
2987 classes returns a value of 2, reload does not check to ensure
2988 that the constraints of the insn are met. Setting a cost of
2989 other than 2 will allow reload to verify that the constraints are
2990 met. You should do this if the `movM' pattern's constraints do
2991 not allow such copying. */
2993 #define REGISTER_MOVE_COST(FROM, TO) \
2994 ((FROM) == GR_REGS && (TO) == GR_REGS ? 2 \
2995 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
2996 : (FROM) == GR_REGS && (TO) == FP_REGS ? 4 \
2997 : (FROM) == FP_REGS && (TO) == GR_REGS ? 4 \
2998 : (((FROM) == HI_REG || (FROM) == LO_REG \
2999 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3000 && (TO) == GR_REGS) ? 6 \
3001 : (((TO) == HI_REG || (TO) == LO_REG \
3002 || (TO) == MD_REGS || (FROM) == HILO_REG) \
3003 && (FROM) == GR_REGS) ? 6 \
3006 /* ??? Fix this to be right for the R8000. */
3007 #define MEMORY_MOVE_COST(MODE) \
3008 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4)
3010 /* A C expression for the cost of a branch instruction. A value of
3011 1 is the default; other values are interpreted relative to that. */
3013 /* ??? Fix this to be right for the R8000. */
3014 #define BRANCH_COST \
3015 ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 2 : 1)
3017 /* A C statement (sans semicolon) to update the integer variable COST
3018 based on the relationship between INSN that is dependent on
3019 DEP_INSN through the dependence LINK. The default is to make no
3020 adjustment to COST. On the MIPS, ignore the cost of anti- and
3021 output-dependencies. */
3023 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3024 if (REG_NOTE_KIND (LINK) != 0) \
3025 (COST) = 0; /* Anti or output dependence. */
3027 /* Optionally define this if you have added predicates to
3028 `MACHINE.c'. This macro is called within an initializer of an
3029 array of structures. The first field in the structure is the
3030 name of a predicate and the second field is an array of rtl
3031 codes. For each predicate, list all rtl codes that can be in
3032 expressions matched by the predicate. The list should have a
3033 trailing comma. Here is an example of two entries in the list
3034 for a typical RISC machine:
3036 #define PREDICATE_CODES \
3037 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3038 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3040 Defining this macro does not affect the generated code (however,
3041 incorrect definitions that omit an rtl code that may be matched
3042 by the predicate can cause the compiler to malfunction).
3043 Instead, it allows the table built by `genrecog' to be more
3044 compact and efficient, thus speeding up the compiler. The most
3045 important predicates to include in the list specified by this
3046 macro are thoses used in the most insn patterns. */
3048 #define PREDICATE_CODES \
3049 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3050 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3051 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3052 {"reg_or_0_operand", { REG, CONST_INT, SUBREG }}, \
3053 {"small_int", { CONST_INT }}, \
3054 {"large_int", { CONST_INT }}, \
3055 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3056 {"simple_memory_operand", { MEM, SUBREG }}, \
3057 {"equality_op", { EQ, NE }}, \
3058 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3060 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3061 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3062 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3063 SYMBOL_REF, LABEL_REF, SUBREG, \
3067 /* If defined, a C statement to be executed just prior to the
3068 output of assembler code for INSN, to modify the extracted
3069 operands so they will be output differently.
3071 Here the argument OPVEC is the vector containing the operands
3072 extracted from INSN, and NOPERANDS is the number of elements of
3073 the vector which contain meaningful data for this insn. The
3074 contents of this vector are what will be used to convert the
3075 insn template into assembler code, so you can change the
3076 assembler output by changing the contents of the vector.
3078 We use it to check if the current insn needs a nop in front of it
3079 because of load delays, and also to update the delay slot
3082 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3083 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3086 /* Tell final.c how to eliminate redundant test instructions.
3087 Here we define machine-dependent flags and fields in cc_status
3088 (see `conditions.h'). */
3090 /* A list of names to be used for additional modes for condition code
3091 values in registers. These names are added to `enum machine_mode'
3092 and all have class `MODE_CC'. By convention, they should start
3093 with `CC' and end with `mode'.
3095 You should only define this macro if your machine does not use
3096 `cc0' and only if additional modes are required.
3098 On the MIPS, we use CC_FPmode for all floating point except for not
3099 equal, CC_REV_FPmode for not equal (to reverse the sense of the
3100 jump), CC_EQmode for integer equality/inequality comparisons,
3101 CC_0mode for comparisons against 0, and CCmode for other integer
3104 #define EXTRA_CC_MODES CC_EQmode, CC_FPmode, CC_0mode, CC_REV_FPmode
3106 /* A list of C strings giving the names for the modes listed in
3107 `EXTRA_CC_MODES'. */
3109 #define EXTRA_CC_NAMES "CC_EQ", "CC_FP", "CC_0", "CC_REV_FP"
3111 /* Returns a mode from class `MODE_CC' to be used when comparison
3112 operation code OP is applied to rtx X. */
3114 #define SELECT_CC_MODE(OP, X, Y) \
3115 (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
3117 : ((OP == NE) ? CC_REV_FPmode : CC_FPmode))
3120 /* Control the assembler format that we output. */
3122 /* Output at beginning of assembler file.
3123 If we are optimizing to use the global pointer, create a temporary
3124 file to hold all of the text stuff, and write it out to the end.
3125 This is needed because the MIPS assembler is evidently one pass,
3126 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3127 declaration when the code is processed, it generates a two
3128 instruction sequence. */
3130 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3132 /* Output to assembler file text saying following lines
3133 may contain character constants, extra white space, comments, etc. */
3135 #define ASM_APP_ON " #APP\n"
3137 /* Output to assembler file text saying following lines
3138 no longer contain unusual constructs. */
3140 #define ASM_APP_OFF " #NO_APP\n"
3142 /* How to refer to registers in assembler output.
3143 This sequence is indexed by compiler's hard-register-number (see above).
3145 In order to support the two different conventions for register names,
3146 we use the name of a table set up in mips.c, which is overwritten
3147 if -mrnames is used. */
3149 #define REGISTER_NAMES \
3151 &mips_reg_names[ 0][0], \
3152 &mips_reg_names[ 1][0], \
3153 &mips_reg_names[ 2][0], \
3154 &mips_reg_names[ 3][0], \
3155 &mips_reg_names[ 4][0], \
3156 &mips_reg_names[ 5][0], \
3157 &mips_reg_names[ 6][0], \
3158 &mips_reg_names[ 7][0], \
3159 &mips_reg_names[ 8][0], \
3160 &mips_reg_names[ 9][0], \
3161 &mips_reg_names[10][0], \
3162 &mips_reg_names[11][0], \
3163 &mips_reg_names[12][0], \
3164 &mips_reg_names[13][0], \
3165 &mips_reg_names[14][0], \
3166 &mips_reg_names[15][0], \
3167 &mips_reg_names[16][0], \
3168 &mips_reg_names[17][0], \
3169 &mips_reg_names[18][0], \
3170 &mips_reg_names[19][0], \
3171 &mips_reg_names[20][0], \
3172 &mips_reg_names[21][0], \
3173 &mips_reg_names[22][0], \
3174 &mips_reg_names[23][0], \
3175 &mips_reg_names[24][0], \
3176 &mips_reg_names[25][0], \
3177 &mips_reg_names[26][0], \
3178 &mips_reg_names[27][0], \
3179 &mips_reg_names[28][0], \
3180 &mips_reg_names[29][0], \
3181 &mips_reg_names[30][0], \
3182 &mips_reg_names[31][0], \
3183 &mips_reg_names[32][0], \
3184 &mips_reg_names[33][0], \
3185 &mips_reg_names[34][0], \
3186 &mips_reg_names[35][0], \
3187 &mips_reg_names[36][0], \
3188 &mips_reg_names[37][0], \
3189 &mips_reg_names[38][0], \
3190 &mips_reg_names[39][0], \
3191 &mips_reg_names[40][0], \
3192 &mips_reg_names[41][0], \
3193 &mips_reg_names[42][0], \
3194 &mips_reg_names[43][0], \
3195 &mips_reg_names[44][0], \
3196 &mips_reg_names[45][0], \
3197 &mips_reg_names[46][0], \
3198 &mips_reg_names[47][0], \
3199 &mips_reg_names[48][0], \
3200 &mips_reg_names[49][0], \
3201 &mips_reg_names[50][0], \
3202 &mips_reg_names[51][0], \
3203 &mips_reg_names[52][0], \
3204 &mips_reg_names[53][0], \
3205 &mips_reg_names[54][0], \
3206 &mips_reg_names[55][0], \
3207 &mips_reg_names[56][0], \
3208 &mips_reg_names[57][0], \
3209 &mips_reg_names[58][0], \
3210 &mips_reg_names[59][0], \
3211 &mips_reg_names[60][0], \
3212 &mips_reg_names[61][0], \
3213 &mips_reg_names[62][0], \
3214 &mips_reg_names[63][0], \
3215 &mips_reg_names[64][0], \
3216 &mips_reg_names[65][0], \
3217 &mips_reg_names[66][0], \
3218 &mips_reg_names[67][0], \
3219 &mips_reg_names[68][0], \
3222 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3223 So define this for it. */
3224 #define DEBUG_REGISTER_NAMES \
3226 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3227 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3228 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3229 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3230 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3231 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3232 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3233 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3234 "hi", "lo", "accum","$fcr31","$rap" \
3237 /* If defined, a C initializer for an array of structures
3238 containing a name and a register number. This macro defines
3239 additional names for hard registers, thus allowing the `asm'
3240 option in declarations to refer to registers using alternate
3243 We define both names for the integer registers here. */
3245 #define ADDITIONAL_REGISTER_NAMES \
3247 { "$0", 0 + GP_REG_FIRST }, \
3248 { "$1", 1 + GP_REG_FIRST }, \
3249 { "$2", 2 + GP_REG_FIRST }, \
3250 { "$3", 3 + GP_REG_FIRST }, \
3251 { "$4", 4 + GP_REG_FIRST }, \
3252 { "$5", 5 + GP_REG_FIRST }, \
3253 { "$6", 6 + GP_REG_FIRST }, \
3254 { "$7", 7 + GP_REG_FIRST }, \
3255 { "$8", 8 + GP_REG_FIRST }, \
3256 { "$9", 9 + GP_REG_FIRST }, \
3257 { "$10", 10 + GP_REG_FIRST }, \
3258 { "$11", 11 + GP_REG_FIRST }, \
3259 { "$12", 12 + GP_REG_FIRST }, \
3260 { "$13", 13 + GP_REG_FIRST }, \
3261 { "$14", 14 + GP_REG_FIRST }, \
3262 { "$15", 15 + GP_REG_FIRST }, \
3263 { "$16", 16 + GP_REG_FIRST }, \
3264 { "$17", 17 + GP_REG_FIRST }, \
3265 { "$18", 18 + GP_REG_FIRST }, \
3266 { "$19", 19 + GP_REG_FIRST }, \
3267 { "$20", 20 + GP_REG_FIRST }, \
3268 { "$21", 21 + GP_REG_FIRST }, \
3269 { "$22", 22 + GP_REG_FIRST }, \
3270 { "$23", 23 + GP_REG_FIRST }, \
3271 { "$24", 24 + GP_REG_FIRST }, \
3272 { "$25", 25 + GP_REG_FIRST }, \
3273 { "$26", 26 + GP_REG_FIRST }, \
3274 { "$27", 27 + GP_REG_FIRST }, \
3275 { "$28", 28 + GP_REG_FIRST }, \
3276 { "$29", 29 + GP_REG_FIRST }, \
3277 { "$30", 30 + GP_REG_FIRST }, \
3278 { "$31", 31 + GP_REG_FIRST }, \
3279 { "$sp", 29 + GP_REG_FIRST }, \
3280 { "$fp", 30 + GP_REG_FIRST }, \
3281 { "at", 1 + GP_REG_FIRST }, \
3282 { "v0", 2 + GP_REG_FIRST }, \
3283 { "v1", 3 + GP_REG_FIRST }, \
3284 { "a0", 4 + GP_REG_FIRST }, \
3285 { "a1", 5 + GP_REG_FIRST }, \
3286 { "a2", 6 + GP_REG_FIRST }, \
3287 { "a3", 7 + GP_REG_FIRST }, \
3288 { "t0", 8 + GP_REG_FIRST }, \
3289 { "t1", 9 + GP_REG_FIRST }, \
3290 { "t2", 10 + GP_REG_FIRST }, \
3291 { "t3", 11 + GP_REG_FIRST }, \
3292 { "t4", 12 + GP_REG_FIRST }, \
3293 { "t5", 13 + GP_REG_FIRST }, \
3294 { "t6", 14 + GP_REG_FIRST }, \
3295 { "t7", 15 + GP_REG_FIRST }, \
3296 { "s0", 16 + GP_REG_FIRST }, \
3297 { "s1", 17 + GP_REG_FIRST }, \
3298 { "s2", 18 + GP_REG_FIRST }, \
3299 { "s3", 19 + GP_REG_FIRST }, \
3300 { "s4", 20 + GP_REG_FIRST }, \
3301 { "s5", 21 + GP_REG_FIRST }, \
3302 { "s6", 22 + GP_REG_FIRST }, \
3303 { "s7", 23 + GP_REG_FIRST }, \
3304 { "t8", 24 + GP_REG_FIRST }, \
3305 { "t9", 25 + GP_REG_FIRST }, \
3306 { "k0", 26 + GP_REG_FIRST }, \
3307 { "k1", 27 + GP_REG_FIRST }, \
3308 { "gp", 28 + GP_REG_FIRST }, \
3309 { "sp", 29 + GP_REG_FIRST }, \
3310 { "fp", 30 + GP_REG_FIRST }, \
3311 { "ra", 31 + GP_REG_FIRST }, \
3312 { "$sp", 29 + GP_REG_FIRST }, \
3313 { "$fp", 30 + GP_REG_FIRST }, \
3314 { "cc", FPSW_REGNUM }, \
3317 /* Define results of standard character escape sequences. */
3318 #define TARGET_BELL 007
3319 #define TARGET_BS 010
3320 #define TARGET_TAB 011
3321 #define TARGET_NEWLINE 012
3322 #define TARGET_VT 013
3323 #define TARGET_FF 014
3324 #define TARGET_CR 015
3326 /* A C compound statement to output to stdio stream STREAM the
3327 assembler syntax for an instruction operand X. X is an RTL
3330 CODE is a value that can be used to specify one of several ways
3331 of printing the operand. It is used when identical operands
3332 must be printed differently depending on the context. CODE
3333 comes from the `%' specification that was used to request
3334 printing of the operand. If the specification was just `%DIGIT'
3335 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3336 is the ASCII code for LTR.
3338 If X is a register, this macro should print the register's name.
3339 The names can be found in an array `reg_names' whose type is
3340 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3342 When the machine description has a specification `%PUNCT' (a `%'
3343 followed by a punctuation character), this macro is called with
3344 a null pointer for X and the punctuation character for CODE.
3346 See mips.c for the MIPS specific codes. */
3348 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3350 /* A C expression which evaluates to true if CODE is a valid
3351 punctuation character for use in the `PRINT_OPERAND' macro. If
3352 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3353 punctuation characters (except for the standard one, `%') are
3354 used in this way. */
3356 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3358 /* A C compound statement to output to stdio stream STREAM the
3359 assembler syntax for an instruction operand that is a memory
3360 reference whose address is ADDR. ADDR is an RTL expression.
3362 On some machines, the syntax for a symbolic address depends on
3363 the section that the address refers to. On these machines,
3364 define the macro `ENCODE_SECTION_INFO' to store the information
3365 into the `symbol_ref', and then check for it here. */
3367 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3370 /* A C statement, to be executed after all slot-filler instructions
3371 have been output. If necessary, call `dbr_sequence_length' to
3372 determine the number of slots filled in a sequence (zero if not
3373 currently outputting a sequence), to decide how many no-ops to
3374 output, or whatever.
3376 Don't define this macro if it has nothing to do, but it is
3377 helpful in reading assembly output if the extent of the delay
3378 sequence is made explicit (e.g. with white space).
3380 Note that output routines for instructions with delay slots must
3381 be prepared to deal with not being output as part of a sequence
3382 (i.e. when the scheduling pass is not run, or when no slot
3383 fillers could be found.) The variable `final_sequence' is null
3384 when not processing a sequence, otherwise it contains the
3385 `sequence' rtx being output. */
3387 #define DBR_OUTPUT_SEQEND(STREAM) \
3390 if (set_nomacro > 0 && --set_nomacro == 0) \
3391 fputs ("\t.set\tmacro\n", STREAM); \
3393 if (set_noreorder > 0 && --set_noreorder == 0) \
3394 fputs ("\t.set\treorder\n", STREAM); \
3396 dslots_jump_filled++; \
3397 fputs ("\n", STREAM); \
3402 /* How to tell the debugger about changes of source files. Note, the
3403 mips ECOFF format cannot deal with changes of files inside of
3404 functions, which means the output of parser generators like bison
3405 is generally not debuggable without using the -l switch. Lose,
3406 lose, lose. Silicon graphics seems to want all .file's hardwired
3409 #ifndef SET_FILE_NUMBER
3410 #define SET_FILE_NUMBER() ++num_source_filenames
3413 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3414 mips_output_filename (STREAM, NAME)
3416 /* This is defined so that it can be overridden in iris6.h. */
3417 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3420 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3421 output_quoted_string (STREAM, NAME); \
3422 fputs ("\n", STREAM); \
3426 /* This is how to output a note the debugger telling it the line number
3427 to which the following sequence of instructions corresponds.
3428 Silicon graphics puts a label after each .loc. */
3430 #ifndef LABEL_AFTER_LOC
3431 #define LABEL_AFTER_LOC(STREAM)
3434 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3435 mips_output_lineno (STREAM, LINE)
3437 /* The MIPS implementation uses some labels for it's own purpose. The
3438 following lists what labels are created, and are all formed by the
3439 pattern $L[a-z].*. The machine independent portion of GCC creates
3440 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3442 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3443 $Lb[0-9]+ Begin blocks for MIPS debug support
3444 $Lc[0-9]+ Label for use in s<xx> operation.
3445 $Le[0-9]+ End blocks for MIPS debug support
3446 $Lp\..+ Half-pic labels. */
3448 /* This is how to output the definition of a user-level label named NAME,
3449 such as the label on a static function or variable NAME.
3451 If we are optimizing the gp, remember that this label has been put
3452 out, so we know not to emit an .extern for it in mips_asm_file_end.
3453 We use one of the common bits in the IDENTIFIER tree node for this,
3454 since those bits seem to be unused, and we don't have any method
3455 of getting the decl nodes from the name. */
3457 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
3459 assemble_name (STREAM, NAME); \
3460 fputs (":\n", STREAM); \
3464 /* A C statement (sans semicolon) to output to the stdio stream
3465 STREAM any text necessary for declaring the name NAME of an
3466 initialized variable which is being defined. This macro must
3467 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3468 The argument DECL is the `VAR_DECL' tree node representing the
3471 If this macro is not defined, then the variable name is defined
3472 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
3474 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3477 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
3478 HALF_PIC_DECLARE (NAME); \
3483 /* This is how to output a command to make the user-level label named NAME
3484 defined for reference from other files. */
3486 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
3488 fputs ("\t.globl\t", STREAM); \
3489 assemble_name (STREAM, NAME); \
3490 fputs ("\n", STREAM); \
3493 /* This says how to define a global common symbol. */
3495 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
3496 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
3498 /* This says how to define a local common symbol (ie, not visible to
3501 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3502 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
3505 /* This says how to output an external. It would be possible not to
3506 output anything and let undefined symbol become external. However
3507 the assembler uses length information on externals to allocate in
3508 data/sdata bss/sbss, thereby saving exec time. */
3510 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3511 mips_output_external(STREAM,DECL,NAME)
3513 /* This says what to print at the end of the assembly file */
3514 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
3517 /* This is how to declare a function name. The actual work of
3518 emitting the label is moved to function_prologue, so that we can
3519 get the line number correctly emitted before the .ent directive,
3520 and after any .file directives.
3522 Also, switch files if we are optimizing the global pointer. */
3524 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
3526 extern FILE *asm_out_text_file; \
3527 if (TARGET_GP_OPT) \
3529 STREAM = asm_out_text_file; \
3530 /* ??? text_section gets called too soon. If the previous \
3531 function is in a special section and we're not, we have \
3532 to switch back to the text section. We can't call \
3533 text_section again as gcc thinks we're already there. */ \
3534 /* ??? See varasm.c. There are other things that get output \
3535 too early, like alignment (before we've switched STREAM). */ \
3536 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
3537 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
3540 HALF_PIC_DECLARE (NAME); \
3543 /* This is how to output a reference to a user-level label named NAME.
3544 `assemble_name' uses this. */
3546 #define ASM_OUTPUT_LABELREF(STREAM,NAME) \
3547 fprintf (STREAM, "%s%s", USER_LABEL_PREFIX, NAME)
3549 /* This is how to output an internal numbered label where
3550 PREFIX is the class of label and NUM is the number within the class. */
3552 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
3553 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
3555 /* This is how to store into the string LABEL
3556 the symbol_ref name of an internal numbered label where
3557 PREFIX is the class of label and NUM is the number within the class.
3558 This is suitable for output with `assemble_name'. */
3560 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3561 sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
3563 /* This is how to output an assembler line defining a `double' constant. */
3565 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
3566 mips_output_double (STREAM, VALUE)
3569 /* This is how to output an assembler line defining a `float' constant. */
3571 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
3572 mips_output_float (STREAM, VALUE)
3575 /* This is how to output an assembler line defining an `int' constant. */
3577 #define ASM_OUTPUT_INT(STREAM,VALUE) \
3579 fprintf (STREAM, "\t.word\t"); \
3580 output_addr_const (STREAM, (VALUE)); \
3581 fprintf (STREAM, "\n"); \
3584 /* Likewise for 64 bit, `char' and `short' constants. */
3586 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
3590 fprintf (STREAM, "\t.dword\t"); \
3591 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
3592 /* We can't use 'X' for negative numbers, because then we won't \
3593 get the right value for the upper 32 bits. */ \
3594 output_addr_const (STREAM, VALUE); \
3596 /* We must use 'X', because otherwise LONG_MIN will print as \
3597 a number that the Irix 6 assembler won't accept. */ \
3598 print_operand (STREAM, VALUE, 'X'); \
3599 fprintf (STREAM, "\n"); \
3603 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
3604 UNITS_PER_WORD, 1); \
3605 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
3606 UNITS_PER_WORD, 1); \
3610 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
3612 fprintf (STREAM, "\t.half\t"); \
3613 output_addr_const (STREAM, (VALUE)); \
3614 fprintf (STREAM, "\n"); \
3617 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
3619 fprintf (STREAM, "\t.byte\t"); \
3620 output_addr_const (STREAM, (VALUE)); \
3621 fprintf (STREAM, "\n"); \
3624 /* This is how to output an assembler line for a numeric constant byte. */
3626 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
3627 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
3629 /* This is how to output an element of a case-vector that is absolute. */
3631 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3632 fprintf (STREAM, "\t%s\t%sL%d\n", \
3633 TARGET_LONG64 ? ".dword" : ".word", \
3634 LOCAL_LABEL_PREFIX, \
3637 /* This is how to output an element of a case-vector that is relative.
3638 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3639 TARGET_EMBEDDED_PIC). */
3641 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, VALUE, REL) \
3643 if (TARGET_EMBEDDED_PIC) \
3644 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3645 TARGET_LONG64 ? ".dword" : ".word", \
3646 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3647 else if (mips_abi == ABI_32) \
3648 fprintf (STREAM, "\t%s\t%sL%d\n", \
3649 TARGET_LONG64 ? ".gpdword" : ".gpword", \
3650 LOCAL_LABEL_PREFIX, VALUE); \
3652 fprintf (STREAM, "\t%s\t%sL%d\n", \
3653 TARGET_LONG64 ? ".dword" : ".word", \
3654 LOCAL_LABEL_PREFIX, VALUE); \
3657 /* When generating embedded PIC code we want to put the jump table in
3658 the .text section. In all other cases, we want to put the jump
3659 table in the .rdata section. Unfortunately, we can't use
3660 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3661 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3662 section if appropriate. */
3663 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3665 if (TARGET_EMBEDDED_PIC) \
3667 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
3670 /* This is how to output an assembler line
3671 that says to advance the location counter
3672 to a multiple of 2**LOG bytes. */
3674 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3676 int mask = (1 << (LOG)) - 1; \
3677 fprintf (STREAM, "\t.align\t%d\n", (LOG)); \
3680 /* This is how to output an assembler line to to advance the location
3681 counter by SIZE bytes. */
3683 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3684 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
3686 /* This is how to output a string. */
3687 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3689 register int i, c, len = (LEN), cur_pos = 17; \
3690 register unsigned char *string = (unsigned char *)(STRING); \
3691 fprintf ((STREAM), "\t.ascii\t\""); \
3692 for (i = 0; i < len; i++) \
3694 register int c = string[i]; \
3700 putc ('\\', (STREAM)); \
3701 putc (c, (STREAM)); \
3705 case TARGET_NEWLINE: \
3706 fputs ("\\n", (STREAM)); \
3708 && (((c = string[i+1]) >= '\040' && c <= '~') \
3709 || c == TARGET_TAB)) \
3710 cur_pos = 32767; /* break right here */ \
3716 fputs ("\\t", (STREAM)); \
3721 fputs ("\\f", (STREAM)); \
3726 fputs ("\\b", (STREAM)); \
3731 fputs ("\\r", (STREAM)); \
3736 if (c >= ' ' && c < 0177) \
3738 putc (c, (STREAM)); \
3743 fprintf ((STREAM), "\\%03o", c); \
3748 if (cur_pos > 72 && i+1 < len) \
3751 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
3754 fprintf ((STREAM), "\"\n"); \
3757 /* Handle certain cpp directives used in header files on sysV. */
3758 #define SCCS_DIRECTIVE
3760 /* Output #ident as a in the read-only data section. */
3761 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3764 int size = strlen (p) + 1; \
3766 assemble_string (p, size); \
3769 /* Default to -G 8 */
3770 #ifndef MIPS_DEFAULT_GVALUE
3771 #define MIPS_DEFAULT_GVALUE 8
3774 /* Define the strings to put out for each section in the object file. */
3775 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3776 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3777 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3778 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3779 #define READONLY_DATA_SECTION rdata_section
3780 #define SMALL_DATA_SECTION sdata_section
3782 /* What other sections we support other than the normal .data/.text. */
3784 #define EXTRA_SECTIONS in_sdata, in_rdata
3786 /* Define the additional functions to select our additional sections. */
3788 /* on the MIPS it is not a good idea to put constants in the text
3789 section, since this defeats the sdata/data mechanism. This is
3790 especially true when -O is used. In this case an effort is made to
3791 address with faster (gp) register relative addressing, which can
3792 only get at sdata and sbss items (there is no stext !!) However,
3793 if the constant is too large for sdata, and it's readonly, it
3794 will go into the .rdata section. */
3796 #define EXTRA_SECTION_FUNCTIONS \
3800 if (in_section != in_sdata) \
3802 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
3803 in_section = in_sdata; \
3810 if (in_section != in_rdata) \
3812 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
3813 in_section = in_rdata; \
3817 /* Given a decl node or constant node, choose the section to output it in
3818 and select that section. */
3820 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
3822 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
3825 /* Store in OUTPUT a string (made with alloca) containing
3826 an assembler-name for a local static variable named NAME.
3827 LABELNO is an integer which is different for each call. */
3829 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
3830 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
3831 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
3833 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3836 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3837 TARGET_64BIT ? "dsubu" : "subu", \
3838 reg_names[STACK_POINTER_REGNUM], \
3839 reg_names[STACK_POINTER_REGNUM], \
3840 TARGET_64BIT ? "sd" : "sw", \
3842 reg_names[STACK_POINTER_REGNUM]); \
3846 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3849 if (! set_noreorder) \
3850 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3852 dslots_load_total++; \
3853 dslots_load_filled++; \
3854 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3855 TARGET_64BIT ? "ld" : "lw", \
3857 reg_names[STACK_POINTER_REGNUM], \
3858 TARGET_64BIT ? "daddu" : "addu", \
3859 reg_names[STACK_POINTER_REGNUM], \
3860 reg_names[STACK_POINTER_REGNUM]); \
3862 if (! set_noreorder) \
3863 fprintf (STREAM, "\t.set\treorder\n"); \
3867 /* Define the parentheses used to group arithmetic operations
3868 in assembler code. */
3870 #define ASM_OPEN_PAREN "("
3871 #define ASM_CLOSE_PAREN ")"
3873 /* How to start an assembler comment.
3874 The leading space is important (the mips native assembler requires it). */
3875 #ifndef ASM_COMMENT_START
3876 #define ASM_COMMENT_START " #"
3880 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
3881 and mips-tdump.c to print them out.
3883 These must match the corresponding definitions in gdb/mipsread.c.
3884 Unfortunately, gcc and gdb do not currently share any directories. */
3886 #define CODE_MASK 0x8F300
3887 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
3888 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
3889 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
3892 /* Default definitions for size_t and ptrdiff_t. */
3895 #define NO_BUILTIN_SIZE_TYPE
3896 #define SIZE_TYPE (TARGET_LONG64 ? "long unsigned int" : "unsigned int")
3899 #ifndef PTRDIFF_TYPE
3900 #define NO_BUILTIN_PTRDIFF_TYPE
3901 #define PTRDIFF_TYPE (TARGET_LONG64 ? "long int" : "int")
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