1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-97, 1998 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern char *language_string;
32 extern int may_call_alloca;
33 extern char **save_argv;
34 extern int target_flags;
35 extern char *version_string;
37 /* MIPS external variables defined in mips.c. */
41 CMP_SI, /* compare four byte integers */
42 CMP_DI, /* compare eight byte integers */
43 CMP_SF, /* compare single precision floats */
44 CMP_DF, /* compare double precision floats */
45 CMP_MAX /* max comparison type */
48 /* types of delay slot */
50 DELAY_NONE, /* no delay slot */
51 DELAY_LOAD, /* load from memory delay */
52 DELAY_HILO, /* move from/to hi/lo registers */
53 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
56 /* Which processor to schedule for. Since there is no difference between
57 a R2000 and R3000 in terms of the scheduler, we collapse them into
58 just an R3000. The elements of the enumeration must match exactly
59 the cpu attribute in the mips.md machine description. */
75 /* Recast the cpu class to be the cpu attribute. */
76 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
78 /* Which ABI to use. These are constants because abi64.h must check their
79 value at preprocessing time. */
86 #ifndef MIPS_ABI_DEFAULT
87 /* We define this away so that there is no extra runtime cost if the target
88 doesn't support multiple ABIs. */
89 #define mips_abi ABI_32
94 /* Whether to emit abicalls code sequences or not. */
96 enum mips_abicalls_type {
101 /* Recast the abicalls class to be the abicalls attribute. */
102 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
104 /* Which type of block move to do (whether or not the last store is
105 split out so it can fill a branch delay slot). */
107 enum block_move_type {
108 BLOCK_MOVE_NORMAL, /* generate complete block move */
109 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
110 BLOCK_MOVE_LAST /* generate just the last store */
113 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
114 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
115 extern char *current_function_file; /* filename current function is in */
116 extern int num_source_filenames; /* current .file # */
117 extern int inside_function; /* != 0 if inside of a function */
118 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
119 extern int file_in_function_warning; /* warning given about .file in func */
120 extern int sdb_label_count; /* block start/end next label # */
121 extern int sdb_begin_function_line; /* Starting Line of current function */
122 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
123 extern int g_switch_value; /* value of the -G xx switch */
124 extern int g_switch_set; /* whether -G xx was passed. */
125 extern int sym_lineno; /* sgi next label # for each stmt */
126 extern int set_noreorder; /* # of nested .set noreorder's */
127 extern int set_nomacro; /* # of nested .set nomacro's */
128 extern int set_noat; /* # of nested .set noat's */
129 extern int set_volatile; /* # of nested .set volatile's */
130 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
131 extern int mips_dbx_regno[]; /* Map register # to debug register # */
132 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
133 extern enum cmp_type branch_type; /* what type of branch to use */
134 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
135 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
136 extern int mips_isa; /* architectural level */
137 extern int mips16; /* whether generating mips16 code */
138 extern int mips16_hard_float; /* mips16 without -msoft-float */
139 extern int mips_entry; /* generate entry/exit for mips16 */
140 extern char *mips_cpu_string; /* for -mcpu=<xxx> */
141 extern char *mips_isa_string; /* for -mips{1,2,3,4} */
142 extern char *mips_abi_string; /* for -mabi={32,n32,64} */
143 extern char *mips_entry_string; /* for -mentry */
144 extern char *mips_no_mips16_string; /* for -mno-mips16 */
145 extern int mips_split_addresses; /* perform high/lo_sum support */
146 extern int dslots_load_total; /* total # load related delay slots */
147 extern int dslots_load_filled; /* # filled load delay slots */
148 extern int dslots_jump_total; /* total # jump related delay slots */
149 extern int dslots_jump_filled; /* # filled jump delay slots */
150 extern int dslots_number_nops; /* # of nops needed by previous insn */
151 extern int num_refs[3]; /* # 1/2/3 word references */
152 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
153 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
154 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
155 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
156 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
157 extern int mips_string_length; /* length of strings for mips16 */
158 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
160 /* Functions within mips.c that we reference. */
162 extern void abort_with_insn ();
163 extern int arith32_operand ();
164 extern int arith_operand ();
165 extern int cmp_op ();
166 extern long compute_frame_size ();
167 extern int const_float_1_operand ();
168 extern void expand_block_move ();
169 extern int equality_op ();
170 extern void final_prescan_insn ();
171 extern struct rtx_def * function_arg ();
172 extern void function_arg_advance ();
173 extern int function_arg_partial_nregs ();
174 extern int function_arg_pass_by_reference ();
175 extern void function_epilogue ();
176 extern void function_prologue ();
177 extern void gen_conditional_branch ();
178 extern void gen_conditional_move ();
179 extern struct rtx_def * gen_int_relational ();
180 extern void init_cumulative_args ();
181 extern int large_int ();
182 extern void machine_dependent_reorg ();
183 extern int mips_address_cost ();
184 extern void mips_asm_file_end ();
185 extern void mips_asm_file_start ();
186 extern int mips_can_use_return_insn ();
187 extern int mips_const_double_ok ();
188 extern void mips_count_memory_refs ();
189 extern int mips_debugger_offset ();
190 extern void mips_declare_object ();
191 extern int mips_epilogue_delay_slots ();
192 extern void mips_expand_epilogue ();
193 extern void mips_expand_prologue ();
194 extern int mips_check_split ();
195 extern char *mips_fill_delay_slot ();
196 extern char *mips_move_1word ();
197 extern char *mips_move_2words ();
198 extern void mips_output_double ();
199 extern int mips_output_external ();
200 extern void mips_output_float ();
201 extern void mips_output_filename ();
202 extern void mips_output_lineno ();
203 extern char *output_block_move ();
204 extern void override_options ();
205 extern int pc_or_label_operand ();
206 extern void print_operand_address ();
207 extern void print_operand ();
208 extern void print_options ();
209 extern int reg_or_0_operand ();
210 extern int simple_epilogue_p ();
211 extern int simple_memory_operand ();
212 extern int double_memory_operand ();
213 extern int small_int ();
215 extern int uns_arith_operand ();
216 extern struct rtx_def * embedded_pic_offset ();
217 extern void mips_order_regs_for_local_alloc ();
218 extern struct rtx_def * mips16_gp_pseudo_reg ();
219 extern struct rtx_def * mips16_gp_offset ();
220 extern int mips16_gp_offset_p ();
221 extern int mips16_constant ();
222 extern int mips16_constant_after_function_p ();
223 extern int build_mips16_call_stub ();
225 /* Recognition functions that return if a condition is true. */
226 extern int address_operand ();
227 extern int call_insn_operand ();
228 extern int const_double_operand ();
229 extern int const_int_operand ();
230 extern int consttable_operand ();
231 extern int general_operand ();
232 extern int immediate_operand ();
233 extern int memory_address_p ();
234 extern int memory_operand ();
235 extern int nonimmediate_operand ();
236 extern int nonmemory_operand ();
237 extern int pic_address_needs_scratch ();
238 extern int register_operand ();
239 extern int scratch_operand ();
240 extern int move_operand ();
241 extern int movdi_operand ();
242 extern int se_register_operand ();
243 extern int se_reg_or_0_operand ();
244 extern int se_uns_arith_operand ();
245 extern int se_arith_operand ();
246 extern int se_nonmemory_operand ();
247 extern int se_nonimmediate_operand ();
248 extern int m16_uimm3_b ();
249 extern int m16_simm4_1 ();
250 extern int m16_nsimm4_1 ();
251 extern int m16_simm5_1 ();
252 extern int m16_nsimm5_1 ();
253 extern int m16_uimm5_4 ();
254 extern int m16_nuimm5_4 ();
255 extern int m16_simm8_1 ();
256 extern int m16_nsimm8_1 ();
257 extern int m16_uimm8_1 ();
258 extern int m16_nuimm8_1 ();
259 extern int m16_uimm8_m1_1 ();
260 extern int m16_uimm8_4 ();
261 extern int m16_nuimm8_4 ();
262 extern int m16_simm8_8 ();
263 extern int m16_nsimm8_8 ();
264 extern int m16_usym8_4 ();
265 extern int m16_usym5_4 ();
267 /* Functions to change what output section we are using. */
268 extern void data_section ();
269 extern void rdata_section ();
270 extern void readonly_data_section ();
271 extern void sdata_section ();
272 extern void text_section ();
273 extern void mips_select_rtx_section ();
274 extern void mips_select_section ();
276 /* Stubs for half-pic support if not OSF/1 reference platform. */
279 #define HALF_PIC_P() 0
280 #define HALF_PIC_NUMBER_PTRS 0
281 #define HALF_PIC_NUMBER_REFS 0
282 #define HALF_PIC_ENCODE(DECL)
283 #define HALF_PIC_DECLARE(NAME)
284 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
285 #define HALF_PIC_ADDRESS_P(X) 0
286 #define HALF_PIC_PTR(X) X
287 #define HALF_PIC_FINISH(STREAM)
291 /* Run-time compilation parameters selecting different hardware subsets. */
293 /* Macros used in the machine description to test the flags. */
295 /* Bits for real switches */
296 #define MASK_INT64 0x00000001 /* ints are 64 bits */
297 #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
298 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
299 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
300 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
301 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
302 #define MASK_STATS 0x00000040 /* print statistics to stderr */
303 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
304 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
305 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
306 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
307 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
308 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
309 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
310 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
311 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
312 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
313 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
314 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
315 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
316 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
317 #define MASK_MIPS16 0x01000000 /* Generate mips16 code */
319 /* Dummy switches used only in spec's*/
320 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
322 /* Debug switches, not documented */
323 #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */
324 #define MASK_DEBUG_A 0x20000000 /* don't allow <label>($reg) addrs */
325 #define MASK_DEBUG_B 0x10000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
326 #define MASK_DEBUG_C 0x08000000 /* don't expand seq, etc. */
327 #define MASK_DEBUG_D 0x04000000 /* don't do define_split's */
328 #define MASK_DEBUG_E 0x02000000 /* function_arg debug */
329 #define MASK_DEBUG_F 0
330 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
331 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
332 #define MASK_DEBUG_I 0x00200000 /* unused */
334 /* r4000 64 bit sizes */
335 #define TARGET_INT64 (target_flags & MASK_INT64)
336 #define TARGET_LONG64 (target_flags & MASK_LONG64)
337 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
338 #define TARGET_64BIT (target_flags & MASK_64BIT)
340 /* Mips vs. GNU linker */
341 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
343 /* generate mips 3900 insns */
344 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
346 /* Mips vs. GNU assembler */
347 #define TARGET_GAS (target_flags & MASK_GAS)
348 #define TARGET_UNIX_ASM (!TARGET_GAS)
349 #define TARGET_MIPS_AS TARGET_UNIX_ASM
352 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
353 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
354 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
355 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
356 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
357 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
358 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
359 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
360 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
361 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
363 /* Reg. Naming in .s ($21 vs. $a0) */
364 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
366 /* Optimize for Sdata/Sbss */
367 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
369 /* print program statistics */
370 #define TARGET_STATS (target_flags & MASK_STATS)
372 /* call memcpy instead of inline code */
373 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
375 /* .abicalls, etc from Pyramid V.4 */
376 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
378 /* OSF pic references to externs */
379 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
381 /* software floating point */
382 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
383 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
385 /* always call through a register */
386 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
388 /* generate embedded PIC code;
390 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
392 /* for embedded systems, optimize for
393 reduced RAM space instead of for
395 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
397 /* generate big endian code. */
398 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
400 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
401 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
403 #define TARGET_MAD (target_flags & MASK_MAD)
405 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
407 /* This is true if we must enable the assembly language file switching
410 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
412 /* We must disable the function end stabs when doing the file switching trick,
413 because the Lscope stabs end up in the wrong place, making it impossible
414 to debug the resulting code. */
415 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
417 /* Generate mips16 code */
418 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
420 /* Macro to define tables used to set the flags.
421 This is a list in braces of pairs in braces,
422 each pair being { "NAME", VALUE }
423 where VALUE is the bits to set or minus the bits to clear.
424 An empty string NAME is used to identify the default VALUE. */
426 #define TARGET_SWITCHES \
428 {"int64", MASK_INT64 | MASK_LONG64}, \
429 {"long64", MASK_LONG64}, \
430 {"split-addresses", MASK_SPLIT_ADDR}, \
431 {"no-split-addresses", -MASK_SPLIT_ADDR}, \
432 {"mips-as", -MASK_GAS}, \
434 {"rnames", MASK_NAME_REGS}, \
435 {"no-rnames", -MASK_NAME_REGS}, \
436 {"gpOPT", MASK_GPOPT}, \
437 {"gpopt", MASK_GPOPT}, \
438 {"no-gpOPT", -MASK_GPOPT}, \
439 {"no-gpopt", -MASK_GPOPT}, \
440 {"stats", MASK_STATS}, \
441 {"no-stats", -MASK_STATS}, \
442 {"memcpy", MASK_MEMCPY}, \
443 {"no-memcpy", -MASK_MEMCPY}, \
444 {"mips-tfile", MASK_MIPS_TFILE}, \
445 {"no-mips-tfile", -MASK_MIPS_TFILE}, \
446 {"soft-float", MASK_SOFT_FLOAT}, \
447 {"hard-float", -MASK_SOFT_FLOAT}, \
448 {"fp64", MASK_FLOAT64}, \
449 {"fp32", -MASK_FLOAT64}, \
450 {"gp64", MASK_64BIT}, \
451 {"gp32", -MASK_64BIT}, \
452 {"abicalls", MASK_ABICALLS}, \
453 {"no-abicalls", -MASK_ABICALLS}, \
454 {"half-pic", MASK_HALF_PIC}, \
455 {"no-half-pic", -MASK_HALF_PIC}, \
456 {"long-calls", MASK_LONG_CALLS}, \
457 {"no-long-calls", -MASK_LONG_CALLS}, \
458 {"embedded-pic", MASK_EMBEDDED_PIC}, \
459 {"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
460 {"embedded-data", MASK_EMBEDDED_DATA}, \
461 {"no-embedded-data", -MASK_EMBEDDED_DATA}, \
462 {"eb", MASK_BIG_ENDIAN}, \
463 {"el", -MASK_BIG_ENDIAN}, \
464 {"single-float", MASK_SINGLE_FLOAT}, \
465 {"double-float", -MASK_SINGLE_FLOAT}, \
467 {"no-mad", -MASK_MAD}, \
468 {"fix4300", MASK_4300_MUL_FIX}, \
469 {"no-fix4300", -MASK_4300_MUL_FIX}, \
470 {"4650", MASK_MAD | MASK_SINGLE_FLOAT}, \
471 {"3900", MASK_MIPS3900}, \
472 {"debug", MASK_DEBUG}, \
473 {"debuga", MASK_DEBUG_A}, \
474 {"debugb", MASK_DEBUG_B}, \
475 {"debugc", MASK_DEBUG_C}, \
476 {"debugd", MASK_DEBUG_D}, \
477 {"debuge", MASK_DEBUG_E}, \
478 {"debugf", MASK_DEBUG_F}, \
479 {"debugg", MASK_DEBUG_G}, \
480 {"debugh", MASK_DEBUG_H}, \
481 {"debugi", MASK_DEBUG_I}, \
482 {"", (TARGET_DEFAULT \
483 | TARGET_CPU_DEFAULT \
484 | TARGET_ENDIAN_DEFAULT)} \
487 /* Default target_flags if no switches are specified */
489 #ifndef TARGET_DEFAULT
490 #define TARGET_DEFAULT 0
493 #ifndef TARGET_CPU_DEFAULT
494 #define TARGET_CPU_DEFAULT 0
497 #ifndef TARGET_ENDIAN_DEFAULT
499 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
501 #define TARGET_ENDIAN_DEFAULT 0
505 #ifndef MULTILIB_DEFAULTS
506 #if TARGET_ENDIAN_DEFAULT == 0
507 #define MULTILIB_DEFAULTS { "EL", "mips1" }
509 #define MULTILIB_DEFAULTS { "EB", "mips1" }
513 /* We must pass -EL to the linker by default for little endian embedded
514 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
515 linker will default to using big-endian output files. The OUTPUT_FORMAT
516 line must be in the linker script, otherwise -EB/-EL will not work. */
518 #ifndef LINKER_ENDIAN_SPEC
519 #if TARGET_ENDIAN_DEFAULT == 0
520 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
522 #define LINKER_ENDIAN_SPEC ""
526 /* This macro is similar to `TARGET_SWITCHES' but defines names of
527 command options that have values. Its definition is an
528 initializer with a subgrouping for each command option.
530 Each subgrouping contains a string constant, that defines the
531 fixed part of the option name, and the address of a variable.
532 The variable, type `char *', is set to the variable part of the
533 given option if the fixed part matches. The actual option name
534 is made by appending `-m' to the specified name.
536 Here is an example which defines `-mshort-data-NUMBER'. If the
537 given option is `-mshort-data-512', the variable `m88k_short_data'
538 will be set to the string `"512"'.
540 extern char *m88k_short_data;
541 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
543 #define TARGET_OPTIONS \
545 SUBTARGET_TARGET_OPTIONS \
546 { "cpu=", &mips_cpu_string }, \
547 { "ips", &mips_isa_string }, \
548 { "entry", &mips_entry_string }, \
549 { "no-mips16", &mips_no_mips16_string } \
552 /* This is meant to be redefined in the host dependent files. */
553 #define SUBTARGET_TARGET_OPTIONS
555 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
556 #define GENERATE_MULT3 (TARGET_MIPS3900 \
558 #define GENERATE_MADD (TARGET_MIPS3900 \
563 /* Macros to decide whether certain features are available or not,
564 depending on the instruction set architecture level. */
566 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
567 #define HAVE_SQRT_P() (mips_isa >= 2)
569 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
570 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
571 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
572 target_flags, and -mgp64 sets MASK_64BIT.
574 Setting MASK_64BIT in target_flags will cause gcc to assume that
575 registers are 64 bits wide. int, long and void * will be 32 bit;
576 this may be changed with -mint64 or -mlong64.
578 The gen* programs link code that refers to MASK_64BIT. They don't
579 actually use the information in target_flags; they just refer to
582 /* Switch Recognition by gcc.c. Add -G xx support */
584 #ifdef SWITCH_TAKES_ARG
585 #undef SWITCH_TAKES_ARG
588 #define SWITCH_TAKES_ARG(CHAR) \
589 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
591 /* Sometimes certain combinations of command options do not make sense
592 on a particular target machine. You can define a macro
593 `OVERRIDE_OPTIONS' to take account of this. This macro, if
594 defined, is executed once just after all the command options have
597 On the MIPS, it is used to handle -G. We also use it to set up all
598 of the tables referenced in the other macros. */
600 #define OVERRIDE_OPTIONS override_options ()
602 /* Zero or more C statements that may conditionally modify two
603 variables `fixed_regs' and `call_used_regs' (both of type `char
604 []') after they have been initialized from the two preceding
607 This is necessary in case the fixed or call-clobbered registers
608 depend on target flags.
610 You need not define this macro if it has no work to do.
612 If the usage of an entire class of registers depends on the target
613 flags, you may indicate this to GCC by using this macro to modify
614 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
615 the classes which should not be used by GCC. Also define the macro
616 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
617 letter for a class that shouldn't be used.
619 (However, if this class is not included in `GENERAL_REGS' and all
620 of the insn patterns whose constraints permit this class are
621 controlled by target switches, then GCC will automatically avoid
622 using these registers when the target switches are opposed to
625 #define CONDITIONAL_REGISTER_USAGE \
628 if (!TARGET_HARD_FLOAT) \
632 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
633 fixed_regs[regno] = call_used_regs[regno] = 1; \
634 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
635 fixed_regs[regno] = call_used_regs[regno] = 1; \
637 else if (mips_isa < 4) \
641 /* We only have a single condition code register. We \
642 implement this by hiding all the condition code registers, \
643 and generating RTL that refers directly to ST_REG_FIRST. */ \
644 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
645 fixed_regs[regno] = call_used_regs[regno] = 1; \
647 /* In mips16 mode, we permit the $t temporary registers to be used \
648 for reload. We prohibit the unused $s registers, since they \
649 are caller saved, and saving them via a mips16 register would \
650 probably waste more time than just reloading the value. */ \
653 fixed_regs[18] = call_used_regs[18] = 1; \
654 fixed_regs[19] = call_used_regs[19] = 1; \
655 fixed_regs[20] = call_used_regs[20] = 1; \
656 fixed_regs[21] = call_used_regs[21] = 1; \
657 fixed_regs[22] = call_used_regs[22] = 1; \
658 fixed_regs[23] = call_used_regs[23] = 1; \
659 fixed_regs[26] = call_used_regs[26] = 1; \
660 fixed_regs[27] = call_used_regs[27] = 1; \
661 fixed_regs[30] = call_used_regs[30] = 1; \
663 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
667 /* This is meant to be redefined in the host dependent files. */
668 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
670 /* Show we can debug even without a frame pointer. */
671 #define CAN_DEBUG_WITHOUT_FP
673 /* Complain about missing specs and predefines that should be defined in each
674 of the target tm files to override the defaults. This is mostly a place-
675 holder until I can get each of the files updated [mm]. */
677 #if defined(OSF_OS) \
678 || defined(DECSTATION) \
679 || defined(SGI_TARGET) \
680 || defined(MIPS_NEWS) \
681 || defined(MIPS_SYSV) \
682 || defined(MIPS_SVR4) \
683 || defined(MIPS_BSD43)
685 #ifndef CPP_PREDEFINES
686 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
690 #error "Define LIB_SPEC in the appropriate tm.h file"
693 #ifndef STARTFILE_SPEC
694 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
698 #error "Define MACHINE_TYPE in the appropriate tm.h file"
702 /* Tell collect what flags to pass to nm. */
704 #define NM_FLAGS "-Bp"
708 /* Names to predefine in the preprocessor for this target machine. */
710 #ifndef CPP_PREDEFINES
711 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
712 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
713 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
716 /* Assembler specs. */
718 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
721 #define MIPS_AS_ASM_SPEC "\
722 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
723 %{pipe: %e-pipe is not supported.} \
724 %{K} %(subtarget_mips_as_asm_spec)"
726 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
727 rather than gas. It may be overridden by subtargets. */
729 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
730 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
733 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
736 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
738 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
739 GAS_ASM_SPEC as the default, depending upon the value of
742 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
745 #define TARGET_ASM_SPEC "\
746 %{mmips-as: %(mips_as_asm_spec)} \
747 %{!mmips-as: %(gas_asm_spec)}"
751 #define TARGET_ASM_SPEC "\
752 %{!mgas: %(mips_as_asm_spec)} \
753 %{mgas: %(gas_asm_spec)}"
757 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
758 to the assembler. It may be overridden by subtargets. */
759 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
760 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
762 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
765 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
766 the assembler. It may be overridden by subtargets. */
767 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
768 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
769 %{g} %{g0} %{g1} %{g2} %{g3} \
770 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
771 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
772 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
773 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
776 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
777 overridden by subtargets. */
779 #ifndef SUBTARGET_ASM_SPEC
780 #define SUBTARGET_ASM_SPEC ""
783 /* ASM_SPEC is the set of arguments to pass to the assembler. */
786 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
787 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
788 %(subtarget_asm_optimizing_spec) \
789 %(subtarget_asm_debugging_spec) \
791 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
793 %(subtarget_asm_spec)"
795 /* Specify to run a post-processor, mips-tfile after the assembler
796 has run to stuff the mips debug information into the object file.
797 This is needed because the $#!%^ MIPS assembler provides no way
798 of specifying such information in the assembly file. If we are
799 cross compiling, disable mips-tfile unless the user specifies
802 #ifndef ASM_FINAL_SPEC
803 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
805 #define ASM_FINAL_SPEC "\
806 %{mmips-as: %{!mno-mips-tfile: \
807 \n mips-tfile %{v*: -v} \
809 %{!K: %{save-temps: -I %b.o~}} \
810 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
811 %{.s:%i} %{!.s:%g.s}}}"
815 #define ASM_FINAL_SPEC "\
816 %{!mgas: %{!mno-mips-tfile: \
817 \n mips-tfile %{v*: -v} \
819 %{!K: %{save-temps: -I %b.o~}} \
820 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
821 %{.s:%i} %{!.s:%g.s}}}"
824 #endif /* ASM_FINAL_SPEC */
826 /* Redefinition of libraries used. Mips doesn't support normal
827 UNIX style profiling via calling _mcount. It does offer
828 profiling that samples the PC, so do what we can... */
831 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
834 /* Extra switches sometimes passed to the linker. */
835 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
836 will interpret it as a -b option. */
840 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
841 %{bestGnum} %{shared} %{non_shared} \
842 %(linker_endian_spec)"
843 #endif /* LINK_SPEC defined */
845 /* Specs for the compiler proper */
847 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
848 overridden by subtargets. */
849 #ifndef SUBTARGET_CC1_SPEC
850 #define SUBTARGET_CC1_SPEC ""
853 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
857 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
858 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
859 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
860 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
861 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
862 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
863 %{m4650:-mcpu=r4650} \
864 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
865 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
866 %{pic-none: -mno-half-pic} \
867 %{pic-lib: -mhalf-pic} \
868 %{pic-extern: -mhalf-pic} \
869 %{pic-calls: -mhalf-pic} \
871 %(subtarget_cc1_spec) "
874 /* Preprocessor specs. */
876 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
877 be overridden by subtargets. */
879 #ifndef SUBTARGET_CPP_SIZE_SPEC
880 #define SUBTARGET_CPP_SIZE_SPEC "\
881 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
882 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
885 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
886 overridden by subtargets. */
887 #ifndef SUBTARGET_CPP_SPEC
888 #define SUBTARGET_CPP_SPEC ""
891 /* If we're using 64bit longs, then we have to define __LONG_MAX__
892 correctly. Similarly for 64bit ints and __INT_MAX__. */
893 #ifndef LONG_MAX_SPEC
894 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
895 #define LONG_MAX_SPEC "%{!mno-long64:-D__LONG_MAX__=9223372036854775807L}"
897 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
901 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
905 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
906 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
907 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
908 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
909 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
910 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
911 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
912 %(subtarget_cpp_size_spec) \
913 %{mips3:-U__mips -D__mips=3 -D__mips64} \
914 %{mips4:-U__mips -D__mips=4 -D__mips64} \
915 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
916 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
917 %{m4650:%{!msoft-float:-D__mips_single_float}} \
918 %{msoft-float:-D__mips_soft_float} \
919 %{mabi=eabi:-D__mips_eabi} \
920 %{mips16:%{!mno-mips16:-D__mips16}} \
921 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
922 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
924 %(subtarget_cpp_spec) "
927 /* This macro defines names of additional specifications to put in the specs
928 that can be used in various specifications like CC1_SPEC. Its definition
929 is an initializer with a subgrouping for each command option.
931 Each subgrouping contains a string constant, that defines the
932 specification name, and a string constant that used by the GNU CC driver
935 Do not define this macro if it does not need to do anything. */
937 #define EXTRA_SPECS \
938 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
939 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
940 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
941 { "long_max_spec", LONG_MAX_SPEC }, \
942 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
943 { "gas_asm_spec", GAS_ASM_SPEC }, \
944 { "target_asm_spec", TARGET_ASM_SPEC }, \
945 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
946 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
947 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
948 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
949 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
950 SUBTARGET_EXTRA_SPECS
952 #ifndef SUBTARGET_EXTRA_SPECS
953 #define SUBTARGET_EXTRA_SPECS
956 /* If defined, this macro is an additional prefix to try after
957 `STANDARD_EXEC_PREFIX'. */
959 #ifndef MD_EXEC_PREFIX
960 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
963 #ifndef MD_STARTFILE_PREFIX
964 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
968 /* Print subsidiary information on the compiler version in use. */
970 #define MIPS_VERSION "[AL 1.1, MM 40]"
973 #define MACHINE_TYPE "BSD Mips"
976 #ifndef TARGET_VERSION_INTERNAL
977 #define TARGET_VERSION_INTERNAL(STREAM) \
978 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
981 #ifndef TARGET_VERSION
982 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
986 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
987 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
988 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
990 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
991 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
994 /* By default, turn on GDB extensions. */
995 #define DEFAULT_GDB_EXTENSIONS 1
997 /* If we are passing smuggling stabs through the MIPS ECOFF object
998 format, put a comment in front of the .stab<x> operation so
999 that the MIPS assembler does not choke. The mips-tfile program
1000 will correctly put the stab into the object file. */
1002 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
1003 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
1004 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
1006 /* Local compiler-generated symbols must have a prefix that the assembler
1007 understands. By default, this is $, although some targets (e.g.,
1008 NetBSD-ELF) need to override this. */
1010 #ifndef LOCAL_LABEL_PREFIX
1011 #define LOCAL_LABEL_PREFIX "$"
1014 /* By default on the mips, external symbols do not have an underscore
1015 prepended, but some targets (e.g., NetBSD) require this. */
1017 #ifndef USER_LABEL_PREFIX
1018 #define USER_LABEL_PREFIX ""
1021 /* Forward references to tags are allowed. */
1022 #define SDB_ALLOW_FORWARD_REFERENCES
1024 /* Unknown tags are also allowed. */
1025 #define SDB_ALLOW_UNKNOWN_REFERENCES
1027 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1028 since the length can run past this up to a continuation point. */
1029 #define DBX_CONTIN_LENGTH 1500
1031 /* How to renumber registers for dbx and gdb. */
1032 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1034 /* The mapping from gcc register number to DWARF 2 CFA column number.
1035 This mapping does not allow for tracking register 0, since SGI's broken
1036 dwarf reader thinks column 0 is used for the frame address, but since
1037 register 0 is fixed this is not a problem. */
1038 #define DWARF_FRAME_REGNUM(REG) \
1039 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1041 /* The DWARF 2 CFA column which tracks the return address. */
1042 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1044 /* Before the prologue, RA lives in r31. */
1045 #define INCOMING_RETURN_ADDR_RTX gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
1047 /* Overrides for the COFF debug format. */
1048 #define PUT_SDB_SCL(a) \
1050 extern FILE *asm_out_text_file; \
1051 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1054 #define PUT_SDB_INT_VAL(a) \
1056 extern FILE *asm_out_text_file; \
1057 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1060 #define PUT_SDB_VAL(a) \
1062 extern FILE *asm_out_text_file; \
1063 fputs ("\t.val\t", asm_out_text_file); \
1064 output_addr_const (asm_out_text_file, (a)); \
1065 fputc (';', asm_out_text_file); \
1068 #define PUT_SDB_DEF(a) \
1070 extern FILE *asm_out_text_file; \
1071 fprintf (asm_out_text_file, "\t%s.def\t", \
1072 (TARGET_GAS) ? "" : "#"); \
1073 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1074 fputc (';', asm_out_text_file); \
1077 #define PUT_SDB_PLAIN_DEF(a) \
1079 extern FILE *asm_out_text_file; \
1080 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1081 (TARGET_GAS) ? "" : "#", (a)); \
1084 #define PUT_SDB_ENDEF \
1086 extern FILE *asm_out_text_file; \
1087 fprintf (asm_out_text_file, "\t.endef\n"); \
1090 #define PUT_SDB_TYPE(a) \
1092 extern FILE *asm_out_text_file; \
1093 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1096 #define PUT_SDB_SIZE(a) \
1098 extern FILE *asm_out_text_file; \
1099 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1102 #define PUT_SDB_DIM(a) \
1104 extern FILE *asm_out_text_file; \
1105 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1108 #ifndef PUT_SDB_START_DIM
1109 #define PUT_SDB_START_DIM \
1111 extern FILE *asm_out_text_file; \
1112 fprintf (asm_out_text_file, "\t.dim\t"); \
1116 #ifndef PUT_SDB_NEXT_DIM
1117 #define PUT_SDB_NEXT_DIM(a) \
1119 extern FILE *asm_out_text_file; \
1120 fprintf (asm_out_text_file, "%d,", a); \
1124 #ifndef PUT_SDB_LAST_DIM
1125 #define PUT_SDB_LAST_DIM(a) \
1127 extern FILE *asm_out_text_file; \
1128 fprintf (asm_out_text_file, "%d;", a); \
1132 #define PUT_SDB_TAG(a) \
1134 extern FILE *asm_out_text_file; \
1135 fprintf (asm_out_text_file, "\t.tag\t"); \
1136 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1137 fputc (';', asm_out_text_file); \
1140 /* For block start and end, we create labels, so that
1141 later we can figure out where the correct offset is.
1142 The normal .ent/.end serve well enough for functions,
1143 so those are just commented out. */
1145 #define PUT_SDB_BLOCK_START(LINE) \
1147 extern FILE *asm_out_text_file; \
1148 fprintf (asm_out_text_file, \
1149 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1150 LOCAL_LABEL_PREFIX, \
1152 (TARGET_GAS) ? "" : "#", \
1153 LOCAL_LABEL_PREFIX, \
1156 sdb_label_count++; \
1159 #define PUT_SDB_BLOCK_END(LINE) \
1161 extern FILE *asm_out_text_file; \
1162 fprintf (asm_out_text_file, \
1163 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1164 LOCAL_LABEL_PREFIX, \
1166 (TARGET_GAS) ? "" : "#", \
1167 LOCAL_LABEL_PREFIX, \
1170 sdb_label_count++; \
1173 #define PUT_SDB_FUNCTION_START(LINE)
1175 #define PUT_SDB_FUNCTION_END(LINE) \
1177 extern FILE *asm_out_text_file; \
1178 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1181 #define PUT_SDB_EPILOGUE_END(NAME)
1183 #define PUT_SDB_SRC_FILE(FILENAME) \
1185 extern FILE *asm_out_text_file; \
1186 output_file_directive (asm_out_text_file, (FILENAME)); \
1189 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1190 sprintf ((BUFFER), ".%dfake", (NUMBER));
1192 /* Correct the offset of automatic variables and arguments. Note that
1193 the MIPS debug format wants all automatic variables and arguments
1194 to be in terms of the virtual frame pointer (stack pointer before
1195 any adjustment in the function), while the MIPS 3.0 linker wants
1196 the frame pointer to be the stack pointer after the initial
1199 #define DEBUGGER_AUTO_OFFSET(X) mips_debugger_offset (X, 0)
1200 #define DEBUGGER_ARG_OFFSET(OFFSET, X) mips_debugger_offset (X, OFFSET)
1203 /* Tell collect that the object format is ECOFF */
1204 #ifndef OBJECT_FORMAT_ROSE
1205 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1206 #define EXTENDED_COFF /* ECOFF, not normal coff */
1209 #if 0 /* These definitions normally have no effect because
1210 MIPS systems define USE_COLLECT2, so
1211 assemble_constructor does nothing anyway. */
1213 /* Don't use the default definitions, because we don't have gld.
1214 Also, we don't want stabs when generating ECOFF output.
1215 Instead we depend on collect to handle these. */
1217 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1218 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1222 /* Target machine storage layout */
1224 /* Define in order to support both big and little endian float formats
1225 in the same gcc binary. */
1226 #define REAL_ARITHMETIC
1228 /* Define this if most significant bit is lowest numbered
1229 in instructions that operate on numbered bit-fields.
1231 #define BITS_BIG_ENDIAN 0
1233 /* Define this if most significant byte of a word is the lowest numbered. */
1234 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1236 /* Define this if most significant word of a multiword number is the lowest. */
1237 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1239 /* Define this to set the endianness to use in libgcc2.c, which can
1240 not depend on target_flags. */
1241 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1242 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1244 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1247 /* Number of bits in an addressable storage unit */
1248 #define BITS_PER_UNIT 8
1250 /* Width in bits of a "word", which is the contents of a machine register.
1251 Note that this is not necessarily the width of data type `int';
1252 if using 16-bit ints on a 68000, this would still be 32.
1253 But on a machine with 16-bit registers, this would be 16. */
1254 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1255 #define MAX_BITS_PER_WORD 64
1257 /* Width of a word, in units (bytes). */
1258 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1259 #define MIN_UNITS_PER_WORD 4
1261 /* For MIPS, width of a floating point register. */
1262 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1264 /* A C expression for the size in bits of the type `int' on the
1265 target machine. If you don't define this, the default is one
1267 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1268 #define MAX_INT_TYPE_SIZE 64
1270 /* Tell the preprocessor the maximum size of wchar_t. */
1271 #ifndef MAX_WCHAR_TYPE_SIZE
1272 #ifndef WCHAR_TYPE_SIZE
1273 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1277 /* A C expression for the size in bits of the type `short' on the
1278 target machine. If you don't define this, the default is half a
1279 word. (If this would be less than one storage unit, it is
1280 rounded up to one unit.) */
1281 #define SHORT_TYPE_SIZE 16
1283 /* A C expression for the size in bits of the type `long' on the
1284 target machine. If you don't define this, the default is one
1286 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1287 #define MAX_LONG_TYPE_SIZE 64
1289 /* A C expression for the size in bits of the type `long long' on the
1290 target machine. If you don't define this, the default is two
1292 #define LONG_LONG_TYPE_SIZE 64
1294 /* A C expression for the size in bits of the type `char' on the
1295 target machine. If you don't define this, the default is one
1296 quarter of a word. (If this would be less than one storage unit,
1297 it is rounded up to one unit.) */
1298 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1300 /* A C expression for the size in bits of the type `float' on the
1301 target machine. If you don't define this, the default is one
1303 #define FLOAT_TYPE_SIZE 32
1305 /* A C expression for the size in bits of the type `double' on the
1306 target machine. If you don't define this, the default is two
1308 #define DOUBLE_TYPE_SIZE 64
1310 /* A C expression for the size in bits of the type `long double' on
1311 the target machine. If you don't define this, the default is two
1313 #define LONG_DOUBLE_TYPE_SIZE 64
1315 /* Width in bits of a pointer.
1316 See also the macro `Pmode' defined below. */
1317 #ifndef POINTER_SIZE
1318 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1321 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1322 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1324 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1325 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1327 /* Allocation boundary (in *bits*) for the code of a function. */
1328 #define FUNCTION_BOUNDARY 32
1330 /* Alignment of field after `int : 0' in a structure. */
1331 #define EMPTY_FIELD_BOUNDARY 32
1333 /* Every structure's size must be a multiple of this. */
1334 /* 8 is observed right on a DECstation and on riscos 4.02. */
1335 #define STRUCTURE_SIZE_BOUNDARY 8
1337 /* There is no point aligning anything to a rounder boundary than this. */
1338 #define BIGGEST_ALIGNMENT 64
1340 /* Set this nonzero if move instructions will actually fail to work
1341 when given unaligned data. */
1342 #define STRICT_ALIGNMENT 1
1344 /* Define this if you wish to imitate the way many other C compilers
1345 handle alignment of bitfields and the structures that contain
1348 The behavior is that the type written for a bitfield (`int',
1349 `short', or other integer type) imposes an alignment for the
1350 entire structure, as if the structure really did contain an
1351 ordinary field of that type. In addition, the bitfield is placed
1352 within the structure so that it would fit within such a field,
1353 not crossing a boundary for it.
1355 Thus, on most machines, a bitfield whose type is written as `int'
1356 would not cross a four-byte boundary, and would force four-byte
1357 alignment for the whole structure. (The alignment used may not
1358 be four bytes; it is controlled by the other alignment
1361 If the macro is defined, its definition should be a C expression;
1362 a nonzero value for the expression enables this behavior. */
1364 #define PCC_BITFIELD_TYPE_MATTERS 1
1366 /* If defined, a C expression to compute the alignment given to a
1367 constant that is being placed in memory. CONSTANT is the constant
1368 and ALIGN is the alignment that the object would ordinarily have.
1369 The value of this macro is used instead of that alignment to align
1372 If this macro is not defined, then ALIGN is used.
1374 The typical use of this macro is to increase alignment for string
1375 constants to be word aligned so that `strcpy' calls that copy
1376 constants can be done inline. */
1378 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1379 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1380 && (ALIGN) < BITS_PER_WORD \
1384 /* If defined, a C expression to compute the alignment for a static
1385 variable. TYPE is the data type, and ALIGN is the alignment that
1386 the object would ordinarily have. The value of this macro is used
1387 instead of that alignment to align the object.
1389 If this macro is not defined, then ALIGN is used.
1391 One use of this macro is to increase alignment of medium-size
1392 data to make it all fit in fewer cache lines. Another is to
1393 cause character arrays to be word-aligned so that `strcpy' calls
1394 that copy constants to character arrays can be done inline. */
1396 #undef DATA_ALIGNMENT
1397 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1398 ((((ALIGN) < BITS_PER_WORD) \
1399 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1400 || TREE_CODE (TYPE) == UNION_TYPE \
1401 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1403 /* Define this macro if an argument declared as `char' or `short' in a
1404 prototype should actually be passed as an `int'. In addition to
1405 avoiding errors in certain cases of mismatch, it also makes for
1406 better code on certain machines. */
1408 #define PROMOTE_PROTOTYPES
1410 /* Define if operations between registers always perform the operation
1411 on the full register even if a narrower mode is specified. */
1412 #define WORD_REGISTER_OPERATIONS
1414 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1415 will either zero-extend or sign-extend. The value of this macro should
1416 be the code that says which one of the two operations is implicitly
1417 done, NIL if none. */
1418 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1420 /* Define this macro if it is advisable to hold scalars in registers
1421 in a wider mode than that declared by the program. In such cases,
1422 the value is constrained to be within the bounds of the declared
1423 type, but kept valid in the wider mode. The signedness of the
1424 extension may differ from that of the type.
1426 We promote any value smaller than SImode up to SImode. We don't
1427 want to promote to DImode when in 64 bit mode, because that would
1428 prevent us from using the faster SImode multiply and divide
1431 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1432 if (GET_MODE_CLASS (MODE) == MODE_INT \
1433 && GET_MODE_SIZE (MODE) < 4) \
1436 /* Define this if function arguments should also be promoted using the above
1439 #define PROMOTE_FUNCTION_ARGS
1441 /* Likewise, if the function return value is promoted. */
1443 #define PROMOTE_FUNCTION_RETURN
1445 /* Standard register usage. */
1447 /* Number of actual hardware registers.
1448 The hardware registers are assigned numbers for the compiler
1449 from 0 to just below FIRST_PSEUDO_REGISTER.
1450 All registers that the compiler knows about must be given numbers,
1451 even those that are not normally considered general registers.
1453 On the Mips, we have 32 integer registers, 32 floating point
1454 registers, 8 condition code registers, and the special registers
1455 hi, lo, hilo, and rap. The 8 condition code registers are only
1456 used if mips_isa >= 4. The hilo register is only used in 64 bit
1457 mode. It represents a 64 bit value stored as two 32 bit values in
1458 the hi and lo registers; this is the result of the mult
1459 instruction. rap is a pointer to the stack where the return
1460 address reg ($31) was stored. This is needed for C++ exception
1463 #define FIRST_PSEUDO_REGISTER 76
1465 /* 1 for registers that have pervasive standard uses
1466 and are not available for the register allocator.
1468 On the MIPS, see conventions, page D-2 */
1470 #define FIXED_REGISTERS \
1472 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1473 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1474 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1475 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1476 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1480 /* 1 for registers not available across function calls.
1481 These must include the FIXED_REGISTERS and also any
1482 registers that can be used without being saved.
1483 The latter must include the registers where values are returned
1484 and the register where structure-value addresses are passed.
1485 Aside from that, you can include as many other registers as you like. */
1487 #define CALL_USED_REGISTERS \
1489 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1490 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1491 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1492 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1493 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1497 /* Internal macros to classify a register number as to whether it's a
1498 general purpose register, a floating point register, a
1499 multiply/divide register, or a status register. */
1501 #define GP_REG_FIRST 0
1502 #define GP_REG_LAST 31
1503 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1504 #define GP_DBX_FIRST 0
1506 #define FP_REG_FIRST 32
1507 #define FP_REG_LAST 63
1508 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1509 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1511 #define MD_REG_FIRST 64
1512 #define MD_REG_LAST 66
1513 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1515 #define ST_REG_FIRST 67
1516 #define ST_REG_LAST 74
1517 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1519 #define RAP_REG_NUM 75
1521 #define AT_REGNUM (GP_REG_FIRST + 1)
1522 #define HI_REGNUM (MD_REG_FIRST + 0)
1523 #define LO_REGNUM (MD_REG_FIRST + 1)
1524 #define HILO_REGNUM (MD_REG_FIRST + 2)
1526 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1527 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1528 should be used instead. */
1529 #define FPSW_REGNUM ST_REG_FIRST
1531 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1532 #define M16_REG_P(REGNO) \
1533 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1534 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1535 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1536 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1538 /* Return number of consecutive hard regs needed starting at reg REGNO
1539 to hold something of mode MODE.
1540 This is ordinarily the length in words of a value of mode MODE
1541 but can be less for certain modes in special long registers.
1543 On the MIPS, all general registers are one word long. Except on
1544 the R4000 with the FR bit set, the floating point uses register
1545 pairs, with the second register not being allocable. */
1547 #define HARD_REGNO_NREGS(REGNO, MODE) \
1548 (! FP_REG_P (REGNO) \
1549 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1550 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1552 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1553 MODE. In 32 bit mode, require that DImode and DFmode be in even
1554 registers. For DImode, this makes some of the insns easier to
1555 write, since you don't have to worry about a DImode value in
1556 registers 3 & 4, producing a result in 4 & 5.
1558 To make the code simpler HARD_REGNO_MODE_OK now just references an
1559 array built in override_options. Because machmodes.h is not yet
1560 included before this file is processed, the MODE bound can't be
1563 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1565 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1566 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1568 /* Value is 1 if it is a good idea to tie two pseudo registers
1569 when one has mode MODE1 and one has mode MODE2.
1570 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1571 for any hard reg, then this must be 0 for correct output. */
1572 #define MODES_TIEABLE_P(MODE1, MODE2) \
1573 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1574 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1575 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1576 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1578 /* MIPS pc is not overloaded on a register. */
1579 /* #define PC_REGNUM xx */
1581 /* Register to use for pushing function arguments. */
1582 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1584 /* Offset from the stack pointer to the first available location. Use
1585 the default value zero. */
1586 /* #define STACK_POINTER_OFFSET 0 */
1588 /* Base register for access to local variables of the function. We
1589 pretend that the frame pointer is $1, and then eliminate it to
1590 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1591 a fixed register, and will not be used for anything else. */
1592 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1594 /* $30 is not available on the mips16, so we use $17 as the frame
1596 #define HARD_FRAME_POINTER_REGNUM \
1597 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1599 /* Value should be nonzero if functions must have frame pointers.
1600 Zero means the frame pointer need not be set up (and parms
1601 may be accessed via the stack pointer) in functions that seem suitable.
1602 This is computed in `reload', in reload1.c. */
1603 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1605 /* Base register for access to arguments of the function. */
1606 #define ARG_POINTER_REGNUM GP_REG_FIRST
1608 /* Fake register that holds the address on the stack of the
1609 current function's return address. */
1610 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1612 /* Register in which static-chain is passed to a function. */
1613 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1615 /* If the structure value address is passed in a register, then
1616 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1617 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1619 /* If the structure value address is not passed in a register, define
1620 `STRUCT_VALUE' as an expression returning an RTX for the place
1621 where the address is passed. If it returns 0, the address is
1622 passed as an "invisible" first argument. */
1623 #define STRUCT_VALUE 0
1625 /* Mips registers used in prologue/epilogue code when the stack frame
1626 is larger than 32K bytes. These registers must come from the
1627 scratch register set, and not used for passing and returning
1628 arguments and any other information used in the calling sequence
1629 (such as pic). Must start at 12, since t0/t3 are parameter passing
1630 registers in the 64 bit ABI. */
1632 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1633 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1635 /* Define this macro if it is as good or better to call a constant
1636 function address than to call an address kept in a register. */
1637 #define NO_FUNCTION_CSE 1
1639 /* Define this macro if it is as good or better for a function to
1640 call itself with an explicit address than to call an address
1641 kept in a register. */
1642 #define NO_RECURSIVE_FUNCTION_CSE 1
1644 /* The register number of the register used to address a table of
1645 static data addresses in memory. In some cases this register is
1646 defined by a processor's "application binary interface" (ABI).
1647 When this macro is defined, RTL is generated for this register
1648 once, as with the stack pointer and frame pointer registers. If
1649 this macro is not defined, it is up to the machine-dependent
1650 files to allocate such a register (if necessary). */
1651 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1653 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1655 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1656 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1657 isn't always called for static inline functions. */
1658 #define INIT_EXPANDERS \
1660 embedded_pic_fnaddr_rtx = NULL; \
1661 mips16_gp_pseudo_rtx = NULL; \
1664 /* Define the classes of registers for register constraints in the
1665 machine description. Also define ranges of constants.
1667 One of the classes must always be named ALL_REGS and include all hard regs.
1668 If there is more than one class, another class must be named NO_REGS
1669 and contain no registers.
1671 The name GENERAL_REGS must be the name of a class (or an alias for
1672 another name such as ALL_REGS). This is the class of registers
1673 that is allowed by "g" or "r" in a register constraint.
1674 Also, registers outside this class are allocated only when
1675 instructions express preferences for them.
1677 The classes must be numbered in nondecreasing order; that is,
1678 a larger-numbered class must never be contained completely
1679 in a smaller-numbered class.
1681 For any two classes, it is very desirable that there be another
1682 class that represents their union. */
1686 NO_REGS, /* no registers in set */
1687 M16_NA_REGS, /* mips16 regs not used to pass args */
1688 M16_REGS, /* mips16 directly accessible registers */
1689 T_REG, /* mips16 T register ($24) */
1690 M16_T_REGS, /* mips16 registers plus T register */
1691 GR_REGS, /* integer registers */
1692 FP_REGS, /* floating point registers */
1693 HI_REG, /* hi register */
1694 LO_REG, /* lo register */
1695 HILO_REG, /* hilo register pair for 64 bit mode mult */
1696 MD_REGS, /* multiply/divide registers (hi/lo) */
1697 ST_REGS, /* status registers (fp status) */
1698 ALL_REGS, /* all registers */
1699 LIM_REG_CLASSES /* max value + 1 */
1702 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1704 #define GENERAL_REGS GR_REGS
1706 /* An initializer containing the names of the register classes as C
1707 string constants. These names are used in writing some of the
1710 #define REG_CLASS_NAMES \
1727 /* An initializer containing the contents of the register classes,
1728 as integers which are bit masks. The Nth integer specifies the
1729 contents of class N. The way the integer MASK is interpreted is
1730 that register R is in the class if `MASK & (1 << R)' is 1.
1732 When the machine has more than 32 registers, an integer does not
1733 suffice. Then the integers are replaced by sub-initializers,
1734 braced groupings containing several integers. Each
1735 sub-initializer must be suitable as an initializer for the type
1736 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1738 #define REG_CLASS_CONTENTS \
1740 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1741 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1742 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1743 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1744 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1745 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1746 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1747 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1748 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1749 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1750 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1751 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1752 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1756 /* A C expression whose value is a register class containing hard
1757 register REGNO. In general there is more that one such class;
1758 choose a class which is "minimal", meaning that no smaller class
1759 also contains the register. */
1761 extern enum reg_class mips_regno_to_class[];
1763 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1765 /* A macro whose definition is the name of the class to which a
1766 valid base register must belong. A base register is one used in
1767 an address which is the register value plus a displacement. */
1769 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1771 /* A macro whose definition is the name of the class to which a
1772 valid index register must belong. An index register is one used
1773 in an address where its value is either multiplied by a scale
1774 factor or added to another register (as well as added to a
1777 #define INDEX_REG_CLASS NO_REGS
1779 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1780 registers explicitly used in the rtl to be used as spill registers
1781 but prevents the compiler from extending the lifetime of these
1784 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1786 /* This macro is used later on in the file. */
1787 #define GR_REG_CLASS_P(CLASS) \
1788 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1789 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1791 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1792 is the default value (allocate the registers in numeric order). We
1793 define it just so that we can override it for the mips16 target in
1794 ORDER_REGS_FOR_LOCAL_ALLOC. */
1796 #define REG_ALLOC_ORDER \
1797 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1798 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1799 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1800 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1801 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1804 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1805 to be rearranged based on a particular function. On the mips16, we
1806 want to allocate $24 (T_REG) before other registers for
1807 instructions for which it is possible. */
1809 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1811 /* REGISTER AND CONSTANT CLASSES */
1813 /* Get reg_class from a letter such as appears in the machine
1816 DEFINED REGISTER CLASSES:
1818 'd' General (aka integer) registers
1819 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1820 'y' General registers (in both mips16 and non mips16 mode)
1821 'e' mips16 non argument registers (M16_NA_REGS)
1822 't' mips16 temporary register ($24)
1823 'f' Floating point registers
1826 'x' Multiply/divide registers
1828 'z' FP Status register
1829 'b' All registers */
1831 extern enum reg_class mips_char_to_class[];
1833 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1835 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1836 string can be used to stand for particular ranges of immediate
1837 operands. This macro defines what the ranges are. C is the
1838 letter, and VALUE is a constant value. Return 1 if VALUE is
1839 in the range specified by C. */
1843 `I' is used for the range of constants an arithmetic insn can
1844 actually contain (16 bits signed integers).
1846 `J' is used for the range which is just zero (ie, $r0).
1848 `K' is used for the range of constants a logical insn can actually
1849 contain (16 bit zero-extended integers).
1851 `L' is used for the range of constants that be loaded with lui
1852 (ie, the bottom 16 bits are zero).
1854 `M' is used for the range of constants that take two words to load
1855 (ie, not matched by `I', `K', and `L').
1857 `N' is used for negative 16 bit constants other than -65536.
1859 `O' is a 15 bit signed integer.
1861 `P' is used for positive 16 bit constants. */
1863 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1864 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1866 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1867 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1868 : (C) == 'J' ? ((VALUE) == 0) \
1869 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1870 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1871 && (((VALUE) & ~2147483647) == 0 \
1872 || ((VALUE) & ~2147483647) == ~2147483647)) \
1873 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1874 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1875 && (((VALUE) & 0x0000ffff) != 0 \
1876 || (((VALUE) & ~2147483647) != 0 \
1877 && ((VALUE) & ~2147483647) != ~2147483647))) \
1878 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1879 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1880 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1883 /* Similar, but for floating constants, and defining letters G and H.
1884 Here VALUE is the CONST_DOUBLE rtx itself. */
1888 'G' : Floating point 0 */
1890 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1892 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1894 /* Letters in the range `Q' through `U' may be defined in a
1895 machine-dependent fashion to stand for arbitrary operand types.
1896 The machine description macro `EXTRA_CONSTRAINT' is passed the
1897 operand as its first argument and the constraint letter as its
1900 `Q' is for mips16 GP relative constants
1901 `R' is for memory references which take 1 word for the instruction.
1902 `S' is for references to extern items which are PIC for OSF/rose.
1903 `T' is for memory addresses that can be used to load two words. */
1905 #define EXTRA_CONSTRAINT(OP,CODE) \
1906 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
1907 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
1908 && mips16_gp_offset_p (OP)) \
1909 : (GET_CODE (OP) != MEM) ? FALSE \
1910 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1911 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1912 && HALF_PIC_ADDRESS_P (OP)) \
1915 /* Given an rtx X being reloaded into a reg required to be
1916 in class CLASS, return the class of reg to actually use.
1917 In general this is just CLASS; but on some machines
1918 in some cases it is preferable to use a more restrictive class. */
1920 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1921 ((CLASS) != ALL_REGS \
1922 ? (! TARGET_MIPS16 \
1924 : ((CLASS) != GR_REGS \
1927 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1928 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1929 ? (TARGET_SOFT_FLOAT \
1930 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1932 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1933 || GET_MODE (X) == VOIDmode) \
1934 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1937 /* Certain machines have the property that some registers cannot be
1938 copied to some other registers without using memory. Define this
1939 macro on those machines to be a C expression that is non-zero if
1940 objects of mode MODE in registers of CLASS1 can only be copied to
1941 registers of class CLASS2 by storing a register of CLASS1 into
1942 memory and loading that memory location into a register of CLASS2.
1944 Do not define this macro if its value would always be zero. */
1946 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1947 ((!TARGET_DEBUG_H_MODE \
1948 && GET_MODE_CLASS (MODE) == MODE_INT \
1949 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1950 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1951 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1952 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1953 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1955 /* The HI and LO registers can only be reloaded via the general
1956 registers. Condition code registers can only be loaded to the
1957 general registers, and from the floating point registers. */
1959 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1960 mips_secondary_reload_class (CLASS, MODE, X, 1)
1961 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1962 mips_secondary_reload_class (CLASS, MODE, X, 0)
1964 /* Not declared above, with the other functions, because enum
1965 reg_class is not declared yet. */
1966 extern enum reg_class mips_secondary_reload_class ();
1968 /* Return the maximum number of consecutive registers
1969 needed to represent mode MODE in a register of class CLASS. */
1971 #define CLASS_UNITS(mode, size) \
1972 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
1974 #define CLASS_MAX_NREGS(CLASS, MODE) \
1975 ((CLASS) == FP_REGS \
1977 ? CLASS_UNITS (MODE, 8) \
1978 : 2 * CLASS_UNITS (MODE, 8)) \
1979 : CLASS_UNITS (MODE, UNITS_PER_WORD))
1981 /* If defined, this is a C expression whose value should be
1982 nonzero if the insn INSN has the effect of mysteriously
1983 clobbering the contents of hard register number REGNO. By
1984 "mysterious" we mean that the insn's RTL expression doesn't
1985 describe such an effect.
1987 If this macro is not defined, it means that no insn clobbers
1988 registers mysteriously. This is the usual situation; all else
1989 being equal, it is best for the RTL expression to show all the
1992 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
1995 /* Stack layout; function entry, exit and calling. */
1997 /* Define this if pushing a word on the stack
1998 makes the stack pointer a smaller address. */
1999 #define STACK_GROWS_DOWNWARD
2001 /* Define this if the nominal address of the stack frame
2002 is at the high-address end of the local variables;
2003 that is, each additional local variable allocated
2004 goes at a more negative offset in the frame. */
2005 /* #define FRAME_GROWS_DOWNWARD */
2007 /* Offset within stack frame to start allocating local variables at.
2008 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2009 first local allocated. Otherwise, it is the offset to the BEGINNING
2010 of the first local allocated. */
2011 #define STARTING_FRAME_OFFSET \
2012 (current_function_outgoing_args_size \
2013 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2015 /* Offset from the stack pointer register to an item dynamically
2016 allocated on the stack, e.g., by `alloca'.
2018 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2019 length of the outgoing arguments. The default is correct for most
2020 machines. See `function.c' for details.
2022 The MIPS ABI states that functions which dynamically allocate the
2023 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2024 we are trying to create a second frame pointer to the function, so
2025 allocate some stack space to make it happy.
2027 However, the linker currently complains about linking any code that
2028 dynamically allocates stack space, and there seems to be a bug in
2029 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2032 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2033 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2034 ? 4*UNITS_PER_WORD \
2035 : current_function_outgoing_args_size)
2038 /* The return address for the current frame is in r31 is this is a leaf
2039 function. Otherwise, it is on the stack. It is at a variable offset
2040 from sp/fp/ap, so we define a fake hard register rap which is a
2041 poiner to the return address on the stack. This always gets eliminated
2042 during reload to be either the frame pointer or the stack pointer plus
2045 /* ??? This definition fails for leaf functions. There is currently no
2046 general solution for this problem. */
2048 /* ??? There appears to be no way to get the return address of any previous
2049 frame except by disassembling instructions in the prologue/epilogue.
2050 So currently we support only the current frame. */
2052 #define RETURN_ADDR_RTX(count, frame) \
2054 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2057 /* Structure to be filled in by compute_frame_size with register
2058 save masks, and offsets for the current function. */
2060 struct mips_frame_info
2062 long total_size; /* # bytes that the entire frame takes up */
2063 long var_size; /* # bytes that variables take up */
2064 long args_size; /* # bytes that outgoing arguments take up */
2065 long extra_size; /* # bytes of extra gunk */
2066 int gp_reg_size; /* # bytes needed to store gp regs */
2067 int fp_reg_size; /* # bytes needed to store fp regs */
2068 long mask; /* mask of saved gp registers */
2069 long fmask; /* mask of saved fp registers */
2070 long gp_save_offset; /* offset from vfp to store gp registers */
2071 long fp_save_offset; /* offset from vfp to store fp registers */
2072 long gp_sp_offset; /* offset from new sp to store gp registers */
2073 long fp_sp_offset; /* offset from new sp to store fp registers */
2074 int initialized; /* != 0 if frame size already calculated */
2075 int num_gp; /* number of gp registers saved */
2076 int num_fp; /* number of fp registers saved */
2077 long insns_len; /* length of insns; mips16 only */
2080 extern struct mips_frame_info current_frame_info;
2082 /* If defined, this macro specifies a table of register pairs used to
2083 eliminate unneeded registers that point into the stack frame. If
2084 it is not defined, the only elimination attempted by the compiler
2085 is to replace references to the frame pointer with references to
2088 The definition of this macro is a list of structure
2089 initializations, each of which specifies an original and
2090 replacement register.
2092 On some machines, the position of the argument pointer is not
2093 known until the compilation is completed. In such a case, a
2094 separate hard register must be used for the argument pointer.
2095 This register can be eliminated by replacing it with either the
2096 frame pointer or the argument pointer, depending on whether or not
2097 the frame pointer has been eliminated.
2099 In this case, you might specify:
2100 #define ELIMINABLE_REGS \
2101 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2102 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2103 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2105 Note that the elimination of the argument pointer with the stack
2106 pointer is specified first since that is the preferred elimination.
2108 The eliminations to $17 are only used on the mips16. See the
2109 definition of HARD_FRAME_POINTER_REGNUM. */
2111 #define ELIMINABLE_REGS \
2112 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2113 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2114 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2115 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2116 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2117 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2118 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2119 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2120 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2122 /* A C expression that returns non-zero if the compiler is allowed to
2123 try to replace register number FROM-REG with register number
2124 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2125 defined, and will usually be the constant 1, since most of the
2126 cases preventing register elimination are things that the compiler
2127 already knows about.
2129 When not in mips16 and mips64, we can always eliminate to the
2130 frame pointer. We can eliminate to the stack pointer unless
2131 a frame pointer is needed. In mips16 mode, we need a frame
2132 pointer for a large frame; otherwise, reload may be unable
2133 to compute the address of a local variable, since there is
2134 no way to add a large constant to the stack pointer
2135 without using a temporary register.
2137 In mips16, for some instructions (eg lwu), we can't eliminate the
2138 frame pointer for the stack pointer. These instructions are
2139 only generated in TARGET_64BIT mode.
2142 #define CAN_ELIMINATE(FROM, TO) \
2143 ((TO) == HARD_FRAME_POINTER_REGNUM \
2144 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2145 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2146 && (! TARGET_MIPS16 \
2147 || compute_frame_size (get_frame_size ()) < 32768)))
2149 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2150 specifies the initial difference between the specified pair of
2151 registers. This macro must be defined if `ELIMINABLE_REGS' is
2154 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2155 { compute_frame_size (get_frame_size ()); \
2156 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2157 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2158 (OFFSET) = - current_function_outgoing_args_size; \
2159 else if ((FROM) == FRAME_POINTER_REGNUM) \
2161 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2162 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2163 (OFFSET) = (current_frame_info.total_size \
2164 - current_function_outgoing_args_size \
2165 - ((mips_abi != ABI_32 && mips_abi != ABI_EABI) \
2166 ? current_function_pretend_args_size \
2168 else if ((FROM) == ARG_POINTER_REGNUM) \
2169 (OFFSET) = (current_frame_info.total_size \
2170 - ((mips_abi != ABI_32 && mips_abi != ABI_EABI) \
2171 ? current_function_pretend_args_size \
2173 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2174 so we must add 4 bytes to the offset to get the right value. */ \
2175 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2176 (OFFSET) = current_frame_info.gp_sp_offset \
2177 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2178 * (BYTES_BIG_ENDIAN != 0)); \
2181 /* If we generate an insn to push BYTES bytes,
2182 this says how many the stack pointer really advances by.
2183 On the vax, sp@- in a byte insn really pushes a word. */
2185 /* #define PUSH_ROUNDING(BYTES) 0 */
2187 /* If defined, the maximum amount of space required for outgoing
2188 arguments will be computed and placed into the variable
2189 `current_function_outgoing_args_size'. No space will be pushed
2190 onto the stack for each call; instead, the function prologue
2191 should increase the stack frame size by this amount.
2193 It is not proper to define both `PUSH_ROUNDING' and
2194 `ACCUMULATE_OUTGOING_ARGS'. */
2195 #define ACCUMULATE_OUTGOING_ARGS
2197 /* Offset from the argument pointer register to the first argument's
2198 address. On some machines it may depend on the data type of the
2201 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2202 the first argument's address.
2204 On the MIPS, we must skip the first argument position if we are
2205 returning a structure or a union, to account for its address being
2206 passed in $4. However, at the current time, this produces a compiler
2207 that can't bootstrap, so comment it out for now. */
2210 #define FIRST_PARM_OFFSET(FNDECL) \
2212 && TREE_TYPE (FNDECL) != 0 \
2213 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2214 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2215 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2219 #define FIRST_PARM_OFFSET(FNDECL) 0
2222 /* When a parameter is passed in a register, stack space is still
2223 allocated for it. For the MIPS, stack space must be allocated, cf
2224 Asm Lang Prog Guide page 7-8.
2226 BEWARE that some space is also allocated for non existing arguments
2227 in register. In case an argument list is of form GF used registers
2228 are a0 (a2,a3), but we should push over a1... */
2230 #define REG_PARM_STACK_SPACE(FNDECL) \
2231 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2233 /* Define this if it is the responsibility of the caller to
2234 allocate the area reserved for arguments passed in registers.
2235 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2236 of this macro is to determine whether the space is included in
2237 `current_function_outgoing_args_size'. */
2238 #define OUTGOING_REG_PARM_STACK_SPACE
2240 /* Align stack frames on 64 bits (Double Word ). */
2241 #define STACK_BOUNDARY 64
2243 /* Make sure 4 words are always allocated on the stack. */
2245 #ifndef STACK_ARGS_ADJUST
2246 #define STACK_ARGS_ADJUST(SIZE) \
2248 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2249 SIZE.constant = 4 * UNITS_PER_WORD; \
2254 /* A C expression that should indicate the number of bytes of its
2255 own arguments that a function function pops on returning, or 0
2256 if the function pops no arguments and the caller must therefore
2257 pop them all after the function returns.
2259 FUNDECL is the declaration node of the function (as a tree).
2261 FUNTYPE is a C variable whose value is a tree node that
2262 describes the function in question. Normally it is a node of
2263 type `FUNCTION_TYPE' that describes the data type of the function.
2264 From this it is possible to obtain the data types of the value
2265 and arguments (if known).
2267 When a call to a library function is being considered, FUNTYPE
2268 will contain an identifier node for the library function. Thus,
2269 if you need to distinguish among various library functions, you
2270 can do so by their names. Note that "library function" in this
2271 context means a function used to perform arithmetic, whose name
2272 is known specially in the compiler and was not mentioned in the
2273 C code being compiled.
2275 STACK-SIZE is the number of bytes of arguments passed on the
2276 stack. If a variable number of bytes is passed, it is zero, and
2277 argument popping will always be the responsibility of the
2278 calling function. */
2280 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2283 /* Symbolic macros for the registers used to return integer and floating
2286 #define GP_RETURN (GP_REG_FIRST + 2)
2287 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2289 /* Symbolic macros for the first/last argument registers. */
2291 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2292 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2293 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2294 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2296 #define MAX_ARGS_IN_REGISTERS 4
2298 /* Define how to find the value returned by a library function
2299 assuming the value has mode MODE. Because we define
2300 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2301 PROMOTE_MODE does. */
2303 #define LIBCALL_VALUE(MODE) \
2305 ((GET_MODE_CLASS (MODE) != MODE_INT \
2306 || GET_MODE_SIZE (MODE) >= 4) \
2309 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2310 && (! TARGET_SINGLE_FLOAT \
2311 || GET_MODE_SIZE (MODE) <= 4)) \
2315 /* Define how to find the value returned by a function.
2316 VALTYPE is the data type of the value (as a tree).
2317 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2318 otherwise, FUNC is 0. */
2320 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2323 /* 1 if N is a possible register number for a function value.
2324 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2325 Currently, R2 and F0 are only implemented here (C has no complex type) */
2327 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2329 /* 1 if N is a possible register number for function argument passing.
2330 We have no FP argument registers when soft-float. When FP registers
2331 are 32 bits, we can't directly reference the odd numbered ones. */
2333 #define FUNCTION_ARG_REGNO_P(N) \
2334 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2335 || ((! TARGET_SOFT_FLOAT \
2336 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2337 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2338 && ! fixed_regs[N]))
2340 /* A C expression which can inhibit the returning of certain function
2341 values in registers, based on the type of value. A nonzero value says
2342 to return the function value in memory, just as large structures are
2343 always returned. Here TYPE will be a C expression of type
2344 `tree', representing the data type of the value.
2346 Note that values of mode `BLKmode' must be explicitly
2347 handled by this macro. Also, the option `-fpcc-struct-return'
2348 takes effect regardless of this macro. On most systems, it is
2349 possible to leave the macro undefined; this causes a default
2350 definition to be used, whose value is the constant 1 for BLKmode
2351 values, and 0 otherwise.
2353 GCC normally converts 1 byte structures into chars, 2 byte
2354 structs into shorts, and 4 byte structs into ints, and returns
2355 them this way. Defining the following macro overrides this,
2356 to give us MIPS cc compatibility. */
2358 #define RETURN_IN_MEMORY(TYPE) \
2359 (TYPE_MODE (TYPE) == BLKmode)
2361 /* A code distinguishing the floating point format of the target
2362 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2363 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2365 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2368 /* Define a data type for recording info about an argument list
2369 during the scan of that argument list. This data type should
2370 hold all necessary information about the function itself
2371 and about the args processed so far, enough to enable macros
2372 such as FUNCTION_ARG to determine where the next arg should go.
2374 On the mips16, we need to keep track of which floating point
2375 arguments were passed in general registers, but would have been
2376 passed in the FP regs if this were a 32 bit function, so that we
2377 can move them to the FP regs if we wind up calling a 32 bit
2378 function. We record this information in fp_code, encoded in base
2379 four. A zero digit means no floating point argument, a one digit
2380 means an SFmode argument, and a two digit means a DFmode argument,
2381 and a three digit is not used. The low order digit is the first
2382 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2383 an SFmode argument. ??? A more sophisticated approach will be
2384 needed if MIPS_ABI != ABI_32. */
2386 typedef struct mips_args {
2387 int gp_reg_found; /* whether a gp register was found yet */
2388 int arg_number; /* argument number */
2389 int arg_words; /* # total words the arguments take */
2390 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2391 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2392 int fp_code; /* Mode of FP arguments (mips16) */
2393 int num_adjusts; /* number of adjustments made */
2394 /* Adjustments made to args pass in regs. */
2395 /* ??? The size is doubled to work around a
2396 bug in the code that sets the adjustments
2398 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2401 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2402 for a call to a function whose data type is FNTYPE.
2403 For a library call, FNTYPE is 0.
2407 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2408 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2410 /* Update the data in CUM to advance over an argument
2411 of mode MODE and data type TYPE.
2412 (TYPE is null for libcalls where that information may not be available.) */
2414 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2415 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2417 /* Determine where to put an argument to a function.
2418 Value is zero to push the argument on the stack,
2419 or a hard register in which to store the argument.
2421 MODE is the argument's machine mode.
2422 TYPE is the data type of the argument (as a tree).
2423 This is null for libcalls where that information may
2425 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2426 the preceding args and about the function being called.
2427 NAMED is nonzero if this argument is a named parameter
2428 (otherwise it is an extra parameter matching an ellipsis). */
2430 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2431 function_arg( &CUM, MODE, TYPE, NAMED)
2433 /* For an arg passed partly in registers and partly in memory,
2434 this is the number of registers used.
2435 For args passed entirely in registers or entirely in memory, zero. */
2437 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2438 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2440 /* If defined, a C expression that gives the alignment boundary, in
2441 bits, of an argument with the specified mode and type. If it is
2442 not defined, `PARM_BOUNDARY' is used for all arguments. */
2444 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2446 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2448 : TYPE_ALIGN(TYPE)) \
2449 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2451 : GET_MODE_ALIGNMENT(MODE)))
2454 /* This macro generates the assembly code for function entry.
2455 FILE is a stdio stream to output the code to.
2456 SIZE is an int: how many units of temporary storage to allocate.
2457 Refer to the array `regs_ever_live' to determine which registers
2458 to save; `regs_ever_live[I]' is nonzero if register number I
2459 is ever used in the function. This macro is responsible for
2460 knowing which registers should not be saved even if used. */
2462 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2464 /* This macro generates the assembly code for function exit,
2465 on machines that need it. If FUNCTION_EPILOGUE is not defined
2466 then individual return instructions are generated for each
2467 return statement. Args are same as for FUNCTION_PROLOGUE. */
2469 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2471 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2473 #define MUST_SAVE_REGISTER(regno) \
2474 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2475 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2476 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2478 /* ALIGN FRAMES on double word boundaries */
2480 #define MIPS_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
2483 /* Output assembler code to FILE to increment profiler label # LABELNO
2484 for profiling a function entry. */
2486 #define FUNCTION_PROFILER(FILE, LABELNO) \
2488 if (TARGET_MIPS16) \
2489 sorry ("mips16 function profiling"); \
2490 fprintf (FILE, "\t.set\tnoreorder\n"); \
2491 fprintf (FILE, "\t.set\tnoat\n"); \
2492 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2493 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2494 fprintf (FILE, "\tjal\t_mcount\n"); \
2496 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2497 TARGET_64BIT ? "dsubu" : "subu", \
2498 reg_names[STACK_POINTER_REGNUM], \
2499 reg_names[STACK_POINTER_REGNUM], \
2500 Pmode == DImode ? 16 : 8); \
2501 fprintf (FILE, "\t.set\treorder\n"); \
2502 fprintf (FILE, "\t.set\tat\n"); \
2505 /* Define this macro if the code for function profiling should come
2506 before the function prologue. Normally, the profiling code comes
2509 /* #define PROFILE_BEFORE_PROLOGUE */
2511 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2512 the stack pointer does not matter. The value is tested only in
2513 functions that have frame pointers.
2514 No definition is equivalent to always zero. */
2516 #define EXIT_IGNORE_STACK 1
2519 /* A C statement to output, on the stream FILE, assembler code for a
2520 block of data that contains the constant parts of a trampoline.
2521 This code should not include a label--the label is taken care of
2524 #define TRAMPOLINE_TEMPLATE(STREAM) \
2526 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2527 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2528 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2529 if (Pmode == DImode) \
2531 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2532 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2536 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2537 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2539 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2540 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2541 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2542 if (Pmode == DImode) \
2544 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2545 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2549 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2550 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2554 /* A C expression for the size in bytes of the trampoline, as an
2557 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2559 /* Alignment required for trampolines, in bits. */
2561 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2563 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2564 program and data caches. */
2566 #ifndef CACHE_FLUSH_FUNC
2567 #define CACHE_FLUSH_FUNC "_flush_cache"
2570 /* A C statement to initialize the variable parts of a trampoline.
2571 ADDR is an RTX for the address of the trampoline; FNADDR is an
2572 RTX for the address of the nested function; STATIC_CHAIN is an
2573 RTX for the static chain value that should be passed to the
2574 function when it is called. */
2576 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2579 if (Pmode == DImode) \
2581 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2582 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2586 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2587 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2590 /* Flush both caches. We need to flush the data cache in case \
2591 the system has a write-back cache. */ \
2592 /* ??? Should check the return value for errors. */ \
2593 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, CACHE_FLUSH_FUNC), \
2594 0, VOIDmode, 3, addr, Pmode, \
2595 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2596 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2599 /* Addressing modes, and classification of registers for them. */
2601 /* #define HAVE_POST_INCREMENT */
2602 /* #define HAVE_POST_DECREMENT */
2604 /* #define HAVE_PRE_DECREMENT */
2605 /* #define HAVE_PRE_INCREMENT */
2607 /* These assume that REGNO is a hard or pseudo reg number.
2608 They give nonzero only if REGNO is a hard reg of the suitable class
2609 or a pseudo reg currently allocated to a suitable hard reg.
2610 These definitions are NOT overridden anywhere. */
2612 #define BASE_REG_P(regno, mode) \
2614 ? (M16_REG_P (regno) \
2615 || (regno) == FRAME_POINTER_REGNUM \
2616 || (regno) == ARG_POINTER_REGNUM \
2617 || ((regno) == STACK_POINTER_REGNUM \
2618 && (GET_MODE_SIZE (mode) == 4 \
2619 || GET_MODE_SIZE (mode) == 8))) \
2622 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2623 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2626 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2627 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2629 #define REGNO_OK_FOR_INDEX_P(regno) 0
2630 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2631 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2633 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2634 and check its validity for a certain class.
2635 We have two alternate definitions for each of them.
2636 The usual definition accepts all pseudo regs; the other rejects them all.
2637 The symbol REG_OK_STRICT causes the latter definition to be used.
2639 Most source files want to accept pseudo regs in the hope that
2640 they will get allocated to the class that the insn wants them to be in.
2641 Some source files that are used after register allocation
2642 need to be strict. */
2644 #ifndef REG_OK_STRICT
2646 #define REG_OK_STRICT_P 0
2647 #define REG_OK_FOR_INDEX_P(X) 0
2648 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2649 GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
2653 #define REG_OK_STRICT_P 1
2654 #define REG_OK_FOR_INDEX_P(X) 0
2655 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2656 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
2661 /* Maximum number of registers that can appear in a valid memory address. */
2663 #define MAX_REGS_PER_ADDRESS 1
2665 /* A C compound statement with a conditional `goto LABEL;' executed
2666 if X (an RTX) is a legitimate memory address on the target
2667 machine for a memory operand of mode MODE.
2669 It usually pays to define several simpler macros to serve as
2670 subroutines for this one. Otherwise it may be too complicated
2673 This macro must exist in two variants: a strict variant and a
2674 non-strict one. The strict variant is used in the reload pass.
2675 It must be defined so that any pseudo-register that has not been
2676 allocated a hard register is considered a memory reference. In
2677 contexts where some kind of register is required, a
2678 pseudo-register with no hard register must be rejected.
2680 The non-strict variant is used in other passes. It must be
2681 defined to accept all pseudo-registers in every context where
2682 some kind of register is required.
2684 Compiler source files that want to use the strict variant of
2685 this macro define the macro `REG_OK_STRICT'. You should use an
2686 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2687 in that case and the non-strict variant otherwise.
2689 Typically among the subroutines used to define
2690 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2691 acceptable registers for various purposes (one for base
2692 registers, one for index registers, and so on). Then only these
2693 subroutine macros need have two variants; the higher levels of
2694 macros may be the same whether strict or not.
2696 Normally, constant addresses which are the sum of a `symbol_ref'
2697 and an integer are stored inside a `const' RTX to mark them as
2698 constant. Therefore, there is no need to recognize such sums
2699 specifically as legitimate addresses. Normally you would simply
2700 recognize any `const' as legitimate.
2702 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2703 constant sums that are not marked with `const'. It assumes
2704 that a naked `plus' indicates indexing. If so, then you *must*
2705 reject such naked constant sums as illegitimate addresses, so
2706 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2708 On some machines, whether a symbolic address is legitimate
2709 depends on the section that the address refers to. On these
2710 machines, define the macro `ENCODE_SECTION_INFO' to store the
2711 information into the `symbol_ref', and then check for it here.
2712 When you see a `const', you will have to look inside it to find
2713 the `symbol_ref' in order to determine the section. */
2716 #define GO_PRINTF(x) trace(x)
2717 #define GO_PRINTF2(x,y) trace(x,y)
2718 #define GO_DEBUG_RTX(x) debug_rtx(x)
2721 #define GO_PRINTF(x)
2722 #define GO_PRINTF2(x,y)
2723 #define GO_DEBUG_RTX(x)
2726 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2728 register rtx xinsn = (X); \
2730 if (TARGET_DEBUG_B_MODE) \
2732 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2733 (REG_OK_STRICT_P) ? "" : "not "); \
2734 GO_DEBUG_RTX (xinsn); \
2737 /* The mips16 can only use the stack pointer as a base register when \
2738 loading SImode or DImode values. */ \
2739 if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \
2742 if (CONSTANT_ADDRESS_P (xinsn) \
2743 && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \
2744 && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \
2747 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2749 register rtx xlow0 = XEXP (xinsn, 0); \
2750 register rtx xlow1 = XEXP (xinsn, 1); \
2752 if (GET_CODE (xlow0) == REG \
2753 && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \
2754 && mips_check_split (xlow1, MODE)) \
2758 if (GET_CODE (xinsn) == PLUS) \
2760 register rtx xplus0 = XEXP (xinsn, 0); \
2761 register rtx xplus1 = XEXP (xinsn, 1); \
2762 register enum rtx_code code0 = GET_CODE (xplus0); \
2763 register enum rtx_code code1 = GET_CODE (xplus1); \
2765 /* The mips16 can only use the stack pointer as a base register \
2766 when loading SImode or DImode values. */ \
2767 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \
2769 if (code1 == CONST_INT \
2770 && INTVAL (xplus1) >= -32768 \
2771 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2774 /* On the mips16, we represent GP relative offsets in RTL. \
2775 These are 16 bit signed values, and can serve as register \
2778 && mips16_gp_offset_p (xplus1)) \
2781 /* For some code sequences, you actually get better code by \
2782 pretending that the MIPS supports an address mode of a \
2783 constant address + a register, even though the real \
2784 machine doesn't support it. This is because the \
2785 assembler can use $r1 to load just the high 16 bits, add \
2786 in the register, and fold the low 16 bits into the memory \
2787 reference, whereas the compiler generates a 4 instruction \
2788 sequence. On the other hand, CSE is not as effective. \
2789 It would be a win to generate the lui directly, but the \
2790 MIPS assembler does not have syntax to generate the \
2791 appropriate relocation. */ \
2793 /* Also accept CONST_INT addresses here, so no else. */ \
2794 /* Reject combining an embedded PIC text segment reference \
2795 with a register. That requires an additional \
2797 /* ??? Reject combining an address with a register for the MIPS \
2798 64 bit ABI, because the SGI assembler can not handle this. */ \
2799 if (!TARGET_DEBUG_A_MODE \
2800 && (mips_abi == ABI_32 || mips_abi == ABI_EABI) \
2801 && CONSTANT_ADDRESS_P (xplus1) \
2802 && ! mips_split_addresses \
2803 && (!TARGET_EMBEDDED_PIC \
2805 || GET_CODE (XEXP (xplus1, 0)) != MINUS) \
2806 && !TARGET_MIPS16) \
2811 if (TARGET_DEBUG_B_MODE) \
2812 GO_PRINTF ("Not a legitimate address\n"); \
2816 /* A C expression that is 1 if the RTX X is a constant which is a
2817 valid address. This is defined to be the same as `CONSTANT_P (X)',
2818 but rejecting CONST_DOUBLE. */
2819 /* When pic, we must reject addresses of the form symbol+large int.
2820 This is because an instruction `sw $4,s+70000' needs to be converted
2821 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2822 assembler would use $at as a temp to load in the large offset. In this
2823 case $at is already in use. We convert such problem addresses to
2824 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2825 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2826 #define CONSTANT_ADDRESS_P(X) \
2827 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2828 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2829 || (GET_CODE (X) == CONST \
2830 && ! (flag_pic && pic_address_needs_scratch (X)) \
2831 && (mips_abi == ABI_32 || mips_abi == ABI_EABI))) \
2832 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2834 /* Define this, so that when PIC, reload won't try to reload invalid
2835 addresses which require two reload registers. */
2837 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2839 /* Nonzero if the constant value X is a legitimate general operand.
2840 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2842 At present, GAS doesn't understand li.[sd], so don't allow it
2843 to be generated at present. Also, the MIPS assembler does not
2844 grok li.d Infinity. */
2846 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2847 #define LEGITIMATE_CONSTANT_P(X) \
2848 ((GET_CODE (X) != CONST_DOUBLE \
2849 || mips_const_double_ok (X, GET_MODE (X))) \
2850 && ! (GET_CODE (X) == CONST \
2851 && mips_abi != ABI_32 && mips_abi != ABI_EABI) \
2852 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2854 /* A C compound statement that attempts to replace X with a valid
2855 memory address for an operand of mode MODE. WIN will be a C
2856 statement label elsewhere in the code; the macro definition may
2859 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2861 to avoid further processing if the address has become legitimate.
2863 X will always be the result of a call to `break_out_memory_refs',
2864 and OLDX will be the operand that was given to that function to
2867 The code generated by this macro should not alter the
2868 substructure of X. If it transforms X into a more legitimate
2869 form, it should assign X (which will always be a C variable) a
2872 It is not necessary for this macro to come up with a legitimate
2873 address. The compiler has standard ways of doing so in all
2874 cases. In fact, it is safe for this macro to do nothing. But
2875 often a machine-dependent strategy can generate better code.
2877 For the MIPS, transform:
2879 memory(X + <large int>)
2883 Y = <large int> & ~0x7fff;
2885 memory (Z + (<large int> & 0x7fff));
2887 This is for CSE to find several similar references, and only use one Z.
2889 When PIC, convert addresses of the form memory (symbol+large int) to
2890 memory (reg+large int). */
2893 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2895 register rtx xinsn = (X); \
2897 if (TARGET_DEBUG_B_MODE) \
2899 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2900 GO_DEBUG_RTX (xinsn); \
2903 if (mips_split_addresses && mips_check_split (X, MODE)) \
2905 /* ??? Is this ever executed? */ \
2906 X = gen_rtx (LO_SUM, Pmode, \
2907 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2911 if (GET_CODE (xinsn) == CONST \
2912 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2913 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2914 || (mips_abi != ABI_32 && mips_abi != ABI_EABI))) \
2916 rtx ptr_reg = gen_reg_rtx (Pmode); \
2917 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2919 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2921 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2922 if (SMALL_INT (constant)) \
2924 /* Otherwise we fall through so the code below will fix the \
2929 if (GET_CODE (xinsn) == PLUS) \
2931 register rtx xplus0 = XEXP (xinsn, 0); \
2932 register rtx xplus1 = XEXP (xinsn, 1); \
2933 register enum rtx_code code0 = GET_CODE (xplus0); \
2934 register enum rtx_code code1 = GET_CODE (xplus1); \
2936 if (code0 != REG && code1 == REG) \
2938 xplus0 = XEXP (xinsn, 1); \
2939 xplus1 = XEXP (xinsn, 0); \
2940 code0 = GET_CODE (xplus0); \
2941 code1 = GET_CODE (xplus1); \
2944 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
2945 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
2947 rtx int_reg = gen_reg_rtx (Pmode); \
2948 rtx ptr_reg = gen_reg_rtx (Pmode); \
2950 emit_move_insn (int_reg, \
2951 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
2953 emit_insn (gen_rtx (SET, VOIDmode, \
2955 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
2957 X = gen_rtx (PLUS, Pmode, ptr_reg, \
2958 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
2963 if (TARGET_DEBUG_B_MODE) \
2964 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
2968 /* A C statement or compound statement with a conditional `goto
2969 LABEL;' executed if memory address X (an RTX) can have different
2970 meanings depending on the machine mode of the memory reference it
2973 Autoincrement and autodecrement addresses typically have
2974 mode-dependent effects because the amount of the increment or
2975 decrement is the size of the operand being addressed. Some
2976 machines have other mode-dependent addresses. Many RISC machines
2977 have no mode-dependent addresses.
2979 You may assume that ADDR is a valid address for the machine. */
2981 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2984 /* Define this macro if references to a symbol must be treated
2985 differently depending on something about the variable or
2986 function named by the symbol (such as what section it is in).
2988 The macro definition, if any, is executed immediately after the
2989 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
2990 The value of the rtl will be a `mem' whose address is a
2993 The usual thing for this macro to do is to a flag in the
2994 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
2995 name string in the `symbol_ref' (if one bit is not enough
2998 The best way to modify the name string is by adding text to the
2999 beginning, with suitable punctuation to prevent any ambiguity.
3000 Allocate the new name in `saveable_obstack'. You will have to
3001 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3002 and output the name accordingly.
3004 You can also check the information stored in the `symbol_ref' in
3005 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3006 `PRINT_OPERAND_ADDRESS'.
3008 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3011 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3012 symbols which are not in the .text section.
3014 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3015 constants which are put in the .text section. We also record the
3016 total length of all such strings; this total is used to decide
3017 whether we need to split the constant table, and need not be
3018 precisely correct. */
3020 #define ENCODE_SECTION_INFO(DECL) \
3023 if (TARGET_MIPS16) \
3025 if (TREE_CODE (DECL) == STRING_CST \
3026 && ! flag_writable_strings) \
3028 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3029 mips_string_length += TREE_STRING_LENGTH (DECL); \
3032 if (TARGET_EMBEDDED_PIC) \
3034 if (TREE_CODE (DECL) == VAR_DECL) \
3035 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3036 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3037 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3038 else if (TREE_CODE (DECL) == STRING_CST \
3039 && ! flag_writable_strings) \
3040 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3042 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3045 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
3047 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3049 if (size > 0 && size <= mips_section_threshold) \
3050 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3053 else if (HALF_PIC_P ()) \
3055 HALF_PIC_ENCODE (DECL); \
3060 /* The mips16 wants the constant pool to be after the function,
3061 because the PC relative load instructions use unsigned offsets. */
3063 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3065 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3066 mips_string_length = 0;
3069 /* In mips16 mode, put most string constants after the function. */
3070 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3071 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3074 /* Specify the machine mode that this machine uses
3075 for the index in the tablejump instruction.
3076 ??? Using HImode in mips16 mode can cause overflow. However, the
3077 overflow is no more likely than the overflow in a branch
3078 instruction. Large functions can currently break in both ways. */
3079 #define CASE_VECTOR_MODE \
3080 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3082 /* Define as C expression which evaluates to nonzero if the tablejump
3083 instruction expects the table to contain offsets from the address of the
3085 Do not define this if the table should contain absolute addresses. */
3086 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3088 /* Specify the tree operation to be used to convert reals to integers. */
3089 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3091 /* This is the kind of divide that is easiest to do in the general case. */
3092 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3094 /* Define this as 1 if `char' should by default be signed; else as 0. */
3095 #ifndef DEFAULT_SIGNED_CHAR
3096 #define DEFAULT_SIGNED_CHAR 1
3099 /* Max number of bytes we can move from memory to memory
3100 in one reasonably fast instruction. */
3101 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3102 #define MAX_MOVE_MAX 8
3104 /* Define this macro as a C expression which is nonzero if
3105 accessing less than a word of memory (i.e. a `char' or a
3106 `short') is no faster than accessing a word of memory, i.e., if
3107 such access require more than one instruction or if there is no
3108 difference in cost between byte and (aligned) word loads.
3110 On RISC machines, it tends to generate better code to define
3111 this as 1, since it avoids making a QI or HI mode register. */
3112 #define SLOW_BYTE_ACCESS 1
3114 /* We assume that the store-condition-codes instructions store 0 for false
3115 and some other value for true. This is the value stored for true. */
3117 #define STORE_FLAG_VALUE 1
3119 /* Define this if zero-extension is slow (more than one real instruction). */
3120 #define SLOW_ZERO_EXTEND
3122 /* Define this to be nonzero if shift instructions ignore all but the low-order
3124 #define SHIFT_COUNT_TRUNCATED 1
3126 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3127 is done just by pretending it is already truncated. */
3128 /* In 64 bit mode, 32 bit instructions require that register values be properly
3129 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3130 converts a value >32 bits to a value <32 bits. */
3131 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3132 Something needs to be done about this. Perhaps not use any 32 bit
3133 instructions? Perhaps use PROMOTE_MODE? */
3134 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3135 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3137 /* Specify the machine mode that pointers have.
3138 After generation of rtl, the compiler makes no further distinction
3139 between pointers and any other objects of this machine mode. */
3142 #define Pmode (TARGET_LONG64 ? DImode : SImode)
3145 /* A function address in a call instruction
3146 is a word address (for indexing purposes)
3147 so give the MEM rtx a words's mode. */
3149 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3151 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3152 memset, instead of the BSD functions bcopy and bzero. */
3154 #if defined(MIPS_SYSV) || defined(OSF_OS)
3155 #define TARGET_MEM_FUNCTIONS
3159 /* A part of a C `switch' statement that describes the relative
3160 costs of constant RTL expressions. It must contain `case'
3161 labels for expression codes `const_int', `const', `symbol_ref',
3162 `label_ref' and `const_double'. Each case must ultimately reach
3163 a `return' statement to return the relative cost of the use of
3164 that kind of constant value in an expression. The cost may
3165 depend on the precise value of the constant, which is available
3166 for examination in X.
3168 CODE is the expression code--redundant, since it can be obtained
3169 with `GET_CODE (X)'. */
3171 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3173 if (! TARGET_MIPS16) \
3175 /* Always return 0, since we don't have different sized \
3176 instructions, hence different costs according to Richard \
3180 if ((OUTER_CODE) == SET) \
3182 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3184 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3185 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3186 return COSTS_N_INSNS (1); \
3188 return COSTS_N_INSNS (2); \
3190 /* A PLUS could be an address. We don't want to force an address \
3191 to use a register, so accept any signed 16 bit value without \
3193 if ((OUTER_CODE) == PLUS \
3194 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3196 /* A number between 1 and 8 inclusive is efficient for a shift. \
3197 Otherwise, we will need an extended instruction. */ \
3198 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3199 || (OUTER_CODE) == LSHIFTRT) \
3201 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3203 return COSTS_N_INSNS (1); \
3205 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3206 if ((OUTER_CODE) == XOR \
3207 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3209 /* We may be able to use slt or sltu for a comparison with a \
3210 signed 16 bit value. (The boundary conditions aren't quite \
3211 right, but this is just a heuristic anyhow.) */ \
3212 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3213 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3214 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3215 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3216 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3218 /* Equality comparisons with 0 are cheap. */ \
3219 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3220 && INTVAL (X) == 0) \
3223 /* Otherwise, work out the cost to load the value into a \
3225 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3226 return COSTS_N_INSNS (1); \
3227 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3228 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3229 return COSTS_N_INSNS (2); \
3231 return COSTS_N_INSNS (3); \
3234 return COSTS_N_INSNS (2); \
3238 rtx offset = const0_rtx; \
3239 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3241 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3243 /* Treat this like a signed 16 bit CONST_INT. */ \
3244 if ((OUTER_CODE) == PLUS) \
3246 else if ((OUTER_CODE) == SET) \
3247 return COSTS_N_INSNS (1); \
3249 return COSTS_N_INSNS (2); \
3252 if (GET_CODE (symref) == LABEL_REF) \
3253 return COSTS_N_INSNS (2); \
3255 if (GET_CODE (symref) != SYMBOL_REF) \
3256 return COSTS_N_INSNS (4); \
3258 /* let's be paranoid.... */ \
3259 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3260 return COSTS_N_INSNS (2); \
3262 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3266 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3268 case CONST_DOUBLE: \
3271 if (TARGET_MIPS16) \
3272 return COSTS_N_INSNS (4); \
3273 split_double (X, &high, &low); \
3274 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3275 || low == CONST0_RTX (GET_MODE (low))) \
3279 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3280 This can be used, for example, to indicate how costly a multiply
3281 instruction is. In writing this macro, you can use the construct
3282 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3284 This macro is optional; do not define it if the default cost
3285 assumptions are adequate for the target machine.
3287 If -mdebugd is used, change the multiply cost to 2, so multiply by
3288 a constant isn't converted to a series of shifts. This helps
3289 strength reduction, and also makes it easier to identify what the
3290 compiler is doing. */
3292 /* ??? Fix this to be right for the R8000. */
3293 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3296 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3297 if (simple_memory_operand (X, GET_MODE (X))) \
3298 return COSTS_N_INSNS (num_words); \
3300 return COSTS_N_INSNS (2*num_words); \
3304 return COSTS_N_INSNS (6); \
3307 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3312 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3313 return COSTS_N_INSNS (2); \
3320 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3321 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3327 enum machine_mode xmode = GET_MODE (X); \
3328 if (xmode == SFmode || xmode == DFmode) \
3329 return COSTS_N_INSNS (1); \
3331 return COSTS_N_INSNS (4); \
3337 enum machine_mode xmode = GET_MODE (X); \
3338 if (xmode == SFmode || xmode == DFmode) \
3340 if (mips_cpu == PROCESSOR_R3000 \
3341 || mips_cpu == PROCESSOR_R3900) \
3342 return COSTS_N_INSNS (2); \
3343 else if (mips_cpu == PROCESSOR_R6000) \
3344 return COSTS_N_INSNS (3); \
3346 return COSTS_N_INSNS (6); \
3349 if (xmode == DImode && !TARGET_64BIT) \
3350 return COSTS_N_INSNS (4); \
3356 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3363 enum machine_mode xmode = GET_MODE (X); \
3364 if (xmode == SFmode) \
3366 if (mips_cpu == PROCESSOR_R3000 \
3367 || mips_cpu == PROCESSOR_R3900 \
3368 || mips_cpu == PROCESSOR_R5000) \
3369 return COSTS_N_INSNS (4); \
3370 else if (mips_cpu == PROCESSOR_R6000) \
3371 return COSTS_N_INSNS (5); \
3373 return COSTS_N_INSNS (7); \
3376 if (xmode == DFmode) \
3378 if (mips_cpu == PROCESSOR_R3000 \
3379 || mips_cpu == PROCESSOR_R3900 \
3380 || mips_cpu == PROCESSOR_R5000) \
3381 return COSTS_N_INSNS (5); \
3382 else if (mips_cpu == PROCESSOR_R6000) \
3383 return COSTS_N_INSNS (6); \
3385 return COSTS_N_INSNS (8); \
3388 if (mips_cpu == PROCESSOR_R3000) \
3389 return COSTS_N_INSNS (12); \
3390 else if (mips_cpu == PROCESSOR_R3900) \
3391 return COSTS_N_INSNS (2); \
3392 else if (mips_cpu == PROCESSOR_R6000) \
3393 return COSTS_N_INSNS (17); \
3394 else if (mips_cpu == PROCESSOR_R5000) \
3395 return COSTS_N_INSNS (5); \
3397 return COSTS_N_INSNS (10); \
3403 enum machine_mode xmode = GET_MODE (X); \
3404 if (xmode == SFmode) \
3406 if (mips_cpu == PROCESSOR_R3000 \
3407 || mips_cpu == PROCESSOR_R3900) \
3408 return COSTS_N_INSNS (12); \
3409 else if (mips_cpu == PROCESSOR_R6000) \
3410 return COSTS_N_INSNS (15); \
3412 return COSTS_N_INSNS (23); \
3415 if (xmode == DFmode) \
3417 if (mips_cpu == PROCESSOR_R3000 \
3418 || mips_cpu == PROCESSOR_R3900) \
3419 return COSTS_N_INSNS (19); \
3420 else if (mips_cpu == PROCESSOR_R6000) \
3421 return COSTS_N_INSNS (16); \
3423 return COSTS_N_INSNS (36); \
3426 /* fall through */ \
3430 if (mips_cpu == PROCESSOR_R3000 \
3431 || mips_cpu == PROCESSOR_R3900) \
3432 return COSTS_N_INSNS (35); \
3433 else if (mips_cpu == PROCESSOR_R6000) \
3434 return COSTS_N_INSNS (38); \
3435 else if (mips_cpu == PROCESSOR_R5000) \
3436 return COSTS_N_INSNS (36); \
3438 return COSTS_N_INSNS (69); \
3441 /* A sign extend from SImode to DImode in 64 bit mode is often \
3442 zero instructions, because the result can often be used \
3443 directly by another instruction; we'll call it one. */ \
3444 if (TARGET_64BIT && GET_MODE (X) == DImode \
3445 && GET_MODE (XEXP (X, 0)) == SImode) \
3446 return COSTS_N_INSNS (1); \
3448 return COSTS_N_INSNS (2); \
3451 if (TARGET_64BIT && GET_MODE (X) == DImode \
3452 && GET_MODE (XEXP (X, 0)) == SImode) \
3453 return COSTS_N_INSNS (2); \
3455 return COSTS_N_INSNS (1);
3457 /* An expression giving the cost of an addressing mode that
3458 contains ADDRESS. If not defined, the cost is computed from the
3459 form of the ADDRESS expression and the `CONST_COSTS' values.
3461 For most CISC machines, the default cost is a good approximation
3462 of the true cost of the addressing mode. However, on RISC
3463 machines, all instructions normally have the same length and
3464 execution time. Hence all addresses will have equal costs.
3466 In cases where more than one form of an address is known, the
3467 form with the lowest cost will be used. If multiple forms have
3468 the same, lowest, cost, the one that is the most complex will be
3471 For example, suppose an address that is equal to the sum of a
3472 register and a constant is used twice in the same basic block.
3473 When this macro is not defined, the address will be computed in
3474 a register and memory references will be indirect through that
3475 register. On machines where the cost of the addressing mode
3476 containing the sum is no higher than that of a simple indirect
3477 reference, this will produce an additional instruction and
3478 possibly require an additional register. Proper specification
3479 of this macro eliminates this overhead for such machines.
3481 Similar use of this macro is made in strength reduction of loops.
3483 ADDRESS need not be valid as an address. In such a case, the
3484 cost is not relevant and can be any value; invalid addresses
3485 need not be assigned a different cost.
3487 On machines where an address involving more than one register is
3488 as cheap as an address computation involving only one register,
3489 defining `ADDRESS_COST' to reflect this can cause two registers
3490 to be live over a region of code where only one would have been
3491 if `ADDRESS_COST' were not defined in that manner. This effect
3492 should be considered in the definition of this macro.
3493 Equivalent costs should probably only be given to addresses with
3494 different numbers of registers on machines with lots of registers.
3496 This macro will normally either not be defined or be defined as
3499 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3501 /* A C expression for the cost of moving data from a register in
3502 class FROM to one in class TO. The classes are expressed using
3503 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3504 the default; other values are interpreted relative to that.
3506 It is not required that the cost always equal 2 when FROM is the
3507 same as TO; on some machines it is expensive to move between
3508 registers if they are not general registers.
3510 If reload sees an insn consisting of a single `set' between two
3511 hard registers, and if `REGISTER_MOVE_COST' applied to their
3512 classes returns a value of 2, reload does not check to ensure
3513 that the constraints of the insn are met. Setting a cost of
3514 other than 2 will allow reload to verify that the constraints are
3515 met. You should do this if the `movM' pattern's constraints do
3516 not allow such copying. */
3518 #define REGISTER_MOVE_COST(FROM, TO) \
3519 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3520 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3521 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3522 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3523 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3524 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3525 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3526 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3527 : (((FROM) == HI_REG || (FROM) == LO_REG \
3528 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3529 && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6 \
3530 : (((FROM) == HI_REG || (FROM) == LO_REG \
3531 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3532 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 8 : 6) \
3533 : (((TO) == HI_REG || (TO) == LO_REG \
3534 || (TO) == MD_REGS || (TO) == HILO_REG) \
3535 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3536 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3537 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3540 /* ??? Fix this to be right for the R8000. */
3541 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3542 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3543 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3545 /* A C expression for the cost of a branch instruction. A value of
3546 1 is the default; other values are interpreted relative to that. */
3548 /* ??? Fix this to be right for the R8000. */
3549 #define BRANCH_COST \
3551 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3554 /* A C statement (sans semicolon) to update the integer variable COST
3555 based on the relationship between INSN that is dependent on
3556 DEP_INSN through the dependence LINK. The default is to make no
3557 adjustment to COST. On the MIPS, ignore the cost of anti- and
3558 output-dependencies. */
3560 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3561 if (REG_NOTE_KIND (LINK) != 0) \
3562 (COST) = 0; /* Anti or output dependence. */
3564 /* Optionally define this if you have added predicates to
3565 `MACHINE.c'. This macro is called within an initializer of an
3566 array of structures. The first field in the structure is the
3567 name of a predicate and the second field is an array of rtl
3568 codes. For each predicate, list all rtl codes that can be in
3569 expressions matched by the predicate. The list should have a
3570 trailing comma. Here is an example of two entries in the list
3571 for a typical RISC machine:
3573 #define PREDICATE_CODES \
3574 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3575 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3577 Defining this macro does not affect the generated code (however,
3578 incorrect definitions that omit an rtl code that may be matched
3579 by the predicate can cause the compiler to malfunction).
3580 Instead, it allows the table built by `genrecog' to be more
3581 compact and efficient, thus speeding up the compiler. The most
3582 important predicates to include in the list specified by this
3583 macro are thoses used in the most insn patterns. */
3585 #define PREDICATE_CODES \
3586 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3587 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3588 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3589 {"reg_or_0_operand", { REG, CONST_INT, SUBREG }}, \
3590 {"small_int", { CONST_INT }}, \
3591 {"large_int", { CONST_INT }}, \
3592 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3593 {"const_float_1_operand", { CONST_DOUBLE }}, \
3594 {"simple_memory_operand", { MEM, SUBREG }}, \
3595 {"equality_op", { EQ, NE }}, \
3596 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3598 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3599 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3600 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3601 SYMBOL_REF, LABEL_REF, SUBREG, \
3603 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3604 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3605 MEM, SIGN_EXTEND }}, \
3606 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3607 {"se_reg_or_0_operand", { REG, CONST_INT, SUBREG, \
3609 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3611 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3613 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3614 SYMBOL_REF, LABEL_REF, SUBREG, \
3615 REG, SIGN_EXTEND }}, \
3616 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3617 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3618 CONST_DOUBLE, CONST }},
3621 /* If defined, a C statement to be executed just prior to the
3622 output of assembler code for INSN, to modify the extracted
3623 operands so they will be output differently.
3625 Here the argument OPVEC is the vector containing the operands
3626 extracted from INSN, and NOPERANDS is the number of elements of
3627 the vector which contain meaningful data for this insn. The
3628 contents of this vector are what will be used to convert the
3629 insn template into assembler code, so you can change the
3630 assembler output by changing the contents of the vector.
3632 We use it to check if the current insn needs a nop in front of it
3633 because of load delays, and also to update the delay slot
3636 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3637 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3640 /* Control the assembler format that we output. */
3642 /* Output at beginning of assembler file.
3643 If we are optimizing to use the global pointer, create a temporary
3644 file to hold all of the text stuff, and write it out to the end.
3645 This is needed because the MIPS assembler is evidently one pass,
3646 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3647 declaration when the code is processed, it generates a two
3648 instruction sequence. */
3650 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3652 /* Output to assembler file text saying following lines
3653 may contain character constants, extra white space, comments, etc. */
3655 #define ASM_APP_ON " #APP\n"
3657 /* Output to assembler file text saying following lines
3658 no longer contain unusual constructs. */
3660 #define ASM_APP_OFF " #NO_APP\n"
3662 /* How to refer to registers in assembler output.
3663 This sequence is indexed by compiler's hard-register-number (see above).
3665 In order to support the two different conventions for register names,
3666 we use the name of a table set up in mips.c, which is overwritten
3667 if -mrnames is used. */
3669 #define REGISTER_NAMES \
3671 &mips_reg_names[ 0][0], \
3672 &mips_reg_names[ 1][0], \
3673 &mips_reg_names[ 2][0], \
3674 &mips_reg_names[ 3][0], \
3675 &mips_reg_names[ 4][0], \
3676 &mips_reg_names[ 5][0], \
3677 &mips_reg_names[ 6][0], \
3678 &mips_reg_names[ 7][0], \
3679 &mips_reg_names[ 8][0], \
3680 &mips_reg_names[ 9][0], \
3681 &mips_reg_names[10][0], \
3682 &mips_reg_names[11][0], \
3683 &mips_reg_names[12][0], \
3684 &mips_reg_names[13][0], \
3685 &mips_reg_names[14][0], \
3686 &mips_reg_names[15][0], \
3687 &mips_reg_names[16][0], \
3688 &mips_reg_names[17][0], \
3689 &mips_reg_names[18][0], \
3690 &mips_reg_names[19][0], \
3691 &mips_reg_names[20][0], \
3692 &mips_reg_names[21][0], \
3693 &mips_reg_names[22][0], \
3694 &mips_reg_names[23][0], \
3695 &mips_reg_names[24][0], \
3696 &mips_reg_names[25][0], \
3697 &mips_reg_names[26][0], \
3698 &mips_reg_names[27][0], \
3699 &mips_reg_names[28][0], \
3700 &mips_reg_names[29][0], \
3701 &mips_reg_names[30][0], \
3702 &mips_reg_names[31][0], \
3703 &mips_reg_names[32][0], \
3704 &mips_reg_names[33][0], \
3705 &mips_reg_names[34][0], \
3706 &mips_reg_names[35][0], \
3707 &mips_reg_names[36][0], \
3708 &mips_reg_names[37][0], \
3709 &mips_reg_names[38][0], \
3710 &mips_reg_names[39][0], \
3711 &mips_reg_names[40][0], \
3712 &mips_reg_names[41][0], \
3713 &mips_reg_names[42][0], \
3714 &mips_reg_names[43][0], \
3715 &mips_reg_names[44][0], \
3716 &mips_reg_names[45][0], \
3717 &mips_reg_names[46][0], \
3718 &mips_reg_names[47][0], \
3719 &mips_reg_names[48][0], \
3720 &mips_reg_names[49][0], \
3721 &mips_reg_names[50][0], \
3722 &mips_reg_names[51][0], \
3723 &mips_reg_names[52][0], \
3724 &mips_reg_names[53][0], \
3725 &mips_reg_names[54][0], \
3726 &mips_reg_names[55][0], \
3727 &mips_reg_names[56][0], \
3728 &mips_reg_names[57][0], \
3729 &mips_reg_names[58][0], \
3730 &mips_reg_names[59][0], \
3731 &mips_reg_names[60][0], \
3732 &mips_reg_names[61][0], \
3733 &mips_reg_names[62][0], \
3734 &mips_reg_names[63][0], \
3735 &mips_reg_names[64][0], \
3736 &mips_reg_names[65][0], \
3737 &mips_reg_names[66][0], \
3738 &mips_reg_names[67][0], \
3739 &mips_reg_names[68][0], \
3740 &mips_reg_names[69][0], \
3741 &mips_reg_names[70][0], \
3742 &mips_reg_names[71][0], \
3743 &mips_reg_names[72][0], \
3744 &mips_reg_names[73][0], \
3745 &mips_reg_names[74][0], \
3746 &mips_reg_names[75][0], \
3749 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3750 So define this for it. */
3751 #define DEBUG_REGISTER_NAMES \
3753 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3754 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3755 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3756 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3757 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3758 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3759 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3760 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3761 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3762 "$fcc5","$fcc6","$fcc7","$rap" \
3765 /* If defined, a C initializer for an array of structures
3766 containing a name and a register number. This macro defines
3767 additional names for hard registers, thus allowing the `asm'
3768 option in declarations to refer to registers using alternate
3771 We define both names for the integer registers here. */
3773 #define ADDITIONAL_REGISTER_NAMES \
3775 { "$0", 0 + GP_REG_FIRST }, \
3776 { "$1", 1 + GP_REG_FIRST }, \
3777 { "$2", 2 + GP_REG_FIRST }, \
3778 { "$3", 3 + GP_REG_FIRST }, \
3779 { "$4", 4 + GP_REG_FIRST }, \
3780 { "$5", 5 + GP_REG_FIRST }, \
3781 { "$6", 6 + GP_REG_FIRST }, \
3782 { "$7", 7 + GP_REG_FIRST }, \
3783 { "$8", 8 + GP_REG_FIRST }, \
3784 { "$9", 9 + GP_REG_FIRST }, \
3785 { "$10", 10 + GP_REG_FIRST }, \
3786 { "$11", 11 + GP_REG_FIRST }, \
3787 { "$12", 12 + GP_REG_FIRST }, \
3788 { "$13", 13 + GP_REG_FIRST }, \
3789 { "$14", 14 + GP_REG_FIRST }, \
3790 { "$15", 15 + GP_REG_FIRST }, \
3791 { "$16", 16 + GP_REG_FIRST }, \
3792 { "$17", 17 + GP_REG_FIRST }, \
3793 { "$18", 18 + GP_REG_FIRST }, \
3794 { "$19", 19 + GP_REG_FIRST }, \
3795 { "$20", 20 + GP_REG_FIRST }, \
3796 { "$21", 21 + GP_REG_FIRST }, \
3797 { "$22", 22 + GP_REG_FIRST }, \
3798 { "$23", 23 + GP_REG_FIRST }, \
3799 { "$24", 24 + GP_REG_FIRST }, \
3800 { "$25", 25 + GP_REG_FIRST }, \
3801 { "$26", 26 + GP_REG_FIRST }, \
3802 { "$27", 27 + GP_REG_FIRST }, \
3803 { "$28", 28 + GP_REG_FIRST }, \
3804 { "$29", 29 + GP_REG_FIRST }, \
3805 { "$30", 30 + GP_REG_FIRST }, \
3806 { "$31", 31 + GP_REG_FIRST }, \
3807 { "$sp", 29 + GP_REG_FIRST }, \
3808 { "$fp", 30 + GP_REG_FIRST }, \
3809 { "at", 1 + GP_REG_FIRST }, \
3810 { "v0", 2 + GP_REG_FIRST }, \
3811 { "v1", 3 + GP_REG_FIRST }, \
3812 { "a0", 4 + GP_REG_FIRST }, \
3813 { "a1", 5 + GP_REG_FIRST }, \
3814 { "a2", 6 + GP_REG_FIRST }, \
3815 { "a3", 7 + GP_REG_FIRST }, \
3816 { "t0", 8 + GP_REG_FIRST }, \
3817 { "t1", 9 + GP_REG_FIRST }, \
3818 { "t2", 10 + GP_REG_FIRST }, \
3819 { "t3", 11 + GP_REG_FIRST }, \
3820 { "t4", 12 + GP_REG_FIRST }, \
3821 { "t5", 13 + GP_REG_FIRST }, \
3822 { "t6", 14 + GP_REG_FIRST }, \
3823 { "t7", 15 + GP_REG_FIRST }, \
3824 { "s0", 16 + GP_REG_FIRST }, \
3825 { "s1", 17 + GP_REG_FIRST }, \
3826 { "s2", 18 + GP_REG_FIRST }, \
3827 { "s3", 19 + GP_REG_FIRST }, \
3828 { "s4", 20 + GP_REG_FIRST }, \
3829 { "s5", 21 + GP_REG_FIRST }, \
3830 { "s6", 22 + GP_REG_FIRST }, \
3831 { "s7", 23 + GP_REG_FIRST }, \
3832 { "t8", 24 + GP_REG_FIRST }, \
3833 { "t9", 25 + GP_REG_FIRST }, \
3834 { "k0", 26 + GP_REG_FIRST }, \
3835 { "k1", 27 + GP_REG_FIRST }, \
3836 { "gp", 28 + GP_REG_FIRST }, \
3837 { "sp", 29 + GP_REG_FIRST }, \
3838 { "fp", 30 + GP_REG_FIRST }, \
3839 { "ra", 31 + GP_REG_FIRST }, \
3840 { "$sp", 29 + GP_REG_FIRST }, \
3841 { "$fp", 30 + GP_REG_FIRST } \
3844 /* Define results of standard character escape sequences. */
3845 #define TARGET_BELL 007
3846 #define TARGET_BS 010
3847 #define TARGET_TAB 011
3848 #define TARGET_NEWLINE 012
3849 #define TARGET_VT 013
3850 #define TARGET_FF 014
3851 #define TARGET_CR 015
3853 /* A C compound statement to output to stdio stream STREAM the
3854 assembler syntax for an instruction operand X. X is an RTL
3857 CODE is a value that can be used to specify one of several ways
3858 of printing the operand. It is used when identical operands
3859 must be printed differently depending on the context. CODE
3860 comes from the `%' specification that was used to request
3861 printing of the operand. If the specification was just `%DIGIT'
3862 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3863 is the ASCII code for LTR.
3865 If X is a register, this macro should print the register's name.
3866 The names can be found in an array `reg_names' whose type is
3867 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3869 When the machine description has a specification `%PUNCT' (a `%'
3870 followed by a punctuation character), this macro is called with
3871 a null pointer for X and the punctuation character for CODE.
3873 See mips.c for the MIPS specific codes. */
3875 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3877 /* A C expression which evaluates to true if CODE is a valid
3878 punctuation character for use in the `PRINT_OPERAND' macro. If
3879 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3880 punctuation characters (except for the standard one, `%') are
3881 used in this way. */
3883 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3885 /* A C compound statement to output to stdio stream STREAM the
3886 assembler syntax for an instruction operand that is a memory
3887 reference whose address is ADDR. ADDR is an RTL expression.
3889 On some machines, the syntax for a symbolic address depends on
3890 the section that the address refers to. On these machines,
3891 define the macro `ENCODE_SECTION_INFO' to store the information
3892 into the `symbol_ref', and then check for it here. */
3894 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3897 /* A C statement, to be executed after all slot-filler instructions
3898 have been output. If necessary, call `dbr_sequence_length' to
3899 determine the number of slots filled in a sequence (zero if not
3900 currently outputting a sequence), to decide how many no-ops to
3901 output, or whatever.
3903 Don't define this macro if it has nothing to do, but it is
3904 helpful in reading assembly output if the extent of the delay
3905 sequence is made explicit (e.g. with white space).
3907 Note that output routines for instructions with delay slots must
3908 be prepared to deal with not being output as part of a sequence
3909 (i.e. when the scheduling pass is not run, or when no slot
3910 fillers could be found.) The variable `final_sequence' is null
3911 when not processing a sequence, otherwise it contains the
3912 `sequence' rtx being output. */
3914 #define DBR_OUTPUT_SEQEND(STREAM) \
3917 if (set_nomacro > 0 && --set_nomacro == 0) \
3918 fputs ("\t.set\tmacro\n", STREAM); \
3920 if (set_noreorder > 0 && --set_noreorder == 0) \
3921 fputs ("\t.set\treorder\n", STREAM); \
3923 dslots_jump_filled++; \
3924 fputs ("\n", STREAM); \
3929 /* How to tell the debugger about changes of source files. Note, the
3930 mips ECOFF format cannot deal with changes of files inside of
3931 functions, which means the output of parser generators like bison
3932 is generally not debuggable without using the -l switch. Lose,
3933 lose, lose. Silicon graphics seems to want all .file's hardwired
3936 #ifndef SET_FILE_NUMBER
3937 #define SET_FILE_NUMBER() ++num_source_filenames
3940 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3941 mips_output_filename (STREAM, NAME)
3943 /* This is defined so that it can be overridden in iris6.h. */
3944 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3947 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3948 output_quoted_string (STREAM, NAME); \
3949 fputs ("\n", STREAM); \
3953 /* This is how to output a note the debugger telling it the line number
3954 to which the following sequence of instructions corresponds.
3955 Silicon graphics puts a label after each .loc. */
3957 #ifndef LABEL_AFTER_LOC
3958 #define LABEL_AFTER_LOC(STREAM)
3961 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
3962 mips_output_lineno (STREAM, LINE)
3964 /* The MIPS implementation uses some labels for it's own purpose. The
3965 following lists what labels are created, and are all formed by the
3966 pattern $L[a-z].*. The machine independent portion of GCC creates
3967 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3969 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3970 $Lb[0-9]+ Begin blocks for MIPS debug support
3971 $Lc[0-9]+ Label for use in s<xx> operation.
3972 $Le[0-9]+ End blocks for MIPS debug support
3973 $Lp\..+ Half-pic labels. */
3975 /* This is how to output the definition of a user-level label named NAME,
3976 such as the label on a static function or variable NAME.
3978 If we are optimizing the gp, remember that this label has been put
3979 out, so we know not to emit an .extern for it in mips_asm_file_end.
3980 We use one of the common bits in the IDENTIFIER tree node for this,
3981 since those bits seem to be unused, and we don't have any method
3982 of getting the decl nodes from the name. */
3984 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
3986 assemble_name (STREAM, NAME); \
3987 fputs (":\n", STREAM); \
3991 /* A C statement (sans semicolon) to output to the stdio stream
3992 STREAM any text necessary for declaring the name NAME of an
3993 initialized variable which is being defined. This macro must
3994 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
3995 The argument DECL is the `VAR_DECL' tree node representing the
3998 If this macro is not defined, then the variable name is defined
3999 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4001 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4004 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4005 HALF_PIC_DECLARE (NAME); \
4010 /* This is how to output a command to make the user-level label named NAME
4011 defined for reference from other files. */
4013 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4015 fputs ("\t.globl\t", STREAM); \
4016 assemble_name (STREAM, NAME); \
4017 fputs ("\n", STREAM); \
4020 /* This says how to define a global common symbol. */
4022 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
4023 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
4025 /* This says how to define a local common symbol (ie, not visible to
4028 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4029 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4032 /* This says how to output an external. It would be possible not to
4033 output anything and let undefined symbol become external. However
4034 the assembler uses length information on externals to allocate in
4035 data/sdata bss/sbss, thereby saving exec time. */
4037 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4038 mips_output_external(STREAM,DECL,NAME)
4040 /* This says what to print at the end of the assembly file */
4041 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4044 /* This is how to declare a function name. The actual work of
4045 emitting the label is moved to function_prologue, so that we can
4046 get the line number correctly emitted before the .ent directive,
4047 and after any .file directives.
4049 Also, switch files if we are optimizing the global pointer. */
4051 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4053 extern FILE *asm_out_text_file; \
4054 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4056 STREAM = asm_out_text_file; \
4057 /* ??? text_section gets called too soon. If the previous \
4058 function is in a special section and we're not, we have \
4059 to switch back to the text section. We can't call \
4060 text_section again as gcc thinks we're already there. */ \
4061 /* ??? See varasm.c. There are other things that get output \
4062 too early, like alignment (before we've switched STREAM). */ \
4063 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4064 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4067 HALF_PIC_DECLARE (NAME); \
4070 /* This is how to output an internal numbered label where
4071 PREFIX is the class of label and NUM is the number within the class. */
4073 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4074 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4076 /* This is how to store into the string LABEL
4077 the symbol_ref name of an internal numbered label where
4078 PREFIX is the class of label and NUM is the number within the class.
4079 This is suitable for output with `assemble_name'. */
4081 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4082 sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4084 /* This is how to output an assembler line defining a `double' constant. */
4086 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4087 mips_output_double (STREAM, VALUE)
4090 /* This is how to output an assembler line defining a `float' constant. */
4092 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4093 mips_output_float (STREAM, VALUE)
4096 /* This is how to output an assembler line defining an `int' constant. */
4098 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4100 fprintf (STREAM, "\t.word\t"); \
4101 output_addr_const (STREAM, (VALUE)); \
4102 fprintf (STREAM, "\n"); \
4105 /* Likewise for 64 bit, `char' and `short' constants. */
4107 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4111 fprintf (STREAM, "\t.dword\t"); \
4112 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4113 /* We can't use 'X' for negative numbers, because then we won't \
4114 get the right value for the upper 32 bits. */ \
4115 output_addr_const (STREAM, VALUE); \
4117 /* We must use 'X', because otherwise LONG_MIN will print as \
4118 a number that the Irix 6 assembler won't accept. */ \
4119 print_operand (STREAM, VALUE, 'X'); \
4120 fprintf (STREAM, "\n"); \
4124 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4125 UNITS_PER_WORD, 1); \
4126 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4127 UNITS_PER_WORD, 1); \
4131 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4133 fprintf (STREAM, "\t.half\t"); \
4134 output_addr_const (STREAM, (VALUE)); \
4135 fprintf (STREAM, "\n"); \
4138 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4140 fprintf (STREAM, "\t.byte\t"); \
4141 output_addr_const (STREAM, (VALUE)); \
4142 fprintf (STREAM, "\n"); \
4145 /* This is how to output an assembler line for a numeric constant byte. */
4147 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4148 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4150 /* This is how to output an element of a case-vector that is absolute. */
4152 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4153 fprintf (STREAM, "\t%s\t%sL%d\n", \
4154 Pmode == DImode ? ".dword" : ".word", \
4155 LOCAL_LABEL_PREFIX, \
4158 /* This is how to output an element of a case-vector that is relative.
4159 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4160 TARGET_EMBEDDED_PIC). */
4162 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4164 if (TARGET_MIPS16) \
4165 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4166 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4167 else if (TARGET_EMBEDDED_PIC) \
4168 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4169 Pmode == DImode ? ".dword" : ".word", \
4170 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4171 else if (mips_abi == ABI_32) \
4172 fprintf (STREAM, "\t%s\t%sL%d\n", \
4173 Pmode == DImode ? ".gpdword" : ".gpword", \
4174 LOCAL_LABEL_PREFIX, VALUE); \
4176 fprintf (STREAM, "\t%s\t%sL%d\n", \
4177 Pmode == DImode ? ".dword" : ".word", \
4178 LOCAL_LABEL_PREFIX, VALUE); \
4181 /* When generating embedded PIC or mips16 code we want to put the jump
4182 table in the .text section. In all other cases, we want to put the
4183 jump table in the .rdata section. Unfortunately, we can't use
4184 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4185 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4186 section if appropriate. */
4187 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4189 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4190 function_section (current_function_decl); \
4191 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4194 /* This is how to output an assembler line
4195 that says to advance the location counter
4196 to a multiple of 2**LOG bytes. */
4198 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4199 fprintf (STREAM, "\t.align\t%d\n", (LOG));
4201 /* This is how to output an assembler line to to advance the location
4202 counter by SIZE bytes. */
4204 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4205 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4207 /* This is how to output a string. */
4208 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4210 register int i, c, len = (LEN), cur_pos = 17; \
4211 register unsigned char *string = (unsigned char *)(STRING); \
4212 fprintf ((STREAM), "\t.ascii\t\""); \
4213 for (i = 0; i < len; i++) \
4215 register int c = string[i]; \
4221 putc ('\\', (STREAM)); \
4222 putc (c, (STREAM)); \
4226 case TARGET_NEWLINE: \
4227 fputs ("\\n", (STREAM)); \
4229 && (((c = string[i+1]) >= '\040' && c <= '~') \
4230 || c == TARGET_TAB)) \
4231 cur_pos = 32767; /* break right here */ \
4237 fputs ("\\t", (STREAM)); \
4242 fputs ("\\f", (STREAM)); \
4247 fputs ("\\b", (STREAM)); \
4252 fputs ("\\r", (STREAM)); \
4257 if (c >= ' ' && c < 0177) \
4259 putc (c, (STREAM)); \
4264 fprintf ((STREAM), "\\%03o", c); \
4269 if (cur_pos > 72 && i+1 < len) \
4272 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4275 fprintf ((STREAM), "\"\n"); \
4278 /* Handle certain cpp directives used in header files on sysV. */
4279 #define SCCS_DIRECTIVE
4281 /* Output #ident as a in the read-only data section. */
4282 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4285 int size = strlen (p) + 1; \
4287 assemble_string (p, size); \
4290 /* Default to -G 8 */
4291 #ifndef MIPS_DEFAULT_GVALUE
4292 #define MIPS_DEFAULT_GVALUE 8
4295 /* Define the strings to put out for each section in the object file. */
4296 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4297 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4298 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4299 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4300 #define READONLY_DATA_SECTION rdata_section
4301 #define SMALL_DATA_SECTION sdata_section
4303 /* What other sections we support other than the normal .data/.text. */
4305 #define EXTRA_SECTIONS in_sdata, in_rdata
4307 /* Define the additional functions to select our additional sections. */
4309 /* on the MIPS it is not a good idea to put constants in the text
4310 section, since this defeats the sdata/data mechanism. This is
4311 especially true when -O is used. In this case an effort is made to
4312 address with faster (gp) register relative addressing, which can
4313 only get at sdata and sbss items (there is no stext !!) However,
4314 if the constant is too large for sdata, and it's readonly, it
4315 will go into the .rdata section. */
4317 #define EXTRA_SECTION_FUNCTIONS \
4321 if (in_section != in_sdata) \
4323 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4324 in_section = in_sdata; \
4331 if (in_section != in_rdata) \
4333 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4334 in_section = in_rdata; \
4338 /* Given a decl node or constant node, choose the section to output it in
4339 and select that section. */
4341 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4343 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4346 /* Store in OUTPUT a string (made with alloca) containing
4347 an assembler-name for a local static variable named NAME.
4348 LABELNO is an integer which is different for each call. */
4350 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4351 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4352 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4354 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4357 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4358 TARGET_64BIT ? "dsubu" : "subu", \
4359 reg_names[STACK_POINTER_REGNUM], \
4360 reg_names[STACK_POINTER_REGNUM], \
4361 TARGET_64BIT ? "sd" : "sw", \
4363 reg_names[STACK_POINTER_REGNUM]); \
4367 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4370 if (! set_noreorder) \
4371 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4373 dslots_load_total++; \
4374 dslots_load_filled++; \
4375 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4376 TARGET_64BIT ? "ld" : "lw", \
4378 reg_names[STACK_POINTER_REGNUM], \
4379 TARGET_64BIT ? "daddu" : "addu", \
4380 reg_names[STACK_POINTER_REGNUM], \
4381 reg_names[STACK_POINTER_REGNUM]); \
4383 if (! set_noreorder) \
4384 fprintf (STREAM, "\t.set\treorder\n"); \
4388 /* Define the parentheses used to group arithmetic operations
4389 in assembler code. */
4391 #define ASM_OPEN_PAREN "("
4392 #define ASM_CLOSE_PAREN ")"
4394 /* How to start an assembler comment.
4395 The leading space is important (the mips native assembler requires it). */
4396 #ifndef ASM_COMMENT_START
4397 #define ASM_COMMENT_START " #"
4401 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4402 and mips-tdump.c to print them out.
4404 These must match the corresponding definitions in gdb/mipsread.c.
4405 Unfortunately, gcc and gdb do not currently share any directories. */
4407 #define CODE_MASK 0x8F300
4408 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4409 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4410 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4413 /* Default definitions for size_t and ptrdiff_t. */
4416 #define NO_BUILTIN_SIZE_TYPE
4417 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4420 #ifndef PTRDIFF_TYPE
4421 #define NO_BUILTIN_PTRDIFF_TYPE
4422 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4425 /* See mips_expand_prologue's use of loadgp for when this should be
4428 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && mips_abi != ABI_32)
4430 /* In mips16 mode, we need to look through the function to check for
4431 PC relative loads that are out of range. */
4432 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4434 /* We need to use a special set of functions to handle hard floating
4435 point code in mips16 mode. */
4437 #ifndef INIT_SUBTARGET_OPTABS
4438 #define INIT_SUBTARGET_OPTABS
4441 #define INIT_TARGET_OPTABS \
4444 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4445 INIT_SUBTARGET_OPTABS; \
4448 add_optab->handlers[(int) SFmode].libfunc = \
4449 gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3"); \
4450 sub_optab->handlers[(int) SFmode].libfunc = \
4451 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3"); \
4452 smul_optab->handlers[(int) SFmode].libfunc = \
4453 gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3"); \
4454 flodiv_optab->handlers[(int) SFmode].libfunc = \
4455 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3"); \
4457 eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2"); \
4458 nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2"); \
4459 gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2"); \
4460 gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2"); \
4461 ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2"); \
4462 lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2"); \
4464 floatsisf_libfunc = \
4465 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf"); \
4467 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi"); \
4469 if (TARGET_DOUBLE_FLOAT) \
4471 add_optab->handlers[(int) DFmode].libfunc = \
4472 gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3"); \
4473 sub_optab->handlers[(int) DFmode].libfunc = \
4474 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3"); \
4475 smul_optab->handlers[(int) DFmode].libfunc = \
4476 gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3"); \
4477 flodiv_optab->handlers[(int) DFmode].libfunc = \
4478 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3"); \
4480 extendsfdf2_libfunc = \
4481 gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2"); \
4482 truncdfsf2_libfunc = \
4483 gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2"); \
4486 gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2"); \
4488 gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2"); \
4490 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2"); \
4492 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2"); \
4494 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2"); \
4496 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2"); \
4498 floatsidf_libfunc = \
4499 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf"); \
4501 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi"); \
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