1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
76 /* Recast the cpu class to be the cpu attribute. */
77 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
79 /* Which ABI to use. These are constants because abi64.h must check their
80 value at preprocessing time.
82 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
83 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
90 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
91 which is not the same as the above EABI (defined by Cygnus,
92 Greenhills, and Toshiba?). MEABI is not yet complete or published,
93 but at this point it looks like N32 as far as calling conventions go,
94 but allows for either 32 or 64 bit registers.
96 Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
97 EABI the legacy EABI. In the end we may end up calling both ABI's
98 EABI but give them different version numbers, but for now I'm going
99 with different names. */
102 /* Whether to emit abicalls code sequences or not. */
104 enum mips_abicalls_type {
109 /* Recast the abicalls class to be the abicalls attribute. */
110 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
112 /* Which type of block move to do (whether or not the last store is
113 split out so it can fill a branch delay slot). */
115 enum block_move_type {
116 BLOCK_MOVE_NORMAL, /* generate complete block move */
117 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
118 BLOCK_MOVE_LAST /* generate just the last store */
121 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
122 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
123 extern const char *current_function_file; /* filename current function is in */
124 extern int num_source_filenames; /* current .file # */
125 extern int inside_function; /* != 0 if inside of a function */
126 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
127 extern int file_in_function_warning; /* warning given about .file in func */
128 extern int sdb_label_count; /* block start/end next label # */
129 extern int sdb_begin_function_line; /* Starting Line of current function */
130 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
131 extern int g_switch_value; /* value of the -G xx switch */
132 extern int g_switch_set; /* whether -G xx was passed. */
133 extern int sym_lineno; /* sgi next label # for each stmt */
134 extern int set_noreorder; /* # of nested .set noreorder's */
135 extern int set_nomacro; /* # of nested .set nomacro's */
136 extern int set_noat; /* # of nested .set noat's */
137 extern int set_volatile; /* # of nested .set volatile's */
138 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
139 extern int mips_dbx_regno[]; /* Map register # to debug register # */
140 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
141 extern enum cmp_type branch_type; /* what type of branch to use */
142 extern enum processor_type mips_arch; /* which cpu to codegen for */
143 extern enum processor_type mips_tune; /* which cpu to schedule for */
144 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
145 extern int mips_isa; /* architectural level */
146 extern int mips16; /* whether generating mips16 code */
147 extern int mips16_hard_float; /* mips16 without -msoft-float */
148 extern int mips_entry; /* generate entry/exit for mips16 */
149 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
150 extern const char *mips_arch_string; /* for -march=<xxx> */
151 extern const char *mips_tune_string; /* for -mtune=<xxx> */
152 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
153 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
154 extern const char *mips_entry_string; /* for -mentry */
155 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
156 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
157 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
158 extern int mips_split_addresses; /* perform high/lo_sum support */
159 extern int dslots_load_total; /* total # load related delay slots */
160 extern int dslots_load_filled; /* # filled load delay slots */
161 extern int dslots_jump_total; /* total # jump related delay slots */
162 extern int dslots_jump_filled; /* # filled jump delay slots */
163 extern int dslots_number_nops; /* # of nops needed by previous insn */
164 extern int num_refs[3]; /* # 1/2/3 word references */
165 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
166 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
167 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
168 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
169 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
170 extern int mips_string_length; /* length of strings for mips16 */
171 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
173 /* Functions to change what output section we are using. */
174 extern void rdata_section PARAMS ((void));
175 extern void sdata_section PARAMS ((void));
176 extern void sbss_section PARAMS ((void));
178 /* Stubs for half-pic support if not OSF/1 reference platform. */
181 #define HALF_PIC_P() 0
182 #define HALF_PIC_NUMBER_PTRS 0
183 #define HALF_PIC_NUMBER_REFS 0
184 #define HALF_PIC_ENCODE(DECL)
185 #define HALF_PIC_DECLARE(NAME)
186 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it")
187 #define HALF_PIC_ADDRESS_P(X) 0
188 #define HALF_PIC_PTR(X) X
189 #define HALF_PIC_FINISH(STREAM)
192 /* Macros to silence warnings about numbers being signed in traditional
193 C and unsigned in ISO C when compiled on 32-bit hosts. */
195 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
196 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
197 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
200 /* Run-time compilation parameters selecting different hardware subsets. */
202 /* Macros used in the machine description to test the flags. */
204 /* Bits for real switches */
205 #define MASK_INT64 0x00000001 /* ints are 64 bits */
206 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
207 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
208 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
209 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
210 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
211 #define MASK_STATS 0x00000040 /* print statistics to stderr */
212 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
213 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
214 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
215 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
216 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
217 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
218 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
219 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
220 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
221 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
222 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
223 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
224 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
225 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
226 #define MASK_NO_CHECK_ZERO_DIV \
227 0x00200000 /* divide by zero checking */
228 #define MASK_CHECK_RANGE_DIV \
229 0x00400000 /* divide result range checking */
230 #define MASK_UNINIT_CONST_IN_RODATA \
231 0x00800000 /* Store uninitialized
233 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
234 multiply-add operations. */
236 /* Debug switches, not documented */
237 #define MASK_DEBUG 0 /* unused */
238 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
239 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
240 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
241 #define MASK_DEBUG_D 0 /* don't do define_split's */
242 #define MASK_DEBUG_E 0 /* function_arg debug */
243 #define MASK_DEBUG_F 0 /* ??? */
244 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
245 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
246 #define MASK_DEBUG_I 0 /* unused */
248 /* Dummy switches used only in specs */
249 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
251 /* r4000 64 bit sizes */
252 #define TARGET_INT64 (target_flags & MASK_INT64)
253 #define TARGET_LONG64 (target_flags & MASK_LONG64)
254 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
255 #define TARGET_64BIT (target_flags & MASK_64BIT)
257 /* Mips vs. GNU linker */
258 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
260 /* Mips vs. GNU assembler */
261 #define TARGET_GAS (target_flags & MASK_GAS)
262 #define TARGET_MIPS_AS (!TARGET_GAS)
265 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
266 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
267 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
268 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
269 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
270 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
271 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
272 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
273 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
274 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
276 /* Reg. Naming in .s ($21 vs. $a0) */
277 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
279 /* Optimize for Sdata/Sbss */
280 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
282 /* print program statistics */
283 #define TARGET_STATS (target_flags & MASK_STATS)
285 /* call memcpy instead of inline code */
286 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
288 /* .abicalls, etc from Pyramid V.4 */
289 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
291 /* OSF pic references to externs */
292 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
294 /* software floating point */
295 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
296 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
298 /* always call through a register */
299 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
301 /* generate embedded PIC code;
303 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
305 /* for embedded systems, optimize for
306 reduced RAM space instead of for
308 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
310 /* always store uninitialized const
311 variables in rodata, requires
312 TARGET_EMBEDDED_DATA. */
313 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
315 /* generate big endian code. */
316 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
318 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
319 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
321 #define TARGET_MAD (target_flags & MASK_MAD)
323 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
325 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
327 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
328 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
330 /* This is true if we must enable the assembly language file switching
333 #define TARGET_FILE_SWITCHING \
334 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
336 /* We must disable the function end stabs when doing the file switching trick,
337 because the Lscope stabs end up in the wrong place, making it impossible
338 to debug the resulting code. */
339 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
341 /* Generate mips16 code */
342 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
344 /* Architecture target defines. */
345 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
346 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
347 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
348 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
349 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
350 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
352 /* Scheduling target defines. */
353 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
354 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
355 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
356 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
357 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
359 /* Macro to define tables used to set the flags.
360 This is a list in braces of pairs in braces,
361 each pair being { "NAME", VALUE }
362 where VALUE is the bits to set or minus the bits to clear.
363 An empty string NAME is used to identify the default VALUE. */
365 #define TARGET_SWITCHES \
368 N_("No default crt0.o") }, \
369 {"int64", MASK_INT64 | MASK_LONG64, \
370 N_("Use 64-bit int type")}, \
371 {"long64", MASK_LONG64, \
372 N_("Use 64-bit long type")}, \
373 {"long32", -(MASK_LONG64 | MASK_INT64), \
374 N_("Use 32-bit long type")}, \
375 {"split-addresses", MASK_SPLIT_ADDR, \
376 N_("Optimize lui/addiu address loads")}, \
377 {"no-split-addresses", -MASK_SPLIT_ADDR, \
378 N_("Don't optimize lui/addiu address loads")}, \
379 {"mips-as", -MASK_GAS, \
380 N_("Use MIPS as")}, \
383 {"rnames", MASK_NAME_REGS, \
384 N_("Use symbolic register names")}, \
385 {"no-rnames", -MASK_NAME_REGS, \
386 N_("Don't use symbolic register names")}, \
387 {"gpOPT", MASK_GPOPT, \
388 N_("Use GP relative sdata/sbss sections")}, \
389 {"gpopt", MASK_GPOPT, \
390 N_("Use GP relative sdata/sbss sections")}, \
391 {"no-gpOPT", -MASK_GPOPT, \
392 N_("Don't use GP relative sdata/sbss sections")}, \
393 {"no-gpopt", -MASK_GPOPT, \
394 N_("Don't use GP relative sdata/sbss sections")}, \
395 {"stats", MASK_STATS, \
396 N_("Output compiler statistics")}, \
397 {"no-stats", -MASK_STATS, \
398 N_("Don't output compiler statistics")}, \
399 {"memcpy", MASK_MEMCPY, \
400 N_("Don't optimize block moves")}, \
401 {"no-memcpy", -MASK_MEMCPY, \
402 N_("Optimize block moves")}, \
403 {"mips-tfile", MASK_MIPS_TFILE, \
404 N_("Use mips-tfile asm postpass")}, \
405 {"no-mips-tfile", -MASK_MIPS_TFILE, \
406 N_("Don't use mips-tfile asm postpass")}, \
407 {"soft-float", MASK_SOFT_FLOAT, \
408 N_("Use software floating point")}, \
409 {"hard-float", -MASK_SOFT_FLOAT, \
410 N_("Use hardware floating point")}, \
411 {"fp64", MASK_FLOAT64, \
412 N_("Use 64-bit FP registers")}, \
413 {"fp32", -MASK_FLOAT64, \
414 N_("Use 32-bit FP registers")}, \
415 {"gp64", MASK_64BIT, \
416 N_("Use 64-bit general registers")}, \
417 {"gp32", -MASK_64BIT, \
418 N_("Use 32-bit general registers")}, \
419 {"abicalls", MASK_ABICALLS, \
420 N_("Use Irix PIC")}, \
421 {"no-abicalls", -MASK_ABICALLS, \
422 N_("Don't use Irix PIC")}, \
423 {"half-pic", MASK_HALF_PIC, \
424 N_("Use OSF PIC")}, \
425 {"no-half-pic", -MASK_HALF_PIC, \
426 N_("Don't use OSF PIC")}, \
427 {"long-calls", MASK_LONG_CALLS, \
428 N_("Use indirect calls")}, \
429 {"no-long-calls", -MASK_LONG_CALLS, \
430 N_("Don't use indirect calls")}, \
431 {"embedded-pic", MASK_EMBEDDED_PIC, \
432 N_("Use embedded PIC")}, \
433 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
434 N_("Don't use embedded PIC")}, \
435 {"embedded-data", MASK_EMBEDDED_DATA, \
436 N_("Use ROM instead of RAM")}, \
437 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
438 N_("Don't use ROM instead of RAM")}, \
439 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
440 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
441 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
442 N_("Don't put uninitialized constants in ROM")}, \
443 {"eb", MASK_BIG_ENDIAN, \
444 N_("Use big-endian byte order")}, \
445 {"el", -MASK_BIG_ENDIAN, \
446 N_("Use little-endian byte order")}, \
447 {"single-float", MASK_SINGLE_FLOAT, \
448 N_("Use single (32-bit) FP only")}, \
449 {"double-float", -MASK_SINGLE_FLOAT, \
450 N_("Don't use single (32-bit) FP only")}, \
452 N_("Use multiply accumulate")}, \
453 {"no-mad", -MASK_MAD, \
454 N_("Don't use multiply accumulate")}, \
455 {"no-fused-madd", MASK_NO_FUSED_MADD, \
456 N_("Don't generate fused multiply/add instructions")}, \
457 {"fused-madd", -MASK_NO_FUSED_MADD, \
458 N_("Generate fused multiply/add instructions")}, \
459 {"fix4300", MASK_4300_MUL_FIX, \
460 N_("Work around early 4300 hardware bug")}, \
461 {"no-fix4300", -MASK_4300_MUL_FIX, \
462 N_("Don't work around early 4300 hardware bug")}, \
464 N_("Optimize for 3900")}, \
466 N_("Optimize for 4650")}, \
467 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
468 N_("Trap on integer divide by zero")}, \
469 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
470 N_("Don't trap on integer divide by zero")}, \
471 {"check-range-division",MASK_CHECK_RANGE_DIV, \
472 N_("Trap on integer divide overflow")}, \
473 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
474 N_("Don't trap on integer divide overflow")}, \
475 {"debug", MASK_DEBUG, \
477 {"debuga", MASK_DEBUG_A, \
479 {"debugb", MASK_DEBUG_B, \
481 {"debugc", MASK_DEBUG_C, \
483 {"debugd", MASK_DEBUG_D, \
485 {"debuge", MASK_DEBUG_E, \
487 {"debugf", MASK_DEBUG_F, \
489 {"debugg", MASK_DEBUG_G, \
491 {"debugh", MASK_DEBUG_H, \
493 {"debugi", MASK_DEBUG_I, \
495 {"", (TARGET_DEFAULT \
496 | TARGET_CPU_DEFAULT \
497 | TARGET_ENDIAN_DEFAULT), \
501 /* Default target_flags if no switches are specified */
503 #ifndef TARGET_DEFAULT
504 #define TARGET_DEFAULT 0
507 #ifndef TARGET_CPU_DEFAULT
508 #define TARGET_CPU_DEFAULT 0
511 #ifndef TARGET_ENDIAN_DEFAULT
513 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
515 #define TARGET_ENDIAN_DEFAULT 0
519 #ifndef MIPS_ISA_DEFAULT
520 #define MIPS_ISA_DEFAULT 1
525 /* Make this compile time constant for libgcc2 */
527 #define TARGET_64BIT 1
529 #define TARGET_64BIT 0
531 #endif /* IN_LIBGCC2 */
533 #ifndef MULTILIB_ENDIAN_DEFAULT
534 #if TARGET_ENDIAN_DEFAULT == 0
535 #define MULTILIB_ENDIAN_DEFAULT "EL"
537 #define MULTILIB_ENDIAN_DEFAULT "EB"
541 #ifndef MULTILIB_ISA_DEFAULT
542 # if MIPS_ISA_DEFAULT == 1
543 # define MULTILIB_ISA_DEFAULT "mips1"
545 # if MIPS_ISA_DEFAULT == 2
546 # define MULTILIB_ISA_DEFAULT "mips2"
548 # if MIPS_ISA_DEFAULT == 3
549 # define MULTILIB_ISA_DEFAULT "mips3"
551 # if MIPS_ISA_DEFAULT == 4
552 # define MULTILIB_ISA_DEFAULT "mips4"
554 # if MIPS_ISA_DEFAULT == 32
555 # define MULTILIB_ISA_DEFAULT "mips32"
557 # if MIPS_ISA_DEFAULT == 64
558 # define MULTILIB_ISA_DEFAULT "mips64"
560 # define MULTILIB_ISA_DEFAULT "mips1"
569 #ifndef MULTILIB_DEFAULTS
570 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
573 /* We must pass -EL to the linker by default for little endian embedded
574 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
575 linker will default to using big-endian output files. The OUTPUT_FORMAT
576 line must be in the linker script, otherwise -EB/-EL will not work. */
579 #if TARGET_ENDIAN_DEFAULT == 0
580 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
582 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
586 #define TARGET_OPTIONS \
588 SUBTARGET_TARGET_OPTIONS \
589 { "cpu=", &mips_cpu_string, \
590 N_("Specify CPU for scheduling purposes")}, \
591 { "tune=", &mips_tune_string, \
592 N_("Specify CPU for scheduling purposes")}, \
593 { "arch=", &mips_arch_string, \
594 N_("Specify CPU for code generation purposes")}, \
595 { "ips", &mips_isa_string, \
596 N_("Specify a Standard MIPS ISA")}, \
597 { "entry", &mips_entry_string, \
598 N_("Use mips16 entry/exit psuedo ops")}, \
599 { "no-mips16", &mips_no_mips16_string, \
600 N_("Don't use MIPS16 instructions")}, \
601 { "explicit-type-size", &mips_explicit_type_size_string, \
603 { "no-flush-func", &mips_cache_flush_func, \
604 N_("Don't call any cache flush functions")}, \
605 { "flush-func=", &mips_cache_flush_func, \
606 N_("Specify cache flush function")}, \
609 /* This is meant to be redefined in the host dependent files. */
610 #define SUBTARGET_TARGET_OPTIONS
612 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
614 /* Generate three-operand multiply instructions for SImode. */
615 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
620 /* Generate three-operand multiply instructions for DImode. */
621 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
624 /* Macros to decide whether certain features are available or not,
625 depending on the instruction set architecture level. */
627 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
628 #define HAVE_SQRT_P() (mips_isa != 1)
630 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
631 #define ISA_HAS_64BIT_REGS (mips_isa == 3 \
635 /* ISA has branch likely instructions (eg. mips2). */
636 /* Disable branchlikely for tx39 until compare rewrite. They haven't
637 been generated up to this point. */
638 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
639 /* || TARGET_MIPS3900 */)
641 /* ISA has the conditional move instructions introduced in mips4. */
642 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
646 /* ISA has just the integer condition move instructions (movn,movz) */
647 #define ISA_HAS_INT_CONDMOVE 0
651 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
652 branch on CC, and move (both FP and non-FP) on CC. */
653 #define ISA_HAS_8CC (mips_isa == 4 \
658 /* This is a catch all for the other new mips4 instructions: indexed load and
659 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
660 and the FP recip and recip sqrt instructions */
661 #define ISA_HAS_FP4 (mips_isa == 4 \
664 /* ISA has conditional trap instructions. */
665 #define ISA_HAS_COND_TRAP (mips_isa >= 2)
667 /* ISA has multiply-accumulate instructions, madd and msub. */
668 #define ISA_HAS_MADD_MSUB (mips_isa == 32 \
672 /* ISA has nmadd and nmsub instructions. */
673 #define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
676 /* ISA has count leading zeroes/ones instruction (not implemented). */
677 #define ISA_HAS_CLZ_CLO (mips_isa == 32 \
681 /* ISA has double-word count leading zeroes/ones instruction (not
683 #define ISA_HAS_DCLZ_DCLO (mips_isa == 64)
686 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
687 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
688 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
689 target_flags, and -mgp64 sets MASK_64BIT.
691 Setting MASK_64BIT in target_flags will cause gcc to assume that
692 registers are 64 bits wide. int, long and void * will be 32 bit;
693 this may be changed with -mint64 or -mlong64.
695 The gen* programs link code that refers to MASK_64BIT. They don't
696 actually use the information in target_flags; they just refer to
699 /* Switch Recognition by gcc.c. Add -G xx support */
701 #undef SWITCH_TAKES_ARG
702 #define SWITCH_TAKES_ARG(CHAR) \
703 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
705 /* Sometimes certain combinations of command options do not make sense
706 on a particular target machine. You can define a macro
707 `OVERRIDE_OPTIONS' to take account of this. This macro, if
708 defined, is executed once just after all the command options have
711 On the MIPS, it is used to handle -G. We also use it to set up all
712 of the tables referenced in the other macros. */
714 #define OVERRIDE_OPTIONS override_options ()
716 /* Zero or more C statements that may conditionally modify two
717 variables `fixed_regs' and `call_used_regs' (both of type `char
718 []') after they have been initialized from the two preceding
721 This is necessary in case the fixed or call-clobbered registers
722 depend on target flags.
724 You need not define this macro if it has no work to do.
726 If the usage of an entire class of registers depends on the target
727 flags, you may indicate this to GCC by using this macro to modify
728 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
729 the classes which should not be used by GCC. Also define the macro
730 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
731 letter for a class that shouldn't be used.
733 (However, if this class is not included in `GENERAL_REGS' and all
734 of the insn patterns whose constraints permit this class are
735 controlled by target switches, then GCC will automatically avoid
736 using these registers when the target switches are opposed to
739 #define CONDITIONAL_REGISTER_USAGE \
742 if (!TARGET_HARD_FLOAT) \
746 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
747 fixed_regs[regno] = call_used_regs[regno] = 1; \
748 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
749 fixed_regs[regno] = call_used_regs[regno] = 1; \
751 else if (! ISA_HAS_8CC) \
755 /* We only have a single condition code register. We \
756 implement this by hiding all the condition code registers, \
757 and generating RTL that refers directly to ST_REG_FIRST. */ \
758 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
759 fixed_regs[regno] = call_used_regs[regno] = 1; \
761 /* In mips16 mode, we permit the $t temporary registers to be used \
762 for reload. We prohibit the unused $s registers, since they \
763 are caller saved, and saving them via a mips16 register would \
764 probably waste more time than just reloading the value. */ \
767 fixed_regs[18] = call_used_regs[18] = 1; \
768 fixed_regs[19] = call_used_regs[19] = 1; \
769 fixed_regs[20] = call_used_regs[20] = 1; \
770 fixed_regs[21] = call_used_regs[21] = 1; \
771 fixed_regs[22] = call_used_regs[22] = 1; \
772 fixed_regs[23] = call_used_regs[23] = 1; \
773 fixed_regs[26] = call_used_regs[26] = 1; \
774 fixed_regs[27] = call_used_regs[27] = 1; \
775 fixed_regs[30] = call_used_regs[30] = 1; \
777 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
781 /* This is meant to be redefined in the host dependent files. */
782 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
784 /* Show we can debug even without a frame pointer. */
785 #define CAN_DEBUG_WITHOUT_FP
787 /* Complain about missing specs and predefines that should be defined in each
788 of the target tm files to override the defaults. This is mostly a place-
789 holder until I can get each of the files updated [mm]. */
791 #if defined(OSF_OS) \
792 || defined(DECSTATION) \
793 || defined(SGI_TARGET) \
794 || defined(MIPS_NEWS) \
795 || defined(MIPS_SYSV) \
796 || defined(MIPS_SVR4) \
797 || defined(MIPS_BSD43)
799 #ifndef CPP_PREDEFINES
800 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
804 #error "Define LIB_SPEC in the appropriate tm.h file"
807 #ifndef STARTFILE_SPEC
808 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
812 #error "Define MACHINE_TYPE in the appropriate tm.h file"
816 /* Tell collect what flags to pass to nm. */
818 #define NM_FLAGS "-Bn"
822 /* Names to predefine in the preprocessor for this target machine. */
824 #ifndef CPP_PREDEFINES
825 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
826 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
827 -Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
830 /* Assembler specs. */
832 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
835 #define MIPS_AS_ASM_SPEC "\
836 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
837 %{pipe: %e-pipe is not supported} \
838 %{K} %(subtarget_mips_as_asm_spec)"
840 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
841 rather than gas. It may be overridden by subtargets. */
843 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
844 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
847 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
850 #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64} %(abi_gas_asm_spec) %{mabi=32:%{!mips*:-mips1}}"
855 #ifndef MIPS_ABI_DEFAULT
856 #define MIPS_ABI_DEFAULT ABI_32
859 #ifndef ABI_GAS_ASM_SPEC
860 #define ABI_GAS_ASM_SPEC ""
863 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
864 GAS_ASM_SPEC as the default, depending upon the value of
867 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
870 #define TARGET_ASM_SPEC "\
871 %{mmips-as: %(mips_as_asm_spec)} \
872 %{!mmips-as: %(gas_asm_spec)}"
876 #define TARGET_ASM_SPEC "\
877 %{!mgas: %(mips_as_asm_spec)} \
878 %{mgas: %(gas_asm_spec)}"
882 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
883 to the assembler. It may be overridden by subtargets. */
884 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
885 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
887 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
890 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
891 the assembler. It may be overridden by subtargets. */
892 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
893 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
894 %{g} %{g0} %{g1} %{g2} %{g3} \
895 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
896 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
897 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
898 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
901 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
902 overridden by subtargets. */
904 #ifndef SUBTARGET_ASM_SPEC
905 #define SUBTARGET_ASM_SPEC ""
908 /* ASM_SPEC is the set of arguments to pass to the assembler. */
912 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
913 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
914 %(subtarget_asm_optimizing_spec) \
915 %(subtarget_asm_debugging_spec) \
917 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
919 %(subtarget_asm_spec)"
921 /* Specify to run a post-processor, mips-tfile after the assembler
922 has run to stuff the mips debug information into the object file.
923 This is needed because the $#!%^ MIPS assembler provides no way
924 of specifying such information in the assembly file. If we are
925 cross compiling, disable mips-tfile unless the user specifies
928 #ifndef ASM_FINAL_SPEC
929 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
931 #define ASM_FINAL_SPEC "\
932 %{mmips-as: %{!mno-mips-tfile: \
933 \n mips-tfile %{v*: -v} \
935 %{!K: %{save-temps: -I %b.o~}} \
936 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
937 %{.s:%i} %{!.s:%g.s}}}"
941 #define ASM_FINAL_SPEC "\
942 %{!mgas: %{!mno-mips-tfile: \
943 \n mips-tfile %{v*: -v} \
945 %{!K: %{save-temps: -I %b.o~}} \
946 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
947 %{.s:%i} %{!.s:%g.s}}}"
950 #endif /* ASM_FINAL_SPEC */
952 /* Redefinition of libraries used. Mips doesn't support normal
953 UNIX style profiling via calling _mcount. It does offer
954 profiling that samples the PC, so do what we can... */
957 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
960 /* Extra switches sometimes passed to the linker. */
961 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
962 will interpret it as a -b option. */
967 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
968 %{bestGnum} %{shared} %{non_shared}"
969 #endif /* LINK_SPEC defined */
972 /* Specs for the compiler proper */
974 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
975 overridden by subtargets. */
976 #ifndef SUBTARGET_CC1_SPEC
977 #define SUBTARGET_CC1_SPEC ""
980 /* Deal with historic options. */
982 #define CC1_CPU_SPEC "\
984 %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
985 %n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
986 %{m4650:-march=r4650 -mmad -msingle-float \
987 %n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
990 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
991 /* Note, we will need to adjust the following if we ever find a MIPS variant
992 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
993 that show up in this case. */
997 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
998 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
999 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1000 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1001 %{mips32:-mfp32 -mgp32} \
1002 %{mips64:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1003 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
1004 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
1005 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
1006 %{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \
1007 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1008 %{pic-none: -mno-half-pic} \
1009 %{pic-lib: -mhalf-pic} \
1010 %{pic-extern: -mhalf-pic} \
1011 %{pic-calls: -mhalf-pic} \
1013 %(subtarget_cc1_spec) \
1017 /* Preprocessor specs. */
1019 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
1020 be overridden by subtargets. */
1022 #ifndef SUBTARGET_CPP_SIZE_SPEC
1024 #if MIPS_ISA_DEFAULT != 3 && MIPS_ISA_DEFAULT != 4 && MIPS_ISA_DEFAULT != 5 && MIPS_ISA_DEFAULT != 64
1026 /* 32-bit cases first. */
1028 #if MIPS_ABI_DEFAULT == ABI_EABI
1029 #define SUBTARGET_CPP_SIZE_SPEC "\
1030 %{mabi=eabi|!mabi=*:\
1031 %{mips1|mips2|mips32|mlong32|mgp32:%{!mips3:%{!mips4:%{!mips5:%{!mips64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}} \
1033 %{mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1034 %{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}\
1035 %{mips3|mips4|mips5|mips64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}} \
1036 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}}}}}}}\
1039 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1040 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1041 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1042 %{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1046 #if MIPS_ABI_DEFAULT == ABI_O64
1047 #define SUBTARGET_CPP_SIZE_SPEC "\
1049 %{mips1|mips2|mips32|mlong32|mgp32:%{!mips3:%{!mips4:%{!mips5:%{!mips64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}} \
1051 %{mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1052 %{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}\
1053 %{mips3|mips4|mips5|mips64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}} \
1054 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}}}}}}}\
1055 %{mabi=o64|!mabi=*:\
1057 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1058 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1059 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1060 %{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}\
1064 #if MIPS_ABI_DEFAULT == ABI_32
1065 #define SUBTARGET_CPP_SIZE_SPEC "\
1067 %{mips1|mips2|mips32|mlong32|mgp32:%{!mips3:%{!mips4:%{!mips5:%{!mips64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}} \
1069 %{mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1070 %{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}\
1071 %{mips3|mips4|mips5|mips64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}} \
1072 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}}}}}}}\
1075 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1076 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1077 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1078 %{mabi=32|!mabi=*:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}\
1082 #if MIPS_ABI_DEFAULT == ABI_MEABI
1083 #define SUBTARGET_CPP_SIZE_SPEC "\
1085 %{mips1|mips2|mips32|mlong32|mgp32:%{!mips3:%{!mips4:%{!mips5:%{!mips64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}} \
1087 %{mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1088 %{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}\
1089 %{mips3|mips4|mips5|mips64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}} \
1090 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}}}}}}}\
1093 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1094 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1095 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1096 %{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}\
1097 %{mabi=meabi|!mabi=*:\
1098 %{mips3|mips4|mips5|mips64|mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1099 %{!mips3:%{!mips4:%{!mips5:%{!mips64:%{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}}}}}} \
1105 /* 64-bit default ISA. */
1107 #if MIPS_ABI_DEFAULT == ABI_EABI
1108 #define SUBTARGET_CPP_SIZE_SPEC "\
1109 %{mabi=eabi|!mabi=*: \
1110 %{mips1|mips2|mips32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1111 %{mlong32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1112 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1113 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1114 %{mips3|mips4|mips5|mips64:%{!mips1:%{!mips2:%{!mips32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}\
1115 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}}}}}}}}\
1116 %{mgp64:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}\
1119 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1120 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1121 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1122 %{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1126 #if MIPS_ABI_DEFAULT == ABI_O64
1127 #define SUBTARGET_CPP_SIZE_SPEC "\
1129 %{mips1|mips2|mips32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1130 %{mlong32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1131 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1132 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1133 %{mips3|mips4|mips5|mips64:%{!mips1:%{!mips2:%{!mips32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}\
1134 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}}}}}}}}\
1135 %{mgp64:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}\
1136 %{mabi=o64|!mabi=*:\
1138 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1139 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1140 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1141 %{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}\
1145 #if MIPS_ABI_DEFAULT == ABI_32
1146 #define SUBTARGET_CPP_SIZE_SPEC "\
1148 %{mips1|mips2|mips32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1149 %{mlong32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1150 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1151 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1152 %{mips3|mips4|mips5|mips64:%{!mips1:%{!mips2:%{!mips32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}\
1153 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}}}}}}}}\
1154 %{mgp64:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}\
1157 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1158 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1159 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1160 %{mabi=32|!mabi=*:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}\
1164 #if MIPS_ABI_DEFAULT == ABI_MEABI
1165 #define SUBTARGET_CPP_SIZE_SPEC "\
1167 %{mips1|mips2|mips32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1168 %{mlong32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1169 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1170 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1171 %{mips3|mips4|mips5|mips64:%{!mips1:%{!mips2:%{!mips32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}\
1172 %{!mips1:%{!mips2:%{!mips3:%{!mips4:%{!mips5:%{!mips32:%{!mips64:%{!mlong32:%{!mlong64:%{!mgp32:%{!mgp64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}}}}}}}}\
1173 %{mgp64:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}\
1176 %{!mgp32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
1177 %{mgp32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1178 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}} \
1179 %{mabi=32:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}\
1180 %{mabi=meabi|!mabi=*:\
1181 %{mips1|mips2|mips32|mlong32: -D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int} \
1182 %{!mips1:%{!mips2:%{!mips32:%{!mlong32:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}}}} \
1190 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1191 overridden by subtargets. */
1192 #ifndef SUBTARGET_CPP_SPEC
1193 #define SUBTARGET_CPP_SPEC ""
1196 /* If we're using 64bit longs, then we have to define __LONG_MAX__
1197 correctly. Similarly for 64bit ints and __INT_MAX__. */
1198 #ifndef LONG_MAX_SPEC
1199 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
1200 #define LONG_MAX_SPEC "%{!mlong32:-D__LONG_MAX__=9223372036854775807L}"
1202 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
1206 /* Define appropriate macros for fpr register size. */
1207 #ifndef CPP_FPR_SPEC
1208 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_FLOAT64)
1209 #define CPP_FPR_SPEC "-D__mips_fpr=64"
1211 #define CPP_FPR_SPEC "-D__mips_fpr=32"
1215 /* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
1216 of the source file extension. */
1217 #undef CPLUSPLUS_CPP_SPEC
1218 #define CPLUSPLUS_CPP_SPEC "\
1219 -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
1222 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
1226 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
1227 %{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1228 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
1229 %(subtarget_cpp_size_spec) \
1230 %{mips3:-U__mips -D__mips=3 -D__mips64} \
1231 %{mips4:-U__mips -D__mips=4 -D__mips64} \
1232 %{mips32:-U__mips -D__mips=32} \
1233 %{mips64:-U__mips -D__mips=64 -D__mips64} \
1234 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
1235 %{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} %{!mfp32: %{!mfp64: %{mgp32:-D__mips_fpr=32} %{!mgp32: %(cpp_fpr_spec)}}} \
1236 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1237 %{m4650:%{!msoft-float:-D__mips_single_float}} \
1238 %{msoft-float:-D__mips_soft_float} \
1239 %{mabi=eabi:-D__mips_eabi} \
1240 %{mips16:%{!mno-mips16:-D__mips16}} \
1241 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
1242 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
1244 %(subtarget_cpp_spec) "
1247 /* This macro defines names of additional specifications to put in the specs
1248 that can be used in various specifications like CC1_SPEC. Its definition
1249 is an initializer with a subgrouping for each command option.
1251 Each subgrouping contains a string constant, that defines the
1252 specification name, and a string constant that used by the GNU CC driver
1255 Do not define this macro if it does not need to do anything. */
1257 #define EXTRA_SPECS \
1258 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1259 { "cc1_cpu_spec", CC1_CPU_SPEC}, \
1260 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1261 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
1262 { "long_max_spec", LONG_MAX_SPEC }, \
1263 { "cpp_fpr_spec", CPP_FPR_SPEC }, \
1264 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1265 { "gas_asm_spec", GAS_ASM_SPEC }, \
1266 { "abi_gas_asm_spec", ABI_GAS_ASM_SPEC }, \
1267 { "target_asm_spec", TARGET_ASM_SPEC }, \
1268 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1269 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1270 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1271 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1272 { "endian_spec", ENDIAN_SPEC }, \
1273 SUBTARGET_EXTRA_SPECS
1275 #ifndef SUBTARGET_EXTRA_SPECS
1276 #define SUBTARGET_EXTRA_SPECS
1279 /* If defined, this macro is an additional prefix to try after
1280 `STANDARD_EXEC_PREFIX'. */
1282 #ifndef MD_EXEC_PREFIX
1283 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1286 #ifndef MD_STARTFILE_PREFIX
1287 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1291 /* Print subsidiary information on the compiler version in use. */
1293 #define MIPS_VERSION "[AL 1.1, MM 40]"
1295 #ifndef MACHINE_TYPE
1296 #define MACHINE_TYPE "BSD Mips"
1299 #ifndef TARGET_VERSION_INTERNAL
1300 #define TARGET_VERSION_INTERNAL(STREAM) \
1301 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1304 #ifndef TARGET_VERSION
1305 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1309 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1310 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1311 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1313 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1314 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1317 /* By default, turn on GDB extensions. */
1318 #define DEFAULT_GDB_EXTENSIONS 1
1320 /* If we are passing smuggling stabs through the MIPS ECOFF object
1321 format, put a comment in front of the .stab<x> operation so
1322 that the MIPS assembler does not choke. The mips-tfile program
1323 will correctly put the stab into the object file. */
1325 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1326 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1327 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1329 /* Local compiler-generated symbols must have a prefix that the assembler
1330 understands. By default, this is $, although some targets (e.g.,
1331 NetBSD-ELF) need to override this. */
1333 #ifndef LOCAL_LABEL_PREFIX
1334 #define LOCAL_LABEL_PREFIX "$"
1337 /* By default on the mips, external symbols do not have an underscore
1338 prepended, but some targets (e.g., NetBSD) require this. */
1340 #ifndef USER_LABEL_PREFIX
1341 #define USER_LABEL_PREFIX ""
1344 /* Forward references to tags are allowed. */
1345 #define SDB_ALLOW_FORWARD_REFERENCES
1347 /* Unknown tags are also allowed. */
1348 #define SDB_ALLOW_UNKNOWN_REFERENCES
1350 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1351 since the length can run past this up to a continuation point. */
1352 #undef DBX_CONTIN_LENGTH
1353 #define DBX_CONTIN_LENGTH 1500
1355 /* How to renumber registers for dbx and gdb. */
1356 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1358 /* The mapping from gcc register number to DWARF 2 CFA column number.
1359 This mapping does not allow for tracking register 0, since SGI's broken
1360 dwarf reader thinks column 0 is used for the frame address, but since
1361 register 0 is fixed this is not a problem. */
1362 #define DWARF_FRAME_REGNUM(REG) \
1363 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1365 /* The DWARF 2 CFA column which tracks the return address. */
1366 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1368 /* Before the prologue, RA lives in r31. */
1369 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1371 /* Describe how we implement __builtin_eh_return. */
1372 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1373 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1375 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1376 The default for this in 64-bit mode is 8, which causes problems with
1377 SFmode register saves. */
1378 #define DWARF_CIE_DATA_ALIGNMENT 4
1380 /* Overrides for the COFF debug format. */
1381 #define PUT_SDB_SCL(a) \
1383 extern FILE *asm_out_text_file; \
1384 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1387 #define PUT_SDB_INT_VAL(a) \
1389 extern FILE *asm_out_text_file; \
1390 fprintf (asm_out_text_file, "\t.val\t"); \
1391 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1392 fprintf (asm_out_text_file, ";"); \
1395 #define PUT_SDB_VAL(a) \
1397 extern FILE *asm_out_text_file; \
1398 fputs ("\t.val\t", asm_out_text_file); \
1399 output_addr_const (asm_out_text_file, (a)); \
1400 fputc (';', asm_out_text_file); \
1403 #define PUT_SDB_DEF(a) \
1405 extern FILE *asm_out_text_file; \
1406 fprintf (asm_out_text_file, "\t%s.def\t", \
1407 (TARGET_GAS) ? "" : "#"); \
1408 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1409 fputc (';', asm_out_text_file); \
1412 #define PUT_SDB_PLAIN_DEF(a) \
1414 extern FILE *asm_out_text_file; \
1415 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1416 (TARGET_GAS) ? "" : "#", (a)); \
1419 #define PUT_SDB_ENDEF \
1421 extern FILE *asm_out_text_file; \
1422 fprintf (asm_out_text_file, "\t.endef\n"); \
1425 #define PUT_SDB_TYPE(a) \
1427 extern FILE *asm_out_text_file; \
1428 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1431 #define PUT_SDB_SIZE(a) \
1433 extern FILE *asm_out_text_file; \
1434 fprintf (asm_out_text_file, "\t.size\t"); \
1435 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1436 fprintf (asm_out_text_file, ";"); \
1439 #define PUT_SDB_DIM(a) \
1441 extern FILE *asm_out_text_file; \
1442 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1445 #ifndef PUT_SDB_START_DIM
1446 #define PUT_SDB_START_DIM \
1448 extern FILE *asm_out_text_file; \
1449 fprintf (asm_out_text_file, "\t.dim\t"); \
1453 #ifndef PUT_SDB_NEXT_DIM
1454 #define PUT_SDB_NEXT_DIM(a) \
1456 extern FILE *asm_out_text_file; \
1457 fprintf (asm_out_text_file, "%d,", a); \
1461 #ifndef PUT_SDB_LAST_DIM
1462 #define PUT_SDB_LAST_DIM(a) \
1464 extern FILE *asm_out_text_file; \
1465 fprintf (asm_out_text_file, "%d;", a); \
1469 #define PUT_SDB_TAG(a) \
1471 extern FILE *asm_out_text_file; \
1472 fprintf (asm_out_text_file, "\t.tag\t"); \
1473 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1474 fputc (';', asm_out_text_file); \
1477 /* For block start and end, we create labels, so that
1478 later we can figure out where the correct offset is.
1479 The normal .ent/.end serve well enough for functions,
1480 so those are just commented out. */
1482 #define PUT_SDB_BLOCK_START(LINE) \
1484 extern FILE *asm_out_text_file; \
1485 fprintf (asm_out_text_file, \
1486 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1487 LOCAL_LABEL_PREFIX, \
1489 (TARGET_GAS) ? "" : "#", \
1490 LOCAL_LABEL_PREFIX, \
1493 sdb_label_count++; \
1496 #define PUT_SDB_BLOCK_END(LINE) \
1498 extern FILE *asm_out_text_file; \
1499 fprintf (asm_out_text_file, \
1500 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1501 LOCAL_LABEL_PREFIX, \
1503 (TARGET_GAS) ? "" : "#", \
1504 LOCAL_LABEL_PREFIX, \
1507 sdb_label_count++; \
1510 #define PUT_SDB_FUNCTION_START(LINE)
1512 #define PUT_SDB_FUNCTION_END(LINE) \
1514 extern FILE *asm_out_text_file; \
1515 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1518 #define PUT_SDB_EPILOGUE_END(NAME)
1520 #define PUT_SDB_SRC_FILE(FILENAME) \
1522 extern FILE *asm_out_text_file; \
1523 output_file_directive (asm_out_text_file, (FILENAME)); \
1526 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1527 sprintf ((BUFFER), ".%dfake", (NUMBER));
1529 /* Correct the offset of automatic variables and arguments. Note that
1530 the MIPS debug format wants all automatic variables and arguments
1531 to be in terms of the virtual frame pointer (stack pointer before
1532 any adjustment in the function), while the MIPS 3.0 linker wants
1533 the frame pointer to be the stack pointer after the initial
1536 #define DEBUGGER_AUTO_OFFSET(X) \
1537 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1538 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1539 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1541 /* Tell collect that the object format is ECOFF */
1542 #ifndef OBJECT_FORMAT_ROSE
1543 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1544 #define EXTENDED_COFF /* ECOFF, not normal coff */
1547 /* Target machine storage layout */
1549 /* Define in order to support both big and little endian float formats
1550 in the same gcc binary. */
1551 #define REAL_ARITHMETIC
1553 /* Define this if most significant bit is lowest numbered
1554 in instructions that operate on numbered bit-fields.
1556 #define BITS_BIG_ENDIAN 0
1558 /* Define this if most significant byte of a word is the lowest numbered. */
1559 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1561 /* Define this if most significant word of a multiword number is the lowest. */
1562 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1564 /* Define this to set the endianness to use in libgcc2.c, which can
1565 not depend on target_flags. */
1566 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1567 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1569 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1572 /* Width in bits of a "word", which is the contents of a machine register.
1573 Note that this is not necessarily the width of data type `int';
1574 if using 16-bit ints on a 68000, this would still be 32.
1575 But on a machine with 16-bit registers, this would be 16. */
1576 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1577 #define MAX_BITS_PER_WORD 64
1579 /* Width of a word, in units (bytes). */
1580 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1581 #define MIN_UNITS_PER_WORD 4
1583 /* For MIPS, width of a floating point register. */
1584 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1586 /* A C expression for the size in bits of the type `int' on the
1587 target machine. If you don't define this, the default is one
1589 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1591 /* Tell the preprocessor the maximum size of wchar_t. */
1592 #ifndef MAX_WCHAR_TYPE_SIZE
1593 #ifndef WCHAR_TYPE_SIZE
1594 #define MAX_WCHAR_TYPE_SIZE 64
1598 /* A C expression for the size in bits of the type `short' on the
1599 target machine. If you don't define this, the default is half a
1600 word. (If this would be less than one storage unit, it is
1601 rounded up to one unit.) */
1602 #define SHORT_TYPE_SIZE 16
1604 /* A C expression for the size in bits of the type `long' on the
1605 target machine. If you don't define this, the default is one
1607 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1608 #define MAX_LONG_TYPE_SIZE 64
1610 /* A C expression for the size in bits of the type `long long' on the
1611 target machine. If you don't define this, the default is two
1613 #define LONG_LONG_TYPE_SIZE 64
1615 /* A C expression for the size in bits of the type `float' on the
1616 target machine. If you don't define this, the default is one
1618 #define FLOAT_TYPE_SIZE 32
1620 /* A C expression for the size in bits of the type `double' on the
1621 target machine. If you don't define this, the default is two
1623 #define DOUBLE_TYPE_SIZE 64
1625 /* A C expression for the size in bits of the type `long double' on
1626 the target machine. If you don't define this, the default is two
1628 #define LONG_DOUBLE_TYPE_SIZE 64
1630 /* Width in bits of a pointer.
1631 See also the macro `Pmode' defined below. */
1632 #ifndef POINTER_SIZE
1633 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1636 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1637 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1639 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1640 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1641 || mips_abi == ABI_64 \
1642 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1644 /* Allocation boundary (in *bits*) for the code of a function. */
1645 #define FUNCTION_BOUNDARY 32
1647 /* Alignment of field after `int : 0' in a structure. */
1648 #define EMPTY_FIELD_BOUNDARY 32
1650 /* Every structure's size must be a multiple of this. */
1651 /* 8 is observed right on a DECstation and on riscos 4.02. */
1652 #define STRUCTURE_SIZE_BOUNDARY 8
1654 /* There is no point aligning anything to a rounder boundary than this. */
1655 #define BIGGEST_ALIGNMENT 64
1657 /* Set this nonzero if move instructions will actually fail to work
1658 when given unaligned data. */
1659 #define STRICT_ALIGNMENT 1
1661 /* Define this if you wish to imitate the way many other C compilers
1662 handle alignment of bitfields and the structures that contain
1665 The behavior is that the type written for a bitfield (`int',
1666 `short', or other integer type) imposes an alignment for the
1667 entire structure, as if the structure really did contain an
1668 ordinary field of that type. In addition, the bitfield is placed
1669 within the structure so that it would fit within such a field,
1670 not crossing a boundary for it.
1672 Thus, on most machines, a bitfield whose type is written as `int'
1673 would not cross a four-byte boundary, and would force four-byte
1674 alignment for the whole structure. (The alignment used may not
1675 be four bytes; it is controlled by the other alignment
1678 If the macro is defined, its definition should be a C expression;
1679 a nonzero value for the expression enables this behavior. */
1681 #define PCC_BITFIELD_TYPE_MATTERS 1
1683 /* If defined, a C expression to compute the alignment given to a
1684 constant that is being placed in memory. CONSTANT is the constant
1685 and ALIGN is the alignment that the object would ordinarily have.
1686 The value of this macro is used instead of that alignment to align
1689 If this macro is not defined, then ALIGN is used.
1691 The typical use of this macro is to increase alignment for string
1692 constants to be word aligned so that `strcpy' calls that copy
1693 constants can be done inline. */
1695 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1696 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1697 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1699 /* If defined, a C expression to compute the alignment for a static
1700 variable. TYPE is the data type, and ALIGN is the alignment that
1701 the object would ordinarily have. The value of this macro is used
1702 instead of that alignment to align the object.
1704 If this macro is not defined, then ALIGN is used.
1706 One use of this macro is to increase alignment of medium-size
1707 data to make it all fit in fewer cache lines. Another is to
1708 cause character arrays to be word-aligned so that `strcpy' calls
1709 that copy constants to character arrays can be done inline. */
1711 #undef DATA_ALIGNMENT
1712 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1713 ((((ALIGN) < BITS_PER_WORD) \
1714 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1715 || TREE_CODE (TYPE) == UNION_TYPE \
1716 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1719 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1721 #define PAD_VARARGS_DOWN (TARGET_64BIT \
1722 || mips_abi == ABI_MEABI \
1723 ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1725 /* Define this macro if an argument declared as `char' or `short' in a
1726 prototype should actually be passed as an `int'. In addition to
1727 avoiding errors in certain cases of mismatch, it also makes for
1728 better code on certain machines. */
1730 #define PROMOTE_PROTOTYPES 1
1732 /* Define if operations between registers always perform the operation
1733 on the full register even if a narrower mode is specified. */
1734 #define WORD_REGISTER_OPERATIONS
1736 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1737 will either zero-extend or sign-extend. The value of this macro should
1738 be the code that says which one of the two operations is implicitly
1741 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1742 moves. All other referces are zero extended. */
1743 #define LOAD_EXTEND_OP(MODE) \
1744 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1745 ? SIGN_EXTEND : ZERO_EXTEND)
1747 /* Define this macro if it is advisable to hold scalars in registers
1748 in a wider mode than that declared by the program. In such cases,
1749 the value is constrained to be within the bounds of the declared
1750 type, but kept valid in the wider mode. The signedness of the
1751 extension may differ from that of the type.
1753 We promote any value smaller than SImode up to SImode. We don't
1754 want to promote to DImode when in 64 bit mode, because that would
1755 prevent us from using the faster SImode multiply and divide
1758 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1759 if (GET_MODE_CLASS (MODE) == MODE_INT \
1760 && GET_MODE_SIZE (MODE) < 4) \
1763 /* Define this if function arguments should also be promoted using the above
1766 #define PROMOTE_FUNCTION_ARGS
1768 /* Likewise, if the function return value is promoted. */
1770 #define PROMOTE_FUNCTION_RETURN
1772 /* Standard register usage. */
1774 /* Number of actual hardware registers.
1775 The hardware registers are assigned numbers for the compiler
1776 from 0 to just below FIRST_PSEUDO_REGISTER.
1777 All registers that the compiler knows about must be given numbers,
1778 even those that are not normally considered general registers.
1780 On the Mips, we have 32 integer registers, 32 floating point
1781 registers, 8 condition code registers, and the special registers
1782 hi, lo, hilo, and rap. The 8 condition code registers are only
1783 used if mips_isa >= 4. The hilo register is only used in 64 bit
1784 mode. It represents a 64 bit value stored as two 32 bit values in
1785 the hi and lo registers; this is the result of the mult
1786 instruction. rap is a pointer to the stack where the return
1787 address reg ($31) was stored. This is needed for C++ exception
1790 #define FIRST_PSEUDO_REGISTER 76
1792 /* 1 for registers that have pervasive standard uses
1793 and are not available for the register allocator.
1795 On the MIPS, see conventions, page D-2 */
1797 #define FIXED_REGISTERS \
1799 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1800 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1801 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1802 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1803 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1807 /* 1 for registers not available across function calls.
1808 These must include the FIXED_REGISTERS and also any
1809 registers that can be used without being saved.
1810 The latter must include the registers where values are returned
1811 and the register where structure-value addresses are passed.
1812 Aside from that, you can include as many other registers as you like. */
1814 #define CALL_USED_REGISTERS \
1816 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1817 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1818 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1819 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1820 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1823 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1824 problem which makes CALL_USED_REGISTERS *always* include
1825 all the FIXED_REGISTERS. Until this problem has been
1826 resolved this macro can be used to overcome this situation.
1827 In particular, block_propagate() requires this list
1828 be acurate, or we can remove registers which should be live.
1829 This macro is used in regs_invalidated_by_call. */
1832 #define CALL_REALLY_USED_REGISTERS \
1833 { /* General registers. */ \
1834 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1835 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
1836 /* Floating-point registers. */ \
1837 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1838 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1840 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1843 /* Internal macros to classify a register number as to whether it's a
1844 general purpose register, a floating point register, a
1845 multiply/divide register, or a status register. */
1847 #define GP_REG_FIRST 0
1848 #define GP_REG_LAST 31
1849 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1850 #define GP_DBX_FIRST 0
1852 #define FP_REG_FIRST 32
1853 #define FP_REG_LAST 63
1854 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1855 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1857 #define MD_REG_FIRST 64
1858 #define MD_REG_LAST 66
1859 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1861 #define ST_REG_FIRST 67
1862 #define ST_REG_LAST 74
1863 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1865 #define RAP_REG_NUM 75
1867 #define AT_REGNUM (GP_REG_FIRST + 1)
1868 #define HI_REGNUM (MD_REG_FIRST + 0)
1869 #define LO_REGNUM (MD_REG_FIRST + 1)
1870 #define HILO_REGNUM (MD_REG_FIRST + 2)
1872 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1873 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1874 should be used instead. */
1875 #define FPSW_REGNUM ST_REG_FIRST
1877 #define GP_REG_P(REGNO) \
1878 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1879 #define M16_REG_P(REGNO) \
1880 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1881 #define FP_REG_P(REGNO) \
1882 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1883 #define MD_REG_P(REGNO) \
1884 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1885 #define ST_REG_P(REGNO) \
1886 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1888 /* Return number of consecutive hard regs needed starting at reg REGNO
1889 to hold something of mode MODE.
1890 This is ordinarily the length in words of a value of mode MODE
1891 but can be less for certain modes in special long registers.
1893 On the MIPS, all general registers are one word long. Except on
1894 the R4000 with the FR bit set, the floating point uses register
1895 pairs, with the second register not being allocable. */
1897 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1899 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1900 MODE. In 32 bit mode, require that DImode and DFmode be in even
1901 registers. For DImode, this makes some of the insns easier to
1902 write, since you don't have to worry about a DImode value in
1903 registers 3 & 4, producing a result in 4 & 5.
1905 To make the code simpler HARD_REGNO_MODE_OK now just references an
1906 array built in override_options. Because machmodes.h is not yet
1907 included before this file is processed, the MODE bound can't be
1910 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1912 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1913 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1915 /* Value is 1 if it is a good idea to tie two pseudo registers
1916 when one has mode MODE1 and one has mode MODE2.
1917 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1918 for any hard reg, then this must be 0 for correct output. */
1919 #define MODES_TIEABLE_P(MODE1, MODE2) \
1920 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1921 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1922 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1923 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1925 /* MIPS pc is not overloaded on a register. */
1926 /* #define PC_REGNUM xx */
1928 /* Register to use for pushing function arguments. */
1929 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1931 /* Offset from the stack pointer to the first available location. Use
1932 the default value zero. */
1933 /* #define STACK_POINTER_OFFSET 0 */
1935 /* Base register for access to local variables of the function. We
1936 pretend that the frame pointer is $1, and then eliminate it to
1937 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1938 a fixed register, and will not be used for anything else. */
1939 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1941 /* Temporary scratch register for use by the assembler. */
1942 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1944 /* $30 is not available on the mips16, so we use $17 as the frame
1946 #define HARD_FRAME_POINTER_REGNUM \
1947 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1949 /* Value should be nonzero if functions must have frame pointers.
1950 Zero means the frame pointer need not be set up (and parms
1951 may be accessed via the stack pointer) in functions that seem suitable.
1952 This is computed in `reload', in reload1.c. */
1953 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1955 /* Base register for access to arguments of the function. */
1956 #define ARG_POINTER_REGNUM GP_REG_FIRST
1958 /* Fake register that holds the address on the stack of the
1959 current function's return address. */
1960 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1962 /* Register in which static-chain is passed to a function. */
1963 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1965 /* If the structure value address is passed in a register, then
1966 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1967 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1969 /* If the structure value address is not passed in a register, define
1970 `STRUCT_VALUE' as an expression returning an RTX for the place
1971 where the address is passed. If it returns 0, the address is
1972 passed as an "invisible" first argument. */
1973 #define STRUCT_VALUE 0
1975 /* Mips registers used in prologue/epilogue code when the stack frame
1976 is larger than 32K bytes. These registers must come from the
1977 scratch register set, and not used for passing and returning
1978 arguments and any other information used in the calling sequence
1979 (such as pic). Must start at 12, since t0/t3 are parameter passing
1980 registers in the 64 bit ABI. */
1982 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1983 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1985 /* Define this macro if it is as good or better to call a constant
1986 function address than to call an address kept in a register. */
1987 #define NO_FUNCTION_CSE 1
1989 /* Define this macro if it is as good or better for a function to
1990 call itself with an explicit address than to call an address
1991 kept in a register. */
1992 #define NO_RECURSIVE_FUNCTION_CSE 1
1994 /* The register number of the register used to address a table of
1995 static data addresses in memory. In some cases this register is
1996 defined by a processor's "application binary interface" (ABI).
1997 When this macro is defined, RTL is generated for this register
1998 once, as with the stack pointer and frame pointer registers. If
1999 this macro is not defined, it is up to the machine-dependent
2000 files to allocate such a register (if necessary). */
2001 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
2003 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
2005 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
2006 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
2007 isn't always called for static inline functions. */
2008 #define INIT_EXPANDERS \
2010 embedded_pic_fnaddr_rtx = NULL; \
2011 mips16_gp_pseudo_rtx = NULL; \
2014 /* Define the classes of registers for register constraints in the
2015 machine description. Also define ranges of constants.
2017 One of the classes must always be named ALL_REGS and include all hard regs.
2018 If there is more than one class, another class must be named NO_REGS
2019 and contain no registers.
2021 The name GENERAL_REGS must be the name of a class (or an alias for
2022 another name such as ALL_REGS). This is the class of registers
2023 that is allowed by "g" or "r" in a register constraint.
2024 Also, registers outside this class are allocated only when
2025 instructions express preferences for them.
2027 The classes must be numbered in nondecreasing order; that is,
2028 a larger-numbered class must never be contained completely
2029 in a smaller-numbered class.
2031 For any two classes, it is very desirable that there be another
2032 class that represents their union. */
2036 NO_REGS, /* no registers in set */
2037 M16_NA_REGS, /* mips16 regs not used to pass args */
2038 M16_REGS, /* mips16 directly accessible registers */
2039 T_REG, /* mips16 T register ($24) */
2040 M16_T_REGS, /* mips16 registers plus T register */
2041 GR_REGS, /* integer registers */
2042 FP_REGS, /* floating point registers */
2043 HI_REG, /* hi register */
2044 LO_REG, /* lo register */
2045 HILO_REG, /* hilo register pair for 64 bit mode mult */
2046 MD_REGS, /* multiply/divide registers (hi/lo) */
2047 HI_AND_GR_REGS, /* union classes */
2051 ST_REGS, /* status registers (fp status) */
2052 ALL_REGS, /* all registers */
2053 LIM_REG_CLASSES /* max value + 1 */
2056 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2058 #define GENERAL_REGS GR_REGS
2060 /* An initializer containing the names of the register classes as C
2061 string constants. These names are used in writing some of the
2064 #define REG_CLASS_NAMES \
2079 "HILO_AND_GR_REGS", \
2085 /* An initializer containing the contents of the register classes,
2086 as integers which are bit masks. The Nth integer specifies the
2087 contents of class N. The way the integer MASK is interpreted is
2088 that register R is in the class if `MASK & (1 << R)' is 1.
2090 When the machine has more than 32 registers, an integer does not
2091 suffice. Then the integers are replaced by sub-initializers,
2092 braced groupings containing several integers. Each
2093 sub-initializer must be suitable as an initializer for the type
2094 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2096 #define REG_CLASS_CONTENTS \
2098 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2099 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2100 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2101 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2102 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2103 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
2104 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
2105 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
2106 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
2107 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
2108 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
2109 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
2110 { 0xffffffff, 0x00000000, 0x00000002 }, \
2111 { 0xffffffff, 0x00000000, 0x00000004 }, \
2112 { 0x00000000, 0xffffffff, 0x00000001 }, \
2113 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
2114 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
2118 /* A C expression whose value is a register class containing hard
2119 register REGNO. In general there is more that one such class;
2120 choose a class which is "minimal", meaning that no smaller class
2121 also contains the register. */
2123 extern const enum reg_class mips_regno_to_class[];
2125 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2127 /* A macro whose definition is the name of the class to which a
2128 valid base register must belong. A base register is one used in
2129 an address which is the register value plus a displacement. */
2131 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2133 /* A macro whose definition is the name of the class to which a
2134 valid index register must belong. An index register is one used
2135 in an address where its value is either multiplied by a scale
2136 factor or added to another register (as well as added to a
2139 #define INDEX_REG_CLASS NO_REGS
2141 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2142 registers explicitly used in the rtl to be used as spill registers
2143 but prevents the compiler from extending the lifetime of these
2146 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2148 /* This macro is used later on in the file. */
2149 #define GR_REG_CLASS_P(CLASS) \
2150 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2151 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2153 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2154 is the default value (allocate the registers in numeric order). We
2155 define it just so that we can override it for the mips16 target in
2156 ORDER_REGS_FOR_LOCAL_ALLOC. */
2158 #define REG_ALLOC_ORDER \
2159 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2160 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2161 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2162 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2163 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
2166 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2167 to be rearranged based on a particular function. On the mips16, we
2168 want to allocate $24 (T_REG) before other registers for
2169 instructions for which it is possible. */
2171 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2173 /* REGISTER AND CONSTANT CLASSES */
2175 /* Get reg_class from a letter such as appears in the machine
2178 DEFINED REGISTER CLASSES:
2180 'd' General (aka integer) registers
2181 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2182 'y' General registers (in both mips16 and non mips16 mode)
2183 'e' mips16 non argument registers (M16_NA_REGS)
2184 't' mips16 temporary register ($24)
2185 'f' Floating point registers
2188 'x' Multiply/divide registers
2190 'z' FP Status register
2191 'b' All registers */
2193 extern enum reg_class mips_char_to_class[256];
2195 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2197 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2198 string can be used to stand for particular ranges of immediate
2199 operands. This macro defines what the ranges are. C is the
2200 letter, and VALUE is a constant value. Return 1 if VALUE is
2201 in the range specified by C. */
2205 `I' is used for the range of constants an arithmetic insn can
2206 actually contain (16 bits signed integers).
2208 `J' is used for the range which is just zero (ie, $r0).
2210 `K' is used for the range of constants a logical insn can actually
2211 contain (16 bit zero-extended integers).
2213 `L' is used for the range of constants that be loaded with lui
2214 (ie, the bottom 16 bits are zero).
2216 `M' is used for the range of constants that take two words to load
2217 (ie, not matched by `I', `K', and `L').
2219 `N' is used for negative 16 bit constants other than -65536.
2221 `O' is a 15 bit signed integer.
2223 `P' is used for positive 16 bit constants. */
2225 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2226 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2228 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2229 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
2230 : (C) == 'J' ? ((VALUE) == 0) \
2231 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
2232 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2233 && (((VALUE) & ~2147483647) == 0 \
2234 || ((VALUE) & ~2147483647) == ~2147483647)) \
2235 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2236 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2237 && (((VALUE) & 0x0000ffff) != 0 \
2238 || (((VALUE) & ~2147483647) != 0 \
2239 && ((VALUE) & ~2147483647) != ~2147483647))) \
2240 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2241 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2242 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2245 /* Similar, but for floating constants, and defining letters G and H.
2246 Here VALUE is the CONST_DOUBLE rtx itself. */
2250 'G' : Floating point 0 */
2252 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2254 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2256 /* Letters in the range `Q' through `U' may be defined in a
2257 machine-dependent fashion to stand for arbitrary operand types.
2258 The machine description macro `EXTRA_CONSTRAINT' is passed the
2259 operand as its first argument and the constraint letter as its
2262 `Q' is for mips16 GP relative constants
2263 `R' is for memory references which take 1 word for the instruction.
2264 `S' is for references to extern items which are PIC for OSF/rose.
2265 `T' is for memory addresses that can be used to load two words. */
2267 #define EXTRA_CONSTRAINT(OP,CODE) \
2268 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2269 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2270 && mips16_gp_offset_p (OP)) \
2271 : (GET_CODE (OP) != MEM) ? FALSE \
2272 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2273 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
2274 && HALF_PIC_ADDRESS_P (OP)) \
2277 /* Given an rtx X being reloaded into a reg required to be
2278 in class CLASS, return the class of reg to actually use.
2279 In general this is just CLASS; but on some machines
2280 in some cases it is preferable to use a more restrictive class. */
2282 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2283 ((CLASS) != ALL_REGS \
2284 ? (! TARGET_MIPS16 \
2286 : ((CLASS) != GR_REGS \
2289 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2290 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2291 ? (TARGET_SOFT_FLOAT \
2292 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2294 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2295 || GET_MODE (X) == VOIDmode) \
2296 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2299 /* Certain machines have the property that some registers cannot be
2300 copied to some other registers without using memory. Define this
2301 macro on those machines to be a C expression that is non-zero if
2302 objects of mode MODE in registers of CLASS1 can only be copied to
2303 registers of class CLASS2 by storing a register of CLASS1 into
2304 memory and loading that memory location into a register of CLASS2.
2306 Do not define this macro if its value would always be zero. */
2308 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2309 ((!TARGET_DEBUG_H_MODE \
2310 && GET_MODE_CLASS (MODE) == MODE_INT \
2311 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2312 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2313 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2314 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2315 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2317 /* The HI and LO registers can only be reloaded via the general
2318 registers. Condition code registers can only be loaded to the
2319 general registers, and from the floating point registers. */
2321 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2322 mips_secondary_reload_class (CLASS, MODE, X, 1)
2323 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2324 mips_secondary_reload_class (CLASS, MODE, X, 0)
2326 /* Return the maximum number of consecutive registers
2327 needed to represent mode MODE in a register of class CLASS. */
2329 #define CLASS_UNITS(mode, size) \
2330 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2332 #define CLASS_MAX_NREGS(CLASS, MODE) \
2333 ((CLASS) == FP_REGS \
2335 ? CLASS_UNITS (MODE, 8) \
2336 : 2 * CLASS_UNITS (MODE, 8)) \
2337 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2339 /* If defined, gives a class of registers that cannot be used as the
2340 operand of a SUBREG that changes the mode of the object illegally.
2341 When FP regs are larger than integer regs... Er, anyone remember what
2344 In little-endian mode, the hi-lo registers are numbered backwards,
2345 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
2346 word as intended. */
2348 #define CLASS_CANNOT_CHANGE_MODE \
2349 (TARGET_BIG_ENDIAN \
2350 ? (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS) \
2351 : (TARGET_FLOAT64 && ! TARGET_64BIT ? HI_AND_FP_REGS : HI_REG))
2353 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2355 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2356 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2358 /* Stack layout; function entry, exit and calling. */
2360 /* Define this if pushing a word on the stack
2361 makes the stack pointer a smaller address. */
2362 #define STACK_GROWS_DOWNWARD
2364 /* Define this if the nominal address of the stack frame
2365 is at the high-address end of the local variables;
2366 that is, each additional local variable allocated
2367 goes at a more negative offset in the frame. */
2368 /* #define FRAME_GROWS_DOWNWARD */
2370 /* Offset within stack frame to start allocating local variables at.
2371 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2372 first local allocated. Otherwise, it is the offset to the BEGINNING
2373 of the first local allocated. */
2374 #define STARTING_FRAME_OFFSET \
2375 (current_function_outgoing_args_size \
2376 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2378 /* Offset from the stack pointer register to an item dynamically
2379 allocated on the stack, e.g., by `alloca'.
2381 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2382 length of the outgoing arguments. The default is correct for most
2383 machines. See `function.c' for details.
2385 The MIPS ABI states that functions which dynamically allocate the
2386 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2387 we are trying to create a second frame pointer to the function, so
2388 allocate some stack space to make it happy.
2390 However, the linker currently complains about linking any code that
2391 dynamically allocates stack space, and there seems to be a bug in
2392 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2395 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2396 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2397 ? 4*UNITS_PER_WORD \
2398 : current_function_outgoing_args_size)
2401 /* The return address for the current frame is in r31 is this is a leaf
2402 function. Otherwise, it is on the stack. It is at a variable offset
2403 from sp/fp/ap, so we define a fake hard register rap which is a
2404 poiner to the return address on the stack. This always gets eliminated
2405 during reload to be either the frame pointer or the stack pointer plus
2408 /* ??? This definition fails for leaf functions. There is currently no
2409 general solution for this problem. */
2411 /* ??? There appears to be no way to get the return address of any previous
2412 frame except by disassembling instructions in the prologue/epilogue.
2413 So currently we support only the current frame. */
2415 #define RETURN_ADDR_RTX(count, frame) \
2417 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2420 /* Structure to be filled in by compute_frame_size with register
2421 save masks, and offsets for the current function. */
2423 struct mips_frame_info
2425 long total_size; /* # bytes that the entire frame takes up */
2426 long var_size; /* # bytes that variables take up */
2427 long args_size; /* # bytes that outgoing arguments take up */
2428 long extra_size; /* # bytes of extra gunk */
2429 int gp_reg_size; /* # bytes needed to store gp regs */
2430 int fp_reg_size; /* # bytes needed to store fp regs */
2431 long mask; /* mask of saved gp registers */
2432 long fmask; /* mask of saved fp registers */
2433 long gp_save_offset; /* offset from vfp to store gp registers */
2434 long fp_save_offset; /* offset from vfp to store fp registers */
2435 long gp_sp_offset; /* offset from new sp to store gp registers */
2436 long fp_sp_offset; /* offset from new sp to store fp registers */
2437 int initialized; /* != 0 if frame size already calculated */
2438 int num_gp; /* number of gp registers saved */
2439 int num_fp; /* number of fp registers saved */
2440 long insns_len; /* length of insns; mips16 only */
2443 extern struct mips_frame_info current_frame_info;
2445 /* If defined, this macro specifies a table of register pairs used to
2446 eliminate unneeded registers that point into the stack frame. If
2447 it is not defined, the only elimination attempted by the compiler
2448 is to replace references to the frame pointer with references to
2451 The definition of this macro is a list of structure
2452 initializations, each of which specifies an original and
2453 replacement register.
2455 On some machines, the position of the argument pointer is not
2456 known until the compilation is completed. In such a case, a
2457 separate hard register must be used for the argument pointer.
2458 This register can be eliminated by replacing it with either the
2459 frame pointer or the argument pointer, depending on whether or not
2460 the frame pointer has been eliminated.
2462 In this case, you might specify:
2463 #define ELIMINABLE_REGS \
2464 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2465 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2466 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2468 Note that the elimination of the argument pointer with the stack
2469 pointer is specified first since that is the preferred elimination.
2471 The eliminations to $17 are only used on the mips16. See the
2472 definition of HARD_FRAME_POINTER_REGNUM. */
2474 #define ELIMINABLE_REGS \
2475 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2476 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2477 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2478 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2479 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2480 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2481 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2482 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2483 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2484 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2486 /* A C expression that returns non-zero if the compiler is allowed to
2487 try to replace register number FROM-REG with register number
2488 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2489 defined, and will usually be the constant 1, since most of the
2490 cases preventing register elimination are things that the compiler
2491 already knows about.
2493 When not in mips16 and mips64, we can always eliminate to the
2494 frame pointer. We can eliminate to the stack pointer unless
2495 a frame pointer is needed. In mips16 mode, we need a frame
2496 pointer for a large frame; otherwise, reload may be unable
2497 to compute the address of a local variable, since there is
2498 no way to add a large constant to the stack pointer
2499 without using a temporary register.
2501 In mips16, for some instructions (eg lwu), we can't eliminate the
2502 frame pointer for the stack pointer. These instructions are
2503 only generated in TARGET_64BIT mode.
2506 #define CAN_ELIMINATE(FROM, TO) \
2507 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2508 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2509 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2510 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2511 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2512 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2513 && (! TARGET_MIPS16 \
2514 || compute_frame_size (get_frame_size ()) < 32768)))))
2516 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2517 specifies the initial difference between the specified pair of
2518 registers. This macro must be defined if `ELIMINABLE_REGS' is
2521 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2522 { compute_frame_size (get_frame_size ()); \
2523 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2524 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2525 (OFFSET) = - current_function_outgoing_args_size; \
2526 else if ((FROM) == FRAME_POINTER_REGNUM) \
2528 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2529 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2530 (OFFSET) = (current_frame_info.total_size \
2531 - current_function_outgoing_args_size \
2532 - ((mips_abi != ABI_32 \
2533 && mips_abi != ABI_O64 \
2534 && mips_abi != ABI_EABI) \
2535 ? current_function_pretend_args_size \
2537 else if ((FROM) == ARG_POINTER_REGNUM) \
2538 (OFFSET) = (current_frame_info.total_size \
2539 - ((mips_abi != ABI_32 \
2540 && mips_abi != ABI_O64 \
2541 && mips_abi != ABI_EABI) \
2542 ? current_function_pretend_args_size \
2544 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2545 so we must add 4 bytes to the offset to get the right value. */ \
2546 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2548 if (leaf_function_p ()) \
2550 else (OFFSET) = current_frame_info.gp_sp_offset \
2551 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2552 * (BYTES_BIG_ENDIAN != 0)); \
2558 /* If we generate an insn to push BYTES bytes,
2559 this says how many the stack pointer really advances by.
2560 On the VAX, sp@- in a byte insn really pushes a word. */
2562 /* #define PUSH_ROUNDING(BYTES) 0 */
2564 /* If defined, the maximum amount of space required for outgoing
2565 arguments will be computed and placed into the variable
2566 `current_function_outgoing_args_size'. No space will be pushed
2567 onto the stack for each call; instead, the function prologue
2568 should increase the stack frame size by this amount.
2570 It is not proper to define both `PUSH_ROUNDING' and
2571 `ACCUMULATE_OUTGOING_ARGS'. */
2572 #define ACCUMULATE_OUTGOING_ARGS 1
2574 /* Offset from the argument pointer register to the first argument's
2575 address. On some machines it may depend on the data type of the
2578 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2579 the first argument's address.
2581 On the MIPS, we must skip the first argument position if we are
2582 returning a structure or a union, to account for its address being
2583 passed in $4. However, at the current time, this produces a compiler
2584 that can't bootstrap, so comment it out for now. */
2587 #define FIRST_PARM_OFFSET(FNDECL) \
2589 && TREE_TYPE (FNDECL) != 0 \
2590 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2591 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2592 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2596 #define FIRST_PARM_OFFSET(FNDECL) 0
2599 /* When a parameter is passed in a register, stack space is still
2600 allocated for it. For the MIPS, stack space must be allocated, cf
2601 Asm Lang Prog Guide page 7-8.
2603 BEWARE that some space is also allocated for non existing arguments
2604 in register. In case an argument list is of form GF used registers
2605 are a0 (a2,a3), but we should push over a1... */
2607 #define REG_PARM_STACK_SPACE(FNDECL) \
2608 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2610 /* Define this if it is the responsibility of the caller to
2611 allocate the area reserved for arguments passed in registers.
2612 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2613 of this macro is to determine whether the space is included in
2614 `current_function_outgoing_args_size'. */
2615 #define OUTGOING_REG_PARM_STACK_SPACE
2617 /* Align stack frames on 64 bits (Double Word ). */
2618 #ifndef STACK_BOUNDARY
2619 #define STACK_BOUNDARY 64
2622 /* Make sure 4 words are always allocated on the stack. */
2624 #ifndef STACK_ARGS_ADJUST
2625 #define STACK_ARGS_ADJUST(SIZE) \
2627 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2628 SIZE.constant = 4 * UNITS_PER_WORD; \
2633 /* A C expression that should indicate the number of bytes of its
2634 own arguments that a function pops on returning, or 0
2635 if the function pops no arguments and the caller must therefore
2636 pop them all after the function returns.
2638 FUNDECL is the declaration node of the function (as a tree).
2640 FUNTYPE is a C variable whose value is a tree node that
2641 describes the function in question. Normally it is a node of
2642 type `FUNCTION_TYPE' that describes the data type of the function.
2643 From this it is possible to obtain the data types of the value
2644 and arguments (if known).
2646 When a call to a library function is being considered, FUNTYPE
2647 will contain an identifier node for the library function. Thus,
2648 if you need to distinguish among various library functions, you
2649 can do so by their names. Note that "library function" in this
2650 context means a function used to perform arithmetic, whose name
2651 is known specially in the compiler and was not mentioned in the
2652 C code being compiled.
2654 STACK-SIZE is the number of bytes of arguments passed on the
2655 stack. If a variable number of bytes is passed, it is zero, and
2656 argument popping will always be the responsibility of the
2657 calling function. */
2659 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2662 /* Symbolic macros for the registers used to return integer and floating
2665 #define GP_RETURN (GP_REG_FIRST + 2)
2666 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2668 /* Symbolic macros for the first/last argument registers. */
2670 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2671 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2672 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2673 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2675 #define MAX_ARGS_IN_REGISTERS 4
2677 /* Define how to find the value returned by a library function
2678 assuming the value has mode MODE. Because we define
2679 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2680 PROMOTE_MODE does. */
2682 #define LIBCALL_VALUE(MODE) \
2684 ((GET_MODE_CLASS (MODE) != MODE_INT \
2685 || GET_MODE_SIZE (MODE) >= 4) \
2688 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2689 && (! TARGET_SINGLE_FLOAT \
2690 || GET_MODE_SIZE (MODE) <= 4)) \
2694 /* Define how to find the value returned by a function.
2695 VALTYPE is the data type of the value (as a tree).
2696 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2697 otherwise, FUNC is 0. */
2699 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2702 /* 1 if N is a possible register number for a function value.
2703 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2704 Currently, R2 and F0 are only implemented here (C has no complex type) */
2706 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2708 /* 1 if N is a possible register number for function argument passing.
2709 We have no FP argument registers when soft-float. When FP registers
2710 are 32 bits, we can't directly reference the odd numbered ones. */
2712 #define FUNCTION_ARG_REGNO_P(N) \
2713 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2714 || ((! TARGET_SOFT_FLOAT \
2715 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2716 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2717 && ! fixed_regs[N]))
2719 /* A C expression which can inhibit the returning of certain function
2720 values in registers, based on the type of value. A nonzero value says
2721 to return the function value in memory, just as large structures are
2722 always returned. Here TYPE will be a C expression of type
2723 `tree', representing the data type of the value.
2725 Note that values of mode `BLKmode' must be explicitly
2726 handled by this macro. Also, the option `-fpcc-struct-return'
2727 takes effect regardless of this macro. On most systems, it is
2728 possible to leave the macro undefined; this causes a default
2729 definition to be used, whose value is the constant 1 for BLKmode
2730 values, and 0 otherwise.
2732 GCC normally converts 1 byte structures into chars, 2 byte
2733 structs into shorts, and 4 byte structs into ints, and returns
2734 them this way. Defining the following macro overrides this,
2735 to give us MIPS cc compatibility. */
2737 #define RETURN_IN_MEMORY(TYPE) \
2738 (TYPE_MODE (TYPE) == BLKmode)
2741 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2744 /* Define a data type for recording info about an argument list
2745 during the scan of that argument list. This data type should
2746 hold all necessary information about the function itself
2747 and about the args processed so far, enough to enable macros
2748 such as FUNCTION_ARG to determine where the next arg should go.
2750 On the mips16, we need to keep track of which floating point
2751 arguments were passed in general registers, but would have been
2752 passed in the FP regs if this were a 32 bit function, so that we
2753 can move them to the FP regs if we wind up calling a 32 bit
2754 function. We record this information in fp_code, encoded in base
2755 four. A zero digit means no floating point argument, a one digit
2756 means an SFmode argument, and a two digit means a DFmode argument,
2757 and a three digit is not used. The low order digit is the first
2758 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2759 an SFmode argument. ??? A more sophisticated approach will be
2760 needed if MIPS_ABI != ABI_32. */
2762 typedef struct mips_args {
2763 int gp_reg_found; /* whether a gp register was found yet */
2764 unsigned int arg_number; /* argument number */
2765 unsigned int arg_words; /* # total words the arguments take */
2766 unsigned int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2767 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2768 int fp_code; /* Mode of FP arguments (mips16) */
2769 unsigned int num_adjusts; /* number of adjustments made */
2770 /* Adjustments made to args pass in regs. */
2771 /* ??? The size is doubled to work around a
2772 bug in the code that sets the adjustments
2774 int prototype; /* True if the function has a prototype. */
2775 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2778 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2779 for a call to a function whose data type is FNTYPE.
2780 For a library call, FNTYPE is 0.
2784 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2785 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2787 /* Update the data in CUM to advance over an argument
2788 of mode MODE and data type TYPE.
2789 (TYPE is null for libcalls where that information may not be available.) */
2791 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2792 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2794 /* Determine where to put an argument to a function.
2795 Value is zero to push the argument on the stack,
2796 or a hard register in which to store the argument.
2798 MODE is the argument's machine mode.
2799 TYPE is the data type of the argument (as a tree).
2800 This is null for libcalls where that information may
2802 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2803 the preceding args and about the function being called.
2804 NAMED is nonzero if this argument is a named parameter
2805 (otherwise it is an extra parameter matching an ellipsis). */
2807 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2808 function_arg( &CUM, MODE, TYPE, NAMED)
2810 /* For an arg passed partly in registers and partly in memory,
2811 this is the number of registers used.
2812 For args passed entirely in registers or entirely in memory, zero. */
2814 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2815 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2817 /* If defined, a C expression that gives the alignment boundary, in
2818 bits, of an argument with the specified mode and type. If it is
2819 not defined, `PARM_BOUNDARY' is used for all arguments. */
2821 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2823 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2825 : TYPE_ALIGN(TYPE)) \
2826 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2828 : GET_MODE_ALIGNMENT(MODE)))
2831 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2833 #define MUST_SAVE_REGISTER(regno) \
2834 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2835 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2836 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2838 /* ALIGN FRAMES on double word boundaries */
2839 #ifndef MIPS_STACK_ALIGN
2840 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2844 /* Define the `__builtin_va_list' type for the ABI. */
2845 #define BUILD_VA_LIST_TYPE(VALIST) \
2846 (VALIST) = mips_build_va_list ()
2848 /* Implement `va_start' for varargs and stdarg. */
2849 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2850 mips_va_start (stdarg, valist, nextarg)
2852 /* Implement `va_arg'. */
2853 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2854 mips_va_arg (valist, type)
2856 /* Output assembler code to FILE to increment profiler label # LABELNO
2857 for profiling a function entry. */
2859 #define FUNCTION_PROFILER(FILE, LABELNO) \
2861 if (TARGET_MIPS16) \
2862 sorry ("mips16 function profiling"); \
2863 fprintf (FILE, "\t.set\tnoat\n"); \
2864 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2865 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2867 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2868 TARGET_64BIT ? "dsubu" : "subu", \
2869 reg_names[STACK_POINTER_REGNUM], \
2870 reg_names[STACK_POINTER_REGNUM], \
2871 Pmode == DImode ? 16 : 8); \
2872 fprintf (FILE, "\tjal\t_mcount\n"); \
2873 fprintf (FILE, "\t.set\tat\n"); \
2876 /* Define this macro if the code for function profiling should come
2877 before the function prologue. Normally, the profiling code comes
2880 /* #define PROFILE_BEFORE_PROLOGUE */
2882 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2883 the stack pointer does not matter. The value is tested only in
2884 functions that have frame pointers.
2885 No definition is equivalent to always zero. */
2887 #define EXIT_IGNORE_STACK 1
2890 /* A C statement to output, on the stream FILE, assembler code for a
2891 block of data that contains the constant parts of a trampoline.
2892 This code should not include a label--the label is taken care of
2895 #define TRAMPOLINE_TEMPLATE(STREAM) \
2897 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2898 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2899 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2900 if (Pmode == DImode) \
2902 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2903 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2907 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2908 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2910 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2911 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2912 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2913 if (Pmode == DImode) \
2915 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2916 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2920 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2921 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2925 /* A C expression for the size in bytes of the trampoline, as an
2928 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2930 /* Alignment required for trampolines, in bits. */
2932 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2934 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2935 program and data caches. */
2937 #ifndef CACHE_FLUSH_FUNC
2938 #define CACHE_FLUSH_FUNC "_flush_cache"
2941 /* A C statement to initialize the variable parts of a trampoline.
2942 ADDR is an RTX for the address of the trampoline; FNADDR is an
2943 RTX for the address of the nested function; STATIC_CHAIN is an
2944 RTX for the static chain value that should be passed to the
2945 function when it is called. */
2947 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2950 if (Pmode == DImode) \
2952 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2953 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2957 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2958 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2961 /* Flush both caches. We need to flush the data cache in case \
2962 the system has a write-back cache. */ \
2963 /* ??? Should check the return value for errors. */ \
2964 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2965 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2966 0, VOIDmode, 3, addr, Pmode, \
2967 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2968 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2971 /* Addressing modes, and classification of registers for them. */
2973 /* #define HAVE_POST_INCREMENT 0 */
2974 /* #define HAVE_POST_DECREMENT 0 */
2976 /* #define HAVE_PRE_DECREMENT 0 */
2977 /* #define HAVE_PRE_INCREMENT 0 */
2979 /* These assume that REGNO is a hard or pseudo reg number.
2980 They give nonzero only if REGNO is a hard reg of the suitable class
2981 or a pseudo reg currently allocated to a suitable hard reg.
2982 These definitions are NOT overridden anywhere. */
2984 #define BASE_REG_P(regno, mode) \
2986 ? (M16_REG_P (regno) \
2987 || (regno) == FRAME_POINTER_REGNUM \
2988 || (regno) == ARG_POINTER_REGNUM \
2989 || ((regno) == STACK_POINTER_REGNUM \
2990 && (GET_MODE_SIZE (mode) == 4 \
2991 || GET_MODE_SIZE (mode) == 8))) \
2994 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2995 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2998 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2999 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
3001 #define REGNO_OK_FOR_INDEX_P(regno) 0
3002 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3003 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3005 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3006 and check its validity for a certain class.
3007 We have two alternate definitions for each of them.
3008 The usual definition accepts all pseudo regs; the other rejects them all.
3009 The symbol REG_OK_STRICT causes the latter definition to be used.
3011 Most source files want to accept pseudo regs in the hope that
3012 they will get allocated to the class that the insn wants them to be in.
3013 Some source files that are used after register allocation
3014 need to be strict. */
3016 #ifndef REG_OK_STRICT
3017 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3018 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3020 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3021 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3024 #define REG_OK_FOR_INDEX_P(X) 0
3027 /* Maximum number of registers that can appear in a valid memory address. */
3029 #define MAX_REGS_PER_ADDRESS 1
3031 /* A C compound statement with a conditional `goto LABEL;' executed
3032 if X (an RTX) is a legitimate memory address on the target
3033 machine for a memory operand of mode MODE.
3035 It usually pays to define several simpler macros to serve as
3036 subroutines for this one. Otherwise it may be too complicated
3039 This macro must exist in two variants: a strict variant and a
3040 non-strict one. The strict variant is used in the reload pass.
3041 It must be defined so that any pseudo-register that has not been
3042 allocated a hard register is considered a memory reference. In
3043 contexts where some kind of register is required, a
3044 pseudo-register with no hard register must be rejected.
3046 The non-strict variant is used in other passes. It must be
3047 defined to accept all pseudo-registers in every context where
3048 some kind of register is required.
3050 Compiler source files that want to use the strict variant of
3051 this macro define the macro `REG_OK_STRICT'. You should use an
3052 `#ifdef REG_OK_STRICT' conditional to define the strict variant
3053 in that case and the non-strict variant otherwise.
3055 Typically among the subroutines used to define
3056 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
3057 acceptable registers for various purposes (one for base
3058 registers, one for index registers, and so on). Then only these
3059 subroutine macros need have two variants; the higher levels of
3060 macros may be the same whether strict or not.
3062 Normally, constant addresses which are the sum of a `symbol_ref'
3063 and an integer are stored inside a `const' RTX to mark them as
3064 constant. Therefore, there is no need to recognize such sums
3065 specifically as legitimate addresses. Normally you would simply
3066 recognize any `const' as legitimate.
3068 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
3069 constant sums that are not marked with `const'. It assumes
3070 that a naked `plus' indicates indexing. If so, then you *must*
3071 reject such naked constant sums as illegitimate addresses, so
3072 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
3074 On some machines, whether a symbolic address is legitimate
3075 depends on the section that the address refers to. On these
3076 machines, define the macro `ENCODE_SECTION_INFO' to store the
3077 information into the `symbol_ref', and then check for it here.
3078 When you see a `const', you will have to look inside it to find
3079 the `symbol_ref' in order to determine the section. */
3082 #define GO_PRINTF(x) fprintf(stderr, (x))
3083 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3084 #define GO_DEBUG_RTX(x) debug_rtx(x)
3087 #define GO_PRINTF(x)
3088 #define GO_PRINTF2(x,y)
3089 #define GO_DEBUG_RTX(x)
3092 #ifdef REG_OK_STRICT
3093 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3095 if (mips_legitimate_address_p (MODE, X, 1)) \
3099 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3101 if (mips_legitimate_address_p (MODE, X, 0)) \
3106 /* A C expression that is 1 if the RTX X is a constant which is a
3107 valid address. This is defined to be the same as `CONSTANT_P (X)',
3108 but rejecting CONST_DOUBLE. */
3109 /* When pic, we must reject addresses of the form symbol+large int.
3110 This is because an instruction `sw $4,s+70000' needs to be converted
3111 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
3112 assembler would use $at as a temp to load in the large offset. In this
3113 case $at is already in use. We convert such problem addresses to
3114 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
3115 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
3116 #define CONSTANT_ADDRESS_P(X) \
3117 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
3118 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
3119 || (GET_CODE (X) == CONST \
3120 && ! (flag_pic && pic_address_needs_scratch (X)) \
3121 && (mips_abi == ABI_32 \
3122 || mips_abi == ABI_O64 \
3123 || mips_abi == ABI_EABI))) \
3124 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
3126 /* Define this, so that when PIC, reload won't try to reload invalid
3127 addresses which require two reload registers. */
3129 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
3131 /* Nonzero if the constant value X is a legitimate general operand.
3132 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3134 At present, GAS doesn't understand li.[sd], so don't allow it
3135 to be generated at present. Also, the MIPS assembler does not
3136 grok li.d Infinity. */
3138 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3139 Note that the Irix 6 assembler problem may already be fixed.
3140 Note also that the GET_CODE (X) == CONST test catches the mips16
3141 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3142 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3143 ABI_64 to work together, we'll need to fix this. */
3144 #define LEGITIMATE_CONSTANT_P(X) \
3145 ((GET_CODE (X) != CONST_DOUBLE \
3146 || mips_const_double_ok (X, GET_MODE (X))) \
3147 && ! (GET_CODE (X) == CONST \
3149 && (mips_abi == ABI_N32 \
3150 || mips_abi == ABI_64)) \
3151 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3153 /* A C compound statement that attempts to replace X with a valid
3154 memory address for an operand of mode MODE. WIN will be a C
3155 statement label elsewhere in the code; the macro definition may
3158 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3160 to avoid further processing if the address has become legitimate.
3162 X will always be the result of a call to `break_out_memory_refs',
3163 and OLDX will be the operand that was given to that function to
3166 The code generated by this macro should not alter the
3167 substructure of X. If it transforms X into a more legitimate
3168 form, it should assign X (which will always be a C variable) a
3171 It is not necessary for this macro to come up with a legitimate
3172 address. The compiler has standard ways of doing so in all
3173 cases. In fact, it is safe for this macro to do nothing. But
3174 often a machine-dependent strategy can generate better code.
3176 For the MIPS, transform:
3178 memory(X + <large int>)
3182 Y = <large int> & ~0x7fff;
3184 memory (Z + (<large int> & 0x7fff));
3186 This is for CSE to find several similar references, and only use one Z.
3188 When PIC, convert addresses of the form memory (symbol+large int) to
3189 memory (reg+large int). */
3192 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3194 register rtx xinsn = (X); \
3196 if (TARGET_DEBUG_B_MODE) \
3198 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3199 GO_DEBUG_RTX (xinsn); \
3202 if (mips_split_addresses && mips_check_split (X, MODE)) \
3204 /* ??? Is this ever executed? */ \
3205 X = gen_rtx_LO_SUM (Pmode, \
3206 copy_to_mode_reg (Pmode, \
3207 gen_rtx (HIGH, Pmode, X)), \
3212 if (GET_CODE (xinsn) == CONST \
3213 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3214 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3215 || (mips_abi != ABI_32 \
3216 && mips_abi != ABI_O64 \
3217 && mips_abi != ABI_EABI))) \
3219 rtx ptr_reg = gen_reg_rtx (Pmode); \
3220 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3222 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3224 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3225 if (SMALL_INT (constant)) \
3227 /* Otherwise we fall through so the code below will fix the \
3232 if (GET_CODE (xinsn) == PLUS) \
3234 register rtx xplus0 = XEXP (xinsn, 0); \
3235 register rtx xplus1 = XEXP (xinsn, 1); \
3236 register enum rtx_code code0 = GET_CODE (xplus0); \
3237 register enum rtx_code code1 = GET_CODE (xplus1); \
3239 if (code0 != REG && code1 == REG) \
3241 xplus0 = XEXP (xinsn, 1); \
3242 xplus1 = XEXP (xinsn, 0); \
3243 code0 = GET_CODE (xplus0); \
3244 code1 = GET_CODE (xplus1); \
3247 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3248 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3250 rtx int_reg = gen_reg_rtx (Pmode); \
3251 rtx ptr_reg = gen_reg_rtx (Pmode); \
3253 emit_move_insn (int_reg, \
3254 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3256 emit_insn (gen_rtx_SET (VOIDmode, \
3258 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3260 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3265 if (TARGET_DEBUG_B_MODE) \
3266 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3270 /* A C statement or compound statement with a conditional `goto
3271 LABEL;' executed if memory address X (an RTX) can have different
3272 meanings depending on the machine mode of the memory reference it
3275 Autoincrement and autodecrement addresses typically have
3276 mode-dependent effects because the amount of the increment or
3277 decrement is the size of the operand being addressed. Some
3278 machines have other mode-dependent addresses. Many RISC machines
3279 have no mode-dependent addresses.
3281 You may assume that ADDR is a valid address for the machine. */
3283 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3286 /* Define this macro if references to a symbol must be treated
3287 differently depending on something about the variable or
3288 function named by the symbol (such as what section it is in).
3290 The macro definition, if any, is executed immediately after the
3291 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3292 The value of the rtl will be a `mem' whose address is a
3295 The usual thing for this macro to do is to a flag in the
3296 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3297 name string in the `symbol_ref' (if one bit is not enough
3300 The best way to modify the name string is by adding text to the
3301 beginning, with suitable punctuation to prevent any ambiguity.
3302 Allocate the new name in `saveable_obstack'. You will have to
3303 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3304 and output the name accordingly.
3306 You can also check the information stored in the `symbol_ref' in
3307 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3308 `PRINT_OPERAND_ADDRESS'.
3310 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3313 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3314 symbols which are not in the .text section.
3316 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3317 constants which are put in the .text section. We also record the
3318 total length of all such strings; this total is used to decide
3319 whether we need to split the constant table, and need not be
3322 When not mips16 code nor embedded PIC, if a symbol is in a
3323 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3324 splitting the reference so that gas can generate a gp relative
3327 When TARGET_EMBEDDED_DATA is set, we assume that all const
3328 variables will be stored in ROM, which is too far from %gp to use
3329 %gprel addressing. Note that (1) we include "extern const"
3330 variables in this, which mips_select_section doesn't, and (2) we
3331 can't always tell if they're really const (they might be const C++
3332 objects with non-const constructors), so we err on the side of
3333 caution and won't use %gprel anyway (otherwise we'd have to defer
3334 this decision to the linker/loader). The handling of extern consts
3335 is why the DECL_INITIAL macros differ from mips_select_section.
3337 If you are changing this macro, you should look at
3338 mips_select_section and see if it needs a similar change. */
3340 #define ENCODE_SECTION_INFO(DECL, FIRST) \
3343 if (TARGET_MIPS16) \
3345 if ((FIRST) && TREE_CODE (DECL) == STRING_CST \
3346 && ! flag_writable_strings \
3347 /* If this string is from a function, and the function will \
3348 go in a gnu linkonce section, then we can't directly \
3349 access the string. This gets an assembler error \
3350 "unsupported PC relative reference to different section".\
3351 If we modify SELECT_SECTION to put it in function_section\
3352 instead of text_section, it still fails because \
3353 DECL_SECTION_NAME isn't set until assemble_start_function.\
3354 If we fix that, it still fails because strings are shared\
3355 among multiple functions, and we have cross section \
3356 references again. We force it to work by putting string \
3357 addresses in the constant pool and indirecting. */ \
3358 && (! current_function_decl \
3359 || ! DECL_ONE_ONLY (current_function_decl))) \
3361 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3362 mips_string_length += TREE_STRING_LENGTH (DECL); \
3366 if (TARGET_EMBEDDED_DATA \
3367 && (TREE_CODE (DECL) == VAR_DECL \
3368 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3369 && (!DECL_INITIAL (DECL) \
3370 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3372 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3375 else if (TARGET_EMBEDDED_PIC) \
3377 if (TREE_CODE (DECL) == VAR_DECL) \
3378 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3379 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3380 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3381 else if (TREE_CODE (DECL) == STRING_CST \
3382 && ! flag_writable_strings) \
3383 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3385 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3388 else if (TREE_CODE (DECL) == VAR_DECL \
3389 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3390 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3392 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3395 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3398 /* We can not perform GP optimizations on variables which are in \
3399 specific sections, except for .sdata and .sbss which are \
3401 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3402 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3404 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3406 if (size > 0 && size <= mips_section_threshold) \
3407 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3410 else if (HALF_PIC_P ()) \
3413 HALF_PIC_ENCODE (DECL); \
3418 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3419 'the start of the function that this code is output in'. */
3421 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3422 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3423 asm_fprintf ((FILE), "%U%s", \
3424 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3426 asm_fprintf ((FILE), "%U%s", (NAME))
3428 /* The mips16 wants the constant pool to be after the function,
3429 because the PC relative load instructions use unsigned offsets. */
3431 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3433 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3434 mips_string_length = 0;
3437 /* In mips16 mode, put most string constants after the function. */
3438 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3439 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3442 /* Specify the machine mode that this machine uses
3443 for the index in the tablejump instruction.
3444 ??? Using HImode in mips16 mode can cause overflow. However, the
3445 overflow is no more likely than the overflow in a branch
3446 instruction. Large functions can currently break in both ways. */
3447 #define CASE_VECTOR_MODE \
3448 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3450 /* Define as C expression which evaluates to nonzero if the tablejump
3451 instruction expects the table to contain offsets from the address of the
3453 Do not define this if the table should contain absolute addresses. */
3454 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3456 /* Define this as 1 if `char' should by default be signed; else as 0. */
3457 #ifndef DEFAULT_SIGNED_CHAR
3458 #define DEFAULT_SIGNED_CHAR 1
3461 /* Max number of bytes we can move from memory to memory
3462 in one reasonably fast instruction. */
3463 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3464 #define MAX_MOVE_MAX 8
3466 /* Define this macro as a C expression which is nonzero if
3467 accessing less than a word of memory (i.e. a `char' or a
3468 `short') is no faster than accessing a word of memory, i.e., if
3469 such access require more than one instruction or if there is no
3470 difference in cost between byte and (aligned) word loads.
3472 On RISC machines, it tends to generate better code to define
3473 this as 1, since it avoids making a QI or HI mode register. */
3474 #define SLOW_BYTE_ACCESS 1
3476 /* We assume that the store-condition-codes instructions store 0 for false
3477 and some other value for true. This is the value stored for true. */
3479 #define STORE_FLAG_VALUE 1
3481 /* Define this to be nonzero if shift instructions ignore all but the low-order
3483 #define SHIFT_COUNT_TRUNCATED 1
3485 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3486 is done just by pretending it is already truncated. */
3487 /* In 64 bit mode, 32 bit instructions require that register values be properly
3488 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3489 converts a value >32 bits to a value <32 bits. */
3490 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3491 Something needs to be done about this. Perhaps not use any 32 bit
3492 instructions? Perhaps use PROMOTE_MODE? */
3493 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3494 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3496 /* Specify the machine mode that pointers have.
3497 After generation of rtl, the compiler makes no further distinction
3498 between pointers and any other objects of this machine mode.
3500 For MIPS we make pointers are the smaller of longs and gp-registers. */
3503 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3506 /* A function address in a call instruction
3507 is a word address (for indexing purposes)
3508 so give the MEM rtx a words's mode. */
3510 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3512 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3513 memset, instead of the BSD functions bcopy and bzero. */
3515 #if defined(MIPS_SYSV) || defined(OSF_OS)
3516 #define TARGET_MEM_FUNCTIONS
3520 /* A part of a C `switch' statement that describes the relative
3521 costs of constant RTL expressions. It must contain `case'
3522 labels for expression codes `const_int', `const', `symbol_ref',
3523 `label_ref' and `const_double'. Each case must ultimately reach
3524 a `return' statement to return the relative cost of the use of
3525 that kind of constant value in an expression. The cost may
3526 depend on the precise value of the constant, which is available
3527 for examination in X.
3529 CODE is the expression code--redundant, since it can be obtained
3530 with `GET_CODE (X)'. */
3532 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3534 if (! TARGET_MIPS16) \
3536 /* Always return 0, since we don't have different sized \
3537 instructions, hence different costs according to Richard \
3541 if ((OUTER_CODE) == SET) \
3543 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3545 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3546 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3547 return COSTS_N_INSNS (1); \
3549 return COSTS_N_INSNS (2); \
3551 /* A PLUS could be an address. We don't want to force an address \
3552 to use a register, so accept any signed 16 bit value without \
3554 if ((OUTER_CODE) == PLUS \
3555 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3557 /* A number between 1 and 8 inclusive is efficient for a shift. \
3558 Otherwise, we will need an extended instruction. */ \
3559 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3560 || (OUTER_CODE) == LSHIFTRT) \
3562 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3564 return COSTS_N_INSNS (1); \
3566 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3567 if ((OUTER_CODE) == XOR \
3568 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3570 /* We may be able to use slt or sltu for a comparison with a \
3571 signed 16 bit value. (The boundary conditions aren't quite \
3572 right, but this is just a heuristic anyhow.) */ \
3573 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3574 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3575 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3576 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3577 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3579 /* Equality comparisons with 0 are cheap. */ \
3580 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3581 && INTVAL (X) == 0) \
3584 /* Otherwise, work out the cost to load the value into a \
3586 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3587 return COSTS_N_INSNS (1); \
3588 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3589 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3590 return COSTS_N_INSNS (2); \
3592 return COSTS_N_INSNS (3); \
3595 return COSTS_N_INSNS (2); \
3599 rtx offset = const0_rtx; \
3600 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3602 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3604 /* Treat this like a signed 16 bit CONST_INT. */ \
3605 if ((OUTER_CODE) == PLUS) \
3607 else if ((OUTER_CODE) == SET) \
3608 return COSTS_N_INSNS (1); \
3610 return COSTS_N_INSNS (2); \
3613 if (GET_CODE (symref) == LABEL_REF) \
3614 return COSTS_N_INSNS (2); \
3616 if (GET_CODE (symref) != SYMBOL_REF) \
3617 return COSTS_N_INSNS (4); \
3619 /* let's be paranoid.... */ \
3620 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3621 return COSTS_N_INSNS (2); \
3623 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3627 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3629 case CONST_DOUBLE: \
3632 if (TARGET_MIPS16) \
3633 return COSTS_N_INSNS (4); \
3634 split_double (X, &high, &low); \
3635 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3636 || low == CONST0_RTX (GET_MODE (low))) \
3640 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3641 This can be used, for example, to indicate how costly a multiply
3642 instruction is. In writing this macro, you can use the construct
3643 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3645 This macro is optional; do not define it if the default cost
3646 assumptions are adequate for the target machine.
3648 If -mdebugd is used, change the multiply cost to 2, so multiply by
3649 a constant isn't converted to a series of shifts. This helps
3650 strength reduction, and also makes it easier to identify what the
3651 compiler is doing. */
3653 /* ??? Fix this to be right for the R8000. */
3654 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3657 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3658 if (simple_memory_operand (X, GET_MODE (X))) \
3659 return COSTS_N_INSNS (num_words); \
3661 return COSTS_N_INSNS (2*num_words); \
3665 return COSTS_N_INSNS (6); \
3668 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3673 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3674 return COSTS_N_INSNS (2); \
3681 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3682 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3688 enum machine_mode xmode = GET_MODE (X); \
3689 if (xmode == SFmode || xmode == DFmode) \
3690 return COSTS_N_INSNS (1); \
3692 return COSTS_N_INSNS (4); \
3698 enum machine_mode xmode = GET_MODE (X); \
3699 if (xmode == SFmode || xmode == DFmode) \
3703 return COSTS_N_INSNS (2); \
3704 else if (TUNE_MIPS6000) \
3705 return COSTS_N_INSNS (3); \
3707 return COSTS_N_INSNS (6); \
3710 if (xmode == DImode && !TARGET_64BIT) \
3711 return COSTS_N_INSNS (4); \
3717 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3724 enum machine_mode xmode = GET_MODE (X); \
3725 if (xmode == SFmode) \
3730 return COSTS_N_INSNS (4); \
3731 else if (TUNE_MIPS6000) \
3732 return COSTS_N_INSNS (5); \
3734 return COSTS_N_INSNS (7); \
3737 if (xmode == DFmode) \
3742 return COSTS_N_INSNS (5); \
3743 else if (TUNE_MIPS6000) \
3744 return COSTS_N_INSNS (6); \
3746 return COSTS_N_INSNS (8); \
3749 if (TUNE_MIPS3000) \
3750 return COSTS_N_INSNS (12); \
3751 else if (TUNE_MIPS3900) \
3752 return COSTS_N_INSNS (2); \
3753 else if (TUNE_MIPS6000) \
3754 return COSTS_N_INSNS (17); \
3755 else if (TUNE_MIPS5000) \
3756 return COSTS_N_INSNS (5); \
3758 return COSTS_N_INSNS (10); \
3764 enum machine_mode xmode = GET_MODE (X); \
3765 if (xmode == SFmode) \
3769 return COSTS_N_INSNS (12); \
3770 else if (TUNE_MIPS6000) \
3771 return COSTS_N_INSNS (15); \
3773 return COSTS_N_INSNS (23); \
3776 if (xmode == DFmode) \
3780 return COSTS_N_INSNS (19); \
3781 else if (TUNE_MIPS6000) \
3782 return COSTS_N_INSNS (16); \
3784 return COSTS_N_INSNS (36); \
3787 /* fall through */ \
3793 return COSTS_N_INSNS (35); \
3794 else if (TUNE_MIPS6000) \
3795 return COSTS_N_INSNS (38); \
3796 else if (TUNE_MIPS5000) \
3797 return COSTS_N_INSNS (36); \
3799 return COSTS_N_INSNS (69); \
3802 /* A sign extend from SImode to DImode in 64 bit mode is often \
3803 zero instructions, because the result can often be used \
3804 directly by another instruction; we'll call it one. */ \
3805 if (TARGET_64BIT && GET_MODE (X) == DImode \
3806 && GET_MODE (XEXP (X, 0)) == SImode) \
3807 return COSTS_N_INSNS (1); \
3809 return COSTS_N_INSNS (2); \
3812 if (TARGET_64BIT && GET_MODE (X) == DImode \
3813 && GET_MODE (XEXP (X, 0)) == SImode) \
3814 return COSTS_N_INSNS (2); \
3816 return COSTS_N_INSNS (1);
3818 /* An expression giving the cost of an addressing mode that
3819 contains ADDRESS. If not defined, the cost is computed from the
3820 form of the ADDRESS expression and the `CONST_COSTS' values.
3822 For most CISC machines, the default cost is a good approximation
3823 of the true cost of the addressing mode. However, on RISC
3824 machines, all instructions normally have the same length and
3825 execution time. Hence all addresses will have equal costs.
3827 In cases where more than one form of an address is known, the
3828 form with the lowest cost will be used. If multiple forms have
3829 the same, lowest, cost, the one that is the most complex will be
3832 For example, suppose an address that is equal to the sum of a
3833 register and a constant is used twice in the same basic block.
3834 When this macro is not defined, the address will be computed in
3835 a register and memory references will be indirect through that
3836 register. On machines where the cost of the addressing mode
3837 containing the sum is no higher than that of a simple indirect
3838 reference, this will produce an additional instruction and
3839 possibly require an additional register. Proper specification
3840 of this macro eliminates this overhead for such machines.
3842 Similar use of this macro is made in strength reduction of loops.
3844 ADDRESS need not be valid as an address. In such a case, the
3845 cost is not relevant and can be any value; invalid addresses
3846 need not be assigned a different cost.
3848 On machines where an address involving more than one register is
3849 as cheap as an address computation involving only one register,
3850 defining `ADDRESS_COST' to reflect this can cause two registers
3851 to be live over a region of code where only one would have been
3852 if `ADDRESS_COST' were not defined in that manner. This effect
3853 should be considered in the definition of this macro.
3854 Equivalent costs should probably only be given to addresses with
3855 different numbers of registers on machines with lots of registers.
3857 This macro will normally either not be defined or be defined as
3860 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3862 /* A C expression for the cost of moving data from a register in
3863 class FROM to one in class TO. The classes are expressed using
3864 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3865 the default; other values are interpreted relative to that.
3867 It is not required that the cost always equal 2 when FROM is the
3868 same as TO; on some machines it is expensive to move between
3869 registers if they are not general registers.
3871 If reload sees an insn consisting of a single `set' between two
3872 hard registers, and if `REGISTER_MOVE_COST' applied to their
3873 classes returns a value of 2, reload does not check to ensure
3874 that the constraints of the insn are met. Setting a cost of
3875 other than 2 will allow reload to verify that the constraints are
3876 met. You should do this if the `movM' pattern's constraints do
3877 not allow such copying.
3879 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3880 registers the same as for one of moving general registers to
3881 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3882 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3883 isn't clear if it is wise. And it might not work in all cases. We
3884 could solve the DImode LO reg problem by using a multiply, just like
3885 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3886 by using divide instructions. divu puts the remainder in the HI
3887 reg, so doing a divide by -1 will move the value in the HI reg for
3888 all values except -1. We could handle that case by using a signed
3889 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3890 compare/branch to test the input value to see which instruction we
3891 need to use. This gets pretty messy, but it is feasible. */
3893 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3894 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3895 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3896 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3897 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3898 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3899 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3900 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3901 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3902 : (((FROM) == HI_REG || (FROM) == LO_REG \
3903 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3904 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3905 : (((TO) == HI_REG || (TO) == LO_REG \
3906 || (TO) == MD_REGS || (TO) == HILO_REG) \
3907 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3908 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3909 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3912 /* ??? Fix this to be right for the R8000. */
3913 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3914 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3915 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3917 /* Define if copies to/from condition code registers should be avoided.
3919 This is needed for the MIPS because reload_outcc is not complete;
3920 it needs to handle cases where the source is a general or another
3921 condition code register. */
3922 #define AVOID_CCMODE_COPIES
3924 /* A C expression for the cost of a branch instruction. A value of
3925 1 is the default; other values are interpreted relative to that. */
3927 /* ??? Fix this to be right for the R8000. */
3928 #define BRANCH_COST \
3930 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3933 /* If defined, modifies the length assigned to instruction INSN as a
3934 function of the context in which it is used. LENGTH is an lvalue
3935 that contains the initially computed length of the insn and should
3936 be updated with the correct length of the insn. */
3937 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3938 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3941 /* Optionally define this if you have added predicates to
3942 `MACHINE.c'. This macro is called within an initializer of an
3943 array of structures. The first field in the structure is the
3944 name of a predicate and the second field is an array of rtl
3945 codes. For each predicate, list all rtl codes that can be in
3946 expressions matched by the predicate. The list should have a
3947 trailing comma. Here is an example of two entries in the list
3948 for a typical RISC machine:
3950 #define PREDICATE_CODES \
3951 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3952 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3954 Defining this macro does not affect the generated code (however,
3955 incorrect definitions that omit an rtl code that may be matched
3956 by the predicate can cause the compiler to malfunction).
3957 Instead, it allows the table built by `genrecog' to be more
3958 compact and efficient, thus speeding up the compiler. The most
3959 important predicates to include in the list specified by this
3960 macro are thoses used in the most insn patterns. */
3962 #define PREDICATE_CODES \
3963 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3964 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3965 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3966 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3967 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3968 {"small_int", { CONST_INT }}, \
3969 {"large_int", { CONST_INT }}, \
3970 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3971 {"const_float_1_operand", { CONST_DOUBLE }}, \
3972 {"simple_memory_operand", { MEM, SUBREG }}, \
3973 {"equality_op", { EQ, NE }}, \
3974 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3976 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3977 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3978 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3979 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3980 SYMBOL_REF, LABEL_REF, SUBREG, \
3982 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3983 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3984 MEM, SIGN_EXTEND }}, \
3985 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3986 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3988 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3990 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3992 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3993 SYMBOL_REF, LABEL_REF, SUBREG, \
3994 REG, SIGN_EXTEND }}, \
3995 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3996 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3997 CONST_DOUBLE, CONST }}, \
3998 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3999 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
4001 /* A list of predicates that do special things with modes, and so
4002 should not elicit warnings for VOIDmode match_operand. */
4004 #define SPECIAL_MODE_PREDICATES \
4005 "pc_or_label_operand",
4008 /* If defined, a C statement to be executed just prior to the
4009 output of assembler code for INSN, to modify the extracted
4010 operands so they will be output differently.
4012 Here the argument OPVEC is the vector containing the operands
4013 extracted from INSN, and NOPERANDS is the number of elements of
4014 the vector which contain meaningful data for this insn. The
4015 contents of this vector are what will be used to convert the
4016 insn template into assembler code, so you can change the
4017 assembler output by changing the contents of the vector.
4019 We use it to check if the current insn needs a nop in front of it
4020 because of load delays, and also to update the delay slot
4023 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
4024 final_prescan_insn (INSN, OPVEC, NOPERANDS)
4027 /* Control the assembler format that we output. */
4029 /* Output at beginning of assembler file.
4030 If we are optimizing to use the global pointer, create a temporary
4031 file to hold all of the text stuff, and write it out to the end.
4032 This is needed because the MIPS assembler is evidently one pass,
4033 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
4034 declaration when the code is processed, it generates a two
4035 instruction sequence. */
4037 #undef ASM_FILE_START
4038 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
4040 /* Output to assembler file text saying following lines
4041 may contain character constants, extra white space, comments, etc. */
4044 #define ASM_APP_ON " #APP\n"
4047 /* Output to assembler file text saying following lines
4048 no longer contain unusual constructs. */
4051 #define ASM_APP_OFF " #NO_APP\n"
4054 /* How to refer to registers in assembler output.
4055 This sequence is indexed by compiler's hard-register-number (see above).
4057 In order to support the two different conventions for register names,
4058 we use the name of a table set up in mips.c, which is overwritten
4059 if -mrnames is used. */
4061 #define REGISTER_NAMES \
4063 &mips_reg_names[ 0][0], \
4064 &mips_reg_names[ 1][0], \
4065 &mips_reg_names[ 2][0], \
4066 &mips_reg_names[ 3][0], \
4067 &mips_reg_names[ 4][0], \
4068 &mips_reg_names[ 5][0], \
4069 &mips_reg_names[ 6][0], \
4070 &mips_reg_names[ 7][0], \
4071 &mips_reg_names[ 8][0], \
4072 &mips_reg_names[ 9][0], \
4073 &mips_reg_names[10][0], \
4074 &mips_reg_names[11][0], \
4075 &mips_reg_names[12][0], \
4076 &mips_reg_names[13][0], \
4077 &mips_reg_names[14][0], \
4078 &mips_reg_names[15][0], \
4079 &mips_reg_names[16][0], \
4080 &mips_reg_names[17][0], \
4081 &mips_reg_names[18][0], \
4082 &mips_reg_names[19][0], \
4083 &mips_reg_names[20][0], \
4084 &mips_reg_names[21][0], \
4085 &mips_reg_names[22][0], \
4086 &mips_reg_names[23][0], \
4087 &mips_reg_names[24][0], \
4088 &mips_reg_names[25][0], \
4089 &mips_reg_names[26][0], \
4090 &mips_reg_names[27][0], \
4091 &mips_reg_names[28][0], \
4092 &mips_reg_names[29][0], \
4093 &mips_reg_names[30][0], \
4094 &mips_reg_names[31][0], \
4095 &mips_reg_names[32][0], \
4096 &mips_reg_names[33][0], \
4097 &mips_reg_names[34][0], \
4098 &mips_reg_names[35][0], \
4099 &mips_reg_names[36][0], \
4100 &mips_reg_names[37][0], \
4101 &mips_reg_names[38][0], \
4102 &mips_reg_names[39][0], \
4103 &mips_reg_names[40][0], \
4104 &mips_reg_names[41][0], \
4105 &mips_reg_names[42][0], \
4106 &mips_reg_names[43][0], \
4107 &mips_reg_names[44][0], \
4108 &mips_reg_names[45][0], \
4109 &mips_reg_names[46][0], \
4110 &mips_reg_names[47][0], \
4111 &mips_reg_names[48][0], \
4112 &mips_reg_names[49][0], \
4113 &mips_reg_names[50][0], \
4114 &mips_reg_names[51][0], \
4115 &mips_reg_names[52][0], \
4116 &mips_reg_names[53][0], \
4117 &mips_reg_names[54][0], \
4118 &mips_reg_names[55][0], \
4119 &mips_reg_names[56][0], \
4120 &mips_reg_names[57][0], \
4121 &mips_reg_names[58][0], \
4122 &mips_reg_names[59][0], \
4123 &mips_reg_names[60][0], \
4124 &mips_reg_names[61][0], \
4125 &mips_reg_names[62][0], \
4126 &mips_reg_names[63][0], \
4127 &mips_reg_names[64][0], \
4128 &mips_reg_names[65][0], \
4129 &mips_reg_names[66][0], \
4130 &mips_reg_names[67][0], \
4131 &mips_reg_names[68][0], \
4132 &mips_reg_names[69][0], \
4133 &mips_reg_names[70][0], \
4134 &mips_reg_names[71][0], \
4135 &mips_reg_names[72][0], \
4136 &mips_reg_names[73][0], \
4137 &mips_reg_names[74][0], \
4138 &mips_reg_names[75][0], \
4141 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
4142 So define this for it. */
4143 #define DEBUG_REGISTER_NAMES \
4145 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
4146 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
4147 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
4148 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
4149 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
4150 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
4151 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
4152 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
4153 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
4154 "$fcc5","$fcc6","$fcc7","$rap" \
4157 /* If defined, a C initializer for an array of structures
4158 containing a name and a register number. This macro defines
4159 additional names for hard registers, thus allowing the `asm'
4160 option in declarations to refer to registers using alternate
4163 We define both names for the integer registers here. */
4165 #define ADDITIONAL_REGISTER_NAMES \
4167 { "$0", 0 + GP_REG_FIRST }, \
4168 { "$1", 1 + GP_REG_FIRST }, \
4169 { "$2", 2 + GP_REG_FIRST }, \
4170 { "$3", 3 + GP_REG_FIRST }, \
4171 { "$4", 4 + GP_REG_FIRST }, \
4172 { "$5", 5 + GP_REG_FIRST }, \
4173 { "$6", 6 + GP_REG_FIRST }, \
4174 { "$7", 7 + GP_REG_FIRST }, \
4175 { "$8", 8 + GP_REG_FIRST }, \
4176 { "$9", 9 + GP_REG_FIRST }, \
4177 { "$10", 10 + GP_REG_FIRST }, \
4178 { "$11", 11 + GP_REG_FIRST }, \
4179 { "$12", 12 + GP_REG_FIRST }, \
4180 { "$13", 13 + GP_REG_FIRST }, \
4181 { "$14", 14 + GP_REG_FIRST }, \
4182 { "$15", 15 + GP_REG_FIRST }, \
4183 { "$16", 16 + GP_REG_FIRST }, \
4184 { "$17", 17 + GP_REG_FIRST }, \
4185 { "$18", 18 + GP_REG_FIRST }, \
4186 { "$19", 19 + GP_REG_FIRST }, \
4187 { "$20", 20 + GP_REG_FIRST }, \
4188 { "$21", 21 + GP_REG_FIRST }, \
4189 { "$22", 22 + GP_REG_FIRST }, \
4190 { "$23", 23 + GP_REG_FIRST }, \
4191 { "$24", 24 + GP_REG_FIRST }, \
4192 { "$25", 25 + GP_REG_FIRST }, \
4193 { "$26", 26 + GP_REG_FIRST }, \
4194 { "$27", 27 + GP_REG_FIRST }, \
4195 { "$28", 28 + GP_REG_FIRST }, \
4196 { "$29", 29 + GP_REG_FIRST }, \
4197 { "$30", 30 + GP_REG_FIRST }, \
4198 { "$31", 31 + GP_REG_FIRST }, \
4199 { "$sp", 29 + GP_REG_FIRST }, \
4200 { "$fp", 30 + GP_REG_FIRST }, \
4201 { "at", 1 + GP_REG_FIRST }, \
4202 { "v0", 2 + GP_REG_FIRST }, \
4203 { "v1", 3 + GP_REG_FIRST }, \
4204 { "a0", 4 + GP_REG_FIRST }, \
4205 { "a1", 5 + GP_REG_FIRST }, \
4206 { "a2", 6 + GP_REG_FIRST }, \
4207 { "a3", 7 + GP_REG_FIRST }, \
4208 { "t0", 8 + GP_REG_FIRST }, \
4209 { "t1", 9 + GP_REG_FIRST }, \
4210 { "t2", 10 + GP_REG_FIRST }, \
4211 { "t3", 11 + GP_REG_FIRST }, \
4212 { "t4", 12 + GP_REG_FIRST }, \
4213 { "t5", 13 + GP_REG_FIRST }, \
4214 { "t6", 14 + GP_REG_FIRST }, \
4215 { "t7", 15 + GP_REG_FIRST }, \
4216 { "s0", 16 + GP_REG_FIRST }, \
4217 { "s1", 17 + GP_REG_FIRST }, \
4218 { "s2", 18 + GP_REG_FIRST }, \
4219 { "s3", 19 + GP_REG_FIRST }, \
4220 { "s4", 20 + GP_REG_FIRST }, \
4221 { "s5", 21 + GP_REG_FIRST }, \
4222 { "s6", 22 + GP_REG_FIRST }, \
4223 { "s7", 23 + GP_REG_FIRST }, \
4224 { "t8", 24 + GP_REG_FIRST }, \
4225 { "t9", 25 + GP_REG_FIRST }, \
4226 { "k0", 26 + GP_REG_FIRST }, \
4227 { "k1", 27 + GP_REG_FIRST }, \
4228 { "gp", 28 + GP_REG_FIRST }, \
4229 { "sp", 29 + GP_REG_FIRST }, \
4230 { "fp", 30 + GP_REG_FIRST }, \
4231 { "ra", 31 + GP_REG_FIRST }, \
4232 { "$sp", 29 + GP_REG_FIRST }, \
4233 { "$fp", 30 + GP_REG_FIRST } \
4236 /* A C compound statement to output to stdio stream STREAM the
4237 assembler syntax for an instruction operand X. X is an RTL
4240 CODE is a value that can be used to specify one of several ways
4241 of printing the operand. It is used when identical operands
4242 must be printed differently depending on the context. CODE
4243 comes from the `%' specification that was used to request
4244 printing of the operand. If the specification was just `%DIGIT'
4245 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4246 is the ASCII code for LTR.
4248 If X is a register, this macro should print the register's name.
4249 The names can be found in an array `reg_names' whose type is
4250 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4252 When the machine description has a specification `%PUNCT' (a `%'
4253 followed by a punctuation character), this macro is called with
4254 a null pointer for X and the punctuation character for CODE.
4256 See mips.c for the MIPS specific codes. */
4258 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4260 /* A C expression which evaluates to true if CODE is a valid
4261 punctuation character for use in the `PRINT_OPERAND' macro. If
4262 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4263 punctuation characters (except for the standard one, `%') are
4264 used in this way. */
4266 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4268 /* A C compound statement to output to stdio stream STREAM the
4269 assembler syntax for an instruction operand that is a memory
4270 reference whose address is ADDR. ADDR is an RTL expression.
4272 On some machines, the syntax for a symbolic address depends on
4273 the section that the address refers to. On these machines,
4274 define the macro `ENCODE_SECTION_INFO' to store the information
4275 into the `symbol_ref', and then check for it here. */
4277 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4280 /* A C statement, to be executed after all slot-filler instructions
4281 have been output. If necessary, call `dbr_sequence_length' to
4282 determine the number of slots filled in a sequence (zero if not
4283 currently outputting a sequence), to decide how many no-ops to
4284 output, or whatever.
4286 Don't define this macro if it has nothing to do, but it is
4287 helpful in reading assembly output if the extent of the delay
4288 sequence is made explicit (e.g. with white space).
4290 Note that output routines for instructions with delay slots must
4291 be prepared to deal with not being output as part of a sequence
4292 (i.e. when the scheduling pass is not run, or when no slot
4293 fillers could be found.) The variable `final_sequence' is null
4294 when not processing a sequence, otherwise it contains the
4295 `sequence' rtx being output. */
4297 #define DBR_OUTPUT_SEQEND(STREAM) \
4300 if (set_nomacro > 0 && --set_nomacro == 0) \
4301 fputs ("\t.set\tmacro\n", STREAM); \
4303 if (set_noreorder > 0 && --set_noreorder == 0) \
4304 fputs ("\t.set\treorder\n", STREAM); \
4306 dslots_jump_filled++; \
4307 fputs ("\n", STREAM); \
4312 /* How to tell the debugger about changes of source files. Note, the
4313 mips ECOFF format cannot deal with changes of files inside of
4314 functions, which means the output of parser generators like bison
4315 is generally not debuggable without using the -l switch. Lose,
4316 lose, lose. Silicon graphics seems to want all .file's hardwired
4319 #ifndef SET_FILE_NUMBER
4320 #define SET_FILE_NUMBER() ++num_source_filenames
4323 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4324 mips_output_filename (STREAM, NAME)
4326 /* This is defined so that it can be overridden in iris6.h. */
4327 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4330 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4331 output_quoted_string (STREAM, NAME); \
4332 fputs ("\n", STREAM); \
4336 /* This is how to output a note the debugger telling it the line number
4337 to which the following sequence of instructions corresponds.
4338 Silicon graphics puts a label after each .loc. */
4340 #ifndef LABEL_AFTER_LOC
4341 #define LABEL_AFTER_LOC(STREAM)
4344 #ifndef ASM_OUTPUT_SOURCE_LINE
4345 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4346 mips_output_lineno (STREAM, LINE)
4349 /* The MIPS implementation uses some labels for its own purpose. The
4350 following lists what labels are created, and are all formed by the
4351 pattern $L[a-z].*. The machine independent portion of GCC creates
4352 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4354 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4355 $Lb[0-9]+ Begin blocks for MIPS debug support
4356 $Lc[0-9]+ Label for use in s<xx> operation.
4357 $Le[0-9]+ End blocks for MIPS debug support
4358 $Lp\..+ Half-pic labels. */
4360 /* This is how to output the definition of a user-level label named NAME,
4361 such as the label on a static function or variable NAME.
4363 If we are optimizing the gp, remember that this label has been put
4364 out, so we know not to emit an .extern for it in mips_asm_file_end.
4365 We use one of the common bits in the IDENTIFIER tree node for this,
4366 since those bits seem to be unused, and we don't have any method
4367 of getting the decl nodes from the name. */
4369 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4371 assemble_name (STREAM, NAME); \
4372 fputs (":\n", STREAM); \
4376 /* A C statement (sans semicolon) to output to the stdio stream
4377 STREAM any text necessary for declaring the name NAME of an
4378 initialized variable which is being defined. This macro must
4379 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4380 The argument DECL is the `VAR_DECL' tree node representing the
4383 If this macro is not defined, then the variable name is defined
4384 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4386 #undef ASM_DECLARE_OBJECT_NAME
4387 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4390 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4391 HALF_PIC_DECLARE (NAME); \
4396 /* This is how to output a command to make the user-level label named NAME
4397 defined for reference from other files. */
4399 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4401 fputs ("\t.globl\t", STREAM); \
4402 assemble_name (STREAM, NAME); \
4403 fputs ("\n", STREAM); \
4406 /* This says how to define a global common symbol. */
4408 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4410 /* If the target wants uninitialized const declarations in \
4411 .rdata then don't put them in .comm */ \
4412 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4413 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4414 && (DECL_INITIAL (DECL) == 0 \
4415 || DECL_INITIAL (DECL) == error_mark_node)) \
4417 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4418 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4420 READONLY_DATA_SECTION (); \
4421 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4422 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4426 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4431 /* This says how to define a local common symbol (ie, not visible to
4434 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4435 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4438 /* This says how to output an external. It would be possible not to
4439 output anything and let undefined symbol become external. However
4440 the assembler uses length information on externals to allocate in
4441 data/sdata bss/sbss, thereby saving exec time. */
4443 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4444 mips_output_external(STREAM,DECL,NAME)
4446 /* This says what to print at the end of the assembly file */
4448 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4451 /* Play switch file games if we're optimizing the global pointer. */
4454 #define TEXT_SECTION() \
4456 extern FILE *asm_out_text_file; \
4457 if (TARGET_FILE_SWITCHING) \
4458 asm_out_file = asm_out_text_file; \
4459 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4460 fputc ('\n', asm_out_file); \
4464 /* This is how to declare a function name. The actual work of
4465 emitting the label is moved to function_prologue, so that we can
4466 get the line number correctly emitted before the .ent directive,
4467 and after any .file directives. */
4469 #undef ASM_DECLARE_FUNCTION_NAME
4470 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4471 HALF_PIC_DECLARE (NAME)
4473 /* This is how to output an internal numbered label where
4474 PREFIX is the class of label and NUM is the number within the class. */
4476 #undef ASM_OUTPUT_INTERNAL_LABEL
4477 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4478 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4480 /* This is how to store into the string LABEL
4481 the symbol_ref name of an internal numbered label where
4482 PREFIX is the class of label and NUM is the number within the class.
4483 This is suitable for output with `assemble_name'. */
4485 #undef ASM_GENERATE_INTERNAL_LABEL
4486 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4487 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4489 /* This is how to output an element of a case-vector that is absolute. */
4491 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4492 fprintf (STREAM, "\t%s\t%sL%d\n", \
4493 Pmode == DImode ? ".dword" : ".word", \
4494 LOCAL_LABEL_PREFIX, \
4497 /* This is how to output an element of a case-vector that is relative.
4498 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4499 TARGET_EMBEDDED_PIC). */
4501 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4503 if (TARGET_MIPS16) \
4504 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4505 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4506 else if (TARGET_EMBEDDED_PIC) \
4507 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4508 Pmode == DImode ? ".dword" : ".word", \
4509 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4510 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4511 fprintf (STREAM, "\t%s\t%sL%d\n", \
4512 Pmode == DImode ? ".gpdword" : ".gpword", \
4513 LOCAL_LABEL_PREFIX, VALUE); \
4515 fprintf (STREAM, "\t%s\t%sL%d\n", \
4516 Pmode == DImode ? ".dword" : ".word", \
4517 LOCAL_LABEL_PREFIX, VALUE); \
4520 /* When generating embedded PIC or mips16 code we want to put the jump
4521 table in the .text section. In all other cases, we want to put the
4522 jump table in the .rdata section. Unfortunately, we can't use
4523 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4524 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4525 section if appropriate. */
4526 #undef ASM_OUTPUT_CASE_LABEL
4527 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4529 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4530 function_section (current_function_decl); \
4531 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4534 /* This is how to output an assembler line
4535 that says to advance the location counter
4536 to a multiple of 2**LOG bytes. */
4538 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4539 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4541 /* This is how to output an assembler line to advance the location
4542 counter by SIZE bytes. */
4544 #undef ASM_OUTPUT_SKIP
4545 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4546 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4548 /* This is how to output a string. */
4549 #undef ASM_OUTPUT_ASCII
4550 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4551 mips_output_ascii (STREAM, STRING, LEN)
4553 /* Handle certain cpp directives used in header files on sysV. */
4554 #define SCCS_DIRECTIVE
4556 /* Output #ident as a in the read-only data section. */
4557 #undef ASM_OUTPUT_IDENT
4558 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4560 const char *p = STRING; \
4561 int size = strlen (p) + 1; \
4563 assemble_string (p, size); \
4566 /* Default to -G 8 */
4567 #ifndef MIPS_DEFAULT_GVALUE
4568 #define MIPS_DEFAULT_GVALUE 8
4571 /* Define the strings to put out for each section in the object file. */
4572 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4573 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4574 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4575 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4576 #undef READONLY_DATA_SECTION
4577 #define READONLY_DATA_SECTION rdata_section
4578 #define SMALL_DATA_SECTION sdata_section
4580 /* What other sections we support other than the normal .data/.text. */
4582 #undef EXTRA_SECTIONS
4583 #define EXTRA_SECTIONS in_sdata, in_rdata
4585 /* Define the additional functions to select our additional sections. */
4587 /* on the MIPS it is not a good idea to put constants in the text
4588 section, since this defeats the sdata/data mechanism. This is
4589 especially true when -O is used. In this case an effort is made to
4590 address with faster (gp) register relative addressing, which can
4591 only get at sdata and sbss items (there is no stext !!) However,
4592 if the constant is too large for sdata, and it's readonly, it
4593 will go into the .rdata section. */
4595 #undef EXTRA_SECTION_FUNCTIONS
4596 #define EXTRA_SECTION_FUNCTIONS \
4600 if (in_section != in_sdata) \
4602 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4603 in_section = in_sdata; \
4610 if (in_section != in_rdata) \
4612 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4613 in_section = in_rdata; \
4617 /* Given a decl node or constant node, choose the section to output it in
4618 and select that section. */
4620 #undef SELECT_RTX_SECTION
4621 #define SELECT_RTX_SECTION(MODE, RTX, ALIGN) \
4622 mips_select_rtx_section (MODE, RTX)
4624 #undef SELECT_SECTION
4625 #define SELECT_SECTION(DECL, RELOC, ALIGN) \
4626 mips_select_section (DECL, RELOC)
4629 /* Store in OUTPUT a string (made with alloca) containing
4630 an assembler-name for a local static variable named NAME.
4631 LABELNO is an integer which is different for each call. */
4633 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4634 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4635 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4637 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4640 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4641 TARGET_64BIT ? "dsubu" : "subu", \
4642 reg_names[STACK_POINTER_REGNUM], \
4643 reg_names[STACK_POINTER_REGNUM], \
4644 TARGET_64BIT ? "sd" : "sw", \
4646 reg_names[STACK_POINTER_REGNUM]); \
4650 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4653 if (! set_noreorder) \
4654 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4656 dslots_load_total++; \
4657 dslots_load_filled++; \
4658 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4659 TARGET_64BIT ? "ld" : "lw", \
4661 reg_names[STACK_POINTER_REGNUM], \
4662 TARGET_64BIT ? "daddu" : "addu", \
4663 reg_names[STACK_POINTER_REGNUM], \
4664 reg_names[STACK_POINTER_REGNUM]); \
4666 if (! set_noreorder) \
4667 fprintf (STREAM, "\t.set\treorder\n"); \
4671 /* How to start an assembler comment.
4672 The leading space is important (the mips native assembler requires it). */
4673 #ifndef ASM_COMMENT_START
4674 #define ASM_COMMENT_START " #"
4678 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4679 and mips-tdump.c to print them out.
4681 These must match the corresponding definitions in gdb/mipsread.c.
4682 Unfortunately, gcc and gdb do not currently share any directories. */
4684 #define CODE_MASK 0x8F300
4685 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4686 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4687 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4690 /* Default definitions for size_t and ptrdiff_t. */
4693 #define NO_BUILTIN_SIZE_TYPE
4694 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4697 #ifndef PTRDIFF_TYPE
4698 #define NO_BUILTIN_PTRDIFF_TYPE
4699 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4702 /* See mips_expand_prologue's use of loadgp for when this should be
4705 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4706 && mips_abi != ABI_32 \
4707 && mips_abi != ABI_O64)
4709 /* In mips16 mode, we need to look through the function to check for
4710 PC relative loads that are out of range. */
4711 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4713 /* We need to use a special set of functions to handle hard floating
4714 point code in mips16 mode. */
4716 #ifndef INIT_SUBTARGET_OPTABS
4717 #define INIT_SUBTARGET_OPTABS
4720 #define INIT_TARGET_OPTABS \
4723 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4724 INIT_SUBTARGET_OPTABS; \
4727 add_optab->handlers[(int) SFmode].libfunc = \
4728 init_one_libfunc ("__mips16_addsf3"); \
4729 sub_optab->handlers[(int) SFmode].libfunc = \
4730 init_one_libfunc ("__mips16_subsf3"); \
4731 smul_optab->handlers[(int) SFmode].libfunc = \
4732 init_one_libfunc ("__mips16_mulsf3"); \
4733 sdiv_optab->handlers[(int) SFmode].libfunc = \
4734 init_one_libfunc ("__mips16_divsf3"); \
4736 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4737 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4738 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4739 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4740 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4741 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4743 floatsisf_libfunc = \
4744 init_one_libfunc ("__mips16_floatsisf"); \
4746 init_one_libfunc ("__mips16_fixsfsi"); \
4748 if (TARGET_DOUBLE_FLOAT) \
4750 add_optab->handlers[(int) DFmode].libfunc = \
4751 init_one_libfunc ("__mips16_adddf3"); \
4752 sub_optab->handlers[(int) DFmode].libfunc = \
4753 init_one_libfunc ("__mips16_subdf3"); \
4754 smul_optab->handlers[(int) DFmode].libfunc = \
4755 init_one_libfunc ("__mips16_muldf3"); \
4756 sdiv_optab->handlers[(int) DFmode].libfunc = \
4757 init_one_libfunc ("__mips16_divdf3"); \
4759 extendsfdf2_libfunc = \
4760 init_one_libfunc ("__mips16_extendsfdf2"); \
4761 truncdfsf2_libfunc = \
4762 init_one_libfunc ("__mips16_truncdfsf2"); \
4765 init_one_libfunc ("__mips16_eqdf2"); \
4767 init_one_libfunc ("__mips16_nedf2"); \
4769 init_one_libfunc ("__mips16_gtdf2"); \
4771 init_one_libfunc ("__mips16_gedf2"); \
4773 init_one_libfunc ("__mips16_ltdf2"); \
4775 init_one_libfunc ("__mips16_ledf2"); \
4777 floatsidf_libfunc = \
4778 init_one_libfunc ("__mips16_floatsidf"); \
4780 init_one_libfunc ("__mips16_fixdfsi"); \
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