1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 90-98, 1999 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
26 /* Standard GCC variables that we reference. */
28 extern char *asm_file_name;
29 extern char call_used_regs[];
30 extern int current_function_calls_alloca;
31 extern char *language_string;
32 extern int may_call_alloca;
33 extern char **save_argv;
34 extern int target_flags;
35 extern char *version_string;
37 /* MIPS external variables defined in mips.c. */
41 CMP_SI, /* compare four byte integers */
42 CMP_DI, /* compare eight byte integers */
43 CMP_SF, /* compare single precision floats */
44 CMP_DF, /* compare double precision floats */
45 CMP_MAX /* max comparison type */
48 /* types of delay slot */
50 DELAY_NONE, /* no delay slot */
51 DELAY_LOAD, /* load from memory delay */
52 DELAY_HILO, /* move from/to hi/lo registers */
53 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
56 /* Which processor to schedule for. Since there is no difference between
57 a R2000 and R3000 in terms of the scheduler, we collapse them into
58 just an R3000. The elements of the enumeration must match exactly
59 the cpu attribute in the mips.md machine description. */
75 /* Recast the cpu class to be the cpu attribute. */
76 #define mips_cpu_attr ((enum attr_cpu)mips_cpu)
78 /* Which ABI to use. These are constants because abi64.h must check their
79 value at preprocessing time.
81 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
82 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
90 #ifndef MIPS_ABI_DEFAULT
91 /* We define this away so that there is no extra runtime cost if the target
92 doesn't support multiple ABIs. */
93 #define mips_abi ABI_32
98 /* Whether to emit abicalls code sequences or not. */
100 enum mips_abicalls_type {
105 /* Recast the abicalls class to be the abicalls attribute. */
106 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
108 /* Which type of block move to do (whether or not the last store is
109 split out so it can fill a branch delay slot). */
111 enum block_move_type {
112 BLOCK_MOVE_NORMAL, /* generate complete block move */
113 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
114 BLOCK_MOVE_LAST /* generate just the last store */
117 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
118 extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
119 extern char *current_function_file; /* filename current function is in */
120 extern int num_source_filenames; /* current .file # */
121 extern int inside_function; /* != 0 if inside of a function */
122 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
123 extern int file_in_function_warning; /* warning given about .file in func */
124 extern int sdb_label_count; /* block start/end next label # */
125 extern int sdb_begin_function_line; /* Starting Line of current function */
126 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
127 extern int g_switch_value; /* value of the -G xx switch */
128 extern int g_switch_set; /* whether -G xx was passed. */
129 extern int sym_lineno; /* sgi next label # for each stmt */
130 extern int set_noreorder; /* # of nested .set noreorder's */
131 extern int set_nomacro; /* # of nested .set nomacro's */
132 extern int set_noat; /* # of nested .set noat's */
133 extern int set_volatile; /* # of nested .set volatile's */
134 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
135 extern int mips_dbx_regno[]; /* Map register # to debug register # */
136 extern struct rtx_def *branch_cmp[2]; /* operands for compare */
137 extern enum cmp_type branch_type; /* what type of branch to use */
138 extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
139 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
140 extern int mips_isa; /* architectural level */
141 extern int mips16; /* whether generating mips16 code */
142 extern int mips16_hard_float; /* mips16 without -msoft-float */
143 extern int mips_entry; /* generate entry/exit for mips16 */
144 extern char *mips_cpu_string; /* for -mcpu=<xxx> */
145 extern char *mips_isa_string; /* for -mips{1,2,3,4} */
146 extern char *mips_abi_string; /* for -mabi={32,n32,64} */
147 extern char *mips_entry_string; /* for -mentry */
148 extern char *mips_no_mips16_string; /* for -mno-mips16 */
149 extern int mips_split_addresses; /* perform high/lo_sum support */
150 extern int dslots_load_total; /* total # load related delay slots */
151 extern int dslots_load_filled; /* # filled load delay slots */
152 extern int dslots_jump_total; /* total # jump related delay slots */
153 extern int dslots_jump_filled; /* # filled jump delay slots */
154 extern int dslots_number_nops; /* # of nops needed by previous insn */
155 extern int num_refs[3]; /* # 1/2/3 word references */
156 extern struct rtx_def *mips_load_reg; /* register to check for load delay */
157 extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
158 extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
159 extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
160 extern struct rtx_def *embedded_pic_fnaddr_rtx; /* function address */
161 extern int mips_string_length; /* length of strings for mips16 */
162 extern struct rtx_def *mips16_gp_pseudo_rtx; /* psuedo reg holding $gp */
164 /* Functions within mips.c that we reference. Some of these return type
165 HOST_WIDE_INT, so define that here. This is a copy of code in machmode.h.
167 ??? It would be good to try to put this as common code someplace. */
169 #ifndef HOST_BITS_PER_WIDE_INT
171 #if HOST_BITS_PER_LONG > HOST_BITS_PER_INT
172 #define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_LONG
173 #define HOST_WIDE_INT long
175 #define HOST_BITS_PER_WIDE_INT HOST_BITS_PER_INT
176 #define HOST_WIDE_INT int
181 extern void abort_with_insn ();
182 extern int arith32_operand ();
183 extern int arith_operand ();
184 extern int cmp_op ();
185 extern HOST_WIDE_INT compute_frame_size ();
186 extern int const_float_1_operand ();
187 extern void expand_block_move ();
188 extern int equality_op ();
189 extern void final_prescan_insn ();
190 extern struct rtx_def * function_arg ();
191 extern void function_arg_advance ();
192 extern int function_arg_partial_nregs ();
193 extern int function_arg_pass_by_reference ();
194 extern void function_epilogue ();
195 extern void function_prologue ();
196 extern void gen_conditional_branch ();
197 extern void gen_conditional_move ();
198 extern struct rtx_def * gen_int_relational ();
199 extern void init_cumulative_args ();
200 extern int large_int ();
201 extern void machine_dependent_reorg ();
202 extern int mips_address_cost ();
203 extern void mips_asm_file_end ();
204 extern void mips_asm_file_start ();
205 extern int mips_can_use_return_insn ();
206 extern int mips_const_double_ok ();
207 extern void mips_count_memory_refs ();
208 extern HOST_WIDE_INT mips_debugger_offset ();
209 extern void mips_declare_object ();
210 extern int mips_epilogue_delay_slots ();
211 extern void mips_expand_epilogue ();
212 extern void mips_expand_prologue ();
213 extern int mips_check_split ();
214 extern char *mips_fill_delay_slot ();
215 extern char *mips_move_1word ();
216 extern char *mips_move_2words ();
217 extern void mips_output_double ();
218 extern int mips_output_external ();
219 extern void mips_output_float ();
220 extern void mips_output_filename ();
221 extern void mips_output_lineno ();
222 extern char *output_block_move ();
223 extern void override_options ();
224 extern int pc_or_label_operand ();
225 extern void print_operand_address ();
226 extern void print_operand ();
227 extern void print_options ();
228 extern int reg_or_0_operand ();
229 extern int true_reg_or_0_operand ();
230 extern int simple_epilogue_p ();
231 extern int simple_memory_operand ();
232 extern int double_memory_operand ();
233 extern int small_int ();
234 extern void trace ();
235 extern int uns_arith_operand ();
236 extern struct rtx_def * embedded_pic_offset ();
237 extern void mips_order_regs_for_local_alloc ();
238 extern struct rtx_def * mips16_gp_pseudo_reg ();
239 extern struct rtx_def * mips16_gp_offset ();
240 extern int mips16_gp_offset_p ();
241 extern int mips16_constant ();
242 extern int mips16_constant_after_function_p ();
243 extern int build_mips16_call_stub ();
245 /* Recognition functions that return if a condition is true. */
246 extern int address_operand ();
247 extern int call_insn_operand ();
248 extern int const_double_operand ();
249 extern int const_int_operand ();
250 extern int consttable_operand ();
251 extern int general_operand ();
252 extern int immediate_operand ();
253 extern int memory_address_p ();
254 extern int memory_operand ();
255 extern int nonimmediate_operand ();
256 extern int nonmemory_operand ();
257 extern int pic_address_needs_scratch ();
258 extern int register_operand ();
259 extern int scratch_operand ();
260 extern int move_operand ();
261 extern int movdi_operand ();
262 extern int se_register_operand ();
263 extern int se_reg_or_0_operand ();
264 extern int se_uns_arith_operand ();
265 extern int se_arith_operand ();
266 extern int se_nonmemory_operand ();
267 extern int se_nonimmediate_operand ();
268 extern int extend_operator ();
269 extern int highpart_shift_operator ();
270 extern int m16_uimm3_b ();
271 extern int m16_simm4_1 ();
272 extern int m16_nsimm4_1 ();
273 extern int m16_simm5_1 ();
274 extern int m16_nsimm5_1 ();
275 extern int m16_uimm5_4 ();
276 extern int m16_nuimm5_4 ();
277 extern int m16_simm8_1 ();
278 extern int m16_nsimm8_1 ();
279 extern int m16_uimm8_1 ();
280 extern int m16_nuimm8_1 ();
281 extern int m16_uimm8_m1_1 ();
282 extern int m16_uimm8_4 ();
283 extern int m16_nuimm8_4 ();
284 extern int m16_simm8_8 ();
285 extern int m16_nsimm8_8 ();
286 extern int m16_usym8_4 ();
287 extern int m16_usym5_4 ();
289 /* Functions to change what output section we are using. */
290 extern void data_section ();
291 extern void rdata_section ();
292 extern void readonly_data_section ();
293 extern void sdata_section ();
294 extern void text_section ();
295 extern void mips_select_rtx_section ();
296 extern void mips_select_section ();
298 /* Stubs for half-pic support if not OSF/1 reference platform. */
301 #define HALF_PIC_P() 0
302 #define HALF_PIC_NUMBER_PTRS 0
303 #define HALF_PIC_NUMBER_REFS 0
304 #define HALF_PIC_ENCODE(DECL)
305 #define HALF_PIC_DECLARE(NAME)
306 #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
307 #define HALF_PIC_ADDRESS_P(X) 0
308 #define HALF_PIC_PTR(X) X
309 #define HALF_PIC_FINISH(STREAM)
313 /* Run-time compilation parameters selecting different hardware subsets. */
315 /* Macros used in the machine description to test the flags. */
317 /* Bits for real switches */
318 #define MASK_INT64 0x00000001 /* ints are 64 bits */
319 #define MASK_LONG64 0x00000002 /* longs and pointers are 64 bits */
320 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
321 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
322 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
323 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
324 #define MASK_STATS 0x00000040 /* print statistics to stderr */
325 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
326 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
327 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
328 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
329 #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
330 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
331 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
332 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
333 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
334 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
335 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
336 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
337 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
338 #define MASK_MIPS3900 0x00100000 /* like -mips1 only 3900 */
339 #define MASK_MIPS16 0x01000000 /* Generate mips16 code */
340 #define MASK_NO_CHECK_ZERO_DIV 0x04000000 /* divide by zero checking */
341 #define MASK_CHECK_RANGE_DIV 0x08000000 /* divide result range checking */
343 /* Dummy switches used only in spec's*/
344 #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
346 /* Debug switches, not documented */
347 #define MASK_DEBUG 0 /* Eliminate version # in .s file */
348 #define MASK_DEBUG_A 0x40000000 /* don't allow <label>($reg) addrs */
349 #define MASK_DEBUG_B 0x20000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
350 #define MASK_DEBUG_C 0x10000000 /* don't expand seq, etc. */
351 #define MASK_DEBUG_D 0 /* don't do define_split's */
352 #define MASK_DEBUG_E 0 /* function_arg debug */
353 #define MASK_DEBUG_F 0
354 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
355 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
356 #define MASK_DEBUG_I 0 /* unused */
358 /* r4000 64 bit sizes */
359 #define TARGET_INT64 (target_flags & MASK_INT64)
360 #define TARGET_LONG64 (target_flags & MASK_LONG64)
361 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
362 #define TARGET_64BIT (target_flags & MASK_64BIT)
364 /* Mips vs. GNU linker */
365 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
367 /* generate mips 3900 insns */
368 #define TARGET_MIPS3900 (target_flags & MASK_MIPS3900)
370 /* Mips vs. GNU assembler */
371 #define TARGET_GAS (target_flags & MASK_GAS)
372 #define TARGET_UNIX_ASM (!TARGET_GAS)
373 #define TARGET_MIPS_AS TARGET_UNIX_ASM
376 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
377 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
378 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
379 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
380 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
381 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
382 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
383 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
384 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
385 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
387 /* Reg. Naming in .s ($21 vs. $a0) */
388 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
390 /* Optimize for Sdata/Sbss */
391 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
393 /* print program statistics */
394 #define TARGET_STATS (target_flags & MASK_STATS)
396 /* call memcpy instead of inline code */
397 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
399 /* .abicalls, etc from Pyramid V.4 */
400 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
402 /* OSF pic references to externs */
403 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
405 /* software floating point */
406 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
407 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
409 /* always call through a register */
410 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
412 /* generate embedded PIC code;
414 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
416 /* for embedded systems, optimize for
417 reduced RAM space instead of for
419 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
421 /* generate big endian code. */
422 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
424 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
425 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
427 #define TARGET_MAD (target_flags & MASK_MAD)
429 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
431 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
432 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
434 /* This is true if we must enable the assembly language file switching
437 #define TARGET_FILE_SWITCHING (TARGET_GP_OPT && ! TARGET_GAS)
439 /* We must disable the function end stabs when doing the file switching trick,
440 because the Lscope stabs end up in the wrong place, making it impossible
441 to debug the resulting code. */
442 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
444 /* Generate mips16 code */
445 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
447 /* Macro to define tables used to set the flags.
448 This is a list in braces of pairs in braces,
449 each pair being { "NAME", VALUE }
450 where VALUE is the bits to set or minus the bits to clear.
451 An empty string NAME is used to identify the default VALUE. */
453 #define TARGET_SWITCHES \
455 {"int64", MASK_INT64 | MASK_LONG64}, \
456 {"long64", MASK_LONG64}, \
457 {"split-addresses", MASK_SPLIT_ADDR}, \
458 {"no-split-addresses", -MASK_SPLIT_ADDR}, \
459 {"mips-as", -MASK_GAS}, \
461 {"rnames", MASK_NAME_REGS}, \
462 {"no-rnames", -MASK_NAME_REGS}, \
463 {"gpOPT", MASK_GPOPT}, \
464 {"gpopt", MASK_GPOPT}, \
465 {"no-gpOPT", -MASK_GPOPT}, \
466 {"no-gpopt", -MASK_GPOPT}, \
467 {"stats", MASK_STATS}, \
468 {"no-stats", -MASK_STATS}, \
469 {"memcpy", MASK_MEMCPY}, \
470 {"no-memcpy", -MASK_MEMCPY}, \
471 {"mips-tfile", MASK_MIPS_TFILE}, \
472 {"no-mips-tfile", -MASK_MIPS_TFILE}, \
473 {"soft-float", MASK_SOFT_FLOAT}, \
474 {"hard-float", -MASK_SOFT_FLOAT}, \
475 {"fp64", MASK_FLOAT64}, \
476 {"fp32", -MASK_FLOAT64}, \
477 {"gp64", MASK_64BIT}, \
478 {"gp32", -MASK_64BIT}, \
479 {"abicalls", MASK_ABICALLS}, \
480 {"no-abicalls", -MASK_ABICALLS}, \
481 {"half-pic", MASK_HALF_PIC}, \
482 {"no-half-pic", -MASK_HALF_PIC}, \
483 {"long-calls", MASK_LONG_CALLS}, \
484 {"no-long-calls", -MASK_LONG_CALLS}, \
485 {"embedded-pic", MASK_EMBEDDED_PIC}, \
486 {"no-embedded-pic", -MASK_EMBEDDED_PIC}, \
487 {"embedded-data", MASK_EMBEDDED_DATA}, \
488 {"no-embedded-data", -MASK_EMBEDDED_DATA}, \
489 {"eb", MASK_BIG_ENDIAN}, \
490 {"el", -MASK_BIG_ENDIAN}, \
491 {"single-float", MASK_SINGLE_FLOAT}, \
492 {"double-float", -MASK_SINGLE_FLOAT}, \
494 {"no-mad", -MASK_MAD}, \
495 {"fix4300", MASK_4300_MUL_FIX}, \
496 {"no-fix4300", -MASK_4300_MUL_FIX}, \
497 {"4650", MASK_MAD | MASK_SINGLE_FLOAT}, \
498 {"3900", MASK_MIPS3900}, \
499 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV}, \
500 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV}, \
501 {"check-range-division",MASK_CHECK_RANGE_DIV}, \
502 {"no-check-range-division",-MASK_CHECK_RANGE_DIV}, \
503 {"debug", MASK_DEBUG}, \
504 {"debuga", MASK_DEBUG_A}, \
505 {"debugb", MASK_DEBUG_B}, \
506 {"debugc", MASK_DEBUG_C}, \
507 {"debugd", MASK_DEBUG_D}, \
508 {"debuge", MASK_DEBUG_E}, \
509 {"debugf", MASK_DEBUG_F}, \
510 {"debugg", MASK_DEBUG_G}, \
511 {"debugh", MASK_DEBUG_H}, \
512 {"debugi", MASK_DEBUG_I}, \
513 {"", (TARGET_DEFAULT \
514 | TARGET_CPU_DEFAULT \
515 | TARGET_ENDIAN_DEFAULT)} \
518 /* Default target_flags if no switches are specified */
520 #ifndef TARGET_DEFAULT
521 #define TARGET_DEFAULT 0
524 #ifndef TARGET_CPU_DEFAULT
525 #define TARGET_CPU_DEFAULT 0
528 #ifndef TARGET_ENDIAN_DEFAULT
530 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
532 #define TARGET_ENDIAN_DEFAULT 0
536 #ifndef MULTILIB_DEFAULTS
537 #if TARGET_ENDIAN_DEFAULT == 0
538 #define MULTILIB_DEFAULTS { "EL", "mips1" }
540 #define MULTILIB_DEFAULTS { "EB", "mips1" }
544 /* We must pass -EL to the linker by default for little endian embedded
545 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
546 linker will default to using big-endian output files. The OUTPUT_FORMAT
547 line must be in the linker script, otherwise -EB/-EL will not work. */
549 #ifndef LINKER_ENDIAN_SPEC
550 #if TARGET_ENDIAN_DEFAULT == 0
551 #define LINKER_ENDIAN_SPEC "%{!EB:%{!meb:-EL}}"
553 #define LINKER_ENDIAN_SPEC ""
557 /* This macro is similar to `TARGET_SWITCHES' but defines names of
558 command options that have values. Its definition is an
559 initializer with a subgrouping for each command option.
561 Each subgrouping contains a string constant, that defines the
562 fixed part of the option name, and the address of a variable.
563 The variable, type `char *', is set to the variable part of the
564 given option if the fixed part matches. The actual option name
565 is made by appending `-m' to the specified name.
567 Here is an example which defines `-mshort-data-NUMBER'. If the
568 given option is `-mshort-data-512', the variable `m88k_short_data'
569 will be set to the string `"512"'.
571 extern char *m88k_short_data;
572 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
574 #define TARGET_OPTIONS \
576 SUBTARGET_TARGET_OPTIONS \
577 { "cpu=", &mips_cpu_string }, \
578 { "ips", &mips_isa_string }, \
579 { "entry", &mips_entry_string }, \
580 { "no-mips16", &mips_no_mips16_string } \
583 /* This is meant to be redefined in the host dependent files. */
584 #define SUBTARGET_TARGET_OPTIONS
586 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && (TARGET_MIPS3900 || (mips_isa >= 2)))
588 /* Generate three-operand multiply instructions for both SImode and DImode. */
589 #define GENERATE_MULT3 (TARGET_MIPS3900 \
592 /* Macros to decide whether certain features are available or not,
593 depending on the instruction set architecture level. */
595 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
596 #define HAVE_SQRT_P() (mips_isa >= 2)
598 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
599 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
600 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
601 target_flags, and -mgp64 sets MASK_64BIT.
603 Setting MASK_64BIT in target_flags will cause gcc to assume that
604 registers are 64 bits wide. int, long and void * will be 32 bit;
605 this may be changed with -mint64 or -mlong64.
607 The gen* programs link code that refers to MASK_64BIT. They don't
608 actually use the information in target_flags; they just refer to
611 /* Switch Recognition by gcc.c. Add -G xx support */
613 #ifdef SWITCH_TAKES_ARG
614 #undef SWITCH_TAKES_ARG
617 #define SWITCH_TAKES_ARG(CHAR) \
618 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
620 /* Sometimes certain combinations of command options do not make sense
621 on a particular target machine. You can define a macro
622 `OVERRIDE_OPTIONS' to take account of this. This macro, if
623 defined, is executed once just after all the command options have
626 On the MIPS, it is used to handle -G. We also use it to set up all
627 of the tables referenced in the other macros. */
629 #define OVERRIDE_OPTIONS override_options ()
631 /* Zero or more C statements that may conditionally modify two
632 variables `fixed_regs' and `call_used_regs' (both of type `char
633 []') after they have been initialized from the two preceding
636 This is necessary in case the fixed or call-clobbered registers
637 depend on target flags.
639 You need not define this macro if it has no work to do.
641 If the usage of an entire class of registers depends on the target
642 flags, you may indicate this to GCC by using this macro to modify
643 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
644 the classes which should not be used by GCC. Also define the macro
645 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
646 letter for a class that shouldn't be used.
648 (However, if this class is not included in `GENERAL_REGS' and all
649 of the insn patterns whose constraints permit this class are
650 controlled by target switches, then GCC will automatically avoid
651 using these registers when the target switches are opposed to
654 #define CONDITIONAL_REGISTER_USAGE \
657 if (!TARGET_HARD_FLOAT) \
661 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
662 fixed_regs[regno] = call_used_regs[regno] = 1; \
663 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
664 fixed_regs[regno] = call_used_regs[regno] = 1; \
666 else if (mips_isa < 4) \
670 /* We only have a single condition code register. We \
671 implement this by hiding all the condition code registers, \
672 and generating RTL that refers directly to ST_REG_FIRST. */ \
673 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
674 fixed_regs[regno] = call_used_regs[regno] = 1; \
676 /* In mips16 mode, we permit the $t temporary registers to be used \
677 for reload. We prohibit the unused $s registers, since they \
678 are caller saved, and saving them via a mips16 register would \
679 probably waste more time than just reloading the value. */ \
682 fixed_regs[18] = call_used_regs[18] = 1; \
683 fixed_regs[19] = call_used_regs[19] = 1; \
684 fixed_regs[20] = call_used_regs[20] = 1; \
685 fixed_regs[21] = call_used_regs[21] = 1; \
686 fixed_regs[22] = call_used_regs[22] = 1; \
687 fixed_regs[23] = call_used_regs[23] = 1; \
688 fixed_regs[26] = call_used_regs[26] = 1; \
689 fixed_regs[27] = call_used_regs[27] = 1; \
690 fixed_regs[30] = call_used_regs[30] = 1; \
692 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
696 /* This is meant to be redefined in the host dependent files. */
697 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
699 /* Show we can debug even without a frame pointer. */
700 #define CAN_DEBUG_WITHOUT_FP
702 /* Complain about missing specs and predefines that should be defined in each
703 of the target tm files to override the defaults. This is mostly a place-
704 holder until I can get each of the files updated [mm]. */
706 #if defined(OSF_OS) \
707 || defined(DECSTATION) \
708 || defined(SGI_TARGET) \
709 || defined(MIPS_NEWS) \
710 || defined(MIPS_SYSV) \
711 || defined(MIPS_SVR4) \
712 || defined(MIPS_BSD43)
714 #ifndef CPP_PREDEFINES
715 #error "Define CPP_PREDEFINES in the appropriate tm.h file"
719 #error "Define LIB_SPEC in the appropriate tm.h file"
722 #ifndef STARTFILE_SPEC
723 #error "Define STARTFILE_SPEC in the appropriate tm.h file"
727 #error "Define MACHINE_TYPE in the appropriate tm.h file"
731 /* Tell collect what flags to pass to nm. */
733 #define NM_FLAGS "-Bn"
737 /* Names to predefine in the preprocessor for this target machine. */
739 #ifndef CPP_PREDEFINES
740 #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000 -DSYSTYPE_BSD43 \
741 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
742 -Asystem(unix) -Asystem(bsd) -Acpu(mips) -Amachine(mips)"
745 /* Assembler specs. */
747 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
750 #define MIPS_AS_ASM_SPEC "\
751 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
752 %{pipe: %e-pipe is not supported.} \
753 %{K} %(subtarget_mips_as_asm_spec)"
755 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
756 rather than gas. It may be overridden by subtargets. */
758 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
759 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
762 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
765 #define GAS_ASM_SPEC "%{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v}"
767 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
768 GAS_ASM_SPEC as the default, depending upon the value of
771 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
774 #define TARGET_ASM_SPEC "\
775 %{mmips-as: %(mips_as_asm_spec)} \
776 %{!mmips-as: %(gas_asm_spec)}"
780 #define TARGET_ASM_SPEC "\
781 %{!mgas: %(mips_as_asm_spec)} \
782 %{mgas: %(gas_asm_spec)}"
786 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
787 to the assembler. It may be overridden by subtargets. */
788 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
789 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
791 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
794 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
795 the assembler. It may be overridden by subtargets. */
796 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
797 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
798 %{g} %{g0} %{g1} %{g2} %{g3} \
799 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
800 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
801 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
802 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
805 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
806 overridden by subtargets. */
808 #ifndef SUBTARGET_ASM_SPEC
809 #define SUBTARGET_ASM_SPEC ""
812 /* ASM_SPEC is the set of arguments to pass to the assembler. */
815 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
816 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
817 %(subtarget_asm_optimizing_spec) \
818 %(subtarget_asm_debugging_spec) \
820 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
822 %(subtarget_asm_spec)"
824 /* Specify to run a post-processor, mips-tfile after the assembler
825 has run to stuff the mips debug information into the object file.
826 This is needed because the $#!%^ MIPS assembler provides no way
827 of specifying such information in the assembly file. If we are
828 cross compiling, disable mips-tfile unless the user specifies
831 #ifndef ASM_FINAL_SPEC
832 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
834 #define ASM_FINAL_SPEC "\
835 %{mmips-as: %{!mno-mips-tfile: \
836 \n mips-tfile %{v*: -v} \
838 %{!K: %{save-temps: -I %b.o~}} \
839 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
840 %{.s:%i} %{!.s:%g.s}}}"
844 #define ASM_FINAL_SPEC "\
845 %{!mgas: %{!mno-mips-tfile: \
846 \n mips-tfile %{v*: -v} \
848 %{!K: %{save-temps: -I %b.o~}} \
849 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
850 %{.s:%i} %{!.s:%g.s}}}"
853 #endif /* ASM_FINAL_SPEC */
855 /* Redefinition of libraries used. Mips doesn't support normal
856 UNIX style profiling via calling _mcount. It does offer
857 profiling that samples the PC, so do what we can... */
860 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
863 /* Extra switches sometimes passed to the linker. */
864 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
865 will interpret it as a -b option. */
869 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} \
870 %{bestGnum} %{shared} %{non_shared} \
871 %(linker_endian_spec)"
872 #endif /* LINK_SPEC defined */
874 /* Specs for the compiler proper */
876 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
877 overridden by subtargets. */
878 #ifndef SUBTARGET_CC1_SPEC
879 #define SUBTARGET_CC1_SPEC ""
882 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
886 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
887 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
888 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
889 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
890 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
891 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
892 %{m4650:-mcpu=r4650} \
893 %{m3900:-mips1 -mcpu=r3900 -mfp32 -mgp32} \
894 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
895 %{pic-none: -mno-half-pic} \
896 %{pic-lib: -mhalf-pic} \
897 %{pic-extern: -mhalf-pic} \
898 %{pic-calls: -mhalf-pic} \
900 %(subtarget_cc1_spec) "
903 /* Preprocessor specs. */
905 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
906 be overridden by subtargets. */
908 #ifndef SUBTARGET_CPP_SIZE_SPEC
909 #define SUBTARGET_CPP_SIZE_SPEC "\
910 %{mlong64:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int} \
911 %{!mlong64:-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int}"
914 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
915 overridden by subtargets. */
916 #ifndef SUBTARGET_CPP_SPEC
917 #define SUBTARGET_CPP_SPEC ""
920 /* If we're using 64bit longs, then we have to define __LONG_MAX__
921 correctly. Similarly for 64bit ints and __INT_MAX__. */
922 #ifndef LONG_MAX_SPEC
923 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
924 #define LONG_MAX_SPEC "%{!mno-long64:-D__LONG_MAX__=9223372036854775807L}"
926 #define LONG_MAX_SPEC "%{mlong64:-D__LONG_MAX__=9223372036854775807L}"
930 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
934 %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
935 %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
936 %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
937 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
938 %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
939 %{.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
940 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}} \
941 %(subtarget_cpp_size_spec) \
942 %{mips3:-U__mips -D__mips=3 -D__mips64} \
943 %{mips4:-U__mips -D__mips=4 -D__mips64} \
944 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
945 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
946 %{m4650:%{!msoft-float:-D__mips_single_float}} \
947 %{msoft-float:-D__mips_soft_float} \
948 %{mabi=eabi:-D__mips_eabi} \
949 %{mips16:%{!mno-mips16:-D__mips16}} \
950 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
951 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
953 %(subtarget_cpp_spec) "
956 /* This macro defines names of additional specifications to put in the specs
957 that can be used in various specifications like CC1_SPEC. Its definition
958 is an initializer with a subgrouping for each command option.
960 Each subgrouping contains a string constant, that defines the
961 specification name, and a string constant that used by the GNU CC driver
964 Do not define this macro if it does not need to do anything. */
966 #define EXTRA_SPECS \
967 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
968 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
969 { "subtarget_cpp_size_spec", SUBTARGET_CPP_SIZE_SPEC }, \
970 { "long_max_spec", LONG_MAX_SPEC }, \
971 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
972 { "gas_asm_spec", GAS_ASM_SPEC }, \
973 { "target_asm_spec", TARGET_ASM_SPEC }, \
974 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
975 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
976 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
977 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
978 { "linker_endian_spec", LINKER_ENDIAN_SPEC }, \
979 SUBTARGET_EXTRA_SPECS
981 #ifndef SUBTARGET_EXTRA_SPECS
982 #define SUBTARGET_EXTRA_SPECS
985 /* If defined, this macro is an additional prefix to try after
986 `STANDARD_EXEC_PREFIX'. */
988 #ifndef MD_EXEC_PREFIX
989 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
992 #ifndef MD_STARTFILE_PREFIX
993 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
997 /* Print subsidiary information on the compiler version in use. */
999 #define MIPS_VERSION "[AL 1.1, MM 40]"
1001 #ifndef MACHINE_TYPE
1002 #define MACHINE_TYPE "BSD Mips"
1005 #ifndef TARGET_VERSION_INTERNAL
1006 #define TARGET_VERSION_INTERNAL(STREAM) \
1007 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1010 #ifndef TARGET_VERSION
1011 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1015 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1016 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1017 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1019 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1020 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1023 /* By default, turn on GDB extensions. */
1024 #define DEFAULT_GDB_EXTENSIONS 1
1026 /* If we are passing smuggling stabs through the MIPS ECOFF object
1027 format, put a comment in front of the .stab<x> operation so
1028 that the MIPS assembler does not choke. The mips-tfile program
1029 will correctly put the stab into the object file. */
1031 #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
1032 #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
1033 #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
1035 /* Local compiler-generated symbols must have a prefix that the assembler
1036 understands. By default, this is $, although some targets (e.g.,
1037 NetBSD-ELF) need to override this. */
1039 #ifndef LOCAL_LABEL_PREFIX
1040 #define LOCAL_LABEL_PREFIX "$"
1043 /* By default on the mips, external symbols do not have an underscore
1044 prepended, but some targets (e.g., NetBSD) require this. */
1046 #ifndef USER_LABEL_PREFIX
1047 #define USER_LABEL_PREFIX ""
1050 /* Forward references to tags are allowed. */
1051 #define SDB_ALLOW_FORWARD_REFERENCES
1053 /* Unknown tags are also allowed. */
1054 #define SDB_ALLOW_UNKNOWN_REFERENCES
1056 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1057 since the length can run past this up to a continuation point. */
1058 #define DBX_CONTIN_LENGTH 1500
1060 /* How to renumber registers for dbx and gdb. */
1061 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1063 /* The mapping from gcc register number to DWARF 2 CFA column number.
1064 This mapping does not allow for tracking register 0, since SGI's broken
1065 dwarf reader thinks column 0 is used for the frame address, but since
1066 register 0 is fixed this is not a problem. */
1067 #define DWARF_FRAME_REGNUM(REG) \
1068 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1070 /* The DWARF 2 CFA column which tracks the return address. */
1071 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1073 /* Before the prologue, RA lives in r31. */
1074 #define INCOMING_RETURN_ADDR_RTX gen_rtx (REG, VOIDmode, GP_REG_FIRST + 31)
1076 /* Overrides for the COFF debug format. */
1077 #define PUT_SDB_SCL(a) \
1079 extern FILE *asm_out_text_file; \
1080 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1083 #define PUT_SDB_INT_VAL(a) \
1085 extern FILE *asm_out_text_file; \
1086 fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
1089 #define PUT_SDB_VAL(a) \
1091 extern FILE *asm_out_text_file; \
1092 fputs ("\t.val\t", asm_out_text_file); \
1093 output_addr_const (asm_out_text_file, (a)); \
1094 fputc (';', asm_out_text_file); \
1097 #define PUT_SDB_DEF(a) \
1099 extern FILE *asm_out_text_file; \
1100 fprintf (asm_out_text_file, "\t%s.def\t", \
1101 (TARGET_GAS) ? "" : "#"); \
1102 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1103 fputc (';', asm_out_text_file); \
1106 #define PUT_SDB_PLAIN_DEF(a) \
1108 extern FILE *asm_out_text_file; \
1109 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1110 (TARGET_GAS) ? "" : "#", (a)); \
1113 #define PUT_SDB_ENDEF \
1115 extern FILE *asm_out_text_file; \
1116 fprintf (asm_out_text_file, "\t.endef\n"); \
1119 #define PUT_SDB_TYPE(a) \
1121 extern FILE *asm_out_text_file; \
1122 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1125 #define PUT_SDB_SIZE(a) \
1127 extern FILE *asm_out_text_file; \
1128 fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
1131 #define PUT_SDB_DIM(a) \
1133 extern FILE *asm_out_text_file; \
1134 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1137 #ifndef PUT_SDB_START_DIM
1138 #define PUT_SDB_START_DIM \
1140 extern FILE *asm_out_text_file; \
1141 fprintf (asm_out_text_file, "\t.dim\t"); \
1145 #ifndef PUT_SDB_NEXT_DIM
1146 #define PUT_SDB_NEXT_DIM(a) \
1148 extern FILE *asm_out_text_file; \
1149 fprintf (asm_out_text_file, "%d,", a); \
1153 #ifndef PUT_SDB_LAST_DIM
1154 #define PUT_SDB_LAST_DIM(a) \
1156 extern FILE *asm_out_text_file; \
1157 fprintf (asm_out_text_file, "%d;", a); \
1161 #define PUT_SDB_TAG(a) \
1163 extern FILE *asm_out_text_file; \
1164 fprintf (asm_out_text_file, "\t.tag\t"); \
1165 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1166 fputc (';', asm_out_text_file); \
1169 /* For block start and end, we create labels, so that
1170 later we can figure out where the correct offset is.
1171 The normal .ent/.end serve well enough for functions,
1172 so those are just commented out. */
1174 #define PUT_SDB_BLOCK_START(LINE) \
1176 extern FILE *asm_out_text_file; \
1177 fprintf (asm_out_text_file, \
1178 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1179 LOCAL_LABEL_PREFIX, \
1181 (TARGET_GAS) ? "" : "#", \
1182 LOCAL_LABEL_PREFIX, \
1185 sdb_label_count++; \
1188 #define PUT_SDB_BLOCK_END(LINE) \
1190 extern FILE *asm_out_text_file; \
1191 fprintf (asm_out_text_file, \
1192 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1193 LOCAL_LABEL_PREFIX, \
1195 (TARGET_GAS) ? "" : "#", \
1196 LOCAL_LABEL_PREFIX, \
1199 sdb_label_count++; \
1202 #define PUT_SDB_FUNCTION_START(LINE)
1204 #define PUT_SDB_FUNCTION_END(LINE) \
1206 extern FILE *asm_out_text_file; \
1207 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1210 #define PUT_SDB_EPILOGUE_END(NAME)
1212 #define PUT_SDB_SRC_FILE(FILENAME) \
1214 extern FILE *asm_out_text_file; \
1215 output_file_directive (asm_out_text_file, (FILENAME)); \
1218 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1219 sprintf ((BUFFER), ".%dfake", (NUMBER));
1221 /* Correct the offset of automatic variables and arguments. Note that
1222 the MIPS debug format wants all automatic variables and arguments
1223 to be in terms of the virtual frame pointer (stack pointer before
1224 any adjustment in the function), while the MIPS 3.0 linker wants
1225 the frame pointer to be the stack pointer after the initial
1228 #define DEBUGGER_AUTO_OFFSET(X) \
1229 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1230 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1231 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1233 /* Tell collect that the object format is ECOFF */
1234 #ifndef OBJECT_FORMAT_ROSE
1235 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1236 #define EXTENDED_COFF /* ECOFF, not normal coff */
1239 #if 0 /* These definitions normally have no effect because
1240 MIPS systems define USE_COLLECT2, so
1241 assemble_constructor does nothing anyway. */
1243 /* Don't use the default definitions, because we don't have gld.
1244 Also, we don't want stabs when generating ECOFF output.
1245 Instead we depend on collect to handle these. */
1247 #define ASM_OUTPUT_CONSTRUCTOR(file, name)
1248 #define ASM_OUTPUT_DESTRUCTOR(file, name)
1252 /* Target machine storage layout */
1254 /* Define in order to support both big and little endian float formats
1255 in the same gcc binary. */
1256 #define REAL_ARITHMETIC
1258 /* Define this if most significant bit is lowest numbered
1259 in instructions that operate on numbered bit-fields.
1261 #define BITS_BIG_ENDIAN 0
1263 /* Define this if most significant byte of a word is the lowest numbered. */
1264 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1266 /* Define this if most significant word of a multiword number is the lowest. */
1267 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1269 /* Define this to set the endianness to use in libgcc2.c, which can
1270 not depend on target_flags. */
1271 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1272 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1274 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1277 /* Number of bits in an addressable storage unit */
1278 #define BITS_PER_UNIT 8
1280 /* Width in bits of a "word", which is the contents of a machine register.
1281 Note that this is not necessarily the width of data type `int';
1282 if using 16-bit ints on a 68000, this would still be 32.
1283 But on a machine with 16-bit registers, this would be 16. */
1284 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1285 #define MAX_BITS_PER_WORD 64
1287 /* Width of a word, in units (bytes). */
1288 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1289 #define MIN_UNITS_PER_WORD 4
1291 /* For MIPS, width of a floating point register. */
1292 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1294 /* A C expression for the size in bits of the type `int' on the
1295 target machine. If you don't define this, the default is one
1297 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1298 #define MAX_INT_TYPE_SIZE 64
1300 /* Tell the preprocessor the maximum size of wchar_t. */
1301 #ifndef MAX_WCHAR_TYPE_SIZE
1302 #ifndef WCHAR_TYPE_SIZE
1303 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1307 /* A C expression for the size in bits of the type `short' on the
1308 target machine. If you don't define this, the default is half a
1309 word. (If this would be less than one storage unit, it is
1310 rounded up to one unit.) */
1311 #define SHORT_TYPE_SIZE 16
1313 /* A C expression for the size in bits of the type `long' on the
1314 target machine. If you don't define this, the default is one
1316 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1317 #define MAX_LONG_TYPE_SIZE 64
1319 /* A C expression for the size in bits of the type `long long' on the
1320 target machine. If you don't define this, the default is two
1322 #define LONG_LONG_TYPE_SIZE 64
1324 /* A C expression for the size in bits of the type `char' on the
1325 target machine. If you don't define this, the default is one
1326 quarter of a word. (If this would be less than one storage unit,
1327 it is rounded up to one unit.) */
1328 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1330 /* A C expression for the size in bits of the type `float' on the
1331 target machine. If you don't define this, the default is one
1333 #define FLOAT_TYPE_SIZE 32
1335 /* A C expression for the size in bits of the type `double' on the
1336 target machine. If you don't define this, the default is two
1338 #define DOUBLE_TYPE_SIZE 64
1340 /* A C expression for the size in bits of the type `long double' on
1341 the target machine. If you don't define this, the default is two
1343 #define LONG_DOUBLE_TYPE_SIZE 64
1345 /* Width in bits of a pointer.
1346 See also the macro `Pmode' defined below. */
1347 #ifndef POINTER_SIZE
1348 #define POINTER_SIZE (TARGET_LONG64 ? 64 : 32)
1351 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1352 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1354 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1355 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1357 /* Allocation boundary (in *bits*) for the code of a function. */
1358 #define FUNCTION_BOUNDARY 32
1360 /* Alignment of field after `int : 0' in a structure. */
1361 #define EMPTY_FIELD_BOUNDARY 32
1363 /* Every structure's size must be a multiple of this. */
1364 /* 8 is observed right on a DECstation and on riscos 4.02. */
1365 #define STRUCTURE_SIZE_BOUNDARY 8
1367 /* There is no point aligning anything to a rounder boundary than this. */
1368 #define BIGGEST_ALIGNMENT 64
1370 /* Set this nonzero if move instructions will actually fail to work
1371 when given unaligned data. */
1372 #define STRICT_ALIGNMENT 1
1374 /* Define this if you wish to imitate the way many other C compilers
1375 handle alignment of bitfields and the structures that contain
1378 The behavior is that the type written for a bitfield (`int',
1379 `short', or other integer type) imposes an alignment for the
1380 entire structure, as if the structure really did contain an
1381 ordinary field of that type. In addition, the bitfield is placed
1382 within the structure so that it would fit within such a field,
1383 not crossing a boundary for it.
1385 Thus, on most machines, a bitfield whose type is written as `int'
1386 would not cross a four-byte boundary, and would force four-byte
1387 alignment for the whole structure. (The alignment used may not
1388 be four bytes; it is controlled by the other alignment
1391 If the macro is defined, its definition should be a C expression;
1392 a nonzero value for the expression enables this behavior. */
1394 #define PCC_BITFIELD_TYPE_MATTERS 1
1396 /* If defined, a C expression to compute the alignment given to a
1397 constant that is being placed in memory. CONSTANT is the constant
1398 and ALIGN is the alignment that the object would ordinarily have.
1399 The value of this macro is used instead of that alignment to align
1402 If this macro is not defined, then ALIGN is used.
1404 The typical use of this macro is to increase alignment for string
1405 constants to be word aligned so that `strcpy' calls that copy
1406 constants can be done inline. */
1408 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1409 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1410 && (ALIGN) < BITS_PER_WORD \
1414 /* If defined, a C expression to compute the alignment for a static
1415 variable. TYPE is the data type, and ALIGN is the alignment that
1416 the object would ordinarily have. The value of this macro is used
1417 instead of that alignment to align the object.
1419 If this macro is not defined, then ALIGN is used.
1421 One use of this macro is to increase alignment of medium-size
1422 data to make it all fit in fewer cache lines. Another is to
1423 cause character arrays to be word-aligned so that `strcpy' calls
1424 that copy constants to character arrays can be done inline. */
1426 #undef DATA_ALIGNMENT
1427 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1428 ((((ALIGN) < BITS_PER_WORD) \
1429 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1430 || TREE_CODE (TYPE) == UNION_TYPE \
1431 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1433 /* Define this macro if an argument declared as `char' or `short' in a
1434 prototype should actually be passed as an `int'. In addition to
1435 avoiding errors in certain cases of mismatch, it also makes for
1436 better code on certain machines. */
1438 #define PROMOTE_PROTOTYPES
1440 /* Define if operations between registers always perform the operation
1441 on the full register even if a narrower mode is specified. */
1442 #define WORD_REGISTER_OPERATIONS
1444 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1445 will either zero-extend or sign-extend. The value of this macro should
1446 be the code that says which one of the two operations is implicitly
1449 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1450 moves. All other referces are zero extended. */
1451 #define LOAD_EXTEND_OP(MODE) \
1452 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1453 ? SIGN_EXTEND : ZERO_EXTEND)
1455 /* Define this macro if it is advisable to hold scalars in registers
1456 in a wider mode than that declared by the program. In such cases,
1457 the value is constrained to be within the bounds of the declared
1458 type, but kept valid in the wider mode. The signedness of the
1459 extension may differ from that of the type.
1461 We promote any value smaller than SImode up to SImode. We don't
1462 want to promote to DImode when in 64 bit mode, because that would
1463 prevent us from using the faster SImode multiply and divide
1466 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1467 if (GET_MODE_CLASS (MODE) == MODE_INT \
1468 && GET_MODE_SIZE (MODE) < 4) \
1471 /* Define this if function arguments should also be promoted using the above
1474 #define PROMOTE_FUNCTION_ARGS
1476 /* Likewise, if the function return value is promoted. */
1478 #define PROMOTE_FUNCTION_RETURN
1480 /* Standard register usage. */
1482 /* Number of actual hardware registers.
1483 The hardware registers are assigned numbers for the compiler
1484 from 0 to just below FIRST_PSEUDO_REGISTER.
1485 All registers that the compiler knows about must be given numbers,
1486 even those that are not normally considered general registers.
1488 On the Mips, we have 32 integer registers, 32 floating point
1489 registers, 8 condition code registers, and the special registers
1490 hi, lo, hilo, and rap. The 8 condition code registers are only
1491 used if mips_isa >= 4. The hilo register is only used in 64 bit
1492 mode. It represents a 64 bit value stored as two 32 bit values in
1493 the hi and lo registers; this is the result of the mult
1494 instruction. rap is a pointer to the stack where the return
1495 address reg ($31) was stored. This is needed for C++ exception
1498 #define FIRST_PSEUDO_REGISTER 76
1500 /* 1 for registers that have pervasive standard uses
1501 and are not available for the register allocator.
1503 On the MIPS, see conventions, page D-2 */
1505 #define FIXED_REGISTERS \
1507 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1508 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1509 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1510 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1515 /* 1 for registers not available across function calls.
1516 These must include the FIXED_REGISTERS and also any
1517 registers that can be used without being saved.
1518 The latter must include the registers where values are returned
1519 and the register where structure-value addresses are passed.
1520 Aside from that, you can include as many other registers as you like. */
1522 #define CALL_USED_REGISTERS \
1524 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1525 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1526 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1527 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1528 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1532 /* Internal macros to classify a register number as to whether it's a
1533 general purpose register, a floating point register, a
1534 multiply/divide register, or a status register. */
1536 #define GP_REG_FIRST 0
1537 #define GP_REG_LAST 31
1538 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1539 #define GP_DBX_FIRST 0
1541 #define FP_REG_FIRST 32
1542 #define FP_REG_LAST 63
1543 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1544 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1546 #define MD_REG_FIRST 64
1547 #define MD_REG_LAST 66
1548 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1550 #define ST_REG_FIRST 67
1551 #define ST_REG_LAST 74
1552 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1554 #define RAP_REG_NUM 75
1556 #define AT_REGNUM (GP_REG_FIRST + 1)
1557 #define HI_REGNUM (MD_REG_FIRST + 0)
1558 #define LO_REGNUM (MD_REG_FIRST + 1)
1559 #define HILO_REGNUM (MD_REG_FIRST + 2)
1561 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1562 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1563 should be used instead. */
1564 #define FPSW_REGNUM ST_REG_FIRST
1566 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1567 #define M16_REG_P(REGNO) \
1568 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1569 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1570 #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1571 #define ST_REG_P(REGNO) ((unsigned) ((REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1573 /* Return number of consecutive hard regs needed starting at reg REGNO
1574 to hold something of mode MODE.
1575 This is ordinarily the length in words of a value of mode MODE
1576 but can be less for certain modes in special long registers.
1578 On the MIPS, all general registers are one word long. Except on
1579 the R4000 with the FR bit set, the floating point uses register
1580 pairs, with the second register not being allocable. */
1582 #define HARD_REGNO_NREGS(REGNO, MODE) \
1583 (! FP_REG_P (REGNO) \
1584 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1585 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1587 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1588 MODE. In 32 bit mode, require that DImode and DFmode be in even
1589 registers. For DImode, this makes some of the insns easier to
1590 write, since you don't have to worry about a DImode value in
1591 registers 3 & 4, producing a result in 4 & 5.
1593 To make the code simpler HARD_REGNO_MODE_OK now just references an
1594 array built in override_options. Because machmodes.h is not yet
1595 included before this file is processed, the MODE bound can't be
1598 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1600 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1601 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1603 /* Value is 1 if it is a good idea to tie two pseudo registers
1604 when one has mode MODE1 and one has mode MODE2.
1605 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1606 for any hard reg, then this must be 0 for correct output. */
1607 #define MODES_TIEABLE_P(MODE1, MODE2) \
1608 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1609 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1610 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1611 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1613 /* MIPS pc is not overloaded on a register. */
1614 /* #define PC_REGNUM xx */
1616 /* Register to use for pushing function arguments. */
1617 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1619 /* Offset from the stack pointer to the first available location. Use
1620 the default value zero. */
1621 /* #define STACK_POINTER_OFFSET 0 */
1623 /* Base register for access to local variables of the function. We
1624 pretend that the frame pointer is $1, and then eliminate it to
1625 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1626 a fixed register, and will not be used for anything else. */
1627 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1629 /* $30 is not available on the mips16, so we use $17 as the frame
1631 #define HARD_FRAME_POINTER_REGNUM \
1632 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1634 /* Value should be nonzero if functions must have frame pointers.
1635 Zero means the frame pointer need not be set up (and parms
1636 may be accessed via the stack pointer) in functions that seem suitable.
1637 This is computed in `reload', in reload1.c. */
1638 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1640 /* Base register for access to arguments of the function. */
1641 #define ARG_POINTER_REGNUM GP_REG_FIRST
1643 /* Fake register that holds the address on the stack of the
1644 current function's return address. */
1645 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1647 /* Register in which static-chain is passed to a function. */
1648 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1650 /* If the structure value address is passed in a register, then
1651 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1652 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1654 /* If the structure value address is not passed in a register, define
1655 `STRUCT_VALUE' as an expression returning an RTX for the place
1656 where the address is passed. If it returns 0, the address is
1657 passed as an "invisible" first argument. */
1658 #define STRUCT_VALUE 0
1660 /* Mips registers used in prologue/epilogue code when the stack frame
1661 is larger than 32K bytes. These registers must come from the
1662 scratch register set, and not used for passing and returning
1663 arguments and any other information used in the calling sequence
1664 (such as pic). Must start at 12, since t0/t3 are parameter passing
1665 registers in the 64 bit ABI. */
1667 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1668 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1670 /* Define this macro if it is as good or better to call a constant
1671 function address than to call an address kept in a register. */
1672 #define NO_FUNCTION_CSE 1
1674 /* Define this macro if it is as good or better for a function to
1675 call itself with an explicit address than to call an address
1676 kept in a register. */
1677 #define NO_RECURSIVE_FUNCTION_CSE 1
1679 /* The register number of the register used to address a table of
1680 static data addresses in memory. In some cases this register is
1681 defined by a processor's "application binary interface" (ABI).
1682 When this macro is defined, RTL is generated for this register
1683 once, as with the stack pointer and frame pointer registers. If
1684 this macro is not defined, it is up to the machine-dependent
1685 files to allocate such a register (if necessary). */
1686 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1688 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1690 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1691 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1692 isn't always called for static inline functions. */
1693 #define INIT_EXPANDERS \
1695 embedded_pic_fnaddr_rtx = NULL; \
1696 mips16_gp_pseudo_rtx = NULL; \
1699 /* Define the classes of registers for register constraints in the
1700 machine description. Also define ranges of constants.
1702 One of the classes must always be named ALL_REGS and include all hard regs.
1703 If there is more than one class, another class must be named NO_REGS
1704 and contain no registers.
1706 The name GENERAL_REGS must be the name of a class (or an alias for
1707 another name such as ALL_REGS). This is the class of registers
1708 that is allowed by "g" or "r" in a register constraint.
1709 Also, registers outside this class are allocated only when
1710 instructions express preferences for them.
1712 The classes must be numbered in nondecreasing order; that is,
1713 a larger-numbered class must never be contained completely
1714 in a smaller-numbered class.
1716 For any two classes, it is very desirable that there be another
1717 class that represents their union. */
1721 NO_REGS, /* no registers in set */
1722 M16_NA_REGS, /* mips16 regs not used to pass args */
1723 M16_REGS, /* mips16 directly accessible registers */
1724 T_REG, /* mips16 T register ($24) */
1725 M16_T_REGS, /* mips16 registers plus T register */
1726 GR_REGS, /* integer registers */
1727 FP_REGS, /* floating point registers */
1728 HI_REG, /* hi register */
1729 LO_REG, /* lo register */
1730 HILO_REG, /* hilo register pair for 64 bit mode mult */
1731 MD_REGS, /* multiply/divide registers (hi/lo) */
1732 HI_AND_GR_REGS, /* union classes */
1735 ST_REGS, /* status registers (fp status) */
1736 ALL_REGS, /* all registers */
1737 LIM_REG_CLASSES /* max value + 1 */
1740 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1742 #define GENERAL_REGS GR_REGS
1744 /* An initializer containing the names of the register classes as C
1745 string constants. These names are used in writing some of the
1748 #define REG_CLASS_NAMES \
1763 "HILO_AND_GR_REGS", \
1768 /* An initializer containing the contents of the register classes,
1769 as integers which are bit masks. The Nth integer specifies the
1770 contents of class N. The way the integer MASK is interpreted is
1771 that register R is in the class if `MASK & (1 << R)' is 1.
1773 When the machine has more than 32 registers, an integer does not
1774 suffice. Then the integers are replaced by sub-initializers,
1775 braced groupings containing several integers. Each
1776 sub-initializer must be suitable as an initializer for the type
1777 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1779 #define REG_CLASS_CONTENTS \
1781 { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1782 { 0x0003000c, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1783 { 0x000300fc, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1784 { 0x01000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1785 { 0x010300fc, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1786 { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1787 { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1788 { 0x00000000, 0x00000000, 0x00000001 }, /* hi register */ \
1789 { 0x00000000, 0x00000000, 0x00000002 }, /* lo register */ \
1790 { 0x00000000, 0x00000000, 0x00000004 }, /* hilo register */ \
1791 { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1792 { 0xffffffff, 0x00000000, 0x00000001 }, /* union classes */ \
1793 { 0xffffffff, 0x00000000, 0x00000002 }, \
1794 { 0xffffffff, 0x00000000, 0x00000004 }, \
1795 { 0x00000000, 0x00000000, 0x000007f8 }, /* status registers */ \
1796 { 0xffffffff, 0xffffffff, 0x000007ff } /* all registers */ \
1800 /* A C expression whose value is a register class containing hard
1801 register REGNO. In general there is more that one such class;
1802 choose a class which is "minimal", meaning that no smaller class
1803 also contains the register. */
1805 extern enum reg_class mips_regno_to_class[];
1807 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1809 /* A macro whose definition is the name of the class to which a
1810 valid base register must belong. A base register is one used in
1811 an address which is the register value plus a displacement. */
1813 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1815 /* A macro whose definition is the name of the class to which a
1816 valid index register must belong. An index register is one used
1817 in an address where its value is either multiplied by a scale
1818 factor or added to another register (as well as added to a
1821 #define INDEX_REG_CLASS NO_REGS
1823 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1824 registers explicitly used in the rtl to be used as spill registers
1825 but prevents the compiler from extending the lifetime of these
1828 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1830 /* This macro is used later on in the file. */
1831 #define GR_REG_CLASS_P(CLASS) \
1832 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1833 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1835 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1836 is the default value (allocate the registers in numeric order). We
1837 define it just so that we can override it for the mips16 target in
1838 ORDER_REGS_FOR_LOCAL_ALLOC. */
1840 #define REG_ALLOC_ORDER \
1841 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1842 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1843 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1844 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1845 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1848 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1849 to be rearranged based on a particular function. On the mips16, we
1850 want to allocate $24 (T_REG) before other registers for
1851 instructions for which it is possible. */
1853 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1855 /* REGISTER AND CONSTANT CLASSES */
1857 /* Get reg_class from a letter such as appears in the machine
1860 DEFINED REGISTER CLASSES:
1862 'd' General (aka integer) registers
1863 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1864 'y' General registers (in both mips16 and non mips16 mode)
1865 'e' mips16 non argument registers (M16_NA_REGS)
1866 't' mips16 temporary register ($24)
1867 'f' Floating point registers
1870 'x' Multiply/divide registers
1872 'z' FP Status register
1873 'b' All registers */
1875 extern enum reg_class mips_char_to_class[];
1877 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1879 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1880 string can be used to stand for particular ranges of immediate
1881 operands. This macro defines what the ranges are. C is the
1882 letter, and VALUE is a constant value. Return 1 if VALUE is
1883 in the range specified by C. */
1887 `I' is used for the range of constants an arithmetic insn can
1888 actually contain (16 bits signed integers).
1890 `J' is used for the range which is just zero (ie, $r0).
1892 `K' is used for the range of constants a logical insn can actually
1893 contain (16 bit zero-extended integers).
1895 `L' is used for the range of constants that be loaded with lui
1896 (ie, the bottom 16 bits are zero).
1898 `M' is used for the range of constants that take two words to load
1899 (ie, not matched by `I', `K', and `L').
1901 `N' is used for negative 16 bit constants other than -65536.
1903 `O' is a 15 bit signed integer.
1905 `P' is used for positive 16 bit constants. */
1907 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
1908 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
1910 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1911 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
1912 : (C) == 'J' ? ((VALUE) == 0) \
1913 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
1914 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
1915 && (((VALUE) & ~2147483647) == 0 \
1916 || ((VALUE) & ~2147483647) == ~2147483647)) \
1917 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
1918 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
1919 && (((VALUE) & 0x0000ffff) != 0 \
1920 || (((VALUE) & ~2147483647) != 0 \
1921 && ((VALUE) & ~2147483647) != ~2147483647))) \
1922 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1923 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1924 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1927 /* Similar, but for floating constants, and defining letters G and H.
1928 Here VALUE is the CONST_DOUBLE rtx itself. */
1932 'G' : Floating point 0 */
1934 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1936 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1938 /* Letters in the range `Q' through `U' may be defined in a
1939 machine-dependent fashion to stand for arbitrary operand types.
1940 The machine description macro `EXTRA_CONSTRAINT' is passed the
1941 operand as its first argument and the constraint letter as its
1944 `Q' is for mips16 GP relative constants
1945 `R' is for memory references which take 1 word for the instruction.
1946 `S' is for references to extern items which are PIC for OSF/rose.
1947 `T' is for memory addresses that can be used to load two words. */
1949 #define EXTRA_CONSTRAINT(OP,CODE) \
1950 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
1951 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
1952 && mips16_gp_offset_p (OP)) \
1953 : (GET_CODE (OP) != MEM) ? FALSE \
1954 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1955 : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1956 && HALF_PIC_ADDRESS_P (OP)) \
1959 /* Given an rtx X being reloaded into a reg required to be
1960 in class CLASS, return the class of reg to actually use.
1961 In general this is just CLASS; but on some machines
1962 in some cases it is preferable to use a more restrictive class. */
1964 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1965 ((CLASS) != ALL_REGS \
1966 ? (! TARGET_MIPS16 \
1968 : ((CLASS) != GR_REGS \
1971 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1972 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1973 ? (TARGET_SOFT_FLOAT \
1974 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1976 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1977 || GET_MODE (X) == VOIDmode) \
1978 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
1981 /* Certain machines have the property that some registers cannot be
1982 copied to some other registers without using memory. Define this
1983 macro on those machines to be a C expression that is non-zero if
1984 objects of mode MODE in registers of CLASS1 can only be copied to
1985 registers of class CLASS2 by storing a register of CLASS1 into
1986 memory and loading that memory location into a register of CLASS2.
1988 Do not define this macro if its value would always be zero. */
1990 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1991 ((!TARGET_DEBUG_H_MODE \
1992 && GET_MODE_CLASS (MODE) == MODE_INT \
1993 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1994 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1995 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1996 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1997 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1999 /* The HI and LO registers can only be reloaded via the general
2000 registers. Condition code registers can only be loaded to the
2001 general registers, and from the floating point registers. */
2003 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2004 mips_secondary_reload_class (CLASS, MODE, X, 1)
2005 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2006 mips_secondary_reload_class (CLASS, MODE, X, 0)
2008 /* Not declared above, with the other functions, because enum
2009 reg_class is not declared yet. */
2010 extern enum reg_class mips_secondary_reload_class ();
2012 /* Return the maximum number of consecutive registers
2013 needed to represent mode MODE in a register of class CLASS. */
2015 #define CLASS_UNITS(mode, size) \
2016 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2018 #define CLASS_MAX_NREGS(CLASS, MODE) \
2019 ((CLASS) == FP_REGS \
2021 ? CLASS_UNITS (MODE, 8) \
2022 : 2 * CLASS_UNITS (MODE, 8)) \
2023 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2025 /* If defined, this is a C expression whose value should be
2026 nonzero if the insn INSN has the effect of mysteriously
2027 clobbering the contents of hard register number REGNO. By
2028 "mysterious" we mean that the insn's RTL expression doesn't
2029 describe such an effect.
2031 If this macro is not defined, it means that no insn clobbers
2032 registers mysteriously. This is the usual situation; all else
2033 being equal, it is best for the RTL expression to show all the
2036 /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
2039 /* Stack layout; function entry, exit and calling. */
2041 /* Define this if pushing a word on the stack
2042 makes the stack pointer a smaller address. */
2043 #define STACK_GROWS_DOWNWARD
2045 /* Define this if the nominal address of the stack frame
2046 is at the high-address end of the local variables;
2047 that is, each additional local variable allocated
2048 goes at a more negative offset in the frame. */
2049 /* #define FRAME_GROWS_DOWNWARD */
2051 /* Offset within stack frame to start allocating local variables at.
2052 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2053 first local allocated. Otherwise, it is the offset to the BEGINNING
2054 of the first local allocated. */
2055 #define STARTING_FRAME_OFFSET \
2056 (current_function_outgoing_args_size \
2057 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2059 /* Offset from the stack pointer register to an item dynamically
2060 allocated on the stack, e.g., by `alloca'.
2062 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2063 length of the outgoing arguments. The default is correct for most
2064 machines. See `function.c' for details.
2066 The MIPS ABI states that functions which dynamically allocate the
2067 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2068 we are trying to create a second frame pointer to the function, so
2069 allocate some stack space to make it happy.
2071 However, the linker currently complains about linking any code that
2072 dynamically allocates stack space, and there seems to be a bug in
2073 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2076 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2077 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2078 ? 4*UNITS_PER_WORD \
2079 : current_function_outgoing_args_size)
2082 /* The return address for the current frame is in r31 is this is a leaf
2083 function. Otherwise, it is on the stack. It is at a variable offset
2084 from sp/fp/ap, so we define a fake hard register rap which is a
2085 poiner to the return address on the stack. This always gets eliminated
2086 during reload to be either the frame pointer or the stack pointer plus
2089 /* ??? This definition fails for leaf functions. There is currently no
2090 general solution for this problem. */
2092 /* ??? There appears to be no way to get the return address of any previous
2093 frame except by disassembling instructions in the prologue/epilogue.
2094 So currently we support only the current frame. */
2096 #define RETURN_ADDR_RTX(count, frame) \
2098 ? gen_rtx (MEM, Pmode, gen_rtx (REG, Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2101 /* Structure to be filled in by compute_frame_size with register
2102 save masks, and offsets for the current function. */
2104 struct mips_frame_info
2106 long total_size; /* # bytes that the entire frame takes up */
2107 long var_size; /* # bytes that variables take up */
2108 long args_size; /* # bytes that outgoing arguments take up */
2109 long extra_size; /* # bytes of extra gunk */
2110 int gp_reg_size; /* # bytes needed to store gp regs */
2111 int fp_reg_size; /* # bytes needed to store fp regs */
2112 long mask; /* mask of saved gp registers */
2113 long fmask; /* mask of saved fp registers */
2114 long gp_save_offset; /* offset from vfp to store gp registers */
2115 long fp_save_offset; /* offset from vfp to store fp registers */
2116 long gp_sp_offset; /* offset from new sp to store gp registers */
2117 long fp_sp_offset; /* offset from new sp to store fp registers */
2118 int initialized; /* != 0 if frame size already calculated */
2119 int num_gp; /* number of gp registers saved */
2120 int num_fp; /* number of fp registers saved */
2121 long insns_len; /* length of insns; mips16 only */
2124 extern struct mips_frame_info current_frame_info;
2126 /* If defined, this macro specifies a table of register pairs used to
2127 eliminate unneeded registers that point into the stack frame. If
2128 it is not defined, the only elimination attempted by the compiler
2129 is to replace references to the frame pointer with references to
2132 The definition of this macro is a list of structure
2133 initializations, each of which specifies an original and
2134 replacement register.
2136 On some machines, the position of the argument pointer is not
2137 known until the compilation is completed. In such a case, a
2138 separate hard register must be used for the argument pointer.
2139 This register can be eliminated by replacing it with either the
2140 frame pointer or the argument pointer, depending on whether or not
2141 the frame pointer has been eliminated.
2143 In this case, you might specify:
2144 #define ELIMINABLE_REGS \
2145 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2146 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2147 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2149 Note that the elimination of the argument pointer with the stack
2150 pointer is specified first since that is the preferred elimination.
2152 The eliminations to $17 are only used on the mips16. See the
2153 definition of HARD_FRAME_POINTER_REGNUM. */
2155 #define ELIMINABLE_REGS \
2156 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2157 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2158 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2159 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2160 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2161 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2162 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2163 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2164 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2165 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2167 /* A C expression that returns non-zero if the compiler is allowed to
2168 try to replace register number FROM-REG with register number
2169 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2170 defined, and will usually be the constant 1, since most of the
2171 cases preventing register elimination are things that the compiler
2172 already knows about.
2174 When not in mips16 and mips64, we can always eliminate to the
2175 frame pointer. We can eliminate to the stack pointer unless
2176 a frame pointer is needed. In mips16 mode, we need a frame
2177 pointer for a large frame; otherwise, reload may be unable
2178 to compute the address of a local variable, since there is
2179 no way to add a large constant to the stack pointer
2180 without using a temporary register.
2182 In mips16, for some instructions (eg lwu), we can't eliminate the
2183 frame pointer for the stack pointer. These instructions are
2184 only generated in TARGET_64BIT mode.
2187 #define CAN_ELIMINATE(FROM, TO) \
2188 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2189 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2190 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2191 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2192 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2193 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2194 && (! TARGET_MIPS16 \
2195 || compute_frame_size (get_frame_size ()) < 32768)))))
2197 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2198 specifies the initial difference between the specified pair of
2199 registers. This macro must be defined if `ELIMINABLE_REGS' is
2202 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2203 { compute_frame_size (get_frame_size ()); \
2204 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2205 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2206 (OFFSET) = - current_function_outgoing_args_size; \
2207 else if ((FROM) == FRAME_POINTER_REGNUM) \
2209 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2210 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2211 (OFFSET) = (current_frame_info.total_size \
2212 - current_function_outgoing_args_size \
2213 - ((mips_abi != ABI_32 \
2214 && mips_abi != ABI_O64 \
2215 && mips_abi != ABI_EABI) \
2216 ? current_function_pretend_args_size \
2218 else if ((FROM) == ARG_POINTER_REGNUM) \
2219 (OFFSET) = (current_frame_info.total_size \
2220 - ((mips_abi != ABI_32 \
2221 && mips_abi != ABI_O64 \
2222 && mips_abi != ABI_EABI) \
2223 ? current_function_pretend_args_size \
2225 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2226 so we must add 4 bytes to the offset to get the right value. */ \
2227 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2229 if (leaf_function_p ()) \
2231 else (OFFSET) = current_frame_info.gp_sp_offset \
2232 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2233 * (BYTES_BIG_ENDIAN != 0)); \
2237 /* If we generate an insn to push BYTES bytes,
2238 this says how many the stack pointer really advances by.
2239 On the vax, sp@- in a byte insn really pushes a word. */
2241 /* #define PUSH_ROUNDING(BYTES) 0 */
2243 /* If defined, the maximum amount of space required for outgoing
2244 arguments will be computed and placed into the variable
2245 `current_function_outgoing_args_size'. No space will be pushed
2246 onto the stack for each call; instead, the function prologue
2247 should increase the stack frame size by this amount.
2249 It is not proper to define both `PUSH_ROUNDING' and
2250 `ACCUMULATE_OUTGOING_ARGS'. */
2251 #define ACCUMULATE_OUTGOING_ARGS
2253 /* Offset from the argument pointer register to the first argument's
2254 address. On some machines it may depend on the data type of the
2257 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2258 the first argument's address.
2260 On the MIPS, we must skip the first argument position if we are
2261 returning a structure or a union, to account for its address being
2262 passed in $4. However, at the current time, this produces a compiler
2263 that can't bootstrap, so comment it out for now. */
2266 #define FIRST_PARM_OFFSET(FNDECL) \
2268 && TREE_TYPE (FNDECL) != 0 \
2269 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2270 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2271 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2275 #define FIRST_PARM_OFFSET(FNDECL) 0
2278 /* When a parameter is passed in a register, stack space is still
2279 allocated for it. For the MIPS, stack space must be allocated, cf
2280 Asm Lang Prog Guide page 7-8.
2282 BEWARE that some space is also allocated for non existing arguments
2283 in register. In case an argument list is of form GF used registers
2284 are a0 (a2,a3), but we should push over a1... */
2286 #define REG_PARM_STACK_SPACE(FNDECL) \
2287 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2289 /* Define this if it is the responsibility of the caller to
2290 allocate the area reserved for arguments passed in registers.
2291 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2292 of this macro is to determine whether the space is included in
2293 `current_function_outgoing_args_size'. */
2294 #define OUTGOING_REG_PARM_STACK_SPACE
2296 /* Align stack frames on 64 bits (Double Word ). */
2297 #ifndef STACK_BOUNDARY
2298 #define STACK_BOUNDARY 64
2301 /* Make sure 4 words are always allocated on the stack. */
2303 #ifndef STACK_ARGS_ADJUST
2304 #define STACK_ARGS_ADJUST(SIZE) \
2306 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2307 SIZE.constant = 4 * UNITS_PER_WORD; \
2312 /* A C expression that should indicate the number of bytes of its
2313 own arguments that a function pops on returning, or 0
2314 if the function pops no arguments and the caller must therefore
2315 pop them all after the function returns.
2317 FUNDECL is the declaration node of the function (as a tree).
2319 FUNTYPE is a C variable whose value is a tree node that
2320 describes the function in question. Normally it is a node of
2321 type `FUNCTION_TYPE' that describes the data type of the function.
2322 From this it is possible to obtain the data types of the value
2323 and arguments (if known).
2325 When a call to a library function is being considered, FUNTYPE
2326 will contain an identifier node for the library function. Thus,
2327 if you need to distinguish among various library functions, you
2328 can do so by their names. Note that "library function" in this
2329 context means a function used to perform arithmetic, whose name
2330 is known specially in the compiler and was not mentioned in the
2331 C code being compiled.
2333 STACK-SIZE is the number of bytes of arguments passed on the
2334 stack. If a variable number of bytes is passed, it is zero, and
2335 argument popping will always be the responsibility of the
2336 calling function. */
2338 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2341 /* Symbolic macros for the registers used to return integer and floating
2344 #define GP_RETURN (GP_REG_FIRST + 2)
2345 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2347 /* Symbolic macros for the first/last argument registers. */
2349 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2350 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2351 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2352 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2354 #define MAX_ARGS_IN_REGISTERS 4
2356 /* Define how to find the value returned by a library function
2357 assuming the value has mode MODE. Because we define
2358 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2359 PROMOTE_MODE does. */
2361 #define LIBCALL_VALUE(MODE) \
2363 ((GET_MODE_CLASS (MODE) != MODE_INT \
2364 || GET_MODE_SIZE (MODE) >= 4) \
2367 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2368 && (! TARGET_SINGLE_FLOAT \
2369 || GET_MODE_SIZE (MODE) <= 4)) \
2373 /* Define how to find the value returned by a function.
2374 VALTYPE is the data type of the value (as a tree).
2375 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2376 otherwise, FUNC is 0. */
2378 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2381 /* 1 if N is a possible register number for a function value.
2382 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2383 Currently, R2 and F0 are only implemented here (C has no complex type) */
2385 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2387 /* 1 if N is a possible register number for function argument passing.
2388 We have no FP argument registers when soft-float. When FP registers
2389 are 32 bits, we can't directly reference the odd numbered ones. */
2391 #define FUNCTION_ARG_REGNO_P(N) \
2392 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2393 || ((! TARGET_SOFT_FLOAT \
2394 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2395 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2396 && ! fixed_regs[N]))
2398 /* A C expression which can inhibit the returning of certain function
2399 values in registers, based on the type of value. A nonzero value says
2400 to return the function value in memory, just as large structures are
2401 always returned. Here TYPE will be a C expression of type
2402 `tree', representing the data type of the value.
2404 Note that values of mode `BLKmode' must be explicitly
2405 handled by this macro. Also, the option `-fpcc-struct-return'
2406 takes effect regardless of this macro. On most systems, it is
2407 possible to leave the macro undefined; this causes a default
2408 definition to be used, whose value is the constant 1 for BLKmode
2409 values, and 0 otherwise.
2411 GCC normally converts 1 byte structures into chars, 2 byte
2412 structs into shorts, and 4 byte structs into ints, and returns
2413 them this way. Defining the following macro overrides this,
2414 to give us MIPS cc compatibility. */
2416 #define RETURN_IN_MEMORY(TYPE) \
2417 (TYPE_MODE (TYPE) == BLKmode)
2419 /* A code distinguishing the floating point format of the target
2420 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2421 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2423 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2426 /* Define a data type for recording info about an argument list
2427 during the scan of that argument list. This data type should
2428 hold all necessary information about the function itself
2429 and about the args processed so far, enough to enable macros
2430 such as FUNCTION_ARG to determine where the next arg should go.
2432 On the mips16, we need to keep track of which floating point
2433 arguments were passed in general registers, but would have been
2434 passed in the FP regs if this were a 32 bit function, so that we
2435 can move them to the FP regs if we wind up calling a 32 bit
2436 function. We record this information in fp_code, encoded in base
2437 four. A zero digit means no floating point argument, a one digit
2438 means an SFmode argument, and a two digit means a DFmode argument,
2439 and a three digit is not used. The low order digit is the first
2440 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2441 an SFmode argument. ??? A more sophisticated approach will be
2442 needed if MIPS_ABI != ABI_32. */
2444 typedef struct mips_args {
2445 int gp_reg_found; /* whether a gp register was found yet */
2446 int arg_number; /* argument number */
2447 int arg_words; /* # total words the arguments take */
2448 int fp_arg_words; /* # words for FP args (MIPS_EABI only) */
2449 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
2450 int fp_code; /* Mode of FP arguments (mips16) */
2451 int num_adjusts; /* number of adjustments made */
2452 /* Adjustments made to args pass in regs. */
2453 /* ??? The size is doubled to work around a
2454 bug in the code that sets the adjustments
2456 struct rtx_def *adjust[MAX_ARGS_IN_REGISTERS*2];
2459 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2460 for a call to a function whose data type is FNTYPE.
2461 For a library call, FNTYPE is 0.
2465 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2466 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2468 /* Update the data in CUM to advance over an argument
2469 of mode MODE and data type TYPE.
2470 (TYPE is null for libcalls where that information may not be available.) */
2472 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2473 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2475 /* Determine where to put an argument to a function.
2476 Value is zero to push the argument on the stack,
2477 or a hard register in which to store the argument.
2479 MODE is the argument's machine mode.
2480 TYPE is the data type of the argument (as a tree).
2481 This is null for libcalls where that information may
2483 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2484 the preceding args and about the function being called.
2485 NAMED is nonzero if this argument is a named parameter
2486 (otherwise it is an extra parameter matching an ellipsis). */
2488 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2489 function_arg( &CUM, MODE, TYPE, NAMED)
2491 /* For an arg passed partly in registers and partly in memory,
2492 this is the number of registers used.
2493 For args passed entirely in registers or entirely in memory, zero. */
2495 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2496 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2498 /* If defined, a C expression that gives the alignment boundary, in
2499 bits, of an argument with the specified mode and type. If it is
2500 not defined, `PARM_BOUNDARY' is used for all arguments. */
2502 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2504 ? ((TYPE_ALIGN(TYPE) <= (unsigned)PARM_BOUNDARY) \
2506 : TYPE_ALIGN(TYPE)) \
2507 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2509 : GET_MODE_ALIGNMENT(MODE)))
2512 /* This macro generates the assembly code for function entry.
2513 FILE is a stdio stream to output the code to.
2514 SIZE is an int: how many units of temporary storage to allocate.
2515 Refer to the array `regs_ever_live' to determine which registers
2516 to save; `regs_ever_live[I]' is nonzero if register number I
2517 is ever used in the function. This macro is responsible for
2518 knowing which registers should not be saved even if used. */
2520 #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
2522 /* This macro generates the assembly code for function exit,
2523 on machines that need it. If FUNCTION_EPILOGUE is not defined
2524 then individual return instructions are generated for each
2525 return statement. Args are same as for FUNCTION_PROLOGUE. */
2527 #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
2529 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2531 #define MUST_SAVE_REGISTER(regno) \
2532 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2533 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2534 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2536 /* ALIGN FRAMES on double word boundaries */
2537 #ifndef MIPS_STACK_ALIGN
2538 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2542 /* Output assembler code to FILE to increment profiler label # LABELNO
2543 for profiling a function entry. */
2545 #define FUNCTION_PROFILER(FILE, LABELNO) \
2547 if (TARGET_MIPS16) \
2548 sorry ("mips16 function profiling"); \
2549 fprintf (FILE, "\t.set\tnoreorder\n"); \
2550 fprintf (FILE, "\t.set\tnoat\n"); \
2551 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2552 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2553 fprintf (FILE, "\tjal\t_mcount\n"); \
2555 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2556 TARGET_64BIT ? "dsubu" : "subu", \
2557 reg_names[STACK_POINTER_REGNUM], \
2558 reg_names[STACK_POINTER_REGNUM], \
2559 Pmode == DImode ? 16 : 8); \
2560 fprintf (FILE, "\t.set\treorder\n"); \
2561 fprintf (FILE, "\t.set\tat\n"); \
2564 /* Define this macro if the code for function profiling should come
2565 before the function prologue. Normally, the profiling code comes
2568 /* #define PROFILE_BEFORE_PROLOGUE */
2570 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2571 the stack pointer does not matter. The value is tested only in
2572 functions that have frame pointers.
2573 No definition is equivalent to always zero. */
2575 #define EXIT_IGNORE_STACK 1
2578 /* A C statement to output, on the stream FILE, assembler code for a
2579 block of data that contains the constant parts of a trampoline.
2580 This code should not include a label--the label is taken care of
2583 #define TRAMPOLINE_TEMPLATE(STREAM) \
2585 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2586 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2587 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2588 if (Pmode == DImode) \
2590 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2591 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2595 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2596 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2598 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2599 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2600 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2601 if (Pmode == DImode) \
2603 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2604 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2608 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2609 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2613 /* A C expression for the size in bytes of the trampoline, as an
2616 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2618 /* Alignment required for trampolines, in bits. */
2620 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2622 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2623 program and data caches. */
2625 #ifndef CACHE_FLUSH_FUNC
2626 #define CACHE_FLUSH_FUNC "_flush_cache"
2629 /* A C statement to initialize the variable parts of a trampoline.
2630 ADDR is an RTX for the address of the trampoline; FNADDR is an
2631 RTX for the address of the nested function; STATIC_CHAIN is an
2632 RTX for the static chain value that should be passed to the
2633 function when it is called. */
2635 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2638 if (Pmode == DImode) \
2640 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 32)), FUNC); \
2641 emit_move_insn (gen_rtx (MEM, DImode, plus_constant (addr, 40)), CHAIN);\
2645 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), FUNC); \
2646 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 36)), CHAIN);\
2649 /* Flush both caches. We need to flush the data cache in case \
2650 the system has a write-back cache. */ \
2651 /* ??? Should check the return value for errors. */ \
2652 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, CACHE_FLUSH_FUNC), \
2653 0, VOIDmode, 3, addr, Pmode, \
2654 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2655 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2658 /* Addressing modes, and classification of registers for them. */
2660 /* #define HAVE_POST_INCREMENT 0 */
2661 /* #define HAVE_POST_DECREMENT 0 */
2663 /* #define HAVE_PRE_DECREMENT 0 */
2664 /* #define HAVE_PRE_INCREMENT 0 */
2666 /* These assume that REGNO is a hard or pseudo reg number.
2667 They give nonzero only if REGNO is a hard reg of the suitable class
2668 or a pseudo reg currently allocated to a suitable hard reg.
2669 These definitions are NOT overridden anywhere. */
2671 #define BASE_REG_P(regno, mode) \
2673 ? (M16_REG_P (regno) \
2674 || (regno) == FRAME_POINTER_REGNUM \
2675 || (regno) == ARG_POINTER_REGNUM \
2676 || ((regno) == STACK_POINTER_REGNUM \
2677 && (GET_MODE_SIZE (mode) == 4 \
2678 || GET_MODE_SIZE (mode) == 8))) \
2681 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2682 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno], \
2685 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2686 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2688 #define REGNO_OK_FOR_INDEX_P(regno) 0
2689 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2690 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2692 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2693 and check its validity for a certain class.
2694 We have two alternate definitions for each of them.
2695 The usual definition accepts all pseudo regs; the other rejects them all.
2696 The symbol REG_OK_STRICT causes the latter definition to be used.
2698 Most source files want to accept pseudo regs in the hope that
2699 they will get allocated to the class that the insn wants them to be in.
2700 Some source files that are used after register allocation
2701 need to be strict. */
2703 #ifndef REG_OK_STRICT
2705 #define REG_OK_STRICT_P 0
2706 #define REG_OK_FOR_INDEX_P(X) 0
2707 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2708 GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X), (MODE))
2712 #define REG_OK_STRICT_P 1
2713 #define REG_OK_FOR_INDEX_P(X) 0
2714 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2715 REGNO_MODE_OK_FOR_BASE_P (REGNO (X), (MODE))
2720 /* Maximum number of registers that can appear in a valid memory address. */
2722 #define MAX_REGS_PER_ADDRESS 1
2724 /* A C compound statement with a conditional `goto LABEL;' executed
2725 if X (an RTX) is a legitimate memory address on the target
2726 machine for a memory operand of mode MODE.
2728 It usually pays to define several simpler macros to serve as
2729 subroutines for this one. Otherwise it may be too complicated
2732 This macro must exist in two variants: a strict variant and a
2733 non-strict one. The strict variant is used in the reload pass.
2734 It must be defined so that any pseudo-register that has not been
2735 allocated a hard register is considered a memory reference. In
2736 contexts where some kind of register is required, a
2737 pseudo-register with no hard register must be rejected.
2739 The non-strict variant is used in other passes. It must be
2740 defined to accept all pseudo-registers in every context where
2741 some kind of register is required.
2743 Compiler source files that want to use the strict variant of
2744 this macro define the macro `REG_OK_STRICT'. You should use an
2745 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2746 in that case and the non-strict variant otherwise.
2748 Typically among the subroutines used to define
2749 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2750 acceptable registers for various purposes (one for base
2751 registers, one for index registers, and so on). Then only these
2752 subroutine macros need have two variants; the higher levels of
2753 macros may be the same whether strict or not.
2755 Normally, constant addresses which are the sum of a `symbol_ref'
2756 and an integer are stored inside a `const' RTX to mark them as
2757 constant. Therefore, there is no need to recognize such sums
2758 specifically as legitimate addresses. Normally you would simply
2759 recognize any `const' as legitimate.
2761 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2762 constant sums that are not marked with `const'. It assumes
2763 that a naked `plus' indicates indexing. If so, then you *must*
2764 reject such naked constant sums as illegitimate addresses, so
2765 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2767 On some machines, whether a symbolic address is legitimate
2768 depends on the section that the address refers to. On these
2769 machines, define the macro `ENCODE_SECTION_INFO' to store the
2770 information into the `symbol_ref', and then check for it here.
2771 When you see a `const', you will have to look inside it to find
2772 the `symbol_ref' in order to determine the section. */
2775 #define GO_PRINTF(x) trace(x)
2776 #define GO_PRINTF2(x,y) trace(x,y)
2777 #define GO_DEBUG_RTX(x) debug_rtx(x)
2780 #define GO_PRINTF(x)
2781 #define GO_PRINTF2(x,y)
2782 #define GO_DEBUG_RTX(x)
2785 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2787 register rtx xinsn = (X); \
2789 if (TARGET_DEBUG_B_MODE) \
2791 GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
2792 (REG_OK_STRICT_P) ? "" : "not "); \
2793 GO_DEBUG_RTX (xinsn); \
2796 /* The mips16 can only use the stack pointer as a base register when \
2797 loading SImode or DImode values. */ \
2798 if (GET_CODE (xinsn) == REG && REG_MODE_OK_FOR_BASE_P (xinsn, MODE)) \
2801 if (CONSTANT_ADDRESS_P (xinsn) \
2802 && ! (mips_split_addresses && mips_check_split (xinsn, MODE)) \
2803 && (! TARGET_MIPS16 || mips16_constant (xinsn, MODE, 1, 0))) \
2806 if (GET_CODE (xinsn) == LO_SUM && mips_split_addresses) \
2808 register rtx xlow0 = XEXP (xinsn, 0); \
2809 register rtx xlow1 = XEXP (xinsn, 1); \
2811 if (GET_CODE (xlow0) == REG \
2812 && REG_MODE_OK_FOR_BASE_P (xlow0, MODE) \
2813 && mips_check_split (xlow1, MODE)) \
2817 if (GET_CODE (xinsn) == PLUS) \
2819 register rtx xplus0 = XEXP (xinsn, 0); \
2820 register rtx xplus1 = XEXP (xinsn, 1); \
2821 register enum rtx_code code0 = GET_CODE (xplus0); \
2822 register enum rtx_code code1 = GET_CODE (xplus1); \
2824 /* The mips16 can only use the stack pointer as a base register \
2825 when loading SImode or DImode values. */ \
2826 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE)) \
2828 if (code1 == CONST_INT \
2829 && INTVAL (xplus1) >= -32768 \
2830 && INTVAL (xplus1) + GET_MODE_SIZE (MODE) - 1 <= 32767) \
2833 /* On the mips16, we represent GP relative offsets in RTL. \
2834 These are 16 bit signed values, and can serve as register \
2837 && mips16_gp_offset_p (xplus1)) \
2840 /* For some code sequences, you actually get better code by \
2841 pretending that the MIPS supports an address mode of a \
2842 constant address + a register, even though the real \
2843 machine doesn't support it. This is because the \
2844 assembler can use $r1 to load just the high 16 bits, add \
2845 in the register, and fold the low 16 bits into the memory \
2846 reference, whereas the compiler generates a 4 instruction \
2847 sequence. On the other hand, CSE is not as effective. \
2848 It would be a win to generate the lui directly, but the \
2849 MIPS assembler does not have syntax to generate the \
2850 appropriate relocation. */ \
2852 /* Also accept CONST_INT addresses here, so no else. */ \
2853 /* Reject combining an embedded PIC text segment reference \
2854 with a register. That requires an additional \
2856 /* ??? Reject combining an address with a register for the MIPS \
2857 64 bit ABI, because the SGI assembler can not handle this. */ \
2858 if (!TARGET_DEBUG_A_MODE \
2859 && (mips_abi == ABI_32 \
2860 || mips_abi == ABI_O64 \
2861 || mips_abi == ABI_EABI) \
2862 && CONSTANT_ADDRESS_P (xplus1) \
2863 && ! mips_split_addresses \
2864 && (!TARGET_EMBEDDED_PIC \
2866 || GET_CODE (XEXP (xplus1, 0)) != MINUS) \
2867 && !TARGET_MIPS16) \
2872 if (TARGET_DEBUG_B_MODE) \
2873 GO_PRINTF ("Not a legitimate address\n"); \
2877 /* A C expression that is 1 if the RTX X is a constant which is a
2878 valid address. This is defined to be the same as `CONSTANT_P (X)',
2879 but rejecting CONST_DOUBLE. */
2880 /* When pic, we must reject addresses of the form symbol+large int.
2881 This is because an instruction `sw $4,s+70000' needs to be converted
2882 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2883 assembler would use $at as a temp to load in the large offset. In this
2884 case $at is already in use. We convert such problem addresses to
2885 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2886 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2887 #define CONSTANT_ADDRESS_P(X) \
2888 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2889 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2890 || (GET_CODE (X) == CONST \
2891 && ! (flag_pic && pic_address_needs_scratch (X)) \
2892 && (mips_abi == ABI_32 \
2893 || mips_abi == ABI_O64 \
2894 || mips_abi == ABI_EABI))) \
2895 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2897 /* Define this, so that when PIC, reload won't try to reload invalid
2898 addresses which require two reload registers. */
2900 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2902 /* Nonzero if the constant value X is a legitimate general operand.
2903 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2905 At present, GAS doesn't understand li.[sd], so don't allow it
2906 to be generated at present. Also, the MIPS assembler does not
2907 grok li.d Infinity. */
2909 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2910 #define LEGITIMATE_CONSTANT_P(X) \
2911 ((GET_CODE (X) != CONST_DOUBLE \
2912 || mips_const_double_ok (X, GET_MODE (X))) \
2913 && ! (GET_CODE (X) == CONST \
2914 && mips_abi != ABI_32 \
2915 && mips_abi != ABI_O64 \
2916 && mips_abi != ABI_EABI) \
2917 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2919 /* A C compound statement that attempts to replace X with a valid
2920 memory address for an operand of mode MODE. WIN will be a C
2921 statement label elsewhere in the code; the macro definition may
2924 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2926 to avoid further processing if the address has become legitimate.
2928 X will always be the result of a call to `break_out_memory_refs',
2929 and OLDX will be the operand that was given to that function to
2932 The code generated by this macro should not alter the
2933 substructure of X. If it transforms X into a more legitimate
2934 form, it should assign X (which will always be a C variable) a
2937 It is not necessary for this macro to come up with a legitimate
2938 address. The compiler has standard ways of doing so in all
2939 cases. In fact, it is safe for this macro to do nothing. But
2940 often a machine-dependent strategy can generate better code.
2942 For the MIPS, transform:
2944 memory(X + <large int>)
2948 Y = <large int> & ~0x7fff;
2950 memory (Z + (<large int> & 0x7fff));
2952 This is for CSE to find several similar references, and only use one Z.
2954 When PIC, convert addresses of the form memory (symbol+large int) to
2955 memory (reg+large int). */
2958 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2960 register rtx xinsn = (X); \
2962 if (TARGET_DEBUG_B_MODE) \
2964 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
2965 GO_DEBUG_RTX (xinsn); \
2968 if (mips_split_addresses && mips_check_split (X, MODE)) \
2970 /* ??? Is this ever executed? */ \
2971 X = gen_rtx (LO_SUM, Pmode, \
2972 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
2976 if (GET_CODE (xinsn) == CONST \
2977 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2978 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
2979 || (mips_abi != ABI_32 \
2980 && mips_abi != ABI_O64 \
2981 && mips_abi != ABI_EABI))) \
2983 rtx ptr_reg = gen_reg_rtx (Pmode); \
2984 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2986 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2988 X = gen_rtx (PLUS, Pmode, ptr_reg, constant); \
2989 if (SMALL_INT (constant)) \
2991 /* Otherwise we fall through so the code below will fix the \
2996 if (GET_CODE (xinsn) == PLUS) \
2998 register rtx xplus0 = XEXP (xinsn, 0); \
2999 register rtx xplus1 = XEXP (xinsn, 1); \
3000 register enum rtx_code code0 = GET_CODE (xplus0); \
3001 register enum rtx_code code1 = GET_CODE (xplus1); \
3003 if (code0 != REG && code1 == REG) \
3005 xplus0 = XEXP (xinsn, 1); \
3006 xplus1 = XEXP (xinsn, 0); \
3007 code0 = GET_CODE (xplus0); \
3008 code1 = GET_CODE (xplus1); \
3011 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3012 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3014 rtx int_reg = gen_reg_rtx (Pmode); \
3015 rtx ptr_reg = gen_reg_rtx (Pmode); \
3017 emit_move_insn (int_reg, \
3018 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3020 emit_insn (gen_rtx (SET, VOIDmode, \
3022 gen_rtx (PLUS, Pmode, xplus0, int_reg))); \
3024 X = gen_rtx (PLUS, Pmode, ptr_reg, \
3025 GEN_INT (INTVAL (xplus1) & 0x7fff)); \
3030 if (TARGET_DEBUG_B_MODE) \
3031 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3035 /* A C statement or compound statement with a conditional `goto
3036 LABEL;' executed if memory address X (an RTX) can have different
3037 meanings depending on the machine mode of the memory reference it
3040 Autoincrement and autodecrement addresses typically have
3041 mode-dependent effects because the amount of the increment or
3042 decrement is the size of the operand being addressed. Some
3043 machines have other mode-dependent addresses. Many RISC machines
3044 have no mode-dependent addresses.
3046 You may assume that ADDR is a valid address for the machine. */
3048 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3051 /* Define this macro if references to a symbol must be treated
3052 differently depending on something about the variable or
3053 function named by the symbol (such as what section it is in).
3055 The macro definition, if any, is executed immediately after the
3056 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3057 The value of the rtl will be a `mem' whose address is a
3060 The usual thing for this macro to do is to a flag in the
3061 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3062 name string in the `symbol_ref' (if one bit is not enough
3065 The best way to modify the name string is by adding text to the
3066 beginning, with suitable punctuation to prevent any ambiguity.
3067 Allocate the new name in `saveable_obstack'. You will have to
3068 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3069 and output the name accordingly.
3071 You can also check the information stored in the `symbol_ref' in
3072 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3073 `PRINT_OPERAND_ADDRESS'.
3075 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3078 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3079 symbols which are not in the .text section.
3081 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3082 constants which are put in the .text section. We also record the
3083 total length of all such strings; this total is used to decide
3084 whether we need to split the constant table, and need not be
3087 When not mips16 code nor embedded PIC, if a symbol is in a
3088 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3089 splitting the reference so that gas can generate a gp relative
3092 When TARGET_EMBEDDED_DATA is set, we assume that all const
3093 variables will be stored in ROM, which is too far from %gp to use
3094 %gprel addressing. Note that (1) we include "extern const"
3095 variables in this, which mips_select_section doesn't, and (2) we
3096 can't always tell if they're really const (they might be const C++
3097 objects with non-const constructors), so we err on the side of
3098 caution and won't use %gprel anyway (otherwise we'd have to defer
3099 this decision to the linker/loader). The handling of extern consts
3100 is why the DECL_INITIAL macros differ from mips_select_section.
3102 If you are changing this macro, you should look at
3103 mips_select_section and see if it needs a similar change. */
3105 #define ENCODE_SECTION_INFO(DECL) \
3108 if (TARGET_MIPS16) \
3110 if (TREE_CODE (DECL) == STRING_CST \
3111 && ! flag_writable_strings) \
3113 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3114 mips_string_length += TREE_STRING_LENGTH (DECL); \
3118 if (TARGET_EMBEDDED_DATA \
3119 && (TREE_CODE (DECL) == VAR_DECL \
3120 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3121 && (!DECL_INITIAL (DECL) \
3122 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3124 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3127 else if (TARGET_EMBEDDED_PIC) \
3129 if (TREE_CODE (DECL) == VAR_DECL) \
3130 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3131 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3132 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3133 else if (TREE_CODE (DECL) == STRING_CST \
3134 && ! flag_writable_strings) \
3135 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3137 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3140 else if (TREE_CODE (DECL) == VAR_DECL \
3141 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3142 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3144 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3147 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3150 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL) \
3152 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3154 if (size > 0 && size <= mips_section_threshold) \
3155 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3158 else if (HALF_PIC_P ()) \
3160 HALF_PIC_ENCODE (DECL); \
3165 /* The mips16 wants the constant pool to be after the function,
3166 because the PC relative load instructions use unsigned offsets. */
3168 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3170 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3171 mips_string_length = 0;
3174 /* In mips16 mode, put most string constants after the function. */
3175 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3176 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3179 /* Specify the machine mode that this machine uses
3180 for the index in the tablejump instruction.
3181 ??? Using HImode in mips16 mode can cause overflow. However, the
3182 overflow is no more likely than the overflow in a branch
3183 instruction. Large functions can currently break in both ways. */
3184 #define CASE_VECTOR_MODE \
3185 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3187 /* Define as C expression which evaluates to nonzero if the tablejump
3188 instruction expects the table to contain offsets from the address of the
3190 Do not define this if the table should contain absolute addresses. */
3191 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3193 /* Specify the tree operation to be used to convert reals to integers. */
3194 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3196 /* This is the kind of divide that is easiest to do in the general case. */
3197 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3199 /* Define this as 1 if `char' should by default be signed; else as 0. */
3200 #ifndef DEFAULT_SIGNED_CHAR
3201 #define DEFAULT_SIGNED_CHAR 1
3204 /* Max number of bytes we can move from memory to memory
3205 in one reasonably fast instruction. */
3206 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3207 #define MAX_MOVE_MAX 8
3209 /* Define this macro as a C expression which is nonzero if
3210 accessing less than a word of memory (i.e. a `char' or a
3211 `short') is no faster than accessing a word of memory, i.e., if
3212 such access require more than one instruction or if there is no
3213 difference in cost between byte and (aligned) word loads.
3215 On RISC machines, it tends to generate better code to define
3216 this as 1, since it avoids making a QI or HI mode register. */
3217 #define SLOW_BYTE_ACCESS 1
3219 /* We assume that the store-condition-codes instructions store 0 for false
3220 and some other value for true. This is the value stored for true. */
3222 #define STORE_FLAG_VALUE 1
3224 /* Define this if zero-extension is slow (more than one real instruction). */
3225 #define SLOW_ZERO_EXTEND
3227 /* Define this to be nonzero if shift instructions ignore all but the low-order
3229 #define SHIFT_COUNT_TRUNCATED 1
3231 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3232 is done just by pretending it is already truncated. */
3233 /* In 64 bit mode, 32 bit instructions require that register values be properly
3234 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3235 converts a value >32 bits to a value <32 bits. */
3236 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3237 Something needs to be done about this. Perhaps not use any 32 bit
3238 instructions? Perhaps use PROMOTE_MODE? */
3239 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3240 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3242 /* Specify the machine mode that pointers have.
3243 After generation of rtl, the compiler makes no further distinction
3244 between pointers and any other objects of this machine mode. */
3247 #define Pmode ((enum machine_mode)(TARGET_LONG64 ? DImode : SImode))
3250 /* A function address in a call instruction
3251 is a word address (for indexing purposes)
3252 so give the MEM rtx a words's mode. */
3254 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3256 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3257 memset, instead of the BSD functions bcopy and bzero. */
3259 #if defined(MIPS_SYSV) || defined(OSF_OS)
3260 #define TARGET_MEM_FUNCTIONS
3264 /* A part of a C `switch' statement that describes the relative
3265 costs of constant RTL expressions. It must contain `case'
3266 labels for expression codes `const_int', `const', `symbol_ref',
3267 `label_ref' and `const_double'. Each case must ultimately reach
3268 a `return' statement to return the relative cost of the use of
3269 that kind of constant value in an expression. The cost may
3270 depend on the precise value of the constant, which is available
3271 for examination in X.
3273 CODE is the expression code--redundant, since it can be obtained
3274 with `GET_CODE (X)'. */
3276 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3278 if (! TARGET_MIPS16) \
3280 /* Always return 0, since we don't have different sized \
3281 instructions, hence different costs according to Richard \
3285 if ((OUTER_CODE) == SET) \
3287 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3289 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3290 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3291 return COSTS_N_INSNS (1); \
3293 return COSTS_N_INSNS (2); \
3295 /* A PLUS could be an address. We don't want to force an address \
3296 to use a register, so accept any signed 16 bit value without \
3298 if ((OUTER_CODE) == PLUS \
3299 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3301 /* A number between 1 and 8 inclusive is efficient for a shift. \
3302 Otherwise, we will need an extended instruction. */ \
3303 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3304 || (OUTER_CODE) == LSHIFTRT) \
3306 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3308 return COSTS_N_INSNS (1); \
3310 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3311 if ((OUTER_CODE) == XOR \
3312 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3314 /* We may be able to use slt or sltu for a comparison with a \
3315 signed 16 bit value. (The boundary conditions aren't quite \
3316 right, but this is just a heuristic anyhow.) */ \
3317 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3318 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3319 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3320 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3321 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3323 /* Equality comparisons with 0 are cheap. */ \
3324 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3325 && INTVAL (X) == 0) \
3328 /* Otherwise, work out the cost to load the value into a \
3330 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3331 return COSTS_N_INSNS (1); \
3332 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3333 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3334 return COSTS_N_INSNS (2); \
3336 return COSTS_N_INSNS (3); \
3339 return COSTS_N_INSNS (2); \
3343 rtx offset = const0_rtx; \
3344 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3346 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3348 /* Treat this like a signed 16 bit CONST_INT. */ \
3349 if ((OUTER_CODE) == PLUS) \
3351 else if ((OUTER_CODE) == SET) \
3352 return COSTS_N_INSNS (1); \
3354 return COSTS_N_INSNS (2); \
3357 if (GET_CODE (symref) == LABEL_REF) \
3358 return COSTS_N_INSNS (2); \
3360 if (GET_CODE (symref) != SYMBOL_REF) \
3361 return COSTS_N_INSNS (4); \
3363 /* let's be paranoid.... */ \
3364 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3365 return COSTS_N_INSNS (2); \
3367 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3371 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3373 case CONST_DOUBLE: \
3376 if (TARGET_MIPS16) \
3377 return COSTS_N_INSNS (4); \
3378 split_double (X, &high, &low); \
3379 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3380 || low == CONST0_RTX (GET_MODE (low))) \
3384 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3385 This can be used, for example, to indicate how costly a multiply
3386 instruction is. In writing this macro, you can use the construct
3387 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3389 This macro is optional; do not define it if the default cost
3390 assumptions are adequate for the target machine.
3392 If -mdebugd is used, change the multiply cost to 2, so multiply by
3393 a constant isn't converted to a series of shifts. This helps
3394 strength reduction, and also makes it easier to identify what the
3395 compiler is doing. */
3397 /* ??? Fix this to be right for the R8000. */
3398 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3401 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3402 if (simple_memory_operand (X, GET_MODE (X))) \
3403 return COSTS_N_INSNS (num_words); \
3405 return COSTS_N_INSNS (2*num_words); \
3409 return COSTS_N_INSNS (6); \
3412 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3417 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3418 return COSTS_N_INSNS (2); \
3425 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3426 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3432 enum machine_mode xmode = GET_MODE (X); \
3433 if (xmode == SFmode || xmode == DFmode) \
3434 return COSTS_N_INSNS (1); \
3436 return COSTS_N_INSNS (4); \
3442 enum machine_mode xmode = GET_MODE (X); \
3443 if (xmode == SFmode || xmode == DFmode) \
3445 if (mips_cpu == PROCESSOR_R3000 \
3446 || mips_cpu == PROCESSOR_R3900) \
3447 return COSTS_N_INSNS (2); \
3448 else if (mips_cpu == PROCESSOR_R6000) \
3449 return COSTS_N_INSNS (3); \
3451 return COSTS_N_INSNS (6); \
3454 if (xmode == DImode && !TARGET_64BIT) \
3455 return COSTS_N_INSNS (4); \
3461 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3468 enum machine_mode xmode = GET_MODE (X); \
3469 if (xmode == SFmode) \
3471 if (mips_cpu == PROCESSOR_R3000 \
3472 || mips_cpu == PROCESSOR_R3900 \
3473 || mips_cpu == PROCESSOR_R5000) \
3474 return COSTS_N_INSNS (4); \
3475 else if (mips_cpu == PROCESSOR_R6000) \
3476 return COSTS_N_INSNS (5); \
3478 return COSTS_N_INSNS (7); \
3481 if (xmode == DFmode) \
3483 if (mips_cpu == PROCESSOR_R3000 \
3484 || mips_cpu == PROCESSOR_R3900 \
3485 || mips_cpu == PROCESSOR_R5000) \
3486 return COSTS_N_INSNS (5); \
3487 else if (mips_cpu == PROCESSOR_R6000) \
3488 return COSTS_N_INSNS (6); \
3490 return COSTS_N_INSNS (8); \
3493 if (mips_cpu == PROCESSOR_R3000) \
3494 return COSTS_N_INSNS (12); \
3495 else if (mips_cpu == PROCESSOR_R3900) \
3496 return COSTS_N_INSNS (2); \
3497 else if (mips_cpu == PROCESSOR_R6000) \
3498 return COSTS_N_INSNS (17); \
3499 else if (mips_cpu == PROCESSOR_R5000) \
3500 return COSTS_N_INSNS (5); \
3502 return COSTS_N_INSNS (10); \
3508 enum machine_mode xmode = GET_MODE (X); \
3509 if (xmode == SFmode) \
3511 if (mips_cpu == PROCESSOR_R3000 \
3512 || mips_cpu == PROCESSOR_R3900) \
3513 return COSTS_N_INSNS (12); \
3514 else if (mips_cpu == PROCESSOR_R6000) \
3515 return COSTS_N_INSNS (15); \
3517 return COSTS_N_INSNS (23); \
3520 if (xmode == DFmode) \
3522 if (mips_cpu == PROCESSOR_R3000 \
3523 || mips_cpu == PROCESSOR_R3900) \
3524 return COSTS_N_INSNS (19); \
3525 else if (mips_cpu == PROCESSOR_R6000) \
3526 return COSTS_N_INSNS (16); \
3528 return COSTS_N_INSNS (36); \
3531 /* fall through */ \
3535 if (mips_cpu == PROCESSOR_R3000 \
3536 || mips_cpu == PROCESSOR_R3900) \
3537 return COSTS_N_INSNS (35); \
3538 else if (mips_cpu == PROCESSOR_R6000) \
3539 return COSTS_N_INSNS (38); \
3540 else if (mips_cpu == PROCESSOR_R5000) \
3541 return COSTS_N_INSNS (36); \
3543 return COSTS_N_INSNS (69); \
3546 /* A sign extend from SImode to DImode in 64 bit mode is often \
3547 zero instructions, because the result can often be used \
3548 directly by another instruction; we'll call it one. */ \
3549 if (TARGET_64BIT && GET_MODE (X) == DImode \
3550 && GET_MODE (XEXP (X, 0)) == SImode) \
3551 return COSTS_N_INSNS (1); \
3553 return COSTS_N_INSNS (2); \
3556 if (TARGET_64BIT && GET_MODE (X) == DImode \
3557 && GET_MODE (XEXP (X, 0)) == SImode) \
3558 return COSTS_N_INSNS (2); \
3560 return COSTS_N_INSNS (1);
3562 /* An expression giving the cost of an addressing mode that
3563 contains ADDRESS. If not defined, the cost is computed from the
3564 form of the ADDRESS expression and the `CONST_COSTS' values.
3566 For most CISC machines, the default cost is a good approximation
3567 of the true cost of the addressing mode. However, on RISC
3568 machines, all instructions normally have the same length and
3569 execution time. Hence all addresses will have equal costs.
3571 In cases where more than one form of an address is known, the
3572 form with the lowest cost will be used. If multiple forms have
3573 the same, lowest, cost, the one that is the most complex will be
3576 For example, suppose an address that is equal to the sum of a
3577 register and a constant is used twice in the same basic block.
3578 When this macro is not defined, the address will be computed in
3579 a register and memory references will be indirect through that
3580 register. On machines where the cost of the addressing mode
3581 containing the sum is no higher than that of a simple indirect
3582 reference, this will produce an additional instruction and
3583 possibly require an additional register. Proper specification
3584 of this macro eliminates this overhead for such machines.
3586 Similar use of this macro is made in strength reduction of loops.
3588 ADDRESS need not be valid as an address. In such a case, the
3589 cost is not relevant and can be any value; invalid addresses
3590 need not be assigned a different cost.
3592 On machines where an address involving more than one register is
3593 as cheap as an address computation involving only one register,
3594 defining `ADDRESS_COST' to reflect this can cause two registers
3595 to be live over a region of code where only one would have been
3596 if `ADDRESS_COST' were not defined in that manner. This effect
3597 should be considered in the definition of this macro.
3598 Equivalent costs should probably only be given to addresses with
3599 different numbers of registers on machines with lots of registers.
3601 This macro will normally either not be defined or be defined as
3604 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3606 /* A C expression for the cost of moving data from a register in
3607 class FROM to one in class TO. The classes are expressed using
3608 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3609 the default; other values are interpreted relative to that.
3611 It is not required that the cost always equal 2 when FROM is the
3612 same as TO; on some machines it is expensive to move between
3613 registers if they are not general registers.
3615 If reload sees an insn consisting of a single `set' between two
3616 hard registers, and if `REGISTER_MOVE_COST' applied to their
3617 classes returns a value of 2, reload does not check to ensure
3618 that the constraints of the insn are met. Setting a cost of
3619 other than 2 will allow reload to verify that the constraints are
3620 met. You should do this if the `movM' pattern's constraints do
3621 not allow such copying. */
3623 #define REGISTER_MOVE_COST(FROM, TO) \
3624 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3625 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3626 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3627 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3628 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3629 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3630 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3631 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3632 : (((FROM) == HI_REG || (FROM) == LO_REG \
3633 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3634 && ((TO) == M16_REGS || (TO) == M16_NA_REGS)) ? 6 \
3635 : (((FROM) == HI_REG || (FROM) == LO_REG \
3636 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3637 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 8 : 6) \
3638 : (((TO) == HI_REG || (TO) == LO_REG \
3639 || (TO) == MD_REGS || (TO) == HILO_REG) \
3640 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3641 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3642 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3645 /* ??? Fix this to be right for the R8000. */
3646 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3647 (((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 6 : 4) \
3648 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3650 /* Define if copies to/from condition code registers should be avoided.
3652 This is needed for the MIPS because reload_outcc is not complete;
3653 it needs to handle cases where the source is a general or another
3654 condition code register. */
3655 #define AVOID_CCMODE_COPIES
3657 /* A C expression for the cost of a branch instruction. A value of
3658 1 is the default; other values are interpreted relative to that. */
3660 /* ??? Fix this to be right for the R8000. */
3661 #define BRANCH_COST \
3663 && (mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000)) \
3666 /* A C statement (sans semicolon) to update the integer variable COST
3667 based on the relationship between INSN that is dependent on
3668 DEP_INSN through the dependence LINK. The default is to make no
3669 adjustment to COST. On the MIPS, ignore the cost of anti- and
3670 output-dependencies. */
3672 #define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \
3673 if (REG_NOTE_KIND (LINK) != 0) \
3674 (COST) = 0; /* Anti or output dependence. */
3676 /* Optionally define this if you have added predicates to
3677 `MACHINE.c'. This macro is called within an initializer of an
3678 array of structures. The first field in the structure is the
3679 name of a predicate and the second field is an array of rtl
3680 codes. For each predicate, list all rtl codes that can be in
3681 expressions matched by the predicate. The list should have a
3682 trailing comma. Here is an example of two entries in the list
3683 for a typical RISC machine:
3685 #define PREDICATE_CODES \
3686 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3687 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3689 Defining this macro does not affect the generated code (however,
3690 incorrect definitions that omit an rtl code that may be matched
3691 by the predicate can cause the compiler to malfunction).
3692 Instead, it allows the table built by `genrecog' to be more
3693 compact and efficient, thus speeding up the compiler. The most
3694 important predicates to include in the list specified by this
3695 macro are thoses used in the most insn patterns. */
3697 #define PREDICATE_CODES \
3698 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3699 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3700 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3701 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3702 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3703 {"small_int", { CONST_INT }}, \
3704 {"large_int", { CONST_INT }}, \
3705 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3706 {"const_float_1_operand", { CONST_DOUBLE }}, \
3707 {"simple_memory_operand", { MEM, SUBREG }}, \
3708 {"equality_op", { EQ, NE }}, \
3709 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3711 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3712 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3713 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3714 SYMBOL_REF, LABEL_REF, SUBREG, \
3716 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3717 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3718 MEM, SIGN_EXTEND }}, \
3719 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3720 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3722 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3724 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3726 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3727 SYMBOL_REF, LABEL_REF, SUBREG, \
3728 REG, SIGN_EXTEND }}, \
3729 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3730 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3731 CONST_DOUBLE, CONST }}, \
3732 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3733 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3737 /* If defined, a C statement to be executed just prior to the
3738 output of assembler code for INSN, to modify the extracted
3739 operands so they will be output differently.
3741 Here the argument OPVEC is the vector containing the operands
3742 extracted from INSN, and NOPERANDS is the number of elements of
3743 the vector which contain meaningful data for this insn. The
3744 contents of this vector are what will be used to convert the
3745 insn template into assembler code, so you can change the
3746 assembler output by changing the contents of the vector.
3748 We use it to check if the current insn needs a nop in front of it
3749 because of load delays, and also to update the delay slot
3752 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3753 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3756 /* Control the assembler format that we output. */
3758 /* Output at beginning of assembler file.
3759 If we are optimizing to use the global pointer, create a temporary
3760 file to hold all of the text stuff, and write it out to the end.
3761 This is needed because the MIPS assembler is evidently one pass,
3762 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3763 declaration when the code is processed, it generates a two
3764 instruction sequence. */
3766 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3768 /* Output to assembler file text saying following lines
3769 may contain character constants, extra white space, comments, etc. */
3771 #define ASM_APP_ON " #APP\n"
3773 /* Output to assembler file text saying following lines
3774 no longer contain unusual constructs. */
3776 #define ASM_APP_OFF " #NO_APP\n"
3778 /* How to refer to registers in assembler output.
3779 This sequence is indexed by compiler's hard-register-number (see above).
3781 In order to support the two different conventions for register names,
3782 we use the name of a table set up in mips.c, which is overwritten
3783 if -mrnames is used. */
3785 #define REGISTER_NAMES \
3787 &mips_reg_names[ 0][0], \
3788 &mips_reg_names[ 1][0], \
3789 &mips_reg_names[ 2][0], \
3790 &mips_reg_names[ 3][0], \
3791 &mips_reg_names[ 4][0], \
3792 &mips_reg_names[ 5][0], \
3793 &mips_reg_names[ 6][0], \
3794 &mips_reg_names[ 7][0], \
3795 &mips_reg_names[ 8][0], \
3796 &mips_reg_names[ 9][0], \
3797 &mips_reg_names[10][0], \
3798 &mips_reg_names[11][0], \
3799 &mips_reg_names[12][0], \
3800 &mips_reg_names[13][0], \
3801 &mips_reg_names[14][0], \
3802 &mips_reg_names[15][0], \
3803 &mips_reg_names[16][0], \
3804 &mips_reg_names[17][0], \
3805 &mips_reg_names[18][0], \
3806 &mips_reg_names[19][0], \
3807 &mips_reg_names[20][0], \
3808 &mips_reg_names[21][0], \
3809 &mips_reg_names[22][0], \
3810 &mips_reg_names[23][0], \
3811 &mips_reg_names[24][0], \
3812 &mips_reg_names[25][0], \
3813 &mips_reg_names[26][0], \
3814 &mips_reg_names[27][0], \
3815 &mips_reg_names[28][0], \
3816 &mips_reg_names[29][0], \
3817 &mips_reg_names[30][0], \
3818 &mips_reg_names[31][0], \
3819 &mips_reg_names[32][0], \
3820 &mips_reg_names[33][0], \
3821 &mips_reg_names[34][0], \
3822 &mips_reg_names[35][0], \
3823 &mips_reg_names[36][0], \
3824 &mips_reg_names[37][0], \
3825 &mips_reg_names[38][0], \
3826 &mips_reg_names[39][0], \
3827 &mips_reg_names[40][0], \
3828 &mips_reg_names[41][0], \
3829 &mips_reg_names[42][0], \
3830 &mips_reg_names[43][0], \
3831 &mips_reg_names[44][0], \
3832 &mips_reg_names[45][0], \
3833 &mips_reg_names[46][0], \
3834 &mips_reg_names[47][0], \
3835 &mips_reg_names[48][0], \
3836 &mips_reg_names[49][0], \
3837 &mips_reg_names[50][0], \
3838 &mips_reg_names[51][0], \
3839 &mips_reg_names[52][0], \
3840 &mips_reg_names[53][0], \
3841 &mips_reg_names[54][0], \
3842 &mips_reg_names[55][0], \
3843 &mips_reg_names[56][0], \
3844 &mips_reg_names[57][0], \
3845 &mips_reg_names[58][0], \
3846 &mips_reg_names[59][0], \
3847 &mips_reg_names[60][0], \
3848 &mips_reg_names[61][0], \
3849 &mips_reg_names[62][0], \
3850 &mips_reg_names[63][0], \
3851 &mips_reg_names[64][0], \
3852 &mips_reg_names[65][0], \
3853 &mips_reg_names[66][0], \
3854 &mips_reg_names[67][0], \
3855 &mips_reg_names[68][0], \
3856 &mips_reg_names[69][0], \
3857 &mips_reg_names[70][0], \
3858 &mips_reg_names[71][0], \
3859 &mips_reg_names[72][0], \
3860 &mips_reg_names[73][0], \
3861 &mips_reg_names[74][0], \
3862 &mips_reg_names[75][0], \
3865 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3866 So define this for it. */
3867 #define DEBUG_REGISTER_NAMES \
3869 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3870 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3871 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3872 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3873 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3874 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3875 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3876 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3877 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3878 "$fcc5","$fcc6","$fcc7","$rap" \
3881 /* If defined, a C initializer for an array of structures
3882 containing a name and a register number. This macro defines
3883 additional names for hard registers, thus allowing the `asm'
3884 option in declarations to refer to registers using alternate
3887 We define both names for the integer registers here. */
3889 #define ADDITIONAL_REGISTER_NAMES \
3891 { "$0", 0 + GP_REG_FIRST }, \
3892 { "$1", 1 + GP_REG_FIRST }, \
3893 { "$2", 2 + GP_REG_FIRST }, \
3894 { "$3", 3 + GP_REG_FIRST }, \
3895 { "$4", 4 + GP_REG_FIRST }, \
3896 { "$5", 5 + GP_REG_FIRST }, \
3897 { "$6", 6 + GP_REG_FIRST }, \
3898 { "$7", 7 + GP_REG_FIRST }, \
3899 { "$8", 8 + GP_REG_FIRST }, \
3900 { "$9", 9 + GP_REG_FIRST }, \
3901 { "$10", 10 + GP_REG_FIRST }, \
3902 { "$11", 11 + GP_REG_FIRST }, \
3903 { "$12", 12 + GP_REG_FIRST }, \
3904 { "$13", 13 + GP_REG_FIRST }, \
3905 { "$14", 14 + GP_REG_FIRST }, \
3906 { "$15", 15 + GP_REG_FIRST }, \
3907 { "$16", 16 + GP_REG_FIRST }, \
3908 { "$17", 17 + GP_REG_FIRST }, \
3909 { "$18", 18 + GP_REG_FIRST }, \
3910 { "$19", 19 + GP_REG_FIRST }, \
3911 { "$20", 20 + GP_REG_FIRST }, \
3912 { "$21", 21 + GP_REG_FIRST }, \
3913 { "$22", 22 + GP_REG_FIRST }, \
3914 { "$23", 23 + GP_REG_FIRST }, \
3915 { "$24", 24 + GP_REG_FIRST }, \
3916 { "$25", 25 + GP_REG_FIRST }, \
3917 { "$26", 26 + GP_REG_FIRST }, \
3918 { "$27", 27 + GP_REG_FIRST }, \
3919 { "$28", 28 + GP_REG_FIRST }, \
3920 { "$29", 29 + GP_REG_FIRST }, \
3921 { "$30", 30 + GP_REG_FIRST }, \
3922 { "$31", 31 + GP_REG_FIRST }, \
3923 { "$sp", 29 + GP_REG_FIRST }, \
3924 { "$fp", 30 + GP_REG_FIRST }, \
3925 { "at", 1 + GP_REG_FIRST }, \
3926 { "v0", 2 + GP_REG_FIRST }, \
3927 { "v1", 3 + GP_REG_FIRST }, \
3928 { "a0", 4 + GP_REG_FIRST }, \
3929 { "a1", 5 + GP_REG_FIRST }, \
3930 { "a2", 6 + GP_REG_FIRST }, \
3931 { "a3", 7 + GP_REG_FIRST }, \
3932 { "t0", 8 + GP_REG_FIRST }, \
3933 { "t1", 9 + GP_REG_FIRST }, \
3934 { "t2", 10 + GP_REG_FIRST }, \
3935 { "t3", 11 + GP_REG_FIRST }, \
3936 { "t4", 12 + GP_REG_FIRST }, \
3937 { "t5", 13 + GP_REG_FIRST }, \
3938 { "t6", 14 + GP_REG_FIRST }, \
3939 { "t7", 15 + GP_REG_FIRST }, \
3940 { "s0", 16 + GP_REG_FIRST }, \
3941 { "s1", 17 + GP_REG_FIRST }, \
3942 { "s2", 18 + GP_REG_FIRST }, \
3943 { "s3", 19 + GP_REG_FIRST }, \
3944 { "s4", 20 + GP_REG_FIRST }, \
3945 { "s5", 21 + GP_REG_FIRST }, \
3946 { "s6", 22 + GP_REG_FIRST }, \
3947 { "s7", 23 + GP_REG_FIRST }, \
3948 { "t8", 24 + GP_REG_FIRST }, \
3949 { "t9", 25 + GP_REG_FIRST }, \
3950 { "k0", 26 + GP_REG_FIRST }, \
3951 { "k1", 27 + GP_REG_FIRST }, \
3952 { "gp", 28 + GP_REG_FIRST }, \
3953 { "sp", 29 + GP_REG_FIRST }, \
3954 { "fp", 30 + GP_REG_FIRST }, \
3955 { "ra", 31 + GP_REG_FIRST }, \
3956 { "$sp", 29 + GP_REG_FIRST }, \
3957 { "$fp", 30 + GP_REG_FIRST } \
3960 /* Define results of standard character escape sequences. */
3961 #define TARGET_BELL 007
3962 #define TARGET_BS 010
3963 #define TARGET_TAB 011
3964 #define TARGET_NEWLINE 012
3965 #define TARGET_VT 013
3966 #define TARGET_FF 014
3967 #define TARGET_CR 015
3969 /* A C compound statement to output to stdio stream STREAM the
3970 assembler syntax for an instruction operand X. X is an RTL
3973 CODE is a value that can be used to specify one of several ways
3974 of printing the operand. It is used when identical operands
3975 must be printed differently depending on the context. CODE
3976 comes from the `%' specification that was used to request
3977 printing of the operand. If the specification was just `%DIGIT'
3978 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3979 is the ASCII code for LTR.
3981 If X is a register, this macro should print the register's name.
3982 The names can be found in an array `reg_names' whose type is
3983 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3985 When the machine description has a specification `%PUNCT' (a `%'
3986 followed by a punctuation character), this macro is called with
3987 a null pointer for X and the punctuation character for CODE.
3989 See mips.c for the MIPS specific codes. */
3991 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3993 /* A C expression which evaluates to true if CODE is a valid
3994 punctuation character for use in the `PRINT_OPERAND' macro. If
3995 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3996 punctuation characters (except for the standard one, `%') are
3997 used in this way. */
3999 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4001 /* A C compound statement to output to stdio stream STREAM the
4002 assembler syntax for an instruction operand that is a memory
4003 reference whose address is ADDR. ADDR is an RTL expression.
4005 On some machines, the syntax for a symbolic address depends on
4006 the section that the address refers to. On these machines,
4007 define the macro `ENCODE_SECTION_INFO' to store the information
4008 into the `symbol_ref', and then check for it here. */
4010 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4013 /* A C statement, to be executed after all slot-filler instructions
4014 have been output. If necessary, call `dbr_sequence_length' to
4015 determine the number of slots filled in a sequence (zero if not
4016 currently outputting a sequence), to decide how many no-ops to
4017 output, or whatever.
4019 Don't define this macro if it has nothing to do, but it is
4020 helpful in reading assembly output if the extent of the delay
4021 sequence is made explicit (e.g. with white space).
4023 Note that output routines for instructions with delay slots must
4024 be prepared to deal with not being output as part of a sequence
4025 (i.e. when the scheduling pass is not run, or when no slot
4026 fillers could be found.) The variable `final_sequence' is null
4027 when not processing a sequence, otherwise it contains the
4028 `sequence' rtx being output. */
4030 #define DBR_OUTPUT_SEQEND(STREAM) \
4033 if (set_nomacro > 0 && --set_nomacro == 0) \
4034 fputs ("\t.set\tmacro\n", STREAM); \
4036 if (set_noreorder > 0 && --set_noreorder == 0) \
4037 fputs ("\t.set\treorder\n", STREAM); \
4039 dslots_jump_filled++; \
4040 fputs ("\n", STREAM); \
4045 /* How to tell the debugger about changes of source files. Note, the
4046 mips ECOFF format cannot deal with changes of files inside of
4047 functions, which means the output of parser generators like bison
4048 is generally not debuggable without using the -l switch. Lose,
4049 lose, lose. Silicon graphics seems to want all .file's hardwired
4052 #ifndef SET_FILE_NUMBER
4053 #define SET_FILE_NUMBER() ++num_source_filenames
4056 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4057 mips_output_filename (STREAM, NAME)
4059 /* This is defined so that it can be overridden in iris6.h. */
4060 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4063 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4064 output_quoted_string (STREAM, NAME); \
4065 fputs ("\n", STREAM); \
4069 /* This is how to output a note the debugger telling it the line number
4070 to which the following sequence of instructions corresponds.
4071 Silicon graphics puts a label after each .loc. */
4073 #ifndef LABEL_AFTER_LOC
4074 #define LABEL_AFTER_LOC(STREAM)
4077 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4078 mips_output_lineno (STREAM, LINE)
4080 /* The MIPS implementation uses some labels for its own purpose. The
4081 following lists what labels are created, and are all formed by the
4082 pattern $L[a-z].*. The machine independent portion of GCC creates
4083 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4085 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4086 $Lb[0-9]+ Begin blocks for MIPS debug support
4087 $Lc[0-9]+ Label for use in s<xx> operation.
4088 $Le[0-9]+ End blocks for MIPS debug support
4089 $Lp\..+ Half-pic labels. */
4091 /* This is how to output the definition of a user-level label named NAME,
4092 such as the label on a static function or variable NAME.
4094 If we are optimizing the gp, remember that this label has been put
4095 out, so we know not to emit an .extern for it in mips_asm_file_end.
4096 We use one of the common bits in the IDENTIFIER tree node for this,
4097 since those bits seem to be unused, and we don't have any method
4098 of getting the decl nodes from the name. */
4100 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4102 assemble_name (STREAM, NAME); \
4103 fputs (":\n", STREAM); \
4107 /* A C statement (sans semicolon) to output to the stdio stream
4108 STREAM any text necessary for declaring the name NAME of an
4109 initialized variable which is being defined. This macro must
4110 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4111 The argument DECL is the `VAR_DECL' tree node representing the
4114 If this macro is not defined, then the variable name is defined
4115 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4117 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4120 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4121 HALF_PIC_DECLARE (NAME); \
4126 /* This is how to output a command to make the user-level label named NAME
4127 defined for reference from other files. */
4129 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4131 fputs ("\t.globl\t", STREAM); \
4132 assemble_name (STREAM, NAME); \
4133 fputs ("\n", STREAM); \
4136 /* This says how to define a global common symbol. */
4138 #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
4139 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", (SIZE))
4141 /* This says how to define a local common symbol (ie, not visible to
4144 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4145 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4148 /* This says how to output an external. It would be possible not to
4149 output anything and let undefined symbol become external. However
4150 the assembler uses length information on externals to allocate in
4151 data/sdata bss/sbss, thereby saving exec time. */
4153 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4154 mips_output_external(STREAM,DECL,NAME)
4156 /* This says what to print at the end of the assembly file */
4157 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4160 /* This is how to declare a function name. The actual work of
4161 emitting the label is moved to function_prologue, so that we can
4162 get the line number correctly emitted before the .ent directive,
4163 and after any .file directives.
4165 Also, switch files if we are optimizing the global pointer. */
4167 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4169 extern FILE *asm_out_text_file; \
4170 if (TARGET_GP_OPT && ! TARGET_MIPS16) \
4172 STREAM = asm_out_text_file; \
4173 /* ??? text_section gets called too soon. If the previous \
4174 function is in a special section and we're not, we have \
4175 to switch back to the text section. We can't call \
4176 text_section again as gcc thinks we're already there. */ \
4177 /* ??? See varasm.c. There are other things that get output \
4178 too early, like alignment (before we've switched STREAM). */ \
4179 if (DECL_SECTION_NAME (DECL) == NULL_TREE) \
4180 fprintf (STREAM, "%s\n", TEXT_SECTION_ASM_OP); \
4183 HALF_PIC_DECLARE (NAME); \
4186 /* This is how to output an internal numbered label where
4187 PREFIX is the class of label and NUM is the number within the class. */
4189 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4190 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4192 /* This is how to store into the string LABEL
4193 the symbol_ref name of an internal numbered label where
4194 PREFIX is the class of label and NUM is the number within the class.
4195 This is suitable for output with `assemble_name'. */
4197 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4198 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4200 /* This is how to output an assembler line defining a `double' constant. */
4202 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4203 mips_output_double (STREAM, VALUE)
4206 /* This is how to output an assembler line defining a `float' constant. */
4208 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4209 mips_output_float (STREAM, VALUE)
4212 /* This is how to output an assembler line defining an `int' constant. */
4214 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4216 fprintf (STREAM, "\t.word\t"); \
4217 output_addr_const (STREAM, (VALUE)); \
4218 fprintf (STREAM, "\n"); \
4221 /* Likewise for 64 bit, `char' and `short' constants. */
4223 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4227 fprintf (STREAM, "\t.dword\t"); \
4228 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4229 /* We can't use 'X' for negative numbers, because then we won't \
4230 get the right value for the upper 32 bits. */ \
4231 output_addr_const (STREAM, VALUE); \
4233 /* We must use 'X', because otherwise LONG_MIN will print as \
4234 a number that the Irix 6 assembler won't accept. */ \
4235 print_operand (STREAM, VALUE, 'X'); \
4236 fprintf (STREAM, "\n"); \
4240 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4241 UNITS_PER_WORD, 1); \
4242 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4243 UNITS_PER_WORD, 1); \
4247 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4249 fprintf (STREAM, "\t.half\t"); \
4250 output_addr_const (STREAM, (VALUE)); \
4251 fprintf (STREAM, "\n"); \
4254 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4256 fprintf (STREAM, "\t.byte\t"); \
4257 output_addr_const (STREAM, (VALUE)); \
4258 fprintf (STREAM, "\n"); \
4261 /* This is how to output an assembler line for a numeric constant byte. */
4263 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4264 fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
4266 /* This is how to output an element of a case-vector that is absolute. */
4268 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4269 fprintf (STREAM, "\t%s\t%sL%d\n", \
4270 Pmode == DImode ? ".dword" : ".word", \
4271 LOCAL_LABEL_PREFIX, \
4274 /* This is how to output an element of a case-vector that is relative.
4275 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4276 TARGET_EMBEDDED_PIC). */
4278 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4280 if (TARGET_MIPS16) \
4281 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4282 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4283 else if (TARGET_EMBEDDED_PIC) \
4284 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4285 Pmode == DImode ? ".dword" : ".word", \
4286 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4287 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4288 fprintf (STREAM, "\t%s\t%sL%d\n", \
4289 Pmode == DImode ? ".gpdword" : ".gpword", \
4290 LOCAL_LABEL_PREFIX, VALUE); \
4292 fprintf (STREAM, "\t%s\t%sL%d\n", \
4293 Pmode == DImode ? ".dword" : ".word", \
4294 LOCAL_LABEL_PREFIX, VALUE); \
4297 /* When generating embedded PIC or mips16 code we want to put the jump
4298 table in the .text section. In all other cases, we want to put the
4299 jump table in the .rdata section. Unfortunately, we can't use
4300 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4301 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4302 section if appropriate. */
4303 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4305 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4306 function_section (current_function_decl); \
4307 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4310 /* This is how to output an assembler line
4311 that says to advance the location counter
4312 to a multiple of 2**LOG bytes. */
4314 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4315 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4317 /* This is how to output an assembler line to advance the location
4318 counter by SIZE bytes. */
4320 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4321 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4323 /* This is how to output a string. */
4324 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4326 register int i, c, len = (LEN), cur_pos = 17; \
4327 register unsigned char *string = (unsigned char *)(STRING); \
4328 fprintf ((STREAM), "\t.ascii\t\""); \
4329 for (i = 0; i < len; i++) \
4331 register int c = string[i]; \
4337 putc ('\\', (STREAM)); \
4338 putc (c, (STREAM)); \
4342 case TARGET_NEWLINE: \
4343 fputs ("\\n", (STREAM)); \
4345 && (((c = string[i+1]) >= '\040' && c <= '~') \
4346 || c == TARGET_TAB)) \
4347 cur_pos = 32767; /* break right here */ \
4353 fputs ("\\t", (STREAM)); \
4358 fputs ("\\f", (STREAM)); \
4363 fputs ("\\b", (STREAM)); \
4368 fputs ("\\r", (STREAM)); \
4373 if (c >= ' ' && c < 0177) \
4375 putc (c, (STREAM)); \
4380 fprintf ((STREAM), "\\%03o", c); \
4385 if (cur_pos > 72 && i+1 < len) \
4388 fprintf ((STREAM), "\"\n\t.ascii\t\""); \
4391 fprintf ((STREAM), "\"\n"); \
4394 /* Handle certain cpp directives used in header files on sysV. */
4395 #define SCCS_DIRECTIVE
4397 /* Output #ident as a in the read-only data section. */
4398 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4401 int size = strlen (p) + 1; \
4403 assemble_string (p, size); \
4406 /* Default to -G 8 */
4407 #ifndef MIPS_DEFAULT_GVALUE
4408 #define MIPS_DEFAULT_GVALUE 8
4411 /* Define the strings to put out for each section in the object file. */
4412 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4413 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4414 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4415 #define RDATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4416 #define READONLY_DATA_SECTION rdata_section
4417 #define SMALL_DATA_SECTION sdata_section
4419 /* What other sections we support other than the normal .data/.text. */
4421 #define EXTRA_SECTIONS in_sdata, in_rdata
4423 /* Define the additional functions to select our additional sections. */
4425 /* on the MIPS it is not a good idea to put constants in the text
4426 section, since this defeats the sdata/data mechanism. This is
4427 especially true when -O is used. In this case an effort is made to
4428 address with faster (gp) register relative addressing, which can
4429 only get at sdata and sbss items (there is no stext !!) However,
4430 if the constant is too large for sdata, and it's readonly, it
4431 will go into the .rdata section. */
4433 #define EXTRA_SECTION_FUNCTIONS \
4437 if (in_section != in_sdata) \
4439 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4440 in_section = in_sdata; \
4447 if (in_section != in_rdata) \
4449 fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
4450 in_section = in_rdata; \
4454 /* Given a decl node or constant node, choose the section to output it in
4455 and select that section. */
4457 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4459 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4462 /* Store in OUTPUT a string (made with alloca) containing
4463 an assembler-name for a local static variable named NAME.
4464 LABELNO is an integer which is different for each call. */
4466 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4467 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4468 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4470 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4473 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4474 TARGET_64BIT ? "dsubu" : "subu", \
4475 reg_names[STACK_POINTER_REGNUM], \
4476 reg_names[STACK_POINTER_REGNUM], \
4477 TARGET_64BIT ? "sd" : "sw", \
4479 reg_names[STACK_POINTER_REGNUM]); \
4483 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4486 if (! set_noreorder) \
4487 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4489 dslots_load_total++; \
4490 dslots_load_filled++; \
4491 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4492 TARGET_64BIT ? "ld" : "lw", \
4494 reg_names[STACK_POINTER_REGNUM], \
4495 TARGET_64BIT ? "daddu" : "addu", \
4496 reg_names[STACK_POINTER_REGNUM], \
4497 reg_names[STACK_POINTER_REGNUM]); \
4499 if (! set_noreorder) \
4500 fprintf (STREAM, "\t.set\treorder\n"); \
4504 /* Define the parentheses used to group arithmetic operations
4505 in assembler code. */
4507 #define ASM_OPEN_PAREN "("
4508 #define ASM_CLOSE_PAREN ")"
4510 /* How to start an assembler comment.
4511 The leading space is important (the mips native assembler requires it). */
4512 #ifndef ASM_COMMENT_START
4513 #define ASM_COMMENT_START " #"
4517 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4518 and mips-tdump.c to print them out.
4520 These must match the corresponding definitions in gdb/mipsread.c.
4521 Unfortunately, gcc and gdb do not currently share any directories. */
4523 #define CODE_MASK 0x8F300
4524 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4525 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4526 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4529 /* Default definitions for size_t and ptrdiff_t. */
4532 #define NO_BUILTIN_SIZE_TYPE
4533 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4536 #ifndef PTRDIFF_TYPE
4537 #define NO_BUILTIN_PTRDIFF_TYPE
4538 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4541 /* See mips_expand_prologue's use of loadgp for when this should be
4544 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4545 && mips_abi != ABI_32 \
4546 && mips_abi != ABI_O64)
4548 /* In mips16 mode, we need to look through the function to check for
4549 PC relative loads that are out of range. */
4550 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4552 /* We need to use a special set of functions to handle hard floating
4553 point code in mips16 mode. */
4555 #ifndef INIT_SUBTARGET_OPTABS
4556 #define INIT_SUBTARGET_OPTABS
4559 #define INIT_TARGET_OPTABS \
4562 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4563 INIT_SUBTARGET_OPTABS; \
4566 add_optab->handlers[(int) SFmode].libfunc = \
4567 gen_rtx (SYMBOL_REF, Pmode, "__mips16_addsf3"); \
4568 sub_optab->handlers[(int) SFmode].libfunc = \
4569 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subsf3"); \
4570 smul_optab->handlers[(int) SFmode].libfunc = \
4571 gen_rtx (SYMBOL_REF, Pmode, "__mips16_mulsf3"); \
4572 flodiv_optab->handlers[(int) SFmode].libfunc = \
4573 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divsf3"); \
4575 eqsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqsf2"); \
4576 nesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_nesf2"); \
4577 gtsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtsf2"); \
4578 gesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_gesf2"); \
4579 ltsf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltsf2"); \
4580 lesf2_libfunc = gen_rtx (SYMBOL_REF, Pmode, "__mips16_lesf2"); \
4582 floatsisf_libfunc = \
4583 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsisf"); \
4585 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixsfsi"); \
4587 if (TARGET_DOUBLE_FLOAT) \
4589 add_optab->handlers[(int) DFmode].libfunc = \
4590 gen_rtx (SYMBOL_REF, Pmode, "__mips16_adddf3"); \
4591 sub_optab->handlers[(int) DFmode].libfunc = \
4592 gen_rtx (SYMBOL_REF, Pmode, "__mips16_subdf3"); \
4593 smul_optab->handlers[(int) DFmode].libfunc = \
4594 gen_rtx (SYMBOL_REF, Pmode, "__mips16_muldf3"); \
4595 flodiv_optab->handlers[(int) DFmode].libfunc = \
4596 gen_rtx (SYMBOL_REF, Pmode, "__mips16_divdf3"); \
4598 extendsfdf2_libfunc = \
4599 gen_rtx (SYMBOL_REF, Pmode, "__mips16_extendsfdf2"); \
4600 truncdfsf2_libfunc = \
4601 gen_rtx (SYMBOL_REF, Pmode, "__mips16_truncdfsf2"); \
4604 gen_rtx (SYMBOL_REF, Pmode, "__mips16_eqdf2"); \
4606 gen_rtx (SYMBOL_REF, Pmode, "__mips16_nedf2"); \
4608 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gtdf2"); \
4610 gen_rtx (SYMBOL_REF, Pmode, "__mips16_gedf2"); \
4612 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ltdf2"); \
4614 gen_rtx (SYMBOL_REF, Pmode, "__mips16_ledf2"); \
4616 floatsidf_libfunc = \
4617 gen_rtx (SYMBOL_REF, Pmode, "__mips16_floatsidf"); \
4619 gen_rtx (SYMBOL_REF, Pmode, "__mips16_fixdfsi"); \