1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "langhooks.h"
54 #include "sched-int.h"
57 #include "diagnostic.h"
58 #include "target-globals.h"
61 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
62 #define UNSPEC_ADDRESS_P(X) \
63 (GET_CODE (X) == UNSPEC \
64 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
65 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
67 /* Extract the symbol or label from UNSPEC wrapper X. */
68 #define UNSPEC_ADDRESS(X) \
71 /* Extract the symbol type from UNSPEC wrapper X. */
72 #define UNSPEC_ADDRESS_TYPE(X) \
73 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
75 /* The maximum distance between the top of the stack frame and the
76 value $sp has when we save and restore registers.
78 The value for normal-mode code must be a SMALL_OPERAND and must
79 preserve the maximum stack alignment. We therefore use a value
80 of 0x7ff0 in this case.
82 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
83 up to 0x7f8 bytes and can usually save or restore all the registers
84 that we need to save or restore. (Note that we can only use these
85 instructions for o32, for which the stack alignment is 8 bytes.)
87 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
88 RESTORE are not available. We can then use unextended instructions
89 to save and restore registers, and to allocate and deallocate the top
91 #define MIPS_MAX_FIRST_STACK_STEP \
92 (!TARGET_MIPS16 ? 0x7ff0 \
93 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
94 : TARGET_64BIT ? 0x100 : 0x400)
96 /* True if INSN is a mips.md pattern or asm statement. */
97 #define USEFUL_INSN_P(INSN) \
98 (NONDEBUG_INSN_P (INSN) \
99 && GET_CODE (PATTERN (INSN)) != USE \
100 && GET_CODE (PATTERN (INSN)) != CLOBBER \
101 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
102 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
104 /* If INSN is a delayed branch sequence, return the first instruction
105 in the sequence, otherwise return INSN itself. */
106 #define SEQ_BEGIN(INSN) \
107 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
108 ? XVECEXP (PATTERN (INSN), 0, 0) \
111 /* Likewise for the last instruction in a delayed branch sequence. */
112 #define SEQ_END(INSN) \
113 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
114 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
117 /* Execute the following loop body with SUBINSN set to each instruction
118 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
119 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
120 for ((SUBINSN) = SEQ_BEGIN (INSN); \
121 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
122 (SUBINSN) = NEXT_INSN (SUBINSN))
124 /* True if bit BIT is set in VALUE. */
125 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
127 /* Return the opcode for a ptr_mode load of the form:
129 l[wd] DEST, OFFSET(BASE). */
130 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
131 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
136 /* Return the opcode to move register SRC into register DEST. */
137 #define MIPS_MOVE(DEST, SRC) \
138 ((TARGET_64BIT ? 0x2d : 0x21) \
142 /* Return the opcode for:
145 #define MIPS_LUI(DEST, VALUE) \
146 ((0xf << 26) | ((DEST) << 16) | (VALUE))
148 /* Return the opcode to jump to register DEST. */
149 #define MIPS_JR(DEST) \
150 (((DEST) << 21) | 0x8)
152 /* Return the opcode for:
154 bal . + (1 + OFFSET) * 4. */
155 #define MIPS_BAL(OFFSET) \
156 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
158 /* Return the usual opcode for a nop. */
161 /* Classifies an address.
164 A natural register + offset address. The register satisfies
165 mips_valid_base_register_p and the offset is a const_arith_operand.
168 A LO_SUM rtx. The first operand is a valid base register and
169 the second operand is a symbolic address.
172 A signed 16-bit constant address.
175 A constant symbolic address. */
176 enum mips_address_type {
183 /* Macros to create an enumeration identifier for a function prototype. */
184 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
185 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
186 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
187 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
189 /* Classifies the prototype of a built-in function. */
190 enum mips_function_type {
191 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
192 #include "config/mips/mips-ftypes.def"
193 #undef DEF_MIPS_FTYPE
197 /* Specifies how a built-in function should be converted into rtl. */
198 enum mips_builtin_type {
199 /* The function corresponds directly to an .md pattern. The return
200 value is mapped to operand 0 and the arguments are mapped to
201 operands 1 and above. */
204 /* The function corresponds directly to an .md pattern. There is no return
205 value and the arguments are mapped to operands 0 and above. */
206 MIPS_BUILTIN_DIRECT_NO_TARGET,
208 /* The function corresponds to a comparison instruction followed by
209 a mips_cond_move_tf_ps pattern. The first two arguments are the
210 values to compare and the second two arguments are the vector
211 operands for the movt.ps or movf.ps instruction (in assembly order). */
215 /* The function corresponds to a V2SF comparison instruction. Operand 0
216 of this instruction is the result of the comparison, which has mode
217 CCV2 or CCV4. The function arguments are mapped to operands 1 and
218 above. The function's return value is an SImode boolean that is
219 true under the following conditions:
221 MIPS_BUILTIN_CMP_ANY: one of the registers is true
222 MIPS_BUILTIN_CMP_ALL: all of the registers are true
223 MIPS_BUILTIN_CMP_LOWER: the first register is true
224 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
225 MIPS_BUILTIN_CMP_ANY,
226 MIPS_BUILTIN_CMP_ALL,
227 MIPS_BUILTIN_CMP_UPPER,
228 MIPS_BUILTIN_CMP_LOWER,
230 /* As above, but the instruction only sets a single $fcc register. */
231 MIPS_BUILTIN_CMP_SINGLE,
233 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
234 MIPS_BUILTIN_BPOSGE32
237 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
238 #define MIPS_FP_CONDITIONS(MACRO) \
256 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
257 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
258 enum mips_fp_condition {
259 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
262 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
263 #define STRINGIFY(X) #X
264 static const char *const mips_fp_conditions[] = {
265 MIPS_FP_CONDITIONS (STRINGIFY)
268 /* Tuning information that is automatically derived from other sources
269 (such as the scheduler). */
271 /* The architecture and tuning settings that this structure describes. */
275 /* True if this structure describes MIPS16 settings. */
278 /* True if the structure has been initialized. */
281 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
282 when optimizing for speed. */
283 bool fast_mult_zero_zero_p;
286 /* Information about a function's frame layout. */
287 struct GTY(()) mips_frame_info {
288 /* The size of the frame in bytes. */
289 HOST_WIDE_INT total_size;
291 /* The number of bytes allocated to variables. */
292 HOST_WIDE_INT var_size;
294 /* The number of bytes allocated to outgoing function arguments. */
295 HOST_WIDE_INT args_size;
297 /* The number of bytes allocated to the .cprestore slot, or 0 if there
299 HOST_WIDE_INT cprestore_size;
301 /* Bit X is set if the function saves or restores GPR X. */
304 /* Likewise FPR X. */
307 /* Likewise doubleword accumulator X ($acX). */
308 unsigned int acc_mask;
310 /* The number of GPRs, FPRs, doubleword accumulators and COP0
314 unsigned int num_acc;
315 unsigned int num_cop0_regs;
317 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
318 save slots from the top of the frame, or zero if no such slots are
320 HOST_WIDE_INT gp_save_offset;
321 HOST_WIDE_INT fp_save_offset;
322 HOST_WIDE_INT acc_save_offset;
323 HOST_WIDE_INT cop0_save_offset;
325 /* Likewise, but giving offsets from the bottom of the frame. */
326 HOST_WIDE_INT gp_sp_offset;
327 HOST_WIDE_INT fp_sp_offset;
328 HOST_WIDE_INT acc_sp_offset;
329 HOST_WIDE_INT cop0_sp_offset;
331 /* Similar, but the value passed to _mcount. */
332 HOST_WIDE_INT ra_fp_offset;
334 /* The offset of arg_pointer_rtx from the bottom of the frame. */
335 HOST_WIDE_INT arg_pointer_offset;
337 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
338 HOST_WIDE_INT hard_frame_pointer_offset;
341 struct GTY(()) machine_function {
342 /* The next floating-point condition-code register to allocate
343 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
344 unsigned int next_fcc;
346 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
347 rtx mips16_gp_pseudo_rtx;
349 /* The number of extra stack bytes taken up by register varargs.
350 This area is allocated by the callee at the very top of the frame. */
353 /* The current frame information, calculated by mips_compute_frame_info. */
354 struct mips_frame_info frame;
356 /* The register to use as the function's global pointer, or INVALID_REGNUM
357 if the function doesn't need one. */
358 unsigned int global_pointer;
360 /* How many instructions it takes to load a label into $AT, or 0 if
361 this property hasn't yet been calculated. */
362 unsigned int load_label_num_insns;
364 /* True if mips_adjust_insn_length should ignore an instruction's
366 bool ignore_hazard_length_p;
368 /* True if the whole function is suitable for .set noreorder and
370 bool all_noreorder_p;
372 /* True if the function has "inflexible" and "flexible" references
373 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
374 and mips_cfun_has_flexible_gp_ref_p for details. */
375 bool has_inflexible_gp_insn_p;
376 bool has_flexible_gp_insn_p;
378 /* True if the function's prologue must load the global pointer
379 value into pic_offset_table_rtx and store the same value in
380 the function's cprestore slot (if any). Even if this value
381 is currently false, we may decide to set it to true later;
382 see mips_must_initialize_gp_p () for details. */
383 bool must_initialize_gp_p;
385 /* True if the current function must restore $gp after any potential
386 clobber. This value is only meaningful during the first post-epilogue
387 split_insns pass; see mips_must_initialize_gp_p () for details. */
388 bool must_restore_gp_when_clobbered_p;
390 /* True if this is an interrupt handler. */
391 bool interrupt_handler_p;
393 /* True if this is an interrupt handler that uses shadow registers. */
394 bool use_shadow_register_set_p;
396 /* True if this is an interrupt handler that should keep interrupts
398 bool keep_interrupts_masked_p;
400 /* True if this is an interrupt handler that should use DERET
402 bool use_debug_exception_return_p;
405 /* Information about a single argument. */
406 struct mips_arg_info {
407 /* True if the argument is passed in a floating-point register, or
408 would have been if we hadn't run out of registers. */
411 /* The number of words passed in registers, rounded up. */
412 unsigned int reg_words;
414 /* For EABI, the offset of the first register from GP_ARG_FIRST or
415 FP_ARG_FIRST. For other ABIs, the offset of the first register from
416 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
417 comment for details).
419 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
421 unsigned int reg_offset;
423 /* The number of words that must be passed on the stack, rounded up. */
424 unsigned int stack_words;
426 /* The offset from the start of the stack overflow area of the argument's
427 first stack word. Only meaningful when STACK_WORDS is nonzero. */
428 unsigned int stack_offset;
431 /* Information about an address described by mips_address_type.
437 REG is the base register and OFFSET is the constant offset.
440 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
441 is the type of symbol it references.
444 SYMBOL_TYPE is the type of symbol that the address references. */
445 struct mips_address_info {
446 enum mips_address_type type;
449 enum mips_symbol_type symbol_type;
452 /* One stage in a constant building sequence. These sequences have
456 A = A CODE[1] VALUE[1]
457 A = A CODE[2] VALUE[2]
460 where A is an accumulator, each CODE[i] is a binary rtl operation
461 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
462 struct mips_integer_op {
464 unsigned HOST_WIDE_INT value;
467 /* The largest number of operations needed to load an integer constant.
468 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
469 When the lowest bit is clear, we can try, but reject a sequence with
470 an extra SLL at the end. */
471 #define MIPS_MAX_INTEGER_OPS 7
473 /* Information about a MIPS16e SAVE or RESTORE instruction. */
474 struct mips16e_save_restore_info {
475 /* The number of argument registers saved by a SAVE instruction.
476 0 for RESTORE instructions. */
479 /* Bit X is set if the instruction saves or restores GPR X. */
482 /* The total number of bytes to allocate. */
486 /* Costs of various operations on the different architectures. */
488 struct mips_rtx_cost_data
490 unsigned short fp_add;
491 unsigned short fp_mult_sf;
492 unsigned short fp_mult_df;
493 unsigned short fp_div_sf;
494 unsigned short fp_div_df;
495 unsigned short int_mult_si;
496 unsigned short int_mult_di;
497 unsigned short int_div_si;
498 unsigned short int_div_di;
499 unsigned short branch_cost;
500 unsigned short memory_latency;
503 /* Global variables for machine-dependent things. */
505 /* The -G setting, or the configuration's default small-data limit if
506 no -G option is given. */
507 static unsigned int mips_small_data_threshold;
509 /* The number of file directives written by mips_output_filename. */
510 int num_source_filenames;
512 /* The name that appeared in the last .file directive written by
513 mips_output_filename, or "" if mips_output_filename hasn't
514 written anything yet. */
515 const char *current_function_file = "";
517 /* Arrays that map GCC register numbers to debugger register numbers. */
518 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
519 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
521 /* Information about the current function's epilogue, used only while
524 /* A list of queued REG_CFA_RESTORE notes. */
527 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
529 HOST_WIDE_INT cfa_offset;
531 /* The offset of the CFA from the stack pointer while restoring
533 HOST_WIDE_INT cfa_restore_sp_offset;
536 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
537 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
538 struct mips_asm_switch mips_nomacro = { "macro", 0 };
539 struct mips_asm_switch mips_noat = { "at", 0 };
541 /* True if we're writing out a branch-likely instruction rather than a
543 static bool mips_branch_likely;
545 /* The current instruction-set architecture. */
546 enum processor mips_arch;
547 const struct mips_cpu_info *mips_arch_info;
549 /* The processor that we should tune the code for. */
550 enum processor mips_tune;
551 const struct mips_cpu_info *mips_tune_info;
553 /* The ISA level associated with mips_arch. */
556 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
557 static const struct mips_cpu_info *mips_isa_option_info;
559 /* Which cost information to use. */
560 static const struct mips_rtx_cost_data *mips_cost;
562 /* The ambient target flags, excluding MASK_MIPS16. */
563 static int mips_base_target_flags;
565 /* True if MIPS16 is the default mode. */
566 bool mips_base_mips16;
568 /* The ambient values of other global variables. */
569 static int mips_base_schedule_insns; /* flag_schedule_insns */
570 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
571 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
572 static int mips_base_align_loops; /* align_loops */
573 static int mips_base_align_jumps; /* align_jumps */
574 static int mips_base_align_functions; /* align_functions */
576 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
577 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
579 /* Index C is true if character C is a valid PRINT_OPERAND punctation
581 static bool mips_print_operand_punct[256];
583 static GTY (()) int mips_output_filename_first_time = 1;
585 /* mips_split_p[X] is true if symbols of type X can be split by
586 mips_split_symbol. */
587 bool mips_split_p[NUM_SYMBOL_TYPES];
589 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
590 can be split by mips_split_symbol. */
591 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
593 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
594 forced into a PC-relative constant pool. */
595 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
597 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
598 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
599 if they are matched by a special .md file pattern. */
600 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
602 /* Likewise for HIGHs. */
603 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
605 /* Target state for MIPS16. */
606 struct target_globals *mips16_globals;
608 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
609 and returned from mips_sched_reorder2. */
610 static int cached_can_issue_more;
612 /* True if the output uses __mips16_rdhwr. */
613 static bool mips_need_mips16_rdhwr_p;
615 /* Index R is the smallest register class that contains register R. */
616 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
617 LEA_REGS, LEA_REGS, M16_REGS, V1_REG,
618 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
619 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
620 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
621 M16_REGS, M16_REGS, LEA_REGS, LEA_REGS,
622 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
623 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
624 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
625 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
626 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
627 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
628 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
629 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
630 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
631 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
632 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
633 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
634 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
635 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
636 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
637 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
638 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
639 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
640 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
641 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
642 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
643 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
644 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
645 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
646 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
647 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
648 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
649 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
650 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
651 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
652 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
653 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
654 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
655 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
656 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
657 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
658 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
659 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
660 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
661 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
662 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
663 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
666 /* The value of TARGET_ATTRIBUTE_TABLE. */
667 static const struct attribute_spec mips_attribute_table[] = {
668 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
670 { "long_call", 0, 0, false, true, true, NULL, false },
671 { "far", 0, 0, false, true, true, NULL, false },
672 { "near", 0, 0, false, true, true, NULL, false },
673 /* We would really like to treat "mips16" and "nomips16" as type
674 attributes, but GCC doesn't provide the hooks we need to support
675 the right conversion rules. As declaration attributes, they affect
676 code generation but don't carry other semantics. */
677 { "mips16", 0, 0, true, false, false, NULL, false },
678 { "nomips16", 0, 0, true, false, false, NULL, false },
679 /* Allow functions to be specified as interrupt handlers */
680 { "interrupt", 0, 0, false, true, true, NULL, false },
681 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
682 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
683 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
684 { NULL, 0, 0, false, false, false, NULL, false }
687 /* A table describing all the processors GCC knows about; see
688 mips-cpus.def for details. */
689 static const struct mips_cpu_info mips_cpu_info_table[] = {
690 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
691 { NAME, CPU, ISA, FLAGS },
692 #include "mips-cpus.def"
696 /* Default costs. If these are used for a processor we should look
697 up the actual costs. */
698 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
699 COSTS_N_INSNS (7), /* fp_mult_sf */ \
700 COSTS_N_INSNS (8), /* fp_mult_df */ \
701 COSTS_N_INSNS (23), /* fp_div_sf */ \
702 COSTS_N_INSNS (36), /* fp_div_df */ \
703 COSTS_N_INSNS (10), /* int_mult_si */ \
704 COSTS_N_INSNS (10), /* int_mult_di */ \
705 COSTS_N_INSNS (69), /* int_div_si */ \
706 COSTS_N_INSNS (69), /* int_div_di */ \
707 2, /* branch_cost */ \
708 4 /* memory_latency */
710 /* Floating-point costs for processors without an FPU. Just assume that
711 all floating-point libcalls are very expensive. */
712 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
713 COSTS_N_INSNS (256), /* fp_mult_sf */ \
714 COSTS_N_INSNS (256), /* fp_mult_df */ \
715 COSTS_N_INSNS (256), /* fp_div_sf */ \
716 COSTS_N_INSNS (256) /* fp_div_df */
718 /* Costs to use when optimizing for size. */
719 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
720 COSTS_N_INSNS (1), /* fp_add */
721 COSTS_N_INSNS (1), /* fp_mult_sf */
722 COSTS_N_INSNS (1), /* fp_mult_df */
723 COSTS_N_INSNS (1), /* fp_div_sf */
724 COSTS_N_INSNS (1), /* fp_div_df */
725 COSTS_N_INSNS (1), /* int_mult_si */
726 COSTS_N_INSNS (1), /* int_mult_di */
727 COSTS_N_INSNS (1), /* int_div_si */
728 COSTS_N_INSNS (1), /* int_div_di */
730 4 /* memory_latency */
733 /* Costs to use when optimizing for speed, indexed by processor. */
734 static const struct mips_rtx_cost_data
735 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
737 COSTS_N_INSNS (2), /* fp_add */
738 COSTS_N_INSNS (4), /* fp_mult_sf */
739 COSTS_N_INSNS (5), /* fp_mult_df */
740 COSTS_N_INSNS (12), /* fp_div_sf */
741 COSTS_N_INSNS (19), /* fp_div_df */
742 COSTS_N_INSNS (12), /* int_mult_si */
743 COSTS_N_INSNS (12), /* int_mult_di */
744 COSTS_N_INSNS (35), /* int_div_si */
745 COSTS_N_INSNS (35), /* int_div_di */
747 4 /* memory_latency */
751 COSTS_N_INSNS (6), /* int_mult_si */
752 COSTS_N_INSNS (6), /* int_mult_di */
753 COSTS_N_INSNS (36), /* int_div_si */
754 COSTS_N_INSNS (36), /* int_div_di */
756 4 /* memory_latency */
760 COSTS_N_INSNS (36), /* int_mult_si */
761 COSTS_N_INSNS (36), /* int_mult_di */
762 COSTS_N_INSNS (37), /* int_div_si */
763 COSTS_N_INSNS (37), /* int_div_di */
765 4 /* memory_latency */
769 COSTS_N_INSNS (4), /* int_mult_si */
770 COSTS_N_INSNS (11), /* int_mult_di */
771 COSTS_N_INSNS (36), /* int_div_si */
772 COSTS_N_INSNS (68), /* int_div_di */
774 4 /* memory_latency */
777 COSTS_N_INSNS (4), /* fp_add */
778 COSTS_N_INSNS (4), /* fp_mult_sf */
779 COSTS_N_INSNS (5), /* fp_mult_df */
780 COSTS_N_INSNS (17), /* fp_div_sf */
781 COSTS_N_INSNS (32), /* fp_div_df */
782 COSTS_N_INSNS (4), /* int_mult_si */
783 COSTS_N_INSNS (11), /* int_mult_di */
784 COSTS_N_INSNS (36), /* int_div_si */
785 COSTS_N_INSNS (68), /* int_div_di */
787 4 /* memory_latency */
790 COSTS_N_INSNS (4), /* fp_add */
791 COSTS_N_INSNS (4), /* fp_mult_sf */
792 COSTS_N_INSNS (5), /* fp_mult_df */
793 COSTS_N_INSNS (17), /* fp_div_sf */
794 COSTS_N_INSNS (32), /* fp_div_df */
795 COSTS_N_INSNS (4), /* int_mult_si */
796 COSTS_N_INSNS (7), /* int_mult_di */
797 COSTS_N_INSNS (42), /* int_div_si */
798 COSTS_N_INSNS (72), /* int_div_di */
800 4 /* memory_latency */
804 COSTS_N_INSNS (5), /* int_mult_si */
805 COSTS_N_INSNS (5), /* int_mult_di */
806 COSTS_N_INSNS (41), /* int_div_si */
807 COSTS_N_INSNS (41), /* int_div_di */
809 4 /* memory_latency */
812 COSTS_N_INSNS (8), /* fp_add */
813 COSTS_N_INSNS (8), /* fp_mult_sf */
814 COSTS_N_INSNS (10), /* fp_mult_df */
815 COSTS_N_INSNS (34), /* fp_div_sf */
816 COSTS_N_INSNS (64), /* fp_div_df */
817 COSTS_N_INSNS (5), /* int_mult_si */
818 COSTS_N_INSNS (5), /* int_mult_di */
819 COSTS_N_INSNS (41), /* int_div_si */
820 COSTS_N_INSNS (41), /* int_div_di */
822 4 /* memory_latency */
825 COSTS_N_INSNS (4), /* fp_add */
826 COSTS_N_INSNS (4), /* fp_mult_sf */
827 COSTS_N_INSNS (5), /* fp_mult_df */
828 COSTS_N_INSNS (17), /* fp_div_sf */
829 COSTS_N_INSNS (32), /* fp_div_df */
830 COSTS_N_INSNS (5), /* int_mult_si */
831 COSTS_N_INSNS (5), /* int_mult_di */
832 COSTS_N_INSNS (41), /* int_div_si */
833 COSTS_N_INSNS (41), /* int_div_di */
835 4 /* memory_latency */
839 COSTS_N_INSNS (5), /* int_mult_si */
840 COSTS_N_INSNS (5), /* int_mult_di */
841 COSTS_N_INSNS (41), /* int_div_si */
842 COSTS_N_INSNS (41), /* int_div_di */
844 4 /* memory_latency */
847 COSTS_N_INSNS (8), /* fp_add */
848 COSTS_N_INSNS (8), /* fp_mult_sf */
849 COSTS_N_INSNS (10), /* fp_mult_df */
850 COSTS_N_INSNS (34), /* fp_div_sf */
851 COSTS_N_INSNS (64), /* fp_div_df */
852 COSTS_N_INSNS (5), /* int_mult_si */
853 COSTS_N_INSNS (5), /* int_mult_di */
854 COSTS_N_INSNS (41), /* int_div_si */
855 COSTS_N_INSNS (41), /* int_div_di */
857 4 /* memory_latency */
860 COSTS_N_INSNS (4), /* fp_add */
861 COSTS_N_INSNS (4), /* fp_mult_sf */
862 COSTS_N_INSNS (5), /* fp_mult_df */
863 COSTS_N_INSNS (17), /* fp_div_sf */
864 COSTS_N_INSNS (32), /* fp_div_df */
865 COSTS_N_INSNS (5), /* int_mult_si */
866 COSTS_N_INSNS (5), /* int_mult_di */
867 COSTS_N_INSNS (41), /* int_div_si */
868 COSTS_N_INSNS (41), /* int_div_di */
870 4 /* memory_latency */
873 COSTS_N_INSNS (6), /* fp_add */
874 COSTS_N_INSNS (6), /* fp_mult_sf */
875 COSTS_N_INSNS (7), /* fp_mult_df */
876 COSTS_N_INSNS (25), /* fp_div_sf */
877 COSTS_N_INSNS (48), /* fp_div_df */
878 COSTS_N_INSNS (5), /* int_mult_si */
879 COSTS_N_INSNS (5), /* int_mult_di */
880 COSTS_N_INSNS (41), /* int_div_si */
881 COSTS_N_INSNS (41), /* int_div_di */
883 4 /* memory_latency */
900 COSTS_N_INSNS (5), /* int_mult_si */
901 COSTS_N_INSNS (5), /* int_mult_di */
902 COSTS_N_INSNS (72), /* int_div_si */
903 COSTS_N_INSNS (72), /* int_div_di */
905 4 /* memory_latency */
910 COSTS_N_INSNS (6), /* int_mult_si */
911 COSTS_N_INSNS (6), /* int_mult_di */
912 COSTS_N_INSNS (18), /* int_div_si */
913 COSTS_N_INSNS (35), /* int_div_di */
915 4 /* memory_latency */
918 COSTS_N_INSNS (2), /* fp_add */
919 COSTS_N_INSNS (4), /* fp_mult_sf */
920 COSTS_N_INSNS (5), /* fp_mult_df */
921 COSTS_N_INSNS (12), /* fp_div_sf */
922 COSTS_N_INSNS (19), /* fp_div_df */
923 COSTS_N_INSNS (2), /* int_mult_si */
924 COSTS_N_INSNS (2), /* int_mult_di */
925 COSTS_N_INSNS (35), /* int_div_si */
926 COSTS_N_INSNS (35), /* int_div_di */
928 4 /* memory_latency */
931 COSTS_N_INSNS (3), /* fp_add */
932 COSTS_N_INSNS (5), /* fp_mult_sf */
933 COSTS_N_INSNS (6), /* fp_mult_df */
934 COSTS_N_INSNS (15), /* fp_div_sf */
935 COSTS_N_INSNS (16), /* fp_div_df */
936 COSTS_N_INSNS (17), /* int_mult_si */
937 COSTS_N_INSNS (17), /* int_mult_di */
938 COSTS_N_INSNS (38), /* int_div_si */
939 COSTS_N_INSNS (38), /* int_div_di */
941 6 /* memory_latency */
944 COSTS_N_INSNS (6), /* fp_add */
945 COSTS_N_INSNS (7), /* fp_mult_sf */
946 COSTS_N_INSNS (8), /* fp_mult_df */
947 COSTS_N_INSNS (23), /* fp_div_sf */
948 COSTS_N_INSNS (36), /* fp_div_df */
949 COSTS_N_INSNS (10), /* int_mult_si */
950 COSTS_N_INSNS (10), /* int_mult_di */
951 COSTS_N_INSNS (69), /* int_div_si */
952 COSTS_N_INSNS (69), /* int_div_di */
954 6 /* memory_latency */
966 /* The only costs that appear to be updated here are
967 integer multiplication. */
969 COSTS_N_INSNS (4), /* int_mult_si */
970 COSTS_N_INSNS (6), /* int_mult_di */
971 COSTS_N_INSNS (69), /* int_div_si */
972 COSTS_N_INSNS (69), /* int_div_di */
974 4 /* memory_latency */
989 COSTS_N_INSNS (6), /* fp_add */
990 COSTS_N_INSNS (4), /* fp_mult_sf */
991 COSTS_N_INSNS (5), /* fp_mult_df */
992 COSTS_N_INSNS (23), /* fp_div_sf */
993 COSTS_N_INSNS (36), /* fp_div_df */
994 COSTS_N_INSNS (5), /* int_mult_si */
995 COSTS_N_INSNS (5), /* int_mult_di */
996 COSTS_N_INSNS (36), /* int_div_si */
997 COSTS_N_INSNS (36), /* int_div_di */
999 4 /* memory_latency */
1002 COSTS_N_INSNS (6), /* fp_add */
1003 COSTS_N_INSNS (5), /* fp_mult_sf */
1004 COSTS_N_INSNS (6), /* fp_mult_df */
1005 COSTS_N_INSNS (30), /* fp_div_sf */
1006 COSTS_N_INSNS (59), /* fp_div_df */
1007 COSTS_N_INSNS (3), /* int_mult_si */
1008 COSTS_N_INSNS (4), /* int_mult_di */
1009 COSTS_N_INSNS (42), /* int_div_si */
1010 COSTS_N_INSNS (74), /* int_div_di */
1011 1, /* branch_cost */
1012 4 /* memory_latency */
1015 COSTS_N_INSNS (6), /* fp_add */
1016 COSTS_N_INSNS (5), /* fp_mult_sf */
1017 COSTS_N_INSNS (6), /* fp_mult_df */
1018 COSTS_N_INSNS (30), /* fp_div_sf */
1019 COSTS_N_INSNS (59), /* fp_div_df */
1020 COSTS_N_INSNS (5), /* int_mult_si */
1021 COSTS_N_INSNS (9), /* int_mult_di */
1022 COSTS_N_INSNS (42), /* int_div_si */
1023 COSTS_N_INSNS (74), /* int_div_di */
1024 1, /* branch_cost */
1025 4 /* memory_latency */
1028 /* The only costs that are changed here are
1029 integer multiplication. */
1030 COSTS_N_INSNS (6), /* fp_add */
1031 COSTS_N_INSNS (7), /* fp_mult_sf */
1032 COSTS_N_INSNS (8), /* fp_mult_df */
1033 COSTS_N_INSNS (23), /* fp_div_sf */
1034 COSTS_N_INSNS (36), /* fp_div_df */
1035 COSTS_N_INSNS (5), /* int_mult_si */
1036 COSTS_N_INSNS (9), /* int_mult_di */
1037 COSTS_N_INSNS (69), /* int_div_si */
1038 COSTS_N_INSNS (69), /* int_div_di */
1039 1, /* branch_cost */
1040 4 /* memory_latency */
1046 /* The only costs that are changed here are
1047 integer multiplication. */
1048 COSTS_N_INSNS (6), /* fp_add */
1049 COSTS_N_INSNS (7), /* fp_mult_sf */
1050 COSTS_N_INSNS (8), /* fp_mult_df */
1051 COSTS_N_INSNS (23), /* fp_div_sf */
1052 COSTS_N_INSNS (36), /* fp_div_df */
1053 COSTS_N_INSNS (3), /* int_mult_si */
1054 COSTS_N_INSNS (8), /* int_mult_di */
1055 COSTS_N_INSNS (69), /* int_div_si */
1056 COSTS_N_INSNS (69), /* int_div_di */
1057 1, /* branch_cost */
1058 4 /* memory_latency */
1061 COSTS_N_INSNS (2), /* fp_add */
1062 COSTS_N_INSNS (2), /* fp_mult_sf */
1063 COSTS_N_INSNS (2), /* fp_mult_df */
1064 COSTS_N_INSNS (12), /* fp_div_sf */
1065 COSTS_N_INSNS (19), /* fp_div_df */
1066 COSTS_N_INSNS (5), /* int_mult_si */
1067 COSTS_N_INSNS (9), /* int_mult_di */
1068 COSTS_N_INSNS (34), /* int_div_si */
1069 COSTS_N_INSNS (66), /* int_div_di */
1070 1, /* branch_cost */
1071 4 /* memory_latency */
1074 /* These costs are the same as the SB-1A below. */
1075 COSTS_N_INSNS (4), /* fp_add */
1076 COSTS_N_INSNS (4), /* fp_mult_sf */
1077 COSTS_N_INSNS (4), /* fp_mult_df */
1078 COSTS_N_INSNS (24), /* fp_div_sf */
1079 COSTS_N_INSNS (32), /* fp_div_df */
1080 COSTS_N_INSNS (3), /* int_mult_si */
1081 COSTS_N_INSNS (4), /* int_mult_di */
1082 COSTS_N_INSNS (36), /* int_div_si */
1083 COSTS_N_INSNS (68), /* int_div_di */
1084 1, /* branch_cost */
1085 4 /* memory_latency */
1088 /* These costs are the same as the SB-1 above. */
1089 COSTS_N_INSNS (4), /* fp_add */
1090 COSTS_N_INSNS (4), /* fp_mult_sf */
1091 COSTS_N_INSNS (4), /* fp_mult_df */
1092 COSTS_N_INSNS (24), /* fp_div_sf */
1093 COSTS_N_INSNS (32), /* fp_div_df */
1094 COSTS_N_INSNS (3), /* int_mult_si */
1095 COSTS_N_INSNS (4), /* int_mult_di */
1096 COSTS_N_INSNS (36), /* int_div_si */
1097 COSTS_N_INSNS (68), /* int_div_di */
1098 1, /* branch_cost */
1099 4 /* memory_latency */
1106 COSTS_N_INSNS (8), /* int_mult_si */
1107 COSTS_N_INSNS (8), /* int_mult_di */
1108 COSTS_N_INSNS (72), /* int_div_si */
1109 COSTS_N_INSNS (72), /* int_div_di */
1110 1, /* branch_cost */
1111 4 /* memory_latency */
1114 /* These costs are the same as 5KF above. */
1115 COSTS_N_INSNS (4), /* fp_add */
1116 COSTS_N_INSNS (4), /* fp_mult_sf */
1117 COSTS_N_INSNS (5), /* fp_mult_df */
1118 COSTS_N_INSNS (17), /* fp_div_sf */
1119 COSTS_N_INSNS (32), /* fp_div_df */
1120 COSTS_N_INSNS (4), /* int_mult_si */
1121 COSTS_N_INSNS (11), /* int_mult_di */
1122 COSTS_N_INSNS (36), /* int_div_si */
1123 COSTS_N_INSNS (68), /* int_div_di */
1124 1, /* branch_cost */
1125 4 /* memory_latency */
1129 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1130 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1132 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1134 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1135 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1136 struct GTY (()) mflip_mips16_entry {
1140 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1142 /* Hash table callbacks for mflip_mips16_htab. */
1145 mflip_mips16_htab_hash (const void *entry)
1147 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1151 mflip_mips16_htab_eq (const void *entry, const void *name)
1153 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1154 (const char *) name) == 0;
1157 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1158 mode, false if it should next add an attribute for the opposite mode. */
1159 static GTY(()) bool mips16_flipper;
1161 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1162 for -mflip-mips16. Return true if it should use "mips16" and false if
1163 it should use "nomips16". */
1166 mflip_mips16_use_mips16_p (tree decl)
1168 struct mflip_mips16_entry *entry;
1173 /* Use the opposite of the command-line setting for anonymous decls. */
1174 if (!DECL_NAME (decl))
1175 return !mips_base_mips16;
1177 if (!mflip_mips16_htab)
1178 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1179 mflip_mips16_htab_eq, NULL);
1181 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1182 hash = htab_hash_string (name);
1183 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1184 entry = (struct mflip_mips16_entry *) *slot;
1187 mips16_flipper = !mips16_flipper;
1188 entry = ggc_alloc_mflip_mips16_entry ();
1190 entry->mips16_p = mips16_flipper ? !mips_base_mips16 : mips_base_mips16;
1193 return entry->mips16_p;
1196 /* Predicates to test for presence of "near" and "far"/"long_call"
1197 attributes on the given TYPE. */
1200 mips_near_type_p (const_tree type)
1202 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1206 mips_far_type_p (const_tree type)
1208 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1209 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1212 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1215 mips_mips16_decl_p (const_tree decl)
1217 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl)) != NULL;
1221 mips_nomips16_decl_p (const_tree decl)
1223 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
1226 /* Check if the interrupt attribute is set for a function. */
1229 mips_interrupt_type_p (tree type)
1231 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1234 /* Check if the attribute to use shadow register set is set for a function. */
1237 mips_use_shadow_register_set_p (tree type)
1239 return lookup_attribute ("use_shadow_register_set",
1240 TYPE_ATTRIBUTES (type)) != NULL;
1243 /* Check if the attribute to keep interrupts masked is set for a function. */
1246 mips_keep_interrupts_masked_p (tree type)
1248 return lookup_attribute ("keep_interrupts_masked",
1249 TYPE_ATTRIBUTES (type)) != NULL;
1252 /* Check if the attribute to use debug exception return is set for
1256 mips_use_debug_exception_return_p (tree type)
1258 return lookup_attribute ("use_debug_exception_return",
1259 TYPE_ATTRIBUTES (type)) != NULL;
1262 /* Return true if function DECL is a MIPS16 function. Return the ambient
1263 setting if DECL is null. */
1266 mips_use_mips16_mode_p (tree decl)
1270 /* Nested functions must use the same frame pointer as their
1271 parent and must therefore use the same ISA mode. */
1272 tree parent = decl_function_context (decl);
1275 if (mips_mips16_decl_p (decl))
1277 if (mips_nomips16_decl_p (decl))
1280 return mips_base_mips16;
1283 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1286 mips_comp_type_attributes (const_tree type1, const_tree type2)
1288 /* Disallow mixed near/far attributes. */
1289 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1291 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1296 /* Implement TARGET_INSERT_ATTRIBUTES. */
1299 mips_insert_attributes (tree decl, tree *attributes)
1302 bool mips16_p, nomips16_p;
1304 /* Check for "mips16" and "nomips16" attributes. */
1305 mips16_p = lookup_attribute ("mips16", *attributes) != NULL;
1306 nomips16_p = lookup_attribute ("nomips16", *attributes) != NULL;
1307 if (TREE_CODE (decl) != FUNCTION_DECL)
1310 error ("%qs attribute only applies to functions", "mips16");
1312 error ("%qs attribute only applies to functions", "nomips16");
1316 mips16_p |= mips_mips16_decl_p (decl);
1317 nomips16_p |= mips_nomips16_decl_p (decl);
1318 if (mips16_p || nomips16_p)
1320 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1321 if (mips16_p && nomips16_p)
1322 error ("%qE cannot have both %<mips16%> and "
1323 "%<nomips16%> attributes",
1326 else if (TARGET_FLIP_MIPS16 && !DECL_ARTIFICIAL (decl))
1328 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1329 "mips16" attribute, arbitrarily pick one. We must pick the same
1330 setting for duplicate declarations of a function. */
1331 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1332 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1337 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1340 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1342 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1343 if (mips_mips16_decl_p (olddecl) != mips_mips16_decl_p (newdecl))
1344 error ("%qE redeclared with conflicting %qs attributes",
1345 DECL_NAME (newdecl), "mips16");
1346 if (mips_nomips16_decl_p (olddecl) != mips_nomips16_decl_p (newdecl))
1347 error ("%qE redeclared with conflicting %qs attributes",
1348 DECL_NAME (newdecl), "nomips16");
1350 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1351 DECL_ATTRIBUTES (newdecl));
1354 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1355 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1358 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1360 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1362 *base_ptr = XEXP (x, 0);
1363 *offset_ptr = INTVAL (XEXP (x, 1));
1372 static unsigned int mips_build_integer (struct mips_integer_op *,
1373 unsigned HOST_WIDE_INT);
1375 /* A subroutine of mips_build_integer, with the same interface.
1376 Assume that the final action in the sequence should be a left shift. */
1379 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1381 unsigned int i, shift;
1383 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1384 since signed numbers are easier to load than unsigned ones. */
1386 while ((value & 1) == 0)
1387 value /= 2, shift++;
1389 i = mips_build_integer (codes, value);
1390 codes[i].code = ASHIFT;
1391 codes[i].value = shift;
1395 /* As for mips_build_shift, but assume that the final action will be
1396 an IOR or PLUS operation. */
1399 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1401 unsigned HOST_WIDE_INT high;
1404 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1405 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1407 /* The constant is too complex to load with a simple LUI/ORI pair,
1408 so we want to give the recursive call as many trailing zeros as
1409 possible. In this case, we know bit 16 is set and that the
1410 low 16 bits form a negative number. If we subtract that number
1411 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1412 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1413 codes[i].code = PLUS;
1414 codes[i].value = CONST_LOW_PART (value);
1418 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1419 bits gives a value with at least 17 trailing zeros. */
1420 i = mips_build_integer (codes, high);
1421 codes[i].code = IOR;
1422 codes[i].value = value & 0xffff;
1427 /* Fill CODES with a sequence of rtl operations to load VALUE.
1428 Return the number of operations needed. */
1431 mips_build_integer (struct mips_integer_op *codes,
1432 unsigned HOST_WIDE_INT value)
1434 if (SMALL_OPERAND (value)
1435 || SMALL_OPERAND_UNSIGNED (value)
1436 || LUI_OPERAND (value))
1438 /* The value can be loaded with a single instruction. */
1439 codes[0].code = UNKNOWN;
1440 codes[0].value = value;
1443 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1445 /* Either the constant is a simple LUI/ORI combination or its
1446 lowest bit is set. We don't want to shift in this case. */
1447 return mips_build_lower (codes, value);
1449 else if ((value & 0xffff) == 0)
1451 /* The constant will need at least three actions. The lowest
1452 16 bits are clear, so the final action will be a shift. */
1453 return mips_build_shift (codes, value);
1457 /* The final action could be a shift, add or inclusive OR.
1458 Rather than use a complex condition to select the best
1459 approach, try both mips_build_shift and mips_build_lower
1460 and pick the one that gives the shortest sequence.
1461 Note that this case is only used once per constant. */
1462 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1463 unsigned int cost, alt_cost;
1465 cost = mips_build_shift (codes, value);
1466 alt_cost = mips_build_lower (alt_codes, value);
1467 if (alt_cost < cost)
1469 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1476 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1479 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1481 return mips_const_insns (x) > 0;
1484 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1487 mips16_stub_function (const char *name)
1491 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1492 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1496 /* Return true if symbols of type TYPE require a GOT access. */
1499 mips_got_symbol_type_p (enum mips_symbol_type type)
1503 case SYMBOL_GOT_PAGE_OFST:
1504 case SYMBOL_GOT_DISP:
1512 /* Return true if X is a thread-local symbol. */
1515 mips_tls_symbol_p (rtx x)
1517 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1520 /* Return true if SYMBOL_REF X is associated with a global symbol
1521 (in the STB_GLOBAL sense). */
1524 mips_global_symbol_p (const_rtx x)
1526 const_tree decl = SYMBOL_REF_DECL (x);
1529 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1531 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1532 or weak symbols. Relocations in the object file will be against
1533 the target symbol, so it's that symbol's binding that matters here. */
1534 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1537 /* Return true if function X is a libgcc MIPS16 stub function. */
1540 mips16_stub_function_p (const_rtx x)
1542 return (GET_CODE (x) == SYMBOL_REF
1543 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1546 /* Return true if function X is a locally-defined and locally-binding
1550 mips16_local_function_p (const_rtx x)
1552 return (GET_CODE (x) == SYMBOL_REF
1553 && SYMBOL_REF_LOCAL_P (x)
1554 && !SYMBOL_REF_EXTERNAL_P (x)
1555 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x)));
1558 /* Return true if SYMBOL_REF X binds locally. */
1561 mips_symbol_binds_local_p (const_rtx x)
1563 return (SYMBOL_REF_DECL (x)
1564 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1565 : SYMBOL_REF_LOCAL_P (x));
1568 /* Return true if rtx constants of mode MODE should be put into a small
1572 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1574 return (!TARGET_EMBEDDED_DATA
1575 && TARGET_LOCAL_SDATA
1576 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1579 /* Return true if X should not be moved directly into register $25.
1580 We need this because many versions of GAS will treat "la $25,foo" as
1581 part of a call sequence and so allow a global "foo" to be lazily bound. */
1584 mips_dangerous_for_la25_p (rtx x)
1586 return (!TARGET_EXPLICIT_RELOCS
1588 && GET_CODE (x) == SYMBOL_REF
1589 && mips_global_symbol_p (x));
1592 /* Return true if calls to X might need $25 to be valid on entry. */
1595 mips_use_pic_fn_addr_reg_p (const_rtx x)
1597 if (!TARGET_USE_PIC_FN_ADDR_REG)
1600 /* MIPS16 stub functions are guaranteed not to use $25. */
1601 if (mips16_stub_function_p (x))
1604 if (GET_CODE (x) == SYMBOL_REF)
1606 /* If PLTs and copy relocations are available, the static linker
1607 will make sure that $25 is valid on entry to the target function. */
1608 if (TARGET_ABICALLS_PIC0)
1611 /* Locally-defined functions use absolute accesses to set up
1612 the global pointer. */
1613 if (TARGET_ABSOLUTE_ABICALLS
1614 && mips_symbol_binds_local_p (x)
1615 && !SYMBOL_REF_EXTERNAL_P (x))
1622 /* Return the method that should be used to access SYMBOL_REF or
1623 LABEL_REF X in context CONTEXT. */
1625 static enum mips_symbol_type
1626 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1629 return SYMBOL_GOT_DISP;
1631 if (GET_CODE (x) == LABEL_REF)
1633 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1634 code and if we know that the label is in the current function's
1635 text section. LABEL_REFs are used for jump tables as well as
1636 text labels, so we must check whether jump tables live in the
1638 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1639 && !LABEL_REF_NONLOCAL_P (x))
1640 return SYMBOL_PC_RELATIVE;
1642 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1643 return SYMBOL_GOT_PAGE_OFST;
1645 return SYMBOL_ABSOLUTE;
1648 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1650 if (SYMBOL_REF_TLS_MODEL (x))
1653 if (CONSTANT_POOL_ADDRESS_P (x))
1655 if (TARGET_MIPS16_TEXT_LOADS)
1656 return SYMBOL_PC_RELATIVE;
1658 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1659 return SYMBOL_PC_RELATIVE;
1661 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1662 return SYMBOL_GP_RELATIVE;
1665 /* Do not use small-data accesses for weak symbols; they may end up
1667 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1668 return SYMBOL_GP_RELATIVE;
1670 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1672 if (TARGET_ABICALLS_PIC2
1673 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1675 /* There are three cases to consider:
1677 - o32 PIC (either with or without explicit relocs)
1678 - n32/n64 PIC without explicit relocs
1679 - n32/n64 PIC with explicit relocs
1681 In the first case, both local and global accesses will use an
1682 R_MIPS_GOT16 relocation. We must correctly predict which of
1683 the two semantics (local or global) the assembler and linker
1684 will apply. The choice depends on the symbol's binding rather
1685 than its visibility.
1687 In the second case, the assembler will not use R_MIPS_GOT16
1688 relocations, but it chooses between local and global accesses
1689 in the same way as for o32 PIC.
1691 In the third case we have more freedom since both forms of
1692 access will work for any kind of symbol. However, there seems
1693 little point in doing things differently. */
1694 if (mips_global_symbol_p (x))
1695 return SYMBOL_GOT_DISP;
1697 return SYMBOL_GOT_PAGE_OFST;
1700 return SYMBOL_ABSOLUTE;
1703 /* Classify the base of symbolic expression X, given that X appears in
1706 static enum mips_symbol_type
1707 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1711 split_const (x, &x, &offset);
1712 if (UNSPEC_ADDRESS_P (x))
1713 return UNSPEC_ADDRESS_TYPE (x);
1715 return mips_classify_symbol (x, context);
1718 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1719 is the alignment in bytes of SYMBOL_REF X. */
1722 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1724 HOST_WIDE_INT align;
1726 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1727 return IN_RANGE (offset, 0, align - 1);
1730 /* Return true if X is a symbolic constant that can be used in context
1731 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1734 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1735 enum mips_symbol_type *symbol_type)
1739 split_const (x, &x, &offset);
1740 if (UNSPEC_ADDRESS_P (x))
1742 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1743 x = UNSPEC_ADDRESS (x);
1745 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1747 *symbol_type = mips_classify_symbol (x, context);
1748 if (*symbol_type == SYMBOL_TLS)
1754 if (offset == const0_rtx)
1757 /* Check whether a nonzero offset is valid for the underlying
1759 switch (*symbol_type)
1761 case SYMBOL_ABSOLUTE:
1762 case SYMBOL_64_HIGH:
1765 /* If the target has 64-bit pointers and the object file only
1766 supports 32-bit symbols, the values of those symbols will be
1767 sign-extended. In this case we can't allow an arbitrary offset
1768 in case the 32-bit value X + OFFSET has a different sign from X. */
1769 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
1770 return offset_within_block_p (x, INTVAL (offset));
1772 /* In other cases the relocations can handle any offset. */
1775 case SYMBOL_PC_RELATIVE:
1776 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1777 In this case, we no longer have access to the underlying constant,
1778 but the original symbol-based access was known to be valid. */
1779 if (GET_CODE (x) == LABEL_REF)
1784 case SYMBOL_GP_RELATIVE:
1785 /* Make sure that the offset refers to something within the
1786 same object block. This should guarantee that the final
1787 PC- or GP-relative offset is within the 16-bit limit. */
1788 return offset_within_block_p (x, INTVAL (offset));
1790 case SYMBOL_GOT_PAGE_OFST:
1791 case SYMBOL_GOTOFF_PAGE:
1792 /* If the symbol is global, the GOT entry will contain the symbol's
1793 address, and we will apply a 16-bit offset after loading it.
1794 If the symbol is local, the linker should provide enough local
1795 GOT entries for a 16-bit offset, but larger offsets may lead
1797 return SMALL_INT (offset);
1801 /* There is no carry between the HI and LO REL relocations, so the
1802 offset is only valid if we know it won't lead to such a carry. */
1803 return mips_offset_within_alignment_p (x, INTVAL (offset));
1805 case SYMBOL_GOT_DISP:
1806 case SYMBOL_GOTOFF_DISP:
1807 case SYMBOL_GOTOFF_CALL:
1808 case SYMBOL_GOTOFF_LOADGP:
1811 case SYMBOL_GOTTPREL:
1819 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1820 single instruction. We rely on the fact that, in the worst case,
1821 all instructions involved in a MIPS16 address calculation are usually
1825 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
1827 if (mips_use_pcrel_pool_p[(int) type])
1829 if (mode == MAX_MACHINE_MODE)
1830 /* LEAs will be converted into constant-pool references by
1832 type = SYMBOL_PC_RELATIVE;
1834 /* The constant must be loaded and then dereferenced. */
1840 case SYMBOL_ABSOLUTE:
1841 /* When using 64-bit symbols, we need 5 preparatory instructions,
1844 lui $at,%highest(symbol)
1845 daddiu $at,$at,%higher(symbol)
1847 daddiu $at,$at,%hi(symbol)
1850 The final address is then $at + %lo(symbol). With 32-bit
1851 symbols we just need a preparatory LUI for normal mode and
1852 a preparatory LI and SLL for MIPS16. */
1853 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
1855 case SYMBOL_GP_RELATIVE:
1856 /* Treat GP-relative accesses as taking a single instruction on
1857 MIPS16 too; the copy of $gp can often be shared. */
1860 case SYMBOL_PC_RELATIVE:
1861 /* PC-relative constants can be only be used with ADDIUPC,
1862 DADDIUPC, LWPC and LDPC. */
1863 if (mode == MAX_MACHINE_MODE
1864 || GET_MODE_SIZE (mode) == 4
1865 || GET_MODE_SIZE (mode) == 8)
1868 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1871 case SYMBOL_GOT_DISP:
1872 /* The constant will have to be loaded from the GOT before it
1873 is used in an address. */
1874 if (mode != MAX_MACHINE_MODE)
1879 case SYMBOL_GOT_PAGE_OFST:
1880 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1881 local/global classification is accurate. The worst cases are:
1883 (1) For local symbols when generating o32 or o64 code. The assembler
1889 ...and the final address will be $at + %lo(symbol).
1891 (2) For global symbols when -mxgot. The assembler will use:
1893 lui $at,%got_hi(symbol)
1896 ...and the final address will be $at + %got_lo(symbol). */
1899 case SYMBOL_GOTOFF_PAGE:
1900 case SYMBOL_GOTOFF_DISP:
1901 case SYMBOL_GOTOFF_CALL:
1902 case SYMBOL_GOTOFF_LOADGP:
1903 case SYMBOL_64_HIGH:
1909 case SYMBOL_GOTTPREL:
1912 /* A 16-bit constant formed by a single relocation, or a 32-bit
1913 constant formed from a high 16-bit relocation and a low 16-bit
1914 relocation. Use mips_split_p to determine which. 32-bit
1915 constants need an "lui; addiu" sequence for normal mode and
1916 an "li; sll; addiu" sequence for MIPS16 mode. */
1917 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
1920 /* We don't treat a bare TLS symbol as a constant. */
1926 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1927 to load symbols of type TYPE into a register. Return 0 if the given
1928 type of symbol cannot be used as an immediate operand.
1930 Otherwise, return the number of instructions needed to load or store
1931 values of mode MODE to or from addresses of type TYPE. Return 0 if
1932 the given type of symbol is not valid in addresses.
1934 In both cases, treat extended MIPS16 instructions as two instructions. */
1937 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
1939 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
1942 /* A for_each_rtx callback. Stop the search if *X references a
1943 thread-local symbol. */
1946 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1948 return mips_tls_symbol_p (*x);
1951 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1954 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
1956 enum mips_symbol_type type;
1959 /* There is no assembler syntax for expressing an address-sized
1961 if (GET_CODE (x) == HIGH)
1964 /* As an optimization, reject constants that mips_legitimize_move
1967 Suppose we have a multi-instruction sequence that loads constant C
1968 into register R. If R does not get allocated a hard register, and
1969 R is used in an operand that allows both registers and memory
1970 references, reload will consider forcing C into memory and using
1971 one of the instruction's memory alternatives. Returning false
1972 here will force it to use an input reload instead. */
1973 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
1976 split_const (x, &base, &offset);
1977 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
1979 /* See whether we explicitly want these symbols in the pool. */
1980 if (mips_use_pcrel_pool_p[(int) type])
1983 /* The same optimization as for CONST_INT. */
1984 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
1987 /* If MIPS16 constant pools live in the text section, they should
1988 not refer to anything that might need run-time relocation. */
1989 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
1993 /* TLS symbols must be computed by mips_legitimize_move. */
1994 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2000 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2001 constants when we're using a per-function constant pool. */
2004 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2005 const_rtx x ATTRIBUTE_UNUSED)
2007 return !TARGET_MIPS16_PCREL_LOADS;
2010 /* Return true if register REGNO is a valid base register for mode MODE.
2011 STRICT_P is true if REG_OK_STRICT is in effect. */
2014 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2017 if (!HARD_REGISTER_NUM_P (regno))
2021 regno = reg_renumber[regno];
2024 /* These fake registers will be eliminated to either the stack or
2025 hard frame pointer, both of which are usually valid base registers.
2026 Reload deals with the cases where the eliminated form isn't valid. */
2027 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2030 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2031 values, nothing smaller. There are two problems here:
2033 (a) Instantiating virtual registers can introduce new uses of the
2034 stack pointer. If these virtual registers are valid addresses,
2035 the stack pointer should be too.
2037 (b) Most uses of the stack pointer are not made explicit until
2038 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2039 We don't know until that stage whether we'll be eliminating to the
2040 stack pointer (which needs the restriction) or the hard frame
2041 pointer (which doesn't).
2043 All in all, it seems more consistent to only enforce this restriction
2044 during and after reload. */
2045 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2046 return !strict_p || GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2048 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2051 /* Return true if X is a valid base register for mode MODE.
2052 STRICT_P is true if REG_OK_STRICT is in effect. */
2055 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2057 if (!strict_p && GET_CODE (x) == SUBREG)
2061 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2064 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2065 can address a value of mode MODE. */
2068 mips_valid_offset_p (rtx x, enum machine_mode mode)
2070 /* Check that X is a signed 16-bit number. */
2071 if (!const_arith_operand (x, Pmode))
2074 /* We may need to split multiword moves, so make sure that every word
2076 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2077 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2083 /* Return true if a LO_SUM can address a value of mode MODE when the
2084 LO_SUM symbol has type SYMBOL_TYPE. */
2087 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2089 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2091 if (mips_symbol_insns (symbol_type, mode) == 0)
2094 /* Check that there is a known low-part relocation. */
2095 if (mips_lo_relocs[symbol_type] == NULL)
2098 /* We may need to split multiword moves, so make sure that each word
2099 can be accessed without inducing a carry. This is mainly needed
2100 for o64, which has historically only guaranteed 64-bit alignment
2101 for 128-bit types. */
2102 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2103 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2109 /* Return true if X is a valid address for machine mode MODE. If it is,
2110 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2114 mips_classify_address (struct mips_address_info *info, rtx x,
2115 enum machine_mode mode, bool strict_p)
2117 switch (GET_CODE (x))
2121 info->type = ADDRESS_REG;
2123 info->offset = const0_rtx;
2124 return mips_valid_base_register_p (info->reg, mode, strict_p);
2127 info->type = ADDRESS_REG;
2128 info->reg = XEXP (x, 0);
2129 info->offset = XEXP (x, 1);
2130 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2131 && mips_valid_offset_p (info->offset, mode));
2134 info->type = ADDRESS_LO_SUM;
2135 info->reg = XEXP (x, 0);
2136 info->offset = XEXP (x, 1);
2137 /* We have to trust the creator of the LO_SUM to do something vaguely
2138 sane. Target-independent code that creates a LO_SUM should also
2139 create and verify the matching HIGH. Target-independent code that
2140 adds an offset to a LO_SUM must prove that the offset will not
2141 induce a carry. Failure to do either of these things would be
2142 a bug, and we are not required to check for it here. The MIPS
2143 backend itself should only create LO_SUMs for valid symbolic
2144 constants, with the high part being either a HIGH or a copy
2147 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2148 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2149 && mips_valid_lo_sum_p (info->symbol_type, mode));
2152 /* Small-integer addresses don't occur very often, but they
2153 are legitimate if $0 is a valid base register. */
2154 info->type = ADDRESS_CONST_INT;
2155 return !TARGET_MIPS16 && SMALL_INT (x);
2160 info->type = ADDRESS_SYMBOLIC;
2161 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2163 && mips_symbol_insns (info->symbol_type, mode) > 0
2164 && !mips_split_p[info->symbol_type]);
2171 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2174 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2176 struct mips_address_info addr;
2178 return mips_classify_address (&addr, x, mode, strict_p);
2181 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2184 mips_stack_address_p (rtx x, enum machine_mode mode)
2186 struct mips_address_info addr;
2188 return (mips_classify_address (&addr, x, mode, false)
2189 && addr.type == ADDRESS_REG
2190 && addr.reg == stack_pointer_rtx);
2193 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2194 address instruction. Note that such addresses are not considered
2195 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2196 is so restricted. */
2199 mips_lwxs_address_p (rtx addr)
2202 && GET_CODE (addr) == PLUS
2203 && REG_P (XEXP (addr, 1)))
2205 rtx offset = XEXP (addr, 0);
2206 if (GET_CODE (offset) == MULT
2207 && REG_P (XEXP (offset, 0))
2208 && CONST_INT_P (XEXP (offset, 1))
2209 && INTVAL (XEXP (offset, 1)) == 4)
2215 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2216 indexed address instruction. Note that such addresses are
2217 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2218 sense, because their use is so restricted. */
2221 mips_lx_address_p (rtx addr, enum machine_mode mode)
2223 if (GET_CODE (addr) != PLUS
2224 || !REG_P (XEXP (addr, 0))
2225 || !REG_P (XEXP (addr, 1)))
2227 if (ISA_HAS_LBX && mode == QImode)
2229 if (ISA_HAS_LHX && mode == HImode)
2231 if (ISA_HAS_LWX && mode == SImode)
2233 if (ISA_HAS_LDX && mode == DImode)
2238 /* Return true if a value at OFFSET bytes from base register BASE can be
2239 accessed using an unextended MIPS16 instruction. MODE is the mode of
2242 Usually the offset in an unextended instruction is a 5-bit field.
2243 The offset is unsigned and shifted left once for LH and SH, twice
2244 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2245 an 8-bit immediate field that's shifted left twice. */
2248 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2249 unsigned HOST_WIDE_INT offset)
2251 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2253 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2254 return offset < 256U * GET_MODE_SIZE (mode);
2255 return offset < 32U * GET_MODE_SIZE (mode);
2260 /* Return the number of instructions needed to load or store a value
2261 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2262 Assume that multiword moves may need to be split into word moves
2263 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2266 For MIPS16 code, count extended instructions as two instructions. */
2269 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2271 struct mips_address_info addr;
2274 /* BLKmode is used for single unaligned loads and stores and should
2275 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2276 meaningless, so we have to single it out as a special case one way
2278 if (mode != BLKmode && might_split_p)
2279 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2283 if (mips_classify_address (&addr, x, mode, false))
2288 && !mips16_unextended_reference_p (mode, addr.reg,
2289 UINTVAL (addr.offset)))
2293 case ADDRESS_LO_SUM:
2294 return TARGET_MIPS16 ? factor * 2 : factor;
2296 case ADDRESS_CONST_INT:
2299 case ADDRESS_SYMBOLIC:
2300 return factor * mips_symbol_insns (addr.symbol_type, mode);
2305 /* Return the number of instructions needed to load constant X.
2306 Return 0 if X isn't a valid constant. */
2309 mips_const_insns (rtx x)
2311 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2312 enum mips_symbol_type symbol_type;
2315 switch (GET_CODE (x))
2318 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2320 || !mips_split_p[symbol_type])
2323 /* This is simply an LUI for normal mode. It is an extended
2324 LI followed by an extended SLL for MIPS16. */
2325 return TARGET_MIPS16 ? 4 : 1;
2329 /* Unsigned 8-bit constants can be loaded using an unextended
2330 LI instruction. Unsigned 16-bit constants can be loaded
2331 using an extended LI. Negative constants must be loaded
2332 using LI and then negated. */
2333 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2334 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2335 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2336 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2339 return mips_build_integer (codes, INTVAL (x));
2343 /* Allow zeros for normal mode, where we can use $0. */
2344 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2350 /* See if we can refer to X directly. */
2351 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2352 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2354 /* Otherwise try splitting the constant into a base and offset.
2355 If the offset is a 16-bit value, we can load the base address
2356 into a register and then use (D)ADDIU to add in the offset.
2357 If the offset is larger, we can load the base and offset
2358 into separate registers and add them together with (D)ADDU.
2359 However, the latter is only possible before reload; during
2360 and after reload, we must have the option of forcing the
2361 constant into the pool instead. */
2362 split_const (x, &x, &offset);
2365 int n = mips_const_insns (x);
2368 if (SMALL_INT (offset))
2370 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2371 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2378 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2386 /* X is a doubleword constant that can be handled by splitting it into
2387 two words and loading each word separately. Return the number of
2388 instructions required to do this. */
2391 mips_split_const_insns (rtx x)
2393 unsigned int low, high;
2395 low = mips_const_insns (mips_subword (x, false));
2396 high = mips_const_insns (mips_subword (x, true));
2397 gcc_assert (low > 0 && high > 0);
2401 /* Return the number of instructions needed to implement INSN,
2402 given that it loads from or stores to MEM. Count extended
2403 MIPS16 instructions as two instructions. */
2406 mips_load_store_insns (rtx mem, rtx insn)
2408 enum machine_mode mode;
2412 gcc_assert (MEM_P (mem));
2413 mode = GET_MODE (mem);
2415 /* Try to prove that INSN does not need to be split. */
2416 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
2419 set = single_set (insn);
2420 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
2421 might_split_p = false;
2424 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2427 /* Return the number of instructions needed for an integer division. */
2430 mips_idiv_insns (void)
2435 if (TARGET_CHECK_ZERO_DIV)
2437 if (GENERATE_DIVIDE_TRAPS)
2443 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2448 /* Emit a move from SRC to DEST. Assume that the move expanders can
2449 handle all moves if !can_create_pseudo_p (). The distinction is
2450 important because, unlike emit_move_insn, the move expanders know
2451 how to force Pmode objects into the constant pool even when the
2452 constant pool address is not itself legitimate. */
2455 mips_emit_move (rtx dest, rtx src)
2457 return (can_create_pseudo_p ()
2458 ? emit_move_insn (dest, src)
2459 : emit_move_insn_1 (dest, src));
2462 /* Emit a move from SRC to DEST, splitting compound moves into individual
2463 instructions. SPLIT_TYPE is the type of split to perform. */
2466 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
2468 if (mips_split_move_p (dest, src, split_type))
2469 mips_split_move (dest, src, split_type);
2471 mips_emit_move (dest, src);
2474 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2477 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2479 emit_insn (gen_rtx_SET (VOIDmode, target,
2480 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2483 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2484 Return that new register. */
2487 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2491 reg = gen_reg_rtx (mode);
2492 mips_emit_unary (code, reg, op0);
2496 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2499 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2501 emit_insn (gen_rtx_SET (VOIDmode, target,
2502 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2505 /* Compute (CODE OP0 OP1) and store the result in a new register
2506 of mode MODE. Return that new register. */
2509 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2513 reg = gen_reg_rtx (mode);
2514 mips_emit_binary (code, reg, op0, op1);
2518 /* Copy VALUE to a register and return that register. If new pseudos
2519 are allowed, copy it into a new register, otherwise use DEST. */
2522 mips_force_temporary (rtx dest, rtx value)
2524 if (can_create_pseudo_p ())
2525 return force_reg (Pmode, value);
2528 mips_emit_move (dest, value);
2533 /* Emit a call sequence with call pattern PATTERN and return the call
2534 instruction itself (which is not necessarily the last instruction
2535 emitted). ORIG_ADDR is the original, unlegitimized address,
2536 ADDR is the legitimized form, and LAZY_P is true if the call
2537 address is lazily-bound. */
2540 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2544 insn = emit_call_insn (pattern);
2546 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2548 /* MIPS16 JALRs only take MIPS16 registers. If the target
2549 function requires $25 to be valid on entry, we must copy it
2550 there separately. The move instruction can be put in the
2551 call's delay slot. */
2552 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2553 emit_insn_before (gen_move_insn (reg, addr), insn);
2554 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2558 /* Lazy-binding stubs require $gp to be valid on entry. */
2559 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2563 /* See the comment above load_call<mode> for details. */
2564 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2565 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2566 emit_insn (gen_update_got_version ());
2571 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2572 then add CONST_INT OFFSET to the result. */
2575 mips_unspec_address_offset (rtx base, rtx offset,
2576 enum mips_symbol_type symbol_type)
2578 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2579 UNSPEC_ADDRESS_FIRST + symbol_type);
2580 if (offset != const0_rtx)
2581 base = gen_rtx_PLUS (Pmode, base, offset);
2582 return gen_rtx_CONST (Pmode, base);
2585 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2586 type SYMBOL_TYPE. */
2589 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2593 split_const (address, &base, &offset);
2594 return mips_unspec_address_offset (base, offset, symbol_type);
2597 /* If OP is an UNSPEC address, return the address to which it refers,
2598 otherwise return OP itself. */
2601 mips_strip_unspec_address (rtx op)
2605 split_const (op, &base, &offset);
2606 if (UNSPEC_ADDRESS_P (base))
2607 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2611 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2612 high part to BASE and return the result. Just return BASE otherwise.
2613 TEMP is as for mips_force_temporary.
2615 The returned expression can be used as the first operand to a LO_SUM. */
2618 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2619 enum mips_symbol_type symbol_type)
2621 if (mips_split_p[symbol_type])
2623 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2624 addr = mips_force_temporary (temp, addr);
2625 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2630 /* Return an instruction that copies $gp into register REG. We want
2631 GCC to treat the register's value as constant, so that its value
2632 can be rematerialized on demand. */
2635 gen_load_const_gp (rtx reg)
2637 return PMODE_INSN (gen_load_const_gp, (reg));
2640 /* Return a pseudo register that contains the value of $gp throughout
2641 the current function. Such registers are needed by MIPS16 functions,
2642 for which $gp itself is not a valid base register or addition operand. */
2645 mips16_gp_pseudo_reg (void)
2647 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2651 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2653 push_topmost_sequence ();
2655 scan = get_insns ();
2656 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2657 scan = NEXT_INSN (scan);
2659 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2660 insn = emit_insn_after (insn, scan);
2661 INSN_LOCATION (insn) = 0;
2663 pop_topmost_sequence ();
2666 return cfun->machine->mips16_gp_pseudo_rtx;
2669 /* Return a base register that holds pic_offset_table_rtx.
2670 TEMP, if nonnull, is a scratch Pmode base register. */
2673 mips_pic_base_register (rtx temp)
2676 return pic_offset_table_rtx;
2678 if (currently_expanding_to_rtl)
2679 return mips16_gp_pseudo_reg ();
2681 if (can_create_pseudo_p ())
2682 temp = gen_reg_rtx (Pmode);
2685 /* The first post-reload split exposes all references to $gp
2686 (both uses and definitions). All references must remain
2687 explicit after that point.
2689 It is safe to introduce uses of $gp at any time, so for
2690 simplicity, we do that before the split too. */
2691 mips_emit_move (temp, pic_offset_table_rtx);
2693 emit_insn (gen_load_const_gp (temp));
2697 /* Return the RHS of a load_call<mode> insn. */
2700 mips_unspec_call (rtx reg, rtx symbol)
2704 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2705 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
2708 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2709 reference. Return NULL_RTX otherwise. */
2712 mips_strip_unspec_call (rtx src)
2714 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
2715 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
2719 /* Create and return a GOT reference of type TYPE for address ADDR.
2720 TEMP, if nonnull, is a scratch Pmode base register. */
2723 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
2725 rtx base, high, lo_sum_symbol;
2727 base = mips_pic_base_register (temp);
2729 /* If we used the temporary register to load $gp, we can't use
2730 it for the high part as well. */
2731 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
2734 high = mips_unspec_offset_high (temp, base, addr, type);
2735 lo_sum_symbol = mips_unspec_address (addr, type);
2737 if (type == SYMBOL_GOTOFF_CALL)
2738 return mips_unspec_call (high, lo_sum_symbol);
2740 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
2743 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2744 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2745 constant in that context and can be split into high and low parts.
2746 If so, and if LOW_OUT is nonnull, emit the high part and store the
2747 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2749 TEMP is as for mips_force_temporary and is used to load the high
2750 part into a register.
2752 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2753 a legitimize SET_SRC for an .md pattern, otherwise the low part
2754 is guaranteed to be a legitimate address for mode MODE. */
2757 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
2759 enum mips_symbol_context context;
2760 enum mips_symbol_type symbol_type;
2763 context = (mode == MAX_MACHINE_MODE
2764 ? SYMBOL_CONTEXT_LEA
2765 : SYMBOL_CONTEXT_MEM);
2766 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
2768 addr = XEXP (addr, 0);
2769 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2770 && mips_symbol_insns (symbol_type, mode) > 0
2771 && mips_split_hi_p[symbol_type])
2774 switch (symbol_type)
2776 case SYMBOL_GOT_PAGE_OFST:
2777 /* The high part of a page/ofst pair is loaded from the GOT. */
2778 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
2789 if (mips_symbolic_constant_p (addr, context, &symbol_type)
2790 && mips_symbol_insns (symbol_type, mode) > 0
2791 && mips_split_p[symbol_type])
2794 switch (symbol_type)
2796 case SYMBOL_GOT_DISP:
2797 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2798 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
2801 case SYMBOL_GP_RELATIVE:
2802 high = mips_pic_base_register (temp);
2803 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2807 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
2808 high = mips_force_temporary (temp, high);
2809 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
2818 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2819 mips_force_temporary; it is only needed when OFFSET is not a
2823 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
2825 if (!SMALL_OPERAND (offset))
2831 /* Load the full offset into a register so that we can use
2832 an unextended instruction for the address itself. */
2833 high = GEN_INT (offset);
2838 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2839 The addition inside the macro CONST_HIGH_PART may cause an
2840 overflow, so we need to force a sign-extension check. */
2841 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
2842 offset = CONST_LOW_PART (offset);
2844 high = mips_force_temporary (temp, high);
2845 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
2847 return plus_constant (Pmode, reg, offset);
2850 /* The __tls_get_attr symbol. */
2851 static GTY(()) rtx mips_tls_symbol;
2853 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2854 the TLS symbol we are referencing and TYPE is the symbol type to use
2855 (either global dynamic or local dynamic). V0 is an RTX for the
2856 return value location. */
2859 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
2863 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
2865 if (!mips_tls_symbol)
2866 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
2868 loc = mips_unspec_address (sym, type);
2872 emit_insn (gen_rtx_SET (Pmode, a0,
2873 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
2874 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
2875 const0_rtx, NULL_RTX, false);
2876 RTL_CONST_CALL_P (insn) = 1;
2877 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
2878 insn = get_insns ();
2885 /* Return a pseudo register that contains the current thread pointer. */
2888 mips_expand_thread_pointer (rtx tp)
2894 mips_need_mips16_rdhwr_p = true;
2895 fn = mips16_stub_function ("__mips16_rdhwr");
2896 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
2897 if (!call_insn_operand (fn, VOIDmode))
2898 fn = force_reg (Pmode, fn);
2899 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
2902 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
2909 return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
2912 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2913 its address. The return value will be both a valid address and a valid
2914 SET_SRC (either a REG or a LO_SUM). */
2917 mips_legitimize_tls_address (rtx loc)
2919 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
2920 enum tls_model model;
2922 model = SYMBOL_REF_TLS_MODEL (loc);
2923 /* Only TARGET_ABICALLS code can have more than one module; other
2924 code must be be static and should not use a GOT. All TLS models
2925 reduce to local exec in this situation. */
2926 if (!TARGET_ABICALLS)
2927 model = TLS_MODEL_LOCAL_EXEC;
2931 case TLS_MODEL_GLOBAL_DYNAMIC:
2932 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2933 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
2934 dest = gen_reg_rtx (Pmode);
2935 emit_libcall_block (insn, dest, v0, loc);
2938 case TLS_MODEL_LOCAL_DYNAMIC:
2939 v0 = gen_rtx_REG (Pmode, GP_RETURN);
2940 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
2941 tmp1 = gen_reg_rtx (Pmode);
2943 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2944 share the LDM result with other LD model accesses. */
2945 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2947 emit_libcall_block (insn, tmp1, v0, eqv);
2949 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
2950 if (mips_split_p[SYMBOL_DTPREL])
2952 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
2953 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
2956 dest = expand_binop (Pmode, add_optab, tmp1, offset,
2957 0, 0, OPTAB_DIRECT);
2960 case TLS_MODEL_INITIAL_EXEC:
2961 tp = mips_get_tp ();
2962 tmp1 = gen_reg_rtx (Pmode);
2963 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
2964 if (Pmode == DImode)
2965 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
2967 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
2968 dest = gen_reg_rtx (Pmode);
2969 emit_insn (gen_add3_insn (dest, tmp1, tp));
2972 case TLS_MODEL_LOCAL_EXEC:
2973 tmp1 = mips_get_tp ();
2974 offset = mips_unspec_address (loc, SYMBOL_TPREL);
2975 if (mips_split_p[SYMBOL_TPREL])
2977 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
2978 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
2981 dest = expand_binop (Pmode, add_optab, tmp1, offset,
2982 0, 0, OPTAB_DIRECT);
2991 /* If X is not a valid address for mode MODE, force it into a register. */
2994 mips_force_address (rtx x, enum machine_mode mode)
2996 if (!mips_legitimate_address_p (mode, x, false))
2997 x = force_reg (Pmode, x);
3001 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3002 be legitimized in a way that the generic machinery might not expect,
3003 return a new address, otherwise return NULL. MODE is the mode of
3004 the memory being accessed. */
3007 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3008 enum machine_mode mode)
3011 HOST_WIDE_INT offset;
3013 if (mips_tls_symbol_p (x))
3014 return mips_legitimize_tls_address (x);
3016 /* See if the address can split into a high part and a LO_SUM. */
3017 if (mips_split_symbol (NULL, x, mode, &addr))
3018 return mips_force_address (addr, mode);
3020 /* Handle BASE + OFFSET using mips_add_offset. */
3021 mips_split_plus (x, &base, &offset);
3024 if (!mips_valid_base_register_p (base, mode, false))
3025 base = copy_to_mode_reg (Pmode, base);
3026 addr = mips_add_offset (NULL, base, offset);
3027 return mips_force_address (addr, mode);
3033 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3036 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3038 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3039 enum machine_mode mode;
3040 unsigned int i, num_ops;
3043 mode = GET_MODE (dest);
3044 num_ops = mips_build_integer (codes, value);
3046 /* Apply each binary operation to X. Invariant: X is a legitimate
3047 source operand for a SET pattern. */
3048 x = GEN_INT (codes[0].value);
3049 for (i = 1; i < num_ops; i++)
3051 if (!can_create_pseudo_p ())
3053 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3057 x = force_reg (mode, x);
3058 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3061 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3064 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3065 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3069 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3073 /* Split moves of big integers into smaller pieces. */
3074 if (splittable_const_int_operand (src, mode))
3076 mips_move_integer (dest, dest, INTVAL (src));
3080 /* Split moves of symbolic constants into high/low pairs. */
3081 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3083 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3087 /* Generate the appropriate access sequences for TLS symbols. */
3088 if (mips_tls_symbol_p (src))
3090 mips_emit_move (dest, mips_legitimize_tls_address (src));
3094 /* If we have (const (plus symbol offset)), and that expression cannot
3095 be forced into memory, load the symbol first and add in the offset.
3096 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3097 forced into memory, as it usually produces better code. */
3098 split_const (src, &base, &offset);
3099 if (offset != const0_rtx
3100 && (targetm.cannot_force_const_mem (mode, src)
3101 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3103 base = mips_force_temporary (dest, base);
3104 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3108 src = force_const_mem (mode, src);
3110 /* When using explicit relocs, constant pool references are sometimes
3111 not legitimate addresses. */
3112 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3113 mips_emit_move (dest, src);
3116 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3117 sequence that is valid. */
3120 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3122 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3124 mips_emit_move (dest, force_reg (mode, src));
3128 /* We need to deal with constants that would be legitimate
3129 immediate_operands but aren't legitimate move_operands. */
3130 if (CONSTANT_P (src) && !move_operand (src, mode))
3132 mips_legitimize_const_move (mode, dest, src);
3133 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3139 /* Return true if value X in context CONTEXT is a small-data address
3140 that can be rewritten as a LO_SUM. */
3143 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3145 enum mips_symbol_type symbol_type;
3147 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3148 && !mips_split_p[SYMBOL_GP_RELATIVE]
3149 && mips_symbolic_constant_p (x, context, &symbol_type)
3150 && symbol_type == SYMBOL_GP_RELATIVE);
3153 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3154 containing MEM, or null if none. */
3157 mips_small_data_pattern_1 (rtx *loc, void *data)
3159 enum mips_symbol_context context;
3161 /* Ignore things like "g" constraints in asms. We make no particular
3162 guarantee about which symbolic constants are acceptable as asm operands
3163 versus which must be forced into a GPR. */
3164 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3169 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3174 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3175 return mips_rewrite_small_data_p (*loc, context);
3178 /* Return true if OP refers to small data symbols directly, not through
3182 mips_small_data_pattern_p (rtx op)
3184 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3187 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3188 DATA is the containing MEM, or null if none. */
3191 mips_rewrite_small_data_1 (rtx *loc, void *data)
3193 enum mips_symbol_context context;
3197 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3201 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3202 if (mips_rewrite_small_data_p (*loc, context))
3203 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3205 if (GET_CODE (*loc) == LO_SUM)
3211 /* Rewrite instruction pattern PATTERN so that it refers to small data
3212 using explicit relocations. */
3215 mips_rewrite_small_data (rtx pattern)
3217 pattern = copy_insn (pattern);
3218 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3222 /* We need a lot of little routines to check the range of MIPS16 immediate
3226 m16_check_op (rtx op, int low, int high, int mask)
3228 return (CONST_INT_P (op)
3229 && IN_RANGE (INTVAL (op), low, high)
3230 && (INTVAL (op) & mask) == 0);
3234 m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3236 return m16_check_op (op, 0x1, 0x8, 0);
3240 m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3242 return m16_check_op (op, -0x8, 0x7, 0);
3246 m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3248 return m16_check_op (op, -0x7, 0x8, 0);
3252 m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3254 return m16_check_op (op, -0x10, 0xf, 0);
3258 m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3260 return m16_check_op (op, -0xf, 0x10, 0);
3264 m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3266 return m16_check_op (op, -0x10 << 2, 0xf << 2, 3);
3270 m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3272 return m16_check_op (op, -0xf << 2, 0x10 << 2, 3);
3276 m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3278 return m16_check_op (op, -0x80, 0x7f, 0);
3282 m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3284 return m16_check_op (op, -0x7f, 0x80, 0);
3288 m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3290 return m16_check_op (op, 0x0, 0xff, 0);
3294 m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3296 return m16_check_op (op, -0xff, 0x0, 0);
3300 m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3302 return m16_check_op (op, -0x1, 0xfe, 0);
3306 m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3308 return m16_check_op (op, 0x0, 0xff << 2, 3);
3312 m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3314 return m16_check_op (op, -0xff << 2, 0x0, 3);
3318 m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3320 return m16_check_op (op, -0x80 << 3, 0x7f << 3, 7);
3324 m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3326 return m16_check_op (op, -0x7f << 3, 0x80 << 3, 7);
3329 /* The cost of loading values from the constant pool. It should be
3330 larger than the cost of any constant we want to synthesize inline. */
3331 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3333 /* Return the cost of X when used as an operand to the MIPS16 instruction
3334 that implements CODE. Return -1 if there is no such instruction, or if
3335 X is not a valid immediate operand for it. */
3338 mips16_constant_cost (int code, HOST_WIDE_INT x)
3345 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3346 other shifts are extended. The shift patterns truncate the shift
3347 count to the right size, so there are no out-of-range values. */
3348 if (IN_RANGE (x, 1, 8))
3350 return COSTS_N_INSNS (1);
3353 if (IN_RANGE (x, -128, 127))
3355 if (SMALL_OPERAND (x))
3356 return COSTS_N_INSNS (1);
3360 /* Like LE, but reject the always-true case. */
3364 /* We add 1 to the immediate and use SLT. */
3367 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3370 if (IN_RANGE (x, 0, 255))
3372 if (SMALL_OPERAND_UNSIGNED (x))
3373 return COSTS_N_INSNS (1);
3378 /* Equality comparisons with 0 are cheap. */
3388 /* Return true if there is a non-MIPS16 instruction that implements CODE
3389 and if that instruction accepts X as an immediate operand. */
3392 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3399 /* All shift counts are truncated to a valid constant. */
3404 /* Likewise rotates, if the target supports rotates at all. */
3410 /* These instructions take 16-bit unsigned immediates. */
3411 return SMALL_OPERAND_UNSIGNED (x);
3416 /* These instructions take 16-bit signed immediates. */
3417 return SMALL_OPERAND (x);
3423 /* The "immediate" forms of these instructions are really
3424 implemented as comparisons with register 0. */
3429 /* Likewise, meaning that the only valid immediate operand is 1. */
3433 /* We add 1 to the immediate and use SLT. */
3434 return SMALL_OPERAND (x + 1);
3437 /* Likewise SLTU, but reject the always-true case. */
3438 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3442 /* The bit position and size are immediate operands. */
3443 return ISA_HAS_EXT_INS;
3446 /* By default assume that $0 can be used for 0. */
3451 /* Return the cost of binary operation X, given that the instruction
3452 sequence for a word-sized or smaller operation has cost SINGLE_COST
3453 and that the sequence of a double-word operation has cost DOUBLE_COST.
3454 If SPEED is true, optimize for speed otherwise optimize for size. */
3457 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3461 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3466 + set_src_cost (XEXP (x, 0), speed)
3467 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3470 /* Return the cost of floating-point multiplications of mode MODE. */
3473 mips_fp_mult_cost (enum machine_mode mode)
3475 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3478 /* Return the cost of floating-point divisions of mode MODE. */
3481 mips_fp_div_cost (enum machine_mode mode)
3483 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3486 /* Return the cost of sign-extending OP to mode MODE, not including the
3487 cost of OP itself. */
3490 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3493 /* Extended loads are as cheap as unextended ones. */
3496 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3497 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3500 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3501 /* We can use SEB or SEH. */
3502 return COSTS_N_INSNS (1);
3504 /* We need to use a shift left and a shift right. */
3505 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3508 /* Return the cost of zero-extending OP to mode MODE, not including the
3509 cost of OP itself. */
3512 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3515 /* Extended loads are as cheap as unextended ones. */
3518 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3519 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3520 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3522 if (GENERATE_MIPS16E)
3523 /* We can use ZEB or ZEH. */
3524 return COSTS_N_INSNS (1);
3527 /* We need to load 0xff or 0xffff into a register and use AND. */
3528 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3530 /* We can use ANDI. */
3531 return COSTS_N_INSNS (1);
3534 /* Return the cost of moving between two registers of mode MODE,
3535 assuming that the move will be in pieces of at most UNITS bytes. */
3538 mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
3540 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3543 /* Return the cost of moving between two registers of mode MODE. */
3546 mips_set_reg_reg_cost (enum machine_mode mode)
3548 switch (GET_MODE_CLASS (mode))
3551 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3554 case MODE_COMPLEX_FLOAT:
3555 case MODE_VECTOR_FLOAT:
3556 if (TARGET_HARD_FLOAT)
3557 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3561 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3565 /* Return the cost of an operand X that can be trucated for free.
3566 SPEED says whether we're optimizing for size or speed. */
3569 mips_truncated_op_cost (rtx x, bool speed)
3571 if (GET_CODE (x) == TRUNCATE)
3573 return set_src_cost (x, speed);
3576 /* Implement TARGET_RTX_COSTS. */
3579 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3580 int *total, bool speed)
3582 enum machine_mode mode = GET_MODE (x);
3583 bool float_mode_p = FLOAT_MODE_P (mode);
3587 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3588 appear in the instruction stream, and the cost of a comparison is
3589 really the cost of the branch or scc condition. At the time of
3590 writing, GCC only uses an explicit outer COMPARE code when optabs
3591 is testing whether a constant is expensive enough to force into a
3592 register. We want optabs to pass such constants through the MIPS
3593 expanders instead, so make all constants very cheap here. */
3594 if (outer_code == COMPARE)
3596 gcc_assert (CONSTANT_P (x));
3604 /* Treat *clear_upper32-style ANDs as having zero cost in the
3605 second operand. The cost is entirely in the first operand.
3607 ??? This is needed because we would otherwise try to CSE
3608 the constant operand. Although that's the right thing for
3609 instructions that continue to be a register operation throughout
3610 compilation, it is disastrous for instructions that could
3611 later be converted into a memory operation. */
3613 && outer_code == AND
3614 && UINTVAL (x) == 0xffffffff)
3622 cost = mips16_constant_cost (outer_code, INTVAL (x));
3631 /* When not optimizing for size, we care more about the cost
3632 of hot code, and hot code is often in a loop. If a constant
3633 operand needs to be forced into a register, we will often be
3634 able to hoist the constant load out of the loop, so the load
3635 should not contribute to the cost. */
3636 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3648 if (force_to_mem_operand (x, VOIDmode))
3650 *total = COSTS_N_INSNS (1);
3653 cost = mips_const_insns (x);
3656 /* If the constant is likely to be stored in a GPR, SETs of
3657 single-insn constants are as cheap as register sets; we
3658 never want to CSE them.
3660 Don't reduce the cost of storing a floating-point zero in
3661 FPRs. If we have a zero in an FPR for other reasons, we
3662 can get better cfg-cleanup and delayed-branch results by
3663 using it consistently, rather than using $0 sometimes and
3664 an FPR at other times. Also, moves between floating-point
3665 registers are sometimes cheaper than (D)MTC1 $0. */
3667 && outer_code == SET
3668 && !(float_mode_p && TARGET_HARD_FLOAT))
3670 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3671 want to CSE the constant itself. It is usually better to
3672 have N copies of the last operation in the sequence and one
3673 shared copy of the other operations. (Note that this is
3674 not true for MIPS16 code, where the final operation in the
3675 sequence is often an extended instruction.)
3677 Also, if we have a CONST_INT, we don't know whether it is
3678 for a word or doubleword operation, so we cannot rely on
3679 the result of mips_build_integer. */
3680 else if (!TARGET_MIPS16
3681 && (outer_code == SET || mode == VOIDmode))
3683 *total = COSTS_N_INSNS (cost);
3686 /* The value will need to be fetched from the constant pool. */
3687 *total = CONSTANT_POOL_COST;
3691 /* If the address is legitimate, return the number of
3692 instructions it needs. */
3694 cost = mips_address_insns (addr, mode, true);
3697 *total = COSTS_N_INSNS (cost + 1);
3700 /* Check for a scaled indexed address. */
3701 if (mips_lwxs_address_p (addr)
3702 || mips_lx_address_p (addr, mode))
3704 *total = COSTS_N_INSNS (2);
3707 /* Otherwise use the default handling. */
3711 *total = COSTS_N_INSNS (6);
3715 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3719 /* Check for a *clear_upper32 pattern and treat it like a zero
3720 extension. See the pattern's comment for details. */
3723 && CONST_INT_P (XEXP (x, 1))
3724 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3726 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3727 + set_src_cost (XEXP (x, 0), speed));
3730 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
3732 rtx op = XEXP (x, 0);
3733 if (GET_CODE (op) == ASHIFT
3734 && CONST_INT_P (XEXP (op, 1))
3735 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
3737 *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed);
3746 /* Double-word operations use two single-word operations. */
3747 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3756 if (CONSTANT_P (XEXP (x, 1)))
3757 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3760 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3766 *total = mips_cost->fp_add;
3768 *total = COSTS_N_INSNS (4);
3772 /* Low-part immediates need an extended MIPS16 instruction. */
3773 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3774 + set_src_cost (XEXP (x, 0), speed));
3789 /* Branch comparisons have VOIDmode, so use the first operand's
3791 mode = GET_MODE (XEXP (x, 0));
3792 if (FLOAT_MODE_P (mode))
3794 *total = mips_cost->fp_add;
3797 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3803 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3804 && TARGET_FUSED_MADD
3805 && !HONOR_NANS (mode)
3806 && !HONOR_SIGNED_ZEROS (mode))
3808 /* See if we can use NMADD or NMSUB. See mips.md for the
3809 associated patterns. */
3810 rtx op0 = XEXP (x, 0);
3811 rtx op1 = XEXP (x, 1);
3812 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
3814 *total = (mips_fp_mult_cost (mode)
3815 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
3816 + set_src_cost (XEXP (op0, 1), speed)
3817 + set_src_cost (op1, speed));
3820 if (GET_CODE (op1) == MULT)
3822 *total = (mips_fp_mult_cost (mode)
3823 + set_src_cost (op0, speed)
3824 + set_src_cost (XEXP (op1, 0), speed)
3825 + set_src_cost (XEXP (op1, 1), speed));
3834 /* If this is part of a MADD or MSUB, treat the PLUS as
3837 && TARGET_FUSED_MADD
3838 && GET_CODE (XEXP (x, 0)) == MULT)
3841 *total = mips_cost->fp_add;
3845 /* Double-word operations require three single-word operations and
3846 an SLTU. The MIPS16 version then needs to move the result of
3847 the SLTU from $24 to a MIPS16 register. */
3848 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
3849 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
3855 && (ISA_HAS_NMADD4_NMSUB4 (mode) || ISA_HAS_NMADD3_NMSUB3 (mode))
3856 && TARGET_FUSED_MADD
3857 && !HONOR_NANS (mode)
3858 && HONOR_SIGNED_ZEROS (mode))
3860 /* See if we can use NMADD or NMSUB. See mips.md for the
3861 associated patterns. */
3862 rtx op = XEXP (x, 0);
3863 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
3864 && GET_CODE (XEXP (op, 0)) == MULT)
3866 *total = (mips_fp_mult_cost (mode)
3867 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
3868 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
3869 + set_src_cost (XEXP (op, 1), speed));
3875 *total = mips_cost->fp_add;
3877 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
3882 *total = mips_fp_mult_cost (mode);
3883 else if (mode == DImode && !TARGET_64BIT)
3884 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3885 where the mulsidi3 always includes an MFHI and an MFLO. */
3887 ? mips_cost->int_mult_si * 3 + 6
3888 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
3890 *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2);
3891 else if (mode == DImode)
3892 *total = mips_cost->int_mult_di;
3894 *total = mips_cost->int_mult_si;
3898 /* Check for a reciprocal. */
3901 && flag_unsafe_math_optimizations
3902 && XEXP (x, 0) == CONST1_RTX (mode))
3904 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
3905 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3906 division as being free. */
3907 *total = set_src_cost (XEXP (x, 1), speed);
3909 *total = (mips_fp_div_cost (mode)
3910 + set_src_cost (XEXP (x, 1), speed));
3919 *total = mips_fp_div_cost (mode);
3928 /* It is our responsibility to make division by a power of 2
3929 as cheap as 2 register additions if we want the division
3930 expanders to be used for such operations; see the setting
3931 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3932 should always produce shorter code than using
3933 expand_sdiv2_pow2. */
3935 && CONST_INT_P (XEXP (x, 1))
3936 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
3938 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
3941 *total = COSTS_N_INSNS (mips_idiv_insns ());
3943 else if (mode == DImode)
3944 *total = mips_cost->int_div_di;
3946 *total = mips_cost->int_div_si;
3950 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
3954 if (outer_code == SET
3956 && GET_MODE (XEXP (x, 0)) == QImode
3957 && GET_CODE (XEXP (x, 0)) == PLUS)
3959 rtx plus = XEXP (x, 0);
3960 *total = (COSTS_N_INSNS (1)
3961 + mips_truncated_op_cost (XEXP (plus, 0), speed)
3962 + mips_truncated_op_cost (XEXP (plus, 1), speed));
3965 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
3969 case UNSIGNED_FLOAT:
3972 case FLOAT_TRUNCATE:
3973 *total = mips_cost->fp_add;
3977 if (register_operand (SET_DEST (x), VOIDmode)
3978 && reg_or_0_operand (SET_SRC (x), VOIDmode))
3980 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
3990 /* Implement TARGET_ADDRESS_COST. */
3993 mips_address_cost (rtx addr, enum machine_mode mode,
3994 addr_space_t as ATTRIBUTE_UNUSED,
3995 bool speed ATTRIBUTE_UNUSED)
3997 return mips_address_insns (addr, mode, false);
4000 /* Information about a single instruction in a multi-instruction
4002 struct mips_multi_member {
4003 /* True if this is a label, false if it is code. */
4006 /* The output_asm_insn format of the instruction. */
4009 /* The operands to the instruction. */
4010 rtx operands[MAX_RECOG_OPERANDS];
4012 typedef struct mips_multi_member mips_multi_member;
4014 /* Vector definitions for the above. */
4015 DEF_VEC_O(mips_multi_member);
4016 DEF_VEC_ALLOC_O(mips_multi_member, heap);
4018 /* The instructions that make up the current multi-insn sequence. */
4019 static VEC (mips_multi_member, heap) *mips_multi_members;
4021 /* How many instructions (as opposed to labels) are in the current
4022 multi-insn sequence. */
4023 static unsigned int mips_multi_num_insns;
4025 /* Start a new multi-insn sequence. */
4028 mips_multi_start (void)
4030 VEC_truncate (mips_multi_member, mips_multi_members, 0);
4031 mips_multi_num_insns = 0;
4034 /* Add a new, uninitialized member to the current multi-insn sequence. */
4036 static struct mips_multi_member *
4037 mips_multi_add (void)
4039 mips_multi_member empty;
4040 return VEC_safe_push (mips_multi_member, heap, mips_multi_members, empty);
4043 /* Add a normal insn with the given asm format to the current multi-insn
4044 sequence. The other arguments are a null-terminated list of operands. */
4047 mips_multi_add_insn (const char *format, ...)
4049 struct mips_multi_member *member;
4054 member = mips_multi_add ();
4055 member->is_label_p = false;
4056 member->format = format;
4057 va_start (ap, format);
4059 while ((op = va_arg (ap, rtx)))
4060 member->operands[i++] = op;
4062 mips_multi_num_insns++;
4065 /* Add the given label definition to the current multi-insn sequence.
4066 The definition should include the colon. */
4069 mips_multi_add_label (const char *label)
4071 struct mips_multi_member *member;
4073 member = mips_multi_add ();
4074 member->is_label_p = true;
4075 member->format = label;
4078 /* Return the index of the last member of the current multi-insn sequence. */
4081 mips_multi_last_index (void)
4083 return VEC_length (mips_multi_member, mips_multi_members) - 1;
4086 /* Add a copy of an existing instruction to the current multi-insn
4087 sequence. I is the index of the instruction that should be copied. */
4090 mips_multi_copy_insn (unsigned int i)
4092 struct mips_multi_member *member;
4094 member = mips_multi_add ();
4095 memcpy (member, &VEC_index (mips_multi_member, mips_multi_members, i),
4097 gcc_assert (!member->is_label_p);
4100 /* Change the operand of an existing instruction in the current
4101 multi-insn sequence. I is the index of the instruction,
4102 OP is the index of the operand, and X is the new value. */
4105 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4107 VEC_index (mips_multi_member, mips_multi_members, i).operands[op] = x;
4110 /* Write out the asm code for the current multi-insn sequence. */
4113 mips_multi_write (void)
4115 struct mips_multi_member *member;
4118 FOR_EACH_VEC_ELT (mips_multi_member, mips_multi_members, i, member)
4119 if (member->is_label_p)
4120 fprintf (asm_out_file, "%s\n", member->format);
4122 output_asm_insn (member->format, member->operands);
4125 /* Return one word of double-word value OP, taking into account the fixed
4126 endianness of certain registers. HIGH_P is true to select the high part,
4127 false to select the low part. */
4130 mips_subword (rtx op, bool high_p)
4132 unsigned int byte, offset;
4133 enum machine_mode mode;
4135 mode = GET_MODE (op);
4136 if (mode == VOIDmode)
4137 mode = TARGET_64BIT ? TImode : DImode;
4139 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4140 byte = UNITS_PER_WORD;
4144 if (FP_REG_RTX_P (op))
4146 /* Paired FPRs are always ordered little-endian. */
4147 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4148 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4152 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4154 return simplify_gen_subreg (word_mode, op, mode, byte);
4157 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4158 SPLIT_TYPE is the condition under which moves should be split. */
4161 mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4163 return ((split_type != SPLIT_FOR_SPEED
4164 || mips_tuning_info.fast_mult_zero_zero_p)
4165 && src == const0_rtx
4167 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
4168 && (ISA_HAS_DSP_MULT
4169 ? ACC_REG_P (REGNO (dest))
4170 : MD_REG_P (REGNO (dest))));
4173 /* Return true if a move from SRC to DEST should be split into two.
4174 SPLIT_TYPE describes the split condition. */
4177 mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4179 /* Check whether the move can be done using some variant of MULT $0,$0. */
4180 if (mips_mult_move_p (dest, src, split_type))
4183 /* FPR-to-FPR moves can be done in a single instruction, if they're
4185 unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
4186 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4189 /* Check for floating-point loads and stores. */
4190 if (size == 8 && ISA_HAS_LDC1_SDC1)
4192 if (FP_REG_RTX_P (dest) && MEM_P (src))
4194 if (FP_REG_RTX_P (src) && MEM_P (dest))
4198 /* Otherwise split all multiword moves. */
4199 return size > UNITS_PER_WORD;
4202 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4203 SPLIT_TYPE describes the split condition. */
4206 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
4210 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4211 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4213 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4214 emit_insn (gen_move_doubleword_fprdi (dest, src));
4215 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4216 emit_insn (gen_move_doubleword_fprdf (dest, src));
4217 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4218 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4219 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4220 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4221 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4222 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4223 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4224 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4225 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4226 emit_insn (gen_move_doubleword_fprtf (dest, src));
4230 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4232 low_dest = mips_subword (dest, false);
4233 mips_emit_move (low_dest, mips_subword (src, false));
4235 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4237 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4239 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4241 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4243 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4245 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4249 /* The operation can be split into two normal moves. Decide in
4250 which order to do them. */
4251 low_dest = mips_subword (dest, false);
4252 if (REG_P (low_dest)
4253 && reg_overlap_mentioned_p (low_dest, src))
4255 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4256 mips_emit_move (low_dest, mips_subword (src, false));
4260 mips_emit_move (low_dest, mips_subword (src, false));
4261 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4266 /* Return the split type for instruction INSN. */
4268 static enum mips_split_type
4269 mips_insn_split_type (rtx insn)
4271 basic_block bb = BLOCK_FOR_INSN (insn);
4274 if (optimize_bb_for_speed_p (bb))
4275 return SPLIT_FOR_SPEED;
4277 return SPLIT_FOR_SIZE;
4279 /* Once CFG information has been removed, we should trust the optimization
4280 decisions made by previous passes and only split where necessary. */
4281 return SPLIT_IF_NECESSARY;
4284 /* Return true if a move from SRC to DEST in INSN should be split. */
4287 mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
4289 return mips_split_move_p (dest, src, mips_insn_split_type (insn));
4292 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4296 mips_split_move_insn (rtx dest, rtx src, rtx insn)
4298 mips_split_move (dest, src, mips_insn_split_type (insn));
4301 /* Return the appropriate instructions to move SRC into DEST. Assume
4302 that SRC is operand 1 and DEST is operand 0. */
4305 mips_output_move (rtx dest, rtx src)
4307 enum rtx_code dest_code, src_code;
4308 enum machine_mode mode;
4309 enum mips_symbol_type symbol_type;
4312 dest_code = GET_CODE (dest);
4313 src_code = GET_CODE (src);
4314 mode = GET_MODE (dest);
4315 dbl_p = (GET_MODE_SIZE (mode) == 8);
4317 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
4320 if ((src_code == REG && GP_REG_P (REGNO (src)))
4321 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4323 if (dest_code == REG)
4325 if (GP_REG_P (REGNO (dest)))
4326 return "move\t%0,%z1";
4328 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
4330 if (ISA_HAS_DSP_MULT)
4331 return "mult\t%q0,%.,%.";
4333 return "mult\t%.,%.";
4336 /* Moves to HI are handled by special .md insns. */
4337 if (REGNO (dest) == LO_REGNUM)
4340 if (DSP_ACC_REG_P (REGNO (dest)))
4342 static char retval[] = "mt__\t%z1,%q0";
4344 retval[2] = reg_names[REGNO (dest)][4];
4345 retval[3] = reg_names[REGNO (dest)][5];
4349 if (FP_REG_P (REGNO (dest)))
4350 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4352 if (ALL_COP_REG_P (REGNO (dest)))
4354 static char retval[] = "dmtc_\t%z1,%0";
4356 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4357 return dbl_p ? retval : retval + 1;
4360 if (dest_code == MEM)
4361 switch (GET_MODE_SIZE (mode))
4363 case 1: return "sb\t%z1,%0";
4364 case 2: return "sh\t%z1,%0";
4365 case 4: return "sw\t%z1,%0";
4366 case 8: return "sd\t%z1,%0";
4369 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4371 if (src_code == REG)
4373 /* Moves from HI are handled by special .md insns. */
4374 if (REGNO (src) == LO_REGNUM)
4376 /* When generating VR4120 or VR4130 code, we use MACC and
4377 DMACC instead of MFLO. This avoids both the normal
4378 MIPS III HI/LO hazards and the errata related to
4381 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4385 if (DSP_ACC_REG_P (REGNO (src)))
4387 static char retval[] = "mf__\t%0,%q1";
4389 retval[2] = reg_names[REGNO (src)][4];
4390 retval[3] = reg_names[REGNO (src)][5];
4394 if (FP_REG_P (REGNO (src)))
4395 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4397 if (ALL_COP_REG_P (REGNO (src)))
4399 static char retval[] = "dmfc_\t%0,%1";
4401 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4402 return dbl_p ? retval : retval + 1;
4406 if (src_code == MEM)
4407 switch (GET_MODE_SIZE (mode))
4409 case 1: return "lbu\t%0,%1";
4410 case 2: return "lhu\t%0,%1";
4411 case 4: return "lw\t%0,%1";
4412 case 8: return "ld\t%0,%1";
4415 if (src_code == CONST_INT)
4417 /* Don't use the X format for the operand itself, because that
4418 will give out-of-range numbers for 64-bit hosts and 32-bit
4421 return "li\t%0,%1\t\t\t# %X1";
4423 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4426 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4430 if (src_code == HIGH)
4431 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4433 if (CONST_GP_P (src))
4434 return "move\t%0,%1";
4436 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4437 && mips_lo_relocs[symbol_type] != 0)
4439 /* A signed 16-bit constant formed by applying a relocation
4440 operator to a symbolic address. */
4441 gcc_assert (!mips_split_p[symbol_type]);
4442 return "li\t%0,%R1";
4445 if (symbolic_operand (src, VOIDmode))
4447 gcc_assert (TARGET_MIPS16
4448 ? TARGET_MIPS16_TEXT_LOADS
4449 : !TARGET_EXPLICIT_RELOCS);
4450 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4453 if (src_code == REG && FP_REG_P (REGNO (src)))
4455 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4457 if (GET_MODE (dest) == V2SFmode)
4458 return "mov.ps\t%0,%1";
4460 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4463 if (dest_code == MEM)
4464 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4466 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4468 if (src_code == MEM)
4469 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4471 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4473 static char retval[] = "l_c_\t%0,%1";
4475 retval[1] = (dbl_p ? 'd' : 'w');
4476 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4479 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4481 static char retval[] = "s_c_\t%1,%0";
4483 retval[1] = (dbl_p ? 'd' : 'w');
4484 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4490 /* Return true if CMP1 is a suitable second operand for integer ordering
4491 test CODE. See also the *sCC patterns in mips.md. */
4494 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4500 return reg_or_0_operand (cmp1, VOIDmode);
4504 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4508 return arith_operand (cmp1, VOIDmode);
4511 return sle_operand (cmp1, VOIDmode);
4514 return sleu_operand (cmp1, VOIDmode);
4521 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4522 integer ordering test *CODE, or if an equivalent combination can
4523 be formed by adjusting *CODE and *CMP1. When returning true, update
4524 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4528 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4529 enum machine_mode mode)
4531 HOST_WIDE_INT plus_one;
4533 if (mips_int_order_operand_ok_p (*code, *cmp1))
4536 if (CONST_INT_P (*cmp1))
4540 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4541 if (INTVAL (*cmp1) < plus_one)
4544 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4550 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4554 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4565 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4566 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4567 is nonnull, it's OK to set TARGET to the inverse of the result and
4568 flip *INVERT_PTR instead. */
4571 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4572 rtx target, rtx cmp0, rtx cmp1)
4574 enum machine_mode mode;
4576 /* First see if there is a MIPS instruction that can do this operation.
4577 If not, try doing the same for the inverse operation. If that also
4578 fails, force CMP1 into a register and try again. */
4579 mode = GET_MODE (cmp0);
4580 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4581 mips_emit_binary (code, target, cmp0, cmp1);
4584 enum rtx_code inv_code = reverse_condition (code);
4585 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4587 cmp1 = force_reg (mode, cmp1);
4588 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4590 else if (invert_ptr == 0)
4594 inv_target = mips_force_binary (GET_MODE (target),
4595 inv_code, cmp0, cmp1);
4596 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4600 *invert_ptr = !*invert_ptr;
4601 mips_emit_binary (inv_code, target, cmp0, cmp1);
4606 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4607 The register will have the same mode as CMP0. */
4610 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4612 if (cmp1 == const0_rtx)
4615 if (uns_arith_operand (cmp1, VOIDmode))
4616 return expand_binop (GET_MODE (cmp0), xor_optab,
4617 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4619 return expand_binop (GET_MODE (cmp0), sub_optab,
4620 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4623 /* Convert *CODE into a code that can be used in a floating-point
4624 scc instruction (C.cond.fmt). Return true if the values of
4625 the condition code registers will be inverted, with 0 indicating
4626 that the condition holds. */
4629 mips_reversed_fp_cond (enum rtx_code *code)
4636 *code = reverse_condition_maybe_unordered (*code);
4644 /* Allocate a floating-point condition-code register of mode MODE.
4646 These condition code registers are used for certain kinds
4647 of compound operation, such as compare and branches, vconds,
4648 and built-in functions. At expand time, their use is entirely
4649 controlled by MIPS-specific code and is entirely internal
4650 to these compound operations.
4652 We could (and did in the past) expose condition-code values
4653 as pseudo registers and leave the register allocator to pick
4654 appropriate registers. The problem is that it is not practically
4655 possible for the rtl optimizers to guarantee that no spills will
4656 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4657 therefore need spill and reload sequences to handle the worst case.
4659 Although such sequences do exist, they are very expensive and are
4660 not something we'd want to use. This is especially true of CCV2 and
4661 CCV4, where all the shuffling would greatly outweigh whatever benefit
4662 the vectorization itself provides.
4664 The main benefit of having more than one condition-code register
4665 is to allow the pipelining of operations, especially those involving
4666 comparisons and conditional moves. We don't really expect the
4667 registers to be live for long periods, and certainly never want
4668 them to be live across calls.
4670 Also, there should be no penalty attached to using all the available
4671 registers. They are simply bits in the same underlying FPU control
4674 We therefore expose the hardware registers from the outset and use
4675 a simple round-robin allocation scheme. */
4678 mips_allocate_fcc (enum machine_mode mode)
4680 unsigned int regno, count;
4682 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
4686 else if (mode == CCV2mode)
4688 else if (mode == CCV4mode)
4693 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
4694 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
4695 cfun->machine->next_fcc = 0;
4696 regno = ST_REG_FIRST + cfun->machine->next_fcc;
4697 cfun->machine->next_fcc += count;
4698 return gen_rtx_REG (mode, regno);
4701 /* Convert a comparison into something that can be used in a branch or
4702 conditional move. On entry, *OP0 and *OP1 are the values being
4703 compared and *CODE is the code used to compare them.
4705 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4706 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4707 otherwise any standard branch condition can be used. The standard branch
4710 - EQ or NE between two registers.
4711 - any comparison between a register and zero. */
4714 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4719 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4721 if (!need_eq_ne_p && *op1 == const0_rtx)
4723 else if (*code == EQ || *code == NE)
4727 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4731 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4735 /* The comparison needs a separate scc instruction. Store the
4736 result of the scc in *OP0 and compare it against zero. */
4737 bool invert = false;
4738 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4739 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4740 *code = (invert ? EQ : NE);
4744 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4746 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4747 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4753 enum rtx_code cmp_code;
4755 /* Floating-point tests use a separate C.cond.fmt comparison to
4756 set a condition code register. The branch or conditional move
4757 will then compare that register against zero.
4759 Set CMP_CODE to the code of the comparison instruction and
4760 *CODE to the code that the branch or move should use. */
4762 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4764 ? mips_allocate_fcc (CCmode)
4765 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4767 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4771 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4772 and OPERAND[3]. Store the result in OPERANDS[0].
4774 On 64-bit targets, the mode of the comparison and target will always be
4775 SImode, thus possibly narrower than that of the comparison's operands. */
4778 mips_expand_scc (rtx operands[])
4780 rtx target = operands[0];
4781 enum rtx_code code = GET_CODE (operands[1]);
4782 rtx op0 = operands[2];
4783 rtx op1 = operands[3];
4785 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4787 if (code == EQ || code == NE)
4790 && reg_imm10_operand (op1, GET_MODE (op1)))
4791 mips_emit_binary (code, target, op0, op1);
4794 rtx zie = mips_zero_if_equal (op0, op1);
4795 mips_emit_binary (code, target, zie, const0_rtx);
4799 mips_emit_int_order_test (code, 0, target, op0, op1);
4802 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4803 CODE and jump to OPERANDS[3] if the condition holds. */
4806 mips_expand_conditional_branch (rtx *operands)
4808 enum rtx_code code = GET_CODE (operands[0]);
4809 rtx op0 = operands[1];
4810 rtx op1 = operands[2];
4813 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
4814 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
4815 emit_jump_insn (gen_condjump (condition, operands[3]));
4820 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4821 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4824 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
4825 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
4830 reversed_p = mips_reversed_fp_cond (&cond);
4831 cmp_result = mips_allocate_fcc (CCV2mode);
4832 emit_insn (gen_scc_ps (cmp_result,
4833 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
4835 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
4838 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
4842 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4843 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4846 mips_expand_conditional_move (rtx *operands)
4849 enum rtx_code code = GET_CODE (operands[1]);
4850 rtx op0 = XEXP (operands[1], 0);
4851 rtx op1 = XEXP (operands[1], 1);
4853 mips_emit_compare (&code, &op0, &op1, true);
4854 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
4855 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4856 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
4857 operands[2], operands[3])));
4860 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4863 mips_expand_conditional_trap (rtx comparison)
4866 enum machine_mode mode;
4869 /* MIPS conditional trap instructions don't have GT or LE flavors,
4870 so we must swap the operands and convert to LT and GE respectively. */
4871 code = GET_CODE (comparison);
4878 code = swap_condition (code);
4879 op0 = XEXP (comparison, 1);
4880 op1 = XEXP (comparison, 0);
4884 op0 = XEXP (comparison, 0);
4885 op1 = XEXP (comparison, 1);
4889 mode = GET_MODE (XEXP (comparison, 0));
4890 op0 = force_reg (mode, op0);
4891 if (!arith_operand (op1, mode))
4892 op1 = force_reg (mode, op1);
4894 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
4895 gen_rtx_fmt_ee (code, mode, op0, op1),
4899 /* Initialize *CUM for a call to a function of type FNTYPE. */
4902 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
4904 memset (cum, 0, sizeof (*cum));
4905 cum->prototype = (fntype && prototype_p (fntype));
4906 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
4909 /* Fill INFO with information about a single argument. CUM is the
4910 cumulative state for earlier arguments. MODE is the mode of this
4911 argument and TYPE is its type (if known). NAMED is true if this
4912 is a named (fixed) argument rather than a variable one. */
4915 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
4916 enum machine_mode mode, const_tree type, bool named)
4918 bool doubleword_aligned_p;
4919 unsigned int num_bytes, num_words, max_regs;
4921 /* Work out the size of the argument. */
4922 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
4923 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4925 /* Decide whether it should go in a floating-point register, assuming
4926 one is free. Later code checks for availability.
4928 The checks against UNITS_PER_FPVALUE handle the soft-float and
4929 single-float cases. */
4933 /* The EABI conventions have traditionally been defined in terms
4934 of TYPE_MODE, regardless of the actual type. */
4935 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
4936 || mode == V2SFmode)
4937 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4942 /* Only leading floating-point scalars are passed in
4943 floating-point registers. We also handle vector floats the same
4944 say, which is OK because they are not covered by the standard ABI. */
4945 info->fpr_p = (!cum->gp_reg_found
4946 && cum->arg_number < 2
4948 || SCALAR_FLOAT_TYPE_P (type)
4949 || VECTOR_FLOAT_TYPE_P (type))
4950 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4951 || mode == V2SFmode)
4952 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
4957 /* Scalar, complex and vector floating-point types are passed in
4958 floating-point registers, as long as this is a named rather
4959 than a variable argument. */
4960 info->fpr_p = (named
4961 && (type == 0 || FLOAT_TYPE_P (type))
4962 && (GET_MODE_CLASS (mode) == MODE_FLOAT
4963 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4964 || mode == V2SFmode)
4965 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
4967 /* ??? According to the ABI documentation, the real and imaginary
4968 parts of complex floats should be passed in individual registers.
4969 The real and imaginary parts of stack arguments are supposed
4970 to be contiguous and there should be an extra word of padding
4973 This has two problems. First, it makes it impossible to use a
4974 single "void *" va_list type, since register and stack arguments
4975 are passed differently. (At the time of writing, MIPSpro cannot
4976 handle complex float varargs correctly.) Second, it's unclear
4977 what should happen when there is only one register free.
4979 For now, we assume that named complex floats should go into FPRs
4980 if there are two FPRs free, otherwise they should be passed in the
4981 same way as a struct containing two floats. */
4983 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
4984 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
4986 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
4987 info->fpr_p = false;
4997 /* See whether the argument has doubleword alignment. */
4998 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
5001 /* Set REG_OFFSET to the register count we're interested in.
5002 The EABI allocates the floating-point registers separately,
5003 but the other ABIs allocate them like integer registers. */
5004 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
5008 /* Advance to an even register if the argument is doubleword-aligned. */
5009 if (doubleword_aligned_p)
5010 info->reg_offset += info->reg_offset & 1;
5012 /* Work out the offset of a stack argument. */
5013 info->stack_offset = cum->stack_words;
5014 if (doubleword_aligned_p)
5015 info->stack_offset += info->stack_offset & 1;
5017 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
5019 /* Partition the argument between registers and stack. */
5020 info->reg_words = MIN (num_words, max_regs);
5021 info->stack_words = num_words - info->reg_words;
5024 /* INFO describes a register argument that has the normal format for the
5025 argument's mode. Return the register it uses, assuming that FPRs are
5026 available if HARD_FLOAT_P. */
5029 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
5031 if (!info->fpr_p || !hard_float_p)
5032 return GP_ARG_FIRST + info->reg_offset;
5033 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
5034 /* In o32, the second argument is always passed in $f14
5035 for TARGET_DOUBLE_FLOAT, regardless of whether the
5036 first argument was a word or doubleword. */
5037 return FP_ARG_FIRST + 2;
5039 return FP_ARG_FIRST + info->reg_offset;
5042 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5045 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5047 return !TARGET_OLDABI;
5050 /* Implement TARGET_FUNCTION_ARG. */
5053 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
5054 const_tree type, bool named)
5056 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5057 struct mips_arg_info info;
5059 /* We will be called with a mode of VOIDmode after the last argument
5060 has been seen. Whatever we return will be passed to the call expander.
5061 If we need a MIPS16 fp_code, return a REG with the code stored as
5063 if (mode == VOIDmode)
5065 if (TARGET_MIPS16 && cum->fp_code != 0)
5066 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
5071 mips_get_arg_info (&info, cum, mode, type, named);
5073 /* Return straight away if the whole argument is passed on the stack. */
5074 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5077 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5078 contains a double in its entirety, then that 64-bit chunk is passed
5079 in a floating-point register. */
5081 && TARGET_HARD_FLOAT
5084 && TREE_CODE (type) == RECORD_TYPE
5085 && TYPE_SIZE_UNIT (type)
5086 && host_integerp (TYPE_SIZE_UNIT (type), 1))
5090 /* First check to see if there is any such field. */
5091 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5092 if (TREE_CODE (field) == FIELD_DECL
5093 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5094 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5095 && host_integerp (bit_position (field), 0)
5096 && int_bit_position (field) % BITS_PER_WORD == 0)
5101 /* Now handle the special case by returning a PARALLEL
5102 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5103 chunks are passed in registers. */
5105 HOST_WIDE_INT bitpos;
5108 /* assign_parms checks the mode of ENTRY_PARM, so we must
5109 use the actual mode here. */
5110 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5113 field = TYPE_FIELDS (type);
5114 for (i = 0; i < info.reg_words; i++)
5118 for (; field; field = DECL_CHAIN (field))
5119 if (TREE_CODE (field) == FIELD_DECL
5120 && int_bit_position (field) >= bitpos)
5124 && int_bit_position (field) == bitpos
5125 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5126 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5127 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5129 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5132 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5133 GEN_INT (bitpos / BITS_PER_UNIT));
5135 bitpos += BITS_PER_WORD;
5141 /* Handle the n32/n64 conventions for passing complex floating-point
5142 arguments in FPR pairs. The real part goes in the lower register
5143 and the imaginary part goes in the upper register. */
5146 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5149 enum machine_mode inner;
5152 inner = GET_MODE_INNER (mode);
5153 regno = FP_ARG_FIRST + info.reg_offset;
5154 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
5156 /* Real part in registers, imaginary part on stack. */
5157 gcc_assert (info.stack_words == info.reg_words);
5158 return gen_rtx_REG (inner, regno);
5162 gcc_assert (info.stack_words == 0);
5163 real = gen_rtx_EXPR_LIST (VOIDmode,
5164 gen_rtx_REG (inner, regno),
5166 imag = gen_rtx_EXPR_LIST (VOIDmode,
5168 regno + info.reg_words / 2),
5169 GEN_INT (GET_MODE_SIZE (inner)));
5170 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
5174 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
5177 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5180 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
5181 const_tree type, bool named)
5183 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5184 struct mips_arg_info info;
5186 mips_get_arg_info (&info, cum, mode, type, named);
5189 cum->gp_reg_found = true;
5191 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5192 an explanation of what this code does. It assumes that we're using
5193 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5195 if (cum->arg_number < 2 && info.fpr_p)
5196 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5198 /* Advance the register count. This has the effect of setting
5199 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5200 argument required us to skip the final GPR and pass the whole
5201 argument on the stack. */
5202 if (mips_abi != ABI_EABI || !info.fpr_p)
5203 cum->num_gprs = info.reg_offset + info.reg_words;
5204 else if (info.reg_words > 0)
5205 cum->num_fprs += MAX_FPRS_PER_FMT;
5207 /* Advance the stack word count. */
5208 if (info.stack_words > 0)
5209 cum->stack_words = info.stack_offset + info.stack_words;
5214 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5217 mips_arg_partial_bytes (cumulative_args_t cum,
5218 enum machine_mode mode, tree type, bool named)
5220 struct mips_arg_info info;
5222 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5223 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5226 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5227 least PARM_BOUNDARY bits of alignment, but will be given anything up
5228 to STACK_BOUNDARY bits if the type requires it. */
5231 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5233 unsigned int alignment;
5235 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5236 if (alignment < PARM_BOUNDARY)
5237 alignment = PARM_BOUNDARY;
5238 if (alignment > STACK_BOUNDARY)
5239 alignment = STACK_BOUNDARY;
5243 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5244 upward rather than downward. In other words, return true if the
5245 first byte of the stack slot has useful data, false if the last
5249 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5251 /* On little-endian targets, the first byte of every stack argument
5252 is passed in the first byte of the stack slot. */
5253 if (!BYTES_BIG_ENDIAN)
5256 /* Otherwise, integral types are padded downward: the last byte of a
5257 stack argument is passed in the last byte of the stack slot. */
5259 ? (INTEGRAL_TYPE_P (type)
5260 || POINTER_TYPE_P (type)
5261 || FIXED_POINT_TYPE_P (type))
5262 : (SCALAR_INT_MODE_P (mode)
5263 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5266 /* Big-endian o64 pads floating-point arguments downward. */
5267 if (mips_abi == ABI_O64)
5268 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5271 /* Other types are padded upward for o32, o64, n32 and n64. */
5272 if (mips_abi != ABI_EABI)
5275 /* Arguments smaller than a stack slot are padded downward. */
5276 if (mode != BLKmode)
5277 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5279 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5282 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5283 if the least significant byte of the register has useful data. Return
5284 the opposite if the most significant byte does. */
5287 mips_pad_reg_upward (enum machine_mode mode, tree type)
5289 /* No shifting is required for floating-point arguments. */
5290 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5291 return !BYTES_BIG_ENDIAN;
5293 /* Otherwise, apply the same padding to register arguments as we do
5294 to stack arguments. */
5295 return mips_pad_arg_upward (mode, type);
5298 /* Return nonzero when an argument must be passed by reference. */
5301 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5302 enum machine_mode mode, const_tree type,
5303 bool named ATTRIBUTE_UNUSED)
5305 if (mips_abi == ABI_EABI)
5309 /* ??? How should SCmode be handled? */
5310 if (mode == DImode || mode == DFmode
5311 || mode == DQmode || mode == UDQmode
5312 || mode == DAmode || mode == UDAmode)
5315 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5316 return size == -1 || size > UNITS_PER_WORD;
5320 /* If we have a variable-sized parameter, we have no choice. */
5321 return targetm.calls.must_pass_in_stack (mode, type);
5325 /* Implement TARGET_CALLEE_COPIES. */
5328 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5329 enum machine_mode mode ATTRIBUTE_UNUSED,
5330 const_tree type ATTRIBUTE_UNUSED, bool named)
5332 return mips_abi == ABI_EABI && named;
5335 /* See whether VALTYPE is a record whose fields should be returned in
5336 floating-point registers. If so, return the number of fields and
5337 list them in FIELDS (which should have two elements). Return 0
5340 For n32 & n64, a structure with one or two fields is returned in
5341 floating-point registers as long as every field has a floating-point
5345 mips_fpr_return_fields (const_tree valtype, tree *fields)
5353 if (TREE_CODE (valtype) != RECORD_TYPE)
5357 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5359 if (TREE_CODE (field) != FIELD_DECL)
5362 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5368 fields[i++] = field;
5373 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5374 a value in the most significant part of $2/$3 if:
5376 - the target is big-endian;
5378 - the value has a structure or union type (we generalize this to
5379 cover aggregates from other languages too); and
5381 - the structure is not returned in floating-point registers. */
5384 mips_return_in_msb (const_tree valtype)
5388 return (TARGET_NEWABI
5389 && TARGET_BIG_ENDIAN
5390 && AGGREGATE_TYPE_P (valtype)
5391 && mips_fpr_return_fields (valtype, fields) == 0);
5394 /* Return true if the function return value MODE will get returned in a
5395 floating-point register. */
5398 mips_return_mode_in_fpr_p (enum machine_mode mode)
5400 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5402 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5403 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5406 /* Return the representation of an FPR return register when the
5407 value being returned in FP_RETURN has mode VALUE_MODE and the
5408 return type itself has mode TYPE_MODE. On NewABI targets,
5409 the two modes may be different for structures like:
5411 struct __attribute__((packed)) foo { float f; }
5413 where we return the SFmode value of "f" in FP_RETURN, but where
5414 the structure itself has mode BLKmode. */
5417 mips_return_fpr_single (enum machine_mode type_mode,
5418 enum machine_mode value_mode)
5422 x = gen_rtx_REG (value_mode, FP_RETURN);
5423 if (type_mode != value_mode)
5425 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5426 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5431 /* Return a composite value in a pair of floating-point registers.
5432 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5433 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5436 For n32 & n64, $f0 always holds the first value and $f2 the second.
5437 Otherwise the values are packed together as closely as possible. */
5440 mips_return_fpr_pair (enum machine_mode mode,
5441 enum machine_mode mode1, HOST_WIDE_INT offset1,
5442 enum machine_mode mode2, HOST_WIDE_INT offset2)
5446 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5447 return gen_rtx_PARALLEL
5450 gen_rtx_EXPR_LIST (VOIDmode,
5451 gen_rtx_REG (mode1, FP_RETURN),
5453 gen_rtx_EXPR_LIST (VOIDmode,
5454 gen_rtx_REG (mode2, FP_RETURN + inc),
5455 GEN_INT (offset2))));
5459 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5460 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5461 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5464 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5465 enum machine_mode mode)
5473 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5474 func = fn_decl_or_type;
5478 mode = TYPE_MODE (valtype);
5479 unsigned_p = TYPE_UNSIGNED (valtype);
5481 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5482 return values, promote the mode here too. */
5483 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5485 /* Handle structures whose fields are returned in $f0/$f2. */
5486 switch (mips_fpr_return_fields (valtype, fields))
5489 return mips_return_fpr_single (mode,
5490 TYPE_MODE (TREE_TYPE (fields[0])));
5493 return mips_return_fpr_pair (mode,
5494 TYPE_MODE (TREE_TYPE (fields[0])),
5495 int_byte_position (fields[0]),
5496 TYPE_MODE (TREE_TYPE (fields[1])),
5497 int_byte_position (fields[1]));
5500 /* If a value is passed in the most significant part of a register, see
5501 whether we have to round the mode up to a whole number of words. */
5502 if (mips_return_in_msb (valtype))
5504 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5505 if (size % UNITS_PER_WORD != 0)
5507 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5508 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5512 /* For EABI, the class of return register depends entirely on MODE.
5513 For example, "struct { some_type x; }" and "union { some_type x; }"
5514 are returned in the same way as a bare "some_type" would be.
5515 Other ABIs only use FPRs for scalar, complex or vector types. */
5516 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5517 return gen_rtx_REG (mode, GP_RETURN);
5522 /* Handle long doubles for n32 & n64. */
5524 return mips_return_fpr_pair (mode,
5526 DImode, GET_MODE_SIZE (mode) / 2);
5528 if (mips_return_mode_in_fpr_p (mode))
5530 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5531 return mips_return_fpr_pair (mode,
5532 GET_MODE_INNER (mode), 0,
5533 GET_MODE_INNER (mode),
5534 GET_MODE_SIZE (mode) / 2);
5536 return gen_rtx_REG (mode, FP_RETURN);
5540 return gen_rtx_REG (mode, GP_RETURN);
5543 /* Implement TARGET_FUNCTION_VALUE. */
5546 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5547 bool outgoing ATTRIBUTE_UNUSED)
5549 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5552 /* Implement TARGET_LIBCALL_VALUE. */
5555 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5557 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5560 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5562 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5563 Currently, R2 and F0 are only implemented here (C has no complex type). */
5566 mips_function_value_regno_p (const unsigned int regno)
5568 if (regno == GP_RETURN
5569 || regno == FP_RETURN
5570 || (LONG_DOUBLE_TYPE_SIZE == 128
5571 && FP_RETURN != GP_RETURN
5572 && regno == FP_RETURN + 2))
5578 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5579 all BLKmode objects are returned in memory. Under the n32, n64
5580 and embedded ABIs, small structures are returned in a register.
5581 Objects with varying size must still be returned in memory, of
5585 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5587 return (TARGET_OLDABI
5588 ? TYPE_MODE (type) == BLKmode
5589 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5592 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5595 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5596 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5599 CUMULATIVE_ARGS local_cum;
5600 int gp_saved, fp_saved;
5602 /* The caller has advanced CUM up to, but not beyond, the last named
5603 argument. Advance a local copy of CUM past the last "real" named
5604 argument, to find out how many registers are left over. */
5605 local_cum = *get_cumulative_args (cum);
5606 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5609 /* Found out how many registers we need to save. */
5610 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5611 fp_saved = (EABI_FLOAT_VARARGS_P
5612 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5621 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5622 REG_PARM_STACK_SPACE (cfun->decl)
5623 - gp_saved * UNITS_PER_WORD);
5624 mem = gen_frame_mem (BLKmode, ptr);
5625 set_mem_alias_set (mem, get_varargs_alias_set ());
5627 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5632 /* We can't use move_block_from_reg, because it will use
5634 enum machine_mode mode;
5637 /* Set OFF to the offset from virtual_incoming_args_rtx of
5638 the first float register. The FP save area lies below
5639 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5640 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5641 off -= fp_saved * UNITS_PER_FPREG;
5643 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5645 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5646 i += MAX_FPRS_PER_FMT)
5650 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5651 mem = gen_frame_mem (mode, ptr);
5652 set_mem_alias_set (mem, get_varargs_alias_set ());
5653 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5654 off += UNITS_PER_HWFPVALUE;
5658 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5659 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5660 + fp_saved * UNITS_PER_FPREG);
5663 /* Implement TARGET_BUILTIN_VA_LIST. */
5666 mips_build_builtin_va_list (void)
5668 if (EABI_FLOAT_VARARGS_P)
5670 /* We keep 3 pointers, and two offsets.
5672 Two pointers are to the overflow area, which starts at the CFA.
5673 One of these is constant, for addressing into the GPR save area
5674 below it. The other is advanced up the stack through the
5677 The third pointer is to the bottom of the GPR save area.
5678 Since the FPR save area is just below it, we can address
5679 FPR slots off this pointer.
5681 We also keep two one-byte offsets, which are to be subtracted
5682 from the constant pointers to yield addresses in the GPR and
5683 FPR save areas. These are downcounted as float or non-float
5684 arguments are used, and when they get to zero, the argument
5685 must be obtained from the overflow region. */
5686 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5689 record = lang_hooks.types.make_type (RECORD_TYPE);
5691 f_ovfl = build_decl (BUILTINS_LOCATION,
5692 FIELD_DECL, get_identifier ("__overflow_argptr"),
5694 f_gtop = build_decl (BUILTINS_LOCATION,
5695 FIELD_DECL, get_identifier ("__gpr_top"),
5697 f_ftop = build_decl (BUILTINS_LOCATION,
5698 FIELD_DECL, get_identifier ("__fpr_top"),
5700 f_goff = build_decl (BUILTINS_LOCATION,
5701 FIELD_DECL, get_identifier ("__gpr_offset"),
5702 unsigned_char_type_node);
5703 f_foff = build_decl (BUILTINS_LOCATION,
5704 FIELD_DECL, get_identifier ("__fpr_offset"),
5705 unsigned_char_type_node);
5706 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5707 warn on every user file. */
5708 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5709 array = build_array_type (unsigned_char_type_node,
5710 build_index_type (index));
5711 f_res = build_decl (BUILTINS_LOCATION,
5712 FIELD_DECL, get_identifier ("__reserved"), array);
5714 DECL_FIELD_CONTEXT (f_ovfl) = record;
5715 DECL_FIELD_CONTEXT (f_gtop) = record;
5716 DECL_FIELD_CONTEXT (f_ftop) = record;
5717 DECL_FIELD_CONTEXT (f_goff) = record;
5718 DECL_FIELD_CONTEXT (f_foff) = record;
5719 DECL_FIELD_CONTEXT (f_res) = record;
5721 TYPE_FIELDS (record) = f_ovfl;
5722 DECL_CHAIN (f_ovfl) = f_gtop;
5723 DECL_CHAIN (f_gtop) = f_ftop;
5724 DECL_CHAIN (f_ftop) = f_goff;
5725 DECL_CHAIN (f_goff) = f_foff;
5726 DECL_CHAIN (f_foff) = f_res;
5728 layout_type (record);
5732 /* Otherwise, we use 'void *'. */
5733 return ptr_type_node;
5736 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5739 mips_va_start (tree valist, rtx nextarg)
5741 if (EABI_FLOAT_VARARGS_P)
5743 const CUMULATIVE_ARGS *cum;
5744 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5745 tree ovfl, gtop, ftop, goff, foff;
5747 int gpr_save_area_size;
5748 int fpr_save_area_size;
5751 cum = &crtl->args.info;
5753 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5755 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5757 f_ovfl = TYPE_FIELDS (va_list_type_node);
5758 f_gtop = DECL_CHAIN (f_ovfl);
5759 f_ftop = DECL_CHAIN (f_gtop);
5760 f_goff = DECL_CHAIN (f_ftop);
5761 f_foff = DECL_CHAIN (f_goff);
5763 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5765 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5767 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5769 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5771 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5774 /* Emit code to initialize OVFL, which points to the next varargs
5775 stack argument. CUM->STACK_WORDS gives the number of stack
5776 words used by named arguments. */
5777 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5778 if (cum->stack_words > 0)
5779 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5780 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5781 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5783 /* Emit code to initialize GTOP, the top of the GPR save area. */
5784 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5785 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5786 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5788 /* Emit code to initialize FTOP, the top of the FPR save area.
5789 This address is gpr_save_area_bytes below GTOP, rounded
5790 down to the next fp-aligned boundary. */
5791 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5792 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5793 fpr_offset &= -UNITS_PER_FPVALUE;
5795 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
5796 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
5797 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5799 /* Emit code to initialize GOFF, the offset from GTOP of the
5800 next GPR argument. */
5801 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
5802 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
5803 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5805 /* Likewise emit code to initialize FOFF, the offset from FTOP
5806 of the next FPR argument. */
5807 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
5808 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
5809 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5813 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
5814 std_expand_builtin_va_start (valist, nextarg);
5818 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
5822 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5825 tree addr, t, type_size, rounded_size, valist_tmp;
5826 unsigned HOST_WIDE_INT align, boundary;
5829 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
5831 type = build_pointer_type (type);
5833 align = PARM_BOUNDARY / BITS_PER_UNIT;
5834 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
5836 /* When we align parameter on stack for caller, if the parameter
5837 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
5838 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
5839 here with caller. */
5840 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
5841 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
5843 boundary /= BITS_PER_UNIT;
5845 /* Hoist the valist value into a temporary for the moment. */
5846 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
5848 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
5849 requires greater alignment, we must perform dynamic alignment. */
5850 if (boundary > align)
5852 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5853 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
5854 gimplify_and_add (t, pre_p);
5856 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
5857 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
5859 build_int_cst (TREE_TYPE (valist), -boundary)));
5860 gimplify_and_add (t, pre_p);
5865 /* If the actual alignment is less than the alignment of the type,
5866 adjust the type accordingly so that we don't assume strict alignment
5867 when dereferencing the pointer. */
5868 boundary *= BITS_PER_UNIT;
5869 if (boundary < TYPE_ALIGN (type))
5871 type = build_variant_type_copy (type);
5872 TYPE_ALIGN (type) = boundary;
5875 /* Compute the rounded size of the type. */
5876 type_size = size_in_bytes (type);
5877 rounded_size = round_up (type_size, align);
5879 /* Reduce rounded_size so it's sharable with the postqueue. */
5880 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
5884 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
5886 /* Small args are padded downward. */
5887 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
5888 rounded_size, size_int (align));
5889 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
5890 size_binop (MINUS_EXPR, rounded_size, type_size));
5891 addr = fold_build_pointer_plus (addr, t);
5894 /* Compute new value for AP. */
5895 t = fold_build_pointer_plus (valist_tmp, rounded_size);
5896 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5897 gimplify_and_add (t, pre_p);
5899 addr = fold_convert (build_pointer_type (type), addr);
5902 addr = build_va_arg_indirect_ref (addr);
5904 return build_va_arg_indirect_ref (addr);
5907 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5910 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
5916 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5918 type = build_pointer_type (type);
5920 if (!EABI_FLOAT_VARARGS_P)
5921 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5924 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5925 tree ovfl, top, off, align;
5926 HOST_WIDE_INT size, rsize, osize;
5929 f_ovfl = TYPE_FIELDS (va_list_type_node);
5930 f_gtop = DECL_CHAIN (f_ovfl);
5931 f_ftop = DECL_CHAIN (f_gtop);
5932 f_goff = DECL_CHAIN (f_ftop);
5933 f_foff = DECL_CHAIN (f_goff);
5937 TOP be the top of the GPR or FPR save area;
5938 OFF be the offset from TOP of the next register;
5939 ADDR_RTX be the address of the argument;
5940 SIZE be the number of bytes in the argument type;
5941 RSIZE be the number of bytes used to store the argument
5942 when it's in the register save area; and
5943 OSIZE be the number of bytes used to store it when it's
5944 in the stack overflow area.
5946 The code we want is:
5948 1: off &= -rsize; // round down
5951 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5956 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5957 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5961 [1] and [9] can sometimes be optimized away. */
5963 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5965 size = int_size_in_bytes (type);
5967 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
5968 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
5970 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
5971 unshare_expr (valist), f_ftop, NULL_TREE);
5972 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
5973 unshare_expr (valist), f_foff, NULL_TREE);
5975 /* When va_start saves FPR arguments to the stack, each slot
5976 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5977 argument's precision. */
5978 rsize = UNITS_PER_HWFPVALUE;
5980 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5981 (= PARM_BOUNDARY bits). This can be different from RSIZE
5984 (1) On 32-bit targets when TYPE is a structure such as:
5986 struct s { float f; };
5988 Such structures are passed in paired FPRs, so RSIZE
5989 will be 8 bytes. However, the structure only takes
5990 up 4 bytes of memory, so OSIZE will only be 4.
5992 (2) In combinations such as -mgp64 -msingle-float
5993 -fshort-double. Doubles passed in registers will then take
5994 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5995 stack take up UNITS_PER_WORD bytes. */
5996 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
6000 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
6001 unshare_expr (valist), f_gtop, NULL_TREE);
6002 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
6003 unshare_expr (valist), f_goff, NULL_TREE);
6004 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6005 if (rsize > UNITS_PER_WORD)
6007 /* [1] Emit code for: off &= -rsize. */
6008 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
6009 build_int_cst (TREE_TYPE (off), -rsize));
6010 gimplify_assign (unshare_expr (off), t, pre_p);
6015 /* [2] Emit code to branch if off == 0. */
6016 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
6017 build_int_cst (TREE_TYPE (off), 0));
6018 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
6020 /* [5] Emit code for: off -= rsize. We do this as a form of
6021 post-decrement not available to C. */
6022 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
6023 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
6025 /* [4] Emit code for:
6026 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6027 t = fold_convert (sizetype, t);
6028 t = fold_build1 (NEGATE_EXPR, sizetype, t);
6029 t = fold_build_pointer_plus (top, t);
6030 if (BYTES_BIG_ENDIAN && rsize > size)
6031 t = fold_build_pointer_plus_hwi (t, rsize - size);
6032 COND_EXPR_THEN (addr) = t;
6034 if (osize > UNITS_PER_WORD)
6036 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6037 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
6038 u = build_int_cst (TREE_TYPE (t), -osize);
6039 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6040 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
6041 unshare_expr (ovfl), t);
6046 /* [10, 11] Emit code for:
6047 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6049 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
6050 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
6051 if (BYTES_BIG_ENDIAN && osize > size)
6052 t = fold_build_pointer_plus_hwi (t, osize - size);
6054 /* String [9] and [10, 11] together. */
6056 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
6057 COND_EXPR_ELSE (addr) = t;
6059 addr = fold_convert (build_pointer_type (type), addr);
6060 addr = build_va_arg_indirect_ref (addr);
6064 addr = build_va_arg_indirect_ref (addr);
6069 /* Declare a unique, locally-binding function called NAME, then start
6073 mips_start_unique_function (const char *name)
6077 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6078 get_identifier (name),
6079 build_function_type_list (void_type_node, NULL_TREE));
6080 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
6081 NULL_TREE, void_type_node);
6082 TREE_PUBLIC (decl) = 1;
6083 TREE_STATIC (decl) = 1;
6085 DECL_COMDAT_GROUP (decl) = DECL_ASSEMBLER_NAME (decl);
6087 targetm.asm_out.unique_section (decl, 0);
6088 switch_to_section (get_named_section (decl, NULL, 0));
6090 targetm.asm_out.globalize_label (asm_out_file, name);
6091 fputs ("\t.hidden\t", asm_out_file);
6092 assemble_name (asm_out_file, name);
6093 putc ('\n', asm_out_file);
6096 /* Start a definition of function NAME. MIPS16_P indicates whether the
6097 function contains MIPS16 code. */
6100 mips_start_function_definition (const char *name, bool mips16_p)
6103 fprintf (asm_out_file, "\t.set\tmips16\n");
6105 fprintf (asm_out_file, "\t.set\tnomips16\n");
6107 if (!flag_inhibit_size_directive)
6109 fputs ("\t.ent\t", asm_out_file);
6110 assemble_name (asm_out_file, name);
6111 fputs ("\n", asm_out_file);
6114 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
6116 /* Start the definition proper. */
6117 assemble_name (asm_out_file, name);
6118 fputs (":\n", asm_out_file);
6121 /* End a function definition started by mips_start_function_definition. */
6124 mips_end_function_definition (const char *name)
6126 if (!flag_inhibit_size_directive)
6128 fputs ("\t.end\t", asm_out_file);
6129 assemble_name (asm_out_file, name);
6130 fputs ("\n", asm_out_file);
6134 /* Output a definition of the __mips16_rdhwr function. */
6137 mips_output_mips16_rdhwr (void)
6141 name = "__mips16_rdhwr";
6142 mips_start_unique_function (name);
6143 mips_start_function_definition (name, false);
6144 fprintf (asm_out_file,
6146 "\t.set\tmips32r2\n"
6147 "\t.set\tnoreorder\n"
6151 mips_end_function_definition (name);
6154 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6157 mips_ok_for_lazy_binding_p (rtx x)
6159 return (TARGET_USE_GOT
6160 && GET_CODE (x) == SYMBOL_REF
6161 && !SYMBOL_REF_BIND_NOW_P (x)
6162 && !mips_symbol_binds_local_p (x));
6165 /* Load function address ADDR into register DEST. TYPE is as for
6166 mips_expand_call. Return true if we used an explicit lazy-binding
6170 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
6172 /* If we're generating PIC, and this call is to a global function,
6173 try to allow its address to be resolved lazily. This isn't
6174 possible for sibcalls when $gp is call-saved because the value
6175 of $gp on entry to the stub would be our caller's gp, not ours. */
6176 if (TARGET_EXPLICIT_RELOCS
6177 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
6178 && mips_ok_for_lazy_binding_p (addr))
6180 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
6181 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6186 mips_emit_move (dest, addr);
6191 /* Each locally-defined hard-float MIPS16 function has a local symbol
6192 associated with it. This hash table maps the function symbol (FUNC)
6193 to the local symbol (LOCAL). */
6194 struct GTY(()) mips16_local_alias {
6198 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
6200 /* Hash table callbacks for mips16_local_aliases. */
6203 mips16_local_aliases_hash (const void *entry)
6205 const struct mips16_local_alias *alias;
6207 alias = (const struct mips16_local_alias *) entry;
6208 return htab_hash_string (XSTR (alias->func, 0));
6212 mips16_local_aliases_eq (const void *entry1, const void *entry2)
6214 const struct mips16_local_alias *alias1, *alias2;
6216 alias1 = (const struct mips16_local_alias *) entry1;
6217 alias2 = (const struct mips16_local_alias *) entry2;
6218 return rtx_equal_p (alias1->func, alias2->func);
6221 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6222 Return a local alias for it, creating a new one if necessary. */
6225 mips16_local_alias (rtx func)
6227 struct mips16_local_alias *alias, tmp_alias;
6230 /* Create the hash table if this is the first call. */
6231 if (mips16_local_aliases == NULL)
6232 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
6233 mips16_local_aliases_eq, NULL);
6235 /* Look up the function symbol, creating a new entry if need be. */
6236 tmp_alias.func = func;
6237 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
6238 gcc_assert (slot != NULL);
6240 alias = (struct mips16_local_alias *) *slot;
6243 const char *func_name, *local_name;
6246 /* Create a new SYMBOL_REF for the local symbol. The choice of
6247 __fn_local_* is based on the __fn_stub_* names that we've
6248 traditionally used for the non-MIPS16 stub. */
6249 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6250 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6251 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6252 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6254 /* Create a new structure to represent the mapping. */
6255 alias = ggc_alloc_mips16_local_alias ();
6257 alias->local = local;
6260 return alias->local;
6263 /* A chained list of functions for which mips16_build_call_stub has already
6264 generated a stub. NAME is the name of the function and FP_RET_P is true
6265 if the function returns a value in floating-point registers. */
6266 struct mips16_stub {
6267 struct mips16_stub *next;
6271 static struct mips16_stub *mips16_stubs;
6273 /* Return the two-character string that identifies floating-point
6274 return mode MODE in the name of a MIPS16 function stub. */
6277 mips16_call_stub_mode_suffix (enum machine_mode mode)
6281 else if (mode == DFmode)
6283 else if (mode == SCmode)
6285 else if (mode == DCmode)
6287 else if (mode == V2SFmode)
6293 /* Write instructions to move a 32-bit value between general register
6294 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6295 from GPREG to FPREG and 'f' to move in the opposite direction. */
6298 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6300 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6301 reg_names[gpreg], reg_names[fpreg]);
6304 /* Likewise for 64-bit values. */
6307 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6310 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6311 reg_names[gpreg], reg_names[fpreg]);
6312 else if (TARGET_FLOAT64)
6314 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6315 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6316 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6317 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6321 /* Move the least-significant word. */
6322 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6323 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6324 /* ...then the most significant word. */
6325 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6326 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6330 /* Write out code to move floating-point arguments into or out of
6331 general registers. FP_CODE is the code describing which arguments
6332 are present (see the comment above the definition of CUMULATIVE_ARGS
6333 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6336 mips_output_args_xfer (int fp_code, char direction)
6338 unsigned int gparg, fparg, f;
6339 CUMULATIVE_ARGS cum;
6341 /* This code only works for o32 and o64. */
6342 gcc_assert (TARGET_OLDABI);
6344 mips_init_cumulative_args (&cum, NULL);
6346 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6348 enum machine_mode mode;
6349 struct mips_arg_info info;
6353 else if ((f & 3) == 2)
6358 mips_get_arg_info (&info, &cum, mode, NULL, true);
6359 gparg = mips_arg_regno (&info, false);
6360 fparg = mips_arg_regno (&info, true);
6363 mips_output_32bit_xfer (direction, gparg, fparg);
6365 mips_output_64bit_xfer (direction, gparg, fparg);
6367 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6371 /* Write a MIPS16 stub for the current function. This stub is used
6372 for functions which take arguments in the floating-point registers.
6373 It is normal-mode code that moves the floating-point arguments
6374 into the general registers and then jumps to the MIPS16 code. */
6377 mips16_build_function_stub (void)
6379 const char *fnname, *alias_name, *separator;
6380 char *secname, *stubname;
6385 /* Create the name of the stub, and its unique section. */
6386 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6387 alias = mips16_local_alias (symbol);
6389 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6390 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6391 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6392 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6394 /* Build a decl for the stub. */
6395 stubdecl = build_decl (BUILTINS_LOCATION,
6396 FUNCTION_DECL, get_identifier (stubname),
6397 build_function_type_list (void_type_node, NULL_TREE));
6398 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6399 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6400 RESULT_DECL, NULL_TREE, void_type_node);
6402 /* Output a comment. */
6403 fprintf (asm_out_file, "\t# Stub function for %s (",
6404 current_function_name ());
6406 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6408 fprintf (asm_out_file, "%s%s", separator,
6409 (f & 3) == 1 ? "float" : "double");
6412 fprintf (asm_out_file, ")\n");
6414 /* Start the function definition. */
6415 assemble_start_function (stubdecl, stubname);
6416 mips_start_function_definition (stubname, false);
6418 /* If generating pic2 code, either set up the global pointer or
6420 if (TARGET_ABICALLS_PIC2)
6422 if (TARGET_ABSOLUTE_ABICALLS)
6423 fprintf (asm_out_file, "\t.option\tpic0\n");
6426 output_asm_insn ("%(.cpload\t%^%)", NULL);
6427 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6428 target function is. Use a local GOT access when loading the
6429 symbol, to cut down on the number of unnecessary GOT entries
6430 for stubs that aren't needed. */
6431 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6436 /* Load the address of the MIPS16 function into $25. Do this first so
6437 that targets with coprocessor interlocks can use an MFC1 to fill the
6439 output_asm_insn ("la\t%^,%0", &symbol);
6441 /* Move the arguments from floating-point registers to general registers. */
6442 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6444 /* Jump to the MIPS16 function. */
6445 output_asm_insn ("jr\t%^", NULL);
6447 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6448 fprintf (asm_out_file, "\t.option\tpic2\n");
6450 mips_end_function_definition (stubname);
6452 /* If the linker needs to create a dynamic symbol for the target
6453 function, it will associate the symbol with the stub (which,
6454 unlike the target function, follows the proper calling conventions).
6455 It is therefore useful to have a local alias for the target function,
6456 so that it can still be identified as MIPS16 code. As an optimization,
6457 this symbol can also be used for indirect MIPS16 references from
6458 within this file. */
6459 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6461 switch_to_section (function_section (current_function_decl));
6464 /* The current function is a MIPS16 function that returns a value in an FPR.
6465 Copy the return value from its soft-float to its hard-float location.
6466 libgcc2 has special non-MIPS16 helper functions for each case. */
6469 mips16_copy_fpr_return_value (void)
6471 rtx fn, insn, retval;
6473 enum machine_mode return_mode;
6476 return_type = DECL_RESULT (current_function_decl);
6477 return_mode = DECL_MODE (return_type);
6479 name = ACONCAT (("__mips16_ret_",
6480 mips16_call_stub_mode_suffix (return_mode),
6482 fn = mips16_stub_function (name);
6484 /* The function takes arguments in $2 (and possibly $3), so calls
6485 to it cannot be lazily bound. */
6486 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6488 /* Model the call as something that takes the GPR return value as
6489 argument and returns an "updated" value. */
6490 retval = gen_rtx_REG (return_mode, GP_RETURN);
6491 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6492 const0_rtx, NULL_RTX, false);
6493 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6496 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6497 RETVAL is the location of the return value, or null if this is
6498 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6499 arguments and FP_CODE is the code built by mips_function_arg;
6500 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6502 There are three alternatives:
6504 - If a stub was needed, emit the call and return the call insn itself.
6506 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6507 to the new target and return null.
6509 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6512 A stub is needed for calls to functions that, in normal mode,
6513 receive arguments in FPRs or return values in FPRs. The stub
6514 copies the arguments from their soft-float positions to their
6515 hard-float positions, calls the real function, then copies the
6516 return value from its hard-float position to its soft-float
6519 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6520 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6521 automatically redirects the JAL to the stub, otherwise the JAL
6522 continues to call FN directly. */
6525 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6529 struct mips16_stub *l;
6532 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6533 we were invoked with the -msoft-float option. */
6534 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6537 /* Figure out whether the value might come back in a floating-point
6539 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6541 /* We don't need to do anything if there were no floating-point
6542 arguments and the value will not be returned in a floating-point
6544 if (fp_code == 0 && !fp_ret_p)
6547 /* We don't need to do anything if this is a call to a special
6548 MIPS16 support function. */
6550 if (mips16_stub_function_p (fn))
6553 /* If we're calling a locally-defined MIPS16 function, we know that
6554 it will return values in both the "soft-float" and "hard-float"
6555 registers. There is no need to use a stub to move the latter
6557 if (fp_code == 0 && mips16_local_function_p (fn))
6560 /* This code will only work for o32 and o64 abis. The other ABI's
6561 require more sophisticated support. */
6562 gcc_assert (TARGET_OLDABI);
6564 /* If we're calling via a function pointer, use one of the magic
6565 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6566 Each stub expects the function address to arrive in register $2. */
6567 if (GET_CODE (fn) != SYMBOL_REF
6568 || !call_insn_operand (fn, VOIDmode))
6571 rtx stub_fn, insn, addr;
6574 /* If this is a locally-defined and locally-binding function,
6575 avoid the stub by calling the local alias directly. */
6576 if (mips16_local_function_p (fn))
6578 *fn_ptr = mips16_local_alias (fn);
6582 /* Create a SYMBOL_REF for the libgcc.a function. */
6584 sprintf (buf, "__mips16_call_stub_%s_%d",
6585 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6588 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6589 stub_fn = mips16_stub_function (buf);
6591 /* The function uses $2 as an argument, so calls to it
6592 cannot be lazily bound. */
6593 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6595 /* Load the target function into $2. */
6596 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6597 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6599 /* Emit the call. */
6600 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6601 args_size, NULL_RTX, lazy_p);
6603 /* Tell GCC that this call does indeed use the value of $2. */
6604 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6606 /* If we are handling a floating-point return value, we need to
6607 save $18 in the function prologue. Putting a note on the
6608 call will mean that df_regs_ever_live_p ($18) will be true if the
6609 call is not eliminated, and we can check that in the prologue
6612 CALL_INSN_FUNCTION_USAGE (insn) =
6613 gen_rtx_EXPR_LIST (VOIDmode,
6614 gen_rtx_CLOBBER (VOIDmode,
6615 gen_rtx_REG (word_mode, 18)),
6616 CALL_INSN_FUNCTION_USAGE (insn));
6621 /* We know the function we are going to call. If we have already
6622 built a stub, we don't need to do anything further. */
6623 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6624 for (l = mips16_stubs; l != NULL; l = l->next)
6625 if (strcmp (l->name, fnname) == 0)
6630 const char *separator;
6631 char *secname, *stubname;
6632 tree stubid, stubdecl;
6635 /* If the function does not return in FPRs, the special stub
6639 If the function does return in FPRs, the stub section is named
6640 .mips16.call.fp.FNNAME
6642 Build a decl for the stub. */
6643 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6645 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6647 stubid = get_identifier (stubname);
6648 stubdecl = build_decl (BUILTINS_LOCATION,
6649 FUNCTION_DECL, stubid,
6650 build_function_type_list (void_type_node,
6652 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
6653 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6654 RESULT_DECL, NULL_TREE,
6657 /* Output a comment. */
6658 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6660 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6664 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6666 fprintf (asm_out_file, "%s%s", separator,
6667 (f & 3) == 1 ? "float" : "double");
6670 fprintf (asm_out_file, ")\n");
6672 /* Start the function definition. */
6673 assemble_start_function (stubdecl, stubname);
6674 mips_start_function_definition (stubname, false);
6678 fprintf (asm_out_file, "\t.cfi_startproc\n");
6680 /* Create a fake CFA 4 bytes below the stack pointer.
6681 This works around unwinders (like libgcc's) that expect
6682 the CFA for non-signal frames to be unique. */
6683 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6685 /* "Save" $sp in itself so we don't use the fake CFA.
6686 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6687 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6691 /* Load the address of the MIPS16 function into $25. Do this
6692 first so that targets with coprocessor interlocks can use
6693 an MFC1 to fill the delay slot. */
6694 if (TARGET_EXPLICIT_RELOCS)
6696 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6697 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6700 output_asm_insn ("la\t%^,%0", &fn);
6703 /* Move the arguments from general registers to floating-point
6705 mips_output_args_xfer (fp_code, 't');
6709 /* Save the return address in $18 and call the non-MIPS16 function.
6710 The stub's caller knows that $18 might be clobbered, even though
6711 $18 is usually a call-saved register. */
6712 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6713 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6714 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6715 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6717 /* Move the result from floating-point registers to
6718 general registers. */
6719 switch (GET_MODE (retval))
6722 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6724 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6726 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6727 TARGET_LITTLE_ENDIAN
6728 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6730 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6732 /* On 64-bit targets, complex floats are returned in
6733 a single GPR, such that "sd" on a suitably-aligned
6734 target would store the value correctly. */
6735 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6736 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6737 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6738 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6739 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6740 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6741 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6742 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6743 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6744 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6745 reg_names[GP_RETURN],
6746 reg_names[GP_RETURN],
6747 reg_names[GP_RETURN + 1]);
6752 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6756 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6757 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6761 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6767 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6768 fprintf (asm_out_file, "\t.cfi_endproc\n");
6772 /* Jump to the previously-loaded address. */
6773 output_asm_insn ("jr\t%^", NULL);
6776 #ifdef ASM_DECLARE_FUNCTION_SIZE
6777 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6780 mips_end_function_definition (stubname);
6782 /* Record this stub. */
6783 l = XNEW (struct mips16_stub);
6784 l->name = xstrdup (fnname);
6785 l->fp_ret_p = fp_ret_p;
6786 l->next = mips16_stubs;
6790 /* If we expect a floating-point return value, but we've built a
6791 stub which does not expect one, then we're in trouble. We can't
6792 use the existing stub, because it won't handle the floating-point
6793 value. We can't build a new stub, because the linker won't know
6794 which stub to use for the various calls in this object file.
6795 Fortunately, this case is illegal, since it means that a function
6796 was declared in two different ways in a single compilation. */
6797 if (fp_ret_p && !l->fp_ret_p)
6798 error ("cannot handle inconsistent calls to %qs", fnname);
6800 if (retval == NULL_RTX)
6801 insn = gen_call_internal_direct (fn, args_size);
6803 insn = gen_call_value_internal_direct (retval, fn, args_size);
6804 insn = mips_emit_call_insn (insn, fn, fn, false);
6806 /* If we are calling a stub which handles a floating-point return
6807 value, we need to arrange to save $18 in the prologue. We do this
6808 by marking the function call as using the register. The prologue
6809 will later see that it is used, and emit code to save it. */
6811 CALL_INSN_FUNCTION_USAGE (insn) =
6812 gen_rtx_EXPR_LIST (VOIDmode,
6813 gen_rtx_CLOBBER (VOIDmode,
6814 gen_rtx_REG (word_mode, 18)),
6815 CALL_INSN_FUNCTION_USAGE (insn));
6820 /* Expand a call of type TYPE. RESULT is where the result will go (null
6821 for "call"s and "sibcall"s), ADDR is the address of the function,
6822 ARGS_SIZE is the size of the arguments and AUX is the value passed
6823 to us by mips_function_arg. LAZY_P is true if this call already
6824 involves a lazily-bound function address (such as when calling
6825 functions through a MIPS16 hard-float stub).
6827 Return the call itself. */
6830 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
6831 rtx args_size, rtx aux, bool lazy_p)
6833 rtx orig_addr, pattern, insn;
6836 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
6837 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
6840 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
6845 if (!call_insn_operand (addr, VOIDmode))
6847 if (type == MIPS_CALL_EPILOGUE)
6848 addr = MIPS_EPILOGUE_TEMP (Pmode);
6850 addr = gen_reg_rtx (Pmode);
6851 lazy_p |= mips_load_call_address (type, addr, orig_addr);
6856 rtx (*fn) (rtx, rtx);
6858 if (type == MIPS_CALL_SIBCALL)
6859 fn = gen_sibcall_internal;
6861 fn = gen_call_internal;
6863 pattern = fn (addr, args_size);
6865 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
6867 /* Handle return values created by mips_return_fpr_pair. */
6868 rtx (*fn) (rtx, rtx, rtx, rtx);
6871 if (type == MIPS_CALL_SIBCALL)
6872 fn = gen_sibcall_value_multiple_internal;
6874 fn = gen_call_value_multiple_internal;
6876 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
6877 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
6878 pattern = fn (reg1, addr, args_size, reg2);
6882 rtx (*fn) (rtx, rtx, rtx);
6884 if (type == MIPS_CALL_SIBCALL)
6885 fn = gen_sibcall_value_internal;
6887 fn = gen_call_value_internal;
6889 /* Handle return values created by mips_return_fpr_single. */
6890 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
6891 result = XEXP (XVECEXP (result, 0, 0), 0);
6892 pattern = fn (result, addr, args_size);
6895 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
6898 /* Split call instruction INSN into a $gp-clobbering call and
6899 (where necessary) an instruction to restore $gp from its save slot.
6900 CALL_PATTERN is the pattern of the new call. */
6903 mips_split_call (rtx insn, rtx call_pattern)
6905 emit_call_insn (call_pattern);
6906 if (!find_reg_note (insn, REG_NORETURN, 0))
6907 /* Pick a temporary register that is suitable for both MIPS16 and
6908 non-MIPS16 code. $4 and $5 are used for returning complex double
6909 values in soft-float code, so $6 is the first suitable candidate. */
6910 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode, GP_ARG_FIRST + 2));
6913 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6916 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
6918 if (!TARGET_SIBCALLS)
6921 /* Interrupt handlers need special epilogue code and therefore can't
6923 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
6926 /* We can't do a sibcall if the called function is a MIPS16 function
6927 because there is no direct "jx" instruction equivalent to "jalx" to
6928 switch the ISA mode. We only care about cases where the sibling
6929 and normal calls would both be direct. */
6931 && mips_use_mips16_mode_p (decl)
6932 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6935 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6936 functions could be MIPS16 ones unless an attribute explicitly tells
6938 if (TARGET_INTERLINK_MIPS16
6940 && (DECL_EXTERNAL (decl) || !targetm.binds_local_p (decl))
6941 && !mips_nomips16_decl_p (decl)
6942 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode))
6949 /* Emit code to move general operand SRC into condition-code
6950 register DEST given that SCRATCH is a scratch TFmode FPR.
6957 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6960 mips_expand_fcc_reload (rtx dest, rtx src, rtx scratch)
6964 /* Change the source to SFmode. */
6966 src = adjust_address (src, SFmode, 0);
6967 else if (REG_P (src) || GET_CODE (src) == SUBREG)
6968 src = gen_rtx_REG (SFmode, true_regnum (src));
6970 fp1 = gen_rtx_REG (SFmode, REGNO (scratch));
6971 fp2 = gen_rtx_REG (SFmode, REGNO (scratch) + MAX_FPRS_PER_FMT);
6973 mips_emit_move (copy_rtx (fp1), src);
6974 mips_emit_move (copy_rtx (fp2), CONST0_RTX (SFmode));
6975 emit_insn (gen_slt_sf (dest, fp2, fp1));
6978 /* Implement MOVE_BY_PIECES_P. */
6981 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
6985 /* movmemsi is meant to generate code that is at least as good as
6986 move_by_pieces. However, movmemsi effectively uses a by-pieces
6987 implementation both for moves smaller than a word and for
6988 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
6989 bytes. We should allow the tree-level optimisers to do such
6990 moves by pieces, as it often exposes other optimization
6991 opportunities. We might as well continue to use movmemsi at
6992 the rtl level though, as it produces better code when
6993 scheduling is disabled (such as at -O). */
6994 if (currently_expanding_to_rtl)
6996 if (align < BITS_PER_WORD)
6997 return size < UNITS_PER_WORD;
6998 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
7000 /* The default value. If this becomes a target hook, we should
7001 call the default definition instead. */
7002 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
7003 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7006 /* Implement STORE_BY_PIECES_P. */
7009 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7011 /* Storing by pieces involves moving constants into registers
7012 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7013 We need to decide whether it is cheaper to load the address of
7014 constant data into a register and use a block move instead. */
7016 /* If the data is only byte aligned, then:
7018 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7019 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7022 (a2) A block move of 4 bytes from aligned source data can use an
7023 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7024 4 SBs that we would generate when storing by pieces. */
7025 if (align <= BITS_PER_UNIT)
7028 /* If the data is 2-byte aligned, then:
7030 (b1) A block move of less than 4 bytes would use a combination of LBs,
7031 LHs, SBs and SHs. We get better code by using single-instruction
7032 LIs, SBs and SHs instead.
7034 (b2) A block move of 4 bytes from aligned source data would again use
7035 an LW/SWL/SWR sequence. In most cases, loading the address of
7036 the source data would require at least one extra instruction.
7037 It is often more efficient to use 2 single-instruction LIs and
7040 (b3) A block move of up to 3 additional bytes would be like (b1).
7042 (b4) A block move of 8 bytes from aligned source data can use two
7043 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7044 sequences are better than the 4 LIs and 4 SHs that we'd generate
7045 when storing by pieces.
7047 The reasoning for higher alignments is similar:
7049 (c1) A block move of less than 4 bytes would be the same as (b1).
7051 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7052 loading the address of the source data would typically require
7053 at least one extra instruction. It is generally better to use
7056 (c3) A block move of up to 3 additional bytes would be like (b1).
7058 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7059 LD/SD sequence, and in these cases we've traditionally preferred
7060 the memory copy over the more bulky constant moves. */
7064 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7065 Assume that the areas do not overlap. */
7068 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
7070 HOST_WIDE_INT offset, delta;
7071 unsigned HOST_WIDE_INT bits;
7073 enum machine_mode mode;
7076 /* Work out how many bits to move at a time. If both operands have
7077 half-word alignment, it is usually better to move in half words.
7078 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7079 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7080 Otherwise move word-sized chunks. */
7081 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
7082 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
7083 bits = BITS_PER_WORD / 2;
7085 bits = BITS_PER_WORD;
7087 mode = mode_for_size (bits, MODE_INT, 0);
7088 delta = bits / BITS_PER_UNIT;
7090 /* Allocate a buffer for the temporary registers. */
7091 regs = XALLOCAVEC (rtx, length / delta);
7093 /* Load as many BITS-sized chunks as possible. Use a normal load if
7094 the source has enough alignment, otherwise use left/right pairs. */
7095 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7097 regs[i] = gen_reg_rtx (mode);
7098 if (MEM_ALIGN (src) >= bits)
7099 mips_emit_move (regs[i], adjust_address (src, mode, offset));
7102 rtx part = adjust_address (src, BLKmode, offset);
7103 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
7108 /* Copy the chunks to the destination. */
7109 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7110 if (MEM_ALIGN (dest) >= bits)
7111 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
7114 rtx part = adjust_address (dest, BLKmode, offset);
7115 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
7119 /* Mop up any left-over bytes. */
7120 if (offset < length)
7122 src = adjust_address (src, BLKmode, offset);
7123 dest = adjust_address (dest, BLKmode, offset);
7124 move_by_pieces (dest, src, length - offset,
7125 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
7129 /* Helper function for doing a loop-based block operation on memory
7130 reference MEM. Each iteration of the loop will operate on LENGTH
7133 Create a new base register for use within the loop and point it to
7134 the start of MEM. Create a new memory reference that uses this
7135 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7138 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
7139 rtx *loop_reg, rtx *loop_mem)
7141 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
7143 /* Although the new mem does not refer to a known location,
7144 it does keep up to LENGTH bytes of alignment. */
7145 *loop_mem = change_address (mem, BLKmode, *loop_reg);
7146 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
7149 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7150 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7151 the memory regions do not overlap. */
7154 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
7155 HOST_WIDE_INT bytes_per_iter)
7157 rtx label, src_reg, dest_reg, final_src, test;
7158 HOST_WIDE_INT leftover;
7160 leftover = length % bytes_per_iter;
7163 /* Create registers and memory references for use within the loop. */
7164 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
7165 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
7167 /* Calculate the value that SRC_REG should have after the last iteration
7169 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
7172 /* Emit the start of the loop. */
7173 label = gen_label_rtx ();
7176 /* Emit the loop body. */
7177 mips_block_move_straight (dest, src, bytes_per_iter);
7179 /* Move on to the next block. */
7180 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
7181 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7183 /* Emit the loop condition. */
7184 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7185 if (Pmode == DImode)
7186 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7188 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7190 /* Mop up any left-over bytes. */
7192 mips_block_move_straight (dest, src, leftover);
7195 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7196 memory reference SRC to memory reference DEST. */
7199 mips_expand_block_move (rtx dest, rtx src, rtx length)
7201 if (CONST_INT_P (length))
7203 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7205 mips_block_move_straight (dest, src, INTVAL (length));
7210 mips_block_move_loop (dest, src, INTVAL (length),
7211 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7218 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7221 mips_expand_synci_loop (rtx begin, rtx end)
7223 rtx inc, label, end_label, cmp_result, mask, length;
7225 /* Create end_label. */
7226 end_label = gen_label_rtx ();
7228 /* Check if begin equals end. */
7229 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7230 emit_jump_insn (gen_condjump (cmp_result, end_label));
7232 /* Load INC with the cache line size (rdhwr INC,$1). */
7233 inc = gen_reg_rtx (Pmode);
7234 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7236 /* Check if inc is 0. */
7237 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7238 emit_jump_insn (gen_condjump (cmp_result, end_label));
7240 /* Calculate mask. */
7241 mask = mips_force_unary (Pmode, NEG, inc);
7243 /* Mask out begin by mask. */
7244 begin = mips_force_binary (Pmode, AND, begin, mask);
7246 /* Calculate length. */
7247 length = mips_force_binary (Pmode, MINUS, end, begin);
7249 /* Loop back to here. */
7250 label = gen_label_rtx ();
7253 emit_insn (gen_synci (begin));
7255 /* Update length. */
7256 mips_emit_binary (MINUS, length, length, inc);
7259 mips_emit_binary (PLUS, begin, begin, inc);
7261 /* Check if length is greater than 0. */
7262 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7263 emit_jump_insn (gen_condjump (cmp_result, label));
7265 emit_label (end_label);
7268 /* Expand a QI or HI mode atomic memory operation.
7270 GENERATOR contains a pointer to the gen_* function that generates
7271 the SI mode underlying atomic operation using masks that we
7274 RESULT is the return register for the operation. Its value is NULL
7277 MEM is the location of the atomic access.
7279 OLDVAL is the first operand for the operation.
7281 NEWVAL is the optional second operand for the operation. Its value
7282 is NULL if unused. */
7285 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7286 rtx result, rtx mem, rtx oldval, rtx newval)
7288 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7289 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7291 enum machine_mode mode;
7293 mode = GET_MODE (mem);
7295 /* Compute the address of the containing SImode value. */
7296 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7297 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7298 force_reg (Pmode, GEN_INT (-4)));
7300 /* Create a memory reference for it. */
7301 memsi = gen_rtx_MEM (SImode, memsi_addr);
7302 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7303 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7305 /* Work out the byte offset of the QImode or HImode value,
7306 counting from the least significant byte. */
7307 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7308 if (TARGET_BIG_ENDIAN)
7309 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7311 /* Multiply by eight to convert the shift value from bytes to bits. */
7312 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7314 /* Make the final shift an SImode value, so that it can be used in
7315 SImode operations. */
7316 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7318 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7319 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7320 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7321 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7323 /* Compute the equivalent exclusive mask. */
7324 inverted_mask = gen_reg_rtx (SImode);
7325 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7326 gen_rtx_NOT (SImode, mask)));
7328 /* Shift the old value into place. */
7329 if (oldval != const0_rtx)
7331 oldval = convert_modes (SImode, mode, oldval, true);
7332 oldval = force_reg (SImode, oldval);
7333 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7336 /* Do the same for the new value. */
7337 if (newval && newval != const0_rtx)
7339 newval = convert_modes (SImode, mode, newval, true);
7340 newval = force_reg (SImode, newval);
7341 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7344 /* Do the SImode atomic access. */
7346 res = gen_reg_rtx (SImode);
7348 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7350 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7352 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7358 /* Shift and convert the result. */
7359 mips_emit_binary (AND, res, res, mask);
7360 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7361 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7365 /* Return true if it is possible to use left/right accesses for a
7366 bitfield of WIDTH bits starting BITPOS bits into *OP. When
7367 returning true, update *OP, *LEFT and *RIGHT as follows:
7369 *OP is a BLKmode reference to the whole field.
7371 *LEFT is a QImode reference to the first byte if big endian or
7372 the last byte if little endian. This address can be used in the
7373 left-side instructions (LWL, SWL, LDL, SDL).
7375 *RIGHT is a QImode reference to the opposite end of the field and
7376 can be used in the patterning right-side instruction. */
7379 mips_get_unaligned_mem (rtx *op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7380 rtx *left, rtx *right)
7384 /* Check that the operand really is a MEM. Not all the extv and
7385 extzv predicates are checked. */
7389 /* Check that the size is valid. */
7390 if (width != 32 && (!TARGET_64BIT || width != 64))
7393 /* We can only access byte-aligned values. Since we are always passed
7394 a reference to the first byte of the field, it is not necessary to
7395 do anything with BITPOS after this check. */
7396 if (bitpos % BITS_PER_UNIT != 0)
7399 /* Reject aligned bitfields: we want to use a normal load or store
7400 instead of a left/right pair. */
7401 if (MEM_ALIGN (*op) >= width)
7404 /* Create a copy of *OP that refers to the whole field. This also has
7405 the effect of legitimizing *OP's address for BLKmode, possibly
7407 *op = copy_rtx (adjust_address (*op, BLKmode, 0));
7408 set_mem_size (*op, width / BITS_PER_UNIT);
7410 /* Get references to both ends of the field. We deliberately don't
7411 use the original QImode *OP for FIRST since the new BLKmode one
7412 might have a simpler address. */
7413 first = adjust_address (*op, QImode, 0);
7414 last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
7416 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7417 correspond to the MSB and RIGHT to the LSB. */
7418 if (TARGET_BIG_ENDIAN)
7419 *left = first, *right = last;
7421 *left = last, *right = first;
7426 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7427 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7428 the operation is the equivalent of:
7430 (set DEST (*_extract SRC WIDTH BITPOS))
7432 Return true on success. */
7435 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7436 HOST_WIDE_INT bitpos, bool unsigned_p)
7438 rtx left, right, temp;
7439 rtx dest1 = NULL_RTX;
7441 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7442 be a paradoxical word_mode subreg. This is the only case in which
7443 we allow the destination to be larger than the source. */
7444 if (GET_CODE (dest) == SUBREG
7445 && GET_MODE (dest) == DImode
7446 && GET_MODE (SUBREG_REG (dest)) == SImode)
7447 dest = SUBREG_REG (dest);
7449 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7450 be a DImode, create a new temp and emit a zero extend at the end. */
7451 if (GET_MODE (dest) == DImode
7453 && GET_MODE_BITSIZE (SImode) == width)
7456 dest = gen_reg_rtx (SImode);
7459 /* After the above adjustment, the destination must be the same
7460 width as the source. */
7461 if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
7464 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
7467 temp = gen_reg_rtx (GET_MODE (dest));
7468 if (GET_MODE (dest) == DImode)
7470 emit_insn (gen_mov_ldl (temp, src, left));
7471 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7475 emit_insn (gen_mov_lwl (temp, src, left));
7476 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7479 /* If we were loading 32bits and the original register was DI then
7480 sign/zero extend into the orignal dest. */
7484 emit_insn (gen_zero_extendsidi2 (dest1, dest));
7486 emit_insn (gen_extendsidi2 (dest1, dest));
7491 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7492 BITPOS and SRC are the operands passed to the expander; the operation
7493 is the equivalent of:
7495 (set (zero_extract DEST WIDTH BITPOS) SRC)
7497 Return true on success. */
7500 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7501 HOST_WIDE_INT bitpos)
7504 enum machine_mode mode;
7506 if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
7509 mode = mode_for_size (width, MODE_INT, 0);
7510 src = gen_lowpart (mode, src);
7513 emit_insn (gen_mov_sdl (dest, src, left));
7514 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7518 emit_insn (gen_mov_swl (dest, src, left));
7519 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7524 /* Return true if X is a MEM with the same size as MODE. */
7527 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7530 && MEM_SIZE_KNOWN_P (x)
7531 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7534 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7535 source of an "ext" instruction or the destination of an "ins"
7536 instruction. OP must be a register operand and the following
7537 conditions must hold:
7539 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7540 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7541 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7543 Also reject lengths equal to a word as they are better handled
7544 by the move patterns. */
7547 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7549 if (!ISA_HAS_EXT_INS
7550 || !register_operand (op, VOIDmode)
7551 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7554 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7557 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7563 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7564 operation if MAXLEN is the maxium length of consecutive bits that
7565 can make up MASK. MODE is the mode of the operation. See
7566 mask_low_and_shift_len for the actual definition. */
7569 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7571 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7574 /* Return true iff OP1 and OP2 are valid operands together for the
7575 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7576 see the table in the comment before the pattern. */
7579 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7581 return (memory_operand (op1, mode)
7582 ? and_load_operand (op2, mode)
7583 : and_reg_operand (op2, mode));
7586 /* The canonical form of a mask-low-and-shift-left operation is
7587 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7588 cleared. Thus we need to shift MASK to the right before checking if it
7589 is a valid mask value. MODE is the mode of the operation. If true
7590 return the length of the mask, otherwise return -1. */
7593 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7595 HOST_WIDE_INT shval;
7597 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7598 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7601 /* Return true if -msplit-addresses is selected and should be honored.
7603 -msplit-addresses is a half-way house between explicit relocations
7604 and the traditional assembler macros. It can split absolute 32-bit
7605 symbolic constants into a high/lo_sum pair but uses macros for other
7608 Like explicit relocation support for REL targets, it relies
7609 on GNU extensions in the assembler and the linker.
7611 Although this code should work for -O0, it has traditionally
7612 been treated as an optimization. */
7615 mips_split_addresses_p (void)
7617 return (TARGET_SPLIT_ADDRESSES
7621 && !ABI_HAS_64BIT_SYMBOLS);
7624 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7627 mips_init_relocs (void)
7629 memset (mips_split_p, '\0', sizeof (mips_split_p));
7630 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7631 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7632 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7633 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7635 if (TARGET_MIPS16_PCREL_LOADS)
7636 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7639 if (ABI_HAS_64BIT_SYMBOLS)
7641 if (TARGET_EXPLICIT_RELOCS)
7643 mips_split_p[SYMBOL_64_HIGH] = true;
7644 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7645 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7647 mips_split_p[SYMBOL_64_MID] = true;
7648 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7649 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7651 mips_split_p[SYMBOL_64_LOW] = true;
7652 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7653 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7655 mips_split_p[SYMBOL_ABSOLUTE] = true;
7656 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7661 if (TARGET_EXPLICIT_RELOCS
7662 || mips_split_addresses_p ()
7665 mips_split_p[SYMBOL_ABSOLUTE] = true;
7666 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7667 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7674 /* The high part is provided by a pseudo copy of $gp. */
7675 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7676 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7678 else if (TARGET_EXPLICIT_RELOCS)
7679 /* Small data constants are kept whole until after reload,
7680 then lowered by mips_rewrite_small_data. */
7681 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7683 if (TARGET_EXPLICIT_RELOCS)
7685 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7688 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7689 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7693 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7694 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7697 /* Expose the use of $28 as soon as possible. */
7698 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7702 /* The HIGH and LO_SUM are matched by special .md patterns. */
7703 mips_split_p[SYMBOL_GOT_DISP] = true;
7705 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7706 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7707 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7709 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7710 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7711 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7716 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7718 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7719 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7721 /* Expose the use of $28 as soon as possible. */
7722 mips_split_p[SYMBOL_GOT_DISP] = true;
7728 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7729 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7730 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7733 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7734 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7736 if (TARGET_MIPS16_PCREL_LOADS)
7738 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7739 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7743 mips_split_p[SYMBOL_DTPREL] = true;
7744 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7745 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7747 mips_split_p[SYMBOL_TPREL] = true;
7748 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7749 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7752 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7753 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7756 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7757 in context CONTEXT. RELOCS is the array of relocations to use. */
7760 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7761 const char **relocs)
7763 enum mips_symbol_type symbol_type;
7766 symbol_type = mips_classify_symbolic_expression (op, context);
7767 gcc_assert (relocs[symbol_type]);
7769 fputs (relocs[symbol_type], file);
7770 output_addr_const (file, mips_strip_unspec_address (op));
7771 for (p = relocs[symbol_type]; *p != 0; p++)
7776 /* Start a new block with the given asm switch enabled. If we need
7777 to print a directive, emit PREFIX before it and SUFFIX after it. */
7780 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7781 const char *prefix, const char *suffix)
7783 if (asm_switch->nesting_level == 0)
7784 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7785 asm_switch->nesting_level++;
7788 /* Likewise, but end a block. */
7791 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7792 const char *prefix, const char *suffix)
7794 gcc_assert (asm_switch->nesting_level);
7795 asm_switch->nesting_level--;
7796 if (asm_switch->nesting_level == 0)
7797 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7800 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7801 that either print a complete line or print nothing. */
7804 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7806 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7810 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7812 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7815 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7816 The punctuation characters are:
7818 '(' Start a nested ".set noreorder" block.
7819 ')' End a nested ".set noreorder" block.
7820 '[' Start a nested ".set noat" block.
7821 ']' End a nested ".set noat" block.
7822 '<' Start a nested ".set nomacro" block.
7823 '>' End a nested ".set nomacro" block.
7824 '*' Behave like %(%< if generating a delayed-branch sequence.
7825 '#' Print a nop if in a ".set noreorder" block.
7826 '/' Like '#', but do nothing within a delayed-branch sequence.
7827 '?' Print "l" if mips_branch_likely is true
7828 '~' Print a nop if mips_branch_likely is true
7829 '.' Print the name of the register with a hard-wired zero (zero or $0).
7830 '@' Print the name of the assembler temporary register (at or $1).
7831 '^' Print the name of the pic call-through register (t9 or $25).
7832 '+' Print the name of the gp register (usually gp or $28).
7833 '$' Print the name of the stack pointer register (sp or $29).
7835 See also mips_init_print_operand_pucnt. */
7838 mips_print_operand_punctuation (FILE *file, int ch)
7843 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
7847 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
7851 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
7855 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
7859 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
7863 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
7867 if (final_sequence != 0)
7869 mips_print_operand_punctuation (file, '(');
7870 mips_print_operand_punctuation (file, '<');
7875 if (mips_noreorder.nesting_level > 0)
7876 fputs ("\n\tnop", file);
7880 /* Print an extra newline so that the delayed insn is separated
7881 from the following ones. This looks neater and is consistent
7882 with non-nop delayed sequences. */
7883 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
7884 fputs ("\n\tnop\n", file);
7888 if (mips_branch_likely)
7893 if (mips_branch_likely)
7894 fputs ("\n\tnop", file);
7898 fputs (reg_names[GP_REG_FIRST + 0], file);
7902 fputs (reg_names[AT_REGNUM], file);
7906 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
7910 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
7914 fputs (reg_names[STACK_POINTER_REGNUM], file);
7923 /* Initialize mips_print_operand_punct. */
7926 mips_init_print_operand_punct (void)
7930 for (p = "()[]<>*#/?~.@^+$"; *p; p++)
7931 mips_print_operand_punct[(unsigned char) *p] = true;
7934 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7935 associated with condition CODE. Print the condition part of the
7939 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
7953 /* Conveniently, the MIPS names for these conditions are the same
7954 as their RTL equivalents. */
7955 fputs (GET_RTX_NAME (code), file);
7959 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7964 /* Likewise floating-point branches. */
7967 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
7972 fputs ("c1f", file);
7976 fputs ("c1t", file);
7980 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
7985 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7988 mips_print_operand_punct_valid_p (unsigned char code)
7990 return mips_print_operand_punct[code];
7993 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7995 'X' Print CONST_INT OP in hexadecimal format.
7996 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7997 'd' Print CONST_INT OP in decimal.
7998 'm' Print one less than CONST_INT OP in decimal.
7999 'h' Print the high-part relocation associated with OP, after stripping
8001 'R' Print the low-part relocation associated with OP.
8002 'C' Print the integer branch condition for comparison OP.
8003 'N' Print the inverse of the integer branch condition for comparison OP.
8004 'F' Print the FPU branch condition for comparison OP.
8005 'W' Print the inverse of the FPU branch condition for comparison OP.
8006 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8007 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8008 't' Like 'T', but with the EQ/NE cases reversed
8009 'Y' Print mips_fp_conditions[INTVAL (OP)]
8010 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8011 'q' Print a DSP accumulator register.
8012 'D' Print the second part of a double-word register or memory operand.
8013 'L' Print the low-order register in a double-word register operand.
8014 'M' Print high-order register in a double-word register operand.
8015 'z' Print $0 if OP is zero, otherwise print OP normally.
8016 'b' Print the address of a memory operand, without offset. */
8019 mips_print_operand (FILE *file, rtx op, int letter)
8023 if (mips_print_operand_punct_valid_p (letter))
8025 mips_print_operand_punctuation (file, letter);
8030 code = GET_CODE (op);
8035 if (CONST_INT_P (op))
8036 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
8038 output_operand_lossage ("invalid use of '%%%c'", letter);
8042 if (CONST_INT_P (op))
8043 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
8045 output_operand_lossage ("invalid use of '%%%c'", letter);
8049 if (CONST_INT_P (op))
8050 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8052 output_operand_lossage ("invalid use of '%%%c'", letter);
8056 if (CONST_INT_P (op))
8057 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
8059 output_operand_lossage ("invalid use of '%%%c'", letter);
8065 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
8069 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
8073 mips_print_int_branch_condition (file, code, letter);
8077 mips_print_int_branch_condition (file, reverse_condition (code), letter);
8081 mips_print_float_branch_condition (file, code, letter);
8085 mips_print_float_branch_condition (file, reverse_condition (code),
8092 int truth = (code == NE) == (letter == 'T');
8093 fputc ("zfnt"[truth * 2 + (GET_MODE (op) == CCmode)], file);
8098 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
8099 fputs (mips_fp_conditions[UINTVAL (op)], file);
8101 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8108 mips_print_operand (file, op, 0);
8114 if (code == REG && MD_REG_P (REGNO (op)))
8115 fprintf (file, "$ac0");
8116 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
8117 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
8119 output_operand_lossage ("invalid use of '%%%c'", letter);
8127 unsigned int regno = REGNO (op);
8128 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
8129 || (letter == 'L' && TARGET_BIG_ENDIAN)
8132 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
8133 output_operand_lossage ("invalid use of '%%%c'", letter);
8134 /* We need to print $0 .. $31 for COP0 registers. */
8135 if (COP0_REG_P (regno))
8136 fprintf (file, "$%s", ®_names[regno][4]);
8138 fprintf (file, "%s", reg_names[regno]);
8144 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
8145 else if (letter == 'b')
8147 gcc_assert (REG_P (XEXP (op, 0)));
8148 mips_print_operand (file, XEXP (op, 0), 0);
8150 else if (letter && letter != 'z')
8151 output_operand_lossage ("invalid use of '%%%c'", letter);
8153 output_address (XEXP (op, 0));
8157 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
8158 fputs (reg_names[GP_REG_FIRST], file);
8159 else if (letter && letter != 'z')
8160 output_operand_lossage ("invalid use of '%%%c'", letter);
8161 else if (CONST_GP_P (op))
8162 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
8164 output_addr_const (file, mips_strip_unspec_address (op));
8170 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8173 mips_print_operand_address (FILE *file, rtx x)
8175 struct mips_address_info addr;
8177 if (mips_classify_address (&addr, x, word_mode, true))
8181 mips_print_operand (file, addr.offset, 0);
8182 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8185 case ADDRESS_LO_SUM:
8186 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
8188 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8191 case ADDRESS_CONST_INT:
8192 output_addr_const (file, x);
8193 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
8196 case ADDRESS_SYMBOLIC:
8197 output_addr_const (file, mips_strip_unspec_address (x));
8203 /* Implement TARGET_ENCODE_SECTION_INFO. */
8206 mips_encode_section_info (tree decl, rtx rtl, int first)
8208 default_encode_section_info (decl, rtl, first);
8210 if (TREE_CODE (decl) == FUNCTION_DECL)
8212 rtx symbol = XEXP (rtl, 0);
8213 tree type = TREE_TYPE (decl);
8215 /* Encode whether the symbol is short or long. */
8216 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8217 || mips_far_type_p (type))
8218 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8222 /* Implement TARGET_SELECT_RTX_SECTION. */
8225 mips_select_rtx_section (enum machine_mode mode, rtx x,
8226 unsigned HOST_WIDE_INT align)
8228 /* ??? Consider using mergeable small data sections. */
8229 if (mips_rtx_constant_in_small_data_p (mode))
8230 return get_named_section (NULL, ".sdata", 0);
8232 return default_elf_select_rtx_section (mode, x, align);
8235 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8237 The complication here is that, with the combination TARGET_ABICALLS
8238 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8239 absolute addresses, and should therefore not be included in the
8240 read-only part of a DSO. Handle such cases by selecting a normal
8241 data section instead of a read-only one. The logic apes that in
8242 default_function_rodata_section. */
8245 mips_function_rodata_section (tree decl)
8247 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8248 return default_function_rodata_section (decl);
8250 if (decl && DECL_SECTION_NAME (decl))
8252 const char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8253 if (DECL_ONE_ONLY (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8255 char *rname = ASTRDUP (name);
8257 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8259 else if (flag_function_sections
8260 && flag_data_sections
8261 && strncmp (name, ".text.", 6) == 0)
8263 char *rname = ASTRDUP (name);
8264 memcpy (rname + 1, "data", 4);
8265 return get_section (rname, SECTION_WRITE, decl);
8268 return data_section;
8271 /* Implement TARGET_IN_SMALL_DATA_P. */
8274 mips_in_small_data_p (const_tree decl)
8276 unsigned HOST_WIDE_INT size;
8278 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8281 /* We don't yet generate small-data references for -mabicalls
8282 or VxWorks RTP code. See the related -G handling in
8283 mips_option_override. */
8284 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8287 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8291 /* Reject anything that isn't in a known small-data section. */
8292 name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
8293 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8296 /* If a symbol is defined externally, the assembler will use the
8297 usual -G rules when deciding how to implement macros. */
8298 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8301 else if (TARGET_EMBEDDED_DATA)
8303 /* Don't put constants into the small data section: we want them
8304 to be in ROM rather than RAM. */
8305 if (TREE_CODE (decl) != VAR_DECL)
8308 if (TREE_READONLY (decl)
8309 && !TREE_SIDE_EFFECTS (decl)
8310 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8314 /* Enforce -mlocal-sdata. */
8315 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8318 /* Enforce -mextern-sdata. */
8319 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8321 if (DECL_EXTERNAL (decl))
8323 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8327 /* We have traditionally not treated zero-sized objects as small data,
8328 so this is now effectively part of the ABI. */
8329 size = int_size_in_bytes (TREE_TYPE (decl));
8330 return size > 0 && size <= mips_small_data_threshold;
8333 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8334 anchors for small data: the GP register acts as an anchor in that
8335 case. We also don't want to use them for PC-relative accesses,
8336 where the PC acts as an anchor. */
8339 mips_use_anchors_for_symbol_p (const_rtx symbol)
8341 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8343 case SYMBOL_PC_RELATIVE:
8344 case SYMBOL_GP_RELATIVE:
8348 return default_use_anchors_for_symbol_p (symbol);
8352 /* The MIPS debug format wants all automatic variables and arguments
8353 to be in terms of the virtual frame pointer (stack pointer before
8354 any adjustment in the function), while the MIPS 3.0 linker wants
8355 the frame pointer to be the stack pointer after the initial
8356 adjustment. So, we do the adjustment here. The arg pointer (which
8357 is eliminated) points to the virtual frame pointer, while the frame
8358 pointer (which may be eliminated) points to the stack pointer after
8359 the initial adjustments. */
8362 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8364 rtx offset2 = const0_rtx;
8365 rtx reg = eliminate_constant_term (addr, &offset2);
8368 offset = INTVAL (offset2);
8370 if (reg == stack_pointer_rtx
8371 || reg == frame_pointer_rtx
8372 || reg == hard_frame_pointer_rtx)
8374 offset -= cfun->machine->frame.total_size;
8375 if (reg == hard_frame_pointer_rtx)
8376 offset += cfun->machine->frame.hard_frame_pointer_offset;
8382 /* Implement ASM_OUTPUT_EXTERNAL. */
8385 mips_output_external (FILE *file, tree decl, const char *name)
8387 default_elf_asm_output_external (file, decl, name);
8389 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8390 set in order to avoid putting out names that are never really
8392 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8394 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8396 /* When using assembler macros, emit .extern directives for
8397 all small-data externs so that the assembler knows how
8400 In most cases it would be safe (though pointless) to emit
8401 .externs for other symbols too. One exception is when an
8402 object is within the -G limit but declared by the user to
8403 be in a section other than .sbss or .sdata. */
8404 fputs ("\t.extern\t", file);
8405 assemble_name (file, name);
8406 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8407 int_size_in_bytes (TREE_TYPE (decl)));
8412 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8415 mips_output_filename (FILE *stream, const char *name)
8417 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8419 if (write_symbols == DWARF2_DEBUG)
8421 else if (mips_output_filename_first_time)
8423 mips_output_filename_first_time = 0;
8424 num_source_filenames += 1;
8425 current_function_file = name;
8426 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8427 output_quoted_string (stream, name);
8428 putc ('\n', stream);
8430 /* If we are emitting stabs, let dbxout.c handle this (except for
8431 the mips_output_filename_first_time case). */
8432 else if (write_symbols == DBX_DEBUG)
8434 else if (name != current_function_file
8435 && strcmp (name, current_function_file) != 0)
8437 num_source_filenames += 1;
8438 current_function_file = name;
8439 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8440 output_quoted_string (stream, name);
8441 putc ('\n', stream);
8445 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8447 static void ATTRIBUTE_UNUSED
8448 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8453 fputs ("\t.dtprelword\t", file);
8457 fputs ("\t.dtpreldword\t", file);
8463 output_addr_const (file, x);
8464 fputs ("+0x8000", file);
8467 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8470 mips_dwarf_register_span (rtx reg)
8473 enum machine_mode mode;
8475 /* By default, GCC maps increasing register numbers to increasing
8476 memory locations, but paired FPRs are always little-endian,
8477 regardless of the prevailing endianness. */
8478 mode = GET_MODE (reg);
8479 if (FP_REG_P (REGNO (reg))
8480 && TARGET_BIG_ENDIAN
8481 && MAX_FPRS_PER_FMT > 1
8482 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8484 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8485 high = mips_subword (reg, true);
8486 low = mips_subword (reg, false);
8487 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8493 /* DSP ALU can bypass data with no delays for the following pairs. */
8494 enum insn_code dspalu_bypass_table[][2] =
8496 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
8497 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
8498 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
8499 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
8500 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
8501 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
8502 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
8503 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
8507 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
8510 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
8511 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
8512 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
8514 for (i = 0; i < num_bypass; i++)
8516 if (out_icode == dspalu_bypass_table[i][0]
8517 && in_icode == dspalu_bypass_table[i][1])
8523 /* Implement ASM_OUTPUT_ASCII. */
8526 mips_output_ascii (FILE *stream, const char *string, size_t len)
8532 fprintf (stream, "\t.ascii\t\"");
8533 for (i = 0; i < len; i++)
8537 c = (unsigned char) string[i];
8540 if (c == '\\' || c == '\"')
8542 putc ('\\', stream);
8550 fprintf (stream, "\\%03o", c);
8554 if (cur_pos > 72 && i+1 < len)
8557 fprintf (stream, "\"\n\t.ascii\t\"");
8560 fprintf (stream, "\"\n");
8563 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8564 Update *ADDR with the operand that should be printed. */
8567 mips_output_tls_reloc_directive (rtx *addr)
8569 enum mips_symbol_type type;
8571 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8572 *addr = mips_strip_unspec_address (*addr);
8576 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8579 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8586 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8587 macros, mark the symbol as written so that mips_asm_output_external
8588 won't emit an .extern for it. STREAM is the output file, NAME is the
8589 name of the symbol, INIT_STRING is the string that should be written
8590 before the symbol and FINAL_STRING is the string that should be
8591 written after it. FINAL_STRING is a printf format that consumes the
8592 remaining arguments. */
8595 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8596 const char *final_string, ...)
8600 fputs (init_string, stream);
8601 assemble_name (stream, name);
8602 va_start (ap, final_string);
8603 vfprintf (stream, final_string, ap);
8606 if (!TARGET_EXPLICIT_RELOCS)
8608 tree name_tree = get_identifier (name);
8609 TREE_ASM_WRITTEN (name_tree) = 1;
8613 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8614 NAME is the name of the object and ALIGN is the required alignment
8615 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8616 alignment argument. */
8619 mips_declare_common_object (FILE *stream, const char *name,
8620 const char *init_string,
8621 unsigned HOST_WIDE_INT size,
8622 unsigned int align, bool takes_alignment_p)
8624 if (!takes_alignment_p)
8626 size += (align / BITS_PER_UNIT) - 1;
8627 size -= size % (align / BITS_PER_UNIT);
8628 mips_declare_object (stream, name, init_string,
8629 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8632 mips_declare_object (stream, name, init_string,
8633 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8634 size, align / BITS_PER_UNIT);
8637 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8638 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8641 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8642 unsigned HOST_WIDE_INT size,
8645 /* If the target wants uninitialized const declarations in
8646 .rdata then don't put them in .comm. */
8647 if (TARGET_EMBEDDED_DATA
8648 && TARGET_UNINIT_CONST_IN_RODATA
8649 && TREE_CODE (decl) == VAR_DECL
8650 && TREE_READONLY (decl)
8651 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8653 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8654 targetm.asm_out.globalize_label (stream, name);
8656 switch_to_section (readonly_data_section);
8657 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8658 mips_declare_object (stream, name, "",
8659 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8663 mips_declare_common_object (stream, name, "\n\t.comm\t",
8667 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8668 extern int size_directive_output;
8670 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8671 definitions except that it uses mips_declare_object to emit the label. */
8674 mips_declare_object_name (FILE *stream, const char *name,
8675 tree decl ATTRIBUTE_UNUSED)
8677 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8678 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8681 size_directive_output = 0;
8682 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8686 size_directive_output = 1;
8687 size = int_size_in_bytes (TREE_TYPE (decl));
8688 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8691 mips_declare_object (stream, name, "", ":\n");
8694 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8697 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8701 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8702 if (!flag_inhibit_size_directive
8703 && DECL_SIZE (decl) != 0
8706 && DECL_INITIAL (decl) == error_mark_node
8707 && !size_directive_output)
8711 size_directive_output = 1;
8712 size = int_size_in_bytes (TREE_TYPE (decl));
8713 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8718 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8719 with the current ABI. */
8722 mips_mdebug_abi_name (void)
8735 return TARGET_64BIT ? "eabi64" : "eabi32";
8741 /* Implement TARGET_ASM_FILE_START. */
8744 mips_file_start (void)
8746 default_file_start ();
8748 /* Generate a special section to describe the ABI switches used to
8749 produce the resultant binary. */
8751 /* Record the ABI itself. Modern versions of binutils encode
8752 this information in the ELF header flags, but GDB needs the
8753 information in order to correctly debug binaries produced by
8754 older binutils. See the function mips_gdbarch_init in
8756 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8757 mips_mdebug_abi_name ());
8759 /* There is no ELF header flag to distinguish long32 forms of the
8760 EABI from long64 forms. Emit a special section to help tools
8761 such as GDB. Do the same for o64, which is sometimes used with
8763 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8764 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8765 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8767 #ifdef HAVE_AS_GNU_ATTRIBUTE
8771 /* No floating-point operations, -mno-float. */
8772 if (TARGET_NO_FLOAT)
8774 /* Soft-float code, -msoft-float. */
8775 else if (!TARGET_HARD_FLOAT_ABI)
8777 /* Single-float code, -msingle-float. */
8778 else if (!TARGET_DOUBLE_FLOAT)
8780 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8781 else if (!TARGET_64BIT && TARGET_FLOAT64)
8783 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8787 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8791 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8792 if (TARGET_ABICALLS)
8794 fprintf (asm_out_file, "\t.abicalls\n");
8795 if (TARGET_ABICALLS_PIC0)
8796 fprintf (asm_out_file, "\t.option\tpic0\n");
8799 if (flag_verbose_asm)
8800 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8802 mips_small_data_threshold, mips_arch_info->name, mips_isa);
8805 /* Implement TARGET_ASM_CODE_END. */
8808 mips_code_end (void)
8810 if (mips_need_mips16_rdhwr_p)
8811 mips_output_mips16_rdhwr ();
8814 /* Make the last instruction frame-related and note that it performs
8815 the operation described by FRAME_PATTERN. */
8818 mips_set_frame_expr (rtx frame_pattern)
8822 insn = get_last_insn ();
8823 RTX_FRAME_RELATED_P (insn) = 1;
8824 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
8829 /* Return a frame-related rtx that stores REG at MEM.
8830 REG must be a single register. */
8833 mips_frame_set (rtx mem, rtx reg)
8837 set = gen_rtx_SET (VOIDmode, mem, reg);
8838 RTX_FRAME_RELATED_P (set) = 1;
8843 /* Record that the epilogue has restored call-saved register REG. */
8846 mips_add_cfa_restore (rtx reg)
8848 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
8849 mips_epilogue.cfa_restores);
8852 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8853 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8854 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8855 static const unsigned char mips16e_s2_s8_regs[] = {
8856 30, 23, 22, 21, 20, 19, 18
8858 static const unsigned char mips16e_a0_a3_regs[] = {
8862 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8863 ordered from the uppermost in memory to the lowest in memory. */
8864 static const unsigned char mips16e_save_restore_regs[] = {
8865 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8868 /* Return the index of the lowest X in the range [0, SIZE) for which
8869 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8872 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
8877 for (i = 0; i < size; i++)
8878 if (BITSET_P (mask, regs[i]))
8884 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8885 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8886 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8887 is true for all indexes (X, SIZE). */
8890 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
8891 unsigned int size, unsigned int *num_regs_ptr)
8895 i = mips16e_find_first_register (*mask_ptr, regs, size);
8896 for (i++; i < size; i++)
8897 if (!BITSET_P (*mask_ptr, regs[i]))
8900 *mask_ptr |= 1 << regs[i];
8904 /* Return a simplified form of X using the register values in REG_VALUES.
8905 REG_VALUES[R] is the last value assigned to hard register R, or null
8906 if R has not been modified.
8908 This function is rather limited, but is good enough for our purposes. */
8911 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
8913 x = avoid_constant_pool_reference (x);
8917 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8918 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
8919 x0, GET_MODE (XEXP (x, 0)));
8922 if (ARITHMETIC_P (x))
8924 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
8925 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
8926 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
8930 && reg_values[REGNO (x)]
8931 && !rtx_unstable_p (reg_values[REGNO (x)]))
8932 return reg_values[REGNO (x)];
8937 /* Return true if (set DEST SRC) stores an argument register into its
8938 caller-allocated save slot, storing the number of that argument
8939 register in *REGNO_PTR if so. REG_VALUES is as for
8940 mips16e_collect_propagate_value. */
8943 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
8944 unsigned int *regno_ptr)
8946 unsigned int argno, regno;
8947 HOST_WIDE_INT offset, required_offset;
8950 /* Check that this is a word-mode store. */
8951 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
8954 /* Check that the register being saved is an unmodified argument
8956 regno = REGNO (src);
8957 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
8959 argno = regno - GP_ARG_FIRST;
8961 /* Check whether the address is an appropriate stack-pointer or
8962 frame-pointer access. */
8963 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
8964 mips_split_plus (addr, &base, &offset);
8965 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
8966 if (base == hard_frame_pointer_rtx)
8967 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
8968 else if (base != stack_pointer_rtx)
8970 if (offset != required_offset)
8977 /* A subroutine of mips_expand_prologue, called only when generating
8978 MIPS16e SAVE instructions. Search the start of the function for any
8979 instructions that save argument registers into their caller-allocated
8980 save slots. Delete such instructions and return a value N such that
8981 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8982 instructions redundant. */
8985 mips16e_collect_argument_saves (void)
8987 rtx reg_values[FIRST_PSEUDO_REGISTER];
8988 rtx insn, next, set, dest, src;
8989 unsigned int nargs, regno;
8991 push_topmost_sequence ();
8993 memset (reg_values, 0, sizeof (reg_values));
8994 for (insn = get_insns (); insn; insn = next)
8996 next = NEXT_INSN (insn);
8997 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
9003 set = PATTERN (insn);
9004 if (GET_CODE (set) != SET)
9007 dest = SET_DEST (set);
9008 src = SET_SRC (set);
9009 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
9011 if (!BITSET_P (cfun->machine->frame.mask, regno))
9014 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
9017 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
9018 reg_values[REGNO (dest)]
9019 = mips16e_collect_propagate_value (src, reg_values);
9023 pop_topmost_sequence ();
9028 /* Return a move between register REGNO and memory location SP + OFFSET.
9029 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9030 Make the move a load if RESTORE_P, otherwise make it a store. */
9033 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
9034 HOST_WIDE_INT offset, unsigned int regno)
9038 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
9040 reg = gen_rtx_REG (SImode, regno);
9043 mips_add_cfa_restore (reg);
9044 return gen_rtx_SET (VOIDmode, reg, mem);
9047 return gen_rtx_SET (VOIDmode, mem, reg);
9048 return mips_frame_set (mem, reg);
9051 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9052 The instruction must:
9054 - Allocate or deallocate SIZE bytes in total; SIZE is known
9057 - Save or restore as many registers in *MASK_PTR as possible.
9058 The instruction saves the first registers at the top of the
9059 allocated area, with the other registers below it.
9061 - Save NARGS argument registers above the allocated area.
9063 (NARGS is always zero if RESTORE_P.)
9065 The SAVE and RESTORE instructions cannot save and restore all general
9066 registers, so there may be some registers left over for the caller to
9067 handle. Destructively modify *MASK_PTR so that it contains the registers
9068 that still need to be saved or restored. The caller can save these
9069 registers in the memory immediately below *OFFSET_PTR, which is a
9070 byte offset from the bottom of the allocated stack area. */
9073 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
9074 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
9078 HOST_WIDE_INT offset, top_offset;
9079 unsigned int i, regno;
9082 gcc_assert (cfun->machine->frame.num_fp == 0);
9084 /* Calculate the number of elements in the PARALLEL. We need one element
9085 for the stack adjustment, one for each argument register save, and one
9086 for each additional register move. */
9088 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9089 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
9092 /* Create the final PARALLEL. */
9093 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
9096 /* Add the stack pointer adjustment. */
9097 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9098 plus_constant (Pmode, stack_pointer_rtx,
9099 restore_p ? size : -size));
9100 RTX_FRAME_RELATED_P (set) = 1;
9101 XVECEXP (pattern, 0, n++) = set;
9103 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9104 top_offset = restore_p ? size : 0;
9106 /* Save the arguments. */
9107 for (i = 0; i < nargs; i++)
9109 offset = top_offset + i * UNITS_PER_WORD;
9110 set = mips16e_save_restore_reg (restore_p, true, offset,
9112 XVECEXP (pattern, 0, n++) = set;
9115 /* Then fill in the other register moves. */
9116 offset = top_offset;
9117 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9119 regno = mips16e_save_restore_regs[i];
9120 if (BITSET_P (*mask_ptr, regno))
9122 offset -= UNITS_PER_WORD;
9123 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
9124 XVECEXP (pattern, 0, n++) = set;
9125 *mask_ptr &= ~(1 << regno);
9129 /* Tell the caller what offset it should use for the remaining registers. */
9130 *offset_ptr = size + (offset - top_offset);
9132 gcc_assert (n == XVECLEN (pattern, 0));
9137 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9138 pointer. Return true if PATTERN matches the kind of instruction
9139 generated by mips16e_build_save_restore. If INFO is nonnull,
9140 initialize it when returning true. */
9143 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
9144 struct mips16e_save_restore_info *info)
9146 unsigned int i, nargs, mask, extra;
9147 HOST_WIDE_INT top_offset, save_offset, offset;
9148 rtx set, reg, mem, base;
9151 if (!GENERATE_MIPS16E_SAVE_RESTORE)
9154 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9155 top_offset = adjust > 0 ? adjust : 0;
9157 /* Interpret all other members of the PARALLEL. */
9158 save_offset = top_offset - UNITS_PER_WORD;
9162 for (n = 1; n < XVECLEN (pattern, 0); n++)
9164 /* Check that we have a SET. */
9165 set = XVECEXP (pattern, 0, n);
9166 if (GET_CODE (set) != SET)
9169 /* Check that the SET is a load (if restoring) or a store
9171 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
9175 /* Check that the address is the sum of the stack pointer and a
9176 possibly-zero constant offset. */
9177 mips_split_plus (XEXP (mem, 0), &base, &offset);
9178 if (base != stack_pointer_rtx)
9181 /* Check that SET's other operand is a register. */
9182 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
9186 /* Check for argument saves. */
9187 if (offset == top_offset + nargs * UNITS_PER_WORD
9188 && REGNO (reg) == GP_ARG_FIRST + nargs)
9190 else if (offset == save_offset)
9192 while (mips16e_save_restore_regs[i++] != REGNO (reg))
9193 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
9196 mask |= 1 << REGNO (reg);
9197 save_offset -= UNITS_PER_WORD;
9203 /* Check that the restrictions on register ranges are met. */
9205 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
9206 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
9207 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
9208 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
9212 /* Make sure that the topmost argument register is not saved twice.
9213 The checks above ensure that the same is then true for the other
9214 argument registers. */
9215 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
9218 /* Pass back information, if requested. */
9221 info->nargs = nargs;
9223 info->size = (adjust > 0 ? adjust : -adjust);
9229 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9230 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9231 the null terminator. */
9234 mips16e_add_register_range (char *s, unsigned int min_reg,
9235 unsigned int max_reg)
9237 if (min_reg != max_reg)
9238 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9240 s += sprintf (s, ",%s", reg_names[min_reg]);
9244 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9245 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9248 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9250 static char buffer[300];
9252 struct mips16e_save_restore_info info;
9253 unsigned int i, end;
9256 /* Parse the pattern. */
9257 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9260 /* Add the mnemonic. */
9261 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9264 /* Save the arguments. */
9266 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9267 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9268 else if (info.nargs == 1)
9269 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9271 /* Emit the amount of stack space to allocate or deallocate. */
9272 s += sprintf (s, "%d", (int) info.size);
9274 /* Save or restore $16. */
9275 if (BITSET_P (info.mask, 16))
9276 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9278 /* Save or restore $17. */
9279 if (BITSET_P (info.mask, 17))
9280 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9282 /* Save or restore registers in the range $s2...$s8, which
9283 mips16e_s2_s8_regs lists in decreasing order. Note that this
9284 is a software register range; the hardware registers are not
9285 numbered consecutively. */
9286 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9287 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9289 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9290 mips16e_s2_s8_regs[i]);
9292 /* Save or restore registers in the range $a0...$a3. */
9293 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9294 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9296 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9297 mips16e_a0_a3_regs[end - 1]);
9299 /* Save or restore $31. */
9300 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9301 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9306 /* Return true if the current function returns its value in a floating-point
9307 register in MIPS16 mode. */
9310 mips16_cfun_returns_in_fpr_p (void)
9312 tree return_type = DECL_RESULT (current_function_decl);
9313 return (TARGET_MIPS16
9314 && TARGET_HARD_FLOAT_ABI
9315 && !aggregate_value_p (return_type, current_function_decl)
9316 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9319 /* Return true if predicate PRED is true for at least one instruction.
9320 Cache the result in *CACHE, and assume that the result is true
9321 if *CACHE is already true. */
9324 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
9330 push_topmost_sequence ();
9331 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9332 if (USEFUL_INSN_P (insn) && pred (insn))
9337 pop_topmost_sequence ();
9342 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9343 See mips_cfun_has_inflexible_gp_ref_p for details. */
9346 mips_insn_has_inflexible_gp_ref_p (rtx insn)
9348 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9349 indicate that the target could be a traditional MIPS
9350 lazily-binding stub. */
9351 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9354 /* Return true if the current function refers to the global pointer
9355 in a way that forces $28 to be valid. This means that we can't
9356 change the choice of global pointer, even for NewABI code.
9358 One example of this (and one which needs several checks) is that
9359 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9360 (This restriction does not apply to PLTs.) */
9363 mips_cfun_has_inflexible_gp_ref_p (void)
9365 /* If the function has a nonlocal goto, $28 must hold the correct
9366 global pointer for the target function. That is, the target
9367 of the goto implicitly uses $28. */
9368 if (crtl->has_nonlocal_goto)
9371 if (TARGET_ABICALLS_PIC2)
9373 /* Symbolic accesses implicitly use the global pointer unless
9374 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9375 might go to traditional MIPS lazy-binding stubs. */
9376 if (!TARGET_EXPLICIT_RELOCS)
9379 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9380 can be lazily-bound. */
9384 /* MIPS16 functions that return in FPRs need to call an
9385 external libgcc routine. This call is only made explict
9386 during mips_expand_epilogue, and it too might be lazily bound. */
9387 if (mips16_cfun_returns_in_fpr_p ())
9391 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9392 mips_insn_has_inflexible_gp_ref_p);
9395 /* Return true if INSN refers to the global pointer in a "flexible" way.
9396 See mips_cfun_has_flexible_gp_ref_p for details. */
9399 mips_insn_has_flexible_gp_ref_p (rtx insn)
9401 return (get_attr_got (insn) != GOT_UNSET
9402 || mips_small_data_pattern_p (PATTERN (insn))
9403 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9406 /* Return true if the current function references the global pointer,
9407 but if those references do not inherently require the global pointer
9408 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9411 mips_cfun_has_flexible_gp_ref_p (void)
9413 /* Reload can sometimes introduce constant pool references
9414 into a function that otherwise didn't need them. For example,
9415 suppose we have an instruction like:
9417 (set (reg:DF R1) (float:DF (reg:SI R2)))
9419 If R2 turns out to be a constant such as 1, the instruction may
9420 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9421 the option of using this constant if R2 doesn't get allocated
9424 In cases like these, reload will have added the constant to the
9425 pool but no instruction will yet refer to it. */
9426 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9429 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9430 mips_insn_has_flexible_gp_ref_p);
9433 /* Return the register that should be used as the global pointer
9434 within this function. Return INVALID_REGNUM if the function
9435 doesn't need a global pointer. */
9438 mips_global_pointer (void)
9442 /* $gp is always available unless we're using a GOT. */
9443 if (!TARGET_USE_GOT)
9444 return GLOBAL_POINTER_REGNUM;
9446 /* If there are inflexible references to $gp, we must use the
9447 standard register. */
9448 if (mips_cfun_has_inflexible_gp_ref_p ())
9449 return GLOBAL_POINTER_REGNUM;
9451 /* If there are no current references to $gp, then the only uses
9452 we can introduce later are those involved in long branches. */
9453 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9454 return INVALID_REGNUM;
9456 /* If the global pointer is call-saved, try to use a call-clobbered
9458 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9459 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9460 if (!df_regs_ever_live_p (regno)
9461 && call_really_used_regs[regno]
9462 && !fixed_regs[regno]
9463 && regno != PIC_FUNCTION_ADDR_REGNUM)
9466 return GLOBAL_POINTER_REGNUM;
9469 /* Return true if the current function's prologue must load the global
9470 pointer value into pic_offset_table_rtx and store the same value in
9471 the function's cprestore slot (if any).
9473 One problem we have to deal with is that, when emitting GOT-based
9474 position independent code, long-branch sequences will need to load
9475 the address of the branch target from the GOT. We don't know until
9476 the very end of compilation whether (and where) the function needs
9477 long branches, so we must ensure that _any_ branch can access the
9478 global pointer in some form. However, we do not want to pessimize
9479 the usual case in which all branches are short.
9481 We handle this as follows:
9483 (1) During reload, we set cfun->machine->global_pointer to
9484 INVALID_REGNUM if we _know_ that the current function
9485 doesn't need a global pointer. This is only valid if
9486 long branches don't need the GOT.
9488 Otherwise, we assume that we might need a global pointer
9489 and pick an appropriate register.
9491 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9492 we ensure that the global pointer is available at every
9493 block boundary bar entry and exit. We do this in one of two ways:
9495 - If the function has a cprestore slot, we ensure that this
9496 slot is valid at every branch. However, as explained in
9497 point (6) below, there is no guarantee that pic_offset_table_rtx
9498 itself is valid if new uses of the global pointer are introduced
9499 after the first post-epilogue split.
9501 We guarantee that the cprestore slot is valid by loading it
9502 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9503 this register live at every block boundary bar function entry
9504 and exit. It is then invalid to move the load (and thus the
9505 preceding store) across a block boundary.
9507 - If the function has no cprestore slot, we guarantee that
9508 pic_offset_table_rtx itself is valid at every branch.
9510 See mips_eh_uses for the handling of the register liveness.
9512 (3) During prologue and epilogue generation, we emit "ghost"
9513 placeholder instructions to manipulate the global pointer.
9515 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9516 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9517 that the function needs a global pointer. (There is no need to set
9518 them earlier than this, and doing it as late as possible leads to
9519 fewer false positives.)
9521 (5) If cfun->machine->must_initialize_gp_p is true during a
9522 split_insns pass, we split the ghost instructions into real
9523 instructions. These split instructions can then be optimized in
9524 the usual way. Otherwise, we keep the ghost instructions intact,
9525 and optimize for the case where they aren't needed. We still
9526 have the option of splitting them later, if we need to introduce
9527 new uses of the global pointer.
9529 For example, the scheduler ignores a ghost instruction that
9530 stores $28 to the stack, but it handles the split form of
9531 the ghost instruction as an ordinary store.
9533 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9534 is true during the first post-epilogue split_insns pass, we split
9535 calls and restore_gp patterns into instructions that explicitly
9536 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9537 we split these patterns into instructions that _don't_ load from
9540 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9541 time of the split, then any instructions that exist at that time
9542 can make free use of pic_offset_table_rtx. However, if we want
9543 to introduce new uses of the global pointer after the split,
9544 we must explicitly load the value from the cprestore slot, since
9545 pic_offset_table_rtx itself might not be valid at a given point
9548 The idea is that we want to be able to delete redundant
9549 loads from the cprestore slot in the usual case where no
9550 long branches are needed.
9552 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9553 of md_reorg, we decide whether the global pointer is needed for
9554 long branches. If so, we set cfun->machine->must_initialize_gp_p
9555 to true and split the ghost instructions into real instructions
9558 Note that the ghost instructions must have a zero length for three reasons:
9560 - Giving the length of the underlying $gp sequence might cause
9561 us to use long branches in cases where they aren't really needed.
9563 - They would perturb things like alignment calculations.
9565 - More importantly, the hazard detection in md_reorg relies on
9566 empty instructions having a zero length.
9568 If we find a long branch and split the ghost instructions at the
9569 end of md_reorg, the split could introduce more long branches.
9570 That isn't a problem though, because we still do the split before
9571 the final shorten_branches pass.
9573 This is extremely ugly, but it seems like the best compromise between
9574 correctness and efficiency. */
9577 mips_must_initialize_gp_p (void)
9579 return cfun->machine->must_initialize_gp_p;
9582 /* Return true if REGNO is a register that is ordinarily call-clobbered
9583 but must nevertheless be preserved by an interrupt handler. */
9586 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9588 if (MD_REG_P (regno))
9591 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9594 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9596 /* $0 is hard-wired. */
9597 if (regno == GP_REG_FIRST)
9600 /* The interrupt handler can treat kernel registers as
9601 scratch registers. */
9602 if (KERNEL_REG_P (regno))
9605 /* The function will return the stack pointer to its original value
9607 if (regno == STACK_POINTER_REGNUM)
9610 /* Otherwise, return true for registers that aren't ordinarily
9612 return call_really_used_regs[regno];
9618 /* Return true if the current function should treat register REGNO
9622 mips_cfun_call_saved_reg_p (unsigned int regno)
9624 /* If the user makes an ordinarily-call-saved register global,
9625 that register is no longer call-saved. */
9626 if (global_regs[regno])
9629 /* Interrupt handlers need to save extra registers. */
9630 if (cfun->machine->interrupt_handler_p
9631 && mips_interrupt_extra_call_saved_reg_p (regno))
9634 /* call_insns preserve $28 unless they explicitly say otherwise,
9635 so call_really_used_regs[] treats $28 as call-saved. However,
9636 we want the ABI property rather than the default call_insn
9638 return (regno == GLOBAL_POINTER_REGNUM
9639 ? TARGET_CALL_SAVED_GP
9640 : !call_really_used_regs[regno]);
9643 /* Return true if the function body might clobber register REGNO.
9644 We know that REGNO is call-saved. */
9647 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9649 /* Some functions should be treated as clobbering all call-saved
9651 if (crtl->saves_all_registers)
9654 /* DF handles cases where a register is explicitly referenced in
9655 the rtl. Incoming values are passed in call-clobbered registers,
9656 so we can assume that any live call-saved register is set within
9658 if (df_regs_ever_live_p (regno))
9661 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9662 These clobbers are not explicit in the rtl. */
9663 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9666 /* If we're using a call-saved global pointer, the function's
9667 prologue will need to set it up. */
9668 if (cfun->machine->global_pointer == regno)
9671 /* The function's prologue will need to set the frame pointer if
9672 frame_pointer_needed. */
9673 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9676 /* If a MIPS16 function returns a value in FPRs, its epilogue
9677 will need to call an external libgcc routine. This yet-to-be
9678 generated call_insn will clobber $31. */
9679 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9682 /* If REGNO is ordinarily call-clobbered, we must assume that any
9683 called function could modify it. */
9684 if (cfun->machine->interrupt_handler_p
9686 && mips_interrupt_extra_call_saved_reg_p (regno))
9692 /* Return true if the current function must save register REGNO. */
9695 mips_save_reg_p (unsigned int regno)
9697 if (mips_cfun_call_saved_reg_p (regno))
9699 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9702 /* Save both registers in an FPR pair if either one is used. This is
9703 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9704 register to be used without the even register. */
9705 if (FP_REG_P (regno)
9706 && MAX_FPRS_PER_FMT == 2
9707 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9711 /* We need to save the incoming return address if __builtin_eh_return
9712 is being used to set a different return address. */
9713 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9719 /* Populate the current function's mips_frame_info structure.
9721 MIPS stack frames look like:
9723 +-------------------------------+
9725 | incoming stack arguments |
9727 +-------------------------------+
9729 | caller-allocated save area |
9730 A | for register arguments |
9732 +-------------------------------+ <-- incoming stack pointer
9734 | callee-allocated save area |
9735 B | for arguments that are |
9736 | split between registers and |
9739 +-------------------------------+ <-- arg_pointer_rtx
9741 C | callee-allocated save area |
9742 | for register varargs |
9744 +-------------------------------+ <-- frame_pointer_rtx
9745 | | + cop0_sp_offset
9746 | COP0 reg save area | + UNITS_PER_WORD
9748 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9749 | | + UNITS_PER_WORD
9750 | accumulator save area |
9752 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9753 | | + UNITS_PER_HWFPVALUE
9756 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9757 | | + UNITS_PER_WORD
9760 +-------------------------------+ <-- frame_pointer_rtx with
9761 | | \ -fstack-protector
9762 | local variables | | var_size
9764 +-------------------------------+
9766 | $gp save area | | cprestore_size
9768 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9770 | outgoing stack arguments | |
9772 +-------------------------------+ | args_size
9774 | caller-allocated save area | |
9775 | for register arguments | |
9777 +-------------------------------+ <-- stack_pointer_rtx
9778 frame_pointer_rtx without
9780 hard_frame_pointer_rtx for
9783 At least two of A, B and C will be empty.
9785 Dynamic stack allocations such as alloca insert data at point P.
9786 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9787 hard_frame_pointer_rtx unchanged. */
9790 mips_compute_frame_info (void)
9792 struct mips_frame_info *frame;
9793 HOST_WIDE_INT offset, size;
9794 unsigned int regno, i;
9796 /* Set this function's interrupt properties. */
9797 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
9800 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9801 else if (TARGET_HARD_FLOAT)
9802 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9803 else if (TARGET_MIPS16)
9804 error ("interrupt handlers cannot be MIPS16 functions");
9807 cfun->machine->interrupt_handler_p = true;
9808 cfun->machine->use_shadow_register_set_p =
9809 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
9810 cfun->machine->keep_interrupts_masked_p =
9811 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
9812 cfun->machine->use_debug_exception_return_p =
9813 mips_use_debug_exception_return_p (TREE_TYPE
9814 (current_function_decl));
9818 frame = &cfun->machine->frame;
9819 memset (frame, 0, sizeof (*frame));
9820 size = get_frame_size ();
9822 cfun->machine->global_pointer = mips_global_pointer ();
9824 /* The first two blocks contain the outgoing argument area and the $gp save
9825 slot. This area isn't needed in leaf functions, but if the
9826 target-independent frame size is nonzero, we have already committed to
9827 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9828 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
9830 /* The MIPS 3.0 linker does not like functions that dynamically
9831 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9832 looks like we are trying to create a second frame pointer to the
9833 function, so allocate some stack space to make it happy. */
9834 if (cfun->calls_alloca)
9835 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
9837 frame->args_size = 0;
9838 frame->cprestore_size = 0;
9842 frame->args_size = crtl->outgoing_args_size;
9843 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
9845 offset = frame->args_size + frame->cprestore_size;
9847 /* Move above the local variables. */
9848 frame->var_size = MIPS_STACK_ALIGN (size);
9849 offset += frame->var_size;
9851 /* Find out which GPRs we need to save. */
9852 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9853 if (mips_save_reg_p (regno))
9856 frame->mask |= 1 << (regno - GP_REG_FIRST);
9859 /* If this function calls eh_return, we must also save and restore the
9860 EH data registers. */
9861 if (crtl->calls_eh_return)
9862 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
9865 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
9868 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9869 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9870 save all later registers too. */
9871 if (GENERATE_MIPS16E_SAVE_RESTORE)
9873 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
9874 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
9875 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
9876 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
9879 /* Move above the GPR save area. */
9880 if (frame->num_gp > 0)
9882 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
9883 frame->gp_sp_offset = offset - UNITS_PER_WORD;
9886 /* Find out which FPRs we need to save. This loop must iterate over
9887 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9888 if (TARGET_HARD_FLOAT)
9889 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
9890 if (mips_save_reg_p (regno))
9892 frame->num_fp += MAX_FPRS_PER_FMT;
9893 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
9896 /* Move above the FPR save area. */
9897 if (frame->num_fp > 0)
9899 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
9900 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
9903 /* Add in space for the interrupt context information. */
9904 if (cfun->machine->interrupt_handler_p)
9907 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
9910 frame->acc_mask |= (1 << 0);
9913 /* Check accumulators 1, 2, 3. */
9914 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
9915 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
9918 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
9921 /* All interrupt context functions need space to preserve STATUS. */
9922 frame->num_cop0_regs++;
9924 /* If we don't keep interrupts masked, we need to save EPC. */
9925 if (!cfun->machine->keep_interrupts_masked_p)
9926 frame->num_cop0_regs++;
9929 /* Move above the accumulator save area. */
9930 if (frame->num_acc > 0)
9932 /* Each accumulator needs 2 words. */
9933 offset += frame->num_acc * 2 * UNITS_PER_WORD;
9934 frame->acc_sp_offset = offset - UNITS_PER_WORD;
9937 /* Move above the COP0 register save area. */
9938 if (frame->num_cop0_regs > 0)
9940 offset += frame->num_cop0_regs * UNITS_PER_WORD;
9941 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
9944 /* Move above the callee-allocated varargs save area. */
9945 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
9946 frame->arg_pointer_offset = offset;
9948 /* Move above the callee-allocated area for pretend stack arguments. */
9949 offset += crtl->args.pretend_args_size;
9950 frame->total_size = offset;
9952 /* Work out the offsets of the save areas from the top of the frame. */
9953 if (frame->gp_sp_offset > 0)
9954 frame->gp_save_offset = frame->gp_sp_offset - offset;
9955 if (frame->fp_sp_offset > 0)
9956 frame->fp_save_offset = frame->fp_sp_offset - offset;
9957 if (frame->acc_sp_offset > 0)
9958 frame->acc_save_offset = frame->acc_sp_offset - offset;
9959 if (frame->num_cop0_regs > 0)
9960 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
9962 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9963 arguments. This tends to increase the chances of using unextended
9964 instructions for local variables and incoming arguments. */
9966 frame->hard_frame_pointer_offset = frame->args_size;
9969 /* Return the style of GP load sequence that is being used for the
9970 current function. */
9972 enum mips_loadgp_style
9973 mips_current_loadgp_style (void)
9975 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
9981 if (TARGET_ABSOLUTE_ABICALLS)
9982 return LOADGP_ABSOLUTE;
9984 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
9987 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9990 mips_frame_pointer_required (void)
9992 /* If the function contains dynamic stack allocations, we need to
9993 use the frame pointer to access the static parts of the frame. */
9994 if (cfun->calls_alloca)
9997 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9998 reload may be unable to compute the address of a local variable,
9999 since there is no way to add a large constant to the stack pointer
10000 without using a second temporary register. */
10003 mips_compute_frame_info ();
10004 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
10011 /* Make sure that we're not trying to eliminate to the wrong hard frame
10015 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
10017 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
10020 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10021 or argument pointer. TO is either the stack pointer or hard frame
10025 mips_initial_elimination_offset (int from, int to)
10027 HOST_WIDE_INT offset;
10029 mips_compute_frame_info ();
10031 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10034 case FRAME_POINTER_REGNUM:
10035 if (FRAME_GROWS_DOWNWARD)
10036 offset = (cfun->machine->frame.args_size
10037 + cfun->machine->frame.cprestore_size
10038 + cfun->machine->frame.var_size);
10043 case ARG_POINTER_REGNUM:
10044 offset = cfun->machine->frame.arg_pointer_offset;
10048 gcc_unreachable ();
10051 if (to == HARD_FRAME_POINTER_REGNUM)
10052 offset -= cfun->machine->frame.hard_frame_pointer_offset;
10057 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10060 mips_extra_live_on_entry (bitmap regs)
10062 if (TARGET_USE_GOT)
10064 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10065 the global pointer. */
10066 if (!TARGET_ABSOLUTE_ABICALLS)
10067 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10069 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10070 the global pointer. */
10072 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
10074 /* See the comment above load_call<mode> for details. */
10075 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
10079 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10083 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
10088 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
10091 /* Emit code to change the current function's return address to
10092 ADDRESS. SCRATCH is available as a scratch register, if needed.
10093 ADDRESS and SCRATCH are both word-mode GPRs. */
10096 mips_set_return_address (rtx address, rtx scratch)
10100 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
10101 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
10102 cfun->machine->frame.gp_sp_offset);
10103 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
10106 /* Return true if the current function has a cprestore slot. */
10109 mips_cfun_has_cprestore_slot_p (void)
10111 return (cfun->machine->global_pointer != INVALID_REGNUM
10112 && cfun->machine->frame.cprestore_size > 0);
10115 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10116 cprestore slot. LOAD_P is true if the caller wants to load from
10117 the cprestore slot; it is false if the caller wants to store to
10121 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
10124 const struct mips_frame_info *frame;
10126 frame = &cfun->machine->frame;
10127 /* .cprestore always uses the stack pointer instead of the frame pointer.
10128 We have a free choice for direct stores for non-MIPS16 functions,
10129 and for MIPS16 functions whose cprestore slot is in range of the
10130 stack pointer. Using the stack pointer would sometimes give more
10131 (early) scheduling freedom, but using the frame pointer would
10132 sometimes give more (late) scheduling freedom. It's hard to
10133 predict which applies to a given function, so let's keep things
10136 Loads must always use the frame pointer in functions that call
10137 alloca, and there's little benefit to using the stack pointer
10139 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
10141 *base = hard_frame_pointer_rtx;
10142 *offset = frame->args_size - frame->hard_frame_pointer_offset;
10146 *base = stack_pointer_rtx;
10147 *offset = frame->args_size;
10151 /* Return true if X is the load or store address of the cprestore slot;
10152 LOAD_P says which. */
10155 mips_cprestore_address_p (rtx x, bool load_p)
10157 rtx given_base, required_base;
10158 HOST_WIDE_INT given_offset, required_offset;
10160 mips_split_plus (x, &given_base, &given_offset);
10161 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
10162 return given_base == required_base && given_offset == required_offset;
10165 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10166 going to load from it, false if we are going to store to it.
10167 Use TEMP as a temporary register if need be. */
10170 mips_cprestore_slot (rtx temp, bool load_p)
10173 HOST_WIDE_INT offset;
10175 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
10176 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
10179 /* Emit instructions to save global pointer value GP into cprestore
10180 slot MEM. OFFSET is the offset that MEM applies to the base register.
10182 MEM may not be a legitimate address. If it isn't, TEMP is a
10183 temporary register that can be used, otherwise it is a SCRATCH. */
10186 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
10188 if (TARGET_CPRESTORE_DIRECTIVE)
10190 gcc_assert (gp == pic_offset_table_rtx);
10191 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
10194 mips_emit_move (mips_cprestore_slot (temp, false), gp);
10197 /* Restore $gp from its save slot, using TEMP as a temporary base register
10198 if need be. This function is for o32 and o64 abicalls only.
10200 See mips_must_initialize_gp_p for details about how we manage the
10204 mips_restore_gp_from_cprestore_slot (rtx temp)
10206 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
10208 if (!cfun->machine->must_restore_gp_when_clobbered_p)
10210 emit_note (NOTE_INSN_DELETED);
10216 mips_emit_move (temp, mips_cprestore_slot (temp, true));
10217 mips_emit_move (pic_offset_table_rtx, temp);
10220 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
10221 if (!TARGET_EXPLICIT_RELOCS)
10222 emit_insn (gen_blockage ());
10225 /* A function to save or store a register. The first argument is the
10226 register and the second is the stack slot. */
10227 typedef void (*mips_save_restore_fn) (rtx, rtx);
10229 /* Use FN to save or restore register REGNO. MODE is the register's
10230 mode and OFFSET is the offset of its save slot from the current
10234 mips_save_restore_reg (enum machine_mode mode, int regno,
10235 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10239 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10241 fn (gen_rtx_REG (mode, regno), mem);
10244 /* Call FN for each accumlator that is saved by the current function.
10245 SP_OFFSET is the offset of the current stack pointer from the start
10249 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10251 HOST_WIDE_INT offset;
10254 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10255 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10257 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10258 offset -= UNITS_PER_WORD;
10259 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10260 offset -= UNITS_PER_WORD;
10263 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10264 if (BITSET_P (cfun->machine->frame.acc_mask,
10265 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10267 mips_save_restore_reg (word_mode, regno, offset, fn);
10268 offset -= UNITS_PER_WORD;
10272 /* Call FN for each register that is saved by the current function.
10273 SP_OFFSET is the offset of the current stack pointer from the start
10277 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10278 mips_save_restore_fn fn)
10280 enum machine_mode fpr_mode;
10281 HOST_WIDE_INT offset;
10284 /* Save registers starting from high to low. The debuggers prefer at least
10285 the return register be stored at func+4, and also it allows us not to
10286 need a nop in the epilogue if at least one register is reloaded in
10287 addition to return address. */
10288 offset = cfun->machine->frame.gp_sp_offset - sp_offset;
10289 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10290 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST))
10292 /* Record the ra offset for use by mips_function_profiler. */
10293 if (regno == RETURN_ADDR_REGNUM)
10294 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10295 mips_save_restore_reg (word_mode, regno, offset, fn);
10296 offset -= UNITS_PER_WORD;
10299 /* This loop must iterate over the same space as its companion in
10300 mips_compute_frame_info. */
10301 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10302 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10303 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10304 regno >= FP_REG_FIRST;
10305 regno -= MAX_FPRS_PER_FMT)
10306 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10308 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10309 offset -= GET_MODE_SIZE (fpr_mode);
10313 /* Return true if a move between register REGNO and its save slot (MEM)
10314 can be done in a single move. LOAD_P is true if we are loading
10315 from the slot, false if we are storing to it. */
10318 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10320 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10321 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10324 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10325 GET_MODE (mem), mem, load_p) == NO_REGS;
10328 /* Emit a move from SRC to DEST, given that one of them is a register
10329 save slot and that the other is a register. TEMP is a temporary
10330 GPR of the same mode that is available if need be. */
10333 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10335 unsigned int regno;
10340 regno = REGNO (src);
10345 regno = REGNO (dest);
10349 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10351 /* We don't yet know whether we'll need this instruction or not.
10352 Postpone the decision by emitting a ghost move. This move
10353 is specifically not frame-related; only the split version is. */
10355 emit_insn (gen_move_gpdi (dest, src));
10357 emit_insn (gen_move_gpsi (dest, src));
10361 if (regno == HI_REGNUM)
10365 mips_emit_move (temp, src);
10367 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10368 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10370 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10371 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10376 emit_insn (gen_mfhidi_ti (temp,
10377 gen_rtx_REG (TImode, MD_REG_FIRST)));
10379 emit_insn (gen_mfhisi_di (temp,
10380 gen_rtx_REG (DImode, MD_REG_FIRST)));
10381 mips_emit_move (dest, temp);
10384 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10385 mips_emit_move (dest, src);
10388 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10389 mips_emit_move (temp, src);
10390 mips_emit_move (dest, temp);
10393 mips_set_frame_expr (mips_frame_set (dest, src));
10396 /* If we're generating n32 or n64 abicalls, and the current function
10397 does not use $28 as its global pointer, emit a cplocal directive.
10398 Use pic_offset_table_rtx as the argument to the directive. */
10401 mips_output_cplocal (void)
10403 if (!TARGET_EXPLICIT_RELOCS
10404 && mips_must_initialize_gp_p ()
10405 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10406 output_asm_insn (".cplocal %+", 0);
10409 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10412 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10414 const char *fnname;
10416 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10417 floating-point arguments. */
10419 && TARGET_HARD_FLOAT_ABI
10420 && crtl->args.info.fp_code != 0)
10421 mips16_build_function_stub ();
10423 /* Get the function name the same way that toplev.c does before calling
10424 assemble_start_function. This is needed so that the name used here
10425 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10426 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10427 mips_start_function_definition (fnname, TARGET_MIPS16);
10429 /* Output MIPS-specific frame information. */
10430 if (!flag_inhibit_size_directive)
10432 const struct mips_frame_info *frame;
10434 frame = &cfun->machine->frame;
10436 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10438 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10439 "# vars= " HOST_WIDE_INT_PRINT_DEC
10441 ", args= " HOST_WIDE_INT_PRINT_DEC
10442 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10443 reg_names[frame_pointer_needed
10444 ? HARD_FRAME_POINTER_REGNUM
10445 : STACK_POINTER_REGNUM],
10446 (frame_pointer_needed
10447 ? frame->total_size - frame->hard_frame_pointer_offset
10448 : frame->total_size),
10449 reg_names[RETURN_ADDR_REGNUM],
10451 frame->num_gp, frame->num_fp,
10453 frame->cprestore_size);
10455 /* .mask MASK, OFFSET. */
10456 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10457 frame->mask, frame->gp_save_offset);
10459 /* .fmask MASK, OFFSET. */
10460 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10461 frame->fmask, frame->fp_save_offset);
10464 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10465 Also emit the ".set noreorder; .set nomacro" sequence for functions
10467 if (mips_must_initialize_gp_p ()
10468 && mips_current_loadgp_style () == LOADGP_OLDABI)
10472 /* This is a fixed-form sequence. The position of the
10473 first two instructions is important because of the
10474 way _gp_disp is defined. */
10475 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10476 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10477 output_asm_insn ("sll\t$2,16", 0);
10478 output_asm_insn ("addu\t$2,$3", 0);
10482 /* .cpload must be in a .set noreorder but not a
10483 .set nomacro block. */
10484 mips_push_asm_switch (&mips_noreorder);
10485 output_asm_insn (".cpload\t%^", 0);
10486 if (!cfun->machine->all_noreorder_p)
10487 mips_pop_asm_switch (&mips_noreorder);
10489 mips_push_asm_switch (&mips_nomacro);
10492 else if (cfun->machine->all_noreorder_p)
10494 mips_push_asm_switch (&mips_noreorder);
10495 mips_push_asm_switch (&mips_nomacro);
10498 /* Tell the assembler which register we're using as the global
10499 pointer. This is needed for thunks, since they can use either
10500 explicit relocs or assembler macros. */
10501 mips_output_cplocal ();
10504 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10507 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10508 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10510 const char *fnname;
10512 /* Reinstate the normal $gp. */
10513 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10514 mips_output_cplocal ();
10516 if (cfun->machine->all_noreorder_p)
10518 mips_pop_asm_switch (&mips_nomacro);
10519 mips_pop_asm_switch (&mips_noreorder);
10522 /* Get the function name the same way that toplev.c does before calling
10523 assemble_start_function. This is needed so that the name used here
10524 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10525 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10526 mips_end_function_definition (fnname);
10529 /* Emit an optimisation barrier for accesses to the current frame. */
10532 mips_frame_barrier (void)
10534 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10537 /* Save register REG to MEM. Make the instruction frame-related. */
10540 mips_save_reg (rtx reg, rtx mem)
10542 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10546 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
10548 x1 = mips_frame_set (mips_subword (mem, false),
10549 mips_subword (reg, false));
10550 x2 = mips_frame_set (mips_subword (mem, true),
10551 mips_subword (reg, true));
10552 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10555 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10558 /* The __gnu_local_gp symbol. */
10560 static GTY(()) rtx mips_gnu_local_gp;
10562 /* If we're generating n32 or n64 abicalls, emit instructions
10563 to set up the global pointer. */
10566 mips_emit_loadgp (void)
10568 rtx addr, offset, incoming_address, base, index, pic_reg;
10570 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10571 switch (mips_current_loadgp_style ())
10573 case LOADGP_ABSOLUTE:
10574 if (mips_gnu_local_gp == NULL)
10576 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10577 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10579 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10580 (pic_reg, mips_gnu_local_gp)));
10583 case LOADGP_OLDABI:
10584 /* Added by mips_output_function_prologue. */
10587 case LOADGP_NEWABI:
10588 addr = XEXP (DECL_RTL (current_function_decl), 0);
10589 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10590 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10591 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10592 (pic_reg, offset, incoming_address)));
10596 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10597 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10598 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10606 emit_insn (PMODE_INSN (gen_copygp_mips16,
10607 (pic_offset_table_rtx, pic_reg)));
10609 /* Emit a blockage if there are implicit uses of the GP register.
10610 This includes profiled functions, because FUNCTION_PROFILE uses
10612 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10613 emit_insn (gen_loadgp_blockage ());
10616 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10619 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
10621 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
10624 /* Expand the "prologue" pattern. */
10627 mips_expand_prologue (void)
10629 const struct mips_frame_info *frame;
10630 HOST_WIDE_INT size;
10631 unsigned int nargs;
10634 if (cfun->machine->global_pointer != INVALID_REGNUM)
10636 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10637 or implicitly. If so, we can commit to using a global pointer
10638 straight away, otherwise we need to defer the decision. */
10639 if (mips_cfun_has_inflexible_gp_ref_p ()
10640 || mips_cfun_has_flexible_gp_ref_p ())
10642 cfun->machine->must_initialize_gp_p = true;
10643 cfun->machine->must_restore_gp_when_clobbered_p = true;
10646 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
10649 frame = &cfun->machine->frame;
10650 size = frame->total_size;
10652 if (flag_stack_usage_info)
10653 current_function_static_stack_size = size;
10655 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10656 bytes beforehand; this is enough to cover the register save area
10657 without going out of range. */
10658 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
10659 || frame->num_cop0_regs > 0)
10661 HOST_WIDE_INT step1;
10663 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
10664 if (GENERATE_MIPS16E_SAVE_RESTORE)
10666 HOST_WIDE_INT offset;
10667 unsigned int mask, regno;
10669 /* Try to merge argument stores into the save instruction. */
10670 nargs = mips16e_collect_argument_saves ();
10672 /* Build the save instruction. */
10673 mask = frame->mask;
10674 insn = mips16e_build_save_restore (false, &mask, &offset,
10676 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10677 mips_frame_barrier ();
10680 /* Check if we need to save other registers. */
10681 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
10682 if (BITSET_P (mask, regno - GP_REG_FIRST))
10684 offset -= UNITS_PER_WORD;
10685 mips_save_restore_reg (word_mode, regno,
10686 offset, mips_save_reg);
10691 if (cfun->machine->interrupt_handler_p)
10693 HOST_WIDE_INT offset;
10696 /* If this interrupt is using a shadow register set, we need to
10697 get the stack pointer from the previous register set. */
10698 if (cfun->machine->use_shadow_register_set_p)
10699 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
10700 stack_pointer_rtx));
10702 if (!cfun->machine->keep_interrupts_masked_p)
10704 /* Move from COP0 Cause to K0. */
10705 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
10706 gen_rtx_REG (SImode,
10707 COP0_CAUSE_REG_NUM)));
10708 /* Move from COP0 EPC to K1. */
10709 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10710 gen_rtx_REG (SImode,
10711 COP0_EPC_REG_NUM)));
10714 /* Allocate the first part of the frame. */
10715 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
10717 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10718 mips_frame_barrier ();
10721 /* Start at the uppermost location for saving. */
10722 offset = frame->cop0_sp_offset - size;
10723 if (!cfun->machine->keep_interrupts_masked_p)
10725 /* Push EPC into its stack slot. */
10726 mem = gen_frame_mem (word_mode,
10727 plus_constant (Pmode, stack_pointer_rtx,
10729 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10730 offset -= UNITS_PER_WORD;
10733 /* Move from COP0 Status to K1. */
10734 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
10735 gen_rtx_REG (SImode,
10736 COP0_STATUS_REG_NUM)));
10738 /* Right justify the RIPL in k0. */
10739 if (!cfun->machine->keep_interrupts_masked_p)
10740 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
10741 gen_rtx_REG (SImode, K0_REG_NUM),
10742 GEN_INT (CAUSE_IPL)));
10744 /* Push Status into its stack slot. */
10745 mem = gen_frame_mem (word_mode,
10746 plus_constant (Pmode, stack_pointer_rtx,
10748 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
10749 offset -= UNITS_PER_WORD;
10751 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10752 if (!cfun->machine->keep_interrupts_masked_p)
10753 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10756 gen_rtx_REG (SImode, K0_REG_NUM)));
10758 if (!cfun->machine->keep_interrupts_masked_p)
10759 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10760 IE is already the correct value, so we don't have to do
10761 anything explicit. */
10762 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10765 gen_rtx_REG (SImode, GP_REG_FIRST)));
10767 /* Disable interrupts by clearing the KSU, ERL, EXL,
10769 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
10772 gen_rtx_REG (SImode, GP_REG_FIRST)));
10776 insn = gen_add3_insn (stack_pointer_rtx,
10779 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10780 mips_frame_barrier ();
10783 mips_for_each_saved_acc (size, mips_save_reg);
10784 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
10788 /* Allocate the rest of the frame. */
10791 if (SMALL_OPERAND (-size))
10792 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
10794 GEN_INT (-size)))) = 1;
10797 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
10800 /* There are no instructions to add or subtract registers
10801 from the stack pointer, so use the frame pointer as a
10802 temporary. We should always be using a frame pointer
10803 in this case anyway. */
10804 gcc_assert (frame_pointer_needed);
10805 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10806 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
10807 hard_frame_pointer_rtx,
10808 MIPS_PROLOGUE_TEMP (Pmode)));
10809 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
10812 emit_insn (gen_sub3_insn (stack_pointer_rtx,
10814 MIPS_PROLOGUE_TEMP (Pmode)));
10816 /* Describe the combined effect of the previous instructions. */
10817 mips_set_frame_expr
10818 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
10819 plus_constant (Pmode, stack_pointer_rtx, -size)));
10821 mips_frame_barrier ();
10824 /* Set up the frame pointer, if we're using one. */
10825 if (frame_pointer_needed)
10827 HOST_WIDE_INT offset;
10829 offset = frame->hard_frame_pointer_offset;
10832 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10833 RTX_FRAME_RELATED_P (insn) = 1;
10835 else if (SMALL_OPERAND (offset))
10837 insn = gen_add3_insn (hard_frame_pointer_rtx,
10838 stack_pointer_rtx, GEN_INT (offset));
10839 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
10843 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
10844 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
10845 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
10846 hard_frame_pointer_rtx,
10847 MIPS_PROLOGUE_TEMP (Pmode)));
10848 mips_set_frame_expr
10849 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
10850 plus_constant (Pmode, stack_pointer_rtx, offset)));
10854 mips_emit_loadgp ();
10856 /* Initialize the $gp save slot. */
10857 if (mips_cfun_has_cprestore_slot_p ())
10859 rtx base, mem, gp, temp;
10860 HOST_WIDE_INT offset;
10862 mips_get_cprestore_base_and_offset (&base, &offset, false);
10863 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
10864 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10865 temp = (SMALL_OPERAND (offset)
10866 ? gen_rtx_SCRATCH (Pmode)
10867 : MIPS_PROLOGUE_TEMP (Pmode));
10868 emit_insn (PMODE_INSN (gen_potential_cprestore,
10869 (mem, GEN_INT (offset), gp, temp)));
10871 mips_get_cprestore_base_and_offset (&base, &offset, true);
10872 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
10873 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
10876 /* We need to search back to the last use of K0 or K1. */
10877 if (cfun->machine->interrupt_handler_p)
10879 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
10881 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
10883 /* Emit a move from K1 to COP0 Status after insn. */
10884 gcc_assert (insn != NULL_RTX);
10885 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
10886 gen_rtx_REG (SImode, K1_REG_NUM)),
10890 /* If we are profiling, make sure no instructions are scheduled before
10891 the call to mcount. */
10893 emit_insn (gen_blockage ());
10896 /* Attach all pending register saves to the previous instruction.
10897 Return that instruction. */
10900 mips_epilogue_emit_cfa_restores (void)
10904 insn = get_last_insn ();
10905 gcc_assert (insn && !REG_NOTES (insn));
10906 if (mips_epilogue.cfa_restores)
10908 RTX_FRAME_RELATED_P (insn) = 1;
10909 REG_NOTES (insn) = mips_epilogue.cfa_restores;
10910 mips_epilogue.cfa_restores = 0;
10915 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
10916 now at REG + OFFSET. */
10919 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
10923 insn = mips_epilogue_emit_cfa_restores ();
10924 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
10926 RTX_FRAME_RELATED_P (insn) = 1;
10927 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
10928 plus_constant (Pmode, reg, offset),
10930 mips_epilogue.cfa_reg = reg;
10931 mips_epilogue.cfa_offset = offset;
10935 /* Emit instructions to restore register REG from slot MEM. Also update
10936 the cfa_restores list. */
10939 mips_restore_reg (rtx reg, rtx mem)
10941 /* There's no MIPS16 instruction to load $31 directly. Load into
10942 $7 instead and adjust the return insn appropriately. */
10943 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
10944 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
10945 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10947 mips_add_cfa_restore (mips_subword (reg, true));
10948 mips_add_cfa_restore (mips_subword (reg, false));
10951 mips_add_cfa_restore (reg);
10953 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
10954 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
10955 /* The CFA is currently defined in terms of the register whose
10956 value we have just restored. Redefine the CFA in terms of
10957 the stack pointer. */
10958 mips_epilogue_set_cfa (stack_pointer_rtx,
10959 mips_epilogue.cfa_restore_sp_offset);
10962 /* Emit code to set the stack pointer to BASE + OFFSET, given that
10963 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
10964 BASE, if not the stack pointer, is available as a temporary. */
10967 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
10969 if (base == stack_pointer_rtx && offset == const0_rtx)
10972 mips_frame_barrier ();
10973 if (offset == const0_rtx)
10975 emit_move_insn (stack_pointer_rtx, base);
10976 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
10978 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
10980 emit_insn (gen_add3_insn (base, base, offset));
10981 mips_epilogue_set_cfa (base, new_frame_size);
10982 emit_move_insn (stack_pointer_rtx, base);
10986 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
10987 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
10991 /* Emit any instructions needed before a return. */
10994 mips_expand_before_return (void)
10996 /* When using a call-clobbered gp, we start out with unified call
10997 insns that include instructions to restore the gp. We then split
10998 these unified calls after reload. These split calls explicitly
10999 clobber gp, so there is no need to define
11000 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11002 For consistency, we should also insert an explicit clobber of $28
11003 before return insns, so that the post-reload optimizers know that
11004 the register is not live on exit. */
11005 if (TARGET_CALL_CLOBBERED_GP)
11006 emit_clobber (pic_offset_table_rtx);
11009 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11013 mips_expand_epilogue (bool sibcall_p)
11015 const struct mips_frame_info *frame;
11016 HOST_WIDE_INT step1, step2;
11017 rtx base, adjust, insn;
11019 if (!sibcall_p && mips_can_use_return_insn ())
11021 emit_jump_insn (gen_return ());
11025 /* In MIPS16 mode, if the return value should go into a floating-point
11026 register, we need to call a helper routine to copy it over. */
11027 if (mips16_cfun_returns_in_fpr_p ())
11028 mips16_copy_fpr_return_value ();
11030 /* Split the frame into two. STEP1 is the amount of stack we should
11031 deallocate before restoring the registers. STEP2 is the amount we
11032 should deallocate afterwards.
11034 Start off by assuming that no registers need to be restored. */
11035 frame = &cfun->machine->frame;
11036 step1 = frame->total_size;
11039 /* Work out which register holds the frame address. */
11040 if (!frame_pointer_needed)
11041 base = stack_pointer_rtx;
11044 base = hard_frame_pointer_rtx;
11045 step1 -= frame->hard_frame_pointer_offset;
11047 mips_epilogue.cfa_reg = base;
11048 mips_epilogue.cfa_offset = step1;
11049 mips_epilogue.cfa_restores = NULL_RTX;
11051 /* If we need to restore registers, deallocate as much stack as
11052 possible in the second step without going out of range. */
11053 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
11054 || frame->num_cop0_regs > 0)
11056 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
11060 /* Get an rtx for STEP1 that we can add to BASE. */
11061 adjust = GEN_INT (step1);
11062 if (!SMALL_OPERAND (step1))
11064 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
11065 adjust = MIPS_EPILOGUE_TEMP (Pmode);
11067 mips_deallocate_stack (base, adjust, step2);
11069 /* If we're using addressing macros, $gp is implicitly used by all
11070 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11072 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
11073 emit_insn (gen_blockage ());
11075 mips_epilogue.cfa_restore_sp_offset = step2;
11076 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
11078 unsigned int regno, mask;
11079 HOST_WIDE_INT offset;
11082 /* Generate the restore instruction. */
11083 mask = frame->mask;
11084 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
11086 /* Restore any other registers manually. */
11087 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11088 if (BITSET_P (mask, regno - GP_REG_FIRST))
11090 offset -= UNITS_PER_WORD;
11091 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
11094 /* Restore the remaining registers and deallocate the final bit
11096 mips_frame_barrier ();
11097 emit_insn (restore);
11098 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
11102 /* Restore the registers. */
11103 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
11104 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
11107 if (cfun->machine->interrupt_handler_p)
11109 HOST_WIDE_INT offset;
11112 offset = frame->cop0_sp_offset - (frame->total_size - step2);
11113 if (!cfun->machine->keep_interrupts_masked_p)
11115 /* Restore the original EPC. */
11116 mem = gen_frame_mem (word_mode,
11117 plus_constant (Pmode, stack_pointer_rtx,
11119 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11120 offset -= UNITS_PER_WORD;
11122 /* Move to COP0 EPC. */
11123 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
11124 gen_rtx_REG (SImode, K0_REG_NUM)));
11127 /* Restore the original Status. */
11128 mem = gen_frame_mem (word_mode,
11129 plus_constant (Pmode, stack_pointer_rtx,
11131 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11132 offset -= UNITS_PER_WORD;
11134 /* If we don't use shoadow register set, we need to update SP. */
11135 if (!cfun->machine->use_shadow_register_set_p)
11136 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11138 /* The choice of position is somewhat arbitrary in this case. */
11139 mips_epilogue_emit_cfa_restores ();
11141 /* Move to COP0 Status. */
11142 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11143 gen_rtx_REG (SImode, K0_REG_NUM)));
11146 /* Deallocate the final bit of the frame. */
11147 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11149 gcc_assert (!mips_epilogue.cfa_restores);
11151 /* Add in the __builtin_eh_return stack adjustment. We need to
11152 use a temporary in MIPS16 code. */
11153 if (crtl->calls_eh_return)
11157 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
11158 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
11159 MIPS_EPILOGUE_TEMP (Pmode),
11160 EH_RETURN_STACKADJ_RTX));
11161 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
11164 emit_insn (gen_add3_insn (stack_pointer_rtx,
11166 EH_RETURN_STACKADJ_RTX));
11171 mips_expand_before_return ();
11172 if (cfun->machine->interrupt_handler_p)
11174 /* Interrupt handlers generate eret or deret. */
11175 if (cfun->machine->use_debug_exception_return_p)
11176 emit_jump_insn (gen_mips_deret ());
11178 emit_jump_insn (gen_mips_eret ());
11184 /* When generating MIPS16 code, the normal
11185 mips_for_each_saved_gpr_and_fpr path will restore the return
11186 address into $7 rather than $31. */
11188 && !GENERATE_MIPS16E_SAVE_RESTORE
11189 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
11191 /* simple_returns cannot rely on values that are only available
11192 on paths through the epilogue (because return paths that do
11193 not pass through the epilogue may nevertheless reuse a
11194 simple_return that occurs at the end of the epilogue).
11195 Use a normal return here instead. */
11196 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
11197 pat = gen_return_internal (reg);
11201 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
11202 pat = gen_simple_return_internal (reg);
11204 emit_jump_insn (pat);
11208 /* Search from the beginning to the first use of K0 or K1. */
11209 if (cfun->machine->interrupt_handler_p
11210 && !cfun->machine->keep_interrupts_masked_p)
11212 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
11214 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
11216 gcc_assert (insn != NULL_RTX);
11217 /* Insert disable interrupts before the first use of K0 or K1. */
11218 emit_insn_before (gen_mips_di (), insn);
11219 emit_insn_before (gen_mips_ehb (), insn);
11223 /* Return nonzero if this function is known to have a null epilogue.
11224 This allows the optimizer to omit jumps to jumps if no stack
11228 mips_can_use_return_insn (void)
11230 /* Interrupt handlers need to go through the epilogue. */
11231 if (cfun->machine->interrupt_handler_p)
11234 if (!reload_completed)
11240 /* In MIPS16 mode, a function that returns a floating-point value
11241 needs to arrange to copy the return value into the floating-point
11243 if (mips16_cfun_returns_in_fpr_p ())
11246 return cfun->machine->frame.total_size == 0;
11249 /* Return true if register REGNO can store a value of mode MODE.
11250 The result of this function is cached in mips_hard_regno_mode_ok. */
11253 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
11256 enum mode_class mclass;
11258 if (mode == CCV2mode)
11259 return (ISA_HAS_8CC
11260 && ST_REG_P (regno)
11261 && (regno - ST_REG_FIRST) % 2 == 0);
11263 if (mode == CCV4mode)
11264 return (ISA_HAS_8CC
11265 && ST_REG_P (regno)
11266 && (regno - ST_REG_FIRST) % 4 == 0);
11268 if (mode == CCmode)
11269 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
11271 size = GET_MODE_SIZE (mode);
11272 mclass = GET_MODE_CLASS (mode);
11274 if (GP_REG_P (regno))
11275 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11277 if (FP_REG_P (regno)
11278 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11279 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11281 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11282 if (TARGET_LOONGSON_VECTORS
11283 && (mode == V2SImode
11284 || mode == V4HImode
11285 || mode == V8QImode
11286 || mode == DImode))
11289 if (mclass == MODE_FLOAT
11290 || mclass == MODE_COMPLEX_FLOAT
11291 || mclass == MODE_VECTOR_FLOAT)
11292 return size <= UNITS_PER_FPVALUE;
11294 /* Allow integer modes that fit into a single register. We need
11295 to put integers into FPRs when using instructions like CVT
11296 and TRUNC. There's no point allowing sizes smaller than a word,
11297 because the FPU has no appropriate load/store instructions. */
11298 if (mclass == MODE_INT)
11299 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11302 if (ACC_REG_P (regno)
11303 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11305 if (MD_REG_P (regno))
11307 /* After a multiplication or division, clobbering HI makes
11308 the value of LO unpredictable, and vice versa. This means
11309 that, for all interesting cases, HI and LO are effectively
11312 We model this by requiring that any value that uses HI
11314 if (size <= UNITS_PER_WORD * 2)
11315 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11319 /* DSP accumulators do not have the same restrictions as
11320 HI and LO, so we can treat them as normal doubleword
11322 if (size <= UNITS_PER_WORD)
11325 if (size <= UNITS_PER_WORD * 2
11326 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11331 if (ALL_COP_REG_P (regno))
11332 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11334 if (regno == GOT_VERSION_REGNUM)
11335 return mode == SImode;
11340 /* Implement HARD_REGNO_NREGS. */
11343 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11345 if (ST_REG_P (regno))
11346 /* The size of FP status registers is always 4, because they only hold
11347 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11348 return (GET_MODE_SIZE (mode) + 3) / 4;
11350 if (FP_REG_P (regno))
11351 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11353 /* All other registers are word-sized. */
11354 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11357 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11358 in mips_hard_regno_nregs. */
11361 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11367 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11368 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11370 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11371 size = MIN (size, 4);
11372 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11374 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11376 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11377 size = MIN (size, UNITS_PER_FPREG);
11378 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11380 if (!hard_reg_set_empty_p (left))
11381 size = MIN (size, UNITS_PER_WORD);
11382 return (GET_MODE_SIZE (mode) + size - 1) / size;
11385 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11388 mips_cannot_change_mode_class (enum machine_mode from,
11389 enum machine_mode to,
11390 enum reg_class rclass)
11392 /* Allow conversions between different Loongson integer vectors,
11393 and between those vectors and DImode. */
11394 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11395 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11398 /* Otherwise, there are several problems with changing the modes of
11399 values in floating-point registers:
11401 - When a multi-word value is stored in paired floating-point
11402 registers, the first register always holds the low word. We
11403 therefore can't allow FPRs to change between single-word and
11404 multi-word modes on big-endian targets.
11406 - GCC assumes that each word of a multiword register can be
11407 accessed individually using SUBREGs. This is not true for
11408 floating-point registers if they are bigger than a word.
11410 - Loading a 32-bit value into a 64-bit floating-point register
11411 will not sign-extend the value, despite what LOAD_EXTEND_OP
11412 says. We can't allow FPRs to change from SImode to a wider
11413 mode on 64-bit targets.
11415 - If the FPU has already interpreted a value in one format, we
11416 must not ask it to treat the value as having a different
11419 We therefore disallow all mode changes involving FPRs. */
11421 return reg_classes_intersect_p (FP_REGS, rclass);
11424 /* Implement target hook small_register_classes_for_mode_p. */
11427 mips_small_register_classes_for_mode_p (enum machine_mode mode
11430 return TARGET_MIPS16;
11433 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11436 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11441 return TARGET_HARD_FLOAT;
11444 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11447 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11454 /* Implement MODES_TIEABLE_P. */
11457 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11459 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11460 prefer to put one of them in FPRs. */
11461 return (mode1 == mode2
11462 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11463 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11466 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11469 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11471 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11474 if (reg_class_subset_p (FP_REGS, rclass)
11475 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11478 if (reg_class_subset_p (GR_REGS, rclass))
11481 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11487 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11488 Return a "canonical" class to represent it in later calculations. */
11491 mips_canonicalize_move_class (reg_class_t rclass)
11493 /* All moves involving accumulator registers have the same cost. */
11494 if (reg_class_subset_p (rclass, ACC_REGS))
11497 /* Likewise promote subclasses of general registers to the most
11498 interesting containing class. */
11499 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11501 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11502 rclass = GENERAL_REGS;
11507 /* Return the cost of moving a value of mode MODE from a register of
11508 class FROM to a GPR. Return 0 for classes that are unions of other
11509 classes handled by this function. */
11512 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
11518 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11522 /* MFLO and MFHI. */
11530 /* LUI followed by MOVF. */
11536 /* This choice of value is historical. */
11544 /* Return the cost of moving a value of mode MODE from a GPR to a
11545 register of class TO. Return 0 for classes that are unions of
11546 other classes handled by this function. */
11549 mips_move_from_gpr_cost (enum machine_mode mode, reg_class_t to)
11554 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11558 /* MTLO and MTHI. */
11566 /* A secondary reload through an FPR scratch. */
11567 return (mips_register_move_cost (mode, GENERAL_REGS, FP_REGS)
11568 + mips_register_move_cost (mode, FP_REGS, ST_REGS));
11573 /* This choice of value is historical. */
11581 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
11582 maximum of the move costs for subclasses; regclass will work out
11583 the maximum for us. */
11586 mips_register_move_cost (enum machine_mode mode,
11587 reg_class_t from, reg_class_t to)
11592 from = mips_canonicalize_move_class (from);
11593 to = mips_canonicalize_move_class (to);
11595 /* Handle moves that can be done without using general-purpose registers. */
11596 if (from == FP_REGS)
11598 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
11602 /* The sequence generated by mips_expand_fcc_reload. */
11606 /* Handle cases in which only one class deviates from the ideal. */
11607 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
11609 return mips_move_from_gpr_cost (mode, to);
11611 return mips_move_to_gpr_cost (mode, from);
11613 /* Handles cases that require a GPR temporary. */
11614 cost1 = mips_move_to_gpr_cost (mode, from);
11617 cost2 = mips_move_from_gpr_cost (mode, to);
11619 return cost1 + cost2;
11625 /* Implement TARGET_MEMORY_MOVE_COST. */
11628 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
11630 return (mips_cost->memory_latency
11631 + memory_move_secondary_cost (mode, rclass, in));
11634 /* Return the register class required for a secondary register when
11635 copying between one of the registers in RCLASS and value X, which
11636 has mode MODE. X is the source of the move if IN_P, otherwise it
11637 is the destination. Return NO_REGS if no secondary register is
11641 mips_secondary_reload_class (enum reg_class rclass,
11642 enum machine_mode mode, rtx x, bool in_p)
11646 /* If X is a constant that cannot be loaded into $25, it must be loaded
11647 into some other GPR. No other register class allows a direct move. */
11648 if (mips_dangerous_for_la25_p (x))
11649 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
11651 regno = true_regnum (x);
11654 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11655 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
11661 /* Copying from accumulator registers to anywhere other than a general
11662 register requires a temporary general register. */
11663 if (reg_class_subset_p (rclass, ACC_REGS))
11664 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11665 if (ACC_REG_P (regno))
11666 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11668 /* We can only copy a value to a condition code register from a
11669 floating-point register, and even then we require a scratch
11670 floating-point register. We can only copy a value out of a
11671 condition-code register into a general register. */
11672 if (reg_class_subset_p (rclass, ST_REGS))
11676 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
11678 if (ST_REG_P (regno))
11682 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11685 if (reg_class_subset_p (rclass, FP_REGS))
11688 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
11689 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11690 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11693 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
11694 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11697 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
11698 /* We can force the constant to memory and use lwc1
11699 and ldc1. As above, we will use pairs of lwc1s if
11700 ldc1 is not supported. */
11703 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
11704 /* In this case we can use mov.fmt. */
11707 /* Otherwise, we need to reload through an integer register. */
11710 if (FP_REG_P (regno))
11711 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
11716 /* Implement TARGET_MODE_REP_EXTENDED. */
11719 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
11721 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11722 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
11723 return SIGN_EXTEND;
11728 /* Implement TARGET_VALID_POINTER_MODE. */
11731 mips_valid_pointer_mode (enum machine_mode mode)
11733 return mode == SImode || (TARGET_64BIT && mode == DImode);
11736 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11739 mips_vector_mode_supported_p (enum machine_mode mode)
11744 return TARGET_PAIRED_SINGLE_FLOAT;
11759 return TARGET_LOONGSON_VECTORS;
11766 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11769 mips_scalar_mode_supported_p (enum machine_mode mode)
11771 if (ALL_FIXED_POINT_MODE_P (mode)
11772 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
11775 return default_scalar_mode_supported_p (mode);
11778 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11780 static enum machine_mode
11781 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
11783 if (TARGET_PAIRED_SINGLE_FLOAT
11789 /* Implement TARGET_INIT_LIBFUNCS. */
11792 mips_init_libfuncs (void)
11794 if (TARGET_FIX_VR4120)
11796 /* Register the special divsi3 and modsi3 functions needed to work
11797 around VR4120 division errata. */
11798 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
11799 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
11802 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
11804 /* Register the MIPS16 -mhard-float stubs. */
11805 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
11806 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
11807 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
11808 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
11810 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
11811 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
11812 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
11813 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
11814 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
11815 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
11816 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
11818 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
11819 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
11820 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
11822 if (TARGET_DOUBLE_FLOAT)
11824 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
11825 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
11826 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
11827 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
11829 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
11830 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
11831 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
11832 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
11833 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
11834 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
11835 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
11837 set_conv_libfunc (sext_optab, DFmode, SFmode,
11838 "__mips16_extendsfdf2");
11839 set_conv_libfunc (trunc_optab, SFmode, DFmode,
11840 "__mips16_truncdfsf2");
11841 set_conv_libfunc (sfix_optab, SImode, DFmode,
11842 "__mips16_fix_truncdfsi");
11843 set_conv_libfunc (sfloat_optab, DFmode, SImode,
11844 "__mips16_floatsidf");
11845 set_conv_libfunc (ufloat_optab, DFmode, SImode,
11846 "__mips16_floatunsidf");
11850 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11851 on an external non-MIPS16 routine to implement __sync_synchronize.
11852 Similarly for the rest of the ll/sc libfuncs. */
11855 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
11856 init_sync_libfuncs (UNITS_PER_WORD);
11860 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11863 mips_process_load_label (rtx target)
11865 rtx base, gp, intop;
11866 HOST_WIDE_INT offset;
11868 mips_multi_start ();
11872 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
11873 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
11877 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
11878 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
11882 gp = pic_offset_table_rtx;
11883 if (mips_cfun_has_cprestore_slot_p ())
11885 gp = gen_rtx_REG (Pmode, AT_REGNUM);
11886 mips_get_cprestore_base_and_offset (&base, &offset, true);
11887 if (!SMALL_OPERAND (offset))
11889 intop = GEN_INT (CONST_HIGH_PART (offset));
11890 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
11891 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
11894 offset = CONST_LOW_PART (offset);
11896 intop = GEN_INT (offset);
11897 if (ISA_HAS_LOAD_DELAY)
11898 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
11900 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
11902 if (ISA_HAS_LOAD_DELAY)
11903 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
11905 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
11906 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
11911 /* Return the number of instructions needed to load a label into $AT. */
11913 static unsigned int
11914 mips_load_label_num_insns (void)
11916 if (cfun->machine->load_label_num_insns == 0)
11918 mips_process_load_label (pc_rtx);
11919 cfun->machine->load_label_num_insns = mips_multi_num_insns;
11921 return cfun->machine->load_label_num_insns;
11924 /* Emit an asm sequence to start a noat block and load the address
11925 of a label into $1. */
11928 mips_output_load_label (rtx target)
11930 mips_push_asm_switch (&mips_noat);
11931 if (TARGET_EXPLICIT_RELOCS)
11933 mips_process_load_label (target);
11934 mips_multi_write ();
11938 if (Pmode == DImode)
11939 output_asm_insn ("dla\t%@,%0", &target);
11941 output_asm_insn ("la\t%@,%0", &target);
11945 /* Return the length of INSN. LENGTH is the initial length computed by
11946 attributes in the machine-description file. */
11949 mips_adjust_insn_length (rtx insn, int length)
11951 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11952 of a PIC long-branch sequence. Substitute the correct value. */
11953 if (length == MAX_PIC_BRANCH_LENGTH
11954 && INSN_CODE (insn) >= 0
11955 && get_attr_type (insn) == TYPE_BRANCH)
11957 /* Add the branch-over instruction and its delay slot, if this
11958 is a conditional branch. */
11959 length = simplejump_p (insn) ? 0 : 8;
11961 /* Load the label into $AT and jump to it. Ignore the delay
11962 slot of the jump. */
11963 length += 4 * mips_load_label_num_insns() + 4;
11966 /* A unconditional jump has an unfilled delay slot if it is not part
11967 of a sequence. A conditional jump normally has a delay slot, but
11968 does not on MIPS16. */
11969 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
11972 /* See how many nops might be needed to avoid hardware hazards. */
11973 if (!cfun->machine->ignore_hazard_length_p && INSN_CODE (insn) >= 0)
11974 switch (get_attr_hazard (insn))
11988 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11989 the .md file length attributes are 4-based for both modes.
11990 Adjust the MIPS16 ones here. */
11997 /* Return the assembly code for INSN, which has the operands given by
11998 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11999 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12000 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12001 version of BRANCH_IF_TRUE. */
12004 mips_output_conditional_branch (rtx insn, rtx *operands,
12005 const char *branch_if_true,
12006 const char *branch_if_false)
12008 unsigned int length;
12009 rtx taken, not_taken;
12011 gcc_assert (LABEL_P (operands[0]));
12013 length = get_attr_length (insn);
12016 /* Just a simple conditional branch. */
12017 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
12018 return branch_if_true;
12021 /* Generate a reversed branch around a direct jump. This fallback does
12022 not use branch-likely instructions. */
12023 mips_branch_likely = false;
12024 not_taken = gen_label_rtx ();
12025 taken = operands[0];
12027 /* Generate the reversed branch to NOT_TAKEN. */
12028 operands[0] = not_taken;
12029 output_asm_insn (branch_if_false, operands);
12031 /* If INSN has a delay slot, we must provide delay slots for both the
12032 branch to NOT_TAKEN and the conditional jump. We must also ensure
12033 that INSN's delay slot is executed in the appropriate cases. */
12034 if (final_sequence)
12036 /* This first delay slot will always be executed, so use INSN's
12037 delay slot if is not annulled. */
12038 if (!INSN_ANNULLED_BRANCH_P (insn))
12040 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12041 asm_out_file, optimize, 1, NULL);
12042 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12045 output_asm_insn ("nop", 0);
12046 fprintf (asm_out_file, "\n");
12049 /* Output the unconditional branch to TAKEN. */
12050 if (TARGET_ABSOLUTE_JUMPS)
12051 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
12054 mips_output_load_label (taken);
12055 output_asm_insn ("jr\t%@%]%/", 0);
12058 /* Now deal with its delay slot; see above. */
12059 if (final_sequence)
12061 /* This delay slot will only be executed if the branch is taken.
12062 Use INSN's delay slot if is annulled. */
12063 if (INSN_ANNULLED_BRANCH_P (insn))
12065 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12066 asm_out_file, optimize, 1, NULL);
12067 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12070 output_asm_insn ("nop", 0);
12071 fprintf (asm_out_file, "\n");
12074 /* Output NOT_TAKEN. */
12075 targetm.asm_out.internal_label (asm_out_file, "L",
12076 CODE_LABEL_NUMBER (not_taken));
12080 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12081 if some ordering condition is true. The condition is given by
12082 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12083 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12084 its second is always zero. */
12087 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
12089 const char *branch[2];
12091 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12092 Make BRANCH[0] branch on the inverse condition. */
12093 switch (GET_CODE (operands[1]))
12095 /* These cases are equivalent to comparisons against zero. */
12097 inverted_p = !inverted_p;
12098 /* Fall through. */
12100 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
12101 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
12104 /* These cases are always true or always false. */
12106 inverted_p = !inverted_p;
12107 /* Fall through. */
12109 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
12110 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
12114 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
12115 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
12118 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
12121 /* Start a block of code that needs access to the LL, SC and SYNC
12125 mips_start_ll_sc_sync_block (void)
12127 if (!ISA_HAS_LL_SC)
12129 output_asm_insn (".set\tpush", 0);
12130 output_asm_insn (".set\tmips2", 0);
12134 /* End a block started by mips_start_ll_sc_sync_block. */
12137 mips_end_ll_sc_sync_block (void)
12139 if (!ISA_HAS_LL_SC)
12140 output_asm_insn (".set\tpop", 0);
12143 /* Output and/or return the asm template for a sync instruction. */
12146 mips_output_sync (void)
12148 mips_start_ll_sc_sync_block ();
12149 output_asm_insn ("sync", 0);
12150 mips_end_ll_sc_sync_block ();
12154 /* Return the asm template associated with sync_insn1 value TYPE.
12155 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12157 static const char *
12158 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
12162 case SYNC_INSN1_MOVE:
12163 return "move\t%0,%z2";
12164 case SYNC_INSN1_LI:
12165 return "li\t%0,%2";
12166 case SYNC_INSN1_ADDU:
12167 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12168 case SYNC_INSN1_ADDIU:
12169 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12170 case SYNC_INSN1_SUBU:
12171 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12172 case SYNC_INSN1_AND:
12173 return "and\t%0,%1,%z2";
12174 case SYNC_INSN1_ANDI:
12175 return "andi\t%0,%1,%2";
12176 case SYNC_INSN1_OR:
12177 return "or\t%0,%1,%z2";
12178 case SYNC_INSN1_ORI:
12179 return "ori\t%0,%1,%2";
12180 case SYNC_INSN1_XOR:
12181 return "xor\t%0,%1,%z2";
12182 case SYNC_INSN1_XORI:
12183 return "xori\t%0,%1,%2";
12185 gcc_unreachable ();
12188 /* Return the asm template associated with sync_insn2 value TYPE. */
12190 static const char *
12191 mips_sync_insn2_template (enum attr_sync_insn2 type)
12195 case SYNC_INSN2_NOP:
12196 gcc_unreachable ();
12197 case SYNC_INSN2_AND:
12198 return "and\t%0,%1,%z2";
12199 case SYNC_INSN2_XOR:
12200 return "xor\t%0,%1,%z2";
12201 case SYNC_INSN2_NOT:
12202 return "nor\t%0,%1,%.";
12204 gcc_unreachable ();
12207 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12208 the value of the one of the sync_* attributes. Return the operand
12209 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12210 have the associated attribute. */
12213 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
12216 default_value = operands[index - 1];
12217 return default_value;
12220 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12221 sequence for it. */
12224 mips_process_sync_loop (rtx insn, rtx *operands)
12226 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12227 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
12228 unsigned int tmp3_insn;
12229 enum attr_sync_insn1 insn1;
12230 enum attr_sync_insn2 insn2;
12233 enum memmodel model;
12235 /* Read an operand from the sync_WHAT attribute and store it in
12236 variable WHAT. DEFAULT is the default value if no attribute
12238 #define READ_OPERAND(WHAT, DEFAULT) \
12239 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12242 /* Read the memory. */
12243 READ_OPERAND (mem, 0);
12245 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12247 /* Read the other attributes. */
12248 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12249 READ_OPERAND (oldval, at);
12250 READ_OPERAND (cmp, 0);
12251 READ_OPERAND (newval, at);
12252 READ_OPERAND (inclusive_mask, 0);
12253 READ_OPERAND (exclusive_mask, 0);
12254 READ_OPERAND (required_oldval, 0);
12255 READ_OPERAND (insn1_op2, 0);
12256 insn1 = get_attr_sync_insn1 (insn);
12257 insn2 = get_attr_sync_insn2 (insn);
12259 /* Don't bother setting CMP result that is never used. */
12260 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
12263 memmodel_attr = get_attr_sync_memmodel (insn);
12264 switch (memmodel_attr)
12267 model = MEMMODEL_ACQ_REL;
12270 model = MEMMODEL_ACQUIRE;
12273 model = (enum memmodel) INTVAL (operands[memmodel_attr]);
12276 mips_multi_start ();
12278 /* Output the release side of the memory barrier. */
12279 if (need_atomic_barrier_p (model, true))
12281 if (required_oldval == 0 && TARGET_OCTEON)
12283 /* Octeon doesn't reorder reads, so a full barrier can be
12284 created by using SYNCW to order writes combined with the
12285 write from the following SC. When the SC successfully
12286 completes, we know that all preceding writes are also
12287 committed to the coherent memory system. It is possible
12288 for a single SYNCW to fail, but a pair of them will never
12289 fail, so we use two. */
12290 mips_multi_add_insn ("syncw", NULL);
12291 mips_multi_add_insn ("syncw", NULL);
12294 mips_multi_add_insn ("sync", NULL);
12297 /* Output the branch-back label. */
12298 mips_multi_add_label ("1:");
12300 /* OLDVAL = *MEM. */
12301 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12302 oldval, mem, NULL);
12304 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12305 if (required_oldval)
12307 if (inclusive_mask == 0)
12311 gcc_assert (oldval != at);
12312 mips_multi_add_insn ("and\t%0,%1,%2",
12313 at, oldval, inclusive_mask, NULL);
12316 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12318 /* CMP = 0 [delay slot]. */
12320 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
12323 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12324 if (exclusive_mask == 0)
12328 gcc_assert (oldval != at);
12329 mips_multi_add_insn ("and\t%0,%1,%z2",
12330 at, oldval, exclusive_mask, NULL);
12334 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12336 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12337 at least one instruction in that case. */
12338 if (insn1 == SYNC_INSN1_MOVE
12339 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12343 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12344 newval, oldval, insn1_op2, NULL);
12348 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12349 if (insn2 == SYNC_INSN2_NOP)
12353 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12354 newval, tmp2, inclusive_mask, NULL);
12357 tmp3_insn = mips_multi_last_index ();
12359 /* $AT = $TMP1 | $TMP3. */
12360 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12362 mips_multi_set_operand (tmp3_insn, 0, at);
12367 gcc_assert (tmp1 != tmp3);
12368 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12371 /* if (!commit (*MEM = $AT)) goto 1.
12373 This will sometimes be a delayed branch; see the write code below
12375 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12376 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12378 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12379 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12381 mips_multi_copy_insn (tmp3_insn);
12382 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12384 else if (!(required_oldval && cmp))
12385 mips_multi_add_insn ("nop", NULL);
12387 /* CMP = 1 -- either standalone or in a delay slot. */
12388 if (required_oldval && cmp)
12389 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
12391 /* Output the acquire side of the memory barrier. */
12392 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
12393 mips_multi_add_insn ("sync", NULL);
12395 /* Output the exit label, if needed. */
12396 if (required_oldval)
12397 mips_multi_add_label ("2:");
12399 #undef READ_OPERAND
12402 /* Output and/or return the asm template for sync loop INSN, which has
12403 the operands given by OPERANDS. */
12406 mips_output_sync_loop (rtx insn, rtx *operands)
12408 mips_process_sync_loop (insn, operands);
12410 /* Use branch-likely instructions to work around the LL/SC R10000
12412 mips_branch_likely = TARGET_FIX_R10000;
12414 mips_push_asm_switch (&mips_noreorder);
12415 mips_push_asm_switch (&mips_nomacro);
12416 mips_push_asm_switch (&mips_noat);
12417 mips_start_ll_sc_sync_block ();
12419 mips_multi_write ();
12421 mips_end_ll_sc_sync_block ();
12422 mips_pop_asm_switch (&mips_noat);
12423 mips_pop_asm_switch (&mips_nomacro);
12424 mips_pop_asm_switch (&mips_noreorder);
12429 /* Return the number of individual instructions in sync loop INSN,
12430 which has the operands given by OPERANDS. */
12433 mips_sync_loop_insns (rtx insn, rtx *operands)
12435 mips_process_sync_loop (insn, operands);
12436 return mips_multi_num_insns;
12439 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12440 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12442 When working around R4000 and R4400 errata, we need to make sure that
12443 the division is not immediately followed by a shift[1][2]. We also
12444 need to stop the division from being put into a branch delay slot[3].
12445 The easiest way to avoid both problems is to add a nop after the
12446 division. When a divide-by-zero check is needed, this nop can be
12447 used to fill the branch delay slot.
12449 [1] If a double-word or a variable shift executes immediately
12450 after starting an integer division, the shift may give an
12451 incorrect result. See quotations of errata #16 and #28 from
12452 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12453 in mips.md for details.
12455 [2] A similar bug to [1] exists for all revisions of the
12456 R4000 and the R4400 when run in an MC configuration.
12457 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12459 "19. In this following sequence:
12461 ddiv (or ddivu or div or divu)
12462 dsll32 (or dsrl32, dsra32)
12464 if an MPT stall occurs, while the divide is slipping the cpu
12465 pipeline, then the following double shift would end up with an
12468 Workaround: The compiler needs to avoid generating any
12469 sequence with divide followed by extended double shift."
12471 This erratum is also present in "MIPS R4400MC Errata, Processor
12472 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12473 & 3.0" as errata #10 and #4, respectively.
12475 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12476 (also valid for MIPS R4000MC processors):
12478 "52. R4000SC: This bug does not apply for the R4000PC.
12480 There are two flavors of this bug:
12482 1) If the instruction just after divide takes an RF exception
12483 (tlb-refill, tlb-invalid) and gets an instruction cache
12484 miss (both primary and secondary) and the line which is
12485 currently in secondary cache at this index had the first
12486 data word, where the bits 5..2 are set, then R4000 would
12487 get a wrong result for the div.
12492 ------------------- # end-of page. -tlb-refill
12497 ------------------- # end-of page. -tlb-invalid
12500 2) If the divide is in the taken branch delay slot, where the
12501 target takes RF exception and gets an I-cache miss for the
12502 exception vector or where I-cache miss occurs for the
12503 target address, under the above mentioned scenarios, the
12504 div would get wrong results.
12507 j r2 # to next page mapped or unmapped
12508 div r8,r9 # this bug would be there as long
12509 # as there is an ICache miss and
12510 nop # the "data pattern" is present
12513 beq r0, r0, NextPage # to Next page
12517 This bug is present for div, divu, ddiv, and ddivu
12520 Workaround: For item 1), OS could make sure that the next page
12521 after the divide instruction is also mapped. For item 2), the
12522 compiler could make sure that the divide instruction is not in
12523 the branch delay slot."
12525 These processors have PRId values of 0x00004220 and 0x00004300 for
12526 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12529 mips_output_division (const char *division, rtx *operands)
12534 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
12536 output_asm_insn (s, operands);
12539 if (TARGET_CHECK_ZERO_DIV)
12543 output_asm_insn (s, operands);
12544 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
12546 else if (GENERATE_DIVIDE_TRAPS)
12548 /* Avoid long replay penalty on load miss by putting the trap before
12551 output_asm_insn ("teq\t%2,%.,7", operands);
12554 output_asm_insn (s, operands);
12555 s = "teq\t%2,%.,7";
12560 output_asm_insn ("%(bne\t%2,%.,1f", operands);
12561 output_asm_insn (s, operands);
12562 s = "break\t7%)\n1:";
12568 /* Return true if IN_INSN is a multiply-add or multiply-subtract
12569 instruction and if OUT_INSN assigns to the accumulator operand. */
12572 mips_linked_madd_p (rtx out_insn, rtx in_insn)
12574 enum attr_accum_in accum_in;
12575 int accum_in_opnum;
12578 if (recog_memoized (in_insn) < 0)
12581 accum_in = get_attr_accum_in (in_insn);
12582 if (accum_in == ACCUM_IN_NONE)
12585 accum_in_opnum = accum_in - ACCUM_IN_0;
12587 extract_insn (in_insn);
12588 gcc_assert (accum_in_opnum < recog_data.n_operands);
12589 accum_in_op = recog_data.operand[accum_in_opnum];
12591 return reg_set_p (accum_in_op, out_insn);
12594 /* True if the dependency between OUT_INSN and IN_INSN is on the store
12595 data rather than the address. We need this because the cprestore
12596 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
12597 which causes the default routine to abort. We just return false
12601 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
12603 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
12606 return !store_data_bypass_p (out_insn, in_insn);
12610 /* Variables and flags used in scheduler hooks when tuning for
12614 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
12617 /* If true, then next ALU1/2 instruction will go to ALU1. */
12620 /* If true, then next FALU1/2 unstruction will go to FALU1. */
12623 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
12624 int alu1_core_unit_code;
12625 int alu2_core_unit_code;
12626 int falu1_core_unit_code;
12627 int falu2_core_unit_code;
12629 /* True if current cycle has a multi instruction.
12630 This flag is used in mips_ls2_dfa_post_advance_cycle. */
12631 bool cycle_has_multi_p;
12633 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
12634 These are used in mips_ls2_dfa_post_advance_cycle to initialize
12636 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
12637 instruction to go ALU1. */
12638 rtx alu1_turn_enabled_insn;
12639 rtx alu2_turn_enabled_insn;
12640 rtx falu1_turn_enabled_insn;
12641 rtx falu2_turn_enabled_insn;
12644 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
12645 dependencies have no cost, except on the 20Kc where output-dependence
12646 is treated like input-dependence. */
12649 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
12650 rtx dep ATTRIBUTE_UNUSED, int cost)
12652 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
12655 if (REG_NOTE_KIND (link) != 0)
12660 /* Return the number of instructions that can be issued per cycle. */
12663 mips_issue_rate (void)
12667 case PROCESSOR_74KC:
12668 case PROCESSOR_74KF2_1:
12669 case PROCESSOR_74KF1_1:
12670 case PROCESSOR_74KF3_2:
12671 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12672 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12673 but in reality only a maximum of 3 insns can be issued as
12674 floating-point loads and stores also require a slot in the
12676 case PROCESSOR_R10000:
12677 /* All R10K Processors are quad-issue (being the first MIPS
12678 processors to support this feature). */
12681 case PROCESSOR_20KC:
12682 case PROCESSOR_R4130:
12683 case PROCESSOR_R5400:
12684 case PROCESSOR_R5500:
12685 case PROCESSOR_R7000:
12686 case PROCESSOR_R9000:
12687 case PROCESSOR_OCTEON:
12688 case PROCESSOR_OCTEON2:
12691 case PROCESSOR_SB1:
12692 case PROCESSOR_SB1A:
12693 /* This is actually 4, but we get better performance if we claim 3.
12694 This is partly because of unwanted speculative code motion with the
12695 larger number, and partly because in most common cases we can't
12696 reach the theoretical max of 4. */
12699 case PROCESSOR_LOONGSON_2E:
12700 case PROCESSOR_LOONGSON_2F:
12701 case PROCESSOR_LOONGSON_3A:
12704 case PROCESSOR_XLP:
12705 return (reload_completed ? 4 : 3);
12712 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12715 mips_ls2_init_dfa_post_cycle_insn (void)
12718 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12719 mips_ls2.alu1_turn_enabled_insn = get_insns ();
12723 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12724 mips_ls2.alu2_turn_enabled_insn = get_insns ();
12728 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12729 mips_ls2.falu1_turn_enabled_insn = get_insns ();
12733 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12734 mips_ls2.falu2_turn_enabled_insn = get_insns ();
12737 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
12738 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
12739 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
12740 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
12743 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12744 Init data used in mips_dfa_post_advance_cycle. */
12747 mips_init_dfa_post_cycle_insn (void)
12749 if (TUNE_LOONGSON_2EF)
12750 mips_ls2_init_dfa_post_cycle_insn ();
12753 /* Initialize STATE when scheduling for Loongson 2E/2F.
12754 Support round-robin dispatch scheme by enabling only one of
12755 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12759 mips_ls2_dfa_post_advance_cycle (state_t state)
12761 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
12763 /* Though there are no non-pipelined ALU1 insns,
12764 we can get an instruction of type 'multi' before reload. */
12765 gcc_assert (mips_ls2.cycle_has_multi_p);
12766 mips_ls2.alu1_turn_p = false;
12769 mips_ls2.cycle_has_multi_p = false;
12771 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
12772 /* We have a non-pipelined alu instruction in the core,
12773 adjust round-robin counter. */
12774 mips_ls2.alu1_turn_p = true;
12776 if (mips_ls2.alu1_turn_p)
12778 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
12779 gcc_unreachable ();
12783 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
12784 gcc_unreachable ();
12787 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
12789 /* There are no non-pipelined FALU1 insns. */
12790 gcc_unreachable ();
12791 mips_ls2.falu1_turn_p = false;
12794 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
12795 /* We have a non-pipelined falu instruction in the core,
12796 adjust round-robin counter. */
12797 mips_ls2.falu1_turn_p = true;
12799 if (mips_ls2.falu1_turn_p)
12801 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
12802 gcc_unreachable ();
12806 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
12807 gcc_unreachable ();
12811 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12812 This hook is being called at the start of each cycle. */
12815 mips_dfa_post_advance_cycle (void)
12817 if (TUNE_LOONGSON_2EF)
12818 mips_ls2_dfa_post_advance_cycle (curr_state);
12821 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12822 be as wide as the scheduling freedom in the DFA. */
12825 mips_multipass_dfa_lookahead (void)
12827 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12831 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
12840 /* Remove the instruction at index LOWER from ready queue READY and
12841 reinsert it in front of the instruction at index HIGHER. LOWER must
12845 mips_promote_ready (rtx *ready, int lower, int higher)
12850 new_head = ready[lower];
12851 for (i = lower; i < higher; i++)
12852 ready[i] = ready[i + 1];
12853 ready[i] = new_head;
12856 /* If the priority of the instruction at POS2 in the ready queue READY
12857 is within LIMIT units of that of the instruction at POS1, swap the
12858 instructions if POS2 is not already less than POS1. */
12861 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
12864 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
12868 temp = ready[pos1];
12869 ready[pos1] = ready[pos2];
12870 ready[pos2] = temp;
12874 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12875 that may clobber hi or lo. */
12876 static rtx mips_macc_chains_last_hilo;
12878 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12879 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12882 mips_macc_chains_record (rtx insn)
12884 if (get_attr_may_clobber_hilo (insn))
12885 mips_macc_chains_last_hilo = insn;
12888 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12889 has NREADY elements, looking for a multiply-add or multiply-subtract
12890 instruction that is cumulative with mips_macc_chains_last_hilo.
12891 If there is one, promote it ahead of anything else that might
12892 clobber hi or lo. */
12895 mips_macc_chains_reorder (rtx *ready, int nready)
12899 if (mips_macc_chains_last_hilo != 0)
12900 for (i = nready - 1; i >= 0; i--)
12901 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
12903 for (j = nready - 1; j > i; j--)
12904 if (recog_memoized (ready[j]) >= 0
12905 && get_attr_may_clobber_hilo (ready[j]))
12907 mips_promote_ready (ready, i, j);
12914 /* The last instruction to be scheduled. */
12915 static rtx vr4130_last_insn;
12917 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12918 points to an rtx that is initially an instruction. Nullify the rtx
12919 if the instruction uses the value of register X. */
12922 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
12927 insn_ptr = (rtx *) data;
12930 && reg_referenced_p (x, PATTERN (*insn_ptr)))
12934 /* Return true if there is true register dependence between vr4130_last_insn
12938 vr4130_true_reg_dependence_p (rtx insn)
12940 note_stores (PATTERN (vr4130_last_insn),
12941 vr4130_true_reg_dependence_p_1, &insn);
12945 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12946 the ready queue and that INSN2 is the instruction after it, return
12947 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12948 in which INSN1 and INSN2 can probably issue in parallel, but for
12949 which (INSN2, INSN1) should be less sensitive to instruction
12950 alignment than (INSN1, INSN2). See 4130.md for more details. */
12953 vr4130_swap_insns_p (rtx insn1, rtx insn2)
12955 sd_iterator_def sd_it;
12958 /* Check for the following case:
12960 1) there is some other instruction X with an anti dependence on INSN1;
12961 2) X has a higher priority than INSN2; and
12962 3) X is an arithmetic instruction (and thus has no unit restrictions).
12964 If INSN1 is the last instruction blocking X, it would better to
12965 choose (INSN1, X) over (INSN2, INSN1). */
12966 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
12967 if (DEP_TYPE (dep) == REG_DEP_ANTI
12968 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
12969 && recog_memoized (DEP_CON (dep)) >= 0
12970 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
12973 if (vr4130_last_insn != 0
12974 && recog_memoized (insn1) >= 0
12975 && recog_memoized (insn2) >= 0)
12977 /* See whether INSN1 and INSN2 use different execution units,
12978 or if they are both ALU-type instructions. If so, they can
12979 probably execute in parallel. */
12980 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
12981 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
12982 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
12984 /* If only one of the instructions has a dependence on
12985 vr4130_last_insn, prefer to schedule the other one first. */
12986 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
12987 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
12988 if (dep1_p != dep2_p)
12991 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12992 is not an ALU-type instruction and if INSN1 uses the same
12993 execution unit. (Note that if this condition holds, we already
12994 know that INSN2 uses a different execution unit.) */
12995 if (class1 != VR4130_CLASS_ALU
12996 && recog_memoized (vr4130_last_insn) >= 0
12997 && class1 == get_attr_vr4130_class (vr4130_last_insn))
13004 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13005 queue with at least two instructions. Swap the first two if
13006 vr4130_swap_insns_p says that it could be worthwhile. */
13009 vr4130_reorder (rtx *ready, int nready)
13011 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
13012 mips_promote_ready (ready, nready - 2, nready - 1);
13015 /* Record whether last 74k AGEN instruction was a load or store. */
13016 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
13018 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13019 resets to TYPE_UNKNOWN state. */
13022 mips_74k_agen_init (rtx insn)
13024 if (!insn || CALL_P (insn) || JUMP_P (insn))
13025 mips_last_74k_agen_insn = TYPE_UNKNOWN;
13028 enum attr_type type = get_attr_type (insn);
13029 if (type == TYPE_LOAD || type == TYPE_STORE)
13030 mips_last_74k_agen_insn = type;
13034 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13035 loads to be grouped together, and multiple stores to be grouped
13036 together. Swap things around in the ready queue to make this happen. */
13039 mips_74k_agen_reorder (rtx *ready, int nready)
13042 int store_pos, load_pos;
13047 for (i = nready - 1; i >= 0; i--)
13049 rtx insn = ready[i];
13050 if (USEFUL_INSN_P (insn))
13051 switch (get_attr_type (insn))
13054 if (store_pos == -1)
13059 if (load_pos == -1)
13068 if (load_pos == -1 || store_pos == -1)
13071 switch (mips_last_74k_agen_insn)
13074 /* Prefer to schedule loads since they have a higher latency. */
13076 /* Swap loads to the front of the queue. */
13077 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
13080 /* Swap stores to the front of the queue. */
13081 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
13088 /* Implement TARGET_SCHED_INIT. */
13091 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13092 int max_ready ATTRIBUTE_UNUSED)
13094 mips_macc_chains_last_hilo = 0;
13095 vr4130_last_insn = 0;
13096 mips_74k_agen_init (NULL_RTX);
13098 /* When scheduling for Loongson2, branch instructions go to ALU1,
13099 therefore basic block is most likely to start with round-robin counter
13100 pointed to ALU2. */
13101 mips_ls2.alu1_turn_p = false;
13102 mips_ls2.falu1_turn_p = true;
13105 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13108 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13109 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13111 if (!reload_completed
13112 && TUNE_MACC_CHAINS
13114 mips_macc_chains_reorder (ready, *nreadyp);
13116 if (reload_completed
13118 && !TARGET_VR4130_ALIGN
13120 vr4130_reorder (ready, *nreadyp);
13123 mips_74k_agen_reorder (ready, *nreadyp);
13126 /* Implement TARGET_SCHED_REORDER. */
13129 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13130 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13132 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13133 return mips_issue_rate ();
13136 /* Implement TARGET_SCHED_REORDER2. */
13139 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13140 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13142 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13143 return cached_can_issue_more;
13146 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13149 mips_ls2_variable_issue (rtx insn)
13151 if (mips_ls2.alu1_turn_p)
13153 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
13154 mips_ls2.alu1_turn_p = false;
13158 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
13159 mips_ls2.alu1_turn_p = true;
13162 if (mips_ls2.falu1_turn_p)
13164 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
13165 mips_ls2.falu1_turn_p = false;
13169 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
13170 mips_ls2.falu1_turn_p = true;
13173 if (recog_memoized (insn) >= 0)
13174 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
13177 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13180 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13181 rtx insn, int more)
13183 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13184 if (USEFUL_INSN_P (insn))
13186 if (get_attr_type (insn) != TYPE_GHOST)
13188 if (!reload_completed && TUNE_MACC_CHAINS)
13189 mips_macc_chains_record (insn);
13190 vr4130_last_insn = insn;
13192 mips_74k_agen_init (insn);
13193 else if (TUNE_LOONGSON_2EF)
13194 mips_ls2_variable_issue (insn);
13197 /* Instructions of type 'multi' should all be split before
13198 the second scheduling pass. */
13199 gcc_assert (!reload_completed
13200 || recog_memoized (insn) < 0
13201 || get_attr_type (insn) != TYPE_MULTI);
13203 cached_can_issue_more = more;
13207 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13208 return the first operand of the associated PREF or PREFX insn. */
13211 mips_prefetch_cookie (rtx write, rtx locality)
13213 /* store_streamed / load_streamed. */
13214 if (INTVAL (locality) <= 0)
13215 return GEN_INT (INTVAL (write) + 4);
13217 /* store / load. */
13218 if (INTVAL (locality) <= 2)
13221 /* store_retained / load_retained. */
13222 return GEN_INT (INTVAL (write) + 6);
13225 /* Flags that indicate when a built-in function is available.
13227 BUILTIN_AVAIL_NON_MIPS16
13228 The function is available on the current target, but only
13229 in non-MIPS16 mode. */
13230 #define BUILTIN_AVAIL_NON_MIPS16 1
13232 /* Declare an availability predicate for built-in functions that
13233 require non-MIPS16 mode and also require COND to be true.
13234 NAME is the main part of the predicate's name. */
13235 #define AVAIL_NON_MIPS16(NAME, COND) \
13236 static unsigned int \
13237 mips_builtin_avail_##NAME (void) \
13239 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13242 /* This structure describes a single built-in function. */
13243 struct mips_builtin_description {
13244 /* The code of the main .md file instruction. See mips_builtin_type
13245 for more information. */
13246 enum insn_code icode;
13248 /* The floating-point comparison code to use with ICODE, if any. */
13249 enum mips_fp_condition cond;
13251 /* The name of the built-in function. */
13254 /* Specifies how the function should be expanded. */
13255 enum mips_builtin_type builtin_type;
13257 /* The function's prototype. */
13258 enum mips_function_type function_type;
13260 /* Whether the function is available. */
13261 unsigned int (*avail) (void);
13264 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13265 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13266 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13267 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13268 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13269 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13270 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13271 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13272 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13273 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13275 /* Construct a mips_builtin_description from the given arguments.
13277 INSN is the name of the associated instruction pattern, without the
13278 leading CODE_FOR_mips_.
13280 CODE is the floating-point condition code associated with the
13281 function. It can be 'f' if the field is not applicable.
13283 NAME is the name of the function itself, without the leading
13286 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13288 AVAIL is the name of the availability predicate, without the leading
13289 mips_builtin_avail_. */
13290 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13291 FUNCTION_TYPE, AVAIL) \
13292 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13293 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13294 mips_builtin_avail_ ## AVAIL }
13296 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13297 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13298 are as for MIPS_BUILTIN. */
13299 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13300 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13302 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13303 are subject to mips_builtin_avail_<AVAIL>. */
13304 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13305 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13306 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13307 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13308 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13310 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13311 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13312 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13313 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13314 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13315 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13317 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13318 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13320 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13321 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13323 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13324 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13327 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13328 are subject to mips_builtin_avail_mips3d. */
13329 #define CMP_4S_BUILTINS(INSN, COND) \
13330 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13331 MIPS_BUILTIN_CMP_ANY, \
13332 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13333 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13334 MIPS_BUILTIN_CMP_ALL, \
13335 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13337 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13338 instruction requires mips_builtin_avail_<AVAIL>. */
13339 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13340 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13341 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13343 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13344 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13347 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13348 #define CMP_BUILTINS(COND) \
13349 MOVTF_BUILTINS (c, COND, paired_single), \
13350 MOVTF_BUILTINS (cabs, COND, mips3d), \
13351 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13352 CMP_PS_BUILTINS (c, COND, paired_single), \
13353 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13354 CMP_4S_BUILTINS (c, COND), \
13355 CMP_4S_BUILTINS (cabs, COND)
13357 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13358 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13359 and AVAIL are as for MIPS_BUILTIN. */
13360 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13361 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13362 FUNCTION_TYPE, AVAIL)
13364 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13365 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13366 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13367 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13368 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13370 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13371 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13372 builtin_description field. */
13373 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13374 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13375 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13376 FUNCTION_TYPE, mips_builtin_avail_loongson }
13378 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13379 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13380 builtin_description field. */
13381 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13382 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13384 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13385 We use functions of this form when the same insn can be usefully applied
13386 to more than one datatype. */
13387 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13388 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13390 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13391 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13392 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13393 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13394 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13395 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13396 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13397 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13399 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13400 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13401 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13402 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13403 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13404 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13405 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13406 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13407 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13408 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13409 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13410 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13411 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13412 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13413 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13414 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13415 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13416 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13417 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13418 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13419 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13420 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13421 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13422 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13423 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13424 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13425 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13426 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13427 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13428 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13430 static const struct mips_builtin_description mips_builtins[] = {
13431 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13432 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13433 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13434 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13435 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13436 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13437 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13438 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13440 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13441 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13442 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13443 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13444 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13446 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13447 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13448 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13449 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13450 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13451 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13453 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13454 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13455 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13456 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13457 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13458 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13460 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13462 /* Built-in functions for the SB-1 processor. */
13463 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13465 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13466 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13467 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13468 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13469 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13470 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13471 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13472 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13473 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13474 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13475 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13476 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13477 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13478 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13479 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13480 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13481 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13482 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13483 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13484 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13485 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13486 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
13487 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
13488 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13489 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13490 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13491 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13492 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13493 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
13494 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
13495 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
13496 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13497 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13498 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13499 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13500 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
13501 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13502 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
13503 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
13504 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13505 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
13506 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13507 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13508 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
13509 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
13510 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
13511 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
13512 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
13513 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13514 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13515 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
13516 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13517 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13518 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
13519 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13520 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13521 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
13522 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13523 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13524 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13525 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
13526 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
13527 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
13528 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13529 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
13530 BPOSGE_BUILTIN (32, dsp),
13532 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
13533 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
13534 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13535 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13536 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13537 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13538 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13539 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13540 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13541 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13542 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
13543 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13544 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13545 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13546 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13547 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13548 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
13549 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13550 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
13551 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
13552 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13553 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
13554 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
13555 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13556 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13557 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13558 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
13559 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13560 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13561 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13562 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13563 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13564 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
13565 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13566 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
13568 /* Built-in functions for the DSP ASE (32-bit only). */
13569 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13570 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13571 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13572 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
13573 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13574 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13575 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13576 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13577 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13578 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13579 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13580 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13581 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
13582 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13583 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13584 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
13585 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
13586 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13587 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
13588 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
13589 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
13590 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13591 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13592 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
13593 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
13594 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
13595 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
13597 /* Built-in functions for the DSP ASE (64-bit only). */
13598 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
13600 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
13601 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13602 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13603 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13604 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13605 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13606 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13607 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13608 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13609 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
13611 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
13612 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
13613 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
13614 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
13615 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13616 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13617 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13618 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13619 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13620 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13621 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
13622 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
13623 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13624 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13625 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13626 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13627 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
13628 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13629 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13630 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13631 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
13632 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
13633 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13634 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13635 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13636 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13637 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13638 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13639 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13640 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13641 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13642 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13643 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13644 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13645 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13646 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13647 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13648 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13649 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
13650 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
13651 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13652 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13653 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13654 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13655 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13656 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13657 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13658 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13659 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
13660 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13661 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13662 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13663 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13664 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
13665 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
13666 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13667 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13668 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13669 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
13670 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13671 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
13672 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
13673 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13674 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13675 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13676 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13677 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13678 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13679 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13680 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13681 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13682 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13683 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
13684 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
13685 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
13686 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
13687 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13688 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13689 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13690 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13691 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13692 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13693 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
13694 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
13695 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
13696 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
13697 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13698 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13699 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13700 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13701 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13702 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13703 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13704 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13705 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
13706 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
13707 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
13708 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
13709 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
13710 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
13712 /* Sundry other built-in functions. */
13713 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
13716 /* Index I is the function declaration for mips_builtins[I], or null if the
13717 function isn't defined on this target. */
13718 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
13720 /* MODE is a vector mode whose elements have type TYPE. Return the type
13721 of the vector itself. */
13724 mips_builtin_vector_type (tree type, enum machine_mode mode)
13726 static tree types[2 * (int) MAX_MACHINE_MODE];
13729 mode_index = (int) mode;
13731 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
13732 mode_index += MAX_MACHINE_MODE;
13734 if (types[mode_index] == NULL_TREE)
13735 types[mode_index] = build_vector_type_for_mode (type, mode);
13736 return types[mode_index];
13739 /* Return a type for 'const volatile void *'. */
13742 mips_build_cvpointer_type (void)
13746 if (cache == NULL_TREE)
13747 cache = build_pointer_type (build_qualified_type
13749 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
13753 /* Source-level argument types. */
13754 #define MIPS_ATYPE_VOID void_type_node
13755 #define MIPS_ATYPE_INT integer_type_node
13756 #define MIPS_ATYPE_POINTER ptr_type_node
13757 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13759 /* Standard mode-based argument types. */
13760 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13761 #define MIPS_ATYPE_SI intSI_type_node
13762 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13763 #define MIPS_ATYPE_DI intDI_type_node
13764 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13765 #define MIPS_ATYPE_SF float_type_node
13766 #define MIPS_ATYPE_DF double_type_node
13768 /* Vector argument types. */
13769 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13770 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13771 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13772 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13773 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13774 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13775 #define MIPS_ATYPE_UV2SI \
13776 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13777 #define MIPS_ATYPE_UV4HI \
13778 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13779 #define MIPS_ATYPE_UV8QI \
13780 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13782 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13783 their associated MIPS_ATYPEs. */
13784 #define MIPS_FTYPE_ATYPES1(A, B) \
13785 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13787 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13788 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13790 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13791 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13793 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13794 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13797 /* Return the function type associated with function prototype TYPE. */
13800 mips_build_function_type (enum mips_function_type type)
13802 static tree types[(int) MIPS_MAX_FTYPE_MAX];
13804 if (types[(int) type] == NULL_TREE)
13807 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13808 case MIPS_FTYPE_NAME##NUM ARGS: \
13809 types[(int) type] \
13810 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13813 #include "config/mips/mips-ftypes.def"
13814 #undef DEF_MIPS_FTYPE
13816 gcc_unreachable ();
13819 return types[(int) type];
13822 /* Implement TARGET_INIT_BUILTINS. */
13825 mips_init_builtins (void)
13827 const struct mips_builtin_description *d;
13830 /* Iterate through all of the bdesc arrays, initializing all of the
13831 builtin functions. */
13832 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
13834 d = &mips_builtins[i];
13836 mips_builtin_decls[i]
13837 = add_builtin_function (d->name,
13838 mips_build_function_type (d->function_type),
13839 i, BUILT_IN_MD, NULL, NULL);
13843 /* Implement TARGET_BUILTIN_DECL. */
13846 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
13848 if (code >= ARRAY_SIZE (mips_builtins))
13849 return error_mark_node;
13850 return mips_builtin_decls[code];
13853 /* Take argument ARGNO from EXP's argument list and convert it into
13854 an expand operand. Store the operand in *OP. */
13857 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
13858 unsigned int argno)
13863 arg = CALL_EXPR_ARG (exp, argno);
13864 value = expand_normal (arg);
13865 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
13868 /* Expand instruction ICODE as part of a built-in function sequence.
13869 Use the first NOPS elements of OPS as the instruction's operands.
13870 HAS_TARGET_P is true if operand 0 is a target; it is false if the
13871 instruction has no target.
13873 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
13876 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
13877 struct expand_operand *ops, bool has_target_p)
13879 if (!maybe_expand_insn (icode, nops, ops))
13881 error ("invalid argument to built-in function");
13882 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
13884 return has_target_p ? ops[0].value : const0_rtx;
13887 /* Expand a floating-point comparison for built-in function call EXP.
13888 The first NARGS arguments are the values to be compared. ICODE is
13889 the .md pattern that does the comparison and COND is the condition
13890 that is being tested. Return an rtx for the result. */
13893 mips_expand_builtin_compare_1 (enum insn_code icode,
13894 enum mips_fp_condition cond,
13895 tree exp, int nargs)
13897 struct expand_operand ops[MAX_RECOG_OPERANDS];
13901 /* The instruction should have a target operand, an operand for each
13902 argument, and an operand for COND. */
13903 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
13905 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
13907 create_fixed_operand (&ops[opno++], output);
13908 for (argno = 0; argno < nargs; argno++)
13909 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13910 create_integer_operand (&ops[opno++], (int) cond);
13911 return mips_expand_builtin_insn (icode, opno, ops, true);
13914 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13915 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13916 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13917 suggests a good place to put the result. */
13920 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
13923 struct expand_operand ops[MAX_RECOG_OPERANDS];
13926 /* Map any target to operand 0. */
13929 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
13931 /* Map the arguments to the other operands. */
13932 gcc_assert (opno + call_expr_nargs (exp)
13933 == insn_data[icode].n_generator_args);
13934 for (argno = 0; argno < call_expr_nargs (exp); argno++)
13935 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
13937 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
13940 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13941 function; TYPE says which. EXP is the CALL_EXPR that calls the
13942 function, ICODE is the instruction that should be used to compare
13943 the first two arguments, and COND is the condition it should test.
13944 TARGET, if nonnull, suggests a good place to put the result. */
13947 mips_expand_builtin_movtf (enum mips_builtin_type type,
13948 enum insn_code icode, enum mips_fp_condition cond,
13949 rtx target, tree exp)
13951 struct expand_operand ops[4];
13954 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
13955 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
13956 if (type == MIPS_BUILTIN_MOVT)
13958 mips_prepare_builtin_arg (&ops[2], exp, 2);
13959 mips_prepare_builtin_arg (&ops[1], exp, 3);
13963 mips_prepare_builtin_arg (&ops[1], exp, 2);
13964 mips_prepare_builtin_arg (&ops[2], exp, 3);
13966 create_fixed_operand (&ops[3], cmp_result);
13967 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
13971 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13972 into TARGET otherwise. Return TARGET. */
13975 mips_builtin_branch_and_move (rtx condition, rtx target,
13976 rtx value_if_true, rtx value_if_false)
13978 rtx true_label, done_label;
13980 true_label = gen_label_rtx ();
13981 done_label = gen_label_rtx ();
13983 /* First assume that CONDITION is false. */
13984 mips_emit_move (target, value_if_false);
13986 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13987 emit_jump_insn (gen_condjump (condition, true_label));
13988 emit_jump_insn (gen_jump (done_label));
13991 /* Fix TARGET if CONDITION is true. */
13992 emit_label (true_label);
13993 mips_emit_move (target, value_if_true);
13995 emit_label (done_label);
13999 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14000 the CALL_EXPR that calls the function, ICODE is the code of the
14001 comparison instruction, and COND is the condition it should test.
14002 TARGET, if nonnull, suggests a good place to put the boolean result. */
14005 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
14006 enum insn_code icode, enum mips_fp_condition cond,
14007 rtx target, tree exp)
14009 rtx offset, condition, cmp_result;
14011 if (target == 0 || GET_MODE (target) != SImode)
14012 target = gen_reg_rtx (SImode);
14013 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
14014 call_expr_nargs (exp));
14016 /* If the comparison sets more than one register, we define the result
14017 to be 0 if all registers are false and -1 if all registers are true.
14018 The value of the complete result is indeterminate otherwise. */
14019 switch (builtin_type)
14021 case MIPS_BUILTIN_CMP_ALL:
14022 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
14023 return mips_builtin_branch_and_move (condition, target,
14024 const0_rtx, const1_rtx);
14026 case MIPS_BUILTIN_CMP_UPPER:
14027 case MIPS_BUILTIN_CMP_LOWER:
14028 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
14029 condition = gen_single_cc (cmp_result, offset);
14030 return mips_builtin_branch_and_move (condition, target,
14031 const1_rtx, const0_rtx);
14034 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
14035 return mips_builtin_branch_and_move (condition, target,
14036 const1_rtx, const0_rtx);
14040 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14041 if nonnull, suggests a good place to put the boolean result. */
14044 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
14046 rtx condition, cmp_result;
14049 if (target == 0 || GET_MODE (target) != SImode)
14050 target = gen_reg_rtx (SImode);
14052 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
14054 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
14059 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
14060 return mips_builtin_branch_and_move (condition, target,
14061 const1_rtx, const0_rtx);
14064 /* Implement TARGET_EXPAND_BUILTIN. */
14067 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
14068 enum machine_mode mode, int ignore)
14071 unsigned int fcode, avail;
14072 const struct mips_builtin_description *d;
14074 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14075 fcode = DECL_FUNCTION_CODE (fndecl);
14076 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
14077 d = &mips_builtins[fcode];
14078 avail = d->avail ();
14079 gcc_assert (avail != 0);
14082 error ("built-in function %qE not supported for MIPS16",
14083 DECL_NAME (fndecl));
14084 return ignore ? const0_rtx : CONST0_RTX (mode);
14086 switch (d->builtin_type)
14088 case MIPS_BUILTIN_DIRECT:
14089 return mips_expand_builtin_direct (d->icode, target, exp, true);
14091 case MIPS_BUILTIN_DIRECT_NO_TARGET:
14092 return mips_expand_builtin_direct (d->icode, target, exp, false);
14094 case MIPS_BUILTIN_MOVT:
14095 case MIPS_BUILTIN_MOVF:
14096 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
14097 d->cond, target, exp);
14099 case MIPS_BUILTIN_CMP_ANY:
14100 case MIPS_BUILTIN_CMP_ALL:
14101 case MIPS_BUILTIN_CMP_UPPER:
14102 case MIPS_BUILTIN_CMP_LOWER:
14103 case MIPS_BUILTIN_CMP_SINGLE:
14104 return mips_expand_builtin_compare (d->builtin_type, d->icode,
14105 d->cond, target, exp);
14107 case MIPS_BUILTIN_BPOSGE32:
14108 return mips_expand_builtin_bposge (d->builtin_type, target);
14110 gcc_unreachable ();
14113 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14114 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14115 struct mips16_constant {
14116 struct mips16_constant *next;
14119 enum machine_mode mode;
14122 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14123 first constant, HIGHEST_ADDRESS is the highest address that the first
14124 byte of the pool can have, and INSN_ADDRESS is the current instruction
14126 struct mips16_constant_pool {
14127 struct mips16_constant *first;
14128 int highest_address;
14132 /* Add constant VALUE to POOL and return its label. MODE is the
14133 value's mode (used for CONST_INTs, etc.). */
14136 mips16_add_constant (struct mips16_constant_pool *pool,
14137 rtx value, enum machine_mode mode)
14139 struct mips16_constant **p, *c;
14140 bool first_of_size_p;
14142 /* See whether the constant is already in the pool. If so, return the
14143 existing label, otherwise leave P pointing to the place where the
14144 constant should be added.
14146 Keep the pool sorted in increasing order of mode size so that we can
14147 reduce the number of alignments needed. */
14148 first_of_size_p = true;
14149 for (p = &pool->first; *p != 0; p = &(*p)->next)
14151 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
14152 return (*p)->label;
14153 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
14155 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
14156 first_of_size_p = false;
14159 /* In the worst case, the constant needed by the earliest instruction
14160 will end up at the end of the pool. The entire pool must then be
14161 accessible from that instruction.
14163 When adding the first constant, set the pool's highest address to
14164 the address of the first out-of-range byte. Adjust this address
14165 downwards each time a new constant is added. */
14166 if (pool->first == 0)
14167 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14168 of the instruction with the lowest two bits clear. The base PC
14169 value for LDPC has the lowest three bits clear. Assume the worst
14170 case here; namely that the PC-relative instruction occupies the
14171 last 2 bytes in an aligned word. */
14172 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
14173 pool->highest_address -= GET_MODE_SIZE (mode);
14174 if (first_of_size_p)
14175 /* Take into account the worst possible padding due to alignment. */
14176 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
14178 /* Create a new entry. */
14179 c = XNEW (struct mips16_constant);
14182 c->label = gen_label_rtx ();
14189 /* Output constant VALUE after instruction INSN and return the last
14190 instruction emitted. MODE is the mode of the constant. */
14193 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
14195 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
14197 rtx size = GEN_INT (GET_MODE_SIZE (mode));
14198 return emit_insn_after (gen_consttable_int (value, size), insn);
14201 if (SCALAR_FLOAT_MODE_P (mode))
14202 return emit_insn_after (gen_consttable_float (value), insn);
14204 if (VECTOR_MODE_P (mode))
14208 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
14209 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
14210 CONST_VECTOR_ELT (value, i), insn);
14214 gcc_unreachable ();
14217 /* Dump out the constants in CONSTANTS after INSN. */
14220 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
14222 struct mips16_constant *c, *next;
14226 for (c = constants; c != NULL; c = next)
14228 /* If necessary, increase the alignment of PC. */
14229 if (align < GET_MODE_SIZE (c->mode))
14231 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
14232 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
14234 align = GET_MODE_SIZE (c->mode);
14236 insn = emit_label_after (c->label, insn);
14237 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
14243 emit_barrier_after (insn);
14246 /* Return the length of instruction INSN. */
14249 mips16_insn_length (rtx insn)
14253 rtx body = PATTERN (insn);
14254 if (GET_CODE (body) == ADDR_VEC)
14255 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
14256 if (GET_CODE (body) == ADDR_DIFF_VEC)
14257 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14259 return get_attr_length (insn);
14262 /* If *X is a symbolic constant that refers to the constant pool, add
14263 the constant to POOL and rewrite *X to use the constant's label. */
14266 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14268 rtx base, offset, label;
14270 split_const (*x, &base, &offset);
14271 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14273 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
14274 get_pool_mode (base));
14275 base = gen_rtx_LABEL_REF (Pmode, label);
14276 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14280 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14281 INSN is the instruction we're rewriting and POOL points to the current
14283 struct mips16_rewrite_pool_refs_info {
14285 struct mips16_constant_pool *pool;
14288 /* Rewrite *X so that constant pool references refer to the constant's
14289 label instead. DATA points to a mips16_rewrite_pool_refs_info
14293 mips16_rewrite_pool_refs (rtx *x, void *data)
14295 struct mips16_rewrite_pool_refs_info *info =
14296 (struct mips16_rewrite_pool_refs_info *) data;
14298 if (force_to_mem_operand (*x, Pmode))
14300 rtx mem = force_const_mem (GET_MODE (*x), *x);
14301 validate_change (info->insn, x, mem, false);
14306 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
14310 /* Don't rewrite the __mips16_rdwr symbol. */
14311 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14314 if (TARGET_MIPS16_TEXT_LOADS)
14315 mips16_rewrite_pool_constant (info->pool, x);
14317 return GET_CODE (*x) == CONST ? -1 : 0;
14320 /* Return whether CFG is used in mips_reorg. */
14323 mips_cfg_in_reorg (void)
14325 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14326 || TARGET_RELAX_PIC_CALLS);
14329 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14330 otherwise assume that they are already split. */
14333 mips16_lay_out_constants (bool split_p)
14335 struct mips16_constant_pool pool;
14336 struct mips16_rewrite_pool_refs_info info;
14339 if (!TARGET_MIPS16_PCREL_LOADS)
14344 if (mips_cfg_in_reorg ())
14345 split_all_insns ();
14347 split_all_insns_noflow ();
14350 memset (&pool, 0, sizeof (pool));
14351 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14353 /* Rewrite constant pool references in INSN. */
14354 if (USEFUL_INSN_P (insn))
14358 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14361 pool.insn_address += mips16_insn_length (insn);
14363 if (pool.first != NULL)
14365 /* If there are no natural barriers between the first user of
14366 the pool and the highest acceptable address, we'll need to
14367 create a new instruction to jump around the constant pool.
14368 In the worst case, this instruction will be 4 bytes long.
14370 If it's too late to do this transformation after INSN,
14371 do it immediately before INSN. */
14372 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14376 label = gen_label_rtx ();
14378 jump = emit_jump_insn_before (gen_jump (label), insn);
14379 JUMP_LABEL (jump) = label;
14380 LABEL_NUSES (label) = 1;
14381 barrier = emit_barrier_after (jump);
14383 emit_label_after (label, barrier);
14384 pool.insn_address += 4;
14387 /* See whether the constant pool is now out of range of the first
14388 user. If so, output the constants after the previous barrier.
14389 Note that any instructions between BARRIER and INSN (inclusive)
14390 will use negative offsets to refer to the pool. */
14391 if (pool.insn_address > pool.highest_address)
14393 mips16_emit_constants (pool.first, barrier);
14397 else if (BARRIER_P (insn))
14401 mips16_emit_constants (pool.first, get_last_insn ());
14404 /* Return true if it is worth r10k_simplify_address's while replacing
14405 an address with X. We are looking for constants, and for addresses
14406 at a known offset from the incoming stack pointer. */
14409 r10k_simplified_address_p (rtx x)
14411 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14413 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14416 /* X is an expression that appears in INSN. Try to use the UD chains
14417 to simplify it, returning the simplified form on success and the
14418 original form otherwise. Replace the incoming value of $sp with
14419 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14422 r10k_simplify_address (rtx x, rtx insn)
14424 rtx newx, op0, op1, set, def_insn, note;
14426 struct df_link *defs;
14431 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14432 if (op0 != XEXP (x, 0))
14433 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14434 op0, GET_MODE (XEXP (x, 0)));
14436 else if (BINARY_P (x))
14438 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14439 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14440 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14441 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14443 else if (GET_CODE (x) == LO_SUM)
14445 /* LO_SUMs can be offset from HIGHs, if we know they won't
14446 overflow. See mips_classify_address for the rationale behind
14448 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14449 if (GET_CODE (op0) == HIGH)
14450 newx = XEXP (x, 1);
14452 else if (REG_P (x))
14454 /* Uses are recorded by regno_reg_rtx, not X itself. */
14455 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14457 defs = DF_REF_CHAIN (use);
14459 /* Require a single definition. */
14460 if (defs && defs->next == NULL)
14463 if (DF_REF_IS_ARTIFICIAL (def))
14465 /* Replace the incoming value of $sp with
14466 virtual_incoming_args_rtx. */
14467 if (x == stack_pointer_rtx
14468 && DF_REF_BB (def) == ENTRY_BLOCK_PTR)
14469 newx = virtual_incoming_args_rtx;
14471 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14474 /* Make sure that DEF_INSN is a single set of REG. */
14475 def_insn = DF_REF_INSN (def);
14476 if (NONJUMP_INSN_P (def_insn))
14478 set = single_set (def_insn);
14479 if (set && rtx_equal_p (SET_DEST (set), x))
14481 /* Prefer to use notes, since the def-use chains
14482 are often shorter. */
14483 note = find_reg_equal_equiv_note (def_insn);
14485 newx = XEXP (note, 0);
14487 newx = SET_SRC (set);
14488 newx = r10k_simplify_address (newx, def_insn);
14494 if (newx && r10k_simplified_address_p (newx))
14499 /* Return true if ADDRESS is known to be an uncached address
14500 on R10K systems. */
14503 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
14505 unsigned HOST_WIDE_INT upper;
14507 /* Check for KSEG1. */
14508 if (address + 0x60000000 < 0x20000000)
14511 /* Check for uncached XKPHYS addresses. */
14512 if (Pmode == DImode)
14514 upper = (address >> 40) & 0xf9ffff;
14515 if (upper == 0x900000 || upper == 0xb80000)
14521 /* Return true if we can prove that an access to address X in instruction
14522 INSN would be safe from R10K speculation. This X is a general
14523 expression; it might not be a legitimate address. */
14526 r10k_safe_address_p (rtx x, rtx insn)
14529 HOST_WIDE_INT offset_val;
14531 x = r10k_simplify_address (x, insn);
14533 /* Check for references to the stack frame. It doesn't really matter
14534 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
14535 allows us to assume that accesses to any part of the eventual frame
14536 is safe from speculation at any point in the function. */
14537 mips_split_plus (x, &base, &offset_val);
14538 if (base == virtual_incoming_args_rtx
14539 && offset_val >= -cfun->machine->frame.total_size
14540 && offset_val < cfun->machine->frame.args_size)
14543 /* Check for uncached addresses. */
14544 if (CONST_INT_P (x))
14545 return r10k_uncached_address_p (INTVAL (x));
14547 /* Check for accesses to a static object. */
14548 split_const (x, &base, &offset);
14549 return offset_within_block_p (base, INTVAL (offset));
14552 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
14553 an in-range access to an automatic variable, or to an object with
14554 a link-time-constant address. */
14557 r10k_safe_mem_expr_p (tree expr, HOST_WIDE_INT offset)
14559 HOST_WIDE_INT bitoffset, bitsize;
14560 tree inner, var_offset;
14561 enum machine_mode mode;
14562 int unsigned_p, volatile_p;
14564 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
14565 &unsigned_p, &volatile_p, false);
14566 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
14569 offset += bitoffset / BITS_PER_UNIT;
14570 return offset >= 0 && offset < tree_low_cst (DECL_SIZE_UNIT (inner), 1);
14573 /* A for_each_rtx callback for which DATA points to the instruction
14574 containing *X. Stop the search if we find a MEM that is not safe
14575 from R10K speculation. */
14578 r10k_needs_protection_p_1 (rtx *loc, void *data)
14587 && MEM_OFFSET_KNOWN_P (mem)
14588 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
14591 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
14597 /* A note_stores callback for which DATA points to an instruction pointer.
14598 If *DATA is nonnull, make it null if it X contains a MEM that is not
14599 safe from R10K speculation. */
14602 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
14607 insn_ptr = (rtx *) data;
14608 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
14609 *insn_ptr = NULL_RTX;
14612 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
14613 Return nonzero if the call is not to a declared function. */
14616 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
14625 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
14631 /* Return true if instruction INSN needs to be protected by an R10K
14635 r10k_needs_protection_p (rtx insn)
14638 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
14640 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
14642 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
14643 return insn == NULL_RTX;
14646 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
14649 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14650 edge is unconditional. */
14653 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
14658 FOR_EACH_EDGE (e, ei, bb->preds)
14659 if (!single_succ_p (e->src)
14660 || !TEST_BIT (protected_bbs, e->src->index)
14661 || (e->flags & EDGE_COMPLEX) != 0)
14666 /* Implement -mr10k-cache-barrier= for the current function. */
14669 r10k_insert_cache_barriers (void)
14671 int *rev_post_order;
14674 sbitmap protected_bbs;
14675 rtx insn, end, unprotected_region;
14679 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14683 /* Calculate dominators. */
14684 calculate_dominance_info (CDI_DOMINATORS);
14686 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14687 X is protected by a cache barrier. */
14688 protected_bbs = sbitmap_alloc (last_basic_block);
14689 sbitmap_zero (protected_bbs);
14691 /* Iterate over the basic blocks in reverse post-order. */
14692 rev_post_order = XNEWVEC (int, last_basic_block);
14693 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
14694 for (i = 0; i < n; i++)
14696 bb = BASIC_BLOCK (rev_post_order[i]);
14698 /* If this block is only reached by unconditional edges, and if the
14699 source of every edge is protected, the beginning of the block is
14701 if (r10k_protected_bb_p (bb, protected_bbs))
14702 unprotected_region = NULL_RTX;
14704 unprotected_region = pc_rtx;
14705 end = NEXT_INSN (BB_END (bb));
14707 /* UNPROTECTED_REGION is:
14709 - null if we are processing a protected region,
14710 - pc_rtx if we are processing an unprotected region but have
14711 not yet found the first instruction in it
14712 - the first instruction in an unprotected region otherwise. */
14713 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
14715 if (unprotected_region && USEFUL_INSN_P (insn))
14717 if (recog_memoized (insn) == CODE_FOR_mips_cache)
14718 /* This CACHE instruction protects the following code. */
14719 unprotected_region = NULL_RTX;
14722 /* See if INSN is the first instruction in this
14723 unprotected region. */
14724 if (unprotected_region == pc_rtx)
14725 unprotected_region = insn;
14727 /* See if INSN needs to be protected. If so,
14728 we must insert a cache barrier somewhere between
14729 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14730 clear which position is better performance-wise,
14731 but as a tie-breaker, we assume that it is better
14732 to allow delay slots to be back-filled where
14733 possible, and that it is better not to insert
14734 barriers in the middle of already-scheduled code.
14735 We therefore insert the barrier at the beginning
14737 if (r10k_needs_protection_p (insn))
14739 emit_insn_before (gen_r10k_cache_barrier (),
14740 unprotected_region);
14741 unprotected_region = NULL_RTX;
14747 /* The called function is not required to protect the exit path.
14748 The code that follows a call is therefore unprotected. */
14749 unprotected_region = pc_rtx;
14752 /* Record whether the end of this block is protected. */
14753 if (unprotected_region == NULL_RTX)
14754 SET_BIT (protected_bbs, bb->index);
14756 XDELETEVEC (rev_post_order);
14758 sbitmap_free (protected_bbs);
14760 free_dominance_info (CDI_DOMINATORS);
14763 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14764 otherwise. If INSN has two call rtx, then store the second one in
14768 mips_call_expr_from_insn (rtx insn, rtx *second_call)
14773 if (!CALL_P (insn))
14776 x = PATTERN (insn);
14777 if (GET_CODE (x) == PARALLEL)
14779 /* Calls returning complex values have two CALL rtx. Look for the second
14780 one here, and return it via the SECOND_CALL arg. */
14781 x2 = XVECEXP (x, 0, 1);
14782 if (GET_CODE (x2) == SET)
14784 if (GET_CODE (x2) == CALL)
14787 x = XVECEXP (x, 0, 0);
14789 if (GET_CODE (x) == SET)
14791 gcc_assert (GET_CODE (x) == CALL);
14796 /* REG is set in DEF. See if the definition is one of the ways we load a
14797 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
14798 If it is, return the symbol reference of the function, otherwise return
14801 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
14802 the values of source registers, otherwise treat such registers as
14803 having an unknown value. */
14806 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
14810 if (DF_REF_IS_ARTIFICIAL (def))
14813 def_insn = DF_REF_INSN (def);
14814 set = single_set (def_insn);
14815 if (set && rtx_equal_p (SET_DEST (set), reg))
14817 rtx note, src, symbol;
14819 /* First see whether the source is a plain symbol. This is used
14820 when calling symbols that are not lazily bound. */
14821 src = SET_SRC (set);
14822 if (GET_CODE (src) == SYMBOL_REF)
14825 /* Handle %call16 references. */
14826 symbol = mips_strip_unspec_call (src);
14829 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14833 /* If we have something more complicated, look for a
14834 REG_EQUAL or REG_EQUIV note. */
14835 note = find_reg_equal_equiv_note (def_insn);
14836 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
14837 return XEXP (note, 0);
14839 /* Follow at most one simple register copy. Such copies are
14840 interesting in cases like:
14844 locally_binding_fn (...);
14849 locally_binding_fn (...);
14851 locally_binding_fn (...);
14853 where the load of locally_binding_fn can legitimately be
14854 hoisted or shared. However, we do not expect to see complex
14855 chains of copies, so a full worklist solution to the problem
14856 would probably be overkill. */
14857 if (recurse_p && REG_P (src))
14858 return mips_find_pic_call_symbol (def_insn, src, false);
14864 /* Find the definition of the use of REG in INSN. See if the definition
14865 is one of the ways we load a register with a symbol address for a
14866 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
14867 of the function, otherwise return NULL_RTX. RECURSE_P is as for
14868 mips_pic_call_symbol_from_set. */
14871 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
14874 struct df_link *defs;
14877 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
14880 defs = DF_REF_CHAIN (use);
14883 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14887 /* If we have more than one definition, they need to be identical. */
14888 for (defs = defs->next; defs; defs = defs->next)
14892 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
14893 if (!rtx_equal_p (symbol, other))
14900 /* Replace the args_size operand of the call expression CALL with the
14901 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14904 mips_annotate_pic_call_expr (rtx call, rtx symbol)
14908 args_size = XEXP (call, 1);
14909 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
14910 gen_rtvec (2, args_size, symbol),
14914 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14915 if instead of the arg_size argument it contains the call attributes. If
14916 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14917 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14921 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
14923 rtx args_size, symbol;
14925 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
14928 args_size = operands[args_size_opno];
14929 if (GET_CODE (args_size) != UNSPEC)
14931 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
14933 symbol = XVECEXP (args_size, 0, 1);
14934 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
14936 operands[args_size_opno] = symbol;
14940 /* Use DF to annotate PIC indirect calls with the function symbol they
14944 mips_annotate_pic_calls (void)
14950 FOR_BB_INSNS (bb, insn)
14952 rtx call, reg, symbol, second_call;
14955 call = mips_call_expr_from_insn (insn, &second_call);
14958 gcc_assert (MEM_P (XEXP (call, 0)));
14959 reg = XEXP (XEXP (call, 0), 0);
14963 symbol = mips_find_pic_call_symbol (insn, reg, true);
14966 mips_annotate_pic_call_expr (call, symbol);
14968 mips_annotate_pic_call_expr (second_call, symbol);
14973 /* A temporary variable used by for_each_rtx callbacks, etc. */
14974 static rtx mips_sim_insn;
14976 /* A structure representing the state of the processor pipeline.
14977 Used by the mips_sim_* family of functions. */
14979 /* The maximum number of instructions that can be issued in a cycle.
14980 (Caches mips_issue_rate.) */
14981 unsigned int issue_rate;
14983 /* The current simulation time. */
14986 /* How many more instructions can be issued in the current cycle. */
14987 unsigned int insns_left;
14989 /* LAST_SET[X].INSN is the last instruction to set register X.
14990 LAST_SET[X].TIME is the time at which that instruction was issued.
14991 INSN is null if no instruction has yet set register X. */
14995 } last_set[FIRST_PSEUDO_REGISTER];
14997 /* The pipeline's current DFA state. */
15001 /* Reset STATE to the initial simulation state. */
15004 mips_sim_reset (struct mips_sim *state)
15006 curr_state = state->dfa_state;
15009 state->insns_left = state->issue_rate;
15010 memset (&state->last_set, 0, sizeof (state->last_set));
15011 state_reset (curr_state);
15013 targetm.sched.init (0, false, 0);
15014 advance_state (curr_state);
15017 /* Initialize STATE before its first use. DFA_STATE points to an
15018 allocated but uninitialized DFA state. */
15021 mips_sim_init (struct mips_sim *state, state_t dfa_state)
15023 if (targetm.sched.init_dfa_pre_cycle_insn)
15024 targetm.sched.init_dfa_pre_cycle_insn ();
15026 if (targetm.sched.init_dfa_post_cycle_insn)
15027 targetm.sched.init_dfa_post_cycle_insn ();
15029 state->issue_rate = mips_issue_rate ();
15030 state->dfa_state = dfa_state;
15031 mips_sim_reset (state);
15034 /* Advance STATE by one clock cycle. */
15037 mips_sim_next_cycle (struct mips_sim *state)
15039 curr_state = state->dfa_state;
15042 state->insns_left = state->issue_rate;
15043 advance_state (curr_state);
15046 /* Advance simulation state STATE until instruction INSN can read
15050 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
15052 unsigned int regno, end_regno;
15054 end_regno = END_REGNO (reg);
15055 for (regno = REGNO (reg); regno < end_regno; regno++)
15056 if (state->last_set[regno].insn != 0)
15060 t = (state->last_set[regno].time
15061 + insn_latency (state->last_set[regno].insn, insn));
15062 while (state->time < t)
15063 mips_sim_next_cycle (state);
15067 /* A for_each_rtx callback. If *X is a register, advance simulation state
15068 DATA until mips_sim_insn can read the register's value. */
15071 mips_sim_wait_regs_2 (rtx *x, void *data)
15074 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
15078 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15081 mips_sim_wait_regs_1 (rtx *x, void *data)
15083 for_each_rtx (x, mips_sim_wait_regs_2, data);
15086 /* Advance simulation state STATE until all of INSN's register
15087 dependencies are satisfied. */
15090 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
15092 mips_sim_insn = insn;
15093 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
15096 /* Advance simulation state STATE until the units required by
15097 instruction INSN are available. */
15100 mips_sim_wait_units (struct mips_sim *state, rtx insn)
15104 tmp_state = alloca (state_size ());
15105 while (state->insns_left == 0
15106 || (memcpy (tmp_state, state->dfa_state, state_size ()),
15107 state_transition (tmp_state, insn) >= 0))
15108 mips_sim_next_cycle (state);
15111 /* Advance simulation state STATE until INSN is ready to issue. */
15114 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
15116 mips_sim_wait_regs (state, insn);
15117 mips_sim_wait_units (state, insn);
15120 /* mips_sim_insn has just set X. Update the LAST_SET array
15121 in simulation state DATA. */
15124 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
15126 struct mips_sim *state;
15128 state = (struct mips_sim *) data;
15131 unsigned int regno, end_regno;
15133 end_regno = END_REGNO (x);
15134 for (regno = REGNO (x); regno < end_regno; regno++)
15136 state->last_set[regno].insn = mips_sim_insn;
15137 state->last_set[regno].time = state->time;
15142 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15143 can issue immediately (i.e., that mips_sim_wait_insn has already
15147 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
15149 curr_state = state->dfa_state;
15151 state_transition (curr_state, insn);
15152 state->insns_left = targetm.sched.variable_issue (0, false, insn,
15153 state->insns_left);
15155 mips_sim_insn = insn;
15156 note_stores (PATTERN (insn), mips_sim_record_set, state);
15159 /* Simulate issuing a NOP in state STATE. */
15162 mips_sim_issue_nop (struct mips_sim *state)
15164 if (state->insns_left == 0)
15165 mips_sim_next_cycle (state);
15166 state->insns_left--;
15169 /* Update simulation state STATE so that it's ready to accept the instruction
15170 after INSN. INSN should be part of the main rtl chain, not a member of a
15174 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
15176 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15178 mips_sim_issue_nop (state);
15180 switch (GET_CODE (SEQ_BEGIN (insn)))
15184 /* We can't predict the processor state after a call or label. */
15185 mips_sim_reset (state);
15189 /* The delay slots of branch likely instructions are only executed
15190 when the branch is taken. Therefore, if the caller has simulated
15191 the delay slot instruction, STATE does not really reflect the state
15192 of the pipeline for the instruction after the delay slot. Also,
15193 branch likely instructions tend to incur a penalty when not taken,
15194 so there will probably be an extra delay between the branch and
15195 the instruction after the delay slot. */
15196 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
15197 mips_sim_reset (state);
15205 /* Use simulator state STATE to calculate the execution time of
15206 instruction sequence SEQ. */
15208 static unsigned int
15209 mips_seq_time (struct mips_sim *state, rtx seq)
15211 mips_sim_reset (state);
15212 for (rtx insn = seq; insn; insn = NEXT_INSN (insn))
15214 mips_sim_wait_insn (state, insn);
15215 mips_sim_issue_insn (state, insn);
15217 return state->time;
15220 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15221 setting SETTING, using STATE to simulate instruction sequences. */
15223 static unsigned int
15224 mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
15226 mips_tuning_info.fast_mult_zero_zero_p = setting;
15229 enum machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
15230 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
15231 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
15233 /* If the target provides mulsidi3_32bit then that's the most likely
15234 consumer of the result. Test for bypasses. */
15235 if (dword_mode == DImode && HAVE_maddsidi4)
15237 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
15238 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
15241 unsigned int time = mips_seq_time (state, get_insns ());
15246 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15247 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15248 Prefer MULT -- which is shorter -- in the event of a tie. */
15251 mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
15254 /* No MTLO or MTHI available. */
15255 mips_tuning_info.fast_mult_zero_zero_p = true;
15258 unsigned int true_time = mips_mult_zero_zero_cost (state, true);
15259 unsigned int false_time = mips_mult_zero_zero_cost (state, false);
15260 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
15264 /* Set up costs based on the current architecture and tuning settings. */
15267 mips_set_tuning_info (void)
15269 if (mips_tuning_info.initialized_p
15270 && mips_tuning_info.arch == mips_arch
15271 && mips_tuning_info.tune == mips_tune
15272 && mips_tuning_info.mips16_p == TARGET_MIPS16)
15275 mips_tuning_info.arch = mips_arch;
15276 mips_tuning_info.tune = mips_tune;
15277 mips_tuning_info.mips16_p = TARGET_MIPS16;
15278 mips_tuning_info.initialized_p = true;
15282 struct mips_sim state;
15283 mips_sim_init (&state, alloca (state_size ()));
15285 mips_set_fast_mult_zero_zero_p (&state);
15290 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15293 mips_expand_to_rtl_hook (void)
15295 /* We need to call this at a point where we can safely create sequences
15296 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15297 need to call it at a point where the DFA infrastructure is not
15298 already in use, so we can't just call it lazily on demand.
15300 At present, mips_tuning_info is only needed during post-expand
15301 RTL passes such as split_insns, so this hook should be early enough.
15302 We may need to move the call elsewhere if mips_tuning_info starts
15303 to be used for other things (such as rtx_costs, or expanders that
15304 could be called during gimple optimization). */
15305 mips_set_tuning_info ();
15308 /* The VR4130 pipeline issues aligned pairs of instructions together,
15309 but it stalls the second instruction if it depends on the first.
15310 In order to cut down the amount of logic required, this dependence
15311 check is not based on a full instruction decode. Instead, any non-SPECIAL
15312 instruction is assumed to modify the register specified by bits 20-16
15313 (which is usually the "rt" field).
15315 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15316 input, so we can end up with a false dependence between the branch
15317 and its delay slot. If this situation occurs in instruction INSN,
15318 try to avoid it by swapping rs and rt. */
15321 vr4130_avoid_branch_rt_conflict (rtx insn)
15325 first = SEQ_BEGIN (insn);
15326 second = SEQ_END (insn);
15328 && NONJUMP_INSN_P (second)
15329 && GET_CODE (PATTERN (first)) == SET
15330 && GET_CODE (SET_DEST (PATTERN (first))) == PC
15331 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
15333 /* Check for the right kind of condition. */
15334 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
15335 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
15336 && REG_P (XEXP (cond, 0))
15337 && REG_P (XEXP (cond, 1))
15338 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
15339 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
15341 /* SECOND mentions the rt register but not the rs register. */
15342 rtx tmp = XEXP (cond, 0);
15343 XEXP (cond, 0) = XEXP (cond, 1);
15344 XEXP (cond, 1) = tmp;
15349 /* Implement -mvr4130-align. Go through each basic block and simulate the
15350 processor pipeline. If we find that a pair of instructions could execute
15351 in parallel, and the first of those instructions is not 8-byte aligned,
15352 insert a nop to make it aligned. */
15355 vr4130_align_insns (void)
15357 struct mips_sim state;
15358 rtx insn, subinsn, last, last2, next;
15363 /* LAST is the last instruction before INSN to have a nonzero length.
15364 LAST2 is the last such instruction before LAST. */
15368 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15371 mips_sim_init (&state, alloca (state_size ()));
15372 for (insn = get_insns (); insn != 0; insn = next)
15374 unsigned int length;
15376 next = NEXT_INSN (insn);
15378 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15379 This isn't really related to the alignment pass, but we do it on
15380 the fly to avoid a separate instruction walk. */
15381 vr4130_avoid_branch_rt_conflict (insn);
15383 length = get_attr_length (insn);
15384 if (length > 0 && USEFUL_INSN_P (insn))
15385 FOR_EACH_SUBINSN (subinsn, insn)
15387 mips_sim_wait_insn (&state, subinsn);
15389 /* If we want this instruction to issue in parallel with the
15390 previous one, make sure that the previous instruction is
15391 aligned. There are several reasons why this isn't worthwhile
15392 when the second instruction is a call:
15394 - Calls are less likely to be performance critical,
15395 - There's a good chance that the delay slot can execute
15396 in parallel with the call.
15397 - The return address would then be unaligned.
15399 In general, if we're going to insert a nop between instructions
15400 X and Y, it's better to insert it immediately after X. That
15401 way, if the nop makes Y aligned, it will also align any labels
15402 between X and Y. */
15403 if (state.insns_left != state.issue_rate
15404 && !CALL_P (subinsn))
15406 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
15408 /* SUBINSN is the first instruction in INSN and INSN is
15409 aligned. We want to align the previous instruction
15410 instead, so insert a nop between LAST2 and LAST.
15412 Note that LAST could be either a single instruction
15413 or a branch with a delay slot. In the latter case,
15414 LAST, like INSN, is already aligned, but the delay
15415 slot must have some extra delay that stops it from
15416 issuing at the same time as the branch. We therefore
15417 insert a nop before the branch in order to align its
15419 gcc_assert (last2);
15420 emit_insn_after (gen_nop (), last2);
15423 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
15425 /* SUBINSN is the delay slot of INSN, but INSN is
15426 currently unaligned. Insert a nop between
15427 LAST and INSN to align it. */
15429 emit_insn_after (gen_nop (), last);
15433 mips_sim_issue_insn (&state, subinsn);
15435 mips_sim_finish_insn (&state, insn);
15437 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15438 length = get_attr_length (insn);
15441 /* If the instruction is an asm statement or multi-instruction
15442 mips.md patern, the length is only an estimate. Insert an
15443 8 byte alignment after it so that the following instructions
15444 can be handled correctly. */
15445 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
15446 && (recog_memoized (insn) < 0 || length >= 8))
15448 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15449 next = NEXT_INSN (next);
15450 mips_sim_next_cycle (&state);
15453 else if (length & 4)
15454 aligned_p = !aligned_p;
15459 /* See whether INSN is an aligned label. */
15460 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15466 /* This structure records that the current function has a LO_SUM
15467 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15468 the largest offset applied to BASE by all such LO_SUMs. */
15469 struct mips_lo_sum_offset {
15471 HOST_WIDE_INT offset;
15474 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15477 mips_hash_base (rtx base)
15479 int do_not_record_p;
15481 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
15484 /* Hash-table callbacks for mips_lo_sum_offsets. */
15487 mips_lo_sum_offset_hash (const void *entry)
15489 return mips_hash_base (((const struct mips_lo_sum_offset *) entry)->base);
15493 mips_lo_sum_offset_eq (const void *entry, const void *value)
15495 return rtx_equal_p (((const struct mips_lo_sum_offset *) entry)->base,
15496 (const_rtx) value);
15499 /* Look up symbolic constant X in HTAB, which is a hash table of
15500 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
15501 paired with a recorded LO_SUM, otherwise record X in the table. */
15504 mips_lo_sum_offset_lookup (htab_t htab, rtx x, enum insert_option option)
15508 struct mips_lo_sum_offset *entry;
15510 /* Split X into a base and offset. */
15511 split_const (x, &base, &offset);
15512 if (UNSPEC_ADDRESS_P (base))
15513 base = UNSPEC_ADDRESS (base);
15515 /* Look up the base in the hash table. */
15516 slot = htab_find_slot_with_hash (htab, base, mips_hash_base (base), option);
15520 entry = (struct mips_lo_sum_offset *) *slot;
15521 if (option == INSERT)
15525 entry = XNEW (struct mips_lo_sum_offset);
15526 entry->base = base;
15527 entry->offset = INTVAL (offset);
15532 if (INTVAL (offset) > entry->offset)
15533 entry->offset = INTVAL (offset);
15536 return INTVAL (offset) <= entry->offset;
15539 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
15540 Record every LO_SUM in *LOC. */
15543 mips_record_lo_sum (rtx *loc, void *data)
15545 if (GET_CODE (*loc) == LO_SUM)
15546 mips_lo_sum_offset_lookup ((htab_t) data, XEXP (*loc, 1), INSERT);
15550 /* Return true if INSN is a SET of an orphaned high-part relocation.
15551 HTAB is a hash table of mips_lo_sum_offsets that describes all the
15552 LO_SUMs in the current function. */
15555 mips_orphaned_high_part_p (htab_t htab, rtx insn)
15557 enum mips_symbol_type type;
15560 set = single_set (insn);
15563 /* Check for %his. */
15565 if (GET_CODE (x) == HIGH
15566 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
15567 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
15569 /* Check for local %gots (and %got_pages, which is redundant but OK). */
15570 if (GET_CODE (x) == UNSPEC
15571 && XINT (x, 1) == UNSPEC_LOAD_GOT
15572 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
15573 SYMBOL_CONTEXT_LEA, &type)
15574 && type == SYMBOL_GOTOFF_PAGE)
15575 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
15580 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
15581 INSN and a previous instruction, avoid it by inserting nops after
15584 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
15585 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
15586 before using the value of that register. *HILO_DELAY counts the
15587 number of instructions since the last hilo hazard (that is,
15588 the number of instructions since the last MFLO or MFHI).
15590 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
15591 for the next instruction.
15593 LO_REG is an rtx for the LO register, used in dependence checking. */
15596 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
15597 rtx *delayed_reg, rtx lo_reg)
15602 pattern = PATTERN (insn);
15604 /* Do not put the whole function in .set noreorder if it contains
15605 an asm statement. We don't know whether there will be hazards
15606 between the asm statement and the gcc-generated code. */
15607 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
15608 cfun->machine->all_noreorder_p = false;
15610 /* Ignore zero-length instructions (barriers and the like). */
15611 ninsns = get_attr_length (insn) / 4;
15615 /* Work out how many nops are needed. Note that we only care about
15616 registers that are explicitly mentioned in the instruction's pattern.
15617 It doesn't matter that calls use the argument registers or that they
15618 clobber hi and lo. */
15619 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
15620 nops = 2 - *hilo_delay;
15621 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
15626 /* Insert the nops between this instruction and the previous one.
15627 Each new nop takes us further from the last hilo hazard. */
15628 *hilo_delay += nops;
15630 emit_insn_after (gen_hazard_nop (), after);
15632 /* Set up the state for the next instruction. */
15633 *hilo_delay += ninsns;
15635 if (INSN_CODE (insn) >= 0)
15636 switch (get_attr_hazard (insn))
15646 set = single_set (insn);
15648 *delayed_reg = SET_DEST (set);
15653 /* Go through the instruction stream and insert nops where necessary.
15654 Also delete any high-part relocations whose partnering low parts
15655 are now all dead. See if the whole function can then be put into
15656 .set noreorder and .set nomacro. */
15659 mips_reorg_process_insns (void)
15661 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
15665 /* Force all instructions to be split into their final form. */
15666 split_all_insns_noflow ();
15668 /* Recalculate instruction lengths without taking nops into account. */
15669 cfun->machine->ignore_hazard_length_p = true;
15670 shorten_branches (get_insns ());
15672 cfun->machine->all_noreorder_p = true;
15674 /* We don't track MIPS16 PC-relative offsets closely enough to make
15675 a good job of "set .noreorder" code in MIPS16 mode. */
15677 cfun->machine->all_noreorder_p = false;
15679 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
15680 if (!TARGET_EXPLICIT_RELOCS)
15681 cfun->machine->all_noreorder_p = false;
15683 /* Profiled functions can't be all noreorder because the profiler
15684 support uses assembler macros. */
15686 cfun->machine->all_noreorder_p = false;
15688 /* Code compiled with -mfix-vr4120 or -mfix-24k can't be all noreorder
15689 because we rely on the assembler to work around some errata. */
15690 if (TARGET_FIX_VR4120 || TARGET_FIX_24K)
15691 cfun->machine->all_noreorder_p = false;
15693 /* The same is true for -mfix-vr4130 if we might generate MFLO or
15694 MFHI instructions. Note that we avoid using MFLO and MFHI if
15695 the VR4130 MACC and DMACC instructions are available instead;
15696 see the *mfhilo_{si,di}_macc patterns. */
15697 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
15698 cfun->machine->all_noreorder_p = false;
15700 htab = htab_create (37, mips_lo_sum_offset_hash,
15701 mips_lo_sum_offset_eq, free);
15703 /* Make a first pass over the instructions, recording all the LO_SUMs. */
15704 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15705 FOR_EACH_SUBINSN (subinsn, insn)
15706 if (USEFUL_INSN_P (subinsn))
15707 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, htab);
15712 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
15714 /* Make a second pass over the instructions. Delete orphaned
15715 high-part relocations or turn them into NOPs. Avoid hazards
15716 by inserting NOPs. */
15717 for (insn = get_insns (); insn != 0; insn = next_insn)
15719 next_insn = NEXT_INSN (insn);
15720 if (USEFUL_INSN_P (insn))
15722 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
15724 /* If we find an orphaned high-part relocation in a delay
15725 slot, it's easier to turn that instruction into a NOP than
15726 to delete it. The delay slot will be a NOP either way. */
15727 FOR_EACH_SUBINSN (subinsn, insn)
15728 if (INSN_P (subinsn))
15730 if (mips_orphaned_high_part_p (htab, subinsn))
15732 PATTERN (subinsn) = gen_nop ();
15733 INSN_CODE (subinsn) = CODE_FOR_nop;
15735 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
15736 &delayed_reg, lo_reg);
15742 /* INSN is a single instruction. Delete it if it's an
15743 orphaned high-part relocation. */
15744 if (mips_orphaned_high_part_p (htab, insn))
15745 delete_insn (insn);
15746 /* Also delete cache barriers if the last instruction
15747 was an annulled branch. INSN will not be speculatively
15749 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
15751 && JUMP_P (SEQ_BEGIN (last_insn))
15752 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
15753 delete_insn (insn);
15756 mips_avoid_hazard (last_insn, insn, &hilo_delay,
15757 &delayed_reg, lo_reg);
15764 htab_delete (htab);
15767 /* Return true if the function has a long branch instruction. */
15770 mips_has_long_branch_p (void)
15775 /* We need up-to-date instruction lengths. */
15776 shorten_branches (get_insns ());
15778 /* Look for a branch that is longer than normal. The normal length for
15779 non-MIPS16 branches is 8, because the length includes the delay slot.
15780 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
15781 but they have no delay slot. */
15782 normal_length = (TARGET_MIPS16 ? 4 : 8);
15783 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15784 FOR_EACH_SUBINSN (subinsn, insn)
15785 if (JUMP_P (subinsn)
15786 && USEFUL_INSN_P (subinsn)
15787 && get_attr_length (subinsn) > normal_length
15788 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
15794 /* If we are using a GOT, but have not decided to use a global pointer yet,
15795 see whether we need one to implement long branches. Convert the ghost
15796 global-pointer instructions into real ones if so. */
15799 mips_expand_ghost_gp_insns (void)
15801 /* Quick exit if we already know that we will or won't need a
15803 if (!TARGET_USE_GOT
15804 || cfun->machine->global_pointer == INVALID_REGNUM
15805 || mips_must_initialize_gp_p ())
15808 /* Run a full check for long branches. */
15809 if (!mips_has_long_branch_p ())
15812 /* We've now established that we need $gp. */
15813 cfun->machine->must_initialize_gp_p = true;
15814 split_all_insns_noflow ();
15819 /* Subroutine of mips_reorg to manage passes that require DF. */
15822 mips_df_reorg (void)
15824 /* Create def-use chains. */
15825 df_set_flags (DF_EQ_NOTES);
15826 df_chain_add_problem (DF_UD_CHAIN);
15829 if (TARGET_RELAX_PIC_CALLS)
15830 mips_annotate_pic_calls ();
15832 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
15833 r10k_insert_cache_barriers ();
15835 df_finish_pass (false);
15838 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
15839 called very late in mips_reorg, but the caller is required to run
15840 mips16_lay_out_constants on the result. */
15843 mips16_load_branch_target (rtx dest, rtx src)
15845 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
15849 if (mips_cfun_has_cprestore_slot_p ())
15850 mips_emit_move (dest, mips_cprestore_slot (dest, true));
15852 mips_emit_move (dest, pic_offset_table_rtx);
15853 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
15854 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
15855 emit_insn (gen_rtx_SET (VOIDmode, dest,
15856 PMODE_INSN (gen_unspec_got, (dest, page))));
15857 emit_insn (gen_rtx_SET (VOIDmode, dest,
15858 gen_rtx_LO_SUM (Pmode, dest, low)));
15862 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
15863 mips_emit_move (dest, src);
15867 /* If we're compiling a MIPS16 function, look for and split any long branches.
15868 This must be called after all other instruction modifications in
15872 mips16_split_long_branches (void)
15874 bool something_changed;
15876 if (!TARGET_MIPS16)
15879 /* Loop until the alignments for all targets are sufficient. */
15884 shorten_branches (get_insns ());
15885 something_changed = false;
15886 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
15888 && USEFUL_INSN_P (insn)
15889 && get_attr_length (insn) > 8
15890 && (any_condjump_p (insn) || any_uncondjump_p (insn)))
15892 rtx old_label, new_label, temp, saved_temp;
15893 rtx target, jump, jump_sequence;
15897 /* Free up a MIPS16 register by saving it in $1. */
15898 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
15899 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
15900 emit_move_insn (saved_temp, temp);
15902 /* Load the branch target into TEMP. */
15903 old_label = JUMP_LABEL (insn);
15904 target = gen_rtx_LABEL_REF (Pmode, old_label);
15905 mips16_load_branch_target (temp, target);
15907 /* Jump to the target and restore the register's
15909 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
15910 (temp, temp, saved_temp)));
15911 JUMP_LABEL (jump) = old_label;
15912 LABEL_NUSES (old_label)++;
15914 /* Rewrite any symbolic references that are supposed to use
15915 a PC-relative constant pool. */
15916 mips16_lay_out_constants (false);
15918 if (simplejump_p (insn))
15919 /* We're going to replace INSN with a longer form. */
15920 new_label = NULL_RTX;
15923 /* Create a branch-around label for the original
15925 new_label = gen_label_rtx ();
15926 emit_label (new_label);
15929 jump_sequence = get_insns ();
15932 emit_insn_after (jump_sequence, insn);
15934 invert_jump (insn, new_label, false);
15936 delete_insn (insn);
15937 something_changed = true;
15940 while (something_changed);
15943 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15948 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15949 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15950 to date if the CFG is available. */
15951 if (mips_cfg_in_reorg ())
15952 compute_bb_for_insn ();
15953 mips16_lay_out_constants (true);
15954 if (mips_cfg_in_reorg ())
15957 free_bb_for_insn ();
15960 if (optimize > 0 && flag_delayed_branch)
15962 cleanup_barriers ();
15963 dbr_schedule (get_insns ());
15965 mips_reorg_process_insns ();
15967 && TARGET_EXPLICIT_RELOCS
15969 && TARGET_VR4130_ALIGN)
15970 vr4130_align_insns ();
15971 if (mips_expand_ghost_gp_insns ())
15972 /* The expansion could invalidate some of the VR4130 alignment
15973 optimizations, but this should be an extremely rare case anyhow. */
15974 mips_reorg_process_insns ();
15975 mips16_split_long_branches ();
15978 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15979 in order to avoid duplicating too much logic from elsewhere. */
15982 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15983 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15986 rtx this_rtx, temp1, temp2, insn, fnaddr;
15987 bool use_sibcall_p;
15989 /* Pretend to be a post-reload pass while generating rtl. */
15990 reload_completed = 1;
15992 /* Mark the end of the (empty) prologue. */
15993 emit_note (NOTE_INSN_PROLOGUE_END);
15995 /* Determine if we can use a sibcall to call FUNCTION directly. */
15996 fnaddr = XEXP (DECL_RTL (function), 0);
15997 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
15998 && const_call_insn_operand (fnaddr, Pmode));
16000 /* Determine if we need to load FNADDR from the GOT. */
16002 && (mips_got_symbol_type_p
16003 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
16005 /* Pick a global pointer. Use a call-clobbered register if
16006 TARGET_CALL_SAVED_GP. */
16007 cfun->machine->global_pointer
16008 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
16009 cfun->machine->must_initialize_gp_p = true;
16010 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
16012 /* Set up the global pointer for n32 or n64 abicalls. */
16013 mips_emit_loadgp ();
16016 /* We need two temporary registers in some cases. */
16017 temp1 = gen_rtx_REG (Pmode, 2);
16018 temp2 = gen_rtx_REG (Pmode, 3);
16020 /* Find out which register contains the "this" pointer. */
16021 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16022 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
16024 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
16026 /* Add DELTA to THIS_RTX. */
16029 rtx offset = GEN_INT (delta);
16030 if (!SMALL_OPERAND (delta))
16032 mips_emit_move (temp1, offset);
16035 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
16038 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16039 if (vcall_offset != 0)
16043 /* Set TEMP1 to *THIS_RTX. */
16044 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
16046 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16047 addr = mips_add_offset (temp2, temp1, vcall_offset);
16049 /* Load the offset and add it to THIS_RTX. */
16050 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
16051 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
16054 /* Jump to the target function. Use a sibcall if direct jumps are
16055 allowed, otherwise load the address into a register first. */
16058 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
16059 SIBLING_CALL_P (insn) = 1;
16063 /* This is messy. GAS treats "la $25,foo" as part of a call
16064 sequence and may allow a global "foo" to be lazily bound.
16065 The general move patterns therefore reject this combination.
16067 In this context, lazy binding would actually be OK
16068 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16069 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16070 We must therefore load the address via a temporary
16071 register if mips_dangerous_for_la25_p.
16073 If we jump to the temporary register rather than $25,
16074 the assembler can use the move insn to fill the jump's
16077 We can use the same technique for MIPS16 code, where $25
16078 is not a valid JR register. */
16079 if (TARGET_USE_PIC_FN_ADDR_REG
16081 && !mips_dangerous_for_la25_p (fnaddr))
16082 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
16083 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
16085 if (TARGET_USE_PIC_FN_ADDR_REG
16086 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
16087 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
16088 emit_jump_insn (gen_indirect_jump (temp1));
16091 /* Run just enough of rest_of_compilation. This sequence was
16092 "borrowed" from alpha.c. */
16093 insn = get_insns ();
16094 split_all_insns_noflow ();
16095 mips16_lay_out_constants (true);
16096 shorten_branches (insn);
16097 final_start_function (insn, file, 1);
16098 final (insn, file, 1);
16099 final_end_function ();
16101 /* Clean up the vars set above. Note that final_end_function resets
16102 the global pointer for us. */
16103 reload_completed = 0;
16106 /* The last argument passed to mips_set_mips16_mode, or negative if the
16107 function hasn't been called yet. */
16108 static int was_mips16_p = -1;
16110 /* Set up the target-dependent global state so that it matches the
16111 current function's ISA mode. */
16114 mips_set_mips16_mode (int mips16_p)
16116 if (mips16_p == was_mips16_p)
16119 /* Restore base settings of various flags. */
16120 target_flags = mips_base_target_flags;
16121 flag_schedule_insns = mips_base_schedule_insns;
16122 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
16123 flag_move_loop_invariants = mips_base_move_loop_invariants;
16124 align_loops = mips_base_align_loops;
16125 align_jumps = mips_base_align_jumps;
16126 align_functions = mips_base_align_functions;
16130 /* Switch to MIPS16 mode. */
16131 target_flags |= MASK_MIPS16;
16133 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16134 target_flags &= ~MASK_SYNCI;
16136 /* Don't run the scheduler before reload, since it tends to
16137 increase register pressure. */
16138 flag_schedule_insns = 0;
16140 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16141 the whole function to be in a single section. */
16142 flag_reorder_blocks_and_partition = 0;
16144 /* Don't move loop invariants, because it tends to increase
16145 register pressure. It also introduces an extra move in cases
16146 where the constant is the first operand in a two-operand binary
16147 instruction, or when it forms a register argument to a functon
16149 flag_move_loop_invariants = 0;
16151 target_flags |= MASK_EXPLICIT_RELOCS;
16153 /* Experiments suggest we get the best overall section-anchor
16154 results from using the range of an unextended LW or SW. Code
16155 that makes heavy use of byte or short accesses can do better
16156 with ranges of 0...31 and 0...63 respectively, but most code is
16157 sensitive to the range of LW and SW instead. */
16158 targetm.min_anchor_offset = 0;
16159 targetm.max_anchor_offset = 127;
16161 targetm.const_anchor = 0;
16163 /* MIPS16 has no BAL instruction. */
16164 target_flags &= ~MASK_RELAX_PIC_CALLS;
16166 /* The R4000 errata don't apply to any known MIPS16 cores.
16167 It's simpler to make the R4000 fixes and MIPS16 mode
16168 mutually exclusive. */
16169 target_flags &= ~MASK_FIX_R4000;
16171 if (flag_pic && !TARGET_OLDABI)
16172 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16175 sorry ("MIPS16 -mxgot code");
16177 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
16178 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16182 /* Switch to normal (non-MIPS16) mode. */
16183 target_flags &= ~MASK_MIPS16;
16185 /* Provide default values for align_* for 64-bit targets. */
16188 if (align_loops == 0)
16190 if (align_jumps == 0)
16192 if (align_functions == 0)
16193 align_functions = 8;
16196 targetm.min_anchor_offset = -32768;
16197 targetm.max_anchor_offset = 32767;
16199 targetm.const_anchor = 0x8000;
16202 /* (Re)initialize MIPS target internals for new ISA. */
16203 mips_init_relocs ();
16207 if (!mips16_globals)
16208 mips16_globals = save_target_globals ();
16210 restore_target_globals (mips16_globals);
16213 restore_target_globals (&default_target_globals);
16215 was_mips16_p = mips16_p;
16218 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16219 function should use the MIPS16 ISA and switch modes accordingly. */
16222 mips_set_current_function (tree fndecl)
16224 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl));
16227 /* Allocate a chunk of memory for per-function machine-dependent data. */
16229 static struct machine_function *
16230 mips_init_machine_status (void)
16232 return ggc_alloc_cleared_machine_function ();
16235 /* Return the processor associated with the given ISA level, or null
16236 if the ISA isn't valid. */
16238 static const struct mips_cpu_info *
16239 mips_cpu_info_from_isa (int isa)
16243 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16244 if (mips_cpu_info_table[i].isa == isa)
16245 return mips_cpu_info_table + i;
16250 /* Return a mips_cpu_info entry determined by an option valued
16253 static const struct mips_cpu_info *
16254 mips_cpu_info_from_opt (int opt)
16258 case MIPS_ARCH_OPTION_FROM_ABI:
16259 /* 'from-abi' selects the most compatible architecture for the
16260 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16261 ABIs. For the EABIs, we have to decide whether we're using
16262 the 32-bit or 64-bit version. */
16263 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
16264 : ABI_NEEDS_64BIT_REGS ? 3
16265 : (TARGET_64BIT ? 3 : 1));
16267 case MIPS_ARCH_OPTION_NATIVE:
16268 gcc_unreachable ();
16271 return &mips_cpu_info_table[opt];
16275 /* Return a default mips_cpu_info entry, given that no -march= option
16276 was explicitly specified. */
16278 static const struct mips_cpu_info *
16279 mips_default_arch (void)
16281 #if defined (MIPS_CPU_STRING_DEFAULT)
16283 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16284 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
16285 return mips_cpu_info_table + i;
16286 gcc_unreachable ();
16287 #elif defined (MIPS_ISA_DEFAULT)
16288 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
16290 /* 'from-abi' makes a good default: you get whatever the ABI
16292 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
16296 /* Set up globals to generate code for the ISA or processor
16297 described by INFO. */
16300 mips_set_architecture (const struct mips_cpu_info *info)
16304 mips_arch_info = info;
16305 mips_arch = info->cpu;
16306 mips_isa = info->isa;
16310 /* Likewise for tuning. */
16313 mips_set_tune (const struct mips_cpu_info *info)
16317 mips_tune_info = info;
16318 mips_tune = info->cpu;
16322 /* Implement TARGET_OPTION_OVERRIDE. */
16325 mips_option_override (void)
16327 int i, start, regno, mode;
16329 if (global_options_set.x_mips_isa_option)
16330 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
16332 /* Process flags as though we were generating non-MIPS16 code. */
16333 mips_base_mips16 = TARGET_MIPS16;
16334 target_flags &= ~MASK_MIPS16;
16336 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16337 SUBTARGET_OVERRIDE_OPTIONS;
16340 /* -mno-float overrides -mhard-float and -msoft-float. */
16341 if (TARGET_NO_FLOAT)
16343 target_flags |= MASK_SOFT_FLOAT_ABI;
16344 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
16347 if (TARGET_FLIP_MIPS16)
16348 TARGET_INTERLINK_MIPS16 = 1;
16350 /* Set the small data limit. */
16351 mips_small_data_threshold = (global_options_set.x_g_switch_value
16353 : MIPS_DEFAULT_GVALUE);
16355 /* The following code determines the architecture and register size.
16356 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16357 The GAS and GCC code should be kept in sync as much as possible. */
16359 if (global_options_set.x_mips_arch_option)
16360 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
16362 if (mips_isa_option_info != 0)
16364 if (mips_arch_info == 0)
16365 mips_set_architecture (mips_isa_option_info);
16366 else if (mips_arch_info->isa != mips_isa_option_info->isa)
16367 error ("%<-%s%> conflicts with the other architecture options, "
16368 "which specify a %s processor",
16369 mips_isa_option_info->name,
16370 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
16373 if (mips_arch_info == 0)
16374 mips_set_architecture (mips_default_arch ());
16376 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
16377 error ("%<-march=%s%> is not compatible with the selected ABI",
16378 mips_arch_info->name);
16380 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16381 if (global_options_set.x_mips_tune_option)
16382 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
16384 if (mips_tune_info == 0)
16385 mips_set_tune (mips_arch_info);
16387 if ((target_flags_explicit & MASK_64BIT) != 0)
16389 /* The user specified the size of the integer registers. Make sure
16390 it agrees with the ABI and ISA. */
16391 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
16392 error ("%<-mgp64%> used with a 32-bit processor");
16393 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
16394 error ("%<-mgp32%> used with a 64-bit ABI");
16395 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
16396 error ("%<-mgp64%> used with a 32-bit ABI");
16400 /* Infer the integer register size from the ABI and processor.
16401 Restrict ourselves to 32-bit registers if that's all the
16402 processor has, or if the ABI cannot handle 64-bit registers. */
16403 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
16404 target_flags &= ~MASK_64BIT;
16406 target_flags |= MASK_64BIT;
16409 if ((target_flags_explicit & MASK_FLOAT64) != 0)
16411 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
16412 error ("unsupported combination: %s", "-mfp64 -msingle-float");
16413 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
16414 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
16415 else if (!TARGET_64BIT && TARGET_FLOAT64)
16417 if (!ISA_HAS_MXHC1)
16418 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
16419 " the target supports the mfhc1 and mthc1 instructions");
16420 else if (mips_abi != ABI_32)
16421 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
16427 /* -msingle-float selects 32-bit float registers. Otherwise the
16428 float registers should be the same size as the integer ones. */
16429 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
16430 target_flags |= MASK_FLOAT64;
16432 target_flags &= ~MASK_FLOAT64;
16435 /* End of code shared with GAS. */
16437 /* If a -mlong* option was given, check that it matches the ABI,
16438 otherwise infer the -mlong* setting from the other options. */
16439 if ((target_flags_explicit & MASK_LONG64) != 0)
16443 if (mips_abi == ABI_N32)
16444 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
16445 else if (mips_abi == ABI_32)
16446 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
16447 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
16448 /* We have traditionally allowed non-abicalls code to use
16449 an LP64 form of o64. However, it would take a bit more
16450 effort to support the combination of 32-bit GOT entries
16451 and 64-bit pointers, so we treat the abicalls case as
16453 error ("the combination of %qs and %qs is incompatible with %qs",
16454 "-mabi=o64", "-mabicalls", "-mlong64");
16458 if (mips_abi == ABI_64)
16459 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
16464 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
16465 target_flags |= MASK_LONG64;
16467 target_flags &= ~MASK_LONG64;
16470 if (!TARGET_OLDABI)
16471 flag_pcc_struct_return = 0;
16473 /* Decide which rtx_costs structure to use. */
16475 mips_cost = &mips_rtx_cost_optimize_size;
16477 mips_cost = &mips_rtx_cost_data[mips_tune];
16479 /* If the user hasn't specified a branch cost, use the processor's
16481 if (mips_branch_cost == 0)
16482 mips_branch_cost = mips_cost->branch_cost;
16484 /* If neither -mbranch-likely nor -mno-branch-likely was given
16485 on the command line, set MASK_BRANCHLIKELY based on the target
16486 architecture and tuning flags. Annulled delay slots are a
16487 size win, so we only consider the processor-specific tuning
16488 for !optimize_size. */
16489 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
16491 if (ISA_HAS_BRANCHLIKELY
16493 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
16494 target_flags |= MASK_BRANCHLIKELY;
16496 target_flags &= ~MASK_BRANCHLIKELY;
16498 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
16499 warning (0, "the %qs architecture does not support branch-likely"
16500 " instructions", mips_arch_info->name);
16502 /* The effect of -mabicalls isn't defined for the EABI. */
16503 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
16505 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
16506 target_flags &= ~MASK_ABICALLS;
16509 /* PIC requires -mabicalls. */
16512 if (mips_abi == ABI_EABI)
16513 error ("cannot generate position-independent code for %qs",
16515 else if (!TARGET_ABICALLS)
16516 error ("position-independent code requires %qs", "-mabicalls");
16519 if (TARGET_ABICALLS_PIC2)
16520 /* We need to set flag_pic for executables as well as DSOs
16521 because we may reference symbols that are not defined in
16522 the final executable. (MIPS does not use things like
16523 copy relocs, for example.)
16525 There is a body of code that uses __PIC__ to distinguish
16526 between -mabicalls and -mno-abicalls code. The non-__PIC__
16527 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
16528 long as any indirect jumps use $25. */
16531 /* -mvr4130-align is a "speed over size" optimization: it usually produces
16532 faster code, but at the expense of more nops. Enable it at -O3 and
16534 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
16535 target_flags |= MASK_VR4130_ALIGN;
16537 /* Prefer a call to memcpy over inline code when optimizing for size,
16538 though see MOVE_RATIO in mips.h. */
16539 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
16540 target_flags |= MASK_MEMCPY;
16542 /* If we have a nonzero small-data limit, check that the -mgpopt
16543 setting is consistent with the other target flags. */
16544 if (mips_small_data_threshold > 0)
16548 if (!TARGET_EXPLICIT_RELOCS)
16549 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
16551 TARGET_LOCAL_SDATA = false;
16552 TARGET_EXTERN_SDATA = false;
16556 if (TARGET_VXWORKS_RTP)
16557 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
16559 if (TARGET_ABICALLS)
16560 warning (0, "cannot use small-data accesses for %qs",
16565 /* Make sure that the user didn't turn off paired single support when
16566 MIPS-3D support is requested. */
16568 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
16569 && !TARGET_PAIRED_SINGLE_FLOAT)
16570 error ("%<-mips3d%> requires %<-mpaired-single%>");
16572 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
16574 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
16576 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
16577 and TARGET_HARD_FLOAT_ABI are both true. */
16578 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
16579 error ("%qs must be used with %qs",
16580 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
16581 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
16583 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
16585 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
16586 warning (0, "the %qs architecture does not support paired-single"
16587 " instructions", mips_arch_info->name);
16589 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
16590 && !TARGET_CACHE_BUILTIN)
16592 error ("%qs requires a target that provides the %qs instruction",
16593 "-mr10k-cache-barrier", "cache");
16594 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
16597 /* If TARGET_DSPR2, enable MASK_DSP. */
16599 target_flags |= MASK_DSP;
16601 /* .eh_frame addresses should be the same width as a C pointer.
16602 Most MIPS ABIs support only one pointer size, so the assembler
16603 will usually know exactly how big an .eh_frame address is.
16605 Unfortunately, this is not true of the 64-bit EABI. The ABI was
16606 originally defined to use 64-bit pointers (i.e. it is LP64), and
16607 this is still the default mode. However, we also support an n32-like
16608 ILP32 mode, which is selected by -mlong32. The problem is that the
16609 assembler has traditionally not had an -mlong option, so it has
16610 traditionally not known whether we're using the ILP32 or LP64 form.
16612 As it happens, gas versions up to and including 2.19 use _32-bit_
16613 addresses for EABI64 .cfi_* directives. This is wrong for the
16614 default LP64 mode, so we can't use the directives by default.
16615 Moreover, since gas's current behavior is at odds with gcc's
16616 default behavior, it seems unwise to rely on future versions
16617 of gas behaving the same way. We therefore avoid using .cfi
16618 directives for -mlong32 as well. */
16619 if (mips_abi == ABI_EABI && TARGET_64BIT)
16620 flag_dwarf2_cfi_asm = 0;
16622 /* .cfi_* directives generate a read-only section, so fall back on
16623 manual .eh_frame creation if we need the section to be writable. */
16624 if (TARGET_WRITABLE_EH_FRAME)
16625 flag_dwarf2_cfi_asm = 0;
16627 mips_init_print_operand_punct ();
16629 /* Set up array to map GCC register number to debug register number.
16630 Ignore the special purpose register numbers. */
16632 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16634 mips_dbx_regno[i] = INVALID_REGNUM;
16635 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
16636 mips_dwarf_regno[i] = i;
16638 mips_dwarf_regno[i] = INVALID_REGNUM;
16641 start = GP_DBX_FIRST - GP_REG_FIRST;
16642 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
16643 mips_dbx_regno[i] = i + start;
16645 start = FP_DBX_FIRST - FP_REG_FIRST;
16646 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
16647 mips_dbx_regno[i] = i + start;
16649 /* Accumulator debug registers use big-endian ordering. */
16650 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
16651 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
16652 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
16653 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
16654 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
16656 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
16657 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
16660 /* Set up mips_hard_regno_mode_ok. */
16661 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
16662 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
16663 mips_hard_regno_mode_ok[mode][regno]
16664 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
16666 /* Function to allocate machine-dependent function status. */
16667 init_machine_status = &mips_init_machine_status;
16669 /* Default to working around R4000 errata only if the processor
16670 was selected explicitly. */
16671 if ((target_flags_explicit & MASK_FIX_R4000) == 0
16672 && strcmp (mips_arch_info->name, "r4000") == 0)
16673 target_flags |= MASK_FIX_R4000;
16675 /* Default to working around R4400 errata only if the processor
16676 was selected explicitly. */
16677 if ((target_flags_explicit & MASK_FIX_R4400) == 0
16678 && strcmp (mips_arch_info->name, "r4400") == 0)
16679 target_flags |= MASK_FIX_R4400;
16681 /* Default to working around R10000 errata only if the processor
16682 was selected explicitly. */
16683 if ((target_flags_explicit & MASK_FIX_R10000) == 0
16684 && strcmp (mips_arch_info->name, "r10000") == 0)
16685 target_flags |= MASK_FIX_R10000;
16687 /* Make sure that branch-likely instructions available when using
16688 -mfix-r10000. The instructions are not available if either:
16690 1. -mno-branch-likely was passed.
16691 2. The selected ISA does not support branch-likely and
16692 the command line does not include -mbranch-likely. */
16693 if (TARGET_FIX_R10000
16694 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
16695 ? !ISA_HAS_BRANCHLIKELY
16696 : !TARGET_BRANCHLIKELY))
16697 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
16699 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
16701 warning (0, "the %qs architecture does not support the synci "
16702 "instruction", mips_arch_info->name);
16703 target_flags &= ~MASK_SYNCI;
16706 /* Only optimize PIC indirect calls if they are actually required. */
16707 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
16708 target_flags &= ~MASK_RELAX_PIC_CALLS;
16710 /* Save base state of options. */
16711 mips_base_target_flags = target_flags;
16712 mips_base_schedule_insns = flag_schedule_insns;
16713 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
16714 mips_base_move_loop_invariants = flag_move_loop_invariants;
16715 mips_base_align_loops = align_loops;
16716 mips_base_align_jumps = align_jumps;
16717 mips_base_align_functions = align_functions;
16719 /* Now select the ISA mode.
16721 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
16722 MIPS16 mode afterwards if need be. */
16723 mips_set_mips16_mode (false);
16726 /* Swap the register information for registers I and I + 1, which
16727 currently have the wrong endianness. Note that the registers'
16728 fixedness and call-clobberedness might have been set on the
16732 mips_swap_registers (unsigned int i)
16737 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
16738 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
16740 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
16741 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
16742 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
16743 SWAP_STRING (reg_names[i], reg_names[i + 1]);
16749 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
16752 mips_conditional_register_usage (void)
16757 /* These DSP control register fields are global. */
16758 global_regs[CCDSP_PO_REGNUM] = 1;
16759 global_regs[CCDSP_SC_REGNUM] = 1;
16762 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16763 reg_class_contents[(int) DSP_ACC_REGS]);
16765 if (!TARGET_HARD_FLOAT)
16767 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16768 reg_class_contents[(int) FP_REGS]);
16769 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16770 reg_class_contents[(int) ST_REGS]);
16772 else if (!ISA_HAS_8CC)
16774 /* We only have a single condition-code register. We implement
16775 this by fixing all the condition-code registers and generating
16776 RTL that refers directly to ST_REG_FIRST. */
16777 AND_COMPL_HARD_REG_SET (accessible_reg_set,
16778 reg_class_contents[(int) ST_REGS]);
16779 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
16780 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
16784 /* In MIPS16 mode, we permit the $t temporary registers to be used
16785 for reload. We prohibit the unused $s registers, since they
16786 are call-saved, and saving them via a MIPS16 register would
16787 probably waste more time than just reloading the value. */
16788 fixed_regs[18] = call_used_regs[18] = 1;
16789 fixed_regs[19] = call_used_regs[19] = 1;
16790 fixed_regs[20] = call_used_regs[20] = 1;
16791 fixed_regs[21] = call_used_regs[21] = 1;
16792 fixed_regs[22] = call_used_regs[22] = 1;
16793 fixed_regs[23] = call_used_regs[23] = 1;
16794 fixed_regs[26] = call_used_regs[26] = 1;
16795 fixed_regs[27] = call_used_regs[27] = 1;
16796 fixed_regs[30] = call_used_regs[30] = 1;
16798 /* Do not allow HI and LO to be treated as register operands.
16799 There are no MTHI or MTLO instructions (or any real need
16800 for them) and one-way registers cannot easily be reloaded. */
16801 AND_COMPL_HARD_REG_SET (operand_reg_set,
16802 reg_class_contents[(int) MD_REGS]);
16804 /* $f20-$f23 are call-clobbered for n64. */
16805 if (mips_abi == ABI_64)
16808 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
16809 call_really_used_regs[regno] = call_used_regs[regno] = 1;
16811 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
16813 if (mips_abi == ABI_N32)
16816 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
16817 call_really_used_regs[regno] = call_used_regs[regno] = 1;
16819 /* Make sure that double-register accumulator values are correctly
16820 ordered for the current endianness. */
16821 if (TARGET_LITTLE_ENDIAN)
16823 unsigned int regno;
16825 mips_swap_registers (MD_REG_FIRST);
16826 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
16827 mips_swap_registers (regno);
16831 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16832 other registers for instructions for which it is possible. This
16833 encourages the compiler to use CMP in cases where an XOR would
16834 require some register shuffling. */
16837 mips_order_regs_for_local_alloc (void)
16841 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
16842 reg_alloc_order[i] = i;
16846 /* It really doesn't matter where we put register 0, since it is
16847 a fixed register anyhow. */
16848 reg_alloc_order[0] = 24;
16849 reg_alloc_order[24] = 0;
16853 /* Implement EH_USES. */
16856 mips_eh_uses (unsigned int regno)
16858 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
16860 /* We need to force certain registers to be live in order to handle
16861 PIC long branches correctly. See mips_must_initialize_gp_p for
16863 if (mips_cfun_has_cprestore_slot_p ())
16865 if (regno == CPRESTORE_SLOT_REGNUM)
16870 if (cfun->machine->global_pointer == regno)
16878 /* Implement EPILOGUE_USES. */
16881 mips_epilogue_uses (unsigned int regno)
16883 /* Say that the epilogue uses the return address register. Note that
16884 in the case of sibcalls, the values "used by the epilogue" are
16885 considered live at the start of the called function. */
16886 if (regno == RETURN_ADDR_REGNUM)
16889 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16890 See the comment above load_call<mode> for details. */
16891 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
16894 /* An interrupt handler must preserve some registers that are
16895 ordinarily call-clobbered. */
16896 if (cfun->machine->interrupt_handler_p
16897 && mips_interrupt_extra_call_saved_reg_p (regno))
16903 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16906 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
16908 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
16911 /* Return true if INSN needs to be wrapped in ".set noat".
16912 INSN has NOPERANDS operands, stored in OPVEC. */
16915 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
16919 if (recog_memoized (insn) >= 0)
16920 for (i = 0; i < noperands; i++)
16921 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
16926 /* Implement FINAL_PRESCAN_INSN. */
16929 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
16931 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16932 mips_push_asm_switch (&mips_noat);
16935 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16938 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
16939 rtx *opvec, int noperands)
16941 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
16942 mips_pop_asm_switch (&mips_noat);
16945 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16946 EXT_CODE is the code of the extension used. Return NULL if widening
16947 multiplication shouldn't be used. */
16950 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
16954 signed_p = ext_code == SIGN_EXTEND;
16957 /* Don't use widening multiplication with MULT when we have DMUL. Even
16958 with the extension of its input operands DMUL is faster. Note that
16959 the extension is not needed for signed multiplication. In order to
16960 ensure that we always remove the redundant sign-extension in this
16961 case we still expand mulsidi3 for DMUL. */
16963 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
16966 ? gen_mulsidi3_64bit_mips16
16967 : gen_umulsidi3_64bit_mips16);
16968 if (TARGET_FIX_R4000)
16970 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
16976 ? gen_mulsidi3_32bit_mips16
16977 : gen_umulsidi3_32bit_mips16);
16978 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
16979 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
16980 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
16984 /* Return the size in bytes of the trampoline code, padded to
16985 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16986 function address immediately follow. */
16989 mips_trampoline_code_size (void)
16991 if (TARGET_USE_PIC_FN_ADDR_REG)
16993 else if (ptr_mode == DImode)
16995 else if (ISA_HAS_LOAD_DELAY)
17001 /* Implement TARGET_TRAMPOLINE_INIT. */
17004 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
17006 rtx addr, end_addr, high, low, opcode, mem;
17009 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
17011 /* Work out the offsets of the pointers from the start of the
17012 trampoline code. */
17013 end_addr_offset = mips_trampoline_code_size ();
17014 static_chain_offset = end_addr_offset;
17015 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
17017 /* Get pointers to the beginning and end of the code block. */
17018 addr = force_reg (Pmode, XEXP (m_tramp, 0));
17019 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
17021 #define OP(X) gen_int_mode (X, SImode)
17023 /* Build up the code in TRAMPOLINE. */
17025 if (TARGET_USE_PIC_FN_ADDR_REG)
17027 /* $25 contains the address of the trampoline. Emit code of the form:
17029 l[wd] $1, target_function_offset($25)
17030 l[wd] $static_chain, static_chain_offset($25)
17033 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
17034 target_function_offset,
17035 PIC_FUNCTION_ADDR_REGNUM));
17036 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17037 static_chain_offset,
17038 PIC_FUNCTION_ADDR_REGNUM));
17039 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
17040 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
17042 else if (ptr_mode == DImode)
17044 /* It's too cumbersome to create the full 64-bit address, so let's
17050 1: l[wd] $25, target_function_offset - 12($31)
17051 l[wd] $static_chain, static_chain_offset - 12($31)
17055 where 12 is the offset of "1:" from the start of the code block. */
17056 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
17057 trampoline[i++] = OP (MIPS_BAL (1));
17058 trampoline[i++] = OP (MIPS_NOP);
17059 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17060 target_function_offset - 12,
17061 RETURN_ADDR_REGNUM));
17062 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17063 static_chain_offset - 12,
17064 RETURN_ADDR_REGNUM));
17065 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17066 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
17070 /* If the target has load delays, emit:
17072 lui $1, %hi(end_addr)
17073 lw $25, %lo(end_addr + ...)($1)
17074 lw $static_chain, %lo(end_addr + ...)($1)
17080 lui $1, %hi(end_addr)
17081 lw $25, %lo(end_addr + ...)($1)
17083 lw $static_chain, %lo(end_addr + ...)($1). */
17085 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
17086 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
17087 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
17088 NULL, false, OPTAB_WIDEN);
17089 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
17090 NULL, false, OPTAB_WIDEN);
17091 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
17093 /* Emit the LUI. */
17094 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
17095 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
17096 NULL, false, OPTAB_WIDEN);
17098 /* Emit the load of the target function. */
17099 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17100 target_function_offset - end_addr_offset,
17102 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
17103 NULL, false, OPTAB_WIDEN);
17105 /* Emit the JR here, if we can. */
17106 if (!ISA_HAS_LOAD_DELAY)
17107 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17109 /* Emit the load of the static chain register. */
17110 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17111 static_chain_offset - end_addr_offset,
17113 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
17114 NULL, false, OPTAB_WIDEN);
17116 /* Emit the JR, if we couldn't above. */
17117 if (ISA_HAS_LOAD_DELAY)
17119 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17120 trampoline[i++] = OP (MIPS_NOP);
17126 /* Copy the trampoline code. Leave any padding uninitialized. */
17127 for (j = 0; j < i; j++)
17129 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
17130 mips_emit_move (mem, trampoline[j]);
17133 /* Set up the static chain pointer field. */
17134 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
17135 mips_emit_move (mem, chain_value);
17137 /* Set up the target function field. */
17138 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
17139 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
17141 /* Flush the code part of the trampoline. */
17142 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
17143 emit_insn (gen_clear_cache (addr, end_addr));
17146 /* Implement FUNCTION_PROFILER. */
17148 void mips_function_profiler (FILE *file)
17151 sorry ("mips16 function profiling");
17152 if (TARGET_LONG_CALLS)
17154 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
17155 if (Pmode == DImode)
17156 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
17158 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
17160 mips_push_asm_switch (&mips_noat);
17161 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
17162 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
17163 /* _mcount treats $2 as the static chain register. */
17164 if (cfun->static_chain_decl != NULL)
17165 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
17166 reg_names[STATIC_CHAIN_REGNUM]);
17167 if (TARGET_MCOUNT_RA_ADDRESS)
17169 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
17170 ra save location. */
17171 if (cfun->machine->frame.ra_fp_offset == 0)
17172 /* ra not saved, pass zero. */
17173 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
17175 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
17176 Pmode == DImode ? "dla" : "la", reg_names[12],
17177 cfun->machine->frame.ra_fp_offset,
17178 reg_names[STACK_POINTER_REGNUM]);
17180 if (!TARGET_NEWABI)
17182 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
17183 TARGET_64BIT ? "dsubu" : "subu",
17184 reg_names[STACK_POINTER_REGNUM],
17185 reg_names[STACK_POINTER_REGNUM],
17186 Pmode == DImode ? 16 : 8);
17188 if (TARGET_LONG_CALLS)
17189 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
17191 fprintf (file, "\tjal\t_mcount\n");
17192 mips_pop_asm_switch (&mips_noat);
17193 /* _mcount treats $2 as the static chain register. */
17194 if (cfun->static_chain_decl != NULL)
17195 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
17199 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
17200 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
17201 when TARGET_LOONGSON_VECTORS is true. */
17203 static unsigned HOST_WIDE_INT
17204 mips_shift_truncation_mask (enum machine_mode mode)
17206 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
17209 return GET_MODE_BITSIZE (mode) - 1;
17212 /* Implement TARGET_PREPARE_PCH_SAVE. */
17215 mips_prepare_pch_save (void)
17217 /* We are called in a context where the current MIPS16 vs. non-MIPS16
17218 setting should be irrelevant. The question then is: which setting
17219 makes most sense at load time?
17221 The PCH is loaded before the first token is read. We should never
17222 have switched into MIPS16 mode by that point, and thus should not
17223 have populated mips16_globals. Nor can we load the entire contents
17224 of mips16_globals from the PCH file, because mips16_globals contains
17225 a combination of GGC and non-GGC data.
17227 There is therefore no point in trying save the GGC part of
17228 mips16_globals to the PCH file, or to preserve MIPS16ness across
17229 the PCH save and load. The loading compiler would not have access
17230 to the non-GGC parts of mips16_globals (either from the PCH file,
17231 or from a copy that the loading compiler generated itself) and would
17232 have to call target_reinit anyway.
17234 It therefore seems best to switch back to non-MIPS16 mode at
17235 save time, and to ensure that mips16_globals remains null after
17237 mips_set_mips16_mode (false);
17238 mips16_globals = 0;
17241 /* Generate or test for an insn that supports a constant permutation. */
17243 #define MAX_VECT_LEN 8
17245 struct expand_vec_perm_d
17247 rtx target, op0, op1;
17248 unsigned char perm[MAX_VECT_LEN];
17249 enum machine_mode vmode;
17250 unsigned char nelt;
17255 /* Construct (set target (vec_select op0 (parallel perm))) and
17256 return true if that's a valid instruction in the active ISA. */
17259 mips_expand_vselect (rtx target, rtx op0,
17260 const unsigned char *perm, unsigned nelt)
17262 rtx rperm[MAX_VECT_LEN], x;
17265 for (i = 0; i < nelt; ++i)
17266 rperm[i] = GEN_INT (perm[i]);
17268 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
17269 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
17270 x = gen_rtx_SET (VOIDmode, target, x);
17273 if (recog_memoized (x) < 0)
17281 /* Similar, but generate a vec_concat from op0 and op1 as well. */
17284 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
17285 const unsigned char *perm, unsigned nelt)
17287 enum machine_mode v2mode;
17290 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
17291 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
17292 return mips_expand_vselect (target, x, perm, nelt);
17295 /* Recognize patterns for even-odd extraction. */
17298 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
17300 unsigned i, odd, nelt = d->nelt;
17301 rtx t0, t1, t2, t3;
17303 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
17305 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
17312 for (i = 1; i < nelt; ++i)
17313 if (d->perm[i] != i * 2 + odd)
17319 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
17320 t0 = gen_reg_rtx (d->vmode);
17321 t1 = gen_reg_rtx (d->vmode);
17325 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
17326 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
17328 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
17330 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
17334 t2 = gen_reg_rtx (d->vmode);
17335 t3 = gen_reg_rtx (d->vmode);
17336 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
17337 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
17338 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
17339 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
17341 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
17343 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
17347 gcc_unreachable ();
17352 /* Recognize patterns for the Loongson PSHUFH instruction. */
17355 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
17360 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
17362 if (d->vmode != V4HImode)
17367 /* Convert the selector into the packed 8-bit form for pshufh. */
17368 /* Recall that loongson is little-endian only. No big-endian
17369 adjustment required. */
17370 for (i = mask = 0; i < 4; i++)
17371 mask |= (d->perm[i] & 3) << (i * 2);
17372 rmask = force_reg (SImode, GEN_INT (mask));
17374 if (d->one_vector_p)
17375 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
17378 rtx t0, t1, x, merge, rmerge[4];
17380 t0 = gen_reg_rtx (V4HImode);
17381 t1 = gen_reg_rtx (V4HImode);
17382 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
17383 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
17385 for (i = 0; i < 4; ++i)
17386 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
17387 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
17388 merge = force_reg (V4HImode, merge);
17390 x = gen_rtx_AND (V4HImode, merge, t1);
17391 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
17393 x = gen_rtx_NOT (V4HImode, merge);
17394 x = gen_rtx_AND (V4HImode, x, t0);
17395 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
17397 x = gen_rtx_IOR (V4HImode, t0, t1);
17398 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
17404 /* Recognize broadcast patterns for the Loongson. */
17407 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
17412 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
17414 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
17415 if (d->vmode != V8QImode)
17417 if (!d->one_vector_p)
17421 for (i = 1; i < 8; ++i)
17422 if (d->perm[i] != elt)
17428 /* With one interleave we put two of the desired element adjacent. */
17429 t0 = gen_reg_rtx (V8QImode);
17431 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
17433 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
17435 /* Shuffle that one HImode element into all locations. */
17438 t1 = gen_reg_rtx (V4HImode);
17439 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
17440 force_reg (SImode, GEN_INT (elt))));
17442 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
17447 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
17449 unsigned int i, nelt = d->nelt;
17450 unsigned char perm2[MAX_VECT_LEN];
17452 if (d->one_vector_p)
17454 /* Try interleave with alternating operands. */
17455 memcpy (perm2, d->perm, sizeof(perm2));
17456 for (i = 1; i < nelt; i += 2)
17458 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
17463 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
17467 /* Try again with swapped operands. */
17468 for (i = 0; i < nelt; ++i)
17469 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
17470 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
17474 if (mips_expand_vpc_loongson_even_odd (d))
17476 if (mips_expand_vpc_loongson_pshufh (d))
17478 if (mips_expand_vpc_loongson_bcast (d))
17483 /* Expand a vec_perm_const pattern. */
17486 mips_expand_vec_perm_const (rtx operands[4])
17488 struct expand_vec_perm_d d;
17489 int i, nelt, which;
17490 unsigned char orig_perm[MAX_VECT_LEN];
17494 d.target = operands[0];
17495 d.op0 = operands[1];
17496 d.op1 = operands[2];
17499 d.vmode = GET_MODE (d.target);
17500 gcc_assert (VECTOR_MODE_P (d.vmode));
17501 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
17502 d.testing_p = false;
17504 for (i = which = 0; i < nelt; ++i)
17506 rtx e = XVECEXP (sel, 0, i);
17507 int ei = INTVAL (e) & (2 * nelt - 1);
17508 which |= (ei < nelt ? 1 : 2);
17511 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
17519 d.one_vector_p = false;
17520 if (!rtx_equal_p (d.op0, d.op1))
17525 for (i = 0; i < nelt; ++i)
17526 d.perm[i] &= nelt - 1;
17528 d.one_vector_p = true;
17533 d.one_vector_p = true;
17537 ok = mips_expand_vec_perm_const_1 (&d);
17539 /* If we were given a two-vector permutation which just happened to
17540 have both input vectors equal, we folded this into a one-vector
17541 permutation. There are several loongson patterns that are matched
17542 via direct vec_select+vec_concat expansion, but we do not have
17543 support in mips_expand_vec_perm_const_1 to guess the adjustment
17544 that should be made for a single operand. Just try again with
17545 the original permutation. */
17546 if (!ok && which == 3)
17548 d.op0 = operands[1];
17549 d.op1 = operands[2];
17550 d.one_vector_p = false;
17551 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
17552 ok = mips_expand_vec_perm_const_1 (&d);
17558 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
17561 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
17562 const unsigned char *sel)
17564 struct expand_vec_perm_d d;
17565 unsigned int i, nelt, which;
17569 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
17570 d.testing_p = true;
17571 memcpy (d.perm, sel, nelt);
17573 /* Categorize the set of elements in the selector. */
17574 for (i = which = 0; i < nelt; ++i)
17576 unsigned char e = d.perm[i];
17577 gcc_assert (e < 2 * nelt);
17578 which |= (e < nelt ? 1 : 2);
17581 /* For all elements from second vector, fold the elements to first. */
17583 for (i = 0; i < nelt; ++i)
17586 /* Check whether the mask can be applied to the vector type. */
17587 d.one_vector_p = (which != 3);
17589 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
17590 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
17591 if (!d.one_vector_p)
17592 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
17595 ret = mips_expand_vec_perm_const_1 (&d);
17601 /* Expand an integral vector unpack operation. */
17604 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
17606 enum machine_mode imode = GET_MODE (operands[1]);
17607 rtx (*unpack) (rtx, rtx, rtx);
17608 rtx (*cmpgt) (rtx, rtx, rtx);
17609 rtx tmp, dest, zero;
17615 unpack = gen_loongson_punpckhbh;
17617 unpack = gen_loongson_punpcklbh;
17618 cmpgt = gen_loongson_pcmpgtb;
17622 unpack = gen_loongson_punpckhhw;
17624 unpack = gen_loongson_punpcklhw;
17625 cmpgt = gen_loongson_pcmpgth;
17628 gcc_unreachable ();
17631 zero = force_reg (imode, CONST0_RTX (imode));
17636 tmp = gen_reg_rtx (imode);
17637 emit_insn (cmpgt (tmp, zero, operands[1]));
17640 dest = gen_reg_rtx (imode);
17641 emit_insn (unpack (dest, operands[1], tmp));
17643 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
17646 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
17649 mips_constant_elt_p (rtx x)
17651 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
17654 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
17657 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
17659 struct expand_vec_perm_d d;
17663 if (elt != const0_rtx)
17664 elt = force_reg (GET_MODE_INNER (vmode), elt);
17666 elt = gen_lowpart (DImode, elt);
17668 t1 = gen_reg_rtx (vmode);
17672 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
17675 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
17678 gcc_unreachable ();
17681 memset (&d, 0, sizeof (d));
17686 d.nelt = GET_MODE_NUNITS (vmode);
17687 d.one_vector_p = true;
17689 ok = mips_expand_vec_perm_const_1 (&d);
17693 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
17694 elements of VALS with zeros, copy the constant vector to TARGET. */
17697 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
17698 rtx target, rtx vals)
17700 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
17703 for (i = 0; i < nelt; ++i)
17705 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
17706 RTVEC_ELT (vec, i) = const0_rtx;
17709 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
17713 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
17716 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
17718 mips_expand_vi_constant (V4HImode, 4, target, vals);
17720 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
17721 GEN_INT (one_var)));
17724 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
17727 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
17728 unsigned nelt, unsigned nvar, rtx target, rtx vals)
17730 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
17731 unsigned int i, isize = GET_MODE_SIZE (imode);
17734 mips_expand_vi_constant (vmode, nelt, mem, vals);
17736 for (i = 0; i < nelt; ++i)
17738 rtx x = XVECEXP (vals, 0, i);
17739 if (!mips_constant_elt_p (x))
17740 emit_move_insn (adjust_address (mem, imode, i * isize), x);
17743 emit_move_insn (target, mem);
17746 /* Expand a vector initialization. */
17749 mips_expand_vector_init (rtx target, rtx vals)
17751 enum machine_mode vmode = GET_MODE (target);
17752 enum machine_mode imode = GET_MODE_INNER (vmode);
17753 unsigned i, nelt = GET_MODE_NUNITS (vmode);
17754 unsigned nvar = 0, one_var = -1u;
17755 bool all_same = true;
17758 for (i = 0; i < nelt; ++i)
17760 x = XVECEXP (vals, 0, i);
17761 if (!mips_constant_elt_p (x))
17762 nvar++, one_var = i;
17763 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
17767 /* Load constants from the pool, or whatever's handy. */
17770 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
17774 /* For two-part initialization, always use CONCAT. */
17777 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
17778 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
17779 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
17780 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17784 /* Loongson is the only cpu with vectors with more elements. */
17785 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
17787 /* If all values are identical, broadcast the value. */
17790 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
17794 /* If we've only got one non-variable V4HImode, use PINSRH. */
17795 if (nvar == 1 && vmode == V4HImode)
17797 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
17801 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
17804 /* Expand a vector reduction. */
17807 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
17809 enum machine_mode vmode = GET_MODE (in);
17810 unsigned char perm2[2];
17811 rtx last, next, fold, x;
17815 fold = gen_reg_rtx (vmode);
17819 /* Use PUL/PLU to produce { L, H } op { H, L }.
17820 By reversing the pair order, rather than a pure interleave high,
17821 we avoid erroneous exceptional conditions that we might otherwise
17822 produce from the computation of H op H. */
17825 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
17830 /* Use interleave to produce { H, L } op { H, H }. */
17831 emit_insn (gen_loongson_punpckhwd (fold, last, last));
17835 /* Perform the first reduction with interleave,
17836 and subsequent reductions with shifts. */
17837 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
17839 next = gen_reg_rtx (vmode);
17840 emit_insn (gen (next, last, fold));
17843 fold = gen_reg_rtx (vmode);
17844 x = force_reg (SImode, GEN_INT (16));
17845 emit_insn (gen_vec_shr_v4hi (fold, last, x));
17849 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
17851 next = gen_reg_rtx (vmode);
17852 emit_insn (gen (next, last, fold));
17855 fold = gen_reg_rtx (vmode);
17856 x = force_reg (SImode, GEN_INT (16));
17857 emit_insn (gen_vec_shr_v8qi (fold, last, x));
17859 next = gen_reg_rtx (vmode);
17860 emit_insn (gen (next, last, fold));
17863 fold = gen_reg_rtx (vmode);
17864 x = force_reg (SImode, GEN_INT (8));
17865 emit_insn (gen_vec_shr_v8qi (fold, last, x));
17869 gcc_unreachable ();
17872 emit_insn (gen (target, last, fold));
17875 /* Expand a vector minimum/maximum. */
17878 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
17879 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
17881 enum machine_mode vmode = GET_MODE (target);
17884 tc = gen_reg_rtx (vmode);
17885 t0 = gen_reg_rtx (vmode);
17886 t1 = gen_reg_rtx (vmode);
17889 emit_insn (cmp (tc, op0, op1));
17891 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
17892 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
17894 x = gen_rtx_NOT (vmode, tc);
17895 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
17896 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
17898 x = gen_rtx_IOR (vmode, t0, t1);
17899 emit_insn (gen_rtx_SET (VOIDmode, target, x));
17902 /* Initialize the GCC target structure. */
17903 #undef TARGET_ASM_ALIGNED_HI_OP
17904 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
17905 #undef TARGET_ASM_ALIGNED_SI_OP
17906 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
17907 #undef TARGET_ASM_ALIGNED_DI_OP
17908 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
17910 #undef TARGET_OPTION_OVERRIDE
17911 #define TARGET_OPTION_OVERRIDE mips_option_override
17913 #undef TARGET_LEGITIMIZE_ADDRESS
17914 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
17916 #undef TARGET_ASM_FUNCTION_PROLOGUE
17917 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
17918 #undef TARGET_ASM_FUNCTION_EPILOGUE
17919 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
17920 #undef TARGET_ASM_SELECT_RTX_SECTION
17921 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
17922 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
17923 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
17925 #undef TARGET_SCHED_INIT
17926 #define TARGET_SCHED_INIT mips_sched_init
17927 #undef TARGET_SCHED_REORDER
17928 #define TARGET_SCHED_REORDER mips_sched_reorder
17929 #undef TARGET_SCHED_REORDER2
17930 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
17931 #undef TARGET_SCHED_VARIABLE_ISSUE
17932 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
17933 #undef TARGET_SCHED_ADJUST_COST
17934 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
17935 #undef TARGET_SCHED_ISSUE_RATE
17936 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
17937 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
17938 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
17939 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
17940 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
17941 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
17942 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
17943 mips_multipass_dfa_lookahead
17944 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
17945 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
17946 mips_small_register_classes_for_mode_p
17948 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
17949 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
17951 #undef TARGET_INSERT_ATTRIBUTES
17952 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
17953 #undef TARGET_MERGE_DECL_ATTRIBUTES
17954 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
17955 #undef TARGET_SET_CURRENT_FUNCTION
17956 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
17958 #undef TARGET_VALID_POINTER_MODE
17959 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
17960 #undef TARGET_REGISTER_MOVE_COST
17961 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
17962 #undef TARGET_MEMORY_MOVE_COST
17963 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
17964 #undef TARGET_RTX_COSTS
17965 #define TARGET_RTX_COSTS mips_rtx_costs
17966 #undef TARGET_ADDRESS_COST
17967 #define TARGET_ADDRESS_COST mips_address_cost
17969 #undef TARGET_IN_SMALL_DATA_P
17970 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
17972 #undef TARGET_MACHINE_DEPENDENT_REORG
17973 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
17975 #undef TARGET_PREFERRED_RELOAD_CLASS
17976 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
17978 #undef TARGET_EXPAND_TO_RTL_HOOK
17979 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
17980 #undef TARGET_ASM_FILE_START
17981 #define TARGET_ASM_FILE_START mips_file_start
17982 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
17983 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
17984 #undef TARGET_ASM_CODE_END
17985 #define TARGET_ASM_CODE_END mips_code_end
17987 #undef TARGET_INIT_LIBFUNCS
17988 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
17990 #undef TARGET_BUILD_BUILTIN_VA_LIST
17991 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
17992 #undef TARGET_EXPAND_BUILTIN_VA_START
17993 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
17994 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
17995 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
17997 #undef TARGET_PROMOTE_FUNCTION_MODE
17998 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
17999 #undef TARGET_PROMOTE_PROTOTYPES
18000 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18002 #undef TARGET_FUNCTION_VALUE
18003 #define TARGET_FUNCTION_VALUE mips_function_value
18004 #undef TARGET_LIBCALL_VALUE
18005 #define TARGET_LIBCALL_VALUE mips_libcall_value
18006 #undef TARGET_FUNCTION_VALUE_REGNO_P
18007 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
18008 #undef TARGET_RETURN_IN_MEMORY
18009 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
18010 #undef TARGET_RETURN_IN_MSB
18011 #define TARGET_RETURN_IN_MSB mips_return_in_msb
18013 #undef TARGET_ASM_OUTPUT_MI_THUNK
18014 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
18015 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
18016 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
18018 #undef TARGET_PRINT_OPERAND
18019 #define TARGET_PRINT_OPERAND mips_print_operand
18020 #undef TARGET_PRINT_OPERAND_ADDRESS
18021 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
18022 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
18023 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
18025 #undef TARGET_SETUP_INCOMING_VARARGS
18026 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
18027 #undef TARGET_STRICT_ARGUMENT_NAMING
18028 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
18029 #undef TARGET_MUST_PASS_IN_STACK
18030 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
18031 #undef TARGET_PASS_BY_REFERENCE
18032 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
18033 #undef TARGET_CALLEE_COPIES
18034 #define TARGET_CALLEE_COPIES mips_callee_copies
18035 #undef TARGET_ARG_PARTIAL_BYTES
18036 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
18037 #undef TARGET_FUNCTION_ARG
18038 #define TARGET_FUNCTION_ARG mips_function_arg
18039 #undef TARGET_FUNCTION_ARG_ADVANCE
18040 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
18041 #undef TARGET_FUNCTION_ARG_BOUNDARY
18042 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
18044 #undef TARGET_MODE_REP_EXTENDED
18045 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
18047 #undef TARGET_VECTOR_MODE_SUPPORTED_P
18048 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
18050 #undef TARGET_SCALAR_MODE_SUPPORTED_P
18051 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
18053 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
18054 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
18056 #undef TARGET_INIT_BUILTINS
18057 #define TARGET_INIT_BUILTINS mips_init_builtins
18058 #undef TARGET_BUILTIN_DECL
18059 #define TARGET_BUILTIN_DECL mips_builtin_decl
18060 #undef TARGET_EXPAND_BUILTIN
18061 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
18063 #undef TARGET_HAVE_TLS
18064 #define TARGET_HAVE_TLS HAVE_AS_TLS
18066 #undef TARGET_CANNOT_FORCE_CONST_MEM
18067 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
18069 #undef TARGET_LEGITIMATE_CONSTANT_P
18070 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
18072 #undef TARGET_ENCODE_SECTION_INFO
18073 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
18075 #undef TARGET_ATTRIBUTE_TABLE
18076 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
18077 /* All our function attributes are related to how out-of-line copies should
18078 be compiled or called. They don't in themselves prevent inlining. */
18079 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
18080 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
18082 #undef TARGET_EXTRA_LIVE_ON_ENTRY
18083 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
18085 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
18086 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
18087 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
18088 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
18090 #undef TARGET_COMP_TYPE_ATTRIBUTES
18091 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
18093 #ifdef HAVE_AS_DTPRELWORD
18094 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
18095 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
18097 #undef TARGET_DWARF_REGISTER_SPAN
18098 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
18100 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
18101 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
18103 #undef TARGET_LEGITIMATE_ADDRESS_P
18104 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
18106 #undef TARGET_FRAME_POINTER_REQUIRED
18107 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
18109 #undef TARGET_CAN_ELIMINATE
18110 #define TARGET_CAN_ELIMINATE mips_can_eliminate
18112 #undef TARGET_CONDITIONAL_REGISTER_USAGE
18113 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
18115 #undef TARGET_TRAMPOLINE_INIT
18116 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
18118 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
18119 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
18121 #undef TARGET_SHIFT_TRUNCATION_MASK
18122 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
18124 #undef TARGET_PREPARE_PCH_SAVE
18125 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
18127 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
18128 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
18130 struct gcc_target targetm = TARGET_INITIALIZER;
18132 #include "gt-mips.h"