1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
38 #include "stringpool.h"
39 #include "stor-layout.h"
50 #include "hash-table.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
56 #include "sched-int.h"
57 #include "pointer-set.h"
59 #include "basic-block.h"
60 #include "tree-ssa-alias.h"
61 #include "internal-fn.h"
62 #include "gimple-fold.h"
64 #include "gimple-expr.h"
69 #include "diagnostic.h"
70 #include "target-globals.h"
72 #include "tree-pass.h"
77 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
78 #define UNSPEC_ADDRESS_P(X) \
79 (GET_CODE (X) == UNSPEC \
80 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
81 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
83 /* Extract the symbol or label from UNSPEC wrapper X. */
84 #define UNSPEC_ADDRESS(X) \
87 /* Extract the symbol type from UNSPEC wrapper X. */
88 #define UNSPEC_ADDRESS_TYPE(X) \
89 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
91 /* The maximum distance between the top of the stack frame and the
92 value $sp has when we save and restore registers.
94 The value for normal-mode code must be a SMALL_OPERAND and must
95 preserve the maximum stack alignment. We therefore use a value
96 of 0x7ff0 in this case.
98 microMIPS LWM and SWM support 12-bit offsets (from -0x800 to 0x7ff),
99 so we use a maximum of 0x7f0 for TARGET_MICROMIPS.
101 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
102 up to 0x7f8 bytes and can usually save or restore all the registers
103 that we need to save or restore. (Note that we can only use these
104 instructions for o32, for which the stack alignment is 8 bytes.)
106 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
107 RESTORE are not available. We can then use unextended instructions
108 to save and restore registers, and to allocate and deallocate the top
109 part of the frame. */
110 #define MIPS_MAX_FIRST_STACK_STEP \
111 (!TARGET_COMPRESSION ? 0x7ff0 \
112 : TARGET_MICROMIPS || GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
113 : TARGET_64BIT ? 0x100 : 0x400)
115 /* True if INSN is a mips.md pattern or asm statement. */
116 /* ??? This test exists through the compiler, perhaps it should be
118 #define USEFUL_INSN_P(INSN) \
119 (NONDEBUG_INSN_P (INSN) \
120 && GET_CODE (PATTERN (INSN)) != USE \
121 && GET_CODE (PATTERN (INSN)) != CLOBBER)
123 /* If INSN is a delayed branch sequence, return the first instruction
124 in the sequence, otherwise return INSN itself. */
125 #define SEQ_BEGIN(INSN) \
126 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
127 ? XVECEXP (PATTERN (INSN), 0, 0) \
130 /* Likewise for the last instruction in a delayed branch sequence. */
131 #define SEQ_END(INSN) \
132 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
133 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
136 /* Execute the following loop body with SUBINSN set to each instruction
137 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
138 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
139 for ((SUBINSN) = SEQ_BEGIN (INSN); \
140 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
141 (SUBINSN) = NEXT_INSN (SUBINSN))
143 /* True if bit BIT is set in VALUE. */
144 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
146 /* Return the opcode for a ptr_mode load of the form:
148 l[wd] DEST, OFFSET(BASE). */
149 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
150 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
155 /* Return the opcode to move register SRC into register DEST. */
156 #define MIPS_MOVE(DEST, SRC) \
157 ((TARGET_64BIT ? 0x2d : 0x21) \
161 /* Return the opcode for:
164 #define MIPS_LUI(DEST, VALUE) \
165 ((0xf << 26) | ((DEST) << 16) | (VALUE))
167 /* Return the opcode to jump to register DEST. */
168 #define MIPS_JR(DEST) \
169 (((DEST) << 21) | 0x8)
171 /* Return the opcode for:
173 bal . + (1 + OFFSET) * 4. */
174 #define MIPS_BAL(OFFSET) \
175 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
177 /* Return the usual opcode for a nop. */
180 /* Classifies an address.
183 A natural register + offset address. The register satisfies
184 mips_valid_base_register_p and the offset is a const_arith_operand.
187 A LO_SUM rtx. The first operand is a valid base register and
188 the second operand is a symbolic address.
191 A signed 16-bit constant address.
194 A constant symbolic address. */
195 enum mips_address_type {
202 /* Macros to create an enumeration identifier for a function prototype. */
203 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
204 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
205 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
206 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
208 /* Classifies the prototype of a built-in function. */
209 enum mips_function_type {
210 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
211 #include "config/mips/mips-ftypes.def"
212 #undef DEF_MIPS_FTYPE
216 /* Specifies how a built-in function should be converted into rtl. */
217 enum mips_builtin_type {
218 /* The function corresponds directly to an .md pattern. The return
219 value is mapped to operand 0 and the arguments are mapped to
220 operands 1 and above. */
223 /* The function corresponds directly to an .md pattern. There is no return
224 value and the arguments are mapped to operands 0 and above. */
225 MIPS_BUILTIN_DIRECT_NO_TARGET,
227 /* The function corresponds to a comparison instruction followed by
228 a mips_cond_move_tf_ps pattern. The first two arguments are the
229 values to compare and the second two arguments are the vector
230 operands for the movt.ps or movf.ps instruction (in assembly order). */
234 /* The function corresponds to a V2SF comparison instruction. Operand 0
235 of this instruction is the result of the comparison, which has mode
236 CCV2 or CCV4. The function arguments are mapped to operands 1 and
237 above. The function's return value is an SImode boolean that is
238 true under the following conditions:
240 MIPS_BUILTIN_CMP_ANY: one of the registers is true
241 MIPS_BUILTIN_CMP_ALL: all of the registers are true
242 MIPS_BUILTIN_CMP_LOWER: the first register is true
243 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
244 MIPS_BUILTIN_CMP_ANY,
245 MIPS_BUILTIN_CMP_ALL,
246 MIPS_BUILTIN_CMP_UPPER,
247 MIPS_BUILTIN_CMP_LOWER,
249 /* As above, but the instruction only sets a single $fcc register. */
250 MIPS_BUILTIN_CMP_SINGLE,
252 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
253 MIPS_BUILTIN_BPOSGE32
256 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
257 #define MIPS_FP_CONDITIONS(MACRO) \
275 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
276 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
277 enum mips_fp_condition {
278 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND)
280 #undef DECLARE_MIPS_COND
282 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
283 #define STRINGIFY(X) #X
284 static const char *const mips_fp_conditions[] = {
285 MIPS_FP_CONDITIONS (STRINGIFY)
289 /* A class used to control a comdat-style stub that we output in each
290 translation unit that needs it. */
291 class mips_one_only_stub {
293 virtual ~mips_one_only_stub () {}
295 /* Return the name of the stub. */
296 virtual const char *get_name () = 0;
298 /* Output the body of the function to asm_out_file. */
299 virtual void output_body () = 0;
302 /* Tuning information that is automatically derived from other sources
303 (such as the scheduler). */
305 /* The architecture and tuning settings that this structure describes. */
309 /* True if this structure describes MIPS16 settings. */
312 /* True if the structure has been initialized. */
315 /* True if "MULT $0, $0" is preferable to "MTLO $0; MTHI $0"
316 when optimizing for speed. */
317 bool fast_mult_zero_zero_p;
320 /* Information about a function's frame layout. */
321 struct GTY(()) mips_frame_info {
322 /* The size of the frame in bytes. */
323 HOST_WIDE_INT total_size;
325 /* The number of bytes allocated to variables. */
326 HOST_WIDE_INT var_size;
328 /* The number of bytes allocated to outgoing function arguments. */
329 HOST_WIDE_INT args_size;
331 /* The number of bytes allocated to the .cprestore slot, or 0 if there
333 HOST_WIDE_INT cprestore_size;
335 /* Bit X is set if the function saves or restores GPR X. */
338 /* Likewise FPR X. */
341 /* Likewise doubleword accumulator X ($acX). */
342 unsigned int acc_mask;
344 /* The number of GPRs, FPRs, doubleword accumulators and COP0
348 unsigned int num_acc;
349 unsigned int num_cop0_regs;
351 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
352 save slots from the top of the frame, or zero if no such slots are
354 HOST_WIDE_INT gp_save_offset;
355 HOST_WIDE_INT fp_save_offset;
356 HOST_WIDE_INT acc_save_offset;
357 HOST_WIDE_INT cop0_save_offset;
359 /* Likewise, but giving offsets from the bottom of the frame. */
360 HOST_WIDE_INT gp_sp_offset;
361 HOST_WIDE_INT fp_sp_offset;
362 HOST_WIDE_INT acc_sp_offset;
363 HOST_WIDE_INT cop0_sp_offset;
365 /* Similar, but the value passed to _mcount. */
366 HOST_WIDE_INT ra_fp_offset;
368 /* The offset of arg_pointer_rtx from the bottom of the frame. */
369 HOST_WIDE_INT arg_pointer_offset;
371 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
372 HOST_WIDE_INT hard_frame_pointer_offset;
375 struct GTY(()) machine_function {
376 /* The next floating-point condition-code register to allocate
377 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
378 unsigned int next_fcc;
380 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
381 rtx mips16_gp_pseudo_rtx;
383 /* The number of extra stack bytes taken up by register varargs.
384 This area is allocated by the callee at the very top of the frame. */
387 /* The current frame information, calculated by mips_compute_frame_info. */
388 struct mips_frame_info frame;
390 /* The register to use as the function's global pointer, or INVALID_REGNUM
391 if the function doesn't need one. */
392 unsigned int global_pointer;
394 /* How many instructions it takes to load a label into $AT, or 0 if
395 this property hasn't yet been calculated. */
396 unsigned int load_label_num_insns;
398 /* True if mips_adjust_insn_length should ignore an instruction's
400 bool ignore_hazard_length_p;
402 /* True if the whole function is suitable for .set noreorder and
404 bool all_noreorder_p;
406 /* True if the function has "inflexible" and "flexible" references
407 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
408 and mips_cfun_has_flexible_gp_ref_p for details. */
409 bool has_inflexible_gp_insn_p;
410 bool has_flexible_gp_insn_p;
412 /* True if the function's prologue must load the global pointer
413 value into pic_offset_table_rtx and store the same value in
414 the function's cprestore slot (if any). Even if this value
415 is currently false, we may decide to set it to true later;
416 see mips_must_initialize_gp_p () for details. */
417 bool must_initialize_gp_p;
419 /* True if the current function must restore $gp after any potential
420 clobber. This value is only meaningful during the first post-epilogue
421 split_insns pass; see mips_must_initialize_gp_p () for details. */
422 bool must_restore_gp_when_clobbered_p;
424 /* True if this is an interrupt handler. */
425 bool interrupt_handler_p;
427 /* True if this is an interrupt handler that uses shadow registers. */
428 bool use_shadow_register_set_p;
430 /* True if this is an interrupt handler that should keep interrupts
432 bool keep_interrupts_masked_p;
434 /* True if this is an interrupt handler that should use DERET
436 bool use_debug_exception_return_p;
439 /* Information about a single argument. */
440 struct mips_arg_info {
441 /* True if the argument is passed in a floating-point register, or
442 would have been if we hadn't run out of registers. */
445 /* The number of words passed in registers, rounded up. */
446 unsigned int reg_words;
448 /* For EABI, the offset of the first register from GP_ARG_FIRST or
449 FP_ARG_FIRST. For other ABIs, the offset of the first register from
450 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
451 comment for details).
453 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
455 unsigned int reg_offset;
457 /* The number of words that must be passed on the stack, rounded up. */
458 unsigned int stack_words;
460 /* The offset from the start of the stack overflow area of the argument's
461 first stack word. Only meaningful when STACK_WORDS is nonzero. */
462 unsigned int stack_offset;
465 /* Information about an address described by mips_address_type.
471 REG is the base register and OFFSET is the constant offset.
474 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
475 is the type of symbol it references.
478 SYMBOL_TYPE is the type of symbol that the address references. */
479 struct mips_address_info {
480 enum mips_address_type type;
483 enum mips_symbol_type symbol_type;
486 /* One stage in a constant building sequence. These sequences have
490 A = A CODE[1] VALUE[1]
491 A = A CODE[2] VALUE[2]
494 where A is an accumulator, each CODE[i] is a binary rtl operation
495 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
496 struct mips_integer_op {
498 unsigned HOST_WIDE_INT value;
501 /* The largest number of operations needed to load an integer constant.
502 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
503 When the lowest bit is clear, we can try, but reject a sequence with
504 an extra SLL at the end. */
505 #define MIPS_MAX_INTEGER_OPS 7
507 /* Information about a MIPS16e SAVE or RESTORE instruction. */
508 struct mips16e_save_restore_info {
509 /* The number of argument registers saved by a SAVE instruction.
510 0 for RESTORE instructions. */
513 /* Bit X is set if the instruction saves or restores GPR X. */
516 /* The total number of bytes to allocate. */
520 /* Costs of various operations on the different architectures. */
522 struct mips_rtx_cost_data
524 unsigned short fp_add;
525 unsigned short fp_mult_sf;
526 unsigned short fp_mult_df;
527 unsigned short fp_div_sf;
528 unsigned short fp_div_df;
529 unsigned short int_mult_si;
530 unsigned short int_mult_di;
531 unsigned short int_div_si;
532 unsigned short int_div_di;
533 unsigned short branch_cost;
534 unsigned short memory_latency;
537 /* Global variables for machine-dependent things. */
539 /* The -G setting, or the configuration's default small-data limit if
540 no -G option is given. */
541 static unsigned int mips_small_data_threshold;
543 /* The number of file directives written by mips_output_filename. */
544 int num_source_filenames;
546 /* The name that appeared in the last .file directive written by
547 mips_output_filename, or "" if mips_output_filename hasn't
548 written anything yet. */
549 const char *current_function_file = "";
551 /* Arrays that map GCC register numbers to debugger register numbers. */
552 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
553 int mips_dwarf_regno[FIRST_PSEUDO_REGISTER];
555 /* Information about the current function's epilogue, used only while
558 /* A list of queued REG_CFA_RESTORE notes. */
561 /* The CFA is currently defined as CFA_REG + CFA_OFFSET. */
563 HOST_WIDE_INT cfa_offset;
565 /* The offset of the CFA from the stack pointer while restoring
567 HOST_WIDE_INT cfa_restore_sp_offset;
570 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
571 struct mips_asm_switch mips_noreorder = { "reorder", 0 };
572 struct mips_asm_switch mips_nomacro = { "macro", 0 };
573 struct mips_asm_switch mips_noat = { "at", 0 };
575 /* True if we're writing out a branch-likely instruction rather than a
577 static bool mips_branch_likely;
579 /* The current instruction-set architecture. */
580 enum processor mips_arch;
581 const struct mips_cpu_info *mips_arch_info;
583 /* The processor that we should tune the code for. */
584 enum processor mips_tune;
585 const struct mips_cpu_info *mips_tune_info;
587 /* The ISA level associated with mips_arch. */
590 /* The ISA revision level. This is 0 for MIPS I to V and N for
594 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
595 static const struct mips_cpu_info *mips_isa_option_info;
597 /* Which cost information to use. */
598 static const struct mips_rtx_cost_data *mips_cost;
600 /* The ambient target flags, excluding MASK_MIPS16. */
601 static int mips_base_target_flags;
603 /* The default compression mode. */
604 unsigned int mips_base_compression_flags;
606 /* The ambient values of other global variables. */
607 static int mips_base_schedule_insns; /* flag_schedule_insns */
608 static int mips_base_reorder_blocks_and_partition; /* flag_reorder... */
609 static int mips_base_move_loop_invariants; /* flag_move_loop_invariants */
610 static int mips_base_align_loops; /* align_loops */
611 static int mips_base_align_jumps; /* align_jumps */
612 static int mips_base_align_functions; /* align_functions */
614 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
615 bool mips_hard_regno_mode_ok[(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
617 /* Index C is true if character C is a valid PRINT_OPERAND punctation
619 static bool mips_print_operand_punct[256];
621 static GTY (()) int mips_output_filename_first_time = 1;
623 /* mips_split_p[X] is true if symbols of type X can be split by
624 mips_split_symbol. */
625 bool mips_split_p[NUM_SYMBOL_TYPES];
627 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
628 can be split by mips_split_symbol. */
629 bool mips_split_hi_p[NUM_SYMBOL_TYPES];
631 /* mips_use_pcrel_pool_p[X] is true if symbols of type X should be
632 forced into a PC-relative constant pool. */
633 bool mips_use_pcrel_pool_p[NUM_SYMBOL_TYPES];
635 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
636 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
637 if they are matched by a special .md file pattern. */
638 const char *mips_lo_relocs[NUM_SYMBOL_TYPES];
640 /* Likewise for HIGHs. */
641 const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
643 /* Target state for MIPS16. */
644 struct target_globals *mips16_globals;
646 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
647 and returned from mips_sched_reorder2. */
648 static int cached_can_issue_more;
650 /* The stubs for various MIPS16 support functions, if used. */
651 static mips_one_only_stub *mips16_rdhwr_stub;
652 static mips_one_only_stub *mips16_get_fcsr_stub;
653 static mips_one_only_stub *mips16_set_fcsr_stub;
655 /* Index R is the smallest register class that contains register R. */
656 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
657 LEA_REGS, LEA_REGS, M16_STORE_REGS, V1_REG,
658 M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS, M16_STORE_REGS,
659 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
660 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
661 M16_REGS, M16_STORE_REGS, LEA_REGS, LEA_REGS,
662 LEA_REGS, LEA_REGS, LEA_REGS, LEA_REGS,
663 T_REG, PIC_FN_ADDR_REG, LEA_REGS, LEA_REGS,
664 LEA_REGS, M16_SP_REGS, LEA_REGS, LEA_REGS,
666 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
667 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
668 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
669 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
670 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
671 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
672 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
673 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
674 MD0_REG, MD1_REG, NO_REGS, ST_REGS,
675 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
676 ST_REGS, ST_REGS, ST_REGS, NO_REGS,
677 NO_REGS, FRAME_REGS, FRAME_REGS, NO_REGS,
678 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
679 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
680 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
681 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
682 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
683 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
684 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
685 COP0_REGS, COP0_REGS, COP0_REGS, COP0_REGS,
686 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
687 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
688 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
689 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
690 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
691 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
692 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
693 COP2_REGS, COP2_REGS, COP2_REGS, COP2_REGS,
694 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
695 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
696 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
697 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
698 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
699 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
700 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
701 COP3_REGS, COP3_REGS, COP3_REGS, COP3_REGS,
702 DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS, DSP_ACC_REGS,
703 DSP_ACC_REGS, DSP_ACC_REGS, ALL_REGS, ALL_REGS,
704 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
707 /* The value of TARGET_ATTRIBUTE_TABLE. */
708 static const struct attribute_spec mips_attribute_table[] = {
709 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
711 { "long_call", 0, 0, false, true, true, NULL, false },
712 { "far", 0, 0, false, true, true, NULL, false },
713 { "near", 0, 0, false, true, true, NULL, false },
714 /* We would really like to treat "mips16" and "nomips16" as type
715 attributes, but GCC doesn't provide the hooks we need to support
716 the right conversion rules. As declaration attributes, they affect
717 code generation but don't carry other semantics. */
718 { "mips16", 0, 0, true, false, false, NULL, false },
719 { "nomips16", 0, 0, true, false, false, NULL, false },
720 { "micromips", 0, 0, true, false, false, NULL, false },
721 { "nomicromips", 0, 0, true, false, false, NULL, false },
722 { "nocompression", 0, 0, true, false, false, NULL, false },
723 /* Allow functions to be specified as interrupt handlers */
724 { "interrupt", 0, 0, false, true, true, NULL, false },
725 { "use_shadow_register_set", 0, 0, false, true, true, NULL, false },
726 { "keep_interrupts_masked", 0, 0, false, true, true, NULL, false },
727 { "use_debug_exception_return", 0, 0, false, true, true, NULL, false },
728 { NULL, 0, 0, false, false, false, NULL, false }
731 /* A table describing all the processors GCC knows about; see
732 mips-cpus.def for details. */
733 static const struct mips_cpu_info mips_cpu_info_table[] = {
734 #define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
735 { NAME, CPU, ISA, FLAGS },
736 #include "mips-cpus.def"
740 /* Default costs. If these are used for a processor we should look
741 up the actual costs. */
742 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
743 COSTS_N_INSNS (7), /* fp_mult_sf */ \
744 COSTS_N_INSNS (8), /* fp_mult_df */ \
745 COSTS_N_INSNS (23), /* fp_div_sf */ \
746 COSTS_N_INSNS (36), /* fp_div_df */ \
747 COSTS_N_INSNS (10), /* int_mult_si */ \
748 COSTS_N_INSNS (10), /* int_mult_di */ \
749 COSTS_N_INSNS (69), /* int_div_si */ \
750 COSTS_N_INSNS (69), /* int_div_di */ \
751 2, /* branch_cost */ \
752 4 /* memory_latency */
754 /* Floating-point costs for processors without an FPU. Just assume that
755 all floating-point libcalls are very expensive. */
756 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
757 COSTS_N_INSNS (256), /* fp_mult_sf */ \
758 COSTS_N_INSNS (256), /* fp_mult_df */ \
759 COSTS_N_INSNS (256), /* fp_div_sf */ \
760 COSTS_N_INSNS (256) /* fp_div_df */
762 /* Costs to use when optimizing for size. */
763 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size = {
764 COSTS_N_INSNS (1), /* fp_add */
765 COSTS_N_INSNS (1), /* fp_mult_sf */
766 COSTS_N_INSNS (1), /* fp_mult_df */
767 COSTS_N_INSNS (1), /* fp_div_sf */
768 COSTS_N_INSNS (1), /* fp_div_df */
769 COSTS_N_INSNS (1), /* int_mult_si */
770 COSTS_N_INSNS (1), /* int_mult_di */
771 COSTS_N_INSNS (1), /* int_div_si */
772 COSTS_N_INSNS (1), /* int_div_di */
774 4 /* memory_latency */
777 /* Costs to use when optimizing for speed, indexed by processor. */
778 static const struct mips_rtx_cost_data
779 mips_rtx_cost_data[NUM_PROCESSOR_VALUES] = {
781 COSTS_N_INSNS (2), /* fp_add */
782 COSTS_N_INSNS (4), /* fp_mult_sf */
783 COSTS_N_INSNS (5), /* fp_mult_df */
784 COSTS_N_INSNS (12), /* fp_div_sf */
785 COSTS_N_INSNS (19), /* fp_div_df */
786 COSTS_N_INSNS (12), /* int_mult_si */
787 COSTS_N_INSNS (12), /* int_mult_di */
788 COSTS_N_INSNS (35), /* int_div_si */
789 COSTS_N_INSNS (35), /* int_div_di */
791 4 /* memory_latency */
795 COSTS_N_INSNS (6), /* int_mult_si */
796 COSTS_N_INSNS (6), /* int_mult_di */
797 COSTS_N_INSNS (36), /* int_div_si */
798 COSTS_N_INSNS (36), /* int_div_di */
800 4 /* memory_latency */
804 COSTS_N_INSNS (36), /* int_mult_si */
805 COSTS_N_INSNS (36), /* int_mult_di */
806 COSTS_N_INSNS (37), /* int_div_si */
807 COSTS_N_INSNS (37), /* int_div_di */
809 4 /* memory_latency */
813 COSTS_N_INSNS (4), /* int_mult_si */
814 COSTS_N_INSNS (11), /* int_mult_di */
815 COSTS_N_INSNS (36), /* int_div_si */
816 COSTS_N_INSNS (68), /* int_div_di */
818 4 /* memory_latency */
821 COSTS_N_INSNS (4), /* fp_add */
822 COSTS_N_INSNS (4), /* fp_mult_sf */
823 COSTS_N_INSNS (5), /* fp_mult_df */
824 COSTS_N_INSNS (17), /* fp_div_sf */
825 COSTS_N_INSNS (32), /* fp_div_df */
826 COSTS_N_INSNS (4), /* int_mult_si */
827 COSTS_N_INSNS (11), /* int_mult_di */
828 COSTS_N_INSNS (36), /* int_div_si */
829 COSTS_N_INSNS (68), /* int_div_di */
831 4 /* memory_latency */
834 COSTS_N_INSNS (4), /* fp_add */
835 COSTS_N_INSNS (4), /* fp_mult_sf */
836 COSTS_N_INSNS (5), /* fp_mult_df */
837 COSTS_N_INSNS (17), /* fp_div_sf */
838 COSTS_N_INSNS (32), /* fp_div_df */
839 COSTS_N_INSNS (4), /* int_mult_si */
840 COSTS_N_INSNS (7), /* int_mult_di */
841 COSTS_N_INSNS (42), /* int_div_si */
842 COSTS_N_INSNS (72), /* int_div_di */
844 4 /* memory_latency */
848 COSTS_N_INSNS (5), /* int_mult_si */
849 COSTS_N_INSNS (5), /* int_mult_di */
850 COSTS_N_INSNS (41), /* int_div_si */
851 COSTS_N_INSNS (41), /* int_div_di */
853 4 /* memory_latency */
856 COSTS_N_INSNS (8), /* fp_add */
857 COSTS_N_INSNS (8), /* fp_mult_sf */
858 COSTS_N_INSNS (10), /* fp_mult_df */
859 COSTS_N_INSNS (34), /* fp_div_sf */
860 COSTS_N_INSNS (64), /* fp_div_df */
861 COSTS_N_INSNS (5), /* int_mult_si */
862 COSTS_N_INSNS (5), /* int_mult_di */
863 COSTS_N_INSNS (41), /* int_div_si */
864 COSTS_N_INSNS (41), /* int_div_di */
866 4 /* memory_latency */
869 COSTS_N_INSNS (4), /* fp_add */
870 COSTS_N_INSNS (4), /* fp_mult_sf */
871 COSTS_N_INSNS (5), /* fp_mult_df */
872 COSTS_N_INSNS (17), /* fp_div_sf */
873 COSTS_N_INSNS (32), /* fp_div_df */
874 COSTS_N_INSNS (5), /* int_mult_si */
875 COSTS_N_INSNS (5), /* int_mult_di */
876 COSTS_N_INSNS (41), /* int_div_si */
877 COSTS_N_INSNS (41), /* int_div_di */
879 4 /* memory_latency */
883 COSTS_N_INSNS (5), /* int_mult_si */
884 COSTS_N_INSNS (5), /* int_mult_di */
885 COSTS_N_INSNS (41), /* int_div_si */
886 COSTS_N_INSNS (41), /* int_div_di */
888 4 /* memory_latency */
891 COSTS_N_INSNS (8), /* fp_add */
892 COSTS_N_INSNS (8), /* fp_mult_sf */
893 COSTS_N_INSNS (10), /* fp_mult_df */
894 COSTS_N_INSNS (34), /* fp_div_sf */
895 COSTS_N_INSNS (64), /* fp_div_df */
896 COSTS_N_INSNS (5), /* int_mult_si */
897 COSTS_N_INSNS (5), /* int_mult_di */
898 COSTS_N_INSNS (41), /* int_div_si */
899 COSTS_N_INSNS (41), /* int_div_di */
901 4 /* memory_latency */
904 COSTS_N_INSNS (4), /* fp_add */
905 COSTS_N_INSNS (4), /* fp_mult_sf */
906 COSTS_N_INSNS (5), /* fp_mult_df */
907 COSTS_N_INSNS (17), /* fp_div_sf */
908 COSTS_N_INSNS (32), /* fp_div_df */
909 COSTS_N_INSNS (5), /* int_mult_si */
910 COSTS_N_INSNS (5), /* int_mult_di */
911 COSTS_N_INSNS (41), /* int_div_si */
912 COSTS_N_INSNS (41), /* int_div_di */
914 4 /* memory_latency */
917 COSTS_N_INSNS (6), /* fp_add */
918 COSTS_N_INSNS (6), /* fp_mult_sf */
919 COSTS_N_INSNS (7), /* fp_mult_df */
920 COSTS_N_INSNS (25), /* fp_div_sf */
921 COSTS_N_INSNS (48), /* fp_div_df */
922 COSTS_N_INSNS (5), /* int_mult_si */
923 COSTS_N_INSNS (5), /* int_mult_di */
924 COSTS_N_INSNS (41), /* int_div_si */
925 COSTS_N_INSNS (41), /* int_div_di */
927 4 /* memory_latency */
944 COSTS_N_INSNS (5), /* int_mult_si */
945 COSTS_N_INSNS (5), /* int_mult_di */
946 COSTS_N_INSNS (72), /* int_div_si */
947 COSTS_N_INSNS (72), /* int_div_di */
949 4 /* memory_latency */
954 COSTS_N_INSNS (6), /* int_mult_si */
955 COSTS_N_INSNS (6), /* int_mult_di */
956 COSTS_N_INSNS (18), /* int_div_si */
957 COSTS_N_INSNS (35), /* int_div_di */
959 4 /* memory_latency */
962 COSTS_N_INSNS (2), /* fp_add */
963 COSTS_N_INSNS (4), /* fp_mult_sf */
964 COSTS_N_INSNS (5), /* fp_mult_df */
965 COSTS_N_INSNS (12), /* fp_div_sf */
966 COSTS_N_INSNS (19), /* fp_div_df */
967 COSTS_N_INSNS (2), /* int_mult_si */
968 COSTS_N_INSNS (2), /* int_mult_di */
969 COSTS_N_INSNS (35), /* int_div_si */
970 COSTS_N_INSNS (35), /* int_div_di */
972 4 /* memory_latency */
975 COSTS_N_INSNS (3), /* fp_add */
976 COSTS_N_INSNS (5), /* fp_mult_sf */
977 COSTS_N_INSNS (6), /* fp_mult_df */
978 COSTS_N_INSNS (15), /* fp_div_sf */
979 COSTS_N_INSNS (16), /* fp_div_df */
980 COSTS_N_INSNS (17), /* int_mult_si */
981 COSTS_N_INSNS (17), /* int_mult_di */
982 COSTS_N_INSNS (38), /* int_div_si */
983 COSTS_N_INSNS (38), /* int_div_di */
985 6 /* memory_latency */
988 COSTS_N_INSNS (6), /* fp_add */
989 COSTS_N_INSNS (7), /* fp_mult_sf */
990 COSTS_N_INSNS (8), /* fp_mult_df */
991 COSTS_N_INSNS (23), /* fp_div_sf */
992 COSTS_N_INSNS (36), /* fp_div_df */
993 COSTS_N_INSNS (10), /* int_mult_si */
994 COSTS_N_INSNS (10), /* int_mult_di */
995 COSTS_N_INSNS (69), /* int_div_si */
996 COSTS_N_INSNS (69), /* int_div_di */
998 6 /* memory_latency */
1010 /* The only costs that appear to be updated here are
1011 integer multiplication. */
1013 COSTS_N_INSNS (4), /* int_mult_si */
1014 COSTS_N_INSNS (6), /* int_mult_di */
1015 COSTS_N_INSNS (69), /* int_div_si */
1016 COSTS_N_INSNS (69), /* int_div_di */
1017 1, /* branch_cost */
1018 4 /* memory_latency */
1033 COSTS_N_INSNS (6), /* fp_add */
1034 COSTS_N_INSNS (4), /* fp_mult_sf */
1035 COSTS_N_INSNS (5), /* fp_mult_df */
1036 COSTS_N_INSNS (23), /* fp_div_sf */
1037 COSTS_N_INSNS (36), /* fp_div_df */
1038 COSTS_N_INSNS (5), /* int_mult_si */
1039 COSTS_N_INSNS (5), /* int_mult_di */
1040 COSTS_N_INSNS (36), /* int_div_si */
1041 COSTS_N_INSNS (36), /* int_div_di */
1042 1, /* branch_cost */
1043 4 /* memory_latency */
1046 COSTS_N_INSNS (6), /* fp_add */
1047 COSTS_N_INSNS (5), /* fp_mult_sf */
1048 COSTS_N_INSNS (6), /* fp_mult_df */
1049 COSTS_N_INSNS (30), /* fp_div_sf */
1050 COSTS_N_INSNS (59), /* fp_div_df */
1051 COSTS_N_INSNS (3), /* int_mult_si */
1052 COSTS_N_INSNS (4), /* int_mult_di */
1053 COSTS_N_INSNS (42), /* int_div_si */
1054 COSTS_N_INSNS (74), /* int_div_di */
1055 1, /* branch_cost */
1056 4 /* memory_latency */
1059 COSTS_N_INSNS (6), /* fp_add */
1060 COSTS_N_INSNS (5), /* fp_mult_sf */
1061 COSTS_N_INSNS (6), /* fp_mult_df */
1062 COSTS_N_INSNS (30), /* fp_div_sf */
1063 COSTS_N_INSNS (59), /* fp_div_df */
1064 COSTS_N_INSNS (5), /* int_mult_si */
1065 COSTS_N_INSNS (9), /* int_mult_di */
1066 COSTS_N_INSNS (42), /* int_div_si */
1067 COSTS_N_INSNS (74), /* int_div_di */
1068 1, /* branch_cost */
1069 4 /* memory_latency */
1072 COSTS_N_INSNS (4), /* fp_add */
1073 COSTS_N_INSNS (4), /* fp_mult_sf */
1074 COSTS_N_INSNS (256), /* fp_mult_df */
1075 COSTS_N_INSNS (8), /* fp_div_sf */
1076 COSTS_N_INSNS (256), /* fp_div_df */
1077 COSTS_N_INSNS (4), /* int_mult_si */
1078 COSTS_N_INSNS (256), /* int_mult_di */
1079 COSTS_N_INSNS (37), /* int_div_si */
1080 COSTS_N_INSNS (256), /* int_div_di */
1081 1, /* branch_cost */
1082 4 /* memory_latency */
1085 /* The only costs that are changed here are
1086 integer multiplication. */
1087 COSTS_N_INSNS (6), /* fp_add */
1088 COSTS_N_INSNS (7), /* fp_mult_sf */
1089 COSTS_N_INSNS (8), /* fp_mult_df */
1090 COSTS_N_INSNS (23), /* fp_div_sf */
1091 COSTS_N_INSNS (36), /* fp_div_df */
1092 COSTS_N_INSNS (5), /* int_mult_si */
1093 COSTS_N_INSNS (9), /* int_mult_di */
1094 COSTS_N_INSNS (69), /* int_div_si */
1095 COSTS_N_INSNS (69), /* int_div_di */
1096 1, /* branch_cost */
1097 4 /* memory_latency */
1103 /* The only costs that are changed here are
1104 integer multiplication. */
1105 COSTS_N_INSNS (6), /* fp_add */
1106 COSTS_N_INSNS (7), /* fp_mult_sf */
1107 COSTS_N_INSNS (8), /* fp_mult_df */
1108 COSTS_N_INSNS (23), /* fp_div_sf */
1109 COSTS_N_INSNS (36), /* fp_div_df */
1110 COSTS_N_INSNS (3), /* int_mult_si */
1111 COSTS_N_INSNS (8), /* int_mult_di */
1112 COSTS_N_INSNS (69), /* int_div_si */
1113 COSTS_N_INSNS (69), /* int_div_di */
1114 1, /* branch_cost */
1115 4 /* memory_latency */
1118 COSTS_N_INSNS (2), /* fp_add */
1119 COSTS_N_INSNS (2), /* fp_mult_sf */
1120 COSTS_N_INSNS (2), /* fp_mult_df */
1121 COSTS_N_INSNS (12), /* fp_div_sf */
1122 COSTS_N_INSNS (19), /* fp_div_df */
1123 COSTS_N_INSNS (5), /* int_mult_si */
1124 COSTS_N_INSNS (9), /* int_mult_di */
1125 COSTS_N_INSNS (34), /* int_div_si */
1126 COSTS_N_INSNS (66), /* int_div_di */
1127 1, /* branch_cost */
1128 4 /* memory_latency */
1131 /* These costs are the same as the SB-1A below. */
1132 COSTS_N_INSNS (4), /* fp_add */
1133 COSTS_N_INSNS (4), /* fp_mult_sf */
1134 COSTS_N_INSNS (4), /* fp_mult_df */
1135 COSTS_N_INSNS (24), /* fp_div_sf */
1136 COSTS_N_INSNS (32), /* fp_div_df */
1137 COSTS_N_INSNS (3), /* int_mult_si */
1138 COSTS_N_INSNS (4), /* int_mult_di */
1139 COSTS_N_INSNS (36), /* int_div_si */
1140 COSTS_N_INSNS (68), /* int_div_di */
1141 1, /* branch_cost */
1142 4 /* memory_latency */
1145 /* These costs are the same as the SB-1 above. */
1146 COSTS_N_INSNS (4), /* fp_add */
1147 COSTS_N_INSNS (4), /* fp_mult_sf */
1148 COSTS_N_INSNS (4), /* fp_mult_df */
1149 COSTS_N_INSNS (24), /* fp_div_sf */
1150 COSTS_N_INSNS (32), /* fp_div_df */
1151 COSTS_N_INSNS (3), /* int_mult_si */
1152 COSTS_N_INSNS (4), /* int_mult_di */
1153 COSTS_N_INSNS (36), /* int_div_si */
1154 COSTS_N_INSNS (68), /* int_div_di */
1155 1, /* branch_cost */
1156 4 /* memory_latency */
1163 COSTS_N_INSNS (8), /* int_mult_si */
1164 COSTS_N_INSNS (8), /* int_mult_di */
1165 COSTS_N_INSNS (72), /* int_div_si */
1166 COSTS_N_INSNS (72), /* int_div_di */
1167 1, /* branch_cost */
1168 4 /* memory_latency */
1171 /* These costs are the same as 5KF above. */
1172 COSTS_N_INSNS (4), /* fp_add */
1173 COSTS_N_INSNS (4), /* fp_mult_sf */
1174 COSTS_N_INSNS (5), /* fp_mult_df */
1175 COSTS_N_INSNS (17), /* fp_div_sf */
1176 COSTS_N_INSNS (32), /* fp_div_df */
1177 COSTS_N_INSNS (4), /* int_mult_si */
1178 COSTS_N_INSNS (11), /* int_mult_di */
1179 COSTS_N_INSNS (36), /* int_div_si */
1180 COSTS_N_INSNS (68), /* int_div_di */
1181 1, /* branch_cost */
1182 4 /* memory_latency */
1185 COSTS_N_INSNS (4), /* fp_add */
1186 COSTS_N_INSNS (5), /* fp_mult_sf */
1187 COSTS_N_INSNS (5), /* fp_mult_df */
1188 COSTS_N_INSNS (17), /* fp_div_sf */
1189 COSTS_N_INSNS (17), /* fp_div_df */
1190 COSTS_N_INSNS (5), /* int_mult_si */
1191 COSTS_N_INSNS (5), /* int_mult_di */
1192 COSTS_N_INSNS (8), /* int_div_si */
1193 COSTS_N_INSNS (8), /* int_div_di */
1194 2, /* branch_cost */
1195 10 /* memory_latency */
1199 static rtx mips_find_pic_call_symbol (rtx, rtx, bool);
1200 static int mips_register_move_cost (enum machine_mode, reg_class_t,
1202 static unsigned int mips_function_arg_boundary (enum machine_mode, const_tree);
1204 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1205 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1206 struct GTY (()) mflip_mips16_entry {
1210 static GTY ((param_is (struct mflip_mips16_entry))) htab_t mflip_mips16_htab;
1212 /* Hash table callbacks for mflip_mips16_htab. */
1215 mflip_mips16_htab_hash (const void *entry)
1217 return htab_hash_string (((const struct mflip_mips16_entry *) entry)->name);
1221 mflip_mips16_htab_eq (const void *entry, const void *name)
1223 return strcmp (((const struct mflip_mips16_entry *) entry)->name,
1224 (const char *) name) == 0;
1227 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1228 mode, false if it should next add an attribute for the opposite mode. */
1229 static GTY(()) bool mips16_flipper;
1231 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1232 for -mflip-mips16. Return true if it should use "mips16" and false if
1233 it should use "nomips16". */
1236 mflip_mips16_use_mips16_p (tree decl)
1238 struct mflip_mips16_entry *entry;
1242 bool base_is_mips16 = (mips_base_compression_flags & MASK_MIPS16) != 0;
1244 /* Use the opposite of the command-line setting for anonymous decls. */
1245 if (!DECL_NAME (decl))
1246 return !base_is_mips16;
1248 if (!mflip_mips16_htab)
1249 mflip_mips16_htab = htab_create_ggc (37, mflip_mips16_htab_hash,
1250 mflip_mips16_htab_eq, NULL);
1252 name = IDENTIFIER_POINTER (DECL_NAME (decl));
1253 hash = htab_hash_string (name);
1254 slot = htab_find_slot_with_hash (mflip_mips16_htab, name, hash, INSERT);
1255 entry = (struct mflip_mips16_entry *) *slot;
1258 mips16_flipper = !mips16_flipper;
1259 entry = ggc_alloc<mflip_mips16_entry> ();
1261 entry->mips16_p = mips16_flipper ? !base_is_mips16 : base_is_mips16;
1264 return entry->mips16_p;
1267 /* Predicates to test for presence of "near" and "far"/"long_call"
1268 attributes on the given TYPE. */
1271 mips_near_type_p (const_tree type)
1273 return lookup_attribute ("near", TYPE_ATTRIBUTES (type)) != NULL;
1277 mips_far_type_p (const_tree type)
1279 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type)) != NULL
1280 || lookup_attribute ("far", TYPE_ATTRIBUTES (type)) != NULL);
1284 /* Check if the interrupt attribute is set for a function. */
1287 mips_interrupt_type_p (tree type)
1289 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
1292 /* Check if the attribute to use shadow register set is set for a function. */
1295 mips_use_shadow_register_set_p (tree type)
1297 return lookup_attribute ("use_shadow_register_set",
1298 TYPE_ATTRIBUTES (type)) != NULL;
1301 /* Check if the attribute to keep interrupts masked is set for a function. */
1304 mips_keep_interrupts_masked_p (tree type)
1306 return lookup_attribute ("keep_interrupts_masked",
1307 TYPE_ATTRIBUTES (type)) != NULL;
1310 /* Check if the attribute to use debug exception return is set for
1314 mips_use_debug_exception_return_p (tree type)
1316 return lookup_attribute ("use_debug_exception_return",
1317 TYPE_ATTRIBUTES (type)) != NULL;
1320 /* Return the set of compression modes that are explicitly required
1321 by the attributes in ATTRIBUTES. */
1324 mips_get_compress_on_flags (tree attributes)
1326 unsigned int flags = 0;
1328 if (lookup_attribute ("mips16", attributes) != NULL)
1329 flags |= MASK_MIPS16;
1331 if (lookup_attribute ("micromips", attributes) != NULL)
1332 flags |= MASK_MICROMIPS;
1337 /* Return the set of compression modes that are explicitly forbidden
1338 by the attributes in ATTRIBUTES. */
1341 mips_get_compress_off_flags (tree attributes)
1343 unsigned int flags = 0;
1345 if (lookup_attribute ("nocompression", attributes) != NULL)
1346 flags |= MASK_MIPS16 | MASK_MICROMIPS;
1348 if (lookup_attribute ("nomips16", attributes) != NULL)
1349 flags |= MASK_MIPS16;
1351 if (lookup_attribute ("nomicromips", attributes) != NULL)
1352 flags |= MASK_MICROMIPS;
1357 /* Return the compression mode that should be used for function DECL.
1358 Return the ambient setting if DECL is null. */
1361 mips_get_compress_mode (tree decl)
1363 unsigned int flags, force_on;
1365 flags = mips_base_compression_flags;
1368 /* Nested functions must use the same frame pointer as their
1369 parent and must therefore use the same ISA mode. */
1370 tree parent = decl_function_context (decl);
1373 force_on = mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1376 flags &= ~mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1381 /* Return the attribute name associated with MASK_MIPS16 and MASK_MICROMIPS
1385 mips_get_compress_on_name (unsigned int flags)
1387 if (flags == MASK_MIPS16)
1392 /* Return the attribute name that forbids MASK_MIPS16 and MASK_MICROMIPS
1396 mips_get_compress_off_name (unsigned int flags)
1398 if (flags == MASK_MIPS16)
1400 if (flags == MASK_MICROMIPS)
1401 return "nomicromips";
1402 return "nocompression";
1405 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1408 mips_comp_type_attributes (const_tree type1, const_tree type2)
1410 /* Disallow mixed near/far attributes. */
1411 if (mips_far_type_p (type1) && mips_near_type_p (type2))
1413 if (mips_near_type_p (type1) && mips_far_type_p (type2))
1418 /* Implement TARGET_INSERT_ATTRIBUTES. */
1421 mips_insert_attributes (tree decl, tree *attributes)
1424 unsigned int compression_flags, nocompression_flags;
1426 /* Check for "mips16" and "nomips16" attributes. */
1427 compression_flags = mips_get_compress_on_flags (*attributes);
1428 nocompression_flags = mips_get_compress_off_flags (*attributes);
1430 if (TREE_CODE (decl) != FUNCTION_DECL)
1432 if (nocompression_flags)
1433 error ("%qs attribute only applies to functions",
1434 mips_get_compress_off_name (nocompression_flags));
1436 if (compression_flags)
1437 error ("%qs attribute only applies to functions",
1438 mips_get_compress_on_name (nocompression_flags));
1442 compression_flags |= mips_get_compress_on_flags (DECL_ATTRIBUTES (decl));
1443 nocompression_flags |=
1444 mips_get_compress_off_flags (DECL_ATTRIBUTES (decl));
1446 if (compression_flags && nocompression_flags)
1447 error ("%qE cannot have both %qs and %qs attributes",
1448 DECL_NAME (decl), mips_get_compress_on_name (compression_flags),
1449 mips_get_compress_off_name (nocompression_flags));
1451 if (compression_flags & MASK_MIPS16
1452 && compression_flags & MASK_MICROMIPS)
1453 error ("%qE cannot have both %qs and %qs attributes",
1454 DECL_NAME (decl), "mips16", "micromips");
1456 if (TARGET_FLIP_MIPS16
1457 && !DECL_ARTIFICIAL (decl)
1458 && compression_flags == 0
1459 && nocompression_flags == 0)
1461 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1462 "mips16" attribute, arbitrarily pick one. We must pick the same
1463 setting for duplicate declarations of a function. */
1464 name = mflip_mips16_use_mips16_p (decl) ? "mips16" : "nomips16";
1465 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1466 name = "nomicromips";
1467 *attributes = tree_cons (get_identifier (name), NULL, *attributes);
1472 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1475 mips_merge_decl_attributes (tree olddecl, tree newdecl)
1479 diff = (mips_get_compress_on_flags (DECL_ATTRIBUTES (olddecl))
1480 ^ mips_get_compress_on_flags (DECL_ATTRIBUTES (newdecl)));
1482 error ("%qE redeclared with conflicting %qs attributes",
1483 DECL_NAME (newdecl), mips_get_compress_on_name (diff));
1485 diff = (mips_get_compress_off_flags (DECL_ATTRIBUTES (olddecl))
1486 ^ mips_get_compress_off_flags (DECL_ATTRIBUTES (newdecl)));
1488 error ("%qE redeclared with conflicting %qs attributes",
1489 DECL_NAME (newdecl), mips_get_compress_off_name (diff));
1491 return merge_attributes (DECL_ATTRIBUTES (olddecl),
1492 DECL_ATTRIBUTES (newdecl));
1495 /* Implement TARGET_CAN_INLINE_P. */
1498 mips_can_inline_p (tree caller, tree callee)
1500 if (mips_get_compress_mode (callee) != mips_get_compress_mode (caller))
1502 return default_target_can_inline_p (caller, callee);
1505 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1506 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1509 mips_split_plus (rtx x, rtx *base_ptr, HOST_WIDE_INT *offset_ptr)
1511 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
1513 *base_ptr = XEXP (x, 0);
1514 *offset_ptr = INTVAL (XEXP (x, 1));
1523 static unsigned int mips_build_integer (struct mips_integer_op *,
1524 unsigned HOST_WIDE_INT);
1526 /* A subroutine of mips_build_integer, with the same interface.
1527 Assume that the final action in the sequence should be a left shift. */
1530 mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
1532 unsigned int i, shift;
1534 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1535 since signed numbers are easier to load than unsigned ones. */
1537 while ((value & 1) == 0)
1538 value /= 2, shift++;
1540 i = mips_build_integer (codes, value);
1541 codes[i].code = ASHIFT;
1542 codes[i].value = shift;
1546 /* As for mips_build_shift, but assume that the final action will be
1547 an IOR or PLUS operation. */
1550 mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
1552 unsigned HOST_WIDE_INT high;
1555 high = value & ~(unsigned HOST_WIDE_INT) 0xffff;
1556 if (!LUI_OPERAND (high) && (value & 0x18000) == 0x18000)
1558 /* The constant is too complex to load with a simple LUI/ORI pair,
1559 so we want to give the recursive call as many trailing zeros as
1560 possible. In this case, we know bit 16 is set and that the
1561 low 16 bits form a negative number. If we subtract that number
1562 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1563 i = mips_build_integer (codes, CONST_HIGH_PART (value));
1564 codes[i].code = PLUS;
1565 codes[i].value = CONST_LOW_PART (value);
1569 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1570 bits gives a value with at least 17 trailing zeros. */
1571 i = mips_build_integer (codes, high);
1572 codes[i].code = IOR;
1573 codes[i].value = value & 0xffff;
1578 /* Fill CODES with a sequence of rtl operations to load VALUE.
1579 Return the number of operations needed. */
1582 mips_build_integer (struct mips_integer_op *codes,
1583 unsigned HOST_WIDE_INT value)
1585 if (SMALL_OPERAND (value)
1586 || SMALL_OPERAND_UNSIGNED (value)
1587 || LUI_OPERAND (value))
1589 /* The value can be loaded with a single instruction. */
1590 codes[0].code = UNKNOWN;
1591 codes[0].value = value;
1594 else if ((value & 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value)))
1596 /* Either the constant is a simple LUI/ORI combination or its
1597 lowest bit is set. We don't want to shift in this case. */
1598 return mips_build_lower (codes, value);
1600 else if ((value & 0xffff) == 0)
1602 /* The constant will need at least three actions. The lowest
1603 16 bits are clear, so the final action will be a shift. */
1604 return mips_build_shift (codes, value);
1608 /* The final action could be a shift, add or inclusive OR.
1609 Rather than use a complex condition to select the best
1610 approach, try both mips_build_shift and mips_build_lower
1611 and pick the one that gives the shortest sequence.
1612 Note that this case is only used once per constant. */
1613 struct mips_integer_op alt_codes[MIPS_MAX_INTEGER_OPS];
1614 unsigned int cost, alt_cost;
1616 cost = mips_build_shift (codes, value);
1617 alt_cost = mips_build_lower (alt_codes, value);
1618 if (alt_cost < cost)
1620 memcpy (codes, alt_codes, alt_cost * sizeof (codes[0]));
1627 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1630 mips_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1632 return mips_const_insns (x) > 0;
1635 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
1638 mips16_stub_function (const char *name)
1642 x = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
1643 SYMBOL_REF_FLAGS (x) |= (SYMBOL_FLAG_EXTERNAL | SYMBOL_FLAG_FUNCTION);
1647 /* Return a legitimate call address for STUB, given that STUB is a MIPS16
1648 support function. */
1651 mips16_stub_call_address (mips_one_only_stub *stub)
1653 rtx fn = mips16_stub_function (stub->get_name ());
1654 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_LOCAL;
1655 if (!call_insn_operand (fn, VOIDmode))
1656 fn = force_reg (Pmode, fn);
1660 /* A stub for moving the thread pointer into TLS_GET_TP_REGNUM. */
1662 class mips16_rdhwr_one_only_stub : public mips_one_only_stub
1664 virtual const char *get_name ();
1665 virtual void output_body ();
1669 mips16_rdhwr_one_only_stub::get_name ()
1671 return "__mips16_rdhwr";
1675 mips16_rdhwr_one_only_stub::output_body ()
1677 fprintf (asm_out_file,
1679 "\t.set\tmips32r2\n"
1680 "\t.set\tnoreorder\n"
1686 /* A stub for moving the FCSR into GET_FCSR_REGNUM. */
1687 class mips16_get_fcsr_one_only_stub : public mips_one_only_stub
1689 virtual const char *get_name ();
1690 virtual void output_body ();
1694 mips16_get_fcsr_one_only_stub::get_name ()
1696 return "__mips16_get_fcsr";
1700 mips16_get_fcsr_one_only_stub::output_body ()
1702 fprintf (asm_out_file,
1704 "\tj\t$31\n", reg_names[GET_FCSR_REGNUM]);
1707 /* A stub for moving SET_FCSR_REGNUM into the FCSR. */
1708 class mips16_set_fcsr_one_only_stub : public mips_one_only_stub
1710 virtual const char *get_name ();
1711 virtual void output_body ();
1715 mips16_set_fcsr_one_only_stub::get_name ()
1717 return "__mips16_set_fcsr";
1721 mips16_set_fcsr_one_only_stub::output_body ()
1723 fprintf (asm_out_file,
1725 "\tj\t$31\n", reg_names[SET_FCSR_REGNUM]);
1728 /* Return true if symbols of type TYPE require a GOT access. */
1731 mips_got_symbol_type_p (enum mips_symbol_type type)
1735 case SYMBOL_GOT_PAGE_OFST:
1736 case SYMBOL_GOT_DISP:
1744 /* Return true if X is a thread-local symbol. */
1747 mips_tls_symbol_p (rtx x)
1749 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
1752 /* Return true if SYMBOL_REF X is associated with a global symbol
1753 (in the STB_GLOBAL sense). */
1756 mips_global_symbol_p (const_rtx x)
1758 const_tree decl = SYMBOL_REF_DECL (x);
1761 return !SYMBOL_REF_LOCAL_P (x) || SYMBOL_REF_EXTERNAL_P (x);
1763 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1764 or weak symbols. Relocations in the object file will be against
1765 the target symbol, so it's that symbol's binding that matters here. */
1766 return DECL_P (decl) && (TREE_PUBLIC (decl) || DECL_WEAK (decl));
1769 /* Return true if function X is a libgcc MIPS16 stub function. */
1772 mips16_stub_function_p (const_rtx x)
1774 return (GET_CODE (x) == SYMBOL_REF
1775 && strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
1778 /* Return true if function X is a locally-defined and locally-binding
1782 mips16_local_function_p (const_rtx x)
1784 return (GET_CODE (x) == SYMBOL_REF
1785 && SYMBOL_REF_LOCAL_P (x)
1786 && !SYMBOL_REF_EXTERNAL_P (x)
1787 && (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16));
1790 /* Return true if SYMBOL_REF X binds locally. */
1793 mips_symbol_binds_local_p (const_rtx x)
1795 return (SYMBOL_REF_DECL (x)
1796 ? targetm.binds_local_p (SYMBOL_REF_DECL (x))
1797 : SYMBOL_REF_LOCAL_P (x));
1800 /* Return true if rtx constants of mode MODE should be put into a small
1804 mips_rtx_constant_in_small_data_p (enum machine_mode mode)
1806 return (!TARGET_EMBEDDED_DATA
1807 && TARGET_LOCAL_SDATA
1808 && GET_MODE_SIZE (mode) <= mips_small_data_threshold);
1811 /* Return true if X should not be moved directly into register $25.
1812 We need this because many versions of GAS will treat "la $25,foo" as
1813 part of a call sequence and so allow a global "foo" to be lazily bound. */
1816 mips_dangerous_for_la25_p (rtx x)
1818 return (!TARGET_EXPLICIT_RELOCS
1820 && GET_CODE (x) == SYMBOL_REF
1821 && mips_global_symbol_p (x));
1824 /* Return true if calls to X might need $25 to be valid on entry. */
1827 mips_use_pic_fn_addr_reg_p (const_rtx x)
1829 if (!TARGET_USE_PIC_FN_ADDR_REG)
1832 /* MIPS16 stub functions are guaranteed not to use $25. */
1833 if (mips16_stub_function_p (x))
1836 if (GET_CODE (x) == SYMBOL_REF)
1838 /* If PLTs and copy relocations are available, the static linker
1839 will make sure that $25 is valid on entry to the target function. */
1840 if (TARGET_ABICALLS_PIC0)
1843 /* Locally-defined functions use absolute accesses to set up
1844 the global pointer. */
1845 if (TARGET_ABSOLUTE_ABICALLS
1846 && mips_symbol_binds_local_p (x)
1847 && !SYMBOL_REF_EXTERNAL_P (x))
1854 /* Return the method that should be used to access SYMBOL_REF or
1855 LABEL_REF X in context CONTEXT. */
1857 static enum mips_symbol_type
1858 mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
1861 return SYMBOL_GOT_DISP;
1863 if (GET_CODE (x) == LABEL_REF)
1865 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1866 code and if we know that the label is in the current function's
1867 text section. LABEL_REFs are used for jump tables as well as
1868 text labels, so we must check whether jump tables live in the
1870 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1871 && !LABEL_REF_NONLOCAL_P (x))
1872 return SYMBOL_PC_RELATIVE;
1874 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
1875 return SYMBOL_GOT_PAGE_OFST;
1877 return SYMBOL_ABSOLUTE;
1880 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1882 if (SYMBOL_REF_TLS_MODEL (x))
1885 if (CONSTANT_POOL_ADDRESS_P (x))
1887 if (TARGET_MIPS16_TEXT_LOADS)
1888 return SYMBOL_PC_RELATIVE;
1890 if (TARGET_MIPS16_PCREL_LOADS && context == SYMBOL_CONTEXT_MEM)
1891 return SYMBOL_PC_RELATIVE;
1893 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x)))
1894 return SYMBOL_GP_RELATIVE;
1897 /* Do not use small-data accesses for weak symbols; they may end up
1899 if (TARGET_GPOPT && SYMBOL_REF_SMALL_P (x) && !SYMBOL_REF_WEAK (x))
1900 return SYMBOL_GP_RELATIVE;
1902 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1904 if (TARGET_ABICALLS_PIC2
1905 && !(TARGET_ABSOLUTE_ABICALLS && mips_symbol_binds_local_p (x)))
1907 /* There are three cases to consider:
1909 - o32 PIC (either with or without explicit relocs)
1910 - n32/n64 PIC without explicit relocs
1911 - n32/n64 PIC with explicit relocs
1913 In the first case, both local and global accesses will use an
1914 R_MIPS_GOT16 relocation. We must correctly predict which of
1915 the two semantics (local or global) the assembler and linker
1916 will apply. The choice depends on the symbol's binding rather
1917 than its visibility.
1919 In the second case, the assembler will not use R_MIPS_GOT16
1920 relocations, but it chooses between local and global accesses
1921 in the same way as for o32 PIC.
1923 In the third case we have more freedom since both forms of
1924 access will work for any kind of symbol. However, there seems
1925 little point in doing things differently. */
1926 if (mips_global_symbol_p (x))
1927 return SYMBOL_GOT_DISP;
1929 return SYMBOL_GOT_PAGE_OFST;
1932 return SYMBOL_ABSOLUTE;
1935 /* Classify the base of symbolic expression X, given that X appears in
1938 static enum mips_symbol_type
1939 mips_classify_symbolic_expression (rtx x, enum mips_symbol_context context)
1943 split_const (x, &x, &offset);
1944 if (UNSPEC_ADDRESS_P (x))
1945 return UNSPEC_ADDRESS_TYPE (x);
1947 return mips_classify_symbol (x, context);
1950 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1951 is the alignment in bytes of SYMBOL_REF X. */
1954 mips_offset_within_alignment_p (rtx x, HOST_WIDE_INT offset)
1956 HOST_WIDE_INT align;
1958 align = SYMBOL_REF_DECL (x) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x)) : 1;
1959 return IN_RANGE (offset, 0, align - 1);
1962 /* Return true if X is a symbolic constant that can be used in context
1963 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1966 mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
1967 enum mips_symbol_type *symbol_type)
1971 split_const (x, &x, &offset);
1972 if (UNSPEC_ADDRESS_P (x))
1974 *symbol_type = UNSPEC_ADDRESS_TYPE (x);
1975 x = UNSPEC_ADDRESS (x);
1977 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1979 *symbol_type = mips_classify_symbol (x, context);
1980 if (*symbol_type == SYMBOL_TLS)
1986 if (offset == const0_rtx)
1989 /* Check whether a nonzero offset is valid for the underlying
1991 switch (*symbol_type)
1993 case SYMBOL_ABSOLUTE:
1994 case SYMBOL_64_HIGH:
1997 /* If the target has 64-bit pointers and the object file only
1998 supports 32-bit symbols, the values of those symbols will be
1999 sign-extended. In this case we can't allow an arbitrary offset
2000 in case the 32-bit value X + OFFSET has a different sign from X. */
2001 if (Pmode == DImode && !ABI_HAS_64BIT_SYMBOLS)
2002 return offset_within_block_p (x, INTVAL (offset));
2004 /* In other cases the relocations can handle any offset. */
2007 case SYMBOL_PC_RELATIVE:
2008 /* Allow constant pool references to be converted to LABEL+CONSTANT.
2009 In this case, we no longer have access to the underlying constant,
2010 but the original symbol-based access was known to be valid. */
2011 if (GET_CODE (x) == LABEL_REF)
2016 case SYMBOL_GP_RELATIVE:
2017 /* Make sure that the offset refers to something within the
2018 same object block. This should guarantee that the final
2019 PC- or GP-relative offset is within the 16-bit limit. */
2020 return offset_within_block_p (x, INTVAL (offset));
2022 case SYMBOL_GOT_PAGE_OFST:
2023 case SYMBOL_GOTOFF_PAGE:
2024 /* If the symbol is global, the GOT entry will contain the symbol's
2025 address, and we will apply a 16-bit offset after loading it.
2026 If the symbol is local, the linker should provide enough local
2027 GOT entries for a 16-bit offset, but larger offsets may lead
2029 return SMALL_INT (offset);
2033 /* There is no carry between the HI and LO REL relocations, so the
2034 offset is only valid if we know it won't lead to such a carry. */
2035 return mips_offset_within_alignment_p (x, INTVAL (offset));
2037 case SYMBOL_GOT_DISP:
2038 case SYMBOL_GOTOFF_DISP:
2039 case SYMBOL_GOTOFF_CALL:
2040 case SYMBOL_GOTOFF_LOADGP:
2043 case SYMBOL_GOTTPREL:
2051 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
2052 single instruction. We rely on the fact that, in the worst case,
2053 all instructions involved in a MIPS16 address calculation are usually
2057 mips_symbol_insns_1 (enum mips_symbol_type type, enum machine_mode mode)
2059 if (mips_use_pcrel_pool_p[(int) type])
2061 if (mode == MAX_MACHINE_MODE)
2062 /* LEAs will be converted into constant-pool references by
2064 type = SYMBOL_PC_RELATIVE;
2066 /* The constant must be loaded and then dereferenced. */
2072 case SYMBOL_ABSOLUTE:
2073 /* When using 64-bit symbols, we need 5 preparatory instructions,
2076 lui $at,%highest(symbol)
2077 daddiu $at,$at,%higher(symbol)
2079 daddiu $at,$at,%hi(symbol)
2082 The final address is then $at + %lo(symbol). With 32-bit
2083 symbols we just need a preparatory LUI for normal mode and
2084 a preparatory LI and SLL for MIPS16. */
2085 return ABI_HAS_64BIT_SYMBOLS ? 6 : TARGET_MIPS16 ? 3 : 2;
2087 case SYMBOL_GP_RELATIVE:
2088 /* Treat GP-relative accesses as taking a single instruction on
2089 MIPS16 too; the copy of $gp can often be shared. */
2092 case SYMBOL_PC_RELATIVE:
2093 /* PC-relative constants can be only be used with ADDIUPC,
2094 DADDIUPC, LWPC and LDPC. */
2095 if (mode == MAX_MACHINE_MODE
2096 || GET_MODE_SIZE (mode) == 4
2097 || GET_MODE_SIZE (mode) == 8)
2100 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
2103 case SYMBOL_GOT_DISP:
2104 /* The constant will have to be loaded from the GOT before it
2105 is used in an address. */
2106 if (mode != MAX_MACHINE_MODE)
2111 case SYMBOL_GOT_PAGE_OFST:
2112 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
2113 local/global classification is accurate. The worst cases are:
2115 (1) For local symbols when generating o32 or o64 code. The assembler
2121 ...and the final address will be $at + %lo(symbol).
2123 (2) For global symbols when -mxgot. The assembler will use:
2125 lui $at,%got_hi(symbol)
2128 ...and the final address will be $at + %got_lo(symbol). */
2131 case SYMBOL_GOTOFF_PAGE:
2132 case SYMBOL_GOTOFF_DISP:
2133 case SYMBOL_GOTOFF_CALL:
2134 case SYMBOL_GOTOFF_LOADGP:
2135 case SYMBOL_64_HIGH:
2141 case SYMBOL_GOTTPREL:
2144 /* A 16-bit constant formed by a single relocation, or a 32-bit
2145 constant formed from a high 16-bit relocation and a low 16-bit
2146 relocation. Use mips_split_p to determine which. 32-bit
2147 constants need an "lui; addiu" sequence for normal mode and
2148 an "li; sll; addiu" sequence for MIPS16 mode. */
2149 return !mips_split_p[type] ? 1 : TARGET_MIPS16 ? 3 : 2;
2152 /* We don't treat a bare TLS symbol as a constant. */
2158 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
2159 to load symbols of type TYPE into a register. Return 0 if the given
2160 type of symbol cannot be used as an immediate operand.
2162 Otherwise, return the number of instructions needed to load or store
2163 values of mode MODE to or from addresses of type TYPE. Return 0 if
2164 the given type of symbol is not valid in addresses.
2166 In both cases, instruction counts are based off BASE_INSN_LENGTH. */
2169 mips_symbol_insns (enum mips_symbol_type type, enum machine_mode mode)
2171 return mips_symbol_insns_1 (type, mode) * (TARGET_MIPS16 ? 2 : 1);
2174 /* A for_each_rtx callback. Stop the search if *X references a
2175 thread-local symbol. */
2178 mips_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2180 return mips_tls_symbol_p (*x);
2183 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
2186 mips_cannot_force_const_mem (enum machine_mode mode, rtx x)
2188 enum mips_symbol_type type;
2191 /* There is no assembler syntax for expressing an address-sized
2193 if (GET_CODE (x) == HIGH)
2196 /* As an optimization, reject constants that mips_legitimize_move
2199 Suppose we have a multi-instruction sequence that loads constant C
2200 into register R. If R does not get allocated a hard register, and
2201 R is used in an operand that allows both registers and memory
2202 references, reload will consider forcing C into memory and using
2203 one of the instruction's memory alternatives. Returning false
2204 here will force it to use an input reload instead. */
2205 if (CONST_INT_P (x) && mips_legitimate_constant_p (mode, x))
2208 split_const (x, &base, &offset);
2209 if (mips_symbolic_constant_p (base, SYMBOL_CONTEXT_LEA, &type))
2211 /* See whether we explicitly want these symbols in the pool. */
2212 if (mips_use_pcrel_pool_p[(int) type])
2215 /* The same optimization as for CONST_INT. */
2216 if (SMALL_INT (offset) && mips_symbol_insns (type, MAX_MACHINE_MODE) > 0)
2219 /* If MIPS16 constant pools live in the text section, they should
2220 not refer to anything that might need run-time relocation. */
2221 if (TARGET_MIPS16_PCREL_LOADS && mips_got_symbol_type_p (type))
2225 /* TLS symbols must be computed by mips_legitimize_move. */
2226 if (for_each_rtx (&x, &mips_tls_symbol_ref_1, NULL))
2232 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2233 constants when we're using a per-function constant pool. */
2236 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED,
2237 const_rtx x ATTRIBUTE_UNUSED)
2239 return !TARGET_MIPS16_PCREL_LOADS;
2242 /* Return true if register REGNO is a valid base register for mode MODE.
2243 STRICT_P is true if REG_OK_STRICT is in effect. */
2246 mips_regno_mode_ok_for_base_p (int regno, enum machine_mode mode,
2249 if (!HARD_REGISTER_NUM_P (regno))
2253 regno = reg_renumber[regno];
2256 /* These fake registers will be eliminated to either the stack or
2257 hard frame pointer, both of which are usually valid base registers.
2258 Reload deals with the cases where the eliminated form isn't valid. */
2259 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM)
2262 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2263 values, nothing smaller. */
2264 if (TARGET_MIPS16 && regno == STACK_POINTER_REGNUM)
2265 return GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8;
2267 return TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
2270 /* Return true if X is a valid base register for mode MODE.
2271 STRICT_P is true if REG_OK_STRICT is in effect. */
2274 mips_valid_base_register_p (rtx x, enum machine_mode mode, bool strict_p)
2276 if (!strict_p && GET_CODE (x) == SUBREG)
2280 && mips_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p));
2283 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2284 can address a value of mode MODE. */
2287 mips_valid_offset_p (rtx x, enum machine_mode mode)
2289 /* Check that X is a signed 16-bit number. */
2290 if (!const_arith_operand (x, Pmode))
2293 /* We may need to split multiword moves, so make sure that every word
2295 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2296 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD))
2302 /* Return true if a LO_SUM can address a value of mode MODE when the
2303 LO_SUM symbol has type SYMBOL_TYPE. */
2306 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type, enum machine_mode mode)
2308 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2310 if (mips_symbol_insns (symbol_type, mode) == 0)
2313 /* Check that there is a known low-part relocation. */
2314 if (mips_lo_relocs[symbol_type] == NULL)
2317 /* We may need to split multiword moves, so make sure that each word
2318 can be accessed without inducing a carry. This is mainly needed
2319 for o64, which has historically only guaranteed 64-bit alignment
2320 for 128-bit types. */
2321 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
2322 && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))
2328 /* Return true if X is a valid address for machine mode MODE. If it is,
2329 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2333 mips_classify_address (struct mips_address_info *info, rtx x,
2334 enum machine_mode mode, bool strict_p)
2336 switch (GET_CODE (x))
2340 info->type = ADDRESS_REG;
2342 info->offset = const0_rtx;
2343 return mips_valid_base_register_p (info->reg, mode, strict_p);
2346 info->type = ADDRESS_REG;
2347 info->reg = XEXP (x, 0);
2348 info->offset = XEXP (x, 1);
2349 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2350 && mips_valid_offset_p (info->offset, mode));
2353 info->type = ADDRESS_LO_SUM;
2354 info->reg = XEXP (x, 0);
2355 info->offset = XEXP (x, 1);
2356 /* We have to trust the creator of the LO_SUM to do something vaguely
2357 sane. Target-independent code that creates a LO_SUM should also
2358 create and verify the matching HIGH. Target-independent code that
2359 adds an offset to a LO_SUM must prove that the offset will not
2360 induce a carry. Failure to do either of these things would be
2361 a bug, and we are not required to check for it here. The MIPS
2362 backend itself should only create LO_SUMs for valid symbolic
2363 constants, with the high part being either a HIGH or a copy
2366 = mips_classify_symbolic_expression (info->offset, SYMBOL_CONTEXT_MEM);
2367 return (mips_valid_base_register_p (info->reg, mode, strict_p)
2368 && mips_valid_lo_sum_p (info->symbol_type, mode));
2371 /* Small-integer addresses don't occur very often, but they
2372 are legitimate if $0 is a valid base register. */
2373 info->type = ADDRESS_CONST_INT;
2374 return !TARGET_MIPS16 && SMALL_INT (x);
2379 info->type = ADDRESS_SYMBOLIC;
2380 return (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_MEM,
2382 && mips_symbol_insns (info->symbol_type, mode) > 0
2383 && !mips_split_p[info->symbol_type]);
2390 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2393 mips_legitimate_address_p (enum machine_mode mode, rtx x, bool strict_p)
2395 struct mips_address_info addr;
2397 return mips_classify_address (&addr, x, mode, strict_p);
2400 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2403 mips_stack_address_p (rtx x, enum machine_mode mode)
2405 struct mips_address_info addr;
2407 return (mips_classify_address (&addr, x, mode, false)
2408 && addr.type == ADDRESS_REG
2409 && addr.reg == stack_pointer_rtx);
2412 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2413 address instruction. Note that such addresses are not considered
2414 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2415 is so restricted. */
2418 mips_lwxs_address_p (rtx addr)
2421 && GET_CODE (addr) == PLUS
2422 && REG_P (XEXP (addr, 1)))
2424 rtx offset = XEXP (addr, 0);
2425 if (GET_CODE (offset) == MULT
2426 && REG_P (XEXP (offset, 0))
2427 && CONST_INT_P (XEXP (offset, 1))
2428 && INTVAL (XEXP (offset, 1)) == 4)
2434 /* Return true if ADDR matches the pattern for the L{B,H,W,D}{,U}X load
2435 indexed address instruction. Note that such addresses are
2436 not considered legitimate in the TARGET_LEGITIMATE_ADDRESS_P
2437 sense, because their use is so restricted. */
2440 mips_lx_address_p (rtx addr, enum machine_mode mode)
2442 if (GET_CODE (addr) != PLUS
2443 || !REG_P (XEXP (addr, 0))
2444 || !REG_P (XEXP (addr, 1)))
2446 if (ISA_HAS_LBX && mode == QImode)
2448 if (ISA_HAS_LHX && mode == HImode)
2450 if (ISA_HAS_LWX && mode == SImode)
2452 if (ISA_HAS_LDX && mode == DImode)
2457 /* Return true if a value at OFFSET bytes from base register BASE can be
2458 accessed using an unextended MIPS16 instruction. MODE is the mode of
2461 Usually the offset in an unextended instruction is a 5-bit field.
2462 The offset is unsigned and shifted left once for LH and SH, twice
2463 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2464 an 8-bit immediate field that's shifted left twice. */
2467 mips16_unextended_reference_p (enum machine_mode mode, rtx base,
2468 unsigned HOST_WIDE_INT offset)
2470 if (mode != BLKmode && offset % GET_MODE_SIZE (mode) == 0)
2472 if (GET_MODE_SIZE (mode) == 4 && base == stack_pointer_rtx)
2473 return offset < 256U * GET_MODE_SIZE (mode);
2474 return offset < 32U * GET_MODE_SIZE (mode);
2479 /* Return the number of instructions needed to load or store a value
2480 of mode MODE at address X, assuming that BASE_INSN_LENGTH is the
2481 length of one instruction. Return 0 if X isn't valid for MODE.
2482 Assume that multiword moves may need to be split into word moves
2483 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2487 mips_address_insns (rtx x, enum machine_mode mode, bool might_split_p)
2489 struct mips_address_info addr;
2492 /* BLKmode is used for single unaligned loads and stores and should
2493 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2494 meaningless, so we have to single it out as a special case one way
2496 if (mode != BLKmode && might_split_p)
2497 factor = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
2501 if (mips_classify_address (&addr, x, mode, false))
2506 && !mips16_unextended_reference_p (mode, addr.reg,
2507 UINTVAL (addr.offset)))
2511 case ADDRESS_LO_SUM:
2512 return TARGET_MIPS16 ? factor * 2 : factor;
2514 case ADDRESS_CONST_INT:
2517 case ADDRESS_SYMBOLIC:
2518 return factor * mips_symbol_insns (addr.symbol_type, mode);
2523 /* Return true if X fits within an unsigned field of BITS bits that is
2524 shifted left SHIFT bits before being used. */
2527 mips_unsigned_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2529 return (x & ((1 << shift) - 1)) == 0 && x < ((unsigned) 1 << (shift + bits));
2532 /* Return true if X fits within a signed field of BITS bits that is
2533 shifted left SHIFT bits before being used. */
2536 mips_signed_immediate_p (unsigned HOST_WIDE_INT x, int bits, int shift = 0)
2538 x += 1 << (bits + shift - 1);
2539 return mips_unsigned_immediate_p (x, bits, shift);
2542 /* Return true if X is legitimate for accessing values of mode MODE,
2543 if it is based on a MIPS16 register, and if the offset satisfies
2544 OFFSET_PREDICATE. */
2547 m16_based_address_p (rtx x, enum machine_mode mode,
2548 insn_operand_predicate_fn offset_predicate)
2550 struct mips_address_info addr;
2552 return (mips_classify_address (&addr, x, mode, false)
2553 && addr.type == ADDRESS_REG
2554 && M16_REG_P (REGNO (addr.reg))
2555 && offset_predicate (addr.offset, mode));
2558 /* Return true if X is a legitimate address that conforms to the requirements
2559 for a microMIPS LWSP or SWSP insn. */
2562 lwsp_swsp_address_p (rtx x, enum machine_mode mode)
2564 struct mips_address_info addr;
2566 return (mips_classify_address (&addr, x, mode, false)
2567 && addr.type == ADDRESS_REG
2568 && REGNO (addr.reg) == STACK_POINTER_REGNUM
2569 && uw5_operand (addr.offset, mode));
2572 /* Return true if X is a legitimate address with a 12-bit offset.
2573 MODE is the mode of the value being accessed. */
2576 umips_12bit_offset_address_p (rtx x, enum machine_mode mode)
2578 struct mips_address_info addr;
2580 return (mips_classify_address (&addr, x, mode, false)
2581 && addr.type == ADDRESS_REG
2582 && CONST_INT_P (addr.offset)
2583 && UMIPS_12BIT_OFFSET_P (INTVAL (addr.offset)));
2586 /* Return the number of instructions needed to load constant X,
2587 assuming that BASE_INSN_LENGTH is the length of one instruction.
2588 Return 0 if X isn't a valid constant. */
2591 mips_const_insns (rtx x)
2593 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
2594 enum mips_symbol_type symbol_type;
2597 switch (GET_CODE (x))
2600 if (!mips_symbolic_constant_p (XEXP (x, 0), SYMBOL_CONTEXT_LEA,
2602 || !mips_split_p[symbol_type])
2605 /* This is simply an LUI for normal mode. It is an extended
2606 LI followed by an extended SLL for MIPS16. */
2607 return TARGET_MIPS16 ? 4 : 1;
2611 /* Unsigned 8-bit constants can be loaded using an unextended
2612 LI instruction. Unsigned 16-bit constants can be loaded
2613 using an extended LI. Negative constants must be loaded
2614 using LI and then negated. */
2615 return (IN_RANGE (INTVAL (x), 0, 255) ? 1
2616 : SMALL_OPERAND_UNSIGNED (INTVAL (x)) ? 2
2617 : IN_RANGE (-INTVAL (x), 0, 255) ? 2
2618 : SMALL_OPERAND_UNSIGNED (-INTVAL (x)) ? 3
2621 return mips_build_integer (codes, INTVAL (x));
2625 /* Allow zeros for normal mode, where we can use $0. */
2626 return !TARGET_MIPS16 && x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;
2632 /* See if we can refer to X directly. */
2633 if (mips_symbolic_constant_p (x, SYMBOL_CONTEXT_LEA, &symbol_type))
2634 return mips_symbol_insns (symbol_type, MAX_MACHINE_MODE);
2636 /* Otherwise try splitting the constant into a base and offset.
2637 If the offset is a 16-bit value, we can load the base address
2638 into a register and then use (D)ADDIU to add in the offset.
2639 If the offset is larger, we can load the base and offset
2640 into separate registers and add them together with (D)ADDU.
2641 However, the latter is only possible before reload; during
2642 and after reload, we must have the option of forcing the
2643 constant into the pool instead. */
2644 split_const (x, &x, &offset);
2647 int n = mips_const_insns (x);
2650 if (SMALL_INT (offset))
2652 else if (!targetm.cannot_force_const_mem (GET_MODE (x), x))
2653 return n + 1 + mips_build_integer (codes, INTVAL (offset));
2660 return mips_symbol_insns (mips_classify_symbol (x, SYMBOL_CONTEXT_LEA),
2668 /* X is a doubleword constant that can be handled by splitting it into
2669 two words and loading each word separately. Return the number of
2670 instructions required to do this, assuming that BASE_INSN_LENGTH
2671 is the length of one instruction. */
2674 mips_split_const_insns (rtx x)
2676 unsigned int low, high;
2678 low = mips_const_insns (mips_subword (x, false));
2679 high = mips_const_insns (mips_subword (x, true));
2680 gcc_assert (low > 0 && high > 0);
2684 /* Return the number of instructions needed to implement INSN,
2685 given that it loads from or stores to MEM. Assume that
2686 BASE_INSN_LENGTH is the length of one instruction. */
2689 mips_load_store_insns (rtx mem, rtx insn)
2691 enum machine_mode mode;
2695 gcc_assert (MEM_P (mem));
2696 mode = GET_MODE (mem);
2698 /* Try to prove that INSN does not need to be split. */
2699 might_split_p = GET_MODE_SIZE (mode) > UNITS_PER_WORD;
2702 set = single_set (insn);
2703 if (set && !mips_split_move_insn_p (SET_DEST (set), SET_SRC (set), insn))
2704 might_split_p = false;
2707 return mips_address_insns (XEXP (mem, 0), mode, might_split_p);
2710 /* Return the number of instructions needed for an integer division,
2711 assuming that BASE_INSN_LENGTH is the length of one instruction. */
2714 mips_idiv_insns (void)
2719 if (TARGET_CHECK_ZERO_DIV)
2721 if (GENERATE_DIVIDE_TRAPS)
2727 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
2732 /* Emit a move from SRC to DEST. Assume that the move expanders can
2733 handle all moves if !can_create_pseudo_p (). The distinction is
2734 important because, unlike emit_move_insn, the move expanders know
2735 how to force Pmode objects into the constant pool even when the
2736 constant pool address is not itself legitimate. */
2739 mips_emit_move (rtx dest, rtx src)
2741 return (can_create_pseudo_p ()
2742 ? emit_move_insn (dest, src)
2743 : emit_move_insn_1 (dest, src));
2746 /* Emit a move from SRC to DEST, splitting compound moves into individual
2747 instructions. SPLIT_TYPE is the type of split to perform. */
2750 mips_emit_move_or_split (rtx dest, rtx src, enum mips_split_type split_type)
2752 if (mips_split_move_p (dest, src, split_type))
2753 mips_split_move (dest, src, split_type);
2755 mips_emit_move (dest, src);
2758 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2761 mips_emit_unary (enum rtx_code code, rtx target, rtx op0)
2763 emit_insn (gen_rtx_SET (VOIDmode, target,
2764 gen_rtx_fmt_e (code, GET_MODE (op0), op0)));
2767 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2768 Return that new register. */
2771 mips_force_unary (enum machine_mode mode, enum rtx_code code, rtx op0)
2775 reg = gen_reg_rtx (mode);
2776 mips_emit_unary (code, reg, op0);
2780 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2783 mips_emit_binary (enum rtx_code code, rtx target, rtx op0, rtx op1)
2785 emit_insn (gen_rtx_SET (VOIDmode, target,
2786 gen_rtx_fmt_ee (code, GET_MODE (target), op0, op1)));
2789 /* Compute (CODE OP0 OP1) and store the result in a new register
2790 of mode MODE. Return that new register. */
2793 mips_force_binary (enum machine_mode mode, enum rtx_code code, rtx op0, rtx op1)
2797 reg = gen_reg_rtx (mode);
2798 mips_emit_binary (code, reg, op0, op1);
2802 /* Copy VALUE to a register and return that register. If new pseudos
2803 are allowed, copy it into a new register, otherwise use DEST. */
2806 mips_force_temporary (rtx dest, rtx value)
2808 if (can_create_pseudo_p ())
2809 return force_reg (Pmode, value);
2812 mips_emit_move (dest, value);
2817 /* Emit a call sequence with call pattern PATTERN and return the call
2818 instruction itself (which is not necessarily the last instruction
2819 emitted). ORIG_ADDR is the original, unlegitimized address,
2820 ADDR is the legitimized form, and LAZY_P is true if the call
2821 address is lazily-bound. */
2824 mips_emit_call_insn (rtx pattern, rtx orig_addr, rtx addr, bool lazy_p)
2828 insn = emit_call_insn (pattern);
2830 if (TARGET_MIPS16 && mips_use_pic_fn_addr_reg_p (orig_addr))
2832 /* MIPS16 JALRs only take MIPS16 registers. If the target
2833 function requires $25 to be valid on entry, we must copy it
2834 there separately. The move instruction can be put in the
2835 call's delay slot. */
2836 reg = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
2837 emit_insn_before (gen_move_insn (reg, addr), insn);
2838 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
2842 /* Lazy-binding stubs require $gp to be valid on entry. */
2843 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
2847 /* See the comment above load_call<mode> for details. */
2848 use_reg (&CALL_INSN_FUNCTION_USAGE (insn),
2849 gen_rtx_REG (Pmode, GOT_VERSION_REGNUM));
2850 emit_insn (gen_update_got_version ());
2854 && TARGET_EXPLICIT_RELOCS
2855 && TARGET_CALL_CLOBBERED_GP)
2857 rtx post_call_tmp_reg = gen_rtx_REG (word_mode, POST_CALL_TMP_REG);
2858 clobber_reg (&CALL_INSN_FUNCTION_USAGE (insn), post_call_tmp_reg);
2864 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2865 then add CONST_INT OFFSET to the result. */
2868 mips_unspec_address_offset (rtx base, rtx offset,
2869 enum mips_symbol_type symbol_type)
2871 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base),
2872 UNSPEC_ADDRESS_FIRST + symbol_type);
2873 if (offset != const0_rtx)
2874 base = gen_rtx_PLUS (Pmode, base, offset);
2875 return gen_rtx_CONST (Pmode, base);
2878 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2879 type SYMBOL_TYPE. */
2882 mips_unspec_address (rtx address, enum mips_symbol_type symbol_type)
2886 split_const (address, &base, &offset);
2887 return mips_unspec_address_offset (base, offset, symbol_type);
2890 /* If OP is an UNSPEC address, return the address to which it refers,
2891 otherwise return OP itself. */
2894 mips_strip_unspec_address (rtx op)
2898 split_const (op, &base, &offset);
2899 if (UNSPEC_ADDRESS_P (base))
2900 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset));
2904 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2905 high part to BASE and return the result. Just return BASE otherwise.
2906 TEMP is as for mips_force_temporary.
2908 The returned expression can be used as the first operand to a LO_SUM. */
2911 mips_unspec_offset_high (rtx temp, rtx base, rtx addr,
2912 enum mips_symbol_type symbol_type)
2914 if (mips_split_p[symbol_type])
2916 addr = gen_rtx_HIGH (Pmode, mips_unspec_address (addr, symbol_type));
2917 addr = mips_force_temporary (temp, addr);
2918 base = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, addr, base));
2923 /* Return an instruction that copies $gp into register REG. We want
2924 GCC to treat the register's value as constant, so that its value
2925 can be rematerialized on demand. */
2928 gen_load_const_gp (rtx reg)
2930 return PMODE_INSN (gen_load_const_gp, (reg));
2933 /* Return a pseudo register that contains the value of $gp throughout
2934 the current function. Such registers are needed by MIPS16 functions,
2935 for which $gp itself is not a valid base register or addition operand. */
2938 mips16_gp_pseudo_reg (void)
2940 if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
2944 cfun->machine->mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
2946 push_topmost_sequence ();
2948 scan = get_insns ();
2949 while (NEXT_INSN (scan) && !INSN_P (NEXT_INSN (scan)))
2950 scan = NEXT_INSN (scan);
2952 insn = gen_load_const_gp (cfun->machine->mips16_gp_pseudo_rtx);
2953 insn = emit_insn_after (insn, scan);
2954 INSN_LOCATION (insn) = 0;
2956 pop_topmost_sequence ();
2959 return cfun->machine->mips16_gp_pseudo_rtx;
2962 /* Return a base register that holds pic_offset_table_rtx.
2963 TEMP, if nonnull, is a scratch Pmode base register. */
2966 mips_pic_base_register (rtx temp)
2969 return pic_offset_table_rtx;
2971 if (currently_expanding_to_rtl)
2972 return mips16_gp_pseudo_reg ();
2974 if (can_create_pseudo_p ())
2975 temp = gen_reg_rtx (Pmode);
2978 /* The first post-reload split exposes all references to $gp
2979 (both uses and definitions). All references must remain
2980 explicit after that point.
2982 It is safe to introduce uses of $gp at any time, so for
2983 simplicity, we do that before the split too. */
2984 mips_emit_move (temp, pic_offset_table_rtx);
2986 emit_insn (gen_load_const_gp (temp));
2990 /* Return the RHS of a load_call<mode> insn. */
2993 mips_unspec_call (rtx reg, rtx symbol)
2997 vec = gen_rtvec (3, reg, symbol, gen_rtx_REG (SImode, GOT_VERSION_REGNUM));
2998 return gen_rtx_UNSPEC (Pmode, vec, UNSPEC_LOAD_CALL);
3001 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
3002 reference. Return NULL_RTX otherwise. */
3005 mips_strip_unspec_call (rtx src)
3007 if (GET_CODE (src) == UNSPEC && XINT (src, 1) == UNSPEC_LOAD_CALL)
3008 return mips_strip_unspec_address (XVECEXP (src, 0, 1));
3012 /* Create and return a GOT reference of type TYPE for address ADDR.
3013 TEMP, if nonnull, is a scratch Pmode base register. */
3016 mips_got_load (rtx temp, rtx addr, enum mips_symbol_type type)
3018 rtx base, high, lo_sum_symbol;
3020 base = mips_pic_base_register (temp);
3022 /* If we used the temporary register to load $gp, we can't use
3023 it for the high part as well. */
3024 if (temp != NULL && reg_overlap_mentioned_p (base, temp))
3027 high = mips_unspec_offset_high (temp, base, addr, type);
3028 lo_sum_symbol = mips_unspec_address (addr, type);
3030 if (type == SYMBOL_GOTOFF_CALL)
3031 return mips_unspec_call (high, lo_sum_symbol);
3033 return PMODE_INSN (gen_unspec_got, (high, lo_sum_symbol));
3036 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
3037 it appears in a MEM of that mode. Return true if ADDR is a legitimate
3038 constant in that context and can be split into high and low parts.
3039 If so, and if LOW_OUT is nonnull, emit the high part and store the
3040 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
3042 TEMP is as for mips_force_temporary and is used to load the high
3043 part into a register.
3045 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
3046 a legitimize SET_SRC for an .md pattern, otherwise the low part
3047 is guaranteed to be a legitimate address for mode MODE. */
3050 mips_split_symbol (rtx temp, rtx addr, enum machine_mode mode, rtx *low_out)
3052 enum mips_symbol_context context;
3053 enum mips_symbol_type symbol_type;
3056 context = (mode == MAX_MACHINE_MODE
3057 ? SYMBOL_CONTEXT_LEA
3058 : SYMBOL_CONTEXT_MEM);
3059 if (GET_CODE (addr) == HIGH && context == SYMBOL_CONTEXT_LEA)
3061 addr = XEXP (addr, 0);
3062 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3063 && mips_symbol_insns (symbol_type, mode) > 0
3064 && mips_split_hi_p[symbol_type])
3067 switch (symbol_type)
3069 case SYMBOL_GOT_PAGE_OFST:
3070 /* The high part of a page/ofst pair is loaded from the GOT. */
3071 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_PAGE);
3082 if (mips_symbolic_constant_p (addr, context, &symbol_type)
3083 && mips_symbol_insns (symbol_type, mode) > 0
3084 && mips_split_p[symbol_type])
3087 switch (symbol_type)
3089 case SYMBOL_GOT_DISP:
3090 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
3091 *low_out = mips_got_load (temp, addr, SYMBOL_GOTOFF_DISP);
3094 case SYMBOL_GP_RELATIVE:
3095 high = mips_pic_base_register (temp);
3096 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3100 high = gen_rtx_HIGH (Pmode, copy_rtx (addr));
3101 high = mips_force_temporary (temp, high);
3102 *low_out = gen_rtx_LO_SUM (Pmode, high, addr);
3111 /* Return a legitimate address for REG + OFFSET. TEMP is as for
3112 mips_force_temporary; it is only needed when OFFSET is not a
3116 mips_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset)
3118 if (!SMALL_OPERAND (offset))
3124 /* Load the full offset into a register so that we can use
3125 an unextended instruction for the address itself. */
3126 high = GEN_INT (offset);
3131 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3132 The addition inside the macro CONST_HIGH_PART may cause an
3133 overflow, so we need to force a sign-extension check. */
3134 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode);
3135 offset = CONST_LOW_PART (offset);
3137 high = mips_force_temporary (temp, high);
3138 reg = mips_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg));
3140 return plus_constant (Pmode, reg, offset);
3143 /* The __tls_get_attr symbol. */
3144 static GTY(()) rtx mips_tls_symbol;
3146 /* Return an instruction sequence that calls __tls_get_addr. SYM is
3147 the TLS symbol we are referencing and TYPE is the symbol type to use
3148 (either global dynamic or local dynamic). V0 is an RTX for the
3149 return value location. */
3152 mips_call_tls_get_addr (rtx sym, enum mips_symbol_type type, rtx v0)
3156 a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
3158 if (!mips_tls_symbol)
3159 mips_tls_symbol = init_one_libfunc ("__tls_get_addr");
3161 loc = mips_unspec_address (sym, type);
3165 emit_insn (gen_rtx_SET (Pmode, a0,
3166 gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, loc)));
3167 insn = mips_expand_call (MIPS_CALL_NORMAL, v0, mips_tls_symbol,
3168 const0_rtx, NULL_RTX, false);
3169 RTL_CONST_CALL_P (insn) = 1;
3170 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0);
3171 insn = get_insns ();
3178 /* Return a pseudo register that contains the current thread pointer. */
3181 mips_expand_thread_pointer (rtx tp)
3187 if (!mips16_rdhwr_stub)
3188 mips16_rdhwr_stub = new mips16_rdhwr_one_only_stub ();
3189 fn = mips16_stub_call_address (mips16_rdhwr_stub);
3190 emit_insn (PMODE_INSN (gen_tls_get_tp_mips16, (tp, fn)));
3193 emit_insn (PMODE_INSN (gen_tls_get_tp, (tp)));
3200 return mips_expand_thread_pointer (gen_reg_rtx (Pmode));
3203 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
3204 its address. The return value will be both a valid address and a valid
3205 SET_SRC (either a REG or a LO_SUM). */
3208 mips_legitimize_tls_address (rtx loc)
3210 rtx dest, insn, v0, tp, tmp1, tmp2, eqv, offset;
3211 enum tls_model model;
3213 model = SYMBOL_REF_TLS_MODEL (loc);
3214 /* Only TARGET_ABICALLS code can have more than one module; other
3215 code must be be static and should not use a GOT. All TLS models
3216 reduce to local exec in this situation. */
3217 if (!TARGET_ABICALLS)
3218 model = TLS_MODEL_LOCAL_EXEC;
3222 case TLS_MODEL_GLOBAL_DYNAMIC:
3223 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3224 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSGD, v0);
3225 dest = gen_reg_rtx (Pmode);
3226 emit_libcall_block (insn, dest, v0, loc);
3229 case TLS_MODEL_LOCAL_DYNAMIC:
3230 v0 = gen_rtx_REG (Pmode, GP_RETURN);
3231 insn = mips_call_tls_get_addr (loc, SYMBOL_TLSLDM, v0);
3232 tmp1 = gen_reg_rtx (Pmode);
3234 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
3235 share the LDM result with other LD model accesses. */
3236 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3238 emit_libcall_block (insn, tmp1, v0, eqv);
3240 offset = mips_unspec_address (loc, SYMBOL_DTPREL);
3241 if (mips_split_p[SYMBOL_DTPREL])
3243 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_DTPREL);
3244 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3247 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3248 0, 0, OPTAB_DIRECT);
3251 case TLS_MODEL_INITIAL_EXEC:
3252 tp = mips_get_tp ();
3253 tmp1 = gen_reg_rtx (Pmode);
3254 tmp2 = mips_unspec_address (loc, SYMBOL_GOTTPREL);
3255 if (Pmode == DImode)
3256 emit_insn (gen_load_gotdi (tmp1, pic_offset_table_rtx, tmp2));
3258 emit_insn (gen_load_gotsi (tmp1, pic_offset_table_rtx, tmp2));
3259 dest = gen_reg_rtx (Pmode);
3260 emit_insn (gen_add3_insn (dest, tmp1, tp));
3263 case TLS_MODEL_LOCAL_EXEC:
3264 tmp1 = mips_get_tp ();
3265 offset = mips_unspec_address (loc, SYMBOL_TPREL);
3266 if (mips_split_p[SYMBOL_TPREL])
3268 tmp2 = mips_unspec_offset_high (NULL, tmp1, loc, SYMBOL_TPREL);
3269 dest = gen_rtx_LO_SUM (Pmode, tmp2, offset);
3272 dest = expand_binop (Pmode, add_optab, tmp1, offset,
3273 0, 0, OPTAB_DIRECT);
3282 /* Implement "TARGET = __builtin_mips_get_fcsr ()" for MIPS16,
3286 mips16_expand_get_fcsr (rtx target)
3288 if (!mips16_get_fcsr_stub)
3289 mips16_get_fcsr_stub = new mips16_get_fcsr_one_only_stub ();
3290 rtx fn = mips16_stub_call_address (mips16_get_fcsr_stub);
3291 emit_insn (PMODE_INSN (gen_mips_get_fcsr_mips16, (fn)));
3292 emit_move_insn (target, gen_rtx_REG (SImode, GET_FCSR_REGNUM));
3295 /* Implement __builtin_mips_set_fcsr (TARGET) for MIPS16, using a stub. */
3298 mips16_expand_set_fcsr (rtx newval)
3300 if (!mips16_set_fcsr_stub)
3301 mips16_set_fcsr_stub = new mips16_set_fcsr_one_only_stub ();
3302 rtx fn = mips16_stub_call_address (mips16_set_fcsr_stub);
3303 emit_move_insn (gen_rtx_REG (SImode, SET_FCSR_REGNUM), newval);
3304 emit_insn (PMODE_INSN (gen_mips_set_fcsr_mips16, (fn)));
3307 /* If X is not a valid address for mode MODE, force it into a register. */
3310 mips_force_address (rtx x, enum machine_mode mode)
3312 if (!mips_legitimate_address_p (mode, x, false))
3313 x = force_reg (Pmode, x);
3317 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
3318 be legitimized in a way that the generic machinery might not expect,
3319 return a new address, otherwise return NULL. MODE is the mode of
3320 the memory being accessed. */
3323 mips_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3324 enum machine_mode mode)
3327 HOST_WIDE_INT offset;
3329 if (mips_tls_symbol_p (x))
3330 return mips_legitimize_tls_address (x);
3332 /* See if the address can split into a high part and a LO_SUM. */
3333 if (mips_split_symbol (NULL, x, mode, &addr))
3334 return mips_force_address (addr, mode);
3336 /* Handle BASE + OFFSET using mips_add_offset. */
3337 mips_split_plus (x, &base, &offset);
3340 if (!mips_valid_base_register_p (base, mode, false))
3341 base = copy_to_mode_reg (Pmode, base);
3342 addr = mips_add_offset (NULL, base, offset);
3343 return mips_force_address (addr, mode);
3349 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3352 mips_move_integer (rtx temp, rtx dest, unsigned HOST_WIDE_INT value)
3354 struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
3355 enum machine_mode mode;
3356 unsigned int i, num_ops;
3359 mode = GET_MODE (dest);
3360 num_ops = mips_build_integer (codes, value);
3362 /* Apply each binary operation to X. Invariant: X is a legitimate
3363 source operand for a SET pattern. */
3364 x = GEN_INT (codes[0].value);
3365 for (i = 1; i < num_ops; i++)
3367 if (!can_create_pseudo_p ())
3369 emit_insn (gen_rtx_SET (VOIDmode, temp, x));
3373 x = force_reg (mode, x);
3374 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value));
3377 emit_insn (gen_rtx_SET (VOIDmode, dest, x));
3380 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3381 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3385 mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
3389 /* Split moves of big integers into smaller pieces. */
3390 if (splittable_const_int_operand (src, mode))
3392 mips_move_integer (dest, dest, INTVAL (src));
3396 /* Split moves of symbolic constants into high/low pairs. */
3397 if (mips_split_symbol (dest, src, MAX_MACHINE_MODE, &src))
3399 emit_insn (gen_rtx_SET (VOIDmode, dest, src));
3403 /* Generate the appropriate access sequences for TLS symbols. */
3404 if (mips_tls_symbol_p (src))
3406 mips_emit_move (dest, mips_legitimize_tls_address (src));
3410 /* If we have (const (plus symbol offset)), and that expression cannot
3411 be forced into memory, load the symbol first and add in the offset.
3412 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3413 forced into memory, as it usually produces better code. */
3414 split_const (src, &base, &offset);
3415 if (offset != const0_rtx
3416 && (targetm.cannot_force_const_mem (mode, src)
3417 || (!TARGET_MIPS16 && can_create_pseudo_p ())))
3419 base = mips_force_temporary (dest, base);
3420 mips_emit_move (dest, mips_add_offset (NULL, base, INTVAL (offset)));
3424 src = force_const_mem (mode, src);
3426 /* When using explicit relocs, constant pool references are sometimes
3427 not legitimate addresses. */
3428 mips_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0));
3429 mips_emit_move (dest, src);
3432 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3433 sequence that is valid. */
3436 mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
3438 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
3440 mips_emit_move (dest, force_reg (mode, src));
3444 /* We need to deal with constants that would be legitimate
3445 immediate_operands but aren't legitimate move_operands. */
3446 if (CONSTANT_P (src) && !move_operand (src, mode))
3448 mips_legitimize_const_move (mode, dest, src);
3449 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src));
3455 /* Return true if value X in context CONTEXT is a small-data address
3456 that can be rewritten as a LO_SUM. */
3459 mips_rewrite_small_data_p (rtx x, enum mips_symbol_context context)
3461 enum mips_symbol_type symbol_type;
3463 return (mips_lo_relocs[SYMBOL_GP_RELATIVE]
3464 && !mips_split_p[SYMBOL_GP_RELATIVE]
3465 && mips_symbolic_constant_p (x, context, &symbol_type)
3466 && symbol_type == SYMBOL_GP_RELATIVE);
3469 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3470 containing MEM, or null if none. */
3473 mips_small_data_pattern_1 (rtx *loc, void *data)
3475 enum mips_symbol_context context;
3477 /* Ignore things like "g" constraints in asms. We make no particular
3478 guarantee about which symbolic constants are acceptable as asm operands
3479 versus which must be forced into a GPR. */
3480 if (GET_CODE (*loc) == LO_SUM || GET_CODE (*loc) == ASM_OPERANDS)
3485 if (for_each_rtx (&XEXP (*loc, 0), mips_small_data_pattern_1, *loc))
3490 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3491 return mips_rewrite_small_data_p (*loc, context);
3494 /* Return true if OP refers to small data symbols directly, not through
3498 mips_small_data_pattern_p (rtx op)
3500 return for_each_rtx (&op, mips_small_data_pattern_1, NULL);
3503 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3504 DATA is the containing MEM, or null if none. */
3507 mips_rewrite_small_data_1 (rtx *loc, void *data)
3509 enum mips_symbol_context context;
3513 for_each_rtx (&XEXP (*loc, 0), mips_rewrite_small_data_1, *loc);
3517 context = data ? SYMBOL_CONTEXT_MEM : SYMBOL_CONTEXT_LEA;
3518 if (mips_rewrite_small_data_p (*loc, context))
3519 *loc = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, *loc);
3521 if (GET_CODE (*loc) == LO_SUM)
3527 /* Rewrite instruction pattern PATTERN so that it refers to small data
3528 using explicit relocations. */
3531 mips_rewrite_small_data (rtx pattern)
3533 pattern = copy_insn (pattern);
3534 for_each_rtx (&pattern, mips_rewrite_small_data_1, NULL);
3538 /* The cost of loading values from the constant pool. It should be
3539 larger than the cost of any constant we want to synthesize inline. */
3540 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3542 /* Return the cost of X when used as an operand to the MIPS16 instruction
3543 that implements CODE. Return -1 if there is no such instruction, or if
3544 X is not a valid immediate operand for it. */
3547 mips16_constant_cost (int code, HOST_WIDE_INT x)
3554 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3555 other shifts are extended. The shift patterns truncate the shift
3556 count to the right size, so there are no out-of-range values. */
3557 if (IN_RANGE (x, 1, 8))
3559 return COSTS_N_INSNS (1);
3562 if (IN_RANGE (x, -128, 127))
3564 if (SMALL_OPERAND (x))
3565 return COSTS_N_INSNS (1);
3569 /* Like LE, but reject the always-true case. */
3573 /* We add 1 to the immediate and use SLT. */
3576 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3579 if (IN_RANGE (x, 0, 255))
3581 if (SMALL_OPERAND_UNSIGNED (x))
3582 return COSTS_N_INSNS (1);
3587 /* Equality comparisons with 0 are cheap. */
3597 /* Return true if there is a non-MIPS16 instruction that implements CODE
3598 and if that instruction accepts X as an immediate operand. */
3601 mips_immediate_operand_p (int code, HOST_WIDE_INT x)
3608 /* All shift counts are truncated to a valid constant. */
3613 /* Likewise rotates, if the target supports rotates at all. */
3619 /* These instructions take 16-bit unsigned immediates. */
3620 return SMALL_OPERAND_UNSIGNED (x);
3625 /* These instructions take 16-bit signed immediates. */
3626 return SMALL_OPERAND (x);
3632 /* The "immediate" forms of these instructions are really
3633 implemented as comparisons with register 0. */
3638 /* Likewise, meaning that the only valid immediate operand is 1. */
3642 /* We add 1 to the immediate and use SLT. */
3643 return SMALL_OPERAND (x + 1);
3646 /* Likewise SLTU, but reject the always-true case. */
3647 return SMALL_OPERAND (x + 1) && x + 1 != 0;
3651 /* The bit position and size are immediate operands. */
3652 return ISA_HAS_EXT_INS;
3655 /* By default assume that $0 can be used for 0. */
3660 /* Return the cost of binary operation X, given that the instruction
3661 sequence for a word-sized or smaller operation has cost SINGLE_COST
3662 and that the sequence of a double-word operation has cost DOUBLE_COST.
3663 If SPEED is true, optimize for speed otherwise optimize for size. */
3666 mips_binary_cost (rtx x, int single_cost, int double_cost, bool speed)
3670 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2)
3675 + set_src_cost (XEXP (x, 0), speed)
3676 + rtx_cost (XEXP (x, 1), GET_CODE (x), 1, speed));
3679 /* Return the cost of floating-point multiplications of mode MODE. */
3682 mips_fp_mult_cost (enum machine_mode mode)
3684 return mode == DFmode ? mips_cost->fp_mult_df : mips_cost->fp_mult_sf;
3687 /* Return the cost of floating-point divisions of mode MODE. */
3690 mips_fp_div_cost (enum machine_mode mode)
3692 return mode == DFmode ? mips_cost->fp_div_df : mips_cost->fp_div_sf;
3695 /* Return the cost of sign-extending OP to mode MODE, not including the
3696 cost of OP itself. */
3699 mips_sign_extend_cost (enum machine_mode mode, rtx op)
3702 /* Extended loads are as cheap as unextended ones. */
3705 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3706 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3709 if (ISA_HAS_SEB_SEH || GENERATE_MIPS16E)
3710 /* We can use SEB or SEH. */
3711 return COSTS_N_INSNS (1);
3713 /* We need to use a shift left and a shift right. */
3714 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3717 /* Return the cost of zero-extending OP to mode MODE, not including the
3718 cost of OP itself. */
3721 mips_zero_extend_cost (enum machine_mode mode, rtx op)
3724 /* Extended loads are as cheap as unextended ones. */
3727 if (TARGET_64BIT && mode == DImode && GET_MODE (op) == SImode)
3728 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3729 return COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 2);
3731 if (GENERATE_MIPS16E)
3732 /* We can use ZEB or ZEH. */
3733 return COSTS_N_INSNS (1);
3736 /* We need to load 0xff or 0xffff into a register and use AND. */
3737 return COSTS_N_INSNS (GET_MODE (op) == QImode ? 2 : 3);
3739 /* We can use ANDI. */
3740 return COSTS_N_INSNS (1);
3743 /* Return the cost of moving between two registers of mode MODE,
3744 assuming that the move will be in pieces of at most UNITS bytes. */
3747 mips_set_reg_reg_piece_cost (enum machine_mode mode, unsigned int units)
3749 return COSTS_N_INSNS ((GET_MODE_SIZE (mode) + units - 1) / units);
3752 /* Return the cost of moving between two registers of mode MODE. */
3755 mips_set_reg_reg_cost (enum machine_mode mode)
3757 switch (GET_MODE_CLASS (mode))
3760 return mips_set_reg_reg_piece_cost (mode, GET_MODE_SIZE (CCmode));
3763 case MODE_COMPLEX_FLOAT:
3764 case MODE_VECTOR_FLOAT:
3765 if (TARGET_HARD_FLOAT)
3766 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_HWFPVALUE);
3770 return mips_set_reg_reg_piece_cost (mode, UNITS_PER_WORD);
3774 /* Implement TARGET_RTX_COSTS. */
3777 mips_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
3778 int *total, bool speed)
3780 enum machine_mode mode = GET_MODE (x);
3781 bool float_mode_p = FLOAT_MODE_P (mode);
3785 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3786 appear in the instruction stream, and the cost of a comparison is
3787 really the cost of the branch or scc condition. At the time of
3788 writing, GCC only uses an explicit outer COMPARE code when optabs
3789 is testing whether a constant is expensive enough to force into a
3790 register. We want optabs to pass such constants through the MIPS
3791 expanders instead, so make all constants very cheap here. */
3792 if (outer_code == COMPARE)
3794 gcc_assert (CONSTANT_P (x));
3802 /* Treat *clear_upper32-style ANDs as having zero cost in the
3803 second operand. The cost is entirely in the first operand.
3805 ??? This is needed because we would otherwise try to CSE
3806 the constant operand. Although that's the right thing for
3807 instructions that continue to be a register operation throughout
3808 compilation, it is disastrous for instructions that could
3809 later be converted into a memory operation. */
3811 && outer_code == AND
3812 && UINTVAL (x) == 0xffffffff)
3820 cost = mips16_constant_cost (outer_code, INTVAL (x));
3829 /* When not optimizing for size, we care more about the cost
3830 of hot code, and hot code is often in a loop. If a constant
3831 operand needs to be forced into a register, we will often be
3832 able to hoist the constant load out of the loop, so the load
3833 should not contribute to the cost. */
3834 if (speed || mips_immediate_operand_p (outer_code, INTVAL (x)))
3846 if (force_to_mem_operand (x, VOIDmode))
3848 *total = COSTS_N_INSNS (1);
3851 cost = mips_const_insns (x);
3854 /* If the constant is likely to be stored in a GPR, SETs of
3855 single-insn constants are as cheap as register sets; we
3856 never want to CSE them.
3858 Don't reduce the cost of storing a floating-point zero in
3859 FPRs. If we have a zero in an FPR for other reasons, we
3860 can get better cfg-cleanup and delayed-branch results by
3861 using it consistently, rather than using $0 sometimes and
3862 an FPR at other times. Also, moves between floating-point
3863 registers are sometimes cheaper than (D)MTC1 $0. */
3865 && outer_code == SET
3866 && !(float_mode_p && TARGET_HARD_FLOAT))
3868 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3869 want to CSE the constant itself. It is usually better to
3870 have N copies of the last operation in the sequence and one
3871 shared copy of the other operations. (Note that this is
3872 not true for MIPS16 code, where the final operation in the
3873 sequence is often an extended instruction.)
3875 Also, if we have a CONST_INT, we don't know whether it is
3876 for a word or doubleword operation, so we cannot rely on
3877 the result of mips_build_integer. */
3878 else if (!TARGET_MIPS16
3879 && (outer_code == SET || mode == VOIDmode))
3881 *total = COSTS_N_INSNS (cost);
3884 /* The value will need to be fetched from the constant pool. */
3885 *total = CONSTANT_POOL_COST;
3889 /* If the address is legitimate, return the number of
3890 instructions it needs. */
3892 cost = mips_address_insns (addr, mode, true);
3895 *total = COSTS_N_INSNS (cost + 1);
3898 /* Check for a scaled indexed address. */
3899 if (mips_lwxs_address_p (addr)
3900 || mips_lx_address_p (addr, mode))
3902 *total = COSTS_N_INSNS (2);
3905 /* Otherwise use the default handling. */
3909 *total = COSTS_N_INSNS (6);
3913 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1);
3917 /* Check for a *clear_upper32 pattern and treat it like a zero
3918 extension. See the pattern's comment for details. */
3921 && CONST_INT_P (XEXP (x, 1))
3922 && UINTVAL (XEXP (x, 1)) == 0xffffffff)
3924 *total = (mips_zero_extend_cost (mode, XEXP (x, 0))
3925 + set_src_cost (XEXP (x, 0), speed));
3928 if (ISA_HAS_CINS && CONST_INT_P (XEXP (x, 1)))
3930 rtx op = XEXP (x, 0);
3931 if (GET_CODE (op) == ASHIFT
3932 && CONST_INT_P (XEXP (op, 1))
3933 && mask_low_and_shift_p (mode, XEXP (x, 1), XEXP (op, 1), 32))
3935 *total = COSTS_N_INSNS (1) + set_src_cost (XEXP (op, 0), speed);
3939 /* (AND (NOT op0) (NOT op1) is a nor operation that can be done in
3940 a single instruction. */
3942 && GET_CODE (XEXP (x, 0)) == NOT
3943 && GET_CODE (XEXP (x, 1)) == NOT)
3945 cost = GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1;
3946 *total = (COSTS_N_INSNS (cost)
3947 + set_src_cost (XEXP (XEXP (x, 0), 0), speed)
3948 + set_src_cost (XEXP (XEXP (x, 1), 0), speed));
3956 /* Double-word operations use two single-word operations. */
3957 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3966 if (CONSTANT_P (XEXP (x, 1)))
3967 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3970 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3976 *total = mips_cost->fp_add;
3978 *total = COSTS_N_INSNS (4);
3982 /* Low-part immediates need an extended MIPS16 instruction. */
3983 *total = (COSTS_N_INSNS (TARGET_MIPS16 ? 2 : 1)
3984 + set_src_cost (XEXP (x, 0), speed));
3999 /* Branch comparisons have VOIDmode, so use the first operand's
4001 mode = GET_MODE (XEXP (x, 0));
4002 if (FLOAT_MODE_P (mode))
4004 *total = mips_cost->fp_add;
4007 *total = mips_binary_cost (x, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
4013 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
4014 && TARGET_FUSED_MADD
4015 && !HONOR_NANS (mode)
4016 && !HONOR_SIGNED_ZEROS (mode))
4018 /* See if we can use NMADD or NMSUB. See mips.md for the
4019 associated patterns. */
4020 rtx op0 = XEXP (x, 0);
4021 rtx op1 = XEXP (x, 1);
4022 if (GET_CODE (op0) == MULT && GET_CODE (XEXP (op0, 0)) == NEG)
4024 *total = (mips_fp_mult_cost (mode)
4025 + set_src_cost (XEXP (XEXP (op0, 0), 0), speed)
4026 + set_src_cost (XEXP (op0, 1), speed)
4027 + set_src_cost (op1, speed));
4030 if (GET_CODE (op1) == MULT)
4032 *total = (mips_fp_mult_cost (mode)
4033 + set_src_cost (op0, speed)
4034 + set_src_cost (XEXP (op1, 0), speed)
4035 + set_src_cost (XEXP (op1, 1), speed));
4044 /* If this is part of a MADD or MSUB, treat the PLUS as
4046 if ((ISA_HAS_FP_MADD4_MSUB4 || ISA_HAS_FP_MADD3_MSUB3)
4047 && TARGET_FUSED_MADD
4048 && GET_CODE (XEXP (x, 0)) == MULT)
4051 *total = mips_cost->fp_add;
4055 /* Double-word operations require three single-word operations and
4056 an SLTU. The MIPS16 version then needs to move the result of
4057 the SLTU from $24 to a MIPS16 register. */
4058 *total = mips_binary_cost (x, COSTS_N_INSNS (1),
4059 COSTS_N_INSNS (TARGET_MIPS16 ? 5 : 4),
4065 && (ISA_HAS_NMADD4_NMSUB4 || ISA_HAS_NMADD3_NMSUB3)
4066 && TARGET_FUSED_MADD
4067 && !HONOR_NANS (mode)
4068 && HONOR_SIGNED_ZEROS (mode))
4070 /* See if we can use NMADD or NMSUB. See mips.md for the
4071 associated patterns. */
4072 rtx op = XEXP (x, 0);
4073 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS)
4074 && GET_CODE (XEXP (op, 0)) == MULT)
4076 *total = (mips_fp_mult_cost (mode)
4077 + set_src_cost (XEXP (XEXP (op, 0), 0), speed)
4078 + set_src_cost (XEXP (XEXP (op, 0), 1), speed)
4079 + set_src_cost (XEXP (op, 1), speed));
4085 *total = mips_cost->fp_add;
4087 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1);
4092 *total = mips_fp_mult_cost (mode);
4093 else if (mode == DImode && !TARGET_64BIT)
4094 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
4095 where the mulsidi3 always includes an MFHI and an MFLO. */
4097 ? mips_cost->int_mult_si * 3 + 6
4098 : COSTS_N_INSNS (ISA_HAS_MUL3 ? 7 : 9));
4100 *total = COSTS_N_INSNS (ISA_HAS_MUL3 ? 1 : 2) + 1;
4101 else if (mode == DImode)
4102 *total = mips_cost->int_mult_di;
4104 *total = mips_cost->int_mult_si;
4108 /* Check for a reciprocal. */
4110 && ISA_HAS_FP_RECIP_RSQRT (mode)
4111 && flag_unsafe_math_optimizations
4112 && XEXP (x, 0) == CONST1_RTX (mode))
4114 if (outer_code == SQRT || GET_CODE (XEXP (x, 1)) == SQRT)
4115 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
4116 division as being free. */
4117 *total = set_src_cost (XEXP (x, 1), speed);
4119 *total = (mips_fp_div_cost (mode)
4120 + set_src_cost (XEXP (x, 1), speed));
4129 *total = mips_fp_div_cost (mode);
4138 /* It is our responsibility to make division by a power of 2
4139 as cheap as 2 register additions if we want the division
4140 expanders to be used for such operations; see the setting
4141 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
4142 should always produce shorter code than using
4143 expand_sdiv2_pow2. */
4145 && CONST_INT_P (XEXP (x, 1))
4146 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
4148 *total = COSTS_N_INSNS (2) + set_src_cost (XEXP (x, 0), speed);
4151 *total = COSTS_N_INSNS (mips_idiv_insns ());
4153 else if (mode == DImode)
4154 *total = mips_cost->int_div_di;
4156 *total = mips_cost->int_div_si;
4160 *total = mips_sign_extend_cost (mode, XEXP (x, 0));
4164 if (outer_code == SET
4166 && (GET_CODE (XEXP (x, 0)) == TRUNCATE
4167 || GET_CODE (XEXP (x, 0)) == SUBREG)
4168 && GET_MODE (XEXP (x, 0)) == QImode
4169 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
4171 *total = set_src_cost (XEXP (XEXP (x, 0), 0), speed);
4174 *total = mips_zero_extend_cost (mode, XEXP (x, 0));
4178 case UNSIGNED_FLOAT:
4181 case FLOAT_TRUNCATE:
4182 *total = mips_cost->fp_add;
4186 if (register_operand (SET_DEST (x), VOIDmode)
4187 && reg_or_0_operand (SET_SRC (x), VOIDmode))
4189 *total = mips_set_reg_reg_cost (GET_MODE (SET_DEST (x)));
4199 /* Implement TARGET_ADDRESS_COST. */
4202 mips_address_cost (rtx addr, enum machine_mode mode,
4203 addr_space_t as ATTRIBUTE_UNUSED,
4204 bool speed ATTRIBUTE_UNUSED)
4206 return mips_address_insns (addr, mode, false);
4209 /* Information about a single instruction in a multi-instruction
4211 struct mips_multi_member {
4212 /* True if this is a label, false if it is code. */
4215 /* The output_asm_insn format of the instruction. */
4218 /* The operands to the instruction. */
4219 rtx operands[MAX_RECOG_OPERANDS];
4221 typedef struct mips_multi_member mips_multi_member;
4223 /* The instructions that make up the current multi-insn sequence. */
4224 static vec<mips_multi_member> mips_multi_members;
4226 /* How many instructions (as opposed to labels) are in the current
4227 multi-insn sequence. */
4228 static unsigned int mips_multi_num_insns;
4230 /* Start a new multi-insn sequence. */
4233 mips_multi_start (void)
4235 mips_multi_members.truncate (0);
4236 mips_multi_num_insns = 0;
4239 /* Add a new, uninitialized member to the current multi-insn sequence. */
4241 static struct mips_multi_member *
4242 mips_multi_add (void)
4244 mips_multi_member empty;
4245 return mips_multi_members.safe_push (empty);
4248 /* Add a normal insn with the given asm format to the current multi-insn
4249 sequence. The other arguments are a null-terminated list of operands. */
4252 mips_multi_add_insn (const char *format, ...)
4254 struct mips_multi_member *member;
4259 member = mips_multi_add ();
4260 member->is_label_p = false;
4261 member->format = format;
4262 va_start (ap, format);
4264 while ((op = va_arg (ap, rtx)))
4265 member->operands[i++] = op;
4267 mips_multi_num_insns++;
4270 /* Add the given label definition to the current multi-insn sequence.
4271 The definition should include the colon. */
4274 mips_multi_add_label (const char *label)
4276 struct mips_multi_member *member;
4278 member = mips_multi_add ();
4279 member->is_label_p = true;
4280 member->format = label;
4283 /* Return the index of the last member of the current multi-insn sequence. */
4286 mips_multi_last_index (void)
4288 return mips_multi_members.length () - 1;
4291 /* Add a copy of an existing instruction to the current multi-insn
4292 sequence. I is the index of the instruction that should be copied. */
4295 mips_multi_copy_insn (unsigned int i)
4297 struct mips_multi_member *member;
4299 member = mips_multi_add ();
4300 memcpy (member, &mips_multi_members[i], sizeof (*member));
4301 gcc_assert (!member->is_label_p);
4304 /* Change the operand of an existing instruction in the current
4305 multi-insn sequence. I is the index of the instruction,
4306 OP is the index of the operand, and X is the new value. */
4309 mips_multi_set_operand (unsigned int i, unsigned int op, rtx x)
4311 mips_multi_members[i].operands[op] = x;
4314 /* Write out the asm code for the current multi-insn sequence. */
4317 mips_multi_write (void)
4319 struct mips_multi_member *member;
4322 FOR_EACH_VEC_ELT (mips_multi_members, i, member)
4323 if (member->is_label_p)
4324 fprintf (asm_out_file, "%s\n", member->format);
4326 output_asm_insn (member->format, member->operands);
4329 /* Return one word of double-word value OP, taking into account the fixed
4330 endianness of certain registers. HIGH_P is true to select the high part,
4331 false to select the low part. */
4334 mips_subword (rtx op, bool high_p)
4336 unsigned int byte, offset;
4337 enum machine_mode mode;
4339 mode = GET_MODE (op);
4340 if (mode == VOIDmode)
4341 mode = TARGET_64BIT ? TImode : DImode;
4343 if (TARGET_BIG_ENDIAN ? !high_p : high_p)
4344 byte = UNITS_PER_WORD;
4348 if (FP_REG_RTX_P (op))
4350 /* Paired FPRs are always ordered little-endian. */
4351 offset = (UNITS_PER_WORD < UNITS_PER_HWFPVALUE ? high_p : byte != 0);
4352 return gen_rtx_REG (word_mode, REGNO (op) + offset);
4356 return mips_rewrite_small_data (adjust_address (op, word_mode, byte));
4358 return simplify_gen_subreg (word_mode, op, mode, byte);
4361 /* Return true if SRC should be moved into DEST using "MULT $0, $0".
4362 SPLIT_TYPE is the condition under which moves should be split. */
4365 mips_mult_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4367 return ((split_type != SPLIT_FOR_SPEED
4368 || mips_tuning_info.fast_mult_zero_zero_p)
4369 && src == const0_rtx
4371 && GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
4372 && (ISA_HAS_DSP_MULT
4373 ? ACC_REG_P (REGNO (dest))
4374 : MD_REG_P (REGNO (dest))));
4377 /* Return true if a move from SRC to DEST should be split into two.
4378 SPLIT_TYPE describes the split condition. */
4381 mips_split_move_p (rtx dest, rtx src, enum mips_split_type split_type)
4383 /* Check whether the move can be done using some variant of MULT $0,$0. */
4384 if (mips_mult_move_p (dest, src, split_type))
4387 /* FPR-to-FPR moves can be done in a single instruction, if they're
4389 unsigned int size = GET_MODE_SIZE (GET_MODE (dest));
4390 if (size == 8 && FP_REG_RTX_P (src) && FP_REG_RTX_P (dest))
4393 /* Check for floating-point loads and stores. */
4394 if (size == 8 && ISA_HAS_LDC1_SDC1)
4396 if (FP_REG_RTX_P (dest) && MEM_P (src))
4398 if (FP_REG_RTX_P (src) && MEM_P (dest))
4402 /* Otherwise split all multiword moves. */
4403 return size > UNITS_PER_WORD;
4406 /* Split a move from SRC to DEST, given that mips_split_move_p holds.
4407 SPLIT_TYPE describes the split condition. */
4410 mips_split_move (rtx dest, rtx src, enum mips_split_type split_type)
4414 gcc_checking_assert (mips_split_move_p (dest, src, split_type));
4415 if (FP_REG_RTX_P (dest) || FP_REG_RTX_P (src))
4417 if (!TARGET_64BIT && GET_MODE (dest) == DImode)
4418 emit_insn (gen_move_doubleword_fprdi (dest, src));
4419 else if (!TARGET_64BIT && GET_MODE (dest) == DFmode)
4420 emit_insn (gen_move_doubleword_fprdf (dest, src));
4421 else if (!TARGET_64BIT && GET_MODE (dest) == V2SFmode)
4422 emit_insn (gen_move_doubleword_fprv2sf (dest, src));
4423 else if (!TARGET_64BIT && GET_MODE (dest) == V2SImode)
4424 emit_insn (gen_move_doubleword_fprv2si (dest, src));
4425 else if (!TARGET_64BIT && GET_MODE (dest) == V4HImode)
4426 emit_insn (gen_move_doubleword_fprv4hi (dest, src));
4427 else if (!TARGET_64BIT && GET_MODE (dest) == V8QImode)
4428 emit_insn (gen_move_doubleword_fprv8qi (dest, src));
4429 else if (TARGET_64BIT && GET_MODE (dest) == TFmode)
4430 emit_insn (gen_move_doubleword_fprtf (dest, src));
4434 else if (REG_P (dest) && REGNO (dest) == MD_REG_FIRST)
4436 low_dest = mips_subword (dest, false);
4437 mips_emit_move (low_dest, mips_subword (src, false));
4439 emit_insn (gen_mthidi_ti (dest, mips_subword (src, true), low_dest));
4441 emit_insn (gen_mthisi_di (dest, mips_subword (src, true), low_dest));
4443 else if (REG_P (src) && REGNO (src) == MD_REG_FIRST)
4445 mips_emit_move (mips_subword (dest, false), mips_subword (src, false));
4447 emit_insn (gen_mfhidi_ti (mips_subword (dest, true), src));
4449 emit_insn (gen_mfhisi_di (mips_subword (dest, true), src));
4453 /* The operation can be split into two normal moves. Decide in
4454 which order to do them. */
4455 low_dest = mips_subword (dest, false);
4456 if (REG_P (low_dest)
4457 && reg_overlap_mentioned_p (low_dest, src))
4459 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4460 mips_emit_move (low_dest, mips_subword (src, false));
4464 mips_emit_move (low_dest, mips_subword (src, false));
4465 mips_emit_move (mips_subword (dest, true), mips_subword (src, true));
4470 /* Return the split type for instruction INSN. */
4472 static enum mips_split_type
4473 mips_insn_split_type (rtx insn)
4475 basic_block bb = BLOCK_FOR_INSN (insn);
4478 if (optimize_bb_for_speed_p (bb))
4479 return SPLIT_FOR_SPEED;
4481 return SPLIT_FOR_SIZE;
4483 /* Once CFG information has been removed, we should trust the optimization
4484 decisions made by previous passes and only split where necessary. */
4485 return SPLIT_IF_NECESSARY;
4488 /* Return true if a move from SRC to DEST in INSN should be split. */
4491 mips_split_move_insn_p (rtx dest, rtx src, rtx insn)
4493 return mips_split_move_p (dest, src, mips_insn_split_type (insn));
4496 /* Split a move from SRC to DEST in INSN, given that mips_split_move_insn_p
4500 mips_split_move_insn (rtx dest, rtx src, rtx insn)
4502 mips_split_move (dest, src, mips_insn_split_type (insn));
4505 /* Return the appropriate instructions to move SRC into DEST. Assume
4506 that SRC is operand 1 and DEST is operand 0. */
4509 mips_output_move (rtx dest, rtx src)
4511 enum rtx_code dest_code, src_code;
4512 enum machine_mode mode;
4513 enum mips_symbol_type symbol_type;
4516 dest_code = GET_CODE (dest);
4517 src_code = GET_CODE (src);
4518 mode = GET_MODE (dest);
4519 dbl_p = (GET_MODE_SIZE (mode) == 8);
4521 if (mips_split_move_p (dest, src, SPLIT_IF_NECESSARY))
4524 if ((src_code == REG && GP_REG_P (REGNO (src)))
4525 || (!TARGET_MIPS16 && src == CONST0_RTX (mode)))
4527 if (dest_code == REG)
4529 if (GP_REG_P (REGNO (dest)))
4530 return "move\t%0,%z1";
4532 if (mips_mult_move_p (dest, src, SPLIT_IF_NECESSARY))
4534 if (ISA_HAS_DSP_MULT)
4535 return "mult\t%q0,%.,%.";
4537 return "mult\t%.,%.";
4540 /* Moves to HI are handled by special .md insns. */
4541 if (REGNO (dest) == LO_REGNUM)
4544 if (DSP_ACC_REG_P (REGNO (dest)))
4546 static char retval[] = "mt__\t%z1,%q0";
4548 retval[2] = reg_names[REGNO (dest)][4];
4549 retval[3] = reg_names[REGNO (dest)][5];
4553 if (FP_REG_P (REGNO (dest)))
4554 return dbl_p ? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4556 if (ALL_COP_REG_P (REGNO (dest)))
4558 static char retval[] = "dmtc_\t%z1,%0";
4560 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4561 return dbl_p ? retval : retval + 1;
4564 if (dest_code == MEM)
4565 switch (GET_MODE_SIZE (mode))
4567 case 1: return "sb\t%z1,%0";
4568 case 2: return "sh\t%z1,%0";
4569 case 4: return "sw\t%z1,%0";
4570 case 8: return "sd\t%z1,%0";
4573 if (dest_code == REG && GP_REG_P (REGNO (dest)))
4575 if (src_code == REG)
4577 /* Moves from HI are handled by special .md insns. */
4578 if (REGNO (src) == LO_REGNUM)
4580 /* When generating VR4120 or VR4130 code, we use MACC and
4581 DMACC instead of MFLO. This avoids both the normal
4582 MIPS III HI/LO hazards and the errata related to
4585 return dbl_p ? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4589 if (DSP_ACC_REG_P (REGNO (src)))
4591 static char retval[] = "mf__\t%0,%q1";
4593 retval[2] = reg_names[REGNO (src)][4];
4594 retval[3] = reg_names[REGNO (src)][5];
4598 if (FP_REG_P (REGNO (src)))
4599 return dbl_p ? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4601 if (ALL_COP_REG_P (REGNO (src)))
4603 static char retval[] = "dmfc_\t%0,%1";
4605 retval[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4606 return dbl_p ? retval : retval + 1;
4610 if (src_code == MEM)
4611 switch (GET_MODE_SIZE (mode))
4613 case 1: return "lbu\t%0,%1";
4614 case 2: return "lhu\t%0,%1";
4615 case 4: return "lw\t%0,%1";
4616 case 8: return "ld\t%0,%1";
4619 if (src_code == CONST_INT)
4621 /* Don't use the X format for the operand itself, because that
4622 will give out-of-range numbers for 64-bit hosts and 32-bit
4625 return "li\t%0,%1\t\t\t# %X1";
4627 if (SMALL_OPERAND_UNSIGNED (INTVAL (src)))
4630 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src)))
4634 if (src_code == HIGH)
4635 return TARGET_MIPS16 ? "#" : "lui\t%0,%h1";
4637 if (CONST_GP_P (src))
4638 return "move\t%0,%1";
4640 if (mips_symbolic_constant_p (src, SYMBOL_CONTEXT_LEA, &symbol_type)
4641 && mips_lo_relocs[symbol_type] != 0)
4643 /* A signed 16-bit constant formed by applying a relocation
4644 operator to a symbolic address. */
4645 gcc_assert (!mips_split_p[symbol_type]);
4646 return "li\t%0,%R1";
4649 if (symbolic_operand (src, VOIDmode))
4651 gcc_assert (TARGET_MIPS16
4652 ? TARGET_MIPS16_TEXT_LOADS
4653 : !TARGET_EXPLICIT_RELOCS);
4654 return dbl_p ? "dla\t%0,%1" : "la\t%0,%1";
4657 if (src_code == REG && FP_REG_P (REGNO (src)))
4659 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4661 if (GET_MODE (dest) == V2SFmode)
4662 return "mov.ps\t%0,%1";
4664 return dbl_p ? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4667 if (dest_code == MEM)
4668 return dbl_p ? "sdc1\t%1,%0" : "swc1\t%1,%0";
4670 if (dest_code == REG && FP_REG_P (REGNO (dest)))
4672 if (src_code == MEM)
4673 return dbl_p ? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4675 if (dest_code == REG && ALL_COP_REG_P (REGNO (dest)) && src_code == MEM)
4677 static char retval[] = "l_c_\t%0,%1";
4679 retval[1] = (dbl_p ? 'd' : 'w');
4680 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest));
4683 if (dest_code == MEM && src_code == REG && ALL_COP_REG_P (REGNO (src)))
4685 static char retval[] = "s_c_\t%1,%0";
4687 retval[1] = (dbl_p ? 'd' : 'w');
4688 retval[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src));
4694 /* Return true if CMP1 is a suitable second operand for integer ordering
4695 test CODE. See also the *sCC patterns in mips.md. */
4698 mips_int_order_operand_ok_p (enum rtx_code code, rtx cmp1)
4704 return reg_or_0_operand (cmp1, VOIDmode);
4708 return !TARGET_MIPS16 && cmp1 == const1_rtx;
4712 return arith_operand (cmp1, VOIDmode);
4715 return sle_operand (cmp1, VOIDmode);
4718 return sleu_operand (cmp1, VOIDmode);
4725 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4726 integer ordering test *CODE, or if an equivalent combination can
4727 be formed by adjusting *CODE and *CMP1. When returning true, update
4728 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4732 mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1,
4733 enum machine_mode mode)
4735 HOST_WIDE_INT plus_one;
4737 if (mips_int_order_operand_ok_p (*code, *cmp1))
4740 if (CONST_INT_P (*cmp1))
4744 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4745 if (INTVAL (*cmp1) < plus_one)
4748 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4754 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode);
4758 *cmp1 = force_reg (mode, GEN_INT (plus_one));
4769 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4770 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4771 is nonnull, it's OK to set TARGET to the inverse of the result and
4772 flip *INVERT_PTR instead. */
4775 mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr,
4776 rtx target, rtx cmp0, rtx cmp1)
4778 enum machine_mode mode;
4780 /* First see if there is a MIPS instruction that can do this operation.
4781 If not, try doing the same for the inverse operation. If that also
4782 fails, force CMP1 into a register and try again. */
4783 mode = GET_MODE (cmp0);
4784 if (mips_canonicalize_int_order_test (&code, &cmp1, mode))
4785 mips_emit_binary (code, target, cmp0, cmp1);
4788 enum rtx_code inv_code = reverse_condition (code);
4789 if (!mips_canonicalize_int_order_test (&inv_code, &cmp1, mode))
4791 cmp1 = force_reg (mode, cmp1);
4792 mips_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1);
4794 else if (invert_ptr == 0)
4798 inv_target = mips_force_binary (GET_MODE (target),
4799 inv_code, cmp0, cmp1);
4800 mips_emit_binary (XOR, target, inv_target, const1_rtx);
4804 *invert_ptr = !*invert_ptr;
4805 mips_emit_binary (inv_code, target, cmp0, cmp1);
4810 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4811 The register will have the same mode as CMP0. */
4814 mips_zero_if_equal (rtx cmp0, rtx cmp1)
4816 if (cmp1 == const0_rtx)
4819 if (uns_arith_operand (cmp1, VOIDmode))
4820 return expand_binop (GET_MODE (cmp0), xor_optab,
4821 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4823 return expand_binop (GET_MODE (cmp0), sub_optab,
4824 cmp0, cmp1, 0, 0, OPTAB_DIRECT);
4827 /* Convert *CODE into a code that can be used in a floating-point
4828 scc instruction (C.cond.fmt). Return true if the values of
4829 the condition code registers will be inverted, with 0 indicating
4830 that the condition holds. */
4833 mips_reversed_fp_cond (enum rtx_code *code)
4840 *code = reverse_condition_maybe_unordered (*code);
4848 /* Allocate a floating-point condition-code register of mode MODE.
4850 These condition code registers are used for certain kinds
4851 of compound operation, such as compare and branches, vconds,
4852 and built-in functions. At expand time, their use is entirely
4853 controlled by MIPS-specific code and is entirely internal
4854 to these compound operations.
4856 We could (and did in the past) expose condition-code values
4857 as pseudo registers and leave the register allocator to pick
4858 appropriate registers. The problem is that it is not practically
4859 possible for the rtl optimizers to guarantee that no spills will
4860 be needed, even when AVOID_CCMODE_COPIES is defined. We would
4861 therefore need spill and reload sequences to handle the worst case.
4863 Although such sequences do exist, they are very expensive and are
4864 not something we'd want to use. This is especially true of CCV2 and
4865 CCV4, where all the shuffling would greatly outweigh whatever benefit
4866 the vectorization itself provides.
4868 The main benefit of having more than one condition-code register
4869 is to allow the pipelining of operations, especially those involving
4870 comparisons and conditional moves. We don't really expect the
4871 registers to be live for long periods, and certainly never want
4872 them to be live across calls.
4874 Also, there should be no penalty attached to using all the available
4875 registers. They are simply bits in the same underlying FPU control
4878 We therefore expose the hardware registers from the outset and use
4879 a simple round-robin allocation scheme. */
4882 mips_allocate_fcc (enum machine_mode mode)
4884 unsigned int regno, count;
4886 gcc_assert (TARGET_HARD_FLOAT && ISA_HAS_8CC);
4890 else if (mode == CCV2mode)
4892 else if (mode == CCV4mode)
4897 cfun->machine->next_fcc += -cfun->machine->next_fcc & (count - 1);
4898 if (cfun->machine->next_fcc > ST_REG_LAST - ST_REG_FIRST)
4899 cfun->machine->next_fcc = 0;
4900 regno = ST_REG_FIRST + cfun->machine->next_fcc;
4901 cfun->machine->next_fcc += count;
4902 return gen_rtx_REG (mode, regno);
4905 /* Convert a comparison into something that can be used in a branch or
4906 conditional move. On entry, *OP0 and *OP1 are the values being
4907 compared and *CODE is the code used to compare them.
4909 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4910 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4911 otherwise any standard branch condition can be used. The standard branch
4914 - EQ or NE between two registers.
4915 - any comparison between a register and zero. */
4918 mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p)
4923 if (GET_MODE_CLASS (GET_MODE (*op0)) == MODE_INT)
4925 if (!need_eq_ne_p && *op1 == const0_rtx)
4927 else if (*code == EQ || *code == NE)
4931 *op0 = mips_zero_if_equal (cmp_op0, cmp_op1);
4935 *op1 = force_reg (GET_MODE (cmp_op0), cmp_op1);
4939 /* The comparison needs a separate scc instruction. Store the
4940 result of the scc in *OP0 and compare it against zero. */
4941 bool invert = false;
4942 *op0 = gen_reg_rtx (GET_MODE (cmp_op0));
4943 mips_emit_int_order_test (*code, &invert, *op0, cmp_op0, cmp_op1);
4944 *code = (invert ? EQ : NE);
4948 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0)))
4950 *op0 = gen_rtx_REG (CCDSPmode, CCDSP_CC_REGNUM);
4951 mips_emit_binary (*code, *op0, cmp_op0, cmp_op1);
4957 enum rtx_code cmp_code;
4959 /* Floating-point tests use a separate C.cond.fmt comparison to
4960 set a condition code register. The branch or conditional move
4961 will then compare that register against zero.
4963 Set CMP_CODE to the code of the comparison instruction and
4964 *CODE to the code that the branch or move should use. */
4966 *code = mips_reversed_fp_cond (&cmp_code) ? EQ : NE;
4968 ? mips_allocate_fcc (CCmode)
4969 : gen_rtx_REG (CCmode, FPSW_REGNUM));
4971 mips_emit_binary (cmp_code, *op0, cmp_op0, cmp_op1);
4975 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4976 and OPERAND[3]. Store the result in OPERANDS[0].
4978 On 64-bit targets, the mode of the comparison and target will always be
4979 SImode, thus possibly narrower than that of the comparison's operands. */
4982 mips_expand_scc (rtx operands[])
4984 rtx target = operands[0];
4985 enum rtx_code code = GET_CODE (operands[1]);
4986 rtx op0 = operands[2];
4987 rtx op1 = operands[3];
4989 gcc_assert (GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT);
4991 if (code == EQ || code == NE)
4994 && reg_imm10_operand (op1, GET_MODE (op1)))
4995 mips_emit_binary (code, target, op0, op1);
4998 rtx zie = mips_zero_if_equal (op0, op1);
4999 mips_emit_binary (code, target, zie, const0_rtx);
5003 mips_emit_int_order_test (code, 0, target, op0, op1);
5006 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
5007 CODE and jump to OPERANDS[3] if the condition holds. */
5010 mips_expand_conditional_branch (rtx *operands)
5012 enum rtx_code code = GET_CODE (operands[0]);
5013 rtx op0 = operands[1];
5014 rtx op1 = operands[2];
5017 mips_emit_compare (&code, &op0, &op1, TARGET_MIPS16);
5018 condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
5019 emit_jump_insn (gen_condjump (condition, operands[3]));
5024 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
5025 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
5028 mips_expand_vcondv2sf (rtx dest, rtx true_src, rtx false_src,
5029 enum rtx_code cond, rtx cmp_op0, rtx cmp_op1)
5034 reversed_p = mips_reversed_fp_cond (&cond);
5035 cmp_result = mips_allocate_fcc (CCV2mode);
5036 emit_insn (gen_scc_ps (cmp_result,
5037 gen_rtx_fmt_ee (cond, VOIDmode, cmp_op0, cmp_op1)));
5039 emit_insn (gen_mips_cond_move_tf_ps (dest, false_src, true_src,
5042 emit_insn (gen_mips_cond_move_tf_ps (dest, true_src, false_src,
5046 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
5047 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
5050 mips_expand_conditional_move (rtx *operands)
5053 enum rtx_code code = GET_CODE (operands[1]);
5054 rtx op0 = XEXP (operands[1], 0);
5055 rtx op1 = XEXP (operands[1], 1);
5057 mips_emit_compare (&code, &op0, &op1, true);
5058 cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1);
5059 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
5060 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), cond,
5061 operands[2], operands[3])));
5064 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
5067 mips_expand_conditional_trap (rtx comparison)
5070 enum machine_mode mode;
5073 /* MIPS conditional trap instructions don't have GT or LE flavors,
5074 so we must swap the operands and convert to LT and GE respectively. */
5075 code = GET_CODE (comparison);
5082 code = swap_condition (code);
5083 op0 = XEXP (comparison, 1);
5084 op1 = XEXP (comparison, 0);
5088 op0 = XEXP (comparison, 0);
5089 op1 = XEXP (comparison, 1);
5093 mode = GET_MODE (XEXP (comparison, 0));
5094 op0 = force_reg (mode, op0);
5095 if (!arith_operand (op1, mode))
5096 op1 = force_reg (mode, op1);
5098 emit_insn (gen_rtx_TRAP_IF (VOIDmode,
5099 gen_rtx_fmt_ee (code, mode, op0, op1),
5103 /* Initialize *CUM for a call to a function of type FNTYPE. */
5106 mips_init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype)
5108 memset (cum, 0, sizeof (*cum));
5109 cum->prototype = (fntype && prototype_p (fntype));
5110 cum->gp_reg_found = (cum->prototype && stdarg_p (fntype));
5113 /* Fill INFO with information about a single argument. CUM is the
5114 cumulative state for earlier arguments. MODE is the mode of this
5115 argument and TYPE is its type (if known). NAMED is true if this
5116 is a named (fixed) argument rather than a variable one. */
5119 mips_get_arg_info (struct mips_arg_info *info, const CUMULATIVE_ARGS *cum,
5120 enum machine_mode mode, const_tree type, bool named)
5122 bool doubleword_aligned_p;
5123 unsigned int num_bytes, num_words, max_regs;
5125 /* Work out the size of the argument. */
5126 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5127 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5129 /* Decide whether it should go in a floating-point register, assuming
5130 one is free. Later code checks for availability.
5132 The checks against UNITS_PER_FPVALUE handle the soft-float and
5133 single-float cases. */
5137 /* The EABI conventions have traditionally been defined in terms
5138 of TYPE_MODE, regardless of the actual type. */
5139 info->fpr_p = ((GET_MODE_CLASS (mode) == MODE_FLOAT
5140 || mode == V2SFmode)
5141 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5146 /* Only leading floating-point scalars are passed in
5147 floating-point registers. We also handle vector floats the same
5148 say, which is OK because they are not covered by the standard ABI. */
5149 info->fpr_p = (!cum->gp_reg_found
5150 && cum->arg_number < 2
5152 || SCALAR_FLOAT_TYPE_P (type)
5153 || VECTOR_FLOAT_TYPE_P (type))
5154 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5155 || mode == V2SFmode)
5156 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
5161 /* Scalar, complex and vector floating-point types are passed in
5162 floating-point registers, as long as this is a named rather
5163 than a variable argument. */
5164 info->fpr_p = (named
5165 && (type == 0 || FLOAT_TYPE_P (type))
5166 && (GET_MODE_CLASS (mode) == MODE_FLOAT
5167 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5168 || mode == V2SFmode)
5169 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FPVALUE);
5171 /* ??? According to the ABI documentation, the real and imaginary
5172 parts of complex floats should be passed in individual registers.
5173 The real and imaginary parts of stack arguments are supposed
5174 to be contiguous and there should be an extra word of padding
5177 This has two problems. First, it makes it impossible to use a
5178 single "void *" va_list type, since register and stack arguments
5179 are passed differently. (At the time of writing, MIPSpro cannot
5180 handle complex float varargs correctly.) Second, it's unclear
5181 what should happen when there is only one register free.
5183 For now, we assume that named complex floats should go into FPRs
5184 if there are two FPRs free, otherwise they should be passed in the
5185 same way as a struct containing two floats. */
5187 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5188 && GET_MODE_UNIT_SIZE (mode) < UNITS_PER_FPVALUE)
5190 if (cum->num_gprs >= MAX_ARGS_IN_REGISTERS - 1)
5191 info->fpr_p = false;
5201 /* See whether the argument has doubleword alignment. */
5202 doubleword_aligned_p = (mips_function_arg_boundary (mode, type)
5205 /* Set REG_OFFSET to the register count we're interested in.
5206 The EABI allocates the floating-point registers separately,
5207 but the other ABIs allocate them like integer registers. */
5208 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p
5212 /* Advance to an even register if the argument is doubleword-aligned. */
5213 if (doubleword_aligned_p)
5214 info->reg_offset += info->reg_offset & 1;
5216 /* Work out the offset of a stack argument. */
5217 info->stack_offset = cum->stack_words;
5218 if (doubleword_aligned_p)
5219 info->stack_offset += info->stack_offset & 1;
5221 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset;
5223 /* Partition the argument between registers and stack. */
5224 info->reg_words = MIN (num_words, max_regs);
5225 info->stack_words = num_words - info->reg_words;
5228 /* INFO describes a register argument that has the normal format for the
5229 argument's mode. Return the register it uses, assuming that FPRs are
5230 available if HARD_FLOAT_P. */
5233 mips_arg_regno (const struct mips_arg_info *info, bool hard_float_p)
5235 if (!info->fpr_p || !hard_float_p)
5236 return GP_ARG_FIRST + info->reg_offset;
5237 else if (mips_abi == ABI_32 && TARGET_DOUBLE_FLOAT && info->reg_offset > 0)
5238 /* In o32, the second argument is always passed in $f14
5239 for TARGET_DOUBLE_FLOAT, regardless of whether the
5240 first argument was a word or doubleword. */
5241 return FP_ARG_FIRST + 2;
5243 return FP_ARG_FIRST + info->reg_offset;
5246 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
5249 mips_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
5251 return !TARGET_OLDABI;
5254 /* Implement TARGET_FUNCTION_ARG. */
5257 mips_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
5258 const_tree type, bool named)
5260 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5261 struct mips_arg_info info;
5263 /* We will be called with a mode of VOIDmode after the last argument
5264 has been seen. Whatever we return will be passed to the call expander.
5265 If we need a MIPS16 fp_code, return a REG with the code stored as
5267 if (mode == VOIDmode)
5269 if (TARGET_MIPS16 && cum->fp_code != 0)
5270 return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
5275 mips_get_arg_info (&info, cum, mode, type, named);
5277 /* Return straight away if the whole argument is passed on the stack. */
5278 if (info.reg_offset == MAX_ARGS_IN_REGISTERS)
5281 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
5282 contains a double in its entirety, then that 64-bit chunk is passed
5283 in a floating-point register. */
5285 && TARGET_HARD_FLOAT
5288 && TREE_CODE (type) == RECORD_TYPE
5289 && TYPE_SIZE_UNIT (type)
5290 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type)))
5294 /* First check to see if there is any such field. */
5295 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
5296 if (TREE_CODE (field) == FIELD_DECL
5297 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5298 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
5299 && tree_fits_shwi_p (bit_position (field))
5300 && int_bit_position (field) % BITS_PER_WORD == 0)
5305 /* Now handle the special case by returning a PARALLEL
5306 indicating where each 64-bit chunk goes. INFO.REG_WORDS
5307 chunks are passed in registers. */
5309 HOST_WIDE_INT bitpos;
5312 /* assign_parms checks the mode of ENTRY_PARM, so we must
5313 use the actual mode here. */
5314 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (info.reg_words));
5317 field = TYPE_FIELDS (type);
5318 for (i = 0; i < info.reg_words; i++)
5322 for (; field; field = DECL_CHAIN (field))
5323 if (TREE_CODE (field) == FIELD_DECL
5324 && int_bit_position (field) >= bitpos)
5328 && int_bit_position (field) == bitpos
5329 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field))
5330 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
5331 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i);
5333 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i);
5336 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5337 GEN_INT (bitpos / BITS_PER_UNIT));
5339 bitpos += BITS_PER_WORD;
5345 /* Handle the n32/n64 conventions for passing complex floating-point
5346 arguments in FPR pairs. The real part goes in the lower register
5347 and the imaginary part goes in the upper register. */
5350 && GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5353 enum machine_mode inner;
5356 inner = GET_MODE_INNER (mode);
5357 regno = FP_ARG_FIRST + info.reg_offset;
5358 if (info.reg_words * UNITS_PER_WORD == GET_MODE_SIZE (inner))
5360 /* Real part in registers, imaginary part on stack. */
5361 gcc_assert (info.stack_words == info.reg_words);
5362 return gen_rtx_REG (inner, regno);
5366 gcc_assert (info.stack_words == 0);
5367 real = gen_rtx_EXPR_LIST (VOIDmode,
5368 gen_rtx_REG (inner, regno),
5370 imag = gen_rtx_EXPR_LIST (VOIDmode,
5372 regno + info.reg_words / 2),
5373 GEN_INT (GET_MODE_SIZE (inner)));
5374 return gen_rtx_PARALLEL (mode, gen_rtvec (2, real, imag));
5378 return gen_rtx_REG (mode, mips_arg_regno (&info, TARGET_HARD_FLOAT));
5381 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5384 mips_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
5385 const_tree type, bool named)
5387 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
5388 struct mips_arg_info info;
5390 mips_get_arg_info (&info, cum, mode, type, named);
5393 cum->gp_reg_found = true;
5395 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
5396 an explanation of what this code does. It assumes that we're using
5397 either the o32 or the o64 ABI, both of which pass at most 2 arguments
5399 if (cum->arg_number < 2 && info.fpr_p)
5400 cum->fp_code += (mode == SFmode ? 1 : 2) << (cum->arg_number * 2);
5402 /* Advance the register count. This has the effect of setting
5403 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5404 argument required us to skip the final GPR and pass the whole
5405 argument on the stack. */
5406 if (mips_abi != ABI_EABI || !info.fpr_p)
5407 cum->num_gprs = info.reg_offset + info.reg_words;
5408 else if (info.reg_words > 0)
5409 cum->num_fprs += MAX_FPRS_PER_FMT;
5411 /* Advance the stack word count. */
5412 if (info.stack_words > 0)
5413 cum->stack_words = info.stack_offset + info.stack_words;
5418 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5421 mips_arg_partial_bytes (cumulative_args_t cum,
5422 enum machine_mode mode, tree type, bool named)
5424 struct mips_arg_info info;
5426 mips_get_arg_info (&info, get_cumulative_args (cum), mode, type, named);
5427 return info.stack_words > 0 ? info.reg_words * UNITS_PER_WORD : 0;
5430 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5431 least PARM_BOUNDARY bits of alignment, but will be given anything up
5432 to STACK_BOUNDARY bits if the type requires it. */
5435 mips_function_arg_boundary (enum machine_mode mode, const_tree type)
5437 unsigned int alignment;
5439 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode);
5440 if (alignment < PARM_BOUNDARY)
5441 alignment = PARM_BOUNDARY;
5442 if (alignment > STACK_BOUNDARY)
5443 alignment = STACK_BOUNDARY;
5447 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5448 upward rather than downward. In other words, return true if the
5449 first byte of the stack slot has useful data, false if the last
5453 mips_pad_arg_upward (enum machine_mode mode, const_tree type)
5455 /* On little-endian targets, the first byte of every stack argument
5456 is passed in the first byte of the stack slot. */
5457 if (!BYTES_BIG_ENDIAN)
5460 /* Otherwise, integral types are padded downward: the last byte of a
5461 stack argument is passed in the last byte of the stack slot. */
5463 ? (INTEGRAL_TYPE_P (type)
5464 || POINTER_TYPE_P (type)
5465 || FIXED_POINT_TYPE_P (type))
5466 : (SCALAR_INT_MODE_P (mode)
5467 || ALL_SCALAR_FIXED_POINT_MODE_P (mode)))
5470 /* Big-endian o64 pads floating-point arguments downward. */
5471 if (mips_abi == ABI_O64)
5472 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5475 /* Other types are padded upward for o32, o64, n32 and n64. */
5476 if (mips_abi != ABI_EABI)
5479 /* Arguments smaller than a stack slot are padded downward. */
5480 if (mode != BLKmode)
5481 return GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY;
5483 return int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT);
5486 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5487 if the least significant byte of the register has useful data. Return
5488 the opposite if the most significant byte does. */
5491 mips_pad_reg_upward (enum machine_mode mode, tree type)
5493 /* No shifting is required for floating-point arguments. */
5494 if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
5495 return !BYTES_BIG_ENDIAN;
5497 /* Otherwise, apply the same padding to register arguments as we do
5498 to stack arguments. */
5499 return mips_pad_arg_upward (mode, type);
5502 /* Return nonzero when an argument must be passed by reference. */
5505 mips_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED,
5506 enum machine_mode mode, const_tree type,
5507 bool named ATTRIBUTE_UNUSED)
5509 if (mips_abi == ABI_EABI)
5513 /* ??? How should SCmode be handled? */
5514 if (mode == DImode || mode == DFmode
5515 || mode == DQmode || mode == UDQmode
5516 || mode == DAmode || mode == UDAmode)
5519 size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
5520 return size == -1 || size > UNITS_PER_WORD;
5524 /* If we have a variable-sized parameter, we have no choice. */
5525 return targetm.calls.must_pass_in_stack (mode, type);
5529 /* Implement TARGET_CALLEE_COPIES. */
5532 mips_callee_copies (cumulative_args_t cum ATTRIBUTE_UNUSED,
5533 enum machine_mode mode ATTRIBUTE_UNUSED,
5534 const_tree type ATTRIBUTE_UNUSED, bool named)
5536 return mips_abi == ABI_EABI && named;
5539 /* See whether VALTYPE is a record whose fields should be returned in
5540 floating-point registers. If so, return the number of fields and
5541 list them in FIELDS (which should have two elements). Return 0
5544 For n32 & n64, a structure with one or two fields is returned in
5545 floating-point registers as long as every field has a floating-point
5549 mips_fpr_return_fields (const_tree valtype, tree *fields)
5557 if (TREE_CODE (valtype) != RECORD_TYPE)
5561 for (field = TYPE_FIELDS (valtype); field != 0; field = DECL_CHAIN (field))
5563 if (TREE_CODE (field) != FIELD_DECL)
5566 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field)))
5572 fields[i++] = field;
5577 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5578 a value in the most significant part of $2/$3 if:
5580 - the target is big-endian;
5582 - the value has a structure or union type (we generalize this to
5583 cover aggregates from other languages too); and
5585 - the structure is not returned in floating-point registers. */
5588 mips_return_in_msb (const_tree valtype)
5592 return (TARGET_NEWABI
5593 && TARGET_BIG_ENDIAN
5594 && AGGREGATE_TYPE_P (valtype)
5595 && mips_fpr_return_fields (valtype, fields) == 0);
5598 /* Return true if the function return value MODE will get returned in a
5599 floating-point register. */
5602 mips_return_mode_in_fpr_p (enum machine_mode mode)
5604 return ((GET_MODE_CLASS (mode) == MODE_FLOAT
5606 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5607 && GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_HWFPVALUE);
5610 /* Return the representation of an FPR return register when the
5611 value being returned in FP_RETURN has mode VALUE_MODE and the
5612 return type itself has mode TYPE_MODE. On NewABI targets,
5613 the two modes may be different for structures like:
5615 struct __attribute__((packed)) foo { float f; }
5617 where we return the SFmode value of "f" in FP_RETURN, but where
5618 the structure itself has mode BLKmode. */
5621 mips_return_fpr_single (enum machine_mode type_mode,
5622 enum machine_mode value_mode)
5626 x = gen_rtx_REG (value_mode, FP_RETURN);
5627 if (type_mode != value_mode)
5629 x = gen_rtx_EXPR_LIST (VOIDmode, x, const0_rtx);
5630 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x));
5635 /* Return a composite value in a pair of floating-point registers.
5636 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5637 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5640 For n32 & n64, $f0 always holds the first value and $f2 the second.
5641 Otherwise the values are packed together as closely as possible. */
5644 mips_return_fpr_pair (enum machine_mode mode,
5645 enum machine_mode mode1, HOST_WIDE_INT offset1,
5646 enum machine_mode mode2, HOST_WIDE_INT offset2)
5650 inc = (TARGET_NEWABI ? 2 : MAX_FPRS_PER_FMT);
5651 return gen_rtx_PARALLEL
5654 gen_rtx_EXPR_LIST (VOIDmode,
5655 gen_rtx_REG (mode1, FP_RETURN),
5657 gen_rtx_EXPR_LIST (VOIDmode,
5658 gen_rtx_REG (mode2, FP_RETURN + inc),
5659 GEN_INT (offset2))));
5663 /* Implement TARGET_FUNCTION_VALUE and TARGET_LIBCALL_VALUE.
5664 For normal calls, VALTYPE is the return type and MODE is VOIDmode.
5665 For libcalls, VALTYPE is null and MODE is the mode of the return value. */
5668 mips_function_value_1 (const_tree valtype, const_tree fn_decl_or_type,
5669 enum machine_mode mode)
5677 if (fn_decl_or_type && DECL_P (fn_decl_or_type))
5678 func = fn_decl_or_type;
5682 mode = TYPE_MODE (valtype);
5683 unsigned_p = TYPE_UNSIGNED (valtype);
5685 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5686 return values, promote the mode here too. */
5687 mode = promote_function_mode (valtype, mode, &unsigned_p, func, 1);
5689 /* Handle structures whose fields are returned in $f0/$f2. */
5690 switch (mips_fpr_return_fields (valtype, fields))
5693 return mips_return_fpr_single (mode,
5694 TYPE_MODE (TREE_TYPE (fields[0])));
5697 return mips_return_fpr_pair (mode,
5698 TYPE_MODE (TREE_TYPE (fields[0])),
5699 int_byte_position (fields[0]),
5700 TYPE_MODE (TREE_TYPE (fields[1])),
5701 int_byte_position (fields[1]));
5704 /* If a value is passed in the most significant part of a register, see
5705 whether we have to round the mode up to a whole number of words. */
5706 if (mips_return_in_msb (valtype))
5708 HOST_WIDE_INT size = int_size_in_bytes (valtype);
5709 if (size % UNITS_PER_WORD != 0)
5711 size += UNITS_PER_WORD - size % UNITS_PER_WORD;
5712 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
5716 /* For EABI, the class of return register depends entirely on MODE.
5717 For example, "struct { some_type x; }" and "union { some_type x; }"
5718 are returned in the same way as a bare "some_type" would be.
5719 Other ABIs only use FPRs for scalar, complex or vector types. */
5720 if (mips_abi != ABI_EABI && !FLOAT_TYPE_P (valtype))
5721 return gen_rtx_REG (mode, GP_RETURN);
5726 /* Handle long doubles for n32 & n64. */
5728 return mips_return_fpr_pair (mode,
5730 DImode, GET_MODE_SIZE (mode) / 2);
5732 if (mips_return_mode_in_fpr_p (mode))
5734 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5735 return mips_return_fpr_pair (mode,
5736 GET_MODE_INNER (mode), 0,
5737 GET_MODE_INNER (mode),
5738 GET_MODE_SIZE (mode) / 2);
5740 return gen_rtx_REG (mode, FP_RETURN);
5744 return gen_rtx_REG (mode, GP_RETURN);
5747 /* Implement TARGET_FUNCTION_VALUE. */
5750 mips_function_value (const_tree valtype, const_tree fn_decl_or_type,
5751 bool outgoing ATTRIBUTE_UNUSED)
5753 return mips_function_value_1 (valtype, fn_decl_or_type, VOIDmode);
5756 /* Implement TARGET_LIBCALL_VALUE. */
5759 mips_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
5761 return mips_function_value_1 (NULL_TREE, NULL_TREE, mode);
5764 /* Implement TARGET_FUNCTION_VALUE_REGNO_P.
5766 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
5767 Currently, R2 and F0 are only implemented here (C has no complex type). */
5770 mips_function_value_regno_p (const unsigned int regno)
5772 if (regno == GP_RETURN
5773 || regno == FP_RETURN
5774 || (LONG_DOUBLE_TYPE_SIZE == 128
5775 && FP_RETURN != GP_RETURN
5776 && regno == FP_RETURN + 2))
5782 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5783 all BLKmode objects are returned in memory. Under the n32, n64
5784 and embedded ABIs, small structures are returned in a register.
5785 Objects with varying size must still be returned in memory, of
5789 mips_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED)
5791 return (TARGET_OLDABI
5792 ? TYPE_MODE (type) == BLKmode
5793 : !IN_RANGE (int_size_in_bytes (type), 0, 2 * UNITS_PER_WORD));
5796 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5799 mips_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode,
5800 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5803 CUMULATIVE_ARGS local_cum;
5804 int gp_saved, fp_saved;
5806 /* The caller has advanced CUM up to, but not beyond, the last named
5807 argument. Advance a local copy of CUM past the last "real" named
5808 argument, to find out how many registers are left over. */
5809 local_cum = *get_cumulative_args (cum);
5810 mips_function_arg_advance (pack_cumulative_args (&local_cum), mode, type,
5813 /* Found out how many registers we need to save. */
5814 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs;
5815 fp_saved = (EABI_FLOAT_VARARGS_P
5816 ? MAX_ARGS_IN_REGISTERS - local_cum.num_fprs
5825 ptr = plus_constant (Pmode, virtual_incoming_args_rtx,
5826 REG_PARM_STACK_SPACE (cfun->decl)
5827 - gp_saved * UNITS_PER_WORD);
5828 mem = gen_frame_mem (BLKmode, ptr);
5829 set_mem_alias_set (mem, get_varargs_alias_set ());
5831 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
5836 /* We can't use move_block_from_reg, because it will use
5838 enum machine_mode mode;
5841 /* Set OFF to the offset from virtual_incoming_args_rtx of
5842 the first float register. The FP save area lies below
5843 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5844 off = (-gp_saved * UNITS_PER_WORD) & -UNITS_PER_FPVALUE;
5845 off -= fp_saved * UNITS_PER_FPREG;
5847 mode = TARGET_SINGLE_FLOAT ? SFmode : DFmode;
5849 for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS;
5850 i += MAX_FPRS_PER_FMT)
5854 ptr = plus_constant (Pmode, virtual_incoming_args_rtx, off);
5855 mem = gen_frame_mem (mode, ptr);
5856 set_mem_alias_set (mem, get_varargs_alias_set ());
5857 mips_emit_move (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
5858 off += UNITS_PER_HWFPVALUE;
5862 if (REG_PARM_STACK_SPACE (cfun->decl) == 0)
5863 cfun->machine->varargs_size = (gp_saved * UNITS_PER_WORD
5864 + fp_saved * UNITS_PER_FPREG);
5867 /* Implement TARGET_BUILTIN_VA_LIST. */
5870 mips_build_builtin_va_list (void)
5872 if (EABI_FLOAT_VARARGS_P)
5874 /* We keep 3 pointers, and two offsets.
5876 Two pointers are to the overflow area, which starts at the CFA.
5877 One of these is constant, for addressing into the GPR save area
5878 below it. The other is advanced up the stack through the
5881 The third pointer is to the bottom of the GPR save area.
5882 Since the FPR save area is just below it, we can address
5883 FPR slots off this pointer.
5885 We also keep two one-byte offsets, which are to be subtracted
5886 from the constant pointers to yield addresses in the GPR and
5887 FPR save areas. These are downcounted as float or non-float
5888 arguments are used, and when they get to zero, the argument
5889 must be obtained from the overflow region. */
5890 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff, f_res, record;
5893 record = lang_hooks.types.make_type (RECORD_TYPE);
5895 f_ovfl = build_decl (BUILTINS_LOCATION,
5896 FIELD_DECL, get_identifier ("__overflow_argptr"),
5898 f_gtop = build_decl (BUILTINS_LOCATION,
5899 FIELD_DECL, get_identifier ("__gpr_top"),
5901 f_ftop = build_decl (BUILTINS_LOCATION,
5902 FIELD_DECL, get_identifier ("__fpr_top"),
5904 f_goff = build_decl (BUILTINS_LOCATION,
5905 FIELD_DECL, get_identifier ("__gpr_offset"),
5906 unsigned_char_type_node);
5907 f_foff = build_decl (BUILTINS_LOCATION,
5908 FIELD_DECL, get_identifier ("__fpr_offset"),
5909 unsigned_char_type_node);
5910 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5911 warn on every user file. */
5912 index = build_int_cst (NULL_TREE, GET_MODE_SIZE (ptr_mode) - 2 - 1);
5913 array = build_array_type (unsigned_char_type_node,
5914 build_index_type (index));
5915 f_res = build_decl (BUILTINS_LOCATION,
5916 FIELD_DECL, get_identifier ("__reserved"), array);
5918 DECL_FIELD_CONTEXT (f_ovfl) = record;
5919 DECL_FIELD_CONTEXT (f_gtop) = record;
5920 DECL_FIELD_CONTEXT (f_ftop) = record;
5921 DECL_FIELD_CONTEXT (f_goff) = record;
5922 DECL_FIELD_CONTEXT (f_foff) = record;
5923 DECL_FIELD_CONTEXT (f_res) = record;
5925 TYPE_FIELDS (record) = f_ovfl;
5926 DECL_CHAIN (f_ovfl) = f_gtop;
5927 DECL_CHAIN (f_gtop) = f_ftop;
5928 DECL_CHAIN (f_ftop) = f_goff;
5929 DECL_CHAIN (f_goff) = f_foff;
5930 DECL_CHAIN (f_foff) = f_res;
5932 layout_type (record);
5936 /* Otherwise, we use 'void *'. */
5937 return ptr_type_node;
5940 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5943 mips_va_start (tree valist, rtx nextarg)
5945 if (EABI_FLOAT_VARARGS_P)
5947 const CUMULATIVE_ARGS *cum;
5948 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
5949 tree ovfl, gtop, ftop, goff, foff;
5951 int gpr_save_area_size;
5952 int fpr_save_area_size;
5955 cum = &crtl->args.info;
5957 = (MAX_ARGS_IN_REGISTERS - cum->num_gprs) * UNITS_PER_WORD;
5959 = (MAX_ARGS_IN_REGISTERS - cum->num_fprs) * UNITS_PER_FPREG;
5961 f_ovfl = TYPE_FIELDS (va_list_type_node);
5962 f_gtop = DECL_CHAIN (f_ovfl);
5963 f_ftop = DECL_CHAIN (f_gtop);
5964 f_goff = DECL_CHAIN (f_ftop);
5965 f_foff = DECL_CHAIN (f_goff);
5967 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
5969 gtop = build3 (COMPONENT_REF, TREE_TYPE (f_gtop), valist, f_gtop,
5971 ftop = build3 (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop,
5973 goff = build3 (COMPONENT_REF, TREE_TYPE (f_goff), valist, f_goff,
5975 foff = build3 (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff,
5978 /* Emit code to initialize OVFL, which points to the next varargs
5979 stack argument. CUM->STACK_WORDS gives the number of stack
5980 words used by named arguments. */
5981 t = make_tree (TREE_TYPE (ovfl), virtual_incoming_args_rtx);
5982 if (cum->stack_words > 0)
5983 t = fold_build_pointer_plus_hwi (t, cum->stack_words * UNITS_PER_WORD);
5984 t = build2 (MODIFY_EXPR, TREE_TYPE (ovfl), ovfl, t);
5985 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5987 /* Emit code to initialize GTOP, the top of the GPR save area. */
5988 t = make_tree (TREE_TYPE (gtop), virtual_incoming_args_rtx);
5989 t = build2 (MODIFY_EXPR, TREE_TYPE (gtop), gtop, t);
5990 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5992 /* Emit code to initialize FTOP, the top of the FPR save area.
5993 This address is gpr_save_area_bytes below GTOP, rounded
5994 down to the next fp-aligned boundary. */
5995 t = make_tree (TREE_TYPE (ftop), virtual_incoming_args_rtx);
5996 fpr_offset = gpr_save_area_size + UNITS_PER_FPVALUE - 1;
5997 fpr_offset &= -UNITS_PER_FPVALUE;
5999 t = fold_build_pointer_plus_hwi (t, -fpr_offset);
6000 t = build2 (MODIFY_EXPR, TREE_TYPE (ftop), ftop, t);
6001 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6003 /* Emit code to initialize GOFF, the offset from GTOP of the
6004 next GPR argument. */
6005 t = build2 (MODIFY_EXPR, TREE_TYPE (goff), goff,
6006 build_int_cst (TREE_TYPE (goff), gpr_save_area_size));
6007 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6009 /* Likewise emit code to initialize FOFF, the offset from FTOP
6010 of the next FPR argument. */
6011 t = build2 (MODIFY_EXPR, TREE_TYPE (foff), foff,
6012 build_int_cst (TREE_TYPE (foff), fpr_save_area_size));
6013 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6017 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size);
6018 std_expand_builtin_va_start (valist, nextarg);
6022 /* Like std_gimplify_va_arg_expr, but apply alignment to zero-sized
6026 mips_std_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6029 tree addr, t, type_size, rounded_size, valist_tmp;
6030 unsigned HOST_WIDE_INT align, boundary;
6033 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, false);
6035 type = build_pointer_type (type);
6037 align = PARM_BOUNDARY / BITS_PER_UNIT;
6038 boundary = targetm.calls.function_arg_boundary (TYPE_MODE (type), type);
6040 /* When we align parameter on stack for caller, if the parameter
6041 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
6042 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
6043 here with caller. */
6044 if (boundary > MAX_SUPPORTED_STACK_ALIGNMENT)
6045 boundary = MAX_SUPPORTED_STACK_ALIGNMENT;
6047 boundary /= BITS_PER_UNIT;
6049 /* Hoist the valist value into a temporary for the moment. */
6050 valist_tmp = get_initialized_tmp_var (valist, pre_p, NULL);
6052 /* va_list pointer is aligned to PARM_BOUNDARY. If argument actually
6053 requires greater alignment, we must perform dynamic alignment. */
6054 if (boundary > align)
6056 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6057 fold_build_pointer_plus_hwi (valist_tmp, boundary - 1));
6058 gimplify_and_add (t, pre_p);
6060 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist_tmp,
6061 fold_build2 (BIT_AND_EXPR, TREE_TYPE (valist),
6063 build_int_cst (TREE_TYPE (valist), -boundary)));
6064 gimplify_and_add (t, pre_p);
6069 /* If the actual alignment is less than the alignment of the type,
6070 adjust the type accordingly so that we don't assume strict alignment
6071 when dereferencing the pointer. */
6072 boundary *= BITS_PER_UNIT;
6073 if (boundary < TYPE_ALIGN (type))
6075 type = build_variant_type_copy (type);
6076 TYPE_ALIGN (type) = boundary;
6079 /* Compute the rounded size of the type. */
6080 type_size = size_in_bytes (type);
6081 rounded_size = round_up (type_size, align);
6083 /* Reduce rounded_size so it's sharable with the postqueue. */
6084 gimplify_expr (&rounded_size, pre_p, post_p, is_gimple_val, fb_rvalue);
6088 if (PAD_VARARGS_DOWN && !integer_zerop (rounded_size))
6090 /* Small args are padded downward. */
6091 t = fold_build2_loc (input_location, GT_EXPR, sizetype,
6092 rounded_size, size_int (align));
6093 t = fold_build3 (COND_EXPR, sizetype, t, size_zero_node,
6094 size_binop (MINUS_EXPR, rounded_size, type_size));
6095 addr = fold_build_pointer_plus (addr, t);
6098 /* Compute new value for AP. */
6099 t = fold_build_pointer_plus (valist_tmp, rounded_size);
6100 t = build2 (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
6101 gimplify_and_add (t, pre_p);
6103 addr = fold_convert (build_pointer_type (type), addr);
6106 addr = build_va_arg_indirect_ref (addr);
6108 return build_va_arg_indirect_ref (addr);
6111 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
6114 mips_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6120 indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6122 type = build_pointer_type (type);
6124 if (!EABI_FLOAT_VARARGS_P)
6125 addr = mips_std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6128 tree f_ovfl, f_gtop, f_ftop, f_goff, f_foff;
6129 tree ovfl, top, off, align;
6130 HOST_WIDE_INT size, rsize, osize;
6133 f_ovfl = TYPE_FIELDS (va_list_type_node);
6134 f_gtop = DECL_CHAIN (f_ovfl);
6135 f_ftop = DECL_CHAIN (f_gtop);
6136 f_goff = DECL_CHAIN (f_ftop);
6137 f_foff = DECL_CHAIN (f_goff);
6141 TOP be the top of the GPR or FPR save area;
6142 OFF be the offset from TOP of the next register;
6143 ADDR_RTX be the address of the argument;
6144 SIZE be the number of bytes in the argument type;
6145 RSIZE be the number of bytes used to store the argument
6146 when it's in the register save area; and
6147 OSIZE be the number of bytes used to store it when it's
6148 in the stack overflow area.
6150 The code we want is:
6152 1: off &= -rsize; // round down
6155 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
6160 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
6161 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
6165 [1] and [9] can sometimes be optimized away. */
6167 ovfl = build3 (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl,
6169 size = int_size_in_bytes (type);
6171 if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
6172 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
6174 top = build3 (COMPONENT_REF, TREE_TYPE (f_ftop),
6175 unshare_expr (valist), f_ftop, NULL_TREE);
6176 off = build3 (COMPONENT_REF, TREE_TYPE (f_foff),
6177 unshare_expr (valist), f_foff, NULL_TREE);
6179 /* When va_start saves FPR arguments to the stack, each slot
6180 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
6181 argument's precision. */
6182 rsize = UNITS_PER_HWFPVALUE;
6184 /* Overflow arguments are padded to UNITS_PER_WORD bytes
6185 (= PARM_BOUNDARY bits). This can be different from RSIZE
6188 (1) On 32-bit targets when TYPE is a structure such as:
6190 struct s { float f; };
6192 Such structures are passed in paired FPRs, so RSIZE
6193 will be 8 bytes. However, the structure only takes
6194 up 4 bytes of memory, so OSIZE will only be 4.
6196 (2) In combinations such as -mgp64 -msingle-float
6197 -fshort-double. Doubles passed in registers will then take
6198 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
6199 stack take up UNITS_PER_WORD bytes. */
6200 osize = MAX (GET_MODE_SIZE (TYPE_MODE (type)), UNITS_PER_WORD);
6204 top = build3 (COMPONENT_REF, TREE_TYPE (f_gtop),
6205 unshare_expr (valist), f_gtop, NULL_TREE);
6206 off = build3 (COMPONENT_REF, TREE_TYPE (f_goff),
6207 unshare_expr (valist), f_goff, NULL_TREE);
6208 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
6209 if (rsize > UNITS_PER_WORD)
6211 /* [1] Emit code for: off &= -rsize. */
6212 t = build2 (BIT_AND_EXPR, TREE_TYPE (off), unshare_expr (off),
6213 build_int_cst (TREE_TYPE (off), -rsize));
6214 gimplify_assign (unshare_expr (off), t, pre_p);
6219 /* [2] Emit code to branch if off == 0. */
6220 t = build2 (NE_EXPR, boolean_type_node, unshare_expr (off),
6221 build_int_cst (TREE_TYPE (off), 0));
6222 addr = build3 (COND_EXPR, ptr_type_node, t, NULL_TREE, NULL_TREE);
6224 /* [5] Emit code for: off -= rsize. We do this as a form of
6225 post-decrement not available to C. */
6226 t = fold_convert (TREE_TYPE (off), build_int_cst (NULL_TREE, rsize));
6227 t = build2 (POSTDECREMENT_EXPR, TREE_TYPE (off), off, t);
6229 /* [4] Emit code for:
6230 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
6231 t = fold_convert (sizetype, t);
6232 t = fold_build1 (NEGATE_EXPR, sizetype, t);
6233 t = fold_build_pointer_plus (top, t);
6234 if (BYTES_BIG_ENDIAN && rsize > size)
6235 t = fold_build_pointer_plus_hwi (t, rsize - size);
6236 COND_EXPR_THEN (addr) = t;
6238 if (osize > UNITS_PER_WORD)
6240 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
6241 t = fold_build_pointer_plus_hwi (unshare_expr (ovfl), osize - 1);
6242 u = build_int_cst (TREE_TYPE (t), -osize);
6243 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6244 align = build2 (MODIFY_EXPR, TREE_TYPE (ovfl),
6245 unshare_expr (ovfl), t);
6250 /* [10, 11] Emit code for:
6251 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
6253 u = fold_convert (TREE_TYPE (ovfl), build_int_cst (NULL_TREE, osize));
6254 t = build2 (POSTINCREMENT_EXPR, TREE_TYPE (ovfl), ovfl, u);
6255 if (BYTES_BIG_ENDIAN && osize > size)
6256 t = fold_build_pointer_plus_hwi (t, osize - size);
6258 /* String [9] and [10, 11] together. */
6260 t = build2 (COMPOUND_EXPR, TREE_TYPE (t), align, t);
6261 COND_EXPR_ELSE (addr) = t;
6263 addr = fold_convert (build_pointer_type (type), addr);
6264 addr = build_va_arg_indirect_ref (addr);
6268 addr = build_va_arg_indirect_ref (addr);
6273 /* Declare a unique, locally-binding function called NAME, then start
6277 mips_start_unique_function (const char *name)
6281 decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL,
6282 get_identifier (name),
6283 build_function_type_list (void_type_node, NULL_TREE));
6284 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL,
6285 NULL_TREE, void_type_node);
6286 TREE_PUBLIC (decl) = 1;
6287 TREE_STATIC (decl) = 1;
6289 cgraph_create_node (decl)->set_comdat_group (DECL_ASSEMBLER_NAME (decl));
6291 targetm.asm_out.unique_section (decl, 0);
6292 switch_to_section (get_named_section (decl, NULL, 0));
6294 targetm.asm_out.globalize_label (asm_out_file, name);
6295 fputs ("\t.hidden\t", asm_out_file);
6296 assemble_name (asm_out_file, name);
6297 putc ('\n', asm_out_file);
6300 /* Start a definition of function NAME. MIPS16_P indicates whether the
6301 function contains MIPS16 code. */
6304 mips_start_function_definition (const char *name, bool mips16_p)
6307 fprintf (asm_out_file, "\t.set\tmips16\n");
6309 fprintf (asm_out_file, "\t.set\tnomips16\n");
6311 if (TARGET_MICROMIPS)
6312 fprintf (asm_out_file, "\t.set\tmicromips\n");
6313 #ifdef HAVE_GAS_MICROMIPS
6315 fprintf (asm_out_file, "\t.set\tnomicromips\n");
6318 if (!flag_inhibit_size_directive)
6320 fputs ("\t.ent\t", asm_out_file);
6321 assemble_name (asm_out_file, name);
6322 fputs ("\n", asm_out_file);
6325 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, name, "function");
6327 /* Start the definition proper. */
6328 assemble_name (asm_out_file, name);
6329 fputs (":\n", asm_out_file);
6332 /* End a function definition started by mips_start_function_definition. */
6335 mips_end_function_definition (const char *name)
6337 if (!flag_inhibit_size_directive)
6339 fputs ("\t.end\t", asm_out_file);
6340 assemble_name (asm_out_file, name);
6341 fputs ("\n", asm_out_file);
6345 /* If *STUB_PTR points to a stub, output a comdat-style definition for it,
6346 then free *STUB_PTR. */
6349 mips_finish_stub (mips_one_only_stub **stub_ptr)
6351 mips_one_only_stub *stub = *stub_ptr;
6355 const char *name = stub->get_name ();
6356 mips_start_unique_function (name);
6357 mips_start_function_definition (name, false);
6358 stub->output_body ();
6359 mips_end_function_definition (name);
6364 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
6367 mips_ok_for_lazy_binding_p (rtx x)
6369 return (TARGET_USE_GOT
6370 && GET_CODE (x) == SYMBOL_REF
6371 && !SYMBOL_REF_BIND_NOW_P (x)
6372 && !mips_symbol_binds_local_p (x));
6375 /* Load function address ADDR into register DEST. TYPE is as for
6376 mips_expand_call. Return true if we used an explicit lazy-binding
6380 mips_load_call_address (enum mips_call_type type, rtx dest, rtx addr)
6382 /* If we're generating PIC, and this call is to a global function,
6383 try to allow its address to be resolved lazily. This isn't
6384 possible for sibcalls when $gp is call-saved because the value
6385 of $gp on entry to the stub would be our caller's gp, not ours. */
6386 if (TARGET_EXPLICIT_RELOCS
6387 && !(type == MIPS_CALL_SIBCALL && TARGET_CALL_SAVED_GP)
6388 && mips_ok_for_lazy_binding_p (addr))
6390 addr = mips_got_load (dest, addr, SYMBOL_GOTOFF_CALL);
6391 emit_insn (gen_rtx_SET (VOIDmode, dest, addr));
6396 mips_emit_move (dest, addr);
6401 /* Each locally-defined hard-float MIPS16 function has a local symbol
6402 associated with it. This hash table maps the function symbol (FUNC)
6403 to the local symbol (LOCAL). */
6404 struct GTY(()) mips16_local_alias {
6408 static GTY ((param_is (struct mips16_local_alias))) htab_t mips16_local_aliases;
6410 /* Hash table callbacks for mips16_local_aliases. */
6413 mips16_local_aliases_hash (const void *entry)
6415 const struct mips16_local_alias *alias;
6417 alias = (const struct mips16_local_alias *) entry;
6418 return htab_hash_string (XSTR (alias->func, 0));
6422 mips16_local_aliases_eq (const void *entry1, const void *entry2)
6424 const struct mips16_local_alias *alias1, *alias2;
6426 alias1 = (const struct mips16_local_alias *) entry1;
6427 alias2 = (const struct mips16_local_alias *) entry2;
6428 return rtx_equal_p (alias1->func, alias2->func);
6431 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
6432 Return a local alias for it, creating a new one if necessary. */
6435 mips16_local_alias (rtx func)
6437 struct mips16_local_alias *alias, tmp_alias;
6440 /* Create the hash table if this is the first call. */
6441 if (mips16_local_aliases == NULL)
6442 mips16_local_aliases = htab_create_ggc (37, mips16_local_aliases_hash,
6443 mips16_local_aliases_eq, NULL);
6445 /* Look up the function symbol, creating a new entry if need be. */
6446 tmp_alias.func = func;
6447 slot = htab_find_slot (mips16_local_aliases, &tmp_alias, INSERT);
6448 gcc_assert (slot != NULL);
6450 alias = (struct mips16_local_alias *) *slot;
6453 const char *func_name, *local_name;
6456 /* Create a new SYMBOL_REF for the local symbol. The choice of
6457 __fn_local_* is based on the __fn_stub_* names that we've
6458 traditionally used for the non-MIPS16 stub. */
6459 func_name = targetm.strip_name_encoding (XSTR (func, 0));
6460 local_name = ACONCAT (("__fn_local_", func_name, NULL));
6461 local = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (local_name));
6462 SYMBOL_REF_FLAGS (local) = SYMBOL_REF_FLAGS (func) | SYMBOL_FLAG_LOCAL;
6464 /* Create a new structure to represent the mapping. */
6465 alias = ggc_alloc<struct mips16_local_alias> ();
6467 alias->local = local;
6470 return alias->local;
6473 /* A chained list of functions for which mips16_build_call_stub has already
6474 generated a stub. NAME is the name of the function and FP_RET_P is true
6475 if the function returns a value in floating-point registers. */
6476 struct mips16_stub {
6477 struct mips16_stub *next;
6481 static struct mips16_stub *mips16_stubs;
6483 /* Return the two-character string that identifies floating-point
6484 return mode MODE in the name of a MIPS16 function stub. */
6487 mips16_call_stub_mode_suffix (enum machine_mode mode)
6491 else if (mode == DFmode)
6493 else if (mode == SCmode)
6495 else if (mode == DCmode)
6497 else if (mode == V2SFmode)
6503 /* Write instructions to move a 32-bit value between general register
6504 GPREG and floating-point register FPREG. DIRECTION is 't' to move
6505 from GPREG to FPREG and 'f' to move in the opposite direction. */
6508 mips_output_32bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6510 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6511 reg_names[gpreg], reg_names[fpreg]);
6514 /* Likewise for 64-bit values. */
6517 mips_output_64bit_xfer (char direction, unsigned int gpreg, unsigned int fpreg)
6520 fprintf (asm_out_file, "\tdm%cc1\t%s,%s\n", direction,
6521 reg_names[gpreg], reg_names[fpreg]);
6522 else if (TARGET_FLOAT64)
6524 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6525 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6526 fprintf (asm_out_file, "\tm%chc1\t%s,%s\n", direction,
6527 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg]);
6531 /* Move the least-significant word. */
6532 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6533 reg_names[gpreg + TARGET_BIG_ENDIAN], reg_names[fpreg]);
6534 /* ...then the most significant word. */
6535 fprintf (asm_out_file, "\tm%cc1\t%s,%s\n", direction,
6536 reg_names[gpreg + TARGET_LITTLE_ENDIAN], reg_names[fpreg + 1]);
6540 /* Write out code to move floating-point arguments into or out of
6541 general registers. FP_CODE is the code describing which arguments
6542 are present (see the comment above the definition of CUMULATIVE_ARGS
6543 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
6546 mips_output_args_xfer (int fp_code, char direction)
6548 unsigned int gparg, fparg, f;
6549 CUMULATIVE_ARGS cum;
6551 /* This code only works for o32 and o64. */
6552 gcc_assert (TARGET_OLDABI);
6554 mips_init_cumulative_args (&cum, NULL);
6556 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6558 enum machine_mode mode;
6559 struct mips_arg_info info;
6563 else if ((f & 3) == 2)
6568 mips_get_arg_info (&info, &cum, mode, NULL, true);
6569 gparg = mips_arg_regno (&info, false);
6570 fparg = mips_arg_regno (&info, true);
6573 mips_output_32bit_xfer (direction, gparg, fparg);
6575 mips_output_64bit_xfer (direction, gparg, fparg);
6577 mips_function_arg_advance (pack_cumulative_args (&cum), mode, NULL, true);
6581 /* Write a MIPS16 stub for the current function. This stub is used
6582 for functions which take arguments in the floating-point registers.
6583 It is normal-mode code that moves the floating-point arguments
6584 into the general registers and then jumps to the MIPS16 code. */
6587 mips16_build_function_stub (void)
6589 const char *fnname, *alias_name, *separator;
6590 char *secname, *stubname;
6595 /* Create the name of the stub, and its unique section. */
6596 symbol = XEXP (DECL_RTL (current_function_decl), 0);
6597 alias = mips16_local_alias (symbol);
6599 fnname = targetm.strip_name_encoding (XSTR (symbol, 0));
6600 alias_name = targetm.strip_name_encoding (XSTR (alias, 0));
6601 secname = ACONCAT ((".mips16.fn.", fnname, NULL));
6602 stubname = ACONCAT (("__fn_stub_", fnname, NULL));
6604 /* Build a decl for the stub. */
6605 stubdecl = build_decl (BUILTINS_LOCATION,
6606 FUNCTION_DECL, get_identifier (stubname),
6607 build_function_type_list (void_type_node, NULL_TREE));
6608 set_decl_section_name (stubdecl, secname);
6609 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6610 RESULT_DECL, NULL_TREE, void_type_node);
6612 /* Output a comment. */
6613 fprintf (asm_out_file, "\t# Stub function for %s (",
6614 current_function_name ());
6616 for (f = (unsigned int) crtl->args.info.fp_code; f != 0; f >>= 2)
6618 fprintf (asm_out_file, "%s%s", separator,
6619 (f & 3) == 1 ? "float" : "double");
6622 fprintf (asm_out_file, ")\n");
6624 /* Start the function definition. */
6625 assemble_start_function (stubdecl, stubname);
6626 mips_start_function_definition (stubname, false);
6628 /* If generating pic2 code, either set up the global pointer or
6630 if (TARGET_ABICALLS_PIC2)
6632 if (TARGET_ABSOLUTE_ABICALLS)
6633 fprintf (asm_out_file, "\t.option\tpic0\n");
6636 output_asm_insn ("%(.cpload\t%^%)", NULL);
6637 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6638 target function is. Use a local GOT access when loading the
6639 symbol, to cut down on the number of unnecessary GOT entries
6640 for stubs that aren't needed. */
6641 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol);
6646 /* Load the address of the MIPS16 function into $25. Do this first so
6647 that targets with coprocessor interlocks can use an MFC1 to fill the
6649 output_asm_insn ("la\t%^,%0", &symbol);
6651 /* Move the arguments from floating-point registers to general registers. */
6652 mips_output_args_xfer (crtl->args.info.fp_code, 'f');
6654 /* Jump to the MIPS16 function. */
6655 output_asm_insn ("jr\t%^", NULL);
6657 if (TARGET_ABICALLS_PIC2 && TARGET_ABSOLUTE_ABICALLS)
6658 fprintf (asm_out_file, "\t.option\tpic2\n");
6660 mips_end_function_definition (stubname);
6662 /* If the linker needs to create a dynamic symbol for the target
6663 function, it will associate the symbol with the stub (which,
6664 unlike the target function, follows the proper calling conventions).
6665 It is therefore useful to have a local alias for the target function,
6666 so that it can still be identified as MIPS16 code. As an optimization,
6667 this symbol can also be used for indirect MIPS16 references from
6668 within this file. */
6669 ASM_OUTPUT_DEF (asm_out_file, alias_name, fnname);
6671 switch_to_section (function_section (current_function_decl));
6674 /* The current function is a MIPS16 function that returns a value in an FPR.
6675 Copy the return value from its soft-float to its hard-float location.
6676 libgcc2 has special non-MIPS16 helper functions for each case. */
6679 mips16_copy_fpr_return_value (void)
6681 rtx fn, insn, retval;
6683 enum machine_mode return_mode;
6686 return_type = DECL_RESULT (current_function_decl);
6687 return_mode = DECL_MODE (return_type);
6689 name = ACONCAT (("__mips16_ret_",
6690 mips16_call_stub_mode_suffix (return_mode),
6692 fn = mips16_stub_function (name);
6694 /* The function takes arguments in $2 (and possibly $3), so calls
6695 to it cannot be lazily bound. */
6696 SYMBOL_REF_FLAGS (fn) |= SYMBOL_FLAG_BIND_NOW;
6698 /* Model the call as something that takes the GPR return value as
6699 argument and returns an "updated" value. */
6700 retval = gen_rtx_REG (return_mode, GP_RETURN);
6701 insn = mips_expand_call (MIPS_CALL_EPILOGUE, retval, fn,
6702 const0_rtx, NULL_RTX, false);
6703 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), retval);
6706 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6707 RETVAL is the location of the return value, or null if this is
6708 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6709 arguments and FP_CODE is the code built by mips_function_arg;
6710 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6712 There are three alternatives:
6714 - If a stub was needed, emit the call and return the call insn itself.
6716 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6717 to the new target and return null.
6719 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6722 A stub is needed for calls to functions that, in normal mode,
6723 receive arguments in FPRs or return values in FPRs. The stub
6724 copies the arguments from their soft-float positions to their
6725 hard-float positions, calls the real function, then copies the
6726 return value from its hard-float position to its soft-float
6729 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6730 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6731 automatically redirects the JAL to the stub, otherwise the JAL
6732 continues to call FN directly. */
6735 mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
6739 struct mips16_stub *l;
6742 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6743 we were invoked with the -msoft-float option. */
6744 if (!TARGET_MIPS16 || TARGET_SOFT_FLOAT_ABI)
6747 /* Figure out whether the value might come back in a floating-point
6749 fp_ret_p = retval && mips_return_mode_in_fpr_p (GET_MODE (retval));
6751 /* We don't need to do anything if there were no floating-point
6752 arguments and the value will not be returned in a floating-point
6754 if (fp_code == 0 && !fp_ret_p)
6757 /* We don't need to do anything if this is a call to a special
6758 MIPS16 support function. */
6760 if (mips16_stub_function_p (fn))
6763 /* If we're calling a locally-defined MIPS16 function, we know that
6764 it will return values in both the "soft-float" and "hard-float"
6765 registers. There is no need to use a stub to move the latter
6767 if (fp_code == 0 && mips16_local_function_p (fn))
6770 /* This code will only work for o32 and o64 abis. The other ABI's
6771 require more sophisticated support. */
6772 gcc_assert (TARGET_OLDABI);
6774 /* If we're calling via a function pointer, use one of the magic
6775 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6776 Each stub expects the function address to arrive in register $2. */
6777 if (GET_CODE (fn) != SYMBOL_REF
6778 || !call_insn_operand (fn, VOIDmode))
6781 rtx stub_fn, insn, addr;
6784 /* If this is a locally-defined and locally-binding function,
6785 avoid the stub by calling the local alias directly. */
6786 if (mips16_local_function_p (fn))
6788 *fn_ptr = mips16_local_alias (fn);
6792 /* Create a SYMBOL_REF for the libgcc.a function. */
6794 sprintf (buf, "__mips16_call_stub_%s_%d",
6795 mips16_call_stub_mode_suffix (GET_MODE (retval)),
6798 sprintf (buf, "__mips16_call_stub_%d", fp_code);
6799 stub_fn = mips16_stub_function (buf);
6801 /* The function uses $2 as an argument, so calls to it
6802 cannot be lazily bound. */
6803 SYMBOL_REF_FLAGS (stub_fn) |= SYMBOL_FLAG_BIND_NOW;
6805 /* Load the target function into $2. */
6806 addr = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
6807 lazy_p = mips_load_call_address (MIPS_CALL_NORMAL, addr, fn);
6809 /* Emit the call. */
6810 insn = mips_expand_call (MIPS_CALL_NORMAL, retval, stub_fn,
6811 args_size, NULL_RTX, lazy_p);
6813 /* Tell GCC that this call does indeed use the value of $2. */
6814 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), addr);
6816 /* If we are handling a floating-point return value, we need to
6817 save $18 in the function prologue. Putting a note on the
6818 call will mean that df_regs_ever_live_p ($18) will be true if the
6819 call is not eliminated, and we can check that in the prologue
6822 CALL_INSN_FUNCTION_USAGE (insn) =
6823 gen_rtx_EXPR_LIST (VOIDmode,
6824 gen_rtx_CLOBBER (VOIDmode,
6825 gen_rtx_REG (word_mode, 18)),
6826 CALL_INSN_FUNCTION_USAGE (insn));
6831 /* We know the function we are going to call. If we have already
6832 built a stub, we don't need to do anything further. */
6833 fnname = targetm.strip_name_encoding (XSTR (fn, 0));
6834 for (l = mips16_stubs; l != NULL; l = l->next)
6835 if (strcmp (l->name, fnname) == 0)
6840 const char *separator;
6841 char *secname, *stubname;
6842 tree stubid, stubdecl;
6845 /* If the function does not return in FPRs, the special stub
6849 If the function does return in FPRs, the stub section is named
6850 .mips16.call.fp.FNNAME
6852 Build a decl for the stub. */
6853 secname = ACONCAT ((".mips16.call.", fp_ret_p ? "fp." : "",
6855 stubname = ACONCAT (("__call_stub_", fp_ret_p ? "fp_" : "",
6857 stubid = get_identifier (stubname);
6858 stubdecl = build_decl (BUILTINS_LOCATION,
6859 FUNCTION_DECL, stubid,
6860 build_function_type_list (void_type_node,
6862 set_decl_section_name (stubdecl, secname);
6863 DECL_RESULT (stubdecl) = build_decl (BUILTINS_LOCATION,
6864 RESULT_DECL, NULL_TREE,
6867 /* Output a comment. */
6868 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
6870 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
6874 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
6876 fprintf (asm_out_file, "%s%s", separator,
6877 (f & 3) == 1 ? "float" : "double");
6880 fprintf (asm_out_file, ")\n");
6882 /* Start the function definition. */
6883 assemble_start_function (stubdecl, stubname);
6884 mips_start_function_definition (stubname, false);
6888 fprintf (asm_out_file, "\t.cfi_startproc\n");
6890 /* Create a fake CFA 4 bytes below the stack pointer.
6891 This works around unwinders (like libgcc's) that expect
6892 the CFA for non-signal frames to be unique. */
6893 fprintf (asm_out_file, "\t.cfi_def_cfa 29,-4\n");
6895 /* "Save" $sp in itself so we don't use the fake CFA.
6896 This is: DW_CFA_val_expression r29, { DW_OP_reg29 }. */
6897 fprintf (asm_out_file, "\t.cfi_escape 0x16,29,1,0x6d\n");
6901 /* Load the address of the MIPS16 function into $25. Do this
6902 first so that targets with coprocessor interlocks can use
6903 an MFC1 to fill the delay slot. */
6904 if (TARGET_EXPLICIT_RELOCS)
6906 output_asm_insn ("lui\t%^,%%hi(%0)", &fn);
6907 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn);
6910 output_asm_insn ("la\t%^,%0", &fn);
6913 /* Move the arguments from general registers to floating-point
6915 mips_output_args_xfer (fp_code, 't');
6919 /* Save the return address in $18 and call the non-MIPS16 function.
6920 The stub's caller knows that $18 might be clobbered, even though
6921 $18 is usually a call-saved register. */
6922 fprintf (asm_out_file, "\tmove\t%s,%s\n",
6923 reg_names[GP_REG_FIRST + 18], reg_names[RETURN_ADDR_REGNUM]);
6924 output_asm_insn (MIPS_CALL ("jal", &fn, 0, -1), &fn);
6925 fprintf (asm_out_file, "\t.cfi_register 31,18\n");
6927 /* Move the result from floating-point registers to
6928 general registers. */
6929 switch (GET_MODE (retval))
6932 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_BIG_ENDIAN,
6934 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6936 mips_output_32bit_xfer ('f', GP_RETURN + TARGET_LITTLE_ENDIAN,
6937 TARGET_LITTLE_ENDIAN
6938 ? FP_REG_FIRST + MAX_FPRS_PER_FMT
6940 if (GET_MODE (retval) == SCmode && TARGET_64BIT)
6942 /* On 64-bit targets, complex floats are returned in
6943 a single GPR, such that "sd" on a suitably-aligned
6944 target would store the value correctly. */
6945 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6946 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6947 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6948 fprintf (asm_out_file, "\tdsll\t%s,%s,32\n",
6949 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN],
6950 reg_names[GP_RETURN + TARGET_LITTLE_ENDIAN]);
6951 fprintf (asm_out_file, "\tdsrl\t%s,%s,32\n",
6952 reg_names[GP_RETURN + TARGET_BIG_ENDIAN],
6953 reg_names[GP_RETURN + TARGET_BIG_ENDIAN]);
6954 fprintf (asm_out_file, "\tor\t%s,%s,%s\n",
6955 reg_names[GP_RETURN],
6956 reg_names[GP_RETURN],
6957 reg_names[GP_RETURN + 1]);
6962 mips_output_32bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6966 mips_output_64bit_xfer ('f', GP_RETURN + (8 / UNITS_PER_WORD),
6967 FP_REG_FIRST + MAX_FPRS_PER_FMT);
6971 mips_output_64bit_xfer ('f', GP_RETURN, FP_REG_FIRST);
6977 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 18]);
6978 fprintf (asm_out_file, "\t.cfi_endproc\n");
6982 /* Jump to the previously-loaded address. */
6983 output_asm_insn ("jr\t%^", NULL);
6986 #ifdef ASM_DECLARE_FUNCTION_SIZE
6987 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
6990 mips_end_function_definition (stubname);
6992 /* Record this stub. */
6993 l = XNEW (struct mips16_stub);
6994 l->name = xstrdup (fnname);
6995 l->fp_ret_p = fp_ret_p;
6996 l->next = mips16_stubs;
7000 /* If we expect a floating-point return value, but we've built a
7001 stub which does not expect one, then we're in trouble. We can't
7002 use the existing stub, because it won't handle the floating-point
7003 value. We can't build a new stub, because the linker won't know
7004 which stub to use for the various calls in this object file.
7005 Fortunately, this case is illegal, since it means that a function
7006 was declared in two different ways in a single compilation. */
7007 if (fp_ret_p && !l->fp_ret_p)
7008 error ("cannot handle inconsistent calls to %qs", fnname);
7010 if (retval == NULL_RTX)
7011 insn = gen_call_internal_direct (fn, args_size);
7013 insn = gen_call_value_internal_direct (retval, fn, args_size);
7014 insn = mips_emit_call_insn (insn, fn, fn, false);
7016 /* If we are calling a stub which handles a floating-point return
7017 value, we need to arrange to save $18 in the prologue. We do this
7018 by marking the function call as using the register. The prologue
7019 will later see that it is used, and emit code to save it. */
7021 CALL_INSN_FUNCTION_USAGE (insn) =
7022 gen_rtx_EXPR_LIST (VOIDmode,
7023 gen_rtx_CLOBBER (VOIDmode,
7024 gen_rtx_REG (word_mode, 18)),
7025 CALL_INSN_FUNCTION_USAGE (insn));
7030 /* Expand a call of type TYPE. RESULT is where the result will go (null
7031 for "call"s and "sibcall"s), ADDR is the address of the function,
7032 ARGS_SIZE is the size of the arguments and AUX is the value passed
7033 to us by mips_function_arg. LAZY_P is true if this call already
7034 involves a lazily-bound function address (such as when calling
7035 functions through a MIPS16 hard-float stub).
7037 Return the call itself. */
7040 mips_expand_call (enum mips_call_type type, rtx result, rtx addr,
7041 rtx args_size, rtx aux, bool lazy_p)
7043 rtx orig_addr, pattern, insn;
7046 fp_code = aux == 0 ? 0 : (int) GET_MODE (aux);
7047 insn = mips16_build_call_stub (result, &addr, args_size, fp_code);
7050 gcc_assert (!lazy_p && type == MIPS_CALL_NORMAL);
7055 if (!call_insn_operand (addr, VOIDmode))
7057 if (type == MIPS_CALL_EPILOGUE)
7058 addr = MIPS_EPILOGUE_TEMP (Pmode);
7060 addr = gen_reg_rtx (Pmode);
7061 lazy_p |= mips_load_call_address (type, addr, orig_addr);
7066 rtx (*fn) (rtx, rtx);
7068 if (type == MIPS_CALL_SIBCALL)
7069 fn = gen_sibcall_internal;
7071 fn = gen_call_internal;
7073 pattern = fn (addr, args_size);
7075 else if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 2)
7077 /* Handle return values created by mips_return_fpr_pair. */
7078 rtx (*fn) (rtx, rtx, rtx, rtx);
7081 if (type == MIPS_CALL_SIBCALL)
7082 fn = gen_sibcall_value_multiple_internal;
7084 fn = gen_call_value_multiple_internal;
7086 reg1 = XEXP (XVECEXP (result, 0, 0), 0);
7087 reg2 = XEXP (XVECEXP (result, 0, 1), 0);
7088 pattern = fn (reg1, addr, args_size, reg2);
7092 rtx (*fn) (rtx, rtx, rtx);
7094 if (type == MIPS_CALL_SIBCALL)
7095 fn = gen_sibcall_value_internal;
7097 fn = gen_call_value_internal;
7099 /* Handle return values created by mips_return_fpr_single. */
7100 if (GET_CODE (result) == PARALLEL && XVECLEN (result, 0) == 1)
7101 result = XEXP (XVECEXP (result, 0, 0), 0);
7102 pattern = fn (result, addr, args_size);
7105 return mips_emit_call_insn (pattern, orig_addr, addr, lazy_p);
7108 /* Split call instruction INSN into a $gp-clobbering call and
7109 (where necessary) an instruction to restore $gp from its save slot.
7110 CALL_PATTERN is the pattern of the new call. */
7113 mips_split_call (rtx insn, rtx call_pattern)
7115 emit_call_insn (call_pattern);
7116 if (!find_reg_note (insn, REG_NORETURN, 0))
7117 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode,
7118 POST_CALL_TMP_REG));
7121 /* Return true if a call to DECL may need to use JALX. */
7124 mips_call_may_need_jalx_p (tree decl)
7126 /* If the current translation unit would use a different mode for DECL,
7127 assume that the call needs JALX. */
7128 if (mips_get_compress_mode (decl) != TARGET_COMPRESSION)
7131 /* mips_get_compress_mode is always accurate for locally-binding
7132 functions in the current translation unit. */
7133 if (!DECL_EXTERNAL (decl) && targetm.binds_local_p (decl))
7136 /* When -minterlink-compressed is in effect, assume that functions
7137 could use a different encoding mode unless an attribute explicitly
7138 tells us otherwise. */
7139 if (TARGET_INTERLINK_COMPRESSED)
7141 if (!TARGET_COMPRESSION
7142 && mips_get_compress_off_flags (DECL_ATTRIBUTES (decl)) ==0)
7144 if (TARGET_COMPRESSION
7145 && mips_get_compress_on_flags (DECL_ATTRIBUTES (decl)) == 0)
7152 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
7155 mips_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7157 if (!TARGET_SIBCALLS)
7160 /* Interrupt handlers need special epilogue code and therefore can't
7162 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
7165 /* Direct Js are only possible to functions that use the same ISA encoding.
7166 There is no JX counterpoart of JALX. */
7168 && const_call_insn_operand (XEXP (DECL_RTL (decl), 0), VOIDmode)
7169 && mips_call_may_need_jalx_p (decl))
7172 /* Sibling calls should not prevent lazy binding. Lazy-binding stubs
7173 require $gp to be valid on entry, so sibcalls can only use stubs
7174 if $gp is call-clobbered. */
7176 && TARGET_CALL_SAVED_GP
7177 && !TARGET_ABICALLS_PIC0
7178 && !targetm.binds_local_p (decl))
7185 /* Implement MOVE_BY_PIECES_P. */
7188 mips_move_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7192 /* movmemsi is meant to generate code that is at least as good as
7193 move_by_pieces. However, movmemsi effectively uses a by-pieces
7194 implementation both for moves smaller than a word and for
7195 word-aligned moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT
7196 bytes. We should allow the tree-level optimisers to do such
7197 moves by pieces, as it often exposes other optimization
7198 opportunities. We might as well continue to use movmemsi at
7199 the rtl level though, as it produces better code when
7200 scheduling is disabled (such as at -O). */
7201 if (currently_expanding_to_rtl)
7203 if (align < BITS_PER_WORD)
7204 return size < UNITS_PER_WORD;
7205 return size <= MIPS_MAX_MOVE_BYTES_STRAIGHT;
7207 /* The default value. If this becomes a target hook, we should
7208 call the default definition instead. */
7209 return (move_by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1)
7210 < (unsigned int) MOVE_RATIO (optimize_insn_for_speed_p ()));
7213 /* Implement STORE_BY_PIECES_P. */
7216 mips_store_by_pieces_p (unsigned HOST_WIDE_INT size, unsigned int align)
7218 /* Storing by pieces involves moving constants into registers
7219 of size MIN (ALIGN, BITS_PER_WORD), then storing them.
7220 We need to decide whether it is cheaper to load the address of
7221 constant data into a register and use a block move instead. */
7223 /* If the data is only byte aligned, then:
7225 (a1) A block move of less than 4 bytes would involve three 3 LBs and
7226 3 SBs. We might as well use 3 single-instruction LIs and 3 SBs
7229 (a2) A block move of 4 bytes from aligned source data can use an
7230 LW/SWL/SWR sequence. This is often better than the 4 LIs and
7231 4 SBs that we would generate when storing by pieces. */
7232 if (align <= BITS_PER_UNIT)
7235 /* If the data is 2-byte aligned, then:
7237 (b1) A block move of less than 4 bytes would use a combination of LBs,
7238 LHs, SBs and SHs. We get better code by using single-instruction
7239 LIs, SBs and SHs instead.
7241 (b2) A block move of 4 bytes from aligned source data would again use
7242 an LW/SWL/SWR sequence. In most cases, loading the address of
7243 the source data would require at least one extra instruction.
7244 It is often more efficient to use 2 single-instruction LIs and
7247 (b3) A block move of up to 3 additional bytes would be like (b1).
7249 (b4) A block move of 8 bytes from aligned source data can use two
7250 LW/SWL/SWR sequences or a single LD/SDL/SDR sequence. Both
7251 sequences are better than the 4 LIs and 4 SHs that we'd generate
7252 when storing by pieces.
7254 The reasoning for higher alignments is similar:
7256 (c1) A block move of less than 4 bytes would be the same as (b1).
7258 (c2) A block move of 4 bytes would use an LW/SW sequence. Again,
7259 loading the address of the source data would typically require
7260 at least one extra instruction. It is generally better to use
7263 (c3) A block move of up to 3 additional bytes would be like (b1).
7265 (c4) A block move of 8 bytes can use two LW/SW sequences or a single
7266 LD/SD sequence, and in these cases we've traditionally preferred
7267 the memory copy over the more bulky constant moves. */
7271 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
7272 Assume that the areas do not overlap. */
7275 mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
7277 HOST_WIDE_INT offset, delta;
7278 unsigned HOST_WIDE_INT bits;
7280 enum machine_mode mode;
7283 /* Work out how many bits to move at a time. If both operands have
7284 half-word alignment, it is usually better to move in half words.
7285 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
7286 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
7287 Otherwise move word-sized chunks. */
7288 if (MEM_ALIGN (src) == BITS_PER_WORD / 2
7289 && MEM_ALIGN (dest) == BITS_PER_WORD / 2)
7290 bits = BITS_PER_WORD / 2;
7292 bits = BITS_PER_WORD;
7294 mode = mode_for_size (bits, MODE_INT, 0);
7295 delta = bits / BITS_PER_UNIT;
7297 /* Allocate a buffer for the temporary registers. */
7298 regs = XALLOCAVEC (rtx, length / delta);
7300 /* Load as many BITS-sized chunks as possible. Use a normal load if
7301 the source has enough alignment, otherwise use left/right pairs. */
7302 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7304 regs[i] = gen_reg_rtx (mode);
7305 if (MEM_ALIGN (src) >= bits)
7306 mips_emit_move (regs[i], adjust_address (src, mode, offset));
7309 rtx part = adjust_address (src, BLKmode, offset);
7310 set_mem_size (part, delta);
7311 if (!mips_expand_ext_as_unaligned_load (regs[i], part, bits, 0, 0))
7316 /* Copy the chunks to the destination. */
7317 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
7318 if (MEM_ALIGN (dest) >= bits)
7319 mips_emit_move (adjust_address (dest, mode, offset), regs[i]);
7322 rtx part = adjust_address (dest, BLKmode, offset);
7323 set_mem_size (part, delta);
7324 if (!mips_expand_ins_as_unaligned_store (part, regs[i], bits, 0))
7328 /* Mop up any left-over bytes. */
7329 if (offset < length)
7331 src = adjust_address (src, BLKmode, offset);
7332 dest = adjust_address (dest, BLKmode, offset);
7333 move_by_pieces (dest, src, length - offset,
7334 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), 0);
7338 /* Helper function for doing a loop-based block operation on memory
7339 reference MEM. Each iteration of the loop will operate on LENGTH
7342 Create a new base register for use within the loop and point it to
7343 the start of MEM. Create a new memory reference that uses this
7344 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
7347 mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
7348 rtx *loop_reg, rtx *loop_mem)
7350 *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
7352 /* Although the new mem does not refer to a known location,
7353 it does keep up to LENGTH bytes of alignment. */
7354 *loop_mem = change_address (mem, BLKmode, *loop_reg);
7355 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT));
7358 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
7359 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
7360 the memory regions do not overlap. */
7363 mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length,
7364 HOST_WIDE_INT bytes_per_iter)
7366 rtx label, src_reg, dest_reg, final_src, test;
7367 HOST_WIDE_INT leftover;
7369 leftover = length % bytes_per_iter;
7372 /* Create registers and memory references for use within the loop. */
7373 mips_adjust_block_mem (src, bytes_per_iter, &src_reg, &src);
7374 mips_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest);
7376 /* Calculate the value that SRC_REG should have after the last iteration
7378 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length),
7381 /* Emit the start of the loop. */
7382 label = gen_label_rtx ();
7385 /* Emit the loop body. */
7386 mips_block_move_straight (dest, src, bytes_per_iter);
7388 /* Move on to the next block. */
7389 mips_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter));
7390 mips_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter));
7392 /* Emit the loop condition. */
7393 test = gen_rtx_NE (VOIDmode, src_reg, final_src);
7394 if (Pmode == DImode)
7395 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label));
7397 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label));
7399 /* Mop up any left-over bytes. */
7401 mips_block_move_straight (dest, src, leftover);
7404 /* Expand a movmemsi instruction, which copies LENGTH bytes from
7405 memory reference SRC to memory reference DEST. */
7408 mips_expand_block_move (rtx dest, rtx src, rtx length)
7410 if (CONST_INT_P (length))
7412 if (INTVAL (length) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)
7414 mips_block_move_straight (dest, src, INTVAL (length));
7419 mips_block_move_loop (dest, src, INTVAL (length),
7420 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER);
7427 /* Expand a loop of synci insns for the address range [BEGIN, END). */
7430 mips_expand_synci_loop (rtx begin, rtx end)
7432 rtx inc, label, end_label, cmp_result, mask, length;
7434 /* Create end_label. */
7435 end_label = gen_label_rtx ();
7437 /* Check if begin equals end. */
7438 cmp_result = gen_rtx_EQ (VOIDmode, begin, end);
7439 emit_jump_insn (gen_condjump (cmp_result, end_label));
7441 /* Load INC with the cache line size (rdhwr INC,$1). */
7442 inc = gen_reg_rtx (Pmode);
7443 emit_insn (PMODE_INSN (gen_rdhwr_synci_step, (inc)));
7445 /* Check if inc is 0. */
7446 cmp_result = gen_rtx_EQ (VOIDmode, inc, const0_rtx);
7447 emit_jump_insn (gen_condjump (cmp_result, end_label));
7449 /* Calculate mask. */
7450 mask = mips_force_unary (Pmode, NEG, inc);
7452 /* Mask out begin by mask. */
7453 begin = mips_force_binary (Pmode, AND, begin, mask);
7455 /* Calculate length. */
7456 length = mips_force_binary (Pmode, MINUS, end, begin);
7458 /* Loop back to here. */
7459 label = gen_label_rtx ();
7462 emit_insn (gen_synci (begin));
7464 /* Update length. */
7465 mips_emit_binary (MINUS, length, length, inc);
7468 mips_emit_binary (PLUS, begin, begin, inc);
7470 /* Check if length is greater than 0. */
7471 cmp_result = gen_rtx_GT (VOIDmode, length, const0_rtx);
7472 emit_jump_insn (gen_condjump (cmp_result, label));
7474 emit_label (end_label);
7477 /* Expand a QI or HI mode atomic memory operation.
7479 GENERATOR contains a pointer to the gen_* function that generates
7480 the SI mode underlying atomic operation using masks that we
7483 RESULT is the return register for the operation. Its value is NULL
7486 MEM is the location of the atomic access.
7488 OLDVAL is the first operand for the operation.
7490 NEWVAL is the optional second operand for the operation. Its value
7491 is NULL if unused. */
7494 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator,
7495 rtx result, rtx mem, rtx oldval, rtx newval)
7497 rtx orig_addr, memsi_addr, memsi, shift, shiftsi, unshifted_mask;
7498 rtx unshifted_mask_reg, mask, inverted_mask, si_op;
7500 enum machine_mode mode;
7502 mode = GET_MODE (mem);
7504 /* Compute the address of the containing SImode value. */
7505 orig_addr = force_reg (Pmode, XEXP (mem, 0));
7506 memsi_addr = mips_force_binary (Pmode, AND, orig_addr,
7507 force_reg (Pmode, GEN_INT (-4)));
7509 /* Create a memory reference for it. */
7510 memsi = gen_rtx_MEM (SImode, memsi_addr);
7511 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER);
7512 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem);
7514 /* Work out the byte offset of the QImode or HImode value,
7515 counting from the least significant byte. */
7516 shift = mips_force_binary (Pmode, AND, orig_addr, GEN_INT (3));
7517 if (TARGET_BIG_ENDIAN)
7518 mips_emit_binary (XOR, shift, shift, GEN_INT (mode == QImode ? 3 : 2));
7520 /* Multiply by eight to convert the shift value from bytes to bits. */
7521 mips_emit_binary (ASHIFT, shift, shift, GEN_INT (3));
7523 /* Make the final shift an SImode value, so that it can be used in
7524 SImode operations. */
7525 shiftsi = force_reg (SImode, gen_lowpart (SImode, shift));
7527 /* Set MASK to an inclusive mask of the QImode or HImode value. */
7528 unshifted_mask = GEN_INT (GET_MODE_MASK (mode));
7529 unshifted_mask_reg = force_reg (SImode, unshifted_mask);
7530 mask = mips_force_binary (SImode, ASHIFT, unshifted_mask_reg, shiftsi);
7532 /* Compute the equivalent exclusive mask. */
7533 inverted_mask = gen_reg_rtx (SImode);
7534 emit_insn (gen_rtx_SET (VOIDmode, inverted_mask,
7535 gen_rtx_NOT (SImode, mask)));
7537 /* Shift the old value into place. */
7538 if (oldval != const0_rtx)
7540 oldval = convert_modes (SImode, mode, oldval, true);
7541 oldval = force_reg (SImode, oldval);
7542 oldval = mips_force_binary (SImode, ASHIFT, oldval, shiftsi);
7545 /* Do the same for the new value. */
7546 if (newval && newval != const0_rtx)
7548 newval = convert_modes (SImode, mode, newval, true);
7549 newval = force_reg (SImode, newval);
7550 newval = mips_force_binary (SImode, ASHIFT, newval, shiftsi);
7553 /* Do the SImode atomic access. */
7555 res = gen_reg_rtx (SImode);
7557 si_op = generator.fn_6 (res, memsi, mask, inverted_mask, oldval, newval);
7559 si_op = generator.fn_5 (res, memsi, mask, inverted_mask, oldval);
7561 si_op = generator.fn_4 (memsi, mask, inverted_mask, oldval);
7567 /* Shift and convert the result. */
7568 mips_emit_binary (AND, res, res, mask);
7569 mips_emit_binary (LSHIFTRT, res, res, shiftsi);
7570 mips_emit_move (result, gen_lowpart (GET_MODE (result), res));
7574 /* Return true if it is possible to use left/right accesses for a
7575 bitfield of WIDTH bits starting BITPOS bits into BLKmode memory OP.
7576 When returning true, update *LEFT and *RIGHT as follows:
7578 *LEFT is a QImode reference to the first byte if big endian or
7579 the last byte if little endian. This address can be used in the
7580 left-side instructions (LWL, SWL, LDL, SDL).
7582 *RIGHT is a QImode reference to the opposite end of the field and
7583 can be used in the patterning right-side instruction. */
7586 mips_get_unaligned_mem (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos,
7587 rtx *left, rtx *right)
7591 /* Check that the size is valid. */
7592 if (width != 32 && (!TARGET_64BIT || width != 64))
7595 /* We can only access byte-aligned values. Since we are always passed
7596 a reference to the first byte of the field, it is not necessary to
7597 do anything with BITPOS after this check. */
7598 if (bitpos % BITS_PER_UNIT != 0)
7601 /* Reject aligned bitfields: we want to use a normal load or store
7602 instead of a left/right pair. */
7603 if (MEM_ALIGN (op) >= width)
7606 /* Get references to both ends of the field. */
7607 first = adjust_address (op, QImode, 0);
7608 last = adjust_address (op, QImode, width / BITS_PER_UNIT - 1);
7610 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
7611 correspond to the MSB and RIGHT to the LSB. */
7612 if (TARGET_BIG_ENDIAN)
7613 *left = first, *right = last;
7615 *left = last, *right = first;
7620 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
7621 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
7622 the operation is the equivalent of:
7624 (set DEST (*_extract SRC WIDTH BITPOS))
7626 Return true on success. */
7629 mips_expand_ext_as_unaligned_load (rtx dest, rtx src, HOST_WIDE_INT width,
7630 HOST_WIDE_INT bitpos, bool unsigned_p)
7632 rtx left, right, temp;
7633 rtx dest1 = NULL_RTX;
7635 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
7636 be a DImode, create a new temp and emit a zero extend at the end. */
7637 if (GET_MODE (dest) == DImode
7639 && GET_MODE_BITSIZE (SImode) == width)
7642 dest = gen_reg_rtx (SImode);
7645 if (!mips_get_unaligned_mem (src, width, bitpos, &left, &right))
7648 temp = gen_reg_rtx (GET_MODE (dest));
7649 if (GET_MODE (dest) == DImode)
7651 emit_insn (gen_mov_ldl (temp, src, left));
7652 emit_insn (gen_mov_ldr (dest, copy_rtx (src), right, temp));
7656 emit_insn (gen_mov_lwl (temp, src, left));
7657 emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
7660 /* If we were loading 32bits and the original register was DI then
7661 sign/zero extend into the orignal dest. */
7665 emit_insn (gen_zero_extendsidi2 (dest1, dest));
7667 emit_insn (gen_extendsidi2 (dest1, dest));
7672 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7673 BITPOS and SRC are the operands passed to the expander; the operation
7674 is the equivalent of:
7676 (set (zero_extract DEST WIDTH BITPOS) SRC)
7678 Return true on success. */
7681 mips_expand_ins_as_unaligned_store (rtx dest, rtx src, HOST_WIDE_INT width,
7682 HOST_WIDE_INT bitpos)
7685 enum machine_mode mode;
7687 if (!mips_get_unaligned_mem (dest, width, bitpos, &left, &right))
7690 mode = mode_for_size (width, MODE_INT, 0);
7691 src = gen_lowpart (mode, src);
7694 emit_insn (gen_mov_sdl (dest, src, left));
7695 emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
7699 emit_insn (gen_mov_swl (dest, src, left));
7700 emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
7705 /* Return true if X is a MEM with the same size as MODE. */
7708 mips_mem_fits_mode_p (enum machine_mode mode, rtx x)
7711 && MEM_SIZE_KNOWN_P (x)
7712 && MEM_SIZE (x) == GET_MODE_SIZE (mode));
7715 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7716 source of an "ext" instruction or the destination of an "ins"
7717 instruction. OP must be a register operand and the following
7718 conditions must hold:
7720 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7721 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7722 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7724 Also reject lengths equal to a word as they are better handled
7725 by the move patterns. */
7728 mips_use_ins_ext_p (rtx op, HOST_WIDE_INT width, HOST_WIDE_INT bitpos)
7730 if (!ISA_HAS_EXT_INS
7731 || !register_operand (op, VOIDmode)
7732 || GET_MODE_BITSIZE (GET_MODE (op)) > BITS_PER_WORD)
7735 if (!IN_RANGE (width, 1, GET_MODE_BITSIZE (GET_MODE (op)) - 1))
7738 if (bitpos < 0 || bitpos + width > GET_MODE_BITSIZE (GET_MODE (op)))
7744 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7745 operation if MAXLEN is the maxium length of consecutive bits that
7746 can make up MASK. MODE is the mode of the operation. See
7747 mask_low_and_shift_len for the actual definition. */
7750 mask_low_and_shift_p (enum machine_mode mode, rtx mask, rtx shift, int maxlen)
7752 return IN_RANGE (mask_low_and_shift_len (mode, mask, shift), 1, maxlen);
7755 /* Return true iff OP1 and OP2 are valid operands together for the
7756 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7757 see the table in the comment before the pattern. */
7760 and_operands_ok (enum machine_mode mode, rtx op1, rtx op2)
7762 return (memory_operand (op1, mode)
7763 ? and_load_operand (op2, mode)
7764 : and_reg_operand (op2, mode));
7767 /* The canonical form of a mask-low-and-shift-left operation is
7768 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7769 cleared. Thus we need to shift MASK to the right before checking if it
7770 is a valid mask value. MODE is the mode of the operation. If true
7771 return the length of the mask, otherwise return -1. */
7774 mask_low_and_shift_len (enum machine_mode mode, rtx mask, rtx shift)
7776 HOST_WIDE_INT shval;
7778 shval = INTVAL (shift) & (GET_MODE_BITSIZE (mode) - 1);
7779 return exact_log2 ((UINTVAL (mask) >> shval) + 1);
7782 /* Return true if -msplit-addresses is selected and should be honored.
7784 -msplit-addresses is a half-way house between explicit relocations
7785 and the traditional assembler macros. It can split absolute 32-bit
7786 symbolic constants into a high/lo_sum pair but uses macros for other
7789 Like explicit relocation support for REL targets, it relies
7790 on GNU extensions in the assembler and the linker.
7792 Although this code should work for -O0, it has traditionally
7793 been treated as an optimization. */
7796 mips_split_addresses_p (void)
7798 return (TARGET_SPLIT_ADDRESSES
7802 && !ABI_HAS_64BIT_SYMBOLS);
7805 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7808 mips_init_relocs (void)
7810 memset (mips_split_p, '\0', sizeof (mips_split_p));
7811 memset (mips_split_hi_p, '\0', sizeof (mips_split_hi_p));
7812 memset (mips_use_pcrel_pool_p, '\0', sizeof (mips_use_pcrel_pool_p));
7813 memset (mips_hi_relocs, '\0', sizeof (mips_hi_relocs));
7814 memset (mips_lo_relocs, '\0', sizeof (mips_lo_relocs));
7816 if (TARGET_MIPS16_PCREL_LOADS)
7817 mips_use_pcrel_pool_p[SYMBOL_ABSOLUTE] = true;
7820 if (ABI_HAS_64BIT_SYMBOLS)
7822 if (TARGET_EXPLICIT_RELOCS)
7824 mips_split_p[SYMBOL_64_HIGH] = true;
7825 mips_hi_relocs[SYMBOL_64_HIGH] = "%highest(";
7826 mips_lo_relocs[SYMBOL_64_HIGH] = "%higher(";
7828 mips_split_p[SYMBOL_64_MID] = true;
7829 mips_hi_relocs[SYMBOL_64_MID] = "%higher(";
7830 mips_lo_relocs[SYMBOL_64_MID] = "%hi(";
7832 mips_split_p[SYMBOL_64_LOW] = true;
7833 mips_hi_relocs[SYMBOL_64_LOW] = "%hi(";
7834 mips_lo_relocs[SYMBOL_64_LOW] = "%lo(";
7836 mips_split_p[SYMBOL_ABSOLUTE] = true;
7837 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7842 if (TARGET_EXPLICIT_RELOCS
7843 || mips_split_addresses_p ()
7846 mips_split_p[SYMBOL_ABSOLUTE] = true;
7847 mips_hi_relocs[SYMBOL_ABSOLUTE] = "%hi(";
7848 mips_lo_relocs[SYMBOL_ABSOLUTE] = "%lo(";
7855 /* The high part is provided by a pseudo copy of $gp. */
7856 mips_split_p[SYMBOL_GP_RELATIVE] = true;
7857 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gprel(";
7859 else if (TARGET_EXPLICIT_RELOCS)
7860 /* Small data constants are kept whole until after reload,
7861 then lowered by mips_rewrite_small_data. */
7862 mips_lo_relocs[SYMBOL_GP_RELATIVE] = "%gp_rel(";
7864 if (TARGET_EXPLICIT_RELOCS)
7866 mips_split_p[SYMBOL_GOT_PAGE_OFST] = true;
7869 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got_page(";
7870 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%got_ofst(";
7874 mips_lo_relocs[SYMBOL_GOTOFF_PAGE] = "%got(";
7875 mips_lo_relocs[SYMBOL_GOT_PAGE_OFST] = "%lo(";
7878 /* Expose the use of $28 as soon as possible. */
7879 mips_split_hi_p[SYMBOL_GOT_PAGE_OFST] = true;
7883 /* The HIGH and LO_SUM are matched by special .md patterns. */
7884 mips_split_p[SYMBOL_GOT_DISP] = true;
7886 mips_split_p[SYMBOL_GOTOFF_DISP] = true;
7887 mips_hi_relocs[SYMBOL_GOTOFF_DISP] = "%got_hi(";
7888 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_lo(";
7890 mips_split_p[SYMBOL_GOTOFF_CALL] = true;
7891 mips_hi_relocs[SYMBOL_GOTOFF_CALL] = "%call_hi(";
7892 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call_lo(";
7897 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got_disp(";
7899 mips_lo_relocs[SYMBOL_GOTOFF_DISP] = "%got(";
7900 mips_lo_relocs[SYMBOL_GOTOFF_CALL] = "%call16(";
7902 /* Expose the use of $28 as soon as possible. */
7903 mips_split_p[SYMBOL_GOT_DISP] = true;
7909 mips_split_p[SYMBOL_GOTOFF_LOADGP] = true;
7910 mips_hi_relocs[SYMBOL_GOTOFF_LOADGP] = "%hi(%neg(%gp_rel(";
7911 mips_lo_relocs[SYMBOL_GOTOFF_LOADGP] = "%lo(%neg(%gp_rel(";
7914 mips_lo_relocs[SYMBOL_TLSGD] = "%tlsgd(";
7915 mips_lo_relocs[SYMBOL_TLSLDM] = "%tlsldm(";
7917 if (TARGET_MIPS16_PCREL_LOADS)
7919 mips_use_pcrel_pool_p[SYMBOL_DTPREL] = true;
7920 mips_use_pcrel_pool_p[SYMBOL_TPREL] = true;
7924 mips_split_p[SYMBOL_DTPREL] = true;
7925 mips_hi_relocs[SYMBOL_DTPREL] = "%dtprel_hi(";
7926 mips_lo_relocs[SYMBOL_DTPREL] = "%dtprel_lo(";
7928 mips_split_p[SYMBOL_TPREL] = true;
7929 mips_hi_relocs[SYMBOL_TPREL] = "%tprel_hi(";
7930 mips_lo_relocs[SYMBOL_TPREL] = "%tprel_lo(";
7933 mips_lo_relocs[SYMBOL_GOTTPREL] = "%gottprel(";
7934 mips_lo_relocs[SYMBOL_HALF] = "%half(";
7937 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7938 in context CONTEXT. RELOCS is the array of relocations to use. */
7941 mips_print_operand_reloc (FILE *file, rtx op, enum mips_symbol_context context,
7942 const char **relocs)
7944 enum mips_symbol_type symbol_type;
7947 symbol_type = mips_classify_symbolic_expression (op, context);
7948 gcc_assert (relocs[symbol_type]);
7950 fputs (relocs[symbol_type], file);
7951 output_addr_const (file, mips_strip_unspec_address (op));
7952 for (p = relocs[symbol_type]; *p != 0; p++)
7957 /* Start a new block with the given asm switch enabled. If we need
7958 to print a directive, emit PREFIX before it and SUFFIX after it. */
7961 mips_push_asm_switch_1 (struct mips_asm_switch *asm_switch,
7962 const char *prefix, const char *suffix)
7964 if (asm_switch->nesting_level == 0)
7965 fprintf (asm_out_file, "%s.set\tno%s%s", prefix, asm_switch->name, suffix);
7966 asm_switch->nesting_level++;
7969 /* Likewise, but end a block. */
7972 mips_pop_asm_switch_1 (struct mips_asm_switch *asm_switch,
7973 const char *prefix, const char *suffix)
7975 gcc_assert (asm_switch->nesting_level);
7976 asm_switch->nesting_level--;
7977 if (asm_switch->nesting_level == 0)
7978 fprintf (asm_out_file, "%s.set\t%s%s", prefix, asm_switch->name, suffix);
7981 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7982 that either print a complete line or print nothing. */
7985 mips_push_asm_switch (struct mips_asm_switch *asm_switch)
7987 mips_push_asm_switch_1 (asm_switch, "\t", "\n");
7991 mips_pop_asm_switch (struct mips_asm_switch *asm_switch)
7993 mips_pop_asm_switch_1 (asm_switch, "\t", "\n");
7996 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7997 The punctuation characters are:
7999 '(' Start a nested ".set noreorder" block.
8000 ')' End a nested ".set noreorder" block.
8001 '[' Start a nested ".set noat" block.
8002 ']' End a nested ".set noat" block.
8003 '<' Start a nested ".set nomacro" block.
8004 '>' End a nested ".set nomacro" block.
8005 '*' Behave like %(%< if generating a delayed-branch sequence.
8006 '#' Print a nop if in a ".set noreorder" block.
8007 '/' Like '#', but do nothing within a delayed-branch sequence.
8008 '?' Print "l" if mips_branch_likely is true
8009 '~' Print a nop if mips_branch_likely is true
8010 '.' Print the name of the register with a hard-wired zero (zero or $0).
8011 '@' Print the name of the assembler temporary register (at or $1).
8012 '^' Print the name of the pic call-through register (t9 or $25).
8013 '+' Print the name of the gp register (usually gp or $28).
8014 '$' Print the name of the stack pointer register (sp or $29).
8015 ':' Print "c" to use the compact version if the delay slot is a nop.
8016 '!' Print "s" to use the short version if the delay slot contains a
8019 See also mips_init_print_operand_pucnt. */
8022 mips_print_operand_punctuation (FILE *file, int ch)
8027 mips_push_asm_switch_1 (&mips_noreorder, "", "\n\t");
8031 mips_pop_asm_switch_1 (&mips_noreorder, "\n\t", "");
8035 mips_push_asm_switch_1 (&mips_noat, "", "\n\t");
8039 mips_pop_asm_switch_1 (&mips_noat, "\n\t", "");
8043 mips_push_asm_switch_1 (&mips_nomacro, "", "\n\t");
8047 mips_pop_asm_switch_1 (&mips_nomacro, "\n\t", "");
8051 if (final_sequence != 0)
8053 mips_print_operand_punctuation (file, '(');
8054 mips_print_operand_punctuation (file, '<');
8059 if (mips_noreorder.nesting_level > 0)
8060 fputs ("\n\tnop", file);
8064 /* Print an extra newline so that the delayed insn is separated
8065 from the following ones. This looks neater and is consistent
8066 with non-nop delayed sequences. */
8067 if (mips_noreorder.nesting_level > 0 && final_sequence == 0)
8068 fputs ("\n\tnop\n", file);
8072 if (mips_branch_likely)
8077 if (mips_branch_likely)
8078 fputs ("\n\tnop", file);
8082 fputs (reg_names[GP_REG_FIRST + 0], file);
8086 fputs (reg_names[AT_REGNUM], file);
8090 fputs (reg_names[PIC_FUNCTION_ADDR_REGNUM], file);
8094 fputs (reg_names[PIC_OFFSET_TABLE_REGNUM], file);
8098 fputs (reg_names[STACK_POINTER_REGNUM], file);
8102 /* When final_sequence is 0, the delay slot will be a nop. We can
8103 use the compact version for microMIPS. */
8104 if (final_sequence == 0)
8109 /* If the delay slot instruction is short, then use the
8111 if (final_sequence == 0
8112 || get_attr_length (XVECEXP (final_sequence, 0, 1)) == 2)
8122 /* Initialize mips_print_operand_punct. */
8125 mips_init_print_operand_punct (void)
8129 for (p = "()[]<>*#/?~.@^+$:!"; *p; p++)
8130 mips_print_operand_punct[(unsigned char) *p] = true;
8133 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
8134 associated with condition CODE. Print the condition part of the
8138 mips_print_int_branch_condition (FILE *file, enum rtx_code code, int letter)
8152 /* Conveniently, the MIPS names for these conditions are the same
8153 as their RTL equivalents. */
8154 fputs (GET_RTX_NAME (code), file);
8158 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8163 /* Likewise floating-point branches. */
8166 mips_print_float_branch_condition (FILE *file, enum rtx_code code, int letter)
8171 fputs ("c1f", file);
8175 fputs ("c1t", file);
8179 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter);
8184 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8187 mips_print_operand_punct_valid_p (unsigned char code)
8189 return mips_print_operand_punct[code];
8192 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
8194 'X' Print CONST_INT OP in hexadecimal format.
8195 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
8196 'd' Print CONST_INT OP in decimal.
8197 'm' Print one less than CONST_INT OP in decimal.
8198 'h' Print the high-part relocation associated with OP, after stripping
8200 'R' Print the low-part relocation associated with OP.
8201 'C' Print the integer branch condition for comparison OP.
8202 'N' Print the inverse of the integer branch condition for comparison OP.
8203 'F' Print the FPU branch condition for comparison OP.
8204 'W' Print the inverse of the FPU branch condition for comparison OP.
8205 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
8206 'z' for (eq:?I ...), 'n' for (ne:?I ...).
8207 't' Like 'T', but with the EQ/NE cases reversed
8208 'Y' Print mips_fp_conditions[INTVAL (OP)]
8209 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
8210 'q' Print a DSP accumulator register.
8211 'D' Print the second part of a double-word register or memory operand.
8212 'L' Print the low-order register in a double-word register operand.
8213 'M' Print high-order register in a double-word register operand.
8214 'z' Print $0 if OP is zero, otherwise print OP normally.
8215 'b' Print the address of a memory operand, without offset. */
8218 mips_print_operand (FILE *file, rtx op, int letter)
8222 if (mips_print_operand_punct_valid_p (letter))
8224 mips_print_operand_punctuation (file, letter);
8229 code = GET_CODE (op);
8234 if (CONST_INT_P (op))
8235 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
8237 output_operand_lossage ("invalid use of '%%%c'", letter);
8241 if (CONST_INT_P (op))
8242 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op) & 0xffff);
8244 output_operand_lossage ("invalid use of '%%%c'", letter);
8248 if (CONST_INT_P (op))
8249 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op));
8251 output_operand_lossage ("invalid use of '%%%c'", letter);
8255 if (CONST_INT_P (op))
8256 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (op) - 1);
8258 output_operand_lossage ("invalid use of '%%%c'", letter);
8264 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_hi_relocs);
8268 mips_print_operand_reloc (file, op, SYMBOL_CONTEXT_LEA, mips_lo_relocs);
8272 mips_print_int_branch_condition (file, code, letter);
8276 mips_print_int_branch_condition (file, reverse_condition (code), letter);
8280 mips_print_float_branch_condition (file, code, letter);
8284 mips_print_float_branch_condition (file, reverse_condition (code),
8291 int truth = (code == NE) == (letter == 'T');
8292 fputc ("zfnt"[truth * 2 + ST_REG_P (REGNO (XEXP (op, 0)))], file);
8297 if (code == CONST_INT && UINTVAL (op) < ARRAY_SIZE (mips_fp_conditions))
8298 fputs (mips_fp_conditions[UINTVAL (op)], file);
8300 output_operand_lossage ("'%%%c' is not a valid operand prefix",
8307 mips_print_operand (file, op, 0);
8313 if (code == REG && MD_REG_P (REGNO (op)))
8314 fprintf (file, "$ac0");
8315 else if (code == REG && DSP_ACC_REG_P (REGNO (op)))
8316 fprintf (file, "$ac%c", reg_names[REGNO (op)][3]);
8318 output_operand_lossage ("invalid use of '%%%c'", letter);
8326 unsigned int regno = REGNO (op);
8327 if ((letter == 'M' && TARGET_LITTLE_ENDIAN)
8328 || (letter == 'L' && TARGET_BIG_ENDIAN)
8331 else if (letter && letter != 'z' && letter != 'M' && letter != 'L')
8332 output_operand_lossage ("invalid use of '%%%c'", letter);
8333 /* We need to print $0 .. $31 for COP0 registers. */
8334 if (COP0_REG_P (regno))
8335 fprintf (file, "$%s", ®_names[regno][4]);
8337 fprintf (file, "%s", reg_names[regno]);
8343 output_address (plus_constant (Pmode, XEXP (op, 0), 4));
8344 else if (letter == 'b')
8346 gcc_assert (REG_P (XEXP (op, 0)));
8347 mips_print_operand (file, XEXP (op, 0), 0);
8349 else if (letter && letter != 'z')
8350 output_operand_lossage ("invalid use of '%%%c'", letter);
8352 output_address (XEXP (op, 0));
8356 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op)))
8357 fputs (reg_names[GP_REG_FIRST], file);
8358 else if (letter && letter != 'z')
8359 output_operand_lossage ("invalid use of '%%%c'", letter);
8360 else if (CONST_GP_P (op))
8361 fputs (reg_names[GLOBAL_POINTER_REGNUM], file);
8363 output_addr_const (file, mips_strip_unspec_address (op));
8369 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
8372 mips_print_operand_address (FILE *file, rtx x)
8374 struct mips_address_info addr;
8376 if (mips_classify_address (&addr, x, word_mode, true))
8380 mips_print_operand (file, addr.offset, 0);
8381 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8384 case ADDRESS_LO_SUM:
8385 mips_print_operand_reloc (file, addr.offset, SYMBOL_CONTEXT_MEM,
8387 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]);
8390 case ADDRESS_CONST_INT:
8391 output_addr_const (file, x);
8392 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]);
8395 case ADDRESS_SYMBOLIC:
8396 output_addr_const (file, mips_strip_unspec_address (x));
8402 /* Implement TARGET_ENCODE_SECTION_INFO. */
8405 mips_encode_section_info (tree decl, rtx rtl, int first)
8407 default_encode_section_info (decl, rtl, first);
8409 if (TREE_CODE (decl) == FUNCTION_DECL)
8411 rtx symbol = XEXP (rtl, 0);
8412 tree type = TREE_TYPE (decl);
8414 /* Encode whether the symbol is short or long. */
8415 if ((TARGET_LONG_CALLS && !mips_near_type_p (type))
8416 || mips_far_type_p (type))
8417 SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_LONG_CALL;
8421 /* Implement TARGET_SELECT_RTX_SECTION. */
8424 mips_select_rtx_section (enum machine_mode mode, rtx x,
8425 unsigned HOST_WIDE_INT align)
8427 /* ??? Consider using mergeable small data sections. */
8428 if (mips_rtx_constant_in_small_data_p (mode))
8429 return get_named_section (NULL, ".sdata", 0);
8431 return default_elf_select_rtx_section (mode, x, align);
8434 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
8436 The complication here is that, with the combination TARGET_ABICALLS
8437 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
8438 absolute addresses, and should therefore not be included in the
8439 read-only part of a DSO. Handle such cases by selecting a normal
8440 data section instead of a read-only one. The logic apes that in
8441 default_function_rodata_section. */
8444 mips_function_rodata_section (tree decl)
8446 if (!TARGET_ABICALLS || TARGET_ABSOLUTE_ABICALLS || TARGET_GPWORD)
8447 return default_function_rodata_section (decl);
8449 if (decl && DECL_SECTION_NAME (decl))
8451 const char *name = DECL_SECTION_NAME (decl);
8452 if (DECL_COMDAT_GROUP (decl) && strncmp (name, ".gnu.linkonce.t.", 16) == 0)
8454 char *rname = ASTRDUP (name);
8456 return get_section (rname, SECTION_LINKONCE | SECTION_WRITE, decl);
8458 else if (flag_function_sections
8459 && flag_data_sections
8460 && strncmp (name, ".text.", 6) == 0)
8462 char *rname = ASTRDUP (name);
8463 memcpy (rname + 1, "data", 4);
8464 return get_section (rname, SECTION_WRITE, decl);
8467 return data_section;
8470 /* Implement TARGET_IN_SMALL_DATA_P. */
8473 mips_in_small_data_p (const_tree decl)
8475 unsigned HOST_WIDE_INT size;
8477 if (TREE_CODE (decl) == STRING_CST || TREE_CODE (decl) == FUNCTION_DECL)
8480 /* We don't yet generate small-data references for -mabicalls
8481 or VxWorks RTP code. See the related -G handling in
8482 mips_option_override. */
8483 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
8486 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
8490 /* Reject anything that isn't in a known small-data section. */
8491 name = DECL_SECTION_NAME (decl);
8492 if (strcmp (name, ".sdata") != 0 && strcmp (name, ".sbss") != 0)
8495 /* If a symbol is defined externally, the assembler will use the
8496 usual -G rules when deciding how to implement macros. */
8497 if (mips_lo_relocs[SYMBOL_GP_RELATIVE] || !DECL_EXTERNAL (decl))
8500 else if (TARGET_EMBEDDED_DATA)
8502 /* Don't put constants into the small data section: we want them
8503 to be in ROM rather than RAM. */
8504 if (TREE_CODE (decl) != VAR_DECL)
8507 if (TREE_READONLY (decl)
8508 && !TREE_SIDE_EFFECTS (decl)
8509 && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
8513 /* Enforce -mlocal-sdata. */
8514 if (!TARGET_LOCAL_SDATA && !TREE_PUBLIC (decl))
8517 /* Enforce -mextern-sdata. */
8518 if (!TARGET_EXTERN_SDATA && DECL_P (decl))
8520 if (DECL_EXTERNAL (decl))
8522 if (DECL_COMMON (decl) && DECL_INITIAL (decl) == NULL)
8526 /* We have traditionally not treated zero-sized objects as small data,
8527 so this is now effectively part of the ABI. */
8528 size = int_size_in_bytes (TREE_TYPE (decl));
8529 return size > 0 && size <= mips_small_data_threshold;
8532 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
8533 anchors for small data: the GP register acts as an anchor in that
8534 case. We also don't want to use them for PC-relative accesses,
8535 where the PC acts as an anchor. */
8538 mips_use_anchors_for_symbol_p (const_rtx symbol)
8540 switch (mips_classify_symbol (symbol, SYMBOL_CONTEXT_MEM))
8542 case SYMBOL_PC_RELATIVE:
8543 case SYMBOL_GP_RELATIVE:
8547 return default_use_anchors_for_symbol_p (symbol);
8551 /* The MIPS debug format wants all automatic variables and arguments
8552 to be in terms of the virtual frame pointer (stack pointer before
8553 any adjustment in the function), while the MIPS 3.0 linker wants
8554 the frame pointer to be the stack pointer after the initial
8555 adjustment. So, we do the adjustment here. The arg pointer (which
8556 is eliminated) points to the virtual frame pointer, while the frame
8557 pointer (which may be eliminated) points to the stack pointer after
8558 the initial adjustments. */
8561 mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
8563 rtx offset2 = const0_rtx;
8564 rtx reg = eliminate_constant_term (addr, &offset2);
8567 offset = INTVAL (offset2);
8569 if (reg == stack_pointer_rtx
8570 || reg == frame_pointer_rtx
8571 || reg == hard_frame_pointer_rtx)
8573 offset -= cfun->machine->frame.total_size;
8574 if (reg == hard_frame_pointer_rtx)
8575 offset += cfun->machine->frame.hard_frame_pointer_offset;
8581 /* Implement ASM_OUTPUT_EXTERNAL. */
8584 mips_output_external (FILE *file, tree decl, const char *name)
8586 default_elf_asm_output_external (file, decl, name);
8588 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
8589 set in order to avoid putting out names that are never really
8591 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl)))
8593 if (!TARGET_EXPLICIT_RELOCS && mips_in_small_data_p (decl))
8595 /* When using assembler macros, emit .extern directives for
8596 all small-data externs so that the assembler knows how
8599 In most cases it would be safe (though pointless) to emit
8600 .externs for other symbols too. One exception is when an
8601 object is within the -G limit but declared by the user to
8602 be in a section other than .sbss or .sdata. */
8603 fputs ("\t.extern\t", file);
8604 assemble_name (file, name);
8605 fprintf (file, ", " HOST_WIDE_INT_PRINT_DEC "\n",
8606 int_size_in_bytes (TREE_TYPE (decl)));
8611 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
8614 mips_output_filename (FILE *stream, const char *name)
8616 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
8618 if (write_symbols == DWARF2_DEBUG)
8620 else if (mips_output_filename_first_time)
8622 mips_output_filename_first_time = 0;
8623 num_source_filenames += 1;
8624 current_function_file = name;
8625 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8626 output_quoted_string (stream, name);
8627 putc ('\n', stream);
8629 /* If we are emitting stabs, let dbxout.c handle this (except for
8630 the mips_output_filename_first_time case). */
8631 else if (write_symbols == DBX_DEBUG)
8633 else if (name != current_function_file
8634 && strcmp (name, current_function_file) != 0)
8636 num_source_filenames += 1;
8637 current_function_file = name;
8638 fprintf (stream, "\t.file\t%d ", num_source_filenames);
8639 output_quoted_string (stream, name);
8640 putc ('\n', stream);
8644 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
8646 static void ATTRIBUTE_UNUSED
8647 mips_output_dwarf_dtprel (FILE *file, int size, rtx x)
8652 fputs ("\t.dtprelword\t", file);
8656 fputs ("\t.dtpreldword\t", file);
8662 output_addr_const (file, x);
8663 fputs ("+0x8000", file);
8666 /* Implement TARGET_DWARF_REGISTER_SPAN. */
8669 mips_dwarf_register_span (rtx reg)
8672 enum machine_mode mode;
8674 /* By default, GCC maps increasing register numbers to increasing
8675 memory locations, but paired FPRs are always little-endian,
8676 regardless of the prevailing endianness. */
8677 mode = GET_MODE (reg);
8678 if (FP_REG_P (REGNO (reg))
8679 && TARGET_BIG_ENDIAN
8680 && MAX_FPRS_PER_FMT > 1
8681 && GET_MODE_SIZE (mode) > UNITS_PER_FPREG)
8683 gcc_assert (GET_MODE_SIZE (mode) == UNITS_PER_HWFPVALUE);
8684 high = mips_subword (reg, true);
8685 low = mips_subword (reg, false);
8686 return gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, high, low));
8692 /* DSP ALU can bypass data with no delays for the following pairs. */
8693 enum insn_code dspalu_bypass_table[][2] =
8695 {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
8696 {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
8697 {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
8698 {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
8699 {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
8700 {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
8701 {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
8702 {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
8706 mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
8709 int num_bypass = ARRAY_SIZE (dspalu_bypass_table);
8710 enum insn_code out_icode = (enum insn_code) INSN_CODE (out_insn);
8711 enum insn_code in_icode = (enum insn_code) INSN_CODE (in_insn);
8713 for (i = 0; i < num_bypass; i++)
8715 if (out_icode == dspalu_bypass_table[i][0]
8716 && in_icode == dspalu_bypass_table[i][1])
8722 /* Implement ASM_OUTPUT_ASCII. */
8725 mips_output_ascii (FILE *stream, const char *string, size_t len)
8731 fprintf (stream, "\t.ascii\t\"");
8732 for (i = 0; i < len; i++)
8736 c = (unsigned char) string[i];
8739 if (c == '\\' || c == '\"')
8741 putc ('\\', stream);
8749 fprintf (stream, "\\%03o", c);
8753 if (cur_pos > 72 && i+1 < len)
8756 fprintf (stream, "\"\n\t.ascii\t\"");
8759 fprintf (stream, "\"\n");
8762 /* Return the pseudo-op for full SYMBOL_(D)TPREL address *ADDR.
8763 Update *ADDR with the operand that should be printed. */
8766 mips_output_tls_reloc_directive (rtx *addr)
8768 enum mips_symbol_type type;
8770 type = mips_classify_symbolic_expression (*addr, SYMBOL_CONTEXT_LEA);
8771 *addr = mips_strip_unspec_address (*addr);
8775 return Pmode == SImode ? ".dtprelword\t%0" : ".dtpreldword\t%0";
8778 return Pmode == SImode ? ".tprelword\t%0" : ".tpreldword\t%0";
8785 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8786 macros, mark the symbol as written so that mips_asm_output_external
8787 won't emit an .extern for it. STREAM is the output file, NAME is the
8788 name of the symbol, INIT_STRING is the string that should be written
8789 before the symbol and FINAL_STRING is the string that should be
8790 written after it. FINAL_STRING is a printf format that consumes the
8791 remaining arguments. */
8794 mips_declare_object (FILE *stream, const char *name, const char *init_string,
8795 const char *final_string, ...)
8799 fputs (init_string, stream);
8800 assemble_name (stream, name);
8801 va_start (ap, final_string);
8802 vfprintf (stream, final_string, ap);
8805 if (!TARGET_EXPLICIT_RELOCS)
8807 tree name_tree = get_identifier (name);
8808 TREE_ASM_WRITTEN (name_tree) = 1;
8812 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8813 NAME is the name of the object and ALIGN is the required alignment
8814 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8815 alignment argument. */
8818 mips_declare_common_object (FILE *stream, const char *name,
8819 const char *init_string,
8820 unsigned HOST_WIDE_INT size,
8821 unsigned int align, bool takes_alignment_p)
8823 if (!takes_alignment_p)
8825 size += (align / BITS_PER_UNIT) - 1;
8826 size -= size % (align / BITS_PER_UNIT);
8827 mips_declare_object (stream, name, init_string,
8828 "," HOST_WIDE_INT_PRINT_UNSIGNED "\n", size);
8831 mips_declare_object (stream, name, init_string,
8832 "," HOST_WIDE_INT_PRINT_UNSIGNED ",%u\n",
8833 size, align / BITS_PER_UNIT);
8836 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8837 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8840 mips_output_aligned_decl_common (FILE *stream, tree decl, const char *name,
8841 unsigned HOST_WIDE_INT size,
8844 /* If the target wants uninitialized const declarations in
8845 .rdata then don't put them in .comm. */
8846 if (TARGET_EMBEDDED_DATA
8847 && TARGET_UNINIT_CONST_IN_RODATA
8848 && TREE_CODE (decl) == VAR_DECL
8849 && TREE_READONLY (decl)
8850 && (DECL_INITIAL (decl) == 0 || DECL_INITIAL (decl) == error_mark_node))
8852 if (TREE_PUBLIC (decl) && DECL_NAME (decl))
8853 targetm.asm_out.globalize_label (stream, name);
8855 switch_to_section (readonly_data_section);
8856 ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
8857 mips_declare_object (stream, name, "",
8858 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n",
8862 mips_declare_common_object (stream, name, "\n\t.comm\t",
8866 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8867 extern int size_directive_output;
8869 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8870 definitions except that it uses mips_declare_object to emit the label. */
8873 mips_declare_object_name (FILE *stream, const char *name,
8874 tree decl ATTRIBUTE_UNUSED)
8876 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8877 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8880 size_directive_output = 0;
8881 if (!flag_inhibit_size_directive && DECL_SIZE (decl))
8885 size_directive_output = 1;
8886 size = int_size_in_bytes (TREE_TYPE (decl));
8887 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8890 mips_declare_object (stream, name, "", ":\n");
8893 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8896 mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
8900 name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
8901 if (!flag_inhibit_size_directive
8902 && DECL_SIZE (decl) != 0
8905 && DECL_INITIAL (decl) == error_mark_node
8906 && !size_directive_output)
8910 size_directive_output = 1;
8911 size = int_size_in_bytes (TREE_TYPE (decl));
8912 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8917 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8918 with the current ABI. */
8921 mips_mdebug_abi_name (void)
8934 return TARGET_64BIT ? "eabi64" : "eabi32";
8940 /* Implement TARGET_ASM_FILE_START. */
8943 mips_file_start (void)
8945 default_file_start ();
8947 /* Generate a special section to describe the ABI switches used to
8948 produce the resultant binary. */
8950 /* Record the ABI itself. Modern versions of binutils encode
8951 this information in the ELF header flags, but GDB needs the
8952 information in order to correctly debug binaries produced by
8953 older binutils. See the function mips_gdbarch_init in
8955 fprintf (asm_out_file, "\t.section .mdebug.%s\n\t.previous\n",
8956 mips_mdebug_abi_name ());
8958 /* There is no ELF header flag to distinguish long32 forms of the
8959 EABI from long64 forms. Emit a special section to help tools
8960 such as GDB. Do the same for o64, which is sometimes used with
8962 if (mips_abi == ABI_EABI || mips_abi == ABI_O64)
8963 fprintf (asm_out_file, "\t.section .gcc_compiled_long%d\n"
8964 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
8966 /* Record the NaN encoding. */
8967 if (HAVE_AS_NAN || mips_nan != MIPS_IEEE_754_DEFAULT)
8968 fprintf (asm_out_file, "\t.nan\t%s\n",
8969 mips_nan == MIPS_IEEE_754_2008 ? "2008" : "legacy");
8971 #ifdef HAVE_AS_GNU_ATTRIBUTE
8975 /* No floating-point operations, -mno-float. */
8976 if (TARGET_NO_FLOAT)
8978 /* Soft-float code, -msoft-float. */
8979 else if (!TARGET_HARD_FLOAT_ABI)
8981 /* Single-float code, -msingle-float. */
8982 else if (!TARGET_DOUBLE_FLOAT)
8984 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8985 else if (!TARGET_64BIT && TARGET_FLOAT64)
8987 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8991 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n", attr);
8995 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8996 if (TARGET_ABICALLS)
8998 fprintf (asm_out_file, "\t.abicalls\n");
8999 if (TARGET_ABICALLS_PIC0)
9000 fprintf (asm_out_file, "\t.option\tpic0\n");
9003 if (flag_verbose_asm)
9004 fprintf (asm_out_file, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
9006 mips_small_data_threshold, mips_arch_info->name, mips_isa);
9009 /* Implement TARGET_ASM_CODE_END. */
9012 mips_code_end (void)
9014 mips_finish_stub (&mips16_rdhwr_stub);
9015 mips_finish_stub (&mips16_get_fcsr_stub);
9016 mips_finish_stub (&mips16_set_fcsr_stub);
9019 /* Make the last instruction frame-related and note that it performs
9020 the operation described by FRAME_PATTERN. */
9023 mips_set_frame_expr (rtx frame_pattern)
9027 insn = get_last_insn ();
9028 RTX_FRAME_RELATED_P (insn) = 1;
9029 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
9034 /* Return a frame-related rtx that stores REG at MEM.
9035 REG must be a single register. */
9038 mips_frame_set (rtx mem, rtx reg)
9042 set = gen_rtx_SET (VOIDmode, mem, reg);
9043 RTX_FRAME_RELATED_P (set) = 1;
9048 /* Record that the epilogue has restored call-saved register REG. */
9051 mips_add_cfa_restore (rtx reg)
9053 mips_epilogue.cfa_restores = alloc_reg_note (REG_CFA_RESTORE, reg,
9054 mips_epilogue.cfa_restores);
9057 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
9058 mips16e_s2_s8_regs[X], it must also save the registers in indexes
9059 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
9060 static const unsigned char mips16e_s2_s8_regs[] = {
9061 30, 23, 22, 21, 20, 19, 18
9063 static const unsigned char mips16e_a0_a3_regs[] = {
9067 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
9068 ordered from the uppermost in memory to the lowest in memory. */
9069 static const unsigned char mips16e_save_restore_regs[] = {
9070 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
9073 /* Return the index of the lowest X in the range [0, SIZE) for which
9074 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
9077 mips16e_find_first_register (unsigned int mask, const unsigned char *regs,
9082 for (i = 0; i < size; i++)
9083 if (BITSET_P (mask, regs[i]))
9089 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
9090 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
9091 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
9092 is true for all indexes (X, SIZE). */
9095 mips16e_mask_registers (unsigned int *mask_ptr, const unsigned char *regs,
9096 unsigned int size, unsigned int *num_regs_ptr)
9100 i = mips16e_find_first_register (*mask_ptr, regs, size);
9101 for (i++; i < size; i++)
9102 if (!BITSET_P (*mask_ptr, regs[i]))
9105 *mask_ptr |= 1 << regs[i];
9109 /* Return a simplified form of X using the register values in REG_VALUES.
9110 REG_VALUES[R] is the last value assigned to hard register R, or null
9111 if R has not been modified.
9113 This function is rather limited, but is good enough for our purposes. */
9116 mips16e_collect_propagate_value (rtx x, rtx *reg_values)
9118 x = avoid_constant_pool_reference (x);
9122 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9123 return simplify_gen_unary (GET_CODE (x), GET_MODE (x),
9124 x0, GET_MODE (XEXP (x, 0)));
9127 if (ARITHMETIC_P (x))
9129 rtx x0 = mips16e_collect_propagate_value (XEXP (x, 0), reg_values);
9130 rtx x1 = mips16e_collect_propagate_value (XEXP (x, 1), reg_values);
9131 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), x0, x1);
9135 && reg_values[REGNO (x)]
9136 && !rtx_unstable_p (reg_values[REGNO (x)]))
9137 return reg_values[REGNO (x)];
9142 /* Return true if (set DEST SRC) stores an argument register into its
9143 caller-allocated save slot, storing the number of that argument
9144 register in *REGNO_PTR if so. REG_VALUES is as for
9145 mips16e_collect_propagate_value. */
9148 mips16e_collect_argument_save_p (rtx dest, rtx src, rtx *reg_values,
9149 unsigned int *regno_ptr)
9151 unsigned int argno, regno;
9152 HOST_WIDE_INT offset, required_offset;
9155 /* Check that this is a word-mode store. */
9156 if (!MEM_P (dest) || !REG_P (src) || GET_MODE (dest) != word_mode)
9159 /* Check that the register being saved is an unmodified argument
9161 regno = REGNO (src);
9162 if (!IN_RANGE (regno, GP_ARG_FIRST, GP_ARG_LAST) || reg_values[regno])
9164 argno = regno - GP_ARG_FIRST;
9166 /* Check whether the address is an appropriate stack-pointer or
9167 frame-pointer access. */
9168 addr = mips16e_collect_propagate_value (XEXP (dest, 0), reg_values);
9169 mips_split_plus (addr, &base, &offset);
9170 required_offset = cfun->machine->frame.total_size + argno * UNITS_PER_WORD;
9171 if (base == hard_frame_pointer_rtx)
9172 required_offset -= cfun->machine->frame.hard_frame_pointer_offset;
9173 else if (base != stack_pointer_rtx)
9175 if (offset != required_offset)
9182 /* A subroutine of mips_expand_prologue, called only when generating
9183 MIPS16e SAVE instructions. Search the start of the function for any
9184 instructions that save argument registers into their caller-allocated
9185 save slots. Delete such instructions and return a value N such that
9186 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
9187 instructions redundant. */
9190 mips16e_collect_argument_saves (void)
9192 rtx reg_values[FIRST_PSEUDO_REGISTER];
9193 rtx insn, next, set, dest, src;
9194 unsigned int nargs, regno;
9196 push_topmost_sequence ();
9198 memset (reg_values, 0, sizeof (reg_values));
9199 for (insn = get_insns (); insn; insn = next)
9201 next = NEXT_INSN (insn);
9202 if (NOTE_P (insn) || DEBUG_INSN_P (insn))
9208 set = PATTERN (insn);
9209 if (GET_CODE (set) != SET)
9212 dest = SET_DEST (set);
9213 src = SET_SRC (set);
9214 if (mips16e_collect_argument_save_p (dest, src, reg_values, ®no))
9216 if (!BITSET_P (cfun->machine->frame.mask, regno))
9219 nargs = MAX (nargs, (regno - GP_ARG_FIRST) + 1);
9222 else if (REG_P (dest) && GET_MODE (dest) == word_mode)
9223 reg_values[REGNO (dest)]
9224 = mips16e_collect_propagate_value (src, reg_values);
9228 pop_topmost_sequence ();
9233 /* Return a move between register REGNO and memory location SP + OFFSET.
9234 REG_PARM_P is true if SP + OFFSET belongs to REG_PARM_STACK_SPACE.
9235 Make the move a load if RESTORE_P, otherwise make it a store. */
9238 mips16e_save_restore_reg (bool restore_p, bool reg_parm_p,
9239 HOST_WIDE_INT offset, unsigned int regno)
9243 mem = gen_frame_mem (SImode, plus_constant (Pmode, stack_pointer_rtx,
9245 reg = gen_rtx_REG (SImode, regno);
9248 mips_add_cfa_restore (reg);
9249 return gen_rtx_SET (VOIDmode, reg, mem);
9252 return gen_rtx_SET (VOIDmode, mem, reg);
9253 return mips_frame_set (mem, reg);
9256 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
9257 The instruction must:
9259 - Allocate or deallocate SIZE bytes in total; SIZE is known
9262 - Save or restore as many registers in *MASK_PTR as possible.
9263 The instruction saves the first registers at the top of the
9264 allocated area, with the other registers below it.
9266 - Save NARGS argument registers above the allocated area.
9268 (NARGS is always zero if RESTORE_P.)
9270 The SAVE and RESTORE instructions cannot save and restore all general
9271 registers, so there may be some registers left over for the caller to
9272 handle. Destructively modify *MASK_PTR so that it contains the registers
9273 that still need to be saved or restored. The caller can save these
9274 registers in the memory immediately below *OFFSET_PTR, which is a
9275 byte offset from the bottom of the allocated stack area. */
9278 mips16e_build_save_restore (bool restore_p, unsigned int *mask_ptr,
9279 HOST_WIDE_INT *offset_ptr, unsigned int nargs,
9283 HOST_WIDE_INT offset, top_offset;
9284 unsigned int i, regno;
9287 gcc_assert (cfun->machine->frame.num_fp == 0);
9289 /* Calculate the number of elements in the PARALLEL. We need one element
9290 for the stack adjustment, one for each argument register save, and one
9291 for each additional register move. */
9293 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9294 if (BITSET_P (*mask_ptr, mips16e_save_restore_regs[i]))
9297 /* Create the final PARALLEL. */
9298 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (n));
9301 /* Add the stack pointer adjustment. */
9302 set = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
9303 plus_constant (Pmode, stack_pointer_rtx,
9304 restore_p ? size : -size));
9305 RTX_FRAME_RELATED_P (set) = 1;
9306 XVECEXP (pattern, 0, n++) = set;
9308 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9309 top_offset = restore_p ? size : 0;
9311 /* Save the arguments. */
9312 for (i = 0; i < nargs; i++)
9314 offset = top_offset + i * UNITS_PER_WORD;
9315 set = mips16e_save_restore_reg (restore_p, true, offset,
9317 XVECEXP (pattern, 0, n++) = set;
9320 /* Then fill in the other register moves. */
9321 offset = top_offset;
9322 for (i = 0; i < ARRAY_SIZE (mips16e_save_restore_regs); i++)
9324 regno = mips16e_save_restore_regs[i];
9325 if (BITSET_P (*mask_ptr, regno))
9327 offset -= UNITS_PER_WORD;
9328 set = mips16e_save_restore_reg (restore_p, false, offset, regno);
9329 XVECEXP (pattern, 0, n++) = set;
9330 *mask_ptr &= ~(1 << regno);
9334 /* Tell the caller what offset it should use for the remaining registers. */
9335 *offset_ptr = size + (offset - top_offset);
9337 gcc_assert (n == XVECLEN (pattern, 0));
9342 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
9343 pointer. Return true if PATTERN matches the kind of instruction
9344 generated by mips16e_build_save_restore. If INFO is nonnull,
9345 initialize it when returning true. */
9348 mips16e_save_restore_pattern_p (rtx pattern, HOST_WIDE_INT adjust,
9349 struct mips16e_save_restore_info *info)
9351 unsigned int i, nargs, mask, extra;
9352 HOST_WIDE_INT top_offset, save_offset, offset;
9353 rtx set, reg, mem, base;
9356 if (!GENERATE_MIPS16E_SAVE_RESTORE)
9359 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
9360 top_offset = adjust > 0 ? adjust : 0;
9362 /* Interpret all other members of the PARALLEL. */
9363 save_offset = top_offset - UNITS_PER_WORD;
9367 for (n = 1; n < XVECLEN (pattern, 0); n++)
9369 /* Check that we have a SET. */
9370 set = XVECEXP (pattern, 0, n);
9371 if (GET_CODE (set) != SET)
9374 /* Check that the SET is a load (if restoring) or a store
9376 mem = adjust > 0 ? SET_SRC (set) : SET_DEST (set);
9380 /* Check that the address is the sum of the stack pointer and a
9381 possibly-zero constant offset. */
9382 mips_split_plus (XEXP (mem, 0), &base, &offset);
9383 if (base != stack_pointer_rtx)
9386 /* Check that SET's other operand is a register. */
9387 reg = adjust > 0 ? SET_DEST (set) : SET_SRC (set);
9391 /* Check for argument saves. */
9392 if (offset == top_offset + nargs * UNITS_PER_WORD
9393 && REGNO (reg) == GP_ARG_FIRST + nargs)
9395 else if (offset == save_offset)
9397 while (mips16e_save_restore_regs[i++] != REGNO (reg))
9398 if (i == ARRAY_SIZE (mips16e_save_restore_regs))
9401 mask |= 1 << REGNO (reg);
9402 save_offset -= UNITS_PER_WORD;
9408 /* Check that the restrictions on register ranges are met. */
9410 mips16e_mask_registers (&mask, mips16e_s2_s8_regs,
9411 ARRAY_SIZE (mips16e_s2_s8_regs), &extra);
9412 mips16e_mask_registers (&mask, mips16e_a0_a3_regs,
9413 ARRAY_SIZE (mips16e_a0_a3_regs), &extra);
9417 /* Make sure that the topmost argument register is not saved twice.
9418 The checks above ensure that the same is then true for the other
9419 argument registers. */
9420 if (nargs > 0 && BITSET_P (mask, GP_ARG_FIRST + nargs - 1))
9423 /* Pass back information, if requested. */
9426 info->nargs = nargs;
9428 info->size = (adjust > 0 ? adjust : -adjust);
9434 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
9435 for the register range [MIN_REG, MAX_REG]. Return a pointer to
9436 the null terminator. */
9439 mips16e_add_register_range (char *s, unsigned int min_reg,
9440 unsigned int max_reg)
9442 if (min_reg != max_reg)
9443 s += sprintf (s, ",%s-%s", reg_names[min_reg], reg_names[max_reg]);
9445 s += sprintf (s, ",%s", reg_names[min_reg]);
9449 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
9450 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
9453 mips16e_output_save_restore (rtx pattern, HOST_WIDE_INT adjust)
9455 static char buffer[300];
9457 struct mips16e_save_restore_info info;
9458 unsigned int i, end;
9461 /* Parse the pattern. */
9462 if (!mips16e_save_restore_pattern_p (pattern, adjust, &info))
9465 /* Add the mnemonic. */
9466 s = strcpy (buffer, adjust > 0 ? "restore\t" : "save\t");
9469 /* Save the arguments. */
9471 s += sprintf (s, "%s-%s,", reg_names[GP_ARG_FIRST],
9472 reg_names[GP_ARG_FIRST + info.nargs - 1]);
9473 else if (info.nargs == 1)
9474 s += sprintf (s, "%s,", reg_names[GP_ARG_FIRST]);
9476 /* Emit the amount of stack space to allocate or deallocate. */
9477 s += sprintf (s, "%d", (int) info.size);
9479 /* Save or restore $16. */
9480 if (BITSET_P (info.mask, 16))
9481 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 16]);
9483 /* Save or restore $17. */
9484 if (BITSET_P (info.mask, 17))
9485 s += sprintf (s, ",%s", reg_names[GP_REG_FIRST + 17]);
9487 /* Save or restore registers in the range $s2...$s8, which
9488 mips16e_s2_s8_regs lists in decreasing order. Note that this
9489 is a software register range; the hardware registers are not
9490 numbered consecutively. */
9491 end = ARRAY_SIZE (mips16e_s2_s8_regs);
9492 i = mips16e_find_first_register (info.mask, mips16e_s2_s8_regs, end);
9494 s = mips16e_add_register_range (s, mips16e_s2_s8_regs[end - 1],
9495 mips16e_s2_s8_regs[i]);
9497 /* Save or restore registers in the range $a0...$a3. */
9498 end = ARRAY_SIZE (mips16e_a0_a3_regs);
9499 i = mips16e_find_first_register (info.mask, mips16e_a0_a3_regs, end);
9501 s = mips16e_add_register_range (s, mips16e_a0_a3_regs[i],
9502 mips16e_a0_a3_regs[end - 1]);
9504 /* Save or restore $31. */
9505 if (BITSET_P (info.mask, RETURN_ADDR_REGNUM))
9506 s += sprintf (s, ",%s", reg_names[RETURN_ADDR_REGNUM]);
9511 /* Return true if the current function returns its value in a floating-point
9512 register in MIPS16 mode. */
9515 mips16_cfun_returns_in_fpr_p (void)
9517 tree return_type = DECL_RESULT (current_function_decl);
9518 return (TARGET_MIPS16
9519 && TARGET_HARD_FLOAT_ABI
9520 && !aggregate_value_p (return_type, current_function_decl)
9521 && mips_return_mode_in_fpr_p (DECL_MODE (return_type)));
9524 /* Return true if predicate PRED is true for at least one instruction.
9525 Cache the result in *CACHE, and assume that the result is true
9526 if *CACHE is already true. */
9529 mips_find_gp_ref (bool *cache, bool (*pred) (rtx))
9535 push_topmost_sequence ();
9536 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9537 if (USEFUL_INSN_P (insn) && pred (insn))
9542 pop_topmost_sequence ();
9547 /* Return true if INSN refers to the global pointer in an "inflexible" way.
9548 See mips_cfun_has_inflexible_gp_ref_p for details. */
9551 mips_insn_has_inflexible_gp_ref_p (rtx insn)
9553 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
9554 indicate that the target could be a traditional MIPS
9555 lazily-binding stub. */
9556 return find_reg_fusage (insn, USE, pic_offset_table_rtx);
9559 /* Return true if the current function refers to the global pointer
9560 in a way that forces $28 to be valid. This means that we can't
9561 change the choice of global pointer, even for NewABI code.
9563 One example of this (and one which needs several checks) is that
9564 $28 must be valid when calling traditional MIPS lazy-binding stubs.
9565 (This restriction does not apply to PLTs.) */
9568 mips_cfun_has_inflexible_gp_ref_p (void)
9570 /* If the function has a nonlocal goto, $28 must hold the correct
9571 global pointer for the target function. That is, the target
9572 of the goto implicitly uses $28. */
9573 if (crtl->has_nonlocal_goto)
9576 if (TARGET_ABICALLS_PIC2)
9578 /* Symbolic accesses implicitly use the global pointer unless
9579 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
9580 might go to traditional MIPS lazy-binding stubs. */
9581 if (!TARGET_EXPLICIT_RELOCS)
9584 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
9585 can be lazily-bound. */
9589 /* MIPS16 functions that return in FPRs need to call an
9590 external libgcc routine. This call is only made explict
9591 during mips_expand_epilogue, and it too might be lazily bound. */
9592 if (mips16_cfun_returns_in_fpr_p ())
9596 return mips_find_gp_ref (&cfun->machine->has_inflexible_gp_insn_p,
9597 mips_insn_has_inflexible_gp_ref_p);
9600 /* Return true if INSN refers to the global pointer in a "flexible" way.
9601 See mips_cfun_has_flexible_gp_ref_p for details. */
9604 mips_insn_has_flexible_gp_ref_p (rtx insn)
9606 return (get_attr_got (insn) != GOT_UNSET
9607 || mips_small_data_pattern_p (PATTERN (insn))
9608 || reg_overlap_mentioned_p (pic_offset_table_rtx, PATTERN (insn)));
9611 /* Return true if the current function references the global pointer,
9612 but if those references do not inherently require the global pointer
9613 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
9616 mips_cfun_has_flexible_gp_ref_p (void)
9618 /* Reload can sometimes introduce constant pool references
9619 into a function that otherwise didn't need them. For example,
9620 suppose we have an instruction like:
9622 (set (reg:DF R1) (float:DF (reg:SI R2)))
9624 If R2 turns out to be a constant such as 1, the instruction may
9625 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
9626 the option of using this constant if R2 doesn't get allocated
9629 In cases like these, reload will have added the constant to the
9630 pool but no instruction will yet refer to it. */
9631 if (TARGET_ABICALLS_PIC2 && !reload_completed && crtl->uses_const_pool)
9634 return mips_find_gp_ref (&cfun->machine->has_flexible_gp_insn_p,
9635 mips_insn_has_flexible_gp_ref_p);
9638 /* Return the register that should be used as the global pointer
9639 within this function. Return INVALID_REGNUM if the function
9640 doesn't need a global pointer. */
9643 mips_global_pointer (void)
9647 /* $gp is always available unless we're using a GOT. */
9648 if (!TARGET_USE_GOT)
9649 return GLOBAL_POINTER_REGNUM;
9651 /* If there are inflexible references to $gp, we must use the
9652 standard register. */
9653 if (mips_cfun_has_inflexible_gp_ref_p ())
9654 return GLOBAL_POINTER_REGNUM;
9656 /* If there are no current references to $gp, then the only uses
9657 we can introduce later are those involved in long branches. */
9658 if (TARGET_ABSOLUTE_JUMPS && !mips_cfun_has_flexible_gp_ref_p ())
9659 return INVALID_REGNUM;
9661 /* If the global pointer is call-saved, try to use a call-clobbered
9663 if (TARGET_CALL_SAVED_GP && crtl->is_leaf)
9664 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
9665 if (!df_regs_ever_live_p (regno)
9666 && call_really_used_regs[regno]
9667 && !fixed_regs[regno]
9668 && regno != PIC_FUNCTION_ADDR_REGNUM)
9671 return GLOBAL_POINTER_REGNUM;
9674 /* Return true if the current function's prologue must load the global
9675 pointer value into pic_offset_table_rtx and store the same value in
9676 the function's cprestore slot (if any).
9678 One problem we have to deal with is that, when emitting GOT-based
9679 position independent code, long-branch sequences will need to load
9680 the address of the branch target from the GOT. We don't know until
9681 the very end of compilation whether (and where) the function needs
9682 long branches, so we must ensure that _any_ branch can access the
9683 global pointer in some form. However, we do not want to pessimize
9684 the usual case in which all branches are short.
9686 We handle this as follows:
9688 (1) During reload, we set cfun->machine->global_pointer to
9689 INVALID_REGNUM if we _know_ that the current function
9690 doesn't need a global pointer. This is only valid if
9691 long branches don't need the GOT.
9693 Otherwise, we assume that we might need a global pointer
9694 and pick an appropriate register.
9696 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
9697 we ensure that the global pointer is available at every
9698 block boundary bar entry and exit. We do this in one of two ways:
9700 - If the function has a cprestore slot, we ensure that this
9701 slot is valid at every branch. However, as explained in
9702 point (6) below, there is no guarantee that pic_offset_table_rtx
9703 itself is valid if new uses of the global pointer are introduced
9704 after the first post-epilogue split.
9706 We guarantee that the cprestore slot is valid by loading it
9707 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
9708 this register live at every block boundary bar function entry
9709 and exit. It is then invalid to move the load (and thus the
9710 preceding store) across a block boundary.
9712 - If the function has no cprestore slot, we guarantee that
9713 pic_offset_table_rtx itself is valid at every branch.
9715 See mips_eh_uses for the handling of the register liveness.
9717 (3) During prologue and epilogue generation, we emit "ghost"
9718 placeholder instructions to manipulate the global pointer.
9720 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
9721 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
9722 that the function needs a global pointer. (There is no need to set
9723 them earlier than this, and doing it as late as possible leads to
9724 fewer false positives.)
9726 (5) If cfun->machine->must_initialize_gp_p is true during a
9727 split_insns pass, we split the ghost instructions into real
9728 instructions. These split instructions can then be optimized in
9729 the usual way. Otherwise, we keep the ghost instructions intact,
9730 and optimize for the case where they aren't needed. We still
9731 have the option of splitting them later, if we need to introduce
9732 new uses of the global pointer.
9734 For example, the scheduler ignores a ghost instruction that
9735 stores $28 to the stack, but it handles the split form of
9736 the ghost instruction as an ordinary store.
9738 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
9739 is true during the first post-epilogue split_insns pass, we split
9740 calls and restore_gp patterns into instructions that explicitly
9741 load pic_offset_table_rtx from the cprestore slot. Otherwise,
9742 we split these patterns into instructions that _don't_ load from
9745 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
9746 time of the split, then any instructions that exist at that time
9747 can make free use of pic_offset_table_rtx. However, if we want
9748 to introduce new uses of the global pointer after the split,
9749 we must explicitly load the value from the cprestore slot, since
9750 pic_offset_table_rtx itself might not be valid at a given point
9753 The idea is that we want to be able to delete redundant
9754 loads from the cprestore slot in the usual case where no
9755 long branches are needed.
9757 (7) If cfun->machine->must_initialize_gp_p is still false at the end
9758 of md_reorg, we decide whether the global pointer is needed for
9759 long branches. If so, we set cfun->machine->must_initialize_gp_p
9760 to true and split the ghost instructions into real instructions
9763 Note that the ghost instructions must have a zero length for three reasons:
9765 - Giving the length of the underlying $gp sequence might cause
9766 us to use long branches in cases where they aren't really needed.
9768 - They would perturb things like alignment calculations.
9770 - More importantly, the hazard detection in md_reorg relies on
9771 empty instructions having a zero length.
9773 If we find a long branch and split the ghost instructions at the
9774 end of md_reorg, the split could introduce more long branches.
9775 That isn't a problem though, because we still do the split before
9776 the final shorten_branches pass.
9778 This is extremely ugly, but it seems like the best compromise between
9779 correctness and efficiency. */
9782 mips_must_initialize_gp_p (void)
9784 return cfun->machine->must_initialize_gp_p;
9787 /* Return true if REGNO is a register that is ordinarily call-clobbered
9788 but must nevertheless be preserved by an interrupt handler. */
9791 mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
9793 if (MD_REG_P (regno))
9796 if (TARGET_DSP && DSP_ACC_REG_P (regno))
9799 if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
9801 /* $0 is hard-wired. */
9802 if (regno == GP_REG_FIRST)
9805 /* The interrupt handler can treat kernel registers as
9806 scratch registers. */
9807 if (KERNEL_REG_P (regno))
9810 /* The function will return the stack pointer to its original value
9812 if (regno == STACK_POINTER_REGNUM)
9815 /* Otherwise, return true for registers that aren't ordinarily
9817 return call_really_used_regs[regno];
9823 /* Return true if the current function should treat register REGNO
9827 mips_cfun_call_saved_reg_p (unsigned int regno)
9829 /* If the user makes an ordinarily-call-saved register global,
9830 that register is no longer call-saved. */
9831 if (global_regs[regno])
9834 /* Interrupt handlers need to save extra registers. */
9835 if (cfun->machine->interrupt_handler_p
9836 && mips_interrupt_extra_call_saved_reg_p (regno))
9839 /* call_insns preserve $28 unless they explicitly say otherwise,
9840 so call_really_used_regs[] treats $28 as call-saved. However,
9841 we want the ABI property rather than the default call_insn
9843 return (regno == GLOBAL_POINTER_REGNUM
9844 ? TARGET_CALL_SAVED_GP
9845 : !call_really_used_regs[regno]);
9848 /* Return true if the function body might clobber register REGNO.
9849 We know that REGNO is call-saved. */
9852 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno)
9854 /* Some functions should be treated as clobbering all call-saved
9856 if (crtl->saves_all_registers)
9859 /* DF handles cases where a register is explicitly referenced in
9860 the rtl. Incoming values are passed in call-clobbered registers,
9861 so we can assume that any live call-saved register is set within
9863 if (df_regs_ever_live_p (regno))
9866 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9867 These clobbers are not explicit in the rtl. */
9868 if (crtl->profile && MIPS_SAVE_REG_FOR_PROFILING_P (regno))
9871 /* If we're using a call-saved global pointer, the function's
9872 prologue will need to set it up. */
9873 if (cfun->machine->global_pointer == regno)
9876 /* The function's prologue will need to set the frame pointer if
9877 frame_pointer_needed. */
9878 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
9881 /* If a MIPS16 function returns a value in FPRs, its epilogue
9882 will need to call an external libgcc routine. This yet-to-be
9883 generated call_insn will clobber $31. */
9884 if (regno == RETURN_ADDR_REGNUM && mips16_cfun_returns_in_fpr_p ())
9887 /* If REGNO is ordinarily call-clobbered, we must assume that any
9888 called function could modify it. */
9889 if (cfun->machine->interrupt_handler_p
9891 && mips_interrupt_extra_call_saved_reg_p (regno))
9897 /* Return true if the current function must save register REGNO. */
9900 mips_save_reg_p (unsigned int regno)
9902 if (mips_cfun_call_saved_reg_p (regno))
9904 if (mips_cfun_might_clobber_call_saved_reg_p (regno))
9907 /* Save both registers in an FPR pair if either one is used. This is
9908 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9909 register to be used without the even register. */
9910 if (FP_REG_P (regno)
9911 && MAX_FPRS_PER_FMT == 2
9912 && mips_cfun_might_clobber_call_saved_reg_p (regno + 1))
9916 /* We need to save the incoming return address if __builtin_eh_return
9917 is being used to set a different return address. */
9918 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return)
9924 /* Populate the current function's mips_frame_info structure.
9926 MIPS stack frames look like:
9928 +-------------------------------+
9930 | incoming stack arguments |
9932 +-------------------------------+
9934 | caller-allocated save area |
9935 A | for register arguments |
9937 +-------------------------------+ <-- incoming stack pointer
9939 | callee-allocated save area |
9940 B | for arguments that are |
9941 | split between registers and |
9944 +-------------------------------+ <-- arg_pointer_rtx
9946 C | callee-allocated save area |
9947 | for register varargs |
9949 +-------------------------------+ <-- frame_pointer_rtx
9950 | | + cop0_sp_offset
9951 | COP0 reg save area | + UNITS_PER_WORD
9953 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9954 | | + UNITS_PER_WORD
9955 | accumulator save area |
9957 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9958 | | + UNITS_PER_HWFPVALUE
9961 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9962 | | + UNITS_PER_WORD
9965 +-------------------------------+ <-- frame_pointer_rtx with
9966 | | \ -fstack-protector
9967 | local variables | | var_size
9969 +-------------------------------+
9971 | $gp save area | | cprestore_size
9973 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9975 | outgoing stack arguments | |
9977 +-------------------------------+ | args_size
9979 | caller-allocated save area | |
9980 | for register arguments | |
9982 +-------------------------------+ <-- stack_pointer_rtx
9983 frame_pointer_rtx without
9985 hard_frame_pointer_rtx for
9988 At least two of A, B and C will be empty.
9990 Dynamic stack allocations such as alloca insert data at point P.
9991 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9992 hard_frame_pointer_rtx unchanged. */
9995 mips_compute_frame_info (void)
9997 struct mips_frame_info *frame;
9998 HOST_WIDE_INT offset, size;
9999 unsigned int regno, i;
10001 /* Set this function's interrupt properties. */
10002 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
10004 if (mips_isa_rev < 2)
10005 error ("the %<interrupt%> attribute requires a MIPS32r2 processor or greater");
10006 else if (TARGET_HARD_FLOAT)
10007 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
10008 else if (TARGET_MIPS16)
10009 error ("interrupt handlers cannot be MIPS16 functions");
10012 cfun->machine->interrupt_handler_p = true;
10013 cfun->machine->use_shadow_register_set_p =
10014 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
10015 cfun->machine->keep_interrupts_masked_p =
10016 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
10017 cfun->machine->use_debug_exception_return_p =
10018 mips_use_debug_exception_return_p (TREE_TYPE
10019 (current_function_decl));
10023 frame = &cfun->machine->frame;
10024 memset (frame, 0, sizeof (*frame));
10025 size = get_frame_size ();
10027 cfun->machine->global_pointer = mips_global_pointer ();
10029 /* The first two blocks contain the outgoing argument area and the $gp save
10030 slot. This area isn't needed in leaf functions, but if the
10031 target-independent frame size is nonzero, we have already committed to
10032 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
10033 if ((size == 0 || FRAME_GROWS_DOWNWARD) && crtl->is_leaf)
10035 /* The MIPS 3.0 linker does not like functions that dynamically
10036 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
10037 looks like we are trying to create a second frame pointer to the
10038 function, so allocate some stack space to make it happy. */
10039 if (cfun->calls_alloca)
10040 frame->args_size = REG_PARM_STACK_SPACE (cfun->decl);
10042 frame->args_size = 0;
10043 frame->cprestore_size = 0;
10047 frame->args_size = crtl->outgoing_args_size;
10048 frame->cprestore_size = MIPS_GP_SAVE_AREA_SIZE;
10050 offset = frame->args_size + frame->cprestore_size;
10052 /* Move above the local variables. */
10053 frame->var_size = MIPS_STACK_ALIGN (size);
10054 offset += frame->var_size;
10056 /* Find out which GPRs we need to save. */
10057 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
10058 if (mips_save_reg_p (regno))
10061 frame->mask |= 1 << (regno - GP_REG_FIRST);
10064 /* If this function calls eh_return, we must also save and restore the
10065 EH data registers. */
10066 if (crtl->calls_eh_return)
10067 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; i++)
10070 frame->mask |= 1 << (EH_RETURN_DATA_REGNO (i) - GP_REG_FIRST);
10073 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
10074 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
10075 save all later registers too. */
10076 if (GENERATE_MIPS16E_SAVE_RESTORE)
10078 mips16e_mask_registers (&frame->mask, mips16e_s2_s8_regs,
10079 ARRAY_SIZE (mips16e_s2_s8_regs), &frame->num_gp);
10080 mips16e_mask_registers (&frame->mask, mips16e_a0_a3_regs,
10081 ARRAY_SIZE (mips16e_a0_a3_regs), &frame->num_gp);
10084 /* Move above the GPR save area. */
10085 if (frame->num_gp > 0)
10087 offset += MIPS_STACK_ALIGN (frame->num_gp * UNITS_PER_WORD);
10088 frame->gp_sp_offset = offset - UNITS_PER_WORD;
10091 /* Find out which FPRs we need to save. This loop must iterate over
10092 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
10093 if (TARGET_HARD_FLOAT)
10094 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
10095 if (mips_save_reg_p (regno))
10097 frame->num_fp += MAX_FPRS_PER_FMT;
10098 frame->fmask |= ~(~0 << MAX_FPRS_PER_FMT) << (regno - FP_REG_FIRST);
10101 /* Move above the FPR save area. */
10102 if (frame->num_fp > 0)
10104 offset += MIPS_STACK_ALIGN (frame->num_fp * UNITS_PER_FPREG);
10105 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
10108 /* Add in space for the interrupt context information. */
10109 if (cfun->machine->interrupt_handler_p)
10112 if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
10115 frame->acc_mask |= (1 << 0);
10118 /* Check accumulators 1, 2, 3. */
10119 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
10120 if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
10123 frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
10126 /* All interrupt context functions need space to preserve STATUS. */
10127 frame->num_cop0_regs++;
10129 /* If we don't keep interrupts masked, we need to save EPC. */
10130 if (!cfun->machine->keep_interrupts_masked_p)
10131 frame->num_cop0_regs++;
10134 /* Move above the accumulator save area. */
10135 if (frame->num_acc > 0)
10137 /* Each accumulator needs 2 words. */
10138 offset += frame->num_acc * 2 * UNITS_PER_WORD;
10139 frame->acc_sp_offset = offset - UNITS_PER_WORD;
10142 /* Move above the COP0 register save area. */
10143 if (frame->num_cop0_regs > 0)
10145 offset += frame->num_cop0_regs * UNITS_PER_WORD;
10146 frame->cop0_sp_offset = offset - UNITS_PER_WORD;
10149 /* Move above the callee-allocated varargs save area. */
10150 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
10151 frame->arg_pointer_offset = offset;
10153 /* Move above the callee-allocated area for pretend stack arguments. */
10154 offset += crtl->args.pretend_args_size;
10155 frame->total_size = offset;
10157 /* Work out the offsets of the save areas from the top of the frame. */
10158 if (frame->gp_sp_offset > 0)
10159 frame->gp_save_offset = frame->gp_sp_offset - offset;
10160 if (frame->fp_sp_offset > 0)
10161 frame->fp_save_offset = frame->fp_sp_offset - offset;
10162 if (frame->acc_sp_offset > 0)
10163 frame->acc_save_offset = frame->acc_sp_offset - offset;
10164 if (frame->num_cop0_regs > 0)
10165 frame->cop0_save_offset = frame->cop0_sp_offset - offset;
10167 /* MIPS16 code offsets the frame pointer by the size of the outgoing
10168 arguments. This tends to increase the chances of using unextended
10169 instructions for local variables and incoming arguments. */
10171 frame->hard_frame_pointer_offset = frame->args_size;
10174 /* Return the style of GP load sequence that is being used for the
10175 current function. */
10177 enum mips_loadgp_style
10178 mips_current_loadgp_style (void)
10180 if (!TARGET_USE_GOT || cfun->machine->global_pointer == INVALID_REGNUM)
10181 return LOADGP_NONE;
10183 if (TARGET_RTP_PIC)
10186 if (TARGET_ABSOLUTE_ABICALLS)
10187 return LOADGP_ABSOLUTE;
10189 return TARGET_NEWABI ? LOADGP_NEWABI : LOADGP_OLDABI;
10192 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
10195 mips_frame_pointer_required (void)
10197 /* If the function contains dynamic stack allocations, we need to
10198 use the frame pointer to access the static parts of the frame. */
10199 if (cfun->calls_alloca)
10202 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
10203 reload may be unable to compute the address of a local variable,
10204 since there is no way to add a large constant to the stack pointer
10205 without using a second temporary register. */
10208 mips_compute_frame_info ();
10209 if (!SMALL_OPERAND (cfun->machine->frame.total_size))
10216 /* Make sure that we're not trying to eliminate to the wrong hard frame
10220 mips_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
10222 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM);
10225 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
10226 or argument pointer. TO is either the stack pointer or hard frame
10230 mips_initial_elimination_offset (int from, int to)
10232 HOST_WIDE_INT offset;
10234 mips_compute_frame_info ();
10236 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
10239 case FRAME_POINTER_REGNUM:
10240 if (FRAME_GROWS_DOWNWARD)
10241 offset = (cfun->machine->frame.args_size
10242 + cfun->machine->frame.cprestore_size
10243 + cfun->machine->frame.var_size);
10248 case ARG_POINTER_REGNUM:
10249 offset = cfun->machine->frame.arg_pointer_offset;
10253 gcc_unreachable ();
10256 if (to == HARD_FRAME_POINTER_REGNUM)
10257 offset -= cfun->machine->frame.hard_frame_pointer_offset;
10262 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
10265 mips_extra_live_on_entry (bitmap regs)
10267 if (TARGET_USE_GOT)
10269 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
10270 the global pointer. */
10271 if (!TARGET_ABSOLUTE_ABICALLS)
10272 bitmap_set_bit (regs, PIC_FUNCTION_ADDR_REGNUM);
10274 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
10275 the global pointer. */
10277 bitmap_set_bit (regs, MIPS16_PIC_TEMP_REGNUM);
10279 /* See the comment above load_call<mode> for details. */
10280 bitmap_set_bit (regs, GOT_VERSION_REGNUM);
10284 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
10288 mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
10293 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
10296 /* Emit code to change the current function's return address to
10297 ADDRESS. SCRATCH is available as a scratch register, if needed.
10298 ADDRESS and SCRATCH are both word-mode GPRs. */
10301 mips_set_return_address (rtx address, rtx scratch)
10305 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM));
10306 slot_address = mips_add_offset (scratch, stack_pointer_rtx,
10307 cfun->machine->frame.gp_sp_offset);
10308 mips_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address);
10311 /* Return true if the current function has a cprestore slot. */
10314 mips_cfun_has_cprestore_slot_p (void)
10316 return (cfun->machine->global_pointer != INVALID_REGNUM
10317 && cfun->machine->frame.cprestore_size > 0);
10320 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
10321 cprestore slot. LOAD_P is true if the caller wants to load from
10322 the cprestore slot; it is false if the caller wants to store to
10326 mips_get_cprestore_base_and_offset (rtx *base, HOST_WIDE_INT *offset,
10329 const struct mips_frame_info *frame;
10331 frame = &cfun->machine->frame;
10332 /* .cprestore always uses the stack pointer instead of the frame pointer.
10333 We have a free choice for direct stores for non-MIPS16 functions,
10334 and for MIPS16 functions whose cprestore slot is in range of the
10335 stack pointer. Using the stack pointer would sometimes give more
10336 (early) scheduling freedom, but using the frame pointer would
10337 sometimes give more (late) scheduling freedom. It's hard to
10338 predict which applies to a given function, so let's keep things
10341 Loads must always use the frame pointer in functions that call
10342 alloca, and there's little benefit to using the stack pointer
10344 if (frame_pointer_needed && !(TARGET_CPRESTORE_DIRECTIVE && !load_p))
10346 *base = hard_frame_pointer_rtx;
10347 *offset = frame->args_size - frame->hard_frame_pointer_offset;
10351 *base = stack_pointer_rtx;
10352 *offset = frame->args_size;
10356 /* Return true if X is the load or store address of the cprestore slot;
10357 LOAD_P says which. */
10360 mips_cprestore_address_p (rtx x, bool load_p)
10362 rtx given_base, required_base;
10363 HOST_WIDE_INT given_offset, required_offset;
10365 mips_split_plus (x, &given_base, &given_offset);
10366 mips_get_cprestore_base_and_offset (&required_base, &required_offset, load_p);
10367 return given_base == required_base && given_offset == required_offset;
10370 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
10371 going to load from it, false if we are going to store to it.
10372 Use TEMP as a temporary register if need be. */
10375 mips_cprestore_slot (rtx temp, bool load_p)
10378 HOST_WIDE_INT offset;
10380 mips_get_cprestore_base_and_offset (&base, &offset, load_p);
10381 return gen_frame_mem (Pmode, mips_add_offset (temp, base, offset));
10384 /* Emit instructions to save global pointer value GP into cprestore
10385 slot MEM. OFFSET is the offset that MEM applies to the base register.
10387 MEM may not be a legitimate address. If it isn't, TEMP is a
10388 temporary register that can be used, otherwise it is a SCRATCH. */
10391 mips_save_gp_to_cprestore_slot (rtx mem, rtx offset, rtx gp, rtx temp)
10393 if (TARGET_CPRESTORE_DIRECTIVE)
10395 gcc_assert (gp == pic_offset_table_rtx);
10396 emit_insn (PMODE_INSN (gen_cprestore, (mem, offset)));
10399 mips_emit_move (mips_cprestore_slot (temp, false), gp);
10402 /* Restore $gp from its save slot, using TEMP as a temporary base register
10403 if need be. This function is for o32 and o64 abicalls only.
10405 See mips_must_initialize_gp_p for details about how we manage the
10409 mips_restore_gp_from_cprestore_slot (rtx temp)
10411 gcc_assert (TARGET_ABICALLS && TARGET_OLDABI && epilogue_completed);
10413 if (!cfun->machine->must_restore_gp_when_clobbered_p)
10415 emit_note (NOTE_INSN_DELETED);
10421 mips_emit_move (temp, mips_cprestore_slot (temp, true));
10422 mips_emit_move (pic_offset_table_rtx, temp);
10425 mips_emit_move (pic_offset_table_rtx, mips_cprestore_slot (temp, true));
10426 if (!TARGET_EXPLICIT_RELOCS)
10427 emit_insn (gen_blockage ());
10430 /* A function to save or store a register. The first argument is the
10431 register and the second is the stack slot. */
10432 typedef void (*mips_save_restore_fn) (rtx, rtx);
10434 /* Use FN to save or restore register REGNO. MODE is the register's
10435 mode and OFFSET is the offset of its save slot from the current
10439 mips_save_restore_reg (enum machine_mode mode, int regno,
10440 HOST_WIDE_INT offset, mips_save_restore_fn fn)
10444 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx,
10446 fn (gen_rtx_REG (mode, regno), mem);
10449 /* Call FN for each accumlator that is saved by the current function.
10450 SP_OFFSET is the offset of the current stack pointer from the start
10454 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
10456 HOST_WIDE_INT offset;
10459 offset = cfun->machine->frame.acc_sp_offset - sp_offset;
10460 if (BITSET_P (cfun->machine->frame.acc_mask, 0))
10462 mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
10463 offset -= UNITS_PER_WORD;
10464 mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
10465 offset -= UNITS_PER_WORD;
10468 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
10469 if (BITSET_P (cfun->machine->frame.acc_mask,
10470 ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
10472 mips_save_restore_reg (word_mode, regno, offset, fn);
10473 offset -= UNITS_PER_WORD;
10477 /* Save register REG to MEM. Make the instruction frame-related. */
10480 mips_save_reg (rtx reg, rtx mem)
10482 if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
10486 mips_emit_move_or_split (mem, reg, SPLIT_IF_NECESSARY);
10488 x1 = mips_frame_set (mips_subword (mem, false),
10489 mips_subword (reg, false));
10490 x2 = mips_frame_set (mips_subword (mem, true),
10491 mips_subword (reg, true));
10492 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));
10495 mips_emit_save_slot_move (mem, reg, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
10498 /* Capture the register combinations that are allowed in a SWM or LWM
10499 instruction. The entries are ordered by number of registers set in
10500 the mask. We also ignore the single register encodings because a
10501 normal SW/LW is preferred. */
10503 static const unsigned int umips_swm_mask[17] = {
10504 0xc0ff0000, 0x80ff0000, 0x40ff0000, 0x807f0000,
10505 0x00ff0000, 0x803f0000, 0x007f0000, 0x801f0000,
10506 0x003f0000, 0x800f0000, 0x001f0000, 0x80070000,
10507 0x000f0000, 0x80030000, 0x00070000, 0x80010000,
10511 static const unsigned int umips_swm_encoding[17] = {
10512 25, 24, 9, 23, 8, 22, 7, 21, 6, 20, 5, 19, 4, 18, 3, 17, 2
10515 /* Try to use a microMIPS LWM or SWM instruction to save or restore
10516 as many GPRs in *MASK as possible. *OFFSET is the offset from the
10517 stack pointer of the topmost save slot.
10519 Remove from *MASK all registers that were handled using LWM and SWM.
10520 Update *OFFSET so that it points to the first unused save slot. */
10523 umips_build_save_restore (mips_save_restore_fn fn,
10524 unsigned *mask, HOST_WIDE_INT *offset)
10528 rtx pattern, set, reg, mem;
10529 HOST_WIDE_INT this_offset;
10532 /* Try matching $16 to $31 (s0 to ra). */
10533 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
10534 if ((*mask & 0xffff0000) == umips_swm_mask[i])
10537 if (i == ARRAY_SIZE (umips_swm_mask))
10540 /* Get the offset of the lowest save slot. */
10541 nregs = (umips_swm_encoding[i] & 0xf) + (umips_swm_encoding[i] >> 4);
10542 this_offset = *offset - UNITS_PER_WORD * (nregs - 1);
10544 /* LWM/SWM can only support offsets from -2048 to 2047. */
10545 if (!UMIPS_12BIT_OFFSET_P (this_offset))
10548 /* Create the final PARALLEL. */
10549 pattern = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs));
10550 this_base = stack_pointer_rtx;
10552 /* For registers $16-$23 and $30. */
10553 for (j = 0; j < (umips_swm_encoding[i] & 0xf); j++)
10555 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10556 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10557 unsigned int regno = (j != 8) ? 16 + j : 30;
10558 *mask &= ~(1 << regno);
10559 reg = gen_rtx_REG (SImode, regno);
10560 if (fn == mips_save_reg)
10561 set = mips_frame_set (mem, reg);
10564 set = gen_rtx_SET (VOIDmode, reg, mem);
10565 mips_add_cfa_restore (reg);
10567 XVECEXP (pattern, 0, j) = set;
10570 /* For register $31. */
10571 if (umips_swm_encoding[i] >> 4)
10573 HOST_WIDE_INT offset = this_offset + j * UNITS_PER_WORD;
10574 *mask &= ~(1 << 31);
10575 mem = gen_frame_mem (SImode, plus_constant (Pmode, this_base, offset));
10576 reg = gen_rtx_REG (SImode, 31);
10577 if (fn == mips_save_reg)
10578 set = mips_frame_set (mem, reg);
10581 set = gen_rtx_SET (VOIDmode, reg, mem);
10582 mips_add_cfa_restore (reg);
10584 XVECEXP (pattern, 0, j) = set;
10587 pattern = emit_insn (pattern);
10588 if (fn == mips_save_reg)
10589 RTX_FRAME_RELATED_P (pattern) = 1;
10591 /* Adjust the last offset. */
10592 *offset -= UNITS_PER_WORD * nregs;
10597 /* Call FN for each register that is saved by the current function.
10598 SP_OFFSET is the offset of the current stack pointer from the start
10602 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
10603 mips_save_restore_fn fn)
10605 enum machine_mode fpr_mode;
10607 const struct mips_frame_info *frame = &cfun->machine->frame;
10608 HOST_WIDE_INT offset;
10611 /* Save registers starting from high to low. The debuggers prefer at least
10612 the return register be stored at func+4, and also it allows us not to
10613 need a nop in the epilogue if at least one register is reloaded in
10614 addition to return address. */
10615 offset = frame->gp_sp_offset - sp_offset;
10616 mask = frame->mask;
10618 if (TARGET_MICROMIPS)
10619 umips_build_save_restore (fn, &mask, &offset);
10621 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
10622 if (BITSET_P (mask, regno - GP_REG_FIRST))
10624 /* Record the ra offset for use by mips_function_profiler. */
10625 if (regno == RETURN_ADDR_REGNUM)
10626 cfun->machine->frame.ra_fp_offset = offset + sp_offset;
10627 mips_save_restore_reg (word_mode, regno, offset, fn);
10628 offset -= UNITS_PER_WORD;
10631 /* This loop must iterate over the same space as its companion in
10632 mips_compute_frame_info. */
10633 offset = cfun->machine->frame.fp_sp_offset - sp_offset;
10634 fpr_mode = (TARGET_SINGLE_FLOAT ? SFmode : DFmode);
10635 for (regno = FP_REG_LAST - MAX_FPRS_PER_FMT + 1;
10636 regno >= FP_REG_FIRST;
10637 regno -= MAX_FPRS_PER_FMT)
10638 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST))
10640 mips_save_restore_reg (fpr_mode, regno, offset, fn);
10641 offset -= GET_MODE_SIZE (fpr_mode);
10645 /* Return true if a move between register REGNO and its save slot (MEM)
10646 can be done in a single move. LOAD_P is true if we are loading
10647 from the slot, false if we are storing to it. */
10650 mips_direct_save_slot_move_p (unsigned int regno, rtx mem, bool load_p)
10652 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
10653 if (TARGET_MIPS16 && !load_p && regno == RETURN_ADDR_REGNUM)
10656 return mips_secondary_reload_class (REGNO_REG_CLASS (regno),
10657 GET_MODE (mem), mem, load_p) == NO_REGS;
10660 /* Emit a move from SRC to DEST, given that one of them is a register
10661 save slot and that the other is a register. TEMP is a temporary
10662 GPR of the same mode that is available if need be. */
10665 mips_emit_save_slot_move (rtx dest, rtx src, rtx temp)
10667 unsigned int regno;
10672 regno = REGNO (src);
10677 regno = REGNO (dest);
10681 if (regno == cfun->machine->global_pointer && !mips_must_initialize_gp_p ())
10683 /* We don't yet know whether we'll need this instruction or not.
10684 Postpone the decision by emitting a ghost move. This move
10685 is specifically not frame-related; only the split version is. */
10687 emit_insn (gen_move_gpdi (dest, src));
10689 emit_insn (gen_move_gpsi (dest, src));
10693 if (regno == HI_REGNUM)
10697 mips_emit_move (temp, src);
10699 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
10700 temp, gen_rtx_REG (DImode, LO_REGNUM)));
10702 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
10703 temp, gen_rtx_REG (SImode, LO_REGNUM)));
10708 emit_insn (gen_mfhidi_ti (temp,
10709 gen_rtx_REG (TImode, MD_REG_FIRST)));
10711 emit_insn (gen_mfhisi_di (temp,
10712 gen_rtx_REG (DImode, MD_REG_FIRST)));
10713 mips_emit_move (dest, temp);
10716 else if (mips_direct_save_slot_move_p (regno, mem, mem == src))
10717 mips_emit_move (dest, src);
10720 gcc_assert (!reg_overlap_mentioned_p (dest, temp));
10721 mips_emit_move (temp, src);
10722 mips_emit_move (dest, temp);
10725 mips_set_frame_expr (mips_frame_set (dest, src));
10728 /* If we're generating n32 or n64 abicalls, and the current function
10729 does not use $28 as its global pointer, emit a cplocal directive.
10730 Use pic_offset_table_rtx as the argument to the directive. */
10733 mips_output_cplocal (void)
10735 if (!TARGET_EXPLICIT_RELOCS
10736 && mips_must_initialize_gp_p ()
10737 && cfun->machine->global_pointer != GLOBAL_POINTER_REGNUM)
10738 output_asm_insn (".cplocal %+", 0);
10741 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
10744 mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10746 const char *fnname;
10748 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
10749 floating-point arguments. */
10751 && TARGET_HARD_FLOAT_ABI
10752 && crtl->args.info.fp_code != 0)
10753 mips16_build_function_stub ();
10755 /* Get the function name the same way that toplev.c does before calling
10756 assemble_start_function. This is needed so that the name used here
10757 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10758 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10759 mips_start_function_definition (fnname, TARGET_MIPS16);
10761 /* Output MIPS-specific frame information. */
10762 if (!flag_inhibit_size_directive)
10764 const struct mips_frame_info *frame;
10766 frame = &cfun->machine->frame;
10768 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
10770 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC ",%s\t\t"
10771 "# vars= " HOST_WIDE_INT_PRINT_DEC
10773 ", args= " HOST_WIDE_INT_PRINT_DEC
10774 ", gp= " HOST_WIDE_INT_PRINT_DEC "\n",
10775 reg_names[frame_pointer_needed
10776 ? HARD_FRAME_POINTER_REGNUM
10777 : STACK_POINTER_REGNUM],
10778 (frame_pointer_needed
10779 ? frame->total_size - frame->hard_frame_pointer_offset
10780 : frame->total_size),
10781 reg_names[RETURN_ADDR_REGNUM],
10783 frame->num_gp, frame->num_fp,
10785 frame->cprestore_size);
10787 /* .mask MASK, OFFSET. */
10788 fprintf (file, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10789 frame->mask, frame->gp_save_offset);
10791 /* .fmask MASK, OFFSET. */
10792 fprintf (file, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC "\n",
10793 frame->fmask, frame->fp_save_offset);
10796 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
10797 Also emit the ".set noreorder; .set nomacro" sequence for functions
10799 if (mips_must_initialize_gp_p ()
10800 && mips_current_loadgp_style () == LOADGP_OLDABI)
10804 /* This is a fixed-form sequence. The position of the
10805 first two instructions is important because of the
10806 way _gp_disp is defined. */
10807 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
10808 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
10809 output_asm_insn ("sll\t$2,16", 0);
10810 output_asm_insn ("addu\t$2,$3", 0);
10814 /* .cpload must be in a .set noreorder but not a
10815 .set nomacro block. */
10816 mips_push_asm_switch (&mips_noreorder);
10817 output_asm_insn (".cpload\t%^", 0);
10818 if (!cfun->machine->all_noreorder_p)
10819 mips_pop_asm_switch (&mips_noreorder);
10821 mips_push_asm_switch (&mips_nomacro);
10824 else if (cfun->machine->all_noreorder_p)
10826 mips_push_asm_switch (&mips_noreorder);
10827 mips_push_asm_switch (&mips_nomacro);
10830 /* Tell the assembler which register we're using as the global
10831 pointer. This is needed for thunks, since they can use either
10832 explicit relocs or assembler macros. */
10833 mips_output_cplocal ();
10836 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
10839 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
10840 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
10842 const char *fnname;
10844 /* Reinstate the normal $gp. */
10845 SET_REGNO (pic_offset_table_rtx, GLOBAL_POINTER_REGNUM);
10846 mips_output_cplocal ();
10848 if (cfun->machine->all_noreorder_p)
10850 mips_pop_asm_switch (&mips_nomacro);
10851 mips_pop_asm_switch (&mips_noreorder);
10854 /* Get the function name the same way that toplev.c does before calling
10855 assemble_start_function. This is needed so that the name used here
10856 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
10857 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
10858 mips_end_function_definition (fnname);
10861 /* Emit an optimisation barrier for accesses to the current frame. */
10864 mips_frame_barrier (void)
10866 emit_clobber (gen_frame_mem (BLKmode, stack_pointer_rtx));
10870 /* The __gnu_local_gp symbol. */
10872 static GTY(()) rtx mips_gnu_local_gp;
10874 /* If we're generating n32 or n64 abicalls, emit instructions
10875 to set up the global pointer. */
10878 mips_emit_loadgp (void)
10880 rtx addr, offset, incoming_address, base, index, pic_reg;
10882 pic_reg = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
10883 switch (mips_current_loadgp_style ())
10885 case LOADGP_ABSOLUTE:
10886 if (mips_gnu_local_gp == NULL)
10888 mips_gnu_local_gp = gen_rtx_SYMBOL_REF (Pmode, "__gnu_local_gp");
10889 SYMBOL_REF_FLAGS (mips_gnu_local_gp) |= SYMBOL_FLAG_LOCAL;
10891 emit_insn (PMODE_INSN (gen_loadgp_absolute,
10892 (pic_reg, mips_gnu_local_gp)));
10895 case LOADGP_OLDABI:
10896 /* Added by mips_output_function_prologue. */
10899 case LOADGP_NEWABI:
10900 addr = XEXP (DECL_RTL (current_function_decl), 0);
10901 offset = mips_unspec_address (addr, SYMBOL_GOTOFF_LOADGP);
10902 incoming_address = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
10903 emit_insn (PMODE_INSN (gen_loadgp_newabi,
10904 (pic_reg, offset, incoming_address)));
10908 base = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_BASE));
10909 index = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (VXWORKS_GOTT_INDEX));
10910 emit_insn (PMODE_INSN (gen_loadgp_rtp, (pic_reg, base, index)));
10918 emit_insn (PMODE_INSN (gen_copygp_mips16,
10919 (pic_offset_table_rtx, pic_reg)));
10921 /* Emit a blockage if there are implicit uses of the GP register.
10922 This includes profiled functions, because FUNCTION_PROFILE uses
10924 if (!TARGET_EXPLICIT_RELOCS || crtl->profile)
10925 emit_insn (gen_loadgp_blockage ());
10928 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10930 #if PROBE_INTERVAL > 32768
10931 #error Cannot use indexed addressing mode for stack probing
10934 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
10935 inclusive. These are offsets from the current stack pointer. */
10938 mips_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size)
10941 sorry ("-fstack-check=specific not implemented for MIPS16");
10943 /* See if we have a constant small number of probes to generate. If so,
10944 that's the easy case. */
10945 if (first + size <= 32768)
10949 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
10950 it exceeds SIZE. If only one probe is needed, this will not
10951 generate any code. Then probe at FIRST + SIZE. */
10952 for (i = PROBE_INTERVAL; i < size; i += PROBE_INTERVAL)
10953 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10956 emit_stack_probe (plus_constant (Pmode, stack_pointer_rtx,
10960 /* Otherwise, do the same as above, but in a loop. Note that we must be
10961 extra careful with variables wrapping around because we might be at
10962 the very top (or the very bottom) of the address space and we have
10963 to be able to handle this case properly; in particular, we use an
10964 equality test for the loop condition. */
10967 HOST_WIDE_INT rounded_size;
10968 rtx r3 = MIPS_PROLOGUE_TEMP (Pmode);
10969 rtx r12 = MIPS_PROLOGUE_TEMP2 (Pmode);
10971 /* Sanity check for the addressing mode we're going to use. */
10972 gcc_assert (first <= 32768);
10975 /* Step 1: round SIZE to the previous multiple of the interval. */
10977 rounded_size = size & -PROBE_INTERVAL;
10980 /* Step 2: compute initial and final value of the loop counter. */
10982 /* TEST_ADDR = SP + FIRST. */
10983 emit_insn (gen_rtx_SET (VOIDmode, r3,
10984 plus_constant (Pmode, stack_pointer_rtx,
10987 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
10988 if (rounded_size > 32768)
10990 emit_move_insn (r12, GEN_INT (rounded_size));
10991 emit_insn (gen_rtx_SET (VOIDmode, r12,
10992 gen_rtx_MINUS (Pmode, r3, r12)));
10995 emit_insn (gen_rtx_SET (VOIDmode, r12,
10996 plus_constant (Pmode, r3, -rounded_size)));
10999 /* Step 3: the loop
11001 while (TEST_ADDR != LAST_ADDR)
11003 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11007 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11008 until it is equal to ROUNDED_SIZE. */
11010 emit_insn (PMODE_INSN (gen_probe_stack_range, (r3, r3, r12)));
11013 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11014 that SIZE is equal to ROUNDED_SIZE. */
11016 if (size != rounded_size)
11017 emit_stack_probe (plus_constant (Pmode, r12, rounded_size - size));
11020 /* Make sure nothing is scheduled before we are done. */
11021 emit_insn (gen_blockage ());
11024 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
11025 absolute addresses. */
11028 mips_output_probe_stack_range (rtx reg1, rtx reg2)
11030 static int labelno = 0;
11031 char loop_lab[32], end_lab[32], tmp[64];
11034 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno);
11035 ASM_GENERATE_INTERNAL_LABEL (end_lab, "LPSRE", labelno++);
11037 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab);
11039 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11042 strcpy (tmp, "%(%<beq\t%0,%1,");
11043 output_asm_insn (strcat (tmp, &end_lab[1]), xops);
11045 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11046 xops[1] = GEN_INT (-PROBE_INTERVAL);
11047 if (TARGET_64BIT && TARGET_LONG64)
11048 output_asm_insn ("daddiu\t%0,%0,%1", xops);
11050 output_asm_insn ("addiu\t%0,%0,%1", xops);
11052 /* Probe at TEST_ADDR and branch. */
11053 fprintf (asm_out_file, "\tb\t");
11054 assemble_name_raw (asm_out_file, loop_lab);
11055 fputc ('\n', asm_out_file);
11057 output_asm_insn ("sd\t$0,0(%0)%)", xops);
11059 output_asm_insn ("sw\t$0,0(%0)%)", xops);
11061 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, end_lab);
11066 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
11069 mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
11071 return REG_P (*x) && KERNEL_REG_P (REGNO (*x));
11074 /* Expand the "prologue" pattern. */
11077 mips_expand_prologue (void)
11079 const struct mips_frame_info *frame;
11080 HOST_WIDE_INT size;
11081 unsigned int nargs;
11084 if (cfun->machine->global_pointer != INVALID_REGNUM)
11086 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
11087 or implicitly. If so, we can commit to using a global pointer
11088 straight away, otherwise we need to defer the decision. */
11089 if (mips_cfun_has_inflexible_gp_ref_p ()
11090 || mips_cfun_has_flexible_gp_ref_p ())
11092 cfun->machine->must_initialize_gp_p = true;
11093 cfun->machine->must_restore_gp_when_clobbered_p = true;
11096 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
11099 frame = &cfun->machine->frame;
11100 size = frame->total_size;
11102 if (flag_stack_usage_info)
11103 current_function_static_stack_size = size;
11105 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK)
11107 if (crtl->is_leaf && !cfun->calls_alloca)
11109 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT)
11110 mips_emit_probe_stack_range (STACK_CHECK_PROTECT,
11111 size - STACK_CHECK_PROTECT);
11114 mips_emit_probe_stack_range (STACK_CHECK_PROTECT, size);
11117 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
11118 bytes beforehand; this is enough to cover the register save area
11119 without going out of range. */
11120 if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
11121 || frame->num_cop0_regs > 0)
11123 HOST_WIDE_INT step1;
11125 step1 = MIN (size, MIPS_MAX_FIRST_STACK_STEP);
11126 if (GENERATE_MIPS16E_SAVE_RESTORE)
11128 HOST_WIDE_INT offset;
11129 unsigned int mask, regno;
11131 /* Try to merge argument stores into the save instruction. */
11132 nargs = mips16e_collect_argument_saves ();
11134 /* Build the save instruction. */
11135 mask = frame->mask;
11136 insn = mips16e_build_save_restore (false, &mask, &offset,
11138 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11139 mips_frame_barrier ();
11142 /* Check if we need to save other registers. */
11143 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11144 if (BITSET_P (mask, regno - GP_REG_FIRST))
11146 offset -= UNITS_PER_WORD;
11147 mips_save_restore_reg (word_mode, regno,
11148 offset, mips_save_reg);
11153 if (cfun->machine->interrupt_handler_p)
11155 HOST_WIDE_INT offset;
11158 /* If this interrupt is using a shadow register set, we need to
11159 get the stack pointer from the previous register set. */
11160 if (cfun->machine->use_shadow_register_set_p)
11161 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
11162 stack_pointer_rtx));
11164 if (!cfun->machine->keep_interrupts_masked_p)
11166 /* Move from COP0 Cause to K0. */
11167 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
11168 gen_rtx_REG (SImode,
11169 COP0_CAUSE_REG_NUM)));
11170 /* Move from COP0 EPC to K1. */
11171 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11172 gen_rtx_REG (SImode,
11173 COP0_EPC_REG_NUM)));
11176 /* Allocate the first part of the frame. */
11177 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
11179 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11180 mips_frame_barrier ();
11183 /* Start at the uppermost location for saving. */
11184 offset = frame->cop0_sp_offset - size;
11185 if (!cfun->machine->keep_interrupts_masked_p)
11187 /* Push EPC into its stack slot. */
11188 mem = gen_frame_mem (word_mode,
11189 plus_constant (Pmode, stack_pointer_rtx,
11191 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11192 offset -= UNITS_PER_WORD;
11195 /* Move from COP0 Status to K1. */
11196 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
11197 gen_rtx_REG (SImode,
11198 COP0_STATUS_REG_NUM)));
11200 /* Right justify the RIPL in k0. */
11201 if (!cfun->machine->keep_interrupts_masked_p)
11202 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
11203 gen_rtx_REG (SImode, K0_REG_NUM),
11204 GEN_INT (CAUSE_IPL)));
11206 /* Push Status into its stack slot. */
11207 mem = gen_frame_mem (word_mode,
11208 plus_constant (Pmode, stack_pointer_rtx,
11210 mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
11211 offset -= UNITS_PER_WORD;
11213 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
11214 if (!cfun->machine->keep_interrupts_masked_p)
11215 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11218 gen_rtx_REG (SImode, K0_REG_NUM)));
11220 if (!cfun->machine->keep_interrupts_masked_p)
11221 /* Enable interrupts by clearing the KSU ERL and EXL bits.
11222 IE is already the correct value, so we don't have to do
11223 anything explicit. */
11224 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11227 gen_rtx_REG (SImode, GP_REG_FIRST)));
11229 /* Disable interrupts by clearing the KSU, ERL, EXL,
11231 emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
11234 gen_rtx_REG (SImode, GP_REG_FIRST)));
11238 insn = gen_add3_insn (stack_pointer_rtx,
11241 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11242 mips_frame_barrier ();
11245 mips_for_each_saved_acc (size, mips_save_reg);
11246 mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
11250 /* Allocate the rest of the frame. */
11253 if (SMALL_OPERAND (-size))
11254 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx,
11256 GEN_INT (-size)))) = 1;
11259 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (size));
11262 /* There are no instructions to add or subtract registers
11263 from the stack pointer, so use the frame pointer as a
11264 temporary. We should always be using a frame pointer
11265 in this case anyway. */
11266 gcc_assert (frame_pointer_needed);
11267 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11268 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
11269 hard_frame_pointer_rtx,
11270 MIPS_PROLOGUE_TEMP (Pmode)));
11271 mips_emit_move (stack_pointer_rtx, hard_frame_pointer_rtx);
11274 emit_insn (gen_sub3_insn (stack_pointer_rtx,
11276 MIPS_PROLOGUE_TEMP (Pmode)));
11278 /* Describe the combined effect of the previous instructions. */
11279 mips_set_frame_expr
11280 (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
11281 plus_constant (Pmode, stack_pointer_rtx, -size)));
11283 mips_frame_barrier ();
11286 /* Set up the frame pointer, if we're using one. */
11287 if (frame_pointer_needed)
11289 HOST_WIDE_INT offset;
11291 offset = frame->hard_frame_pointer_offset;
11294 insn = mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11295 RTX_FRAME_RELATED_P (insn) = 1;
11297 else if (SMALL_OPERAND (offset))
11299 insn = gen_add3_insn (hard_frame_pointer_rtx,
11300 stack_pointer_rtx, GEN_INT (offset));
11301 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
11305 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode), GEN_INT (offset));
11306 mips_emit_move (hard_frame_pointer_rtx, stack_pointer_rtx);
11307 emit_insn (gen_add3_insn (hard_frame_pointer_rtx,
11308 hard_frame_pointer_rtx,
11309 MIPS_PROLOGUE_TEMP (Pmode)));
11310 mips_set_frame_expr
11311 (gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx,
11312 plus_constant (Pmode, stack_pointer_rtx, offset)));
11316 mips_emit_loadgp ();
11318 /* Initialize the $gp save slot. */
11319 if (mips_cfun_has_cprestore_slot_p ())
11321 rtx base, mem, gp, temp;
11322 HOST_WIDE_INT offset;
11324 mips_get_cprestore_base_and_offset (&base, &offset, false);
11325 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11326 gp = TARGET_MIPS16 ? MIPS16_PIC_TEMP : pic_offset_table_rtx;
11327 temp = (SMALL_OPERAND (offset)
11328 ? gen_rtx_SCRATCH (Pmode)
11329 : MIPS_PROLOGUE_TEMP (Pmode));
11330 emit_insn (PMODE_INSN (gen_potential_cprestore,
11331 (mem, GEN_INT (offset), gp, temp)));
11333 mips_get_cprestore_base_and_offset (&base, &offset, true);
11334 mem = gen_frame_mem (Pmode, plus_constant (Pmode, base, offset));
11335 emit_insn (PMODE_INSN (gen_use_cprestore, (mem)));
11338 /* We need to search back to the last use of K0 or K1. */
11339 if (cfun->machine->interrupt_handler_p)
11341 for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
11343 && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
11345 /* Emit a move from K1 to COP0 Status after insn. */
11346 gcc_assert (insn != NULL_RTX);
11347 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11348 gen_rtx_REG (SImode, K1_REG_NUM)),
11352 /* If we are profiling, make sure no instructions are scheduled before
11353 the call to mcount. */
11355 emit_insn (gen_blockage ());
11358 /* Attach all pending register saves to the previous instruction.
11359 Return that instruction. */
11362 mips_epilogue_emit_cfa_restores (void)
11366 insn = get_last_insn ();
11367 gcc_assert (insn && !REG_NOTES (insn));
11368 if (mips_epilogue.cfa_restores)
11370 RTX_FRAME_RELATED_P (insn) = 1;
11371 REG_NOTES (insn) = mips_epilogue.cfa_restores;
11372 mips_epilogue.cfa_restores = 0;
11377 /* Like mips_epilogue_emit_cfa_restores, but also record that the CFA is
11378 now at REG + OFFSET. */
11381 mips_epilogue_set_cfa (rtx reg, HOST_WIDE_INT offset)
11385 insn = mips_epilogue_emit_cfa_restores ();
11386 if (reg != mips_epilogue.cfa_reg || offset != mips_epilogue.cfa_offset)
11388 RTX_FRAME_RELATED_P (insn) = 1;
11389 REG_NOTES (insn) = alloc_reg_note (REG_CFA_DEF_CFA,
11390 plus_constant (Pmode, reg, offset),
11392 mips_epilogue.cfa_reg = reg;
11393 mips_epilogue.cfa_offset = offset;
11397 /* Emit instructions to restore register REG from slot MEM. Also update
11398 the cfa_restores list. */
11401 mips_restore_reg (rtx reg, rtx mem)
11403 /* There's no MIPS16 instruction to load $31 directly. Load into
11404 $7 instead and adjust the return insn appropriately. */
11405 if (TARGET_MIPS16 && REGNO (reg) == RETURN_ADDR_REGNUM)
11406 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
11407 else if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
11409 mips_add_cfa_restore (mips_subword (reg, true));
11410 mips_add_cfa_restore (mips_subword (reg, false));
11413 mips_add_cfa_restore (reg);
11415 mips_emit_save_slot_move (reg, mem, MIPS_EPILOGUE_TEMP (GET_MODE (reg)));
11416 if (REGNO (reg) == REGNO (mips_epilogue.cfa_reg))
11417 /* The CFA is currently defined in terms of the register whose
11418 value we have just restored. Redefine the CFA in terms of
11419 the stack pointer. */
11420 mips_epilogue_set_cfa (stack_pointer_rtx,
11421 mips_epilogue.cfa_restore_sp_offset);
11424 /* Emit code to set the stack pointer to BASE + OFFSET, given that
11425 BASE + OFFSET is NEW_FRAME_SIZE bytes below the top of the frame.
11426 BASE, if not the stack pointer, is available as a temporary. */
11429 mips_deallocate_stack (rtx base, rtx offset, HOST_WIDE_INT new_frame_size)
11431 if (base == stack_pointer_rtx && offset == const0_rtx)
11434 mips_frame_barrier ();
11435 if (offset == const0_rtx)
11437 emit_move_insn (stack_pointer_rtx, base);
11438 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11440 else if (TARGET_MIPS16 && base != stack_pointer_rtx)
11442 emit_insn (gen_add3_insn (base, base, offset));
11443 mips_epilogue_set_cfa (base, new_frame_size);
11444 emit_move_insn (stack_pointer_rtx, base);
11448 emit_insn (gen_add3_insn (stack_pointer_rtx, base, offset));
11449 mips_epilogue_set_cfa (stack_pointer_rtx, new_frame_size);
11453 /* Emit any instructions needed before a return. */
11456 mips_expand_before_return (void)
11458 /* When using a call-clobbered gp, we start out with unified call
11459 insns that include instructions to restore the gp. We then split
11460 these unified calls after reload. These split calls explicitly
11461 clobber gp, so there is no need to define
11462 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
11464 For consistency, we should also insert an explicit clobber of $28
11465 before return insns, so that the post-reload optimizers know that
11466 the register is not live on exit. */
11467 if (TARGET_CALL_CLOBBERED_GP)
11468 emit_clobber (pic_offset_table_rtx);
11471 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
11475 mips_expand_epilogue (bool sibcall_p)
11477 const struct mips_frame_info *frame;
11478 HOST_WIDE_INT step1, step2;
11479 rtx base, adjust, insn;
11480 bool use_jraddiusp_p = false;
11482 if (!sibcall_p && mips_can_use_return_insn ())
11484 emit_jump_insn (gen_return ());
11488 /* In MIPS16 mode, if the return value should go into a floating-point
11489 register, we need to call a helper routine to copy it over. */
11490 if (mips16_cfun_returns_in_fpr_p ())
11491 mips16_copy_fpr_return_value ();
11493 /* Split the frame into two. STEP1 is the amount of stack we should
11494 deallocate before restoring the registers. STEP2 is the amount we
11495 should deallocate afterwards.
11497 Start off by assuming that no registers need to be restored. */
11498 frame = &cfun->machine->frame;
11499 step1 = frame->total_size;
11502 /* Work out which register holds the frame address. */
11503 if (!frame_pointer_needed)
11504 base = stack_pointer_rtx;
11507 base = hard_frame_pointer_rtx;
11508 step1 -= frame->hard_frame_pointer_offset;
11510 mips_epilogue.cfa_reg = base;
11511 mips_epilogue.cfa_offset = step1;
11512 mips_epilogue.cfa_restores = NULL_RTX;
11514 /* If we need to restore registers, deallocate as much stack as
11515 possible in the second step without going out of range. */
11516 if ((frame->mask | frame->fmask | frame->acc_mask) != 0
11517 || frame->num_cop0_regs > 0)
11519 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
11523 /* Get an rtx for STEP1 that we can add to BASE. */
11524 adjust = GEN_INT (step1);
11525 if (!SMALL_OPERAND (step1))
11527 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), adjust);
11528 adjust = MIPS_EPILOGUE_TEMP (Pmode);
11530 mips_deallocate_stack (base, adjust, step2);
11532 /* If we're using addressing macros, $gp is implicitly used by all
11533 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
11535 if (TARGET_CALL_SAVED_GP && !TARGET_EXPLICIT_RELOCS)
11536 emit_insn (gen_blockage ());
11538 mips_epilogue.cfa_restore_sp_offset = step2;
11539 if (GENERATE_MIPS16E_SAVE_RESTORE && frame->mask != 0)
11541 unsigned int regno, mask;
11542 HOST_WIDE_INT offset;
11545 /* Generate the restore instruction. */
11546 mask = frame->mask;
11547 restore = mips16e_build_save_restore (true, &mask, &offset, 0, step2);
11549 /* Restore any other registers manually. */
11550 for (regno = GP_REG_FIRST; regno < GP_REG_LAST; regno++)
11551 if (BITSET_P (mask, regno - GP_REG_FIRST))
11553 offset -= UNITS_PER_WORD;
11554 mips_save_restore_reg (word_mode, regno, offset, mips_restore_reg);
11557 /* Restore the remaining registers and deallocate the final bit
11559 mips_frame_barrier ();
11560 emit_insn (restore);
11561 mips_epilogue_set_cfa (stack_pointer_rtx, 0);
11565 /* Restore the registers. */
11566 mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
11567 mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
11570 if (cfun->machine->interrupt_handler_p)
11572 HOST_WIDE_INT offset;
11575 offset = frame->cop0_sp_offset - (frame->total_size - step2);
11576 if (!cfun->machine->keep_interrupts_masked_p)
11578 /* Restore the original EPC. */
11579 mem = gen_frame_mem (word_mode,
11580 plus_constant (Pmode, stack_pointer_rtx,
11582 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11583 offset -= UNITS_PER_WORD;
11585 /* Move to COP0 EPC. */
11586 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
11587 gen_rtx_REG (SImode, K0_REG_NUM)));
11590 /* Restore the original Status. */
11591 mem = gen_frame_mem (word_mode,
11592 plus_constant (Pmode, stack_pointer_rtx,
11594 mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
11595 offset -= UNITS_PER_WORD;
11597 /* If we don't use shadow register set, we need to update SP. */
11598 if (!cfun->machine->use_shadow_register_set_p)
11599 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11601 /* The choice of position is somewhat arbitrary in this case. */
11602 mips_epilogue_emit_cfa_restores ();
11604 /* Move to COP0 Status. */
11605 emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
11606 gen_rtx_REG (SImode, K0_REG_NUM)));
11608 else if (TARGET_MICROMIPS
11609 && !crtl->calls_eh_return
11612 && mips_unsigned_immediate_p (step2, 5, 2))
11613 use_jraddiusp_p = true;
11615 /* Deallocate the final bit of the frame. */
11616 mips_deallocate_stack (stack_pointer_rtx, GEN_INT (step2), 0);
11619 if (!use_jraddiusp_p)
11620 gcc_assert (!mips_epilogue.cfa_restores);
11622 /* Add in the __builtin_eh_return stack adjustment. We need to
11623 use a temporary in MIPS16 code. */
11624 if (crtl->calls_eh_return)
11628 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode), stack_pointer_rtx);
11629 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode),
11630 MIPS_EPILOGUE_TEMP (Pmode),
11631 EH_RETURN_STACKADJ_RTX));
11632 mips_emit_move (stack_pointer_rtx, MIPS_EPILOGUE_TEMP (Pmode));
11635 emit_insn (gen_add3_insn (stack_pointer_rtx,
11637 EH_RETURN_STACKADJ_RTX));
11642 mips_expand_before_return ();
11643 if (cfun->machine->interrupt_handler_p)
11645 /* Interrupt handlers generate eret or deret. */
11646 if (cfun->machine->use_debug_exception_return_p)
11647 emit_jump_insn (gen_mips_deret ());
11649 emit_jump_insn (gen_mips_eret ());
11655 /* When generating MIPS16 code, the normal
11656 mips_for_each_saved_gpr_and_fpr path will restore the return
11657 address into $7 rather than $31. */
11659 && !GENERATE_MIPS16E_SAVE_RESTORE
11660 && BITSET_P (frame->mask, RETURN_ADDR_REGNUM))
11662 /* simple_returns cannot rely on values that are only available
11663 on paths through the epilogue (because return paths that do
11664 not pass through the epilogue may nevertheless reuse a
11665 simple_return that occurs at the end of the epilogue).
11666 Use a normal return here instead. */
11667 rtx reg = gen_rtx_REG (Pmode, GP_REG_FIRST + 7);
11668 pat = gen_return_internal (reg);
11670 else if (use_jraddiusp_p)
11671 pat = gen_jraddiusp (GEN_INT (step2));
11674 rtx reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
11675 pat = gen_simple_return_internal (reg);
11677 emit_jump_insn (pat);
11678 if (use_jraddiusp_p)
11679 mips_epilogue_set_cfa (stack_pointer_rtx, step2);
11683 /* Search from the beginning to the first use of K0 or K1. */
11684 if (cfun->machine->interrupt_handler_p
11685 && !cfun->machine->keep_interrupts_masked_p)
11687 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
11689 && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
11691 gcc_assert (insn != NULL_RTX);
11692 /* Insert disable interrupts before the first use of K0 or K1. */
11693 emit_insn_before (gen_mips_di (), insn);
11694 emit_insn_before (gen_mips_ehb (), insn);
11698 /* Return nonzero if this function is known to have a null epilogue.
11699 This allows the optimizer to omit jumps to jumps if no stack
11703 mips_can_use_return_insn (void)
11705 /* Interrupt handlers need to go through the epilogue. */
11706 if (cfun->machine->interrupt_handler_p)
11709 if (!reload_completed)
11715 /* In MIPS16 mode, a function that returns a floating-point value
11716 needs to arrange to copy the return value into the floating-point
11718 if (mips16_cfun_returns_in_fpr_p ())
11721 return cfun->machine->frame.total_size == 0;
11724 /* Return true if register REGNO can store a value of mode MODE.
11725 The result of this function is cached in mips_hard_regno_mode_ok. */
11728 mips_hard_regno_mode_ok_p (unsigned int regno, enum machine_mode mode)
11731 enum mode_class mclass;
11733 if (mode == CCV2mode)
11734 return (ISA_HAS_8CC
11735 && ST_REG_P (regno)
11736 && (regno - ST_REG_FIRST) % 2 == 0);
11738 if (mode == CCV4mode)
11739 return (ISA_HAS_8CC
11740 && ST_REG_P (regno)
11741 && (regno - ST_REG_FIRST) % 4 == 0);
11743 if (mode == CCmode)
11744 return ISA_HAS_8CC ? ST_REG_P (regno) : regno == FPSW_REGNUM;
11746 size = GET_MODE_SIZE (mode);
11747 mclass = GET_MODE_CLASS (mode);
11749 if (GP_REG_P (regno))
11750 return ((regno - GP_REG_FIRST) & 1) == 0 || size <= UNITS_PER_WORD;
11752 if (FP_REG_P (regno)
11753 && (((regno - FP_REG_FIRST) % MAX_FPRS_PER_FMT) == 0
11754 || (MIN_FPRS_PER_FMT == 1 && size <= UNITS_PER_FPREG)))
11756 /* Allow 64-bit vector modes for Loongson-2E/2F. */
11757 if (TARGET_LOONGSON_VECTORS
11758 && (mode == V2SImode
11759 || mode == V4HImode
11760 || mode == V8QImode
11761 || mode == DImode))
11764 if (mclass == MODE_FLOAT
11765 || mclass == MODE_COMPLEX_FLOAT
11766 || mclass == MODE_VECTOR_FLOAT)
11767 return size <= UNITS_PER_FPVALUE;
11769 /* Allow integer modes that fit into a single register. We need
11770 to put integers into FPRs when using instructions like CVT
11771 and TRUNC. There's no point allowing sizes smaller than a word,
11772 because the FPU has no appropriate load/store instructions. */
11773 if (mclass == MODE_INT)
11774 return size >= MIN_UNITS_PER_WORD && size <= UNITS_PER_FPREG;
11777 if (ACC_REG_P (regno)
11778 && (INTEGRAL_MODE_P (mode) || ALL_FIXED_POINT_MODE_P (mode)))
11780 if (MD_REG_P (regno))
11782 /* After a multiplication or division, clobbering HI makes
11783 the value of LO unpredictable, and vice versa. This means
11784 that, for all interesting cases, HI and LO are effectively
11787 We model this by requiring that any value that uses HI
11789 if (size <= UNITS_PER_WORD * 2)
11790 return regno == (size <= UNITS_PER_WORD ? LO_REGNUM : MD_REG_FIRST);
11794 /* DSP accumulators do not have the same restrictions as
11795 HI and LO, so we can treat them as normal doubleword
11797 if (size <= UNITS_PER_WORD)
11800 if (size <= UNITS_PER_WORD * 2
11801 && ((regno - DSP_ACC_REG_FIRST) & 1) == 0)
11806 if (ALL_COP_REG_P (regno))
11807 return mclass == MODE_INT && size <= UNITS_PER_WORD;
11809 if (regno == GOT_VERSION_REGNUM)
11810 return mode == SImode;
11815 /* Implement HARD_REGNO_NREGS. */
11818 mips_hard_regno_nregs (int regno, enum machine_mode mode)
11820 if (ST_REG_P (regno))
11821 /* The size of FP status registers is always 4, because they only hold
11822 CCmode values, and CCmode is always considered to be 4 bytes wide. */
11823 return (GET_MODE_SIZE (mode) + 3) / 4;
11825 if (FP_REG_P (regno))
11826 return (GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG;
11828 /* All other registers are word-sized. */
11829 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
11832 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
11833 in mips_hard_regno_nregs. */
11836 mips_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
11842 COPY_HARD_REG_SET (left, reg_class_contents[(int) rclass]);
11843 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) ST_REGS]))
11845 if (HARD_REGNO_MODE_OK (ST_REG_FIRST, mode))
11846 size = MIN (size, 4);
11847 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) ST_REGS]);
11849 if (hard_reg_set_intersect_p (left, reg_class_contents[(int) FP_REGS]))
11851 if (HARD_REGNO_MODE_OK (FP_REG_FIRST, mode))
11852 size = MIN (size, UNITS_PER_FPREG);
11853 AND_COMPL_HARD_REG_SET (left, reg_class_contents[(int) FP_REGS]);
11855 if (!hard_reg_set_empty_p (left))
11856 size = MIN (size, UNITS_PER_WORD);
11857 return (GET_MODE_SIZE (mode) + size - 1) / size;
11860 /* Implement CANNOT_CHANGE_MODE_CLASS. */
11863 mips_cannot_change_mode_class (enum machine_mode from,
11864 enum machine_mode to,
11865 enum reg_class rclass)
11867 /* Allow conversions between different Loongson integer vectors,
11868 and between those vectors and DImode. */
11869 if (GET_MODE_SIZE (from) == 8 && GET_MODE_SIZE (to) == 8
11870 && INTEGRAL_MODE_P (from) && INTEGRAL_MODE_P (to))
11873 /* Otherwise, there are several problems with changing the modes of
11874 values in floating-point registers:
11876 - When a multi-word value is stored in paired floating-point
11877 registers, the first register always holds the low word. We
11878 therefore can't allow FPRs to change between single-word and
11879 multi-word modes on big-endian targets.
11881 - GCC assumes that each word of a multiword register can be
11882 accessed individually using SUBREGs. This is not true for
11883 floating-point registers if they are bigger than a word.
11885 - Loading a 32-bit value into a 64-bit floating-point register
11886 will not sign-extend the value, despite what LOAD_EXTEND_OP
11887 says. We can't allow FPRs to change from SImode to a wider
11888 mode on 64-bit targets.
11890 - If the FPU has already interpreted a value in one format, we
11891 must not ask it to treat the value as having a different
11894 We therefore disallow all mode changes involving FPRs. */
11896 return reg_classes_intersect_p (FP_REGS, rclass);
11899 /* Implement target hook small_register_classes_for_mode_p. */
11902 mips_small_register_classes_for_mode_p (enum machine_mode mode
11905 return TARGET_MIPS16;
11908 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
11911 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode)
11916 return TARGET_HARD_FLOAT;
11919 return TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT;
11922 return TARGET_HARD_FLOAT && TARGET_PAIRED_SINGLE_FLOAT;
11929 /* Implement MODES_TIEABLE_P. */
11932 mips_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
11934 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
11935 prefer to put one of them in FPRs. */
11936 return (mode1 == mode2
11937 || (!mips_mode_ok_for_mov_fmt_p (mode1)
11938 && !mips_mode_ok_for_mov_fmt_p (mode2)));
11941 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11944 mips_preferred_reload_class (rtx x, reg_class_t rclass)
11946 if (mips_dangerous_for_la25_p (x) && reg_class_subset_p (LEA_REGS, rclass))
11949 if (reg_class_subset_p (FP_REGS, rclass)
11950 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x)))
11953 if (reg_class_subset_p (GR_REGS, rclass))
11956 if (TARGET_MIPS16 && reg_class_subset_p (M16_REGS, rclass))
11962 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
11963 Return a "canonical" class to represent it in later calculations. */
11966 mips_canonicalize_move_class (reg_class_t rclass)
11968 /* All moves involving accumulator registers have the same cost. */
11969 if (reg_class_subset_p (rclass, ACC_REGS))
11972 /* Likewise promote subclasses of general registers to the most
11973 interesting containing class. */
11974 if (TARGET_MIPS16 && reg_class_subset_p (rclass, M16_REGS))
11976 else if (reg_class_subset_p (rclass, GENERAL_REGS))
11977 rclass = GENERAL_REGS;
11982 /* Return the cost of moving a value from a register of class FROM to a GPR.
11983 Return 0 for classes that are unions of other classes handled by this
11987 mips_move_to_gpr_cost (reg_class_t from)
11993 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
11997 /* MFLO and MFHI. */
12007 /* This choice of value is historical. */
12015 /* Return the cost of moving a value from a GPR to a register of class TO.
12016 Return 0 for classes that are unions of other classes handled by this
12020 mips_move_from_gpr_cost (reg_class_t to)
12026 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
12030 /* MTLO and MTHI. */
12040 /* This choice of value is historical. */
12048 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
12049 maximum of the move costs for subclasses; regclass will work out
12050 the maximum for us. */
12053 mips_register_move_cost (enum machine_mode mode,
12054 reg_class_t from, reg_class_t to)
12059 from = mips_canonicalize_move_class (from);
12060 to = mips_canonicalize_move_class (to);
12062 /* Handle moves that can be done without using general-purpose registers. */
12063 if (from == FP_REGS)
12065 if (to == FP_REGS && mips_mode_ok_for_mov_fmt_p (mode))
12070 /* Handle cases in which only one class deviates from the ideal. */
12071 dregs = TARGET_MIPS16 ? M16_REGS : GENERAL_REGS;
12073 return mips_move_from_gpr_cost (to);
12075 return mips_move_to_gpr_cost (from);
12077 /* Handles cases that require a GPR temporary. */
12078 cost1 = mips_move_to_gpr_cost (from);
12081 cost2 = mips_move_from_gpr_cost (to);
12083 return cost1 + cost2;
12089 /* Implement TARGET_REGISTER_PRIORITY. */
12092 mips_register_priority (int hard_regno)
12094 /* Treat MIPS16 registers with higher priority than other regs. */
12096 && TEST_HARD_REG_BIT (reg_class_contents[M16_REGS], hard_regno))
12101 /* Implement TARGET_MEMORY_MOVE_COST. */
12104 mips_memory_move_cost (enum machine_mode mode, reg_class_t rclass, bool in)
12106 return (mips_cost->memory_latency
12107 + memory_move_secondary_cost (mode, rclass, in));
12110 /* Return the register class required for a secondary register when
12111 copying between one of the registers in RCLASS and value X, which
12112 has mode MODE. X is the source of the move if IN_P, otherwise it
12113 is the destination. Return NO_REGS if no secondary register is
12117 mips_secondary_reload_class (enum reg_class rclass,
12118 enum machine_mode mode, rtx x, bool)
12122 /* If X is a constant that cannot be loaded into $25, it must be loaded
12123 into some other GPR. No other register class allows a direct move. */
12124 if (mips_dangerous_for_la25_p (x))
12125 return reg_class_subset_p (rclass, LEA_REGS) ? NO_REGS : LEA_REGS;
12127 regno = true_regnum (x);
12130 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
12131 if (!reg_class_subset_p (rclass, M16_REGS) && !M16_REG_P (regno))
12137 /* Copying from accumulator registers to anywhere other than a general
12138 register requires a temporary general register. */
12139 if (reg_class_subset_p (rclass, ACC_REGS))
12140 return GP_REG_P (regno) ? NO_REGS : GR_REGS;
12141 if (ACC_REG_P (regno))
12142 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12144 if (reg_class_subset_p (rclass, FP_REGS))
12147 && (GET_MODE_SIZE (mode) == 4 || GET_MODE_SIZE (mode) == 8))
12148 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
12149 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
12152 if (GP_REG_P (regno) || x == CONST0_RTX (mode))
12153 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
12156 if (CONSTANT_P (x) && !targetm.cannot_force_const_mem (mode, x))
12157 /* We can force the constant to memory and use lwc1
12158 and ldc1. As above, we will use pairs of lwc1s if
12159 ldc1 is not supported. */
12162 if (FP_REG_P (regno) && mips_mode_ok_for_mov_fmt_p (mode))
12163 /* In this case we can use mov.fmt. */
12166 /* Otherwise, we need to reload through an integer register. */
12169 if (FP_REG_P (regno))
12170 return reg_class_subset_p (rclass, GR_REGS) ? NO_REGS : GR_REGS;
12175 /* Implement TARGET_MODE_REP_EXTENDED. */
12178 mips_mode_rep_extended (enum machine_mode mode, enum machine_mode mode_rep)
12180 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
12181 if (TARGET_64BIT && mode == SImode && mode_rep == DImode)
12182 return SIGN_EXTEND;
12187 /* Implement TARGET_VALID_POINTER_MODE. */
12190 mips_valid_pointer_mode (enum machine_mode mode)
12192 return mode == SImode || (TARGET_64BIT && mode == DImode);
12195 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
12198 mips_vector_mode_supported_p (enum machine_mode mode)
12203 return TARGET_PAIRED_SINGLE_FLOAT;
12218 return TARGET_LOONGSON_VECTORS;
12225 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
12228 mips_scalar_mode_supported_p (enum machine_mode mode)
12230 if (ALL_FIXED_POINT_MODE_P (mode)
12231 && GET_MODE_PRECISION (mode) <= 2 * BITS_PER_WORD)
12234 return default_scalar_mode_supported_p (mode);
12237 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
12239 static enum machine_mode
12240 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED)
12242 if (TARGET_PAIRED_SINGLE_FLOAT
12248 /* Implement TARGET_INIT_LIBFUNCS. */
12251 mips_init_libfuncs (void)
12253 if (TARGET_FIX_VR4120)
12255 /* Register the special divsi3 and modsi3 functions needed to work
12256 around VR4120 division errata. */
12257 set_optab_libfunc (sdiv_optab, SImode, "__vr4120_divsi3");
12258 set_optab_libfunc (smod_optab, SImode, "__vr4120_modsi3");
12261 if (TARGET_MIPS16 && TARGET_HARD_FLOAT_ABI)
12263 /* Register the MIPS16 -mhard-float stubs. */
12264 set_optab_libfunc (add_optab, SFmode, "__mips16_addsf3");
12265 set_optab_libfunc (sub_optab, SFmode, "__mips16_subsf3");
12266 set_optab_libfunc (smul_optab, SFmode, "__mips16_mulsf3");
12267 set_optab_libfunc (sdiv_optab, SFmode, "__mips16_divsf3");
12269 set_optab_libfunc (eq_optab, SFmode, "__mips16_eqsf2");
12270 set_optab_libfunc (ne_optab, SFmode, "__mips16_nesf2");
12271 set_optab_libfunc (gt_optab, SFmode, "__mips16_gtsf2");
12272 set_optab_libfunc (ge_optab, SFmode, "__mips16_gesf2");
12273 set_optab_libfunc (lt_optab, SFmode, "__mips16_ltsf2");
12274 set_optab_libfunc (le_optab, SFmode, "__mips16_lesf2");
12275 set_optab_libfunc (unord_optab, SFmode, "__mips16_unordsf2");
12277 set_conv_libfunc (sfix_optab, SImode, SFmode, "__mips16_fix_truncsfsi");
12278 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__mips16_floatsisf");
12279 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__mips16_floatunsisf");
12281 if (TARGET_DOUBLE_FLOAT)
12283 set_optab_libfunc (add_optab, DFmode, "__mips16_adddf3");
12284 set_optab_libfunc (sub_optab, DFmode, "__mips16_subdf3");
12285 set_optab_libfunc (smul_optab, DFmode, "__mips16_muldf3");
12286 set_optab_libfunc (sdiv_optab, DFmode, "__mips16_divdf3");
12288 set_optab_libfunc (eq_optab, DFmode, "__mips16_eqdf2");
12289 set_optab_libfunc (ne_optab, DFmode, "__mips16_nedf2");
12290 set_optab_libfunc (gt_optab, DFmode, "__mips16_gtdf2");
12291 set_optab_libfunc (ge_optab, DFmode, "__mips16_gedf2");
12292 set_optab_libfunc (lt_optab, DFmode, "__mips16_ltdf2");
12293 set_optab_libfunc (le_optab, DFmode, "__mips16_ledf2");
12294 set_optab_libfunc (unord_optab, DFmode, "__mips16_unorddf2");
12296 set_conv_libfunc (sext_optab, DFmode, SFmode,
12297 "__mips16_extendsfdf2");
12298 set_conv_libfunc (trunc_optab, SFmode, DFmode,
12299 "__mips16_truncdfsf2");
12300 set_conv_libfunc (sfix_optab, SImode, DFmode,
12301 "__mips16_fix_truncdfsi");
12302 set_conv_libfunc (sfloat_optab, DFmode, SImode,
12303 "__mips16_floatsidf");
12304 set_conv_libfunc (ufloat_optab, DFmode, SImode,
12305 "__mips16_floatunsidf");
12309 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
12310 on an external non-MIPS16 routine to implement __sync_synchronize.
12311 Similarly for the rest of the ll/sc libfuncs. */
12314 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
12315 init_sync_libfuncs (UNITS_PER_WORD);
12319 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
12322 mips_process_load_label (rtx target)
12324 rtx base, gp, intop;
12325 HOST_WIDE_INT offset;
12327 mips_multi_start ();
12331 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target, 0);
12332 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target, 0);
12336 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target, 0);
12337 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target, 0);
12341 gp = pic_offset_table_rtx;
12342 if (mips_cfun_has_cprestore_slot_p ())
12344 gp = gen_rtx_REG (Pmode, AT_REGNUM);
12345 mips_get_cprestore_base_and_offset (&base, &offset, true);
12346 if (!SMALL_OPERAND (offset))
12348 intop = GEN_INT (CONST_HIGH_PART (offset));
12349 mips_multi_add_insn ("lui\t%0,%1", gp, intop, 0);
12350 mips_multi_add_insn ("addu\t%0,%0,%1", gp, base, 0);
12353 offset = CONST_LOW_PART (offset);
12355 intop = GEN_INT (offset);
12356 if (ISA_HAS_LOAD_DELAY)
12357 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp, intop, base, 0);
12359 mips_multi_add_insn ("lw\t%0,%1(%2)", gp, intop, base, 0);
12361 if (ISA_HAS_LOAD_DELAY)
12362 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target, gp, 0);
12364 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target, gp, 0);
12365 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target, 0);
12370 /* Return the number of instructions needed to load a label into $AT. */
12372 static unsigned int
12373 mips_load_label_num_insns (void)
12375 if (cfun->machine->load_label_num_insns == 0)
12377 mips_process_load_label (pc_rtx);
12378 cfun->machine->load_label_num_insns = mips_multi_num_insns;
12380 return cfun->machine->load_label_num_insns;
12383 /* Emit an asm sequence to start a noat block and load the address
12384 of a label into $1. */
12387 mips_output_load_label (rtx target)
12389 mips_push_asm_switch (&mips_noat);
12390 if (TARGET_EXPLICIT_RELOCS)
12392 mips_process_load_label (target);
12393 mips_multi_write ();
12397 if (Pmode == DImode)
12398 output_asm_insn ("dla\t%@,%0", &target);
12400 output_asm_insn ("la\t%@,%0", &target);
12404 /* Return the length of INSN. LENGTH is the initial length computed by
12405 attributes in the machine-description file. */
12408 mips_adjust_insn_length (rtx insn, int length)
12410 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
12411 of a PIC long-branch sequence. Substitute the correct value. */
12412 if (length == MAX_PIC_BRANCH_LENGTH
12414 && INSN_CODE (insn) >= 0
12415 && get_attr_type (insn) == TYPE_BRANCH)
12417 /* Add the branch-over instruction and its delay slot, if this
12418 is a conditional branch. */
12419 length = simplejump_p (insn) ? 0 : 8;
12421 /* Add the size of a load into $AT. */
12422 length += BASE_INSN_LENGTH * mips_load_label_num_insns ();
12424 /* Add the length of an indirect jump, ignoring the delay slot. */
12425 length += TARGET_COMPRESSION ? 2 : 4;
12428 /* A unconditional jump has an unfilled delay slot if it is not part
12429 of a sequence. A conditional jump normally has a delay slot, but
12430 does not on MIPS16. */
12431 if (CALL_P (insn) || (TARGET_MIPS16 ? simplejump_p (insn) : JUMP_P (insn)))
12432 length += TARGET_MIPS16 ? 2 : 4;
12434 /* See how many nops might be needed to avoid hardware hazards. */
12435 if (!cfun->machine->ignore_hazard_length_p
12437 && INSN_CODE (insn) >= 0)
12438 switch (get_attr_hazard (insn))
12444 length += NOP_INSN_LENGTH;
12448 length += NOP_INSN_LENGTH * 2;
12455 /* Return the assembly code for INSN, which has the operands given by
12456 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
12457 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
12458 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
12459 version of BRANCH_IF_TRUE. */
12462 mips_output_conditional_branch (rtx insn, rtx *operands,
12463 const char *branch_if_true,
12464 const char *branch_if_false)
12466 unsigned int length;
12467 rtx taken, not_taken;
12469 gcc_assert (LABEL_P (operands[0]));
12471 length = get_attr_length (insn);
12474 /* Just a simple conditional branch. */
12475 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
12476 return branch_if_true;
12479 /* Generate a reversed branch around a direct jump. This fallback does
12480 not use branch-likely instructions. */
12481 mips_branch_likely = false;
12482 not_taken = gen_label_rtx ();
12483 taken = operands[0];
12485 /* Generate the reversed branch to NOT_TAKEN. */
12486 operands[0] = not_taken;
12487 output_asm_insn (branch_if_false, operands);
12489 /* If INSN has a delay slot, we must provide delay slots for both the
12490 branch to NOT_TAKEN and the conditional jump. We must also ensure
12491 that INSN's delay slot is executed in the appropriate cases. */
12492 if (final_sequence)
12494 /* This first delay slot will always be executed, so use INSN's
12495 delay slot if is not annulled. */
12496 if (!INSN_ANNULLED_BRANCH_P (insn))
12498 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12499 asm_out_file, optimize, 1, NULL);
12500 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12503 output_asm_insn ("nop", 0);
12504 fprintf (asm_out_file, "\n");
12507 /* Output the unconditional branch to TAKEN. */
12508 if (TARGET_ABSOLUTE_JUMPS)
12509 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken);
12512 mips_output_load_label (taken);
12513 output_asm_insn ("jr\t%@%]%/", 0);
12516 /* Now deal with its delay slot; see above. */
12517 if (final_sequence)
12519 /* This delay slot will only be executed if the branch is taken.
12520 Use INSN's delay slot if is annulled. */
12521 if (INSN_ANNULLED_BRANCH_P (insn))
12523 final_scan_insn (XVECEXP (final_sequence, 0, 1),
12524 asm_out_file, optimize, 1, NULL);
12525 INSN_DELETED_P (XVECEXP (final_sequence, 0, 1)) = 1;
12528 output_asm_insn ("nop", 0);
12529 fprintf (asm_out_file, "\n");
12532 /* Output NOT_TAKEN. */
12533 targetm.asm_out.internal_label (asm_out_file, "L",
12534 CODE_LABEL_NUMBER (not_taken));
12538 /* Return the assembly code for INSN, which branches to OPERANDS[0]
12539 if some ordering condition is true. The condition is given by
12540 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
12541 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
12542 its second is always zero. */
12545 mips_output_order_conditional_branch (rtx insn, rtx *operands, bool inverted_p)
12547 const char *branch[2];
12549 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
12550 Make BRANCH[0] branch on the inverse condition. */
12551 switch (GET_CODE (operands[1]))
12553 /* These cases are equivalent to comparisons against zero. */
12555 inverted_p = !inverted_p;
12556 /* Fall through. */
12558 branch[!inverted_p] = MIPS_BRANCH ("bne", "%2,%.,%0");
12559 branch[inverted_p] = MIPS_BRANCH ("beq", "%2,%.,%0");
12562 /* These cases are always true or always false. */
12564 inverted_p = !inverted_p;
12565 /* Fall through. */
12567 branch[!inverted_p] = MIPS_BRANCH ("beq", "%.,%.,%0");
12568 branch[inverted_p] = MIPS_BRANCH ("bne", "%.,%.,%0");
12572 branch[!inverted_p] = MIPS_BRANCH ("b%C1z", "%2,%0");
12573 branch[inverted_p] = MIPS_BRANCH ("b%N1z", "%2,%0");
12576 return mips_output_conditional_branch (insn, operands, branch[1], branch[0]);
12579 /* Start a block of code that needs access to the LL, SC and SYNC
12583 mips_start_ll_sc_sync_block (void)
12585 if (!ISA_HAS_LL_SC)
12587 output_asm_insn (".set\tpush", 0);
12589 output_asm_insn (".set\tmips3", 0);
12591 output_asm_insn (".set\tmips2", 0);
12595 /* End a block started by mips_start_ll_sc_sync_block. */
12598 mips_end_ll_sc_sync_block (void)
12600 if (!ISA_HAS_LL_SC)
12601 output_asm_insn (".set\tpop", 0);
12604 /* Output and/or return the asm template for a sync instruction. */
12607 mips_output_sync (void)
12609 mips_start_ll_sc_sync_block ();
12610 output_asm_insn ("sync", 0);
12611 mips_end_ll_sc_sync_block ();
12615 /* Return the asm template associated with sync_insn1 value TYPE.
12616 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
12618 static const char *
12619 mips_sync_insn1_template (enum attr_sync_insn1 type, bool is_64bit_p)
12623 case SYNC_INSN1_MOVE:
12624 return "move\t%0,%z2";
12625 case SYNC_INSN1_LI:
12626 return "li\t%0,%2";
12627 case SYNC_INSN1_ADDU:
12628 return is_64bit_p ? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
12629 case SYNC_INSN1_ADDIU:
12630 return is_64bit_p ? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
12631 case SYNC_INSN1_SUBU:
12632 return is_64bit_p ? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
12633 case SYNC_INSN1_AND:
12634 return "and\t%0,%1,%z2";
12635 case SYNC_INSN1_ANDI:
12636 return "andi\t%0,%1,%2";
12637 case SYNC_INSN1_OR:
12638 return "or\t%0,%1,%z2";
12639 case SYNC_INSN1_ORI:
12640 return "ori\t%0,%1,%2";
12641 case SYNC_INSN1_XOR:
12642 return "xor\t%0,%1,%z2";
12643 case SYNC_INSN1_XORI:
12644 return "xori\t%0,%1,%2";
12646 gcc_unreachable ();
12649 /* Return the asm template associated with sync_insn2 value TYPE. */
12651 static const char *
12652 mips_sync_insn2_template (enum attr_sync_insn2 type)
12656 case SYNC_INSN2_NOP:
12657 gcc_unreachable ();
12658 case SYNC_INSN2_AND:
12659 return "and\t%0,%1,%z2";
12660 case SYNC_INSN2_XOR:
12661 return "xor\t%0,%1,%z2";
12662 case SYNC_INSN2_NOT:
12663 return "nor\t%0,%1,%.";
12665 gcc_unreachable ();
12668 /* OPERANDS are the operands to a sync loop instruction and INDEX is
12669 the value of the one of the sync_* attributes. Return the operand
12670 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
12671 have the associated attribute. */
12674 mips_get_sync_operand (rtx *operands, int index, rtx default_value)
12677 default_value = operands[index - 1];
12678 return default_value;
12681 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
12682 sequence for it. */
12685 mips_process_sync_loop (rtx insn, rtx *operands)
12687 rtx at, mem, oldval, newval, inclusive_mask, exclusive_mask;
12688 rtx required_oldval, insn1_op2, tmp1, tmp2, tmp3, cmp;
12689 unsigned int tmp3_insn;
12690 enum attr_sync_insn1 insn1;
12691 enum attr_sync_insn2 insn2;
12694 enum memmodel model;
12696 /* Read an operand from the sync_WHAT attribute and store it in
12697 variable WHAT. DEFAULT is the default value if no attribute
12699 #define READ_OPERAND(WHAT, DEFAULT) \
12700 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
12703 /* Read the memory. */
12704 READ_OPERAND (mem, 0);
12706 is_64bit_p = (GET_MODE_BITSIZE (GET_MODE (mem)) == 64);
12708 /* Read the other attributes. */
12709 at = gen_rtx_REG (GET_MODE (mem), AT_REGNUM);
12710 READ_OPERAND (oldval, at);
12711 READ_OPERAND (cmp, 0);
12712 READ_OPERAND (newval, at);
12713 READ_OPERAND (inclusive_mask, 0);
12714 READ_OPERAND (exclusive_mask, 0);
12715 READ_OPERAND (required_oldval, 0);
12716 READ_OPERAND (insn1_op2, 0);
12717 insn1 = get_attr_sync_insn1 (insn);
12718 insn2 = get_attr_sync_insn2 (insn);
12720 /* Don't bother setting CMP result that is never used. */
12721 if (cmp && find_reg_note (insn, REG_UNUSED, cmp))
12724 memmodel_attr = get_attr_sync_memmodel (insn);
12725 switch (memmodel_attr)
12728 model = MEMMODEL_ACQ_REL;
12731 model = MEMMODEL_ACQUIRE;
12734 model = (enum memmodel) INTVAL (operands[memmodel_attr]);
12737 mips_multi_start ();
12739 /* Output the release side of the memory barrier. */
12740 if (need_atomic_barrier_p (model, true))
12742 if (required_oldval == 0 && TARGET_OCTEON)
12744 /* Octeon doesn't reorder reads, so a full barrier can be
12745 created by using SYNCW to order writes combined with the
12746 write from the following SC. When the SC successfully
12747 completes, we know that all preceding writes are also
12748 committed to the coherent memory system. It is possible
12749 for a single SYNCW to fail, but a pair of them will never
12750 fail, so we use two. */
12751 mips_multi_add_insn ("syncw", NULL);
12752 mips_multi_add_insn ("syncw", NULL);
12755 mips_multi_add_insn ("sync", NULL);
12758 /* Output the branch-back label. */
12759 mips_multi_add_label ("1:");
12761 /* OLDVAL = *MEM. */
12762 mips_multi_add_insn (is_64bit_p ? "lld\t%0,%1" : "ll\t%0,%1",
12763 oldval, mem, NULL);
12765 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
12766 if (required_oldval)
12768 if (inclusive_mask == 0)
12772 gcc_assert (oldval != at);
12773 mips_multi_add_insn ("and\t%0,%1,%2",
12774 at, oldval, inclusive_mask, NULL);
12777 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1, required_oldval, NULL);
12779 /* CMP = 0 [delay slot]. */
12781 mips_multi_add_insn ("li\t%0,0", cmp, NULL);
12784 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
12785 if (exclusive_mask == 0)
12789 gcc_assert (oldval != at);
12790 mips_multi_add_insn ("and\t%0,%1,%z2",
12791 at, oldval, exclusive_mask, NULL);
12795 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
12797 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
12798 at least one instruction in that case. */
12799 if (insn1 == SYNC_INSN1_MOVE
12800 && (tmp1 != const0_rtx || insn2 != SYNC_INSN2_NOP))
12804 mips_multi_add_insn (mips_sync_insn1_template (insn1, is_64bit_p),
12805 newval, oldval, insn1_op2, NULL);
12809 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
12810 if (insn2 == SYNC_INSN2_NOP)
12814 mips_multi_add_insn (mips_sync_insn2_template (insn2),
12815 newval, tmp2, inclusive_mask, NULL);
12818 tmp3_insn = mips_multi_last_index ();
12820 /* $AT = $TMP1 | $TMP3. */
12821 if (tmp1 == const0_rtx || tmp3 == const0_rtx)
12823 mips_multi_set_operand (tmp3_insn, 0, at);
12828 gcc_assert (tmp1 != tmp3);
12829 mips_multi_add_insn ("or\t%0,%1,%2", at, tmp1, tmp3, NULL);
12832 /* if (!commit (*MEM = $AT)) goto 1.
12834 This will sometimes be a delayed branch; see the write code below
12836 mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL);
12837 mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL);
12839 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
12840 if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval)
12842 mips_multi_copy_insn (tmp3_insn);
12843 mips_multi_set_operand (mips_multi_last_index (), 0, newval);
12845 else if (!(required_oldval && cmp))
12846 mips_multi_add_insn ("nop", NULL);
12848 /* CMP = 1 -- either standalone or in a delay slot. */
12849 if (required_oldval && cmp)
12850 mips_multi_add_insn ("li\t%0,1", cmp, NULL);
12852 /* Output the acquire side of the memory barrier. */
12853 if (TARGET_SYNC_AFTER_SC && need_atomic_barrier_p (model, false))
12854 mips_multi_add_insn ("sync", NULL);
12856 /* Output the exit label, if needed. */
12857 if (required_oldval)
12858 mips_multi_add_label ("2:");
12860 #undef READ_OPERAND
12863 /* Output and/or return the asm template for sync loop INSN, which has
12864 the operands given by OPERANDS. */
12867 mips_output_sync_loop (rtx insn, rtx *operands)
12869 mips_process_sync_loop (insn, operands);
12871 /* Use branch-likely instructions to work around the LL/SC R10000
12873 mips_branch_likely = TARGET_FIX_R10000;
12875 mips_push_asm_switch (&mips_noreorder);
12876 mips_push_asm_switch (&mips_nomacro);
12877 mips_push_asm_switch (&mips_noat);
12878 mips_start_ll_sc_sync_block ();
12880 mips_multi_write ();
12882 mips_end_ll_sc_sync_block ();
12883 mips_pop_asm_switch (&mips_noat);
12884 mips_pop_asm_switch (&mips_nomacro);
12885 mips_pop_asm_switch (&mips_noreorder);
12890 /* Return the number of individual instructions in sync loop INSN,
12891 which has the operands given by OPERANDS. */
12894 mips_sync_loop_insns (rtx insn, rtx *operands)
12896 mips_process_sync_loop (insn, operands);
12897 return mips_multi_num_insns;
12900 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
12901 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
12903 When working around R4000 and R4400 errata, we need to make sure that
12904 the division is not immediately followed by a shift[1][2]. We also
12905 need to stop the division from being put into a branch delay slot[3].
12906 The easiest way to avoid both problems is to add a nop after the
12907 division. When a divide-by-zero check is needed, this nop can be
12908 used to fill the branch delay slot.
12910 [1] If a double-word or a variable shift executes immediately
12911 after starting an integer division, the shift may give an
12912 incorrect result. See quotations of errata #16 and #28 from
12913 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12914 in mips.md for details.
12916 [2] A similar bug to [1] exists for all revisions of the
12917 R4000 and the R4400 when run in an MC configuration.
12918 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
12920 "19. In this following sequence:
12922 ddiv (or ddivu or div or divu)
12923 dsll32 (or dsrl32, dsra32)
12925 if an MPT stall occurs, while the divide is slipping the cpu
12926 pipeline, then the following double shift would end up with an
12929 Workaround: The compiler needs to avoid generating any
12930 sequence with divide followed by extended double shift."
12932 This erratum is also present in "MIPS R4400MC Errata, Processor
12933 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
12934 & 3.0" as errata #10 and #4, respectively.
12936 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
12937 (also valid for MIPS R4000MC processors):
12939 "52. R4000SC: This bug does not apply for the R4000PC.
12941 There are two flavors of this bug:
12943 1) If the instruction just after divide takes an RF exception
12944 (tlb-refill, tlb-invalid) and gets an instruction cache
12945 miss (both primary and secondary) and the line which is
12946 currently in secondary cache at this index had the first
12947 data word, where the bits 5..2 are set, then R4000 would
12948 get a wrong result for the div.
12953 ------------------- # end-of page. -tlb-refill
12958 ------------------- # end-of page. -tlb-invalid
12961 2) If the divide is in the taken branch delay slot, where the
12962 target takes RF exception and gets an I-cache miss for the
12963 exception vector or where I-cache miss occurs for the
12964 target address, under the above mentioned scenarios, the
12965 div would get wrong results.
12968 j r2 # to next page mapped or unmapped
12969 div r8,r9 # this bug would be there as long
12970 # as there is an ICache miss and
12971 nop # the "data pattern" is present
12974 beq r0, r0, NextPage # to Next page
12978 This bug is present for div, divu, ddiv, and ddivu
12981 Workaround: For item 1), OS could make sure that the next page
12982 after the divide instruction is also mapped. For item 2), the
12983 compiler could make sure that the divide instruction is not in
12984 the branch delay slot."
12986 These processors have PRId values of 0x00004220 and 0x00004300 for
12987 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
12990 mips_output_division (const char *division, rtx *operands)
12995 if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
12997 output_asm_insn (s, operands);
13000 if (TARGET_CHECK_ZERO_DIV)
13004 output_asm_insn (s, operands);
13005 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
13007 else if (GENERATE_DIVIDE_TRAPS)
13009 /* Avoid long replay penalty on load miss by putting the trap before
13012 output_asm_insn ("teq\t%2,%.,7", operands);
13015 output_asm_insn (s, operands);
13016 s = "teq\t%2,%.,7";
13021 output_asm_insn ("%(bne\t%2,%.,1f", operands);
13022 output_asm_insn (s, operands);
13023 s = "break\t7%)\n1:";
13029 /* Return true if destination of IN_INSN is used as add source in
13030 OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
13031 madd.s dst, x, y, z
13032 madd.s a, dst, b, c */
13035 mips_fmadd_bypass (rtx out_insn, rtx in_insn)
13037 int dst_reg, src_reg;
13039 gcc_assert (get_attr_type (in_insn) == TYPE_FMADD);
13040 gcc_assert (get_attr_type (out_insn) == TYPE_FMADD);
13042 extract_insn (in_insn);
13043 dst_reg = REG_P (recog_data.operand[0]);
13045 extract_insn (out_insn);
13046 src_reg = REG_P (recog_data.operand[1]);
13048 if (dst_reg == src_reg)
13054 /* Return true if IN_INSN is a multiply-add or multiply-subtract
13055 instruction and if OUT_INSN assigns to the accumulator operand. */
13058 mips_linked_madd_p (rtx out_insn, rtx in_insn)
13060 enum attr_accum_in accum_in;
13061 int accum_in_opnum;
13064 if (recog_memoized (in_insn) < 0)
13067 accum_in = get_attr_accum_in (in_insn);
13068 if (accum_in == ACCUM_IN_NONE)
13071 accum_in_opnum = accum_in - ACCUM_IN_0;
13073 extract_insn (in_insn);
13074 gcc_assert (accum_in_opnum < recog_data.n_operands);
13075 accum_in_op = recog_data.operand[accum_in_opnum];
13077 return reg_set_p (accum_in_op, out_insn);
13080 /* True if the dependency between OUT_INSN and IN_INSN is on the store
13081 data rather than the address. We need this because the cprestore
13082 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
13083 which causes the default routine to abort. We just return false
13087 mips_store_data_bypass_p (rtx out_insn, rtx in_insn)
13089 if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
13092 return !store_data_bypass_p (out_insn, in_insn);
13096 /* Variables and flags used in scheduler hooks when tuning for
13100 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
13103 /* If true, then next ALU1/2 instruction will go to ALU1. */
13106 /* If true, then next FALU1/2 unstruction will go to FALU1. */
13109 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
13110 int alu1_core_unit_code;
13111 int alu2_core_unit_code;
13112 int falu1_core_unit_code;
13113 int falu2_core_unit_code;
13115 /* True if current cycle has a multi instruction.
13116 This flag is used in mips_ls2_dfa_post_advance_cycle. */
13117 bool cycle_has_multi_p;
13119 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
13120 These are used in mips_ls2_dfa_post_advance_cycle to initialize
13122 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
13123 instruction to go ALU1. */
13124 rtx alu1_turn_enabled_insn;
13125 rtx alu2_turn_enabled_insn;
13126 rtx falu1_turn_enabled_insn;
13127 rtx falu2_turn_enabled_insn;
13130 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
13131 dependencies have no cost, except on the 20Kc where output-dependence
13132 is treated like input-dependence. */
13135 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
13136 rtx dep ATTRIBUTE_UNUSED, int cost)
13138 if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT
13141 if (REG_NOTE_KIND (link) != 0)
13146 /* Return the number of instructions that can be issued per cycle. */
13149 mips_issue_rate (void)
13153 case PROCESSOR_74KC:
13154 case PROCESSOR_74KF2_1:
13155 case PROCESSOR_74KF1_1:
13156 case PROCESSOR_74KF3_2:
13157 /* The 74k is not strictly quad-issue cpu, but can be seen as one
13158 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
13159 but in reality only a maximum of 3 insns can be issued as
13160 floating-point loads and stores also require a slot in the
13162 case PROCESSOR_R10000:
13163 /* All R10K Processors are quad-issue (being the first MIPS
13164 processors to support this feature). */
13167 case PROCESSOR_20KC:
13168 case PROCESSOR_R4130:
13169 case PROCESSOR_R5400:
13170 case PROCESSOR_R5500:
13171 case PROCESSOR_R5900:
13172 case PROCESSOR_R7000:
13173 case PROCESSOR_R9000:
13174 case PROCESSOR_OCTEON:
13175 case PROCESSOR_OCTEON2:
13178 case PROCESSOR_SB1:
13179 case PROCESSOR_SB1A:
13180 /* This is actually 4, but we get better performance if we claim 3.
13181 This is partly because of unwanted speculative code motion with the
13182 larger number, and partly because in most common cases we can't
13183 reach the theoretical max of 4. */
13186 case PROCESSOR_LOONGSON_2E:
13187 case PROCESSOR_LOONGSON_2F:
13188 case PROCESSOR_LOONGSON_3A:
13189 case PROCESSOR_P5600:
13192 case PROCESSOR_XLP:
13193 return (reload_completed ? 4 : 3);
13200 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
13203 mips_ls2_init_dfa_post_cycle_insn (void)
13206 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
13207 mips_ls2.alu1_turn_enabled_insn = get_insns ();
13211 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
13212 mips_ls2.alu2_turn_enabled_insn = get_insns ();
13216 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
13217 mips_ls2.falu1_turn_enabled_insn = get_insns ();
13221 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
13222 mips_ls2.falu2_turn_enabled_insn = get_insns ();
13225 mips_ls2.alu1_core_unit_code = get_cpu_unit_code ("ls2_alu1_core");
13226 mips_ls2.alu2_core_unit_code = get_cpu_unit_code ("ls2_alu2_core");
13227 mips_ls2.falu1_core_unit_code = get_cpu_unit_code ("ls2_falu1_core");
13228 mips_ls2.falu2_core_unit_code = get_cpu_unit_code ("ls2_falu2_core");
13231 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
13232 Init data used in mips_dfa_post_advance_cycle. */
13235 mips_init_dfa_post_cycle_insn (void)
13237 if (TUNE_LOONGSON_2EF)
13238 mips_ls2_init_dfa_post_cycle_insn ();
13241 /* Initialize STATE when scheduling for Loongson 2E/2F.
13242 Support round-robin dispatch scheme by enabling only one of
13243 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
13247 mips_ls2_dfa_post_advance_cycle (state_t state)
13249 if (cpu_unit_reservation_p (state, mips_ls2.alu1_core_unit_code))
13251 /* Though there are no non-pipelined ALU1 insns,
13252 we can get an instruction of type 'multi' before reload. */
13253 gcc_assert (mips_ls2.cycle_has_multi_p);
13254 mips_ls2.alu1_turn_p = false;
13257 mips_ls2.cycle_has_multi_p = false;
13259 if (cpu_unit_reservation_p (state, mips_ls2.alu2_core_unit_code))
13260 /* We have a non-pipelined alu instruction in the core,
13261 adjust round-robin counter. */
13262 mips_ls2.alu1_turn_p = true;
13264 if (mips_ls2.alu1_turn_p)
13266 if (state_transition (state, mips_ls2.alu1_turn_enabled_insn) >= 0)
13267 gcc_unreachable ();
13271 if (state_transition (state, mips_ls2.alu2_turn_enabled_insn) >= 0)
13272 gcc_unreachable ();
13275 if (cpu_unit_reservation_p (state, mips_ls2.falu1_core_unit_code))
13277 /* There are no non-pipelined FALU1 insns. */
13278 gcc_unreachable ();
13279 mips_ls2.falu1_turn_p = false;
13282 if (cpu_unit_reservation_p (state, mips_ls2.falu2_core_unit_code))
13283 /* We have a non-pipelined falu instruction in the core,
13284 adjust round-robin counter. */
13285 mips_ls2.falu1_turn_p = true;
13287 if (mips_ls2.falu1_turn_p)
13289 if (state_transition (state, mips_ls2.falu1_turn_enabled_insn) >= 0)
13290 gcc_unreachable ();
13294 if (state_transition (state, mips_ls2.falu2_turn_enabled_insn) >= 0)
13295 gcc_unreachable ();
13299 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
13300 This hook is being called at the start of each cycle. */
13303 mips_dfa_post_advance_cycle (void)
13305 if (TUNE_LOONGSON_2EF)
13306 mips_ls2_dfa_post_advance_cycle (curr_state);
13309 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
13310 be as wide as the scheduling freedom in the DFA. */
13313 mips_multipass_dfa_lookahead (void)
13315 /* Can schedule up to 4 of the 6 function units in any one cycle. */
13319 if (TUNE_LOONGSON_2EF || TUNE_LOONGSON_3A)
13331 /* Remove the instruction at index LOWER from ready queue READY and
13332 reinsert it in front of the instruction at index HIGHER. LOWER must
13336 mips_promote_ready (rtx *ready, int lower, int higher)
13341 new_head = ready[lower];
13342 for (i = lower; i < higher; i++)
13343 ready[i] = ready[i + 1];
13344 ready[i] = new_head;
13347 /* If the priority of the instruction at POS2 in the ready queue READY
13348 is within LIMIT units of that of the instruction at POS1, swap the
13349 instructions if POS2 is not already less than POS1. */
13352 mips_maybe_swap_ready (rtx *ready, int pos1, int pos2, int limit)
13355 && INSN_PRIORITY (ready[pos1]) + limit >= INSN_PRIORITY (ready[pos2]))
13359 temp = ready[pos1];
13360 ready[pos1] = ready[pos2];
13361 ready[pos2] = temp;
13365 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
13366 that may clobber hi or lo. */
13367 static rtx mips_macc_chains_last_hilo;
13369 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
13370 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
13373 mips_macc_chains_record (rtx insn)
13375 if (get_attr_may_clobber_hilo (insn))
13376 mips_macc_chains_last_hilo = insn;
13379 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
13380 has NREADY elements, looking for a multiply-add or multiply-subtract
13381 instruction that is cumulative with mips_macc_chains_last_hilo.
13382 If there is one, promote it ahead of anything else that might
13383 clobber hi or lo. */
13386 mips_macc_chains_reorder (rtx *ready, int nready)
13390 if (mips_macc_chains_last_hilo != 0)
13391 for (i = nready - 1; i >= 0; i--)
13392 if (mips_linked_madd_p (mips_macc_chains_last_hilo, ready[i]))
13394 for (j = nready - 1; j > i; j--)
13395 if (recog_memoized (ready[j]) >= 0
13396 && get_attr_may_clobber_hilo (ready[j]))
13398 mips_promote_ready (ready, i, j);
13405 /* The last instruction to be scheduled. */
13406 static rtx vr4130_last_insn;
13408 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
13409 points to an rtx that is initially an instruction. Nullify the rtx
13410 if the instruction uses the value of register X. */
13413 vr4130_true_reg_dependence_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
13418 insn_ptr = (rtx *) data;
13421 && reg_referenced_p (x, PATTERN (*insn_ptr)))
13425 /* Return true if there is true register dependence between vr4130_last_insn
13429 vr4130_true_reg_dependence_p (rtx insn)
13431 note_stores (PATTERN (vr4130_last_insn),
13432 vr4130_true_reg_dependence_p_1, &insn);
13436 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
13437 the ready queue and that INSN2 is the instruction after it, return
13438 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
13439 in which INSN1 and INSN2 can probably issue in parallel, but for
13440 which (INSN2, INSN1) should be less sensitive to instruction
13441 alignment than (INSN1, INSN2). See 4130.md for more details. */
13444 vr4130_swap_insns_p (rtx insn1, rtx insn2)
13446 sd_iterator_def sd_it;
13449 /* Check for the following case:
13451 1) there is some other instruction X with an anti dependence on INSN1;
13452 2) X has a higher priority than INSN2; and
13453 3) X is an arithmetic instruction (and thus has no unit restrictions).
13455 If INSN1 is the last instruction blocking X, it would better to
13456 choose (INSN1, X) over (INSN2, INSN1). */
13457 FOR_EACH_DEP (insn1, SD_LIST_FORW, sd_it, dep)
13458 if (DEP_TYPE (dep) == REG_DEP_ANTI
13459 && INSN_PRIORITY (DEP_CON (dep)) > INSN_PRIORITY (insn2)
13460 && recog_memoized (DEP_CON (dep)) >= 0
13461 && get_attr_vr4130_class (DEP_CON (dep)) == VR4130_CLASS_ALU)
13464 if (vr4130_last_insn != 0
13465 && recog_memoized (insn1) >= 0
13466 && recog_memoized (insn2) >= 0)
13468 /* See whether INSN1 and INSN2 use different execution units,
13469 or if they are both ALU-type instructions. If so, they can
13470 probably execute in parallel. */
13471 enum attr_vr4130_class class1 = get_attr_vr4130_class (insn1);
13472 enum attr_vr4130_class class2 = get_attr_vr4130_class (insn2);
13473 if (class1 != class2 || class1 == VR4130_CLASS_ALU)
13475 /* If only one of the instructions has a dependence on
13476 vr4130_last_insn, prefer to schedule the other one first. */
13477 bool dep1_p = vr4130_true_reg_dependence_p (insn1);
13478 bool dep2_p = vr4130_true_reg_dependence_p (insn2);
13479 if (dep1_p != dep2_p)
13482 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
13483 is not an ALU-type instruction and if INSN1 uses the same
13484 execution unit. (Note that if this condition holds, we already
13485 know that INSN2 uses a different execution unit.) */
13486 if (class1 != VR4130_CLASS_ALU
13487 && recog_memoized (vr4130_last_insn) >= 0
13488 && class1 == get_attr_vr4130_class (vr4130_last_insn))
13495 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
13496 queue with at least two instructions. Swap the first two if
13497 vr4130_swap_insns_p says that it could be worthwhile. */
13500 vr4130_reorder (rtx *ready, int nready)
13502 if (vr4130_swap_insns_p (ready[nready - 1], ready[nready - 2]))
13503 mips_promote_ready (ready, nready - 2, nready - 1);
13506 /* Record whether last 74k AGEN instruction was a load or store. */
13507 static enum attr_type mips_last_74k_agen_insn = TYPE_UNKNOWN;
13509 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
13510 resets to TYPE_UNKNOWN state. */
13513 mips_74k_agen_init (rtx insn)
13515 if (!insn || CALL_P (insn) || JUMP_P (insn))
13516 mips_last_74k_agen_insn = TYPE_UNKNOWN;
13519 enum attr_type type = get_attr_type (insn);
13520 if (type == TYPE_LOAD || type == TYPE_STORE)
13521 mips_last_74k_agen_insn = type;
13525 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
13526 loads to be grouped together, and multiple stores to be grouped
13527 together. Swap things around in the ready queue to make this happen. */
13530 mips_74k_agen_reorder (rtx *ready, int nready)
13533 int store_pos, load_pos;
13538 for (i = nready - 1; i >= 0; i--)
13540 rtx insn = ready[i];
13541 if (USEFUL_INSN_P (insn))
13542 switch (get_attr_type (insn))
13545 if (store_pos == -1)
13550 if (load_pos == -1)
13559 if (load_pos == -1 || store_pos == -1)
13562 switch (mips_last_74k_agen_insn)
13565 /* Prefer to schedule loads since they have a higher latency. */
13567 /* Swap loads to the front of the queue. */
13568 mips_maybe_swap_ready (ready, load_pos, store_pos, 4);
13571 /* Swap stores to the front of the queue. */
13572 mips_maybe_swap_ready (ready, store_pos, load_pos, 4);
13579 /* Implement TARGET_SCHED_INIT. */
13582 mips_sched_init (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13583 int max_ready ATTRIBUTE_UNUSED)
13585 mips_macc_chains_last_hilo = 0;
13586 vr4130_last_insn = 0;
13587 mips_74k_agen_init (NULL_RTX);
13589 /* When scheduling for Loongson2, branch instructions go to ALU1,
13590 therefore basic block is most likely to start with round-robin counter
13591 pointed to ALU2. */
13592 mips_ls2.alu1_turn_p = false;
13593 mips_ls2.falu1_turn_p = true;
13596 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
13599 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13600 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13602 if (!reload_completed
13603 && TUNE_MACC_CHAINS
13605 mips_macc_chains_reorder (ready, *nreadyp);
13607 if (reload_completed
13609 && !TARGET_VR4130_ALIGN
13611 vr4130_reorder (ready, *nreadyp);
13614 mips_74k_agen_reorder (ready, *nreadyp);
13617 /* Implement TARGET_SCHED_REORDER. */
13620 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13621 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13623 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13624 return mips_issue_rate ();
13627 /* Implement TARGET_SCHED_REORDER2. */
13630 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13631 rtx *ready, int *nreadyp, int cycle ATTRIBUTE_UNUSED)
13633 mips_sched_reorder_1 (file, verbose, ready, nreadyp, cycle);
13634 return cached_can_issue_more;
13637 /* Update round-robin counters for ALU1/2 and FALU1/2. */
13640 mips_ls2_variable_issue (rtx insn)
13642 if (mips_ls2.alu1_turn_p)
13644 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu1_core_unit_code))
13645 mips_ls2.alu1_turn_p = false;
13649 if (cpu_unit_reservation_p (curr_state, mips_ls2.alu2_core_unit_code))
13650 mips_ls2.alu1_turn_p = true;
13653 if (mips_ls2.falu1_turn_p)
13655 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu1_core_unit_code))
13656 mips_ls2.falu1_turn_p = false;
13660 if (cpu_unit_reservation_p (curr_state, mips_ls2.falu2_core_unit_code))
13661 mips_ls2.falu1_turn_p = true;
13664 if (recog_memoized (insn) >= 0)
13665 mips_ls2.cycle_has_multi_p |= (get_attr_type (insn) == TYPE_MULTI);
13668 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
13671 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED,
13672 rtx insn, int more)
13674 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
13675 if (USEFUL_INSN_P (insn))
13677 if (get_attr_type (insn) != TYPE_GHOST)
13679 if (!reload_completed && TUNE_MACC_CHAINS)
13680 mips_macc_chains_record (insn);
13681 vr4130_last_insn = insn;
13683 mips_74k_agen_init (insn);
13684 else if (TUNE_LOONGSON_2EF)
13685 mips_ls2_variable_issue (insn);
13688 /* Instructions of type 'multi' should all be split before
13689 the second scheduling pass. */
13690 gcc_assert (!reload_completed
13691 || recog_memoized (insn) < 0
13692 || get_attr_type (insn) != TYPE_MULTI);
13694 cached_can_issue_more = more;
13698 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
13699 return the first operand of the associated PREF or PREFX insn. */
13702 mips_prefetch_cookie (rtx write, rtx locality)
13704 /* store_streamed / load_streamed. */
13705 if (INTVAL (locality) <= 0)
13706 return GEN_INT (INTVAL (write) + 4);
13708 /* store / load. */
13709 if (INTVAL (locality) <= 2)
13712 /* store_retained / load_retained. */
13713 return GEN_INT (INTVAL (write) + 6);
13716 /* Flags that indicate when a built-in function is available.
13718 BUILTIN_AVAIL_NON_MIPS16
13719 The function is available on the current target if !TARGET_MIPS16.
13721 BUILTIN_AVAIL_MIPS16
13722 The function is available on the current target if TARGET_MIPS16. */
13723 #define BUILTIN_AVAIL_NON_MIPS16 1
13724 #define BUILTIN_AVAIL_MIPS16 2
13726 /* Declare an availability predicate for built-in functions that
13727 require non-MIPS16 mode and also require COND to be true.
13728 NAME is the main part of the predicate's name. */
13729 #define AVAIL_NON_MIPS16(NAME, COND) \
13730 static unsigned int \
13731 mips_builtin_avail_##NAME (void) \
13733 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
13736 /* Declare an availability predicate for built-in functions that
13737 support both MIPS16 and non-MIPS16 code and also require COND
13738 to be true. NAME is the main part of the predicate's name. */
13739 #define AVAIL_ALL(NAME, COND) \
13740 static unsigned int \
13741 mips_builtin_avail_##NAME (void) \
13743 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 | BUILTIN_AVAIL_MIPS16 : 0; \
13746 /* This structure describes a single built-in function. */
13747 struct mips_builtin_description {
13748 /* The code of the main .md file instruction. See mips_builtin_type
13749 for more information. */
13750 enum insn_code icode;
13752 /* The floating-point comparison code to use with ICODE, if any. */
13753 enum mips_fp_condition cond;
13755 /* The name of the built-in function. */
13758 /* Specifies how the function should be expanded. */
13759 enum mips_builtin_type builtin_type;
13761 /* The function's prototype. */
13762 enum mips_function_type function_type;
13764 /* Whether the function is available. */
13765 unsigned int (*avail) (void);
13768 AVAIL_ALL (hard_float, TARGET_HARD_FLOAT_ABI)
13769 AVAIL_NON_MIPS16 (paired_single, TARGET_PAIRED_SINGLE_FLOAT)
13770 AVAIL_NON_MIPS16 (sb1_paired_single, TARGET_SB1 && TARGET_PAIRED_SINGLE_FLOAT)
13771 AVAIL_NON_MIPS16 (mips3d, TARGET_MIPS3D)
13772 AVAIL_NON_MIPS16 (dsp, TARGET_DSP)
13773 AVAIL_NON_MIPS16 (dspr2, TARGET_DSPR2)
13774 AVAIL_NON_MIPS16 (dsp_32, !TARGET_64BIT && TARGET_DSP)
13775 AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
13776 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
13777 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
13778 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
13780 /* Construct a mips_builtin_description from the given arguments.
13782 INSN is the name of the associated instruction pattern, without the
13783 leading CODE_FOR_mips_.
13785 CODE is the floating-point condition code associated with the
13786 function. It can be 'f' if the field is not applicable.
13788 NAME is the name of the function itself, without the leading
13791 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
13793 AVAIL is the name of the availability predicate, without the leading
13794 mips_builtin_avail_. */
13795 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
13796 FUNCTION_TYPE, AVAIL) \
13797 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
13798 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
13799 mips_builtin_avail_ ## AVAIL }
13801 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
13802 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
13803 are as for MIPS_BUILTIN. */
13804 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13805 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
13807 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
13808 are subject to mips_builtin_avail_<AVAIL>. */
13809 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
13810 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
13811 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
13812 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
13813 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
13815 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
13816 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
13817 while the any and all forms are subject to mips_builtin_avail_mips3d. */
13818 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
13819 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
13820 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
13822 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
13823 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
13825 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
13826 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
13828 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
13829 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
13832 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
13833 are subject to mips_builtin_avail_mips3d. */
13834 #define CMP_4S_BUILTINS(INSN, COND) \
13835 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
13836 MIPS_BUILTIN_CMP_ANY, \
13837 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
13838 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
13839 MIPS_BUILTIN_CMP_ALL, \
13840 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
13842 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
13843 instruction requires mips_builtin_avail_<AVAIL>. */
13844 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
13845 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
13846 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13848 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
13849 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
13852 /* Define all the built-in functions related to C.cond.fmt condition COND. */
13853 #define CMP_BUILTINS(COND) \
13854 MOVTF_BUILTINS (c, COND, paired_single), \
13855 MOVTF_BUILTINS (cabs, COND, mips3d), \
13856 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
13857 CMP_PS_BUILTINS (c, COND, paired_single), \
13858 CMP_PS_BUILTINS (cabs, COND, mips3d), \
13859 CMP_4S_BUILTINS (c, COND), \
13860 CMP_4S_BUILTINS (cabs, COND)
13862 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
13863 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
13864 and AVAIL are as for MIPS_BUILTIN. */
13865 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
13866 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
13867 FUNCTION_TYPE, AVAIL)
13869 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
13870 branch instruction. AVAIL is as for MIPS_BUILTIN. */
13871 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
13872 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
13873 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
13875 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
13876 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13877 builtin_description field. */
13878 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
13879 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
13880 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
13881 FUNCTION_TYPE, mips_builtin_avail_loongson }
13883 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
13884 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
13885 builtin_description field. */
13886 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
13887 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
13889 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
13890 We use functions of this form when the same insn can be usefully applied
13891 to more than one datatype. */
13892 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
13893 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
13895 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
13896 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
13897 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
13898 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
13899 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
13900 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
13901 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
13902 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
13904 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
13905 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
13906 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
13907 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
13908 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
13909 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
13910 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
13911 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
13912 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
13913 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
13914 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
13915 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
13916 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
13917 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
13918 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
13919 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
13920 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
13921 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
13922 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
13923 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
13924 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
13925 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
13926 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
13927 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
13928 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
13929 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
13930 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
13931 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
13932 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
13933 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
13935 static const struct mips_builtin_description mips_builtins[] = {
13936 #define MIPS_GET_FCSR 0
13937 DIRECT_BUILTIN (get_fcsr, MIPS_USI_FTYPE_VOID, hard_float),
13938 #define MIPS_SET_FCSR 1
13939 DIRECT_NO_TARGET_BUILTIN (set_fcsr, MIPS_VOID_FTYPE_USI, hard_float),
13941 DIRECT_BUILTIN (pll_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13942 DIRECT_BUILTIN (pul_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13943 DIRECT_BUILTIN (plu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13944 DIRECT_BUILTIN (puu_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, paired_single),
13945 DIRECT_BUILTIN (cvt_ps_s, MIPS_V2SF_FTYPE_SF_SF, paired_single),
13946 DIRECT_BUILTIN (cvt_s_pl, MIPS_SF_FTYPE_V2SF, paired_single),
13947 DIRECT_BUILTIN (cvt_s_pu, MIPS_SF_FTYPE_V2SF, paired_single),
13948 DIRECT_BUILTIN (abs_ps, MIPS_V2SF_FTYPE_V2SF, paired_single),
13950 DIRECT_BUILTIN (alnv_ps, MIPS_V2SF_FTYPE_V2SF_V2SF_INT, paired_single),
13951 DIRECT_BUILTIN (addr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13952 DIRECT_BUILTIN (mulr_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13953 DIRECT_BUILTIN (cvt_pw_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13954 DIRECT_BUILTIN (cvt_ps_pw, MIPS_V2SF_FTYPE_V2SF, mips3d),
13956 DIRECT_BUILTIN (recip1_s, MIPS_SF_FTYPE_SF, mips3d),
13957 DIRECT_BUILTIN (recip1_d, MIPS_DF_FTYPE_DF, mips3d),
13958 DIRECT_BUILTIN (recip1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13959 DIRECT_BUILTIN (recip2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13960 DIRECT_BUILTIN (recip2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13961 DIRECT_BUILTIN (recip2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13963 DIRECT_BUILTIN (rsqrt1_s, MIPS_SF_FTYPE_SF, mips3d),
13964 DIRECT_BUILTIN (rsqrt1_d, MIPS_DF_FTYPE_DF, mips3d),
13965 DIRECT_BUILTIN (rsqrt1_ps, MIPS_V2SF_FTYPE_V2SF, mips3d),
13966 DIRECT_BUILTIN (rsqrt2_s, MIPS_SF_FTYPE_SF_SF, mips3d),
13967 DIRECT_BUILTIN (rsqrt2_d, MIPS_DF_FTYPE_DF_DF, mips3d),
13968 DIRECT_BUILTIN (rsqrt2_ps, MIPS_V2SF_FTYPE_V2SF_V2SF, mips3d),
13970 MIPS_FP_CONDITIONS (CMP_BUILTINS),
13972 /* Built-in functions for the SB-1 processor. */
13973 DIRECT_BUILTIN (sqrt_ps, MIPS_V2SF_FTYPE_V2SF, sb1_paired_single),
13975 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
13976 DIRECT_BUILTIN (addq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13977 DIRECT_BUILTIN (addq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13978 DIRECT_BUILTIN (addq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13979 DIRECT_BUILTIN (addu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13980 DIRECT_BUILTIN (addu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13981 DIRECT_BUILTIN (subq_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13982 DIRECT_BUILTIN (subq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
13983 DIRECT_BUILTIN (subq_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
13984 DIRECT_BUILTIN (subu_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13985 DIRECT_BUILTIN (subu_s_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
13986 DIRECT_BUILTIN (addsc, MIPS_SI_FTYPE_SI_SI, dsp),
13987 DIRECT_BUILTIN (addwc, MIPS_SI_FTYPE_SI_SI, dsp),
13988 DIRECT_BUILTIN (modsub, MIPS_SI_FTYPE_SI_SI, dsp),
13989 DIRECT_BUILTIN (raddu_w_qb, MIPS_SI_FTYPE_V4QI, dsp),
13990 DIRECT_BUILTIN (absq_s_ph, MIPS_V2HI_FTYPE_V2HI, dsp),
13991 DIRECT_BUILTIN (absq_s_w, MIPS_SI_FTYPE_SI, dsp),
13992 DIRECT_BUILTIN (precrq_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13993 DIRECT_BUILTIN (precrq_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13994 DIRECT_BUILTIN (precrq_rs_ph_w, MIPS_V2HI_FTYPE_SI_SI, dsp),
13995 DIRECT_BUILTIN (precrqu_s_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dsp),
13996 DIRECT_BUILTIN (preceq_w_phl, MIPS_SI_FTYPE_V2HI, dsp),
13997 DIRECT_BUILTIN (preceq_w_phr, MIPS_SI_FTYPE_V2HI, dsp),
13998 DIRECT_BUILTIN (precequ_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
13999 DIRECT_BUILTIN (precequ_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
14000 DIRECT_BUILTIN (precequ_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
14001 DIRECT_BUILTIN (precequ_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
14002 DIRECT_BUILTIN (preceu_ph_qbl, MIPS_V2HI_FTYPE_V4QI, dsp),
14003 DIRECT_BUILTIN (preceu_ph_qbr, MIPS_V2HI_FTYPE_V4QI, dsp),
14004 DIRECT_BUILTIN (preceu_ph_qbla, MIPS_V2HI_FTYPE_V4QI, dsp),
14005 DIRECT_BUILTIN (preceu_ph_qbra, MIPS_V2HI_FTYPE_V4QI, dsp),
14006 DIRECT_BUILTIN (shll_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
14007 DIRECT_BUILTIN (shll_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14008 DIRECT_BUILTIN (shll_s_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14009 DIRECT_BUILTIN (shll_s_w, MIPS_SI_FTYPE_SI_SI, dsp),
14010 DIRECT_BUILTIN (shrl_qb, MIPS_V4QI_FTYPE_V4QI_SI, dsp),
14011 DIRECT_BUILTIN (shra_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14012 DIRECT_BUILTIN (shra_r_ph, MIPS_V2HI_FTYPE_V2HI_SI, dsp),
14013 DIRECT_BUILTIN (shra_r_w, MIPS_SI_FTYPE_SI_SI, dsp),
14014 DIRECT_BUILTIN (muleu_s_ph_qbl, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
14015 DIRECT_BUILTIN (muleu_s_ph_qbr, MIPS_V2HI_FTYPE_V4QI_V2HI, dsp),
14016 DIRECT_BUILTIN (mulq_rs_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14017 DIRECT_BUILTIN (muleq_s_w_phl, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
14018 DIRECT_BUILTIN (muleq_s_w_phr, MIPS_SI_FTYPE_V2HI_V2HI, dsp),
14019 DIRECT_BUILTIN (bitrev, MIPS_SI_FTYPE_SI, dsp),
14020 DIRECT_BUILTIN (insv, MIPS_SI_FTYPE_SI_SI, dsp),
14021 DIRECT_BUILTIN (repl_qb, MIPS_V4QI_FTYPE_SI, dsp),
14022 DIRECT_BUILTIN (repl_ph, MIPS_V2HI_FTYPE_SI, dsp),
14023 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14024 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14025 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb, MIPS_VOID_FTYPE_V4QI_V4QI, dsp),
14026 DIRECT_BUILTIN (cmpgu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14027 DIRECT_BUILTIN (cmpgu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14028 DIRECT_BUILTIN (cmpgu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dsp),
14029 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14030 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14031 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph, MIPS_VOID_FTYPE_V2HI_V2HI, dsp),
14032 DIRECT_BUILTIN (pick_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dsp),
14033 DIRECT_BUILTIN (pick_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14034 DIRECT_BUILTIN (packrl_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dsp),
14035 DIRECT_NO_TARGET_BUILTIN (wrdsp, MIPS_VOID_FTYPE_SI_SI, dsp),
14036 DIRECT_BUILTIN (rddsp, MIPS_SI_FTYPE_SI, dsp),
14037 DIRECT_BUILTIN (lbux, MIPS_SI_FTYPE_POINTER_SI, dsp),
14038 DIRECT_BUILTIN (lhx, MIPS_SI_FTYPE_POINTER_SI, dsp),
14039 DIRECT_BUILTIN (lwx, MIPS_SI_FTYPE_POINTER_SI, dsp),
14040 BPOSGE_BUILTIN (32, dsp),
14042 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
14043 DIRECT_BUILTIN (absq_s_qb, MIPS_V4QI_FTYPE_V4QI, dspr2),
14044 DIRECT_BUILTIN (addu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14045 DIRECT_BUILTIN (addu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14046 DIRECT_BUILTIN (adduh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14047 DIRECT_BUILTIN (adduh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14048 DIRECT_BUILTIN (append, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14049 DIRECT_BUILTIN (balign, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14050 DIRECT_BUILTIN (cmpgdu_eq_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14051 DIRECT_BUILTIN (cmpgdu_lt_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14052 DIRECT_BUILTIN (cmpgdu_le_qb, MIPS_SI_FTYPE_V4QI_V4QI, dspr2),
14053 DIRECT_BUILTIN (mul_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14054 DIRECT_BUILTIN (mul_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14055 DIRECT_BUILTIN (mulq_rs_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14056 DIRECT_BUILTIN (mulq_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14057 DIRECT_BUILTIN (mulq_s_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14058 DIRECT_BUILTIN (precr_qb_ph, MIPS_V4QI_FTYPE_V2HI_V2HI, dspr2),
14059 DIRECT_BUILTIN (precr_sra_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
14060 DIRECT_BUILTIN (precr_sra_r_ph_w, MIPS_V2HI_FTYPE_SI_SI_SI, dspr2),
14061 DIRECT_BUILTIN (prepend, MIPS_SI_FTYPE_SI_SI_SI, dspr2),
14062 DIRECT_BUILTIN (shra_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
14063 DIRECT_BUILTIN (shra_r_qb, MIPS_V4QI_FTYPE_V4QI_SI, dspr2),
14064 DIRECT_BUILTIN (shrl_ph, MIPS_V2HI_FTYPE_V2HI_SI, dspr2),
14065 DIRECT_BUILTIN (subu_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14066 DIRECT_BUILTIN (subu_s_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14067 DIRECT_BUILTIN (subuh_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14068 DIRECT_BUILTIN (subuh_r_qb, MIPS_V4QI_FTYPE_V4QI_V4QI, dspr2),
14069 DIRECT_BUILTIN (addqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14070 DIRECT_BUILTIN (addqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14071 DIRECT_BUILTIN (addqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14072 DIRECT_BUILTIN (addqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14073 DIRECT_BUILTIN (subqh_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14074 DIRECT_BUILTIN (subqh_r_ph, MIPS_V2HI_FTYPE_V2HI_V2HI, dspr2),
14075 DIRECT_BUILTIN (subqh_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14076 DIRECT_BUILTIN (subqh_r_w, MIPS_SI_FTYPE_SI_SI, dspr2),
14078 /* Built-in functions for the DSP ASE (32-bit only). */
14079 DIRECT_BUILTIN (dpau_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14080 DIRECT_BUILTIN (dpau_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14081 DIRECT_BUILTIN (dpsu_h_qbl, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14082 DIRECT_BUILTIN (dpsu_h_qbr, MIPS_DI_FTYPE_DI_V4QI_V4QI, dsp_32),
14083 DIRECT_BUILTIN (dpaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14084 DIRECT_BUILTIN (dpsq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14085 DIRECT_BUILTIN (mulsaq_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14086 DIRECT_BUILTIN (dpaq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14087 DIRECT_BUILTIN (dpsq_sa_l_w, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14088 DIRECT_BUILTIN (maq_s_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14089 DIRECT_BUILTIN (maq_s_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14090 DIRECT_BUILTIN (maq_sa_w_phl, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14091 DIRECT_BUILTIN (maq_sa_w_phr, MIPS_DI_FTYPE_DI_V2HI_V2HI, dsp_32),
14092 DIRECT_BUILTIN (extr_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14093 DIRECT_BUILTIN (extr_r_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14094 DIRECT_BUILTIN (extr_rs_w, MIPS_SI_FTYPE_DI_SI, dsp_32),
14095 DIRECT_BUILTIN (extr_s_h, MIPS_SI_FTYPE_DI_SI, dsp_32),
14096 DIRECT_BUILTIN (extp, MIPS_SI_FTYPE_DI_SI, dsp_32),
14097 DIRECT_BUILTIN (extpdp, MIPS_SI_FTYPE_DI_SI, dsp_32),
14098 DIRECT_BUILTIN (shilo, MIPS_DI_FTYPE_DI_SI, dsp_32),
14099 DIRECT_BUILTIN (mthlip, MIPS_DI_FTYPE_DI_SI, dsp_32),
14100 DIRECT_BUILTIN (madd, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14101 DIRECT_BUILTIN (maddu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
14102 DIRECT_BUILTIN (msub, MIPS_DI_FTYPE_DI_SI_SI, dsp_32),
14103 DIRECT_BUILTIN (msubu, MIPS_DI_FTYPE_DI_USI_USI, dsp_32),
14104 DIRECT_BUILTIN (mult, MIPS_DI_FTYPE_SI_SI, dsp_32),
14105 DIRECT_BUILTIN (multu, MIPS_DI_FTYPE_USI_USI, dsp_32),
14107 /* Built-in functions for the DSP ASE (64-bit only). */
14108 DIRECT_BUILTIN (ldx, MIPS_DI_FTYPE_POINTER_SI, dsp_64),
14110 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
14111 DIRECT_BUILTIN (dpa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14112 DIRECT_BUILTIN (dps_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14113 DIRECT_BUILTIN (mulsa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14114 DIRECT_BUILTIN (dpax_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14115 DIRECT_BUILTIN (dpsx_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14116 DIRECT_BUILTIN (dpaqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14117 DIRECT_BUILTIN (dpaqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14118 DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14119 DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
14121 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
14122 LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
14123 LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
14124 LOONGSON_BUILTIN (packushb, MIPS_UV8QI_FTYPE_UV4HI_UV4HI),
14125 LOONGSON_BUILTIN_SUFFIX (paddw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14126 LOONGSON_BUILTIN_SUFFIX (paddh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14127 LOONGSON_BUILTIN_SUFFIX (paddb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14128 LOONGSON_BUILTIN_SUFFIX (paddw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14129 LOONGSON_BUILTIN_SUFFIX (paddh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14130 LOONGSON_BUILTIN_SUFFIX (paddb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14131 LOONGSON_BUILTIN_SUFFIX (paddd, u, MIPS_UDI_FTYPE_UDI_UDI),
14132 LOONGSON_BUILTIN_SUFFIX (paddd, s, MIPS_DI_FTYPE_DI_DI),
14133 LOONGSON_BUILTIN (paddsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14134 LOONGSON_BUILTIN (paddsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14135 LOONGSON_BUILTIN (paddush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14136 LOONGSON_BUILTIN (paddusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14137 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_ud, MIPS_UDI_FTYPE_UDI_UDI),
14138 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_uw, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14139 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_uh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14140 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_ub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14141 LOONGSON_BUILTIN_ALIAS (pandn_d, pandn_sd, MIPS_DI_FTYPE_DI_DI),
14142 LOONGSON_BUILTIN_ALIAS (pandn_w, pandn_sw, MIPS_V2SI_FTYPE_V2SI_V2SI),
14143 LOONGSON_BUILTIN_ALIAS (pandn_h, pandn_sh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14144 LOONGSON_BUILTIN_ALIAS (pandn_b, pandn_sb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14145 LOONGSON_BUILTIN (pavgh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14146 LOONGSON_BUILTIN (pavgb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14147 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14148 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14149 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14150 LOONGSON_BUILTIN_SUFFIX (pcmpeqw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14151 LOONGSON_BUILTIN_SUFFIX (pcmpeqh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14152 LOONGSON_BUILTIN_SUFFIX (pcmpeqb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14153 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14154 LOONGSON_BUILTIN_SUFFIX (pcmpgth, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14155 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14156 LOONGSON_BUILTIN_SUFFIX (pcmpgtw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14157 LOONGSON_BUILTIN_SUFFIX (pcmpgth, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14158 LOONGSON_BUILTIN_SUFFIX (pcmpgtb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14159 LOONGSON_BUILTIN_SUFFIX (pextrh, u, MIPS_UV4HI_FTYPE_UV4HI_USI),
14160 LOONGSON_BUILTIN_SUFFIX (pextrh, s, MIPS_V4HI_FTYPE_V4HI_USI),
14161 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14162 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14163 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14164 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14165 LOONGSON_BUILTIN_SUFFIX (pinsrh_0, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14166 LOONGSON_BUILTIN_SUFFIX (pinsrh_1, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14167 LOONGSON_BUILTIN_SUFFIX (pinsrh_2, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14168 LOONGSON_BUILTIN_SUFFIX (pinsrh_3, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14169 LOONGSON_BUILTIN (pmaddhw, MIPS_V2SI_FTYPE_V4HI_V4HI),
14170 LOONGSON_BUILTIN (pmaxsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14171 LOONGSON_BUILTIN (pmaxub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14172 LOONGSON_BUILTIN (pminsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14173 LOONGSON_BUILTIN (pminub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14174 LOONGSON_BUILTIN_SUFFIX (pmovmskb, u, MIPS_UV8QI_FTYPE_UV8QI),
14175 LOONGSON_BUILTIN_SUFFIX (pmovmskb, s, MIPS_V8QI_FTYPE_V8QI),
14176 LOONGSON_BUILTIN (pmulhuh, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14177 LOONGSON_BUILTIN (pmulhh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14178 LOONGSON_BUILTIN (pmullh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14179 LOONGSON_BUILTIN (pmuluw, MIPS_UDI_FTYPE_UV2SI_UV2SI),
14180 LOONGSON_BUILTIN (pasubub, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14181 LOONGSON_BUILTIN (biadd, MIPS_UV4HI_FTYPE_UV8QI),
14182 LOONGSON_BUILTIN (psadbh, MIPS_UV4HI_FTYPE_UV8QI_UV8QI),
14183 LOONGSON_BUILTIN_SUFFIX (pshufh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14184 LOONGSON_BUILTIN_SUFFIX (pshufh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14185 LOONGSON_BUILTIN_SUFFIX (psllh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14186 LOONGSON_BUILTIN_SUFFIX (psllh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14187 LOONGSON_BUILTIN_SUFFIX (psllw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14188 LOONGSON_BUILTIN_SUFFIX (psllw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14189 LOONGSON_BUILTIN_SUFFIX (psrah, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14190 LOONGSON_BUILTIN_SUFFIX (psrah, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14191 LOONGSON_BUILTIN_SUFFIX (psraw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14192 LOONGSON_BUILTIN_SUFFIX (psraw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14193 LOONGSON_BUILTIN_SUFFIX (psrlh, u, MIPS_UV4HI_FTYPE_UV4HI_UQI),
14194 LOONGSON_BUILTIN_SUFFIX (psrlh, s, MIPS_V4HI_FTYPE_V4HI_UQI),
14195 LOONGSON_BUILTIN_SUFFIX (psrlw, u, MIPS_UV2SI_FTYPE_UV2SI_UQI),
14196 LOONGSON_BUILTIN_SUFFIX (psrlw, s, MIPS_V2SI_FTYPE_V2SI_UQI),
14197 LOONGSON_BUILTIN_SUFFIX (psubw, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14198 LOONGSON_BUILTIN_SUFFIX (psubh, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14199 LOONGSON_BUILTIN_SUFFIX (psubb, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14200 LOONGSON_BUILTIN_SUFFIX (psubw, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14201 LOONGSON_BUILTIN_SUFFIX (psubh, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14202 LOONGSON_BUILTIN_SUFFIX (psubb, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14203 LOONGSON_BUILTIN_SUFFIX (psubd, u, MIPS_UDI_FTYPE_UDI_UDI),
14204 LOONGSON_BUILTIN_SUFFIX (psubd, s, MIPS_DI_FTYPE_DI_DI),
14205 LOONGSON_BUILTIN (psubsh, MIPS_V4HI_FTYPE_V4HI_V4HI),
14206 LOONGSON_BUILTIN (psubsb, MIPS_V8QI_FTYPE_V8QI_V8QI),
14207 LOONGSON_BUILTIN (psubush, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14208 LOONGSON_BUILTIN (psubusb, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14209 LOONGSON_BUILTIN_SUFFIX (punpckhbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14210 LOONGSON_BUILTIN_SUFFIX (punpckhhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14211 LOONGSON_BUILTIN_SUFFIX (punpckhwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14212 LOONGSON_BUILTIN_SUFFIX (punpckhbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14213 LOONGSON_BUILTIN_SUFFIX (punpckhhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14214 LOONGSON_BUILTIN_SUFFIX (punpckhwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14215 LOONGSON_BUILTIN_SUFFIX (punpcklbh, u, MIPS_UV8QI_FTYPE_UV8QI_UV8QI),
14216 LOONGSON_BUILTIN_SUFFIX (punpcklhw, u, MIPS_UV4HI_FTYPE_UV4HI_UV4HI),
14217 LOONGSON_BUILTIN_SUFFIX (punpcklwd, u, MIPS_UV2SI_FTYPE_UV2SI_UV2SI),
14218 LOONGSON_BUILTIN_SUFFIX (punpcklbh, s, MIPS_V8QI_FTYPE_V8QI_V8QI),
14219 LOONGSON_BUILTIN_SUFFIX (punpcklhw, s, MIPS_V4HI_FTYPE_V4HI_V4HI),
14220 LOONGSON_BUILTIN_SUFFIX (punpcklwd, s, MIPS_V2SI_FTYPE_V2SI_V2SI),
14222 /* Sundry other built-in functions. */
14223 DIRECT_NO_TARGET_BUILTIN (cache, MIPS_VOID_FTYPE_SI_CVPOINTER, cache)
14226 /* Index I is the function declaration for mips_builtins[I], or null if the
14227 function isn't defined on this target. */
14228 static GTY(()) tree mips_builtin_decls[ARRAY_SIZE (mips_builtins)];
14230 /* MODE is a vector mode whose elements have type TYPE. Return the type
14231 of the vector itself. */
14234 mips_builtin_vector_type (tree type, enum machine_mode mode)
14236 static tree types[2 * (int) MAX_MACHINE_MODE];
14239 mode_index = (int) mode;
14241 if (TREE_CODE (type) == INTEGER_TYPE && TYPE_UNSIGNED (type))
14242 mode_index += MAX_MACHINE_MODE;
14244 if (types[mode_index] == NULL_TREE)
14245 types[mode_index] = build_vector_type_for_mode (type, mode);
14246 return types[mode_index];
14249 /* Return a type for 'const volatile void *'. */
14252 mips_build_cvpointer_type (void)
14256 if (cache == NULL_TREE)
14257 cache = build_pointer_type (build_qualified_type
14259 TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE));
14263 /* Source-level argument types. */
14264 #define MIPS_ATYPE_VOID void_type_node
14265 #define MIPS_ATYPE_INT integer_type_node
14266 #define MIPS_ATYPE_POINTER ptr_type_node
14267 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
14269 /* Standard mode-based argument types. */
14270 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
14271 #define MIPS_ATYPE_SI intSI_type_node
14272 #define MIPS_ATYPE_USI unsigned_intSI_type_node
14273 #define MIPS_ATYPE_DI intDI_type_node
14274 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
14275 #define MIPS_ATYPE_SF float_type_node
14276 #define MIPS_ATYPE_DF double_type_node
14278 /* Vector argument types. */
14279 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
14280 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
14281 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
14282 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
14283 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
14284 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
14285 #define MIPS_ATYPE_UV2SI \
14286 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
14287 #define MIPS_ATYPE_UV4HI \
14288 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
14289 #define MIPS_ATYPE_UV8QI \
14290 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
14292 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
14293 their associated MIPS_ATYPEs. */
14294 #define MIPS_FTYPE_ATYPES1(A, B) \
14295 MIPS_ATYPE_##A, MIPS_ATYPE_##B
14297 #define MIPS_FTYPE_ATYPES2(A, B, C) \
14298 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
14300 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
14301 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
14303 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
14304 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
14307 /* Return the function type associated with function prototype TYPE. */
14310 mips_build_function_type (enum mips_function_type type)
14312 static tree types[(int) MIPS_MAX_FTYPE_MAX];
14314 if (types[(int) type] == NULL_TREE)
14317 #define DEF_MIPS_FTYPE(NUM, ARGS) \
14318 case MIPS_FTYPE_NAME##NUM ARGS: \
14319 types[(int) type] \
14320 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
14323 #include "config/mips/mips-ftypes.def"
14324 #undef DEF_MIPS_FTYPE
14326 gcc_unreachable ();
14329 return types[(int) type];
14332 /* Implement TARGET_INIT_BUILTINS. */
14335 mips_init_builtins (void)
14337 const struct mips_builtin_description *d;
14340 /* Iterate through all of the bdesc arrays, initializing all of the
14341 builtin functions. */
14342 for (i = 0; i < ARRAY_SIZE (mips_builtins); i++)
14344 d = &mips_builtins[i];
14346 mips_builtin_decls[i]
14347 = add_builtin_function (d->name,
14348 mips_build_function_type (d->function_type),
14349 i, BUILT_IN_MD, NULL, NULL);
14353 /* Implement TARGET_BUILTIN_DECL. */
14356 mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
14358 if (code >= ARRAY_SIZE (mips_builtins))
14359 return error_mark_node;
14360 return mips_builtin_decls[code];
14363 /* Take argument ARGNO from EXP's argument list and convert it into
14364 an expand operand. Store the operand in *OP. */
14367 mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
14368 unsigned int argno)
14373 arg = CALL_EXPR_ARG (exp, argno);
14374 value = expand_normal (arg);
14375 create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
14378 /* Expand instruction ICODE as part of a built-in function sequence.
14379 Use the first NOPS elements of OPS as the instruction's operands.
14380 HAS_TARGET_P is true if operand 0 is a target; it is false if the
14381 instruction has no target.
14383 Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
14386 mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
14387 struct expand_operand *ops, bool has_target_p)
14389 if (!maybe_expand_insn (icode, nops, ops))
14391 error ("invalid argument to built-in function");
14392 return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
14394 return has_target_p ? ops[0].value : const0_rtx;
14397 /* Expand a floating-point comparison for built-in function call EXP.
14398 The first NARGS arguments are the values to be compared. ICODE is
14399 the .md pattern that does the comparison and COND is the condition
14400 that is being tested. Return an rtx for the result. */
14403 mips_expand_builtin_compare_1 (enum insn_code icode,
14404 enum mips_fp_condition cond,
14405 tree exp, int nargs)
14407 struct expand_operand ops[MAX_RECOG_OPERANDS];
14411 /* The instruction should have a target operand, an operand for each
14412 argument, and an operand for COND. */
14413 gcc_assert (nargs + 2 == insn_data[(int) icode].n_generator_args);
14415 output = mips_allocate_fcc (insn_data[(int) icode].operand[0].mode);
14417 create_fixed_operand (&ops[opno++], output);
14418 for (argno = 0; argno < nargs; argno++)
14419 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14420 create_integer_operand (&ops[opno++], (int) cond);
14421 return mips_expand_builtin_insn (icode, opno, ops, true);
14424 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
14425 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
14426 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
14427 suggests a good place to put the result. */
14430 mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
14433 struct expand_operand ops[MAX_RECOG_OPERANDS];
14436 /* Map any target to operand 0. */
14439 create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
14441 /* Map the arguments to the other operands. */
14442 gcc_assert (opno + call_expr_nargs (exp)
14443 == insn_data[icode].n_generator_args);
14444 for (argno = 0; argno < call_expr_nargs (exp); argno++)
14445 mips_prepare_builtin_arg (&ops[opno++], exp, argno);
14447 return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
14450 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
14451 function; TYPE says which. EXP is the CALL_EXPR that calls the
14452 function, ICODE is the instruction that should be used to compare
14453 the first two arguments, and COND is the condition it should test.
14454 TARGET, if nonnull, suggests a good place to put the result. */
14457 mips_expand_builtin_movtf (enum mips_builtin_type type,
14458 enum insn_code icode, enum mips_fp_condition cond,
14459 rtx target, tree exp)
14461 struct expand_operand ops[4];
14464 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
14465 create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
14466 if (type == MIPS_BUILTIN_MOVT)
14468 mips_prepare_builtin_arg (&ops[2], exp, 2);
14469 mips_prepare_builtin_arg (&ops[1], exp, 3);
14473 mips_prepare_builtin_arg (&ops[1], exp, 2);
14474 mips_prepare_builtin_arg (&ops[2], exp, 3);
14476 create_fixed_operand (&ops[3], cmp_result);
14477 return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
14481 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
14482 into TARGET otherwise. Return TARGET. */
14485 mips_builtin_branch_and_move (rtx condition, rtx target,
14486 rtx value_if_true, rtx value_if_false)
14488 rtx true_label, done_label;
14490 true_label = gen_label_rtx ();
14491 done_label = gen_label_rtx ();
14493 /* First assume that CONDITION is false. */
14494 mips_emit_move (target, value_if_false);
14496 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
14497 emit_jump_insn (gen_condjump (condition, true_label));
14498 emit_jump_insn (gen_jump (done_label));
14501 /* Fix TARGET if CONDITION is true. */
14502 emit_label (true_label);
14503 mips_emit_move (target, value_if_true);
14505 emit_label (done_label);
14509 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
14510 the CALL_EXPR that calls the function, ICODE is the code of the
14511 comparison instruction, and COND is the condition it should test.
14512 TARGET, if nonnull, suggests a good place to put the boolean result. */
14515 mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
14516 enum insn_code icode, enum mips_fp_condition cond,
14517 rtx target, tree exp)
14519 rtx offset, condition, cmp_result;
14521 if (target == 0 || GET_MODE (target) != SImode)
14522 target = gen_reg_rtx (SImode);
14523 cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
14524 call_expr_nargs (exp));
14526 /* If the comparison sets more than one register, we define the result
14527 to be 0 if all registers are false and -1 if all registers are true.
14528 The value of the complete result is indeterminate otherwise. */
14529 switch (builtin_type)
14531 case MIPS_BUILTIN_CMP_ALL:
14532 condition = gen_rtx_NE (VOIDmode, cmp_result, constm1_rtx);
14533 return mips_builtin_branch_and_move (condition, target,
14534 const0_rtx, const1_rtx);
14536 case MIPS_BUILTIN_CMP_UPPER:
14537 case MIPS_BUILTIN_CMP_LOWER:
14538 offset = GEN_INT (builtin_type == MIPS_BUILTIN_CMP_UPPER);
14539 condition = gen_single_cc (cmp_result, offset);
14540 return mips_builtin_branch_and_move (condition, target,
14541 const1_rtx, const0_rtx);
14544 condition = gen_rtx_NE (VOIDmode, cmp_result, const0_rtx);
14545 return mips_builtin_branch_and_move (condition, target,
14546 const1_rtx, const0_rtx);
14550 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
14551 if nonnull, suggests a good place to put the boolean result. */
14554 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target)
14556 rtx condition, cmp_result;
14559 if (target == 0 || GET_MODE (target) != SImode)
14560 target = gen_reg_rtx (SImode);
14562 cmp_result = gen_rtx_REG (CCDSPmode, CCDSP_PO_REGNUM);
14564 if (builtin_type == MIPS_BUILTIN_BPOSGE32)
14569 condition = gen_rtx_GE (VOIDmode, cmp_result, GEN_INT (cmp_value));
14570 return mips_builtin_branch_and_move (condition, target,
14571 const1_rtx, const0_rtx);
14574 /* Implement TARGET_EXPAND_BUILTIN. */
14577 mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
14578 enum machine_mode mode, int ignore)
14581 unsigned int fcode, avail;
14582 const struct mips_builtin_description *d;
14584 fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
14585 fcode = DECL_FUNCTION_CODE (fndecl);
14586 gcc_assert (fcode < ARRAY_SIZE (mips_builtins));
14587 d = &mips_builtins[fcode];
14588 avail = d->avail ();
14589 gcc_assert (avail != 0);
14590 if (TARGET_MIPS16 && !(avail & BUILTIN_AVAIL_MIPS16))
14592 error ("built-in function %qE not supported for MIPS16",
14593 DECL_NAME (fndecl));
14594 return ignore ? const0_rtx : CONST0_RTX (mode);
14596 switch (d->builtin_type)
14598 case MIPS_BUILTIN_DIRECT:
14599 return mips_expand_builtin_direct (d->icode, target, exp, true);
14601 case MIPS_BUILTIN_DIRECT_NO_TARGET:
14602 return mips_expand_builtin_direct (d->icode, target, exp, false);
14604 case MIPS_BUILTIN_MOVT:
14605 case MIPS_BUILTIN_MOVF:
14606 return mips_expand_builtin_movtf (d->builtin_type, d->icode,
14607 d->cond, target, exp);
14609 case MIPS_BUILTIN_CMP_ANY:
14610 case MIPS_BUILTIN_CMP_ALL:
14611 case MIPS_BUILTIN_CMP_UPPER:
14612 case MIPS_BUILTIN_CMP_LOWER:
14613 case MIPS_BUILTIN_CMP_SINGLE:
14614 return mips_expand_builtin_compare (d->builtin_type, d->icode,
14615 d->cond, target, exp);
14617 case MIPS_BUILTIN_BPOSGE32:
14618 return mips_expand_builtin_bposge (d->builtin_type, target);
14620 gcc_unreachable ();
14623 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
14624 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
14625 struct mips16_constant {
14626 struct mips16_constant *next;
14629 enum machine_mode mode;
14632 /* Information about an incomplete MIPS16 constant pool. FIRST is the
14633 first constant, HIGHEST_ADDRESS is the highest address that the first
14634 byte of the pool can have, and INSN_ADDRESS is the current instruction
14636 struct mips16_constant_pool {
14637 struct mips16_constant *first;
14638 int highest_address;
14642 /* Add constant VALUE to POOL and return its label. MODE is the
14643 value's mode (used for CONST_INTs, etc.). */
14646 mips16_add_constant (struct mips16_constant_pool *pool,
14647 rtx value, enum machine_mode mode)
14649 struct mips16_constant **p, *c;
14650 bool first_of_size_p;
14652 /* See whether the constant is already in the pool. If so, return the
14653 existing label, otherwise leave P pointing to the place where the
14654 constant should be added.
14656 Keep the pool sorted in increasing order of mode size so that we can
14657 reduce the number of alignments needed. */
14658 first_of_size_p = true;
14659 for (p = &pool->first; *p != 0; p = &(*p)->next)
14661 if (mode == (*p)->mode && rtx_equal_p (value, (*p)->value))
14662 return (*p)->label;
14663 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE ((*p)->mode))
14665 if (GET_MODE_SIZE (mode) == GET_MODE_SIZE ((*p)->mode))
14666 first_of_size_p = false;
14669 /* In the worst case, the constant needed by the earliest instruction
14670 will end up at the end of the pool. The entire pool must then be
14671 accessible from that instruction.
14673 When adding the first constant, set the pool's highest address to
14674 the address of the first out-of-range byte. Adjust this address
14675 downwards each time a new constant is added. */
14676 if (pool->first == 0)
14677 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
14678 of the instruction with the lowest two bits clear. The base PC
14679 value for LDPC has the lowest three bits clear. Assume the worst
14680 case here; namely that the PC-relative instruction occupies the
14681 last 2 bytes in an aligned word. */
14682 pool->highest_address = pool->insn_address - (UNITS_PER_WORD - 2) + 0x8000;
14683 pool->highest_address -= GET_MODE_SIZE (mode);
14684 if (first_of_size_p)
14685 /* Take into account the worst possible padding due to alignment. */
14686 pool->highest_address -= GET_MODE_SIZE (mode) - 1;
14688 /* Create a new entry. */
14689 c = XNEW (struct mips16_constant);
14692 c->label = gen_label_rtx ();
14699 /* Output constant VALUE after instruction INSN and return the last
14700 instruction emitted. MODE is the mode of the constant. */
14703 mips16_emit_constants_1 (enum machine_mode mode, rtx value, rtx insn)
14705 if (SCALAR_INT_MODE_P (mode) || ALL_SCALAR_FIXED_POINT_MODE_P (mode))
14707 rtx size = GEN_INT (GET_MODE_SIZE (mode));
14708 return emit_insn_after (gen_consttable_int (value, size), insn);
14711 if (SCALAR_FLOAT_MODE_P (mode))
14712 return emit_insn_after (gen_consttable_float (value), insn);
14714 if (VECTOR_MODE_P (mode))
14718 for (i = 0; i < CONST_VECTOR_NUNITS (value); i++)
14719 insn = mips16_emit_constants_1 (GET_MODE_INNER (mode),
14720 CONST_VECTOR_ELT (value, i), insn);
14724 gcc_unreachable ();
14727 /* Dump out the constants in CONSTANTS after INSN. */
14730 mips16_emit_constants (struct mips16_constant *constants, rtx insn)
14732 struct mips16_constant *c, *next;
14736 for (c = constants; c != NULL; c = next)
14738 /* If necessary, increase the alignment of PC. */
14739 if (align < GET_MODE_SIZE (c->mode))
14741 int align_log = floor_log2 (GET_MODE_SIZE (c->mode));
14742 insn = emit_insn_after (gen_align (GEN_INT (align_log)), insn);
14744 align = GET_MODE_SIZE (c->mode);
14746 insn = emit_label_after (c->label, insn);
14747 insn = mips16_emit_constants_1 (c->mode, c->value, insn);
14753 emit_barrier_after (insn);
14756 /* Return the length of instruction INSN. */
14759 mips16_insn_length (rtx insn)
14761 if (JUMP_TABLE_DATA_P (insn))
14763 rtx body = PATTERN (insn);
14764 if (GET_CODE (body) == ADDR_VEC)
14765 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 0);
14766 else if (GET_CODE (body) == ADDR_DIFF_VEC)
14767 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, 1);
14769 gcc_unreachable ();
14771 return get_attr_length (insn);
14774 /* If *X is a symbolic constant that refers to the constant pool, add
14775 the constant to POOL and rewrite *X to use the constant's label. */
14778 mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
14780 rtx base, offset, label;
14782 split_const (*x, &base, &offset);
14783 if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
14785 label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
14786 get_pool_mode (base));
14787 base = gen_rtx_LABEL_REF (Pmode, label);
14788 *x = mips_unspec_address_offset (base, offset, SYMBOL_PC_RELATIVE);
14792 /* This structure is used to communicate with mips16_rewrite_pool_refs.
14793 INSN is the instruction we're rewriting and POOL points to the current
14795 struct mips16_rewrite_pool_refs_info {
14797 struct mips16_constant_pool *pool;
14800 /* Rewrite *X so that constant pool references refer to the constant's
14801 label instead. DATA points to a mips16_rewrite_pool_refs_info
14805 mips16_rewrite_pool_refs (rtx *x, void *data)
14807 struct mips16_rewrite_pool_refs_info *info =
14808 (struct mips16_rewrite_pool_refs_info *) data;
14810 if (force_to_mem_operand (*x, Pmode))
14812 rtx mem = force_const_mem (GET_MODE (*x), *x);
14813 validate_change (info->insn, x, mem, false);
14818 mips16_rewrite_pool_constant (info->pool, &XEXP (*x, 0));
14822 /* Don't rewrite the __mips16_rdwr symbol. */
14823 if (GET_CODE (*x) == UNSPEC && XINT (*x, 1) == UNSPEC_TLS_GET_TP)
14826 if (TARGET_MIPS16_TEXT_LOADS)
14827 mips16_rewrite_pool_constant (info->pool, x);
14829 return GET_CODE (*x) == CONST ? -1 : 0;
14832 /* Return whether CFG is used in mips_reorg. */
14835 mips_cfg_in_reorg (void)
14837 return (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
14838 || TARGET_RELAX_PIC_CALLS);
14841 /* Build MIPS16 constant pools. Split the instructions if SPLIT_P,
14842 otherwise assume that they are already split. */
14845 mips16_lay_out_constants (bool split_p)
14847 struct mips16_constant_pool pool;
14848 struct mips16_rewrite_pool_refs_info info;
14851 if (!TARGET_MIPS16_PCREL_LOADS)
14856 if (mips_cfg_in_reorg ())
14857 split_all_insns ();
14859 split_all_insns_noflow ();
14862 memset (&pool, 0, sizeof (pool));
14863 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14865 /* Rewrite constant pool references in INSN. */
14866 if (USEFUL_INSN_P (insn))
14870 for_each_rtx (&PATTERN (insn), mips16_rewrite_pool_refs, &info);
14873 pool.insn_address += mips16_insn_length (insn);
14875 if (pool.first != NULL)
14877 /* If there are no natural barriers between the first user of
14878 the pool and the highest acceptable address, we'll need to
14879 create a new instruction to jump around the constant pool.
14880 In the worst case, this instruction will be 4 bytes long.
14882 If it's too late to do this transformation after INSN,
14883 do it immediately before INSN. */
14884 if (barrier == 0 && pool.insn_address + 4 > pool.highest_address)
14888 label = gen_label_rtx ();
14890 jump = emit_jump_insn_before (gen_jump (label), insn);
14891 JUMP_LABEL (jump) = label;
14892 LABEL_NUSES (label) = 1;
14893 barrier = emit_barrier_after (jump);
14895 emit_label_after (label, barrier);
14896 pool.insn_address += 4;
14899 /* See whether the constant pool is now out of range of the first
14900 user. If so, output the constants after the previous barrier.
14901 Note that any instructions between BARRIER and INSN (inclusive)
14902 will use negative offsets to refer to the pool. */
14903 if (pool.insn_address > pool.highest_address)
14905 mips16_emit_constants (pool.first, barrier);
14909 else if (BARRIER_P (insn))
14913 mips16_emit_constants (pool.first, get_last_insn ());
14916 /* Return true if it is worth r10k_simplify_address's while replacing
14917 an address with X. We are looking for constants, and for addresses
14918 at a known offset from the incoming stack pointer. */
14921 r10k_simplified_address_p (rtx x)
14923 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
14925 return x == virtual_incoming_args_rtx || CONSTANT_P (x);
14928 /* X is an expression that appears in INSN. Try to use the UD chains
14929 to simplify it, returning the simplified form on success and the
14930 original form otherwise. Replace the incoming value of $sp with
14931 virtual_incoming_args_rtx (which should never occur in X otherwise). */
14934 r10k_simplify_address (rtx x, rtx insn)
14936 rtx newx, op0, op1, set, def_insn, note;
14938 struct df_link *defs;
14943 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14944 if (op0 != XEXP (x, 0))
14945 newx = simplify_gen_unary (GET_CODE (x), GET_MODE (x),
14946 op0, GET_MODE (XEXP (x, 0)));
14948 else if (BINARY_P (x))
14950 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14951 op1 = r10k_simplify_address (XEXP (x, 1), insn);
14952 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
14953 newx = simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
14955 else if (GET_CODE (x) == LO_SUM)
14957 /* LO_SUMs can be offset from HIGHs, if we know they won't
14958 overflow. See mips_classify_address for the rationale behind
14960 op0 = r10k_simplify_address (XEXP (x, 0), insn);
14961 if (GET_CODE (op0) == HIGH)
14962 newx = XEXP (x, 1);
14964 else if (REG_P (x))
14966 /* Uses are recorded by regno_reg_rtx, not X itself. */
14967 use = df_find_use (insn, regno_reg_rtx[REGNO (x)]);
14969 defs = DF_REF_CHAIN (use);
14971 /* Require a single definition. */
14972 if (defs && defs->next == NULL)
14975 if (DF_REF_IS_ARTIFICIAL (def))
14977 /* Replace the incoming value of $sp with
14978 virtual_incoming_args_rtx. */
14979 if (x == stack_pointer_rtx
14980 && DF_REF_BB (def) == ENTRY_BLOCK_PTR_FOR_FN (cfun))
14981 newx = virtual_incoming_args_rtx;
14983 else if (dominated_by_p (CDI_DOMINATORS, DF_REF_BB (use),
14986 /* Make sure that DEF_INSN is a single set of REG. */
14987 def_insn = DF_REF_INSN (def);
14988 if (NONJUMP_INSN_P (def_insn))
14990 set = single_set (def_insn);
14991 if (set && rtx_equal_p (SET_DEST (set), x))
14993 /* Prefer to use notes, since the def-use chains
14994 are often shorter. */
14995 note = find_reg_equal_equiv_note (def_insn);
14997 newx = XEXP (note, 0);
14999 newx = SET_SRC (set);
15000 newx = r10k_simplify_address (newx, def_insn);
15006 if (newx && r10k_simplified_address_p (newx))
15011 /* Return true if ADDRESS is known to be an uncached address
15012 on R10K systems. */
15015 r10k_uncached_address_p (unsigned HOST_WIDE_INT address)
15017 unsigned HOST_WIDE_INT upper;
15019 /* Check for KSEG1. */
15020 if (address + 0x60000000 < 0x20000000)
15023 /* Check for uncached XKPHYS addresses. */
15024 if (Pmode == DImode)
15026 upper = (address >> 40) & 0xf9ffff;
15027 if (upper == 0x900000 || upper == 0xb80000)
15033 /* Return true if we can prove that an access to address X in instruction
15034 INSN would be safe from R10K speculation. This X is a general
15035 expression; it might not be a legitimate address. */
15038 r10k_safe_address_p (rtx x, rtx insn)
15041 HOST_WIDE_INT offset_val;
15043 x = r10k_simplify_address (x, insn);
15045 /* Check for references to the stack frame. It doesn't really matter
15046 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
15047 allows us to assume that accesses to any part of the eventual frame
15048 is safe from speculation at any point in the function. */
15049 mips_split_plus (x, &base, &offset_val);
15050 if (base == virtual_incoming_args_rtx
15051 && offset_val >= -cfun->machine->frame.total_size
15052 && offset_val < cfun->machine->frame.args_size)
15055 /* Check for uncached addresses. */
15056 if (CONST_INT_P (x))
15057 return r10k_uncached_address_p (INTVAL (x));
15059 /* Check for accesses to a static object. */
15060 split_const (x, &base, &offset);
15061 return offset_within_block_p (base, INTVAL (offset));
15064 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
15065 an in-range access to an automatic variable, or to an object with
15066 a link-time-constant address. */
15069 r10k_safe_mem_expr_p (tree expr, unsigned HOST_WIDE_INT offset)
15071 HOST_WIDE_INT bitoffset, bitsize;
15072 tree inner, var_offset;
15073 enum machine_mode mode;
15074 int unsigned_p, volatile_p;
15076 inner = get_inner_reference (expr, &bitsize, &bitoffset, &var_offset, &mode,
15077 &unsigned_p, &volatile_p, false);
15078 if (!DECL_P (inner) || !DECL_SIZE_UNIT (inner) || var_offset)
15081 offset += bitoffset / BITS_PER_UNIT;
15082 return offset < tree_to_uhwi (DECL_SIZE_UNIT (inner));
15085 /* A for_each_rtx callback for which DATA points to the instruction
15086 containing *X. Stop the search if we find a MEM that is not safe
15087 from R10K speculation. */
15090 r10k_needs_protection_p_1 (rtx *loc, void *data)
15099 && MEM_OFFSET_KNOWN_P (mem)
15100 && r10k_safe_mem_expr_p (MEM_EXPR (mem), MEM_OFFSET (mem)))
15103 if (r10k_safe_address_p (XEXP (mem, 0), (rtx) data))
15109 /* A note_stores callback for which DATA points to an instruction pointer.
15110 If *DATA is nonnull, make it null if it X contains a MEM that is not
15111 safe from R10K speculation. */
15114 r10k_needs_protection_p_store (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
15119 insn_ptr = (rtx *) data;
15120 if (*insn_ptr && for_each_rtx (&x, r10k_needs_protection_p_1, *insn_ptr))
15121 *insn_ptr = NULL_RTX;
15124 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
15125 Return nonzero if the call is not to a declared function. */
15128 r10k_needs_protection_p_call (rtx *loc, void *data ATTRIBUTE_UNUSED)
15137 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_DECL (x))
15143 /* Return true if instruction INSN needs to be protected by an R10K
15147 r10k_needs_protection_p (rtx insn)
15150 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_call, NULL);
15152 if (mips_r10k_cache_barrier == R10K_CACHE_BARRIER_STORE)
15154 note_stores (PATTERN (insn), r10k_needs_protection_p_store, &insn);
15155 return insn == NULL_RTX;
15158 return for_each_rtx (&PATTERN (insn), r10k_needs_protection_p_1, insn);
15161 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
15162 edge is unconditional. */
15165 r10k_protected_bb_p (basic_block bb, sbitmap protected_bbs)
15170 FOR_EACH_EDGE (e, ei, bb->preds)
15171 if (!single_succ_p (e->src)
15172 || !bitmap_bit_p (protected_bbs, e->src->index)
15173 || (e->flags & EDGE_COMPLEX) != 0)
15178 /* Implement -mr10k-cache-barrier= for the current function. */
15181 r10k_insert_cache_barriers (void)
15183 int *rev_post_order;
15186 sbitmap protected_bbs;
15187 rtx insn, end, unprotected_region;
15191 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
15195 /* Calculate dominators. */
15196 calculate_dominance_info (CDI_DOMINATORS);
15198 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
15199 X is protected by a cache barrier. */
15200 protected_bbs = sbitmap_alloc (last_basic_block_for_fn (cfun));
15201 bitmap_clear (protected_bbs);
15203 /* Iterate over the basic blocks in reverse post-order. */
15204 rev_post_order = XNEWVEC (int, last_basic_block_for_fn (cfun));
15205 n = pre_and_rev_post_order_compute (NULL, rev_post_order, false);
15206 for (i = 0; i < n; i++)
15208 bb = BASIC_BLOCK_FOR_FN (cfun, rev_post_order[i]);
15210 /* If this block is only reached by unconditional edges, and if the
15211 source of every edge is protected, the beginning of the block is
15213 if (r10k_protected_bb_p (bb, protected_bbs))
15214 unprotected_region = NULL_RTX;
15216 unprotected_region = pc_rtx;
15217 end = NEXT_INSN (BB_END (bb));
15219 /* UNPROTECTED_REGION is:
15221 - null if we are processing a protected region,
15222 - pc_rtx if we are processing an unprotected region but have
15223 not yet found the first instruction in it
15224 - the first instruction in an unprotected region otherwise. */
15225 for (insn = BB_HEAD (bb); insn != end; insn = NEXT_INSN (insn))
15227 if (unprotected_region && USEFUL_INSN_P (insn))
15229 if (recog_memoized (insn) == CODE_FOR_mips_cache)
15230 /* This CACHE instruction protects the following code. */
15231 unprotected_region = NULL_RTX;
15234 /* See if INSN is the first instruction in this
15235 unprotected region. */
15236 if (unprotected_region == pc_rtx)
15237 unprotected_region = insn;
15239 /* See if INSN needs to be protected. If so,
15240 we must insert a cache barrier somewhere between
15241 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
15242 clear which position is better performance-wise,
15243 but as a tie-breaker, we assume that it is better
15244 to allow delay slots to be back-filled where
15245 possible, and that it is better not to insert
15246 barriers in the middle of already-scheduled code.
15247 We therefore insert the barrier at the beginning
15249 if (r10k_needs_protection_p (insn))
15251 emit_insn_before (gen_r10k_cache_barrier (),
15252 unprotected_region);
15253 unprotected_region = NULL_RTX;
15259 /* The called function is not required to protect the exit path.
15260 The code that follows a call is therefore unprotected. */
15261 unprotected_region = pc_rtx;
15264 /* Record whether the end of this block is protected. */
15265 if (unprotected_region == NULL_RTX)
15266 bitmap_set_bit (protected_bbs, bb->index);
15268 XDELETEVEC (rev_post_order);
15270 sbitmap_free (protected_bbs);
15272 free_dominance_info (CDI_DOMINATORS);
15275 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
15276 otherwise. If INSN has two call rtx, then store the second one in
15280 mips_call_expr_from_insn (rtx insn, rtx *second_call)
15285 if (!CALL_P (insn))
15288 x = PATTERN (insn);
15289 if (GET_CODE (x) == PARALLEL)
15291 /* Calls returning complex values have two CALL rtx. Look for the second
15292 one here, and return it via the SECOND_CALL arg. */
15293 x2 = XVECEXP (x, 0, 1);
15294 if (GET_CODE (x2) == SET)
15296 if (GET_CODE (x2) == CALL)
15299 x = XVECEXP (x, 0, 0);
15301 if (GET_CODE (x) == SET)
15303 gcc_assert (GET_CODE (x) == CALL);
15308 /* REG is set in DEF. See if the definition is one of the ways we load a
15309 register with a symbol address for a mips_use_pic_fn_addr_reg_p call.
15310 If it is, return the symbol reference of the function, otherwise return
15313 If RECURSE_P is true, use mips_find_pic_call_symbol to interpret
15314 the values of source registers, otherwise treat such registers as
15315 having an unknown value. */
15318 mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
15322 if (DF_REF_IS_ARTIFICIAL (def))
15325 def_insn = DF_REF_INSN (def);
15326 set = single_set (def_insn);
15327 if (set && rtx_equal_p (SET_DEST (set), reg))
15329 rtx note, src, symbol;
15331 /* First see whether the source is a plain symbol. This is used
15332 when calling symbols that are not lazily bound. */
15333 src = SET_SRC (set);
15334 if (GET_CODE (src) == SYMBOL_REF)
15337 /* Handle %call16 references. */
15338 symbol = mips_strip_unspec_call (src);
15341 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15345 /* If we have something more complicated, look for a
15346 REG_EQUAL or REG_EQUIV note. */
15347 note = find_reg_equal_equiv_note (def_insn);
15348 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
15349 return XEXP (note, 0);
15351 /* Follow at most one simple register copy. Such copies are
15352 interesting in cases like:
15356 locally_binding_fn (...);
15361 locally_binding_fn (...);
15363 locally_binding_fn (...);
15365 where the load of locally_binding_fn can legitimately be
15366 hoisted or shared. However, we do not expect to see complex
15367 chains of copies, so a full worklist solution to the problem
15368 would probably be overkill. */
15369 if (recurse_p && REG_P (src))
15370 return mips_find_pic_call_symbol (def_insn, src, false);
15376 /* Find the definition of the use of REG in INSN. See if the definition
15377 is one of the ways we load a register with a symbol address for a
15378 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference
15379 of the function, otherwise return NULL_RTX. RECURSE_P is as for
15380 mips_pic_call_symbol_from_set. */
15383 mips_find_pic_call_symbol (rtx insn, rtx reg, bool recurse_p)
15386 struct df_link *defs;
15389 use = df_find_use (insn, regno_reg_rtx[REGNO (reg)]);
15392 defs = DF_REF_CHAIN (use);
15395 symbol = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15399 /* If we have more than one definition, they need to be identical. */
15400 for (defs = defs->next; defs; defs = defs->next)
15404 other = mips_pic_call_symbol_from_set (defs->ref, reg, recurse_p);
15405 if (!rtx_equal_p (symbol, other))
15412 /* Replace the args_size operand of the call expression CALL with the
15413 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
15416 mips_annotate_pic_call_expr (rtx call, rtx symbol)
15420 args_size = XEXP (call, 1);
15421 XEXP (call, 1) = gen_rtx_UNSPEC (GET_MODE (args_size),
15422 gen_rtvec (2, args_size, symbol),
15426 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
15427 if instead of the arg_size argument it contains the call attributes. If
15428 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
15429 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
15433 mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
15435 rtx args_size, symbol;
15437 if (!TARGET_RELAX_PIC_CALLS || args_size_opno == -1)
15440 args_size = operands[args_size_opno];
15441 if (GET_CODE (args_size) != UNSPEC)
15443 gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
15445 symbol = XVECEXP (args_size, 0, 1);
15446 gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
15448 operands[args_size_opno] = symbol;
15452 /* Use DF to annotate PIC indirect calls with the function symbol they
15456 mips_annotate_pic_calls (void)
15461 FOR_EACH_BB_FN (bb, cfun)
15462 FOR_BB_INSNS (bb, insn)
15464 rtx call, reg, symbol, second_call;
15467 call = mips_call_expr_from_insn (insn, &second_call);
15470 gcc_assert (MEM_P (XEXP (call, 0)));
15471 reg = XEXP (XEXP (call, 0), 0);
15475 symbol = mips_find_pic_call_symbol (insn, reg, true);
15478 mips_annotate_pic_call_expr (call, symbol);
15480 mips_annotate_pic_call_expr (second_call, symbol);
15485 /* A temporary variable used by for_each_rtx callbacks, etc. */
15486 static rtx mips_sim_insn;
15488 /* A structure representing the state of the processor pipeline.
15489 Used by the mips_sim_* family of functions. */
15491 /* The maximum number of instructions that can be issued in a cycle.
15492 (Caches mips_issue_rate.) */
15493 unsigned int issue_rate;
15495 /* The current simulation time. */
15498 /* How many more instructions can be issued in the current cycle. */
15499 unsigned int insns_left;
15501 /* LAST_SET[X].INSN is the last instruction to set register X.
15502 LAST_SET[X].TIME is the time at which that instruction was issued.
15503 INSN is null if no instruction has yet set register X. */
15507 } last_set[FIRST_PSEUDO_REGISTER];
15509 /* The pipeline's current DFA state. */
15513 /* Reset STATE to the initial simulation state. */
15516 mips_sim_reset (struct mips_sim *state)
15518 curr_state = state->dfa_state;
15521 state->insns_left = state->issue_rate;
15522 memset (&state->last_set, 0, sizeof (state->last_set));
15523 state_reset (curr_state);
15525 targetm.sched.init (0, false, 0);
15526 advance_state (curr_state);
15529 /* Initialize STATE before its first use. DFA_STATE points to an
15530 allocated but uninitialized DFA state. */
15533 mips_sim_init (struct mips_sim *state, state_t dfa_state)
15535 if (targetm.sched.init_dfa_pre_cycle_insn)
15536 targetm.sched.init_dfa_pre_cycle_insn ();
15538 if (targetm.sched.init_dfa_post_cycle_insn)
15539 targetm.sched.init_dfa_post_cycle_insn ();
15541 state->issue_rate = mips_issue_rate ();
15542 state->dfa_state = dfa_state;
15543 mips_sim_reset (state);
15546 /* Advance STATE by one clock cycle. */
15549 mips_sim_next_cycle (struct mips_sim *state)
15551 curr_state = state->dfa_state;
15554 state->insns_left = state->issue_rate;
15555 advance_state (curr_state);
15558 /* Advance simulation state STATE until instruction INSN can read
15562 mips_sim_wait_reg (struct mips_sim *state, rtx insn, rtx reg)
15564 unsigned int regno, end_regno;
15566 end_regno = END_REGNO (reg);
15567 for (regno = REGNO (reg); regno < end_regno; regno++)
15568 if (state->last_set[regno].insn != 0)
15572 t = (state->last_set[regno].time
15573 + insn_latency (state->last_set[regno].insn, insn));
15574 while (state->time < t)
15575 mips_sim_next_cycle (state);
15579 /* A for_each_rtx callback. If *X is a register, advance simulation state
15580 DATA until mips_sim_insn can read the register's value. */
15583 mips_sim_wait_regs_2 (rtx *x, void *data)
15586 mips_sim_wait_reg ((struct mips_sim *) data, mips_sim_insn, *x);
15590 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
15593 mips_sim_wait_regs_1 (rtx *x, void *data)
15595 for_each_rtx (x, mips_sim_wait_regs_2, data);
15598 /* Advance simulation state STATE until all of INSN's register
15599 dependencies are satisfied. */
15602 mips_sim_wait_regs (struct mips_sim *state, rtx insn)
15604 mips_sim_insn = insn;
15605 note_uses (&PATTERN (insn), mips_sim_wait_regs_1, state);
15608 /* Advance simulation state STATE until the units required by
15609 instruction INSN are available. */
15612 mips_sim_wait_units (struct mips_sim *state, rtx insn)
15616 tmp_state = alloca (state_size ());
15617 while (state->insns_left == 0
15618 || (memcpy (tmp_state, state->dfa_state, state_size ()),
15619 state_transition (tmp_state, insn) >= 0))
15620 mips_sim_next_cycle (state);
15623 /* Advance simulation state STATE until INSN is ready to issue. */
15626 mips_sim_wait_insn (struct mips_sim *state, rtx insn)
15628 mips_sim_wait_regs (state, insn);
15629 mips_sim_wait_units (state, insn);
15632 /* mips_sim_insn has just set X. Update the LAST_SET array
15633 in simulation state DATA. */
15636 mips_sim_record_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
15638 struct mips_sim *state;
15640 state = (struct mips_sim *) data;
15643 unsigned int regno, end_regno;
15645 end_regno = END_REGNO (x);
15646 for (regno = REGNO (x); regno < end_regno; regno++)
15648 state->last_set[regno].insn = mips_sim_insn;
15649 state->last_set[regno].time = state->time;
15654 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
15655 can issue immediately (i.e., that mips_sim_wait_insn has already
15659 mips_sim_issue_insn (struct mips_sim *state, rtx insn)
15661 curr_state = state->dfa_state;
15663 state_transition (curr_state, insn);
15664 state->insns_left = targetm.sched.variable_issue (0, false, insn,
15665 state->insns_left);
15667 mips_sim_insn = insn;
15668 note_stores (PATTERN (insn), mips_sim_record_set, state);
15671 /* Simulate issuing a NOP in state STATE. */
15674 mips_sim_issue_nop (struct mips_sim *state)
15676 if (state->insns_left == 0)
15677 mips_sim_next_cycle (state);
15678 state->insns_left--;
15681 /* Update simulation state STATE so that it's ready to accept the instruction
15682 after INSN. INSN should be part of the main rtl chain, not a member of a
15686 mips_sim_finish_insn (struct mips_sim *state, rtx insn)
15688 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
15690 mips_sim_issue_nop (state);
15692 switch (GET_CODE (SEQ_BEGIN (insn)))
15696 /* We can't predict the processor state after a call or label. */
15697 mips_sim_reset (state);
15701 /* The delay slots of branch likely instructions are only executed
15702 when the branch is taken. Therefore, if the caller has simulated
15703 the delay slot instruction, STATE does not really reflect the state
15704 of the pipeline for the instruction after the delay slot. Also,
15705 branch likely instructions tend to incur a penalty when not taken,
15706 so there will probably be an extra delay between the branch and
15707 the instruction after the delay slot. */
15708 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn)))
15709 mips_sim_reset (state);
15717 /* Use simulator state STATE to calculate the execution time of
15718 instruction sequence SEQ. */
15720 static unsigned int
15721 mips_seq_time (struct mips_sim *state, rtx seq)
15723 mips_sim_reset (state);
15724 for (rtx insn = seq; insn; insn = NEXT_INSN (insn))
15726 mips_sim_wait_insn (state, insn);
15727 mips_sim_issue_insn (state, insn);
15729 return state->time;
15732 /* Return the execution-time cost of mips_tuning_info.fast_mult_zero_zero_p
15733 setting SETTING, using STATE to simulate instruction sequences. */
15735 static unsigned int
15736 mips_mult_zero_zero_cost (struct mips_sim *state, bool setting)
15738 mips_tuning_info.fast_mult_zero_zero_p = setting;
15741 enum machine_mode dword_mode = TARGET_64BIT ? TImode : DImode;
15742 rtx hilo = gen_rtx_REG (dword_mode, MD_REG_FIRST);
15743 mips_emit_move_or_split (hilo, const0_rtx, SPLIT_FOR_SPEED);
15745 /* If the target provides mulsidi3_32bit then that's the most likely
15746 consumer of the result. Test for bypasses. */
15747 if (dword_mode == DImode && HAVE_maddsidi4)
15749 rtx gpr = gen_rtx_REG (SImode, GP_REG_FIRST + 4);
15750 emit_insn (gen_maddsidi4 (hilo, gpr, gpr, hilo));
15753 unsigned int time = mips_seq_time (state, get_insns ());
15758 /* Check the relative speeds of "MULT $0,$0" and "MTLO $0; MTHI $0"
15759 and set up mips_tuning_info.fast_mult_zero_zero_p accordingly.
15760 Prefer MULT -- which is shorter -- in the event of a tie. */
15763 mips_set_fast_mult_zero_zero_p (struct mips_sim *state)
15766 /* No MTLO or MTHI available. */
15767 mips_tuning_info.fast_mult_zero_zero_p = true;
15770 unsigned int true_time = mips_mult_zero_zero_cost (state, true);
15771 unsigned int false_time = mips_mult_zero_zero_cost (state, false);
15772 mips_tuning_info.fast_mult_zero_zero_p = (true_time <= false_time);
15776 /* Set up costs based on the current architecture and tuning settings. */
15779 mips_set_tuning_info (void)
15781 if (mips_tuning_info.initialized_p
15782 && mips_tuning_info.arch == mips_arch
15783 && mips_tuning_info.tune == mips_tune
15784 && mips_tuning_info.mips16_p == TARGET_MIPS16)
15787 mips_tuning_info.arch = mips_arch;
15788 mips_tuning_info.tune = mips_tune;
15789 mips_tuning_info.mips16_p = TARGET_MIPS16;
15790 mips_tuning_info.initialized_p = true;
15794 struct mips_sim state;
15795 mips_sim_init (&state, alloca (state_size ()));
15797 mips_set_fast_mult_zero_zero_p (&state);
15802 /* Implement TARGET_EXPAND_TO_RTL_HOOK. */
15805 mips_expand_to_rtl_hook (void)
15807 /* We need to call this at a point where we can safely create sequences
15808 of instructions, so TARGET_OVERRIDE_OPTIONS is too early. We also
15809 need to call it at a point where the DFA infrastructure is not
15810 already in use, so we can't just call it lazily on demand.
15812 At present, mips_tuning_info is only needed during post-expand
15813 RTL passes such as split_insns, so this hook should be early enough.
15814 We may need to move the call elsewhere if mips_tuning_info starts
15815 to be used for other things (such as rtx_costs, or expanders that
15816 could be called during gimple optimization). */
15817 mips_set_tuning_info ();
15820 /* The VR4130 pipeline issues aligned pairs of instructions together,
15821 but it stalls the second instruction if it depends on the first.
15822 In order to cut down the amount of logic required, this dependence
15823 check is not based on a full instruction decode. Instead, any non-SPECIAL
15824 instruction is assumed to modify the register specified by bits 20-16
15825 (which is usually the "rt" field).
15827 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
15828 input, so we can end up with a false dependence between the branch
15829 and its delay slot. If this situation occurs in instruction INSN,
15830 try to avoid it by swapping rs and rt. */
15833 vr4130_avoid_branch_rt_conflict (rtx insn)
15837 first = SEQ_BEGIN (insn);
15838 second = SEQ_END (insn);
15840 && NONJUMP_INSN_P (second)
15841 && GET_CODE (PATTERN (first)) == SET
15842 && GET_CODE (SET_DEST (PATTERN (first))) == PC
15843 && GET_CODE (SET_SRC (PATTERN (first))) == IF_THEN_ELSE)
15845 /* Check for the right kind of condition. */
15846 rtx cond = XEXP (SET_SRC (PATTERN (first)), 0);
15847 if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
15848 && REG_P (XEXP (cond, 0))
15849 && REG_P (XEXP (cond, 1))
15850 && reg_referenced_p (XEXP (cond, 1), PATTERN (second))
15851 && !reg_referenced_p (XEXP (cond, 0), PATTERN (second)))
15853 /* SECOND mentions the rt register but not the rs register. */
15854 rtx tmp = XEXP (cond, 0);
15855 XEXP (cond, 0) = XEXP (cond, 1);
15856 XEXP (cond, 1) = tmp;
15861 /* Implement -mvr4130-align. Go through each basic block and simulate the
15862 processor pipeline. If we find that a pair of instructions could execute
15863 in parallel, and the first of those instructions is not 8-byte aligned,
15864 insert a nop to make it aligned. */
15867 vr4130_align_insns (void)
15869 struct mips_sim state;
15870 rtx insn, subinsn, last, last2, next;
15875 /* LAST is the last instruction before INSN to have a nonzero length.
15876 LAST2 is the last such instruction before LAST. */
15880 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
15883 mips_sim_init (&state, alloca (state_size ()));
15884 for (insn = get_insns (); insn != 0; insn = next)
15886 unsigned int length;
15888 next = NEXT_INSN (insn);
15890 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
15891 This isn't really related to the alignment pass, but we do it on
15892 the fly to avoid a separate instruction walk. */
15893 vr4130_avoid_branch_rt_conflict (insn);
15895 length = get_attr_length (insn);
15896 if (length > 0 && USEFUL_INSN_P (insn))
15897 FOR_EACH_SUBINSN (subinsn, insn)
15899 mips_sim_wait_insn (&state, subinsn);
15901 /* If we want this instruction to issue in parallel with the
15902 previous one, make sure that the previous instruction is
15903 aligned. There are several reasons why this isn't worthwhile
15904 when the second instruction is a call:
15906 - Calls are less likely to be performance critical,
15907 - There's a good chance that the delay slot can execute
15908 in parallel with the call.
15909 - The return address would then be unaligned.
15911 In general, if we're going to insert a nop between instructions
15912 X and Y, it's better to insert it immediately after X. That
15913 way, if the nop makes Y aligned, it will also align any labels
15914 between X and Y. */
15915 if (state.insns_left != state.issue_rate
15916 && !CALL_P (subinsn))
15918 if (subinsn == SEQ_BEGIN (insn) && aligned_p)
15920 /* SUBINSN is the first instruction in INSN and INSN is
15921 aligned. We want to align the previous instruction
15922 instead, so insert a nop between LAST2 and LAST.
15924 Note that LAST could be either a single instruction
15925 or a branch with a delay slot. In the latter case,
15926 LAST, like INSN, is already aligned, but the delay
15927 slot must have some extra delay that stops it from
15928 issuing at the same time as the branch. We therefore
15929 insert a nop before the branch in order to align its
15931 gcc_assert (last2);
15932 emit_insn_after (gen_nop (), last2);
15935 else if (subinsn != SEQ_BEGIN (insn) && !aligned_p)
15937 /* SUBINSN is the delay slot of INSN, but INSN is
15938 currently unaligned. Insert a nop between
15939 LAST and INSN to align it. */
15941 emit_insn_after (gen_nop (), last);
15945 mips_sim_issue_insn (&state, subinsn);
15947 mips_sim_finish_insn (&state, insn);
15949 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
15950 length = get_attr_length (insn);
15953 /* If the instruction is an asm statement or multi-instruction
15954 mips.md patern, the length is only an estimate. Insert an
15955 8 byte alignment after it so that the following instructions
15956 can be handled correctly. */
15957 if (NONJUMP_INSN_P (SEQ_BEGIN (insn))
15958 && (recog_memoized (insn) < 0 || length >= 8))
15960 next = emit_insn_after (gen_align (GEN_INT (3)), insn);
15961 next = NEXT_INSN (next);
15962 mips_sim_next_cycle (&state);
15965 else if (length & 4)
15966 aligned_p = !aligned_p;
15971 /* See whether INSN is an aligned label. */
15972 if (LABEL_P (insn) && label_to_alignment (insn) >= 3)
15978 /* This structure records that the current function has a LO_SUM
15979 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
15980 the largest offset applied to BASE by all such LO_SUMs. */
15981 struct mips_lo_sum_offset {
15983 HOST_WIDE_INT offset;
15986 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
15989 mips_hash_base (rtx base)
15991 int do_not_record_p;
15993 return hash_rtx (base, GET_MODE (base), &do_not_record_p, NULL, false);
15996 /* Hashtable helpers. */
15998 struct mips_lo_sum_offset_hasher : typed_free_remove <mips_lo_sum_offset>
16000 typedef mips_lo_sum_offset value_type;
16001 typedef rtx_def compare_type;
16002 static inline hashval_t hash (const value_type *);
16003 static inline bool equal (const value_type *, const compare_type *);
16006 /* Hash-table callbacks for mips_lo_sum_offsets. */
16009 mips_lo_sum_offset_hasher::hash (const value_type *entry)
16011 return mips_hash_base (entry->base);
16015 mips_lo_sum_offset_hasher::equal (const value_type *entry,
16016 const compare_type *value)
16018 return rtx_equal_p (entry->base, value);
16021 typedef hash_table<mips_lo_sum_offset_hasher> mips_offset_table;
16023 /* Look up symbolic constant X in HTAB, which is a hash table of
16024 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
16025 paired with a recorded LO_SUM, otherwise record X in the table. */
16028 mips_lo_sum_offset_lookup (mips_offset_table *htab, rtx x,
16029 enum insert_option option)
16032 mips_lo_sum_offset **slot;
16033 struct mips_lo_sum_offset *entry;
16035 /* Split X into a base and offset. */
16036 split_const (x, &base, &offset);
16037 if (UNSPEC_ADDRESS_P (base))
16038 base = UNSPEC_ADDRESS (base);
16040 /* Look up the base in the hash table. */
16041 slot = htab->find_slot_with_hash (base, mips_hash_base (base), option);
16045 entry = (struct mips_lo_sum_offset *) *slot;
16046 if (option == INSERT)
16050 entry = XNEW (struct mips_lo_sum_offset);
16051 entry->base = base;
16052 entry->offset = INTVAL (offset);
16057 if (INTVAL (offset) > entry->offset)
16058 entry->offset = INTVAL (offset);
16061 return INTVAL (offset) <= entry->offset;
16064 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
16065 Record every LO_SUM in *LOC. */
16068 mips_record_lo_sum (rtx *loc, void *data)
16070 if (GET_CODE (*loc) == LO_SUM)
16071 mips_lo_sum_offset_lookup ((mips_offset_table*) data,
16072 XEXP (*loc, 1), INSERT);
16076 /* Return true if INSN is a SET of an orphaned high-part relocation.
16077 HTAB is a hash table of mips_lo_sum_offsets that describes all the
16078 LO_SUMs in the current function. */
16081 mips_orphaned_high_part_p (mips_offset_table *htab, rtx insn)
16083 enum mips_symbol_type type;
16086 set = single_set (insn);
16089 /* Check for %his. */
16091 if (GET_CODE (x) == HIGH
16092 && absolute_symbolic_operand (XEXP (x, 0), VOIDmode))
16093 return !mips_lo_sum_offset_lookup (htab, XEXP (x, 0), NO_INSERT);
16095 /* Check for local %gots (and %got_pages, which is redundant but OK). */
16096 if (GET_CODE (x) == UNSPEC
16097 && XINT (x, 1) == UNSPEC_LOAD_GOT
16098 && mips_symbolic_constant_p (XVECEXP (x, 0, 1),
16099 SYMBOL_CONTEXT_LEA, &type)
16100 && type == SYMBOL_GOTOFF_PAGE)
16101 return !mips_lo_sum_offset_lookup (htab, XVECEXP (x, 0, 1), NO_INSERT);
16106 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
16107 INSN and a previous instruction, avoid it by inserting nops after
16110 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
16111 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
16112 before using the value of that register. *HILO_DELAY counts the
16113 number of instructions since the last hilo hazard (that is,
16114 the number of instructions since the last MFLO or MFHI).
16116 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
16117 for the next instruction.
16119 LO_REG is an rtx for the LO register, used in dependence checking. */
16122 mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
16123 rtx *delayed_reg, rtx lo_reg)
16128 pattern = PATTERN (insn);
16130 /* Do not put the whole function in .set noreorder if it contains
16131 an asm statement. We don't know whether there will be hazards
16132 between the asm statement and the gcc-generated code. */
16133 if (GET_CODE (pattern) == ASM_INPUT || asm_noperands (pattern) >= 0)
16134 cfun->machine->all_noreorder_p = false;
16136 /* Ignore zero-length instructions (barriers and the like). */
16137 ninsns = get_attr_length (insn) / 4;
16141 /* Work out how many nops are needed. Note that we only care about
16142 registers that are explicitly mentioned in the instruction's pattern.
16143 It doesn't matter that calls use the argument registers or that they
16144 clobber hi and lo. */
16145 if (*hilo_delay < 2 && reg_set_p (lo_reg, pattern))
16146 nops = 2 - *hilo_delay;
16147 else if (*delayed_reg != 0 && reg_referenced_p (*delayed_reg, pattern))
16152 /* Insert the nops between this instruction and the previous one.
16153 Each new nop takes us further from the last hilo hazard. */
16154 *hilo_delay += nops;
16156 emit_insn_after (gen_hazard_nop (), after);
16158 /* Set up the state for the next instruction. */
16159 *hilo_delay += ninsns;
16161 if (INSN_CODE (insn) >= 0)
16162 switch (get_attr_hazard (insn))
16172 set = single_set (insn);
16174 *delayed_reg = SET_DEST (set);
16179 /* Go through the instruction stream and insert nops where necessary.
16180 Also delete any high-part relocations whose partnering low parts
16181 are now all dead. See if the whole function can then be put into
16182 .set noreorder and .set nomacro. */
16185 mips_reorg_process_insns (void)
16187 rtx insn, last_insn, subinsn, next_insn, lo_reg, delayed_reg;
16190 /* Force all instructions to be split into their final form. */
16191 split_all_insns_noflow ();
16193 /* Recalculate instruction lengths without taking nops into account. */
16194 cfun->machine->ignore_hazard_length_p = true;
16195 shorten_branches (get_insns ());
16197 cfun->machine->all_noreorder_p = true;
16199 /* We don't track MIPS16 PC-relative offsets closely enough to make
16200 a good job of "set .noreorder" code in MIPS16 mode. */
16202 cfun->machine->all_noreorder_p = false;
16204 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
16205 if (!TARGET_EXPLICIT_RELOCS)
16206 cfun->machine->all_noreorder_p = false;
16208 /* Profiled functions can't be all noreorder because the profiler
16209 support uses assembler macros. */
16211 cfun->machine->all_noreorder_p = false;
16213 /* Code compiled with -mfix-vr4120, -mfix-rm7000 or -mfix-24k can't be
16214 all noreorder because we rely on the assembler to work around some
16215 errata. The R5900 too has several bugs. */
16216 if (TARGET_FIX_VR4120
16217 || TARGET_FIX_RM7000
16219 || TARGET_MIPS5900)
16220 cfun->machine->all_noreorder_p = false;
16222 /* The same is true for -mfix-vr4130 if we might generate MFLO or
16223 MFHI instructions. Note that we avoid using MFLO and MFHI if
16224 the VR4130 MACC and DMACC instructions are available instead;
16225 see the *mfhilo_{si,di}_macc patterns. */
16226 if (TARGET_FIX_VR4130 && !ISA_HAS_MACCHI)
16227 cfun->machine->all_noreorder_p = false;
16229 mips_offset_table htab (37);
16231 /* Make a first pass over the instructions, recording all the LO_SUMs. */
16232 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16233 FOR_EACH_SUBINSN (subinsn, insn)
16234 if (USEFUL_INSN_P (subinsn))
16236 rtx body = PATTERN (insn);
16237 int noperands = asm_noperands (body);
16238 if (noperands >= 0)
16240 rtx *ops = XALLOCAVEC (rtx, noperands);
16241 bool *used = XALLOCAVEC (bool, noperands);
16242 const char *string = decode_asm_operands (body, ops, NULL, NULL,
16244 get_referenced_operands (string, used, noperands);
16245 for (int i = 0; i < noperands; ++i)
16247 for_each_rtx (&ops[i], mips_record_lo_sum, &htab);
16250 for_each_rtx (&PATTERN (subinsn), mips_record_lo_sum, &htab);
16256 lo_reg = gen_rtx_REG (SImode, LO_REGNUM);
16258 /* Make a second pass over the instructions. Delete orphaned
16259 high-part relocations or turn them into NOPs. Avoid hazards
16260 by inserting NOPs. */
16261 for (insn = get_insns (); insn != 0; insn = next_insn)
16263 next_insn = NEXT_INSN (insn);
16264 if (USEFUL_INSN_P (insn))
16266 if (GET_CODE (PATTERN (insn)) == SEQUENCE)
16268 /* If we find an orphaned high-part relocation in a delay
16269 slot, it's easier to turn that instruction into a NOP than
16270 to delete it. The delay slot will be a NOP either way. */
16271 FOR_EACH_SUBINSN (subinsn, insn)
16272 if (INSN_P (subinsn))
16274 if (mips_orphaned_high_part_p (&htab, subinsn))
16276 PATTERN (subinsn) = gen_nop ();
16277 INSN_CODE (subinsn) = CODE_FOR_nop;
16279 mips_avoid_hazard (last_insn, subinsn, &hilo_delay,
16280 &delayed_reg, lo_reg);
16286 /* INSN is a single instruction. Delete it if it's an
16287 orphaned high-part relocation. */
16288 if (mips_orphaned_high_part_p (&htab, insn))
16289 delete_insn (insn);
16290 /* Also delete cache barriers if the last instruction
16291 was an annulled branch. INSN will not be speculatively
16293 else if (recog_memoized (insn) == CODE_FOR_r10k_cache_barrier
16295 && JUMP_P (SEQ_BEGIN (last_insn))
16296 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn)))
16297 delete_insn (insn);
16300 mips_avoid_hazard (last_insn, insn, &hilo_delay,
16301 &delayed_reg, lo_reg);
16309 /* Return true if the function has a long branch instruction. */
16312 mips_has_long_branch_p (void)
16317 /* We need up-to-date instruction lengths. */
16318 shorten_branches (get_insns ());
16320 /* Look for a branch that is longer than normal. The normal length for
16321 non-MIPS16 branches is 8, because the length includes the delay slot.
16322 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
16323 but they have no delay slot. */
16324 normal_length = (TARGET_MIPS16 ? 4 : 8);
16325 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16326 FOR_EACH_SUBINSN (subinsn, insn)
16327 if (JUMP_P (subinsn)
16328 && get_attr_length (subinsn) > normal_length
16329 && (any_condjump_p (subinsn) || any_uncondjump_p (subinsn)))
16335 /* If we are using a GOT, but have not decided to use a global pointer yet,
16336 see whether we need one to implement long branches. Convert the ghost
16337 global-pointer instructions into real ones if so. */
16340 mips_expand_ghost_gp_insns (void)
16342 /* Quick exit if we already know that we will or won't need a
16344 if (!TARGET_USE_GOT
16345 || cfun->machine->global_pointer == INVALID_REGNUM
16346 || mips_must_initialize_gp_p ())
16349 /* Run a full check for long branches. */
16350 if (!mips_has_long_branch_p ())
16353 /* We've now established that we need $gp. */
16354 cfun->machine->must_initialize_gp_p = true;
16355 split_all_insns_noflow ();
16360 /* Subroutine of mips_reorg to manage passes that require DF. */
16363 mips_df_reorg (void)
16365 /* Create def-use chains. */
16366 df_set_flags (DF_EQ_NOTES);
16367 df_chain_add_problem (DF_UD_CHAIN);
16370 if (TARGET_RELAX_PIC_CALLS)
16371 mips_annotate_pic_calls ();
16373 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE)
16374 r10k_insert_cache_barriers ();
16376 df_finish_pass (false);
16379 /* Emit code to load LABEL_REF SRC into MIPS16 register DEST. This is
16380 called very late in mips_reorg, but the caller is required to run
16381 mips16_lay_out_constants on the result. */
16384 mips16_load_branch_target (rtx dest, rtx src)
16386 if (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
16390 if (mips_cfun_has_cprestore_slot_p ())
16391 mips_emit_move (dest, mips_cprestore_slot (dest, true));
16393 mips_emit_move (dest, pic_offset_table_rtx);
16394 page = mips_unspec_address (src, SYMBOL_GOTOFF_PAGE);
16395 low = mips_unspec_address (src, SYMBOL_GOT_PAGE_OFST);
16396 emit_insn (gen_rtx_SET (VOIDmode, dest,
16397 PMODE_INSN (gen_unspec_got, (dest, page))));
16398 emit_insn (gen_rtx_SET (VOIDmode, dest,
16399 gen_rtx_LO_SUM (Pmode, dest, low)));
16403 src = mips_unspec_address (src, SYMBOL_ABSOLUTE);
16404 mips_emit_move (dest, src);
16408 /* If we're compiling a MIPS16 function, look for and split any long branches.
16409 This must be called after all other instruction modifications in
16413 mips16_split_long_branches (void)
16415 bool something_changed;
16417 if (!TARGET_MIPS16)
16420 /* Loop until the alignments for all targets are sufficient. */
16425 shorten_branches (get_insns ());
16426 something_changed = false;
16427 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
16429 && get_attr_length (insn) > 4
16430 && (any_condjump_p (insn) || any_uncondjump_p (insn)))
16432 rtx old_label, new_label, temp, saved_temp;
16433 rtx target, jump, jump_sequence;
16437 /* Free up a MIPS16 register by saving it in $1. */
16438 saved_temp = gen_rtx_REG (Pmode, AT_REGNUM);
16439 temp = gen_rtx_REG (Pmode, GP_REG_FIRST + 2);
16440 emit_move_insn (saved_temp, temp);
16442 /* Load the branch target into TEMP. */
16443 old_label = JUMP_LABEL (insn);
16444 target = gen_rtx_LABEL_REF (Pmode, old_label);
16445 mips16_load_branch_target (temp, target);
16447 /* Jump to the target and restore the register's
16449 jump = emit_jump_insn (PMODE_INSN (gen_indirect_jump_and_restore,
16450 (temp, temp, saved_temp)));
16451 JUMP_LABEL (jump) = old_label;
16452 LABEL_NUSES (old_label)++;
16454 /* Rewrite any symbolic references that are supposed to use
16455 a PC-relative constant pool. */
16456 mips16_lay_out_constants (false);
16458 if (simplejump_p (insn))
16459 /* We're going to replace INSN with a longer form. */
16460 new_label = NULL_RTX;
16463 /* Create a branch-around label for the original
16465 new_label = gen_label_rtx ();
16466 emit_label (new_label);
16469 jump_sequence = get_insns ();
16472 emit_insn_after (jump_sequence, insn);
16474 invert_jump (insn, new_label, false);
16476 delete_insn (insn);
16477 something_changed = true;
16480 while (something_changed);
16483 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
16488 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
16489 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
16490 to date if the CFG is available. */
16491 if (mips_cfg_in_reorg ())
16492 compute_bb_for_insn ();
16493 mips16_lay_out_constants (true);
16494 if (mips_cfg_in_reorg ())
16497 free_bb_for_insn ();
16501 /* We use a machine specific pass to do a second machine dependent reorg
16502 pass after delay branch scheduling. */
16504 static unsigned int
16505 mips_machine_reorg2 (void)
16507 mips_reorg_process_insns ();
16509 && TARGET_EXPLICIT_RELOCS
16511 && TARGET_VR4130_ALIGN)
16512 vr4130_align_insns ();
16513 if (mips_expand_ghost_gp_insns ())
16514 /* The expansion could invalidate some of the VR4130 alignment
16515 optimizations, but this should be an extremely rare case anyhow. */
16516 mips_reorg_process_insns ();
16517 mips16_split_long_branches ();
16523 const pass_data pass_data_mips_machine_reorg2 =
16525 RTL_PASS, /* type */
16526 "mach2", /* name */
16527 OPTGROUP_NONE, /* optinfo_flags */
16528 true, /* has_execute */
16529 TV_MACH_DEP, /* tv_id */
16530 0, /* properties_required */
16531 0, /* properties_provided */
16532 0, /* properties_destroyed */
16533 0, /* todo_flags_start */
16534 0, /* todo_flags_finish */
16537 class pass_mips_machine_reorg2 : public rtl_opt_pass
16540 pass_mips_machine_reorg2(gcc::context *ctxt)
16541 : rtl_opt_pass(pass_data_mips_machine_reorg2, ctxt)
16544 /* opt_pass methods: */
16545 virtual unsigned int execute (function *) { return mips_machine_reorg2 (); }
16547 }; // class pass_mips_machine_reorg2
16549 } // anon namespace
16552 make_pass_mips_machine_reorg2 (gcc::context *ctxt)
16554 return new pass_mips_machine_reorg2 (ctxt);
16558 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
16559 in order to avoid duplicating too much logic from elsewhere. */
16562 mips_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16563 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16566 rtx this_rtx, temp1, temp2, insn, fnaddr;
16567 bool use_sibcall_p;
16569 /* Pretend to be a post-reload pass while generating rtl. */
16570 reload_completed = 1;
16572 /* Mark the end of the (empty) prologue. */
16573 emit_note (NOTE_INSN_PROLOGUE_END);
16575 /* Determine if we can use a sibcall to call FUNCTION directly. */
16576 fnaddr = XEXP (DECL_RTL (function), 0);
16577 use_sibcall_p = (mips_function_ok_for_sibcall (function, NULL)
16578 && const_call_insn_operand (fnaddr, Pmode));
16580 /* Determine if we need to load FNADDR from the GOT. */
16582 && (mips_got_symbol_type_p
16583 (mips_classify_symbol (fnaddr, SYMBOL_CONTEXT_LEA))))
16585 /* Pick a global pointer. Use a call-clobbered register if
16586 TARGET_CALL_SAVED_GP. */
16587 cfun->machine->global_pointer
16588 = TARGET_CALL_SAVED_GP ? 15 : GLOBAL_POINTER_REGNUM;
16589 cfun->machine->must_initialize_gp_p = true;
16590 SET_REGNO (pic_offset_table_rtx, cfun->machine->global_pointer);
16592 /* Set up the global pointer for n32 or n64 abicalls. */
16593 mips_emit_loadgp ();
16596 /* We need two temporary registers in some cases. */
16597 temp1 = gen_rtx_REG (Pmode, 2);
16598 temp2 = gen_rtx_REG (Pmode, 3);
16600 /* Find out which register contains the "this" pointer. */
16601 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16602 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1);
16604 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST);
16606 /* Add DELTA to THIS_RTX. */
16609 rtx offset = GEN_INT (delta);
16610 if (!SMALL_OPERAND (delta))
16612 mips_emit_move (temp1, offset);
16615 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset));
16618 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
16619 if (vcall_offset != 0)
16623 /* Set TEMP1 to *THIS_RTX. */
16624 mips_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx));
16626 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
16627 addr = mips_add_offset (temp2, temp1, vcall_offset);
16629 /* Load the offset and add it to THIS_RTX. */
16630 mips_emit_move (temp1, gen_rtx_MEM (Pmode, addr));
16631 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1));
16634 /* Jump to the target function. Use a sibcall if direct jumps are
16635 allowed, otherwise load the address into a register first. */
16638 insn = emit_call_insn (gen_sibcall_internal (fnaddr, const0_rtx));
16639 SIBLING_CALL_P (insn) = 1;
16643 /* This is messy. GAS treats "la $25,foo" as part of a call
16644 sequence and may allow a global "foo" to be lazily bound.
16645 The general move patterns therefore reject this combination.
16647 In this context, lazy binding would actually be OK
16648 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
16649 TARGET_CALL_SAVED_GP; see mips_load_call_address.
16650 We must therefore load the address via a temporary
16651 register if mips_dangerous_for_la25_p.
16653 If we jump to the temporary register rather than $25,
16654 the assembler can use the move insn to fill the jump's
16657 We can use the same technique for MIPS16 code, where $25
16658 is not a valid JR register. */
16659 if (TARGET_USE_PIC_FN_ADDR_REG
16661 && !mips_dangerous_for_la25_p (fnaddr))
16662 temp1 = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
16663 mips_load_call_address (MIPS_CALL_SIBCALL, temp1, fnaddr);
16665 if (TARGET_USE_PIC_FN_ADDR_REG
16666 && REGNO (temp1) != PIC_FUNCTION_ADDR_REGNUM)
16667 mips_emit_move (gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM), temp1);
16668 emit_jump_insn (gen_indirect_jump (temp1));
16671 /* Run just enough of rest_of_compilation. This sequence was
16672 "borrowed" from alpha.c. */
16673 insn = get_insns ();
16674 split_all_insns_noflow ();
16675 mips16_lay_out_constants (true);
16676 shorten_branches (insn);
16677 final_start_function (insn, file, 1);
16678 final (insn, file, 1);
16679 final_end_function ();
16681 /* Clean up the vars set above. Note that final_end_function resets
16682 the global pointer for us. */
16683 reload_completed = 0;
16687 /* The last argument passed to mips_set_compression_mode,
16688 or negative if the function hasn't been called yet. */
16689 static unsigned int old_compression_mode = -1;
16691 /* Set up the target-dependent global state for ISA mode COMPRESSION_MODE,
16692 which is either MASK_MIPS16 or MASK_MICROMIPS. */
16695 mips_set_compression_mode (unsigned int compression_mode)
16698 if (compression_mode == old_compression_mode)
16701 /* Restore base settings of various flags. */
16702 target_flags = mips_base_target_flags;
16703 flag_schedule_insns = mips_base_schedule_insns;
16704 flag_reorder_blocks_and_partition = mips_base_reorder_blocks_and_partition;
16705 flag_move_loop_invariants = mips_base_move_loop_invariants;
16706 align_loops = mips_base_align_loops;
16707 align_jumps = mips_base_align_jumps;
16708 align_functions = mips_base_align_functions;
16709 target_flags &= ~(MASK_MIPS16 | MASK_MICROMIPS);
16710 target_flags |= compression_mode;
16712 if (compression_mode & MASK_MIPS16)
16714 /* Switch to MIPS16 mode. */
16715 target_flags |= MASK_MIPS16;
16717 /* Turn off SYNCI if it was on, MIPS16 doesn't support it. */
16718 target_flags &= ~MASK_SYNCI;
16720 /* Don't run the scheduler before reload, since it tends to
16721 increase register pressure. */
16722 flag_schedule_insns = 0;
16724 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
16725 the whole function to be in a single section. */
16726 flag_reorder_blocks_and_partition = 0;
16728 /* Don't move loop invariants, because it tends to increase
16729 register pressure. It also introduces an extra move in cases
16730 where the constant is the first operand in a two-operand binary
16731 instruction, or when it forms a register argument to a functon
16733 flag_move_loop_invariants = 0;
16735 target_flags |= MASK_EXPLICIT_RELOCS;
16737 /* Experiments suggest we get the best overall section-anchor
16738 results from using the range of an unextended LW or SW. Code
16739 that makes heavy use of byte or short accesses can do better
16740 with ranges of 0...31 and 0...63 respectively, but most code is
16741 sensitive to the range of LW and SW instead. */
16742 targetm.min_anchor_offset = 0;
16743 targetm.max_anchor_offset = 127;
16745 targetm.const_anchor = 0;
16747 /* MIPS16 has no BAL instruction. */
16748 target_flags &= ~MASK_RELAX_PIC_CALLS;
16750 /* The R4000 errata don't apply to any known MIPS16 cores.
16751 It's simpler to make the R4000 fixes and MIPS16 mode
16752 mutually exclusive. */
16753 target_flags &= ~MASK_FIX_R4000;
16755 if (flag_pic && !TARGET_OLDABI)
16756 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
16759 sorry ("MIPS16 -mxgot code");
16761 if (TARGET_HARD_FLOAT_ABI && !TARGET_OLDABI)
16762 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
16766 /* Switch to microMIPS or the standard encoding. */
16768 if (TARGET_MICROMIPS)
16769 /* Avoid branch likely. */
16770 target_flags &= ~MASK_BRANCHLIKELY;
16772 /* Provide default values for align_* for 64-bit targets. */
16775 if (align_loops == 0)
16777 if (align_jumps == 0)
16779 if (align_functions == 0)
16780 align_functions = 8;
16783 targetm.min_anchor_offset = -32768;
16784 targetm.max_anchor_offset = 32767;
16786 targetm.const_anchor = 0x8000;
16789 /* (Re)initialize MIPS target internals for new ISA. */
16790 mips_init_relocs ();
16792 if (compression_mode & MASK_MIPS16)
16794 if (!mips16_globals)
16795 mips16_globals = save_target_globals_default_opts ();
16797 restore_target_globals (mips16_globals);
16800 restore_target_globals (&default_target_globals);
16802 old_compression_mode = compression_mode;
16805 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
16806 function should use the MIPS16 or microMIPS ISA and switch modes
16810 mips_set_current_function (tree fndecl)
16812 mips_set_compression_mode (mips_get_compress_mode (fndecl));
16815 /* Allocate a chunk of memory for per-function machine-dependent data. */
16817 static struct machine_function *
16818 mips_init_machine_status (void)
16820 return ggc_cleared_alloc<machine_function> ();
16823 /* Return the processor associated with the given ISA level, or null
16824 if the ISA isn't valid. */
16826 static const struct mips_cpu_info *
16827 mips_cpu_info_from_isa (int isa)
16831 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16832 if (mips_cpu_info_table[i].isa == isa)
16833 return mips_cpu_info_table + i;
16838 /* Return a mips_cpu_info entry determined by an option valued
16841 static const struct mips_cpu_info *
16842 mips_cpu_info_from_opt (int opt)
16846 case MIPS_ARCH_OPTION_FROM_ABI:
16847 /* 'from-abi' selects the most compatible architecture for the
16848 given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
16849 ABIs. For the EABIs, we have to decide whether we're using
16850 the 32-bit or 64-bit version. */
16851 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
16852 : ABI_NEEDS_64BIT_REGS ? 3
16853 : (TARGET_64BIT ? 3 : 1));
16855 case MIPS_ARCH_OPTION_NATIVE:
16856 gcc_unreachable ();
16859 return &mips_cpu_info_table[opt];
16863 /* Return a default mips_cpu_info entry, given that no -march= option
16864 was explicitly specified. */
16866 static const struct mips_cpu_info *
16867 mips_default_arch (void)
16869 #if defined (MIPS_CPU_STRING_DEFAULT)
16871 for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
16872 if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
16873 return mips_cpu_info_table + i;
16874 gcc_unreachable ();
16875 #elif defined (MIPS_ISA_DEFAULT)
16876 return mips_cpu_info_from_isa (MIPS_ISA_DEFAULT);
16878 /* 'from-abi' makes a good default: you get whatever the ABI
16880 return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
16884 /* Set up globals to generate code for the ISA or processor
16885 described by INFO. */
16888 mips_set_architecture (const struct mips_cpu_info *info)
16892 mips_arch_info = info;
16893 mips_arch = info->cpu;
16894 mips_isa = info->isa;
16898 mips_isa_rev = (mips_isa & 31) + 1;
16902 /* Likewise for tuning. */
16905 mips_set_tune (const struct mips_cpu_info *info)
16909 mips_tune_info = info;
16910 mips_tune = info->cpu;
16914 /* Implement TARGET_OPTION_OVERRIDE. */
16917 mips_option_override (void)
16919 int i, start, regno, mode;
16921 if (global_options_set.x_mips_isa_option)
16922 mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
16924 #ifdef SUBTARGET_OVERRIDE_OPTIONS
16925 SUBTARGET_OVERRIDE_OPTIONS;
16928 /* MIPS16 and microMIPS cannot coexist. */
16929 if (TARGET_MICROMIPS && TARGET_MIPS16)
16930 error ("unsupported combination: %s", "-mips16 -mmicromips");
16932 /* Save the base compression state and process flags as though we
16933 were generating uncompressed code. */
16934 mips_base_compression_flags = TARGET_COMPRESSION;
16935 target_flags &= ~TARGET_COMPRESSION;
16937 /* -mno-float overrides -mhard-float and -msoft-float. */
16938 if (TARGET_NO_FLOAT)
16940 target_flags |= MASK_SOFT_FLOAT_ABI;
16941 target_flags_explicit |= MASK_SOFT_FLOAT_ABI;
16944 if (TARGET_FLIP_MIPS16)
16945 TARGET_INTERLINK_COMPRESSED = 1;
16947 /* Set the small data limit. */
16948 mips_small_data_threshold = (global_options_set.x_g_switch_value
16950 : MIPS_DEFAULT_GVALUE);
16952 /* The following code determines the architecture and register size.
16953 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
16954 The GAS and GCC code should be kept in sync as much as possible. */
16956 if (global_options_set.x_mips_arch_option)
16957 mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
16959 if (mips_isa_option_info != 0)
16961 if (mips_arch_info == 0)
16962 mips_set_architecture (mips_isa_option_info);
16963 else if (mips_arch_info->isa != mips_isa_option_info->isa)
16964 error ("%<-%s%> conflicts with the other architecture options, "
16965 "which specify a %s processor",
16966 mips_isa_option_info->name,
16967 mips_cpu_info_from_isa (mips_arch_info->isa)->name);
16970 if (mips_arch_info == 0)
16971 mips_set_architecture (mips_default_arch ());
16973 if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
16974 error ("%<-march=%s%> is not compatible with the selected ABI",
16975 mips_arch_info->name);
16977 /* Optimize for mips_arch, unless -mtune selects a different processor. */
16978 if (global_options_set.x_mips_tune_option)
16979 mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
16981 if (mips_tune_info == 0)
16982 mips_set_tune (mips_arch_info);
16984 if ((target_flags_explicit & MASK_64BIT) != 0)
16986 /* The user specified the size of the integer registers. Make sure
16987 it agrees with the ABI and ISA. */
16988 if (TARGET_64BIT && !ISA_HAS_64BIT_REGS)
16989 error ("%<-mgp64%> used with a 32-bit processor");
16990 else if (!TARGET_64BIT && ABI_NEEDS_64BIT_REGS)
16991 error ("%<-mgp32%> used with a 64-bit ABI");
16992 else if (TARGET_64BIT && ABI_NEEDS_32BIT_REGS)
16993 error ("%<-mgp64%> used with a 32-bit ABI");
16997 /* Infer the integer register size from the ABI and processor.
16998 Restrict ourselves to 32-bit registers if that's all the
16999 processor has, or if the ABI cannot handle 64-bit registers. */
17000 if (ABI_NEEDS_32BIT_REGS || !ISA_HAS_64BIT_REGS)
17001 target_flags &= ~MASK_64BIT;
17003 target_flags |= MASK_64BIT;
17006 if ((target_flags_explicit & MASK_FLOAT64) != 0)
17008 if (TARGET_SINGLE_FLOAT && TARGET_FLOAT64)
17009 error ("unsupported combination: %s", "-mfp64 -msingle-float");
17010 else if (TARGET_64BIT && TARGET_DOUBLE_FLOAT && !TARGET_FLOAT64)
17011 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
17012 else if (!TARGET_64BIT && TARGET_FLOAT64)
17014 if (!ISA_HAS_MXHC1)
17015 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
17016 " the target supports the mfhc1 and mthc1 instructions");
17017 else if (mips_abi != ABI_32)
17018 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
17024 /* -msingle-float selects 32-bit float registers. Otherwise the
17025 float registers should be the same size as the integer ones. */
17026 if (TARGET_64BIT && TARGET_DOUBLE_FLOAT)
17027 target_flags |= MASK_FLOAT64;
17029 target_flags &= ~MASK_FLOAT64;
17032 /* End of code shared with GAS. */
17034 /* The R5900 FPU only supports single precision. */
17035 if (TARGET_MIPS5900 && TARGET_HARD_FLOAT_ABI && TARGET_DOUBLE_FLOAT)
17036 error ("unsupported combination: %s",
17037 "-march=r5900 -mhard-float -mdouble-float");
17039 /* If a -mlong* option was given, check that it matches the ABI,
17040 otherwise infer the -mlong* setting from the other options. */
17041 if ((target_flags_explicit & MASK_LONG64) != 0)
17045 if (mips_abi == ABI_N32)
17046 error ("%qs is incompatible with %qs", "-mabi=n32", "-mlong64");
17047 else if (mips_abi == ABI_32)
17048 error ("%qs is incompatible with %qs", "-mabi=32", "-mlong64");
17049 else if (mips_abi == ABI_O64 && TARGET_ABICALLS)
17050 /* We have traditionally allowed non-abicalls code to use
17051 an LP64 form of o64. However, it would take a bit more
17052 effort to support the combination of 32-bit GOT entries
17053 and 64-bit pointers, so we treat the abicalls case as
17055 error ("the combination of %qs and %qs is incompatible with %qs",
17056 "-mabi=o64", "-mabicalls", "-mlong64");
17060 if (mips_abi == ABI_64)
17061 error ("%qs is incompatible with %qs", "-mabi=64", "-mlong32");
17066 if ((mips_abi == ABI_EABI && TARGET_64BIT) || mips_abi == ABI_64)
17067 target_flags |= MASK_LONG64;
17069 target_flags &= ~MASK_LONG64;
17072 if (!TARGET_OLDABI)
17073 flag_pcc_struct_return = 0;
17075 /* Decide which rtx_costs structure to use. */
17077 mips_cost = &mips_rtx_cost_optimize_size;
17079 mips_cost = &mips_rtx_cost_data[mips_tune];
17081 /* If the user hasn't specified a branch cost, use the processor's
17083 if (mips_branch_cost == 0)
17084 mips_branch_cost = mips_cost->branch_cost;
17086 /* If neither -mbranch-likely nor -mno-branch-likely was given
17087 on the command line, set MASK_BRANCHLIKELY based on the target
17088 architecture and tuning flags. Annulled delay slots are a
17089 size win, so we only consider the processor-specific tuning
17090 for !optimize_size. */
17091 if ((target_flags_explicit & MASK_BRANCHLIKELY) == 0)
17093 if (ISA_HAS_BRANCHLIKELY
17095 || (mips_tune_info->tune_flags & PTF_AVOID_BRANCHLIKELY) == 0))
17096 target_flags |= MASK_BRANCHLIKELY;
17098 target_flags &= ~MASK_BRANCHLIKELY;
17100 else if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
17101 warning (0, "the %qs architecture does not support branch-likely"
17102 " instructions", mips_arch_info->name);
17104 /* If the user hasn't specified -mimadd or -mno-imadd set
17105 MASK_IMADD based on the target architecture and tuning
17107 if ((target_flags_explicit & MASK_IMADD) == 0)
17109 if (ISA_HAS_MADD_MSUB &&
17110 (mips_tune_info->tune_flags & PTF_AVOID_IMADD) == 0)
17111 target_flags |= MASK_IMADD;
17113 target_flags &= ~MASK_IMADD;
17115 else if (TARGET_IMADD && !ISA_HAS_MADD_MSUB)
17116 warning (0, "the %qs architecture does not support madd or msub"
17117 " instructions", mips_arch_info->name);
17119 /* The effect of -mabicalls isn't defined for the EABI. */
17120 if (mips_abi == ABI_EABI && TARGET_ABICALLS)
17122 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
17123 target_flags &= ~MASK_ABICALLS;
17126 /* PIC requires -mabicalls. */
17129 if (mips_abi == ABI_EABI)
17130 error ("cannot generate position-independent code for %qs",
17132 else if (!TARGET_ABICALLS)
17133 error ("position-independent code requires %qs", "-mabicalls");
17136 if (TARGET_ABICALLS_PIC2)
17137 /* We need to set flag_pic for executables as well as DSOs
17138 because we may reference symbols that are not defined in
17139 the final executable. (MIPS does not use things like
17140 copy relocs, for example.)
17142 There is a body of code that uses __PIC__ to distinguish
17143 between -mabicalls and -mno-abicalls code. The non-__PIC__
17144 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
17145 long as any indirect jumps use $25. */
17148 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17149 faster code, but at the expense of more nops. Enable it at -O3 and
17151 if (optimize > 2 && (target_flags_explicit & MASK_VR4130_ALIGN) == 0)
17152 target_flags |= MASK_VR4130_ALIGN;
17154 /* Prefer a call to memcpy over inline code when optimizing for size,
17155 though see MOVE_RATIO in mips.h. */
17156 if (optimize_size && (target_flags_explicit & MASK_MEMCPY) == 0)
17157 target_flags |= MASK_MEMCPY;
17159 /* If we have a nonzero small-data limit, check that the -mgpopt
17160 setting is consistent with the other target flags. */
17161 if (mips_small_data_threshold > 0)
17165 if (!TARGET_EXPLICIT_RELOCS)
17166 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
17168 TARGET_LOCAL_SDATA = false;
17169 TARGET_EXTERN_SDATA = false;
17173 if (TARGET_VXWORKS_RTP)
17174 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
17176 if (TARGET_ABICALLS)
17177 warning (0, "cannot use small-data accesses for %qs",
17182 /* Pre-IEEE 754-2008 MIPS hardware has a quirky almost-IEEE format
17183 for all its floating point. */
17184 if (mips_nan != MIPS_IEEE_754_2008)
17186 REAL_MODE_FORMAT (SFmode) = &mips_single_format;
17187 REAL_MODE_FORMAT (DFmode) = &mips_double_format;
17188 REAL_MODE_FORMAT (TFmode) = &mips_quad_format;
17191 /* Make sure that the user didn't turn off paired single support when
17192 MIPS-3D support is requested. */
17194 && (target_flags_explicit & MASK_PAIRED_SINGLE_FLOAT)
17195 && !TARGET_PAIRED_SINGLE_FLOAT)
17196 error ("%<-mips3d%> requires %<-mpaired-single%>");
17198 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
17200 target_flags |= MASK_PAIRED_SINGLE_FLOAT;
17202 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
17203 and TARGET_HARD_FLOAT_ABI are both true. */
17204 if (TARGET_PAIRED_SINGLE_FLOAT && !(TARGET_FLOAT64 && TARGET_HARD_FLOAT_ABI))
17206 error ("%qs must be used with %qs",
17207 TARGET_MIPS3D ? "-mips3d" : "-mpaired-single",
17208 TARGET_HARD_FLOAT_ABI ? "-mfp64" : "-mhard-float");
17209 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
17213 /* Make sure that -mpaired-single is only used on ISAs that support it.
17214 We must disable it otherwise since it relies on other ISA properties
17215 like ISA_HAS_8CC having their normal values. */
17216 if (TARGET_PAIRED_SINGLE_FLOAT && !ISA_HAS_PAIRED_SINGLE)
17218 error ("the %qs architecture does not support paired-single"
17219 " instructions", mips_arch_info->name);
17220 target_flags &= ~MASK_PAIRED_SINGLE_FLOAT;
17224 if (mips_r10k_cache_barrier != R10K_CACHE_BARRIER_NONE
17225 && !TARGET_CACHE_BUILTIN)
17227 error ("%qs requires a target that provides the %qs instruction",
17228 "-mr10k-cache-barrier", "cache");
17229 mips_r10k_cache_barrier = R10K_CACHE_BARRIER_NONE;
17232 /* If TARGET_DSPR2, enable TARGET_DSP. */
17236 /* .eh_frame addresses should be the same width as a C pointer.
17237 Most MIPS ABIs support only one pointer size, so the assembler
17238 will usually know exactly how big an .eh_frame address is.
17240 Unfortunately, this is not true of the 64-bit EABI. The ABI was
17241 originally defined to use 64-bit pointers (i.e. it is LP64), and
17242 this is still the default mode. However, we also support an n32-like
17243 ILP32 mode, which is selected by -mlong32. The problem is that the
17244 assembler has traditionally not had an -mlong option, so it has
17245 traditionally not known whether we're using the ILP32 or LP64 form.
17247 As it happens, gas versions up to and including 2.19 use _32-bit_
17248 addresses for EABI64 .cfi_* directives. This is wrong for the
17249 default LP64 mode, so we can't use the directives by default.
17250 Moreover, since gas's current behavior is at odds with gcc's
17251 default behavior, it seems unwise to rely on future versions
17252 of gas behaving the same way. We therefore avoid using .cfi
17253 directives for -mlong32 as well. */
17254 if (mips_abi == ABI_EABI && TARGET_64BIT)
17255 flag_dwarf2_cfi_asm = 0;
17257 /* .cfi_* directives generate a read-only section, so fall back on
17258 manual .eh_frame creation if we need the section to be writable. */
17259 if (TARGET_WRITABLE_EH_FRAME)
17260 flag_dwarf2_cfi_asm = 0;
17262 mips_init_print_operand_punct ();
17264 /* Set up array to map GCC register number to debug register number.
17265 Ignore the special purpose register numbers. */
17267 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
17269 mips_dbx_regno[i] = IGNORED_DWARF_REGNUM;
17270 if (GP_REG_P (i) || FP_REG_P (i) || ALL_COP_REG_P (i))
17271 mips_dwarf_regno[i] = i;
17273 mips_dwarf_regno[i] = INVALID_REGNUM;
17276 start = GP_DBX_FIRST - GP_REG_FIRST;
17277 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
17278 mips_dbx_regno[i] = i + start;
17280 start = FP_DBX_FIRST - FP_REG_FIRST;
17281 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
17282 mips_dbx_regno[i] = i + start;
17284 /* Accumulator debug registers use big-endian ordering. */
17285 mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
17286 mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
17287 mips_dwarf_regno[HI_REGNUM] = MD_REG_FIRST + 0;
17288 mips_dwarf_regno[LO_REGNUM] = MD_REG_FIRST + 1;
17289 for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
17291 mips_dwarf_regno[i + TARGET_LITTLE_ENDIAN] = i;
17292 mips_dwarf_regno[i + TARGET_BIG_ENDIAN] = i + 1;
17295 /* Set up mips_hard_regno_mode_ok. */
17296 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
17297 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
17298 mips_hard_regno_mode_ok[mode][regno]
17299 = mips_hard_regno_mode_ok_p (regno, (enum machine_mode) mode);
17301 /* Function to allocate machine-dependent function status. */
17302 init_machine_status = &mips_init_machine_status;
17304 /* Default to working around R4000 errata only if the processor
17305 was selected explicitly. */
17306 if ((target_flags_explicit & MASK_FIX_R4000) == 0
17307 && strcmp (mips_arch_info->name, "r4000") == 0)
17308 target_flags |= MASK_FIX_R4000;
17310 /* Default to working around R4400 errata only if the processor
17311 was selected explicitly. */
17312 if ((target_flags_explicit & MASK_FIX_R4400) == 0
17313 && strcmp (mips_arch_info->name, "r4400") == 0)
17314 target_flags |= MASK_FIX_R4400;
17316 /* Default to working around R10000 errata only if the processor
17317 was selected explicitly. */
17318 if ((target_flags_explicit & MASK_FIX_R10000) == 0
17319 && strcmp (mips_arch_info->name, "r10000") == 0)
17320 target_flags |= MASK_FIX_R10000;
17322 /* Make sure that branch-likely instructions available when using
17323 -mfix-r10000. The instructions are not available if either:
17325 1. -mno-branch-likely was passed.
17326 2. The selected ISA does not support branch-likely and
17327 the command line does not include -mbranch-likely. */
17328 if (TARGET_FIX_R10000
17329 && ((target_flags_explicit & MASK_BRANCHLIKELY) == 0
17330 ? !ISA_HAS_BRANCHLIKELY
17331 : !TARGET_BRANCHLIKELY))
17332 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
17334 if (TARGET_SYNCI && !ISA_HAS_SYNCI)
17336 warning (0, "the %qs architecture does not support the synci "
17337 "instruction", mips_arch_info->name);
17338 target_flags &= ~MASK_SYNCI;
17341 /* Only optimize PIC indirect calls if they are actually required. */
17342 if (!TARGET_USE_GOT || !TARGET_EXPLICIT_RELOCS)
17343 target_flags &= ~MASK_RELAX_PIC_CALLS;
17345 /* Save base state of options. */
17346 mips_base_target_flags = target_flags;
17347 mips_base_schedule_insns = flag_schedule_insns;
17348 mips_base_reorder_blocks_and_partition = flag_reorder_blocks_and_partition;
17349 mips_base_move_loop_invariants = flag_move_loop_invariants;
17350 mips_base_align_loops = align_loops;
17351 mips_base_align_jumps = align_jumps;
17352 mips_base_align_functions = align_functions;
17354 /* Now select the ISA mode.
17356 Do all CPP-sensitive stuff in uncompressed mode; we'll switch modes
17357 later if required. */
17358 mips_set_compression_mode (0);
17360 /* We register a second machine specific reorg pass after delay slot
17361 filling. Registering the pass must be done at start up. It's
17362 convenient to do it here. */
17363 opt_pass *new_pass = make_pass_mips_machine_reorg2 (g);
17364 struct register_pass_info insert_pass_mips_machine_reorg2 =
17366 new_pass, /* pass */
17367 "dbr", /* reference_pass_name */
17368 1, /* ref_pass_instance_number */
17369 PASS_POS_INSERT_AFTER /* po_op */
17371 register_pass (&insert_pass_mips_machine_reorg2);
17373 if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
17374 REAL_MODE_FORMAT (SFmode) = &spu_single_format;
17377 /* Swap the register information for registers I and I + 1, which
17378 currently have the wrong endianness. Note that the registers'
17379 fixedness and call-clobberedness might have been set on the
17383 mips_swap_registers (unsigned int i)
17388 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
17389 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
17391 SWAP_INT (fixed_regs[i], fixed_regs[i + 1]);
17392 SWAP_INT (call_used_regs[i], call_used_regs[i + 1]);
17393 SWAP_INT (call_really_used_regs[i], call_really_used_regs[i + 1]);
17394 SWAP_STRING (reg_names[i], reg_names[i + 1]);
17400 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
17403 mips_conditional_register_usage (void)
17408 /* These DSP control register fields are global. */
17409 global_regs[CCDSP_PO_REGNUM] = 1;
17410 global_regs[CCDSP_SC_REGNUM] = 1;
17413 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17414 reg_class_contents[(int) DSP_ACC_REGS]);
17416 if (!TARGET_HARD_FLOAT)
17418 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17419 reg_class_contents[(int) FP_REGS]);
17420 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17421 reg_class_contents[(int) ST_REGS]);
17423 else if (!ISA_HAS_8CC)
17425 /* We only have a single condition-code register. We implement
17426 this by fixing all the condition-code registers and generating
17427 RTL that refers directly to ST_REG_FIRST. */
17428 AND_COMPL_HARD_REG_SET (accessible_reg_set,
17429 reg_class_contents[(int) ST_REGS]);
17430 SET_HARD_REG_BIT (accessible_reg_set, FPSW_REGNUM);
17431 fixed_regs[FPSW_REGNUM] = call_used_regs[FPSW_REGNUM] = 1;
17435 /* In MIPS16 mode, we prohibit the unused $s registers, since they
17436 are call-saved, and saving them via a MIPS16 register would
17437 probably waste more time than just reloading the value.
17439 We permit the $t temporary registers when optimizing for speed
17440 but not when optimizing for space because using them results in
17441 code that is larger (but faster) then not using them. We do
17442 allow $24 (t8) because it is used in CMP and CMPI instructions
17443 and $25 (t9) because it is used as the function call address in
17446 fixed_regs[18] = call_used_regs[18] = 1;
17447 fixed_regs[19] = call_used_regs[19] = 1;
17448 fixed_regs[20] = call_used_regs[20] = 1;
17449 fixed_regs[21] = call_used_regs[21] = 1;
17450 fixed_regs[22] = call_used_regs[22] = 1;
17451 fixed_regs[23] = call_used_regs[23] = 1;
17452 fixed_regs[26] = call_used_regs[26] = 1;
17453 fixed_regs[27] = call_used_regs[27] = 1;
17454 fixed_regs[30] = call_used_regs[30] = 1;
17457 fixed_regs[8] = call_used_regs[8] = 1;
17458 fixed_regs[9] = call_used_regs[9] = 1;
17459 fixed_regs[10] = call_used_regs[10] = 1;
17460 fixed_regs[11] = call_used_regs[11] = 1;
17461 fixed_regs[12] = call_used_regs[12] = 1;
17462 fixed_regs[13] = call_used_regs[13] = 1;
17463 fixed_regs[14] = call_used_regs[14] = 1;
17464 fixed_regs[15] = call_used_regs[15] = 1;
17467 /* Do not allow HI and LO to be treated as register operands.
17468 There are no MTHI or MTLO instructions (or any real need
17469 for them) and one-way registers cannot easily be reloaded. */
17470 AND_COMPL_HARD_REG_SET (operand_reg_set,
17471 reg_class_contents[(int) MD_REGS]);
17473 /* $f20-$f23 are call-clobbered for n64. */
17474 if (mips_abi == ABI_64)
17477 for (regno = FP_REG_FIRST + 20; regno < FP_REG_FIRST + 24; regno++)
17478 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17480 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
17482 if (mips_abi == ABI_N32)
17485 for (regno = FP_REG_FIRST + 21; regno <= FP_REG_FIRST + 31; regno+=2)
17486 call_really_used_regs[regno] = call_used_regs[regno] = 1;
17488 /* Make sure that double-register accumulator values are correctly
17489 ordered for the current endianness. */
17490 if (TARGET_LITTLE_ENDIAN)
17492 unsigned int regno;
17494 mips_swap_registers (MD_REG_FIRST);
17495 for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno += 2)
17496 mips_swap_registers (regno);
17500 /* Implement EH_USES. */
17503 mips_eh_uses (unsigned int regno)
17505 if (reload_completed && !TARGET_ABSOLUTE_JUMPS)
17507 /* We need to force certain registers to be live in order to handle
17508 PIC long branches correctly. See mips_must_initialize_gp_p for
17510 if (mips_cfun_has_cprestore_slot_p ())
17512 if (regno == CPRESTORE_SLOT_REGNUM)
17517 if (cfun->machine->global_pointer == regno)
17525 /* Implement EPILOGUE_USES. */
17528 mips_epilogue_uses (unsigned int regno)
17530 /* Say that the epilogue uses the return address register. Note that
17531 in the case of sibcalls, the values "used by the epilogue" are
17532 considered live at the start of the called function. */
17533 if (regno == RETURN_ADDR_REGNUM)
17536 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17537 See the comment above load_call<mode> for details. */
17538 if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
17541 /* An interrupt handler must preserve some registers that are
17542 ordinarily call-clobbered. */
17543 if (cfun->machine->interrupt_handler_p
17544 && mips_interrupt_extra_call_saved_reg_p (regno))
17550 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
17553 mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
17555 return REG_P (*x) && REGNO (*x) == AT_REGNUM;
17558 /* Return true if INSN needs to be wrapped in ".set noat".
17559 INSN has NOPERANDS operands, stored in OPVEC. */
17562 mips_need_noat_wrapper_p (rtx insn, rtx *opvec, int noperands)
17566 if (recog_memoized (insn) >= 0)
17567 for (i = 0; i < noperands; i++)
17568 if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
17573 /* Implement FINAL_PRESCAN_INSN. */
17576 mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
17578 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17579 mips_push_asm_switch (&mips_noat);
17582 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
17585 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED, rtx insn,
17586 rtx *opvec, int noperands)
17588 if (mips_need_noat_wrapper_p (insn, opvec, noperands))
17589 mips_pop_asm_switch (&mips_noat);
17592 /* Return the function that is used to expand the <u>mulsidi3 pattern.
17593 EXT_CODE is the code of the extension used. Return NULL if widening
17594 multiplication shouldn't be used. */
17597 mips_mulsidi3_gen_fn (enum rtx_code ext_code)
17601 signed_p = ext_code == SIGN_EXTEND;
17604 /* Don't use widening multiplication with MULT when we have DMUL. Even
17605 with the extension of its input operands DMUL is faster. Note that
17606 the extension is not needed for signed multiplication. In order to
17607 ensure that we always remove the redundant sign-extension in this
17608 case we still expand mulsidi3 for DMUL. */
17610 return signed_p ? gen_mulsidi3_64bit_dmul : NULL;
17613 ? gen_mulsidi3_64bit_mips16
17614 : gen_umulsidi3_64bit_mips16);
17615 if (TARGET_FIX_R4000)
17617 return signed_p ? gen_mulsidi3_64bit : gen_umulsidi3_64bit;
17623 ? gen_mulsidi3_32bit_mips16
17624 : gen_umulsidi3_32bit_mips16);
17625 if (TARGET_FIX_R4000 && !ISA_HAS_DSP)
17626 return signed_p ? gen_mulsidi3_32bit_r4000 : gen_umulsidi3_32bit_r4000;
17627 return signed_p ? gen_mulsidi3_32bit : gen_umulsidi3_32bit;
17631 /* Return true if PATTERN matches the kind of instruction generated by
17632 umips_build_save_restore. SAVE_P is true for store. */
17635 umips_save_restore_pattern_p (bool save_p, rtx pattern)
17639 HOST_WIDE_INT first_offset = 0;
17640 rtx first_base = 0;
17641 unsigned int regmask = 0;
17643 for (n = 0; n < XVECLEN (pattern, 0); n++)
17645 rtx set, reg, mem, this_base;
17646 HOST_WIDE_INT this_offset;
17648 /* Check that we have a SET. */
17649 set = XVECEXP (pattern, 0, n);
17650 if (GET_CODE (set) != SET)
17653 /* Check that the SET is a load (if restoring) or a store
17655 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17656 if (!MEM_P (mem) || MEM_VOLATILE_P (mem))
17659 /* Check that the address is the sum of base and a possibly-zero
17660 constant offset. Determine if the offset is in range. */
17661 mips_split_plus (XEXP (mem, 0), &this_base, &this_offset);
17662 if (!REG_P (this_base))
17667 if (!UMIPS_12BIT_OFFSET_P (this_offset))
17669 first_base = this_base;
17670 first_offset = this_offset;
17674 /* Check that the save slots are consecutive. */
17675 if (REGNO (this_base) != REGNO (first_base)
17676 || this_offset != first_offset + UNITS_PER_WORD * n)
17680 /* Check that SET's other operand is a register. */
17681 reg = save_p ? SET_SRC (set) : SET_DEST (set);
17685 regmask |= 1 << REGNO (reg);
17688 for (i = 0; i < ARRAY_SIZE (umips_swm_mask); i++)
17689 if (regmask == umips_swm_mask[i])
17695 /* Return the assembly instruction for microMIPS LWM or SWM.
17696 SAVE_P and PATTERN are as for umips_save_restore_pattern_p. */
17699 umips_output_save_restore (bool save_p, rtx pattern)
17701 static char buffer[300];
17704 HOST_WIDE_INT offset;
17705 rtx base, mem, set, last_set, last_reg;
17707 /* Parse the pattern. */
17708 gcc_assert (umips_save_restore_pattern_p (save_p, pattern));
17710 s = strcpy (buffer, save_p ? "swm\t" : "lwm\t");
17712 n = XVECLEN (pattern, 0);
17714 set = XVECEXP (pattern, 0, 0);
17715 mem = save_p ? SET_DEST (set) : SET_SRC (set);
17716 mips_split_plus (XEXP (mem, 0), &base, &offset);
17718 last_set = XVECEXP (pattern, 0, n - 1);
17719 last_reg = save_p ? SET_SRC (last_set) : SET_DEST (last_set);
17721 if (REGNO (last_reg) == 31)
17724 gcc_assert (n <= 9);
17728 s += sprintf (s, "%s,", reg_names[16]);
17730 s += sprintf (s, "%s-%s,", reg_names[16], reg_names[15 + n]);
17732 s += sprintf (s, "%s-%s,%s,", reg_names[16], reg_names[23],
17735 if (REGNO (last_reg) == 31)
17736 s += sprintf (s, "%s,", reg_names[31]);
17738 s += sprintf (s, "%d(%s)", (int)offset, reg_names[REGNO (base)]);
17742 /* Return true if MEM1 and MEM2 use the same base register, and the
17743 offset of MEM2 equals the offset of MEM1 plus 4. FIRST_REG is the
17744 register into (from) which the contents of MEM1 will be loaded
17745 (stored), depending on the value of LOAD_P.
17746 SWAP_P is true when the 1st and 2nd instructions are swapped. */
17749 umips_load_store_pair_p_1 (bool load_p, bool swap_p,
17750 rtx first_reg, rtx mem1, rtx mem2)
17753 HOST_WIDE_INT offset1, offset2;
17755 if (!MEM_P (mem1) || !MEM_P (mem2))
17758 mips_split_plus (XEXP (mem1, 0), &base1, &offset1);
17759 mips_split_plus (XEXP (mem2, 0), &base2, &offset2);
17761 if (!REG_P (base1) || !rtx_equal_p (base1, base2))
17764 /* Avoid invalid load pair instructions. */
17765 if (load_p && REGNO (first_reg) == REGNO (base1))
17768 /* We must avoid this case for anti-dependence.
17771 first_reg is $2, but the base is $3. */
17774 && REGNO (first_reg) + 1 == REGNO (base1))
17777 if (offset2 != offset1 + 4)
17780 if (!UMIPS_12BIT_OFFSET_P (offset1))
17786 /* OPERANDS describes the operands to a pair of SETs, in the order
17787 dest1, src1, dest2, src2. Return true if the operands can be used
17788 in an LWP or SWP instruction; LOAD_P says which. */
17791 umips_load_store_pair_p (bool load_p, rtx *operands)
17793 rtx reg1, reg2, mem1, mem2;
17797 reg1 = operands[0];
17798 reg2 = operands[2];
17799 mem1 = operands[1];
17800 mem2 = operands[3];
17804 reg1 = operands[1];
17805 reg2 = operands[3];
17806 mem1 = operands[0];
17807 mem2 = operands[2];
17810 if (REGNO (reg2) == REGNO (reg1) + 1)
17811 return umips_load_store_pair_p_1 (load_p, false, reg1, mem1, mem2);
17813 if (REGNO (reg1) == REGNO (reg2) + 1)
17814 return umips_load_store_pair_p_1 (load_p, true, reg2, mem2, mem1);
17819 /* Return the assembly instruction for a microMIPS LWP or SWP in which
17820 the first register is REG and the first memory slot is MEM.
17821 LOAD_P is true for LWP. */
17824 umips_output_load_store_pair_1 (bool load_p, rtx reg, rtx mem)
17826 rtx ops[] = {reg, mem};
17829 output_asm_insn ("lwp\t%0,%1", ops);
17831 output_asm_insn ("swp\t%0,%1", ops);
17834 /* Output the assembly instruction for a microMIPS LWP or SWP instruction.
17835 LOAD_P and OPERANDS are as for umips_load_store_pair_p. */
17838 umips_output_load_store_pair (bool load_p, rtx *operands)
17840 rtx reg1, reg2, mem1, mem2;
17843 reg1 = operands[0];
17844 reg2 = operands[2];
17845 mem1 = operands[1];
17846 mem2 = operands[3];
17850 reg1 = operands[1];
17851 reg2 = operands[3];
17852 mem1 = operands[0];
17853 mem2 = operands[2];
17856 if (REGNO (reg2) == REGNO (reg1) + 1)
17858 umips_output_load_store_pair_1 (load_p, reg1, mem1);
17862 gcc_assert (REGNO (reg1) == REGNO (reg2) + 1);
17863 umips_output_load_store_pair_1 (load_p, reg2, mem2);
17866 /* Return true if REG1 and REG2 match the criteria for a movep insn. */
17869 umips_movep_target_p (rtx reg1, rtx reg2)
17871 int regno1, regno2, pair;
17873 static const int match[8] = {
17874 0x00000060, /* 5, 6 */
17875 0x000000a0, /* 5, 7 */
17876 0x000000c0, /* 6, 7 */
17877 0x00200010, /* 4, 21 */
17878 0x00400010, /* 4, 22 */
17879 0x00000030, /* 4, 5 */
17880 0x00000050, /* 4, 6 */
17881 0x00000090 /* 4, 7 */
17884 if (!REG_P (reg1) || !REG_P (reg2))
17887 regno1 = REGNO (reg1);
17888 regno2 = REGNO (reg2);
17890 if (!GP_REG_P (regno1) || !GP_REG_P (regno2))
17893 pair = (1 << regno1) | (1 << regno2);
17895 for (i = 0; i < ARRAY_SIZE (match); i++)
17896 if (pair == match[i])
17902 /* Return the size in bytes of the trampoline code, padded to
17903 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
17904 function address immediately follow. */
17907 mips_trampoline_code_size (void)
17909 if (TARGET_USE_PIC_FN_ADDR_REG)
17911 else if (ptr_mode == DImode)
17913 else if (ISA_HAS_LOAD_DELAY)
17919 /* Implement TARGET_TRAMPOLINE_INIT. */
17922 mips_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
17924 rtx addr, end_addr, high, low, opcode, mem;
17927 HOST_WIDE_INT end_addr_offset, static_chain_offset, target_function_offset;
17929 /* Work out the offsets of the pointers from the start of the
17930 trampoline code. */
17931 end_addr_offset = mips_trampoline_code_size ();
17932 static_chain_offset = end_addr_offset;
17933 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode);
17935 /* Get pointers to the beginning and end of the code block. */
17936 addr = force_reg (Pmode, XEXP (m_tramp, 0));
17937 end_addr = mips_force_binary (Pmode, PLUS, addr, GEN_INT (end_addr_offset));
17939 #define OP(X) gen_int_mode (X, SImode)
17941 /* Build up the code in TRAMPOLINE. */
17943 if (TARGET_USE_PIC_FN_ADDR_REG)
17945 /* $25 contains the address of the trampoline. Emit code of the form:
17947 l[wd] $1, target_function_offset($25)
17948 l[wd] $static_chain, static_chain_offset($25)
17951 trampoline[i++] = OP (MIPS_LOAD_PTR (AT_REGNUM,
17952 target_function_offset,
17953 PIC_FUNCTION_ADDR_REGNUM));
17954 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17955 static_chain_offset,
17956 PIC_FUNCTION_ADDR_REGNUM));
17957 trampoline[i++] = OP (MIPS_JR (AT_REGNUM));
17958 trampoline[i++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM, AT_REGNUM));
17960 else if (ptr_mode == DImode)
17962 /* It's too cumbersome to create the full 64-bit address, so let's
17968 1: l[wd] $25, target_function_offset - 12($31)
17969 l[wd] $static_chain, static_chain_offset - 12($31)
17973 where 12 is the offset of "1:" from the start of the code block. */
17974 trampoline[i++] = OP (MIPS_MOVE (AT_REGNUM, RETURN_ADDR_REGNUM));
17975 trampoline[i++] = OP (MIPS_BAL (1));
17976 trampoline[i++] = OP (MIPS_NOP);
17977 trampoline[i++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
17978 target_function_offset - 12,
17979 RETURN_ADDR_REGNUM));
17980 trampoline[i++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
17981 static_chain_offset - 12,
17982 RETURN_ADDR_REGNUM));
17983 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
17984 trampoline[i++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM, AT_REGNUM));
17988 /* If the target has load delays, emit:
17990 lui $1, %hi(end_addr)
17991 lw $25, %lo(end_addr + ...)($1)
17992 lw $static_chain, %lo(end_addr + ...)($1)
17998 lui $1, %hi(end_addr)
17999 lw $25, %lo(end_addr + ...)($1)
18001 lw $static_chain, %lo(end_addr + ...)($1). */
18003 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
18004 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
18005 high = expand_simple_binop (SImode, PLUS, end_addr, GEN_INT (0x8000),
18006 NULL, false, OPTAB_WIDEN);
18007 high = expand_simple_binop (SImode, LSHIFTRT, high, GEN_INT (16),
18008 NULL, false, OPTAB_WIDEN);
18009 low = convert_to_mode (SImode, gen_lowpart (HImode, end_addr), true);
18011 /* Emit the LUI. */
18012 opcode = OP (MIPS_LUI (AT_REGNUM, 0));
18013 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, high,
18014 NULL, false, OPTAB_WIDEN);
18016 /* Emit the load of the target function. */
18017 opcode = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM,
18018 target_function_offset - end_addr_offset,
18020 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
18021 NULL, false, OPTAB_WIDEN);
18023 /* Emit the JR here, if we can. */
18024 if (!ISA_HAS_LOAD_DELAY)
18025 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18027 /* Emit the load of the static chain register. */
18028 opcode = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM,
18029 static_chain_offset - end_addr_offset,
18031 trampoline[i++] = expand_simple_binop (SImode, IOR, opcode, low,
18032 NULL, false, OPTAB_WIDEN);
18034 /* Emit the JR, if we couldn't above. */
18035 if (ISA_HAS_LOAD_DELAY)
18037 trampoline[i++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM));
18038 trampoline[i++] = OP (MIPS_NOP);
18044 /* Copy the trampoline code. Leave any padding uninitialized. */
18045 for (j = 0; j < i; j++)
18047 mem = adjust_address (m_tramp, SImode, j * GET_MODE_SIZE (SImode));
18048 mips_emit_move (mem, trampoline[j]);
18051 /* Set up the static chain pointer field. */
18052 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset);
18053 mips_emit_move (mem, chain_value);
18055 /* Set up the target function field. */
18056 mem = adjust_address (m_tramp, ptr_mode, target_function_offset);
18057 mips_emit_move (mem, XEXP (DECL_RTL (fndecl), 0));
18059 /* Flush the code part of the trampoline. */
18060 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE)));
18061 emit_insn (gen_clear_cache (addr, end_addr));
18064 /* Implement FUNCTION_PROFILER. */
18066 void mips_function_profiler (FILE *file)
18069 sorry ("mips16 function profiling");
18070 if (TARGET_LONG_CALLS)
18072 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
18073 if (Pmode == DImode)
18074 fprintf (file, "\tdla\t%s,_mcount\n", reg_names[3]);
18076 fprintf (file, "\tla\t%s,_mcount\n", reg_names[3]);
18078 mips_push_asm_switch (&mips_noat);
18079 fprintf (file, "\tmove\t%s,%s\t\t# save current return address\n",
18080 reg_names[AT_REGNUM], reg_names[RETURN_ADDR_REGNUM]);
18081 /* _mcount treats $2 as the static chain register. */
18082 if (cfun->static_chain_decl != NULL)
18083 fprintf (file, "\tmove\t%s,%s\n", reg_names[2],
18084 reg_names[STATIC_CHAIN_REGNUM]);
18085 if (TARGET_MCOUNT_RA_ADDRESS)
18087 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
18088 ra save location. */
18089 if (cfun->machine->frame.ra_fp_offset == 0)
18090 /* ra not saved, pass zero. */
18091 fprintf (file, "\tmove\t%s,%s\n", reg_names[12], reg_names[0]);
18093 fprintf (file, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC "(%s)\n",
18094 Pmode == DImode ? "dla" : "la", reg_names[12],
18095 cfun->machine->frame.ra_fp_offset,
18096 reg_names[STACK_POINTER_REGNUM]);
18098 if (!TARGET_NEWABI)
18100 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
18101 TARGET_64BIT ? "dsubu" : "subu",
18102 reg_names[STACK_POINTER_REGNUM],
18103 reg_names[STACK_POINTER_REGNUM],
18104 Pmode == DImode ? 16 : 8);
18106 if (TARGET_LONG_CALLS)
18107 fprintf (file, "\tjalr\t%s\n", reg_names[3]);
18109 fprintf (file, "\tjal\t_mcount\n");
18110 mips_pop_asm_switch (&mips_noat);
18111 /* _mcount treats $2 as the static chain register. */
18112 if (cfun->static_chain_decl != NULL)
18113 fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM],
18117 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
18118 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
18119 when TARGET_LOONGSON_VECTORS is true. */
18121 static unsigned HOST_WIDE_INT
18122 mips_shift_truncation_mask (enum machine_mode mode)
18124 if (TARGET_LOONGSON_VECTORS && VECTOR_MODE_P (mode))
18127 return GET_MODE_BITSIZE (mode) - 1;
18130 /* Implement TARGET_PREPARE_PCH_SAVE. */
18133 mips_prepare_pch_save (void)
18135 /* We are called in a context where the current MIPS16 vs. non-MIPS16
18136 setting should be irrelevant. The question then is: which setting
18137 makes most sense at load time?
18139 The PCH is loaded before the first token is read. We should never
18140 have switched into MIPS16 mode by that point, and thus should not
18141 have populated mips16_globals. Nor can we load the entire contents
18142 of mips16_globals from the PCH file, because mips16_globals contains
18143 a combination of GGC and non-GGC data.
18145 There is therefore no point in trying save the GGC part of
18146 mips16_globals to the PCH file, or to preserve MIPS16ness across
18147 the PCH save and load. The loading compiler would not have access
18148 to the non-GGC parts of mips16_globals (either from the PCH file,
18149 or from a copy that the loading compiler generated itself) and would
18150 have to call target_reinit anyway.
18152 It therefore seems best to switch back to non-MIPS16 mode at
18153 save time, and to ensure that mips16_globals remains null after
18155 mips_set_compression_mode (0);
18156 mips16_globals = 0;
18159 /* Generate or test for an insn that supports a constant permutation. */
18161 #define MAX_VECT_LEN 8
18163 struct expand_vec_perm_d
18165 rtx target, op0, op1;
18166 unsigned char perm[MAX_VECT_LEN];
18167 enum machine_mode vmode;
18168 unsigned char nelt;
18173 /* Construct (set target (vec_select op0 (parallel perm))) and
18174 return true if that's a valid instruction in the active ISA. */
18177 mips_expand_vselect (rtx target, rtx op0,
18178 const unsigned char *perm, unsigned nelt)
18180 rtx rperm[MAX_VECT_LEN], x;
18183 for (i = 0; i < nelt; ++i)
18184 rperm[i] = GEN_INT (perm[i]);
18186 x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (nelt, rperm));
18187 x = gen_rtx_VEC_SELECT (GET_MODE (target), op0, x);
18188 x = gen_rtx_SET (VOIDmode, target, x);
18191 if (recog_memoized (x) < 0)
18199 /* Similar, but generate a vec_concat from op0 and op1 as well. */
18202 mips_expand_vselect_vconcat (rtx target, rtx op0, rtx op1,
18203 const unsigned char *perm, unsigned nelt)
18205 enum machine_mode v2mode;
18208 v2mode = GET_MODE_2XWIDER_MODE (GET_MODE (op0));
18209 x = gen_rtx_VEC_CONCAT (v2mode, op0, op1);
18210 return mips_expand_vselect (target, x, perm, nelt);
18213 /* Recognize patterns for even-odd extraction. */
18216 mips_expand_vpc_loongson_even_odd (struct expand_vec_perm_d *d)
18218 unsigned i, odd, nelt = d->nelt;
18219 rtx t0, t1, t2, t3;
18221 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18223 /* Even-odd for V2SI/V2SFmode is matched by interleave directly. */
18230 for (i = 1; i < nelt; ++i)
18231 if (d->perm[i] != i * 2 + odd)
18237 /* We need 2*log2(N)-1 operations to achieve odd/even with interleave. */
18238 t0 = gen_reg_rtx (d->vmode);
18239 t1 = gen_reg_rtx (d->vmode);
18243 emit_insn (gen_loongson_punpckhhw (t0, d->op0, d->op1));
18244 emit_insn (gen_loongson_punpcklhw (t1, d->op0, d->op1));
18246 emit_insn (gen_loongson_punpckhhw (d->target, t1, t0));
18248 emit_insn (gen_loongson_punpcklhw (d->target, t1, t0));
18252 t2 = gen_reg_rtx (d->vmode);
18253 t3 = gen_reg_rtx (d->vmode);
18254 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op1));
18255 emit_insn (gen_loongson_punpcklbh (t1, d->op0, d->op1));
18256 emit_insn (gen_loongson_punpckhbh (t2, t1, t0));
18257 emit_insn (gen_loongson_punpcklbh (t3, t1, t0));
18259 emit_insn (gen_loongson_punpckhbh (d->target, t3, t2));
18261 emit_insn (gen_loongson_punpcklbh (d->target, t3, t2));
18265 gcc_unreachable ();
18270 /* Recognize patterns for the Loongson PSHUFH instruction. */
18273 mips_expand_vpc_loongson_pshufh (struct expand_vec_perm_d *d)
18278 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18280 if (d->vmode != V4HImode)
18285 /* Convert the selector into the packed 8-bit form for pshufh. */
18286 /* Recall that loongson is little-endian only. No big-endian
18287 adjustment required. */
18288 for (i = mask = 0; i < 4; i++)
18289 mask |= (d->perm[i] & 3) << (i * 2);
18290 rmask = force_reg (SImode, GEN_INT (mask));
18292 if (d->one_vector_p)
18293 emit_insn (gen_loongson_pshufh (d->target, d->op0, rmask));
18296 rtx t0, t1, x, merge, rmerge[4];
18298 t0 = gen_reg_rtx (V4HImode);
18299 t1 = gen_reg_rtx (V4HImode);
18300 emit_insn (gen_loongson_pshufh (t1, d->op1, rmask));
18301 emit_insn (gen_loongson_pshufh (t0, d->op0, rmask));
18303 for (i = 0; i < 4; ++i)
18304 rmerge[i] = (d->perm[i] & 4 ? constm1_rtx : const0_rtx);
18305 merge = gen_rtx_CONST_VECTOR (V4HImode, gen_rtvec_v (4, rmerge));
18306 merge = force_reg (V4HImode, merge);
18308 x = gen_rtx_AND (V4HImode, merge, t1);
18309 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18311 x = gen_rtx_NOT (V4HImode, merge);
18312 x = gen_rtx_AND (V4HImode, x, t0);
18313 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18315 x = gen_rtx_IOR (V4HImode, t0, t1);
18316 emit_insn (gen_rtx_SET (VOIDmode, d->target, x));
18322 /* Recognize broadcast patterns for the Loongson. */
18325 mips_expand_vpc_loongson_bcast (struct expand_vec_perm_d *d)
18330 if (!(TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS))
18332 /* Note that we've already matched V2SI via punpck and V4HI via pshufh. */
18333 if (d->vmode != V8QImode)
18335 if (!d->one_vector_p)
18339 for (i = 1; i < 8; ++i)
18340 if (d->perm[i] != elt)
18346 /* With one interleave we put two of the desired element adjacent. */
18347 t0 = gen_reg_rtx (V8QImode);
18349 emit_insn (gen_loongson_punpcklbh (t0, d->op0, d->op0));
18351 emit_insn (gen_loongson_punpckhbh (t0, d->op0, d->op0));
18353 /* Shuffle that one HImode element into all locations. */
18356 t1 = gen_reg_rtx (V4HImode);
18357 emit_insn (gen_loongson_pshufh (t1, gen_lowpart (V4HImode, t0),
18358 force_reg (SImode, GEN_INT (elt))));
18360 emit_move_insn (d->target, gen_lowpart (V8QImode, t1));
18365 mips_expand_vec_perm_const_1 (struct expand_vec_perm_d *d)
18367 unsigned int i, nelt = d->nelt;
18368 unsigned char perm2[MAX_VECT_LEN];
18370 if (d->one_vector_p)
18372 /* Try interleave with alternating operands. */
18373 memcpy (perm2, d->perm, sizeof(perm2));
18374 for (i = 1; i < nelt; i += 2)
18376 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1, perm2, nelt))
18381 if (mips_expand_vselect_vconcat (d->target, d->op0, d->op1,
18385 /* Try again with swapped operands. */
18386 for (i = 0; i < nelt; ++i)
18387 perm2[i] = (d->perm[i] + nelt) & (2 * nelt - 1);
18388 if (mips_expand_vselect_vconcat (d->target, d->op1, d->op0, perm2, nelt))
18392 if (mips_expand_vpc_loongson_even_odd (d))
18394 if (mips_expand_vpc_loongson_pshufh (d))
18396 if (mips_expand_vpc_loongson_bcast (d))
18401 /* Expand a vec_perm_const pattern. */
18404 mips_expand_vec_perm_const (rtx operands[4])
18406 struct expand_vec_perm_d d;
18407 int i, nelt, which;
18408 unsigned char orig_perm[MAX_VECT_LEN];
18412 d.target = operands[0];
18413 d.op0 = operands[1];
18414 d.op1 = operands[2];
18417 d.vmode = GET_MODE (d.target);
18418 gcc_assert (VECTOR_MODE_P (d.vmode));
18419 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18420 d.testing_p = false;
18422 for (i = which = 0; i < nelt; ++i)
18424 rtx e = XVECEXP (sel, 0, i);
18425 int ei = INTVAL (e) & (2 * nelt - 1);
18426 which |= (ei < nelt ? 1 : 2);
18429 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18437 d.one_vector_p = false;
18438 if (!rtx_equal_p (d.op0, d.op1))
18443 for (i = 0; i < nelt; ++i)
18444 d.perm[i] &= nelt - 1;
18446 d.one_vector_p = true;
18451 d.one_vector_p = true;
18455 ok = mips_expand_vec_perm_const_1 (&d);
18457 /* If we were given a two-vector permutation which just happened to
18458 have both input vectors equal, we folded this into a one-vector
18459 permutation. There are several loongson patterns that are matched
18460 via direct vec_select+vec_concat expansion, but we do not have
18461 support in mips_expand_vec_perm_const_1 to guess the adjustment
18462 that should be made for a single operand. Just try again with
18463 the original permutation. */
18464 if (!ok && which == 3)
18466 d.op0 = operands[1];
18467 d.op1 = operands[2];
18468 d.one_vector_p = false;
18469 memcpy (d.perm, orig_perm, MAX_VECT_LEN);
18470 ok = mips_expand_vec_perm_const_1 (&d);
18476 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST_OK. */
18479 mips_vectorize_vec_perm_const_ok (enum machine_mode vmode,
18480 const unsigned char *sel)
18482 struct expand_vec_perm_d d;
18483 unsigned int i, nelt, which;
18487 d.nelt = nelt = GET_MODE_NUNITS (d.vmode);
18488 d.testing_p = true;
18489 memcpy (d.perm, sel, nelt);
18491 /* Categorize the set of elements in the selector. */
18492 for (i = which = 0; i < nelt; ++i)
18494 unsigned char e = d.perm[i];
18495 gcc_assert (e < 2 * nelt);
18496 which |= (e < nelt ? 1 : 2);
18499 /* For all elements from second vector, fold the elements to first. */
18501 for (i = 0; i < nelt; ++i)
18504 /* Check whether the mask can be applied to the vector type. */
18505 d.one_vector_p = (which != 3);
18507 d.target = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 1);
18508 d.op1 = d.op0 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 2);
18509 if (!d.one_vector_p)
18510 d.op1 = gen_raw_REG (d.vmode, LAST_VIRTUAL_REGISTER + 3);
18513 ret = mips_expand_vec_perm_const_1 (&d);
18519 /* Expand an integral vector unpack operation. */
18522 mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
18524 enum machine_mode imode = GET_MODE (operands[1]);
18525 rtx (*unpack) (rtx, rtx, rtx);
18526 rtx (*cmpgt) (rtx, rtx, rtx);
18527 rtx tmp, dest, zero;
18533 unpack = gen_loongson_punpckhbh;
18535 unpack = gen_loongson_punpcklbh;
18536 cmpgt = gen_loongson_pcmpgtb;
18540 unpack = gen_loongson_punpckhhw;
18542 unpack = gen_loongson_punpcklhw;
18543 cmpgt = gen_loongson_pcmpgth;
18546 gcc_unreachable ();
18549 zero = force_reg (imode, CONST0_RTX (imode));
18554 tmp = gen_reg_rtx (imode);
18555 emit_insn (cmpgt (tmp, zero, operands[1]));
18558 dest = gen_reg_rtx (imode);
18559 emit_insn (unpack (dest, operands[1], tmp));
18561 emit_move_insn (operands[0], gen_lowpart (GET_MODE (operands[0]), dest));
18564 /* A subroutine of mips_expand_vec_init, match constant vector elements. */
18567 mips_constant_elt_p (rtx x)
18569 return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
18572 /* A subroutine of mips_expand_vec_init, expand via broadcast. */
18575 mips_expand_vi_broadcast (enum machine_mode vmode, rtx target, rtx elt)
18577 struct expand_vec_perm_d d;
18581 if (elt != const0_rtx)
18582 elt = force_reg (GET_MODE_INNER (vmode), elt);
18584 elt = gen_lowpart (DImode, elt);
18586 t1 = gen_reg_rtx (vmode);
18590 emit_insn (gen_loongson_vec_init1_v8qi (t1, elt));
18593 emit_insn (gen_loongson_vec_init1_v4hi (t1, elt));
18596 gcc_unreachable ();
18599 memset (&d, 0, sizeof (d));
18604 d.nelt = GET_MODE_NUNITS (vmode);
18605 d.one_vector_p = true;
18607 ok = mips_expand_vec_perm_const_1 (&d);
18611 /* A subroutine of mips_expand_vec_init, replacing all of the non-constant
18612 elements of VALS with zeros, copy the constant vector to TARGET. */
18615 mips_expand_vi_constant (enum machine_mode vmode, unsigned nelt,
18616 rtx target, rtx vals)
18618 rtvec vec = shallow_copy_rtvec (XVEC (vals, 0));
18621 for (i = 0; i < nelt; ++i)
18623 if (!mips_constant_elt_p (RTVEC_ELT (vec, i)))
18624 RTVEC_ELT (vec, i) = const0_rtx;
18627 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, vec));
18631 /* A subroutine of mips_expand_vec_init, expand via pinsrh. */
18634 mips_expand_vi_loongson_one_pinsrh (rtx target, rtx vals, unsigned one_var)
18636 mips_expand_vi_constant (V4HImode, 4, target, vals);
18638 emit_insn (gen_vec_setv4hi (target, target, XVECEXP (vals, 0, one_var),
18639 GEN_INT (one_var)));
18642 /* A subroutine of mips_expand_vec_init, expand anything via memory. */
18645 mips_expand_vi_general (enum machine_mode vmode, enum machine_mode imode,
18646 unsigned nelt, unsigned nvar, rtx target, rtx vals)
18648 rtx mem = assign_stack_temp (vmode, GET_MODE_SIZE (vmode));
18649 unsigned int i, isize = GET_MODE_SIZE (imode);
18652 mips_expand_vi_constant (vmode, nelt, mem, vals);
18654 for (i = 0; i < nelt; ++i)
18656 rtx x = XVECEXP (vals, 0, i);
18657 if (!mips_constant_elt_p (x))
18658 emit_move_insn (adjust_address (mem, imode, i * isize), x);
18661 emit_move_insn (target, mem);
18664 /* Expand a vector initialization. */
18667 mips_expand_vector_init (rtx target, rtx vals)
18669 enum machine_mode vmode = GET_MODE (target);
18670 enum machine_mode imode = GET_MODE_INNER (vmode);
18671 unsigned i, nelt = GET_MODE_NUNITS (vmode);
18672 unsigned nvar = 0, one_var = -1u;
18673 bool all_same = true;
18676 for (i = 0; i < nelt; ++i)
18678 x = XVECEXP (vals, 0, i);
18679 if (!mips_constant_elt_p (x))
18680 nvar++, one_var = i;
18681 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
18685 /* Load constants from the pool, or whatever's handy. */
18688 emit_move_insn (target, gen_rtx_CONST_VECTOR (vmode, XVEC (vals, 0)));
18692 /* For two-part initialization, always use CONCAT. */
18695 rtx op0 = force_reg (imode, XVECEXP (vals, 0, 0));
18696 rtx op1 = force_reg (imode, XVECEXP (vals, 0, 1));
18697 x = gen_rtx_VEC_CONCAT (vmode, op0, op1);
18698 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18702 /* Loongson is the only cpu with vectors with more elements. */
18703 gcc_assert (TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS);
18705 /* If all values are identical, broadcast the value. */
18708 mips_expand_vi_broadcast (vmode, target, XVECEXP (vals, 0, 0));
18712 /* If we've only got one non-variable V4HImode, use PINSRH. */
18713 if (nvar == 1 && vmode == V4HImode)
18715 mips_expand_vi_loongson_one_pinsrh (target, vals, one_var);
18719 mips_expand_vi_general (vmode, imode, nelt, nvar, target, vals);
18722 /* Expand a vector reduction. */
18725 mips_expand_vec_reduc (rtx target, rtx in, rtx (*gen)(rtx, rtx, rtx))
18727 enum machine_mode vmode = GET_MODE (in);
18728 unsigned char perm2[2];
18729 rtx last, next, fold, x;
18733 fold = gen_reg_rtx (vmode);
18737 /* Use PUL/PLU to produce { L, H } op { H, L }.
18738 By reversing the pair order, rather than a pure interleave high,
18739 we avoid erroneous exceptional conditions that we might otherwise
18740 produce from the computation of H op H. */
18743 ok = mips_expand_vselect_vconcat (fold, last, last, perm2, 2);
18748 /* Use interleave to produce { H, L } op { H, H }. */
18749 emit_insn (gen_loongson_punpckhwd (fold, last, last));
18753 /* Perform the first reduction with interleave,
18754 and subsequent reductions with shifts. */
18755 emit_insn (gen_loongson_punpckhwd_hi (fold, last, last));
18757 next = gen_reg_rtx (vmode);
18758 emit_insn (gen (next, last, fold));
18761 fold = gen_reg_rtx (vmode);
18762 x = force_reg (SImode, GEN_INT (16));
18763 emit_insn (gen_vec_shr_v4hi (fold, last, x));
18767 emit_insn (gen_loongson_punpckhwd_qi (fold, last, last));
18769 next = gen_reg_rtx (vmode);
18770 emit_insn (gen (next, last, fold));
18773 fold = gen_reg_rtx (vmode);
18774 x = force_reg (SImode, GEN_INT (16));
18775 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18777 next = gen_reg_rtx (vmode);
18778 emit_insn (gen (next, last, fold));
18781 fold = gen_reg_rtx (vmode);
18782 x = force_reg (SImode, GEN_INT (8));
18783 emit_insn (gen_vec_shr_v8qi (fold, last, x));
18787 gcc_unreachable ();
18790 emit_insn (gen (target, last, fold));
18793 /* Expand a vector minimum/maximum. */
18796 mips_expand_vec_minmax (rtx target, rtx op0, rtx op1,
18797 rtx (*cmp) (rtx, rtx, rtx), bool min_p)
18799 enum machine_mode vmode = GET_MODE (target);
18802 tc = gen_reg_rtx (vmode);
18803 t0 = gen_reg_rtx (vmode);
18804 t1 = gen_reg_rtx (vmode);
18807 emit_insn (cmp (tc, op0, op1));
18809 x = gen_rtx_AND (vmode, tc, (min_p ? op1 : op0));
18810 emit_insn (gen_rtx_SET (VOIDmode, t0, x));
18812 x = gen_rtx_NOT (vmode, tc);
18813 x = gen_rtx_AND (vmode, x, (min_p ? op0 : op1));
18814 emit_insn (gen_rtx_SET (VOIDmode, t1, x));
18816 x = gen_rtx_IOR (vmode, t0, t1);
18817 emit_insn (gen_rtx_SET (VOIDmode, target, x));
18820 /* Implement TARGET_CASE_VALUES_THRESHOLD. */
18823 mips_case_values_threshold (void)
18825 /* In MIPS16 mode using a larger case threshold generates smaller code. */
18826 if (TARGET_MIPS16 && optimize_size)
18829 return default_case_values_threshold ();
18832 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
18835 mips_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
18837 if (!TARGET_HARD_FLOAT_ABI)
18839 tree exceptions_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
18840 tree fcsr_orig_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
18841 tree fcsr_mod_var = create_tmp_var (MIPS_ATYPE_USI, NULL);
18842 tree get_fcsr = mips_builtin_decls[MIPS_GET_FCSR];
18843 tree set_fcsr = mips_builtin_decls[MIPS_SET_FCSR];
18844 tree get_fcsr_hold_call = build_call_expr (get_fcsr, 0);
18845 tree hold_assign_orig = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
18846 fcsr_orig_var, get_fcsr_hold_call);
18847 tree hold_mod_val = build2 (BIT_AND_EXPR, MIPS_ATYPE_USI, fcsr_orig_var,
18848 build_int_cst (MIPS_ATYPE_USI, 0xfffff003));
18849 tree hold_assign_mod = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
18850 fcsr_mod_var, hold_mod_val);
18851 tree set_fcsr_hold_call = build_call_expr (set_fcsr, 1, fcsr_mod_var);
18852 tree hold_all = build2 (COMPOUND_EXPR, MIPS_ATYPE_USI,
18853 hold_assign_orig, hold_assign_mod);
18854 *hold = build2 (COMPOUND_EXPR, void_type_node, hold_all,
18855 set_fcsr_hold_call);
18857 *clear = build_call_expr (set_fcsr, 1, fcsr_mod_var);
18859 tree get_fcsr_update_call = build_call_expr (get_fcsr, 0);
18860 *update = build2 (MODIFY_EXPR, MIPS_ATYPE_USI,
18861 exceptions_var, get_fcsr_update_call);
18862 tree set_fcsr_update_call = build_call_expr (set_fcsr, 1, fcsr_orig_var);
18863 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
18864 set_fcsr_update_call);
18865 tree atomic_feraiseexcept
18866 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
18867 tree int_exceptions_var = fold_convert (integer_type_node,
18869 tree atomic_feraiseexcept_call = build_call_expr (atomic_feraiseexcept,
18870 1, int_exceptions_var);
18871 *update = build2 (COMPOUND_EXPR, void_type_node, *update,
18872 atomic_feraiseexcept_call);
18875 /* Implement TARGET_SPILL_CLASS. */
18878 mips_spill_class (reg_class_t rclass ATTRIBUTE_UNUSED,
18879 enum machine_mode mode ATTRIBUTE_UNUSED)
18886 /* Implement TARGET_LRA_P. */
18891 return mips_lra_flag;
18894 /* Initialize the GCC target structure. */
18895 #undef TARGET_ASM_ALIGNED_HI_OP
18896 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
18897 #undef TARGET_ASM_ALIGNED_SI_OP
18898 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
18899 #undef TARGET_ASM_ALIGNED_DI_OP
18900 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
18902 #undef TARGET_OPTION_OVERRIDE
18903 #define TARGET_OPTION_OVERRIDE mips_option_override
18905 #undef TARGET_LEGITIMIZE_ADDRESS
18906 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
18908 #undef TARGET_ASM_FUNCTION_PROLOGUE
18909 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
18910 #undef TARGET_ASM_FUNCTION_EPILOGUE
18911 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
18912 #undef TARGET_ASM_SELECT_RTX_SECTION
18913 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
18914 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
18915 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
18917 #undef TARGET_SCHED_INIT
18918 #define TARGET_SCHED_INIT mips_sched_init
18919 #undef TARGET_SCHED_REORDER
18920 #define TARGET_SCHED_REORDER mips_sched_reorder
18921 #undef TARGET_SCHED_REORDER2
18922 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
18923 #undef TARGET_SCHED_VARIABLE_ISSUE
18924 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
18925 #undef TARGET_SCHED_ADJUST_COST
18926 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
18927 #undef TARGET_SCHED_ISSUE_RATE
18928 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
18929 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
18930 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
18931 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
18932 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
18933 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
18934 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
18935 mips_multipass_dfa_lookahead
18936 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
18937 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
18938 mips_small_register_classes_for_mode_p
18940 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
18941 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
18943 #undef TARGET_INSERT_ATTRIBUTES
18944 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
18945 #undef TARGET_MERGE_DECL_ATTRIBUTES
18946 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
18947 #undef TARGET_CAN_INLINE_P
18948 #define TARGET_CAN_INLINE_P mips_can_inline_p
18949 #undef TARGET_SET_CURRENT_FUNCTION
18950 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
18952 #undef TARGET_VALID_POINTER_MODE
18953 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
18954 #undef TARGET_REGISTER_MOVE_COST
18955 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
18956 #undef TARGET_REGISTER_PRIORITY
18957 #define TARGET_REGISTER_PRIORITY mips_register_priority
18958 #undef TARGET_MEMORY_MOVE_COST
18959 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
18960 #undef TARGET_RTX_COSTS
18961 #define TARGET_RTX_COSTS mips_rtx_costs
18962 #undef TARGET_ADDRESS_COST
18963 #define TARGET_ADDRESS_COST mips_address_cost
18965 #undef TARGET_IN_SMALL_DATA_P
18966 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
18968 #undef TARGET_MACHINE_DEPENDENT_REORG
18969 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
18971 #undef TARGET_PREFERRED_RELOAD_CLASS
18972 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
18974 #undef TARGET_EXPAND_TO_RTL_HOOK
18975 #define TARGET_EXPAND_TO_RTL_HOOK mips_expand_to_rtl_hook
18976 #undef TARGET_ASM_FILE_START
18977 #define TARGET_ASM_FILE_START mips_file_start
18978 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
18979 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
18980 #undef TARGET_ASM_CODE_END
18981 #define TARGET_ASM_CODE_END mips_code_end
18983 #undef TARGET_INIT_LIBFUNCS
18984 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
18986 #undef TARGET_BUILD_BUILTIN_VA_LIST
18987 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
18988 #undef TARGET_EXPAND_BUILTIN_VA_START
18989 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
18990 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
18991 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
18993 #undef TARGET_PROMOTE_FUNCTION_MODE
18994 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
18995 #undef TARGET_PROMOTE_PROTOTYPES
18996 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
18998 #undef TARGET_FUNCTION_VALUE
18999 #define TARGET_FUNCTION_VALUE mips_function_value
19000 #undef TARGET_LIBCALL_VALUE
19001 #define TARGET_LIBCALL_VALUE mips_libcall_value
19002 #undef TARGET_FUNCTION_VALUE_REGNO_P
19003 #define TARGET_FUNCTION_VALUE_REGNO_P mips_function_value_regno_p
19004 #undef TARGET_RETURN_IN_MEMORY
19005 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
19006 #undef TARGET_RETURN_IN_MSB
19007 #define TARGET_RETURN_IN_MSB mips_return_in_msb
19009 #undef TARGET_ASM_OUTPUT_MI_THUNK
19010 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
19011 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
19012 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
19014 #undef TARGET_PRINT_OPERAND
19015 #define TARGET_PRINT_OPERAND mips_print_operand
19016 #undef TARGET_PRINT_OPERAND_ADDRESS
19017 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
19018 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
19019 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
19021 #undef TARGET_SETUP_INCOMING_VARARGS
19022 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
19023 #undef TARGET_STRICT_ARGUMENT_NAMING
19024 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
19025 #undef TARGET_MUST_PASS_IN_STACK
19026 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
19027 #undef TARGET_PASS_BY_REFERENCE
19028 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
19029 #undef TARGET_CALLEE_COPIES
19030 #define TARGET_CALLEE_COPIES mips_callee_copies
19031 #undef TARGET_ARG_PARTIAL_BYTES
19032 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
19033 #undef TARGET_FUNCTION_ARG
19034 #define TARGET_FUNCTION_ARG mips_function_arg
19035 #undef TARGET_FUNCTION_ARG_ADVANCE
19036 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
19037 #undef TARGET_FUNCTION_ARG_BOUNDARY
19038 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
19040 #undef TARGET_MODE_REP_EXTENDED
19041 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
19043 #undef TARGET_VECTOR_MODE_SUPPORTED_P
19044 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
19046 #undef TARGET_SCALAR_MODE_SUPPORTED_P
19047 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
19049 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
19050 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
19052 #undef TARGET_INIT_BUILTINS
19053 #define TARGET_INIT_BUILTINS mips_init_builtins
19054 #undef TARGET_BUILTIN_DECL
19055 #define TARGET_BUILTIN_DECL mips_builtin_decl
19056 #undef TARGET_EXPAND_BUILTIN
19057 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
19059 #undef TARGET_HAVE_TLS
19060 #define TARGET_HAVE_TLS HAVE_AS_TLS
19062 #undef TARGET_CANNOT_FORCE_CONST_MEM
19063 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
19065 #undef TARGET_LEGITIMATE_CONSTANT_P
19066 #define TARGET_LEGITIMATE_CONSTANT_P mips_legitimate_constant_p
19068 #undef TARGET_ENCODE_SECTION_INFO
19069 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
19071 #undef TARGET_ATTRIBUTE_TABLE
19072 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
19073 /* All our function attributes are related to how out-of-line copies should
19074 be compiled or called. They don't in themselves prevent inlining. */
19075 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
19076 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
19078 #undef TARGET_EXTRA_LIVE_ON_ENTRY
19079 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
19081 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
19082 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
19083 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
19084 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
19086 #undef TARGET_COMP_TYPE_ATTRIBUTES
19087 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
19089 #ifdef HAVE_AS_DTPRELWORD
19090 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
19091 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
19093 #undef TARGET_DWARF_REGISTER_SPAN
19094 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
19096 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
19097 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
19099 #undef TARGET_LEGITIMATE_ADDRESS_P
19100 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
19102 #undef TARGET_FRAME_POINTER_REQUIRED
19103 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
19105 #undef TARGET_CAN_ELIMINATE
19106 #define TARGET_CAN_ELIMINATE mips_can_eliminate
19108 #undef TARGET_CONDITIONAL_REGISTER_USAGE
19109 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
19111 #undef TARGET_TRAMPOLINE_INIT
19112 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
19114 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
19115 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
19117 #undef TARGET_SHIFT_TRUNCATION_MASK
19118 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
19120 #undef TARGET_PREPARE_PCH_SAVE
19121 #define TARGET_PREPARE_PCH_SAVE mips_prepare_pch_save
19123 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
19124 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK mips_vectorize_vec_perm_const_ok
19126 #undef TARGET_CASE_VALUES_THRESHOLD
19127 #define TARGET_CASE_VALUES_THRESHOLD mips_case_values_threshold
19129 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
19130 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV mips_atomic_assign_expand_fenv
19132 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
19133 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
19135 #undef TARGET_SPILL_CLASS
19136 #define TARGET_SPILL_CLASS mips_spill_class
19137 #undef TARGET_LRA_P
19138 #define TARGET_LRA_P mips_lra_p
19140 struct gcc_target targetm = TARGET_INITIALIZER;
19142 #include "gt-mips.h"